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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_crm.h
blob09ed2fa29a99abddd3e0bd9a6b754bcab4b8c449
1 /**
2 **************************************************************************
3 * @file at32f435_437_crm.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 crm header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_CRM_H
29 #define __AT32F435_437_CRM_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup CRM
44 * @{
45 */
46
47 #define CRM_REG(value) PERIPH_REG(CRM_BASE, value)
48 #define CRM_REG_BIT(value) PERIPH_REG_BIT(value)
49
50 /** @defgroup CRM_flags_definition
51 * @brief crm flag
52 * @{
53 */
54
55 #define CRM_HICK_STABLE_FLAG MAKE_VALUE(0x00, 1) /*!< high speed internal clock stable flag */
56 #define CRM_HEXT_STABLE_FLAG MAKE_VALUE(0x00, 17) /*!< high speed external crystal stable flag */
57 #define CRM_PLL_STABLE_FLAG MAKE_VALUE(0x00, 25) /*!< phase locking loop stable flag */
58 #define CRM_LEXT_STABLE_FLAG MAKE_VALUE(0x70, 1) /*!< low speed external crystal stable flag */
59 #define CRM_LICK_STABLE_FLAG MAKE_VALUE(0x74, 1) /*!< low speed internal clock stable flag */
60 #define CRM_ALL_RESET_FLAG MAKE_VALUE(0x74, 24) /*!< all reset flag */
61 #define CRM_NRST_RESET_FLAG MAKE_VALUE(0x74, 26) /*!< nrst pin reset flag */
62 #define CRM_POR_RESET_FLAG MAKE_VALUE(0x74, 27) /*!< power on reset flag */
63 #define CRM_SW_RESET_FLAG MAKE_VALUE(0x74, 28) /*!< software reset flag */
64 #define CRM_WDT_RESET_FLAG MAKE_VALUE(0x74, 29) /*!< watchdog timer reset flag */
65 #define CRM_WWDT_RESET_FLAG MAKE_VALUE(0x74, 30) /*!< window watchdog timer reset flag */
66 #define CRM_LOWPOWER_RESET_FLAG MAKE_VALUE(0x74, 31) /*!< low-power reset flag */
67 #define CRM_LICK_READY_INT_FLAG MAKE_VALUE(0x0C, 0) /*!< low speed internal clock stable interrupt ready flag */
68 #define CRM_LEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 1) /*!< low speed external crystal stable interrupt ready flag */
69 #define CRM_HICK_READY_INT_FLAG MAKE_VALUE(0x0C, 2) /*!< high speed internal clock stable interrupt ready flag */
70 #define CRM_HEXT_READY_INT_FLAG MAKE_VALUE(0x0C, 3) /*!< high speed external crystal stable interrupt ready flag */
71 #define CRM_PLL_READY_INT_FLAG MAKE_VALUE(0x0C, 4) /*!< phase locking loop stable interrupt ready flag */
72 #define CRM_CLOCK_FAILURE_INT_FLAG MAKE_VALUE(0x0C, 7) /*!< clock failure interrupt ready flag */
73
74 /**
75 * @}
76 */
77
78 /** @defgroup CRM_interrupts_definition
79 * @brief crm interrupt
80 * @{
81 */
82
83 #define CRM_LICK_STABLE_INT ((uint32_t)0x00000100) /*!< low speed internal clock stable interrupt */
84 #define CRM_LEXT_STABLE_INT ((uint32_t)0x00000200) /*!< low speed external crystal stable interrupt */
85 #define CRM_HICK_STABLE_INT ((uint32_t)0x00000400) /*!< high speed internal clock stable interrupt */
86 #define CRM_HEXT_STABLE_INT ((uint32_t)0x00000800) /*!< high speed external crystal stable interrupt */
87 #define CRM_PLL_STABLE_INT ((uint32_t)0x00001000) /*!< phase locking loop stable interrupt */
88 #define CRM_CLOCK_FAILURE_INT ((uint32_t)0x00800000) /*!< clock failure interrupt */
89
90 /**
91 * @}
92 */
93
94 /** @defgroup CRM_exported_types
95 * @{
96 */
97
98 /**
99 * @brief crm periph clock
100 */
101 typedef enum
102 {
103 #if defined (AT32F435xx)
104 /* ahb periph1 */
105 CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
106 CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
107 CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
108 CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
109 CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
110 CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
111 CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
112 CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
113 CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
114 CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
115 CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
116 CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
117 CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
118 /* ahb periph2 */
119 CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
120 CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
121 CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
122 /* ahb periph3 */
123 CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
124 CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
125 CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
126 CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
127 /* apb1 periph */
128 CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
129 CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
130 CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
131 CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
132 CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
133 CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
134 CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
135 CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
136 CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
137 CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
138 CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
139 CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
140 CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
141 CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
142 CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
143 CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
144 CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
145 CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
146 CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
147 CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
148 CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
149 CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
150 CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
151 CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
152 CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
153 /* apb2 periph */
154 CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
155 CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
156 CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
157 CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
158 CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
159 CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
160 CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
161 CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
162 CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
163 CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
164 CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
165 CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
166 CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
167 CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
168 CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
169 #endif
170
171 #if defined (AT32F437xx)
172 /* ahb periph1 */
173 CRM_GPIOA_PERIPH_CLOCK = MAKE_VALUE(0x30, 0), /*!< gpioa periph clock */
174 CRM_GPIOB_PERIPH_CLOCK = MAKE_VALUE(0x30, 1), /*!< gpiob periph clock */
175 CRM_GPIOC_PERIPH_CLOCK = MAKE_VALUE(0x30, 2), /*!< gpioc periph clock */
176 CRM_GPIOD_PERIPH_CLOCK = MAKE_VALUE(0x30, 3), /*!< gpiod periph clock */
177 CRM_GPIOE_PERIPH_CLOCK = MAKE_VALUE(0x30, 4), /*!< gpioe periph clock */
178 CRM_GPIOF_PERIPH_CLOCK = MAKE_VALUE(0x30, 5), /*!< gpiof periph clock */
179 CRM_GPIOG_PERIPH_CLOCK = MAKE_VALUE(0x30, 6), /*!< gpiog periph clock */
180 CRM_GPIOH_PERIPH_CLOCK = MAKE_VALUE(0x30, 7), /*!< gpioh periph clock */
181 CRM_CRC_PERIPH_CLOCK = MAKE_VALUE(0x30, 12), /*!< crc periph clock */
182 CRM_EDMA_PERIPH_CLOCK = MAKE_VALUE(0x30, 21), /*!< edma periph clock */
183 CRM_DMA1_PERIPH_CLOCK = MAKE_VALUE(0x30, 22), /*!< dma1 periph clock */
184 CRM_DMA2_PERIPH_CLOCK = MAKE_VALUE(0x30, 24), /*!< dma2 periph clock */
185 CRM_EMAC_PERIPH_CLOCK = MAKE_VALUE(0x30, 25), /*!< emac periph clock */
186 CRM_EMACTX_PERIPH_CLOCK = MAKE_VALUE(0x30, 26), /*!< emac tx periph clock */
187 CRM_EMACRX_PERIPH_CLOCK = MAKE_VALUE(0x30, 27), /*!< emac rx periph clock */
188 CRM_EMACPTP_PERIPH_CLOCK = MAKE_VALUE(0x30, 28), /*!< emac ptp periph clock */
189 CRM_OTGFS2_PERIPH_CLOCK = MAKE_VALUE(0x30, 29), /*!< otgfs2 periph clock */
190 /* ahb periph2 */
191 CRM_DVP_PERIPH_CLOCK = MAKE_VALUE(0x34, 0), /*!< dvp periph clock */
192 CRM_OTGFS1_PERIPH_CLOCK = MAKE_VALUE(0x34, 7), /*!< otgfs1 periph clock */
193 CRM_SDIO1_PERIPH_CLOCK = MAKE_VALUE(0x34, 15), /*!< sdio1 periph clock */
194 /* ahb periph3 */
195 CRM_XMC_PERIPH_CLOCK = MAKE_VALUE(0x38, 0), /*!< xmc periph clock */
196 CRM_QSPI1_PERIPH_CLOCK = MAKE_VALUE(0x38, 1), /*!< qspi1 periph clock */
197 CRM_QSPI2_PERIPH_CLOCK = MAKE_VALUE(0x38, 14), /*!< qspi2 periph clock */
198 CRM_SDIO2_PERIPH_CLOCK = MAKE_VALUE(0x38, 15), /*!< sdio2 periph clock */
199 /* apb1 periph */
200 CRM_TMR2_PERIPH_CLOCK = MAKE_VALUE(0x40, 0), /*!< tmr2 periph clock */
201 CRM_TMR3_PERIPH_CLOCK = MAKE_VALUE(0x40, 1), /*!< tmr3 periph clock */
202 CRM_TMR4_PERIPH_CLOCK = MAKE_VALUE(0x40, 2), /*!< tmr4 periph clock */
203 CRM_TMR5_PERIPH_CLOCK = MAKE_VALUE(0x40, 3), /*!< tmr5 periph clock */
204 CRM_TMR6_PERIPH_CLOCK = MAKE_VALUE(0x40, 4), /*!< tmr6 periph clock */
205 CRM_TMR7_PERIPH_CLOCK = MAKE_VALUE(0x40, 5), /*!< tmr7 periph clock */
206 CRM_TMR12_PERIPH_CLOCK = MAKE_VALUE(0x40, 6), /*!< tmr12 periph clock */
207 CRM_TMR13_PERIPH_CLOCK = MAKE_VALUE(0x40, 7), /*!< tmr13 periph clock */
208 CRM_TMR14_PERIPH_CLOCK = MAKE_VALUE(0x40, 8), /*!< tmr14 periph clock */
209 CRM_WWDT_PERIPH_CLOCK = MAKE_VALUE(0x40, 11), /*!< wwdt periph clock */
210 CRM_SPI2_PERIPH_CLOCK = MAKE_VALUE(0x40, 14), /*!< spi2 periph clock */
211 CRM_SPI3_PERIPH_CLOCK = MAKE_VALUE(0x40, 15), /*!< spi3 periph clock */
212 CRM_USART2_PERIPH_CLOCK = MAKE_VALUE(0x40, 17), /*!< usart2 periph clock */
213 CRM_USART3_PERIPH_CLOCK = MAKE_VALUE(0x40, 18), /*!< usart3 periph clock */
214 CRM_UART4_PERIPH_CLOCK = MAKE_VALUE(0x40, 19), /*!< uart4 periph clock */
215 CRM_UART5_PERIPH_CLOCK = MAKE_VALUE(0x40, 20), /*!< uart5 periph clock */
216 CRM_I2C1_PERIPH_CLOCK = MAKE_VALUE(0x40, 21), /*!< i2c1 periph clock */
217 CRM_I2C2_PERIPH_CLOCK = MAKE_VALUE(0x40, 22), /*!< i2c2 periph clock */
218 CRM_I2C3_PERIPH_CLOCK = MAKE_VALUE(0x40, 23), /*!< i2c3 periph clock */
219 CRM_CAN1_PERIPH_CLOCK = MAKE_VALUE(0x40, 25), /*!< can1 periph clock */
220 CRM_CAN2_PERIPH_CLOCK = MAKE_VALUE(0x40, 26), /*!< can2 periph clock */
221 CRM_PWC_PERIPH_CLOCK = MAKE_VALUE(0x40, 28), /*!< pwc periph clock */
222 CRM_DAC_PERIPH_CLOCK = MAKE_VALUE(0x40, 29), /*!< dac periph clock */
223 CRM_UART7_PERIPH_CLOCK = MAKE_VALUE(0x40, 30), /*!< uart7 periph clock */
224 CRM_UART8_PERIPH_CLOCK = MAKE_VALUE(0x40, 31), /*!< uart8 periph clock */
225 /* apb2 periph */
226 CRM_TMR1_PERIPH_CLOCK = MAKE_VALUE(0x44, 0), /*!< tmr1 periph clock */
227 CRM_TMR8_PERIPH_CLOCK = MAKE_VALUE(0x44, 1), /*!< tmr8 periph clock */
228 CRM_USART1_PERIPH_CLOCK = MAKE_VALUE(0x44, 4), /*!< usart1 periph clock */
229 CRM_USART6_PERIPH_CLOCK = MAKE_VALUE(0x44, 5), /*!< usart6 periph clock */
230 CRM_ADC1_PERIPH_CLOCK = MAKE_VALUE(0x44, 8), /*!< adc1 periph clock */
231 CRM_ADC2_PERIPH_CLOCK = MAKE_VALUE(0x44, 9), /*!< adc2 periph clock */
232 CRM_ADC3_PERIPH_CLOCK = MAKE_VALUE(0x44, 10), /*!< adc3 periph clock */
233 CRM_SPI1_PERIPH_CLOCK = MAKE_VALUE(0x44, 12), /*!< spi1 periph clock */
234 CRM_SPI4_PERIPH_CLOCK = MAKE_VALUE(0x44, 13), /*!< spi4 periph clock */
235 CRM_SCFG_PERIPH_CLOCK = MAKE_VALUE(0x44, 14), /*!< scfg periph clock */
236 CRM_TMR9_PERIPH_CLOCK = MAKE_VALUE(0x44, 16), /*!< tmr9 periph clock */
237 CRM_TMR10_PERIPH_CLOCK = MAKE_VALUE(0x44, 17), /*!< tmr10 periph clock */
238 CRM_TMR11_PERIPH_CLOCK = MAKE_VALUE(0x44, 18), /*!< tmr11 periph clock */
239 CRM_TMR20_PERIPH_CLOCK = MAKE_VALUE(0x44, 20), /*!< tmr20 periph clock */
240 CRM_ACC_PERIPH_CLOCK = MAKE_VALUE(0x44, 29) /*!< acc periph clock */
241 #endif
242
243 } crm_periph_clock_type;
244
245 /**
246 * @brief crm periph reset
247 */
248 typedef enum
249 {
250 #if defined (AT32F435xx)
251 /* ahb periph1 */
252 CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
253 CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
254 CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
255 CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
256 CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
257 CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
258 CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
259 CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
260 CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
261 CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
262 CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
263 CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
264 CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
265 /* ahb periph2 */
266 CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
267 CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
268 CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
269 /* ahb periph3 */
270 CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
271 CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
272 CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
273 CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
274 /* apb1 periph */
275 CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
276 CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
277 CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
278 CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
279 CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
280 CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
281 CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
282 CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
283 CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
284 CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
285 CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
286 CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
287 CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
288 CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
289 CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
290 CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
291 CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
292 CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
293 CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
294 CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
295 CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
296 CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
297 CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
298 CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
299 CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
300 /* apb2 periph */
301 CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
302 CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
303 CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
304 CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
305 CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
306 CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
307 CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
308 CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
309 CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
310 CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
311 CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
312 CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
313 CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
314 #endif
315
316 #if defined (AT32F437xx)
317 /* ahb periph1 */
318 CRM_GPIOA_PERIPH_RESET = MAKE_VALUE(0x10, 0), /*!< gpioa periph reset */
319 CRM_GPIOB_PERIPH_RESET = MAKE_VALUE(0x10, 1), /*!< gpiob periph reset */
320 CRM_GPIOC_PERIPH_RESET = MAKE_VALUE(0x10, 2), /*!< gpioc periph reset */
321 CRM_GPIOD_PERIPH_RESET = MAKE_VALUE(0x10, 3), /*!< gpiod periph reset */
322 CRM_GPIOE_PERIPH_RESET = MAKE_VALUE(0x10, 4), /*!< gpioe periph reset */
323 CRM_GPIOF_PERIPH_RESET = MAKE_VALUE(0x10, 5), /*!< gpiof periph reset */
324 CRM_GPIOG_PERIPH_RESET = MAKE_VALUE(0x10, 6), /*!< gpiog periph reset */
325 CRM_GPIOH_PERIPH_RESET = MAKE_VALUE(0x10, 7), /*!< gpioh periph reset */
326 CRM_CRC_PERIPH_RESET = MAKE_VALUE(0x10, 12), /*!< crc periph reset */
327 CRM_EDMA_PERIPH_RESET = MAKE_VALUE(0x10, 21), /*!< edma periph reset */
328 CRM_DMA1_PERIPH_RESET = MAKE_VALUE(0x10, 22), /*!< dma1 periph reset */
329 CRM_DMA2_PERIPH_RESET = MAKE_VALUE(0x10, 24), /*!< dma2 periph reset */
330 CRM_EMAC_PERIPH_RESET = MAKE_VALUE(0x10, 25), /*!< emac periph reset */
331 CRM_OTGFS2_PERIPH_RESET = MAKE_VALUE(0x10, 29), /*!< otgfs2 periph reset */
332 /* ahb periph2 */
333 CRM_DVP_PERIPH_RESET = MAKE_VALUE(0x14, 0), /*!< dvp periph reset */
334 CRM_OTGFS1_PERIPH_RESET = MAKE_VALUE(0x14, 7), /*!< otgfs1 periph reset */
335 CRM_SDIO1_PERIPH_RESET = MAKE_VALUE(0x14, 15), /*!< sdio1 periph reset */
336 /* ahb periph3 */
337 CRM_XMC_PERIPH_RESET = MAKE_VALUE(0x18, 0), /*!< xmc periph reset */
338 CRM_QSPI1_PERIPH_RESET = MAKE_VALUE(0x18, 1), /*!< qspi1 periph reset */
339 CRM_QSPI2_PERIPH_RESET = MAKE_VALUE(0x18, 14), /*!< qspi2 periph reset */
340 CRM_SDIO2_PERIPH_RESET = MAKE_VALUE(0x18, 15), /*!< sdio2 periph reset */
341 /* apb1 periph */
342 CRM_TMR2_PERIPH_RESET = MAKE_VALUE(0x20, 0), /*!< tmr2 periph reset */
343 CRM_TMR3_PERIPH_RESET = MAKE_VALUE(0x20, 1), /*!< tmr3 periph reset */
344 CRM_TMR4_PERIPH_RESET = MAKE_VALUE(0x20, 2), /*!< tmr4 periph reset */
345 CRM_TMR5_PERIPH_RESET = MAKE_VALUE(0x20, 3), /*!< tmr5 periph reset */
346 CRM_TMR6_PERIPH_RESET = MAKE_VALUE(0x20, 4), /*!< tmr6 periph reset */
347 CRM_TMR7_PERIPH_RESET = MAKE_VALUE(0x20, 5), /*!< tmr7 periph reset */
348 CRM_TMR12_PERIPH_RESET = MAKE_VALUE(0x20, 6), /*!< tmr12 periph reset */
349 CRM_TMR13_PERIPH_RESET = MAKE_VALUE(0x20, 7), /*!< tmr13 periph reset */
350 CRM_TMR14_PERIPH_RESET = MAKE_VALUE(0x20, 8), /*!< tmr14 periph reset */
351 CRM_WWDT_PERIPH_RESET = MAKE_VALUE(0x20, 11), /*!< wwdt periph reset */
352 CRM_SPI2_PERIPH_RESET = MAKE_VALUE(0x20, 14), /*!< spi2 periph reset */
353 CRM_SPI3_PERIPH_RESET = MAKE_VALUE(0x20, 15), /*!< spi3 periph reset */
354 CRM_USART2_PERIPH_RESET = MAKE_VALUE(0x20, 17), /*!< usart2 periph reset */
355 CRM_USART3_PERIPH_RESET = MAKE_VALUE(0x20, 18), /*!< usart3 periph reset */
356 CRM_UART4_PERIPH_RESET = MAKE_VALUE(0x20, 19), /*!< uart4 periph reset */
357 CRM_UART5_PERIPH_RESET = MAKE_VALUE(0x20, 20), /*!< uart5 periph reset */
358 CRM_I2C1_PERIPH_RESET = MAKE_VALUE(0x20, 21), /*!< i2c1 periph reset */
359 CRM_I2C2_PERIPH_RESET = MAKE_VALUE(0x20, 22), /*!< i2c2 periph reset */
360 CRM_I2C3_PERIPH_RESET = MAKE_VALUE(0x20, 23), /*!< i2c3 periph reset */
361 CRM_CAN1_PERIPH_RESET = MAKE_VALUE(0x20, 25), /*!< can1 periph reset */
362 CRM_CAN2_PERIPH_RESET = MAKE_VALUE(0x20, 26), /*!< can2 periph reset */
363 CRM_PWC_PERIPH_RESET = MAKE_VALUE(0x20, 28), /*!< pwc periph reset */
364 CRM_DAC_PERIPH_RESET = MAKE_VALUE(0x20, 29), /*!< dac periph reset */
365 CRM_UART7_PERIPH_RESET = MAKE_VALUE(0x20, 30), /*!< uart7 periph reset */
366 CRM_UART8_PERIPH_RESET = MAKE_VALUE(0x20, 31), /*!< uart8 periph reset */
367 /* apb2 periph */
368 CRM_TMR1_PERIPH_RESET = MAKE_VALUE(0x24, 0), /*!< tmr1 periph reset */
369 CRM_TMR8_PERIPH_RESET = MAKE_VALUE(0x24, 1), /*!< tmr8 periph reset */
370 CRM_USART1_PERIPH_RESET = MAKE_VALUE(0x24, 4), /*!< usart1 periph reset */
371 CRM_USART6_PERIPH_RESET = MAKE_VALUE(0x24, 5), /*!< usart6 periph reset */
372 CRM_ADC_PERIPH_RESET = MAKE_VALUE(0x24, 8), /*!< adc periph reset */
373 CRM_SPI1_PERIPH_RESET = MAKE_VALUE(0x24, 12), /*!< spi1 periph reset */
374 CRM_SPI4_PERIPH_RESET = MAKE_VALUE(0x24, 13), /*!< spi4 periph reset */
375 CRM_SCFG_PERIPH_RESET = MAKE_VALUE(0x24, 14), /*!< scfg periph reset */
376 CRM_TMR9_PERIPH_RESET = MAKE_VALUE(0x24, 16), /*!< tmr9 periph reset */
377 CRM_TMR10_PERIPH_RESET = MAKE_VALUE(0x24, 17), /*!< tmr10 periph reset */
378 CRM_TMR11_PERIPH_RESET = MAKE_VALUE(0x24, 18), /*!< tmr11 periph reset */
379 CRM_TMR20_PERIPH_RESET = MAKE_VALUE(0x24, 20), /*!< tmr20 periph reset */
380 CRM_ACC_PERIPH_RESET = MAKE_VALUE(0x24, 29) /*!< acc periph reset */
381 #endif
382
383 } crm_periph_reset_type;
384
385 /**
386 * @brief crm periph clock in low power mode
387 */
388 typedef enum
389 {
390 #if defined (AT32F435xx)
391 /* ahb periph1 */
392 CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
393 CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
394 CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
395 CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
396 CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
397 CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
398 CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
399 CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
400 CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
401 CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */
402 CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */
403 CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */
404 CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
405 CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
406 CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
407 CRM_EMAC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 25), /*!< emac sleep mode periph clock */
408 CRM_EMACTX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 26), /*!< emac tx sleep mode periph clock */
409 CRM_EMACRX_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 27), /*!< emac rx sleep mode periph clock */
410 CRM_EMACPTP_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 28), /*!< emac ptp sleep mode periph clock */
411 CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
412 /* ahb periph2 */
413 CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
414 CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
415 CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
416 /* ahb periph3 */
417 CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
418 CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
419 CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
420 CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
421 /* apb1 periph */
422 CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
423 CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
424 CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
425 CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
426 CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
427 CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
428 CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
429 CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
430 CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
431 CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
432 CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
433 CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
434 CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
435 CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
436 CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
437 CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
438 CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
439 CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
440 CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
441 CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
442 CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
443 CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
444 CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
445 CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
446 CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
447 /* apb2 periph */
448 CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
449 CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
450 CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
451 CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
452 CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
453 CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
454 CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
455 CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
456 CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
457 CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
458 CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
459 CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
460 CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
461 CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
462 CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
463 #endif
464
465 #if defined (AT32F437xx)
466 /* ahb periph1 */
467 CRM_GPIOA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 0), /*!< gpioa sleep mode periph clock */
468 CRM_GPIOB_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 1), /*!< gpiob sleep mode periph clock */
469 CRM_GPIOC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 2), /*!< gpioc sleep mode periph clock */
470 CRM_GPIOD_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 3), /*!< gpiod sleep mode periph clock */
471 CRM_GPIOE_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 4), /*!< gpioe sleep mode periph clock */
472 CRM_GPIOF_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 5), /*!< gpiof sleep mode periph clock */
473 CRM_GPIOG_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 6), /*!< gpiog sleep mode periph clock */
474 CRM_GPIOH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 7), /*!< gpioh sleep mode periph clock */
475 CRM_CRC_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 12), /*!< crc sleep mode periph clock */
476 CRM_FLASH_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 15), /*!< flash sleep mode periph clock */
477 CRM_SRAM1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 16), /*!< sram1 sleep mode periph clock */
478 CRM_SRAM2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 17), /*!< sram2 sleep mode periph clock */
479 CRM_EDMA_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 21), /*!< edma sleep mode periph clock */
480 CRM_DMA1_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 22), /*!< dma1 sleep mode periph clock */
481 CRM_DMA2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 24), /*!< dma2 sleep mode periph clock */
482 CRM_OTGFS2_PERIPH_LOWPOWER = MAKE_VALUE(0x50, 29), /*!< otgfs2 sleep mode periph clock */
483 /* ahb periph2 */
484 CRM_DVP_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 0), /*!< dvp sleep mode periph clock */
485 CRM_OTGFS1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 7), /*!< otgfs1 sleep mode periph clock */
486 CRM_SDIO1_PERIPH_LOWPOWER = MAKE_VALUE(0x54, 15), /*!< sdio1 sleep mode periph clock */
487 /* ahb periph3 */
488 CRM_XMC_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 0), /*!< xmc sleep mode periph clock */
489 CRM_QSPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 1), /*!< qspi1 sleep mode periph clock */
490 CRM_QSPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 14), /*!< qspi2 sleep mode periph clock */
491 CRM_SDIO2_PERIPH_LOWPOWER = MAKE_VALUE(0x58, 15), /*!< sdio2 sleep mode periph clock */
492 /* apb1 periph */
493 CRM_TMR2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 0), /*!< tmr2 sleep mode periph clock */
494 CRM_TMR3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 1), /*!< tmr3 sleep mode periph clock */
495 CRM_TMR4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 2), /*!< tmr4 sleep mode periph clock */
496 CRM_TMR5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 3), /*!< tmr5 sleep mode periph clock */
497 CRM_TMR6_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 4), /*!< tmr6 sleep mode periph clock */
498 CRM_TMR7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 5), /*!< tmr7 sleep mode periph clock */
499 CRM_TMR12_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 6), /*!< tmr12 sleep mode periph clock */
500 CRM_TMR13_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 7), /*!< tmr13 sleep mode periph clock */
501 CRM_TMR14_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 8), /*!< tmr14 sleep mode periph clock */
502 CRM_WWDT_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 11), /*!< wwdt sleep mode periph clock */
503 CRM_SPI2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 14), /*!< spi2 sleep mode periph clock */
504 CRM_SPI3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 15), /*!< spi3 sleep mode periph clock */
505 CRM_USART2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 17), /*!< usart2 sleep mode periph clock */
506 CRM_USART3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 18), /*!< usart3 sleep mode periph clock */
507 CRM_UART4_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 19), /*!< uart4 sleep mode periph clock */
508 CRM_UART5_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 20), /*!< uart5 sleep mode periph clock */
509 CRM_I2C1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 21), /*!< i2c1 sleep mode periph clock */
510 CRM_I2C2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 22), /*!< i2c2 sleep mode periph clock */
511 CRM_I2C3_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 23), /*!< i2c3 sleep mode periph clock */
512 CRM_CAN1_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 25), /*!< can1 sleep mode periph clock */
513 CRM_CAN2_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 26), /*!< can2 sleep mode periph clock */
514 CRM_PWC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 28), /*!< pwc sleep mode periph clock */
515 CRM_DAC_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 29), /*!< dac sleep mode periph clock */
516 CRM_UART7_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 30), /*!< uart7 sleep mode periph clock */
517 CRM_UART8_PERIPH_LOWPOWER = MAKE_VALUE(0x60, 31), /*!< uart8 sleep mode periph clock */
518 /* apb2 periph */
519 CRM_TMR1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 0), /*!< tmr1 sleep mode periph clock */
520 CRM_TMR8_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 1), /*!< tmr8 sleep mode periph clock */
521 CRM_USART1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 4), /*!< usart1 sleep mode periph clock */
522 CRM_USART6_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 5), /*!< usart6 sleep mode periph clock */
523 CRM_ADC1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 8), /*!< adc1 sleep mode periph clock */
524 CRM_ADC2_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 9), /*!< adc2 sleep mode periph clock */
525 CRM_ADC3_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 10), /*!< adc3 sleep mode periph clock */
526 CRM_SPI1_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 12), /*!< spi1 sleep mode periph clock */
527 CRM_SPI4_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 13), /*!< spi4 sleep mode periph clock */
528 CRM_SCFG_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 14), /*!< scfg sleep mode periph clock */
529 CRM_TMR9_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 16), /*!< tmr9 sleep mode periph clock */
530 CRM_TMR10_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 17), /*!< tmr10 sleep mode periph clock */
531 CRM_TMR11_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 18), /*!< tmr11 sleep mode periph clock */
532 CRM_TMR20_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 20), /*!< tmr20 sleep mode periph clock */
533 CRM_ACC_PERIPH_LOWPOWER = MAKE_VALUE(0x64, 29) /*!< acc sleep mode periph clock */
534 #endif
535
536 } crm_periph_clock_lowpower_type;
537
538 /**
539 * @brief crm pll clock source
540 */
541 typedef enum
542 {
543 CRM_PLL_SOURCE_HICK = 0x00, /*!< high speed internal clock as pll reference clock source */
544 CRM_PLL_SOURCE_HEXT = 0x01 /*!< high speed external crystal as pll reference clock source */
545 } crm_pll_clock_source_type;
546
547 /**
548 * @brief crm pll fr
549 */
550 typedef enum
551 {
552 CRM_PLL_FR_1 = 0x00, /*!< pll post-division div1 */
553 CRM_PLL_FR_2 = 0x01, /*!< pll post-division div2 */
554 CRM_PLL_FR_4 = 0x02, /*!< pll post-division div4 */
555 CRM_PLL_FR_8 = 0x03, /*!< pll post-division div8 */
556 CRM_PLL_FR_16 = 0x04, /*!< pll post-division div16 */
557 CRM_PLL_FR_32 = 0x05 /*!< pll post-division div32 */
558 } crm_pll_fr_type;
559
560 /**
561 * @brief crm clock source
562 */
563 typedef enum
564 {
565 CRM_CLOCK_SOURCE_HICK = 0x00, /*!< high speed internal clock */
566 CRM_CLOCK_SOURCE_HEXT = 0x01, /*!< high speed external crystal */
567 CRM_CLOCK_SOURCE_PLL = 0x02, /*!< phase locking loop */
568 CRM_CLOCK_SOURCE_LEXT = 0x03, /*!< low speed external crystal */
569 CRM_CLOCK_SOURCE_LICK = 0x04 /*!< low speed internal clock */
570 } crm_clock_source_type;
571
572 /**
573 * @brief crm ahb division
574 */
575 typedef enum
576 {
577 CRM_AHB_DIV_1 = 0x00, /*!< sclk div1 to ahbclk */
578 CRM_AHB_DIV_2 = 0x08, /*!< sclk div2 to ahbclk */
579 CRM_AHB_DIV_4 = 0x09, /*!< sclk div4 to ahbclk */
580 CRM_AHB_DIV_8 = 0x0A, /*!< sclk div8 to ahbclk */
581 CRM_AHB_DIV_16 = 0x0B, /*!< sclk div16 to ahbclk */
582 CRM_AHB_DIV_64 = 0x0C, /*!< sclk div64 to ahbclk */
583 CRM_AHB_DIV_128 = 0x0D, /*!< sclk div128 to ahbclk */
584 CRM_AHB_DIV_256 = 0x0E, /*!< sclk div256 to ahbclk */
585 CRM_AHB_DIV_512 = 0x0F /*!< sclk div512 to ahbclk */
586 } crm_ahb_div_type;
587
588 /**
589 * @brief crm apb1 division
590 */
591 typedef enum
592 {
593 CRM_APB1_DIV_1 = 0x00, /*!< ahbclk div1 to apb1clk */
594 CRM_APB1_DIV_2 = 0x04, /*!< ahbclk div2 to apb1clk */
595 CRM_APB1_DIV_4 = 0x05, /*!< ahbclk div4 to apb1clk */
596 CRM_APB1_DIV_8 = 0x06, /*!< ahbclk div8 to apb1clk */
597 CRM_APB1_DIV_16 = 0x07 /*!< ahbclk div16 to apb1clk */
598 } crm_apb1_div_type;
599
600 /**
601 * @brief crm apb2 division
602 */
603 typedef enum
604 {
605 CRM_APB2_DIV_1 = 0x00, /*!< ahbclk div1 to apb2clk */
606 CRM_APB2_DIV_2 = 0x04, /*!< ahbclk div2 to apb2clk */
607 CRM_APB2_DIV_4 = 0x05, /*!< ahbclk div4 to apb2clk */
608 CRM_APB2_DIV_8 = 0x06, /*!< ahbclk div8 to apb2clk */
609 CRM_APB2_DIV_16 = 0x07 /*!< ahbclk div16 to apb2clk */
610 } crm_apb2_div_type;
611
612 /**
613 * @brief crm usb division
614 */
615 typedef enum
616 {
617 CRM_USB_DIV_1_5 = 0x00, /*!< pllclk div1.5 to usbclk */
618 CRM_USB_DIV_1 = 0x01, /*!< pllclk div1 to usbclk */
619 CRM_USB_DIV_2_5 = 0x02, /*!< pllclk div2.5 to usbclk */
620 CRM_USB_DIV_2 = 0x03, /*!< pllclk div2 to usbclk */
621 CRM_USB_DIV_3_5 = 0x04, /*!< pllclk div3.5 to usbclk */
622 CRM_USB_DIV_3 = 0x05, /*!< pllclk div3 to usbclk */
623 CRM_USB_DIV_4_5 = 0x06, /*!< pllclk div4.5 to usbclk */
624 CRM_USB_DIV_4 = 0x07, /*!< pllclk div4 to usbclk */
625 CRM_USB_DIV_5_5 = 0x08, /*!< pllclk div5.5 to usbclk */
626 CRM_USB_DIV_5 = 0x09, /*!< pllclk div5 to usbclk */
627 CRM_USB_DIV_6_5 = 0x0A, /*!< pllclk div6.5 to usbclk */
628 CRM_USB_DIV_6 = 0x0B, /*!< pllclk div6 to usbclk */
629 CRM_USB_DIV_7 = 0x0C /*!< pllclk div7 to usbclk */
630 } crm_usb_div_type;
631
632 /**
633 * @brief crm ertc clock
634 */
635 typedef enum
636 {
637 CRM_ERTC_CLOCK_NOCLK = 0x000, /*!< no clock as ertc clock source */
638 CRM_ERTC_CLOCK_LEXT = 0x001, /*!< low speed external crystal as ertc clock source */
639 CRM_ERTC_CLOCK_LICK = 0x002, /*!< low speed internal clock as ertc clock source */
640 CRM_ERTC_CLOCK_HEXT_DIV_2 = 0x023, /*!< high speed external crystal div2 as ertc clock source */
641 CRM_ERTC_CLOCK_HEXT_DIV_3 = 0x033, /*!< high speed external crystal div3 as ertc clock source */
642 CRM_ERTC_CLOCK_HEXT_DIV_4 = 0x043, /*!< high speed external crystal div4 as ertc clock source */
643 CRM_ERTC_CLOCK_HEXT_DIV_5 = 0x053, /*!< high speed external crystal div5 as ertc clock source */
644 CRM_ERTC_CLOCK_HEXT_DIV_6 = 0x063, /*!< high speed external crystal div6 as ertc clock source */
645 CRM_ERTC_CLOCK_HEXT_DIV_7 = 0x073, /*!< high speed external crystal div7 as ertc clock source */
646 CRM_ERTC_CLOCK_HEXT_DIV_8 = 0x083, /*!< high speed external crystal div8 as ertc clock source */
647 CRM_ERTC_CLOCK_HEXT_DIV_9 = 0x093, /*!< high speed external crystal div9 as ertc clock source */
648 CRM_ERTC_CLOCK_HEXT_DIV_10 = 0x0A3, /*!< high speed external crystal div10 as ertc clock source */
649 CRM_ERTC_CLOCK_HEXT_DIV_11 = 0x0B3, /*!< high speed external crystal div11 as ertc clock source */
650 CRM_ERTC_CLOCK_HEXT_DIV_12 = 0x0C3, /*!< high speed external crystal div12 as ertc clock source */
651 CRM_ERTC_CLOCK_HEXT_DIV_13 = 0x0D3, /*!< high speed external crystal div13 as ertc clock source */
652 CRM_ERTC_CLOCK_HEXT_DIV_14 = 0x0E3, /*!< high speed external crystal div14 as ertc clock source */
653 CRM_ERTC_CLOCK_HEXT_DIV_15 = 0x0F3, /*!< high speed external crystal div15 as ertc clock source */
654 CRM_ERTC_CLOCK_HEXT_DIV_16 = 0x103, /*!< high speed external crystal div16 as ertc clock source */
655 CRM_ERTC_CLOCK_HEXT_DIV_17 = 0x113, /*!< high speed external crystal div17 as ertc clock source */
656 CRM_ERTC_CLOCK_HEXT_DIV_18 = 0x123, /*!< high speed external crystal div18 as ertc clock source */
657 CRM_ERTC_CLOCK_HEXT_DIV_19 = 0x133, /*!< high speed external crystal div19 as ertc clock source */
658 CRM_ERTC_CLOCK_HEXT_DIV_20 = 0x143, /*!< high speed external crystal div20 as ertc clock source */
659 CRM_ERTC_CLOCK_HEXT_DIV_21 = 0x153, /*!< high speed external crystal div21 as ertc clock source */
660 CRM_ERTC_CLOCK_HEXT_DIV_22 = 0x163, /*!< high speed external crystal div22 as ertc clock source */
661 CRM_ERTC_CLOCK_HEXT_DIV_23 = 0x173, /*!< high speed external crystal div23 as ertc clock source */
662 CRM_ERTC_CLOCK_HEXT_DIV_24 = 0x183, /*!< high speed external crystal div24 as ertc clock source */
663 CRM_ERTC_CLOCK_HEXT_DIV_25 = 0x193, /*!< high speed external crystal div25 as ertc clock source */
664 CRM_ERTC_CLOCK_HEXT_DIV_26 = 0x1A3, /*!< high speed external crystal div26 as ertc clock source */
665 CRM_ERTC_CLOCK_HEXT_DIV_27 = 0x1B3, /*!< high speed external crystal div27 as ertc clock source */
666 CRM_ERTC_CLOCK_HEXT_DIV_28 = 0x1C3, /*!< high speed external crystal div28 as ertc clock source */
667 CRM_ERTC_CLOCK_HEXT_DIV_29 = 0x1D3, /*!< high speed external crystal div29 as ertc clock source */
668 CRM_ERTC_CLOCK_HEXT_DIV_30 = 0x1E3, /*!< high speed external crystal div30 as ertc clock source */
669 CRM_ERTC_CLOCK_HEXT_DIV_31 = 0x1F3 /*!< high speed external crystal div31 as ertc clock source */
670 } crm_ertc_clock_type;
671
672 /**
673 * @brief crm hick 48mhz division
674 */
675 typedef enum
676 {
677 CRM_HICK48_DIV6 = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
678 CRM_HICK48_NODIV = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
679 } crm_hick_div_6_type;
680
681 /**
682 * @brief crm sclk select
683 */
684 typedef enum
685 {
686 CRM_SCLK_HICK = 0x00, /*!< select high speed internal clock as sclk */
687 CRM_SCLK_HEXT = 0x01, /*!< select high speed external crystal as sclk */
688 CRM_SCLK_PLL = 0x02 /*!< select phase locking loop clock as sclk */
689 } crm_sclk_type;
690
691 /**
692 * @brief crm clkout index
693 */
694 typedef enum
695 {
696 CRM_CLKOUT_INDEX_1 = 0x00, /*!< clkout1 */
697 CRM_CLKOUT_INDEX_2 = 0x01 /*!< clkout2 */
698 } crm_clkout_index_type;
699
700 /**
701 * @brief crm clkout1 select
702 */
703 typedef enum
704 {
705 CRM_CLKOUT1_HICK = 0x00, /*!< output high speed internal clock to clkout1 pin */
706 CRM_CLKOUT1_LEXT = 0x01, /*!< output low speed external crystal to clkout1 pin */
707 CRM_CLKOUT1_HEXT = 0x02, /*!< output high speed external crystal to clkout1 pin */
708 CRM_CLKOUT1_PLL = 0x03 /*!< output phase locking loop clock to clkout1 pin */
709 } crm_clkout1_select_type;
710
711 /**
712 * @brief crm clkout2 select
713 */
714 typedef enum
715 {
716 CRM_CLKOUT2_SCLK = 0x00, /*!< output system clock to clkout2 pin */
717 CRM_CLKOUT2_HEXT = 0x02, /*!< output high speed external crystal to clkout2 pin */
718 CRM_CLKOUT2_PLL = 0x03, /*!< output phase locking loop clock to clkout2 pin */
719 CRM_CLKOUT2_USB = 0x10, /*!< output usbclk to clkout2 pin */
720 CRM_CLKOUT2_ADC = 0x11, /*!< output adcclk to clkout2 pin */
721 CRM_CLKOUT2_HICK = 0x12, /*!< output high speed internal clock to clkout2 pin */
722 CRM_CLKOUT2_LICK = 0x13, /*!< output low speed internal clock to clkout2 pin */
723 CRM_CLKOUT2_LEXT = 0x14 /*!< output low speed external crystal to clkout2 pin */
724 } crm_clkout2_select_type;
725
726 /**
727 * @brief crm clkout division1
728 */
729 typedef enum
730 {
731 CRM_CLKOUT_DIV1_1 = 0x00, /*!< clkout division1 div1 */
732 CRM_CLKOUT_DIV1_2 = 0x04, /*!< clkout division1 div2 */
733 CRM_CLKOUT_DIV1_3 = 0x05, /*!< clkout division1 div3 */
734 CRM_CLKOUT_DIV1_4 = 0x06, /*!< clkout division1 div4 */
735 CRM_CLKOUT_DIV1_5 = 0x07 /*!< clkout division1 div5 */
736 } crm_clkout_div1_type;
737
738 /**
739 * @brief crm clkout division2
740 */
741 typedef enum
742 {
743 CRM_CLKOUT_DIV2_1 = 0x00, /*!< clkout division2 div1 */
744 CRM_CLKOUT_DIV2_2 = 0x08, /*!< clkout division2 div2 */
745 CRM_CLKOUT_DIV2_4 = 0x09, /*!< clkout division2 div4 */
746 CRM_CLKOUT_DIV2_8 = 0x0A, /*!< clkout division2 div8 */
747 CRM_CLKOUT_DIV2_16 = 0x0B, /*!< clkout division2 div16 */
748 CRM_CLKOUT_DIV2_64 = 0x0C, /*!< clkout division2 div64 */
749 CRM_CLKOUT_DIV2_128 = 0x0D, /*!< clkout division2 div128 */
750 CRM_CLKOUT_DIV2_256 = 0x0E, /*!< clkout division2 div256 */
751 CRM_CLKOUT_DIV2_512 = 0x0F /*!< clkout division2 div512 */
752 } crm_clkout_div2_type;
753
754 /**
755 * @brief crm auto step mode
756 */
757 typedef enum
758 {
759 CRM_AUTO_STEP_MODE_DISABLE = 0x00, /*!< disable auto step mode */
760 CRM_AUTO_STEP_MODE_ENABLE = 0x03 /*!< enable auto step mode */
761 } crm_auto_step_mode_type;
762
763 /**
764 * @brief crm usb 48 mhz clock source select
765 */
766 typedef enum
767 {
768 CRM_USB_CLOCK_SOURCE_PLL = 0x00, /*!< select phase locking loop clock as usb clock source */
769 CRM_USB_CLOCK_SOURCE_HICK = 0x01 /*!< select high speed internal clock as usb clock source */
770 } crm_usb_clock_source_type;
771
772 /**
773 * @brief crm hick as system clock frequency select
774 */
775 typedef enum
776 {
777 CRM_HICK_SCLK_8MHZ = 0x00, /*!< fixed 8 mhz when hick is selected as sclk */
778 CRM_HICK_SCLK_48MHZ = 0x01 /*!< 8 mhz or 48 mhz depend on hickdiv when hick is selected as sclk */
779 } crm_hick_sclk_frequency_type;
780
781 /**
782 * @brief crm emac output pulse width
783 */
784 typedef enum
785 {
786 CRM_EMAC_PULSE_125MS = 0x00, /*!< emac output pulse width 125ms */
787 CRM_EMAC_PULSE_1SCLK = 0x01 /*!< emac output pulse width 1 system clock */
788 } crm_emac_output_pulse_type;
789
790 /**
791 * @brief crm clocks freqency structure
792 */
793 typedef struct
794 {
795 uint32_t sclk_freq; /*!< system clock frequency */
796 uint32_t ahb_freq; /*!< ahb bus clock frequency */
797 uint32_t apb2_freq; /*!< apb2 bus clock frequency */
798 uint32_t apb1_freq; /*!< apb1 bus clock frequency */
799 } crm_clocks_freq_type;
800
801 /**
802 * @brief type define crm register all
803 */
804 typedef struct
805 {
806 /**
807 * @brief crm ctrl register, offset:0x00
808 */
809 union
810 {
811 __IO uint32_t ctrl;
812 struct
813 {
814 __IO uint32_t hicken : 1; /* [0] */
815 __IO uint32_t hickstbl : 1; /* [1] */
816 __IO uint32_t hicktrim : 6; /* [7:2] */
817 __IO uint32_t hickcal : 8; /* [15:8] */
818 __IO uint32_t hexten : 1; /* [16] */
819 __IO uint32_t hextstbl : 1; /* [17] */
820 __IO uint32_t hextbyps : 1; /* [18] */
821 __IO uint32_t cfden : 1; /* [19] */
822 __IO uint32_t reserved1 : 4; /* [23:20] */
823 __IO uint32_t pllen : 1; /* [24] */
824 __IO uint32_t pllstbl : 1; /* [25] */
825 __IO uint32_t reserved2 : 6; /* [31:26] */
826 } ctrl_bit;
827 };
828
829 /**
830 * @brief crm pllcfg register, offset:0x04
831 */
832 union
833 {
834 __IO uint32_t pllcfg;
835 struct
836 {
837 __IO uint32_t pllms : 4; /* [3:0] */
838 __IO uint32_t reserved1 : 2; /* [5:4] */
839 __IO uint32_t pllns : 9; /* [14:6] */
840 __IO uint32_t reserved2 : 1; /* [15] */
841 __IO uint32_t pllfr : 3; /* [18:16] */
842 __IO uint32_t reserved3 : 3; /* [21:19] */
843 __IO uint32_t pllrcs : 1; /* [22] */
844 __IO uint32_t reserved4 : 9; /* [31:23] */
845 } pllcfg_bit;
846 };
847
848 /**
849 * @brief crm cfg register, offset:0x08
850 */
851 union
852 {
853 __IO uint32_t cfg;
854 struct
855 {
856 __IO uint32_t sclksel : 2; /* [1:0] */
857 __IO uint32_t sclksts : 2; /* [3:2] */
858 __IO uint32_t ahbdiv : 4; /* [7:4] */
859 __IO uint32_t reserved1 : 2; /* [9:8] */
860 __IO uint32_t apb1div : 3; /* [12:10] */
861 __IO uint32_t apb2div : 3; /* [15:13] */
862 __IO uint32_t ertcdiv : 5; /* [20:16] */
863 __IO uint32_t clkout1_sel : 2; /* [22:21] */
864 __IO uint32_t reserved2 : 1; /* [23] */
865 __IO uint32_t clkout1div1 : 3; /* [26:24] */
866 __IO uint32_t clkout2div1 : 3; /* [29:27] */
867 __IO uint32_t clkout2_sel1 : 2; /* [31:30] */
868 } cfg_bit;
869 };
870
871 /**
872 * @brief crm clkint register, offset:0x0C
873 */
874 union
875 {
876 __IO uint32_t clkint;
877 struct
878 {
879 __IO uint32_t lickstblf : 1; /* [0] */
880 __IO uint32_t lextstblf : 1; /* [1] */
881 __IO uint32_t hickstblf : 1; /* [2] */
882 __IO uint32_t hextstblf : 1; /* [3] */
883 __IO uint32_t pllstblf : 1; /* [4] */
884 __IO uint32_t reserved1 : 2; /* [6:5] */
885 __IO uint32_t cfdf : 1; /* [7] */
886 __IO uint32_t lickstblien : 1; /* [8] */
887 __IO uint32_t lextstblien : 1; /* [9] */
888 __IO uint32_t hickstblien : 1; /* [10] */
889 __IO uint32_t hextstblien : 1; /* [11] */
890 __IO uint32_t pllstblien : 1; /* [12] */
891 __IO uint32_t reserved2 : 3; /* [15:13] */
892 __IO uint32_t lickstblfc : 1; /* [16] */
893 __IO uint32_t lextstblfc : 1; /* [17] */
894 __IO uint32_t hickstblfc : 1; /* [18] */
895 __IO uint32_t hextstblfc : 1; /* [19] */
896 __IO uint32_t pllstblfc : 1; /* [20] */
897 __IO uint32_t reserved3 : 2; /* [22:21] */
898 __IO uint32_t cfdfc : 1; /* [23] */
899 __IO uint32_t reserved4 : 8; /* [31:24] */
900 } clkint_bit;
901 };
902
903 /**
904 * @brief crm ahbrst1 register, offset:0x10
905 */
906 union
907 {
908 __IO uint32_t ahbrst1;
909 #if defined (AT32F435xx)
910 struct
911 {
912 __IO uint32_t gpioarst : 1; /* [0] */
913 __IO uint32_t gpiobrst : 1; /* [1] */
914 __IO uint32_t gpiocrst : 1; /* [2] */
915 __IO uint32_t gpiodrst : 1; /* [3] */
916 __IO uint32_t gpioerst : 1; /* [4] */
917 __IO uint32_t gpiofrst : 1; /* [5] */
918 __IO uint32_t gpiogrst : 1; /* [6] */
919 __IO uint32_t gpiohrst : 1; /* [7] */
920 __IO uint32_t reserved1 : 4; /* [11:8] */
921 __IO uint32_t crcrst : 1; /* [12] */
922 __IO uint32_t reserved2 : 8; /* [20:13] */
923 __IO uint32_t edmarst : 1; /* [21] */
924 __IO uint32_t dma1rst : 1; /* [22] */
925 __IO uint32_t reserved3 : 1; /* [23] */
926 __IO uint32_t dma2rst : 1; /* [24] */
927 __IO uint32_t reserved4 : 4; /* [28:25] */
928 __IO uint32_t otgfs2rst : 1; /* [29] */
929 __IO uint32_t reserved5 : 2; /* [31:30] */
930 } ahbrst1_bit;
931 #endif
932
933 #if defined (AT32F437xx)
934 struct
935 {
936 __IO uint32_t gpioarst : 1; /* [0] */
937 __IO uint32_t gpiobrst : 1; /* [1] */
938 __IO uint32_t gpiocrst : 1; /* [2] */
939 __IO uint32_t gpiodrst : 1; /* [3] */
940 __IO uint32_t gpioerst : 1; /* [4] */
941 __IO uint32_t gpiofrst : 1; /* [5] */
942 __IO uint32_t gpiogrst : 1; /* [6] */
943 __IO uint32_t gpiohrst : 1; /* [7] */
944 __IO uint32_t reserved1 : 4; /* [11:8] */
945 __IO uint32_t crcrst : 1; /* [12] */
946 __IO uint32_t reserved2 : 8; /* [20:13] */
947 __IO uint32_t edmarst : 1; /* [21] */
948 __IO uint32_t dma1rst : 1; /* [22] */
949 __IO uint32_t reserved3 : 1; /* [23] */
950 __IO uint32_t dma2rst : 1; /* [24] */
951 __IO uint32_t emacrst : 1; /* [25] */
952 __IO uint32_t reserved4 : 3; /* [28:26] */
953 __IO uint32_t otgfs2rst : 1; /* [29] */
954 __IO uint32_t reserved5 : 2; /* [31:30] */
955 } ahbrst1_bit;
956 #endif
957 };
958
959 /**
960 * @brief crm ahbrst2 register, offset:0x14
961 */
962 union
963 {
964 __IO uint32_t ahbrst2;
965 struct
966 {
967 __IO uint32_t dvprst : 1; /* [0] */
968 __IO uint32_t reserved1 : 6; /* [6:1] */
969 __IO uint32_t otgfs1rst : 1; /* [7] */
970 __IO uint32_t reserved2 : 7; /* [14:8] */
971 __IO uint32_t sdio1rst : 1; /* [15] */
972 __IO uint32_t reserved3 : 16;/* [31:16] */
973 } ahbrst2_bit;
974 };
975
976 /**
977 * @brief crm ahbrst3 register, offset:0x18
978 */
979 union
980 {
981 __IO uint32_t ahbrst3;
982 struct
983 {
984 __IO uint32_t xmcrst : 1; /* [0] */
985 __IO uint32_t qspi1rst : 1; /* [1] */
986 __IO uint32_t reserved1 : 12;/* [13:2] */
987 __IO uint32_t qspi2rst : 1; /* [14] */
988 __IO uint32_t sdio2rst : 1; /* [15] */
989 __IO uint32_t reserved3 : 16;/* [31:16] */
990 } ahbrst3_bit;
991 };
992
993 /**
994 * @brief crm reserved1 register, offset:0x1C
995 */
996 __IO uint32_t reserved1;
997
998 /**
999 * @brief crm apb1rst register, offset:0x20
1000 */
1001 union
1002 {
1003 __IO uint32_t apb1rst;
1004 struct
1005 {
1006 __IO uint32_t tmr2rst : 1; /* [0] */
1007 __IO uint32_t tmr3rst : 1; /* [1] */
1008 __IO uint32_t tmr4rst : 1; /* [2] */
1009 __IO uint32_t tmr5rst : 1; /* [3] */
1010 __IO uint32_t tmr6rst : 1; /* [4] */
1011 __IO uint32_t tmr7rst : 1; /* [5] */
1012 __IO uint32_t tmr12rst : 1; /* [6] */
1013 __IO uint32_t tmr13rst : 1; /* [7] */
1014 __IO uint32_t adc14rst : 1; /* [8] */
1015 __IO uint32_t reserved1 : 2; /* [10:9] */
1016 __IO uint32_t wwdtrst : 1; /* [11] */
1017 __IO uint32_t reserved2 : 2; /* [13:12] */
1018 __IO uint32_t spi2rst : 1; /* [14] */
1019 __IO uint32_t spi3rst : 1; /* [15] */
1020 __IO uint32_t reserved3 : 1; /* [16] */
1021 __IO uint32_t usart2rst : 1; /* [17] */
1022 __IO uint32_t usart3rst : 1; /* [18] */
1023 __IO uint32_t uart4rst : 1; /* [19] */
1024 __IO uint32_t uart5rst : 1; /* [20] */
1025 __IO uint32_t i2c1rst : 1; /* [21] */
1026 __IO uint32_t i2c2rst : 1; /* [22] */
1027 __IO uint32_t i2c3rst : 1; /* [23] */
1028 __IO uint32_t reserved4 : 1; /* [24] */
1029 __IO uint32_t can1rst : 1; /* [25] */
1030 __IO uint32_t can2rst : 1; /* [26] */
1031 __IO uint32_t reserved5 : 1; /* [27] */
1032 __IO uint32_t pwcrst : 1; /* [28] */
1033 __IO uint32_t dacrst : 1; /* [29] */
1034 __IO uint32_t uart7rst : 1; /* [30] */
1035 __IO uint32_t uart8rst : 1; /* [31] */
1036 } apb1rst_bit;
1037 };
1038
1039 /**
1040 * @brief crm apb2rst register, offset:0x24
1041 */
1042 union
1043 {
1044 __IO uint32_t apb2rst;
1045 struct
1046 {
1047 __IO uint32_t tmr1rst : 1; /* [0] */
1048 __IO uint32_t tmr8rst : 1; /* [1] */
1049 __IO uint32_t reserved1 : 2; /* [3:2] */
1050 __IO uint32_t usart1rst : 1; /* [4] */
1051 __IO uint32_t usart6rst : 1; /* [5] */
1052 __IO uint32_t reserved2 : 2; /* [7:6] */
1053 __IO uint32_t adcrst : 1; /* [8] */
1054 __IO uint32_t reserved3 : 3; /* [11:9] */
1055 __IO uint32_t spi1rst : 1; /* [12] */
1056 __IO uint32_t spi4rst : 1; /* [13] */
1057 __IO uint32_t scfgrst : 1; /* [14] */
1058 __IO uint32_t reserved4 : 1; /* [15] */
1059 __IO uint32_t tmr9rst : 1; /* [16] */
1060 __IO uint32_t tmr10rst : 1; /* [17] */
1061 __IO uint32_t tmr11rst : 1; /* [18] */
1062 __IO uint32_t reserved5 : 1; /* [19] */
1063 __IO uint32_t tmr20rst : 1; /* [20] */
1064 __IO uint32_t reserved6 : 8; /* [28:21] */
1065 __IO uint32_t accrst : 1; /* [29] */
1066 __IO uint32_t reserved7 : 2; /* [31:30] */
1067 } apb2rst_bit;
1068 };
1069
1070 /**
1071 * @brief crm reserved2 register, offset:0x28~0x2C
1072 */
1073 __IO uint32_t reserved2[2];
1074
1075 /**
1076 * @brief crm ahben1 register, offset:0x30
1077 */
1078 union
1079 {
1080 __IO uint32_t ahben1;
1081 #if defined (AT32F435xx)
1082 struct
1083 {
1084 __IO uint32_t gpioaen : 1; /* [0] */
1085 __IO uint32_t gpioben : 1; /* [1] */
1086 __IO uint32_t gpiocen : 1; /* [2] */
1087 __IO uint32_t gpioden : 1; /* [3] */
1088 __IO uint32_t gpioeen : 1; /* [4] */
1089 __IO uint32_t gpiofen : 1; /* [5] */
1090 __IO uint32_t gpiogen : 1; /* [6] */
1091 __IO uint32_t gpiohen : 1; /* [7] */
1092 __IO uint32_t reserved1 : 4; /* [11:8] */
1093 __IO uint32_t crcen : 1; /* [12] */
1094 __IO uint32_t reserved2 : 8; /* [20:13] */
1095 __IO uint32_t edmaen : 1; /* [21] */
1096 __IO uint32_t dma1en : 1; /* [22] */
1097 __IO uint32_t reserved3 : 1; /* [23] */
1098 __IO uint32_t dma2en : 1; /* [24] */
1099 __IO uint32_t reserved4 : 4; /* [28:25] */
1100 __IO uint32_t otgfs2en : 1; /* [29] */
1101 __IO uint32_t reserved5 : 2; /* [31:30] */
1102 } ahben1_bit;
1103 #endif
1104
1105 #if defined (AT32F437xx)
1106 struct
1107 {
1108 __IO uint32_t gpioaen : 1; /* [0] */
1109 __IO uint32_t gpioben : 1; /* [1] */
1110 __IO uint32_t gpiocen : 1; /* [2] */
1111 __IO uint32_t gpioden : 1; /* [3] */
1112 __IO uint32_t gpioeen : 1; /* [4] */
1113 __IO uint32_t gpiofen : 1; /* [5] */
1114 __IO uint32_t gpiogen : 1; /* [6] */
1115 __IO uint32_t gpiohen : 1; /* [7] */
1116 __IO uint32_t reserved1 : 4; /* [11:8] */
1117 __IO uint32_t crcen : 1; /* [12] */
1118 __IO uint32_t reserved2 : 8; /* [20:13] */
1119 __IO uint32_t edmaen : 1; /* [21] */
1120 __IO uint32_t dma1en : 1; /* [22] */
1121 __IO uint32_t reserved3 : 1; /* [23] */
1122 __IO uint32_t dma2en : 1; /* [24] */
1123 __IO uint32_t emacen : 1; /* [25] */
1124 __IO uint32_t reserved4 : 3; /* [28:26] */
1125 __IO uint32_t otgfs2en : 1; /* [29] */
1126 __IO uint32_t reserved5 : 2; /* [31:30] */
1127 } ahben1_bit;
1128 #endif
1129 };
1130
1131 /**
1132 * @brief crm ahben2 register, offset:0x34
1133 */
1134 union
1135 {
1136 __IO uint32_t ahben2;
1137 struct
1138 {
1139 __IO uint32_t dvpen : 1; /* [0] */
1140 __IO uint32_t reserved1 : 6; /* [6:1] */
1141 __IO uint32_t otgfs1en : 1; /* [7] */
1142 __IO uint32_t reserved2 : 7; /* [14:8] */
1143 __IO uint32_t sdio1en : 1; /* [15] */
1144 __IO uint32_t reserved3 : 16;/* [31:16] */
1145 } ahben2_bit;
1146 };
1147
1148 /**
1149 * @brief crm ahben3 register, offset:0x38
1150 */
1151 union
1152 {
1153 __IO uint32_t ahben3;
1154 struct
1155 {
1156 __IO uint32_t xmcen : 1; /* [0] */
1157 __IO uint32_t qspi1en : 1; /* [1] */
1158 __IO uint32_t reserved1 : 12;/* [13:2] */
1159 __IO uint32_t qspi2en : 1; /* [14] */
1160 __IO uint32_t sdio2en : 1; /* [15] */
1161 __IO uint32_t reserved3 : 16;/* [31:16] */
1162 } ahben3_bit;
1163 };
1164
1165 /**
1166 * @brief crm reserved3 register, offset:0x3C
1167 */
1168 __IO uint32_t reserved3;
1169
1170 /**
1171 * @brief crm apb1en register, offset:0x40
1172 */
1173 union
1174 {
1175 __IO uint32_t apb1en;
1176 struct
1177 {
1178 __IO uint32_t tmr2en : 1; /* [0] */
1179 __IO uint32_t tmr3en : 1; /* [1] */
1180 __IO uint32_t tmr4en : 1; /* [2] */
1181 __IO uint32_t tmr5en : 1; /* [3] */
1182 __IO uint32_t tmr6en : 1; /* [4] */
1183 __IO uint32_t tmr7en : 1; /* [5] */
1184 __IO uint32_t tmr12en : 1; /* [6] */
1185 __IO uint32_t tmr13en : 1; /* [7] */
1186 __IO uint32_t adc14en : 1; /* [8] */
1187 __IO uint32_t reserved1 : 2; /* [10:9] */
1188 __IO uint32_t wwdten : 1; /* [11] */
1189 __IO uint32_t reserved2 : 2; /* [13:12] */
1190 __IO uint32_t spi2en : 1; /* [14] */
1191 __IO uint32_t spi3en : 1; /* [15] */
1192 __IO uint32_t reserved3 : 1; /* [16] */
1193 __IO uint32_t usart2en : 1; /* [17] */
1194 __IO uint32_t usart3en : 1; /* [18] */
1195 __IO uint32_t uart4en : 1; /* [19] */
1196 __IO uint32_t uart5en : 1; /* [20] */
1197 __IO uint32_t i2c1en : 1; /* [21] */
1198 __IO uint32_t i2c2en : 1; /* [22] */
1199 __IO uint32_t i2c3en : 1; /* [23] */
1200 __IO uint32_t reserved4 : 1; /* [24] */
1201 __IO uint32_t can1en : 1; /* [25] */
1202 __IO uint32_t can2en : 1; /* [26] */
1203 __IO uint32_t reserved5 : 1; /* [27] */
1204 __IO uint32_t pwcen : 1; /* [28] */
1205 __IO uint32_t dacen : 1; /* [29] */
1206 __IO uint32_t uart7en : 1; /* [30] */
1207 __IO uint32_t uart8en : 1; /* [31] */
1208 } apb1en_bit;
1209 };
1210
1211 /**
1212 * @brief crm apb2en register, offset:0x44
1213 */
1214 union
1215 {
1216 __IO uint32_t apb2en;
1217 struct
1218 {
1219 __IO uint32_t tmr1en : 1; /* [0] */
1220 __IO uint32_t tmr8en : 1; /* [1] */
1221 __IO uint32_t reserved1 : 2; /* [3:2] */
1222 __IO uint32_t usart1en : 1; /* [4] */
1223 __IO uint32_t usart6en : 1; /* [5] */
1224 __IO uint32_t reserved2 : 2; /* [7:6] */
1225 __IO uint32_t adcen : 1; /* [8] */
1226 __IO uint32_t reserved3 : 3; /* [11:9] */
1227 __IO uint32_t spi1en : 1; /* [12] */
1228 __IO uint32_t spi4en : 1; /* [13] */
1229 __IO uint32_t scfgen : 1; /* [14] */
1230 __IO uint32_t reserved4 : 1; /* [15] */
1231 __IO uint32_t tmr9en : 1; /* [16] */
1232 __IO uint32_t tmr10en : 1; /* [17] */
1233 __IO uint32_t tmr11en : 1; /* [18] */
1234 __IO uint32_t reserved5 : 1; /* [19] */
1235 __IO uint32_t tmr20en : 1; /* [20] */
1236 __IO uint32_t reserved6 : 8; /* [28:21] */
1237 __IO uint32_t accen : 1; /* [29] */
1238 __IO uint32_t reserved7 : 2; /* [31:30] */
1239 } apb2en_bit;
1240 };
1241
1242 /**
1243 * @brief crm reserved4 register, offset:0x48~0x4C
1244 */
1245 __IO uint32_t reserved4[2];
1246
1247 /**
1248 * @brief crm ahblpen1 register, offset:0x50
1249 */
1250 union
1251 {
1252 __IO uint32_t ahblpen1;
1253 #if defined (AT32F435xx)
1254 struct
1255 {
1256 __IO uint32_t gpioalpen : 1; /* [0] */
1257 __IO uint32_t gpioblpen : 1; /* [1] */
1258 __IO uint32_t gpioclpen : 1; /* [2] */
1259 __IO uint32_t gpiodlpen : 1; /* [3] */
1260 __IO uint32_t gpioelpen : 1; /* [4] */
1261 __IO uint32_t gpioflpen : 1; /* [5] */
1262 __IO uint32_t gpioglpen : 1; /* [6] */
1263 __IO uint32_t gpiohlpen : 1; /* [7] */
1264 __IO uint32_t reserved1 : 4; /* [11:8] */
1265 __IO uint32_t crclpen : 1; /* [12] */
1266 __IO uint32_t reserved2 : 8; /* [20:13] */
1267 __IO uint32_t edmalpen : 1; /* [21] */
1268 __IO uint32_t dma1lpen : 1; /* [22] */
1269 __IO uint32_t reserved3 : 1; /* [23] */
1270 __IO uint32_t dma2lpen : 1; /* [24] */
1271 __IO uint32_t reserved4 : 4; /* [28:25] */
1272 __IO uint32_t otgfs2lpen : 1; /* [29] */
1273 __IO uint32_t reserved5 : 2; /* [31:30] */
1274 } ahblpen1_bit;
1275 #endif
1276
1277 #if defined (AT32F437xx)
1278 struct
1279 {
1280 __IO uint32_t gpioalpen : 1; /* [0] */
1281 __IO uint32_t gpioblpen : 1; /* [1] */
1282 __IO uint32_t gpioclpen : 1; /* [2] */
1283 __IO uint32_t gpiodlpen : 1; /* [3] */
1284 __IO uint32_t gpioelpen : 1; /* [4] */
1285 __IO uint32_t gpioflpen : 1; /* [5] */
1286 __IO uint32_t gpioglpen : 1; /* [6] */
1287 __IO uint32_t gpiohlpen : 1; /* [7] */
1288 __IO uint32_t reserved1 : 4; /* [11:8] */
1289 __IO uint32_t crclpen : 1; /* [12] */
1290 __IO uint32_t reserved2 : 8; /* [20:13] */
1291 __IO uint32_t edmalpen : 1; /* [21] */
1292 __IO uint32_t dma1lpen : 1; /* [22] */
1293 __IO uint32_t reserved3 : 1; /* [23] */
1294 __IO uint32_t dma2lpen : 1; /* [24] */
1295 __IO uint32_t emaclpen : 1; /* [25] */
1296 __IO uint32_t reserved4 : 3; /* [28:26] */
1297 __IO uint32_t otgfs2lpen : 1; /* [29] */
1298 __IO uint32_t reserved5 : 2; /* [31:30] */
1299 } ahblpen1_bit;
1300 #endif
1301 };
1302
1303 /**
1304 * @brief crm ahblpen2 register, offset:0x54
1305 */
1306 union
1307 {
1308 __IO uint32_t ahblpen2;
1309 struct
1310 {
1311 __IO uint32_t dvplpen : 1; /* [0] */
1312 __IO uint32_t reserved1 : 6; /* [6:1] */
1313 __IO uint32_t otgfs1lpen : 1; /* [7] */
1314 __IO uint32_t reserved2 : 7; /* [14:8] */
1315 __IO uint32_t sdio1lpen : 1; /* [15] */
1316 __IO uint32_t reserved3 : 16;/* [31:16] */
1317 } ahblpen2_bit;
1318 };
1319
1320 /**
1321 * @brief crm ahblpen3 register, offset:0x58
1322 */
1323 union
1324 {
1325 __IO uint32_t ahblpen3;
1326 struct
1327 {
1328 __IO uint32_t xmclpen : 1; /* [0] */
1329 __IO uint32_t qspi1lpen : 1; /* [1] */
1330 __IO uint32_t reserved1 : 12;/* [13:2] */
1331 __IO uint32_t qspi2lpen : 1; /* [14] */
1332 __IO uint32_t sdio2lpen : 1; /* [15] */
1333 __IO uint32_t reserved3 : 16;/* [31:16] */
1334 } ahblpen3_bit;
1335 };
1336
1337 /**
1338 * @brief crm reserved5 register, offset:0x5C
1339 */
1340 __IO uint32_t reserved5;
1341
1342 /**
1343 * @brief crm apb1lpen register, offset:0x60
1344 */
1345 union
1346 {
1347 __IO uint32_t apb1lpen;
1348 struct
1349 {
1350 __IO uint32_t tmr2lpen : 1; /* [0] */
1351 __IO uint32_t tmr3lpen : 1; /* [1] */
1352 __IO uint32_t tmr4lpen : 1; /* [2] */
1353 __IO uint32_t tmr5lpen : 1; /* [3] */
1354 __IO uint32_t tmr6lpen : 1; /* [4] */
1355 __IO uint32_t tmr7lpen : 1; /* [5] */
1356 __IO uint32_t tmr12lpen : 1; /* [6] */
1357 __IO uint32_t tmr13lpen : 1; /* [7] */
1358 __IO uint32_t adc14lpen : 1; /* [8] */
1359 __IO uint32_t reserved1 : 2; /* [10:9] */
1360 __IO uint32_t wwdtlpen : 1; /* [11] */
1361 __IO uint32_t reserved2 : 2; /* [13:12] */
1362 __IO uint32_t spi2lpen : 1; /* [14] */
1363 __IO uint32_t spi3lpen : 1; /* [15] */
1364 __IO uint32_t reserved3 : 1; /* [16] */
1365 __IO uint32_t usart2lpen : 1; /* [17] */
1366 __IO uint32_t usart3lpen : 1; /* [18] */
1367 __IO uint32_t uart4lpen : 1; /* [19] */
1368 __IO uint32_t uart5lpen : 1; /* [20] */
1369 __IO uint32_t i2c1lpen : 1; /* [21] */
1370 __IO uint32_t i2c2lpen : 1; /* [22] */
1371 __IO uint32_t i2c3lpen : 1; /* [23] */
1372 __IO uint32_t reserved4 : 1; /* [24] */
1373 __IO uint32_t can1lpen : 1; /* [25] */
1374 __IO uint32_t can2lpen : 1; /* [26] */
1375 __IO uint32_t reserved5 : 1; /* [27] */
1376 __IO uint32_t pwclpen : 1; /* [28] */
1377 __IO uint32_t daclpen : 1; /* [29] */
1378 __IO uint32_t uart7lpen : 1; /* [30] */
1379 __IO uint32_t uart8lpen : 1; /* [31] */
1380 } apb1lpen_bit;
1381 };
1382
1383 /**
1384 * @brief crm apb2lpen register, offset:0x64
1385 */
1386 union
1387 {
1388 __IO uint32_t apb2lpen;
1389 struct
1390 {
1391 __IO uint32_t tmr1lpen : 1; /* [0] */
1392 __IO uint32_t tmr8lpen : 1; /* [1] */
1393 __IO uint32_t reserved1 : 2; /* [3:2] */
1394 __IO uint32_t usart1lpen : 1; /* [4] */
1395 __IO uint32_t usart6lpen : 1; /* [5] */
1396 __IO uint32_t reserved2 : 2; /* [7:6] */
1397 __IO uint32_t adclpen : 1; /* [8] */
1398 __IO uint32_t reserved3 : 3; /* [11:9] */
1399 __IO uint32_t spi1lpen : 1; /* [12] */
1400 __IO uint32_t spi4lpen : 1; /* [13] */
1401 __IO uint32_t scfglpen : 1; /* [14] */
1402 __IO uint32_t reserved4 : 1; /* [15] */
1403 __IO uint32_t tmr9lpen : 1; /* [16] */
1404 __IO uint32_t tmr10lpen : 1; /* [17] */
1405 __IO uint32_t tmr11lpen : 1; /* [18] */
1406 __IO uint32_t reserved5 : 1; /* [19] */
1407 __IO uint32_t tmr20lpen : 1; /* [20] */
1408 __IO uint32_t reserved6 : 8; /* [28:21] */
1409 __IO uint32_t acclpen : 1; /* [29] */
1410 __IO uint32_t reserved7 : 2; /* [31:30] */
1411 } apb2lpen_bit;
1412 };
1413
1414 /**
1415 * @brief crm reserved6 register, offset:0x68~0x6C
1416 */
1417 __IO uint32_t reserved6[2];
1418
1419 /**
1420 * @brief crm bpdc register, offset:0x70
1421 */
1422 union
1423 {
1424 __IO uint32_t bpdc;
1425 struct
1426 {
1427 __IO uint32_t lexten : 1; /* [0] */
1428 __IO uint32_t lextstbl : 1; /* [1] */
1429 __IO uint32_t lextbyps : 1; /* [2] */
1430 __IO uint32_t reserved1 : 5; /* [7:3] */
1431 __IO uint32_t ertcsel : 2; /* [9:8] */
1432 __IO uint32_t reserved2 : 5; /* [14:10] */
1433 __IO uint32_t ertcen : 1; /* [15] */
1434 __IO uint32_t bpdrst : 1; /* [16] */
1435 __IO uint32_t reserved3 : 15;/* [31:17] */
1436 } bpdc_bit;
1437 };
1438
1439 /**
1440 * @brief crm ctrlsts register, offset:0x74
1441 */
1442 union
1443 {
1444 __IO uint32_t ctrlsts;
1445 struct
1446 {
1447 __IO uint32_t licken : 1; /* [0] */
1448 __IO uint32_t lickstbl : 1; /* [1] */
1449 __IO uint32_t reserved1 : 22;/* [23:2] */
1450 __IO uint32_t rstfc : 1; /* [24] */
1451 __IO uint32_t reserved2 : 1; /* [25] */
1452 __IO uint32_t nrstf : 1; /* [26] */
1453 __IO uint32_t porrstf : 1; /* [27] */
1454 __IO uint32_t swrstf : 1; /* [28] */
1455 __IO uint32_t wdtrstf : 1; /* [29] */
1456 __IO uint32_t wwdtrstf : 1; /* [30] */
1457 __IO uint32_t lprstf : 1; /* [31] */
1458 } ctrlsts_bit;
1459 };
1460
1461 /**
1462 * @brief crm reserved7 register, offset:0x78~0x9C
1463 */
1464 __IO uint32_t reserved7[10];
1465
1466 /**
1467 * @brief crm misc1 register, offset:0xA0
1468 */
1469 union
1470 {
1471 __IO uint32_t misc1;
1472 struct
1473 {
1474 __IO uint32_t hickcal_key : 8; /* [7:0] */
1475 __IO uint32_t reserved1 : 4; /* [11:8] */
1476 __IO uint32_t hickdiv : 1; /* [12] */
1477 __IO uint32_t hick_to_usb : 1; /* [13] */
1478 __IO uint32_t hick_to_sclk : 1; /* [14] */
1479 __IO uint32_t reserved2 : 1; /* [15] */
1480 __IO uint32_t clkout2_sel2 : 4; /* [19:16] */
1481 __IO uint32_t reserved3 : 4; /* [23:20] */
1482 __IO uint32_t clkout1div2 : 4; /* [27:24] */
1483 __IO uint32_t clkout2div2 : 4; /* [31:28] */
1484 } misc1_bit;
1485 };
1486
1487 /**
1488 * @brief crm misc2 register, offset:0xA4
1489 */
1490 union
1491 {
1492 __IO uint32_t misc2;
1493 struct
1494 {
1495 __IO uint32_t reserved1 : 4; /* [3:0] */
1496 __IO uint32_t auto_step_en : 2; /* [5:4] */
1497 __IO uint32_t reserved2 : 2; /* [7:6] */
1498 __IO uint32_t clk_to_tmr : 1; /* [8] */
1499 __IO uint32_t emac_pps_sel : 1; /* [9] */
1500 __IO uint32_t reserved3 : 2; /* [11:10] */
1501 __IO uint32_t usbdiv : 4; /* [15:12] */
1502 __IO uint32_t reserved4 : 16;/* [31:16] */
1503 } misc2_bit;
1504 };
1505
1506 } crm_type;
1507
1508 /**
1509 * @}
1510 */
1511
1512 #define CRM ((crm_type *) CRM_BASE)
1513
1514 /** @defgroup CRM_exported_functions
1515 * @{
1516 */
1517
1518 void crm_reset(void);
1519 void crm_lext_bypass(confirm_state new_state);
1520 void crm_hext_bypass(confirm_state new_state);
1521 flag_status crm_flag_get(uint32_t flag);
1522 error_status crm_hext_stable_wait(void);
1523 void crm_hick_clock_trimming_set(uint8_t trim_value);
1524 void crm_hick_clock_calibration_set(uint8_t cali_value);
1525 void crm_periph_clock_enable(crm_periph_clock_type value, confirm_state new_state);
1526 void crm_periph_reset(crm_periph_reset_type value, confirm_state new_state);
1527 void crm_periph_lowpower_mode_enable(crm_periph_clock_lowpower_type value, confirm_state new_state);
1528 void crm_clock_source_enable(crm_clock_source_type source, confirm_state new_state);
1529 void crm_flag_clear(uint32_t flag);
1530 void crm_ertc_clock_select(crm_ertc_clock_type value);
1531 void crm_ertc_clock_enable(confirm_state new_state);
1532 void crm_ahb_div_set(crm_ahb_div_type value);
1533 void crm_apb1_div_set(crm_apb1_div_type value);
1534 void crm_apb2_div_set(crm_apb2_div_type value);
1535 void crm_usb_clock_div_set(crm_usb_div_type value);
1536 void crm_clock_failure_detection_enable(confirm_state new_state);
1537 void crm_battery_powered_domain_reset(confirm_state new_state);
1538 void crm_auto_step_mode_enable(confirm_state new_state);
1539 void crm_hick_divider_select(crm_hick_div_6_type value);
1540 void crm_hick_sclk_frequency_select(crm_hick_sclk_frequency_type value);
1541 void crm_usb_clock_source_select(crm_usb_clock_source_type value);
1542 void crm_clkout_to_tmr10_enable(confirm_state new_state);
1543 void crm_pll_config(crm_pll_clock_source_type clock_source, uint16_t pll_ns, \
1544 uint16_t pll_ms, crm_pll_fr_type pll_fr);
1545 void crm_sysclk_switch(crm_sclk_type value);
1546 crm_sclk_type crm_sysclk_switch_status_get(void);
1547 void crm_clocks_freq_get(crm_clocks_freq_type *clocks_struct);
1548 void crm_clock_out1_set(crm_clkout1_select_type clkout);
1549 void crm_clock_out2_set(crm_clkout2_select_type clkout);
1550 void crm_clkout_div_set(crm_clkout_index_type index, crm_clkout_div1_type div1, crm_clkout_div2_type div2);
1551 void crm_emac_output_pulse_set(crm_emac_output_pulse_type width);
1552 void crm_interrupt_enable(uint32_t crm_int, confirm_state new_state);
1553 error_status crm_pll_parameter_calculate(crm_pll_clock_source_type pll_rcs, uint32_t target_sclk_freq, \
1554 uint16_t *ret_ms, uint16_t *ret_ns, uint16_t *ret_fr);
1555
1556 /**
1557 * @}
1558 */
1559
1560 /**
1561 * @}
1562 */
1563
1564 /**
1565 * @}
1566 */
1567
1568 #ifdef __cplusplus
1569 }
1570 #endif
1571
1572 #endif
INAV: Navigation-enabled flight control software