lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_debug.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_mcudbg.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 mcudbg header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* Define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_MCUDBG_H
  29 #define __AT32F435_437_MCUDBG_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup DEBUG
  44   * @{
  45   */
  46
  47 /** @defgroup DEBUG_mode_definition
  48   * @{
  49   */
  50
  51 /* debug ctrl register bit */
  52 #define DEBUG_SLEEP                      0x00000001 /*!< debug sleep mode */
  53 #define DEBUG_DEEPSLEEP                  0x00000002 /*!< debug deepsleep mode */
  54 #define DEBUG_STANDBY                    0x00000004 /*!< debug standby mode */
  55
  56 /* debug apb1 frz register bit */
  57 #define DEBUG_TMR2_PAUSE                 0x00000001 /*!< debug timer2 pause */
  58 #define DEBUG_TMR3_PAUSE                 0x00000002 /*!< debug timer3 pause */
  59 #define DEBUG_TMR4_PAUSE                 0x00000004 /*!< debug timer4 pause */
  60 #define DEBUG_TMR5_PAUSE                 0x00000008 /*!< debug timer5 pause */
  61 #define DEBUG_TMR6_PAUSE                 0x00000010 /*!< debug timer6 pause */
  62 #define DEBUG_TMR7_PAUSE                 0x00000020 /*!< debug timer7 pause */
  63 #define DEBUG_TMR12_PAUSE                0x00000040 /*!< debug timer12 pause */
  64 #define DEBUG_TMR13_PAUSE                0x00000080 /*!< debug timer13 pause */
  65 #define DEBUG_TMR14_PAUSE                0x00000100 /*!< debug timer14 pause */
  66 #define DEBUG_ERTC_PAUSE                 0x00000400 /*!< debug ertc pause */
  67 #define DEBUG_WWDT_PAUSE                 0x00000800 /*!< debug window watchdog timer pause */
  68 #define DEBUG_WDT_PAUSE                  0x00001000 /*!< debug watchdog timer pause */
  69 #define DEBUG_ERTC_512_PAUSE             0x00008000 /*!< debug ertc_512 pause */
  70 #define DEBUG_I2C1_SMBUS_TIMEOUT         0x01000000 /*!< debug i2c1 smbus timeout */
  71 #define DEBUG_I2C2_SMBUS_TIMEOUT         0x08000000 /*!< debug i2c2 smbus timeout */
  72 #define DEBUG_I2C3_SMBUS_TIMEOUT         0x10000000 /*!< debug i2c3 smbus timeout */
  73 #define DEBUG_CAN1_PAUSE                 0x02000000 /*!< debug can1 pause */
  74 #define DEBUG_CAN2_PAUSE                 0x04000000 /*!< debug can2 pause */
  75
  76 /* debug apb2 frz register bit */
  77 #define DEBUG_TMR1_PAUSE                 0x00000001 /*!< debug timer1 pause */
  78 #define DEBUG_TMR8_PAUSE                 0x00000002 /*!< debug timer8 pause */
  79 #define DEBUG_TMR20_PAUSE                0x00000040 /*!< debug timer20 pause */
  80 #define DEBUG_TMR9_PAUSE                 0x00010000 /*!< debug timer9 pause */
  81 #define DEBUG_TMR10_PAUSE                0x00020000 /*!< debug timer10 pause */
  82 #define DEBUG_TMR11_PAUSE                0x00040000 /*!< debug timer11 pause */
  83
  84 /**
  85   * @}
  86   */
  87
  88 /** @defgroup DEBUG_exported_types
  89   * @{
  90   */
  91
  92 /**
  93   * @brief type define debug register all
  94   */
  95 typedef struct
  96 {
  97   /**
  98     * @brief debug idcode register, offset:0x00
  99     */
 100   union
 101   {
 102     __IO uint32_t pid;
 103     struct
 104     {
 105       __IO uint32_t pid                  : 32;/* [31:0] */
 106     } idcode_bit;
 107   };
 108
 109   /**
 110     * @brief debug ctrl register, offset:0x04
 111     */
 112   union
 113   {
 114     __IO uint32_t ctrl;
 115     struct
 116     {
 117       __IO uint32_t sleep_debug          : 1;/* [0] */
 118       __IO uint32_t deepsleep_debug      : 1;/* [1] */
 119       __IO uint32_t standby_debug        : 1;/* [2] */
 120       __IO uint32_t reserved1            : 29;/* [31:3] */
 121     } ctrl_bit;
 122   };
 123   /**
 124     * @brief debug apb1 frz register, offset:0x08
 125     */
 126   union
 127   {
 128     __IO uint32_t apb1_frz;
 129     struct
 130     {
 131       __IO uint32_t tmr2_pause           : 1;/* [0] */
 132       __IO uint32_t tmr3_pause           : 1;/* [1] */
 133       __IO uint32_t tmr4_pause           : 1;/* [2] */
 134       __IO uint32_t tmr5_pause           : 1;/* [3] */
 135       __IO uint32_t tmr6_pause           : 1;/* [4] */
 136       __IO uint32_t tmr7_pause           : 1;/* [5] */
 137       __IO uint32_t tmr12_pause          : 1;/* [6] */
 138       __IO uint32_t tmr13_pause          : 1;/* [7] */
 139       __IO uint32_t tmr14_pause          : 1;/* [8] */
 140       __IO uint32_t reserved1            : 1;/* [9] */
 141       __IO uint32_t ertc_pause           : 1;/* [10] */
 142       __IO uint32_t wwdt_pause           : 1;/* [11] */
 143       __IO uint32_t wdt_pause            : 1;/* [12] */
 144       __IO uint32_t reserved2            : 2;/* [14:13] */
 145       __IO uint32_t ertc_512_pause       : 1;/* [15] */
 146       __IO uint32_t reserved3            : 8;/* [23:16] */
 147       __IO uint32_t i2c1_smbus_timeout   : 1;/* [24] */
 148       __IO uint32_t can1_pause           : 1;/* [25] */
 149       __IO uint32_t can2_pause           : 1;/* [26] */
 150       __IO uint32_t i2c2_smbus_timeout   : 1;/* [27] */
 151       __IO uint32_t i2c3_smbus_timeout   : 1;/* [28] */
 152       __IO uint32_t reserved4            : 3;/* [31:29] */
 153     } apb1_frz_bit;
 154   };
 155   /**
 156     * @brief debug apb2 frz register, offset:0x0c
 157     */
 158   union
 159   {
 160     __IO uint32_t apb2_frz;
 161     struct
 162     {
 163       __IO uint32_t tmr1_pause           : 1;/* [0] */
 164       __IO uint32_t tmr8_pause           : 1;/* [1] */
 165       __IO uint32_t reserved1            : 4;/* [5:2] */
 166       __IO uint32_t tmr20_pause          : 1;/* [6] */
 167       __IO uint32_t reserved2            : 9;/* [15:7] */
 168       __IO uint32_t tmr9_pause           : 1;/* [16] */
 169       __IO uint32_t tmr10_pause          : 1;/* [17] */
 170       __IO uint32_t tmr11_pause          : 1;/* [18] */
 171       __IO uint32_t reserved3            : 13;/* [31:19] */
 172     } apb2_frz_bit;
 173   };
 174
 175 } debug_type;
 176
 177 /**
 178   * @}
 179   */
 180
 181 #define DEBUGMCU                         ((debug_type *) DEBUG_BASE)
 182
 183 /** @defgroup DEBUG_exported_functions
 184   * @{
 185   */
 186
 187 uint32_t debug_device_id_get(void);
 188 void debug_low_power_mode_set(uint32_t low_power_mode, confirm_state new_state);
 189 void debug_apb1_periph_mode_set(uint32_t apb1_periph, confirm_state new_state);
 190 void debug_apb2_periph_mode_set(uint32_t apb2_periph, confirm_state new_state);
 191
 192 /**
 193   * @}
 194   */
 195
 196 /**
 197   * @}
 198   */
 199
 200 /**
 201   * @}
 202   */
 203
 204 #ifdef __cplusplus
 205 }
 206 #endif
 207
 208 #endif