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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_dma.h
blob695d2feb903b297248c7437f87181142d8fd871e
1 /**
2 **************************************************************************
3 * @file at32f435_437_dma.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 dma header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_DMA_H
29 #define __AT32F435_437_DMA_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup DMA
44 * @{
45 */
46
47 /** @defgroup DMA_interrupts_definition
48 * @brief dma interrupt
49 * @{
50 */
51
52 #define DMA_FDT_INT ((uint32_t)0x00000002) /*!< dma full data transfer interrupt */
53 #define DMA_HDT_INT ((uint32_t)0x00000004) /*!< dma half data transfer interrupt */
54 #define DMA_DTERR_INT ((uint32_t)0x00000008) /*!< dma errorr interrupt */
55
56 /**
57 * @}
58 */
59
60 /** @defgroup DMA_flags_definition
61 * @brief edma flag
62 * @{
63 */
64
65 #define DMA1_GL1_FLAG ((uint32_t)0x00000001) /*!< dma1 channel1 global flag */
66 #define DMA1_FDT1_FLAG ((uint32_t)0x00000002) /*!< dma1 channel1 full data transfer flag */
67 #define DMA1_HDT1_FLAG ((uint32_t)0x00000004) /*!< dma1 channel1 half data transfer flag */
68 #define DMA1_DTERR1_FLAG ((uint32_t)0x00000008) /*!< dma1 channel1 error flag */
69 #define DMA1_GL2_FLAG ((uint32_t)0x00000010) /*!< dma1 channel2 global flag */
70 #define DMA1_FDT2_FLAG ((uint32_t)0x00000020) /*!< dma1 channel2 full data transfer flag */
71 #define DMA1_HDT2_FLAG ((uint32_t)0x00000040) /*!< dma1 channel2 half data transfer flag */
72 #define DMA1_DTERR2_FLAG ((uint32_t)0x00000080) /*!< dma1 channel2 error flag */
73 #define DMA1_GL3_FLAG ((uint32_t)0x00000100) /*!< dma1 channel3 global flag */
74 #define DMA1_FDT3_FLAG ((uint32_t)0x00000200) /*!< dma1 channel3 full data transfer flag */
75 #define DMA1_HDT3_FLAG ((uint32_t)0x00000400) /*!< dma1 channel3 half data transfer flag */
76 #define DMA1_DTERR3_FLAG ((uint32_t)0x00000800) /*!< dma1 channel3 error flag */
77 #define DMA1_GL4_FLAG ((uint32_t)0x00001000) /*!< dma1 channel4 global flag */
78 #define DMA1_FDT4_FLAG ((uint32_t)0x00002000) /*!< dma1 channel4 full data transfer flag */
79 #define DMA1_HDT4_FLAG ((uint32_t)0x00004000) /*!< dma1 channel4 half data transfer flag */
80 #define DMA1_DTERR4_FLAG ((uint32_t)0x00008000) /*!< dma1 channel4 error flag */
81 #define DMA1_GL5_FLAG ((uint32_t)0x00010000) /*!< dma1 channel5 global flag */
82 #define DMA1_FDT5_FLAG ((uint32_t)0x00020000) /*!< dma1 channel5 full data transfer flag */
83 #define DMA1_HDT5_FLAG ((uint32_t)0x00040000) /*!< dma1 channel5 half data transfer flag */
84 #define DMA1_DTERR5_FLAG ((uint32_t)0x00080000) /*!< dma1 channel5 error flag */
85 #define DMA1_GL6_FLAG ((uint32_t)0x00100000) /*!< dma1 channel6 global flag */
86 #define DMA1_FDT6_FLAG ((uint32_t)0x00200000) /*!< dma1 channel6 full data transfer flag */
87 #define DMA1_HDT6_FLAG ((uint32_t)0x00400000) /*!< dma1 channel6 half data transfer flag */
88 #define DMA1_DTERR6_FLAG ((uint32_t)0x00800000) /*!< dma1 channel6 error flag */
89 #define DMA1_GL7_FLAG ((uint32_t)0x01000000) /*!< dma1 channel7 global flag */
90 #define DMA1_FDT7_FLAG ((uint32_t)0x02000000) /*!< dma1 channel7 full data transfer flag */
91 #define DMA1_HDT7_FLAG ((uint32_t)0x04000000) /*!< dma1 channel7 half data transfer flag */
92 #define DMA1_DTERR7_FLAG ((uint32_t)0x08000000) /*!< dma1 channel7 error flag */
93
94 #define DMA2_GL1_FLAG ((uint32_t)0x10000001) /*!< dma2 channel1 global flag */
95 #define DMA2_FDT1_FLAG ((uint32_t)0x10000002) /*!< dma2 channel1 full data transfer flag */
96 #define DMA2_HDT1_FLAG ((uint32_t)0x10000004) /*!< dma2 channel1 half data transfer flag */
97 #define DMA2_DTERR1_FLAG ((uint32_t)0x10000008) /*!< dma2 channel1 error flag */
98 #define DMA2_GL2_FLAG ((uint32_t)0x10000010) /*!< dma2 channel2 global flag */
99 #define DMA2_FDT2_FLAG ((uint32_t)0x10000020) /*!< dma2 channel2 full data transfer flag */
100 #define DMA2_HDT2_FLAG ((uint32_t)0x10000040) /*!< dma2 channel2 half data transfer flag */
101 #define DMA2_DTERR2_FLAG ((uint32_t)0x10000080) /*!< dma2 channel2 error flag */
102 #define DMA2_GL3_FLAG ((uint32_t)0x10000100) /*!< dma2 channel3 global flag */
103 #define DMA2_FDT3_FLAG ((uint32_t)0x10000200) /*!< dma2 channel3 full data transfer flag */
104 #define DMA2_HDT3_FLAG ((uint32_t)0x10000400) /*!< dma2 channel3 half data transfer flag */
105 #define DMA2_DTERR3_FLAG ((uint32_t)0x10000800) /*!< dma2 channel3 error flag */
106 #define DMA2_GL4_FLAG ((uint32_t)0x10001000) /*!< dma2 channel4 global flag */
107 #define DMA2_FDT4_FLAG ((uint32_t)0x10002000) /*!< dma2 channel4 full data transfer flag */
108 #define DMA2_HDT4_FLAG ((uint32_t)0x10004000) /*!< dma2 channel4 half data transfer flag */
109 #define DMA2_DTERR4_FLAG ((uint32_t)0x10008000) /*!< dma2 channel4 error flag */
110 #define DMA2_GL5_FLAG ((uint32_t)0x10010000) /*!< dma2 channel5 global flag */
111 #define DMA2_FDT5_FLAG ((uint32_t)0x10020000) /*!< dma2 channel5 full data transfer flag */
112 #define DMA2_HDT5_FLAG ((uint32_t)0x10040000) /*!< dma2 channel5 half data transfer flag */
113 #define DMA2_DTERR5_FLAG ((uint32_t)0x10080000) /*!< dma2 channel5 error flag */
114 #define DMA2_GL6_FLAG ((uint32_t)0x10100000) /*!< dma2 channel6 global flag */
115 #define DMA2_FDT6_FLAG ((uint32_t)0x10200000) /*!< dma2 channel6 full data transfer flag */
116 #define DMA2_HDT6_FLAG ((uint32_t)0x10400000) /*!< dma2 channel6 half data transfer flag */
117 #define DMA2_DTERR6_FLAG ((uint32_t)0x10800000) /*!< dma2 channel6 error flag */
118 #define DMA2_GL7_FLAG ((uint32_t)0x11000000) /*!< dma2 channel7 global flag */
119 #define DMA2_FDT7_FLAG ((uint32_t)0x12000000) /*!< dma2 channel7 full data transfer flag */
120 #define DMA2_HDT7_FLAG ((uint32_t)0x14000000) /*!< dma2 channel7 half data transfer flag */
121 #define DMA2_DTERR7_FLAG ((uint32_t)0x18000000) /*!< dma2 channel7 error flag */
122
123 /**
124 * @brief dmamux flag
125 */
126 #define DMAMUX_SYNC_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux channel1 synchronization overrun event flag */
127 #define DMAMUX_SYNC_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux channel2 synchronization overrun event flag */
128 #define DMAMUX_SYNC_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux channel3 synchronization overrun event flag */
129 #define DMAMUX_SYNC_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux channel4 synchronization overrun event flag */
130 #define DMAMUX_SYNC_OV5_FLAG ((uint32_t)0x00000010) /*!< dmamux channel5 synchronization overrun event flag */
131 #define DMAMUX_SYNC_OV6_FLAG ((uint32_t)0x00000020) /*!< dmamux channel6 synchronization overrun event flag */
132 #define DMAMUX_SYNC_OV7_FLAG ((uint32_t)0x00000040) /*!< dmamux channel7 synchronization overrun event flag */
133
134 #define DMAMUX_GEN_TRIG_OV1_FLAG ((uint32_t)0x00000001) /*!< dmamux generator channel1 overrun event flag */
135 #define DMAMUX_GEN_TRIG_OV2_FLAG ((uint32_t)0x00000002) /*!< dmamux generator channel2 overrun event flag */
136 #define DMAMUX_GEN_TRIG_OV3_FLAG ((uint32_t)0x00000004) /*!< dmamux generator channel3 overrun event flag */
137 #define DMAMUX_GEN_TRIG_OV4_FLAG ((uint32_t)0x00000008) /*!< dmamux generator channel4 overrun event flag */
138
139 /**
140 * @}
141 */
142
143 /** @defgroup DMA_exported_types
144 * @{
145 */
146
147 /**
148 * @brief dma direction type
149 */
150 typedef enum
151 {
152 DMA_DIR_PERIPHERAL_TO_MEMORY = 0x0000, /*!< dma data transfer direction: peripheral to memory */
153 DMA_DIR_MEMORY_TO_PERIPHERAL = 0x0010, /*!< dma data transfer direction: memory to peripheral */
154 DMA_DIR_MEMORY_TO_MEMORY = 0x4000 /*!< dma data transfer direction: memory to memory */
155 } dma_dir_type;
156
157 /**
158 * @brief dma peripheral data size type
159 */
160 typedef enum
161 {
162 DMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< dma peripheral databus width 8bit */
163 DMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< dma peripheral databus width 16bit */
164 DMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< dma peripheral databus width 32bit */
165 } dma_peripheral_data_size_type;
166
167 /**
168 * @brief dma memory data size type
169 */
170 typedef enum
171 {
172 DMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< dma memory databus width 8bit */
173 DMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< dma memory databus width 16bit */
174 DMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< dma memory databus width 32bit */
175 } dma_memory_data_size_type;
176
177 /**
178 * @brief dma priority level type
179 */
180 typedef enum
181 {
182 DMA_PRIORITY_LOW = 0x00, /*!< dma channel priority: low */
183 DMA_PRIORITY_MEDIUM = 0x01, /*!< dma channel priority: medium */
184 DMA_PRIORITY_HIGH = 0x02, /*!< dma channel priority: high */
185 DMA_PRIORITY_VERY_HIGH = 0x03 /*!< dma channel priority: very high */
186 } dma_priority_level_type;
187
188 /**
189 * @brief dmamux request type
190 */
191 typedef enum
192 {
193 DMAMUX_DMAREQ_ID_REQ_G1 = 0x01, /*!< dmamux channel dma request inputs resources: generator channel1 */
194 DMAMUX_DMAREQ_ID_REQ_G2 = 0x02, /*!< dmamux channel dma request inputs resources: generator channel2 */
195 DMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< dmamux channel dma request inputs resources: generator channel3 */
196 DMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< dmamux channel dma request inputs resources: generator channel4 */
197 DMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< dmamux channel dma request inputs resources: adc1 */
198 DMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< dmamux channel dma request inputs resources: adc2 */
199 DMAMUX_DMAREQ_ID_ADC3 = 0x25, /*!< dmamux channel dma request inputs resources: adc3 */
200 DMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< dmamux channel dma request inputs resources: dac1 */
201 DMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< dmamux channel dma request inputs resources: dac2 */
202 DMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< dmamux channel dma request inputs resources: timer6 overflow */
203 DMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< dmamux channel dma request inputs resources: timer7 overflow */
204 DMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< dmamux channel dma request inputs resources: spi1 rx */
205 DMAMUX_DMAREQ_ID_SPI1_TX = 0x0B, /*!< dmamux channel dma request inputs resources: spi1 tx */
206 DMAMUX_DMAREQ_ID_SPI2_RX = 0x0C, /*!< dmamux channel dma request inputs resources: spi2 rx */
207 DMAMUX_DMAREQ_ID_SPI2_TX = 0x0D, /*!< dmamux channel dma request inputs resources: spi2 tx */
208 DMAMUX_DMAREQ_ID_SPI3_RX = 0x0E, /*!< dmamux channel dma request inputs resources: spi3 rx */
209 DMAMUX_DMAREQ_ID_SPI3_TX = 0x0F, /*!< dmamux channel dma request inputs resources: spi3 tx */
210 DMAMUX_DMAREQ_ID_SPI4_RX = 0x6A, /*!< dmamux channel dma request inputs resources: spi4 rx */
211 DMAMUX_DMAREQ_ID_SPI4_TX = 0x6B, /*!< dmamux channel dma request inputs resources: spi4 tx */
212 DMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E, /*!< dmamux channel dma request inputs resources: i2s2_ext_rx */
213 DMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F, /*!< dmamux channel dma request inputs resources: i2s2_ext_tx */
214 DMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70, /*!< dmamux channel dma request inputs resources: i2s3_ext_rx */
215 DMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71, /*!< dmamux channel dma request inputs resources: i2s3_ext_tx */
216 DMAMUX_DMAREQ_ID_I2C1_RX = 0x10, /*!< dmamux channel dma request inputs resources: i2c1_rx */
217 DMAMUX_DMAREQ_ID_I2C1_TX = 0x11, /*!< dmamux channel dma request inputs resources: i2c1_tx */
218 DMAMUX_DMAREQ_ID_I2C2_RX = 0x12, /*!< dmamux channel dma request inputs resources: i2c2_rx */
219 DMAMUX_DMAREQ_ID_I2C2_TX = 0x13, /*!< dmamux channel dma request inputs resources: i2c2_tx */
220 DMAMUX_DMAREQ_ID_I2C3_RX = 0x14, /*!< dmamux channel dma request inputs resources: i2c3_rx */
221 DMAMUX_DMAREQ_ID_I2C3_TX = 0x15, /*!< dmamux channel dma request inputs resources: i2c3_tx */
222 DMAMUX_DMAREQ_ID_USART1_RX = 0x18, /*!< dmamux channel dma request inputs resources: usart1_rx */
223 DMAMUX_DMAREQ_ID_USART1_TX = 0x19, /*!< dmamux channel dma request inputs resources: usart1_tx */
224 DMAMUX_DMAREQ_ID_USART2_RX = 0x1A, /*!< dmamux channel dma request inputs resources: usart2_rx */
225 DMAMUX_DMAREQ_ID_USART2_TX = 0x1B, /*!< dmamux channel dma request inputs resources: usart2_tx */
226 DMAMUX_DMAREQ_ID_USART3_RX = 0x1C, /*!< dmamux channel dma request inputs resources: usart3_rx */
227 DMAMUX_DMAREQ_ID_USART3_TX = 0x1D, /*!< dmamux channel dma request inputs resources: usart3_tx */
228 DMAMUX_DMAREQ_ID_UART4_RX = 0x1E, /*!< dmamux channel dma request inputs resources: uart4_rx */
229 DMAMUX_DMAREQ_ID_UART4_TX = 0x1F, /*!< dmamux channel dma request inputs resources: uart4_tx */
230 DMAMUX_DMAREQ_ID_UART5_RX = 0x20, /*!< dmamux channel dma request inputs resources: uart5_rx */
231 DMAMUX_DMAREQ_ID_UART5_TX = 0x21, /*!< dmamux channel dma request inputs resources: uart5_tx */
232 DMAMUX_DMAREQ_ID_USART6_RX = 0x72, /*!< dmamux channel dma request inputs resources: usart6_rx */
233 DMAMUX_DMAREQ_ID_USART6_TX = 0x73, /*!< dmamux channel dma request inputs resources: usart6_tx */
234 DMAMUX_DMAREQ_ID_UART7_RX = 0x74, /*!< dmamux channel dma request inputs resources: uart7_rx */
235 DMAMUX_DMAREQ_ID_UART7_TX = 0x75, /*!< dmamux channel dma request inputs resources: uart7_tx */
236 DMAMUX_DMAREQ_ID_UART8_RX = 0x76, /*!< dmamux channel dma request inputs resources: uart8_rx */
237 DMAMUX_DMAREQ_ID_UART8_TX = 0x77, /*!< dmamux channel dma request inputs resources: uart8_tx */
238 DMAMUX_DMAREQ_ID_SDIO1 = 0x27, /*!< dmamux channel dma request inputs resources: sdio1 */
239 DMAMUX_DMAREQ_ID_SDIO2 = 0x67, /*!< dmamux channel dma request inputs resources: sdio2 */
240 DMAMUX_DMAREQ_ID_QSPI1 = 0x28, /*!< dmamux channel dma request inputs resources: qspi1 */
241 DMAMUX_DMAREQ_ID_QSPI2 = 0x68, /*!< dmamux channel dma request inputs resources: qspi2 */
242 DMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A, /*!< dmamux channel dma request inputs resources: timer1 ch1 */
243 DMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B, /*!< dmamux channel dma request inputs resources: timer1 ch2 */
244 DMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C, /*!< dmamux channel dma request inputs resources: timer1 ch3 */
245 DMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< dmamux channel dma request inputs resources: timer1 ch4 */
246 DMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< dmamux channel dma request inputs resources: timer1 overflow */
247 DMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< dmamux channel dma request inputs resources: timer1 trigger */
248 DMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< dmamux channel dma request inputs resources: timer1 hall */
249 DMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31, /*!< dmamux channel dma request inputs resources: timer8 ch1 */
250 DMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32, /*!< dmamux channel dma request inputs resources: timer8 ch2 */
251 DMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33, /*!< dmamux channel dma request inputs resources: timer8 ch3 */
252 DMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34, /*!< dmamux channel dma request inputs resources: timer8 ch4 */
253 DMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35, /*!< dmamux channel dma request inputs resources: timer8 overflow */
254 DMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36, /*!< dmamux channel dma request inputs resources: timer8 trigger */
255 DMAMUX_DMAREQ_ID_TMR8_HALL = 0x37, /*!< dmamux channel dma request inputs resources: timer8 hall */
256 DMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38, /*!< dmamux channel dma request inputs resources: timer2 ch1 */
257 DMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39, /*!< dmamux channel dma request inputs resources: timer2 ch2 */
258 DMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A, /*!< dmamux channel dma request inputs resources: timer2 ch3 */
259 DMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B, /*!< dmamux channel dma request inputs resources: timer2 ch4 */
260 DMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C, /*!< dmamux channel dma request inputs resources: timer2 overflow */
261 DMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E, /*!< dmamux channel dma request inputs resources: timer2 trigger */
262 DMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< dmamux channel dma request inputs resources: timer3 ch1 */
263 DMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< dmamux channel dma request inputs resources: timer3 ch2 */
264 DMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< dmamux channel dma request inputs resources: timer3 ch3 */
265 DMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40, /*!< dmamux channel dma request inputs resources: timer3 ch4 */
266 DMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41, /*!< dmamux channel dma request inputs resources: timer3 overflow */
267 DMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42, /*!< dmamux channel dma request inputs resources: timer3 trigger */
268 DMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43, /*!< dmamux channel dma request inputs resources: timer4 ch1 */
269 DMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44, /*!< dmamux channel dma request inputs resources: timer4 ch2 */
270 DMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45, /*!< dmamux channel dma request inputs resources: timer4 ch3 */
271 DMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46, /*!< dmamux channel dma request inputs resources: timer4 ch4 */
272 DMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47, /*!< dmamux channel dma request inputs resources: timer4 overflow */
273 DMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F, /*!< dmamux channel dma request inputs resources: timer4 trigger */
274 DMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48, /*!< dmamux channel dma request inputs resources: timer5 ch1 */
275 DMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49, /*!< dmamux channel dma request inputs resources: timer5 ch2 */
276 DMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A, /*!< dmamux channel dma request inputs resources: timer5 ch3 */
277 DMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B, /*!< dmamux channel dma request inputs resources: timer5 ch4 */
278 DMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C, /*!< dmamux channel dma request inputs resources: timer5 overflow */
279 DMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D, /*!< dmamux channel dma request inputs resources: timer5 trigger */
280 DMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56, /*!< dmamux channel dma request inputs resources: timer20 ch1 */
281 DMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57, /*!< dmamux channel dma request inputs resources: timer20 ch2 */
282 DMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58, /*!< dmamux channel dma request inputs resources: timer20 ch3 */
283 DMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59, /*!< dmamux channel dma request inputs resources: timer20 ch4 */
284 DMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A, /*!< dmamux channel dma request inputs resources: timer20 overflow */
285 DMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D, /*!< dmamux channel dma request inputs resources: timer20 trigger */
286 DMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E, /*!< dmamux channel dma request inputs resources: timer20 hall */
287 DMAMUX_DMAREQ_ID_DVP = 0x69 /*!< dmamux channel dma request inputs resources: dvp */
288 } dmamux_requst_id_sel_type;
289
290 /**
291 * @brief dmamux sync id type
292 */
293 typedef enum
294 {
295 DMAMUX_SYNC_ID_EXINT0 = 0x00, /*!< dmamux channel synchronization inputs resources: exint line0 */
296 DMAMUX_SYNC_ID_EXINT1 = 0x01, /*!< dmamux channel synchronization inputs resources: exint line1 */
297 DMAMUX_SYNC_ID_EXINT2 = 0x02, /*!< dmamux channel synchronization inputs resources: exint line2 */
298 DMAMUX_SYNC_ID_EXINT3 = 0x03, /*!< dmamux channel synchronization inputs resources: exint line3 */
299 DMAMUX_SYNC_ID_EXINT4 = 0x04, /*!< dmamux channel synchronization inputs resources: exint line4 */
300 DMAMUX_SYNC_ID_EXINT5 = 0x05, /*!< dmamux channel synchronization inputs resources: exint line5 */
301 DMAMUX_SYNC_ID_EXINT6 = 0x06, /*!< dmamux channel synchronization inputs resources: exint line6 */
302 DMAMUX_SYNC_ID_EXINT7 = 0x07, /*!< dmamux channel synchronization inputs resources: exint line7 */
303 DMAMUX_SYNC_ID_EXINT8 = 0x08, /*!< dmamux channel synchronization inputs resources: exint line8 */
304 DMAMUX_SYNC_ID_EXINT9 = 0x09, /*!< dmamux channel synchronization inputs resources: exint line9 */
305 DMAMUX_SYNC_ID_EXINT10 = 0x0A, /*!< dmamux channel synchronization inputs resources: exint line10 */
306 DMAMUX_SYNC_ID_EXINT11 = 0x0B, /*!< dmamux channel synchronization inputs resources: exint line11 */
307 DMAMUX_SYNC_ID_EXINT12 = 0x0C, /*!< dmamux channel synchronization inputs resources: exint line12 */
308 DMAMUX_SYNC_ID_EXINT13 = 0x0D, /*!< dmamux channel synchronization inputs resources: exint line13 */
309 DMAMUX_SYNC_ID_EXINT14 = 0x0E, /*!< dmamux channel synchronization inputs resources: exint line14 */
310 DMAMUX_SYNC_ID_EXINT15 = 0x0F, /*!< dmamux channel synchronization inputs resources: exint line15 */
311 DMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux channel synchronization inputs resources: dmamux channel1 event */
312 DMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux channel synchronization inputs resources: dmamux channel2 event */
313 DMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux channel synchronization inputs resources: dmamux channel3 event */
314 DMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux channel synchronization inputs resources: dmamux channel4 event */
315 DMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux channel synchronization inputs resources: dmamux channel5 event */
316 DMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux channel synchronization inputs resources: dmamux channel6 event */
317 DMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux channel synchronization inputs resources: dmamux channel7 event */
318 } dmamux_sync_id_sel_type;
319
320 /**
321 * @brief dmamux sync polarity type
322 */
323 typedef enum
324 {
325 DMAMUX_SYNC_POLARITY_DISABLE = 0x00, /*!< dmamux channel synchronization inputs resources polarity default value */
326 DMAMUX_SYNC_POLARITY_RISING = 0x01, /*!< dmamux channel synchronization inputs resources polarity: rising */
327 DMAMUX_SYNC_POLARITY_FALLING = 0x02, /*!< dmamux channel synchronization inputs resources polarity: falling */
328 DMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03 /*!< dmamux channel synchronization inputs resources polarity: rising_falling */
329 } dmamux_sync_pol_type;
330
331 /**
332 * @brief dmamux generator id type
333 */
334 typedef enum
335 {
336 DMAMUX_GEN_ID_EXINT0 = 0x00, /*!< dmamux generator channel inputs resources: exint line0 */
337 DMAMUX_GEN_ID_EXINT1 = 0x01, /*!< dmamux generator channel inputs resources: exint line1 */
338 DMAMUX_GEN_ID_EXINT2 = 0x02, /*!< dmamux generator channel inputs resources: exint line2 */
339 DMAMUX_GEN_ID_EXINT3 = 0x03, /*!< dmamux generator channel inputs resources: exint line3 */
340 DMAMUX_GEN_ID_EXINT4 = 0x04, /*!< dmamux generator channel inputs resources: exint line4 */
341 DMAMUX_GEN_ID_EXINT5 = 0x05, /*!< dmamux generator channel inputs resources: exint line5 */
342 DMAMUX_GEN_ID_EXINT6 = 0x06, /*!< dmamux generator channel inputs resources: exint line6 */
343 DMAMUX_GEN_ID_EXINT7 = 0x07, /*!< dmamux generator channel inputs resources: exint line7 */
344 DMAMUX_GEN_ID_EXINT8 = 0x08, /*!< dmamux generator channel inputs resources: exint line8 */
345 DMAMUX_GEN_ID_EXINT9 = 0x09, /*!< dmamux generator channel inputs resources: exint line9 */
346 DMAMUX_GEN_ID_EXINT10 = 0x0A, /*!< dmamux generator channel inputs resources: exint line10 */
347 DMAMUX_GEN_ID_EXINT11 = 0x0B, /*!< dmamux generator channel inputs resources: exint line11 */
348 DMAMUX_GEN_ID_EXINT12 = 0x0C, /*!< dmamux generator channel inputs resources: exint line12 */
349 DMAMUX_GEN_ID_EXINT13 = 0x0D, /*!< dmamux generator channel inputs resources: exint line13 */
350 DMAMUX_GEN_ID_EXINT14 = 0x0E, /*!< dmamux generator channel inputs resources: exint line14 */
351 DMAMUX_GEN_ID_EXINT15 = 0x0F, /*!< dmamux generator channel inputs resources: exint line15 */
352 DMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10, /*!< dmamux generator channel inputs resources: dmamux channel1 event */
353 DMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11, /*!< dmamux generator channel inputs resources: dmamux channel2 event */
354 DMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12, /*!< dmamux generator channel inputs resources: dmamux channel3 event */
355 DMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13, /*!< dmamux generator channel inputs resources: dmamux channel4 event */
356 DMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14, /*!< dmamux generator channel inputs resources: dmamux channel5 event */
357 DMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15, /*!< dmamux generator channel inputs resources: dmamux channel6 event */
358 DMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16 /*!< dmamux generator channel inputs resources: dmamux channel7 event */
359 } dmamux_gen_id_sel_type;
360
361 /**
362 * @brief dmamux generator polarity type
363 */
364 typedef enum
365 {
366 DMAMUX_GEN_POLARITY_DISABLE = 0x00, /*!< dmamux generator channel inputs resources polarity default value */
367 DMAMUX_GEN_POLARITY_RISING = 0x01, /*!< dmamux generator channel inputs resources polarity: rising */
368 DMAMUX_GEN_POLARITY_FALLING = 0x02, /*!< dmamux generator channel inputs resources polarity: falling */
369 DMAMUX_GEN_POLARITY_RISING_FALLING = 0x03 /*!< dmamux generator channel inputs resources polarity: rising_falling */
370 } dmamux_gen_pol_type;
371
372 /**
373 * @brief dma init type
374 */
375 typedef struct
376 {
377 uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
378 uint32_t memory_base_addr; /*!< base addrress for memory */
379 dma_dir_type direction; /*!< dma transmit direction, peripheral as source or as destnation */
380 uint16_t buffer_size; /*!< counter to transfer (0~0xFFFF) */
381 confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
382 confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
383 dma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
384 dma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
385 confirm_state loop_mode_enable; /*!< when loop mode enable, buffer size will reload if count to 0*/
386 dma_priority_level_type priority; /*!< dma priority can choose from very high,high,dedium or low */
387 } dma_init_type;
388
389 /**
390 * @brief dmamux sync init type
391 */
392 typedef struct
393 {
394 dmamux_sync_id_sel_type sync_signal_sel; /*!< dma dmamux synchronization input select */
395 uint32_t sync_polarity; /*!< dma dmamux synchronization polarity */
396 uint32_t sync_request_number; /*!< dma dmamux number of dma requests before an output event is generated */
397 confirm_state sync_event_enable; /*!< dma dmamux event generation disabled */
398 confirm_state sync_enable; /*!< dma dmamux synchronization enable */
399 } dmamux_sync_init_type;
400
401 /**
402 * @brief dmamux generator init type
403 */
404 typedef struct
405 {
406 dmamux_gen_id_sel_type gen_signal_sel; /*!< dma dmamux generator dma request trigger input select */
407 dmamux_gen_pol_type gen_polarity; /*!< dma dmamux generator trigger polarity */
408 uint32_t gen_request_number; /*!< dma dmamux the number of dma requests to be generated after a trigger event */
409 confirm_state gen_enable; /*!< dma dmamux generator enable */
410 } dmamux_gen_init_type;
411
412 /**
413 * @brief type define dma1 register
414 */
415 typedef struct
416 {
417 /**
418 * @brief dma sts register, offset:0x00
419 */
420 union
421 {
422 __IO uint32_t sts;
423 struct
424 {
425 __IO uint32_t gf1 : 1; /* [0] */
426 __IO uint32_t fdtf1 : 1; /* [1] */
427 __IO uint32_t hdtf1 : 1; /* [2] */
428 __IO uint32_t dterrf1 : 1; /* [3] */
429 __IO uint32_t gf2 : 1; /* [4] */
430 __IO uint32_t fdtf2 : 1; /* [5] */
431 __IO uint32_t hdtf2 : 1; /* [6] */
432 __IO uint32_t dterrf2 : 1; /* [7] */
433 __IO uint32_t gf3 : 1; /* [8] */
434 __IO uint32_t fdtf3 : 1; /* [9] */
435 __IO uint32_t hdtf3 : 1; /* [10] */
436 __IO uint32_t dterrf3 : 1; /* [11] */
437 __IO uint32_t gf4 : 1; /* [12] */
438 __IO uint32_t fdtf4 : 1; /* [13] */
439 __IO uint32_t hdtf4 : 1; /* [14] */
440 __IO uint32_t dterrf4 : 1; /* [15] */
441 __IO uint32_t gf5 : 1; /* [16] */
442 __IO uint32_t fdtf5 : 1; /* [17] */
443 __IO uint32_t hdtf5 : 1; /* [18] */
444 __IO uint32_t dterrf5 : 1; /* [19] */
445 __IO uint32_t gf6 : 1; /* [20] */
446 __IO uint32_t fdtf6 : 1; /* [21] */
447 __IO uint32_t hdtf6 : 1; /* [22] */
448 __IO uint32_t dterrf6 : 1; /* [23] */
449 __IO uint32_t gf7 : 1; /* [24] */
450 __IO uint32_t fdtf7 : 1; /* [25] */
451 __IO uint32_t hdtf7 : 1; /* [26] */
452 __IO uint32_t dterrf7 : 1; /* [27] */
453 __IO uint32_t reserved1 : 4; /* [31:28] */
454 } sts_bit;
455 };
456
457 /**
458 * @brief dma clr register, offset:0x04
459 */
460 union
461 {
462 __IO uint32_t clr;
463 struct
464 {
465 __IO uint32_t gfc1 : 1; /* [0] */
466 __IO uint32_t fdtfc1 : 1; /* [1] */
467 __IO uint32_t hdtfc1 : 1; /* [2] */
468 __IO uint32_t dterrfc1 : 1; /* [3] */
469 __IO uint32_t gfc2 : 1; /* [4] */
470 __IO uint32_t fdtfc2 : 1; /* [5] */
471 __IO uint32_t hdtfc2 : 1; /* [6] */
472 __IO uint32_t dterrfc2 : 1; /* [7] */
473 __IO uint32_t gfc3 : 1; /* [8] */
474 __IO uint32_t fdtfc3 : 1; /* [9] */
475 __IO uint32_t hdtfc3 : 1; /* [10] */
476 __IO uint32_t dterrfc3 : 1; /* [11] */
477 __IO uint32_t gfc4 : 1; /* [12] */
478 __IO uint32_t fdtfc4 : 1; /* [13] */
479 __IO uint32_t hdtfc4 : 1; /* [14] */
480 __IO uint32_t dterrfc4 : 1; /* [15] */
481 __IO uint32_t gfc5 : 1; /* [16] */
482 __IO uint32_t fdtfc5 : 1; /* [17] */
483 __IO uint32_t hdtfc5 : 1; /* [18] */
484 __IO uint32_t dterrfc5 : 1; /* [19] */
485 __IO uint32_t gfc6 : 1; /* [20] */
486 __IO uint32_t fdtfc6 : 1; /* [21] */
487 __IO uint32_t hdtfc6 : 1; /* [22] */
488 __IO uint32_t dterrfc6 : 1; /* [23] */
489 __IO uint32_t gfc7 : 1; /* [24] */
490 __IO uint32_t fdtfc7 : 1; /* [25] */
491 __IO uint32_t hdtfc7 : 1; /* [26] */
492 __IO uint32_t dterrfc7 : 1; /* [27] */
493 __IO uint32_t reserved1 : 4; /* [31:28] */
494 } clr_bit;
495 };
496
497 /**
498 * @brief reserved, offset:0x08~0xFC
499 */
500 __IO uint32_t reserved1[62];
501
502 /**
503 * @brief dmamux sel register, offset:0x100
504 */
505 union
506 {
507 __IO uint32_t muxsel;
508 struct
509 {
510 __IO uint32_t tblsel : 1; /* [0] */
511 __IO uint32_t reserved1 : 31;/* [31:1] */
512 }muxsel_bit;
513 };
514
515 /**
516 * @brief reserved, offset:0x104~0x12C
517 */
518 __IO uint32_t reserved2[11];
519
520 /**
521 * @brief dmamux syncsts register, offset:0x130
522 */
523 union
524 {
525 __IO uint32_t muxsyncsts;
526 struct
527 {
528 __IO uint32_t syncovf : 7; /* [6:0] */
529 __IO uint32_t reserved1 : 25;/* [31:7] */
530 }muxsyncsts_bit;
531 };
532
533 /**
534 * @brief dmamux syncclr register, offset:0x134
535 */
536 union
537 {
538 __IO uint32_t muxsyncclr;
539 struct
540 {
541 __IO uint32_t syncovfc : 7; /* [6:0] */
542 __IO uint32_t reserved1 : 25;/* [31:7] */
543 }muxsyncclr_bit;
544 };
545
546 /**
547 * @brief dmamux request generator status register, offset:0x138
548 */
549 union
550 {
551 __IO uint32_t muxgsts;
552 struct
553 {
554 __IO uint32_t trgovf : 4; /* [3:0] */
555 __IO uint32_t reserved1 : 28;/* [31:4] */
556 }muxgsts_bit;
557 };
558 /**
559 * @brief dmamux request generator status clear register, offset:0x13C
560 */
561 union
562 {
563 __IO uint32_t muxgclr;
564 struct
565 {
566 __IO uint32_t trgovfc : 4; /* [3:0] */
567 __IO uint32_t reserved1 : 28;/* [31:4] */
568 }muxgclr_bit;
569 };
570 } dma_type;
571
572 /**
573 * @brief type define dma channel register all
574 */
575 typedef struct
576 {
577 /**
578 * @brief dma ch ctrl0 register, offset:0x08+20*(x-1) x=1...7
579 */
580 union
581 {
582 __IO uint32_t ctrl;
583 struct
584 {
585 __IO uint32_t chen : 1; /* [0] */
586 __IO uint32_t fdtien : 1; /* [1] */
587 __IO uint32_t hdtien : 1; /* [2] */
588 __IO uint32_t dterrien : 1; /* [3] */
589 __IO uint32_t dtd : 1; /* [4] */
590 __IO uint32_t lm : 1; /* [5] */
591 __IO uint32_t pincm : 1; /* [6] */
592 __IO uint32_t mincm : 1; /* [7] */
593 __IO uint32_t pwidth : 2; /* [9:8] */
594 __IO uint32_t mwidth : 2; /* [11:10] */
595 __IO uint32_t chpl : 2; /* [13:12] */
596 __IO uint32_t m2m : 1; /* [14] */
597 __IO uint32_t reserved1 : 17;/* [31:15] */
598 } ctrl_bit;
599 };
600
601 /**
602 * @brief dma tcnt register, offset:0x0C+20*(x-1) x=1...7
603 */
604 union
605 {
606 __IO uint32_t dtcnt;
607 struct
608 {
609 __IO uint32_t cnt : 16;/* [15:0] */
610 __IO uint32_t reserved1 : 16;/* [31:16] */
611 } dtcnt_bit;
612 };
613
614 /**
615 * @brief dma cpba register, offset:0x10+20*(x-1) x=1...7
616 */
617 union
618 {
619 __IO uint32_t paddr;
620 struct
621 {
622 __IO uint32_t paddr : 32;/* [31:0] */
623 } paddr_bit;
624 };
625
626 /**
627 * @brief dma cmba register, offset:0x14+20*(x-1) x=1...7
628 */
629 union
630 {
631 __IO uint32_t maddr;
632 struct
633 {
634 __IO uint32_t maddr : 32;/* [31:0] */
635 } maddr_bit;
636 };
637 } dma_channel_type;
638
639 /**
640 * @brief type define dmamux muxsctrl register
641 */
642 typedef struct
643 {
644 /**
645 * @brief dma muxsctrl register
646 */
647 union
648 {
649 __IO uint32_t muxctrl;
650 struct
651 {
652 __IO uint32_t reqsel : 7; /* [6:0] */
653 __IO uint32_t reserved1 : 1; /* [7] */
654 __IO uint32_t syncovien : 1; /* [8] */
655 __IO uint32_t evtgen : 1; /* [9] */
656 __IO uint32_t reserved2 : 6; /* [15:10] */
657 __IO uint32_t syncen : 1; /* [16] */
658 __IO uint32_t syncpol : 2; /* [18:17] */
659 __IO uint32_t reqcnt : 5; /* [23:19] */
660 __IO uint32_t syncsel : 5; /* [28:24] */
661 __IO uint32_t reserved3 : 3; /* [31:29] */
662 }muxctrl_bit;
663 };
664 } dmamux_channel_type;
665
666 /**
667 * @brief type define dmamux request generator register all
668 */
669 typedef struct
670 {
671 /**
672 * @brief dmamux request generator register, offset:0x120+4*(x-1) x=1...4
673 */
674 union
675 {
676 __IO uint32_t gctrl;
677 struct
678 {
679 __IO uint32_t sigsel : 5; /* [4:0] */
680 __IO uint32_t reserved1 : 3; /* [7:5] */
681 __IO uint32_t trgovien : 1; /* [8] */
682 __IO uint32_t reserved2 : 7; /* [15:9] */
683 __IO uint32_t gen : 1; /* [16] */
684 __IO uint32_t gpol : 2; /* [18:17] */
685 __IO uint32_t greqcnt : 5; /* [23:19] */
686 __IO uint32_t reserved3 : 8; /* [31:24] */
687 }gctrl_bit;
688 };
689 } dmamux_generator_type;
690
691 /**
692 * @}
693 */
694
695 #define DMA1 ((dma_type *) DMA1_BASE)
696 #define DMA1_CHANNEL1 ((dma_channel_type *) DMA1_CHANNEL1_BASE)
697 #define DMA1_CHANNEL2 ((dma_channel_type *) DMA1_CHANNEL2_BASE)
698 #define DMA1_CHANNEL3 ((dma_channel_type *) DMA1_CHANNEL3_BASE)
699 #define DMA1_CHANNEL4 ((dma_channel_type *) DMA1_CHANNEL4_BASE)
700 #define DMA1_CHANNEL5 ((dma_channel_type *) DMA1_CHANNEL5_BASE)
701 #define DMA1_CHANNEL6 ((dma_channel_type *) DMA1_CHANNEL6_BASE)
702 #define DMA1_CHANNEL7 ((dma_channel_type *) DMA1_CHANNEL7_BASE)
703
704 #define DMA1MUX_CHANNEL1 ((dmamux_channel_type *) DMA1MUX_CHANNEL1_BASE)
705 #define DMA1MUX_CHANNEL2 ((dmamux_channel_type *) DMA1MUX_CHANNEL2_BASE)
706 #define DMA1MUX_CHANNEL3 ((dmamux_channel_type *) DMA1MUX_CHANNEL3_BASE)
707 #define DMA1MUX_CHANNEL4 ((dmamux_channel_type *) DMA1MUX_CHANNEL4_BASE)
708 #define DMA1MUX_CHANNEL5 ((dmamux_channel_type *) DMA1MUX_CHANNEL5_BASE)
709 #define DMA1MUX_CHANNEL6 ((dmamux_channel_type *) DMA1MUX_CHANNEL6_BASE)
710 #define DMA1MUX_CHANNEL7 ((dmamux_channel_type *) DMA1MUX_CHANNEL7_BASE)
711
712 #define DMA1MUX_GENERATOR1 ((dmamux_generator_type *) DMA1MUX_GENERATOR1_BASE)
713 #define DMA1MUX_GENERATOR2 ((dmamux_generator_type *) DMA1MUX_GENERATOR2_BASE)
714 #define DMA1MUX_GENERATOR3 ((dmamux_generator_type *) DMA1MUX_GENERATOR3_BASE)
715 #define DMA1MUX_GENERATOR4 ((dmamux_generator_type *) DMA1MUX_GENERATOR4_BASE)
716
717 #define DMA2 ((dma_type *) DMA2_BASE)
718 #define DMA2_CHANNEL1 ((dma_channel_type *) DMA2_CHANNEL1_BASE)
719 #define DMA2_CHANNEL2 ((dma_channel_type *) DMA2_CHANNEL2_BASE)
720 #define DMA2_CHANNEL3 ((dma_channel_type *) DMA2_CHANNEL3_BASE)
721 #define DMA2_CHANNEL4 ((dma_channel_type *) DMA2_CHANNEL4_BASE)
722 #define DMA2_CHANNEL5 ((dma_channel_type *) DMA2_CHANNEL5_BASE)
723 #define DMA2_CHANNEL6 ((dma_channel_type *) DMA2_CHANNEL6_BASE)
724 #define DMA2_CHANNEL7 ((dma_channel_type *) DMA2_CHANNEL7_BASE)
725
726 #define DMA2MUX_CHANNEL1 ((dmamux_channel_type *) DMA2MUX_CHANNEL1_BASE)
727 #define DMA2MUX_CHANNEL2 ((dmamux_channel_type *) DMA2MUX_CHANNEL2_BASE)
728 #define DMA2MUX_CHANNEL3 ((dmamux_channel_type *) DMA2MUX_CHANNEL3_BASE)
729 #define DMA2MUX_CHANNEL4 ((dmamux_channel_type *) DMA2MUX_CHANNEL4_BASE)
730 #define DMA2MUX_CHANNEL5 ((dmamux_channel_type *) DMA2MUX_CHANNEL5_BASE)
731 #define DMA2MUX_CHANNEL6 ((dmamux_channel_type *) DMA2MUX_CHANNEL6_BASE)
732 #define DMA2MUX_CHANNEL7 ((dmamux_channel_type *) DMA2MUX_CHANNEL7_BASE)
733
734 #define DMA2MUX_GENERATOR1 ((dmamux_generator_type *) DMA2MUX_GENERATOR1_BASE)
735 #define DMA2MUX_GENERATOR2 ((dmamux_generator_type *) DMA2MUX_GENERATOR2_BASE)
736 #define DMA2MUX_GENERATOR3 ((dmamux_generator_type *) DMA2MUX_GENERATOR3_BASE)
737 #define DMA2MUX_GENERATOR4 ((dmamux_generator_type *) DMA2MUX_GENERATOR4_BASE)
738
739 /** @defgroup DMA_exported_functions
740 * @{
741 */
742
743 /* dma controller function */
744 void dma_reset(dma_channel_type *dmax_channely);
745 void dma_data_number_set(dma_channel_type *dmax_channely, uint16_t data_number);
746 uint16_t dma_data_number_get(dma_channel_type *dmax_channely);
747 void dma_interrupt_enable(dma_channel_type *dmax_channely, uint32_t dma_int, confirm_state new_state);
748 void dma_channel_enable(dma_channel_type *dmax_channely, confirm_state new_state);
749 flag_status dma_flag_get(uint32_t dmax_flag);
750 void dma_flag_clear(uint32_t dmax_flag);
751 void dma_default_para_init(dma_init_type *dma_init_struct);
752 void dma_init(dma_channel_type *dmax_channely, dma_init_type *dma_init_struct);
753
754 /* dma requst multiplexer function */
755 void dma_flexible_config(dma_type* dma_x, dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
756 void dmamux_enable(dma_type *dma_x, confirm_state new_state);
757 void dmamux_init(dmamux_channel_type *dmamux_channelx, dmamux_requst_id_sel_type dmamux_req_sel);
758 void dmamux_sync_default_para_init(dmamux_sync_init_type *dmamux_sync_init_struct);
759 void dmamux_sync_config(dmamux_channel_type *dmamux_channelx, dmamux_sync_init_type *dmamux_sync_init_struct);
760 void dmamux_generator_default_para_init(dmamux_gen_init_type *dmamux_gen_init_struct);
761 void dmamux_generator_config(dmamux_generator_type *dmamux_gen_x, dmamux_gen_init_type *dmamux_gen_init_struct);
762 void dmamux_sync_interrupt_enable(dmamux_channel_type *dmamux_channelx, confirm_state new_state);
763 void dmamux_generator_interrupt_enable(dmamux_generator_type *dmamux_gen_x, confirm_state new_state);
764 flag_status dmamux_sync_flag_get(dma_type *dma_x, uint32_t flag);
765 void dmamux_sync_flag_clear(dma_type *dma_x, uint32_t flag);
766 flag_status dmamux_generator_flag_get(dma_type *dma_x, uint32_t flag);
767 void dmamux_generator_flag_clear(dma_type *dma_x, uint32_t flag);
768
769 /**
770 * @}
771 */
772
773 /**
774 * @}
775 */
776
777 /**
778 * @}
779 */
780
781 #ifdef __cplusplus
782 }
783 #endif
784
785 #endif
INAV: Navigation-enabled flight control software