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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_edma.h
blob0a05936d1f751b746cdf6ef61abf038b94e2a1e9
1 /**
2 **************************************************************************
3 * @file at32f435_437_edma.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 edma header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_EDMA_H
29 #define __AT32F435_437_EDMA_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup EDMA
44 * @{
45 */
46
47 /** @defgroup EDMA_interrupts_definition
48 * @brief edma interrupt
49 * @{
50 */
51
52 #define EDMA_DMERR_INT ((uint32_t)0x00000002) /* edma direct mode error intterrupt */
53 #define EDMA_DTERR_INT ((uint32_t)0x00000004) /* edma data transfer error intterrupt */
54 #define EDMA_HDT_INT ((uint32_t)0x00000008) /* edma half data transfer intterrupt */
55 #define EDMA_FDT_INT ((uint32_t)0x00000010) /* edma full data transfer intterrupt */
56 #define EDMA_FERR_INT ((uint32_t)0x00000080) /* edma fifo error interrupt */
57
58 /**
59 * @}
60 */
61
62 /** @defgroup EDMA_flags_definition
63 * @brief edma flag
64 * @{
65 */
66
67 #define EDMA_FERR1_FLAG ((uint32_t)0x10000001) /* edma stream1 fifo error flag */
68 #define EDMA_DMERR1_FLAG ((uint32_t)0x10000004) /* edma stream1 direct mode error flag */
69 #define EDMA_DTERR1_FLAG ((uint32_t)0x10000008) /* edma stream1 data transfer error flag */
70 #define EDMA_HDT1_FLAG ((uint32_t)0x10000010) /* edma stream1 half data transfer flag */
71 #define EDMA_FDT1_FLAG ((uint32_t)0x10000020) /* edma stream1 full data transfer flag */
72 #define EDMA_FERR2_FLAG ((uint32_t)0x10000040) /* edma stream2 fifo error flag */
73 #define EDMA_DMERR2_FLAG ((uint32_t)0x10000100) /* edma stream2 direct mode error flag */
74 #define EDMA_DTERR2_FLAG ((uint32_t)0x10000200) /* edma stream2 data transfer error flag */
75 #define EDMA_HDT2_FLAG ((uint32_t)0x10000400) /* edma stream2 half data transfer flag */
76 #define EDMA_FDT2_FLAG ((uint32_t)0x10000800) /* edma stream2 full data transfer flag */
77 #define EDMA_FERR3_FLAG ((uint32_t)0x10010000) /* edma stream3 fifo error flag */
78 #define EDMA_DMERR3_FLAG ((uint32_t)0x10040000) /* edma stream3 direct mode error flag */
79 #define EDMA_DTERR3_FLAG ((uint32_t)0x10080000) /* edma stream3 data transfer error flag */
80 #define EDMA_HDT3_FLAG ((uint32_t)0x10100000) /* edma stream3 half data transfer flag */
81 #define EDMA_FDT3_FLAG ((uint32_t)0x10200000) /* edma stream3 full data transfer flag */
82 #define EDMA_FERR4_FLAG ((uint32_t)0x10400000) /* edma stream4 fifo error flag */
83 #define EDMA_DMERR4_FLAG ((uint32_t)0x11000000) /* edma stream4 direct mode error flag */
84 #define EDMA_DTERR4_FLAG ((uint32_t)0x12000000) /* edma stream4 data transfer error flag */
85 #define EDMA_HDT4_FLAG ((uint32_t)0x14000000) /* edma stream4 half data transfer flag */
86 #define EDMA_FDT4_FLAG ((uint32_t)0x18000000) /* edma stream4 full data transfer flag */
87 #define EDMA_FERR5_FLAG ((uint32_t)0x20000001) /* edma stream5 fifo error flag */
88 #define EDMA_DMERR5_FLAG ((uint32_t)0x20000004) /* edma stream5 direct mode error flag */
89 #define EDMA_DTERR5_FLAG ((uint32_t)0x20000008) /* edma stream5 data transfer error flag */
90 #define EDMA_HDT5_FLAG ((uint32_t)0x20000010) /* edma stream5 half data transfer flag */
91 #define EDMA_FDT5_FLAG ((uint32_t)0x20000020) /* edma stream5 full data transfer flag */
92 #define EDMA_FERR6_FLAG ((uint32_t)0x20000040) /* edma stream6 fifo error flag */
93 #define EDMA_DMERR6_FLAG ((uint32_t)0x20000100) /* edma stream6 direct mode error flag */
94 #define EDMA_DTERR6_FLAG ((uint32_t)0x20000200) /* edma stream6 data transfer error flag */
95 #define EDMA_HDT6_FLAG ((uint32_t)0x20000400) /* edma stream6 half data transfer flag */
96 #define EDMA_FDT6_FLAG ((uint32_t)0x20000800) /* edma stream6 full data transfer flag */
97 #define EDMA_FERR7_FLAG ((uint32_t)0x20010000) /* edma stream7 fifo error flag */
98 #define EDMA_DMERR7_FLAG ((uint32_t)0x20040000) /* edma stream7 direct mode error flag */
99 #define EDMA_DTERR7_FLAG ((uint32_t)0x20080000) /* edma stream7 data transfer error flag */
100 #define EDMA_HDT7_FLAG ((uint32_t)0x20100000) /* edma stream7 half data transfer flag */
101 #define EDMA_FDT7_FLAG ((uint32_t)0x20200000) /* edma stream7 full data transfer flag */
102 #define EDMA_FERR8_FLAG ((uint32_t)0x20400000) /* edma stream8 fifo error flag */
103 #define EDMA_DMERR8_FLAG ((uint32_t)0x21000000) /* edma stream8 direct mode error flag */
104 #define EDMA_DTERR8_FLAG ((uint32_t)0x22000000) /* edma stream8 data transfer error flag */
105 #define EDMA_HDT8_FLAG ((uint32_t)0x24000000) /* edma stream8 half data transfer flag */
106 #define EDMA_FDT8_FLAG ((uint32_t)0x28000000) /* edma stream8 full data transfer flag */
107
108 /**
109 * @brief masks define
110 */
111 #define EDMA_STREAM1_INT_MASK (uint32_t)(0x0000003D) /*!< edma stream1 interrupt mask */
112 #define EDMA_STREAM2_INT_MASK (uint32_t)(EDMA_STREAM1_INT_MASK << 6) /*!< edma stream2 interrupt mask */
113 #define EDMA_STREAM3_INT_MASK (uint32_t)(EDMA_STREAM1_INT_MASK << 16) /*!< edma stream3 interrupt mask */
114 #define EDMA_STREAM4_INT_MASK (uint32_t)(EDMA_STREAM1_INT_MASK << 22) /*!< edma stream4 interrupt mask */
115 #define EDMA_STREAM5_INT_MASK (uint32_t)(EDMA_STREAM1_INT_MASK) /*!< edma stream5 interrupt mask */
116 #define EDMA_STREAM6_INT_MASK (uint32_t)(EDMA_STREAM2_INT_MASK) /*!< edma stream6 interrupt mask */
117 #define EDMA_STREAM7_INT_MASK (uint32_t)(EDMA_STREAM3_INT_MASK) /*!< edma stream7 interrupt mask */
118 #define EDMA_STREAM8_INT_MASK (uint32_t)(EDMA_STREAM4_INT_MASK) /*!< edma stream8 interrupt mask */
119
120 /**
121 * @brief edmamux flag
122 */
123 #define EDMAMUX_SYNC_OV1_FLAG ((uint32_t)0x00000001) /*!< edmamux stream1 synchronization overrun event flag */
124 #define EDMAMUX_SYNC_OV2_FLAG ((uint32_t)0x00000002) /*!< edmamux stream2 synchronization overrun event flag */
125 #define EDMAMUX_SYNC_OV3_FLAG ((uint32_t)0x00000004) /*!< edmamux stream3 synchronization overrun event flag */
126 #define EDMAMUX_SYNC_OV4_FLAG ((uint32_t)0x00000008) /*!< edmamux stream4 synchronization overrun event flag */
127 #define EDMAMUX_SYNC_OV5_FLAG ((uint32_t)0x00000010) /*!< edmamux stream5 synchronization overrun event flag */
128 #define EDMAMUX_SYNC_OV6_FLAG ((uint32_t)0x00000020) /*!< edmamux stream6 synchronization overrun event flag */
129 #define EDMAMUX_SYNC_OV7_FLAG ((uint32_t)0x00000040) /*!< edmamux stream7 synchronization overrun event flag */
130 #define EDMAMUX_SYNC_OV8_FLAG ((uint32_t)0x00000080) /*!< edmamux stream8 synchronization overrun event flag */
131
132 #define EDMAMUX_GEN_TRIG_OV1_FLAG ((uint32_t)0x00000001) /*!< edmamux generator channel1 overrun event flag */
133 #define EDMAMUX_GEN_TRIG_OV2_FLAG ((uint32_t)0x00000002) /*!< edmamux generator channel2 overrun event flag */
134 #define EDMAMUX_GEN_TRIG_OV3_FLAG ((uint32_t)0x00000004) /*!< edmamux generator channel3 overrun event flag */
135 #define EDMAMUX_GEN_TRIG_OV4_FLAG ((uint32_t)0x00000008) /*!< edmamux generator channel4 overrun event flag */
136
137 /**
138 * @}
139 */
140
141 /** @defgroup EDMA_exported_types
142 * @{
143 */
144
145 /**
146 * @brief edma memory targets define
147 */
148 typedef enum
149 {
150 EDMA_MEMORY_0 = 0x00, /*!< current target is memory 0 */
151 EDMA_MEMORY_1 = 0x01 /*!< current target is memory 1 */
152 } edma_memory_type;
153
154 /**
155 * @brief edma direction type
156 */
157 typedef enum
158 {
159 EDMA_DIR_PERIPHERAL_TO_MEMORY = 0x00, /*!< data transfer direction: peripheral to memory */
160 EDMA_DIR_MEMORY_TO_PERIPHERAL = 0x01, /*!< data transfer direction: memory to peripheral */
161 EDMA_DIR_MEMORY_TO_MEMORY = 0x02 /*!< data transfer direction: memory to memory */
162 } edma_dir_type;
163
164 /**
165 * @brief edma peripheral data size type
166 */
167 typedef enum
168 {
169 EDMA_PERIPHERAL_DATA_WIDTH_BYTE = 0x00, /*!< peripheral data bus width is 8bit */
170 EDMA_PERIPHERAL_DATA_WIDTH_HALFWORD = 0x01, /*!< peripheral data bus width is 16bit */
171 EDMA_PERIPHERAL_DATA_WIDTH_WORD = 0x02 /*!< peripheral data bus width is 32bit */
172 } edma_peripheral_data_size_type;
173
174 /**
175 * @brief edma memory data size type
176 */
177 typedef enum
178 {
179 EDMA_MEMORY_DATA_WIDTH_BYTE = 0x00, /*!< memory data bus width is 8bit */
180 EDMA_MEMORY_DATA_WIDTH_HALFWORD = 0x01, /*!< memory data bus width is 16bit */
181 EDMA_MEMORY_DATA_WIDTH_WORD = 0x02 /*!< memory data bus width is 32bit */
182 } edma_memory_data_size_type;
183
184 /**
185 * @brief edma priority level type
186 */
187 typedef enum
188 {
189 EDMA_PRIORITY_LOW = 0x00, /*!< stream priority: low */
190 EDMA_PRIORITY_MEDIUM = 0x01, /*!< stream priority: medium */
191 EDMA_PRIORITY_HIGH = 0x02, /*!< stream priority: high */
192 EDMA_PRIORITY_VERY_HIGH = 0x03 /*!< stream priority: very high */
193 } edma_priority_level_type;
194
195 /**
196 * @brief edma fifo threshold level type
197 */
198 typedef enum
199 {
200 EDMA_FIFO_THRESHOLD_1QUARTER = 0x00, /*!< fifo threshold level: 1quarter full */
201 EDMA_FIFO_THRESHOLD_HALF = 0x01, /*!< fifo threshold level: half full */
202 EDMA_FIFO_THRESHOLD_3QUARTER = 0x02, /*!< fifo threshold level: 13quarter full */
203 EDMA_FIFO_THRESHOLD_FULL = 0x03 /*!< fifo threshold level: full */
204 } edma_fifo_threshold_type;
205
206 /**
207 * @brief edma fifo stutas level type
208 */
209 typedef enum
210 {
211 EDMA_FIFO_STATUS_LESS_1QUARTER = 0x00, /*!< fifo stutas level: less 1quarter full */
212 EDMA_FIFO_STATUS_1QUARTER = 0x01, /*!< fifo stutas level: 1quarter full */
213 EDMA_FIFO_STATUS_HALF = 0x02, /*!< fifo stutas level: half full */
214 EDMA_FIFO_STATUS_3QUARTER = 0x03, /*!< fifo stutas level: 3quarter full */
215 EDMA_FIFO_STATUS_EMPTY = 0x04, /*!< fifo stutas level: empty */
216 EDMA_FIFO_STATUS_FULL = 0x05 /*!< fifo stutas level: full */
217 } edma_fifo_stutas_type;
218
219 /**
220 * @brief edma memory continuous mode type
221 */
222 typedef enum
223 {
224 EDMA_MEMORY_SINGLE = 0x00, /*!< memory single transfer */
225 EDMA_MEMORY_BURST_4 = 0x01, /*!< memory burst transfer 4 beats */
226 EDMA_MEMORY_BURST_8 = 0x02, /*!< memory burst transfer 8 beats */
227 EDMA_MEMORY_BURST_16 = 0x03 /*!< memory burst transfer 16 beats */
228 } edma_memory_burst_type;
229
230 /**
231 * @brief edma peripheral continuous mode type
232 */
233 typedef enum
234 {
235 EDMA_PERIPHERAL_SINGLE = 0x00, /*!< peripheral single transfer */
236 EDMA_PERIPHERAL_BURST_4 = 0x01, /*!< peripheral burst transfer 4 beats */
237 EDMA_PERIPHERAL_BURST_8 = 0x02, /*!< peripheral burst transfer 8 beats */
238 EDMA_PERIPHERAL_BURST_16 = 0x03 /*!< peripheral burst transfer 16 beats */
239 } edma_peripheral_burst_type;
240
241 /**
242 * @brief edma peripheral increment offset size type
243 */
244 typedef enum
245 {
246 EDMA_PERIPHERAL_INC_PSIZE = 0x00, /*!< peripheral offset is related to psize*/
247 EDMA_PERIPHERAL_INC_4_BYTE = 0x01 /*!< peripheral offset is 4 byte*/
248 } edma_peripheral_inc_offset_type;
249
250 /**
251 * @brief edmamux request id select type
252 */
253 typedef enum
254 {
255 EDMAMUX_DMAREQ_ID_REQ_G1 = 0x01, /*!< edmamux channel request inputs resources: generator channel1 */
256 EDMAMUX_DMAREQ_ID_REQ_G2 = 0x02, /*!< edmamux channel request inputs resources: generator channel2 */
257 EDMAMUX_DMAREQ_ID_REQ_G3 = 0x03, /*!< edmamux channel request inputs resources: generator channel3 */
258 EDMAMUX_DMAREQ_ID_REQ_G4 = 0x04, /*!< edmamux channel request inputs resources: generator channel4 */
259 EDMAMUX_DMAREQ_ID_ADC1 = 0x05, /*!< edmamux channel request inputs resources: adc1 */
260 EDMAMUX_DMAREQ_ID_ADC2 = 0x24, /*!< edmamux channel request inputs resources: adc2 */
261 EDMAMUX_DMAREQ_ID_ADC3 = 0x25, /*!< edmamux channel request inputs resources: adc3 */
262 EDMAMUX_DMAREQ_ID_DAC1 = 0x06, /*!< edmamux channel request inputs resources: dac1 */
263 EDMAMUX_DMAREQ_ID_DAC2 = 0x29, /*!< edmamux channel request inputs resources: dac2 */
264 EDMAMUX_DMAREQ_ID_TMR6_OVERFLOW = 0x08, /*!< edmamux channel request inputs resources: timer6 overflow */
265 EDMAMUX_DMAREQ_ID_TMR7_OVERFLOW = 0x09, /*!< edmamux channel request inputs resources: timer7 overflow */
266 EDMAMUX_DMAREQ_ID_SPI1_RX = 0x0A, /*!< edmamux channel request inputs resources: spi1 rx */
267 EDMAMUX_DMAREQ_ID_SPI1_TX = 0x0B, /*!< edmamux channel request inputs resources: spi1 tx */
268 EDMAMUX_DMAREQ_ID_SPI2_RX = 0x0C, /*!< edmamux channel request inputs resources: spi2 rx */
269 EDMAMUX_DMAREQ_ID_SPI2_TX = 0x0D, /*!< edmamux channel request inputs resources: spi2 tx */
270 EDMAMUX_DMAREQ_ID_SPI3_RX = 0x0E, /*!< edmamux channel request inputs resources: spi3 rx */
271 EDMAMUX_DMAREQ_ID_SPI3_TX = 0x0F, /*!< edmamux channel request inputs resources: spi3 tx */
272 EDMAMUX_DMAREQ_ID_SPI4_RX = 0x6A, /*!< edmamux channel request inputs resources: spi4 rx */
273 EDMAMUX_DMAREQ_ID_SPI4_TX = 0x6B, /*!< edmamux channel request inputs resources: spi4 tx */
274 EDMAMUX_DMAREQ_ID_I2S2_EXT_RX = 0x6E, /*!< edmamux channel request inputs resources: i2s2_ext_rx */
275 EDMAMUX_DMAREQ_ID_I2S2_EXT_TX = 0x6F, /*!< edmamux channel request inputs resources: i2s2_ext_tx */
276 EDMAMUX_DMAREQ_ID_I2S3_EXT_RX = 0x70, /*!< edmamux channel request inputs resources: i2s3_ext_rx */
277 EDMAMUX_DMAREQ_ID_I2S3_EXT_TX = 0x71, /*!< edmamux channel request inputs resources: i2s3_ext_tx */
278 EDMAMUX_DMAREQ_ID_I2C1_RX = 0x10, /*!< edmamux channel request inputs resources: i2c1_rx */
279 EDMAMUX_DMAREQ_ID_I2C1_TX = 0x11, /*!< edmamux channel request inputs resources: i2c1_tx */
280 EDMAMUX_DMAREQ_ID_I2C2_RX = 0x12, /*!< edmamux channel request inputs resources: i2c2_rx */
281 EDMAMUX_DMAREQ_ID_I2C2_TX = 0x13, /*!< edmamux channel request inputs resources: i2c2_tx */
282 EDMAMUX_DMAREQ_ID_I2C3_RX = 0x14, /*!< edmamux channel request inputs resources: i2c3_rx */
283 EDMAMUX_DMAREQ_ID_I2C3_TX = 0x15, /*!< edmamux channel request inputs resources: i2c3_tx */
284 EDMAMUX_DMAREQ_ID_USART1_RX = 0x18, /*!< edmamux channel request inputs resources: usart1_rx */
285 EDMAMUX_DMAREQ_ID_USART1_TX = 0x19, /*!< edmamux channel request inputs resources: usart1_tx */
286 EDMAMUX_DMAREQ_ID_USART2_RX = 0x1A, /*!< edmamux channel request inputs resources: usart2_rx */
287 EDMAMUX_DMAREQ_ID_USART2_TX = 0x1B, /*!< edmamux channel request inputs resources: usart2_tx */
288 EDMAMUX_DMAREQ_ID_USART3_RX = 0x1C, /*!< edmamux channel request inputs resources: usart3_rx */
289 EDMAMUX_DMAREQ_ID_USART3_TX = 0x1D, /*!< edmamux channel request inputs resources: usart3_tx */
290 EDMAMUX_DMAREQ_ID_UART4_RX = 0x1E, /*!< edmamux channel request inputs resources: uart4_rx */
291 EDMAMUX_DMAREQ_ID_UART4_TX = 0x1F, /*!< edmamux channel request inputs resources: uart4_tx */
292 EDMAMUX_DMAREQ_ID_UART5_RX = 0x20, /*!< edmamux channel request inputs resources: uart5_rx */
293 EDMAMUX_DMAREQ_ID_UART5_TX = 0x21, /*!< edmamux channel request inputs resources: uart5_tx */
294 EDMAMUX_DMAREQ_ID_USART6_RX = 0x72, /*!< edmamux channel request inputs resources: usart6_rx */
295 EDMAMUX_DMAREQ_ID_USART6_TX = 0x73, /*!< edmamux channel request inputs resources: usart6_tx */
296 EDMAMUX_DMAREQ_ID_UART7_RX = 0x74, /*!< edmamux channel request inputs resources: uart7_rx */
297 EDMAMUX_DMAREQ_ID_UART7_TX = 0x75, /*!< edmamux channel request inputs resources: uart7_tx */
298 EDMAMUX_DMAREQ_ID_UART8_RX = 0x76, /*!< edmamux channel request inputs resources: uart8_rx */
299 EDMAMUX_DMAREQ_ID_UART8_TX = 0x77, /*!< edmamux channel request inputs resources: uart8_tx */
300 EDMAMUX_DMAREQ_ID_SDIO1 = 0x27, /*!< edmamux channel request inputs resources: sdio1 */
301 EDMAMUX_DMAREQ_ID_SDIO2 = 0x67, /*!< edmamux channel request inputs resources: sdio2 */
302 EDMAMUX_DMAREQ_ID_QSPI1 = 0x28, /*!< edmamux channel request inputs resources: qspi1 */
303 EDMAMUX_DMAREQ_ID_QSPI2 = 0x68, /*!< edmamux channel request inputs resources: qspi2 */
304 EDMAMUX_DMAREQ_ID_TMR1_CH1 = 0x2A, /*!< edmamux channel request inputs resources: timer1 ch1 */
305 EDMAMUX_DMAREQ_ID_TMR1_CH2 = 0x2B, /*!< edmamux channel request inputs resources: timer1 ch2 */
306 EDMAMUX_DMAREQ_ID_TMR1_CH3 = 0x2C, /*!< edmamux channel request inputs resources: timer1 ch3 */
307 EDMAMUX_DMAREQ_ID_TMR1_CH4 = 0x2D, /*!< edmamux channel request inputs resources: timer1 ch4 */
308 EDMAMUX_DMAREQ_ID_TMR1_OVERFLOW = 0x2E, /*!< edmamux channel request inputs resources: timer1 overflow */
309 EDMAMUX_DMAREQ_ID_TMR1_TRIG = 0x2F, /*!< edmamux channel request inputs resources: timer1 trigger */
310 EDMAMUX_DMAREQ_ID_TMR1_HALL = 0x30, /*!< edmamux channel request inputs resources: timer1 hall */
311 EDMAMUX_DMAREQ_ID_TMR8_CH1 = 0x31, /*!< edmamux channel request inputs resources: timer8 ch1 */
312 EDMAMUX_DMAREQ_ID_TMR8_CH2 = 0x32, /*!< edmamux channel request inputs resources: timer8 ch2 */
313 EDMAMUX_DMAREQ_ID_TMR8_CH3 = 0x33, /*!< edmamux channel request inputs resources: timer8 ch3 */
314 EDMAMUX_DMAREQ_ID_TMR8_CH4 = 0x34, /*!< edmamux channel request inputs resources: timer8 ch4 */
315 EDMAMUX_DMAREQ_ID_TMR8_OVERFLOW = 0x35, /*!< edmamux channel request inputs resources: timer8 overflow */
316 EDMAMUX_DMAREQ_ID_TMR8_TRIG = 0x36, /*!< edmamux channel request inputs resources: timer8 trigger */
317 EDMAMUX_DMAREQ_ID_TMR8_HALL = 0x37, /*!< edmamux channel request inputs resources: timer8 hall */
318 EDMAMUX_DMAREQ_ID_TMR2_CH1 = 0x38, /*!< edmamux channel request inputs resources: timer2 ch1 */
319 EDMAMUX_DMAREQ_ID_TMR2_CH2 = 0x39, /*!< edmamux channel request inputs resources: timer2 ch2 */
320 EDMAMUX_DMAREQ_ID_TMR2_CH3 = 0x3A, /*!< edmamux channel request inputs resources: timer2 ch3 */
321 EDMAMUX_DMAREQ_ID_TMR2_CH4 = 0x3B, /*!< edmamux channel request inputs resources: timer2 ch4 */
322 EDMAMUX_DMAREQ_ID_TMR2_OVERFLOW = 0x3C, /*!< edmamux channel request inputs resources: timer2 overflow */
323 EDMAMUX_DMAREQ_ID_TMR2_TRIG = 0x7E, /*!< edmamux channel request inputs resources: timer2 trigger */
324 EDMAMUX_DMAREQ_ID_TMR3_CH1 = 0x3D, /*!< edmamux channel request inputs resources: timer3 ch1 */
325 EDMAMUX_DMAREQ_ID_TMR3_CH2 = 0x3E, /*!< edmamux channel request inputs resources: timer3 ch2 */
326 EDMAMUX_DMAREQ_ID_TMR3_CH3 = 0x3F, /*!< edmamux channel request inputs resources: timer3 ch3 */
327 EDMAMUX_DMAREQ_ID_TMR3_CH4 = 0x40, /*!< edmamux channel request inputs resources: timer3 ch4 */
328 EDMAMUX_DMAREQ_ID_TMR3_OVERFLOW = 0x41, /*!< edmamux channel request inputs resources: timer3 overflow */
329 EDMAMUX_DMAREQ_ID_TMR3_TRIG = 0x42, /*!< edmamux channel request inputs resources: timer3 trigger */
330 EDMAMUX_DMAREQ_ID_TMR4_CH1 = 0x43, /*!< edmamux channel request inputs resources: timer4 ch1 */
331 EDMAMUX_DMAREQ_ID_TMR4_CH2 = 0x44, /*!< edmamux channel request inputs resources: timer4 ch2 */
332 EDMAMUX_DMAREQ_ID_TMR4_CH3 = 0x45, /*!< edmamux channel request inputs resources: timer4 ch3 */
333 EDMAMUX_DMAREQ_ID_TMR4_CH4 = 0x46, /*!< edmamux channel request inputs resources: timer4 ch4 */
334 EDMAMUX_DMAREQ_ID_TMR4_OVERFLOW = 0x47, /*!< edmamux channel request inputs resources: timer4 overflow */
335 EDMAMUX_DMAREQ_ID_TMR4_TRIG = 0x7F, /*!< edmamux channel request inputs resources: timer4 trigger */
336 EDMAMUX_DMAREQ_ID_TMR5_CH1 = 0x48, /*!< edmamux channel request inputs resources: timer5 ch1 */
337 EDMAMUX_DMAREQ_ID_TMR5_CH2 = 0x49, /*!< edmamux channel request inputs resources: timer5 ch2 */
338 EDMAMUX_DMAREQ_ID_TMR5_CH3 = 0x4A, /*!< edmamux channel request inputs resources: timer5 ch3 */
339 EDMAMUX_DMAREQ_ID_TMR5_CH4 = 0x4B, /*!< edmamux channel request inputs resources: timer5 ch4 */
340 EDMAMUX_DMAREQ_ID_TMR5_OVERFLOW = 0x4C, /*!< edmamux channel request inputs resources: timer5 overflow */
341 EDMAMUX_DMAREQ_ID_TMR5_TRIG = 0x4D, /*!< edmamux channel request inputs resources: timer5 trigger */
342 EDMAMUX_DMAREQ_ID_TMR20_CH1 = 0x56, /*!< edmamux channel request inputs resources: timer20 ch1 */
343 EDMAMUX_DMAREQ_ID_TMR20_CH2 = 0x57, /*!< edmamux channel request inputs resources: timer20 ch2 */
344 EDMAMUX_DMAREQ_ID_TMR20_CH3 = 0x58, /*!< edmamux channel request inputs resources: timer20 ch3 */
345 EDMAMUX_DMAREQ_ID_TMR20_CH4 = 0x59, /*!< edmamux channel request inputs resources: timer20 ch4 */
346 EDMAMUX_DMAREQ_ID_TMR20_OVERFLOW = 0x5A, /*!< edmamux channel request inputs resources: timer20 overflow */
347 EDMAMUX_DMAREQ_ID_TMR20_TRIG = 0x5D, /*!< edmamux channel request inputs resources: timer20 trigger */
348 EDMAMUX_DMAREQ_ID_TMR20_HALL = 0x5E, /*!< edmamux channel request inputs resources: timer20 hall */
349 EDMAMUX_DMAREQ_ID_DVP = 0x69 /*!< edmamux channel request inputs resources: dvp */
350 } edmamux_requst_id_sel_type;
351
352 /**
353 * @brief dmamux sync id select type
354 */
355 typedef enum
356 {
357 EDMAMUX_SYNC_ID_EXINT0 = 0x00, /*!< edmamux channel synchronization inputs resources: exint line0 */
358 EDMAMUX_SYNC_ID_EXINT1 = 0x01, /*!< edmamux channel synchronization inputs resources: exint line1 */
359 EDMAMUX_SYNC_ID_EXINT2 = 0x02, /*!< edmamux channel synchronization inputs resources: exint line2 */
360 EDMAMUX_SYNC_ID_EXINT3 = 0x03, /*!< edmamux channel synchronization inputs resources: exint line3 */
361 EDMAMUX_SYNC_ID_EXINT4 = 0x04, /*!< edmamux channel synchronization inputs resources: exint line4 */
362 EDMAMUX_SYNC_ID_EXINT5 = 0x05, /*!< edmamux channel synchronization inputs resources: exint line5 */
363 EDMAMUX_SYNC_ID_EXINT6 = 0x06, /*!< edmamux channel synchronization inputs resources: exint line6 */
364 EDMAMUX_SYNC_ID_EXINT7 = 0x07, /*!< edmamux channel synchronization inputs resources: exint line7 */
365 EDMAMUX_SYNC_ID_EXINT8 = 0x08, /*!< edmamux channel synchronization inputs resources: exint line8 */
366 EDMAMUX_SYNC_ID_EXINT9 = 0x09, /*!< edmamux channel synchronization inputs resources: exint line9 */
367 EDMAMUX_SYNC_ID_EXINT10 = 0x0A, /*!< edmamux channel synchronization inputs resources: exint line10 */
368 EDMAMUX_SYNC_ID_EXINT11 = 0x0B, /*!< edmamux channel synchronization inputs resources: exint line11 */
369 EDMAMUX_SYNC_ID_EXINT12 = 0x0C, /*!< edmamux channel synchronization inputs resources: exint line12 */
370 EDMAMUX_SYNC_ID_EXINT13 = 0x0D, /*!< edmamux channel synchronization inputs resources: exint line13 */
371 EDMAMUX_SYNC_ID_EXINT14 = 0x0E, /*!< edmamux channel synchronization inputs resources: exint line14 */
372 EDMAMUX_SYNC_ID_EXINT15 = 0x0F, /*!< edmamux channel synchronization inputs resources: exint line15 */
373 EDMAMUX_SYNC_ID_DMAMUX_CH1_EVT = 0x10, /*!< edmamux channel synchronization inputs resources: dmamux channel1 event */
374 EDMAMUX_SYNC_ID_DMAMUX_CH2_EVT = 0x11, /*!< edmamux channel synchronization inputs resources: dmamux channel2 event */
375 EDMAMUX_SYNC_ID_DMAMUX_CH3_EVT = 0x12, /*!< edmamux channel synchronization inputs resources: dmamux channel3 event */
376 EDMAMUX_SYNC_ID_DMAMUX_CH4_EVT = 0x13, /*!< edmamux channel synchronization inputs resources: dmamux channel4 event */
377 EDMAMUX_SYNC_ID_DMAMUX_CH5_EVT = 0x14, /*!< edmamux channel synchronization inputs resources: dmamux channel5 event */
378 EDMAMUX_SYNC_ID_DMAMUX_CH6_EVT = 0x15, /*!< edmamux channel synchronization inputs resources: dmamux channel6 event */
379 EDMAMUX_SYNC_ID_DMAMUX_CH7_EVT = 0x16, /*!< edmamux channel synchronization inputs resources: dmamux channel7 event */
380 EDMAMUX_SYNC_ID_DMAMUX_CH8_EVT = 0x17 /*!< edmamux channel synchronization inputs resources: dmamux channel8 event */
381 } edmamux_sync_id_sel_type;
382
383 /**
384 * @brief dmamux sync polarity type
385 */
386 typedef enum
387 {
388 EDMAMUX_SYNC_POLARITY_DISABLE = 0x00, /*!< edmamux channel synchronization inputs resources polarity default value */
389 EDMAMUX_SYNC_POLARITY_RISING = 0x01, /*!< edmamux channel synchronization inputs resources polarity: rising */
390 EDMAMUX_SYNC_POLARITY_FALLING = 0x02, /*!< edmamux channel synchronization inputs resources polarity: falling */
391 EDMAMUX_SYNC_POLARITY_RISING_FALLING = 0x03 /*!< edmamux channel synchronization inputs resources polarity: rising_falling */
392 } edmamux_sync_pol_type;
393
394 /**
395 * @brief dmamux generator id select type
396 */
397 typedef enum
398 {
399 EDMAMUX_GEN_ID_EXINT0 = 0x00, /*!< edmamux generator channel inputs resources: exint line0 */
400 EDMAMUX_GEN_ID_EXINT1 = 0x01, /*!< edmamux generator channel inputs resources: exint line1 */
401 EDMAMUX_GEN_ID_EXINT2 = 0x02, /*!< edmamux generator channel inputs resources: exint line2 */
402 EDMAMUX_GEN_ID_EXINT3 = 0x03, /*!< edmamux generator channel inputs resources: exint line3 */
403 EDMAMUX_GEN_ID_EXINT4 = 0x04, /*!< edmamux generator channel inputs resources: exint line4 */
404 EDMAMUX_GEN_ID_EXINT5 = 0x05, /*!< edmamux generator channel inputs resources: exint line5 */
405 EDMAMUX_GEN_ID_EXINT6 = 0x06, /*!< edmamux generator channel inputs resources: exint line6 */
406 EDMAMUX_GEN_ID_EXINT7 = 0x07, /*!< edmamux generator channel inputs resources: exint line7 */
407 EDMAMUX_GEN_ID_EXINT8 = 0x08, /*!< edmamux generator channel inputs resources: exint line8 */
408 EDMAMUX_GEN_ID_EXINT9 = 0x09, /*!< edmamux generator channel inputs resources: exint line9 */
409 EDMAMUX_GEN_ID_EXINT10 = 0x0A, /*!< edmamux generator channel inputs resources: exint line10 */
410 EDMAMUX_GEN_ID_EXINT11 = 0x0B, /*!< edmamux generator channel inputs resources: exint line11 */
411 EDMAMUX_GEN_ID_EXINT12 = 0x0C, /*!< edmamux generator channel inputs resources: exint line12 */
412 EDMAMUX_GEN_ID_EXINT13 = 0x0D, /*!< edmamux generator channel inputs resources: exint line13 */
413 EDMAMUX_GEN_ID_EXINT14 = 0x0E, /*!< edmamux generator channel inputs resources: exint line14 */
414 EDMAMUX_GEN_ID_EXINT15 = 0x0F, /*!< edmamux generator channel inputs resources: exint line15 */
415 EDMAMUX_GEN_ID_DMAMUX_CH1_EVT = 0x10, /*!< edmamux generator channel inputs resources: dmamux channel1 event */
416 EDMAMUX_GEN_ID_DMAMUX_CH2_EVT = 0x11, /*!< edmamux generator channel inputs resources: dmamux channel2 event */
417 EDMAMUX_GEN_ID_DMAMUX_CH3_EVT = 0x12, /*!< edmamux generator channel inputs resources: dmamux channel3 event */
418 EDMAMUX_GEN_ID_DMAMUX_CH4_EVT = 0x13, /*!< edmamux generator channel inputs resources: dmamux channel4 event */
419 EDMAMUX_GEN_ID_DMAMUX_CH5_EVT = 0x14, /*!< edmamux generator channel inputs resources: dmamux channel5 event */
420 EDMAMUX_GEN_ID_DMAMUX_CH6_EVT = 0x15, /*!< edmamux generator channel inputs resources: dmamux channel6 event */
421 EDMAMUX_GEN_ID_DMAMUX_CH7_EVT = 0x16, /*!< edmamux generator channel inputs resources: dmamux channel7 event */
422 EDMAMUX_GEN_ID_DMAMUX_CH8_EVT = 0x17 /*!< edmamux generator channel inputs resources: dmamux channel8 event */
423 } edmamux_gen_id_sel_type;
424
425 /**
426 * @brief dmamux generator polarity type
427 */
428 typedef enum
429 {
430 EDMAMUX_GEN_POLARITY_DISABLE = 0x00, /*!< edmamux generator channel inputs resources polarity default value */
431 EDMAMUX_GEN_POLARITY_RISING = 0x01, /*!< edmamux generator channel inputs resources polarity: rising */
432 EDMAMUX_GEN_POLARITY_FALLING = 0x02, /*!< edmamux generator channel inputs resources polarity: falling */
433 EDMAMUX_GEN_POLARITY_RISING_FALLING = 0x03 /*!< edmamux generator channel inputs resources polarity: rising_falling */
434 } edmamux_gen_pol_type;
435
436 /**
437 * @brief edma init type
438 */
439 typedef struct
440 {
441 uint32_t peripheral_base_addr; /*!< base addrress for peripheral */
442 uint32_t memory0_base_addr; /*!< base addrress for memory 0 */
443 edma_dir_type direction; /*!< edma transmit direction, peripheral as source or as destnation */
444 uint16_t buffer_size; /*!< counter to transfer (0~0xFFFF)*/
445 confirm_state peripheral_inc_enable; /*!< periphera address increment after one transmit */
446 confirm_state memory_inc_enable; /*!< memory address increment after one transmit */
447 edma_peripheral_data_size_type peripheral_data_width; /*!< peripheral data width for transmit */
448 edma_memory_data_size_type memory_data_width; /*!< memory data width for transmit */
449 confirm_state loop_mode_enable; /*!< when loop mode enable, buffer size will reload if count to 0*/
450 edma_priority_level_type priority; /*!< edma priority can choose from very high, high, dedium or low */
451 confirm_state fifo_mode_enable; /*!< edma fifo mode enable */
452 edma_fifo_threshold_type fifo_threshold; /*!< edma fifo threshold vaule */
453 edma_memory_burst_type memory_burst_mode; /*!< edma memory burst transfer */
454 edma_peripheral_burst_type peripheral_burst_mode; /*!< edma peripheral burst transfer */
455 } edma_init_type;
456
457 /**
458 * @brief edmamux sync init type
459 */
460 typedef struct
461 {
462 edmamux_sync_id_sel_type sync_signal_sel; /*!< edma dmamux synchronization input select */
463 edmamux_sync_pol_type sync_polarity; /*!< edma dmamux synchronization polarity */
464 uint32_t sync_request_number; /*!< edma dmamux number of dma requests before an output event is generated */
465 confirm_state sync_event_enable; /*!< edma dmamux event generation disabled */
466 confirm_state sync_enable; /*!< edma dmamux synchronization enable */
467 } edmamux_sync_init_type;
468
469 /**
470 * @brief edmamux generator init type
471 */
472 typedef struct
473 {
474 edmamux_gen_id_sel_type gen_signal_sel; /*!< edma dmamux generator dma request trigger input select */
475 edmamux_gen_pol_type gen_polarity; /*!< edma dmamux generator trigger polarity */
476 uint32_t gen_request_number; /*!< edma dmamux the number of dma requests to be generated after a trigger event */
477 confirm_state gen_enable; /*!< edma dmamux generator enable */
478 } edmamux_gen_init_type;
479
480 /**
481 * @brief type define edma register all
482 */
483 typedef struct
484 {
485 /**
486 * @brief edma sts1 register, offset:0x00
487 */
488 union
489 {
490 __IO uint32_t sts1;
491 struct
492 {
493 __IO uint32_t ferrf1 : 1; /* [0] */
494 __IO uint32_t reserved1 : 1; /* [1] */
495 __IO uint32_t dmerrf1 : 1; /* [2] */
496 __IO uint32_t dterrf1 : 1; /* [3] */
497 __IO uint32_t hdtf1 : 1; /* [4] */
498 __IO uint32_t fdtf1 : 1; /* [5] */
499 __IO uint32_t ferrf2 : 1; /* [6] */
500 __IO uint32_t reserved2 : 1; /* [7] */
501 __IO uint32_t dmerrf2 : 1; /* [8] */
502 __IO uint32_t dterrf2 : 1; /* [9] */
503 __IO uint32_t hdtf2 : 1; /* [10] */
504 __IO uint32_t fdtf2 : 1; /* [11] */
505 __IO uint32_t reserved3 : 4; /* [15:13] */
506 __IO uint32_t ferrf3 : 1; /* [16] */
507 __IO uint32_t reserved4 : 1; /* [17] */
508 __IO uint32_t dmerrf3 : 1; /* [18] */
509 __IO uint32_t dterrf3 : 1; /* [19] */
510 __IO uint32_t hdtf3 : 1; /* [20] */
511 __IO uint32_t fdtf3 : 1; /* [21] */
512 __IO uint32_t ferrf4 : 1; /* [22] */
513 __IO uint32_t reserved5 : 1; /* [23] */
514 __IO uint32_t dmerrf4 : 1; /* [24] */
515 __IO uint32_t dterrf4 : 1; /* [25] */
516 __IO uint32_t hdtf4 : 1; /* [26] */
517 __IO uint32_t fdtf4 : 1; /* [27] */
518 __IO uint32_t reserved6 : 4; /* [31:28] */
519 } sts1_bit;
520 };
521 /**
522 * @brief edma sts2 register, offset:0x04
523 */
524 union
525 {
526 __IO uint32_t sts2;
527 struct
528 {
529 __IO uint32_t ferrf5 : 1; /* [0] */
530 __IO uint32_t reserved1 : 1; /* [1] */
531 __IO uint32_t dmerrf5 : 1; /* [2] */
532 __IO uint32_t dterrf5 : 1; /* [3] */
533 __IO uint32_t hdtf5 : 1; /* [4] */
534 __IO uint32_t fdtf5 : 1; /* [5] */
535 __IO uint32_t ferrf6 : 1; /* [6] */
536 __IO uint32_t reserved2 : 1; /* [7] */
537 __IO uint32_t dmerrf6 : 1; /* [8] */
538 __IO uint32_t dterrf6 : 1; /* [9] */
539 __IO uint32_t hdtf6 : 1; /* [10] */
540 __IO uint32_t fdtf6 : 1; /* [11] */
541 __IO uint32_t reserved3 : 4; /* [15:13] */
542 __IO uint32_t ferrf7 : 1; /* [16] */
543 __IO uint32_t reserved4 : 1; /* [17] */
544 __IO uint32_t dmerrf7 : 1; /* [18] */
545 __IO uint32_t dterrf7 : 1; /* [19] */
546 __IO uint32_t hdtf7 : 1; /* [20] */
547 __IO uint32_t fdtf7 : 1; /* [21] */
548 __IO uint32_t ferrf8 : 1; /* [22] */
549 __IO uint32_t reserved5 : 1; /* [23] */
550 __IO uint32_t dmerrf8 : 1; /* [24] */
551 __IO uint32_t dterrf8 : 1; /* [25] */
552 __IO uint32_t hdtf8 : 1; /* [26] */
553 __IO uint32_t fdtf8 : 1; /* [27] */
554 __IO uint32_t reserved6 : 4; /* [31:28] */
555 } sts2_bit;
556 };
557 /**
558 * @brief edma clr1 register, offset:0x08
559 */
560 union
561 {
562 __IO uint32_t clr1;
563 struct
564 {
565 __IO uint32_t ferrfc1 : 1; /* [0] */
566 __IO uint32_t reserved1 : 1; /* [1] */
567 __IO uint32_t dmerrfc1 : 1; /* [2] */
568 __IO uint32_t dterrfc1 : 1; /* [3] */
569 __IO uint32_t hdtfc1 : 1; /* [4] */
570 __IO uint32_t fdtfc1 : 1; /* [5] */
571 __IO uint32_t ferrfc2 : 1; /* [6] */
572 __IO uint32_t reserved2 : 1; /* [7] */
573 __IO uint32_t dmerrfc2 : 1; /* [8] */
574 __IO uint32_t dterrfc2 : 1; /* [9] */
575 __IO uint32_t hdtfc2 : 1; /* [10] */
576 __IO uint32_t fdtfc2 : 1; /* [11] */
577 __IO uint32_t reserved3 : 4; /* [15:13] */
578 __IO uint32_t ferrfc3 : 1; /* [16] */
579 __IO uint32_t reserved4 : 1; /* [17] */
580 __IO uint32_t dmerrfc3 : 1; /* [18] */
581 __IO uint32_t dterrfc3 : 1; /* [19] */
582 __IO uint32_t hdtfc3 : 1; /* [20] */
583 __IO uint32_t fdtfc3 : 1; /* [21] */
584 __IO uint32_t ferrfc4 : 1; /* [22] */
585 __IO uint32_t reserved5 : 1; /* [23] */
586 __IO uint32_t dmerrfc4 : 1; /* [24] */
587 __IO uint32_t dterrfc4 : 1; /* [25] */
588 __IO uint32_t hdtfc4 : 1; /* [26] */
589 __IO uint32_t fdtfc4 : 1; /* [27] */
590 __IO uint32_t reserved6 : 4; /* [31:28] */
591 } clr1_bit;
592 };
593 /**
594 * @brief edma clr2 register, offset:0x0C
595 */
596 union
597 {
598 __IO uint32_t clr2;
599 struct
600 {
601 __IO uint32_t ferrfc5 : 1; /* [0] */
602 __IO uint32_t reserved1 : 1; /* [1] */
603 __IO uint32_t dmerrfc5 : 1; /* [2] */
604 __IO uint32_t dterrfc5 : 1; /* [3] */
605 __IO uint32_t hdtfc5 : 1; /* [4] */
606 __IO uint32_t fdtfc5 : 1; /* [5] */
607 __IO uint32_t ferrfc6 : 1; /* [6] */
608 __IO uint32_t reserved2 : 1; /* [7] */
609 __IO uint32_t dmerrfc6 : 1; /* [8] */
610 __IO uint32_t dterrfc6 : 1; /* [9] */
611 __IO uint32_t hdtfc6 : 1; /* [10] */
612 __IO uint32_t fdtfc6 : 1; /* [11] */
613 __IO uint32_t reserved3 : 4; /* [15:13] */
614 __IO uint32_t ferrfc7 : 1; /* [16] */
615 __IO uint32_t reserved4 : 1; /* [17] */
616 __IO uint32_t dmerrfc7 : 1; /* [18] */
617 __IO uint32_t dterrfc7 : 1; /* [19] */
618 __IO uint32_t hdtfc7 : 1; /* [20] */
619 __IO uint32_t fdtfc7 : 1; /* [21] */
620 __IO uint32_t ferrfc8 : 1; /* [22] */
621 __IO uint32_t reserved5 : 1; /* [23] */
622 __IO uint32_t dmerrfc8 : 1; /* [24] */
623 __IO uint32_t dterrfc8 : 1; /* [25] */
624 __IO uint32_t hdtfc8 : 1; /* [26] */
625 __IO uint32_t fdtfc8 : 1; /* [27] */
626 __IO uint32_t reserved6 : 4; /* [31:28] */
627 } clr2_bit;
628 };
629
630 /**
631 * @brief reserved, offset:0x10~0xCC
632 */
633 __IO uint32_t reserved1[48];
634
635 /**
636 * @brief edma link list ctrl register, offset:0xD0
637 */
638 union
639 {
640 __IO uint32_t llctrl;
641 struct
642 {
643 __IO uint32_t s1llen : 1; /* [0] */
644 __IO uint32_t s2llen : 1; /* [1] */
645 __IO uint32_t s3llen : 1; /* [2] */
646 __IO uint32_t s4llen : 1; /* [3] */
647 __IO uint32_t s5llen : 1; /* [4] */
648 __IO uint32_t s6llen : 1; /* [5] */
649 __IO uint32_t s7llen : 1; /* [6] */
650 __IO uint32_t s8llen : 1; /* [7] */
651 __IO uint32_t reserved1 : 24;/* [31:8] */
652 } llctrl_bit;
653 };
654
655 /**
656 * @brief reserved, offset:0xD4~0xF0
657 */
658 __IO uint32_t reserved2[8];
659
660 /**
661 * @brief edma 2d ctrl register, offset:0xF4
662 */
663 union
664 {
665 __IO uint32_t s2dctrl;
666 struct
667 {
668 __IO uint32_t s12den : 1; /* [0] */
669 __IO uint32_t s22den : 1; /* [1] */
670 __IO uint32_t s32den : 1; /* [2] */
671 __IO uint32_t s42den : 1; /* [3] */
672 __IO uint32_t s52den : 1; /* [4] */
673 __IO uint32_t s62den : 1; /* [5] */
674 __IO uint32_t s72den : 1; /* [6] */
675 __IO uint32_t s82den : 1; /* [7] */
676 __IO uint32_t reserved1 : 24;/* [31:8] */
677 } s2dctrl_bit;
678 };
679
680 /**
681 * @brief reserved, offset:0xF8~0x138
682 */
683 __IO uint32_t reserved3[17];
684
685 /**
686 * @brief edmamux sel register, offset:0x13C
687 */
688 union
689 {
690 __IO uint32_t muxsel;
691 struct
692 {
693 __IO uint32_t tblsel : 1; /* [0] */
694 __IO uint32_t reserved1 : 31;/* [31:1] */
695 }muxsel_bit;
696 };
697
698 /**
699 * @brief reserved, offset:0x140~0x16C
700 */
701 __IO uint32_t reserved4[12];
702
703 /**
704 * @brief edmamux syncsts register, offset:0x170
705 */
706 union
707 {
708 __IO uint32_t muxsyncsts;
709 struct
710 {
711 __IO uint32_t syncovf : 8; /* [7:0] */
712 __IO uint32_t reserved1 : 24;/* [31:8] */
713 }muxsyncsts_bit;
714 };
715
716 /**
717 * @brief edmamux syncclr register, offset:0x174
718 */
719 union
720 {
721 __IO uint32_t muxsyncclr;
722 struct
723 {
724 __IO uint32_t syncovfc : 8; /* [7:0] */
725 __IO uint32_t reserved1 : 24;/* [31:8] */
726 }muxsyncclr_bit;
727 };
728
729 /**
730 * @brief edmamux request generator status register, offset:0x178
731 */
732 union
733 {
734 __IO uint32_t muxgsts;
735 struct
736 {
737 __IO uint32_t trgovf : 4; /* [3:0] */
738 __IO uint32_t reserved1 : 28;/* [31:4] */
739 }muxgsts_bit;
740 };
741
742 /**
743 * @brief edmamux request generator status clear register, offset:0x17C
744 */
745 union
746 {
747 __IO uint32_t muxgclr;
748 struct
749 {
750 __IO uint32_t trgovfc : 4; /* [3:0] */
751 __IO uint32_t reserved1 : 28;/* [31:4] */
752 }muxgclr_bit;
753 };
754
755 } edma_type;
756
757 /**
758 * @brief type define edma stream register all
759 */
760 typedef struct
761 {
762 /**
763 * @brief edma sxctrl register, offset:0x10+0x18*n n=1...8
764 */
765 union
766 {
767 __IO uint32_t ctrl;
768 struct
769 {
770 __IO uint32_t sen : 1; /* [0] */
771 __IO uint32_t dmerrien : 1; /* [1] */
772 __IO uint32_t dterrien : 1; /* [2] */
773 __IO uint32_t hdtien : 1; /* [3] */
774 __IO uint32_t fdtien : 1; /* [4] */
775 __IO uint32_t pfctrl : 1; /* [5] */
776 __IO uint32_t dtd : 2; /* [7:6] */
777 __IO uint32_t lm : 1; /* [8] */
778 __IO uint32_t pincm : 1; /* [9] */
779 __IO uint32_t mincm : 1; /* [10] */
780 __IO uint32_t pwidth : 2; /* [12:11] */
781 __IO uint32_t mwidth : 2; /* [14:13] */
782 __IO uint32_t pincos : 1; /* [15] */
783 __IO uint32_t spl : 2; /* [17:16] */
784 __IO uint32_t dmm : 1; /* [18] */
785 __IO uint32_t cm : 1; /* [19] */
786 __IO uint32_t reserved1 : 1; /* [20] */
787 __IO uint32_t pct : 2; /* [22:21] */
788 __IO uint32_t mct : 2; /* [24:23] */
789 __IO uint32_t reserved2 : 3; /* [27:25] */
790 __IO uint32_t reserved3 : 4; /* [31:28] */
791 } ctrl_bit;
792 };
793 /**
794 * @brief edma dtcnt register, offset:0x14+0x18*n n=1...8
795 */
796 union
797 {
798 __IO uint32_t dtcnt;
799 struct
800 {
801 __IO uint32_t cnt : 16;/* [15:0] */
802 __IO uint32_t reserved1 : 16; /*[31:16] */
803 } dtcnt_bit;
804 };
805 /**
806 * @brief edma paddr register, offset:0x18+0x18*n n=1...8
807 */
808 union
809 {
810 __IO uint32_t paddr;
811 struct
812 {
813 __IO uint32_t paddr : 32;/* [31:0] */
814 } paddr_bit;
815 };
816 /**
817 * @brief edma m0adr register, offset:0x1C+0x18*n n=1...8
818 */
819 union
820 {
821 __IO uint32_t m0addr;
822 struct
823 {
824 __IO uint32_t m0addr : 32;/* [31:0] */
825 } m0addr_bit;
826 };
827 /**
828 * @brief edma m1adr register, offset:0x20+0x18*n n=1...8
829 */
830 union
831 {
832 __IO uint32_t m1addr;
833 struct
834 {
835 __IO uint32_t m1addr : 32;/* [31:0] */
836 } m1addr_bit;
837 };
838 /**
839 * @brief edma fctrl register, offset:0x24+0x18*n n=1...8
840 */
841 union
842 {
843 __IO uint32_t fctrl;
844 struct
845 {
846 __IO uint32_t fthsel : 2; /* [1:0] */
847 __IO uint32_t fen : 1; /* [2] */
848 __IO uint32_t fsts : 3; /* [5:3] */
849 __IO uint32_t reserved1 : 1; /* [6] */
850 __IO uint32_t ferrien : 1; /* [7] */
851 __IO uint32_t reserved2 : 24;/* [31:8] */
852 } fctrl_bit;
853 };
854 } edma_stream_type;
855
856 /**
857 * @brief type define edma stream link list pointer register
858 */
859 typedef struct
860 {
861 /**
862 * @brief edma stream link list pointer register
863 */
864 union
865 {
866 __IO uint32_t llp;
867 struct
868 {
869 __IO uint32_t llp : 32;/* [31:0] */
870 } llp_bit;
871 };
872 } edma_stream_link_list_type;
873
874 /**
875 * @brief type define edma 2d register all
876 */
877 typedef struct
878 {
879 /**
880 * @brief edma s2dcnt register, offset:0x00
881 */
882 union
883 {
884 __IO uint32_t s2dcnt;
885 struct
886 {
887 __IO uint32_t xcnt : 16;/* [15:0] */
888 __IO uint32_t ycnt : 16;/* [31:16] */
889 } s2dcnt_bit;
890 };
891 /**
892 * @brief edma stride register, offset:0x04
893 */
894 union
895 {
896 __IO uint32_t stride;
897 struct
898 {
899 __IO uint32_t srcstd : 16;/* [15:0] */
900 __IO uint32_t dststd : 16;/* [31:16] */
901 } stride_bit;
902 };
903 } edma_stream_2d_type;
904
905 /**
906 * @brief type define edmamux muxsctrl register
907 */
908 typedef struct
909 {
910 /**
911 * @brief edma muxsctrl register
912 */
913 union
914 {
915 __IO uint32_t muxctrl;
916 struct
917 {
918 __IO uint32_t reqsel : 7; /* [6:0] */
919 __IO uint32_t reserved1 : 1; /* [7] */
920 __IO uint32_t syncovien : 1; /* [8] */
921 __IO uint32_t evtgen : 1; /* [9] */
922 __IO uint32_t reserved2 : 6; /* [15:10] */
923 __IO uint32_t syncen : 1; /* [16] */
924 __IO uint32_t syncpol : 2; /* [18:17] */
925 __IO uint32_t reqcnt : 5; /* [23:19] */
926 __IO uint32_t syncsel : 5; /* [28:24] */
927 __IO uint32_t reserved3 : 3; /* [31:29] */
928 }muxctrl_bit;
929 };
930 } edmamux_channel_type;
931
932 /**
933 * @brief type define edmamux request generator register all
934 */
935 typedef struct
936 {
937 /**
938 * @brief edmamux request generator register, offset:0x160+n*4 n=1...8
939 */
940 union
941 {
942 __IO uint32_t gctrl;
943 struct
944 {
945 __IO uint32_t sigsel : 5; /* [4:0] */
946 __IO uint32_t reserved1 : 3; /* [7:5] */
947 __IO uint32_t trgovien : 1; /* [8] */
948 __IO uint32_t reserved2 : 7; /* [15:9] */
949 __IO uint32_t gen : 1; /* [16] */
950 __IO uint32_t gpol : 2; /* [18:17] */
951 __IO uint32_t greqcnt : 5; /* [23:19] */
952 __IO uint32_t reserved3 : 8; /* [31:24] */
953 }gctrl_bit;
954 };
955 } edmamux_generator_type;
956
957 /**
958 * @}
959 */
960
961 #define EDMA ((edma_type *) EDMA_BASE)
962 #define EDMA_STREAM1 ((edma_stream_type *) EDMA_STREAM1_BASE)
963 #define EDMA_STREAM2 ((edma_stream_type *) EDMA_STREAM2_BASE)
964 #define EDMA_STREAM3 ((edma_stream_type *) EDMA_STREAM3_BASE)
965 #define EDMA_STREAM4 ((edma_stream_type *) EDMA_STREAM4_BASE)
966 #define EDMA_STREAM5 ((edma_stream_type *) EDMA_STREAM5_BASE)
967 #define EDMA_STREAM6 ((edma_stream_type *) EDMA_STREAM6_BASE)
968 #define EDMA_STREAM7 ((edma_stream_type *) EDMA_STREAM7_BASE)
969 #define EDMA_STREAM8 ((edma_stream_type *) EDMA_STREAM8_BASE)
970
971 #define EDMA_STREAM1_2D ((edma_stream_2d_type *) EDMA_STREAM1_2D_BASE)
972 #define EDMA_STREAM2_2D ((edma_stream_2d_type *) EDMA_STREAM2_2D_BASE)
973 #define EDMA_STREAM3_2D ((edma_stream_2d_type *) EDMA_STREAM3_2D_BASE)
974 #define EDMA_STREAM4_2D ((edma_stream_2d_type *) EDMA_STREAM4_2D_BASE)
975 #define EDMA_STREAM5_2D ((edma_stream_2d_type *) EDMA_STREAM5_2D_BASE)
976 #define EDMA_STREAM6_2D ((edma_stream_2d_type *) EDMA_STREAM6_2D_BASE)
977 #define EDMA_STREAM7_2D ((edma_stream_2d_type *) EDMA_STREAM7_2D_BASE)
978 #define EDMA_STREAM8_2D ((edma_stream_2d_type *) EDMA_STREAM8_2D_BASE)
979
980 #define EDMA_STREAM1_LL ((edma_stream_link_list_type *) EDMA_STREAM1_LL_BASE)
981 #define EDMA_STREAM2_LL ((edma_stream_link_list_type *) EDMA_STREAM2_LL_BASE)
982 #define EDMA_STREAM3_LL ((edma_stream_link_list_type *) EDMA_STREAM3_LL_BASE)
983 #define EDMA_STREAM4_LL ((edma_stream_link_list_type *) EDMA_STREAM4_LL_BASE)
984 #define EDMA_STREAM5_LL ((edma_stream_link_list_type *) EDMA_STREAM5_LL_BASE)
985 #define EDMA_STREAM6_LL ((edma_stream_link_list_type *) EDMA_STREAM6_LL_BASE)
986 #define EDMA_STREAM7_LL ((edma_stream_link_list_type *) EDMA_STREAM7_LL_BASE)
987 #define EDMA_STREAM8_LL ((edma_stream_link_list_type *) EDMA_STREAM8_LL_BASE)
988
989 #define EDMAMUX_CHANNEL1 ((edmamux_channel_type *) EDMAMUX_CHANNEL1_BASE)
990 #define EDMAMUX_CHANNEL2 ((edmamux_channel_type *) EDMAMUX_CHANNEL2_BASE)
991 #define EDMAMUX_CHANNEL3 ((edmamux_channel_type *) EDMAMUX_CHANNEL3_BASE)
992 #define EDMAMUX_CHANNEL4 ((edmamux_channel_type *) EDMAMUX_CHANNEL4_BASE)
993 #define EDMAMUX_CHANNEL5 ((edmamux_channel_type *) EDMAMUX_CHANNEL5_BASE)
994 #define EDMAMUX_CHANNEL6 ((edmamux_channel_type *) EDMAMUX_CHANNEL6_BASE)
995 #define EDMAMUX_CHANNEL7 ((edmamux_channel_type *) EDMAMUX_CHANNEL7_BASE)
996 #define EDMAMUX_CHANNEL8 ((edmamux_channel_type *) EDMAMUX_CHANNEL8_BASE)
997
998 #define EDMAMUX_GENERATOR1 ((edmamux_generator_type *) EDMAMUX_GENERATOR1_BASE)
999 #define EDMAMUX_GENERATOR2 ((edmamux_generator_type *) EDMAMUX_GENERATOR2_BASE)
1000 #define EDMAMUX_GENERATOR3 ((edmamux_generator_type *) EDMAMUX_GENERATOR3_BASE)
1001 #define EDMAMUX_GENERATOR4 ((edmamux_generator_type *) EDMAMUX_GENERATOR4_BASE)
1002
1003 /** @defgroup EDMA_exported_functions
1004 * @{
1005 */
1006
1007 /* edma controller function */
1008 void edma_reset(edma_stream_type *edma_streamx);
1009 void edma_init(edma_stream_type *edma_streamx, edma_init_type *edma_init_struct);
1010 void edma_default_para_init(edma_init_type *edma_init_struct);
1011 void edma_stream_enable(edma_stream_type *edma_streamx, confirm_state new_state);
1012 void edma_interrupt_enable(edma_stream_type *edma_streamx, uint32_t edma_int, confirm_state new_state);
1013 void edma_peripheral_inc_offset_set(edma_stream_type *edma_streamx, edma_peripheral_inc_offset_type offset);
1014 void edma_flow_controller_enable(edma_stream_type *edma_streamx, confirm_state new_state);
1015 void edma_data_number_set(edma_stream_type *edma_streamx, uint16_t data_number);
1016 uint16_t edma_data_number_get(edma_stream_type *edma_streamx);
1017 void edma_double_buffer_mode_init(edma_stream_type *edma_streamx, uint32_t memory1_addr, edma_memory_type current_memory);
1018 void edma_double_buffer_mode_enable(edma_stream_type *edma_streamx, confirm_state new_state);
1019 void edma_memory_addr_set(edma_stream_type *edma_streamx, uint32_t memory_addr, uint32_t memory_target);
1020 edma_memory_type edma_memory_target_get(edma_stream_type *edma_streamx);
1021 flag_status edma_stream_status_get(edma_stream_type *edma_streamx);
1022 uint8_t edma_fifo_status_get(edma_stream_type *edma_streamx);
1023 flag_status edma_flag_get(uint32_t edma_flag);
1024 void edma_flag_clear(uint32_t edma_flag);
1025
1026 /* edma 2d controller function */
1027 void edma_2d_init(edma_stream_2d_type *edma_streamx_2d, int16_t src_stride, int16_t dst_stride, uint16_t xcnt, uint16_t ycnt);
1028 void edma_2d_enable(edma_stream_2d_type *edma_streamx_2d, confirm_state new_state);
1029
1030 /* dma link list controller function */
1031 void edma_link_list_init(edma_stream_link_list_type *edma_streamx_ll, uint32_t pointer);
1032 void edma_link_list_enable(edma_stream_link_list_type *edma_streamx_ll, confirm_state new_state);
1033
1034 /* edma requst multiplexer function */
1035 void edmamux_enable(confirm_state new_state);
1036 void edmamux_init(edmamux_channel_type *edmamux_channelx, edmamux_requst_id_sel_type edmamux_req_id);
1037 void edmamux_sync_default_para_init(edmamux_sync_init_type *edmamux_sync_init_struct);
1038 void edmamux_sync_config(edmamux_channel_type *edmamux_channelx, edmamux_sync_init_type *edmamux_sync_init_struct);
1039 void edmamux_generator_default_para_init(edmamux_gen_init_type *edmamux_gen_init_struct);
1040 void edmamux_generator_config(edmamux_generator_type *edmamux_gen_x, edmamux_gen_init_type *edmamux_gen_init_struct);
1041 void edmamux_sync_interrupt_enable(edmamux_channel_type *edmamux_channelx, confirm_state new_state);
1042 void edmamux_generator_interrupt_enable(edmamux_generator_type *edmamux_gen_x, confirm_state new_state);
1043 flag_status edmamux_sync_flag_get(uint32_t flag);
1044 void edmamux_sync_flag_clear(uint32_t flag);
1045 flag_status edmamux_generator_flag_get(uint32_t flag);
1046 void edmamux_generator_flag_clear(uint32_t flag);
1047
1048 /**
1049 * @}
1050 */
1051
1052 /**
1053 * @}
1054 */
1055
1056 /**
1057 * @}
1058 */
1059
1060 #ifdef __cplusplus
1061 }
1062 #endif
1063
1064 #endif
INAV: Navigation-enabled flight control software