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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_ertc.h
blob425da44d00968e22bf3da32065a6e0e9109d17d0
1 /**
2 **************************************************************************
3 * @file at32f435_437_ertc.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 ertc header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_ERTC_H
29 #define __AT32F435_437_ERTC_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup ERTC
44 * @{
45 */
46
47 /** @defgroup ERTC_interrupts_definition
48 * @brief ertc interrupt
49 * @{
50 */
51
52 #define ERTC_TP_INT ((uint32_t)0x00000004) /*!< ertc tamper interrupt */
53 #define ERTC_ALA_INT ((uint32_t)0x00001000) /*!< ertc alarm a interrupt */
54 #define ERTC_ALB_INT ((uint32_t)0x00002000) /*!< ertc alarm b interrupt */
55 #define ERTC_WAT_INT ((uint32_t)0x00004000) /*!< ertc wakeup timer interrupt */
56 #define ERTC_TS_INT ((uint32_t)0x00008000) /*!< ertc timestamp interrupt */
57
58 /**
59 * @}
60 */
61
62 /** @defgroup ERTC_flags_definition
63 * @brief ertc flag
64 * @{
65 */
66
67 #define ERTC_ALAWF_FLAG ((uint32_t)0x00000001) /*!< ertc alarm a register allows write flag */
68 #define ERTC_ALBWF_FLAG ((uint32_t)0x00000002) /*!< ertc alarm b register allows write flag */
69 #define ERTC_WATWF_FLAG ((uint32_t)0x00000004) /*!< ertc wakeup timer register allows write flag */
70 #define ERTC_TADJF_FLAG ((uint32_t)0x00000008) /*!< ertc time adjustment flag */
71 #define ERTC_INITF_FLAG ((uint32_t)0x00000010) /*!< ertc calendar initialization flag */
72 #define ERTC_UPDF_FLAG ((uint32_t)0x00000020) /*!< ertc calendar update flag */
73 #define ERTC_IMF_FLAG ((uint32_t)0x00000040) /*!< ertc enter initialization mode flag */
74 #define ERTC_ALAF_FLAG ((uint32_t)0x00000100) /*!< ertc alarm clock a flag */
75 #define ERTC_ALBF_FLAG ((uint32_t)0x00000200) /*!< ertc alarm clock b flag */
76 #define ERTC_WATF_FLAG ((uint32_t)0x00000400) /*!< ertc wakeup timer flag */
77 #define ERTC_TSF_FLAG ((uint32_t)0x00000800) /*!< ertc timestamp flag */
78 #define ERTC_TSOF_FLAG ((uint32_t)0x00001000) /*!< ertc timestamp overflow flag */
79 #define ERTC_TP1F_FLAG ((uint32_t)0x00002000) /*!< ertc tamper detection 1 flag */
80 #define ERTC_TP2F_FLAG ((uint32_t)0x00004000) /*!< ertc tamper detection 2 flag */
81 #define ERTC_CALUPDF_FLAG ((uint32_t)0x00010000) /*!< ertc calibration value update completed flag */
82
83 /**
84 * @brief ertc alarm mask
85 */
86 #define ERTC_ALARM_MASK_NONE ((uint32_t)0x00000000) /*!< ertc alarm match all */
87 #define ERTC_ALARM_MASK_SEC ((uint32_t)0x00000080) /*!< ertc alarm don't match seconds */
88 #define ERTC_ALARM_MASK_MIN ((uint32_t)0x00008000) /*!< ertc alarm don't match minute */
89 #define ERTC_ALARM_MASK_HOUR ((uint32_t)0x00800000) /*!< ertc alarm don't match hour */
90 #define ERTC_ALARM_MASK_DATE_WEEK ((uint32_t)0x80000000) /*!< ertc alarm don't match date or week */
91 #define ERTC_ALARM_MASK_ALL ((uint32_t)0x80808080) /*!< ertc alarm don't match all */
92
93 /**
94 * @}
95 */
96
97 /**
98 * @brief compatible with older versions
99 */
100 #define ERTC_WAT_CLK_CK_A_16BITS ERTC_WAT_CLK_CK_B_16BITS
101 #define ERTC_WAT_CLK_CK_A_17BITS ERTC_WAT_CLK_CK_B_17BITS
102
103 /**
104 * @}
105 */
106
107 /** @defgroup ERTC_exported_types
108 * @{
109 */
110
111 /**
112 * @brief ertc hour mode
113 */
114 typedef enum
115 {
116 ERTC_HOUR_MODE_24 = 0x00, /*!< 24-hour format */
117 ERTC_HOUR_MODE_12 = 0x01 /*!< 12-hour format */
118 } ertc_hour_mode_set_type;
119
120 /**
121 * @brief ertc 12-hour format am/pm
122 */
123 typedef enum
124 {
125 ERTC_24H = 0x00, /*!< 24-hour format */
126 ERTC_AM = 0x00, /*!< 12-hour format, ante meridiem */
127 ERTC_PM = 0x01 /*!< 12-hour format, meridiem */
128 } ertc_am_pm_type;
129
130 /**
131 * @brief ertc week or date select
132 */
133 typedef enum
134 {
135 ERTC_SLECT_DATE = 0x00, /*!< slect date mode */
136 ERTC_SLECT_WEEK = 0x01 /*!< slect week mode */
137 } ertc_week_date_select_type;
138
139 /**
140 * @brief ertc alarm x select
141 */
142 typedef enum
143 {
144 ERTC_ALA = 0x00, /*!< select alarm a */
145 ERTC_ALB = 0x01 /*!< select alarm b */
146 } ertc_alarm_type;
147
148 /**
149 * @brief ertc alarm sub second mask
150 */
151 typedef enum
152 {
153 ERTC_ALARM_SBS_MASK_ALL = 0x00, /*!< do not match the sub-second */
154 ERTC_ALARM_SBS_MASK_14_1 = 0x01, /*!< only compare bit [0] */
155 ERTC_ALARM_SBS_MASK_14_2 = 0x02, /*!< only compare bit [1:0] */
156 ERTC_ALARM_SBS_MASK_14_3 = 0x03, /*!< only compare bit [2:0] */
157 ERTC_ALARM_SBS_MASK_14_4 = 0x04, /*!< only compare bit [3:0] */
158 ERTC_ALARM_SBS_MASK_14_5 = 0x05, /*!< only compare bit [4:0] */
159 ERTC_ALARM_SBS_MASK_14_6 = 0x06, /*!< only compare bit [5:0] */
160 ERTC_ALARM_SBS_MASK_14_7 = 0x07, /*!< only compare bit [6:0] */
161 ERTC_ALARM_SBS_MASK_14_8 = 0x08, /*!< only compare bit [7:0] */
162 ERTC_ALARM_SBS_MASK_14_9 = 0x09, /*!< only compare bit [8:0] */
163 ERTC_ALARM_SBS_MASK_14_10 = 0x0A, /*!< only compare bit [9:0] */
164 ERTC_ALARM_SBS_MASK_14_11 = 0x0B, /*!< only compare bit [10:0] */
165 ERTC_ALARM_SBS_MASK_14_12 = 0x0C, /*!< only compare bit [11:0] */
166 ERTC_ALARM_SBS_MASK_14_13 = 0x0D, /*!< only compare bit [12:0] */
167 ERTC_ALARM_SBS_MASK_14 = 0x0E, /*!< only compare bit [13:0] */
168 ERTC_ALARM_SBS_MASK_NONE = 0x0F /*!< compare bit [14:0] */
169 } ertc_alarm_sbs_mask_type;
170
171 /**
172 * @brief ertc wakeup timer clock select
173 */
174 typedef enum
175 {
176 ERTC_WAT_CLK_ERTCCLK_DIV16 = 0x00, /*!< the wake up timer clock is ERTC_CLK / 16 */
177 ERTC_WAT_CLK_ERTCCLK_DIV8 = 0x01, /*!< the wake up timer clock is ERTC_CLK / 8 */
178 ERTC_WAT_CLK_ERTCCLK_DIV4 = 0x02, /*!< the wake up timer clock is ERTC_CLK / 4 */
179 ERTC_WAT_CLK_ERTCCLK_DIV2 = 0x03, /*!< the wake up timer clock is ERTC_CLK / 2 */
180 ERTC_WAT_CLK_CK_B_16BITS = 0x04, /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT */
181 ERTC_WAT_CLK_CK_B_17BITS = 0x06 /*!< the wake up timer clock is CK_B, wakeup counter = ERTC_WAT + 65535 */
182 } ertc_wakeup_clock_type;
183
184 /**
185 * @brief ertc smooth calibration period
186 */
187 typedef enum
188 {
189 ERTC_SMOOTH_CAL_PERIOD_32 = 0x00, /*!< 32 second calibration period */
190 ERTC_SMOOTH_CAL_PERIOD_16 = 0x01, /*!< 16 second calibration period */
191 ERTC_SMOOTH_CAL_PERIOD_8 = 0x02 /*!< 8 second calibration period */
192 } ertc_smooth_cal_period_type;
193
194 /**
195 * @brief ertc smooth calibration clock add mode
196 */
197 typedef enum
198 {
199 ERTC_SMOOTH_CAL_CLK_ADD_0 = 0x00, /*!< do not increase clock */
200 ERTC_SMOOTH_CAL_CLK_ADD_512 = 0x01 /*!< add 512 clocks */
201 } ertc_smooth_cal_clk_add_type;
202
203 /**
204 * @brief ertc calibration direction mode
205 */
206 typedef enum
207 {
208 ERTC_CAL_DIR_POSITIVE = 0x00, /*!< positive calibration */
209 ERTC_CAL_DIR_NEGATIVE = 0x01 /*!< negative calibration */
210 } ertc_cal_direction_type;
211
212 /**
213 * @brief ertc calibration output mode
214 */
215 typedef enum
216 {
217 ERTC_CAL_OUTPUT_512HZ = 0x00, /*!< output 512 hz */
218 ERTC_CAL_OUTPUT_1HZ = 0x01 /*!< output 1 hz */
219 } ertc_cal_output_select_type;
220
221 /**
222 * @brief time adjust add mode
223 */
224 typedef enum
225 {
226 ERTC_TIME_ADD_NONE = 0x00, /*!< none operation */
227 ERTC_TIME_ADD_1S = 0x01 /*!< add 1 second */
228 } ertc_time_adjust_type;
229
230 /**
231 * @brief ertc daylight saving time hour adjustment mode
232 */
233 typedef enum
234 {
235 ERTC_DST_ADD_1H = 0x00, /*!< add 1 hour */
236 ERTC_DST_DEC_1H = 0x01 /*!< dec 1 hour */
237 } ertc_dst_operation_type;
238
239 /**
240 * @brief ertc daylight saving time store operation mode
241 */
242 typedef enum
243 {
244 ERTC_DST_SAVE_0 = 0x00, /*!< set the bpr register value to 0 */
245 ERTC_DST_SAVE_1 = 0x01 /*!< set the bpr register value to 1 */
246 } ertc_dst_save_type;
247
248 /**
249 * @brief output source
250 */
251 typedef enum
252 {
253 ERTC_OUTPUT_DISABLE = 0x00, /*!< diable output */
254 ERTC_OUTPUT_ALARM_A = 0x01, /*!< output alarm a event */
255 ERTC_OUTPUT_ALARM_B = 0x02, /*!< output alarm b event */
256 ERTC_OUTPUT_WAKEUP = 0x03 /*!< output wakeup event */
257 } ertc_output_source_type;
258
259 /**
260 * @brief output polarity
261 */
262 typedef enum
263 {
264 ERTC_OUTPUT_POLARITY_HIGH = 0x00, /*!< when the event occurs, the output is high */
265 ERTC_OUTPUT_POLARITY_LOW = 0x01 /*!< when the event occurs, the output is low */
266 } ertc_output_polarity_type;
267
268 /**
269 * @brief output type
270 */
271 typedef enum
272 {
273 ERTC_OUTPUT_TYPE_OPEN_DRAIN = 0x00, /*!< open drain output */
274 ERTC_OUTPUT_TYPE_PUSH_PULL = 0x01 /*!< push pull output */
275 } ertc_output_type;
276
277 /**
278 * @brief timestamp/ tamper detection pin selection
279 */
280 typedef enum
281 {
282 ERTC_PIN_PC13 = 0x00, /*!< pc13 is used as timestamp detection pin */
283 ERTC_PIN_PA0 = 0x01 /*!< pa0 is used as timestamp detection pin */
284 } ertc_pin_select_type;
285
286 /**
287 * @brief ertc timestamp valid edge
288 */
289 typedef enum
290 {
291 ERTC_TIMESTAMP_EDGE_RISING = 0x00, /*!< rising edge trigger */
292 ERTC_TIMESTAMP_EDGE_FALLING = 0x01 /*!< falling edge trigger */
293 } ertc_timestamp_valid_edge_type;
294
295 /**
296 * @brief ertc tamper x select
297 */
298 typedef enum
299 {
300 ERTC_TAMPER_1 = 0x00, /*!< tamper 1 */
301 ERTC_TAMPER_2 = 0x01 /*!< tamper 2 */
302 } ertc_tamper_select_type;
303
304 /**
305 * @brief tamper detection pre-charge time
306 */
307 typedef enum
308 {
309 ERTC_TAMPER_PR_1_ERTCCLK = 0x00, /*!< pre-charge time is 1 ERTC_CLK */
310 ERTC_TAMPER_PR_2_ERTCCLK = 0x01, /*!< pre-charge time is 2 ERTC_CLK */
311 ERTC_TAMPER_PR_4_ERTCCLK = 0x02, /*!< pre-charge time is 4 ERTC_CLK */
312 ERTC_TAMPER_PR_8_ERTCCLK = 0x03 /*!< pre-charge time is 8 ERTC_CLK */
313 } ertc_tamper_precharge_type;
314
315 /**
316 * @brief ertc tamper filter
317 */
318 typedef enum
319 {
320 ERTC_TAMPER_FILTER_DISABLE = 0x00, /*!< disable filter function */
321 ERTC_TAMPER_FILTER_2 = 0x01, /*!< 2 consecutive samples arw valid, effective tamper event */
322 ERTC_TAMPER_FILTER_4 = 0x02, /*!< 4 consecutive samples arw valid, effective tamper event */
323 ERTC_TAMPER_FILTER_8 = 0x03 /*!< 8 consecutive samples arw valid, effective tamper event */
324 } ertc_tamper_filter_type;
325
326 /**
327 * @brief ertc tamper detection frequency
328 */
329 typedef enum
330 {
331 ERTC_TAMPER_FREQ_DIV_32768 = 0x00, /*!< ERTC_CLK / 32768 */
332 ERTC_TAMPER_FREQ_DIV_16384 = 0x01, /*!< ERTC_CLK / 16384 */
333 ERTC_TAMPER_FREQ_DIV_8192 = 0x02, /*!< ERTC_CLK / 8192 */
334 ERTC_TAMPER_FREQ_DIV_4096 = 0x03, /*!< ERTC_CLK / 4096 */
335 ERTC_TAMPER_FREQ_DIV_2048 = 0x04, /*!< ERTC_CLK / 2048 */
336 ERTC_TAMPER_FREQ_DIV_1024 = 0x05, /*!< ERTC_CLK / 1024 */
337 ERTC_TAMPER_FREQ_DIV_512 = 0x06, /*!< ERTC_CLK / 512 */
338 ERTC_TAMPER_FREQ_DIV_256 = 0x07 /*!< ERTC_CLK / 256 */
339 } ertc_tamper_detect_freq_type;
340
341 /**
342 * @brief ertc tamper valid edge
343 */
344 typedef enum
345 {
346 ERTC_TAMPER_EDGE_RISING = 0x00, /*!< rising gedge */
347 ERTC_TAMPER_EDGE_FALLING = 0x01, /*!< falling gedge */
348 ERTC_TAMPER_EDGE_LOW = 0x00, /*!< low level */
349 ERTC_TAMPER_EDGE_HIGH = 0x01 /*!< high level */
350 } ertc_tamper_valid_edge_type;
351
352 /**
353 * @brief ertc bpr register
354 */
355 typedef enum
356 {
357 ERTC_DT1 = 0, /*!< bpr data register 0 */
358 ERTC_DT2 = 1, /*!< bpr data register 1 */
359 ERTC_DT3 = 2, /*!< bpr data register 2 */
360 ERTC_DT4 = 3, /*!< bpr data register 3 */
361 ERTC_DT5 = 4, /*!< bpr data register 4 */
362 ERTC_DT6 = 5, /*!< bpr data register 5 */
363 ERTC_DT7 = 6, /*!< bpr data register 6 */
364 ERTC_DT8 = 7, /*!< bpr data register 7 */
365 ERTC_DT9 = 8, /*!< bpr data register 8 */
366 ERTC_DT10 = 9, /*!< bpr data register 9 */
367 ERTC_DT11 = 10, /*!< bpr data register 10 */
368 ERTC_DT12 = 11, /*!< bpr data register 11 */
369 ERTC_DT13 = 12, /*!< bpr data register 12 */
370 ERTC_DT14 = 13, /*!< bpr data register 13 */
371 ERTC_DT15 = 14, /*!< bpr data register 14 */
372 ERTC_DT16 = 15, /*!< bpr data register 15 */
373 ERTC_DT17 = 16, /*!< bpr data register 16 */
374 ERTC_DT18 = 17, /*!< bpr data register 17 */
375 ERTC_DT19 = 18, /*!< bpr data register 18 */
376 ERTC_DT20 = 19 /*!< bpr data register 19 */
377 } ertc_dt_type;
378
379 /**
380 * @brief ertc time
381 */
382 typedef struct
383 {
384 uint8_t year; /*!< year */
385 uint8_t month; /*!< month */
386 uint8_t day; /*!< date */
387 uint8_t hour; /*!< hour */
388 uint8_t min; /*!< minute */
389 uint8_t sec; /*!< second */
390 uint8_t week; /*!< week */
391 ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
392 } ertc_time_type;
393
394 /**
395 * @brief ertc alarm
396 */
397 typedef struct
398 {
399 uint8_t day; /*!< date */
400 uint8_t hour; /*!< hour */
401 uint8_t min; /*!< minute */
402 uint8_t sec; /*!< second */
403 ertc_am_pm_type ampm; /*!< ante meridiem / post meridiem */
404 uint32_t mask; /*!< alarm mask*/
405 uint8_t week_date_sel; /*!< week or date mode */
406 uint8_t week; /*!< week */
407 } ertc_alarm_value_type;
408
409 /**
410 * @brief ertc time reg union
411 */
412 typedef union
413 {
414 __IO uint32_t time;
415 struct
416 {
417 __IO uint32_t s : 7; /* [6:0] */
418 __IO uint32_t reserved1 : 1; /* [7] */
419 __IO uint32_t m : 7; /* [14:8] */
420 __IO uint32_t reserved2 : 1; /* [15] */
421 __IO uint32_t h : 6; /* [21:16] */
422 __IO uint32_t ampm : 1; /* [22] */
423 __IO uint32_t reserved3 : 9; /* [31:23] */
424 } time_bit;
425 } ertc_reg_time_type;
426
427 /**
428 * @brief ertc date reg union
429 */
430 typedef union
431 {
432 __IO uint32_t date;
433 struct
434 {
435 __IO uint32_t d :6; /* [5:0] */
436 __IO uint32_t reserved1 :2; /* [7:6] */
437 __IO uint32_t m :5; /* [12:8] */
438 __IO uint32_t wk :3; /* [15:13] */
439 __IO uint32_t y :8; /* [23:16] */
440 __IO uint32_t reserved2 :8; /* [31:24] */
441 } date_bit;
442 } ertc_reg_date_type;
443
444 /**
445 * @brief ertc alarm reg union
446 */
447 typedef union
448 {
449 __IO uint32_t ala;
450 struct
451 {
452 __IO uint32_t s :7; /* [6:0] */
453 __IO uint32_t mask1 :1; /* [7] */
454 __IO uint32_t m :7; /* [14:8] */
455 __IO uint32_t mask2 :1; /* [15] */
456 __IO uint32_t h :6; /* [21:16] */
457 __IO uint32_t ampm :1; /* [22] */
458 __IO uint32_t mask3 :1; /* [23] */
459 __IO uint32_t d :6; /* [29:24] */
460 __IO uint32_t wksel :1; /* [30] */
461 __IO uint32_t mask4 :1; /* [31] */
462 } ala_bit;
463 } ertc_reg_alarm_type;
464
465 /**
466 * @brief ertc scal reg union
467 */
468 typedef union
469 {
470 __IO uint32_t scal;
471 struct
472 {
473 __IO uint32_t dec :9; /* [8:0] */
474 __IO uint32_t reserved1 :4; /* [12:9] */
475 __IO uint32_t cal16 :1; /* [13] */
476 __IO uint32_t cal8 :1; /* [14] */
477 __IO uint32_t add :1; /* [15] */
478 __IO uint32_t reserved2 :16;/* [31:16] */
479 } scal_bit;
480 } ertc_reg_scal_type;
481
482 /**
483 * @brief ertc tadj reg union
484 */
485 typedef union
486 {
487 __IO uint32_t tadj;
488 struct
489 {
490 __IO uint32_t decsbs :15;/* [14:0] */
491 __IO uint32_t reserved1 :16;/* [30:15] */
492 __IO uint32_t add1s :1; /* [31] */
493 } tadj_bit;
494 } ertc_reg_tadj_type;
495
496 /**
497 * @brief ertc tstm reg union
498 */
499 typedef union
500 {
501 __IO uint32_t tstm;
502 struct
503 {
504 __IO uint32_t s :7; /* [6:0] */
505 __IO uint32_t reserved1 :1; /* [7] */
506 __IO uint32_t m :7; /* [14:8] */
507 __IO uint32_t reserved2 :1; /* [15] */
508 __IO uint32_t h :6; /* [21:16] */
509 __IO uint32_t ampm :1; /* [22] */
510 __IO uint32_t reserved3 :9; /* [31:23] */
511 } tstm_bit;
512 } ertc_reg_tstm_type;
513
514 /**
515 * @brief ertc tsdt register, offset:0x34
516 */
517 typedef union
518 {
519 __IO uint32_t tsdt;
520 struct
521 {
522 __IO uint32_t d :6; /* [5:0] */
523 __IO uint32_t reserved1 :2; /* [7:6] */
524 __IO uint32_t m :5; /* [12:8] */
525 __IO uint32_t wk :3; /* [15:13] */
526 __IO uint32_t reserved2 :16;/* [31:16] */
527 } tsdt_bit;
528 } ertc_reg_tsdt_type;
529
530 /**
531 * @brief type define ertc register all
532 */
533 typedef struct
534 {
535
536 /**
537 * @brief ertc time register, offset:0x00
538 */
539 union
540 {
541 __IO uint32_t time;
542 struct
543 {
544 __IO uint32_t s : 7; /* [6:0] */
545 __IO uint32_t reserved1 : 1; /* [7] */
546 __IO uint32_t m : 7; /* [14:8] */
547 __IO uint32_t reserved2 : 1; /* [15] */
548 __IO uint32_t h : 6; /* [21:16] */
549 __IO uint32_t ampm : 1; /* [22] */
550 __IO uint32_t reserved3 : 9; /* [31:23] */
551 } time_bit;
552 };
553
554 /**
555 * @brief ertc date register, offset:0x04
556 */
557 union
558 {
559 __IO uint32_t date;
560 struct
561 {
562 __IO uint32_t d :6; /* [5:0] */
563 __IO uint32_t reserved1 :2; /* [7:6] */
564 __IO uint32_t m :5; /* [12:8] */
565 __IO uint32_t wk :3; /* [15:13] */
566 __IO uint32_t y :8; /* [23:16] */
567 __IO uint32_t reserved2 :8; /* [31:24] */
568 } date_bit;
569 };
570
571 /**
572 * @brief ertc ctrl register, offset:0x08
573 */
574 union
575 {
576 __IO uint32_t ctrl;
577 struct
578 {
579 __IO uint32_t watclk :3; /* [2:0] */
580 __IO uint32_t tsedg :1; /* [3] */
581 __IO uint32_t rcden :1; /* [4] */
582 __IO uint32_t dren :1; /* [5] */
583 __IO uint32_t hm :1; /* [6] */
584 __IO uint32_t ccalen :1; /* [7] */
585 __IO uint32_t alaen :1; /* [8] */
586 __IO uint32_t alben :1; /* [9] */
587 __IO uint32_t waten :1; /* [10] */
588 __IO uint32_t tsen :1; /* [11] */
589 __IO uint32_t alaien :1; /* [12] */
590 __IO uint32_t albien :1; /* [13] */
591 __IO uint32_t watien :1; /* [14] */
592 __IO uint32_t tsien :1; /* [15] */
593 __IO uint32_t add1h :1; /* [16] */
594 __IO uint32_t dec1h :1; /* [17] */
595 __IO uint32_t bpr :1; /* [18] */
596 __IO uint32_t calosel :1; /* [19] */
597 __IO uint32_t outp :1; /* [20] */
598 __IO uint32_t outsel :2; /* [22:21] */
599 __IO uint32_t caloen :1; /* [23] */
600 __IO uint32_t reserved1 :8; /* [31:24] */
601 } ctrl_bit;
602 };
603
604 /**
605 * @brief ertc sts register, offset:0x0C
606 */
607 union
608 {
609 __IO uint32_t sts;
610 struct
611 {
612 __IO uint32_t alawf :1; /* [0] */
613 __IO uint32_t albwf :1; /* [1] */
614 __IO uint32_t watwf :1; /* [2] */
615 __IO uint32_t tadjf :1; /* [3] */
616 __IO uint32_t initf :1; /* [4] */
617 __IO uint32_t updf :1; /* [5] */
618 __IO uint32_t imf :1; /* [6] */
619 __IO uint32_t imen :1; /* [7] */
620 __IO uint32_t alaf :1; /* [8] */
621 __IO uint32_t albf :1; /* [9] */
622 __IO uint32_t watf :1; /* [10] */
623 __IO uint32_t tsf :1; /* [11] */
624 __IO uint32_t tsof :1; /* [12] */
625 __IO uint32_t tp1f :1; /* [13] */
626 __IO uint32_t tp2f :1; /* [14] */
627 __IO uint32_t reserved1 :1; /* [15] */
628 __IO uint32_t calupdf :1; /* [16] */
629 __IO uint32_t reserved2 :15;/* [31:17] */
630 } sts_bit;
631 };
632
633 /**
634 * @brief ertc div register, offset:0x10
635 */
636 union
637 {
638 __IO uint32_t div;
639 struct
640 {
641 __IO uint32_t divb :15;/* [14:0] */
642 __IO uint32_t reserved1 :1; /* [15] */
643 __IO uint32_t diva :7; /* [22:16] */
644 __IO uint32_t reserved2 :9; /* [31:23] */
645 } div_bit;
646 };
647
648 /**
649 * @brief ertc wat register, offset:0x14
650 */
651 union
652 {
653 __IO uint32_t wat;
654 struct
655 {
656 __IO uint32_t val :16;/* [15:0] */
657 __IO uint32_t reserved1 :16;/* [31:16] */
658 } wat_bit;
659 };
660
661 /**
662 * @brief ertc ccal register, offset:0x18
663 */
664 union
665 {
666 __IO uint32_t ccal;
667 struct
668 {
669 __IO uint32_t calval :5; /* [4:0] */
670 __IO uint32_t reserved1 :2; /* [6:5] */
671 __IO uint32_t caldir :1; /* [7] */
672 __IO uint32_t reserved2 :24;/* [31:8] */
673 } ccal_bit;
674 };
675
676 /**
677 * @brief ertc ala register, offset:0x1C
678 */
679 union
680 {
681 __IO uint32_t ala;
682 struct
683 {
684 __IO uint32_t s :7; /* [6:0] */
685 __IO uint32_t mask1 :1; /* [7] */
686 __IO uint32_t m :7; /* [14:8] */
687 __IO uint32_t mask2 :1; /* [15] */
688 __IO uint32_t h :6; /* [21:16] */
689 __IO uint32_t ampm :1; /* [22] */
690 __IO uint32_t mask3 :1; /* [23] */
691 __IO uint32_t d :6; /* [29:24] */
692 __IO uint32_t wksel :1; /* [30] */
693 __IO uint32_t mask4 :1; /* [31] */
694 } ala_bit;
695 };
696
697 /**
698 * @brief ertc alb register, offset:0x20
699 */
700 union
701 {
702 __IO uint32_t alb;
703 struct
704 {
705 __IO uint32_t s :7; /* [6:0] */
706 __IO uint32_t mask1 :1; /* [7] */
707 __IO uint32_t m :7; /* [14:8] */
708 __IO uint32_t mask2 :1; /* [15] */
709 __IO uint32_t h :6; /* [21:16] */
710 __IO uint32_t ampm :1; /* [22] */
711 __IO uint32_t mask3 :1; /* [23] */
712 __IO uint32_t d :6; /* [29:24] */
713 __IO uint32_t wksel :1; /* [30] */
714 __IO uint32_t mask4 :1; /* [31] */
715 } alb_bit;
716 };
717
718 /**
719 * @brief ertc wp register, offset:0x24
720 */
721 union
722 {
723 __IO uint32_t wp;
724 struct
725 {
726 __IO uint32_t cmd :8; /* [7:0] */
727 __IO uint32_t reserved1 :24;/* [31:8] */
728 } wp_bit;
729 };
730
731 /**
732 * @brief ertc sbs register, offset:0x28
733 */
734 union
735 {
736 __IO uint32_t sbs;
737 struct
738 {
739 __IO uint32_t sbs :16;/* [15:0] */
740 __IO uint32_t reserved1 :16;/* [31:16] */
741 } sbs_bit;
742 };
743
744 /**
745 * @brief ertc tadj register, offset:0x2C
746 */
747 union
748 {
749 __IO uint32_t tadj;
750 struct
751 {
752 __IO uint32_t decsbs :15;/* [14:0] */
753 __IO uint32_t reserved1 :16;/* [30:15] */
754 __IO uint32_t add1s :1; /* [31] */
755 } tadj_bit;
756 };
757
758 /**
759 * @brief ertc tstm register, offset:0x30
760 */
761 union
762 {
763 __IO uint32_t tstm;
764 struct
765 {
766 __IO uint32_t s :7; /* [6:0] */
767 __IO uint32_t reserved1 :1; /* [7] */
768 __IO uint32_t m :7; /* [14:8] */
769 __IO uint32_t reserved2 :1; /* [15] */
770 __IO uint32_t h :6; /* [21:16] */
771 __IO uint32_t ampm :1; /* [22] */
772 __IO uint32_t reserved3 :9; /* [31:23] */
773 } tstm_bit;
774 };
775
776 /**
777 * @brief ertc tsdt register, offset:0x34
778 */
779 union
780 {
781 __IO uint32_t tsdt;
782 struct
783 {
784 __IO uint32_t d :6; /* [5:0] */
785 __IO uint32_t reserved1 :2; /* [7:6] */
786 __IO uint32_t m :5; /* [12:8] */
787 __IO uint32_t wk :3; /* [15:13] */
788 __IO uint32_t reserved2 :16;/* [31:16] */
789 } tsdt_bit;
790 };
791
792 /**
793 * @brief ertc tssbs register, offset:0x38
794 */
795 union
796 {
797 __IO uint32_t tssbs;
798 struct
799 {
800 __IO uint32_t sbs :16;/* [15:0] */
801 __IO uint32_t reserved1 :16;/* [31:16] */
802 } tssbs_bit;
803 };
804
805 /**
806 * @brief ertc scal register, offset:0x3C
807 */
808 union
809 {
810 __IO uint32_t scal;
811 struct
812 {
813 __IO uint32_t dec :9; /* [8:0] */
814 __IO uint32_t reserved1 :4; /* [12:9] */
815 __IO uint32_t cal16 :1; /* [13] */
816 __IO uint32_t cal8 :1; /* [14] */
817 __IO uint32_t add :1; /* [15] */
818 __IO uint32_t reserved2 :16;/* [31:16] */
819 } scal_bit;
820 };
821
822 /**
823 * @brief ertc tamp register, offset:0x40
824 */
825 union
826 {
827 __IO uint32_t tamp;
828 struct
829 {
830 __IO uint32_t tp1en :1; /* [0] */
831 __IO uint32_t tp1edg :1; /* [1] */
832 __IO uint32_t tpien :1; /* [2] */
833 __IO uint32_t tp2en :1; /* [3] */
834 __IO uint32_t tp2edg :1; /* [4] */
835 __IO uint32_t reserved1 :2; /* [6:5] */
836 __IO uint32_t tptsen :1; /* [7] */
837 __IO uint32_t tpfreq :3; /* [10:8] */
838 __IO uint32_t tpflt :2; /* [12:11] */
839 __IO uint32_t tppr :2; /* [14:13] */
840 __IO uint32_t tppu :1; /* [15] */
841 __IO uint32_t tp1pin :1; /* [16] */
842 __IO uint32_t tspin :1; /* [17] */
843 __IO uint32_t outtype :1; /* [18] */
844 __IO uint32_t reserved2 :13;/* [31:19] */
845 } tamp_bit;
846 };
847
848 /**
849 * @brief ertc alasbs register, offset:0x44
850 */
851 union
852 {
853 __IO uint32_t alasbs;
854 struct
855 {
856 __IO uint32_t sbs :15;/* [14:0] */
857 __IO uint32_t reserved1 :9; /* [23:15] */
858 __IO uint32_t sbsmsk :4; /* [27:24] */
859 __IO uint32_t reserved2 :4; /* [31:28] */
860 } alasbs_bit;
861 };
862
863 /**
864 * @brief ertc albsbs register, offset:0x48
865 */
866 union
867 {
868 __IO uint32_t albsbs;
869 struct
870 {
871 __IO uint32_t sbs :15;/* [14:0] */
872 __IO uint32_t reserved1 :9; /* [23:15] */
873 __IO uint32_t sbsmsk :4; /* [27:24] */
874 __IO uint32_t reserved2 :4; /* [31:28] */
875 } albsbs_bit;
876 };
877
878 /**
879 * @brief reserved register, offset:0x4c
880 */
881 __IO uint32_t reserved1;
882
883 /**
884 * @brief ertc dt1 register, offset:0x50
885 */
886 union
887 {
888 __IO uint32_t dt1;
889 struct
890 {
891 __IO uint32_t dt :32;/* [31:0] */
892 } dt1_bit;
893 };
894
895 /**
896 * @brief ertc dt2 register, offset:0x54
897 */
898 union
899 {
900 __IO uint32_t dt2;
901 struct
902 {
903 __IO uint32_t dt :32;/* [31:0] */
904 } dt2_bit;
905 };
906
907 /**
908 * @brief ertc dt3 register, offset:0x58
909 */
910 union
911 {
912 __IO uint32_t dt3;
913 struct
914 {
915 __IO uint32_t dt :32;/* [31:0] */
916 } dt3_bit;
917 };
918
919 /**
920 * @brief ertc dt4 register, offset:0x5C
921 */
922 union
923 {
924 __IO uint32_t dt4;
925 struct
926 {
927 __IO uint32_t dt :32;/* [31:0] */
928 } dt4_bit;
929 };
930
931 /**
932 * @brief ertc dt5 register, offset:0x60
933 */
934 union
935 {
936 __IO uint32_t dt5;
937 struct
938 {
939 __IO uint32_t dt :32;/* [31:0] */
940 } dt5_bit;
941 };
942
943 /**
944 * @brief ertc dt6 register, offset:0x64
945 */
946 union
947 {
948 __IO uint32_t dt6;
949 struct
950 {
951 __IO uint32_t dt :32;/* [31:0] */
952 } dt6_bit;
953 };
954
955 /**
956 * @brief ertc dt7 register, offset:0x68
957 */
958 union
959 {
960 __IO uint32_t dt7;
961 struct
962 {
963 __IO uint32_t dt :32;/* [31:0] */
964 } dt7_bit;
965 };
966
967 /**
968 * @brief ertc dt8 register, offset:0x6C
969 */
970 union
971 {
972 __IO uint32_t dt8;
973 struct
974 {
975 __IO uint32_t dt :32;/* [31:0] */
976 } dt8_bit;
977 };
978
979 /**
980 * @brief ertc dt9 register, offset:0x70
981 */
982 union
983 {
984 __IO uint32_t dt9;
985 struct
986 {
987 __IO uint32_t dt :32;/* [31:0] */
988 } dt9_bit;
989 };
990
991 /**
992 * @brief ertc dt10 register, offset:0x74
993 */
994 union
995 {
996 __IO uint32_t dt10;
997 struct
998 {
999 __IO uint32_t dt :32;/* [31:0] */
1000 } dt10_bit;
1001 };
1002
1003 /**
1004 * @brief ertc dt11 register, offset:0x78
1005 */
1006 union
1007 {
1008 __IO uint32_t dt11;
1009 struct
1010 {
1011 __IO uint32_t dt :32;/* [31:0] */
1012 } dt11_bit;
1013 };
1014
1015 /**
1016 * @brief ertc dt12 register, offset:0x7C
1017 */
1018 union
1019 {
1020 __IO uint32_t dt12;
1021 struct
1022 {
1023 __IO uint32_t dt :32;/* [31:0] */
1024 } dt12_bit;
1025 };
1026
1027 /**
1028 * @brief ertc dt13 register, offset:0x80
1029 */
1030 union
1031 {
1032 __IO uint32_t dt13;
1033 struct
1034 {
1035 __IO uint32_t dt :32;/* [31:0] */
1036 } dt13_bit;
1037 };
1038
1039 /**
1040 * @brief ertc dt14 register, offset:0x84
1041 */
1042 union
1043 {
1044 __IO uint32_t dt14;
1045 struct
1046 {
1047 __IO uint32_t dt :32;/* [31:0] */
1048 } dt14_bit;
1049 };
1050
1051 /**
1052 * @brief ertc dt15 register, offset:0x88
1053 */
1054 union
1055 {
1056 __IO uint32_t dt15;
1057 struct
1058 {
1059 __IO uint32_t dt :32;/* [31:0] */
1060 } dt15_bit;
1061 };
1062
1063 /**
1064 * @brief ertc dt16 register, offset:0x8C
1065 */
1066 union
1067 {
1068 __IO uint32_t dt16;
1069 struct
1070 {
1071 __IO uint32_t dt :32;/* [31:0] */
1072 } dt16_bit;
1073 };
1074
1075 /**
1076 * @brief ertc dt17 register, offset:0x90
1077 */
1078 union
1079 {
1080 __IO uint32_t dt17;
1081 struct
1082 {
1083 __IO uint32_t dt :32;/* [31:0] */
1084 } dt17_bit;
1085 };
1086
1087 /**
1088 * @brief ertc dt18 register, offset:0x94
1089 */
1090 union
1091 {
1092 __IO uint32_t dt18;
1093 struct
1094 {
1095 __IO uint32_t dt :32;/* [31:0] */
1096 } dt18_bit;
1097 };
1098
1099 /**
1100 * @brief ertc dt19 register, offset:0x98
1101 */
1102 union
1103 {
1104 __IO uint32_t dt19;
1105 struct
1106 {
1107 __IO uint32_t dt :32;/* [31:0] */
1108 } dt19_bit;
1109 };
1110
1111 /**
1112 * @brief ertc dt20 register, offset:0x9C
1113 */
1114 union
1115 {
1116 __IO uint32_t dt20;
1117 struct
1118 {
1119 __IO uint32_t dt :32;/* [31:0] */
1120 } dt20_bit;
1121 };
1122
1123
1124 } ertc_type;
1125
1126 /**
1127 * @}
1128 */
1129
1130 #define ERTC ((ertc_type *) ERTC_BASE)
1131
1132 /** @defgroup ERTC_exported_functions
1133 * @{
1134 */
1135
1136 uint8_t ertc_num_to_bcd(uint8_t num);
1137 uint8_t ertc_bcd_to_num(uint8_t bcd);
1138 void ertc_write_protect_enable(void);
1139 void ertc_write_protect_disable(void);
1140 error_status ertc_wait_update(void);
1141 error_status ertc_wait_flag(uint32_t flag, flag_status status);
1142 error_status ertc_init_mode_enter(void);
1143 void ertc_init_mode_exit(void);
1144 error_status ertc_reset(void);
1145 error_status ertc_divider_set(uint16_t div_a, uint16_t div_b);
1146 error_status ertc_hour_mode_set(ertc_hour_mode_set_type mode);
1147 error_status ertc_date_set(uint8_t year, uint8_t month, uint8_t date, uint8_t week);
1148 error_status ertc_time_set(uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
1149 void ertc_calendar_get(ertc_time_type* time);
1150 uint32_t ertc_sub_second_get(void);
1151 void ertc_alarm_mask_set(ertc_alarm_type alarm_x, uint32_t mask);
1152 void ertc_alarm_week_date_select(ertc_alarm_type alarm_x, ertc_week_date_select_type wk);
1153 void ertc_alarm_set(ertc_alarm_type alarm_x, uint8_t week_date, uint8_t hour, uint8_t min, uint8_t sec, ertc_am_pm_type ampm);
1154 void ertc_alarm_sub_second_set(ertc_alarm_type alarm_x, uint32_t value, ertc_alarm_sbs_mask_type mask);
1155 error_status ertc_alarm_enable(ertc_alarm_type alarm_x, confirm_state new_state);
1156 void ertc_alarm_get(ertc_alarm_type alarm_x, ertc_alarm_value_type* alarm);
1157 uint32_t ertc_alarm_sub_second_get(ertc_alarm_type alarm_x);
1158 void ertc_wakeup_clock_set(ertc_wakeup_clock_type clock);
1159 void ertc_wakeup_counter_set(uint32_t counter);
1160 uint16_t ertc_wakeup_counter_get(void);
1161 error_status ertc_wakeup_enable(confirm_state new_state);
1162 error_status ertc_smooth_calibration_config(ertc_smooth_cal_period_type period, ertc_smooth_cal_clk_add_type clk_add, uint32_t clk_dec);
1163 error_status ertc_coarse_calibration_set(ertc_cal_direction_type dir, uint32_t value);
1164 error_status ertc_coarse_calibration_enable(confirm_state new_state);
1165 void ertc_cal_output_select(ertc_cal_output_select_type output);
1166 void ertc_cal_output_enable(confirm_state new_state);
1167 error_status ertc_time_adjust(ertc_time_adjust_type add1s, uint32_t decsbs);
1168 void ertc_daylight_set(ertc_dst_operation_type operation, ertc_dst_save_type save);
1169 uint8_t ertc_daylight_bpr_get(void);
1170 error_status ertc_refer_clock_detect_enable(confirm_state new_state);
1171 void ertc_direct_read_enable(confirm_state new_state);
1172 void ertc_output_set(ertc_output_source_type source, ertc_output_polarity_type polarity, ertc_output_type type);
1173 void ertc_timestamp_pin_select(ertc_pin_select_type pin);
1174 void ertc_timestamp_valid_edge_set(ertc_timestamp_valid_edge_type edge);
1175 void ertc_timestamp_enable(confirm_state new_state);
1176 void ertc_timestamp_get(ertc_time_type* time);
1177 uint32_t ertc_timestamp_sub_second_get(void);
1178 void ertc_tamper_1_pin_select(ertc_pin_select_type pin);
1179 void ertc_tamper_pull_up_enable(confirm_state new_state);
1180 void ertc_tamper_precharge_set(ertc_tamper_precharge_type precharge);
1181 void ertc_tamper_filter_set(ertc_tamper_filter_type filter);
1182 void ertc_tamper_detect_freq_set(ertc_tamper_detect_freq_type freq);
1183 void ertc_tamper_valid_edge_set(ertc_tamper_select_type tamper_x, ertc_tamper_valid_edge_type trigger);
1184 void ertc_tamper_timestamp_enable(confirm_state new_state);
1185 void ertc_tamper_enable(ertc_tamper_select_type tamper_x, confirm_state new_state);
1186 void ertc_interrupt_enable(uint32_t source, confirm_state new_state);
1187 flag_status ertc_interrupt_get(uint32_t source);
1188 flag_status ertc_flag_get(uint32_t flag);
1189 void ertc_flag_clear(uint32_t flag);
1190 void ertc_bpr_data_write(ertc_dt_type dt, uint32_t data);
1191 uint32_t ertc_bpr_data_read(ertc_dt_type dt);
1192
1193 /**
1194 * @}
1195 */
1196
1197 /**
1198 * @}
1199 */
1200
1201 /**
1202 * @}
1203 */
1204
1205 #ifdef __cplusplus
1206 }
1207 #endif
1208
1209 #endif
INAV: Navigation-enabled flight control software