lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_gpio.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_gpio.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 gpio header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_GPIO_H
  29 #define __AT32F435_437_GPIO_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup GPIO
  44   * @{
  45   */
  46
  47 /** @defgroup GPIO_pins_number_definition
  48   * @{
  49   */
  50
  51 #define GPIO_PINS_0                      0x0001 /*!< gpio pins number 0 */
  52 #define GPIO_PINS_1                      0x0002 /*!< gpio pins number 1 */
  53 #define GPIO_PINS_2                      0x0004 /*!< gpio pins number 2 */
  54 #define GPIO_PINS_3                      0x0008 /*!< gpio pins number 3 */
  55 #define GPIO_PINS_4                      0x0010 /*!< gpio pins number 4 */
  56 #define GPIO_PINS_5                      0x0020 /*!< gpio pins number 5 */
  57 #define GPIO_PINS_6                      0x0040 /*!< gpio pins number 6 */
  58 #define GPIO_PINS_7                      0x0080 /*!< gpio pins number 7 */
  59 #define GPIO_PINS_8                      0x0100 /*!< gpio pins number 8 */
  60 #define GPIO_PINS_9                      0x0200 /*!< gpio pins number 9 */
  61 #define GPIO_PINS_10                     0x0400 /*!< gpio pins number 10 */
  62 #define GPIO_PINS_11                     0x0800 /*!< gpio pins number 11 */
  63 #define GPIO_PINS_12                     0x1000 /*!< gpio pins number 12 */
  64 #define GPIO_PINS_13                     0x2000 /*!< gpio pins number 13 */
  65 #define GPIO_PINS_14                     0x4000 /*!< gpio pins number 14 */
  66 #define GPIO_PINS_15                     0x8000 /*!< gpio pins number 15 */
  67 #define GPIO_PINS_ALL                    0xFFFF /*!< gpio all pins */
  68
  69 /**
  70   * @}
  71   */
  72
  73 /** @defgroup GPIO_exported_types
  74   * @{
  75   */
  76
  77 /**
  78   * @brief gpio mode select
  79   */
  80 typedef enum
  81 {
  82   GPIO_MODE_INPUT                        = 0x00, /*!< gpio input mode */
  83   GPIO_MODE_OUTPUT                       = 0x01, /*!< gpio output mode */
  84   GPIO_MODE_MUX                          = 0x02, /*!< gpio mux function mode */
  85   GPIO_MODE_ANALOG                       = 0x03  /*!< gpio analog in/out mode */
  86 } gpio_mode_type;
  87
  88 /**
  89   * @brief gpio output drive strength select
  90   */
  91 typedef enum
  92 {
  93   GPIO_DRIVE_STRENGTH_STRONGER           = 0x01, /*!< stronger sourcing/sinking strength */
  94   GPIO_DRIVE_STRENGTH_MODERATE           = 0x02  /*!< moderate sourcing/sinking strength */
  95 } gpio_drive_type;
  96
  97 /**
  98   * @brief gpio output type
  99   */
 100 typedef enum
 101 {
 102   GPIO_OUTPUT_PUSH_PULL                  = 0x00, /*!< output push-pull */
 103   GPIO_OUTPUT_OPEN_DRAIN                 = 0x01  /*!< output open-drain */
 104 } gpio_output_type;
 105
 106 /**
 107   * @brief gpio pull type
 108   */
 109 typedef enum
 110 {
 111   GPIO_PULL_NONE                         = 0x00, /*!< floating for input, no pull for output */
 112   GPIO_PULL_UP                           = 0x01, /*!< pull-up */
 113   GPIO_PULL_DOWN                         = 0x02  /*!< pull-down */
 114 } gpio_pull_type;
 115
 116 /**
 117   * @brief gpio init type
 118   */
 119 typedef struct
 120 {
 121   uint32_t                               gpio_pins;            /*!< pins number selection */
 122   gpio_output_type                       gpio_out_type;        /*!< output type selection */
 123   gpio_pull_type                         gpio_pull;            /*!< pull type selection */
 124   gpio_mode_type                         gpio_mode;            /*!< mode selection */
 125   gpio_drive_type                        gpio_drive_strength;  /*!< drive strength selection */
 126 } gpio_init_type;
 127
 128 /**
 129   * @brief gpio pins source type
 130   */
 131 typedef enum
 132 {
 133   GPIO_PINS_SOURCE0                      = 0x00, /*!< gpio pins source number 0 */
 134   GPIO_PINS_SOURCE1                      = 0x01, /*!< gpio pins source number 1 */
 135   GPIO_PINS_SOURCE2                      = 0x02, /*!< gpio pins source number 2 */
 136   GPIO_PINS_SOURCE3                      = 0x03, /*!< gpio pins source number 3 */
 137   GPIO_PINS_SOURCE4                      = 0x04, /*!< gpio pins source number 4 */
 138   GPIO_PINS_SOURCE5                      = 0x05, /*!< gpio pins source number 5 */
 139   GPIO_PINS_SOURCE6                      = 0x06, /*!< gpio pins source number 6 */
 140   GPIO_PINS_SOURCE7                      = 0x07, /*!< gpio pins source number 7 */
 141   GPIO_PINS_SOURCE8                      = 0x08, /*!< gpio pins source number 8 */
 142   GPIO_PINS_SOURCE9                      = 0x09, /*!< gpio pins source number 9 */
 143   GPIO_PINS_SOURCE10                     = 0x0A, /*!< gpio pins source number 10 */
 144   GPIO_PINS_SOURCE11                     = 0x0B, /*!< gpio pins source number 11 */
 145   GPIO_PINS_SOURCE12                     = 0x0C, /*!< gpio pins source number 12 */
 146   GPIO_PINS_SOURCE13                     = 0x0D, /*!< gpio pins source number 13 */
 147   GPIO_PINS_SOURCE14                     = 0x0E, /*!< gpio pins source number 14 */
 148   GPIO_PINS_SOURCE15                     = 0x0F  /*!< gpio pins source number 15 */
 149 } gpio_pins_source_type;
 150
 151 /**
 152   * @brief  gpio muxing function selection type
 153   */
 154 typedef enum
 155 {
 156   GPIO_MUX_0                             = 0x00, /*!< gpio muxing function selection 0 */
 157   GPIO_MUX_1                             = 0x01, /*!< gpio muxing function selection 1 */
 158   GPIO_MUX_2                             = 0x02, /*!< gpio muxing function selection 2 */
 159   GPIO_MUX_3                             = 0x03, /*!< gpio muxing function selection 3 */
 160   GPIO_MUX_4                             = 0x04, /*!< gpio muxing function selection 4 */
 161   GPIO_MUX_5                             = 0x05, /*!< gpio muxing function selection 5 */
 162   GPIO_MUX_6                             = 0x06, /*!< gpio muxing function selection 6 */
 163   GPIO_MUX_7                             = 0x07, /*!< gpio muxing function selection 7 */
 164   GPIO_MUX_8                             = 0x08, /*!< gpio muxing function selection 8 */
 165   GPIO_MUX_9                             = 0x09, /*!< gpio muxing function selection 9 */
 166   GPIO_MUX_10                            = 0x0A, /*!< gpio muxing function selection 10 */
 167   GPIO_MUX_11                            = 0x0B, /*!< gpio muxing function selection 11 */
 168   GPIO_MUX_12                            = 0x0C, /*!< gpio muxing function selection 12 */
 169   GPIO_MUX_13                            = 0x0D, /*!< gpio muxing function selection 13 */
 170   GPIO_MUX_14                            = 0x0E, /*!< gpio muxing function selection 14 */
 171   GPIO_MUX_15                            = 0x0F  /*!< gpio muxing function selection 15 */
 172 } gpio_mux_sel_type;
 173
 174 /**
 175   * @brief type define gpio register all
 176   */
 177 typedef struct
 178 {
 179   /**
 180     * @brief gpio mode register, offset:0x00
 181     */
 182   union
 183   {
 184     __IO uint32_t cfgr;
 185     struct
 186     {
 187       __IO uint32_t iomc0                : 2; /* [1:0] */
 188       __IO uint32_t iomc1                : 2; /* [3:2] */
 189       __IO uint32_t iomc2                : 2; /* [5:4] */
 190       __IO uint32_t iomc3                : 2; /* [7:6] */
 191       __IO uint32_t iomc4                : 2; /* [9:8] */
 192       __IO uint32_t iomc5                : 2; /* [11:10] */
 193       __IO uint32_t iomc6                : 2; /* [13:12] */
 194       __IO uint32_t iomc7                : 2; /* [15:14] */
 195       __IO uint32_t iomc8                : 2; /* [17:16] */
 196       __IO uint32_t iomc9                : 2; /* [19:18] */
 197       __IO uint32_t iomc10               : 2; /* [21:20] */
 198       __IO uint32_t iomc11               : 2; /* [23:22] */
 199       __IO uint32_t iomc12               : 2; /* [25:24] */
 200       __IO uint32_t iomc13               : 2; /* [27:26] */
 201       __IO uint32_t iomc14               : 2; /* [29:28] */
 202       __IO uint32_t iomc15               : 2; /* [31:30] */
 203     } cfgr_bit;
 204   };
 205
 206   /**
 207     * @brief gpio output type register, offset:0x04
 208     */
 209   union
 210   {
 211     __IO uint32_t omode;
 212     struct
 213     {
 214       __IO uint32_t om0                  : 1; /* [0] */
 215       __IO uint32_t om1                  : 1; /* [1] */
 216       __IO uint32_t om2                  : 1; /* [2] */
 217       __IO uint32_t om3                  : 1; /* [3] */
 218       __IO uint32_t om4                  : 1; /* [4] */
 219       __IO uint32_t om5                  : 1; /* [5] */
 220       __IO uint32_t om6                  : 1; /* [6] */
 221       __IO uint32_t om7                  : 1; /* [7] */
 222       __IO uint32_t om8                  : 1; /* [8] */
 223       __IO uint32_t om9                  : 1; /* [9] */
 224       __IO uint32_t om10                 : 1; /* [10] */
 225       __IO uint32_t om11                 : 1; /* [11] */
 226       __IO uint32_t om12                 : 1; /* [12] */
 227       __IO uint32_t om13                 : 1; /* [13] */
 228       __IO uint32_t om14                 : 1; /* [14] */
 229       __IO uint32_t om15                 : 1; /* [15] */
 230       __IO uint32_t reserved1            : 16;/* [31:16] */
 231     } omode_bit;
 232   };
 233
 234   /**
 235     * @brief gpio output driver register, offset:0x08
 236     */
 237   union
 238   {
 239     __IO uint32_t odrvr;
 240     struct
 241     {
 242       __IO uint32_t odrv0                : 2; /* [1:0] */
 243       __IO uint32_t odrv1                : 2; /* [3:2] */
 244       __IO uint32_t odrv2                : 2; /* [5:4] */
 245       __IO uint32_t odrv3                : 2; /* [7:6] */
 246       __IO uint32_t odrv4                : 2; /* [9:8] */
 247       __IO uint32_t odrv5                : 2; /* [11:10] */
 248       __IO uint32_t odrv6                : 2; /* [13:12] */
 249       __IO uint32_t odrv7                : 2; /* [15:14] */
 250       __IO uint32_t odrv8                : 2; /* [17:16] */
 251       __IO uint32_t odrv9                : 2; /* [19:18] */
 252       __IO uint32_t odrv10               : 2; /* [21:20] */
 253       __IO uint32_t odrv11               : 2; /* [23:22] */
 254       __IO uint32_t odrv12               : 2; /* [25:24] */
 255       __IO uint32_t odrv13               : 2; /* [27:26] */
 256       __IO uint32_t odrv14               : 2; /* [29:28] */
 257       __IO uint32_t odrv15               : 2; /* [31:30] */
 258     } odrvr_bit;
 259   };
 260
 261   /**
 262     * @brief gpio pull up/down register, offset:0x0C
 263     */
 264   union
 265   {
 266     __IO uint32_t pull;
 267     struct
 268     {
 269       __IO uint32_t pull0                : 2; /* [1:0] */
 270       __IO uint32_t pull1                : 2; /* [3:2] */
 271       __IO uint32_t pull2                : 2; /* [5:4] */
 272       __IO uint32_t pull3                : 2; /* [7:6] */
 273       __IO uint32_t pull4                : 2; /* [9:8] */
 274       __IO uint32_t pull5                : 2; /* [11:10] */
 275       __IO uint32_t pull6                : 2; /* [13:12] */
 276       __IO uint32_t pull7                : 2; /* [15:14] */
 277       __IO uint32_t pull8                : 2; /* [17:16] */
 278       __IO uint32_t pull9                : 2; /* [19:18] */
 279       __IO uint32_t pull10               : 2; /* [21:20] */
 280       __IO uint32_t pull11               : 2; /* [23:22] */
 281       __IO uint32_t pull12               : 2; /* [25:24] */
 282       __IO uint32_t pull13               : 2; /* [27:26] */
 283       __IO uint32_t pull14               : 2; /* [29:28] */
 284       __IO uint32_t pull15               : 2; /* [31:30] */
 285     } pull_bit;
 286   };
 287
 288   /**
 289     * @brief gpio input data register, offset:0x10
 290     */
 291   union
 292   {
 293     __IO uint32_t idt;
 294     struct
 295     {
 296       __IO uint32_t idt0                 : 1; /* [0] */
 297       __IO uint32_t idt1                 : 1; /* [1] */
 298       __IO uint32_t idt2                 : 1; /* [2] */
 299       __IO uint32_t idt3                 : 1; /* [3] */
 300       __IO uint32_t idt4                 : 1; /* [4] */
 301       __IO uint32_t idt5                 : 1; /* [5] */
 302       __IO uint32_t idt6                 : 1; /* [6] */
 303       __IO uint32_t idt7                 : 1; /* [7] */
 304       __IO uint32_t idt8                 : 1; /* [8] */
 305       __IO uint32_t idt9                 : 1; /* [9] */
 306       __IO uint32_t idt10                : 1; /* [10] */
 307       __IO uint32_t idt11                : 1; /* [11] */
 308       __IO uint32_t idt12                : 1; /* [12] */
 309       __IO uint32_t idt13                : 1; /* [13] */
 310       __IO uint32_t idt14                : 1; /* [14] */
 311       __IO uint32_t idt15                : 1; /* [15] */
 312       __IO uint32_t reserved1            : 16;/* [31:16] */
 313     } idt_bit;
 314   };
 315
 316   /**
 317     * @brief gpio output data register, offset:0x14
 318     */
 319   union
 320   {
 321     __IO uint32_t odt;
 322     struct
 323     {
 324       __IO uint32_t odt0                 : 1; /* [0] */
 325       __IO uint32_t odt1                 : 1; /* [1] */
 326       __IO uint32_t odt2                 : 1; /* [2] */
 327       __IO uint32_t odt3                 : 1; /* [3] */
 328       __IO uint32_t odt4                 : 1; /* [4] */
 329       __IO uint32_t odt5                 : 1; /* [5] */
 330       __IO uint32_t odt6                 : 1; /* [6] */
 331       __IO uint32_t odt7                 : 1; /* [7] */
 332       __IO uint32_t odt8                 : 1; /* [8] */
 333       __IO uint32_t odt9                 : 1; /* [9] */
 334       __IO uint32_t odt10                : 1; /* [10] */
 335       __IO uint32_t odt11                : 1; /* [11] */
 336       __IO uint32_t odt12                : 1; /* [12] */
 337       __IO uint32_t odt13                : 1; /* [13] */
 338       __IO uint32_t odt14                : 1; /* [14] */
 339       __IO uint32_t odt15                : 1; /* [15] */
 340       __IO uint32_t reserved1            : 16;/* [31:16] */
 341     } odt_bit;
 342   };
 343
 344   /**
 345     * @brief gpio scr register, offset:0x18
 346     */
 347   union
 348   {
 349     __IO uint32_t scr;
 350     struct
 351     {
 352       __IO uint32_t iosb0                : 1; /* [0] */
 353       __IO uint32_t iosb1                : 1; /* [1] */
 354       __IO uint32_t iosb2                : 1; /* [2] */
 355       __IO uint32_t iosb3                : 1; /* [3] */
 356       __IO uint32_t iosb4                : 1; /* [4] */
 357       __IO uint32_t iosb5                : 1; /* [5] */
 358       __IO uint32_t iosb6                : 1; /* [6] */
 359       __IO uint32_t iosb7                : 1; /* [7] */
 360       __IO uint32_t iosb8                : 1; /* [8] */
 361       __IO uint32_t iosb9                : 1; /* [9] */
 362       __IO uint32_t iosb10               : 1; /* [10] */
 363       __IO uint32_t iosb11               : 1; /* [11] */
 364       __IO uint32_t iosb12               : 1; /* [12] */
 365       __IO uint32_t iosb13               : 1; /* [13] */
 366       __IO uint32_t iosb14               : 1; /* [14] */
 367       __IO uint32_t iosb15               : 1; /* [15] */
 368       __IO uint32_t iocb0                : 1; /* [16] */
 369       __IO uint32_t iocb1                : 1; /* [17] */
 370       __IO uint32_t iocb2                : 1; /* [18] */
 371       __IO uint32_t iocb3                : 1; /* [19] */
 372       __IO uint32_t iocb4                : 1; /* [20] */
 373       __IO uint32_t iocb5                : 1; /* [21] */
 374       __IO uint32_t iocb6                : 1; /* [22] */
 375       __IO uint32_t iocb7                : 1; /* [23] */
 376       __IO uint32_t iocb8                : 1; /* [24] */
 377       __IO uint32_t iocb9                : 1; /* [25] */
 378       __IO uint32_t iocb10               : 1; /* [26] */
 379       __IO uint32_t iocb11               : 1; /* [27] */
 380       __IO uint32_t iocb12               : 1; /* [28] */
 381       __IO uint32_t iocb13               : 1; /* [29] */
 382       __IO uint32_t iocb14               : 1; /* [30] */
 383       __IO uint32_t iocb15               : 1; /* [31] */
 384     } scr_bit;
 385   };
 386
 387   /**
 388     * @brief gpio wpen register, offset:0x1C
 389     */
 390   union
 391   {
 392     __IO uint32_t wpr;
 393     struct
 394     {
 395       __IO uint32_t wpen0                : 1; /* [0] */
 396       __IO uint32_t wpen1                : 1; /* [1] */
 397       __IO uint32_t wpen2                : 1; /* [2] */
 398       __IO uint32_t wpen3                : 1; /* [3] */
 399       __IO uint32_t wpen4                : 1; /* [4] */
 400       __IO uint32_t wpen5                : 1; /* [5] */
 401       __IO uint32_t wpen6                : 1; /* [6] */
 402       __IO uint32_t wpen7                : 1; /* [7] */
 403       __IO uint32_t wpen8                : 1; /* [8] */
 404       __IO uint32_t wpen9                : 1; /* [9] */
 405       __IO uint32_t wpen10               : 1; /* [10] */
 406       __IO uint32_t wpen11               : 1; /* [11] */
 407       __IO uint32_t wpen12               : 1; /* [12] */
 408       __IO uint32_t wpen13               : 1; /* [13] */
 409       __IO uint32_t wpen14               : 1; /* [14] */
 410       __IO uint32_t wpen15               : 1; /* [15] */
 411       __IO uint32_t wpseq                : 1; /* [16] */
 412       __IO uint32_t reserved1            : 15;/* [31:17] */
 413     } wpr_bit;
 414   };
 415
 416   /**
 417     * @brief gpio muxl register, offset:0x20
 418     */
 419   union
 420   {
 421     __IO uint32_t muxl;
 422     struct
 423     {
 424       __IO uint32_t muxl0                : 4; /* [3:0] */
 425       __IO uint32_t muxl1                : 4; /* [7:4] */
 426       __IO uint32_t muxl2                : 4; /* [11:8] */
 427       __IO uint32_t muxl3                : 4; /* [15:12] */
 428       __IO uint32_t muxl4                : 4; /* [19:16] */
 429       __IO uint32_t muxl5                : 4; /* [23:20] */
 430       __IO uint32_t muxl6                : 4; /* [27:24] */
 431       __IO uint32_t muxl7                : 4; /* [31:28] */
 432     } muxl_bit;
 433   };
 434
 435   /**
 436     * @brief gpio muxh register, offset:0x24
 437     */
 438   union
 439   {
 440     __IO uint32_t muxh;
 441     struct
 442     {
 443       __IO uint32_t muxh8                : 4; /* [3:0] */
 444       __IO uint32_t muxh9                : 4; /* [7:4] */
 445       __IO uint32_t muxh10               : 4; /* [11:8] */
 446       __IO uint32_t muxh11               : 4; /* [15:12] */
 447       __IO uint32_t muxh12               : 4; /* [19:16] */
 448       __IO uint32_t muxh13               : 4; /* [23:20] */
 449       __IO uint32_t muxh14               : 4; /* [27:24] */
 450       __IO uint32_t muxh15               : 4; /* [31:28] */
 451     } muxh_bit;
 452   };
 453
 454   /**
 455     * @brief gpio clr register, offset:0x28
 456     */
 457   union
 458   {
 459     __IO uint32_t clr;
 460     struct
 461     {
 462       __IO uint32_t iocb0                : 1; /* [0] */
 463       __IO uint32_t iocb1                : 1; /* [1] */
 464       __IO uint32_t iocb2                : 1; /* [2] */
 465       __IO uint32_t iocb3                : 1; /* [3] */
 466       __IO uint32_t iocb4                : 1; /* [4] */
 467       __IO uint32_t iocb5                : 1; /* [5] */
 468       __IO uint32_t iocb6                : 1; /* [6] */
 469       __IO uint32_t iocb7                : 1; /* [7] */
 470       __IO uint32_t iocb8                : 1; /* [8] */
 471       __IO uint32_t iocb9                : 1; /* [9] */
 472       __IO uint32_t iocb10               : 1; /* [10] */
 473       __IO uint32_t iocb11               : 1; /* [11] */
 474       __IO uint32_t iocb12               : 1; /* [12] */
 475       __IO uint32_t iocb13               : 1; /* [13] */
 476       __IO uint32_t iocb14               : 1; /* [14] */
 477       __IO uint32_t iocb15               : 1; /* [15] */
 478       __IO uint32_t reserved1            : 16;/* [31:16] */
 479     } clr_bit;
 480   };
 481
 482   /**
 483     * @brief gpio reserved1 register, offset:0x2C~0x38
 484     */
 485   __IO uint32_t reserved1[4];
 486
 487   /**
 488     * @brief gpio hdrv register, offset:0x3C
 489     */
 490   union
 491   {
 492     __IO uint32_t hdrv;
 493     struct
 494     {
 495       __IO uint32_t hdrv0                : 1; /* [0] */
 496       __IO uint32_t hdrv1                : 1; /* [1] */
 497       __IO uint32_t hdrv2                : 1; /* [2] */
 498       __IO uint32_t hdrv3                : 1; /* [3] */
 499       __IO uint32_t hdrv4                : 1; /* [4] */
 500       __IO uint32_t hdrv5                : 1; /* [5] */
 501       __IO uint32_t hdrv6                : 1; /* [6] */
 502       __IO uint32_t hdrv7                : 1; /* [7] */
 503       __IO uint32_t hdrv8                : 1; /* [8] */
 504       __IO uint32_t hdrv9                : 1; /* [9] */
 505       __IO uint32_t hdrv10               : 1; /* [10] */
 506       __IO uint32_t hdrv11               : 1; /* [11] */
 507       __IO uint32_t hdrv12               : 1; /* [12] */
 508       __IO uint32_t hdrv13               : 1; /* [13] */
 509       __IO uint32_t hdrv14               : 1; /* [14] */
 510       __IO uint32_t hdrv15               : 1; /* [15] */
 511       __IO uint32_t reserved1            : 16;/* [31:16] */
 512     } hdrv_bit;
 513   };
 514
 515 } gpio_type;
 516
 517 /**
 518   * @}
 519   */
 520
 521 #define GPIOA                            ((gpio_type *) GPIOA_BASE)
 522 #define GPIOB                            ((gpio_type *) GPIOB_BASE)
 523 #define GPIOC                            ((gpio_type *) GPIOC_BASE)
 524 #define GPIOD                            ((gpio_type *) GPIOD_BASE)
 525 #define GPIOE                            ((gpio_type *) GPIOE_BASE)
 526 #define GPIOF                            ((gpio_type *) GPIOF_BASE)
 527 #define GPIOG                            ((gpio_type *) GPIOG_BASE)
 528 #define GPIOH                            ((gpio_type *) GPIOH_BASE)
 529
 530 /** @defgroup GPIO_exported_functions
 531   * @{
 532   */
 533
 534 void gpio_reset(gpio_type *gpio_x);
 535 void gpio_init(gpio_type *gpio_x, gpio_init_type *gpio_init_struct);
 536 void gpio_default_para_init(gpio_init_type *gpio_init_struct);
 537 flag_status gpio_input_data_bit_read(gpio_type *gpio_x, uint16_t pins);
 538 uint16_t gpio_input_data_read(gpio_type *gpio_x);
 539 flag_status gpio_output_data_bit_read(gpio_type *gpio_x, uint16_t pins);
 540 uint16_t gpio_output_data_read(gpio_type *gpio_x);
 541 void gpio_bits_set(gpio_type *gpio_x, uint16_t pins);
 542 void gpio_bits_reset(gpio_type *gpio_x, uint16_t pins);
 543 void gpio_bits_write(gpio_type *gpio_x, uint16_t pins, confirm_state bit_state);
 544 void gpio_port_write(gpio_type *gpio_x, uint16_t port_value);
 545 void gpio_pin_wp_config(gpio_type *gpio_x, uint16_t pins);
 546 void gpio_pins_huge_driven_config(gpio_type *gpio_x, uint16_t pins, confirm_state new_state);
 547 void gpio_pin_mux_config(gpio_type *gpio_x, gpio_pins_source_type gpio_pin_source, gpio_mux_sel_type gpio_mux);
 548
 549 /**
 550   * @}
 551   */
 552
 553 /**
 554   * @}
 555   */
 556
 557 /**
 558   * @}
 559   */
 560
 561 #ifdef __cplusplus
 562 }
 563 #endif
 564
 565 #endif