lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_i2c.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_i2c.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 i2c header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_I2C_H
  29 #define __AT32F435_437_I2C_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup I2C
  44   * @{
  45   */
  46
  47 /**
  48   * @brief maximum number of single transfers
  49   */
  50 #define MAX_TRANSFER_CNT                 255 /*!< maximum number of single transfers */
  51
  52 /** @defgroup I2C_interrupts_definition
  53   * @brief i2c interrupt
  54   * @{
  55   */
  56
  57 #define I2C_TD_INT                       ((uint32_t)0x00000002) /*!< i2c transmit data interrupt */
  58 #define I2C_RD_INT                       ((uint32_t)0x00000004) /*!< i2c receive data interrupt */
  59 #define I2C_ADDR_INT                     ((uint32_t)0x00000008) /*!< i2c address match interrupt */
  60 #define I2C_ACKFIAL_INT                  ((uint32_t)0x00000010) /*!< i2c ack fail interrupt */
  61 #define I2C_STOP_INT                     ((uint32_t)0x00000020) /*!< i2c stop detect interrupt */
  62 #define I2C_TDC_INT                      ((uint32_t)0x00000040) /*!< i2c transmit data complete interrupt */
  63 #define I2C_ERR_INT                      ((uint32_t)0x00000080) /*!< i2c bus error interrupt */
  64
  65 /**
  66   * @}
  67   */
  68
  69 /** @defgroup I2C_flags_definition
  70   * @brief i2c flag
  71   * @{
  72   */
  73
  74 #define  I2C_TDBE_FLAG                   ((uint32_t)0x00000001) /*!< i2c transmit data buffer empty flag */
  75 #define  I2C_TDIS_FLAG                   ((uint32_t)0x00000002) /*!< i2c send interrupt status */
  76 #define  I2C_RDBF_FLAG                   ((uint32_t)0x00000004) /*!< i2c receive data buffer full flag */
  77 #define  I2C_ADDRF_FLAG                  ((uint32_t)0x00000008) /*!< i2c 0~7 bit address match flag */
  78 #define  I2C_ACKFAIL_FLAG                ((uint32_t)0x00000010) /*!< i2c acknowledge failure flag */
  79 #define  I2C_STOPF_FLAG                  ((uint32_t)0x00000020) /*!< i2c stop condition generation complete flag */
  80 #define  I2C_TDC_FLAG                    ((uint32_t)0x00000040) /*!< i2c transmit data complete flag */
  81 #define  I2C_TCRLD_FLAG                  ((uint32_t)0x00000080) /*!< i2c transmission is complete, waiting to load data */
  82 #define  I2C_BUSERR_FLAG                 ((uint32_t)0x00000100) /*!< i2c bus error flag */
  83 #define  I2C_ARLOST_FLAG                 ((uint32_t)0x00000200) /*!< i2c arbitration lost flag */
  84 #define  I2C_OUF_FLAG                    ((uint32_t)0x00000400) /*!< i2c overflow or underflow flag */
  85 #define  I2C_PECERR_FLAG                 ((uint32_t)0x00000800) /*!< i2c pec receive error flag */
  86 #define  I2C_TMOUT_FLAG                  ((uint32_t)0x00001000) /*!< i2c smbus timeout flag */
  87 #define  I2C_ALERTF_FLAG                 ((uint32_t)0x00002000) /*!< i2c smbus alert flag */
  88 #define  I2C_BUSYF_FLAG                  ((uint32_t)0x00008000) /*!< i2c bus busy flag transmission mode */
  89 #define  I2C_SDIR_FLAG                   ((uint32_t)0x00010000) /*!< i2c slave data transmit direction */
  90
  91 /**
  92   * @}
  93   */
  94
  95 /** @defgroup I2C_exported_types
  96   * @{
  97   */
  98
  99 /**
 100   * @brief i2c smbus mode set
 101   */
 102 typedef enum
 103 {
 104   I2C_SMBUS_MODE_DEVICE                  = 0x00, /*!< smbus device mode */
 105   I2C_SMBUS_MODE_HOST                    = 0x01  /*!< smbus host mode */
 106 } i2c_smbus_mode_type;
 107
 108 /**
 109   * @brief i2c address mode
 110   */
 111 typedef enum
 112 {
 113   I2C_ADDRESS_MODE_7BIT                  = 0x00, /*!< 7bit address mode */
 114   I2C_ADDRESS_MODE_10BIT                 = 0x01  /*!< 10bit address mode */
 115 } i2c_address_mode_type;
 116
 117 /**
 118   * @brief i2c transfer direction
 119   */
 120 typedef enum
 121 {
 122   I2C_DIR_TRANSMIT                       = 0x00, /*!< master request a write transfer */
 123   I2C_DIR_RECEIVE                        = 0x01  /*!< master request a read transfer */
 124 } i2c_transfer_dir_type;
 125
 126 /**
 127   * @brief i2c dma requests direction
 128   */
 129 typedef enum
 130 {
 131   I2C_DMA_REQUEST_TX                     = 0x00, /*!< dma transmit request */
 132   I2C_DMA_REQUEST_RX                     = 0x01  /*!< dma receive request */
 133 } i2c_dma_request_type;
 134
 135 /**
 136   * @brief i2c smbus alert pin set
 137   */
 138 typedef enum
 139 {
 140   I2C_SMBUS_ALERT_HIGH                   = 0x00, /*!< smbus alert pin set high */
 141   I2C_SMBUS_ALERT_LOW                    = 0x01  /*!< smbus alert pin set low */
 142 } i2c_smbus_alert_set_type;
 143
 144 /**
 145   * @brief i2c clock timeout detection mode
 146   */
 147 typedef enum
 148 {
 149   I2C_TIMEOUT_DETCET_LOW                 = 0x00, /*!< detect low level timeout */
 150   I2C_TIMEOUT_DETCET_HIGH                = 0x01  /*!< detect high level timeout */
 151 } i2c_timeout_detcet_type;
 152
 153 /**
 154   * @brief i2c own address2 mask
 155   */
 156 typedef enum
 157 {
 158   I2C_ADDR2_NOMASK                       = 0x00, /*!< compare bit      [7:1] */
 159   I2C_ADDR2_MASK01                       = 0x01, /*!< only compare bit [7:2] */
 160   I2C_ADDR2_MASK02                       = 0x02, /*!< only compare bit [7:2] */
 161   I2C_ADDR2_MASK03                       = 0x03, /*!< only compare bit [7:3] */
 162   I2C_ADDR2_MASK04                       = 0x04, /*!< only compare bit [7:4] */
 163   I2C_ADDR2_MASK05                       = 0x05, /*!< only compare bit [7:5] */
 164   I2C_ADDR2_MASK06                       = 0x06, /*!< only compare bit [7:6] */
 165   I2C_ADDR2_MASK07                       = 0x07  /*!< only compare bit [7] */
 166 } i2c_addr2_mask_type;
 167
 168 /**
 169   * @brief i2c reload end mode
 170   */
 171 typedef enum
 172 {
 173   I2C_AUTO_STOP_MODE                     = 0x02000000, /*!< auto generate stop mode */
 174   I2C_SOFT_STOP_MODE                     = 0x00000000, /*!< soft generate stop mode */
 175   I2C_RELOAD_MODE                        = 0x01000000  /*!< reload mode */
 176 } i2c_reload_stop_mode_type;
 177
 178 /**
 179   * @brief i2c start mode
 180   */
 181 typedef enum
 182 {
 183   I2C_WITHOUT_START                      = 0x00000000, /*!< transfer data without start condition */
 184   I2C_GEN_START_READ                     = 0x00002400, /*!< read data and generate start */
 185   I2C_GEN_START_WRITE                    = 0x00002000  /*!< send data and generate start */
 186 } i2c_start_mode_type;
 187
 188 /**
 189   * @brief type define i2c register all
 190   */
 191 typedef struct
 192 {
 193   /**
 194     * @brief i2c ctrl1 register, offset:0x00
 195     */
 196   union
 197   {
 198     __IO uint32_t ctrl1;
 199     struct
 200     {
 201       __IO uint32_t i2cen                : 1; /* [0] */
 202       __IO uint32_t tdien                : 1; /* [1] */
 203       __IO uint32_t rdien                : 1; /* [2] */
 204       __IO uint32_t addrien              : 1; /* [3] */
 205       __IO uint32_t ackfailien           : 1; /* [4] */
 206       __IO uint32_t stopien              : 1; /* [5] */
 207       __IO uint32_t tdcien               : 1; /* [6] */
 208       __IO uint32_t errien               : 1; /* [7] */
 209       __IO uint32_t dflt                 : 4; /* [11:8] */
 210       __IO uint32_t reserved1            : 2; /* [13:12] */
 211       __IO uint32_t dmaten               : 1; /* [14] */
 212       __IO uint32_t dmaren               : 1; /* [15] */
 213       __IO uint32_t sctrl                : 1; /* [16] */
 214       __IO uint32_t stretch              : 1; /* [17] */
 215       __IO uint32_t reserved2            : 1; /* [18] */
 216       __IO uint32_t gcaen                : 1; /* [19] */
 217       __IO uint32_t haddren              : 1; /* [20] */
 218       __IO uint32_t devaddren            : 1; /* [21] */
 219       __IO uint32_t smbalert             : 1; /* [22] */
 220       __IO uint32_t pecen                : 1; /* [23] */
 221       __IO uint32_t reserved3            : 8; /* [31:24] */
 222     } ctrl1_bit;
 223   };
 224
 225   /**
 226     * @brief i2c ctrl2 register, offset:0x04
 227     */
 228   union
 229   {
 230     __IO uint32_t ctrl2;
 231     struct
 232     {
 233       __IO uint32_t saddr                : 10;/* [9:0] */
 234       __IO uint32_t dir                  : 1; /* [10] */
 235       __IO uint32_t addr10               : 1; /* [11] */
 236       __IO uint32_t readh10              : 1; /* [12] */
 237       __IO uint32_t genstart             : 1; /* [13] */
 238       __IO uint32_t genstop              : 1; /* [14] */
 239       __IO uint32_t nacken               : 1; /* [15] */
 240       __IO uint32_t cnt                  : 8; /* [23:16] */
 241       __IO uint32_t rlden                : 1; /* [24] */
 242       __IO uint32_t astopen              : 1; /* [25] */
 243       __IO uint32_t pecten               : 1; /* [26] */
 244       __IO uint32_t reserved1            : 5; /* [31:27] */
 245     } ctrl2_bit;
 246   };
 247
 248   /**
 249     * @brief i2c oaddr1 register, offset:0x08
 250     */
 251   union
 252   {
 253     __IO uint32_t oaddr1;
 254     struct
 255     {
 256       __IO uint32_t addr1                : 10;/* [9:0] */
 257       __IO uint32_t addr1mode            : 1; /* [10] */
 258       __IO uint32_t reserved1            : 4; /* [14:11] */
 259       __IO uint32_t addr1en              : 1; /* [15] */
 260       __IO uint32_t reserved2            : 16;/* [31:16] */
 261     } oaddr1_bit;
 262   };
 263
 264   /**
 265     * @brief i2c oaddr2 register, offset:0x0c
 266     */
 267   union
 268   {
 269     __IO uint32_t oaddr2;
 270     struct
 271     {
 272       __IO uint32_t reserved1            : 1; /* [0] */
 273       __IO uint32_t addr2                : 7; /* [7:1] */
 274       __IO uint32_t addr2mask            : 3; /* [10:8] */
 275       __IO uint32_t reserved2            : 4; /* [14:11] */
 276       __IO uint32_t addr2en              : 1; /* [15] */
 277       __IO uint32_t reserved3            : 16;/* [31:16] */
 278     } oaddr2_bit;
 279   };
 280
 281   /**
 282     * @brief i2c clkctrl register, offset:0x10
 283     */
 284   union
 285   {
 286     __IO uint32_t clkctrl;
 287     struct
 288     {
 289       __IO uint32_t scll                 : 8; /* [7:0] */
 290       __IO uint32_t sclh                 : 8; /* [15:8] */
 291       __IO uint32_t sdad                 : 4; /* [19:16] */
 292       __IO uint32_t scld                 : 4; /* [23:20] */
 293       __IO uint32_t divh                 : 4; /* [27:24] */
 294       __IO uint32_t divl                 : 4; /* [31:28] */
 295     } clkctrl_bit;
 296   };
 297
 298   /**
 299     * @brief i2c timeout register, offset:0x14
 300     */
 301   union
 302   {
 303     __IO uint32_t timeout;
 304     struct
 305     {
 306       __IO uint32_t totime               : 12;/* [11:0] */
 307       __IO uint32_t tomode               : 1; /* [12] */
 308       __IO uint32_t reserved1            : 2; /* [14:13] */
 309       __IO uint32_t toen                 : 1; /* [15] */
 310       __IO uint32_t exttime              : 12;/* [27:16] */
 311       __IO uint32_t reserved2            : 3; /* [30:28] */
 312       __IO uint32_t exten                : 1; /* [31] */
 313     } timeout_bit;
 314   };
 315
 316   /**
 317     * @brief i2c sts register, offset:0x18
 318     */
 319   union
 320   {
 321     __IO uint32_t sts;
 322     struct
 323     {
 324       __IO uint32_t tdbe                 : 1; /* [0] */
 325       __IO uint32_t tdis                 : 1; /* [1] */
 326       __IO uint32_t rdbf                 : 1; /* [2] */
 327       __IO uint32_t addrf                : 1; /* [3] */
 328       __IO uint32_t ackfail              : 1; /* [4] */
 329       __IO uint32_t stopf                : 1; /* [5] */
 330       __IO uint32_t tdc                  : 1; /* [6] */
 331       __IO uint32_t tcrld                : 1; /* [7] */
 332       __IO uint32_t buserr               : 1; /* [8] */
 333       __IO uint32_t arlost               : 1; /* [9] */
 334       __IO uint32_t ouf                  : 1; /* [10] */
 335       __IO uint32_t pecerr               : 1; /* [11] */
 336       __IO uint32_t tmout                : 1; /* [12] */
 337       __IO uint32_t alertf               : 1; /* [13] */
 338       __IO uint32_t reserved1            : 1; /* [14] */
 339       __IO uint32_t busyf                : 1; /* [15] */
 340       __IO uint32_t sdir                 : 1; /* [16] */
 341       __IO uint32_t addr                 : 7; /* [23:17] */
 342       __IO uint32_t reserved2            : 8; /* [31:24] */
 343     } sts_bit;
 344   };
 345
 346   /**
 347     * @brief i2c clr register, offset:0x1c
 348     */
 349   union
 350   {
 351     __IO uint32_t clr;
 352     struct
 353     {
 354       __IO uint32_t reserved1            : 3; /* [2:0] */
 355       __IO uint32_t addrc                : 1; /* [3] */
 356       __IO uint32_t ackfailc             : 1; /* [4] */
 357       __IO uint32_t stopc                : 1; /* [5] */
 358       __IO uint32_t reserved2            : 2; /* [6:7] */
 359       __IO uint32_t buserrc              : 1; /* [8] */
 360       __IO uint32_t arlostc              : 1; /* [9] */
 361       __IO uint32_t oufc                 : 1; /* [10] */
 362       __IO uint32_t pecerrc              : 1; /* [11] */
 363       __IO uint32_t tmoutc               : 1; /* [12] */
 364       __IO uint32_t alertc               : 1; /* [13] */
 365       __IO uint32_t reserved3            : 18;/* [31:14] */
 366     } clr_bit;
 367   };
 368
 369   /**
 370     * @brief i2c pec register, offset:0x20
 371     */
 372   union
 373   {
 374     __IO uint32_t pec;
 375     struct
 376     {
 377       __IO uint32_t pecval               : 8; /* [7:0] */
 378       __IO uint32_t reserved1            : 24;/* [31:8] */
 379     } pec_bit;
 380   };
 381
 382   /**
 383     * @brief i2c rxdt register, offset:0x20
 384     */
 385   union
 386   {
 387     __IO uint32_t rxdt;
 388     struct
 389     {
 390       __IO uint32_t dt                   : 8; /* [7:0] */
 391       __IO uint32_t reserved1            : 24;/* [31:8] */
 392     } rxdt_bit;
 393   };
 394
 395   /**
 396     * @brief i2c txdt register, offset:0x20
 397     */
 398   union
 399   {
 400     __IO uint32_t txdt;
 401     struct
 402     {
 403       __IO uint32_t dt                   : 8; /* [7:0] */
 404       __IO uint32_t reserved1            : 24;/* [31:8] */
 405     } txdt_bit;
 406   };
 407
 408 } i2c_type;
 409
 410 /**
 411   * @}
 412   */
 413
 414 #define I2C1                             ((i2c_type *) I2C1_BASE)
 415 #define I2C2                             ((i2c_type *) I2C2_BASE)
 416 #define I2C3                             ((i2c_type *) I2C3_BASE)
 417
 418 /** @defgroup I2C_exported_functions
 419   * @{
 420   */
 421
 422 void i2c_reset(i2c_type *i2c_x);
 423 void i2c_init(i2c_type *i2c_x, uint8_t dfilters, uint32_t clk);
 424 void i2c_own_address1_set(i2c_type *i2c_x, i2c_address_mode_type mode, uint16_t address);
 425 void i2c_own_address2_set(i2c_type *i2c_x, uint8_t address, i2c_addr2_mask_type mask);
 426 void i2c_own_address2_enable(i2c_type *i2c_x, confirm_state new_state);
 427 void i2c_smbus_enable(i2c_type *i2c_x, i2c_smbus_mode_type mode, confirm_state new_state);
 428 void i2c_enable(i2c_type *i2c_x, confirm_state new_state);
 429 void i2c_clock_stretch_enable(i2c_type *i2c_x, confirm_state new_state);
 430 void i2c_ack_enable(i2c_type *i2c_x, confirm_state new_state);
 431 void i2c_addr10_mode_enable(i2c_type *i2c_x, confirm_state new_state);
 432 void i2c_transfer_addr_set(i2c_type *i2c_x, uint16_t address);
 433 uint16_t i2c_transfer_addr_get(i2c_type *i2c_x);
 434 void i2c_transfer_dir_set(i2c_type *i2c_x, i2c_transfer_dir_type i2c_direction);
 435 i2c_transfer_dir_type i2c_transfer_dir_get(i2c_type *i2c_x);
 436 uint8_t i2c_matched_addr_get(i2c_type *i2c_x);
 437 void i2c_auto_stop_enable(i2c_type *i2c_x, confirm_state new_state);
 438 void i2c_reload_enable(i2c_type *i2c_x, confirm_state new_state);
 439 void i2c_cnt_set(i2c_type *i2c_x, uint8_t cnt);
 440 void i2c_addr10_header_enable(i2c_type *i2c_x, confirm_state new_state);
 441 void i2c_general_call_enable(i2c_type *i2c_x, confirm_state new_state);
 442 void i2c_smbus_alert_set(i2c_type *i2c_x, i2c_smbus_alert_set_type level);
 443 void i2c_slave_data_ctrl_enable(i2c_type *i2c_x, confirm_state new_state);
 444 void i2c_pec_calculate_enable(i2c_type *i2c_x, confirm_state new_state);
 445 void i2c_pec_transmit_enable(i2c_type *i2c_x, confirm_state new_state);
 446 uint8_t i2c_pec_value_get(i2c_type *i2c_x);
 447 void i2c_timeout_set(i2c_type *i2c_x, uint16_t timeout);
 448 void i2c_timeout_detcet_set(i2c_type *i2c_x, i2c_timeout_detcet_type mode);
 449 void i2c_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
 450 void i2c_ext_timeout_set(i2c_type *i2c_x, uint16_t timeout);
 451 void i2c_ext_timeout_enable(i2c_type *i2c_x, confirm_state new_state);
 452 void i2c_interrupt_enable(i2c_type *i2c_x, uint32_t source, confirm_state new_state);
 453 flag_status i2c_interrupt_get(i2c_type *i2c_x, uint16_t source);
 454 void i2c_dma_enable(i2c_type *i2c_x, i2c_dma_request_type dma_req, confirm_state new_state);
 455 void i2c_transmit_set(i2c_type *i2c_x, uint16_t address, uint8_t cnt, i2c_reload_stop_mode_type rld_stop, i2c_start_mode_type start);
 456 void i2c_start_generate(i2c_type *i2c_x);
 457 void i2c_stop_generate(i2c_type *i2c_x);
 458 void i2c_data_send(i2c_type *i2c_x, uint8_t data);
 459 uint8_t i2c_data_receive(i2c_type *i2c_x);
 460 flag_status i2c_flag_get(i2c_type *i2c_x, uint32_t flag);
 461 void i2c_flag_clear(i2c_type *i2c_x, uint32_t flag);
 462
 463 /**
 464   * @}
 465   */
 466
 467 /**
 468   * @}
 469   */
 470
 471 /**
 472   * @}
 473   */
 474
 475 #ifdef __cplusplus
 476 }
 477 #endif
 478
 479 #endif