Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_misc.h
blobd965d02cc2aae1fa39dc501c63a155a834eefdc5
1 /**
2 **************************************************************************
3 * @file at32f435_437_misc.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 misc header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
24 **************************************************************************
27 /* define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_MISC_H
29 #define __AT32F435_437_MISC_H
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
36 /* includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
43 /** @addtogroup MISC
44 * @{
47 /** @defgroup MISC_vector_table_base_address
48 * @{
51 #define NVIC_VECTTAB_RAM ((uint32_t)0x20000000) /*!< nvic vector table based ram address */
52 #define NVIC_VECTTAB_FLASH ((uint32_t)0x08000000) /*!< nvic vector table based flash address */
54 /**
55 * @}
58 /** @defgroup MISC_exported_types
59 * @{
62 /**
63 * @brief nvic interrupt priority group
65 typedef enum
67 NVIC_PRIORITY_GROUP_0 = ((uint32_t)0x7), /*!< 0 bits for preemption priority, 4 bits for subpriority */
68 NVIC_PRIORITY_GROUP_1 = ((uint32_t)0x6), /*!< 1 bits for preemption priority, 3 bits for subpriority */
69 NVIC_PRIORITY_GROUP_2 = ((uint32_t)0x5), /*!< 2 bits for preemption priority, 2 bits for subpriority */
70 NVIC_PRIORITY_GROUP_3 = ((uint32_t)0x4), /*!< 3 bits for preemption priority, 1 bits for subpriority */
71 NVIC_PRIORITY_GROUP_4 = ((uint32_t)0x3) /*!< 4 bits for preemption priority, 0 bits for subpriority */
72 } nvic_priority_group_type;
74 /**
75 * @brief nvic low power mode
77 typedef enum
79 NVIC_LP_SLEEPONEXIT = 0x02, /*!< enable sleep-on-exit feature */
80 NVIC_LP_SLEEPDEEP = 0x04, /*!< enable sleep-deep output signal when entering sleep mode */
81 NVIC_LP_SEVONPEND = 0x10 /*!< send event on pending */
82 } nvic_lowpower_mode_type;
84 /**
85 * @brief systick clock source
87 typedef enum
89 SYSTICK_CLOCK_SOURCE_AHBCLK_DIV8 = ((uint32_t)0x00000000), /*!< systick clock source from core clock div8 */
90 SYSTICK_CLOCK_SOURCE_AHBCLK_NODIV = ((uint32_t)0x00000004) /*!< systick clock source from core clock */
91 } systick_clock_source_type;
93 /**
94 * @}
97 /** @defgroup MISC_exported_functions
98 * @{
101 void nvic_system_reset(void);
102 void nvic_irq_enable(IRQn_Type irqn, uint32_t preempt_priority, uint32_t sub_priority);
103 void nvic_irq_disable(IRQn_Type irqn);
104 void nvic_priority_group_config(nvic_priority_group_type priority_group);
105 void nvic_vector_table_set(uint32_t base, uint32_t offset);
106 void nvic_lowpower_mode_config(nvic_lowpower_mode_type lp_mode, confirm_state new_state);
107 void systick_clock_source_config(systick_clock_source_type source);
110 * @}
114 * @}
118 * @}
121 #ifdef __cplusplus
123 #endif
125 #endif