lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_scfg.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_scfg.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 system config header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_SCFG_H
  29 #define __AT32F435_437_SCFG_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup SCFG
  44   * @{
  45   */
  46
  47 #define SCFG_REG(value)                  PERIPH_REG(SCFG_BASE, value)
  48 #define SCFG_REG_BIT(value)              PERIPH_REG_BIT(value)
  49
  50 /** @defgroup SCFG_exported_types
  51   * @{
  52   */
  53
  54 /**
  55   * @brief scfg xmc addres mapping swap type
  56   */
  57 typedef enum
  58 {
  59   SCFG_XMC_SWAP_NONE                     = 0x00, /* no swap */
  60   SCFG_XMC_SWAP_MODE1                    = 0x01, /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000 */
  61   SCFG_XMC_SWAP_MODE2                    = 0x02, /* qspi2 0x80000000, nand3 0xB0000000 */
  62   SCFG_XMC_SWAP_MODE3                    = 0x03  /* sdram 0x60000000 and 0x70000000, nor psram sram nand2 0xC00000000 and 0xD0000000, qspi2 0x80000000, nand3 0xB0000000 */
  63 } scfg_xmc_swap_type;
  64
  65 /**
  66   * @brief scfg infrared modulation signal source selecting type
  67   */
  68 typedef enum
  69 {
  70   SCFG_IR_SOURCE_TMR10                   = 0x00, /* infrared signal source select tmr10 */
  71   SCFG_IR_SOURCE_USART1                  = 0x01, /* infrared signal source select usart1 */
  72   SCFG_IR_SOURCE_USART2                  = 0x02  /* infrared signal source select usart2 */
  73 } scfg_ir_source_type;
  74
  75 /**
  76   * @brief scfg infrared output polarity selecting type
  77   */
  78 typedef enum
  79 {
  80   SCFG_IR_POLARITY_NO_AFFECTE            = 0x00, /* infrared output polarity no affecte */
  81   SCFG_IR_POLARITY_REVERSE               = 0x01  /* infrared output polarity reverse */
  82 } scfg_ir_polarity_type;
  83
  84 /**
  85   * @brief scfg memory address mapping selecting type
  86   */
  87 typedef enum
  88 {
  89   SCFG_MEM_MAP_MAIN_MEMORY               = 0x00, /* 0x00000000 address mapping from main memory */
  90   SCFG_MEM_MAP_BOOT_MEMORY               = 0x01, /* 0x00000000 address mapping from boot memory */
  91   SCFG_MEM_MAP_XMC_BANK1                 = 0x02, /* 0x00000000 address mapping from xmc bank1 */
  92   SCFG_MEM_MAP_INTERNAL_SRAM             = 0x03, /* 0x00000000 address mapping from internal sram */
  93   SCFG_MEM_MAP_XMC_SDRAM_BANK1           = 0x04  /* 0x00000000 address mapping from xmc sdram bank1 */
  94 } scfg_mem_map_type;
  95
  96 /**
  97   * @brief scfg pin source type
  98   */
  99 typedef enum
 100 {
 101   SCFG_PINS_SOURCE0                      = 0x00,
 102   SCFG_PINS_SOURCE1                      = 0x01,
 103   SCFG_PINS_SOURCE2                      = 0x02,
 104   SCFG_PINS_SOURCE3                      = 0x03,
 105   SCFG_PINS_SOURCE4                      = 0x04,
 106   SCFG_PINS_SOURCE5                      = 0x05,
 107   SCFG_PINS_SOURCE6                      = 0x06,
 108   SCFG_PINS_SOURCE7                      = 0x07,
 109   SCFG_PINS_SOURCE8                      = 0x08,
 110   SCFG_PINS_SOURCE9                      = 0x09,
 111   SCFG_PINS_SOURCE10                     = 0x0A,
 112   SCFG_PINS_SOURCE11                     = 0x0B,
 113   SCFG_PINS_SOURCE12                     = 0x0C,
 114   SCFG_PINS_SOURCE13                     = 0x0D,
 115   SCFG_PINS_SOURCE14                     = 0x0E,
 116   SCFG_PINS_SOURCE15                     = 0x0F
 117 } scfg_pins_source_type;
 118
 119 /**
 120   * @brief gpio port source type
 121   */
 122 typedef enum
 123 {
 124   SCFG_PORT_SOURCE_GPIOA                 = 0x00,
 125   SCFG_PORT_SOURCE_GPIOB                 = 0x01,
 126   SCFG_PORT_SOURCE_GPIOC                 = 0x02,
 127   SCFG_PORT_SOURCE_GPIOD                 = 0x03,
 128   SCFG_PORT_SOURCE_GPIOE                 = 0x04,
 129   SCFG_PORT_SOURCE_GPIOF                 = 0x05,
 130   SCFG_PORT_SOURCE_GPIOG                 = 0x06,
 131   SCFG_PORT_SOURCE_GPIOH                 = 0x07
 132 } scfg_port_source_type;
 133
 134 /**
 135   * @brief scfg emac interface selecting type
 136   */
 137 typedef enum
 138 {
 139   SCFG_EMAC_SELECT_MII                   = 0x00, /* emac interface select mii mode */
 140   SCFG_EMAC_SELECT_RMII                  = 0x01  /* emac interface select rmii mode */
 141 } scfg_emac_interface_type;
 142
 143 /**
 144   * @brief scfg ultra high sourcing/sinking strength pins type
 145   */
 146 typedef enum
 147 {
 148   SCFG_ULTRA_DRIVEN_PB3                  = MAKE_VALUE(0x2C, 0),
 149   SCFG_ULTRA_DRIVEN_PB9                  = MAKE_VALUE(0x2C, 1),
 150   SCFG_ULTRA_DRIVEN_PB10                 = MAKE_VALUE(0x2C, 2),
 151   SCFG_ULTRA_DRIVEN_PD12                 = MAKE_VALUE(0x2C, 5),
 152   SCFG_ULTRA_DRIVEN_PD13                 = MAKE_VALUE(0x2C, 6),
 153   SCFG_ULTRA_DRIVEN_PD14                 = MAKE_VALUE(0x2C, 7),
 154   SCFG_ULTRA_DRIVEN_PD15                 = MAKE_VALUE(0x2C, 8),
 155   SCFG_ULTRA_DRIVEN_PF14                 = MAKE_VALUE(0x2C, 9),
 156   SCFG_ULTRA_DRIVEN_PF15                 = MAKE_VALUE(0x2C, 10)
 157 } scfg_ultra_driven_pins_type;
 158
 159 /**
 160   * @brief type define system config register all
 161   */
 162 typedef struct
 163 {
 164   /**
 165     * @brief scfg cfg1 register, offset:0x00
 166     */
 167   union
 168   {
 169     __IO uint32_t cfg1;
 170     struct
 171     {
 172       __IO uint32_t mem_map_sel          : 3; /* [2:0] */
 173       __IO uint32_t reserved1            : 2; /* [4:3] */
 174       __IO uint32_t ir_pol               : 1; /* [5] */
 175       __IO uint32_t ir_src_sel           : 2; /* [7:6] */
 176       __IO uint32_t reserved2            : 2; /* [9:8] */
 177       __IO uint32_t swap_xmc             : 2; /* [11:10] */
 178       __IO uint32_t reserved3            : 20;/* [31:12] */
 179     } cfg1_bit;
 180   };
 181
 182   /**
 183     * @brief scfg cfg2 register, offset:0x04
 184     */
 185   union
 186   {
 187     __IO uint32_t cfg2;
 188     struct
 189     {
 190       __IO uint32_t reserved1            : 23;/* [22:0] */
 191       __IO uint32_t mii_rmii_sel         : 1; /* [23] */
 192       __IO uint32_t reserved2            : 8; /* [31:24] */
 193     } cfg2_bit;
 194   };
 195
 196   /**
 197     * @brief scfg exintc1 register, offset:0x08
 198     */
 199   union
 200   {
 201     __IO uint32_t exintc1;
 202     struct
 203     {
 204       __IO uint32_t exint0               : 4; /* [3:0] */
 205       __IO uint32_t exint1               : 4; /* [7:4] */
 206       __IO uint32_t exint2               : 4; /* [11:8] */
 207       __IO uint32_t exint3               : 4; /* [15:12] */
 208       __IO uint32_t reserved1            : 16;/* [31:16] */
 209     } exintc1_bit;
 210   };
 211
 212   /**
 213     * @brief scfg exintc2 register, offset:0x0C
 214     */
 215   union
 216   {
 217     __IO uint32_t exintc2;
 218     struct
 219     {
 220       __IO uint32_t exint4               : 4; /* [3:0] */
 221       __IO uint32_t exint5               : 4; /* [7:4] */
 222       __IO uint32_t exint6               : 4; /* [11:8] */
 223       __IO uint32_t exint7               : 4; /* [15:12] */
 224       __IO uint32_t reserved1            : 16;/* [31:16] */
 225     } exintc2_bit;
 226   };
 227
 228   /**
 229     * @brief scfg exintc3 register, offset:0x10
 230     */
 231   union
 232   {
 233     __IO uint32_t exintc3;
 234     struct
 235     {
 236       __IO uint32_t exint8               : 4; /* [3:0] */
 237       __IO uint32_t exint9               : 4; /* [7:4] */
 238       __IO uint32_t exint10              : 4; /* [11:8] */
 239       __IO uint32_t exint11              : 4; /* [15:12] */
 240       __IO uint32_t reserved1            : 16;/* [31:16] */
 241     } exintc3_bit;
 242   };
 243
 244   /**
 245     * @brief scfg exintc4 register, offset:0x14
 246     */
 247   union
 248   {
 249     __IO uint32_t exintc4;
 250     struct
 251     {
 252       __IO uint32_t exint12              : 4; /* [3:0] */
 253       __IO uint32_t exint13              : 4; /* [7:4] */
 254       __IO uint32_t exint14              : 4; /* [11:8] */
 255       __IO uint32_t exint15              : 4; /* [15:12] */
 256       __IO uint32_t reserved1            : 16;/* [31:16] */
 257     } exintc4_bit;
 258   };
 259
 260   /**
 261     * @brief crm reserved1 register, offset:0x18~0x28
 262     */
 263   __IO uint32_t reserved1[5];
 264
 265   /**
 266     * @brief scfg uhdrv register, offset:0x2C
 267     */
 268   union
 269   {
 270     __IO uint32_t uhdrv;
 271     struct
 272     {
 273       __IO uint32_t pb3_uh               : 1; /* [0] */
 274       __IO uint32_t pb9_uh               : 1; /* [1] */
 275       __IO uint32_t pb10_uh              : 1; /* [2] */
 276       __IO uint32_t reserved1            : 2; /* [4:3] */
 277       __IO uint32_t pd12_uh              : 1; /* [5] */
 278       __IO uint32_t pd13_uh              : 1; /* [6] */
 279       __IO uint32_t pd14_uh              : 1; /* [7] */
 280       __IO uint32_t pd15_uh              : 1; /* [8] */
 281       __IO uint32_t pf14_uh              : 1; /* [9] */
 282       __IO uint32_t pf15_uh              : 1; /* [10] */
 283       __IO uint32_t reserved2            : 21;/* [31:11] */
 284     } uhdrv_bit;
 285   };
 286
 287 } scfg_type;
 288
 289 /**
 290   * @}
 291   */
 292
 293 #define SCFG                             ((scfg_type *) SCFG_BASE)
 294
 295 /** @defgroup SCFG_exported_functions
 296   * @{
 297   */
 298
 299 void scfg_reset(void);
 300 void scfg_xmc_mapping_swap_set(scfg_xmc_swap_type xmc_swap);
 301 void scfg_infrared_config(scfg_ir_source_type source, scfg_ir_polarity_type polarity);
 302 void scfg_mem_map_set(scfg_mem_map_type mem_map);
 303 void scfg_emac_interface_set(scfg_emac_interface_type mode);
 304 void scfg_exint_line_config(scfg_port_source_type port_source, scfg_pins_source_type pin_source);
 305 void scfg_pins_ultra_driven_enable(scfg_ultra_driven_pins_type value, confirm_state new_state);
 306
 307 /**
 308   * @}
 309   */
 310
 311 /**
 312   * @}
 313   */
 314
 315 /**
 316   * @}
 317   */
 318
 319 #ifdef __cplusplus
 320 }
 321 #endif
 322
 323 #endif