lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_sdio.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_sdio.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 sdio header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_SDIO_H
  29 #define __AT32F435_437_SDIO_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup SDIO
  44   * @{
  45   */
  46
  47 /** @defgroup SDIO_interrupts_definition
  48   * @brief sdio interrupt
  49   * @{
  50   */
  51
  52 #define SDIO_CMDFAIL_INT                 ((uint32_t)0x00000001) /*!< command response received check failed interrupt */
  53 #define SDIO_DTFAIL_INT                  ((uint32_t)0x00000002) /*!< data block sent/received check failed interrupt */
  54 #define SDIO_CMDTIMEOUT_INT              ((uint32_t)0x00000004) /*!< command response timerout interrupt */
  55 #define SDIO_DTTIMEOUT_INT               ((uint32_t)0x00000008) /*!< data timeout interrupt */
  56 #define SDIO_TXERRU_INT                  ((uint32_t)0x00000010) /*!< transmit underrun error interrupt */
  57 #define SDIO_RXERRO_INT                  ((uint32_t)0x00000020) /*!< received overrun error interrupt */
  58 #define SDIO_CMDRSPCMPL_INT              ((uint32_t)0x00000040) /*!< command response received interrupt */
  59 #define SDIO_CMDCMPL_INT                 ((uint32_t)0x00000080) /*!< command sent interrupt */
  60 #define SDIO_DTCMP_INT                   ((uint32_t)0x00000100) /*!< data sent interrupt */
  61 #define SDIO_SBITERR_INT                 ((uint32_t)0x00000200) /*!< start bit not detected on data bus interrupt */
  62 #define SDIO_DTBLKCMPL_INT               ((uint32_t)0x00000400) /*!< data block sent/received interrupt */
  63 #define SDIO_DOCMD_INT                   ((uint32_t)0x00000800) /*!< command transfer in progress interrupt */
  64 #define SDIO_DOTX_INT                    ((uint32_t)0x00001000) /*!< data transmit in progress interrupt */
  65 #define SDIO_DORX_INT                    ((uint32_t)0x00002000) /*!< data receive in progress interrupt */
  66 #define SDIO_TXBUFH_INT                  ((uint32_t)0x00004000) /*!< transmit buf half empty interrupt */
  67 #define SDIO_RXBUFH_INT                  ((uint32_t)0x00008000) /*!< receive buf half full interrupt */
  68 #define SDIO_TXBUFF_INT                  ((uint32_t)0x00010000) /*!< transmit buf full interrupt */
  69 #define SDIO_RXBUFF_INT                  ((uint32_t)0x00020000) /*!< receive buf full interrupt */
  70 #define SDIO_TXBUFE_INT                  ((uint32_t)0x00040000) /*!< transmit buf empty interrupt */
  71 #define SDIO_RXBUFE_INT                  ((uint32_t)0x00080000) /*!< receive buf empty interrupt */
  72 #define SDIO_TXBUF_INT                   ((uint32_t)0x00100000) /*!< data available in transmit interrupt */
  73 #define SDIO_RXBUF_INT                   ((uint32_t)0x00200000) /*!< data available in receive interrupt */
  74 #define SDIO_SDIOIF_INT                  ((uint32_t)0x00400000) /*!< sdio interface received interrupt */
  75
  76 /**
  77   * @}
  78   */
  79
  80 /** @defgroup SDIO_flags_definition
  81   * @brief sdio flag
  82   * @{
  83   */
  84
  85 #define SDIO_CMDFAIL_FLAG                ((uint32_t)0x00000001) /*!< command response received check failed flag */
  86 #define SDIO_DTFAIL_FLAG                 ((uint32_t)0x00000002) /*!< data block sent/received check failed flag */
  87 #define SDIO_CMDTIMEOUT_FLAG             ((uint32_t)0x00000004) /*!< command response timerout flag */
  88 #define SDIO_DTTIMEOUT_FLAG              ((uint32_t)0x00000008) /*!< data timeout flag */
  89 #define SDIO_TXERRU_FLAG                 ((uint32_t)0x00000010) /*!< transmit underrun error flag */
  90 #define SDIO_RXERRO_FLAG                 ((uint32_t)0x00000020) /*!< received overrun error flag */
  91 #define SDIO_CMDRSPCMPL_FLAG             ((uint32_t)0x00000040) /*!< command response received flag */
  92 #define SDIO_CMDCMPL_FLAG                ((uint32_t)0x00000080) /*!< command sent flag */
  93 #define SDIO_DTCMPL_FLAG                 ((uint32_t)0x00000100) /*!< data sent flag */
  94 #define SDIO_SBITERR_FLAG                ((uint32_t)0x00000200) /*!< start bit not detected on data bus flag */
  95 #define SDIO_DTBLKCMPL_FLAG              ((uint32_t)0x00000400) /*!< data block sent/received flag */
  96 #define SDIO_DOCMD_FLAG                  ((uint32_t)0x00000800) /*!< command transfer in progress flag */
  97 #define SDIO_DOTX_FLAG                   ((uint32_t)0x00001000) /*!< data transmit in progress flag */
  98 #define SDIO_DORX_FLAG                   ((uint32_t)0x00002000) /*!< data receive in progress flag */
  99 #define SDIO_TXBUFH_FLAG                 ((uint32_t)0x00004000) /*!< transmit buf half empty flag */
 100 #define SDIO_RXBUFH_FLAG                 ((uint32_t)0x00008000) /*!< receive buf half full flag */
 101 #define SDIO_TXBUFF_FLAG                 ((uint32_t)0x00010000) /*!< transmit buf full flag */
 102 #define SDIO_RXBUFF_FLAG                 ((uint32_t)0x00020000) /*!< receive buf full flag */
 103 #define SDIO_TXBUFE_FLAG                 ((uint32_t)0x00040000) /*!< transmit buf empty flag */
 104 #define SDIO_RXBUFE_FLAG                 ((uint32_t)0x00080000) /*!< receive buf empty flag */
 105 #define SDIO_TXBUF_FLAG                  ((uint32_t)0x00100000) /*!< data available in transmit flag */
 106 #define SDIO_RXBUF_FLAG                  ((uint32_t)0x00200000) /*!< data available in receive flag */
 107 #define SDIO_SDIOIF_FLAG                 ((uint32_t)0x00400000) /*!< sdio interface received flag */
 108
 109 /**
 110   * @}
 111   */
 112
 113 /** @defgroup SDIO_exported_types
 114   * @{
 115   */
 116
 117 /**
 118   * @brief sdio power state
 119   */
 120 typedef enum
 121 {
 122   SDIO_POWER_OFF                         = 0x00, /*!< power-off, clock to card is stopped */
 123   SDIO_POWER_ON                          = 0x03  /*!< power-on, the card is clocked */
 124 } sdio_power_state_type;
 125
 126 /**
 127   * @brief sdio edge phase
 128   */
 129 typedef enum
 130 {
 131   SDIO_CLOCK_EDGE_RISING                 = 0x00, /*!< sdio bus clock generated on the rising edge of the master clock */
 132   SDIO_CLOCK_EDGE_FALLING                = 0x01  /*!< sdio bus clock generated on the falling edge of the master clock */
 133 } sdio_edge_phase_type;
 134
 135 /**
 136   * @brief sdio bus width
 137   */
 138 typedef enum
 139 {
 140   SDIO_BUS_WIDTH_D1                      = 0x00, /*!< sdio wide bus select 1-bit */
 141   SDIO_BUS_WIDTH_D4                      = 0x01, /*!< sdio wide bus select 4-bit */
 142   SDIO_BUS_WIDTH_D8                      = 0x02  /*!< sdio wide bus select 8-bit */
 143 } sdio_bus_width_type;
 144
 145 /**
 146   * @brief sdio response type
 147   */
 148 typedef enum
 149 {
 150   SDIO_RESPONSE_NO                       = 0x00, /*!< no response */
 151   SDIO_RESPONSE_SHORT                    = 0x01, /*!< short response */
 152   SDIO_RESPONSE_LONG                     = 0x03  /*!< long response */
 153 } sdio_reponse_type;
 154
 155 /**
 156   * @brief sdio wait type
 157   */
 158 typedef enum
 159 {
 160   SDIO_WAIT_FOR_NO                       = 0x00, /*!< no wait */
 161   SDIO_WAIT_FOR_INT                      = 0x01, /*!< wait interrupt request */
 162   SDIO_WAIT_FOR_PEND                     = 0x02  /*!< wait end of transfer */
 163 } sdio_wait_type;
 164
 165 /**
 166   * @brief sdio response register index
 167   */
 168 typedef enum
 169 {
 170   SDIO_RSP1_INDEX                        = 0x00, /*!< response index 1, corresponding to sdio_rsp register 1 */
 171   SDIO_RSP2_INDEX                        = 0x01, /*!< response index 2, corresponding to sdio_rsp register 2 */
 172   SDIO_RSP3_INDEX                        = 0x02, /*!< response index 3, corresponding to sdio_rsp register 3 */
 173   SDIO_RSP4_INDEX                        = 0x03  /*!< response index 4, corresponding to sdio_rsp register 4 */
 174 } sdio_rsp_index_type;
 175
 176 /**
 177   * @brief sdio data block size
 178   */
 179 typedef enum
 180 {
 181   SDIO_DATA_BLOCK_SIZE_1B                = 0x00, /*!< data block size 1 byte */
 182   SDIO_DATA_BLOCK_SIZE_2B                = 0x01, /*!< data block size 2 bytes */
 183   SDIO_DATA_BLOCK_SIZE_4B                = 0x02, /*!< data block size 4 bytes */
 184   SDIO_DATA_BLOCK_SIZE_8B                = 0x03, /*!< data block size 8 bytes */
 185   SDIO_DATA_BLOCK_SIZE_16B               = 0x04, /*!< data block size 16 bytes */
 186   SDIO_DATA_BLOCK_SIZE_32B               = 0x05, /*!< data block size 32 bytes */
 187   SDIO_DATA_BLOCK_SIZE_64B               = 0x06, /*!< data block size 64 bytes */
 188   SDIO_DATA_BLOCK_SIZE_128B              = 0x07, /*!< data block size 128 bytes */
 189   SDIO_DATA_BLOCK_SIZE_256B              = 0x08, /*!< data block size 256 bytes */
 190   SDIO_DATA_BLOCK_SIZE_512B              = 0x09, /*!< data block size 512 bytes */
 191   SDIO_DATA_BLOCK_SIZE_1024B             = 0x0A, /*!< data block size 1024 bytes */
 192   SDIO_DATA_BLOCK_SIZE_2048B             = 0x0B, /*!< data block size 2048 bytes */
 193   SDIO_DATA_BLOCK_SIZE_4096B             = 0x0C, /*!< data block size 4096 bytes */
 194   SDIO_DATA_BLOCK_SIZE_8192B             = 0x0D, /*!< data block size 8192 bytes */
 195   SDIO_DATA_BLOCK_SIZE_16384B            = 0x0E  /*!< data block size 16384 bytes */
 196 } sdio_block_size_type;
 197
 198 /**
 199   * @brief sdio data transfer mode
 200   */
 201 typedef enum
 202 {
 203   SDIO_DATA_BLOCK_TRANSFER               = 0x00, /*!< the sdio block transfer mode */
 204   SDIO_DATA_STREAM_TRANSFER              = 0x01  /*!< the sdio stream transfer mode */
 205 } sdio_transfer_mode_type;
 206
 207 /**
 208   * @brief sdio data transfer direction
 209   */
 210 typedef enum
 211 {
 212   SDIO_DATA_TRANSFER_TO_CARD             = 0x00, /*!< the sdio controller write */
 213   SDIO_DATA_TRANSFER_TO_CONTROLLER       = 0x01  /*!< the sdio controller read */
 214 } sdio_transfer_direction_type;
 215
 216 /**
 217   * @brief sdio read wait mode
 218   */
 219 typedef enum
 220 {
 221   SDIO_READ_WAIT_CONTROLLED_BY_D2        = 0x00, /*!< the sdio read wait on data2 line */
 222   SDIO_READ_WAIT_CONTROLLED_BY_CK        = 0x01  /*!< the sdio read wait on clock line */
 223 } sdio_read_wait_mode_type;
 224
 225 /**
 226   * @brief sdio command structure
 227   */
 228 typedef struct
 229 {
 230   uint32_t                               argument;  /*!< the sdio command argument is sent to a card as part of command message */
 231   uint8_t                                cmd_index; /*!< the sdio command index */
 232   sdio_reponse_type                      rsp_type;  /*!< the sdio response type */
 233   sdio_wait_type                         wait_type; /*!< the sdio wait for interrupt request is enabled or disable */
 234 } sdio_command_struct_type;
 235
 236 /**
 237   * @brief sdio data structure
 238   */
 239 typedef struct
 240 {
 241   uint32_t                               timeout;            /*!< the sdio data timeout period in car bus clock periods */
 242   uint32_t                               data_length;        /*!< the sdio data length */
 243   sdio_block_size_type                   block_size;         /*!< the sdio data block size of block transfer mode */
 244   sdio_transfer_mode_type                transfer_mode;      /*!< the sdio transfer mode, block or stream */
 245   sdio_transfer_direction_type           transfer_direction; /*!< the sdio data transfer direction */
 246 } sdio_data_struct_type;
 247
 248 /**
 249   * @brief type define sdio register all
 250   */
 251 typedef struct
 252 {
 253   /**
 254     * @brief sdio pwrctrl register, offset:0x00
 255     */
 256   union
 257   {
 258     __IO uint32_t pwrctrl;
 259     struct
 260     {
 261       __IO uint32_t ps                   : 2; /* [1:0] */
 262       __IO uint32_t reserved1            : 30;/* [31:2] */
 263     } pwrctrl_bit;
 264   };
 265
 266   /**
 267     * @brief sdio clkctrl register, offset:0x04
 268     */
 269   union
 270   {
 271     __IO uint32_t clkctrl;
 272     struct
 273     {
 274       __IO uint32_t clkdiv_l             : 8; /* [7:0] */
 275       __IO uint32_t clkoen               : 1; /* [8] */
 276       __IO uint32_t pwrsven              : 1; /* [9] */
 277       __IO uint32_t bypsen               : 1; /* [10] */
 278       __IO uint32_t busws                : 2; /* [12:11] */
 279       __IO uint32_t clkegs               : 1; /* [13] */
 280       __IO uint32_t hfcen                : 1; /* [14] */
 281       __IO uint32_t clkdiv_h             : 2; /* [16:15] */
 282       __IO uint32_t reserved1            : 15;/* [31:17] */
 283     } clkctrl_bit;
 284   };
 285
 286   /**
 287     * @brief sdio argu register, offset:0x08
 288     */
 289   union
 290   {
 291     __IO uint32_t argu;
 292     struct
 293     {
 294       __IO uint32_t argu                 : 32;/* [31:0] */
 295     } argu_bit;
 296   };
 297
 298   /**
 299     * @brief sdio cmdctrl register, offset:0x0C
 300     */
 301   union
 302   {
 303     __IO uint32_t cmdctrl;
 304     struct
 305     {
 306       __IO uint32_t cmdidx               : 6; /* [5:0] */
 307       __IO uint32_t rspwt                : 2; /* [7:6] */
 308       __IO uint32_t intwt                : 1; /* [8] */
 309       __IO uint32_t pndwt                : 1; /* [9] */
 310       __IO uint32_t ccsmen               : 1; /* [10] */
 311       __IO uint32_t iosusp               : 1; /* [11] */
 312       __IO uint32_t reserved1            : 20;/* [31:12] */
 313     } cmdctrl_bit;
 314   };
 315
 316   /**
 317     * @brief sdio rspcmd register, offset:0x10
 318     */
 319   union
 320   {
 321     __IO uint32_t rspcmd;
 322     struct
 323     {
 324       __IO uint32_t rspcmd               : 6; /* [5:0] */
 325       __IO uint32_t reserved1            : 26;/* [31:6] */
 326     } rspcmd_bit;
 327   };
 328
 329   /**
 330     * @brief sdio rsp1 register, offset:0x14
 331     */
 332   union
 333   {
 334     __IO uint32_t rsp1;
 335     struct
 336     {
 337       __IO uint32_t cardsts1             : 32;/* [31:0] */
 338     } rsp1_bit;
 339   };
 340
 341   /**
 342     * @brief sdio rsp2 register, offset:0x18
 343     */
 344   union
 345   {
 346     __IO uint32_t rsp2;
 347     struct
 348     {
 349       __IO uint32_t cardsts2             : 32;/* [31:0] */
 350     } rsp2_bit;
 351   };
 352
 353   /**
 354     * @brief sdio rsp3 register, offset:0x1C
 355     */
 356   union
 357   {
 358     __IO uint32_t rsp3;
 359     struct
 360     {
 361       __IO uint32_t cardsts3             : 32;/* [31:0] */
 362     } rsp3_bit;
 363   };
 364
 365   /**
 366     * @brief sdio rsp4 register, offset:0x20
 367     */
 368   union
 369   {
 370     __IO uint32_t rsp4;
 371     struct
 372     {
 373       __IO uint32_t cardsts4             : 32;/* [31:0] */
 374     } rsp4_bit;
 375   };
 376
 377   /**
 378     * @brief sdio dttmr register, offset:0x24
 379     */
 380   union
 381   {
 382     __IO uint32_t dttmr;
 383     struct
 384     {
 385       __IO uint32_t timeout              : 32;/* [31:0] */
 386     } dttmr_bit;
 387   };
 388
 389   /**
 390     * @brief sdio dtlen register, offset:0x28
 391     */
 392   union
 393   {
 394     __IO uint32_t dtlen;
 395     struct
 396     {
 397       __IO uint32_t dtlen                : 25;/* [24:0] */
 398       __IO uint32_t reserved1            : 7; /* [31:25] */
 399     } dtlen_bit;
 400   };
 401
 402   /**
 403     * @brief sdio dtctrl register, offset:0x2C
 404     */
 405   union
 406   {
 407     __IO uint32_t dtctrl;
 408     struct
 409     {
 410       __IO uint32_t tfren                : 1; /* [0] */
 411       __IO uint32_t tfrdir               : 1; /* [1] */
 412       __IO uint32_t tfrmode              : 1; /* [2] */
 413       __IO uint32_t dmaen                : 1; /* [3] */
 414       __IO uint32_t blksize              : 4; /* [7:4] */
 415       __IO uint32_t rdwtstart            : 1; /* [8] */
 416       __IO uint32_t rdwtstop             : 1; /* [9] */
 417       __IO uint32_t rdwtmode             : 1; /* [10] */
 418       __IO uint32_t ioen                 : 1; /* [11] */
 419       __IO uint32_t reserved1            : 20;/* [31:12] */
 420     } dtctrl_bit;
 421   };
 422
 423   /**
 424     * @brief sdio dtcnt register, offset:0x30
 425     */
 426   union
 427   {
 428     __IO uint32_t dtcnt;
 429     struct
 430     {
 431       __IO uint32_t cnt                  : 25;/* [24:0] */
 432       __IO uint32_t reserved1            : 7; /* [31:25] */
 433     } dtcnt_bit;
 434   };
 435
 436   /**
 437     * @brief sdio sts register, offset:0x34
 438     */
 439   union
 440   {
 441     __IO uint32_t sts;
 442     struct
 443     {
 444       __IO uint32_t cmdfail              : 1; /* [0] */
 445       __IO uint32_t dtfail               : 1; /* [1] */
 446       __IO uint32_t cmdtimeout           : 1; /* [2] */
 447       __IO uint32_t dttimeout            : 1; /* [3] */
 448       __IO uint32_t txerru               : 1; /* [4] */
 449       __IO uint32_t rxerro               : 1; /* [5] */
 450       __IO uint32_t cmdrspcmpl           : 1; /* [6] */
 451       __IO uint32_t cmdcmpl              : 1; /* [7] */
 452       __IO uint32_t dtcmpl               : 1; /* [8] */
 453       __IO uint32_t sbiterr              : 1; /* [9] */
 454       __IO uint32_t dtblkcmpl            : 1; /* [10] */
 455       __IO uint32_t docmd                : 1; /* [11] */
 456       __IO uint32_t dotx                 : 1; /* [12] */
 457       __IO uint32_t dorx                 : 1; /* [13] */
 458       __IO uint32_t txbufh               : 1; /* [14] */
 459       __IO uint32_t rxbufh               : 1; /* [15] */
 460       __IO uint32_t txbuff               : 1; /* [16] */
 461       __IO uint32_t rxbuff               : 1; /* [17] */
 462       __IO uint32_t txbufe               : 1; /* [18] */
 463       __IO uint32_t rxbufe               : 1; /* [19] */
 464       __IO uint32_t txbuf                : 1; /* [20] */
 465       __IO uint32_t rxbuf                : 1; /* [21] */
 466       __IO uint32_t ioif                 : 1; /* [22] */
 467       __IO uint32_t reserved1            : 9; /* [31:23] */
 468     } sts_bit;
 469   };
 470
 471   /**
 472     * @brief sdio intclr register, offset:0x38
 473     */
 474   union
 475   {
 476     __IO uint32_t intclr;
 477     struct
 478     {
 479       __IO uint32_t cmdfail              : 1; /* [0] */
 480       __IO uint32_t dtfail               : 1; /* [1] */
 481       __IO uint32_t cmdtimeout           : 1; /* [2] */
 482       __IO uint32_t dttimeout            : 1; /* [3] */
 483       __IO uint32_t txerru               : 1; /* [4] */
 484       __IO uint32_t rxerro               : 1; /* [5] */
 485       __IO uint32_t cmdrspcmpl           : 1; /* [6] */
 486       __IO uint32_t cmdcmpl              : 1; /* [7] */
 487       __IO uint32_t dtcmpl               : 1; /* [8] */
 488       __IO uint32_t sbiterr              : 1; /* [9] */
 489       __IO uint32_t dtblkcmpl            : 1; /* [10] */
 490       __IO uint32_t reserved1            : 11;/* [21:11] */
 491       __IO uint32_t ioif                 : 1; /* [22] */
 492       __IO uint32_t reserved2            : 9; /* [31:23] */
 493     } intclr_bit;
 494   };
 495
 496   /**
 497     * @brief sdio inten register, offset:0x3C
 498     */
 499   union
 500   {
 501     __IO uint32_t inten;
 502     struct
 503     {
 504       __IO uint32_t cmdfailien           : 1; /* [0] */
 505       __IO uint32_t dtfailien            : 1; /* [1] */
 506       __IO uint32_t cmdtimeoutien        : 1; /* [2] */
 507       __IO uint32_t dttimeoutien         : 1; /* [3] */
 508       __IO uint32_t txerruien            : 1; /* [4] */
 509       __IO uint32_t rxerroien            : 1; /* [5] */
 510       __IO uint32_t cmdrspcmplien        : 1; /* [6] */
 511       __IO uint32_t cmdcmplien           : 1; /* [7] */
 512       __IO uint32_t dtcmplien            : 1; /* [8] */
 513       __IO uint32_t sbiterrien           : 1; /* [9] */
 514       __IO uint32_t dtblkcmplien         : 1; /* [10] */
 515       __IO uint32_t docmdien             : 1; /* [11] */
 516       __IO uint32_t dotxien              : 1; /* [12] */
 517       __IO uint32_t dorxien              : 1; /* [13] */
 518       __IO uint32_t txbufhien            : 1; /* [14] */
 519       __IO uint32_t rxbufhien            : 1; /* [15] */
 520       __IO uint32_t txbuffien            : 1; /* [16] */
 521       __IO uint32_t rxbuffien            : 1; /* [17] */
 522       __IO uint32_t txbufeien            : 1; /* [18] */
 523       __IO uint32_t rxbufeien            : 1; /* [19] */
 524       __IO uint32_t txbufien             : 1; /* [20] */
 525       __IO uint32_t rxbufien             : 1; /* [21] */
 526       __IO uint32_t ioifien              : 1; /* [22] */
 527       __IO uint32_t reserved1            : 9; /* [31:23] */
 528     } inten_bit;
 529   };
 530
 531   /**
 532     * @brief sdio reserved1 register, offset:0x40~0x44
 533     */
 534   __IO uint32_t reserved1[2];
 535
 536   /**
 537     * @brief sdio bufcnt register, offset:0x48
 538     */
 539   union
 540   {
 541     __IO uint32_t bufcnt;
 542     struct
 543     {
 544       __IO uint32_t cnt                  : 24;/* [23:0] */
 545       __IO uint32_t reserved1            : 8; /* [31:24] */
 546     } bufcnt_bit;
 547   };
 548
 549   /**
 550     * @brief sdio reserved2 register, offset:0x4C~0x7C
 551     */
 552   __IO uint32_t reserved2[13];
 553
 554   /**
 555     * @brief sdio buf register, offset:0x80
 556     */
 557   union
 558   {
 559     __IO uint32_t buf;
 560     struct
 561     {
 562       __IO uint32_t dt                   : 32;/* [31:0] */
 563     } buf_bit;
 564   };
 565
 566 } sdio_type;
 567
 568 /**
 569   * @}
 570   */
 571
 572 #define SDIO1                            ((sdio_type *) SDIO1_BASE)
 573 #define SDIO2                            ((sdio_type *) SDIO2_BASE)
 574
 575 /** @defgroup SDIO_exported_functions
 576   * @{
 577   */
 578
 579 void sdio_reset(sdio_type *sdio_x);
 580 void sdio_power_set(sdio_type *sdio_x, sdio_power_state_type power_state);
 581 sdio_power_state_type sdio_power_status_get(sdio_type *sdio_x);
 582 void sdio_clock_config(sdio_type *sdio_x, uint16_t clk_div, sdio_edge_phase_type clk_edg);
 583 void sdio_bus_width_config(sdio_type *sdio_x, sdio_bus_width_type width);
 584 void sdio_clock_bypass(sdio_type *sdio_x, confirm_state new_state);
 585 void sdio_power_saving_mode_enable(sdio_type *sdio_x, confirm_state new_state);
 586 void sdio_flow_control_enable(sdio_type *sdio_x, confirm_state new_state);
 587 void sdio_clock_enable(sdio_type *sdio_x, confirm_state new_state);
 588 void sdio_dma_enable(sdio_type *sdio_x, confirm_state new_state);
 589 void sdio_interrupt_enable(sdio_type *sdio_x, uint32_t int_opt,  confirm_state new_state);
 590 flag_status sdio_flag_get(sdio_type *sdio_x, uint32_t flag);
 591 void sdio_flag_clear(sdio_type *sdio_x, uint32_t flag);
 592 void sdio_command_config(sdio_type *sdio_x, sdio_command_struct_type *command_struct);
 593 void sdio_command_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
 594 uint8_t sdio_command_response_get(sdio_type *sdio_x);
 595 uint32_t sdio_response_get(sdio_type *sdio_x, sdio_rsp_index_type reg_index);
 596 void sdio_data_config(sdio_type *sdio_x, sdio_data_struct_type *data_struct);
 597 void sdio_data_state_machine_enable(sdio_type *sdio_x, confirm_state new_state);
 598 uint32_t sdio_data_counter_get(sdio_type *sdio_x);
 599 uint32_t sdio_data_read(sdio_type *sdio_x);
 600 uint32_t sdio_buffer_counter_get(sdio_type *sdio_x);
 601 void sdio_data_write(sdio_type *sdio_x, uint32_t data);
 602 void sdio_read_wait_mode_set(sdio_type *sdio_x, sdio_read_wait_mode_type mode);
 603 void sdio_read_wait_start(sdio_type *sdio_x, confirm_state new_state);
 604 void sdio_read_wait_stop(sdio_type *sdio_x, confirm_state new_state);
 605 void sdio_io_function_enable(sdio_type *sdio_x, confirm_state new_state);
 606 void sdio_io_suspend_command_set(sdio_type *sdio_x, confirm_state new_state);
 607
 608 /**
 609   * @}
 610   */
 611
 612 /**
 613   * @}
 614   */
 615
 616 /**
 617   * @}
 618   */
 619
 620 #ifdef __cplusplus
 621 }
 622 #endif
 623
 624 #endif