lib/main/AT32F43x/Drivers/AT32F43x_StdPeriph_Driver/inc/at32f435_437_spi.h

   1 /**
   2   **************************************************************************
   3   * @file     at32f435_437_spi.h
   4   * @version  v2.1.0
   5   * @date     2022-08-16
   6   * @brief    at32f435_437 spi header file
   7   **************************************************************************
   8   *                       Copyright notice & Disclaimer
   9   *
  10   * The software Board Support Package (BSP) that is made available to
  11   * download from Artery official website is the copyrighted work of Artery.
  12   * Artery authorizes customers to use, copy, and distribute the BSP
  13   * software and its related documentation for the purpose of design and
  14   * development in conjunction with Artery microcontrollers. Use of the
  15   * software is governed by this copyright notice and the following disclaimer.
  16   *
  17   * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
  18   * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
  19   * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
  20   * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
  21   * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
  22   * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
  23   *
  24   **************************************************************************
  25   */
  26
  27 /* Define to prevent recursive inclusion -------------------------------------*/
  28 #ifndef __AT32F435_437_SPI_H
  29 #define __AT32F435_437_SPI_H
  30
  31 #ifdef __cplusplus
  32 extern "C" {
  33 #endif
  34
  35
  36 /* Includes ------------------------------------------------------------------*/
  37 #include "at32f435_437.h"
  38
  39 /** @addtogroup AT32F435_437_periph_driver
  40   * @{
  41   */
  42
  43 /** @addtogroup SPI
  44   * @{
  45   */
  46
  47 /**
  48   * @defgroup SPI_I2S_flags_definition
  49   * @brief spi i2s flag
  50   * @{
  51   */
  52
  53 #define SPI_I2S_RDBF_FLAG                0x0001 /*!< spi or i2s receive data buffer full flag */
  54 #define SPI_I2S_TDBE_FLAG                0x0002 /*!< spi or i2s transmit data buffer empty flag */
  55 #define I2S_ACS_FLAG                     0x0004 /*!< i2s audio channel state flag */
  56 #define I2S_TUERR_FLAG                   0x0008 /*!< i2s transmitter underload error flag */
  57 #define SPI_CCERR_FLAG                   0x0010 /*!< spi crc calculation error flag */
  58 #define SPI_MMERR_FLAG                   0x0020 /*!< spi master mode error flag */
  59 #define SPI_I2S_ROERR_FLAG               0x0040 /*!< spi or i2s receiver overflow error flag */
  60 #define SPI_I2S_BF_FLAG                  0x0080 /*!< spi or i2s busy flag */
  61 #define SPI_CSPAS_FLAG                   0x0100 /*!< spi cs pulse abnormal setting fiag */
  62
  63 /**
  64   * @}
  65   */
  66
  67 /**
  68   * @defgroup SPI_I2S_interrupts_definition
  69   * @brief spi i2s interrupt
  70   * @{
  71   */
  72
  73 #define SPI_I2S_ERROR_INT                0x0020 /*!< error interrupt */
  74 #define SPI_I2S_RDBF_INT                 0x0040 /*!< receive data buffer full interrupt */
  75 #define SPI_I2S_TDBE_INT                 0x0080 /*!< transmit data buffer empty interrupt */
  76
  77 /**
  78   * @}
  79   */
  80
  81 /** @defgroup SPI_exported_types
  82   * @{
  83   */
  84
  85 /**
  86   * @brief spi frame bit num type
  87   */
  88 typedef enum
  89 {
  90   SPI_FRAME_8BIT                         = 0x00, /*!< 8-bit data frame format */
  91   SPI_FRAME_16BIT                        = 0x01  /*!< 16-bit data frame format */
  92 } spi_frame_bit_num_type;
  93
  94 /**
  95   * @brief spi master/slave mode type
  96   */
  97 typedef enum
  98 {
  99   SPI_MODE_SLAVE                         = 0x00, /*!< select as slave mode */
 100   SPI_MODE_MASTER                        = 0x01  /*!< select as master mode */
 101 } spi_master_slave_mode_type;
 102
 103 /**
 104   * @brief spi clock polarity (clkpol) type
 105   */
 106 typedef enum
 107 {
 108   SPI_CLOCK_POLARITY_LOW                 = 0x00, /*!< sck keeps low at idle state */
 109   SPI_CLOCK_POLARITY_HIGH                = 0x01  /*!< sck keeps high at idle state */
 110 } spi_clock_polarity_type;
 111
 112 /**
 113   * @brief spi clock phase (clkpha) type
 114   */
 115 typedef enum
 116 {
 117   SPI_CLOCK_PHASE_1EDGE                  = 0x00, /*!< data capture start from the first clock edge */
 118   SPI_CLOCK_PHASE_2EDGE                  = 0x01  /*!< data capture start from the second clock edge */
 119 } spi_clock_phase_type;
 120
 121 /**
 122   * @brief spi cs mode type
 123   */
 124 typedef enum
 125 {
 126   SPI_CS_HARDWARE_MODE                   = 0x00, /*!< cs is hardware mode */
 127   SPI_CS_SOFTWARE_MODE                   = 0x01  /*!< cs is software mode */
 128 } spi_cs_mode_type;
 129
 130 /**
 131   * @brief spi master clock frequency division type
 132   */
 133 typedef enum
 134 {
 135   SPI_MCLK_DIV_2                         = 0x00, /*!< master clock frequency division 2 */
 136   SPI_MCLK_DIV_3                         = 0x0A, /*!< master clock frequency division 3 */
 137   SPI_MCLK_DIV_4                         = 0x01, /*!< master clock frequency division 4 */
 138   SPI_MCLK_DIV_8                         = 0x02, /*!< master clock frequency division 8 */
 139   SPI_MCLK_DIV_16                        = 0x03, /*!< master clock frequency division 16 */
 140   SPI_MCLK_DIV_32                        = 0x04, /*!< master clock frequency division 32 */
 141   SPI_MCLK_DIV_64                        = 0x05, /*!< master clock frequency division 64 */
 142   SPI_MCLK_DIV_128                       = 0x06, /*!< master clock frequency division 128 */
 143   SPI_MCLK_DIV_256                       = 0x07, /*!< master clock frequency division 256 */
 144   SPI_MCLK_DIV_512                       = 0x08, /*!< master clock frequency division 512 */
 145   SPI_MCLK_DIV_1024                      = 0x09  /*!< master clock frequency division 1024 */
 146 } spi_mclk_freq_div_type;
 147
 148 /**
 149   * @brief spi transmit first bit (lsb/msb) type
 150   */
 151 typedef enum
 152 {
 153   SPI_FIRST_BIT_MSB                      = 0x00, /*!< the frame format is msb first */
 154   SPI_FIRST_BIT_LSB                      = 0x01  /*!< the frame format is lsb first */
 155 } spi_first_bit_type;
 156
 157 /**
 158   * @brief spi transmission mode type
 159   */
 160 typedef enum
 161 {
 162   SPI_TRANSMIT_FULL_DUPLEX               = 0x00, /*!< dual line unidirectional full-duplex mode(slben = 0 and ora = 0) */
 163   SPI_TRANSMIT_SIMPLEX_RX                = 0x01, /*!< dual line unidirectional simplex receive-only mode(slben = 0 and ora = 1) */
 164   SPI_TRANSMIT_HALF_DUPLEX_RX            = 0x02, /*!< single line bidirectional half duplex mode-receiving(slben = 1 and slbtd = 0) */
 165   SPI_TRANSMIT_HALF_DUPLEX_TX            = 0x03  /*!< single line bidirectional half duplex mode-transmitting(slben = 1 and slbtd = 1) */
 166 } spi_transmission_mode_type;
 167
 168 /**
 169   * @brief spi crc direction type
 170   */
 171 typedef enum
 172 {
 173   SPI_CRC_RX                             = 0x0014, /*!< crc direction is rx */
 174   SPI_CRC_TX                             = 0x0018  /*!< crc direction is tx */
 175 } spi_crc_direction_type;
 176
 177 /**
 178   * @brief spi single line bidirectional direction type
 179   */
 180 typedef enum
 181 {
 182   SPI_HALF_DUPLEX_DIRECTION_RX           = 0x00, /*!< single line bidirectional half duplex mode direction: receive(slbtd = 0) */
 183   SPI_HALF_DUPLEX_DIRECTION_TX           = 0x01  /*!< single line bidirectional half duplex mode direction: transmit(slbtd = 1) */
 184 } spi_half_duplex_direction_type;
 185
 186 /**
 187   * @brief spi software cs internal level type
 188   */
 189 typedef enum
 190 {
 191   SPI_SWCS_INTERNAL_LEVEL_LOW            = 0x00, /*!< internal level low */
 192   SPI_SWCS_INTERNAL_LEVEL_HIGHT          = 0x01  /*!< internal level high */
 193 } spi_software_cs_level_type;
 194
 195 /**
 196   * @brief i2s audio protocol type
 197   */
 198 typedef enum
 199 {
 200   I2S_AUDIO_PROTOCOL_PHILLIPS            = 0x00, /*!< i2s philip standard */
 201   I2S_AUDIO_PROTOCOL_MSB                 = 0x01, /*!< msb-justified standard */
 202   I2S_AUDIO_PROTOCOL_LSB                 = 0x02, /*!< lsb-justified standard */
 203   I2S_AUDIO_PROTOCOL_PCM_SHORT           = 0x03, /*!< pcm standard-short frame */
 204   I2S_AUDIO_PROTOCOL_PCM_LONG            = 0x04  /*!< pcm standard-long frame */
 205 } i2s_audio_protocol_type;
 206
 207 /**
 208   * @brief i2s audio frequency type
 209   */
 210 typedef enum
 211 {
 212   I2S_AUDIO_FREQUENCY_DEFAULT            = 2,     /*!< i2s audio sampling frequency default */
 213   I2S_AUDIO_FREQUENCY_8K                 = 8000,  /*!< i2s audio sampling frequency 8k */
 214   I2S_AUDIO_FREQUENCY_11_025K            = 11025, /*!< i2s audio sampling frequency 11.025k */
 215   I2S_AUDIO_FREQUENCY_16K                = 16000, /*!< i2s audio sampling frequency 16k */
 216   I2S_AUDIO_FREQUENCY_22_05K             = 22050, /*!< i2s audio sampling frequency 22.05k */
 217   I2S_AUDIO_FREQUENCY_32K                = 32000, /*!< i2s audio sampling frequency 32k */
 218   I2S_AUDIO_FREQUENCY_44_1K              = 44100, /*!< i2s audio sampling frequency 44.1k */
 219   I2S_AUDIO_FREQUENCY_48K                = 48000, /*!< i2s audio sampling frequency 48k */
 220   I2S_AUDIO_FREQUENCY_96K                = 96000, /*!< i2s audio sampling frequency 96k */
 221   I2S_AUDIO_FREQUENCY_192K               = 192000 /*!< i2s audio sampling frequency 192k */
 222 } i2s_audio_sampling_freq_type;
 223
 224 /**
 225   * @brief i2s data bit num and channel bit num type
 226   */
 227 typedef enum
 228 {
 229   I2S_DATA_16BIT_CHANNEL_16BIT           = 0x01, /*!< 16-bit data packed in 16-bit channel frame */
 230   I2S_DATA_16BIT_CHANNEL_32BIT           = 0x02, /*!< 16-bit data packed in 32-bit channel frame */
 231   I2S_DATA_24BIT_CHANNEL_32BIT           = 0x03, /*!< 24-bit data packed in 32-bit channel frame */
 232   I2S_DATA_32BIT_CHANNEL_32BIT           = 0x04  /*!< 32-bit data packed in 32-bit channel frame */
 233 } i2s_data_channel_format_type;
 234
 235 /**
 236   * @brief i2s operation mode type
 237   */
 238 typedef enum
 239 {
 240   I2S_MODE_SLAVE_TX                      = 0x00, /*!< slave transmission mode */
 241   I2S_MODE_SLAVE_RX                      = 0x01, /*!< slave reception mode */
 242   I2S_MODE_MASTER_TX                     = 0x02, /*!< master transmission mode */
 243   I2S_MODE_MASTER_RX                     = 0x03  /*!< master reception mode */
 244 } i2s_operation_mode_type;
 245
 246 /**
 247   * @brief i2s clock polarity type
 248   */
 249 typedef enum
 250 {
 251   I2S_CLOCK_POLARITY_LOW                 = 0x00, /*!< i2s clock steady state is low level */
 252   I2S_CLOCK_POLARITY_HIGH                = 0x01  /*!< i2s clock steady state is high level */
 253 } i2s_clock_polarity_type;
 254
 255 /**
 256   * @brief spi init type
 257   */
 258 typedef struct
 259 {
 260   spi_transmission_mode_type             transmission_mode;     /*!< transmission mode selection */
 261   spi_master_slave_mode_type             master_slave_mode;     /*!< master or slave mode selection */
 262   spi_mclk_freq_div_type                 mclk_freq_division;    /*!< master clock frequency division selection */
 263   spi_first_bit_type                     first_bit_transmission;/*!< transmit lsb or msb selection */
 264   spi_frame_bit_num_type                 frame_bit_num;         /*!< frame bit num 8 or 16 bit selection */
 265   spi_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
 266   spi_clock_phase_type                   clock_phase;           /*!< clock phase selection */
 267   spi_cs_mode_type                       cs_mode_selection;     /*!< hardware or software cs mode selection */
 268 } spi_init_type;
 269
 270 /**
 271   * @brief i2s init type
 272   */
 273 typedef struct
 274 {
 275   i2s_operation_mode_type                operation_mode;        /*!< operation mode selection */
 276   i2s_audio_protocol_type                audio_protocol;        /*!< audio protocol selection */
 277   i2s_audio_sampling_freq_type           audio_sampling_freq;   /*!< audio frequency selection */
 278   i2s_data_channel_format_type           data_channel_format;   /*!< data bit num and channel bit num selection */
 279   i2s_clock_polarity_type                clock_polarity;        /*!< clock polarity selection */
 280   confirm_state                          mclk_output_enable;    /*!< mclk_output selection */
 281 } i2s_init_type;
 282
 283 /**
 284   * @brief type define spi register all
 285   */
 286 typedef struct
 287 {
 288
 289   /**
 290     * @brief spi ctrl1 register, offset:0x00
 291     */
 292   union
 293   {
 294     __IO uint32_t ctrl1;
 295     struct
 296     {
 297       __IO uint32_t clkpha               : 1; /* [0] */
 298       __IO uint32_t clkpol               : 1; /* [1] */
 299       __IO uint32_t msten                : 1; /* [2] */
 300       __IO uint32_t mdiv_l               : 3; /* [5:3] */
 301       __IO uint32_t spien                : 1; /* [6] */
 302       __IO uint32_t ltf                  : 1; /* [7] */
 303       __IO uint32_t swcsil               : 1; /* [8] */
 304       __IO uint32_t swcsen               : 1; /* [9] */
 305       __IO uint32_t ora                  : 1; /* [10] */
 306       __IO uint32_t fbn                  : 1; /* [11] */
 307       __IO uint32_t ntc                  : 1; /* [12] */
 308       __IO uint32_t ccen                 : 1; /* [13] */
 309       __IO uint32_t slbtd                : 1; /* [14] */
 310       __IO uint32_t slben                : 1; /* [15] */
 311       __IO uint32_t reserved1            : 16;/* [31:16] */
 312     } ctrl1_bit;
 313   };
 314
 315   /**
 316     * @brief spi ctrl2 register, offset:0x04
 317     */
 318   union
 319   {
 320     __IO uint32_t ctrl2;
 321     struct
 322     {
 323       __IO uint32_t dmaren               : 1; /* [0] */
 324       __IO uint32_t dmaten               : 1; /* [1] */
 325       __IO uint32_t hwcsoe               : 1; /* [2] */
 326       __IO uint32_t reserved1            : 1; /* [3] */
 327       __IO uint32_t tien                 : 1; /* [4] */
 328       __IO uint32_t errie                : 1; /* [5] */
 329       __IO uint32_t rdbfie               : 1; /* [6] */
 330       __IO uint32_t tdbeie               : 1; /* [7] */
 331       __IO uint32_t mdiv_h               : 1; /* [8] */
 332       __IO uint32_t mdiv3en              : 1; /* [9] */
 333       __IO uint32_t reserved2            : 22;/* [31:10] */
 334     } ctrl2_bit;
 335   };
 336
 337   /**
 338     * @brief spi sts register, offset:0x08
 339     */
 340   union
 341   {
 342     __IO uint32_t sts;
 343     struct
 344     {
 345       __IO uint32_t rdbf                 : 1; /* [0] */
 346       __IO uint32_t tdbe                 : 1; /* [1] */
 347       __IO uint32_t acs                  : 1; /* [2] */
 348       __IO uint32_t tuerr                : 1; /* [3] */
 349       __IO uint32_t ccerr                : 1; /* [4] */
 350       __IO uint32_t mmerr                : 1; /* [5] */
 351       __IO uint32_t roerr                : 1; /* [6] */
 352       __IO uint32_t bf                   : 1; /* [7] */
 353       __IO uint32_t cspas                : 1; /* [8] */
 354       __IO uint32_t reserved1            : 23;/* [31:9] */
 355     } sts_bit;
 356   };
 357
 358   /**
 359     * @brief spi dt register, offset:0x0C
 360     */
 361   union
 362   {
 363     __IO uint32_t dt;
 364     struct
 365     {
 366       __IO uint32_t dt                  : 16;/* [15:0] */
 367       __IO uint32_t reserved1           : 16;/* [31:16] */
 368     } dt_bit;
 369   };
 370
 371   /**
 372     * @brief spi cpoly register, offset:0x10
 373     */
 374   union
 375   {
 376     __IO uint32_t cpoly;
 377     struct
 378     {
 379       __IO uint32_t cpoly               : 16;/* [15:0] */
 380       __IO uint32_t reserved1           : 16;/* [31:16] */
 381     } cpoly_bit;
 382   };
 383
 384   /**
 385     * @brief spi rcrc register, offset:0x14
 386     */
 387   union
 388   {
 389     __IO uint32_t rcrc;
 390     struct
 391     {
 392       __IO uint32_t rcrc                : 16;/* [15:0] */
 393       __IO uint32_t reserved1           : 16;/* [31:16] */
 394     } rcrc_bit;
 395   };
 396
 397   /**
 398     * @brief spi tcrc register, offset:0x18
 399     */
 400   union
 401   {
 402     __IO uint32_t tcrc;
 403     struct
 404     {
 405       __IO uint32_t tcrc                : 16;/* [15:0] */
 406       __IO uint32_t reserved1           : 16;/* [31:16] */
 407     } tcrc_bit;
 408   };
 409
 410   /**
 411     * @brief spi i2sctrl register, offset:0x1C
 412     */
 413   union
 414   {
 415     __IO uint32_t i2sctrl;
 416     struct
 417     {
 418       __IO uint32_t i2scbn              : 1; /* [0] */
 419       __IO uint32_t i2sdbn              : 2; /* [2:1] */
 420       __IO uint32_t i2sclkpol           : 1; /* [3] */
 421       __IO uint32_t stdsel              : 2; /* [5:4] */
 422       __IO uint32_t reserved1           : 1; /* [6] */
 423       __IO uint32_t pcmfssel            : 1; /* [7] */
 424       __IO uint32_t opersel             : 2; /* [9:8] */
 425       __IO uint32_t i2sen               : 1; /* [10] */
 426       __IO uint32_t i2smsel             : 1; /* [11] */
 427       __IO uint32_t reserved2           : 20;/* [31:12] */
 428     } i2sctrl_bit;
 429   };
 430
 431   /**
 432     * @brief spi i2sclk register, offset:0x20
 433     */
 434   union
 435   {
 436     __IO uint32_t i2sclk;
 437     struct
 438     {
 439       __IO uint32_t i2sdiv_l            : 8; /* [7:0] */
 440       __IO uint32_t i2sodd              : 1; /* [8] */
 441       __IO uint32_t i2smclkoe           : 1; /* [9] */
 442       __IO uint32_t i2sdiv_h            : 2; /* [11:10] */
 443       __IO uint32_t reserved1           : 20;/* [31:12] */
 444     } i2sclk_bit;
 445   };
 446
 447 } spi_type;
 448
 449 /**
 450   * @}
 451   */
 452
 453 #define SPI1                            ((spi_type *) SPI1_BASE)
 454 #define SPI2                            ((spi_type *) SPI2_BASE)
 455 #define SPI3                            ((spi_type *) SPI3_BASE)
 456 #define SPI4                            ((spi_type *) SPI4_BASE)
 457 #define I2S2EXT                         ((spi_type *) I2S2EXT_BASE)
 458 #define I2S3EXT                         ((spi_type *) I2S3EXT_BASE)
 459
 460 /** @defgroup SPI_exported_functions
 461   * @{
 462   */
 463
 464 void spi_i2s_reset(spi_type *spi_x);
 465 void spi_default_para_init(spi_init_type* spi_init_struct);
 466 void spi_init(spi_type* spi_x, spi_init_type* spi_init_struct);
 467 void spi_ti_mode_enable(spi_type* spi_x, confirm_state new_state);
 468 void spi_crc_next_transmit(spi_type* spi_x);
 469 void spi_crc_polynomial_set(spi_type* spi_x, uint16_t crc_poly);
 470 uint16_t spi_crc_polynomial_get(spi_type* spi_x);
 471 void spi_crc_enable(spi_type* spi_x, confirm_state new_state);
 472 uint16_t spi_crc_value_get(spi_type* spi_x, spi_crc_direction_type crc_direction);
 473 void spi_hardware_cs_output_enable(spi_type* spi_x, confirm_state new_state);
 474 void spi_software_cs_internal_level_set(spi_type* spi_x, spi_software_cs_level_type level);
 475 void spi_frame_bit_num_set(spi_type* spi_x, spi_frame_bit_num_type bit_num);
 476 void spi_half_duplex_direction_set(spi_type* spi_x, spi_half_duplex_direction_type direction);
 477 void spi_enable(spi_type* spi_x, confirm_state new_state);
 478 void i2s_default_para_init(i2s_init_type* i2s_init_struct);
 479 void i2s_init(spi_type* spi_x, i2s_init_type* i2s_init_struct);
 480 void i2s_enable(spi_type* spi_x, confirm_state new_state);
 481 void spi_i2s_interrupt_enable(spi_type* spi_x, uint32_t spi_i2s_int, confirm_state new_state);
 482 void spi_i2s_dma_transmitter_enable(spi_type* spi_x, confirm_state new_state);
 483 void spi_i2s_dma_receiver_enable(spi_type* spi_x, confirm_state new_state);
 484 void spi_i2s_data_transmit(spi_type* spi_x, uint16_t tx_data);
 485 uint16_t spi_i2s_data_receive(spi_type* spi_x);
 486 flag_status spi_i2s_flag_get(spi_type* spi_x, uint32_t spi_i2s_flag);
 487 void spi_i2s_flag_clear(spi_type* spi_x, uint32_t spi_i2s_flag);
 488
 489 /**
 490   * @}
 491   */
 492
 493 /**
 494   * @}
 495   */
 496
 497 /**
 498   * @}
 499   */
 500
 501 #ifdef __cplusplus
 502 }
 503 #endif
 504
 505 #endif