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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_tmr.h
blob1e4256bb1eee2bd56ee10698ccf9d5b48fdfd864
1 /**
2 **************************************************************************
3 * @file at32f435_437_tmr.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 tmr header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_TMR_H
29 #define __AT32F435_437_TMR_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup TMR
44 * @{
45 */
46
47 /** @defgroup TMR_flags_definition
48 * @brief tmr flag
49 * @{
50 */
51
52 #define TMR_OVF_FLAG ((uint32_t)0x000001) /*!< tmr flag overflow */
53 #define TMR_C1_FLAG ((uint32_t)0x000002) /*!< tmr flag channel 1 */
54 #define TMR_C2_FLAG ((uint32_t)0x000004) /*!< tmr flag channel 2 */
55 #define TMR_C3_FLAG ((uint32_t)0x000008) /*!< tmr flag channel 3 */
56 #define TMR_C4_FLAG ((uint32_t)0x000010) /*!< tmr flag channel 4 */
57 #define TMR_C5_FLAG ((uint32_t)0x010000) /*!< tmr flag channel 5 */
58 #define TMR_HALL_FLAG ((uint32_t)0x000020) /*!< tmr flag hall */
59 #define TMR_TRIGGER_FLAG ((uint32_t)0x000040) /*!< tmr flag trigger */
60 #define TMR_BRK_FLAG ((uint32_t)0x000080) /*!< tmr flag brake */
61 #define TMR_C1_RECAPTURE_FLAG ((uint32_t)0x000200) /*!< tmr flag channel 1 recapture */
62 #define TMR_C2_RECAPTURE_FLAG ((uint32_t)0x000400) /*!< tmr flag channel 2 recapture */
63 #define TMR_C3_RECAPTURE_FLAG ((uint32_t)0x000800) /*!< tmr flag channel 3 recapture */
64 #define TMR_C4_RECAPTURE_FLAG ((uint32_t)0x001000) /*!< tmr flag channel 4 recapture */
65
66 /**
67 * @}
68 */
69
70 /** @defgroup TMR_interrupt_select_type_definition
71 * @brief tmr interrupt select type
72 * @{
73 */
74
75 #define TMR_OVF_INT ((uint32_t)0x000001) /*!< tmr interrupt overflow */
76 #define TMR_C1_INT ((uint32_t)0x000002) /*!< tmr interrupt channel 1 */
77 #define TMR_C2_INT ((uint32_t)0x000004) /*!< tmr interrupt channel 2 */
78 #define TMR_C3_INT ((uint32_t)0x000008) /*!< tmr interrupt channel 3 */
79 #define TMR_C4_INT ((uint32_t)0x000010) /*!< tmr interrupt channel 4 */
80 #define TMR_HALL_INT ((uint32_t)0x000020) /*!< tmr interrupt hall */
81 #define TMR_TRIGGER_INT ((uint32_t)0x000040) /*!< tmr interrupt trigger */
82 #define TMR_BRK_INT ((uint32_t)0x000080) /*!< tmr interrupt brake */
83
84 /**
85 * @}
86 */
87
88 /** @defgroup TMR_exported_types
89 * @{
90 */
91
92 /**
93 * @brief tmr clock division type
94 */
95 typedef enum
96 {
97 TMR_CLOCK_DIV1 = 0x00, /*!< tmr clock division 1 */
98 TMR_CLOCK_DIV2 = 0x01, /*!< tmr clock division 2 */
99 TMR_CLOCK_DIV4 = 0x02 /*!< tmr clock division 4 */
100 } tmr_clock_division_type;
101
102 /**
103 * @brief tmr counter mode type
104 */
105 typedef enum
106 {
107 TMR_COUNT_UP = 0x00, /*!< tmr counter mode up */
108 TMR_COUNT_DOWN = 0x01, /*!< tmr counter mode down */
109 TMR_COUNT_TWO_WAY_1 = 0x02, /*!< tmr counter mode two way 1 */
110 TMR_COUNT_TWO_WAY_2 = 0x04, /*!< tmr counter mode two way 2 */
111 TMR_COUNT_TWO_WAY_3 = 0x06 /*!< tmr counter mode two way 3 */
112 } tmr_count_mode_type;
113
114 /**
115 * @brief tmr primary mode select type
116 */
117 typedef enum
118 {
119 TMR_PRIMARY_SEL_RESET = 0x00, /*!< tmr primary mode select reset */
120 TMR_PRIMARY_SEL_ENABLE = 0x01, /*!< tmr primary mode select enable */
121 TMR_PRIMARY_SEL_OVERFLOW = 0x02, /*!< tmr primary mode select overflow */
122 TMR_PRIMARY_SEL_COMPARE = 0x03, /*!< tmr primary mode select compare */
123 TMR_PRIMARY_SEL_C1ORAW = 0x04, /*!< tmr primary mode select c1oraw */
124 TMR_PRIMARY_SEL_C2ORAW = 0x05, /*!< tmr primary mode select c2oraw */
125 TMR_PRIMARY_SEL_C3ORAW = 0x06, /*!< tmr primary mode select c3oraw */
126 TMR_PRIMARY_SEL_C4ORAW = 0x07 /*!< tmr primary mode select c4oraw */
127 } tmr_primary_select_type;
128
129 /**
130 * @brief tmr subordinate mode input select type
131 */
132 typedef enum
133 {
134 TMR_SUB_INPUT_SEL_IS0 = 0x00, /*!< subordinate mode input select is0 */
135 TMR_SUB_INPUT_SEL_IS1 = 0x01, /*!< subordinate mode input select is1 */
136 TMR_SUB_INPUT_SEL_IS2 = 0x02, /*!< subordinate mode input select is2 */
137 TMR_SUB_INPUT_SEL_IS3 = 0x03, /*!< subordinate mode input select is3 */
138 TMR_SUB_INPUT_SEL_C1INC = 0x04, /*!< subordinate mode input select c1inc */
139 TMR_SUB_INPUT_SEL_C1DF1 = 0x05, /*!< subordinate mode input select c1df1 */
140 TMR_SUB_INPUT_SEL_C2DF2 = 0x06, /*!< subordinate mode input select c2df2 */
141 TMR_SUB_INPUT_SEL_EXTIN = 0x07 /*!< subordinate mode input select extin */
142 } sub_tmr_input_sel_type;
143
144 /**
145 * @brief tmr subordinate mode select type
146 */
147 typedef enum
148 {
149 TMR_SUB_MODE_DIABLE = 0x00, /*!< subordinate mode disable */
150 TMR_SUB_ENCODER_MODE_A = 0x01, /*!< subordinate mode select encoder mode a */
151 TMR_SUB_ENCODER_MODE_B = 0x02, /*!< subordinate mode select encoder mode b */
152 TMR_SUB_ENCODER_MODE_C = 0x03, /*!< subordinate mode select encoder mode c */
153 TMR_SUB_RESET_MODE = 0x04, /*!< subordinate mode select reset */
154 TMR_SUB_HANG_MODE = 0x05, /*!< subordinate mode select hang */
155 TMR_SUB_TRIGGER_MODE = 0x06, /*!< subordinate mode select trigger */
156 TMR_SUB_EXTERNAL_CLOCK_MODE_A = 0x07 /*!< subordinate mode external clock mode a */
157 } tmr_sub_mode_select_type;
158
159 /**
160 * @brief tmr encoder mode type
161 */
162 typedef enum
163 {
164 TMR_ENCODER_MODE_A = TMR_SUB_ENCODER_MODE_A, /*!< tmr encoder mode a */
165 TMR_ENCODER_MODE_B = TMR_SUB_ENCODER_MODE_B, /*!< tmr encoder mode b */
166 TMR_ENCODER_MODE_C = TMR_SUB_ENCODER_MODE_C /*!< tmr encoder mode c */
167 } tmr_encoder_mode_type;
168
169 /**
170 * @brief tmr output control mode type
171 */
172 typedef enum
173 {
174 TMR_OUTPUT_CONTROL_OFF = 0x00, /*!< tmr output control mode off */
175 TMR_OUTPUT_CONTROL_HIGH = 0x01, /*!< tmr output control mode high */
176 TMR_OUTPUT_CONTROL_LOW = 0x02, /*!< tmr output control mode low */
177 TMR_OUTPUT_CONTROL_SWITCH = 0x03, /*!< tmr output control mode switch */
178 TMR_OUTPUT_CONTROL_FORCE_LOW = 0x04, /*!< tmr output control mode force low */
179 TMR_OUTPUT_CONTROL_FORCE_HIGH = 0x05, /*!< tmr output control mode force high */
180 TMR_OUTPUT_CONTROL_PWM_MODE_A = 0x06, /*!< tmr output control mode pwm a */
181 TMR_OUTPUT_CONTROL_PWM_MODE_B = 0x07 /*!< tmr output control mode pwm b */
182 } tmr_output_control_mode_type;
183
184 /**
185 * @brief tmr force output type
186 */
187 typedef enum
188 {
189 TMR_FORCE_OUTPUT_HIGH = TMR_OUTPUT_CONTROL_FORCE_HIGH, /*!< tmr force output high */
190 TMR_FORCE_OUTPUT_LOW = TMR_OUTPUT_CONTROL_FORCE_LOW /*!< tmr force output low */
191 } tmr_force_output_type;
192
193 /**
194 * @brief tmr output channel polarity type
195 */
196 typedef enum
197 {
198 TMR_OUTPUT_ACTIVE_HIGH = 0x00, /*!< tmr output channel polarity high */
199 TMR_OUTPUT_ACTIVE_LOW = 0x01 /*!< tmr output channel polarity low */
200 } tmr_output_polarity_type;
201
202 /**
203 * @brief tmr input channel polarity type
204 */
205 typedef enum
206 {
207 TMR_INPUT_RISING_EDGE = 0x00, /*!< tmr input channel polarity rising */
208 TMR_INPUT_FALLING_EDGE = 0x01, /*!< tmr input channel polarity falling */
209 TMR_INPUT_BOTH_EDGE = 0x03 /*!< tmr input channel polarity both edge */
210 } tmr_input_polarity_type;
211
212 /**
213 * @brief tmr channel select type
214 */
215 typedef enum
216 {
217 TMR_SELECT_CHANNEL_1 = 0x00, /*!< tmr channel select channel 1 */
218 TMR_SELECT_CHANNEL_1C = 0x01, /*!< tmr channel select channel 1 complementary */
219 TMR_SELECT_CHANNEL_2 = 0x02, /*!< tmr channel select channel 2 */
220 TMR_SELECT_CHANNEL_2C = 0x03, /*!< tmr channel select channel 2 complementary */
221 TMR_SELECT_CHANNEL_3 = 0x04, /*!< tmr channel select channel 3 */
222 TMR_SELECT_CHANNEL_3C = 0x05, /*!< tmr channel select channel 3 complementary */
223 TMR_SELECT_CHANNEL_4 = 0x06, /*!< tmr channel select channel 4 */
224 TMR_SELECT_CHANNEL_5 = 0x07 /*!< tmr channel select channel 5 */
225 } tmr_channel_select_type;
226
227 /**
228 * @brief tmr channel1 input connected type
229 */
230 typedef enum
231 {
232 TMR_CHANEL1_CONNECTED_C1IRAW = 0x00, /*!< channel1 pins is only connected to C1IRAW input */
233 TMR_CHANEL1_2_3_CONNECTED_C1IRAW_XOR = 0x01 /*!< channel1/2/3 pins are connected to C1IRAW input after xored */
234 } tmr_channel1_input_connected_type;
235
236 /**
237 * @brief tmr input channel mapped type channel direction
238 */
239 typedef enum
240 {
241 TMR_CC_CHANNEL_MAPPED_DIRECT = 0x01, /*!< channel is configured as input, mapped direct */
242 TMR_CC_CHANNEL_MAPPED_INDIRECT = 0x02, /*!< channel is configured as input, mapped indirect */
243 TMR_CC_CHANNEL_MAPPED_STI = 0x03 /*!< channel is configured as input, mapped trc */
244 } tmr_input_direction_mapped_type;
245
246 /**
247 * @brief tmr input divider type
248 */
249 typedef enum
250 {
251 TMR_CHANNEL_INPUT_DIV_1 = 0x00, /*!< tmr channel input divider 1 */
252 TMR_CHANNEL_INPUT_DIV_2 = 0x01, /*!< tmr channel input divider 2 */
253 TMR_CHANNEL_INPUT_DIV_4 = 0x02, /*!< tmr channel input divider 4 */
254 TMR_CHANNEL_INPUT_DIV_8 = 0x03 /*!< tmr channel input divider 8 */
255 } tmr_channel_input_divider_type;
256
257 /**
258 * @brief tmr dma request source select type
259 */
260 typedef enum
261 {
262 TMR_DMA_REQUEST_BY_CHANNEL = 0x00, /*!< tmr dma request source select channel */
263 TMR_DMA_REQUEST_BY_OVERFLOW = 0x01 /*!< tmr dma request source select overflow */
264 } tmr_dma_request_source_type;
265
266 /**
267 * @brief tmr dma request type
268 */
269 typedef enum
270 {
271 TMR_OVERFLOW_DMA_REQUEST = 0x00000100, /*!< tmr dma request select overflow */
272 TMR_C1_DMA_REQUEST = 0x00000200, /*!< tmr dma request select channel 1 */
273 TMR_C2_DMA_REQUEST = 0x00000400, /*!< tmr dma request select channel 2 */
274 TMR_C3_DMA_REQUEST = 0x00000800, /*!< tmr dma request select channel 3 */
275 TMR_C4_DMA_REQUEST = 0x00001000, /*!< tmr dma request select channel 4 */
276 TMR_HALL_DMA_REQUEST = 0x00002000, /*!< tmr dma request select hall */
277 TMR_TRIGGER_DMA_REQUEST = 0x00004000 /*!< tmr dma request select trigger */
278 } tmr_dma_request_type;
279
280 /**
281 * @brief tmr event triggered by software type
282 */
283 typedef enum
284 {
285 TMR_OVERFLOW_SWTRIG = 0x00000001, /*!< tmr event triggered by software of overflow */
286 TMR_C1_SWTRIG = 0x00000002, /*!< tmr event triggered by software of channel 1 */
287 TMR_C2_SWTRIG = 0x00000004, /*!< tmr event triggered by software of channel 2 */
288 TMR_C3_SWTRIG = 0x00000008, /*!< tmr event triggered by software of channel 3 */
289 TMR_C4_SWTRIG = 0x00000010, /*!< tmr event triggered by software of channel 4 */
290 TMR_HALL_SWTRIG = 0x00000020, /*!< tmr event triggered by software of hall */
291 TMR_TRIGGER_SWTRIG = 0x00000040, /*!< tmr event triggered by software of trigger */
292 TMR_BRK_SWTRIG = 0x00000080 /*!< tmr event triggered by software of brake */
293 }tmr_event_trigger_type;
294
295 /**
296 * @brief tmr polarity active type
297 */
298 typedef enum
299 {
300 TMR_POLARITY_ACTIVE_HIGH = 0x00, /*!< tmr polarity active high */
301 TMR_POLARITY_ACTIVE_LOW = 0x01, /*!< tmr polarity active low */
302 TMR_POLARITY_ACTIVE_BOTH = 0x02 /*!< tmr polarity active both high ande low */
303 }tmr_polarity_active_type;
304
305 /**
306 * @brief tmr external signal divider type
307 */
308 typedef enum
309 {
310 TMR_ES_FREQUENCY_DIV_1 = 0x00, /*!< tmr external signal frequency divider 1 */
311 TMR_ES_FREQUENCY_DIV_2 = 0x01, /*!< tmr external signal frequency divider 2 */
312 TMR_ES_FREQUENCY_DIV_4 = 0x02, /*!< tmr external signal frequency divider 4 */
313 TMR_ES_FREQUENCY_DIV_8 = 0x03 /*!< tmr external signal frequency divider 8 */
314 }tmr_external_signal_divider_type;
315
316 /**
317 * @brief tmr external signal polarity type
318 */
319 typedef enum
320 {
321 TMR_ES_POLARITY_NON_INVERTED = 0x00, /*!< tmr external signal polarity non-inerted */
322 TMR_ES_POLARITY_INVERTED = 0x01 /*!< tmr external signal polarity inerted */
323 }tmr_external_signal_polarity_type;
324
325 /**
326 * @brief tmr dma transfer length type
327 */
328 typedef enum
329 {
330 TMR_DMA_TRANSFER_1BYTE = 0x00, /*!< tmr dma transfer length 1 byte */
331 TMR_DMA_TRANSFER_2BYTES = 0x01, /*!< tmr dma transfer length 2 bytes */
332 TMR_DMA_TRANSFER_3BYTES = 0x02, /*!< tmr dma transfer length 3 bytes */
333 TMR_DMA_TRANSFER_4BYTES = 0x03, /*!< tmr dma transfer length 4 bytes */
334 TMR_DMA_TRANSFER_5BYTES = 0x04, /*!< tmr dma transfer length 5 bytes */
335 TMR_DMA_TRANSFER_6BYTES = 0x05, /*!< tmr dma transfer length 6 bytes */
336 TMR_DMA_TRANSFER_7BYTES = 0x06, /*!< tmr dma transfer length 7 bytes */
337 TMR_DMA_TRANSFER_8BYTES = 0x07, /*!< tmr dma transfer length 8 bytes */
338 TMR_DMA_TRANSFER_9BYTES = 0x08, /*!< tmr dma transfer length 9 bytes */
339 TMR_DMA_TRANSFER_10BYTES = 0x09, /*!< tmr dma transfer length 10 bytes */
340 TMR_DMA_TRANSFER_11BYTES = 0x0A, /*!< tmr dma transfer length 11 bytes */
341 TMR_DMA_TRANSFER_12BYTES = 0x0B, /*!< tmr dma transfer length 12 bytes */
342 TMR_DMA_TRANSFER_13BYTES = 0x0C, /*!< tmr dma transfer length 13 bytes */
343 TMR_DMA_TRANSFER_14BYTES = 0x0D, /*!< tmr dma transfer length 14 bytes */
344 TMR_DMA_TRANSFER_15BYTES = 0x0E, /*!< tmr dma transfer length 15 bytes */
345 TMR_DMA_TRANSFER_16BYTES = 0x0F, /*!< tmr dma transfer length 16 bytes */
346 TMR_DMA_TRANSFER_17BYTES = 0x10, /*!< tmr dma transfer length 17 bytes */
347 TMR_DMA_TRANSFER_18BYTES = 0x11 /*!< tmr dma transfer length 18 bytes */
348 }tmr_dma_transfer_length_type;
349
350 /**
351 * @brief tmr dma base address type
352 */
353 typedef enum
354 {
355 TMR_CTRL1_ADDRESS = 0x0000, /*!< tmr dma base address ctrl1 */
356 TMR_CTRL2_ADDRESS = 0x0001, /*!< tmr dma base address ctrl2 */
357 TMR_STCTRL_ADDRESS = 0x0002, /*!< tmr dma base address stctrl */
358 TMR_IDEN_ADDRESS = 0x0003, /*!< tmr dma base address iden */
359 TMR_ISTS_ADDRESS = 0x0004, /*!< tmr dma base address ists */
360 TMR_SWEVT_ADDRESS = 0x0005, /*!< tmr dma base address swevt */
361 TMR_CM1_ADDRESS = 0x0006, /*!< tmr dma base address cm1 */
362 TMR_CM2_ADDRESS = 0x0007, /*!< tmr dma base address cm2 */
363 TMR_CCTRL_ADDRESS = 0x0008, /*!< tmr dma base address cctrl */
364 TMR_CVAL_ADDRESS = 0x0009, /*!< tmr dma base address cval */
365 TMR_DIV_ADDRESS = 0x000A, /*!< tmr dma base address div */
366 TMR_PR_ADDRESS = 0x000B, /*!< tmr dma base address pr */
367 TMR_RPR_ADDRESS = 0x000C, /*!< tmr dma base address rpr */
368 TMR_C1DT_ADDRESS = 0x000D, /*!< tmr dma base address c1dt */
369 TMR_C2DT_ADDRESS = 0x000E, /*!< tmr dma base address c2dt */
370 TMR_C3DT_ADDRESS = 0x000F, /*!< tmr dma base address c3dt */
371 TMR_C4DT_ADDRESS = 0x0010, /*!< tmr dma base address c4dt */
372 TMR_BRK_ADDRESS = 0x0011, /*!< tmr dma base address brake */
373 TMR_DMACTRL_ADDRESS = 0x0012 /*!< tmr dma base address dmactrl */
374 }tmr_dma_address_type;
375
376 /**
377 * @brief tmr brk polarity type
378 */
379 typedef enum
380 {
381 TMR_BRK_INPUT_ACTIVE_LOW = 0x00, /*!< tmr brk input channel active low */
382 TMR_BRK_INPUT_ACTIVE_HIGH = 0x01 /*!< tmr brk input channel active high */
383 }tmr_brk_polarity_type;
384
385 /**
386 * @brief tmr write protect level type
387 */
388 typedef enum
389 {
390 TMR_WP_OFF = 0x00, /*!< tmr write protect off */
391 TMR_WP_LEVEL_3 = 0x01, /*!< tmr write protect level 3 */
392 TMR_WP_LEVEL_2 = 0x02, /*!< tmr write protect level 2 */
393 TMR_WP_LEVEL_1 = 0x03 /*!< tmr write protect level 1 */
394 }tmr_wp_level_type;
395
396 /**
397 * @brief tmr input remap type
398 */
399 typedef enum
400 {
401 TMR2_TMR8TRGOUT_TMR5_GPIO = 0x00, /*!< tmr2 input remap to tmr8_trgout or tmr5 remap to gpio */
402 TMR2_PTP_TMR5_LICK = 0x01, /*!< tmr2 input remap to ptp or tmr5 remap to lick */
403 TMR2_OTG1FS_TMR5_LEXT = 0x02, /*!< tmr2 input remap to otg1fs or tmr5 remap to lext */
404 TMR2_OTG2FS_TMR5_ERTC = 0x03 /*!< tmr2 input remap to otg2fs or tmr5 remap to ertc */
405 }tmr_input_remap_type ;
406 /**
407
408 * @brief tmr output config type
409 */
410 typedef struct
411 {
412 tmr_output_control_mode_type oc_mode; /*!< output channel mode */
413 confirm_state oc_idle_state; /*!< output channel idle state */
414 confirm_state occ_idle_state; /*!< output channel complementary idle state */
415 tmr_output_polarity_type oc_polarity; /*!< output channel polarity */
416 tmr_output_polarity_type occ_polarity; /*!< output channel complementary polarity */
417 confirm_state oc_output_state; /*!< output channel enable */
418 confirm_state occ_output_state; /*!< output channel complementary enable */
419 } tmr_output_config_type;
420
421 /**
422 * @brief tmr input capture config type
423 */
424 typedef struct
425 {
426 tmr_channel_select_type input_channel_select; /*!< tmr input channel select */
427 tmr_input_polarity_type input_polarity_select; /*!< tmr input polarity select */
428 tmr_input_direction_mapped_type input_mapped_select; /*!< tmr channel mapped direct or indirect */
429 uint8_t input_filter_value; /*!< tmr channel filter value */
430 } tmr_input_config_type;
431
432 /**
433 * @brief tmr brkdt config type
434 */
435 typedef struct
436 {
437 uint8_t deadtime; /*!< dead-time generator setup */
438 tmr_brk_polarity_type brk_polarity; /*!< tmr brake polarity */
439 tmr_wp_level_type wp_level; /*!< write protect configuration */
440 confirm_state auto_output_enable; /*!< automatic output enable */
441 confirm_state fcsoen_state; /*!< frozen channel status when output enable */
442 confirm_state fcsodis_state; /*!< frozen channel status when output disable */
443 confirm_state brk_enable; /*!< tmr brk enale */
444 } tmr_brkdt_config_type;
445
446 /**
447 * @brief type define tmr register all
448 */
449 typedef struct
450 {
451 /**
452 * @brief tmr ctrl1 register, offset:0x00
453 */
454 union
455 {
456 __IO uint32_t ctrl1;
457 struct
458 {
459 __IO uint32_t tmren : 1; /* [0] */
460 __IO uint32_t ovfen : 1; /* [1] */
461 __IO uint32_t ovfs : 1; /* [2] */
462 __IO uint32_t ocmen : 1; /* [3] */
463 __IO uint32_t cnt_dir : 3; /* [6:4] */
464 __IO uint32_t prben : 1; /* [7] */
465 __IO uint32_t clkdiv : 2; /* [9:8] */
466 __IO uint32_t pmen : 1; /* [10] */
467 __IO uint32_t reserved1 : 21;/* [31:11] */
468 } ctrl1_bit;
469 };
470
471 /**
472 * @brief tmr ctrl2 register, offset:0x04
473 */
474 union
475 {
476 __IO uint32_t ctrl2;
477 struct
478 {
479 __IO uint32_t cbctrl : 1; /* [0] */
480 __IO uint32_t reserved1 : 1; /* [1] */
481 __IO uint32_t ccfs : 1; /* [2] */
482 __IO uint32_t drs : 1; /* [3] */
483 __IO uint32_t ptos : 3; /* [6:4] */
484 __IO uint32_t c1insel : 1; /* [7] */
485 __IO uint32_t c1ios : 1; /* [8] */
486 __IO uint32_t c1cios : 1; /* [9] */
487 __IO uint32_t c2ios : 1; /* [10] */
488 __IO uint32_t c2cios : 1; /* [11] */
489 __IO uint32_t c3ios : 1; /* [12] */
490 __IO uint32_t c3cios : 1; /* [13] */
491 __IO uint32_t c4ios : 1; /* [14] */
492 __IO uint32_t reserved2 : 16;/* [30:15] */
493 __IO uint32_t trgout2en : 1; /* [31] */
494 } ctrl2_bit;
495 };
496
497 /**
498 * @brief tmr smc register, offset:0x08
499 */
500 union
501 {
502 __IO uint32_t stctrl;
503 struct
504 {
505 __IO uint32_t smsel : 3; /* [2:0] */
506 __IO uint32_t reserved1 : 1; /* [3] */
507 __IO uint32_t stis : 3; /* [6:4] */
508 __IO uint32_t sts : 1; /* [7] */
509 __IO uint32_t esf : 4; /* [11:8] */
510 __IO uint32_t esdiv : 2; /* [13:12] */
511 __IO uint32_t ecmben : 1; /* [14] */
512 __IO uint32_t esp : 1; /* [15] */
513 __IO uint32_t reserved2 : 16;/* [31:16] */
514 } stctrl_bit;
515 };
516
517 /**
518 * @brief tmr die register, offset:0x0C
519 */
520 union
521 {
522 __IO uint32_t iden;
523 struct
524 {
525 __IO uint32_t ovfien : 1; /* [0] */
526 __IO uint32_t c1ien : 1; /* [1] */
527 __IO uint32_t c2ien : 1; /* [2] */
528 __IO uint32_t c3ien : 1; /* [3] */
529 __IO uint32_t c4ien : 1; /* [4] */
530 __IO uint32_t hallien : 1; /* [5] */
531 __IO uint32_t tien : 1; /* [6] */
532 __IO uint32_t brkie : 1; /* [7] */
533 __IO uint32_t ovfden : 1; /* [8] */
534 __IO uint32_t c1den : 1; /* [9] */
535 __IO uint32_t c2den : 1; /* [10] */
536 __IO uint32_t c3den : 1; /* [11] */
537 __IO uint32_t c4den : 1; /* [12] */
538 __IO uint32_t hallde : 1; /* [13] */
539 __IO uint32_t tden : 1; /* [14] */
540 __IO uint32_t reserved1 : 17;/* [31:15] */
541 } iden_bit;
542 };
543
544 /**
545 * @brief tmr ists register, offset:0x10
546 */
547 union
548 {
549 __IO uint32_t ists;
550 struct
551 {
552 __IO uint32_t ovfif : 1; /* [0] */
553 __IO uint32_t c1if : 1; /* [1] */
554 __IO uint32_t c2if : 1; /* [2] */
555 __IO uint32_t c3if : 1; /* [3] */
556 __IO uint32_t c4if : 1; /* [4] */
557 __IO uint32_t hallif : 1; /* [5] */
558 __IO uint32_t trgif : 1; /* [6] */
559 __IO uint32_t brkif : 1; /* [7] */
560 __IO uint32_t reserved1 : 1; /* [8] */
561 __IO uint32_t c1rf : 1; /* [9] */
562 __IO uint32_t c2rf : 1; /* [10] */
563 __IO uint32_t c3rf : 1; /* [11] */
564 __IO uint32_t c4rf : 1; /* [12] */
565 __IO uint32_t reserved2 : 19;/* [31:13] */
566 } ists_bit;
567 };
568
569 /**
570 * @brief tmr eveg register, offset:0x14
571 */
572 union
573 {
574 __IO uint32_t swevt;
575 struct
576 {
577 __IO uint32_t ovfswtr : 1; /* [0] */
578 __IO uint32_t c1swtr : 1; /* [1] */
579 __IO uint32_t c2swtr : 1; /* [2] */
580 __IO uint32_t c3swtr : 1; /* [3] */
581 __IO uint32_t c4swtr : 1; /* [4] */
582 __IO uint32_t hallswtr : 1; /* [5] */
583 __IO uint32_t trgswtr : 1; /* [6] */
584 __IO uint32_t brkswtr : 1; /* [7] */
585 __IO uint32_t reserved : 24;/* [31:8] */
586 } swevt_bit;
587 };
588
589 /**
590 * @brief tmr ccm1 register, offset:0x18
591 */
592 union
593 {
594 __IO uint32_t cm1;
595
596 /**
597 * @brief channel mode
598 */
599 struct
600 {
601 __IO uint32_t c1c : 2; /* [1:0] */
602 __IO uint32_t c1oien : 1; /* [2] */
603 __IO uint32_t c1oben : 1; /* [3] */
604 __IO uint32_t c1octrl : 3; /* [6:4] */
605 __IO uint32_t c1osen : 1; /* [7] */
606 __IO uint32_t c2c : 2; /* [9:8] */
607 __IO uint32_t c2oien : 1; /* [10] */
608 __IO uint32_t c2oben : 1; /* [11] */
609 __IO uint32_t c2octrl : 3; /* [14:12] */
610 __IO uint32_t c2osen : 1; /* [15] */
611 __IO uint32_t reserved1 : 16;/* [31:16] */
612 } cm1_output_bit;
613
614 /**
615 * @brief input capture mode
616 */
617 struct
618 {
619 __IO uint32_t c1c : 2; /* [1:0] */
620 __IO uint32_t c1idiv : 2; /* [3:2] */
621 __IO uint32_t c1df : 4; /* [7:4] */
622 __IO uint32_t c2c : 2; /* [9:8] */
623 __IO uint32_t c2idiv : 2; /* [11:10] */
624 __IO uint32_t c2df : 4; /* [15:12] */
625 __IO uint32_t reserved1 : 16;/* [31:16] */
626 } cm1_input_bit;
627 };
628
629 /**
630 * @brief tmr ccm2 register, offset:0x1C
631 */
632 union
633 {
634 __IO uint32_t cm2;
635
636 /**
637 * @brief channel mode
638 */
639 struct
640 {
641 __IO uint32_t c3c : 2; /* [1:0] */
642 __IO uint32_t c3oien : 1; /* [2] */
643 __IO uint32_t c3oben : 1; /* [3] */
644 __IO uint32_t c3octrl : 3; /* [6:4] */
645 __IO uint32_t c3osen : 1; /* [7] */
646 __IO uint32_t c4c : 2; /* [9:8] */
647 __IO uint32_t c4oien : 1; /* [10] */
648 __IO uint32_t c4oben : 1; /* [11] */
649 __IO uint32_t c4octrl : 3; /* [14:12] */
650 __IO uint32_t c4osen : 1; /* [15] */
651 __IO uint32_t reserved1 : 16;/* [31:16] */
652 } cm2_output_bit;
653
654 /**
655 * @brief input capture mode
656 */
657 struct
658 {
659 __IO uint32_t c3c : 2; /* [1:0] */
660 __IO uint32_t c3idiv : 2; /* [3:2] */
661 __IO uint32_t c3df : 4; /* [7:4] */
662 __IO uint32_t c4c : 2; /* [9:8] */
663 __IO uint32_t c4idiv : 2; /* [11:10] */
664 __IO uint32_t c4df : 4; /* [15:12] */
665 __IO uint32_t reserved1 : 16;/* [31:16] */
666 } cm2_input_bit;
667 };
668
669 /**
670 * @brief tmr cce register, offset:0x20
671 */
672 union
673 {
674 uint32_t cctrl;
675 struct
676 {
677 __IO uint32_t c1en : 1; /* [0] */
678 __IO uint32_t c1p : 1; /* [1] */
679 __IO uint32_t c1cen : 1; /* [2] */
680 __IO uint32_t c1cp : 1; /* [3] */
681 __IO uint32_t c2en : 1; /* [4] */
682 __IO uint32_t c2p : 1; /* [5] */
683 __IO uint32_t c2cen : 1; /* [6] */
684 __IO uint32_t c2cp : 1; /* [7] */
685 __IO uint32_t c3en : 1; /* [8] */
686 __IO uint32_t c3p : 1; /* [9] */
687 __IO uint32_t c3cen : 1; /* [10] */
688 __IO uint32_t c3cp : 1; /* [11] */
689 __IO uint32_t c4en : 1; /* [12] */
690 __IO uint32_t c4p : 1; /* [13] */
691 __IO uint32_t reserved1 : 18;/* [31:14] */
692 } cctrl_bit;
693 };
694
695 /**
696 * @brief tmr cnt register, offset:0x24
697 */
698 union
699 {
700 __IO uint32_t cval;
701 struct
702 {
703 __IO uint32_t cval : 32;/* [31:0] */
704 } cval_bit;
705 };
706
707 /**
708 * @brief tmr div, offset:0x28
709 */
710 union
711 {
712 __IO uint32_t div;
713 struct
714 {
715 __IO uint32_t div : 16;/* [15:0] */
716 __IO uint32_t reserved1 : 16;/* [31:16] */
717 } div_bit;
718 };
719
720 /**
721 * @brief tmr pr register, offset:0x2C
722 */
723 union
724 {
725 __IO uint32_t pr;
726 struct
727 {
728 __IO uint32_t pr : 32;/* [31:0] */
729 } pr_bit;
730 };
731
732 /**
733 * @brief tmr rpr register, offset:0x30
734 */
735 union
736 {
737 __IO uint32_t rpr;
738 struct
739 {
740 __IO uint32_t rpr : 16;/* [15:0] */
741 __IO uint32_t reserved1 : 16;/* [31:16] */
742 } rpr_bit;
743 };
744
745 /**
746 * @brief tmr c1dt register, offset:0x34
747 */
748 union
749 {
750 uint32_t c1dt;
751 struct
752 {
753 __IO uint32_t c1dt : 32;/* [31:0] */
754 } c1dt_bit;
755 };
756
757 /**
758 * @brief tmr c2dt register, offset:0x38
759 */
760 union
761 {
762 uint32_t c2dt;
763 struct
764 {
765 __IO uint32_t c2dt : 32;/* [31:0] */
766 } c2dt_bit;
767 };
768
769 /**
770 * @brief tmr c3dt register, offset:0x3C
771 */
772 union
773 {
774 __IO uint32_t c3dt;
775 struct
776 {
777 __IO uint32_t c3dt : 32;/* [31:0] */
778 } c3dt_bit;
779 };
780
781 /**
782 * @brief tmr c4dt register, offset:0x40
783 */
784 union
785 {
786 __IO uint32_t c4dt;
787 struct
788 {
789 __IO uint32_t c4dt : 32;/* [31:0] */
790 } c4dt_bit;
791 };
792
793 /**
794 * @brief tmr brk register, offset:0x44
795 */
796 union
797 {
798 __IO uint32_t brk;
799 struct
800 {
801 __IO uint32_t dtc : 8; /* [7:0] */
802 __IO uint32_t wpc : 2; /* [9:8] */
803 __IO uint32_t fcsodis : 1; /* [10] */
804 __IO uint32_t fcsoen : 1; /* [11] */
805 __IO uint32_t brken : 1; /* [12] */
806 __IO uint32_t brkv : 1; /* [13] */
807 __IO uint32_t aoen : 1; /* [14] */
808 __IO uint32_t oen : 1; /* [15] */
809 __IO uint32_t reserved1 : 16; /* [31:16] */
810 } brk_bit;
811 };
812 /**
813 * @brief tmr dmactrl register, offset:0x48
814 */
815 union
816 {
817 __IO uint32_t dmactrl;
818 struct
819 {
820 __IO uint32_t addr : 5; /* [4:0] */
821 __IO uint32_t reserved1 : 3; /* [7:5] */
822 __IO uint32_t dtb : 5; /* [12:8] */
823 __IO uint32_t reserved2 : 19;/* [31:13] */
824 } dmactrl_bit;
825 };
826
827 /**
828 * @brief tmr dmadt register, offset:0x4C
829 */
830 union
831 {
832 __IO uint32_t dmadt;
833 struct
834 {
835 __IO uint32_t dmadt : 16;/* [15:0] */
836 __IO uint32_t reserved1 : 16;/* [31:16] */
837 } dmadt_bit;
838 };
839
840 /**
841 * @brief tmr rmp register, offset:0x50
842 */
843 union
844 {
845 __IO uint32_t rmp;
846 struct
847 {
848 __IO uint32_t reserved1 : 6; /* [5:0] */
849 __IO uint32_t tmr5_ch4_irmp : 2; /* [7:6] */
850 __IO uint32_t reserved2 : 2; /* [9:8] */
851 __IO uint32_t tmr2_ch1_irmp : 2; /* [11:10] */
852 __IO uint32_t reserved3 : 20;/* [31:16] */
853 } rmp_bit;
854 };
855
856 /**
857 * @brief tmr reserved0 register, offset:0x54-0x6C
858 */
859 __IO uint32_t reserved1[7];
860
861 /**
862 * @brief tmr cm3 register, offset:0x70
863 */
864 union
865 {
866 __IO uint32_t cm3;
867 struct
868 {
869 __IO uint32_t reserved1 : 2; /* [1:0] */
870 __IO uint32_t c5oien : 1; /* [2] */
871 __IO uint32_t c5oben : 1; /* [3] */
872 __IO uint32_t c5octrl : 3; /* [6:4] */
873 __IO uint32_t c5osen : 1; /* [7] */
874 __IO uint32_t reserved2 : 24;/* [31:8] */
875 } cm3_output_bit;
876 };
877
878 /**
879 * @brief tmr c5dt register, offset:0x74
880 */
881 union
882 {
883 __IO uint32_t c5dt;
884 struct
885 {
886 __IO uint32_t c5dt : 32;/* [31:0] */
887 } c5dt_bit;
888 };
889 } tmr_type;
890
891 /**
892 * @}
893 */
894
895 #define TMR1 ((tmr_type *) TMR1_BASE)
896 #define TMR2 ((tmr_type *) TMR2_BASE)
897 #define TMR3 ((tmr_type *) TMR3_BASE)
898 #define TMR4 ((tmr_type *) TMR4_BASE)
899 #define TMR5 ((tmr_type *) TMR5_BASE)
900 #define TMR6 ((tmr_type *) TMR6_BASE)
901 #define TMR7 ((tmr_type *) TMR7_BASE)
902 #define TMR8 ((tmr_type *) TMR8_BASE)
903 #define TMR9 ((tmr_type *) TMR9_BASE)
904 #define TMR10 ((tmr_type *) TMR10_BASE)
905 #define TMR11 ((tmr_type *) TMR11_BASE)
906 #define TMR12 ((tmr_type *) TMR12_BASE)
907 #define TMR13 ((tmr_type *) TMR13_BASE)
908 #define TMR14 ((tmr_type *) TMR14_BASE)
909 #define TMR20 ((tmr_type *) TMR20_BASE)
910
911 /** @defgroup TMR_exported_functions
912 * @{
913 */
914
915 void tmr_reset(tmr_type *tmr_x);
916 void tmr_counter_enable(tmr_type *tmr_x, confirm_state new_state);
917 void tmr_output_default_para_init(tmr_output_config_type *tmr_output_struct);
918 void tmr_input_default_para_init(tmr_input_config_type *tmr_input_struct);
919 void tmr_brkdt_default_para_init(tmr_brkdt_config_type *tmr_brkdt_struct);
920 void tmr_base_init(tmr_type* tmr_x, uint32_t tmr_pr, uint32_t tmr_div);
921 void tmr_clock_source_div_set(tmr_type *tmr_x, tmr_clock_division_type tmr_clock_div);
922 void tmr_cnt_dir_set(tmr_type *tmr_x, tmr_count_mode_type tmr_cnt_dir);
923 void tmr_repetition_counter_set(tmr_type *tmr_x, uint8_t tmr_rpr_value);
924 void tmr_counter_value_set(tmr_type *tmr_x, uint32_t tmr_cnt_value);
925 uint32_t tmr_counter_value_get(tmr_type *tmr_x);
926 void tmr_div_value_set(tmr_type *tmr_x, uint32_t tmr_div_value);
927 uint32_t tmr_div_value_get(tmr_type *tmr_x);
928 void tmr_output_channel_config(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
929 tmr_output_config_type *tmr_output_struct);
930 void tmr_output_channel_mode_select(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
931 tmr_output_control_mode_type oc_mode);
932 void tmr_period_value_set(tmr_type *tmr_x, uint32_t tmr_pr_value);
933 uint32_t tmr_period_value_get(tmr_type *tmr_x);
934 void tmr_channel_value_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
935 uint32_t tmr_channel_value);
936 uint32_t tmr_channel_value_get(tmr_type *tmr_x, tmr_channel_select_type tmr_channel);
937 void tmr_period_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
938 void tmr_output_channel_buffer_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
939 confirm_state new_state);
940 void tmr_output_channel_immediately_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
941 confirm_state new_state);
942 void tmr_output_channel_switch_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
943 confirm_state new_state);
944 void tmr_one_cycle_mode_enable(tmr_type *tmr_x, confirm_state new_state);
945 void tmr_32_bit_function_enable (tmr_type *tmr_x, confirm_state new_state);
946 void tmr_overflow_request_source_set(tmr_type *tmr_x, confirm_state new_state);
947 void tmr_overflow_event_disable(tmr_type *tmr_x, confirm_state new_state);
948 void tmr_input_channel_init(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
949 tmr_channel_input_divider_type divider_factor);
950 void tmr_channel_enable(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, confirm_state new_state);
951 void tmr_input_channel_filter_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
952 uint16_t filter_value);
953 void tmr_pwm_input_config(tmr_type *tmr_x, tmr_input_config_type *input_struct, \
954 tmr_channel_input_divider_type divider_factor);
955 void tmr_channel1_input_select(tmr_type *tmr_x, tmr_channel1_input_connected_type ch1_connect);
956 void tmr_input_channel_divider_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
957 tmr_channel_input_divider_type divider_factor);
958 void tmr_primary_mode_select(tmr_type *tmr_x, tmr_primary_select_type primary_mode);
959 void tmr_sub_mode_select(tmr_type *tmr_x, tmr_sub_mode_select_type sub_mode);
960 void tmr_channel_dma_select(tmr_type *tmr_x, tmr_dma_request_source_type cc_dma_select);
961 void tmr_hall_select(tmr_type *tmr_x, confirm_state new_state);
962 void tmr_channel_buffer_enable(tmr_type *tmr_x, confirm_state new_state);
963 void tmr_trgout2_enable(tmr_type *tmr_x, confirm_state new_state);
964 void tmr_trigger_input_select(tmr_type *tmr_x, sub_tmr_input_sel_type trigger_select);
965 void tmr_sub_sync_mode_set(tmr_type *tmr_x, confirm_state new_state);
966 void tmr_dma_request_enable(tmr_type *tmr_x, tmr_dma_request_type dma_request, confirm_state new_state);
967 void tmr_interrupt_enable(tmr_type *tmr_x, uint32_t tmr_interrupt, confirm_state new_state);
968 flag_status tmr_flag_get(tmr_type *tmr_x, uint32_t tmr_flag);
969 void tmr_flag_clear(tmr_type *tmr_x, uint32_t tmr_flag);
970 void tmr_event_sw_trigger(tmr_type *tmr_x, tmr_event_trigger_type tmr_event);
971 void tmr_output_enable(tmr_type *tmr_x, confirm_state new_state);
972 void tmr_internal_clock_set(tmr_type *tmr_x);
973 void tmr_output_channel_polarity_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
974 tmr_polarity_active_type oc_polarity);
975 void tmr_external_clock_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
976 tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
977 void tmr_external_clock_mode1_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
978 tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
979 void tmr_external_clock_mode2_config(tmr_type *tmr_x, tmr_external_signal_divider_type es_divide, \
980 tmr_external_signal_polarity_type es_polarity, uint16_t es_filter);
981 void tmr_encoder_mode_config(tmr_type *tmr_x, tmr_encoder_mode_type encoder_mode, tmr_input_polarity_type \
982 ic1_polarity, tmr_input_polarity_type ic2_polarity);
983 void tmr_force_output_set(tmr_type *tmr_x, tmr_channel_select_type tmr_channel, \
984 tmr_force_output_type force_output);
985 void tmr_dma_control_config(tmr_type *tmr_x, tmr_dma_transfer_length_type dma_length, \
986 tmr_dma_address_type dma_base_address);
987 void tmr_brkdt_config(tmr_type *tmr_x, tmr_brkdt_config_type *brkdt_struct);
988 void tmr_iremap_config(tmr_type *tmr_x, tmr_input_remap_type input_remap);
989
990 /**
991 * @}
992 */
993
994 /**
995 * @}
996 */
997
998 /**
999 * @}
1000 */
1001
1002 #ifdef __cplusplus
1003 }
1004 #endif
1005
1006 #endif
INAV: Navigation-enabled flight control software