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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / AT32F43x / Drivers / AT32F43x_StdPeriph_Driver / inc / at32f435_437_xmc.h
blob462594d90368676f170caa85e3198da3cda0af98
1 /**
2 **************************************************************************
3 * @file at32f435_437_xmc.h
4 * @version v2.1.0
5 * @date 2022-08-16
6 * @brief at32f435_437 xmc header file
7 **************************************************************************
8 * Copyright notice & Disclaimer
9 *
10 * The software Board Support Package (BSP) that is made available to
11 * download from Artery official website is the copyrighted work of Artery.
12 * Artery authorizes customers to use, copy, and distribute the BSP
13 * software and its related documentation for the purpose of design and
14 * development in conjunction with Artery microcontrollers. Use of the
15 * software is governed by this copyright notice and the following disclaimer.
16 *
17 * THIS SOFTWARE IS PROVIDED ON "AS IS" BASIS WITHOUT WARRANTIES,
18 * GUARANTEES OR REPRESENTATIONS OF ANY KIND. ARTERY EXPRESSLY DISCLAIMS,
19 * TO THE FULLEST EXTENT PERMITTED BY LAW, ALL EXPRESS, IMPLIED OR
20 * STATUTORY OR OTHER WARRANTIES, GUARANTEES OR REPRESENTATIONS,
21 * INCLUDING BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY,
22 * FITNESS FOR A PARTICULAR PURPOSE, OR NON-INFRINGEMENT.
23 *
24 **************************************************************************
25 */
26
27 /* Define to prevent recursive inclusion -------------------------------------*/
28 #ifndef __AT32F435_437_XMC_H
29 #define __AT32F435_437_XMC_H
30
31 #ifdef __cplusplus
32 extern "C" {
33 #endif
34
35
36 /* Includes ------------------------------------------------------------------*/
37 #include "at32f435_437.h"
38
39 /** @addtogroup AT32F435_437_periph_driver
40 * @{
41 */
42
43 /** @addtogroup XMC
44 * @{
45 */
46
47 /** @defgroup XMC_exported_types
48 * @{
49 */
50
51 /**
52 * @brief xmc data address bus multiplexing type
53 */
54 typedef enum
55 {
56 XMC_DATA_ADDR_MUX_DISABLE = 0x00000000, /*!< xmc address/data multiplexing disable */
57 XMC_DATA_ADDR_MUX_ENABLE = 0x00000002 /*!< xmc address/data multiplexing enable */
58 } xmc_data_addr_mux_type;
59
60 /**
61 * @brief xmc burst access mode type
62 */
63 typedef enum
64 {
65 XMC_BURST_MODE_DISABLE = 0x00000000, /*!< xmc burst mode disable */
66 XMC_BURST_MODE_ENABLE = 0x00000100 /*!< xmc burst mode enable */
67 } xmc_burst_access_mode_type;
68
69 /**
70 * @brief xmc asynchronous wait type
71 */
72 typedef enum
73 {
74 XMC_ASYN_WAIT_DISABLE = 0x00000000, /*!< xmc wait signal during asynchronous transfers disbale */
75 XMC_ASYN_WAIT_ENABLE = 0x00008000 /*!< xmc wait signal during asynchronous transfers enable */
76 } xmc_asyn_wait_type;
77
78 /**
79 * @brief xmc wrapped mode type
80 */
81 typedef enum
82 {
83 XMC_WRAPPED_MODE_DISABLE = 0x00000000, /*!< xmc direct wrapped burst is disbale */
84 XMC_WRAPPED_MODE_ENABLE = 0x00000400 /*!< xmc direct wrapped burst is enable */
85 } xmc_wrap_mode_type;
86
87 /**
88 * @brief xmc write operation type
89 */
90 typedef enum
91 {
92 XMC_WRITE_OPERATION_DISABLE = 0x00000000, /*!< xmc write operations is disable */
93 XMC_WRITE_OPERATION_ENABLE = 0x00001000 /*!< xmc write operations is enable */
94 } xmc_write_operation_type;
95
96 /**
97 * @brief xmc wait signal type
98 */
99 typedef enum
100 {
101 XMC_WAIT_SIGNAL_DISABLE = 0x00000000, /*!< xmc nwait signal is disable */
102 XMC_WAIT_SIGNAL_ENABLE = 0x00002000 /*!< xmc nwait signal is enable */
103 } xmc_wait_signal_type;
104
105 /**
106 * @brief xmc write burst type
107 */
108 typedef enum
109 {
110 XMC_WRITE_BURST_SYN_DISABLE = 0x00000000, /*!< xmc write operations are always performed in asynchronous mode */
111 XMC_WRITE_BURST_SYN_ENABLE = 0x00080000 /*!< xmc write operations are performed in synchronous mode */
112 } xmc_write_burst_type;
113
114 /**
115 * @brief xmc extended mode type
116 */
117 typedef enum
118 {
119 XMC_WRITE_TIMING_DISABLE = 0x00000000, /*!< xmc write timing disable */
120 XMC_WRITE_TIMING_ENABLE = 0x00004000 /*!< xmc write timing enable */
121 } xmc_extended_mode_type;
122
123 /**
124 * @brief xmc pccard wait type
125 */
126 typedef enum
127 {
128 XMC_WAIT_OPERATION_DISABLE = 0x00000000, /*!< xmc wait operation for the pc card/nand flash memory bank disable */
129 XMC_WAIT_OPERATION_ENABLE = 0x00000002 /*!< xmc wait operation for the pc card/nand flash memory bank enable */
130 } xmc_nand_pccard_wait_type;
131
132 /**
133 * @brief xmc ecc enable type
134 */
135 typedef enum
136 {
137 XMC_ECC_OPERATION_DISABLE = 0x00000000, /*!< xmc ecc module disable */
138 XMC_ECC_OPERATION_ENABLE = 0x00000040 /*!< xmc ecc module enable */
139 } xmc_ecc_enable_type;
140
141 /**
142 * @brief xmc nor/sram subbank type
143 */
144 typedef enum
145 {
146 XMC_BANK1_NOR_SRAM1 = 0x00000000, /*!< xmc nor/sram subbank1 */
147 XMC_BANK1_NOR_SRAM2 = 0x00000001, /*!< xmc nor/sram subbank2 */
148 XMC_BANK1_NOR_SRAM3 = 0x00000002, /*!< xmc nor/sram subbank3 */
149 XMC_BANK1_NOR_SRAM4 = 0x00000003 /*!< xmc nor/sram subbank4 */
150 } xmc_nor_sram_subbank_type;
151
152 /**
153 * @brief xmc class bank type
154 */
155 typedef enum
156 {
157 XMC_BANK2_NAND = 0x00000000, /*!< xmc nand flash bank2 */
158 XMC_BANK3_NAND = 0x00000001, /*!< xmc nand flash bank3 */
159 XMC_BANK4_PCCARD = 0x00000002, /*!< xmc pc card bank4 */
160 XMC_BANK5_6_SDRAM = 0x00000003 /*!< xmc sdram bank5/6 */
161 } xmc_class_bank_type;
162
163 /**
164 * @brief xmc memory type
165 */
166 typedef enum
167 {
168 XMC_DEVICE_SRAM = 0x00000000, /*!< xmc device choice sram */
169 XMC_DEVICE_PSRAM = 0x00000004, /*!< xmc device choice psram */
170 XMC_DEVICE_NOR = 0x00000008 /*!< xmc device choice nor flash */
171 } xmc_memory_type;
172
173 /**
174 * @brief xmc data width type
175 */
176 typedef enum
177 {
178 XMC_BUSTYPE_8_BITS = 0x00000000, /*!< xmc databuss width 8bits */
179 XMC_BUSTYPE_16_BITS = 0x00000010 /*!< xmc databuss width 16bits */
180 } xmc_data_width_type;
181
182 /**
183 * @brief xmc wait signal polarity type
184 */
185 typedef enum
186 {
187 XMC_WAIT_SIGNAL_LEVEL_LOW = 0x00000000, /*!< xmc nwait active low */
188 XMC_WAIT_SIGNAL_LEVEL_HIGH = 0x00000200 /*!< xmc nwait active high */
189 } xmc_wait_signal_polarity_type;
190
191 /**
192 * @brief xmc wait timing type
193 */
194 typedef enum
195 {
196 XMC_WAIT_SIGNAL_SYN_BEFORE = 0x00000000, /*!< xmc nwait signal is active one data cycle before wait state */
197 XMC_WAIT_SIGNAL_SYN_DURING = 0x00000800 /*!< xmc nwait signal is active during wait state */
198 } xmc_wait_timing_type;
199
200 /**
201 * @brief xmc access mode type
202 */
203 typedef enum
204 {
205 XMC_ACCESS_MODE_A = 0x00000000, /*!< xmc access mode A */
206 XMC_ACCESS_MODE_B = 0x10000000, /*!< xmc access mode B */
207 XMC_ACCESS_MODE_C = 0x20000000, /*!< xmc access mode C */
208 XMC_ACCESS_MODE_D = 0x30000000 /*!< xmc access mode D */
209 } xmc_access_mode_type;
210
211 /**
212 * @brief xmc ecc page size type
213 */
214 typedef enum
215 {
216 XMC_ECC_PAGESIZE_256_BYTES = 0x00000000, /*!< xmc ecc page size 256 bytes */
217 XMC_ECC_PAGESIZE_512_BYTES = 0x00020000, /*!< xmc ecc page size 512 bytes */
218 XMC_ECC_PAGESIZE_1024_BYTES = 0x00040000, /*!< xmc ecc page size 1024 bytes */
219 XMC_ECC_PAGESIZE_2048_BYTES = 0x00060000, /*!< xmc ecc page size 2048 bytes */
220 XMC_ECC_PAGESIZE_4096_BYTES = 0x00080000, /*!< xmc ecc page size 4096 bytes */
221 XMC_ECC_PAGESIZE_8192_BYTES = 0x000A0000 /*!< xmc ecc page size 8192 bytes */
222 } xmc_ecc_pagesize_type;
223
224 /**
225 * @brief xmc interrupt sources type
226 */
227 typedef enum
228 {
229 XMC_INT_RISING_EDGE = 0x00000008, /*!< xmc rising edge detection interrupt enable */
230 XMC_INT_LEVEL = 0x00000010, /*!< xmc high-level edge detection interrupt enable */
231 XMC_INT_FALLING_EDGE = 0x00000020, /*!< xmc falling edge detection interrupt enable */
232 XMC_INT_ERR = 0x00004000 /*!< xmc sdram error interrupt enable */
233 } xmc_interrupt_sources_type;
234
235 /**
236 * @brief xmc interrupt flag type
237 */
238 typedef enum
239 {
240 XMC_RISINGEDGE_FLAG = 0x00000001, /*!< xmc interrupt rising edge detection flag */
241 XMC_LEVEL_FLAG = 0x00000002, /*!< xmc interrupt high-level edge detection flag */
242 XMC_FALLINGEDGE_FLAG = 0x00000004, /*!< xmc interrupt falling edge detection flag */
243 XMC_FEMPT_FLAG = 0x00000040, /*!< xmc fifo empty flag */
244 XMC_ERR_FLAG = 0x00000001, /*!< xmc sdram error flag */
245 XMC_BUSY_FLAG = 0x00000020 /*!< xmc sdram busy flag */
246 } xmc_interrupt_flag_type;
247
248 /**
249 * @brief xmc sdram number of column address type
250 */
251 typedef enum
252 {
253 XMC_COLUMN_8 = 0x00000000, /*!< xmc sdram column address 8bit */
254 XMC_COLUMN_9 = 0x00000001, /*!< xmc sdram column address 9bit */
255 XMC_COLUMN_10 = 0x00000002, /*!< xmc sdram column address 10bit */
256 XMC_COLUMN_11 = 0x00000003 /*!< xmc sdram column address 11bit */
257 }xmc_sdram_column_type;
258
259 /**
260 * @brief xmc sdram number of row address type
261 */
262 typedef enum
263 {
264 XMC_ROW_11 = 0x00000000, /*!< xmc sdram row address 11bit */
265 XMC_ROW_12 = 0x00000001, /*!< xmc sdram row address 12bit */
266 XMC_ROW_13 = 0x00000002 /*!< xmc sdram row address 13bit */
267 }xmc_sdram_row_type;
268
269 /**
270 * @brief xmc sdram memory data bus width type
271 */
272 typedef enum
273 {
274 XMC_MEM_WIDTH_8 = 0x00000000, /*!< xmc sdram data bus width 8 */
275 XMC_MEM_WIDTH_16 = 0x00000001 /*!< xmc sdram data bus width 16 */
276 }xmc_sdram_width_type;
277
278 /**
279 * @brief xmc sdram number of internal banks type
280 */
281 typedef enum
282 {
283 XMC_INBK_2 = 0x00000000, /*!< xmc sdram 2 internal banks */
284 XMC_INBK_4 = 0x00000001 /*!< xmc sdram 4 internal banks */
285 }xmc_sdram_inbk_type;
286
287 /**
288 * @brief xmc sdram cas latency type
289 */
290 typedef enum
291 {
292 XMC_CAS_1 = 0x00000001, /*!< xmc sdram cas 1 */
293 XMC_CAS_2 = 0x00000002, /*!< xmc sdram cas 2 */
294 XMC_CAS_3 = 0x00000003 /*!< xmc sdram cas 3 */
295 }xmc_sdram_cas_type;
296
297 /**
298 * @brief xmc sdram clock div type
299 */
300 typedef enum
301 {
302 XMC_NO_CLK = 0x00000000, /*!< xmc sdram disable clock */
303 XMC_CLKDIV_2 = 0x00000002, /*!< xmc sdram clock div 2 */
304 XMC_CLKDIV_3 = 0x00000003, /*!< xmc sdram clock div 3 */
305 XMC_CLKDIV_4 = 0x00000001 /*!< xmc sdram clock div 4 */
306 }xmc_sdram_clkdiv_type;
307
308 /**
309 * @brief xmc sdram read delay
310 */
311 typedef enum
312 {
313 XMC_READ_DELAY_0 = 0x00000000, /*!< xmc sdram no delay */
314 XMC_READ_DELAY_1 = 0x00000001, /*!< xmc sdram delay 1 clock*/
315 XMC_READ_DELAY_2 = 0x00000002, /*!< xmc sdram delay 2 clock */
316 }xmc_sdram_rd_delay_type;
317
318 /**
319 * @brief xmc sdram bank type
320 */
321 typedef enum
322 {
323 XMC_SDRAM_BANK1 = 0x00000000, /*!< xmc sdram bank 1 */
324 XMC_SDRAM_BANK2 = 0x00000001 /*!< xmc sdram bank 2 */
325 }xmc_sdram_bank_type;
326
327
328 /**
329 * @brief xmc sdram timing delay cycle type
330 */
331 typedef enum
332 {
333 XMC_DELAY_CYCLE_1 = 0x00000000, /*!< xmc sdram timming delay 1 cycle */
334 XMC_DELAY_CYCLE_2 = 0x00000001, /*!< xmc sdram timming delay 2 cycle */
335 XMC_DELAY_CYCLE_3 = 0x00000002, /*!< xmc sdram timming delay 3 cycle */
336 XMC_DELAY_CYCLE_4 = 0x00000003, /*!< xmc sdram timming delay 4 cycle */
337 XMC_DELAY_CYCLE_5 = 0x00000004, /*!< xmc sdram timming delay 5 cycle */
338 XMC_DELAY_CYCLE_6 = 0x00000005, /*!< xmc sdram timming delay 6 cycle */
339 XMC_DELAY_CYCLE_7 = 0x00000006, /*!< xmc sdram timming delay 7 cycle */
340 XMC_DELAY_CYCLE_8 = 0x00000007, /*!< xmc sdram timming delay 8 cycle */
341 XMC_DELAY_CYCLE_9 = 0x00000008, /*!< xmc sdram timming delay 9 cycle */
342 XMC_DELAY_CYCLE_10 = 0x00000009, /*!< xmc sdram timming delay 10 cycle */
343 XMC_DELAY_CYCLE_11 = 0x0000000A, /*!< xmc sdram timming delay 11 cycle */
344 XMC_DELAY_CYCLE_12 = 0x0000000B, /*!< xmc sdram timming delay 12 cycle */
345 XMC_DELAY_CYCLE_13 = 0x0000000C, /*!< xmc sdram timming delay 13 cycle */
346 XMC_DELAY_CYCLE_14 = 0x0000000D, /*!< xmc sdram timming delay 14 cycle */
347 XMC_DELAY_CYCLE_15 = 0x0000000E, /*!< xmc sdram timming delay 15 cycle */
348 XMC_DELAY_CYCLE_16 = 0x0000000F /*!< xmc sdram timming delay 16 cycle */
349 }xmc_sdram_delay_type;
350
351
352 /**
353 * @brief xmc sdram command type
354 */
355 typedef enum
356 {
357 XMC_CMD_NORMAL = 0x00000000, /*!< xmc sdram command normal */
358 XMC_CMD_CLK = 0x00000001, /*!< xmc sdram command clock enable */
359 XMC_CMD_PRECHARG_ALL = 0x00000002, /*!< xmc sdram command precharg all bank */
360 XMC_CMD_AUTO_REFRESH = 0x00000003, /*!< xmc sdram command auto refresh */
361 XMC_CMD_LOAD_MODE = 0x00000004, /*!< xmc sdram command load mode register */
362 XMC_CMD_SELF_REFRESH = 0x00000005, /*!< xmc sdram command self refresh */
363 XMC_CMD_POWER_DOWN = 0x00000006 /*!< xmc sdram command power down */
364 }xmc_command_type;
365
366 /**
367 * @brief xmc sdram command bank select type
368 */
369 typedef enum
370 {
371 XMC_CMD_BANK1 = 0x00000010, /*!< send xmc sdram command to bank1 */
372 XMC_CMD_BANK2 = 0x00000008, /*!< send xmc sdram command to bank2 */
373 XMC_CMD_BANK1_2 = 0x00000018 /*!< send xmc sdram command to bank1 and bank2 */
374 }xmc_cmd_bank1_2_type;
375
376
377 /**
378 * @brief xmc sdram bank status type
379 */
380 typedef enum
381 {
382 XMC_STATUS_NORMAL = 0x00000000, /*!< xmc sdram status normal */
383 XMC_STATUS_SELF_REFRESH = 0x00000001, /*!< xmc sdram status self refresh */
384 XMC_STATUS_POWER_DOWN = 0x00000002, /*!< xmc sdram power down */
385 XMC_STATUS_MASK = 0x00000003 /*!< xmc sdram mask */
386 }xmc_bank_status_type;
387
388
389 /**
390 * @brief nor/sram banks timing parameters
391 */
392 typedef struct
393 {
394 xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
395 xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram write timing enable */
396 uint32_t addr_setup_time; /*!< xmc nor/sram address setup time */
397 uint32_t addr_hold_time; /*!< xmc nor/sram address hold time */
398 uint32_t data_setup_time; /*!< xmc nor/sram data setup time */
399 uint32_t bus_latency_time; /*!< xmc nor/sram bus latency time */
400 uint32_t clk_psc; /*!< xmc nor/sram clock prescale */
401 uint32_t data_latency_time; /*!< xmc nor/sram data latency time */
402 xmc_access_mode_type mode; /*!< xmc nor/sram access mode */
403 } xmc_norsram_timing_init_type;
404
405 /**
406 * @brief xmc nor/sram init structure definition
407 */
408 typedef struct
409 {
410 xmc_nor_sram_subbank_type subbank; /*!< xmc nor/sram subbank */
411 xmc_data_addr_mux_type data_addr_multiplex; /*!< xmc nor/sram address/data multiplexing enable */
412 xmc_memory_type device; /*!< xmc nor/sram memory device */
413 xmc_data_width_type bus_type; /*!< xmc nor/sram data bus width */
414 xmc_burst_access_mode_type burst_mode_enable; /*!< xmc nor/sram burst mode enable */
415 xmc_asyn_wait_type asynwait_enable; /*!< xmc nor/sram nwait in asynchronous transfer enable */
416 xmc_wait_signal_polarity_type wait_signal_lv; /*!< xmc nor/sram nwait polarity */
417 xmc_wrap_mode_type wrapped_mode_enable; /*!< xmc nor/sram wrapped enable */
418 xmc_wait_timing_type wait_signal_config; /*!< xmc nor/sram nwait timing configuration */
419 xmc_write_operation_type write_enable; /*!< xmc nor/sram write enable */
420 xmc_wait_signal_type wait_signal_enable; /*!< xmc nor/sram nwait in synchronous transfer enable */
421 xmc_extended_mode_type write_timing_enable; /*!< xmc nor/sram read-write timing different */
422 xmc_write_burst_type write_burst_syn; /*!< xmc nor/sram memory write mode control */
423 } xmc_norsram_init_type;
424
425 /**
426 * @brief nand and pccard timing parameters xmc
427 */
428
429 typedef struct
430 {
431 xmc_class_bank_type class_bank; /*!< xmc nand/pccard bank */
432 uint32_t mem_setup_time; /*!< xmc nand/pccard memory setup time */
433 uint32_t mem_waite_time; /*!< xmc nand/pccard memory wait time */
434 uint32_t mem_hold_time; /*!< xmc nand/pccard memory hold time */
435 uint32_t mem_hiz_time; /*!< xmc nand/pccard memory databus high resistance time */
436 } xmc_nand_pccard_timinginit_type;
437
438 /**
439 * @brief xmc nand init structure definition
440 */
441
442 typedef struct
443 {
444 xmc_class_bank_type nand_bank; /*!< xmc nand bank */
445 xmc_nand_pccard_wait_type wait_enable; /*!< xmc wait feature enable */
446 xmc_data_width_type bus_type; /*!< xmc nand bus width */
447 xmc_ecc_enable_type ecc_enable; /*!< xmc nand ecc enable */
448 xmc_ecc_pagesize_type ecc_pagesize; /*!< xmc nand ecc page size */
449 uint32_t delay_time_cycle; /*!< xmc nand cle to re delay */
450 uint32_t delay_time_ar; /*!< xmc nand ale to re delay */
451 } xmc_nand_init_type;
452
453 /**
454 * @brief xmc pccard init structure definition
455 */
456
457 typedef struct
458 {
459 xmc_nand_pccard_wait_type enable_wait; /*!< xmc pccard wait feature enable */
460 uint32_t delay_time_cr; /*!< xmc pccard cle to re delay */
461 uint32_t delay_time_ar; /*!< xmc pccard ale to re delay */
462 } xmc_pccard_init_type;
463
464 /**
465 * @brief xmc sdram init structure definition
466 */
467
468 typedef struct
469 {
470 xmc_sdram_bank_type sdram_bank; /*!< xmc sdram bank bype */
471 xmc_sdram_inbk_type internel_banks; /*!< xmc sdram internal banks */
472 xmc_sdram_clkdiv_type clkdiv; /*!< xmc sdram clock div */
473 uint8_t write_protection; /*!< xmc sdram write protection */
474 uint8_t burst_read; /*!< xmc sdram burst read */
475 uint8_t read_delay; /*!< xmc sdram read delay */
476 xmc_sdram_column_type column_address; /*!< xmc sdram column address */
477 xmc_sdram_row_type row_address; /*!< xmc sdram row address */
478 xmc_sdram_cas_type cas; /*!< xmc sdram cas */
479 xmc_sdram_width_type width; /*!< xmc sdram data width */
480 } xmc_sdram_init_type;
481
482 /**
483 * @brief xmc sdram timing structure definition
484 */
485
486 typedef struct
487 {
488 xmc_sdram_delay_type tmrd; /*!< mode register program to active delay */
489 xmc_sdram_delay_type txsr; /*!< exit self-refresh to active delay */
490 xmc_sdram_delay_type tras; /*!< self refresh */
491 xmc_sdram_delay_type trc; /*!< refresh to active delay */
492 xmc_sdram_delay_type twr; /*!< write recovery delay */
493 xmc_sdram_delay_type trp; /*!< precharge to active delay */
494 xmc_sdram_delay_type trcd; /*!< row active to read/write delay */
495 } xmc_sdram_timing_type;
496
497 /**
498 * @brief xmc sdram command structure definition
499 */
500
501 typedef struct
502 {
503 xmc_command_type cmd; /*!< sdram command */
504 xmc_cmd_bank1_2_type cmd_banks; /*!< which bank send command */
505 uint32_t auto_refresh; /*!< auto refresh times */
506 uint32_t data; /*!< mode register data */
507 } xmc_sdram_cmd_type;
508
509 typedef struct
510 {
511 /**
512 * @brief xmc bank1 bk1ctrl register, offset:0x00+0x08*(x-1) x= 1...4
513 */
514 union
515 {
516 __IO uint32_t bk1ctrl;
517 struct
518 {
519 __IO uint32_t en : 1; /* [0] */
520 __IO uint32_t admuxen : 1; /* [1] */
521 __IO uint32_t dev : 2; /* [3:2] */
522 __IO uint32_t extmdbw : 2; /* [5:4] */
523 __IO uint32_t noren : 1; /* [6] */
524 __IO uint32_t reserved1 : 1; /* [7] */
525 __IO uint32_t syncben : 1; /* [8] */
526 __IO uint32_t nwpol : 1; /* [9] */
527 __IO uint32_t wrapen : 1; /* [10] */
528 __IO uint32_t nwtcfg : 1; /* [11] */
529 __IO uint32_t wen : 1; /* [12] */
530 __IO uint32_t nwsen : 1; /* [13] */
531 __IO uint32_t rwtd : 1; /* [14] */
532 __IO uint32_t nwasen : 1; /* [15] */
533 __IO uint32_t crpgs : 3; /* [18:16] */
534 __IO uint32_t mwmc : 1; /* [19] */
535 __IO uint32_t reserved2 : 12;/* [31:20] */
536 } bk1ctrl_bit;
537 };
538
539 /**
540 * @brief xmc bank1 bk1tmg register, offset:0x04+0x08*(x-1) x= 1...4
541 */
542 union
543 {
544 __IO uint32_t bk1tmg;
545 struct
546 {
547 __IO uint32_t addrst : 4; /* [3:0] */
548 __IO uint32_t addrht : 4; /* [7:4] */
549 __IO uint32_t dtst : 8; /* [15:8] */
550 __IO uint32_t buslat : 4; /* [19:16] */
551 __IO uint32_t clkpsc : 4; /* [23:20] */
552 __IO uint32_t dtlat : 4; /* [27:24] */
553 __IO uint32_t asyncm : 2; /* [29:28] */
554 __IO uint32_t reserved1 : 2; /* [31:30] */
555 } bk1tmg_bit;
556 };
557
558 } xmc_bank1_ctrl_tmg_reg_type;
559
560 typedef struct
561 {
562 /**
563 * @brief xmc bank1 bk1tmgwr register, offset:0x104+0x08*(x-1) x= 1...4
564 */
565 union
566 {
567 __IO uint32_t bk1tmgwr;
568 struct
569 {
570 __IO uint32_t addrst : 4; /* [3:0] */
571 __IO uint32_t addrht : 4; /* [7:4] */
572 __IO uint32_t dtst : 8; /* [15:8] */
573 __IO uint32_t buslat : 4; /* [19:16] */
574 __IO uint32_t reserved1 : 8; /* [27:20] */
575 __IO uint32_t asyncm : 2; /* [29:28] */
576 __IO uint32_t reserved2 : 2; /* [31:30] */
577 } bk1tmgwr_bit;
578 };
579
580 /**
581 * @brief xmc bank1 reserved register
582 */
583 __IO uint32_t reserved1;
584
585 } xmc_bank1_tmgwr_reg_type;
586
587 /**
588 * @brief xmc bank1 registers
589 */
590 typedef struct
591 {
592 /**
593 * @brief xmc bank1 ctrl and tmg register, offset:0x00~0x1C
594 */
595 xmc_bank1_ctrl_tmg_reg_type ctrl_tmg_group[4];
596
597 /**
598 * @brief xmc bank1 reserved register, offset:0x20~0x100
599 */
600 __IO uint32_t reserved1[57];
601
602 /**
603 * @brief xmc bank1 tmgwr register, offset:0x104~0x11C
604 */
605 xmc_bank1_tmgwr_reg_type tmgwr_group[4];
606
607 /**
608 * @brief xmc bank1 reserved register, offset:0x120~0x21C
609 */
610 __IO uint32_t reserved2[63];
611
612 /**
613 * @brief xmc bank1 ext register, offset:0x220~0x22C
614 */
615 union
616 {
617 __IO uint32_t ext[4];
618 struct
619 {
620 __IO uint32_t buslatw2w : 8; /* [7:0] */
621 __IO uint32_t buslatr2r : 8; /* [15:8] */
622 __IO uint32_t reserved1 : 16;/* [31:16] */
623 } ext_bit[4];
624 };
625
626 } xmc_bank1_type;
627
628 /**
629 * @brief xmc bank2 registers
630 */
631 typedef struct
632 {
633 /**
634 * @brief xmc bk2ctrl register, offset:0x60
635 */
636 union
637 {
638 __IO uint32_t bk2ctrl;
639 struct
640 {
641 __IO uint32_t reserved1 : 1; /* [0] */
642 __IO uint32_t nwen : 1; /* [1] */
643 __IO uint32_t en : 1; /* [2] */
644 __IO uint32_t dev : 1; /* [3] */
645 __IO uint32_t extmdbw : 2; /* [5:4] */
646 __IO uint32_t eccen : 1; /* [6] */
647 __IO uint32_t reserved2 : 2; /* [8:7] */
648 __IO uint32_t tcr : 4; /* [12:9] */
649 __IO uint32_t tar : 4; /* [16:13] */
650 __IO uint32_t eccpgs : 3; /* [19:17] */
651 __IO uint32_t reserved3 : 12;/* [31:20] */
652 } bk2ctrl_bit;
653 };
654
655 /**
656 * @brief xmc bk2is register, offset:0x64
657 */
658 union
659 {
660 __IO uint32_t bk2is;
661 struct
662 {
663 __IO uint32_t res : 1; /* [0] */
664 __IO uint32_t hls : 1; /* [1] */
665 __IO uint32_t fes : 1; /* [2] */
666 __IO uint32_t reien : 1; /* [3] */
667 __IO uint32_t hlien : 1; /* [4] */
668 __IO uint32_t feien : 1; /* [5] */
669 __IO uint32_t fifoe : 1; /* [6] */
670 __IO uint32_t reserved1 : 25;/* [31:7] */
671 } bk2is_bit;
672 };
673
674 /**
675 * @brief xmc bk2tmgmem register, offset:0x68
676 */
677 union
678 {
679 __IO uint32_t bk2tmgmem;
680 struct
681 {
682 __IO uint32_t cmst : 8; /* [7:0] */
683 __IO uint32_t cmwt : 8; /* [15:8] */
684 __IO uint32_t cmht : 8; /* [23:16] */
685 __IO uint32_t cmdhizt : 8; /* [31:24] */
686 } bk2tmgmem_bit;
687 };
688
689 /**
690 * @brief xmc bk2tmgatt register, offset:0x6C
691 */
692 union
693 {
694 __IO uint32_t bk2tmgatt;
695 struct
696 {
697 __IO uint32_t amst : 8; /* [7:0] */
698 __IO uint32_t amwt : 8; /* [15:8] */
699 __IO uint32_t amht : 8; /* [23:16] */
700 __IO uint32_t amdhizt : 8; /* [31:24] */
701 } bk2tmgatt_bit;
702 };
703
704 /**
705 * @brief xmc reserved register, offset:0x70
706 */
707 __IO uint32_t reserved1;
708
709 /**
710 * @brief xmc bk2ecc register, offset:0x74
711 */
712 union
713 {
714 __IO uint32_t bk2ecc;
715 struct
716 {
717 __IO uint32_t ecc : 32; /* [31:0] */
718 } bk2ecc_bit;
719 };
720
721 } xmc_bank2_type;
722
723 /**
724 * @brief xmc bank3 registers
725 */
726 typedef struct
727 {
728 /**
729 * @brief xmc bk3ctrl register, offset:0x80
730 */
731 union
732 {
733 __IO uint32_t bk3ctrl;
734 struct
735 {
736 __IO uint32_t reserved1 : 1; /* [0] */
737 __IO uint32_t nwen : 1; /* [1] */
738 __IO uint32_t en : 1; /* [2] */
739 __IO uint32_t dev : 1; /* [3] */
740 __IO uint32_t extmdbw : 2; /* [5:4] */
741 __IO uint32_t eccen : 1; /* [6] */
742 __IO uint32_t reserved2 : 2; /* [8:7] */
743 __IO uint32_t tcr : 4; /* [12:9] */
744 __IO uint32_t tar : 4; /* [16:13] */
745 __IO uint32_t eccpgs : 3; /* [19:17] */
746 __IO uint32_t reserved3 : 12;/* [31:20] */
747 } bk3ctrl_bit;
748 };
749
750 /**
751 * @brief xmc bk3is register, offset:0x84
752 */
753 union
754 {
755 __IO uint32_t bk3is;
756 struct
757 {
758 __IO uint32_t res : 1; /* [0] */
759 __IO uint32_t hls : 1; /* [1] */
760 __IO uint32_t fes : 1; /* [2] */
761 __IO uint32_t reien : 1; /* [3] */
762 __IO uint32_t hlien : 1; /* [4] */
763 __IO uint32_t feien : 1; /* [5] */
764 __IO uint32_t fifoe : 1; /* [6] */
765 __IO uint32_t reserved1 : 25;/* [31:7] */
766 } bk3is_bit;
767 };
768
769 /**
770 * @brief xmc bk3tmgmem register, offset:0x88
771 */
772 union
773 {
774 __IO uint32_t bk3tmgmem;
775 struct
776 {
777 __IO uint32_t cmst : 8; /* [7:0] */
778 __IO uint32_t cmwt : 8; /* [15:8] */
779 __IO uint32_t cmht : 8; /* [23:16] */
780 __IO uint32_t cmdhizt : 8; /* [31:24] */
781 } bk3tmgmem_bit;
782 };
783
784 /**
785 * @brief xmc bk3tmgatt register, offset:0x8C
786 */
787 union
788 {
789 __IO uint32_t bk3tmgatt;
790 struct
791 {
792 __IO uint32_t amst : 8; /* [7:0] */
793 __IO uint32_t amwt : 8; /* [15:8] */
794 __IO uint32_t amht : 8; /* [23:16] */
795 __IO uint32_t amdhizt : 8; /* [31:24] */
796 } bk3tmgatt_bit;
797 };
798
799 /**
800 * @brief xmc reserved register, offset:0x90
801 */
802 __IO uint32_t reserved1;
803
804 /**
805 * @brief xmc bk3ecc register, offset:0x94
806 */
807 union
808 {
809 __IO uint32_t bk3ecc;
810 struct
811 {
812 __IO uint32_t ecc : 32; /* [31:0] */
813 } bk3ecc_bit;
814 };
815 } xmc_bank3_type;
816
817 /**
818 * @brief xmc bank4 registers
819 */
820 typedef struct
821 {
822
823 /**
824 * @brief xmc bk4ctrl register, offset:0xA0
825 */
826 union
827 {
828 __IO uint32_t bk4ctrl;
829 struct
830 {
831 __IO uint32_t reserved1 : 1; /* [0] */
832 __IO uint32_t nwen : 1; /* [1] */
833 __IO uint32_t en : 1; /* [2] */
834 __IO uint32_t dev : 1; /* [3] */
835 __IO uint32_t extmdbw : 2; /* [5:4] */
836 __IO uint32_t eccen : 1; /* [6] */
837 __IO uint32_t reserved2 : 2; /* [8:7] */
838 __IO uint32_t tcr : 4; /* [12:9] */
839 __IO uint32_t tar : 4; /* [16:13] */
840 __IO uint32_t eccpgs : 3; /* [19:17] */
841 __IO uint32_t reserved3 : 12;/* [31:20] */
842 } bk4ctrl_bit;
843 };
844
845 /**
846 * @brief xmc bk4is register, offset:0xA4
847 */
848 union
849 {
850 __IO uint32_t bk4is;
851 struct
852 {
853 __IO uint32_t res : 1; /* [0] */
854 __IO uint32_t hls : 1; /* [1] */
855 __IO uint32_t fes : 1; /* [2] */
856 __IO uint32_t reien : 1; /* [3] */
857 __IO uint32_t hlien : 1; /* [4] */
858 __IO uint32_t feien : 1; /* [5] */
859 __IO uint32_t fifoe : 1; /* [6] */
860 __IO uint32_t reserved1 : 25;/* [31:7] */
861 } bk4is_bit;
862 };
863
864 /**
865 * @brief xmc bk4tmgmem register, offset:0xA8
866 */
867 union
868 {
869 __IO uint32_t bk4tmgmem;
870 struct
871 {
872 __IO uint32_t cmst : 8; /* [7:0] */
873 __IO uint32_t cmwt : 8; /* [15:8] */
874 __IO uint32_t cmht : 8; /* [23:16] */
875 __IO uint32_t cmdhizt : 8; /* [31:24] */
876 } bk4tmgmem_bit;
877 };
878
879 /**
880 * @brief xmc bk4tmgatt register, offset:0xAC
881 */
882 union
883 {
884 __IO uint32_t bk4tmgatt;
885 struct
886 {
887 __IO uint32_t amst : 8; /* [7:0] */
888 __IO uint32_t amwt : 8; /* [15:8] */
889 __IO uint32_t amht : 8; /* [23:16] */
890 __IO uint32_t amdhizt : 8; /* [31:24] */
891 } bk4tmgatt_bit;
892 };
893
894 /**
895 * @brief xmc bk4tmgio register, offset:0xB0
896 */
897 union
898 {
899 __IO uint32_t bk4tmgio;
900 struct
901 {
902 __IO uint32_t iost : 8; /* [7:0] */
903 __IO uint32_t iowt : 8; /* [15:8] */
904 __IO uint32_t ioht : 8; /* [23:16] */
905 __IO uint32_t iohizt : 8; /* [31:24] */
906 } bk4tmgio_bit;
907 };
908 } xmc_bank4_type;
909
910 /**
911 * @brief xmc sdram type
912 */
913 typedef struct
914 {
915 /**
916 * @brief xmc sdram ctrl register, offset:0x140~0x144
917 */
918 union
919 {
920 __IO uint32_t ctrl[2];
921 struct
922 {
923 __IO uint32_t ca : 2; /* [1:0] */
924 __IO uint32_t ra : 2; /* [3:2] */
925 __IO uint32_t db : 2; /* [5:4] */
926 __IO uint32_t inbk : 1; /* [6] */
927 __IO uint32_t cas : 2; /* [8:7] */
928 __IO uint32_t wrp : 1; /* [9] */
929 __IO uint32_t clkdiv : 2; /* [11:10] */
930 __IO uint32_t bstr : 1; /* [12] */
931 __IO uint32_t rd : 2; /* [14:13] */
932 __IO uint32_t reserved1 : 17;/* [31:15] */
933 } ctrl_bit[2];
934 };
935
936 /**
937 * @brief xmc sdram tm register, offset:0x148~0x14C
938 */
939 union
940 {
941 __IO uint32_t tm[2];
942 struct
943 {
944 __IO uint32_t tmrd : 4; /* [3:0] */
945 __IO uint32_t txsr : 4; /* [7:4] */
946 __IO uint32_t tras : 4; /* [11:8] */
947 __IO uint32_t trc : 4; /* [15:12] */
948 __IO uint32_t twr : 4; /* [19:16] */
949 __IO uint32_t trp : 4; /* [23:20] */
950 __IO uint32_t trcd : 4; /* [27:24] */
951 __IO uint32_t reserved1 : 4; /* [31:28] */
952 } tm_bit[2];
953
954 };
955
956 /**
957 * @brief xmc sdram cmd register, offset:0x150
958 */
959 union
960 {
961 __IO uint32_t cmd;
962 struct
963 {
964 __IO uint32_t cmd : 3; /* [2:0] */
965 __IO uint32_t bk2 : 1; /* [3] */
966 __IO uint32_t bk1 : 1; /* [4] */
967 __IO uint32_t art : 4; /* [8:5] */
968 __IO uint32_t mrd : 13;/* [21:9] */
969 __IO uint32_t reserved1 : 10;/* [31:22] */
970 } cmd_bit;
971 };
972
973 /**
974 * @brief xmc sdram rcnt register, offset:0x154
975 */
976 union
977 {
978 __IO uint32_t rcnt;
979 struct
980 {
981 __IO uint32_t errc : 1; /* [0] */
982 __IO uint32_t rc : 13;/* [13:1] */
983 __IO uint32_t erien : 1; /* [14] */
984 __IO uint32_t reserved1 : 17;/* [31:15] */
985 } rcnt_bit;
986 };
987
988 /**
989 * @brief xmc sdram sts register, offset:0x158
990 */
991 union
992 {
993 __IO uint32_t sts;
994 struct
995 {
996 __IO uint32_t err : 1; /* [0] */
997 __IO uint32_t bk1sts : 2; /* [2:1] */
998 __IO uint32_t bk2sts : 2; /* [4:3] */
999 __IO uint32_t busy : 1; /* [5] */
1000 __IO uint32_t reserved1 : 26;/* [31:6] */
1001 } sts_bit;
1002 };
1003 }xmc_sdram_type;
1004
1005 /**
1006 * @}
1007 */
1008
1009 #define XMC_BANK1 ((xmc_bank1_type *) XMC_BANK1_REG_BASE)
1010 #define XMC_BANK2 ((xmc_bank2_type *) XMC_BANK2_REG_BASE)
1011 #define XMC_BANK3 ((xmc_bank3_type *) XMC_BANK3_REG_BASE)
1012 #define XMC_BANK4 ((xmc_bank4_type *) XMC_BANK4_REG_BASE)
1013 #define XMC_SDRAM ((xmc_sdram_type *) XMC_SDRAM_REG_BASE)
1014
1015 /** @defgroup XMC_exported_functions
1016 * @{
1017 */
1018
1019 void xmc_nor_sram_reset(xmc_nor_sram_subbank_type xmc_subbank);
1020 void xmc_nor_sram_init(xmc_norsram_init_type* xmc_norsram_init_struct);
1021 void xmc_nor_sram_timing_config(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
1022 xmc_norsram_timing_init_type* xmc_w_timing_struct);
1023 void xmc_norsram_default_para_init(xmc_norsram_init_type* xmc_nor_sram_init_struct);
1024 void xmc_norsram_timing_default_para_init(xmc_norsram_timing_init_type* xmc_rw_timing_struct,
1025 xmc_norsram_timing_init_type* xmc_w_timing_struct);
1026 void xmc_nor_sram_enable(xmc_nor_sram_subbank_type xmc_subbank, confirm_state new_state);
1027 void xmc_ext_timing_config(xmc_nor_sram_subbank_type xmc_sub_bank, uint16_t w2w_timing, uint16_t r2r_timing);
1028 void xmc_nand_reset(xmc_class_bank_type xmc_bank);
1029 void xmc_nand_init(xmc_nand_init_type* xmc_nand_init_struct);
1030 void xmc_nand_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
1031 xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
1032 void xmc_nand_default_para_init(xmc_nand_init_type* xmc_nand_init_struct);
1033 void xmc_nand_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
1034 xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct);
1035 void xmc_nand_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
1036 void xmc_nand_ecc_enable(xmc_class_bank_type xmc_bank, confirm_state new_state);
1037 uint32_t xmc_ecc_get(xmc_class_bank_type xmc_bank);
1038 void xmc_interrupt_enable(xmc_class_bank_type xmc_bank, xmc_interrupt_sources_type xmc_int, confirm_state new_state);
1039 flag_status xmc_flag_status_get(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
1040 void xmc_flag_clear(xmc_class_bank_type xmc_bank, xmc_interrupt_flag_type xmc_flag);
1041 void xmc_pccard_reset(void);
1042 void xmc_pccard_init(xmc_pccard_init_type* xmc_pccard_init_struct);
1043 void xmc_pccard_timing_config(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
1044 xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
1045 xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
1046 void xmc_pccard_default_para_init(xmc_pccard_init_type* xmc_pccard_init_struct);
1047 void xmc_pccard_timing_default_para_init(xmc_nand_pccard_timinginit_type* xmc_common_spacetiming_struct,
1048 xmc_nand_pccard_timinginit_type* xmc_attribute_spacetiming_struct,
1049 xmc_nand_pccard_timinginit_type* xmc_iospace_timing_struct);
1050 void xmc_pccard_enable(confirm_state new_state);
1051 void xmc_sdram_reset(xmc_sdram_bank_type xmc_bank);
1052 void xmc_sdram_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
1053 void xmc_sdram_default_para_init(xmc_sdram_init_type *xmc_sdram_init_struct, xmc_sdram_timing_type *xmc_sdram_timing_struct);
1054 void xmc_sdram_cmd(xmc_sdram_cmd_type *xmc_sdram_cmd_struct);
1055 uint32_t xmc_sdram_status_get(xmc_sdram_bank_type xmc_bank);
1056 void xmc_sdram_refresh_counter_set(uint32_t counter);
1057 void xmc_sdram_auto_refresh_set(uint32_t number);
1058
1059 /**
1060 * @}
1061 */
1062
1063 /**
1064 * @}
1065 */
1066
1067 /**
1068 * @}
1069 */
1070
1071 #ifdef __cplusplus
1072 }
1073 #endif
1074
1075 #endif
INAV: Navigation-enabled flight control software