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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_adc.h
blob687f9cda02c1b1a2cfcb44cd0f277219178fa1a8
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_adc.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of ADC HAL extension module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_ADC_H
40 #define __STM32F7xx_ADC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup ADC
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup ADC_Exported_Types ADC Exported Types
59 * @{
60 */
61
62 /**
63 * @brief Structure definition of ADC and regular group initialization
64 * @note Parameters of this structure are shared within 2 scopes:
65 * - Scope entire ADC (affects regular and injected groups): ClockPrescaler, Resolution, ScanConvMode, DataAlign, ScanConvMode, EOCSelection, LowPowerAutoWait, LowPowerAutoPowerOff, ChannelsBank.
66 * - Scope regular group: ContinuousConvMode, NbrOfConversion, DiscontinuousConvMode, NbrOfDiscConversion, ExternalTrigConvEdge, ExternalTrigConv.
67 * @note The setting of these parameters with function HAL_ADC_Init() is conditioned to ADC state.
68 * ADC state can be either:
69 * - For all parameters: ADC disabled
70 * - For all parameters except 'Resolution', 'ScanConvMode', 'DiscontinuousConvMode', 'NbrOfDiscConversion' : ADC enabled without conversion on going on regular group.
71 * - For parameters 'ExternalTrigConv' and 'ExternalTrigConvEdge': ADC enabled, even with conversion on going.
72 * If ADC is not in the appropriate state to modify some parameters, these parameters setting is bypassed
73 * without error reporting (as it can be the expected behaviour in case of intended action to update another parameter (which fullfills the ADC state condition) on the fly).
74 */
75 typedef struct
76 {
77 uint32_t ClockPrescaler; /*!< Select ADC clock prescaler. The clock is common for
78 all the ADCs.
79 This parameter can be a value of @ref ADC_ClockPrescaler */
80 uint32_t Resolution; /*!< Configures the ADC resolution.
81 This parameter can be a value of @ref ADC_Resolution */
82 uint32_t DataAlign; /*!< Specifies ADC data alignment to right (MSB on register bit 11 and LSB on register bit 0) (default setting)
83 or to left (if regular group: MSB on register bit 15 and LSB on register bit 4, if injected group (MSB kept as signed value due to potential negative value after offset application): MSB on register bit 14 and LSB on register bit 3).
84 This parameter can be a value of @ref ADC_Data_Align */
85 uint32_t ScanConvMode; /*!< Configures the sequencer of regular and injected groups.
86 This parameter can be associated to parameter 'DiscontinuousConvMode' to have main sequence subdivided in successive parts.
87 If disabled: Conversion is performed in single mode (one channel converted, the one defined in rank 1).
88 Parameters 'NbrOfConversion' and 'InjectedNbrOfConversion' are discarded (equivalent to set to 1).
89 If enabled: Conversions are performed in sequence mode (multiple ranks defined by 'NbrOfConversion'/'InjectedNbrOfConversion' and each channel rank).
90 Scan direction is upward: from rank1 to rank 'n'.
91 This parameter can be a value of @ref ADC_Scan_mode.
92 This parameter can be set to ENABLE or DISABLE */
93 uint32_t EOCSelection; /*!< Specifies what EOC (End Of Conversion) flag is used for conversion by polling and interruption: end of conversion of each rank or complete sequence.
94 This parameter can be a value of @ref ADC_EOCSelection.
95 Note: For injected group, end of conversion (flag&IT) is raised only at the end of the sequence.
96 Therefore, if end of conversion is set to end of each conversion, injected group should not be used with interruption (HAL_ADCEx_InjectedStart_IT)
97 or polling (HAL_ADCEx_InjectedStart and HAL_ADCEx_InjectedPollForConversion). By the way, polling is still possible since driver will use an estimated timing for end of injected conversion.
98 Note: If overrun feature is intended to be used, use ADC in mode 'interruption' (function HAL_ADC_Start_IT() ) with parameter EOCSelection set to end of each conversion or in mode 'transfer by DMA' (function HAL_ADC_Start_DMA()).
99 If overrun feature is intended to be bypassed, use ADC in mode 'polling' or 'interruption' with parameter EOCSelection must be set to end of sequence */
100 uint32_t ContinuousConvMode; /*!< Specifies whether the conversion is performed in single mode (one conversion) or continuous mode for regular group,
101 after the selected trigger occurred (software start or external trigger).
102 This parameter can be set to ENABLE or DISABLE. */
103 uint32_t NbrOfConversion; /*!< Specifies the number of ranks that will be converted within the regular group sequencer.
104 To use regular group sequencer and convert several ranks, parameter 'ScanConvMode' must be enabled.
105 This parameter must be a number between Min_Data = 1 and Max_Data = 16. */
106 uint32_t DiscontinuousConvMode; /*!< Specifies whether the conversions sequence of regular group is performed in Complete-sequence/Discontinuous-sequence (main sequence subdivided in successive parts).
107 Discontinuous mode is used only if sequencer is enabled (parameter 'ScanConvMode'). If sequencer is disabled, this parameter is discarded.
108 Discontinuous mode can be enabled only if continuous mode is disabled. If continuous mode is enabled, this parameter setting is discarded.
109 This parameter can be set to ENABLE or DISABLE. */
110 uint32_t NbrOfDiscConversion; /*!< Specifies the number of discontinuous conversions in which the main sequence of regular group (parameter NbrOfConversion) will be subdivided.
111 If parameter 'DiscontinuousConvMode' is disabled, this parameter is discarded.
112 This parameter must be a number between Min_Data = 1 and Max_Data = 8. */
113 uint32_t ExternalTrigConv; /*!< Selects the external event used to trigger the conversion start of regular group.
114 If set to ADC_SOFTWARE_START, external triggers are disabled.
115 If set to external trigger source, triggering is on event rising edge by default.
116 This parameter can be a value of @ref ADC_External_trigger_Source_Regular */
117 uint32_t ExternalTrigConvEdge; /*!< Selects the external trigger edge of regular group.
118 If trigger is set to ADC_SOFTWARE_START, this parameter is discarded.
119 This parameter can be a value of @ref ADC_External_trigger_edge_Regular */
120 uint32_t DMAContinuousRequests; /*!< Specifies whether the DMA requests are performed in one shot mode (DMA transfer stop when number of conversions is reached)
121 or in Continuous mode (DMA transfer unlimited, whatever number of conversions).
122 Note: In continuous mode, DMA must be configured in circular mode. Otherwise an overrun will be triggered when DMA buffer maximum pointer is reached.
123 Note: This parameter must be modified when no conversion is on going on both regular and injected groups (ADC disabled, or ADC enabled without continuous mode or external trigger that could launch a conversion).
124 This parameter can be set to ENABLE or DISABLE. */
125 }ADC_InitTypeDef;
126
127
128
129 /**
130 * @brief Structure definition of ADC channel for regular group
131 * @note The setting of these parameters with function HAL_ADC_ConfigChannel() is conditioned to ADC state.
132 * ADC can be either disabled or enabled without conversion on going on regular group.
133 */
134 typedef struct
135 {
136 uint32_t Channel; /*!< Specifies the channel to configure into ADC regular group.
137 This parameter can be a value of @ref ADC_channels */
138 uint32_t Rank; /*!< Specifies the rank in the regular group sequencer.
139 This parameter must be a number between Min_Data = 1 and Max_Data = 16
140 This parameter can be a value of @ref ADC_regular_rank */
141 uint32_t SamplingTime; /*!< Sampling time value to be set for the selected channel.
142 Unit: ADC clock cycles
143 Conversion time is the addition of sampling time and processing time (12 ADC clock cycles at ADC resolution 12 bits, 11 cycles at 10 bits, 9 cycles at 8 bits, 7 cycles at 6 bits).
144 This parameter can be a value of @ref ADC_sampling_times
145 Caution: This parameter updates the parameter property of the channel, that can be used into regular and/or injected groups.
146 If this same channel has been previously configured in the other group (regular/injected), it will be updated to last setting.
147 Note: In case of usage of internal measurement channels (VrefInt/Vbat/TempSensor),
148 sampling time constraints must be respected (sampling time can be adjusted in function of ADC clock frequency and sampling time setting)
149 Refer to device datasheet for timings values, parameters TS_vrefint, TS_temp (values rough order: 4us min). */
150 uint32_t Offset; /*!< Reserved for future use, can be set to 0 */
151 }ADC_ChannelConfTypeDef;
152
153 /**
154 * @brief ADC Configuration multi-mode structure definition
155 */
156 typedef struct
157 {
158 uint32_t WatchdogMode; /*!< Configures the ADC analog watchdog mode.
159 This parameter can be a value of @ref ADC_analog_watchdog_selection */
160 uint32_t HighThreshold; /*!< Configures the ADC analog watchdog High threshold value.
161 This parameter must be a 12-bit value. */
162 uint32_t LowThreshold; /*!< Configures the ADC analog watchdog High threshold value.
163 This parameter must be a 12-bit value. */
164 uint32_t Channel; /*!< Configures ADC channel for the analog watchdog.
165 This parameter has an effect only if watchdog mode is configured on single channel
166 This parameter can be a value of @ref ADC_channels */
167 uint32_t ITMode; /*!< Specifies whether the analog watchdog is configured
168 is interrupt mode or in polling mode.
169 This parameter can be set to ENABLE or DISABLE */
170 uint32_t WatchdogNumber; /*!< Reserved for future use, can be set to 0 */
171 }ADC_AnalogWDGConfTypeDef;
172
173 /**
174 * @brief HAL ADC state machine: ADC states definition (bitfields)
175 */
176 /* States of ADC global scope */
177 #define HAL_ADC_STATE_RESET ((uint32_t)0x00000000U) /*!< ADC not yet initialized or disabled */
178 #define HAL_ADC_STATE_READY ((uint32_t)0x00000001U) /*!< ADC peripheral ready for use */
179 #define HAL_ADC_STATE_BUSY_INTERNAL ((uint32_t)0x00000002U) /*!< ADC is busy to internal process (initialization, calibration) */
180 #define HAL_ADC_STATE_TIMEOUT ((uint32_t)0x00000004U) /*!< TimeOut occurrence */
181
182 /* States of ADC errors */
183 #define HAL_ADC_STATE_ERROR_INTERNAL ((uint32_t)0x00000010U) /*!< Internal error occurrence */
184 #define HAL_ADC_STATE_ERROR_CONFIG ((uint32_t)0x00000020U) /*!< Configuration error occurrence */
185 #define HAL_ADC_STATE_ERROR_DMA ((uint32_t)0x00000040U) /*!< DMA error occurrence */
186
187 /* States of ADC group regular */
188 #define HAL_ADC_STATE_REG_BUSY ((uint32_t)0x00000100U) /*!< A conversion on group regular is ongoing or can occur (either by continuous mode,
189 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
190 #define HAL_ADC_STATE_REG_EOC ((uint32_t)0x00000200U) /*!< Conversion data available on group regular */
191 #define HAL_ADC_STATE_REG_OVR ((uint32_t)0x00000400U) /*!< Overrun occurrence */
192
193 /* States of ADC group injected */
194 #define HAL_ADC_STATE_INJ_BUSY ((uint32_t)0x00001000U) /*!< A conversion on group injected is ongoing or can occur (either by auto-injection mode,
195 external trigger, low power auto power-on (if feature available), multimode ADC master control (if feature available)) */
196 #define HAL_ADC_STATE_INJ_EOC ((uint32_t)0x00002000U) /*!< Conversion data available on group injected */
197
198 /* States of ADC analog watchdogs */
199 #define HAL_ADC_STATE_AWD1 ((uint32_t)0x00010000U) /*!< Out-of-window occurrence of analog watchdog 1 */
200 #define HAL_ADC_STATE_AWD2 ((uint32_t)0x00020000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 2 */
201 #define HAL_ADC_STATE_AWD3 ((uint32_t)0x00040000U) /*!< Not available on STM32F7 device: Out-of-window occurrence of analog watchdog 3 */
202
203 /* States of ADC multi-mode */
204 #define HAL_ADC_STATE_MULTIMODE_SLAVE ((uint32_t)0x00100000U) /*!< Not available on STM32F7 device: ADC in multimode slave state, controlled by another ADC master ( */
205
206
207 /**
208 * @brief ADC handle Structure definition
209 */
210 typedef struct
211 {
212 ADC_TypeDef *Instance; /*!< Register base address */
213
214 ADC_InitTypeDef Init; /*!< ADC required parameters */
215
216 __IO uint32_t NbrOfCurrentConversionRank; /*!< ADC number of current conversion rank */
217
218 DMA_HandleTypeDef *DMA_Handle; /*!< Pointer DMA Handler */
219
220 HAL_LockTypeDef Lock; /*!< ADC locking object */
221
222 __IO uint32_t State; /*!< ADC communication state */
223
224 __IO uint32_t ErrorCode; /*!< ADC Error code */
225 }ADC_HandleTypeDef;
226 /**
227 * @}
228 */
229
230 /* Exported constants --------------------------------------------------------*/
231 /** @defgroup ADC_Exported_Constants ADC Exported Constants
232 * @{
233 */
234
235 /** @defgroup ADC_Error_Code ADC Error Code
236 * @{
237 */
238 #define HAL_ADC_ERROR_NONE ((uint32_t)0x00U) /*!< No error */
239 #define HAL_ADC_ERROR_INTERNAL ((uint32_t)0x01U) /*!< ADC IP internal error: if problem of clocking,
240 enable/disable, erroneous state */
241 #define HAL_ADC_ERROR_OVR ((uint32_t)0x02U) /*!< Overrun error */
242 #define HAL_ADC_ERROR_DMA ((uint32_t)0x04U) /*!< DMA transfer error */
243 /**
244 * @}
245 */
246
247
248 /** @defgroup ADC_ClockPrescaler ADC Clock Prescaler
249 * @{
250 */
251 #define ADC_CLOCK_SYNC_PCLK_DIV2 ((uint32_t)0x00000000U)
252 #define ADC_CLOCK_SYNC_PCLK_DIV4 ((uint32_t)ADC_CCR_ADCPRE_0)
253 #define ADC_CLOCK_SYNC_PCLK_DIV6 ((uint32_t)ADC_CCR_ADCPRE_1)
254 #define ADC_CLOCK_SYNC_PCLK_DIV8 ((uint32_t)ADC_CCR_ADCPRE)
255 /**
256 * @}
257 */
258
259 /** @defgroup ADC_delay_between_2_sampling_phases ADC Delay Between 2 Sampling Phases
260 * @{
261 */
262 #define ADC_TWOSAMPLINGDELAY_5CYCLES ((uint32_t)0x00000000U)
263 #define ADC_TWOSAMPLINGDELAY_6CYCLES ((uint32_t)ADC_CCR_DELAY_0)
264 #define ADC_TWOSAMPLINGDELAY_7CYCLES ((uint32_t)ADC_CCR_DELAY_1)
265 #define ADC_TWOSAMPLINGDELAY_8CYCLES ((uint32_t)(ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
266 #define ADC_TWOSAMPLINGDELAY_9CYCLES ((uint32_t)ADC_CCR_DELAY_2)
267 #define ADC_TWOSAMPLINGDELAY_10CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
268 #define ADC_TWOSAMPLINGDELAY_11CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
269 #define ADC_TWOSAMPLINGDELAY_12CYCLES ((uint32_t)(ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
270 #define ADC_TWOSAMPLINGDELAY_13CYCLES ((uint32_t)ADC_CCR_DELAY_3)
271 #define ADC_TWOSAMPLINGDELAY_14CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_0))
272 #define ADC_TWOSAMPLINGDELAY_15CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1))
273 #define ADC_TWOSAMPLINGDELAY_16CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_1 | ADC_CCR_DELAY_0))
274 #define ADC_TWOSAMPLINGDELAY_17CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2))
275 #define ADC_TWOSAMPLINGDELAY_18CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_0))
276 #define ADC_TWOSAMPLINGDELAY_19CYCLES ((uint32_t)(ADC_CCR_DELAY_3 | ADC_CCR_DELAY_2 | ADC_CCR_DELAY_1))
277 #define ADC_TWOSAMPLINGDELAY_20CYCLES ((uint32_t)ADC_CCR_DELAY)
278 /**
279 * @}
280 */
281
282 /** @defgroup ADC_Resolution ADC Resolution
283 * @{
284 */
285 #define ADC_RESOLUTION_12B ((uint32_t)0x00000000U)
286 #define ADC_RESOLUTION_10B ((uint32_t)ADC_CR1_RES_0)
287 #define ADC_RESOLUTION_8B ((uint32_t)ADC_CR1_RES_1)
288 #define ADC_RESOLUTION_6B ((uint32_t)ADC_CR1_RES)
289 /**
290 * @}
291 */
292
293 /** @defgroup ADC_External_trigger_edge_Regular ADC External Trigger Edge Regular
294 * @{
295 */
296 #define ADC_EXTERNALTRIGCONVEDGE_NONE ((uint32_t)0x00000000U)
297 #define ADC_EXTERNALTRIGCONVEDGE_RISING ((uint32_t)ADC_CR2_EXTEN_0)
298 #define ADC_EXTERNALTRIGCONVEDGE_FALLING ((uint32_t)ADC_CR2_EXTEN_1)
299 #define ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING ((uint32_t)ADC_CR2_EXTEN)
300 /**
301 * @}
302 */
303
304 /** @defgroup ADC_External_trigger_Source_Regular ADC External Trigger Source Regular
305 * @{
306 */
307 /* Note: Parameter ADC_SOFTWARE_START is a software parameter used for */
308 /* compatibility with other STM32 devices. */
309
310
311 #define ADC_EXTERNALTRIGCONV_T1_CC1 ((uint32_t)0x00000000U)
312 #define ADC_EXTERNALTRIGCONV_T1_CC2 ((uint32_t)ADC_CR2_EXTSEL_0)
313 #define ADC_EXTERNALTRIGCONV_T1_CC3 ((uint32_t)ADC_CR2_EXTSEL_1)
314 #define ADC_EXTERNALTRIGCONV_T2_CC2 ((uint32_t)(ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
315 #define ADC_EXTERNALTRIGCONV_T5_TRGO ((uint32_t)ADC_CR2_EXTSEL_2)
316 #define ADC_EXTERNALTRIGCONV_T4_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
317 #define ADC_EXTERNALTRIGCONV_T3_CC4 ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1))
318 #define ADC_EXTERNALTRIGCONV_T8_TRGO ((uint32_t)(ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
319 #define ADC_EXTERNALTRIGCONV_T8_TRGO2 ((uint32_t)ADC_CR2_EXTSEL_3)
320 #define ADC_EXTERNALTRIGCONV_T1_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_0))
321 #define ADC_EXTERNALTRIGCONV_T1_TRGO2 ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1))
322 #define ADC_EXTERNALTRIGCONV_T2_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_1 | ADC_CR2_EXTSEL_0))
323 #define ADC_EXTERNALTRIGCONV_T4_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2))
324 #define ADC_EXTERNALTRIGCONV_T6_TRGO ((uint32_t)(ADC_CR2_EXTSEL_3 | ADC_CR2_EXTSEL_2 | ADC_CR2_EXTSEL_0))
325
326 #define ADC_EXTERNALTRIGCONV_EXT_IT11 ((uint32_t)ADC_CR2_EXTSEL)
327 #define ADC_SOFTWARE_START ((uint32_t)ADC_CR2_EXTSEL + 1)
328
329 /**
330 * @}
331 */
332
333 /** @defgroup ADC_Data_Align ADC Data Align
334 * @{
335 */
336 #define ADC_DATAALIGN_RIGHT ((uint32_t)0x00000000U)
337 #define ADC_DATAALIGN_LEFT ((uint32_t)ADC_CR2_ALIGN)
338 /**
339 * @}
340 */
341
342 /** @defgroup ADC_Scan_mode ADC sequencer scan mode
343 * @{
344 */
345 #define ADC_SCAN_DISABLE ((uint32_t)0x00000000) /*!< Scan mode disabled */
346 #define ADC_SCAN_ENABLE ((uint32_t)0x00000001) /*!< Scan mode enabled */
347 /**
348 * @}
349 */
350
351 /** @defgroup ADC_regular_rank ADC group regular sequencer rank
352 * @{
353 */
354 #define ADC_REGULAR_RANK_1 ((uint32_t)0x00000001) /*!< ADC regular conversion rank 1 */
355 #define ADC_REGULAR_RANK_2 ((uint32_t)0x00000002) /*!< ADC regular conversion rank 2 */
356 #define ADC_REGULAR_RANK_3 ((uint32_t)0x00000003) /*!< ADC regular conversion rank 3 */
357 #define ADC_REGULAR_RANK_4 ((uint32_t)0x00000004) /*!< ADC regular conversion rank 4 */
358 #define ADC_REGULAR_RANK_5 ((uint32_t)0x00000005) /*!< ADC regular conversion rank 5 */
359 #define ADC_REGULAR_RANK_6 ((uint32_t)0x00000006) /*!< ADC regular conversion rank 6 */
360 #define ADC_REGULAR_RANK_7 ((uint32_t)0x00000007) /*!< ADC regular conversion rank 7 */
361 #define ADC_REGULAR_RANK_8 ((uint32_t)0x00000008) /*!< ADC regular conversion rank 8 */
362 #define ADC_REGULAR_RANK_9 ((uint32_t)0x00000009) /*!< ADC regular conversion rank 9 */
363 #define ADC_REGULAR_RANK_10 ((uint32_t)0x0000000A) /*!< ADC regular conversion rank 10 */
364 #define ADC_REGULAR_RANK_11 ((uint32_t)0x0000000B) /*!< ADC regular conversion rank 11 */
365 #define ADC_REGULAR_RANK_12 ((uint32_t)0x0000000C) /*!< ADC regular conversion rank 12 */
366 #define ADC_REGULAR_RANK_13 ((uint32_t)0x0000000D) /*!< ADC regular conversion rank 13 */
367 #define ADC_REGULAR_RANK_14 ((uint32_t)0x0000000E) /*!< ADC regular conversion rank 14 */
368 #define ADC_REGULAR_RANK_15 ((uint32_t)0x0000000F) /*!< ADC regular conversion rank 15 */
369 #define ADC_REGULAR_RANK_16 ((uint32_t)0x00000010) /*!< ADC regular conversion rank 16 */
370 /**
371 * @}
372 */
373
374 /** @defgroup ADC_channels ADC Common Channels
375 * @{
376 */
377 #define ADC_CHANNEL_0 ((uint32_t)0x00000000U)
378 #define ADC_CHANNEL_1 ((uint32_t)ADC_CR1_AWDCH_0)
379 #define ADC_CHANNEL_2 ((uint32_t)ADC_CR1_AWDCH_1)
380 #define ADC_CHANNEL_3 ((uint32_t)(ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
381 #define ADC_CHANNEL_4 ((uint32_t)ADC_CR1_AWDCH_2)
382 #define ADC_CHANNEL_5 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
383 #define ADC_CHANNEL_6 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
384 #define ADC_CHANNEL_7 ((uint32_t)(ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
385 #define ADC_CHANNEL_8 ((uint32_t)ADC_CR1_AWDCH_3)
386 #define ADC_CHANNEL_9 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_0))
387 #define ADC_CHANNEL_10 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1))
388 #define ADC_CHANNEL_11 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
389 #define ADC_CHANNEL_12 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2))
390 #define ADC_CHANNEL_13 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_0))
391 #define ADC_CHANNEL_14 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1))
392 #define ADC_CHANNEL_15 ((uint32_t)(ADC_CR1_AWDCH_3 | ADC_CR1_AWDCH_2 | ADC_CR1_AWDCH_1 | ADC_CR1_AWDCH_0))
393 #define ADC_CHANNEL_16 ((uint32_t)ADC_CR1_AWDCH_4)
394 #define ADC_CHANNEL_17 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_0))
395 #define ADC_CHANNEL_18 ((uint32_t)(ADC_CR1_AWDCH_4 | ADC_CR1_AWDCH_1))
396
397 #define ADC_CHANNEL_VREFINT ((uint32_t)ADC_CHANNEL_17)
398 #define ADC_CHANNEL_VBAT ((uint32_t)ADC_CHANNEL_18)
399 /**
400 * @}
401 */
402
403 /** @defgroup ADC_sampling_times ADC Sampling Times
404 * @{
405 */
406 #define ADC_SAMPLETIME_3CYCLES ((uint32_t)0x00000000U)
407 #define ADC_SAMPLETIME_15CYCLES ((uint32_t)ADC_SMPR1_SMP10_0)
408 #define ADC_SAMPLETIME_28CYCLES ((uint32_t)ADC_SMPR1_SMP10_1)
409 #define ADC_SAMPLETIME_56CYCLES ((uint32_t)(ADC_SMPR1_SMP10_1 | ADC_SMPR1_SMP10_0))
410 #define ADC_SAMPLETIME_84CYCLES ((uint32_t)ADC_SMPR1_SMP10_2)
411 #define ADC_SAMPLETIME_112CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_0))
412 #define ADC_SAMPLETIME_144CYCLES ((uint32_t)(ADC_SMPR1_SMP10_2 | ADC_SMPR1_SMP10_1))
413 #define ADC_SAMPLETIME_480CYCLES ((uint32_t)ADC_SMPR1_SMP10)
414 /**
415 * @}
416 */
417
418 /** @defgroup ADC_EOCSelection ADC EOC Selection
419 * @{
420 */
421 #define ADC_EOC_SEQ_CONV ((uint32_t)0x00000000U)
422 #define ADC_EOC_SINGLE_CONV ((uint32_t)0x00000001U)
423 #define ADC_EOC_SINGLE_SEQ_CONV ((uint32_t)0x00000002U) /*!< reserved for future use */
424 /**
425 * @}
426 */
427
428 /** @defgroup ADC_Event_type ADC Event Type
429 * @{
430 */
431 #define ADC_AWD_EVENT ((uint32_t)ADC_FLAG_AWD)
432 #define ADC_OVR_EVENT ((uint32_t)ADC_FLAG_OVR)
433 /**
434 * @}
435 */
436
437 /** @defgroup ADC_analog_watchdog_selection ADC Analog Watchdog Selection
438 * @{
439 */
440 #define ADC_ANALOGWATCHDOG_SINGLE_REG ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN))
441 #define ADC_ANALOGWATCHDOG_SINGLE_INJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_JAWDEN))
442 #define ADC_ANALOGWATCHDOG_SINGLE_REGINJEC ((uint32_t)(ADC_CR1_AWDSGL | ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
443 #define ADC_ANALOGWATCHDOG_ALL_REG ((uint32_t)ADC_CR1_AWDEN)
444 #define ADC_ANALOGWATCHDOG_ALL_INJEC ((uint32_t)ADC_CR1_JAWDEN)
445 #define ADC_ANALOGWATCHDOG_ALL_REGINJEC ((uint32_t)(ADC_CR1_AWDEN | ADC_CR1_JAWDEN))
446 #define ADC_ANALOGWATCHDOG_NONE ((uint32_t)0x00000000U)
447 /**
448 * @}
449 */
450
451 /** @defgroup ADC_interrupts_definition ADC Interrupts Definition
452 * @{
453 */
454 #define ADC_IT_EOC ((uint32_t)ADC_CR1_EOCIE)
455 #define ADC_IT_AWD ((uint32_t)ADC_CR1_AWDIE)
456 #define ADC_IT_JEOC ((uint32_t)ADC_CR1_JEOCIE)
457 #define ADC_IT_OVR ((uint32_t)ADC_CR1_OVRIE)
458 /**
459 * @}
460 */
461
462 /** @defgroup ADC_flags_definition ADC Flags Definition
463 * @{
464 */
465 #define ADC_FLAG_AWD ((uint32_t)ADC_SR_AWD)
466 #define ADC_FLAG_EOC ((uint32_t)ADC_SR_EOC)
467 #define ADC_FLAG_JEOC ((uint32_t)ADC_SR_JEOC)
468 #define ADC_FLAG_JSTRT ((uint32_t)ADC_SR_JSTRT)
469 #define ADC_FLAG_STRT ((uint32_t)ADC_SR_STRT)
470 #define ADC_FLAG_OVR ((uint32_t)ADC_SR_OVR)
471 /**
472 * @}
473 */
474
475 /** @defgroup ADC_channels_type ADC Channels Type
476 * @{
477 */
478 #define ADC_ALL_CHANNELS ((uint32_t)0x00000001U)
479 #define ADC_REGULAR_CHANNELS ((uint32_t)0x00000002U) /*!< reserved for future use */
480 #define ADC_INJECTED_CHANNELS ((uint32_t)0x00000003U) /*!< reserved for future use */
481 /**
482 * @}
483 */
484
485 /**
486 * @}
487 */
488
489 /* Exported macro ------------------------------------------------------------*/
490 /** @defgroup ADC_Exported_Macros ADC Exported Macros
491 * @{
492 */
493
494 /** @brief Reset ADC handle state
495 * @param __HANDLE__: ADC handle
496 * @retval None
497 */
498 #define __HAL_ADC_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_ADC_STATE_RESET)
499
500 /**
501 * @brief Enable the ADC peripheral.
502 * @param __HANDLE__: ADC handle
503 * @retval None
504 */
505 #define __HAL_ADC_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 |= ADC_CR2_ADON)
506
507 /**
508 * @brief Disable the ADC peripheral.
509 * @param __HANDLE__: ADC handle
510 * @retval None
511 */
512 #define __HAL_ADC_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR2 &= ~ADC_CR2_ADON)
513
514 /**
515 * @brief Enable the ADC end of conversion interrupt.
516 * @param __HANDLE__: specifies the ADC Handle.
517 * @param __INTERRUPT__: ADC Interrupt.
518 * @retval None
519 */
520 #define __HAL_ADC_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) |= (__INTERRUPT__))
521
522 /**
523 * @brief Disable the ADC end of conversion interrupt.
524 * @param __HANDLE__: specifies the ADC Handle.
525 * @param __INTERRUPT__: ADC interrupt.
526 * @retval None
527 */
528 #define __HAL_ADC_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1) &= ~(__INTERRUPT__))
529
530 /** @brief Check if the specified ADC interrupt source is enabled or disabled.
531 * @param __HANDLE__: specifies the ADC Handle.
532 * @param __INTERRUPT__: specifies the ADC interrupt source to check.
533 * @retval The new state of __IT__ (TRUE or FALSE).
534 */
535 #define __HAL_ADC_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__))
536
537 /**
538 * @brief Clear the ADC's pending flags.
539 * @param __HANDLE__: specifies the ADC Handle.
540 * @param __FLAG__: ADC flag.
541 * @retval None
542 */
543 #define __HAL_ADC_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR) = ~(__FLAG__))
544
545 /**
546 * @brief Get the selected ADC's flag status.
547 * @param __HANDLE__: specifies the ADC Handle.
548 * @param __FLAG__: ADC flag.
549 * @retval None
550 */
551 #define __HAL_ADC_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
552
553 /**
554 * @}
555 */
556
557 /* Include ADC HAL Extension module */
558 #include "stm32f7xx_hal_adc_ex.h"
559
560 /* Exported functions --------------------------------------------------------*/
561 /** @addtogroup ADC_Exported_Functions
562 * @{
563 */
564
565 /** @addtogroup ADC_Exported_Functions_Group1
566 * @{
567 */
568 /* Initialization/de-initialization functions ***********************************/
569 HAL_StatusTypeDef HAL_ADC_Init(ADC_HandleTypeDef* hadc);
570 HAL_StatusTypeDef HAL_ADC_DeInit(ADC_HandleTypeDef *hadc);
571 void HAL_ADC_MspInit(ADC_HandleTypeDef* hadc);
572 void HAL_ADC_MspDeInit(ADC_HandleTypeDef* hadc);
573 /**
574 * @}
575 */
576
577 /** @addtogroup ADC_Exported_Functions_Group2
578 * @{
579 */
580 /* I/O operation functions ******************************************************/
581 HAL_StatusTypeDef HAL_ADC_Start(ADC_HandleTypeDef* hadc);
582 HAL_StatusTypeDef HAL_ADC_Stop(ADC_HandleTypeDef* hadc);
583 HAL_StatusTypeDef HAL_ADC_PollForConversion(ADC_HandleTypeDef* hadc, uint32_t Timeout);
584
585 HAL_StatusTypeDef HAL_ADC_PollForEvent(ADC_HandleTypeDef* hadc, uint32_t EventType, uint32_t Timeout);
586
587 HAL_StatusTypeDef HAL_ADC_Start_IT(ADC_HandleTypeDef* hadc);
588 HAL_StatusTypeDef HAL_ADC_Stop_IT(ADC_HandleTypeDef* hadc);
589
590 void HAL_ADC_IRQHandler(ADC_HandleTypeDef* hadc);
591
592 HAL_StatusTypeDef HAL_ADC_Start_DMA(ADC_HandleTypeDef* hadc, uint32_t* pData, uint32_t Length);
593 HAL_StatusTypeDef HAL_ADC_Stop_DMA(ADC_HandleTypeDef* hadc);
594
595 uint32_t HAL_ADC_GetValue(ADC_HandleTypeDef* hadc);
596
597 void HAL_ADC_ConvCpltCallback(ADC_HandleTypeDef* hadc);
598 void HAL_ADC_ConvHalfCpltCallback(ADC_HandleTypeDef* hadc);
599 void HAL_ADC_LevelOutOfWindowCallback(ADC_HandleTypeDef* hadc);
600 void HAL_ADC_ErrorCallback(ADC_HandleTypeDef *hadc);
601 /**
602 * @}
603 */
604
605 /** @addtogroup ADC_Exported_Functions_Group3
606 * @{
607 */
608 /* Peripheral Control functions *************************************************/
609 HAL_StatusTypeDef HAL_ADC_ConfigChannel(ADC_HandleTypeDef* hadc, ADC_ChannelConfTypeDef* sConfig);
610 HAL_StatusTypeDef HAL_ADC_AnalogWDGConfig(ADC_HandleTypeDef* hadc, ADC_AnalogWDGConfTypeDef* AnalogWDGConfig);
611 /**
612 * @}
613 */
614
615 /** @addtogroup ADC_Exported_Functions_Group4
616 * @{
617 */
618 /* Peripheral State functions ***************************************************/
619 uint32_t HAL_ADC_GetState(ADC_HandleTypeDef* hadc);
620 uint32_t HAL_ADC_GetError(ADC_HandleTypeDef *hadc);
621 /**
622 * @}
623 */
624
625 /**
626 * @}
627 */
628
629 /* Private types -------------------------------------------------------------*/
630 /* Private variables ---------------------------------------------------------*/
631 /* Private constants ---------------------------------------------------------*/
632 /** @defgroup ADC_Private_Constants ADC Private Constants
633 * @{
634 */
635 /* Delay for ADC stabilization time. */
636 /* Maximum delay is 1us (refer to device datasheet, parameter tSTAB). */
637 /* Unit: us */
638 #define ADC_STAB_DELAY_US ((uint32_t) 3U)
639 /* Delay for temperature sensor stabilization time. */
640 /* Maximum delay is 10us (refer to device datasheet, parameter tSTART). */
641 /* Unit: us */
642 #define ADC_TEMPSENSOR_DELAY_US ((uint32_t) 10U)
643 /**
644 * @}
645 */
646
647 /* Private macros ------------------------------------------------------------*/
648 /** @defgroup ADC_Private_Macros ADC Private Macros
649 * @{
650 */
651 /* Macro reserved for internal HAL driver usage, not intended to be used in
652 code of final user */
653
654 /**
655 * @brief Verification of ADC state: enabled or disabled
656 * @param __HANDLE__: ADC handle
657 * @retval SET (ADC enabled) or RESET (ADC disabled)
658 */
659 #define ADC_IS_ENABLE(__HANDLE__) \
660 ((( ((__HANDLE__)->Instance->SR & ADC_SR_ADONS) == ADC_SR_ADONS ) \
661 ) ? SET : RESET)
662
663 /**
664 * @brief Test if conversion trigger of regular group is software start
665 * or external trigger.
666 * @param __HANDLE__: ADC handle
667 * @retval SET (software start) or RESET (external trigger)
668 */
669 #define ADC_IS_SOFTWARE_START_REGULAR(__HANDLE__) \
670 (((__HANDLE__)->Instance->CR2 & ADC_CR2_EXTEN) == RESET)
671
672 /**
673 * @brief Test if conversion trigger of injected group is software start
674 * or external trigger.
675 * @param __HANDLE__: ADC handle
676 * @retval SET (software start) or RESET (external trigger)
677 */
678 #define ADC_IS_SOFTWARE_START_INJECTED(__HANDLE__) \
679 (((__HANDLE__)->Instance->CR2 & ADC_CR2_JEXTEN) == RESET)
680
681 /**
682 * @brief Simultaneously clears and sets specific bits of the handle State
683 * @note: ADC_STATE_CLR_SET() macro is merely aliased to generic macro MODIFY_REG(),
684 * the first parameter is the ADC handle State, the second parameter is the
685 * bit field to clear, the third and last parameter is the bit field to set.
686 * @retval None
687 */
688 #define ADC_STATE_CLR_SET MODIFY_REG
689
690 /**
691 * @brief Clear ADC error code (set it to error code: "no error")
692 * @param __HANDLE__: ADC handle
693 * @retval None
694 */
695 #define ADC_CLEAR_ERRORCODE(__HANDLE__) \
696 ((__HANDLE__)->ErrorCode = HAL_ADC_ERROR_NONE)
697 #define IS_ADC_CLOCKPRESCALER(__ADC_CLOCK__) (((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV2) || \
698 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV4) || \
699 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV6) || \
700 ((__ADC_CLOCK__) == ADC_CLOCK_SYNC_PCLK_DIV8))
701 #define IS_ADC_SAMPLING_DELAY(__DELAY__) (((__DELAY__) == ADC_TWOSAMPLINGDELAY_5CYCLES) || \
702 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_6CYCLES) || \
703 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_7CYCLES) || \
704 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_8CYCLES) || \
705 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_9CYCLES) || \
706 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_10CYCLES) || \
707 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_11CYCLES) || \
708 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_12CYCLES) || \
709 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_13CYCLES) || \
710 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_14CYCLES) || \
711 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_15CYCLES) || \
712 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_16CYCLES) || \
713 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_17CYCLES) || \
714 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_18CYCLES) || \
715 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_19CYCLES) || \
716 ((__DELAY__) == ADC_TWOSAMPLINGDELAY_20CYCLES))
717 #define IS_ADC_RESOLUTION(__RESOLUTION__) (((__RESOLUTION__) == ADC_RESOLUTION_12B) || \
718 ((__RESOLUTION__) == ADC_RESOLUTION_10B) || \
719 ((__RESOLUTION__) == ADC_RESOLUTION_8B) || \
720 ((__RESOLUTION__) == ADC_RESOLUTION_6B))
721 #define IS_ADC_EXT_TRIG_EDGE(__EDGE__) (((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_NONE) || \
722 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISING) || \
723 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_FALLING) || \
724 ((__EDGE__) == ADC_EXTERNALTRIGCONVEDGE_RISINGFALLING))
725 #define IS_ADC_EXT_TRIG(__REGTRIG__) (((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC1) || \
726 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC2) || \
727 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_CC3) || \
728 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_CC2) || \
729 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T5_TRGO) || \
730 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_CC4) || \
731 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T3_CC4) || \
732 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO) || \
733 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T8_TRGO2) || \
734 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO) || \
735 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T1_TRGO2) || \
736 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T2_TRGO) || \
737 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T4_TRGO) || \
738 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_T6_TRGO) || \
739 ((__REGTRIG__) == ADC_EXTERNALTRIGCONV_EXT_IT11) || \
740 ((__REGTRIG__) == ADC_SOFTWARE_START))
741 #define IS_ADC_DATA_ALIGN(__ALIGN__) (((__ALIGN__) == ADC_DATAALIGN_RIGHT) || \
742 ((__ALIGN__) == ADC_DATAALIGN_LEFT))
743
744
745 #define IS_ADC_SAMPLE_TIME(__TIME__) (((__TIME__) == ADC_SAMPLETIME_3CYCLES) || \
746 ((__TIME__) == ADC_SAMPLETIME_15CYCLES) || \
747 ((__TIME__) == ADC_SAMPLETIME_28CYCLES) || \
748 ((__TIME__) == ADC_SAMPLETIME_56CYCLES) || \
749 ((__TIME__) == ADC_SAMPLETIME_84CYCLES) || \
750 ((__TIME__) == ADC_SAMPLETIME_112CYCLES) || \
751 ((__TIME__) == ADC_SAMPLETIME_144CYCLES) || \
752 ((__TIME__) == ADC_SAMPLETIME_480CYCLES))
753 #define IS_ADC_EOCSelection(__EOCSelection__) (((__EOCSelection__) == ADC_EOC_SINGLE_CONV) || \
754 ((__EOCSelection__) == ADC_EOC_SEQ_CONV) || \
755 ((__EOCSelection__) == ADC_EOC_SINGLE_SEQ_CONV))
756 #define IS_ADC_EVENT_TYPE(__EVENT__) (((__EVENT__) == ADC_AWD_EVENT) || \
757 ((__EVENT__) == ADC_OVR_EVENT))
758 #define IS_ADC_ANALOG_WATCHDOG(__WATCHDOG__) (((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REG) || \
759 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_INJEC) || \
760 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_SINGLE_REGINJEC) || \
761 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REG) || \
762 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_INJEC) || \
763 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_ALL_REGINJEC) || \
764 ((__WATCHDOG__) == ADC_ANALOGWATCHDOG_NONE))
765 #define IS_ADC_CHANNELS_TYPE(CHANNEL_TYPE) (((CHANNEL_TYPE) == ADC_ALL_CHANNELS) || \
766 ((CHANNEL_TYPE) == ADC_REGULAR_CHANNELS) || \
767 ((CHANNEL_TYPE) == ADC_INJECTED_CHANNELS))
768
769 #define IS_ADC_REGULAR_RANK(__RANK__) (((__RANK__) == ADC_REGULAR_RANK_1 ) || \
770 ((__RANK__) == ADC_REGULAR_RANK_2 ) || \
771 ((__RANK__) == ADC_REGULAR_RANK_3 ) || \
772 ((__RANK__) == ADC_REGULAR_RANK_4 ) || \
773 ((__RANK__) == ADC_REGULAR_RANK_5 ) || \
774 ((__RANK__) == ADC_REGULAR_RANK_6 ) || \
775 ((__RANK__) == ADC_REGULAR_RANK_7 ) || \
776 ((__RANK__) == ADC_REGULAR_RANK_8 ) || \
777 ((__RANK__) == ADC_REGULAR_RANK_9 ) || \
778 ((__RANK__) == ADC_REGULAR_RANK_10) || \
779 ((__RANK__) == ADC_REGULAR_RANK_11) || \
780 ((__RANK__) == ADC_REGULAR_RANK_12) || \
781 ((__RANK__) == ADC_REGULAR_RANK_13) || \
782 ((__RANK__) == ADC_REGULAR_RANK_14) || \
783 ((__RANK__) == ADC_REGULAR_RANK_15) || \
784 ((__RANK__) == ADC_REGULAR_RANK_16))
785
786 #define IS_ADC_SCAN_MODE(__SCAN_MODE__) (((__SCAN_MODE__) == ADC_SCAN_DISABLE) || \
787 ((__SCAN_MODE__) == ADC_SCAN_ENABLE))
788
789 #define IS_ADC_THRESHOLD(__THRESHOLD__) ((__THRESHOLD__) <= ((uint32_t)0xFFF))
790 #define IS_ADC_REGULAR_LENGTH(__LENGTH__) (((__LENGTH__) >= ((uint32_t)1)) && ((__LENGTH__) <= ((uint32_t)16)))
791 #define IS_ADC_REGULAR_DISC_NUMBER(__NUMBER__) (((__NUMBER__) >= ((uint32_t)1)) && ((__NUMBER__) <= ((uint32_t)8)))
792 #define IS_ADC_RANGE(__RESOLUTION__, __ADC_VALUE__) \
793 ((((__RESOLUTION__) == ADC_RESOLUTION_12B) && ((__ADC_VALUE__) <= ((uint32_t)0x0FFF))) || \
794 (((__RESOLUTION__) == ADC_RESOLUTION_10B) && ((__ADC_VALUE__) <= ((uint32_t)0x03FF))) || \
795 (((__RESOLUTION__) == ADC_RESOLUTION_8B) && ((__ADC_VALUE__) <= ((uint32_t)0x00FF))) || \
796 (((__RESOLUTION__) == ADC_RESOLUTION_6B) && ((__ADC_VALUE__) <= ((uint32_t)0x003F))))
797
798 /**
799 * @brief Set ADC Regular channel sequence length.
800 * @param _NbrOfConversion_: Regular channel sequence length.
801 * @retval None
802 */
803 #define ADC_SQR1(_NbrOfConversion_) (((_NbrOfConversion_) - (uint8_t)1) << 20)
804
805 /**
806 * @brief Set the ADC's sample time for channel numbers between 10 and 18.
807 * @param _SAMPLETIME_: Sample time parameter.
808 * @param _CHANNELNB_: Channel number.
809 * @retval None
810 */
811 #define ADC_SMPR1(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * (((uint32_t)((uint16_t)(_CHANNELNB_))) - 10)))
812
813 /**
814 * @brief Set the ADC's sample time for channel numbers between 0 and 9.
815 * @param _SAMPLETIME_: Sample time parameter.
816 * @param _CHANNELNB_: Channel number.
817 * @retval None
818 */
819 #define ADC_SMPR2(_SAMPLETIME_, _CHANNELNB_) ((_SAMPLETIME_) << (3 * ((uint32_t)((uint16_t)(_CHANNELNB_)))))
820
821 /**
822 * @brief Set the selected regular channel rank for rank between 1 and 6.
823 * @param _CHANNELNB_: Channel number.
824 * @param _RANKNB_: Rank number.
825 * @retval None
826 */
827 #define ADC_SQR3_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 1)))
828
829 /**
830 * @brief Set the selected regular channel rank for rank between 7 and 12.
831 * @param _CHANNELNB_: Channel number.
832 * @param _RANKNB_: Rank number.
833 * @retval None
834 */
835 #define ADC_SQR2_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 7)))
836
837 /**
838 * @brief Set the selected regular channel rank for rank between 13 and 16.
839 * @param _CHANNELNB_: Channel number.
840 * @param _RANKNB_: Rank number.
841 * @retval None
842 */
843 #define ADC_SQR1_RK(_CHANNELNB_, _RANKNB_) (((uint32_t)((uint16_t)(_CHANNELNB_))) << (5 * ((_RANKNB_) - 13)))
844
845 /**
846 * @brief Enable ADC continuous conversion mode.
847 * @param _CONTINUOUS_MODE_: Continuous mode.
848 * @retval None
849 */
850 #define ADC_CR2_CONTINUOUS(_CONTINUOUS_MODE_) ((_CONTINUOUS_MODE_) << 1)
851
852 /**
853 * @brief Configures the number of discontinuous conversions for the regular group channels.
854 * @param _NBR_DISCONTINUOUSCONV_: Number of discontinuous conversions.
855 * @retval None
856 */
857 #define ADC_CR1_DISCONTINUOUS(_NBR_DISCONTINUOUSCONV_) (((_NBR_DISCONTINUOUSCONV_) - 1) << POSITION_VAL(ADC_CR1_DISCNUM))
858
859 /**
860 * @brief Enable ADC scan mode.
861 * @param _SCANCONV_MODE_: Scan conversion mode.
862 * @retval None
863 */
864 #define ADC_CR1_SCANCONV(_SCANCONV_MODE_) ((_SCANCONV_MODE_) << 8)
865
866 /**
867 * @brief Enable the ADC end of conversion selection.
868 * @param _EOCSelection_MODE_: End of conversion selection mode.
869 * @retval None
870 */
871 #define ADC_CR2_EOCSelection(_EOCSelection_MODE_) ((_EOCSelection_MODE_) << 10)
872
873 /**
874 * @brief Enable the ADC DMA continuous request.
875 * @param _DMAContReq_MODE_: DMA continuous request mode.
876 * @retval None
877 */
878 #define ADC_CR2_DMAContReq(_DMAContReq_MODE_) ((_DMAContReq_MODE_) << 9)
879
880 /**
881 * @brief Return resolution bits in CR1 register.
882 * @param __HANDLE__: ADC handle
883 * @retval None
884 */
885 #define ADC_GET_RESOLUTION(__HANDLE__) (((__HANDLE__)->Instance->CR1) & ADC_CR1_RES)
886
887 /**
888 * @}
889 */
890
891 /* Private functions ---------------------------------------------------------*/
892 /** @defgroup ADC_Private_Functions ADC Private Functions
893 * @{
894 */
895
896 /**
897 * @}
898 */
899
900 /**
901 * @}
902 */
903
904 /**
905 * @}
906 */
907
908 #ifdef __cplusplus
909 }
910 #endif
911
912 #endif /*__STM32F7xx_ADC_H */
913
914
915 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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