lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_dma2d.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_dma2d.h
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   Header file of DMA2D HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_DMA2D_H
  40 #define __STM32F7xx_HAL_DMA2D_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_hal_def.h"
  48
  49 #if defined (DMA2D)
  50
  51 /** @addtogroup STM32F7xx_HAL_Driver
  52   * @{
  53   */
  54
  55 /** @addtogroup DMA2D DMA2D
  56   * @brief DMA2D HAL module driver
  57   * @{
  58   */
  59
  60 /* Exported types ------------------------------------------------------------*/
  61 /** @defgroup DMA2D_Exported_Types DMA2D Exported Types
  62   * @{
  63   */
  64 #define MAX_DMA2D_LAYER  2
  65
  66 /**
  67   * @brief DMA2D color Structure definition
  68   */
  69 typedef struct
  70 {
  71   uint32_t Blue;               /*!< Configures the blue value.
  72                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  73
  74   uint32_t Green;              /*!< Configures the green value.
  75                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  76
  77   uint32_t Red;                /*!< Configures the red value.
  78                                     This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF. */
  79 } DMA2D_ColorTypeDef;
  80
  81 /**
  82   * @brief DMA2D CLUT Structure definition
  83   */
  84 typedef struct
  85 {
  86   uint32_t *pCLUT;                  /*!< Configures the DMA2D CLUT memory address.*/
  87
  88   uint32_t CLUTColorMode;           /*!< Configures the DMA2D CLUT color mode.
  89                                          This parameter can be one value of @ref DMA2D_CLUT_CM. */
  90
  91   uint32_t Size;                    /*!< Configures the DMA2D CLUT size.
  92                                          This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.*/
  93 } DMA2D_CLUTCfgTypeDef;
  94
  95 /**
  96   * @brief DMA2D Init structure definition
  97   */
  98 typedef struct
  99 {
 100   uint32_t             Mode;               /*!< Configures the DMA2D transfer mode.
 101                                                 This parameter can be one value of @ref DMA2D_Mode. */
 102
 103   uint32_t             ColorMode;          /*!< Configures the color format of the output image.
 104                                                 This parameter can be one value of @ref DMA2D_Output_Color_Mode. */
 105
 106   uint32_t             OutputOffset;       /*!< Specifies the Offset value.
 107                                                 This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 108 #if defined (DMA2D_OPFCCR_AI)
 109   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value for the output pixel format converter.
 110                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted. */
 111 #endif /* DMA2D_OPFCCR_AI */
 112
 113 #if defined (DMA2D_OPFCCR_RBS)
 114   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR)
 115                                                for the output pixel format converter.
 116                                                This parameter can be one value of @ref DMA2D_RB_Swap. */
 117 #endif /* DMA2D_OPFCCR_RBS */
 118
 119 } DMA2D_InitTypeDef;
 120
 121
 122 /**
 123   * @brief DMA2D Layer structure definition
 124   */
 125 typedef struct
 126 {
 127   uint32_t             InputOffset;       /*!< Configures the DMA2D foreground or background offset.
 128                                                This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF. */
 129
 130   uint32_t             InputColorMode;    /*!< Configures the DMA2D foreground or background color mode.
 131                                                This parameter can be one value of @ref DMA2D_Input_Color_Mode. */
 132
 133   uint32_t             AlphaMode;         /*!< Configures the DMA2D foreground or background alpha mode.
 134                                                This parameter can be one value of @ref DMA2D_Alpha_Mode. */
 135
 136   uint32_t             InputAlpha;        /*!< Specifies the DMA2D foreground or background alpha value and color value in case of A8 or A4 color mode.
 137                                                This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF except for the color modes detailed below.
 138                                                @note In case of A8 or A4 color mode (ARGB), this parameter must be a number between
 139                                                Min_Data = 0x00000000 and Max_Data = 0xFFFFFFFF where
 140                                                - InputAlpha[24:31] is the alpha value ALPHA[0:7]
 141                                                - InputAlpha[16:23] is the red value RED[0:7]
 142                                                - InputAlpha[8:15] is the green value GREEN[0:7]
 143                                                - InputAlpha[0:7] is the blue value BLUE[0:7]. */
 144
 145 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
 146   uint32_t             AlphaInverted;     /*!< Select regular or inverted alpha value.
 147                                                This parameter can be one value of @ref DMA2D_Alpha_Inverted.
 148                                                This feature is only available on devices :
 149                                                STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
 150
 151 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */
 152
 153 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
 154   uint32_t             RedBlueSwap;       /*!< Select regular mode (RGB or ARGB) or swap mode (BGR or ABGR).
 155                                                This parameter can be one value of @ref DMA2D_RB_Swap
 156                                                This feature is only available on devices :
 157                                                STM32F756xx, STM32F767xx, STM32F769xx, STM32F777xx and STM32F779xx.*/
 158
 159 #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */
 160
 161 } DMA2D_LayerCfgTypeDef;
 162
 163 /**
 164   * @brief  HAL DMA2D State structures definition
 165   */
 166 typedef enum
 167 {
 168   HAL_DMA2D_STATE_RESET             = 0x00U,    /*!< DMA2D not yet initialized or disabled       */
 169   HAL_DMA2D_STATE_READY             = 0x01U,    /*!< Peripheral Initialized and ready for use    */
 170   HAL_DMA2D_STATE_BUSY              = 0x02U,    /*!< An internal process is ongoing              */
 171   HAL_DMA2D_STATE_TIMEOUT           = 0x03U,    /*!< Timeout state                               */
 172   HAL_DMA2D_STATE_ERROR             = 0x04U,    /*!< DMA2D state error                           */
 173   HAL_DMA2D_STATE_SUSPEND           = 0x05U     /*!< DMA2D process is suspended                  */
 174 }HAL_DMA2D_StateTypeDef;
 175
 176 /**
 177   * @brief  DMA2D handle Structure definition
 178   */
 179 typedef struct __DMA2D_HandleTypeDef
 180 {
 181   DMA2D_TypeDef               *Instance;                                                    /*!< DMA2D register base address.               */
 182
 183   DMA2D_InitTypeDef           Init;                                                         /*!< DMA2D communication parameters.            */
 184
 185   void                        (* XferCpltCallback)(struct __DMA2D_HandleTypeDef * hdma2d);  /*!< DMA2D transfer complete callback.          */
 186
 187   void                        (* XferErrorCallback)(struct __DMA2D_HandleTypeDef * hdma2d); /*!< DMA2D transfer error callback.             */
 188
 189   DMA2D_LayerCfgTypeDef       LayerCfg[MAX_DMA2D_LAYER];                                    /*!< DMA2D Layers parameters           */
 190
 191   HAL_LockTypeDef             Lock;                                                         /*!< DMA2D lock.                                */
 192
 193   __IO HAL_DMA2D_StateTypeDef State;                                                        /*!< DMA2D transfer state.                      */
 194
 195   __IO uint32_t               ErrorCode;                                                    /*!< DMA2D error code.                          */
 196 } DMA2D_HandleTypeDef;
 197 /**
 198   * @}
 199   */
 200
 201 /* Exported constants --------------------------------------------------------*/
 202 /** @defgroup DMA2D_Exported_Constants DMA2D Exported Constants
 203   * @{
 204   */
 205
 206 /** @defgroup DMA2D_Error_Code DMA2D Error Code
 207   * @{
 208   */
 209 #define HAL_DMA2D_ERROR_NONE        ((uint32_t)0x00000000U)  /*!< No error             */
 210 #define HAL_DMA2D_ERROR_TE          ((uint32_t)0x00000001U)  /*!< Transfer error       */
 211 #define HAL_DMA2D_ERROR_CE          ((uint32_t)0x00000002U)  /*!< Configuration error  */
 212 #define HAL_DMA2D_ERROR_CAE         ((uint32_t)0x00000004U)  /*!< CLUT access error    */
 213 #define HAL_DMA2D_ERROR_TIMEOUT     ((uint32_t)0x00000020U)  /*!< Timeout error        */
 214 /**
 215   * @}
 216   */
 217
 218 /** @defgroup DMA2D_Mode DMA2D Mode
 219   * @{
 220   */
 221 #define DMA2D_M2M                   ((uint32_t)0x00000000U)  /*!< DMA2D memory to memory transfer mode */
 222 #define DMA2D_M2M_PFC               DMA2D_CR_MODE_0          /*!< DMA2D memory to memory with pixel format conversion transfer mode */
 223 #define DMA2D_M2M_BLEND             DMA2D_CR_MODE_1          /*!< DMA2D memory to memory with blending transfer mode */
 224 #define DMA2D_R2M                   DMA2D_CR_MODE            /*!< DMA2D register to memory transfer mode */
 225 /**
 226   * @}
 227   */
 228
 229 /** @defgroup DMA2D_Output_Color_Mode DMA2D Output Color Mode
 230   * @{
 231   */
 232 #define DMA2D_OUTPUT_ARGB8888       ((uint32_t)0x00000000U)               /*!< ARGB8888 DMA2D color mode */
 233 #define DMA2D_OUTPUT_RGB888         DMA2D_OPFCCR_CM_0                     /*!< RGB888 DMA2D color mode   */
 234 #define DMA2D_OUTPUT_RGB565         DMA2D_OPFCCR_CM_1                     /*!< RGB565 DMA2D color mode   */
 235 #define DMA2D_OUTPUT_ARGB1555       (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 DMA2D color mode */
 236 #define DMA2D_OUTPUT_ARGB4444       DMA2D_OPFCCR_CM_2                     /*!< ARGB4444 DMA2D color mode */
 237 /**
 238   * @}
 239   */
 240
 241 /** @defgroup DMA2D_Input_Color_Mode DMA2D Input Color Mode
 242   * @{
 243   */
 244 #define DMA2D_INPUT_ARGB8888        ((uint32_t)0x00000000U)  /*!< ARGB8888 color mode */
 245 #define DMA2D_INPUT_RGB888          ((uint32_t)0x00000001U)  /*!< RGB888 color mode   */
 246 #define DMA2D_INPUT_RGB565          ((uint32_t)0x00000002U)  /*!< RGB565 color mode   */
 247 #define DMA2D_INPUT_ARGB1555        ((uint32_t)0x00000003U)  /*!< ARGB1555 color mode */
 248 #define DMA2D_INPUT_ARGB4444        ((uint32_t)0x00000004U)  /*!< ARGB4444 color mode */
 249 #define DMA2D_INPUT_L8              ((uint32_t)0x00000005U)  /*!< L8 color mode       */
 250 #define DMA2D_INPUT_AL44            ((uint32_t)0x00000006U)  /*!< AL44 color mode     */
 251 #define DMA2D_INPUT_AL88            ((uint32_t)0x00000007U)  /*!< AL88 color mode     */
 252 #define DMA2D_INPUT_L4              ((uint32_t)0x00000008U)  /*!< L4 color mode       */
 253 #define DMA2D_INPUT_A8              ((uint32_t)0x00000009U)  /*!< A8 color mode       */
 254 #define DMA2D_INPUT_A4              ((uint32_t)0x0000000AU)  /*!< A4 color mode       */
 255 /**
 256   * @}
 257   */
 258
 259 /** @defgroup DMA2D_Alpha_Mode DMA2D Alpha Mode
 260   * @{
 261   */
 262 #define DMA2D_NO_MODIF_ALPHA        ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
 263 #define DMA2D_REPLACE_ALPHA         ((uint32_t)0x00000001U)  /*!< Replace original alpha channel value by programmed alpha value */
 264 #define DMA2D_COMBINE_ALPHA         ((uint32_t)0x00000002U)  /*!< Replace original alpha channel value by programmed alpha value
 265                                                                 with original alpha channel value                              */
 266 /**
 267   * @}
 268   */
 269
 270 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
 271 /** @defgroup DMA2D_Alpha_Inverted DMA2D ALPHA Inversion
 272   * @{
 273   */
 274 #define DMA2D_REGULAR_ALPHA         ((uint32_t)0x00000000U)  /*!< No modification of the alpha channel value */
 275 #define DMA2D_INVERTED_ALPHA        ((uint32_t)0x00000001U)  /*!< Invert the alpha channel value */
 276 /**
 277   * @}
 278   */
 279 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI)  */
 280
 281 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
 282 /** @defgroup DMA2D_RB_Swap DMA2D Red and Blue Swap
 283   * @{
 284   */
 285 #define DMA2D_RB_REGULAR            ((uint32_t)0x00000000U)  /*!< Select regular mode (RGB or ARGB) */
 286 #define DMA2D_RB_SWAP               ((uint32_t)0x00000001U)  /*!< Select swap mode (BGR or ABGR) */
 287 /**
 288   * @}
 289   */
 290 #endif /* (DMA2D_FGPFCCR_RBS) && (DMA2D_BGPFCCR_RBS)  */
 291
 292 /** @defgroup DMA2D_CLUT_CM DMA2D CLUT Color Mode
 293   * @{
 294   */
 295 #define DMA2D_CCM_ARGB8888          ((uint32_t)0x00000000U)  /*!< ARGB8888 DMA2D CLUT color mode */
 296 #define DMA2D_CCM_RGB888            ((uint32_t)0x00000001U)  /*!< RGB888 DMA2D CLUT color mode   */
 297 /**
 298   * @}
 299   */
 300
 301
 302 /** @defgroup DMA2D_Interrupts DMA2D Interrupts
 303   * @{
 304   */
 305 #define DMA2D_IT_CE                 DMA2D_CR_CEIE            /*!< Configuration Error Interrupt */
 306 #define DMA2D_IT_CTC                DMA2D_CR_CTCIE           /*!< CLUT Transfer Complete Interrupt */
 307 #define DMA2D_IT_CAE                DMA2D_CR_CAEIE           /*!< CLUT Access Error Interrupt */
 308 #define DMA2D_IT_TW                 DMA2D_CR_TWIE            /*!< Transfer Watermark Interrupt */
 309 #define DMA2D_IT_TC                 DMA2D_CR_TCIE            /*!< Transfer Complete Interrupt */
 310 #define DMA2D_IT_TE                 DMA2D_CR_TEIE            /*!< Transfer Error Interrupt */
 311 /**
 312   * @}
 313   */
 314
 315 /** @defgroup DMA2D_Flags DMA2D Flags
 316   * @{
 317   */
 318 #define DMA2D_FLAG_CE               DMA2D_ISR_CEIF           /*!< Configuration Error Interrupt Flag */
 319 #define DMA2D_FLAG_CTC              DMA2D_ISR_CTCIF          /*!< CLUT Transfer Complete Interrupt Flag */
 320 #define DMA2D_FLAG_CAE              DMA2D_ISR_CAEIF          /*!< CLUT Access Error Interrupt Flag */
 321 #define DMA2D_FLAG_TW               DMA2D_ISR_TWIF           /*!< Transfer Watermark Interrupt Flag */
 322 #define DMA2D_FLAG_TC               DMA2D_ISR_TCIF           /*!< Transfer Complete Interrupt Flag */
 323 #define DMA2D_FLAG_TE               DMA2D_ISR_TEIF           /*!< Transfer Error Interrupt Flag */
 324 /**
 325   * @}
 326   */
 327
 328 /** @defgroup DMA2D_Aliases DMA2D API Aliases
 329   * @{
 330   */
 331 #define HAL_DMA2D_DisableCLUT       HAL_DMA2D_CLUTLoading_Abort    /*!< Aliased to HAL_DMA2D_CLUTLoading_Abort for compatibility with legacy code */
 332 /**
 333   * @}
 334   */
 335
 336
 337 /**
 338   * @}
 339   */
 340 /* Exported macros ------------------------------------------------------------*/
 341 /** @defgroup DMA2D_Exported_Macros DMA2D Exported Macros
 342   * @{
 343   */
 344
 345 /** @brief Reset DMA2D handle state
 346   * @param  __HANDLE__: specifies the DMA2D handle.
 347   * @retval None
 348   */
 349 #define __HAL_DMA2D_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_DMA2D_STATE_RESET)
 350
 351 /**
 352   * @brief  Enable the DMA2D.
 353   * @param  __HANDLE__: DMA2D handle
 354   * @retval None.
 355   */
 356 #define __HAL_DMA2D_ENABLE(__HANDLE__)        ((__HANDLE__)->Instance->CR |= DMA2D_CR_START)
 357
 358
 359 /* Interrupt & Flag management */
 360 /**
 361   * @brief  Get the DMA2D pending flags.
 362   * @param  __HANDLE__: DMA2D handle
 363   * @param  __FLAG__: flag to check.
 364   *          This parameter can be any combination of the following values:
 365   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 366   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 367   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 368   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 369   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 370   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 371   * @retval The state of FLAG.
 372   */
 373 #define __HAL_DMA2D_GET_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ISR & (__FLAG__))
 374
 375 /**
 376   * @brief  Clear the DMA2D pending flags.
 377   * @param  __HANDLE__: DMA2D handle
 378   * @param  __FLAG__: specifies the flag to clear.
 379   *          This parameter can be any combination of the following values:
 380   *            @arg DMA2D_FLAG_CE:  Configuration error flag
 381   *            @arg DMA2D_FLAG_CTC: CLUT transfer complete flag
 382   *            @arg DMA2D_FLAG_CAE: CLUT access error flag
 383   *            @arg DMA2D_FLAG_TW:  Transfer Watermark flag
 384   *            @arg DMA2D_FLAG_TC:  Transfer complete flag
 385   *            @arg DMA2D_FLAG_TE:  Transfer error flag
 386   * @retval None
 387   */
 388 #define __HAL_DMA2D_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->IFCR = (__FLAG__))
 389
 390 /**
 391   * @brief  Enable the specified DMA2D interrupts.
 392   * @param  __HANDLE__: DMA2D handle
 393   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be enabled.
 394   *          This parameter can be any combination of the following values:
 395   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 396   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 397   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 398   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 399   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 400   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 401   * @retval None
 402   */
 403 #define __HAL_DMA2D_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR |= (__INTERRUPT__))
 404
 405 /**
 406   * @brief  Disable the specified DMA2D interrupts.
 407   * @param  __HANDLE__: DMA2D handle
 408   * @param __INTERRUPT__: specifies the DMA2D interrupt sources to be disabled.
 409   *          This parameter can be any combination of the following values:
 410   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 411   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 412   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 413   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 414   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 415   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 416   * @retval None
 417   */
 418 #define __HAL_DMA2D_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR &= ~(__INTERRUPT__))
 419
 420 /**
 421   * @brief  Check whether the specified DMA2D interrupt source is enabled or not.
 422   * @param  __HANDLE__: DMA2D handle
 423   * @param  __INTERRUPT__: specifies the DMA2D interrupt source to check.
 424   *          This parameter can be one of the following values:
 425   *            @arg DMA2D_IT_CE:  Configuration error interrupt mask
 426   *            @arg DMA2D_IT_CTC: CLUT transfer complete interrupt mask
 427   *            @arg DMA2D_IT_CAE: CLUT access error interrupt mask
 428   *            @arg DMA2D_IT_TW:  Transfer Watermark interrupt mask
 429   *            @arg DMA2D_IT_TC:  Transfer complete interrupt mask
 430   *            @arg DMA2D_IT_TE:  Transfer error interrupt mask
 431   * @retval The state of INTERRUPT source.
 432   */
 433 #define __HAL_DMA2D_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->CR & (__INTERRUPT__))
 434
 435 /**
 436   * @}
 437   */
 438
 439 /* Exported functions --------------------------------------------------------*/
 440 /** @addtogroup DMA2D_Exported_Functions DMA2D Exported Functions
 441   * @{
 442   */
 443
 444 /** @addtogroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
 445   * @{
 446   */
 447
 448 /* Initialization and de-initialization functions *******************************/
 449 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d);
 450 HAL_StatusTypeDef HAL_DMA2D_DeInit (DMA2D_HandleTypeDef *hdma2d);
 451 void              HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d);
 452 void              HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d);
 453
 454 /**
 455   * @}
 456   */
 457
 458
 459 /** @addtogroup DMA2D_Exported_Functions_Group2 IO operation functions
 460   * @{
 461   */
 462
 463 /* IO operation functions *******************************************************/
 464 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 465 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width,  uint32_t Height);
 466 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 467 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height);
 468 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d);
 469 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d);
 470 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d);
 471 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 472 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 473 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 474 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 475 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 476 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 477 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout);
 478 void              HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d);
 479 void              HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d);
 480 void              HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d);
 481
 482 /**
 483   * @}
 484   */
 485
 486 /** @addtogroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
 487   * @{
 488   */
 489
 490 /* Peripheral Control functions *************************************************/
 491 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx);
 492 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx);
 493 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line);
 494 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 495 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d);
 496 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime);
 497
 498 /**
 499   * @}
 500   */
 501
 502 /** @addtogroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
 503   * @{
 504   */
 505
 506 /* Peripheral State functions ***************************************************/
 507 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d);
 508 uint32_t               HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d);
 509
 510 /**
 511   * @}
 512   */
 513
 514 /**
 515   * @}
 516   */
 517
 518 /* Private constants ---------------------------------------------------------*/
 519
 520 /** @addtogroup DMA2D_Private_Constants DMA2D Private Constants
 521   * @{
 522   */
 523
 524 /** @defgroup DMA2D_Maximum_Line_WaterMark DMA2D Maximum Line Watermark
 525   * @{
 526   */
 527 #define DMA2D_LINE_WATERMARK_MAX            DMA2D_LWR_LW       /*!< DMA2D maximum line watermark */
 528 /**
 529   * @}
 530   */
 531
 532 /** @defgroup DMA2D_Color_Value DMA2D Color Value
 533   * @{
 534   */
 535 #define DMA2D_COLOR_VALUE                 ((uint32_t)0x000000FFU)  /*!< Color value mask */
 536 /**
 537   * @}
 538   */
 539
 540 /** @defgroup DMA2D_Max_Layer DMA2D Maximum Number of Layers
 541   * @{
 542   */
 543 #define DMA2D_MAX_LAYER         2         /*!< DMA2D maximum number of layers */
 544 /**
 545   * @}
 546   */
 547
 548 /** @defgroup DMA2D_Offset DMA2D Offset
 549   * @{
 550   */
 551 #define DMA2D_OFFSET                DMA2D_FGOR_LO            /*!< Line Offset */
 552 /**
 553   * @}
 554   */
 555
 556 /** @defgroup DMA2D_Size DMA2D Size
 557   * @{
 558   */
 559 #define DMA2D_PIXEL                 (DMA2D_NLR_PL >> 16U)    /*!< DMA2D number of pixels per line */
 560 #define DMA2D_LINE                  DMA2D_NLR_NL             /*!< DMA2D number of lines           */
 561 /**
 562   * @}
 563   */
 564
 565 /** @defgroup DMA2D_CLUT_Size DMA2D CLUT Size
 566   * @{
 567   */
 568 #define DMA2D_CLUT_SIZE             (DMA2D_FGPFCCR_CS >> 8)  /*!< DMA2D CLUT size */
 569 /**
 570   * @}
 571   */
 572
 573 /**
 574   * @}
 575   */
 576
 577
 578 /* Private macros ------------------------------------------------------------*/
 579 /** @defgroup DMA2D_Private_Macros DMA2D Private Macros
 580   * @{
 581   */
 582 #define IS_DMA2D_LAYER(LAYER)                 ((LAYER) <= DMA2D_MAX_LAYER)
 583 #define IS_DMA2D_MODE(MODE)                   (((MODE) == DMA2D_M2M)       || ((MODE) == DMA2D_M2M_PFC) || \
 584                                                ((MODE) == DMA2D_M2M_BLEND) || ((MODE) == DMA2D_R2M))
 585 #define IS_DMA2D_CMODE(MODE_ARGB)             (((MODE_ARGB) == DMA2D_OUTPUT_ARGB8888) || ((MODE_ARGB) == DMA2D_OUTPUT_RGB888)   || \
 586                                                ((MODE_ARGB) == DMA2D_OUTPUT_RGB565)   || ((MODE_ARGB) == DMA2D_OUTPUT_ARGB1555) || \
 587                                                ((MODE_ARGB) == DMA2D_OUTPUT_ARGB4444))
 588 #define IS_DMA2D_COLOR(COLOR)                 ((COLOR) <= DMA2D_COLOR_VALUE)
 589 #define IS_DMA2D_LINE(LINE)                   ((LINE) <= DMA2D_LINE)
 590 #define IS_DMA2D_PIXEL(PIXEL)                 ((PIXEL) <= DMA2D_PIXEL)
 591 #define IS_DMA2D_OFFSET(OOFFSET)              ((OOFFSET) <= DMA2D_OFFSET)
 592 #define IS_DMA2D_INPUT_COLOR_MODE(INPUT_CM)   (((INPUT_CM) == DMA2D_INPUT_ARGB8888) || ((INPUT_CM) == DMA2D_INPUT_RGB888)   || \
 593                                                ((INPUT_CM) == DMA2D_INPUT_RGB565)   || ((INPUT_CM) == DMA2D_INPUT_ARGB1555) || \
 594                                                ((INPUT_CM) == DMA2D_INPUT_ARGB4444) || ((INPUT_CM) == DMA2D_INPUT_L8)       || \
 595                                                ((INPUT_CM) == DMA2D_INPUT_AL44)     || ((INPUT_CM) == DMA2D_INPUT_AL88)     || \
 596                                                ((INPUT_CM) == DMA2D_INPUT_L4)       || ((INPUT_CM) == DMA2D_INPUT_A8)       || \
 597                                                ((INPUT_CM) == DMA2D_INPUT_A4))
 598 #define IS_DMA2D_ALPHA_MODE(AlphaMode)        (((AlphaMode) == DMA2D_NO_MODIF_ALPHA) || \
 599                                                ((AlphaMode) == DMA2D_REPLACE_ALPHA)  || \
 600                                                ((AlphaMode) == DMA2D_COMBINE_ALPHA))
 601
 602 #define IS_DMA2D_ALPHA_INVERTED(Alpha_Inverted) (((Alpha_Inverted) == DMA2D_REGULAR_ALPHA) || \
 603                                                  ((Alpha_Inverted) == DMA2D_INVERTED_ALPHA))
 604
 605 #define IS_DMA2D_RB_SWAP(RB_Swap) (((RB_Swap) == DMA2D_RB_REGULAR) || \
 606                                    ((RB_Swap) == DMA2D_RB_SWAP))
 607
 608 #define IS_DMA2D_CLUT_CM(CLUT_CM)             (((CLUT_CM) == DMA2D_CCM_ARGB8888) || ((CLUT_CM) == DMA2D_CCM_RGB888))
 609 #define IS_DMA2D_CLUT_SIZE(CLUT_SIZE)         ((CLUT_SIZE) <= DMA2D_CLUT_SIZE)
 610 #define IS_DMA2D_LINEWATERMARK(LineWatermark) ((LineWatermark) <= DMA2D_LINE_WATERMARK_MAX)
 611 #define IS_DMA2D_IT(IT)                       (((IT) == DMA2D_IT_CTC) || ((IT) == DMA2D_IT_CAE) || \
 612                                                ((IT) == DMA2D_IT_TW) || ((IT) == DMA2D_IT_TC) || \
 613                                                ((IT) == DMA2D_IT_TE) || ((IT) == DMA2D_IT_CE))
 614 #define IS_DMA2D_GET_FLAG(FLAG)               (((FLAG) == DMA2D_FLAG_CTC) || ((FLAG) == DMA2D_FLAG_CAE) || \
 615                                                ((FLAG) == DMA2D_FLAG_TW)   || ((FLAG) == DMA2D_FLAG_TC)  || \
 616                                                ((FLAG) == DMA2D_FLAG_TE)   || ((FLAG) == DMA2D_FLAG_CE))
 617 /**
 618   * @}
 619   */
 620
 621 /**
 622   * @}
 623   */
 624
 625 /**
 626   * @}
 627   */
 628
 629 #endif /* DMA2D */
 630
 631 #ifdef __cplusplus
 632 }
 633 #endif
 634
 635 #endif /* __STM32F7xx_HAL_DMA2D_H */
 636
 637
 638 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/