lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_nand.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_nand.h
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   Header file of NAND HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_NAND_H
  40 #define __STM32F7xx_HAL_NAND_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_ll_fmc.h"
  48
  49 /** @addtogroup STM32F7xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup NAND
  54   * @{
  55   */
  56
  57 /* Exported typedef ----------------------------------------------------------*/
  58 /* Exported types ------------------------------------------------------------*/
  59 /** @defgroup NAND_Exported_Types NAND Exported Types
  60   * @{
  61   */
  62
  63 /**
  64   * @brief  HAL NAND State structures definition
  65   */
  66 typedef enum
  67 {
  68   HAL_NAND_STATE_RESET     = 0x00U,  /*!< NAND not yet initialized or disabled */
  69   HAL_NAND_STATE_READY     = 0x01U,  /*!< NAND initialized and ready for use   */
  70   HAL_NAND_STATE_BUSY      = 0x02U,  /*!< NAND internal process is ongoing     */
  71   HAL_NAND_STATE_ERROR     = 0x03U   /*!< NAND error state                     */
  72 }HAL_NAND_StateTypeDef;
  73
  74 /**
  75   * @brief  NAND Memory electronic signature Structure definition
  76   */
  77 typedef struct
  78 {
  79   /*<! NAND memory electronic signature maker and device IDs */
  80
  81   uint8_t Maker_Id;
  82
  83   uint8_t Device_Id;
  84
  85   uint8_t Third_Id;
  86
  87   uint8_t Fourth_Id;
  88 }NAND_IDTypeDef;
  89
  90 /**
  91   * @brief  NAND Memory address Structure definition
  92   */
  93 typedef struct
  94 {
  95   uint16_t Page;   /*!< NAND memory Page address  */
  96
  97   uint16_t Plane;   /*!< NAND memory Zone address  */
  98
  99   uint16_t Block;  /*!< NAND memory Block address */
 100
 101 }NAND_AddressTypeDef;
 102
 103 /**
 104   * @brief  NAND Memory info Structure definition
 105   */
 106 typedef struct
 107 {
 108   uint32_t        PageSize;              /*!< NAND memory page (without spare area) size measured in bytes
 109                                               for 8 bits adressing or words for 16 bits addressing             */
 110
 111   uint32_t        SpareAreaSize;         /*!< NAND memory spare area size measured in bytes
 112                                               for 8 bits adressing or words for 16 bits addressing             */
 113
 114   uint32_t        BlockSize;             /*!< NAND memory block size measured in number of pages               */
 115
 116   uint32_t        BlockNbr;              /*!< NAND memory number of total blocks                               */
 117
 118   uint32_t        PlaneNbr;              /*!< NAND memory number of planes                                     */
 119
 120   uint32_t        PlaneSize;             /*!< NAND memory zone size measured in number of blocks               */
 121
 122   FunctionalState ExtraCommandEnable;    /*!< NAND extra command needed for Page reading mode. This
 123                                               parameter is mandatory for some NAND parts after the read
 124                                               command (NAND_CMD_AREA_TRUE1) and before DATA reading sequence.
 125                                               Example: Toshiba THTH58BYG3S0HBAI6.
 126                                               This parameter could be ENABLE or DISABLE
 127                                               Please check the Read Mode sequnece in the NAND device datasheet */
 128 }NAND_DeviceConfigTypeDef;
 129
 130 /**
 131   * @brief  NAND handle Structure definition
 132   */
 133 typedef struct
 134 {
 135   FMC_NAND_TypeDef               *Instance;  /*!< Register base address                                 */
 136
 137   FMC_NAND_InitTypeDef           Init;       /*!< NAND device control configuration parameters          */
 138
 139   HAL_LockTypeDef                Lock;       /*!< NAND locking object                                   */
 140
 141   __IO HAL_NAND_StateTypeDef     State;      /*!< NAND device access state                              */
 142
 143   NAND_DeviceConfigTypeDef       Config;     /*!< NAND phusical characteristic information structure    */
 144
 145 }NAND_HandleTypeDef;
 146 /**
 147   * @}
 148   */
 149
 150 /* Exported constants --------------------------------------------------------*/
 151 /* Exported macro ------------------------------------------------------------*/
 152 /** @defgroup NAND_Exported_Macros NAND Exported Macros
 153  * @{
 154  */
 155
 156 /** @brief Reset NAND handle state
 157   * @param  __HANDLE__: specifies the NAND handle.
 158   * @retval None
 159   */
 160 #define __HAL_NAND_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_NAND_STATE_RESET)
 161
 162 /**
 163   * @}
 164   */
 165
 166 /* Exported functions --------------------------------------------------------*/
 167 /** @addtogroup NAND_Exported_Functions NAND Exported Functions
 168   * @{
 169   */
 170
 171 /** @addtogroup NAND_Exported_Functions_Group1 Initialization and de-initialization functions
 172   * @{
 173   */
 174
 175 /* Initialization/de-initialization functions  ********************************/
 176 HAL_StatusTypeDef  HAL_NAND_Init(NAND_HandleTypeDef *hnand, FMC_NAND_PCC_TimingTypeDef *ComSpace_Timing, FMC_NAND_PCC_TimingTypeDef *AttSpace_Timing);
 177 HAL_StatusTypeDef  HAL_NAND_DeInit(NAND_HandleTypeDef *hnand);
 178
 179 HAL_StatusTypeDef  HAL_NAND_ConfigDevice(NAND_HandleTypeDef *hnand, NAND_DeviceConfigTypeDef *pDeviceConfig);
 180
 181 HAL_StatusTypeDef  HAL_NAND_Read_ID(NAND_HandleTypeDef *hnand, NAND_IDTypeDef *pNAND_ID);
 182
 183 void               HAL_NAND_MspInit(NAND_HandleTypeDef *hnand);
 184 void               HAL_NAND_MspDeInit(NAND_HandleTypeDef *hnand);
 185 void               HAL_NAND_IRQHandler(NAND_HandleTypeDef *hnand);
 186 void               HAL_NAND_ITCallback(NAND_HandleTypeDef *hnand);
 187
 188 /**
 189   * @}
 190   */
 191
 192 /** @addtogroup NAND_Exported_Functions_Group2 Input and Output functions
 193   * @{
 194   */
 195
 196 /* IO operation functions  ****************************************************/
 197
 198 HAL_StatusTypeDef  HAL_NAND_Reset(NAND_HandleTypeDef *hnand);
 199
 200 HAL_StatusTypeDef  HAL_NAND_Read_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToRead);
 201 HAL_StatusTypeDef  HAL_NAND_Write_Page_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumPageToWrite);
 202 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaToRead);
 203 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_8b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint8_t *pBuffer, uint32_t NumSpareAreaTowrite);
 204
 205 HAL_StatusTypeDef  HAL_NAND_Read_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToRead);
 206 HAL_StatusTypeDef  HAL_NAND_Write_Page_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumPageToWrite);
 207 HAL_StatusTypeDef  HAL_NAND_Read_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaToRead);
 208 HAL_StatusTypeDef  HAL_NAND_Write_SpareArea_16b(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress, uint16_t *pBuffer, uint32_t NumSpareAreaTowrite);
 209
 210 HAL_StatusTypeDef  HAL_NAND_Erase_Block(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 211
 212 uint32_t           HAL_NAND_Address_Inc(NAND_HandleTypeDef *hnand, NAND_AddressTypeDef *pAddress);
 213
 214 /**
 215   * @}
 216   */
 217
 218 /** @addtogroup NAND_Exported_Functions_Group3 Peripheral Control functions
 219   * @{
 220   */
 221
 222 /* NAND Control functions  ****************************************************/
 223 HAL_StatusTypeDef  HAL_NAND_ECC_Enable(NAND_HandleTypeDef *hnand);
 224 HAL_StatusTypeDef  HAL_NAND_ECC_Disable(NAND_HandleTypeDef *hnand);
 225 HAL_StatusTypeDef  HAL_NAND_GetECC(NAND_HandleTypeDef *hnand, uint32_t *ECCval, uint32_t Timeout);
 226
 227 /**
 228   * @}
 229   */
 230
 231 /** @addtogroup NAND_Exported_Functions_Group4 Peripheral State functions
 232   * @{
 233   */
 234 /* NAND State functions *******************************************************/
 235 HAL_NAND_StateTypeDef HAL_NAND_GetState(NAND_HandleTypeDef *hnand);
 236 uint32_t              HAL_NAND_Read_Status(NAND_HandleTypeDef *hnand);
 237 /**
 238   * @}
 239   */
 240
 241 /**
 242   * @}
 243   */
 244 /* Private types -------------------------------------------------------------*/
 245 /* Private variables ---------------------------------------------------------*/
 246 /* Private constants ---------------------------------------------------------*/
 247 /** @defgroup NAND_Private_Constants NAND Private Constants
 248   * @{
 249   */
 250 #define NAND_DEVICE                ((uint32_t)0x80000000U)
 251 #define NAND_WRITE_TIMEOUT         ((uint32_t)0x01000000U)
 252
 253 #define CMD_AREA                   ((uint32_t)(1<<16))  /* A16 = CLE high */
 254 #define ADDR_AREA                  ((uint32_t)(1<<17))  /* A17 = ALE high */
 255
 256 #define NAND_CMD_AREA_A            ((uint8_t)0x00U)
 257 #define NAND_CMD_AREA_B            ((uint8_t)0x01U)
 258 #define NAND_CMD_AREA_C            ((uint8_t)0x50U)
 259 #define NAND_CMD_AREA_TRUE1        ((uint8_t)0x30U)
 260
 261 #define NAND_CMD_WRITE0            ((uint8_t)0x80U)
 262 #define NAND_CMD_WRITE_TRUE1       ((uint8_t)0x10U)
 263 #define NAND_CMD_ERASE0            ((uint8_t)0x60U)
 264 #define NAND_CMD_ERASE1            ((uint8_t)0xD0U)
 265 #define NAND_CMD_READID            ((uint8_t)0x90U)
 266 #define NAND_CMD_STATUS            ((uint8_t)0x70U)
 267 #define NAND_CMD_LOCK_STATUS       ((uint8_t)0x7AU)
 268 #define NAND_CMD_RESET             ((uint8_t)0xFFU)
 269
 270 /* NAND memory status */
 271 #define NAND_VALID_ADDRESS         ((uint32_t)0x00000100U)
 272 #define NAND_INVALID_ADDRESS       ((uint32_t)0x00000200U)
 273 #define NAND_TIMEOUT_ERROR         ((uint32_t)0x00000400U)
 274 #define NAND_BUSY                  ((uint32_t)0x00000000U)
 275 #define NAND_ERROR                 ((uint32_t)0x00000001U)
 276 #define NAND_READY                 ((uint32_t)0x00000040U)
 277 /**
 278   * @}
 279   */
 280
 281 /* Private macros ------------------------------------------------------------*/
 282 /** @defgroup NAND_Private_Macros NAND Private Macros
 283   * @{
 284   */
 285
 286 /**
 287   * @brief  NAND memory address computation.
 288   * @param  __ADDRESS__: NAND memory address.
 289   * @param  __HANDLE__ : NAND handle.
 290   * @retval NAND Raw address value
 291   */
 292 #define ARRAY_ADDRESS(__ADDRESS__ , __HANDLE__) ((__ADDRESS__)->Page + \
 293                          (((__ADDRESS__)->Block + (((__ADDRESS__)->Plane) * ((__HANDLE__)->Config.PlaneSize)))* ((__HANDLE__)->Config.BlockSize)))
 294
 295 #define COLUMN_ADDRESS( __HANDLE__) ((__HANDLE__)->Config.PageSize)
 296
 297 /**
 298   * @brief  NAND memory address cycling.
 299   * @param  __ADDRESS__: NAND memory address.
 300   * @retval NAND address cycling value.
 301   */
 302 #define ADDR_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st addressing cycle */
 303 #define ADDR_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd addressing cycle */
 304 #define ADDR_3RD_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 16)      /* 3rd addressing cycle */
 305 #define ADDR_4TH_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 24)      /* 4th addressing cycle */
 306
 307 /**
 308   * @brief  NAND memory Columns cycling.
 309   * @param  __ADDRESS__: NAND memory address.
 310   * @retval NAND Column address cycling value.
 311   */
 312 #define COLUMN_1ST_CYCLE(__ADDRESS__)       (uint8_t)(__ADDRESS__)              /* 1st Column addressing cycle */
 313 #define COLUMN_2ND_CYCLE(__ADDRESS__)       (uint8_t)((__ADDRESS__) >> 8)       /* 2nd Column addressing cycle */
 314
 315 /**
 316   * @}
 317   */
 318
 319 /**
 320   * @}
 321   */
 322 /**
 323   * @}
 324   */
 325
 326 /**
 327   * @}
 328   */
 329
 330 #ifdef __cplusplus
 331 }
 332 #endif
 333
 334 #endif /* __STM32F7xx_HAL_NAND_H */
 335
 336 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/