lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_smbus.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_smbus.h
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   Header file of SMBUS HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_SMBUS_H
  40 #define __STM32F7xx_HAL_SMBUS_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_hal_def.h"
  48
  49 /** @addtogroup STM32F7xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SMBUS
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup SMBUS_Exported_Types SMBUS Exported Types
  59   * @{
  60   */
  61
  62 /** @defgroup SMBUS_Configuration_Structure_definition SMBUS Configuration Structure definition
  63   * @brief  SMBUS Configuration Structure definition
  64   * @{
  65   */
  66 typedef struct
  67 {
  68   uint32_t Timing;                 /*!< Specifies the SMBUS_TIMINGR_register value.
  69                                      This parameter calculated by referring to SMBUS initialization
  70                                             section in Reference manual */
  71   uint32_t AnalogFilter;           /*!< Specifies if Analog Filter is enable or not.
  72                                      This parameter can be a value of @ref SMBUS_Analog_Filter */
  73
  74   uint32_t OwnAddress1;            /*!< Specifies the first device own address.
  75                                      This parameter can be a 7-bit or 10-bit address. */
  76
  77   uint32_t AddressingMode;         /*!< Specifies if 7-bit or 10-bit addressing mode for master is selected.
  78                                      This parameter can be a value of @ref SMBUS_addressing_mode */
  79
  80   uint32_t DualAddressMode;        /*!< Specifies if dual addressing mode is selected.
  81                                      This parameter can be a value of @ref SMBUS_dual_addressing_mode */
  82
  83   uint32_t OwnAddress2;            /*!< Specifies the second device own address if dual addressing mode is selected
  84                                      This parameter can be a 7-bit address. */
  85
  86   uint32_t OwnAddress2Masks;       /*!< Specifies the acknoledge mask address second device own address if dual addressing mode is selected
  87                                      This parameter can be a value of @ref SMBUS_own_address2_masks. */
  88
  89   uint32_t GeneralCallMode;        /*!< Specifies if general call mode is selected.
  90                                      This parameter can be a value of @ref SMBUS_general_call_addressing_mode. */
  91
  92   uint32_t NoStretchMode;          /*!< Specifies if nostretch mode is selected.
  93                                      This parameter can be a value of @ref SMBUS_nostretch_mode */
  94
  95   uint32_t PacketErrorCheckMode;   /*!< Specifies if Packet Error Check mode is selected.
  96                                      This parameter can be a value of @ref SMBUS_packet_error_check_mode */
  97
  98   uint32_t PeripheralMode;         /*!< Specifies which mode of Periphal is selected.
  99                                      This parameter can be a value of @ref SMBUS_peripheral_mode */
 100
 101   uint32_t SMBusTimeout;           /*!< Specifies the content of the 32 Bits SMBUS_TIMEOUT_register value.
 102                                                                                                                                                 (Enable bits and different timeout values)
 103                                      This parameter calculated by referring to SMBUS initialization
 104                                          section in Reference manual */
 105 } SMBUS_InitTypeDef;
 106 /**
 107   * @}
 108   */
 109
 110 /** @defgroup HAL_state_definition HAL state definition
 111   * @brief  HAL State definition
 112   * @{
 113   */
 114 #define HAL_SMBUS_STATE_RESET           (0x00000000U)  /*!< SMBUS not yet initialized or disabled         */
 115 #define HAL_SMBUS_STATE_READY           (0x00000001U)  /*!< SMBUS initialized and ready for use           */
 116 #define HAL_SMBUS_STATE_BUSY            (0x00000002U)  /*!< SMBUS internal process is ongoing             */
 117 #define HAL_SMBUS_STATE_MASTER_BUSY_TX  (0x00000012U)  /*!< Master Data Transmission process is ongoing   */
 118 #define HAL_SMBUS_STATE_MASTER_BUSY_RX  (0x00000022U)  /*!< Master Data Reception process is ongoing      */
 119 #define HAL_SMBUS_STATE_SLAVE_BUSY_TX   (0x00000032U)  /*!< Slave Data Transmission process is ongoing    */
 120 #define HAL_SMBUS_STATE_SLAVE_BUSY_RX   (0x00000042U)  /*!< Slave Data Reception process is ongoing       */
 121 #define HAL_SMBUS_STATE_TIMEOUT         (0x00000003U)  /*!< Timeout state                                 */
 122 #define HAL_SMBUS_STATE_ERROR           (0x00000004U)  /*!< Reception process is ongoing                  */
 123 #define HAL_SMBUS_STATE_LISTEN          (0x00000008U)   /*!< Address Listen Mode is ongoing                */
 124 /**
 125   * @}
 126   */
 127
 128 /** @defgroup SMBUS_Error_Code_definition SMBUS Error Code definition
 129   * @brief  SMBUS Error Code definition
 130   * @{
 131   */
 132 #define HAL_SMBUS_ERROR_NONE            (0x00000000U)    /*!< No error             */
 133 #define HAL_SMBUS_ERROR_BERR            (0x00000001U)    /*!< BERR error           */
 134 #define HAL_SMBUS_ERROR_ARLO            (0x00000002U)    /*!< ARLO error           */
 135 #define HAL_SMBUS_ERROR_ACKF            (0x00000004U)    /*!< ACKF error           */
 136 #define HAL_SMBUS_ERROR_OVR             (0x00000008U)    /*!< OVR error            */
 137 #define HAL_SMBUS_ERROR_HALTIMEOUT      (0x00000010U)    /*!< Timeout error        */
 138 #define HAL_SMBUS_ERROR_BUSTIMEOUT      (0x00000020U)    /*!< Bus Timeout error    */
 139 #define HAL_SMBUS_ERROR_ALERT           (0x00000040U)    /*!< Alert error          */
 140 #define HAL_SMBUS_ERROR_PECERR          (0x00000080U)    /*!< PEC error            */
 141 /**
 142   * @}
 143   */
 144
 145 /** @defgroup SMBUS_handle_Structure_definition SMBUS handle Structure definition
 146   * @brief  SMBUS handle Structure definition
 147   * @{
 148   */
 149 typedef struct
 150 {
 151   I2C_TypeDef                  *Instance;       /*!< SMBUS registers base address       */
 152
 153   SMBUS_InitTypeDef            Init;            /*!< SMBUS communication parameters     */
 154
 155   uint8_t                      *pBuffPtr;       /*!< Pointer to SMBUS transfer buffer   */
 156
 157   uint16_t                     XferSize;        /*!< SMBUS transfer size                */
 158
 159   __IO uint16_t                XferCount;       /*!< SMBUS transfer counter             */
 160
 161   __IO uint32_t                XferOptions;     /*!< SMBUS transfer options             */
 162
 163   __IO uint32_t                PreviousState;   /*!< SMBUS communication Previous state */
 164
 165   HAL_LockTypeDef              Lock;            /*!< SMBUS locking object               */
 166
 167   __IO uint32_t                State;           /*!< SMBUS communication state          */
 168
 169   __IO uint32_t                ErrorCode;       /*!< SMBUS Error code                   */
 170
 171 }SMBUS_HandleTypeDef;
 172 /**
 173   * @}
 174   */
 175
 176 /**
 177   * @}
 178   */
 179 /* Exported constants --------------------------------------------------------*/
 180
 181 /** @defgroup SMBUS_Exported_Constants SMBUS Exported Constants
 182   * @{
 183   */
 184
 185 /** @defgroup SMBUS_Analog_Filter SMBUS Analog Filter
 186   * @{
 187   */
 188 #define SMBUS_ANALOGFILTER_ENABLE               (0x00000000U)
 189 #define SMBUS_ANALOGFILTER_DISABLE              I2C_CR1_ANFOFF
 190 /**
 191   * @}
 192   */
 193
 194 /** @defgroup SMBUS_addressing_mode SMBUS addressing mode
 195   * @{
 196   */
 197 #define SMBUS_ADDRESSINGMODE_7BIT               (0x00000001U)
 198 #define SMBUS_ADDRESSINGMODE_10BIT              (0x00000002U)
 199 /**
 200   * @}
 201   */
 202
 203 /** @defgroup SMBUS_dual_addressing_mode SMBUS dual addressing mode
 204   * @{
 205   */
 206
 207 #define SMBUS_DUALADDRESS_DISABLE               (0x00000000U)
 208 #define SMBUS_DUALADDRESS_ENABLE                I2C_OAR2_OA2EN
 209 /**
 210   * @}
 211   */
 212
 213 /** @defgroup SMBUS_own_address2_masks SMBUS ownaddress2 masks
 214   * @{
 215   */
 216
 217 #define SMBUS_OA2_NOMASK                        ((uint8_t)0x00U)
 218 #define SMBUS_OA2_MASK01                        ((uint8_t)0x01U)
 219 #define SMBUS_OA2_MASK02                        ((uint8_t)0x02U)
 220 #define SMBUS_OA2_MASK03                        ((uint8_t)0x03U)
 221 #define SMBUS_OA2_MASK04                        ((uint8_t)0x04U)
 222 #define SMBUS_OA2_MASK05                        ((uint8_t)0x05U)
 223 #define SMBUS_OA2_MASK06                        ((uint8_t)0x06U)
 224 #define SMBUS_OA2_MASK07                        ((uint8_t)0x07U)
 225 /**
 226   * @}
 227   */
 228
 229
 230 /** @defgroup SMBUS_general_call_addressing_mode SMBUS general call addressing mode
 231   * @{
 232   */
 233 #define SMBUS_GENERALCALL_DISABLE               (0x00000000U)
 234 #define SMBUS_GENERALCALL_ENABLE                I2C_CR1_GCEN
 235 /**
 236   * @}
 237   */
 238
 239 /** @defgroup SMBUS_nostretch_mode  SMBUS nostretch mode
 240   * @{
 241   */
 242 #define SMBUS_NOSTRETCH_DISABLE                 (0x00000000U)
 243 #define SMBUS_NOSTRETCH_ENABLE                  I2C_CR1_NOSTRETCH
 244 /**
 245   * @}
 246   */
 247
 248 /** @defgroup SMBUS_packet_error_check_mode SMBUS packet error check mode
 249   * @{
 250   */
 251 #define SMBUS_PEC_DISABLE                       (0x00000000U)
 252 #define SMBUS_PEC_ENABLE                        I2C_CR1_PECEN
 253 /**
 254   * @}
 255   */
 256
 257 /** @defgroup SMBUS_peripheral_mode SMBUS peripheral mode
 258   * @{
 259   */
 260 #define SMBUS_PERIPHERAL_MODE_SMBUS_HOST        I2C_CR1_SMBHEN
 261 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE       (0x00000000U)
 262 #define SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP   I2C_CR1_SMBDEN
 263 /**
 264   * @}
 265   */
 266
 267 /** @defgroup SMBUS_ReloadEndMode_definition SMBUS ReloadEndMode definition
 268   * @{
 269   */
 270
 271 #define  SMBUS_SOFTEND_MODE                     (0x00000000U)
 272 #define  SMBUS_RELOAD_MODE                      I2C_CR2_RELOAD
 273 #define  SMBUS_AUTOEND_MODE                     I2C_CR2_AUTOEND
 274 #define  SMBUS_SENDPEC_MODE                     I2C_CR2_PECBYTE
 275 /**
 276   * @}
 277   */
 278
 279 /** @defgroup SMBUS_StartStopMode_definition SMBUS StartStopMode definition
 280   * @{
 281   */
 282
 283 #define  SMBUS_NO_STARTSTOP                     (0x00000000U)
 284 #define  SMBUS_GENERATE_STOP                    I2C_CR2_STOP
 285 #define  SMBUS_GENERATE_START_READ              (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN)
 286 #define  SMBUS_GENERATE_START_WRITE             I2C_CR2_START
 287 /**
 288   * @}
 289   */
 290
 291 /** @defgroup SMBUS_XferOptions_definition SMBUS XferOptions definition
 292   * @{
 293   */
 294
 295 /* List of XferOptions in usage of :
 296  * 1- Restart condition when direction change
 297  * 2- No Restart condition in other use cases
 298  */
 299 #define  SMBUS_FIRST_FRAME                      SMBUS_SOFTEND_MODE
 300 #define  SMBUS_NEXT_FRAME                       ((uint32_t)(SMBUS_RELOAD_MODE | SMBUS_SOFTEND_MODE))
 301 #define  SMBUS_FIRST_AND_LAST_FRAME_NO_PEC      SMBUS_AUTOEND_MODE
 302 #define  SMBUS_LAST_FRAME_NO_PEC                SMBUS_AUTOEND_MODE
 303 #define  SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC    ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 304 #define  SMBUS_LAST_FRAME_WITH_PEC              ((uint32_t)(SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))
 305
 306 /* List of XferOptions in usage of :
 307  * 1- Restart condition in all use cases (direction change or not)
 308  */
 309 #define  SMBUS_OTHER_FRAME_NO_PEC               (0x000000AAU)
 310 #define  SMBUS_OTHER_FRAME_WITH_PEC             (0x0000AA00U)
 311 #define  SMBUS_OTHER_AND_LAST_FRAME_NO_PEC      (0x00AA0000U)
 312 #define  SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC    (0xAA000000U)
 313 /**
 314   * @}
 315   */
 316
 317 /** @defgroup SMBUS_Interrupt_configuration_definition SMBUS Interrupt configuration definition
 318   * @brief SMBUS Interrupt definition
 319   *        Elements values convention: 0xXXXXXXXX
 320   *           - XXXXXXXX  : Interrupt control mask
 321   * @{
 322   */
 323 #define SMBUS_IT_ERRI                           I2C_CR1_ERRIE
 324 #define SMBUS_IT_TCI                            I2C_CR1_TCIE
 325 #define SMBUS_IT_STOPI                          I2C_CR1_STOPIE
 326 #define SMBUS_IT_NACKI                          I2C_CR1_NACKIE
 327 #define SMBUS_IT_ADDRI                          I2C_CR1_ADDRIE
 328 #define SMBUS_IT_RXI                            I2C_CR1_RXIE
 329 #define SMBUS_IT_TXI                            I2C_CR1_TXIE
 330 #define SMBUS_IT_TX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_STOPI | SMBUS_IT_NACKI | SMBUS_IT_TXI)
 331 #define SMBUS_IT_RX                             (SMBUS_IT_ERRI | SMBUS_IT_TCI | SMBUS_IT_NACKI | SMBUS_IT_RXI)
 332 #define SMBUS_IT_ALERT                          (SMBUS_IT_ERRI)
 333 #define SMBUS_IT_ADDR                           (SMBUS_IT_ADDRI | SMBUS_IT_STOPI | SMBUS_IT_NACKI)
 334 /**
 335   * @}
 336   */
 337
 338 /** @defgroup SMBUS_Flag_definition SMBUS Flag definition
 339   * @brief Flag definition
 340   *        Elements values convention: 0xXXXXYYYY
 341   *           - XXXXXXXX  : Flag mask
 342   * @{
 343   */
 344
 345 #define  SMBUS_FLAG_TXE                         I2C_ISR_TXE
 346 #define  SMBUS_FLAG_TXIS                        I2C_ISR_TXIS
 347 #define  SMBUS_FLAG_RXNE                        I2C_ISR_RXNE
 348 #define  SMBUS_FLAG_ADDR                        I2C_ISR_ADDR
 349 #define  SMBUS_FLAG_AF                          I2C_ISR_NACKF
 350 #define  SMBUS_FLAG_STOPF                       I2C_ISR_STOPF
 351 #define  SMBUS_FLAG_TC                          I2C_ISR_TC
 352 #define  SMBUS_FLAG_TCR                         I2C_ISR_TCR
 353 #define  SMBUS_FLAG_BERR                        I2C_ISR_BERR
 354 #define  SMBUS_FLAG_ARLO                        I2C_ISR_ARLO
 355 #define  SMBUS_FLAG_OVR                         I2C_ISR_OVR
 356 #define  SMBUS_FLAG_PECERR                      I2C_ISR_PECERR
 357 #define  SMBUS_FLAG_TIMEOUT                     I2C_ISR_TIMEOUT
 358 #define  SMBUS_FLAG_ALERT                       I2C_ISR_ALERT
 359 #define  SMBUS_FLAG_BUSY                        I2C_ISR_BUSY
 360 #define  SMBUS_FLAG_DIR                         I2C_ISR_DIR
 361 /**
 362   * @}
 363   */
 364
 365 /**
 366   * @}
 367   */
 368
 369 /* Exported macros ------------------------------------------------------------*/
 370 /** @defgroup SMBUS_Exported_Macros SMBUS Exported Macros
 371   * @{
 372   */
 373
 374 /** @brief  Reset SMBUS handle state.
 375   * @param  __HANDLE__ specifies the SMBUS Handle.
 376   * @retval None
 377   */
 378 #define __HAL_SMBUS_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SMBUS_STATE_RESET)
 379
 380 /** @brief  Enable the specified SMBUS interrupts.
 381   * @param  __HANDLE__ specifies the SMBUS Handle.
 382   * @param  __INTERRUPT__ specifies the interrupt source to enable.
 383   *        This parameter can be one of the following values:
 384   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
 385   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
 386   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
 387   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
 388   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
 389   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
 390   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
 391   *
 392   * @retval None
 393   */
 394 #define __HAL_SMBUS_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR1 |= (__INTERRUPT__))
 395
 396 /** @brief  Disable the specified SMBUS interrupts.
 397   * @param  __HANDLE__ specifies the SMBUS Handle.
 398   * @param  __INTERRUPT__ specifies the interrupt source to disable.
 399   *        This parameter can be one of the following values:
 400   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
 401   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
 402   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
 403   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
 404   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
 405   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
 406   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
 407   *
 408   * @retval None
 409   */
 410 #define __HAL_SMBUS_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR1 &= (~(__INTERRUPT__)))
 411
 412 /** @brief  Check whether the specified SMBUS interrupt source is enabled or not.
 413   * @param  __HANDLE__ specifies the SMBUS Handle.
 414   * @param  __INTERRUPT__ specifies the SMBUS interrupt source to check.
 415   *          This parameter can be one of the following values:
 416   *            @arg @ref SMBUS_IT_ERRI  Errors interrupt enable
 417   *            @arg @ref SMBUS_IT_TCI   Transfer complete interrupt enable
 418   *            @arg @ref SMBUS_IT_STOPI STOP detection interrupt enable
 419   *            @arg @ref SMBUS_IT_NACKI NACK received interrupt enable
 420   *            @arg @ref SMBUS_IT_ADDRI Address match interrupt enable
 421   *            @arg @ref SMBUS_IT_RXI   RX interrupt enable
 422   *            @arg @ref SMBUS_IT_TXI   TX interrupt enable
 423   *
 424   * @retval The new state of __IT__ (TRUE or FALSE).
 425   */
 426 #define __HAL_SMBUS_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR1 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 427
 428 /** @brief  Check whether the specified SMBUS flag is set or not.
 429   * @param  __HANDLE__ specifies the SMBUS Handle.
 430   * @param  __FLAG__ specifies the flag to check.
 431   *        This parameter can be one of the following values:
 432   *            @arg @ref SMBUS_FLAG_TXE     Transmit data register empty
 433   *            @arg @ref SMBUS_FLAG_TXIS    Transmit interrupt status
 434   *            @arg @ref SMBUS_FLAG_RXNE    Receive data register not empty
 435   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
 436   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
 437   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
 438   *            @arg @ref SMBUS_FLAG_TC      Transfer complete (master mode)
 439   *            @arg @ref SMBUS_FLAG_TCR     Transfer complete reload
 440   *            @arg @ref SMBUS_FLAG_BERR    Bus error
 441   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
 442   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
 443   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
 444   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
 445   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
 446   *            @arg @ref SMBUS_FLAG_BUSY    Bus busy
 447   *            @arg @ref SMBUS_FLAG_DIR     Transfer direction (slave mode)
 448   *
 449   * @retval The new state of __FLAG__ (TRUE or FALSE).
 450   */
 451 #define SMBUS_FLAG_MASK  (0x0001FFFFU)
 452 #define __HAL_SMBUS_GET_FLAG(__HANDLE__, __FLAG__) (((((__HANDLE__)->Instance->ISR) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
 453
 454 /** @brief  Clear the SMBUS pending flags which are cleared by writing 1 in a specific bit.
 455   * @param  __HANDLE__ specifies the SMBUS Handle.
 456   * @param  __FLAG__ specifies the flag to clear.
 457   *          This parameter can be any combination of the following values:
 458   *            @arg @ref SMBUS_FLAG_ADDR    Address matched (slave mode)
 459   *            @arg @ref SMBUS_FLAG_AF      NACK received flag
 460   *            @arg @ref SMBUS_FLAG_STOPF   STOP detection flag
 461   *            @arg @ref SMBUS_FLAG_BERR    Bus error
 462   *            @arg @ref SMBUS_FLAG_ARLO    Arbitration lost
 463   *            @arg @ref SMBUS_FLAG_OVR     Overrun/Underrun
 464   *            @arg @ref SMBUS_FLAG_PECERR  PEC error in reception
 465   *            @arg @ref SMBUS_FLAG_TIMEOUT Timeout or Tlow detection flag
 466   *            @arg @ref SMBUS_FLAG_ALERT   SMBus alert
 467   *
 468   * @retval None
 469   */
 470 #define __HAL_SMBUS_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->ICR = (__FLAG__))
 471
 472 /** @brief  Enable the specified SMBUS peripheral.
 473   * @param  __HANDLE__ specifies the SMBUS Handle.
 474   * @retval None
 475   */
 476 #define __HAL_SMBUS_ENABLE(__HANDLE__)                  (SET_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 477
 478 /** @brief  Disable the specified SMBUS peripheral.
 479   * @param  __HANDLE__ specifies the SMBUS Handle.
 480   * @retval None
 481   */
 482 #define __HAL_SMBUS_DISABLE(__HANDLE__)                 (CLEAR_BIT((__HANDLE__)->Instance->CR1, I2C_CR1_PE))
 483
 484 /** @brief  Generate a Non-Acknowledge SMBUS peripheral in Slave mode.
 485   * @param  __HANDLE__ specifies the SMBUS Handle.
 486   * @retval None
 487   */
 488 #define __HAL_SMBUS_GENERATE_NACK(__HANDLE__)           (SET_BIT((__HANDLE__)->Instance->CR2, I2C_CR2_NACK))
 489
 490 /**
 491   * @}
 492   */
 493
 494
 495 /* Private constants ---------------------------------------------------------*/
 496
 497 /* Private macros ------------------------------------------------------------*/
 498 /** @defgroup SMBUS_Private_Macro SMBUS Private Macros
 499   * @{
 500   */
 501
 502 #define IS_SMBUS_ANALOG_FILTER(FILTER)                  (((FILTER) == SMBUS_ANALOGFILTER_ENABLE) || \
 503                                                           ((FILTER) == SMBUS_ANALOGFILTER_DISABLE))
 504
 505 #define IS_SMBUS_ADDRESSING_MODE(MODE)                  (((MODE) == SMBUS_ADDRESSINGMODE_7BIT)  || \
 506                                                           ((MODE) == SMBUS_ADDRESSINGMODE_10BIT))
 507
 508 #define IS_SMBUS_DUAL_ADDRESS(ADDRESS)                  (((ADDRESS) == SMBUS_DUALADDRESS_DISABLE) || \
 509                                                           ((ADDRESS) == SMBUS_DUALADDRESS_ENABLE))
 510
 511 #define IS_SMBUS_OWN_ADDRESS2_MASK(MASK)                (((MASK) == SMBUS_OA2_NOMASK)    || \
 512                                                          ((MASK) == SMBUS_OA2_MASK01)    || \
 513                                                          ((MASK) == SMBUS_OA2_MASK02)    || \
 514                                                          ((MASK) == SMBUS_OA2_MASK03)    || \
 515                                                          ((MASK) == SMBUS_OA2_MASK04)    || \
 516                                                          ((MASK) == SMBUS_OA2_MASK05)    || \
 517                                                          ((MASK) == SMBUS_OA2_MASK06)    || \
 518                                                          ((MASK) == SMBUS_OA2_MASK07))
 519
 520 #define IS_SMBUS_GENERAL_CALL(CALL)                     (((CALL) == SMBUS_GENERALCALL_DISABLE) || \
 521                                                          ((CALL) == SMBUS_GENERALCALL_ENABLE))
 522
 523 #define IS_SMBUS_NO_STRETCH(STRETCH)                    (((STRETCH) == SMBUS_NOSTRETCH_DISABLE) || \
 524                                                          ((STRETCH) == SMBUS_NOSTRETCH_ENABLE))
 525
 526 #define IS_SMBUS_PEC(PEC)                               (((PEC) == SMBUS_PEC_DISABLE) || \
 527                                                           ((PEC) == SMBUS_PEC_ENABLE))
 528
 529 #define IS_SMBUS_PERIPHERAL_MODE(MODE)                  (((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_HOST)    || \
 530                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE)  || \
 531                                                           ((MODE) == SMBUS_PERIPHERAL_MODE_SMBUS_SLAVE_ARP))
 532
 533 #define IS_SMBUS_TRANSFER_MODE(MODE)                    (((MODE) == SMBUS_RELOAD_MODE)                           || \
 534                                                           ((MODE) == SMBUS_AUTOEND_MODE)                         || \
 535                                                           ((MODE) == SMBUS_SOFTEND_MODE)                         || \
 536                                                           ((MODE) == SMBUS_SENDPEC_MODE)                         || \
 537                                                           ((MODE) == (SMBUS_RELOAD_MODE | SMBUS_SENDPEC_MODE))   || \
 538                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE))  || \
 539                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_RELOAD_MODE))   || \
 540                                                           ((MODE) == (SMBUS_AUTOEND_MODE | SMBUS_SENDPEC_MODE | SMBUS_RELOAD_MODE )))
 541
 542
 543 #define IS_SMBUS_TRANSFER_REQUEST(REQUEST)              (((REQUEST) == SMBUS_GENERATE_STOP)              || \
 544                                                           ((REQUEST) == SMBUS_GENERATE_START_READ)       || \
 545                                                           ((REQUEST) == SMBUS_GENERATE_START_WRITE)      || \
 546                                                           ((REQUEST) == SMBUS_NO_STARTSTOP))
 547
 548
 549 #define IS_SMBUS_TRANSFER_OPTIONS_REQUEST(REQUEST)      (((REQUEST) == SMBUS_FIRST_FRAME)                        || \
 550                                                           ((REQUEST) == SMBUS_NEXT_FRAME)                        || \
 551                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_NO_PEC)       || \
 552                                                           ((REQUEST) == SMBUS_LAST_FRAME_NO_PEC)                 || \
 553                                                           ((REQUEST) == SMBUS_FIRST_AND_LAST_FRAME_WITH_PEC)     || \
 554                                                           ((REQUEST) == SMBUS_LAST_FRAME_WITH_PEC)               || \
 555                                                           IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST))
 556
 557 #define IS_SMBUS_TRANSFER_OTHER_OPTIONS_REQUEST(REQUEST) (((REQUEST) == SMBUS_OTHER_FRAME_NO_PEC)                || \
 558                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_NO_PEC)       || \
 559                                                           ((REQUEST) == SMBUS_OTHER_FRAME_WITH_PEC)              || \
 560                                                           ((REQUEST) == SMBUS_OTHER_AND_LAST_FRAME_WITH_PEC))
 561
 562 #define SMBUS_RESET_CR1(__HANDLE__)                       ((__HANDLE__)->Instance->CR1 &= (uint32_t)~((uint32_t)(I2C_CR1_SMBHEN | I2C_CR1_SMBDEN | I2C_CR1_PECEN)))
 563 #define SMBUS_RESET_CR2(__HANDLE__)                       ((__HANDLE__)->Instance->CR2 &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_HEAD10R | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_RD_WRN)))
 564
 565 #define SMBUS_GENERATE_START(__ADDMODE__,__ADDRESS__)     (((__ADDMODE__) == SMBUS_ADDRESSINGMODE_7BIT) ? (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_START) | (I2C_CR2_AUTOEND)) & (~I2C_CR2_RD_WRN)) : \
 566                                                                   (uint32_t)((((uint32_t)(__ADDRESS__) & (I2C_CR2_SADD)) | (I2C_CR2_ADD10) | (I2C_CR2_START)) & (~I2C_CR2_RD_WRN)))
 567
 568 #define SMBUS_GET_ADDR_MATCH(__HANDLE__)                  (((__HANDLE__)->Instance->ISR & I2C_ISR_ADDCODE) >> 17U)
 569 #define SMBUS_GET_DIR(__HANDLE__)                         (((__HANDLE__)->Instance->ISR & I2C_ISR_DIR) >> 16U)
 570 #define SMBUS_GET_STOP_MODE(__HANDLE__)                   ((__HANDLE__)->Instance->CR2 & I2C_CR2_AUTOEND)
 571 #define SMBUS_GET_PEC_MODE(__HANDLE__)                    ((__HANDLE__)->Instance->CR2 & I2C_CR2_PECBYTE)
 572 #define SMBUS_GET_ALERT_ENABLED(__HANDLE__)                ((__HANDLE__)->Instance->CR1 & I2C_CR1_ALERTEN)
 573
 574 #define SMBUS_GET_ISR_REG(__HANDLE__)                   ((__HANDLE__)->Instance->ISR)
 575 #define SMBUS_CHECK_FLAG(__ISR__, __FLAG__)             ((((__ISR__) & ((__FLAG__) & SMBUS_FLAG_MASK)) == ((__FLAG__) & SMBUS_FLAG_MASK)))
 576
 577 #define IS_SMBUS_OWN_ADDRESS1(ADDRESS1)                         ((ADDRESS1) <= 0x000003FFU)
 578 #define IS_SMBUS_OWN_ADDRESS2(ADDRESS2)                         ((ADDRESS2) <= (uint16_t)0x00FFU)
 579
 580 /**
 581   * @}
 582   */
 583
 584 /* Exported functions --------------------------------------------------------*/
 585 /** @addtogroup SMBUS_Exported_Functions SMBUS Exported Functions
 586   * @{
 587   */
 588
 589 /** @addtogroup SMBUS_Exported_Functions_Group1 Initialization and de-initialization functions
 590  * @{
 591  */
 592
 593 /* Initialization and de-initialization functions  **********************************/
 594 HAL_StatusTypeDef HAL_SMBUS_Init(SMBUS_HandleTypeDef *hsmbus);
 595 HAL_StatusTypeDef HAL_SMBUS_DeInit (SMBUS_HandleTypeDef *hsmbus);
 596 void HAL_SMBUS_MspInit(SMBUS_HandleTypeDef *hsmbus);
 597 void HAL_SMBUS_MspDeInit(SMBUS_HandleTypeDef *hsmbus);
 598
 599 /**
 600   * @}
 601   */
 602
 603 /** @addtogroup SMBUS_Exported_Functions_Group2 Input and Output operation functions
 604  * @{
 605  */
 606
 607 /* IO operation functions  *****************************************************/
 608 /** @addtogroup Blocking_mode_Polling Blocking mode Polling
 609  * @{
 610  */
 611 /******* Blocking mode: Polling */
 612 HAL_StatusTypeDef HAL_SMBUS_IsDeviceReady(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout);
 613 /**
 614   * @}
 615   */
 616
 617 /** @addtogroup Non-Blocking_mode_Interrupt Non-Blocking mode Interrupt
 618  * @{
 619  */
 620 /******* Non-Blocking mode: Interrupt */
 621 HAL_StatusTypeDef HAL_SMBUS_Master_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 622 HAL_StatusTypeDef HAL_SMBUS_Master_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 623 HAL_StatusTypeDef HAL_SMBUS_Master_Abort_IT(SMBUS_HandleTypeDef *hsmbus, uint16_t DevAddress);
 624 HAL_StatusTypeDef HAL_SMBUS_Slave_Transmit_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 625 HAL_StatusTypeDef HAL_SMBUS_Slave_Receive_IT(SMBUS_HandleTypeDef *hsmbus, uint8_t *pData, uint16_t Size, uint32_t XferOptions);
 626
 627 HAL_StatusTypeDef HAL_SMBUS_EnableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 628 HAL_StatusTypeDef HAL_SMBUS_DisableAlert_IT(SMBUS_HandleTypeDef *hsmbus);
 629 HAL_StatusTypeDef HAL_SMBUS_EnableListen_IT(SMBUS_HandleTypeDef *hsmbus);
 630 HAL_StatusTypeDef HAL_SMBUS_DisableListen_IT(SMBUS_HandleTypeDef *hsmbus);
 631 /**
 632   * @}
 633   */
 634
 635 /** @addtogroup SMBUS_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
 636  * @{
 637  */
 638 /******* SMBUS IRQHandler and Callbacks used in non blocking modes (Interrupt) */
 639 void HAL_SMBUS_EV_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 640 void HAL_SMBUS_ER_IRQHandler(SMBUS_HandleTypeDef *hsmbus);
 641 void HAL_SMBUS_MasterTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 642 void HAL_SMBUS_MasterRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 643 void HAL_SMBUS_SlaveTxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 644 void HAL_SMBUS_SlaveRxCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 645 void HAL_SMBUS_AddrCallback(SMBUS_HandleTypeDef *hsmbus, uint8_t TransferDirection, uint16_t AddrMatchCode);
 646 void HAL_SMBUS_ListenCpltCallback(SMBUS_HandleTypeDef *hsmbus);
 647 void HAL_SMBUS_ErrorCallback(SMBUS_HandleTypeDef *hsmbus);
 648
 649 /**
 650   * @}
 651   */
 652
 653 /** @addtogroup SMBUS_Exported_Functions_Group3 Peripheral State and Errors functions
 654  *  @{
 655  */
 656
 657 /* Peripheral State and Errors functions  **************************************************/
 658 uint32_t HAL_SMBUS_GetState(SMBUS_HandleTypeDef *hsmbus);
 659 uint32_t HAL_SMBUS_GetError(SMBUS_HandleTypeDef *hsmbus);
 660
 661 /**
 662   * @}
 663   */
 664
 665 /**
 666   * @}
 667   */
 668
 669 /* Private Functions ---------------------------------------------------------*/
 670 /** @defgroup SMBUS_Private_Functions SMBUS Private Functions
 671   * @{
 672   */
 673 /* Private functions are defined in stm32f7xx_hal_smbus.c file */
 674 /**
 675   * @}
 676   */
 677
 678 /**
 679   * @}
 680   */
 681
 682 /**
 683   * @}
 684   */
 685
 686 /**
 687   * @}
 688   */
 689
 690 #ifdef __cplusplus
 691 }
 692 #endif
 693
 694
 695 #endif /* __STM32F7xx_HAL_SMBUS_H */
 696
 697 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/