lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_spi.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_spi.h
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   Header file of SPI HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_SPI_H
  40 #define __STM32F7xx_HAL_SPI_H
  41
  42 #ifdef __cplusplus
  43 extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_hal_def.h"
  48
  49 /** @addtogroup STM32F7xx_HAL_Driver
  50   * @{
  51   */
  52
  53 /** @addtogroup SPI
  54   * @{
  55   */
  56
  57 /* Exported types ------------------------------------------------------------*/
  58 /** @defgroup SPI_Exported_Types SPI Exported Types
  59   * @{
  60   */
  61
  62 /**
  63   * @brief  SPI Configuration Structure definition
  64   */
  65 typedef struct
  66 {
  67     uint32_t Mode;                /*!< Specifies the SPI operating mode.
  68                                      This parameter can be a value of @ref SPI_Mode */
  69
  70     uint32_t Direction;           /*!< Specifies the SPI bidirectional mode state.
  71                                      This parameter can be a value of @ref SPI_Direction */
  72
  73     uint32_t DataSize;            /*!< Specifies the SPI data size.
  74                                      This parameter can be a value of @ref SPI_Data_Size */
  75
  76     uint32_t CLKPolarity;         /*!< Specifies the serial clock steady state.
  77                                      This parameter can be a value of @ref SPI_Clock_Polarity */
  78
  79     uint32_t CLKPhase;            /*!< Specifies the clock active edge for the bit capture.
  80                                      This parameter can be a value of @ref SPI_Clock_Phase */
  81
  82     uint32_t NSS;                 /*!< Specifies whether the NSS signal is managed by
  83                                      hardware (NSS pin) or by software using the SSI bit.
  84                                      This parameter can be a value of @ref SPI_Slave_Select_management */
  85
  86     uint32_t BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
  87                                      used to configure the transmit and receive SCK clock.
  88                                      This parameter can be a value of @ref SPI_BaudRate_Prescaler
  89                                      @note The communication clock is derived from the master
  90                                      clock. The slave clock does not need to be set. */
  91
  92     uint32_t FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
  93                                      This parameter can be a value of @ref SPI_MSB_LSB_transmission */
  94
  95     uint32_t TIMode;              /*!< Specifies if the TI mode is enabled or not.
  96                                      This parameter can be a value of @ref SPI_TI_mode */
  97
  98     uint32_t CRCCalculation;      /*!< Specifies if the CRC calculation is enabled or not.
  99                                      This parameter can be a value of @ref SPI_CRC_Calculation */
 100
 101     uint32_t CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation.
 102                                      This parameter must be an odd number between Min_Data = 0 and Max_Data = 65535 */
 103
 104     uint32_t CRCLength;           /*!< Specifies the CRC Length used for the CRC calculation.
 105                                      CRC Length is only used with Data8 and Data16, not other data size
 106                                      This parameter can be a value of @ref SPI_CRC_length */
 107
 108     uint32_t NSSPMode;            /*!< Specifies whether the NSSP signal is enabled or not .
 109                                      This parameter can be a value of @ref SPI_NSSP_Mode
 110                                      This mode is activated by the NSSP bit in the SPIx_CR2 register and
 111                                      it takes effect only if the SPI interface is configured as Motorola SPI
 112                                      master (FRF=0) with capture on the first edge (SPIx_CR1 CPHA = 0,
 113                                      CPOL setting is ignored).. */
 114 } SPI_InitTypeDef;
 115
 116 /**
 117   * @brief  HAL SPI State structure definition
 118   */
 119 typedef enum
 120 {
 121     HAL_SPI_STATE_RESET      = 0x00U,    /*!< Peripheral not Initialized                         */
 122     HAL_SPI_STATE_READY      = 0x01U,    /*!< Peripheral Initialized and ready for use           */
 123     HAL_SPI_STATE_BUSY       = 0x02U,    /*!< an internal process is ongoing                     */
 124     HAL_SPI_STATE_BUSY_TX    = 0x03U,    /*!< Data Transmission process is ongoing               */
 125     HAL_SPI_STATE_BUSY_RX    = 0x04U,    /*!< Data Reception process is ongoing                  */
 126     HAL_SPI_STATE_BUSY_TX_RX = 0x05U,    /*!< Data Transmission and Reception process is ongoing */
 127     HAL_SPI_STATE_ERROR      = 0x06U,    /*!< SPI error state                                    */
 128     HAL_SPI_STATE_ABORT      = 0x07U     /*!< SPI abort is ongoing                               */
 129 } HAL_SPI_StateTypeDef;
 130
 131 /**
 132   * @brief  SPI handle Structure definition
 133   */
 134 typedef struct __SPI_HandleTypeDef
 135 {
 136     SPI_TypeDef                *Instance;      /*!< SPI registers base address               */
 137
 138     SPI_InitTypeDef            Init;           /*!< SPI communication parameters             */
 139
 140     uint8_t                    *pTxBuffPtr;    /*!< Pointer to SPI Tx transfer Buffer        */
 141
 142     uint16_t                   TxXferSize;     /*!< SPI Tx Transfer size                     */
 143
 144     __IO uint16_t              TxXferCount;    /*!< SPI Tx Transfer Counter                  */
 145
 146     uint8_t                    *pRxBuffPtr;    /*!< Pointer to SPI Rx transfer Buffer        */
 147
 148     uint16_t                   RxXferSize;     /*!< SPI Rx Transfer size                     */
 149
 150     __IO uint16_t              RxXferCount;    /*!< SPI Rx Transfer Counter                  */
 151
 152     uint32_t                   CRCSize;        /*!< SPI CRC size used for the transfer       */
 153
 154     void (*RxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Rx ISR */
 155
 156     void (*TxISR)(struct __SPI_HandleTypeDef *hspi);                       /*!< function pointer on Tx ISR */
 157
 158     DMA_HandleTypeDef          *hdmatx;        /*!< SPI Tx DMA Handle parameters             */
 159
 160     DMA_HandleTypeDef          *hdmarx;        /*!< SPI Rx DMA Handle parameters             */
 161
 162     HAL_LockTypeDef            Lock;           /*!< Locking object                           */
 163
 164     __IO HAL_SPI_StateTypeDef  State;          /*!< SPI communication state                  */
 165
 166     __IO uint32_t              ErrorCode;      /*!< SPI Error code                           */
 167
 168 } SPI_HandleTypeDef;
 169
 170 /**
 171   * @}
 172   */
 173
 174 /* Exported constants --------------------------------------------------------*/
 175
 176 /** @defgroup SPI_Exported_Constants SPI Exported Constants
 177   * @{
 178   */
 179
 180 /** @defgroup SPI_Error_Code SPI Error Code
 181   * @{
 182   */
 183 #define HAL_SPI_ERROR_NONE              ((uint32_t)0x00000000U)   /*!< No error                               */
 184 #define HAL_SPI_ERROR_MODF              ((uint32_t)0x00000001U)   /*!< MODF error                             */
 185 #define HAL_SPI_ERROR_CRC               ((uint32_t)0x00000002U)   /*!< CRC error                              */
 186 #define HAL_SPI_ERROR_OVR               ((uint32_t)0x00000004U)   /*!< OVR error                              */
 187 #define HAL_SPI_ERROR_FRE               ((uint32_t)0x00000008U)   /*!< FRE error                              */
 188 #define HAL_SPI_ERROR_DMA               ((uint32_t)0x00000010U)   /*!< DMA transfer error                     */
 189 #define HAL_SPI_ERROR_FLAG              ((uint32_t)0x00000020U)   /*!< Error on RXNE/TXE/BSY/FTLVL/FRLVL Flag */
 190 #define HAL_SPI_ERROR_ABORT             ((uint32_t)0x00000040U)   /*!< Error during SPI Abort procedure       */
 191 /**
 192   * @}
 193   */
 194
 195 /** @defgroup SPI_Mode SPI Mode
 196   * @{
 197   */
 198 #define SPI_MODE_SLAVE                  ((uint32_t)0x00000000U)
 199 #define SPI_MODE_MASTER                 (SPI_CR1_MSTR | SPI_CR1_SSI)
 200 /**
 201   * @}
 202   */
 203
 204 /** @defgroup SPI_Direction SPI Direction Mode
 205   * @{
 206   */
 207 #define SPI_DIRECTION_2LINES            ((uint32_t)0x00000000U)
 208 #define SPI_DIRECTION_2LINES_RXONLY     SPI_CR1_RXONLY
 209 #define SPI_DIRECTION_1LINE             SPI_CR1_BIDIMODE
 210 /**
 211   * @}
 212   */
 213
 214 /** @defgroup SPI_Data_Size SPI Data Size
 215   * @{
 216   */
 217 #define SPI_DATASIZE_4BIT               ((uint32_t)0x00000300U)
 218 #define SPI_DATASIZE_5BIT               ((uint32_t)0x00000400U)
 219 #define SPI_DATASIZE_6BIT               ((uint32_t)0x00000500U)
 220 #define SPI_DATASIZE_7BIT               ((uint32_t)0x00000600U)
 221 #define SPI_DATASIZE_8BIT               ((uint32_t)0x00000700U)
 222 #define SPI_DATASIZE_9BIT               ((uint32_t)0x00000800U)
 223 #define SPI_DATASIZE_10BIT              ((uint32_t)0x00000900U)
 224 #define SPI_DATASIZE_11BIT              ((uint32_t)0x00000A00U)
 225 #define SPI_DATASIZE_12BIT              ((uint32_t)0x00000B00U)
 226 #define SPI_DATASIZE_13BIT              ((uint32_t)0x00000C00U)
 227 #define SPI_DATASIZE_14BIT              ((uint32_t)0x00000D00U)
 228 #define SPI_DATASIZE_15BIT              ((uint32_t)0x00000E00U)
 229 #define SPI_DATASIZE_16BIT              ((uint32_t)0x00000F00U)
 230 /**
 231   * @}
 232   */
 233
 234 /** @defgroup SPI_Clock_Polarity SPI Clock Polarity
 235   * @{
 236   */
 237 #define SPI_POLARITY_LOW                ((uint32_t)0x00000000U)
 238 #define SPI_POLARITY_HIGH               SPI_CR1_CPOL
 239 /**
 240   * @}
 241   */
 242
 243 /** @defgroup SPI_Clock_Phase SPI Clock Phase
 244   * @{
 245   */
 246 #define SPI_PHASE_1EDGE                 ((uint32_t)0x00000000U)
 247 #define SPI_PHASE_2EDGE                 SPI_CR1_CPHA
 248 /**
 249   * @}
 250   */
 251
 252 /** @defgroup SPI_Slave_Select_management SPI Slave Select Management
 253   * @{
 254   */
 255 #define SPI_NSS_SOFT                    SPI_CR1_SSM
 256 #define SPI_NSS_HARD_INPUT              ((uint32_t)0x00000000U)
 257 #define SPI_NSS_HARD_OUTPUT             ((uint32_t)0x00040000U)
 258 /**
 259   * @}
 260   */
 261
 262 /** @defgroup SPI_NSSP_Mode SPI NSS Pulse Mode
 263   * @{
 264   */
 265 #define SPI_NSS_PULSE_ENABLE            SPI_CR2_NSSP
 266 #define SPI_NSS_PULSE_DISABLE           ((uint32_t)0x00000000U)
 267 /**
 268   * @}
 269   */
 270
 271 /** @defgroup SPI_BaudRate_Prescaler SPI BaudRate Prescaler
 272   * @{
 273   */
 274 #define SPI_BAUDRATEPRESCALER_2         ((uint32_t)0x00000000U)
 275 #define SPI_BAUDRATEPRESCALER_4         ((uint32_t)0x00000008U)
 276 #define SPI_BAUDRATEPRESCALER_8         ((uint32_t)0x00000010U)
 277 #define SPI_BAUDRATEPRESCALER_16        ((uint32_t)0x00000018U)
 278 #define SPI_BAUDRATEPRESCALER_32        ((uint32_t)0x00000020U)
 279 #define SPI_BAUDRATEPRESCALER_64        ((uint32_t)0x00000028U)
 280 #define SPI_BAUDRATEPRESCALER_128       ((uint32_t)0x00000030U)
 281 #define SPI_BAUDRATEPRESCALER_256       ((uint32_t)0x00000038U)
 282 /**
 283   * @}
 284   */
 285
 286 /** @defgroup SPI_MSB_LSB_transmission SPI MSB LSB Transmission
 287   * @{
 288   */
 289 #define SPI_FIRSTBIT_MSB                ((uint32_t)0x00000000U)
 290 #define SPI_FIRSTBIT_LSB                SPI_CR1_LSBFIRST
 291 /**
 292   * @}
 293   */
 294
 295 /** @defgroup SPI_TI_mode SPI TI Mode
 296   * @{
 297   */
 298 #define SPI_TIMODE_DISABLE              ((uint32_t)0x00000000U)
 299 #define SPI_TIMODE_ENABLE               SPI_CR2_FRF
 300 /**
 301   * @}
 302   */
 303
 304 /** @defgroup SPI_CRC_Calculation SPI CRC Calculation
 305   * @{
 306   */
 307 #define SPI_CRCCALCULATION_DISABLE      ((uint32_t)0x00000000U)
 308 #define SPI_CRCCALCULATION_ENABLE       SPI_CR1_CRCEN
 309 /**
 310   * @}
 311   */
 312
 313 /** @defgroup SPI_CRC_length SPI CRC Length
 314   * @{
 315   * This parameter can be one of the following values:
 316   *     SPI_CRC_LENGTH_DATASIZE: aligned with the data size
 317   *     SPI_CRC_LENGTH_8BIT    : CRC 8bit
 318   *     SPI_CRC_LENGTH_16BIT   : CRC 16bit
 319   */
 320 #define SPI_CRC_LENGTH_DATASIZE         ((uint32_t)0x00000000U)
 321 #define SPI_CRC_LENGTH_8BIT             ((uint32_t)0x00000001U)
 322 #define SPI_CRC_LENGTH_16BIT            ((uint32_t)0x00000002U)
 323 /**
 324   * @}
 325   */
 326
 327 /** @defgroup SPI_FIFO_reception_threshold SPI FIFO Reception Threshold
 328   * @{
 329   * This parameter can be one of the following values:
 330   *     SPI_RXFIFO_THRESHOLD or SPI_RXFIFO_THRESHOLD_QF :
 331   *          RXNE event is generated if the FIFO
 332   *          level is greater or equal to 1/2(16-bits).
 333   *     SPI_RXFIFO_THRESHOLD_HF: RXNE event is generated if the FIFO
 334   *          level is greater or equal to 1/4(8 bits). */
 335 #define SPI_RXFIFO_THRESHOLD            SPI_CR2_FRXTH
 336 #define SPI_RXFIFO_THRESHOLD_QF         SPI_CR2_FRXTH
 337 #define SPI_RXFIFO_THRESHOLD_HF         ((uint32_t)0x00000000U)
 338
 339 /**
 340   * @}
 341   */
 342
 343 /** @defgroup SPI_Interrupt_definition SPI Interrupt Definition
 344   * @{
 345   */
 346 #define SPI_IT_TXE                      SPI_CR2_TXEIE
 347 #define SPI_IT_RXNE                     SPI_CR2_RXNEIE
 348 #define SPI_IT_ERR                      SPI_CR2_ERRIE
 349 /**
 350   * @}
 351   */
 352
 353 /** @defgroup SPI_Flags_definition SPI Flags Definition
 354   * @{
 355   */
 356 #define SPI_FLAG_RXNE                   SPI_SR_RXNE   /* SPI status flag: Rx buffer not empty flag       */
 357 #define SPI_FLAG_TXE                    SPI_SR_TXE    /* SPI status flag: Tx buffer empty flag           */
 358 #define SPI_FLAG_BSY                    SPI_SR_BSY    /* SPI status flag: Busy flag                      */
 359 #define SPI_FLAG_CRCERR                 SPI_SR_CRCERR /* SPI Error flag: CRC error flag                  */
 360 #define SPI_FLAG_MODF                   SPI_SR_MODF   /* SPI Error flag: Mode fault flag                 */
 361 #define SPI_FLAG_OVR                    SPI_SR_OVR    /* SPI Error flag: Overrun flag                    */
 362 #define SPI_FLAG_FRE                    SPI_SR_FRE    /* SPI Error flag: TI mode frame format error flag */
 363 #define SPI_FLAG_FTLVL                  SPI_SR_FTLVL  /* SPI fifo transmission level                     */
 364 #define SPI_FLAG_FRLVL                  SPI_SR_FRLVL  /* SPI fifo reception level                        */
 365 /**
 366   * @}
 367   */
 368
 369 /** @defgroup SPI_transmission_fifo_status_level SPI Transmission FIFO Status Level
 370   * @{
 371   */
 372 #define SPI_FTLVL_EMPTY           ((uint32_t)0x00000000U)
 373 #define SPI_FTLVL_QUARTER_FULL    ((uint32_t)0x00000800U)
 374 #define SPI_FTLVL_HALF_FULL       ((uint32_t)0x00001000U)
 375 #define SPI_FTLVL_FULL            ((uint32_t)0x00001800U)
 376
 377 /**
 378   * @}
 379   */
 380
 381 /** @defgroup SPI_reception_fifo_status_level SPI Reception FIFO Status Level
 382   * @{
 383   */
 384 #define SPI_FRLVL_EMPTY           ((uint32_t)0x00000000U)
 385 #define SPI_FRLVL_QUARTER_FULL    ((uint32_t)0x00000200U)
 386 #define SPI_FRLVL_HALF_FULL       ((uint32_t)0x00000400U)
 387 #define SPI_FRLVL_FULL            ((uint32_t)0x00000600U)
 388 /**
 389   * @}
 390   */
 391
 392 /* Exported macros -----------------------------------------------------------*/
 393 /** @defgroup SPI_Exported_Macros SPI Exported Macros
 394   * @{
 395   */
 396
 397 /** @brief  Reset SPI handle state.
 398   * @param  __HANDLE__: specifies the SPI Handle.
 399   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 400   * @retval None
 401   */
 402 #define __HAL_SPI_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SPI_STATE_RESET)
 403
 404 /** @brief  Enable or disable the specified SPI interrupts.
 405   * @param  __HANDLE__: specifies the SPI Handle.
 406   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 407   * @param  __INTERRUPT__: specifies the interrupt source to enable or disable.
 408   *         This parameter can be one of the following values:
 409   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 410   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 411   *            @arg SPI_IT_ERR: Error interrupt enable
 412   * @retval None
 413   */
 414 #define __HAL_SPI_ENABLE_IT(__HANDLE__, __INTERRUPT__)   ((__HANDLE__)->Instance->CR2 |= (__INTERRUPT__))
 415 #define __HAL_SPI_DISABLE_IT(__HANDLE__, __INTERRUPT__)  ((__HANDLE__)->Instance->CR2 &= (~(__INTERRUPT__)))
 416
 417 /** @brief  Check whether the specified SPI interrupt source is enabled or not.
 418   * @param  __HANDLE__: specifies the SPI Handle.
 419   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 420   * @param  __INTERRUPT__: specifies the SPI interrupt source to check.
 421   *          This parameter can be one of the following values:
 422   *            @arg SPI_IT_TXE: Tx buffer empty interrupt enable
 423   *            @arg SPI_IT_RXNE: RX buffer not empty interrupt enable
 424   *            @arg SPI_IT_ERR: Error interrupt enable
 425   * @retval The new state of __IT__ (TRUE or FALSE).
 426   */
 427 #define __HAL_SPI_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->CR2 & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
 428
 429 /** @brief  Check whether the specified SPI flag is set or not.
 430   * @param  __HANDLE__: specifies the SPI Handle.
 431   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 432   * @param  __FLAG__: specifies the flag to check.
 433   *         This parameter can be one of the following values:
 434   *            @arg SPI_FLAG_RXNE: Receive buffer not empty flag
 435   *            @arg SPI_FLAG_TXE: Transmit buffer empty flag
 436   *            @arg SPI_FLAG_CRCERR: CRC error flag
 437   *            @arg SPI_FLAG_MODF: Mode fault flag
 438   *            @arg SPI_FLAG_OVR: Overrun flag
 439   *            @arg SPI_FLAG_BSY: Busy flag
 440   *            @arg SPI_FLAG_FRE: Frame format error flag
 441   *            @arg SPI_FLAG_FTLVL: SPI fifo transmission level
 442   *            @arg SPI_FLAG_FRLVL: SPI fifo reception level
 443   * @retval The new state of __FLAG__ (TRUE or FALSE).
 444   */
 445 #define __HAL_SPI_GET_FLAG(__HANDLE__, __FLAG__) ((((__HANDLE__)->Instance->SR) & (__FLAG__)) == (__FLAG__))
 446
 447 /** @brief  Clear the SPI CRCERR pending flag.
 448   * @param  __HANDLE__: specifies the SPI Handle.
 449   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 450   * @retval None
 451   */
 452 #define __HAL_SPI_CLEAR_CRCERRFLAG(__HANDLE__) ((__HANDLE__)->Instance->SR = (uint16_t)(~SPI_FLAG_CRCERR))
 453
 454 /** @brief  Clear the SPI MODF pending flag.
 455   * @param  __HANDLE__: specifies the SPI Handle.
 456   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 457   * @retval None
 458   */
 459 #define __HAL_SPI_CLEAR_MODFFLAG(__HANDLE__)       \
 460   do{                                              \
 461     __IO uint32_t tmpreg_modf = 0x00U;             \
 462     tmpreg_modf = (__HANDLE__)->Instance->SR;      \
 463     (__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE); \
 464     UNUSED(tmpreg_modf);                           \
 465   } while(0)
 466
 467 /** @brief  Clear the SPI OVR pending flag.
 468   * @param  __HANDLE__: specifies the SPI Handle.
 469   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 470   * @retval None
 471   */
 472 #define __HAL_SPI_CLEAR_OVRFLAG(__HANDLE__)        \
 473   do{                                              \
 474     __IO uint32_t tmpreg_ovr = 0x00U;              \
 475     tmpreg_ovr = (__HANDLE__)->Instance->DR;       \
 476     tmpreg_ovr = (__HANDLE__)->Instance->SR;       \
 477     UNUSED(tmpreg_ovr);                            \
 478   } while(0)
 479
 480 /** @brief  Clear the SPI FRE pending flag.
 481   * @param  __HANDLE__: specifies the SPI Handle.
 482   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 483   * @retval None
 484   */
 485 #define __HAL_SPI_CLEAR_FREFLAG(__HANDLE__)        \
 486   do{                                              \
 487   __IO uint32_t tmpreg_fre = 0x00U;                \
 488   tmpreg_fre = (__HANDLE__)->Instance->SR;         \
 489   UNUSED(tmpreg_fre);                              \
 490   }while(0)
 491
 492 /** @brief  Enable the SPI peripheral.
 493   * @param  __HANDLE__: specifies the SPI Handle.
 494   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 495   * @retval None
 496   */
 497 #define __HAL_SPI_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 |=  SPI_CR1_SPE)
 498
 499 /** @brief  Disable the SPI peripheral.
 500   * @param  __HANDLE__: specifies the SPI Handle.
 501   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 502   * @retval None
 503   */
 504 #define __HAL_SPI_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_SPE))
 505
 506 /**
 507   * @}
 508   */
 509
 510 /* Private macros ------------------------------------------------------------*/
 511 /** @defgroup SPI_Private_Macros SPI Private Macros
 512   * @{
 513   */
 514
 515 /** @brief  Set the SPI transmit-only mode.
 516   * @param  __HANDLE__: specifies the SPI Handle.
 517   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 518   * @retval None
 519   */
 520 #define SPI_1LINE_TX(__HANDLE__) ((__HANDLE__)->Instance->CR1 |= SPI_CR1_BIDIOE)
 521
 522 /** @brief  Set the SPI receive-only mode.
 523   * @param  __HANDLE__: specifies the SPI Handle.
 524   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 525   * @retval None
 526   */
 527 #define SPI_1LINE_RX(__HANDLE__) ((__HANDLE__)->Instance->CR1 &= (~SPI_CR1_BIDIOE))
 528
 529 /** @brief  Reset the CRC calculation of the SPI.
 530   * @param  __HANDLE__: specifies the SPI Handle.
 531   *         This parameter can be SPI where x: 1, 2, or 3 to select the SPI peripheral.
 532   * @retval None
 533   */
 534 #define SPI_RESET_CRC(__HANDLE__) do{(__HANDLE__)->Instance->CR1 &= (uint16_t)(~SPI_CR1_CRCEN);\
 535                                      (__HANDLE__)->Instance->CR1 |= SPI_CR1_CRCEN;}while(0)
 536
 537 #define IS_SPI_MODE(MODE) (((MODE) == SPI_MODE_SLAVE) || \
 538                            ((MODE) == SPI_MODE_MASTER))
 539
 540 #define IS_SPI_DIRECTION(MODE)   (((MODE) == SPI_DIRECTION_2LINES)        || \
 541                                   ((MODE) == SPI_DIRECTION_2LINES_RXONLY) || \
 542                                   ((MODE) == SPI_DIRECTION_1LINE))
 543
 544 #define IS_SPI_DIRECTION_2LINES(MODE) ((MODE) == SPI_DIRECTION_2LINES)
 545
 546 #define IS_SPI_DIRECTION_2LINES_OR_1LINE(MODE) (((MODE) == SPI_DIRECTION_2LINES) || \
 547                                                 ((MODE) == SPI_DIRECTION_1LINE))
 548
 549 #define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DATASIZE_16BIT) || \
 550                                    ((DATASIZE) == SPI_DATASIZE_15BIT) || \
 551                                    ((DATASIZE) == SPI_DATASIZE_14BIT) || \
 552                                    ((DATASIZE) == SPI_DATASIZE_13BIT) || \
 553                                    ((DATASIZE) == SPI_DATASIZE_12BIT) || \
 554                                    ((DATASIZE) == SPI_DATASIZE_11BIT) || \
 555                                    ((DATASIZE) == SPI_DATASIZE_10BIT) || \
 556                                    ((DATASIZE) == SPI_DATASIZE_9BIT)  || \
 557                                    ((DATASIZE) == SPI_DATASIZE_8BIT)  || \
 558                                    ((DATASIZE) == SPI_DATASIZE_7BIT)  || \
 559                                    ((DATASIZE) == SPI_DATASIZE_6BIT)  || \
 560                                    ((DATASIZE) == SPI_DATASIZE_5BIT)  || \
 561                                    ((DATASIZE) == SPI_DATASIZE_4BIT))
 562
 563 #define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_POLARITY_LOW) || \
 564                            ((CPOL) == SPI_POLARITY_HIGH))
 565
 566 #define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_PHASE_1EDGE) || \
 567                            ((CPHA) == SPI_PHASE_2EDGE))
 568
 569 #define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_SOFT)       || \
 570                          ((NSS) == SPI_NSS_HARD_INPUT) || \
 571                          ((NSS) == SPI_NSS_HARD_OUTPUT))
 572
 573 #define IS_SPI_NSSP(NSSP) (((NSSP) == SPI_NSS_PULSE_ENABLE) || \
 574                            ((NSSP) == SPI_NSS_PULSE_DISABLE))
 575
 576 #define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BAUDRATEPRESCALER_2)   || \
 577                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_4)   || \
 578                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_8)   || \
 579                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_16)  || \
 580                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_32)  || \
 581                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_64)  || \
 582                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_128) || \
 583                                               ((PRESCALER) == SPI_BAUDRATEPRESCALER_256))
 584
 585 #define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FIRSTBIT_MSB) || \
 586                                ((BIT) == SPI_FIRSTBIT_LSB))
 587
 588 #define IS_SPI_TIMODE(MODE) (((MODE) == SPI_TIMODE_DISABLE) || \
 589                              ((MODE) == SPI_TIMODE_ENABLE))
 590
 591 #define IS_SPI_CRC_CALCULATION(CALCULATION) (((CALCULATION) == SPI_CRCCALCULATION_DISABLE) || \
 592                                              ((CALCULATION) == SPI_CRCCALCULATION_ENABLE))
 593
 594 #define IS_SPI_CRC_LENGTH(LENGTH) (((LENGTH) == SPI_CRC_LENGTH_DATASIZE) ||\
 595                                    ((LENGTH) == SPI_CRC_LENGTH_8BIT)  ||   \
 596                                    ((LENGTH) == SPI_CRC_LENGTH_16BIT))
 597
 598 #define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) (((POLYNOMIAL) >= 0x1) && ((POLYNOMIAL) <= 0xFFFFU) && (((POLYNOMIAL)&0x1U) != 0))
 599
 600 /**
 601   * @}
 602   */
 603
 604 /* Exported functions --------------------------------------------------------*/
 605 /** @addtogroup SPI_Exported_Functions
 606   * @{
 607   */
 608
 609 /** @addtogroup SPI_Exported_Functions_Group1 Initialization and de-initialization functions
 610   * @{
 611   */
 612 /* Initialization/de-initialization functions  ********************************/
 613 HAL_StatusTypeDef HAL_SPI_Init(SPI_HandleTypeDef *hspi);
 614 HAL_StatusTypeDef HAL_SPI_DeInit(SPI_HandleTypeDef *hspi);
 615 void HAL_SPI_MspInit(SPI_HandleTypeDef *hspi);
 616 void HAL_SPI_MspDeInit(SPI_HandleTypeDef *hspi);
 617 /**
 618   * @}
 619   */
 620
 621 /** @addtogroup SPI_Exported_Functions_Group2 IO operation functions
 622   * @{
 623   */
 624 /* I/O operation functions  ***************************************************/
 625 HAL_StatusTypeDef HAL_SPI_Transmit(SPI_HandleTypeDef *hspi, const uint8_t *pData, uint16_t Size, uint32_t Timeout);
 626 HAL_StatusTypeDef HAL_SPI_Receive(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size, uint32_t Timeout);
 627 HAL_StatusTypeDef HAL_SPI_TransmitReceive(SPI_HandleTypeDef *hspi, const uint8_t *pTxData, uint8_t *pRxData, uint16_t Size,
 628         uint32_t Timeout);
 629 HAL_StatusTypeDef HAL_SPI_Transmit_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 630 HAL_StatusTypeDef HAL_SPI_Receive_IT(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 631 HAL_StatusTypeDef HAL_SPI_TransmitReceive_IT(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 632         uint16_t Size);
 633 HAL_StatusTypeDef HAL_SPI_Transmit_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 634 HAL_StatusTypeDef HAL_SPI_Receive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pData, uint16_t Size);
 635 HAL_StatusTypeDef HAL_SPI_TransmitReceive_DMA(SPI_HandleTypeDef *hspi, uint8_t *pTxData, uint8_t *pRxData,
 636         uint16_t Size);
 637 HAL_StatusTypeDef HAL_SPI_DMAPause(SPI_HandleTypeDef *hspi);
 638 HAL_StatusTypeDef HAL_SPI_DMAResume(SPI_HandleTypeDef *hspi);
 639 HAL_StatusTypeDef HAL_SPI_DMAStop(SPI_HandleTypeDef *hspi);
 640 /* Transfer Abort functions */
 641 HAL_StatusTypeDef HAL_SPI_Abort(SPI_HandleTypeDef *hspi);
 642 HAL_StatusTypeDef HAL_SPI_Abort_IT(SPI_HandleTypeDef *hspi);
 643
 644 void HAL_SPI_IRQHandler(SPI_HandleTypeDef *hspi);
 645 void HAL_SPI_TxCpltCallback(SPI_HandleTypeDef *hspi);
 646 void HAL_SPI_RxCpltCallback(SPI_HandleTypeDef *hspi);
 647 void HAL_SPI_TxRxCpltCallback(SPI_HandleTypeDef *hspi);
 648 void HAL_SPI_TxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 649 void HAL_SPI_RxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 650 void HAL_SPI_TxRxHalfCpltCallback(SPI_HandleTypeDef *hspi);
 651 void HAL_SPI_ErrorCallback(SPI_HandleTypeDef *hspi);
 652 void HAL_SPI_AbortCpltCallback(SPI_HandleTypeDef *hspi);
 653 /**
 654   * @}
 655   */
 656
 657 /** @addtogroup SPI_Exported_Functions_Group3 Peripheral State and Errors functions
 658   * @{
 659   */
 660
 661 /* Peripheral State and Error functions ***************************************/
 662 HAL_SPI_StateTypeDef HAL_SPI_GetState(SPI_HandleTypeDef *hspi);
 663 uint32_t             HAL_SPI_GetError(SPI_HandleTypeDef *hspi);
 664 /**
 665   * @}
 666   */
 667
 668 /**
 669   * @}
 670   */
 671
 672 /**
 673   * @}
 674   */
 675
 676 /**
 677   * @}
 678   */
 679
 680 #ifdef __cplusplus
 681 }
 682 #endif
 683
 684 #endif /* __STM32F7xx_HAL_SPI_H */
 685
 686 /**
 687   * @}
 688   */
 689 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/