lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Inc/stm32f7xx_hal_sram.h

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_sram.h
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   Header file of SRAM HAL module.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37
  38 /* Define to prevent recursive inclusion -------------------------------------*/
  39 #ifndef __STM32F7xx_HAL_SRAM_H
  40 #define __STM32F7xx_HAL_SRAM_H
  41
  42 #ifdef __cplusplus
  43  extern "C" {
  44 #endif
  45
  46 /* Includes ------------------------------------------------------------------*/
  47 #include "stm32f7xx_ll_fmc.h"
  48
  49 /** @addtogroup STM32F7xx_HAL_Driver
  50   * @{
  51   */
  52 /** @addtogroup SRAM
  53   * @{
  54   */
  55
  56 /* Exported typedef ----------------------------------------------------------*/
  57
  58 /** @defgroup SRAM_Exported_Types SRAM Exported Types
  59   * @{
  60   */
  61 /**
  62   * @brief  HAL SRAM State structures definition
  63   */
  64 typedef enum
  65 {
  66   HAL_SRAM_STATE_RESET     = 0x00U,  /*!< SRAM not yet initialized or disabled           */
  67   HAL_SRAM_STATE_READY     = 0x01U,  /*!< SRAM initialized and ready for use             */
  68   HAL_SRAM_STATE_BUSY      = 0x02U,  /*!< SRAM internal process is ongoing               */
  69   HAL_SRAM_STATE_ERROR     = 0x03U,  /*!< SRAM error state                               */
  70   HAL_SRAM_STATE_PROTECTED = 0x04U   /*!< SRAM peripheral NORSRAM device write protected */
  71
  72 }HAL_SRAM_StateTypeDef;
  73
  74 /**
  75   * @brief  SRAM handle Structure definition
  76   */
  77 typedef struct
  78 {
  79   FMC_NORSRAM_TypeDef           *Instance;  /*!< Register base address                        */
  80
  81   FMC_NORSRAM_EXTENDED_TypeDef  *Extended;  /*!< Extended mode register base address          */
  82
  83   FMC_NORSRAM_InitTypeDef       Init;       /*!< SRAM device control configuration parameters */
  84
  85   HAL_LockTypeDef               Lock;       /*!< SRAM locking object                          */
  86
  87   __IO HAL_SRAM_StateTypeDef    State;      /*!< SRAM device access state                     */
  88
  89   DMA_HandleTypeDef             *hdma;      /*!< Pointer DMA handler                          */
  90
  91 }SRAM_HandleTypeDef;
  92
  93 /**
  94   * @}
  95   */
  96
  97 /* Exported constants --------------------------------------------------------*/
  98 /* Exported macro ------------------------------------------------------------*/
  99
 100 /** @defgroup SRAM_Exported_Macros SRAM Exported Macros
 101  * @{
 102  */
 103
 104 /** @brief Reset SRAM handle state
 105   * @param  __HANDLE__: SRAM handle
 106   * @retval None
 107   */
 108 #define __HAL_SRAM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_SRAM_STATE_RESET)
 109
 110 /**
 111   * @}
 112   */
 113
 114 /* Exported functions --------------------------------------------------------*/
 115 /** @addtogroup SRAM_Exported_Functions SRAM Exported Functions
 116   * @{
 117   */
 118
 119 /** @addtogroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 120  * @{
 121  */
 122
 123 /* Initialization/de-initialization functions  ********************************/
 124 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming);
 125 HAL_StatusTypeDef HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram);
 126 void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram);
 127 void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram);
 128
 129 /**
 130   * @}
 131   */
 132
 133 /** @addtogroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
 134  * @{
 135  */
 136
 137 /* I/O operation functions  ***************************************************/
 138 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize);
 139 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize);
 140 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize);
 141 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize);
 142 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 143 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 144 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize);
 145 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize);
 146
 147 void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma);
 148 void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma);
 149
 150 /**
 151   * @}
 152   */
 153
 154 /** @addtogroup SRAM_Exported_Functions_Group3 Control functions
 155  * @{
 156  */
 157
 158 /* SRAM Control functions  ****************************************************/
 159 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram);
 160 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram);
 161
 162 /**
 163   * @}
 164   */
 165
 166 /** @addtogroup SRAM_Exported_Functions_Group4 Peripheral State functions
 167  * @{
 168  */
 169
 170 /* SRAM  State functions ******************************************************/
 171 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram);
 172
 173 /**
 174   * @}
 175   */
 176
 177 /**
 178   * @}
 179   */
 180
 181 /**
 182   * @}
 183   */
 184
 185 /**
 186   * @}
 187   */
 188
 189 #ifdef __cplusplus
 190 }
 191 #endif
 192
 193 #endif /* __STM32F7xx_HAL_SRAM_H */
 194
 195 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/