?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_hal_tim.h
blob467bc13d5f610101e6bcdb76a2c0c97b88a467c4
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_tim.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of TIM HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_HAL_TIM_H
40 #define __STM32F7xx_HAL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup TIM
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup TIM_Exported_Types TIM Exported Types
59 * @{
60 */
61
62 /**
63 * @brief TIM Time base Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
68 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
69
70 uint32_t CounterMode; /*!< Specifies the counter mode.
71 This parameter can be a value of @ref TIM_Counter_Mode */
72
73 uint32_t Period; /*!< Specifies the period value to be loaded into the active
74 Auto-Reload Register at the next update event.
75 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF. */
76
77 uint32_t ClockDivision; /*!< Specifies the clock division.
78 This parameter can be a value of @ref TIM_ClockDivision */
79
80 uint32_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR down-counter
81 reaches zero, an update event is generated and counting restarts
82 from the RCR value (N).
83 This means in PWM mode that (N+1) corresponds to:
84 - the number of PWM periods in edge-aligned mode
85 - the number of half PWM period in center-aligned mode
86 This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
87 @note This parameter is valid only for TIM1 and TIM8. */
88
89 uint32_t AutoReloadPreload; /*!< Specifies the auto-reload preload.
90 This parameter can be a value of @ref TIM_AutoReloadPreload */
91
92 } TIM_Base_InitTypeDef;
93
94 /**
95 * @brief TIM Output Compare Configuration Structure definition
96 */
97
98 typedef struct
99 {
100 uint32_t OCMode; /*!< Specifies the TIM mode.
101 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
102
103 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
104 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
105
106 uint32_t OCPolarity; /*!< Specifies the output polarity.
107 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
108
109 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
110 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
111 @note This parameter is valid only for TIM1 and TIM8. */
112
113 uint32_t OCFastMode; /*!< Specifies the Fast mode state.
114 This parameter can be a value of @ref TIM_Output_Fast_State
115 @note This parameter is valid only in PWM1 and PWM2 mode. */
116
117
118 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
119 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
120 @note This parameter is valid only for TIM1 and TIM8. */
121
122 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
123 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
124 @note This parameter is valid only for TIM1 and TIM8. */
125 } TIM_OC_InitTypeDef;
126
127 /**
128 * @brief TIM One Pulse Mode Configuration Structure definition
129 */
130 typedef struct
131 {
132 uint32_t OCMode; /*!< Specifies the TIM mode.
133 This parameter can be a value of @ref TIMEx_Output_Compare_and_PWM_modes */
134
135 uint32_t Pulse; /*!< Specifies the pulse value to be loaded into the Capture Compare Register.
136 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF */
137
138 uint32_t OCPolarity; /*!< Specifies the output polarity.
139 This parameter can be a value of @ref TIM_Output_Compare_Polarity */
140
141 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
142 This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
143 @note This parameter is valid only for TIM1 and TIM8. */
144
145 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
146 This parameter can be a value of @ref TIM_Output_Compare_Idle_State
147 @note This parameter is valid only for TIM1 and TIM8. */
148
149 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
150 This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
151 @note This parameter is valid only for TIM1 and TIM8. */
152
153 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
154 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
155
156 uint32_t ICSelection; /*!< Specifies the input.
157 This parameter can be a value of @ref TIM_Input_Capture_Selection */
158
159 uint32_t ICFilter; /*!< Specifies the input capture filter.
160 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
161 } TIM_OnePulse_InitTypeDef;
162
163
164 /**
165 * @brief TIM Input Capture Configuration Structure definition
166 */
167
168 typedef struct
169 {
170 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
171 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
172
173 uint32_t ICSelection; /*!< Specifies the input.
174 This parameter can be a value of @ref TIM_Input_Capture_Selection */
175
176 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
177 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
178
179 uint32_t ICFilter; /*!< Specifies the input capture filter.
180 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
181 } TIM_IC_InitTypeDef;
182
183 /**
184 * @brief TIM Encoder Configuration Structure definition
185 */
186
187 typedef struct
188 {
189 uint32_t EncoderMode; /*!< Specifies the active edge of the input signal.
190 This parameter can be a value of @ref TIM_Encoder_Mode */
191
192 uint32_t IC1Polarity; /*!< Specifies the active edge of the input signal.
193 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
194
195 uint32_t IC1Selection; /*!< Specifies the input.
196 This parameter can be a value of @ref TIM_Input_Capture_Selection */
197
198 uint32_t IC1Prescaler; /*!< Specifies the Input Capture Prescaler.
199 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
200
201 uint32_t IC1Filter; /*!< Specifies the input capture filter.
202 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
203
204 uint32_t IC2Polarity; /*!< Specifies the active edge of the input signal.
205 This parameter can be a value of @ref TIM_Input_Capture_Polarity */
206
207 uint32_t IC2Selection; /*!< Specifies the input.
208 This parameter can be a value of @ref TIM_Input_Capture_Selection */
209
210 uint32_t IC2Prescaler; /*!< Specifies the Input Capture Prescaler.
211 This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
212
213 uint32_t IC2Filter; /*!< Specifies the input capture filter.
214 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
215 } TIM_Encoder_InitTypeDef;
216
217 /**
218 * @brief Clock Configuration Handle Structure definition
219 */
220 typedef struct
221 {
222 uint32_t ClockSource; /*!< TIM clock sources.
223 This parameter can be a value of @ref TIM_Clock_Source */
224 uint32_t ClockPolarity; /*!< TIM clock polarity.
225 This parameter can be a value of @ref TIM_Clock_Polarity */
226 uint32_t ClockPrescaler; /*!< TIM clock prescaler.
227 This parameter can be a value of @ref TIM_Clock_Prescaler */
228 uint32_t ClockFilter; /*!< TIM clock filter.
229 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
230 }TIM_ClockConfigTypeDef;
231
232 /**
233 * @brief Clear Input Configuration Handle Structure definition
234 */
235 typedef struct
236 {
237 uint32_t ClearInputState; /*!< TIM clear Input state.
238 This parameter can be ENABLE or DISABLE */
239 uint32_t ClearInputSource; /*!< TIM clear Input sources.
240 This parameter can be a value of @ref TIMEx_ClearInput_Source */
241 uint32_t ClearInputPolarity; /*!< TIM Clear Input polarity.
242 This parameter can be a value of @ref TIM_ClearInput_Polarity */
243 uint32_t ClearInputPrescaler; /*!< TIM Clear Input prescaler.
244 This parameter can be a value of @ref TIM_ClearInput_Prescaler */
245 uint32_t ClearInputFilter; /*!< TIM Clear Input filter.
246 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
247 }TIM_ClearInputConfigTypeDef;
248
249 /**
250 * @brief TIM Slave configuration Structure definition
251 */
252 typedef struct {
253 uint32_t SlaveMode; /*!< Slave mode selection
254 This parameter can be a value of @ref TIMEx_Slave_Mode */
255 uint32_t InputTrigger; /*!< Input Trigger source
256 This parameter can be a value of @ref TIM_Trigger_Selection */
257 uint32_t TriggerPolarity; /*!< Input Trigger polarity
258 This parameter can be a value of @ref TIM_Trigger_Polarity */
259 uint32_t TriggerPrescaler; /*!< Input trigger prescaler
260 This parameter can be a value of @ref TIM_Trigger_Prescaler */
261 uint32_t TriggerFilter; /*!< Input trigger filter
262 This parameter can be a number between Min_Data = 0x0 and Max_Data = 0xF */
263
264 }TIM_SlaveConfigTypeDef;
265
266 /**
267 * @brief HAL State structures definition
268 */
269 typedef enum
270 {
271 HAL_TIM_STATE_RESET = 0x00U, /*!< Peripheral not yet initialized or disabled */
272 HAL_TIM_STATE_READY = 0x01U, /*!< Peripheral Initialized and ready for use */
273 HAL_TIM_STATE_BUSY = 0x02U, /*!< An internal process is ongoing */
274 HAL_TIM_STATE_TIMEOUT = 0x03U, /*!< Timeout state */
275 HAL_TIM_STATE_ERROR = 0x04U /*!< Reception process is ongoing */
276 }HAL_TIM_StateTypeDef;
277
278 /**
279 * @brief HAL Active channel structures definition
280 */
281 typedef enum
282 {
283 HAL_TIM_ACTIVE_CHANNEL_1 = 0x01U, /*!< The active channel is 1 */
284 HAL_TIM_ACTIVE_CHANNEL_2 = 0x02U, /*!< The active channel is 2 */
285 HAL_TIM_ACTIVE_CHANNEL_3 = 0x04U, /*!< The active channel is 3 */
286 HAL_TIM_ACTIVE_CHANNEL_4 = 0x08U, /*!< The active channel is 4 */
287 HAL_TIM_ACTIVE_CHANNEL_CLEARED = 0x00U /*!< All active channels cleared */
288 }HAL_TIM_ActiveChannel;
289
290 /**
291 * @brief TIM Time Base Handle Structure definition
292 */
293 typedef struct
294 {
295 TIM_TypeDef *Instance; /*!< Register base address */
296 TIM_Base_InitTypeDef Init; /*!< TIM Time Base required parameters */
297 HAL_TIM_ActiveChannel Channel; /*!< Active channel */
298 DMA_HandleTypeDef *hdma[7]; /*!< DMA Handlers array
299 This array is accessed by a @ref DMA_Handle_index */
300 HAL_LockTypeDef Lock; /*!< Locking object */
301 __IO HAL_TIM_StateTypeDef State; /*!< TIM operation state */
302 }TIM_HandleTypeDef;
303 /**
304 * @}
305 */
306
307 /* Exported constants --------------------------------------------------------*/
308 /** @defgroup TIM_Exported_Constants TIM Exported Constants
309 * @{
310 */
311
312 /** @defgroup TIM_Input_Channel_Polarity TIM Input Channel Polarity
313 * @{
314 */
315 #define TIM_INPUTCHANNELPOLARITY_RISING ((uint32_t)0x00000000U) /*!< Polarity for TIx source */
316 #define TIM_INPUTCHANNELPOLARITY_FALLING (TIM_CCER_CC1P) /*!< Polarity for TIx source */
317 #define TIM_INPUTCHANNELPOLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< Polarity for TIx source */
318 /**
319 * @}
320 */
321
322 /** @defgroup TIM_ETR_Polarity TIM ETR Polarity
323 * @{
324 */
325 #define TIM_ETRPOLARITY_INVERTED (TIM_SMCR_ETP) /*!< Polarity for ETR source */
326 #define TIM_ETRPOLARITY_NONINVERTED ((uint32_t)0x0000U) /*!< Polarity for ETR source */
327 /**
328 * @}
329 */
330
331 /** @defgroup TIM_ETR_Prescaler TIM ETR Prescaler
332 * @{
333 */
334 #define TIM_ETRPRESCALER_DIV1 ((uint32_t)0x0000U) /*!< No prescaler is used */
335 #define TIM_ETRPRESCALER_DIV2 (TIM_SMCR_ETPS_0) /*!< ETR input source is divided by 2 */
336 #define TIM_ETRPRESCALER_DIV4 (TIM_SMCR_ETPS_1) /*!< ETR input source is divided by 4 */
337 #define TIM_ETRPRESCALER_DIV8 (TIM_SMCR_ETPS) /*!< ETR input source is divided by 8 */
338 /**
339 * @}
340 */
341
342 /** @defgroup TIM_Counter_Mode TIM Counter Mode
343 * @{
344 */
345 #define TIM_COUNTERMODE_UP ((uint32_t)0x0000U)
346 #define TIM_COUNTERMODE_DOWN TIM_CR1_DIR
347 #define TIM_COUNTERMODE_CENTERALIGNED1 TIM_CR1_CMS_0
348 #define TIM_COUNTERMODE_CENTERALIGNED2 TIM_CR1_CMS_1
349 #define TIM_COUNTERMODE_CENTERALIGNED3 TIM_CR1_CMS
350 /**
351 * @}
352 */
353
354 /** @defgroup TIM_ClockDivision TIM Clock Division
355 * @{
356 */
357 #define TIM_CLOCKDIVISION_DIV1 ((uint32_t)0x0000U)
358 #define TIM_CLOCKDIVISION_DIV2 (TIM_CR1_CKD_0)
359 #define TIM_CLOCKDIVISION_DIV4 (TIM_CR1_CKD_1)
360 /**
361 * @}
362 */
363
364 /** @defgroup TIM_Output_Compare_State TIM Output Compare State
365 * @{
366 */
367 #define TIM_OUTPUTSTATE_DISABLE ((uint32_t)0x0000U)
368 #define TIM_OUTPUTSTATE_ENABLE (TIM_CCER_CC1E)
369
370 /**
371 * @}
372 */
373
374 /** @defgroup TIM_AutoReloadPreload TIM Auto-Reload Preload
375 * @{
376 */
377 #define TIM_AUTORELOAD_PRELOAD_DISABLE ((uint32_t)0x0000) /*!< TIMx_ARR register is not buffered */
378 #define TIM_AUTORELOAD_PRELOAD_ENABLE (TIM_CR1_ARPE) /*!< TIMx_ARR register is buffered */
379
380 /**
381 * @}
382 */
383
384 /** @defgroup TIM_Output_Fast_State TIM Output Fast State
385 * @{
386 */
387 #define TIM_OCFAST_DISABLE ((uint32_t)0x0000U)
388 #define TIM_OCFAST_ENABLE (TIM_CCMR1_OC1FE)
389 /**
390 * @}
391 */
392
393 /** @defgroup TIM_Output_Compare_N_State TIM Complementary Output Compare State
394 * @{
395 */
396 #define TIM_OUTPUTNSTATE_DISABLE ((uint32_t)0x0000U)
397 #define TIM_OUTPUTNSTATE_ENABLE (TIM_CCER_CC1NE)
398 /**
399 * @}
400 */
401
402 /** @defgroup TIM_Output_Compare_Polarity TIM Output Compare Polarity
403 * @{
404 */
405 #define TIM_OCPOLARITY_HIGH ((uint32_t)0x0000U)
406 #define TIM_OCPOLARITY_LOW (TIM_CCER_CC1P)
407 /**
408 * @}
409 */
410
411 /** @defgroup TIM_Output_Compare_N_Polarity TIM Complementary Output Compare Polarity
412 * @{
413 */
414 #define TIM_OCNPOLARITY_HIGH ((uint32_t)0x0000U)
415 #define TIM_OCNPOLARITY_LOW (TIM_CCER_CC1NP)
416 /**
417 * @}
418 */
419
420 /** @defgroup TIM_Output_Compare_Idle_State TIM Output Compare Idle State
421 * @{
422 */
423 #define TIM_OCIDLESTATE_SET (TIM_CR2_OIS1)
424 #define TIM_OCIDLESTATE_RESET ((uint32_t)0x0000U)
425 /**
426 * @}
427 */
428
429 /** @defgroup TIM_Output_Compare_N_Idle_State TIM Output Compare N Idle State
430 * @{
431 */
432 #define TIM_OCNIDLESTATE_SET (TIM_CR2_OIS1N)
433 #define TIM_OCNIDLESTATE_RESET ((uint32_t)0x0000U)
434 /**
435 * @}
436 */
437
438 /** @defgroup TIM_Input_Capture_Polarity TIM Input Capture Polarity
439 * @{
440 */
441 #define TIM_ICPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING
442 #define TIM_ICPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING
443 #define TIM_ICPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE
444 /**
445 * @}
446 */
447
448 /** @defgroup TIM_Input_Capture_Selection TIM Input Capture Selection
449 * @{
450 */
451 #define TIM_ICSELECTION_DIRECTTI (TIM_CCMR1_CC1S_0) /*!< TIM Input 1, 2, 3 or 4 is selected to be
452 connected to IC1, IC2, IC3 or IC4, respectively */
453 #define TIM_ICSELECTION_INDIRECTTI (TIM_CCMR1_CC1S_1) /*!< TIM Input 1, 2, 3 or 4 is selected to be
454 connected to IC2, IC1, IC4 or IC3, respectively */
455 #define TIM_ICSELECTION_TRC (TIM_CCMR1_CC1S) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC */
456
457 /**
458 * @}
459 */
460
461 /** @defgroup TIM_Input_Capture_Prescaler TIM Input Capture Prescaler
462 * @{
463 */
464 #define TIM_ICPSC_DIV1 ((uint32_t)0x0000U) /*!< Capture performed each time an edge is detected on the capture input */
465 #define TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0) /*!< Capture performed once every 2 events */
466 #define TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1) /*!< Capture performed once every 4 events */
467 #define TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC) /*!< Capture performed once every 8 events */
468 /**
469 * @}
470 */
471
472 /** @defgroup TIM_One_Pulse_Mode TIM One Pulse Mode
473 * @{
474 */
475 #define TIM_OPMODE_SINGLE (TIM_CR1_OPM)
476 #define TIM_OPMODE_REPETITIVE ((uint32_t)0x0000U)
477 /**
478 * @}
479 */
480
481 /** @defgroup TIM_Encoder_Mode TIM Encoder Mode
482 * @{
483 */
484 #define TIM_ENCODERMODE_TI1 (TIM_SMCR_SMS_0)
485 #define TIM_ENCODERMODE_TI2 (TIM_SMCR_SMS_1)
486 #define TIM_ENCODERMODE_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0)
487
488 /**
489 * @}
490 */
491
492 /** @defgroup TIM_Interrupt_definition TIM Interrupt definition
493 * @{
494 */
495 #define TIM_IT_UPDATE (TIM_DIER_UIE)
496 #define TIM_IT_CC1 (TIM_DIER_CC1IE)
497 #define TIM_IT_CC2 (TIM_DIER_CC2IE)
498 #define TIM_IT_CC3 (TIM_DIER_CC3IE)
499 #define TIM_IT_CC4 (TIM_DIER_CC4IE)
500 #define TIM_IT_COM (TIM_DIER_COMIE)
501 #define TIM_IT_TRIGGER (TIM_DIER_TIE)
502 #define TIM_IT_BREAK (TIM_DIER_BIE)
503 /**
504 * @}
505 */
506
507 /** @defgroup TIM_Commutation_Source TIM Commutation Source
508 * @{
509 */
510 #define TIM_COMMUTATION_TRGI (TIM_CR2_CCUS)
511 #define TIM_COMMUTATION_SOFTWARE ((uint32_t)0x0000U)
512 /**
513 * @}
514 */
515
516 /** @defgroup TIM_DMA_sources TIM DMA sources
517 * @{
518 */
519 #define TIM_DMA_UPDATE (TIM_DIER_UDE)
520 #define TIM_DMA_CC1 (TIM_DIER_CC1DE)
521 #define TIM_DMA_CC2 (TIM_DIER_CC2DE)
522 #define TIM_DMA_CC3 (TIM_DIER_CC3DE)
523 #define TIM_DMA_CC4 (TIM_DIER_CC4DE)
524 #define TIM_DMA_COM (TIM_DIER_COMDE)
525 #define TIM_DMA_TRIGGER (TIM_DIER_TDE)
526 /**
527 * @}
528 */
529
530 /** @defgroup TIM_Event_Source TIM Event Source
531 * @{
532 */
533 #define TIM_EVENTSOURCE_UPDATE TIM_EGR_UG
534 #define TIM_EVENTSOURCE_CC1 TIM_EGR_CC1G
535 #define TIM_EVENTSOURCE_CC2 TIM_EGR_CC2G
536 #define TIM_EVENTSOURCE_CC3 TIM_EGR_CC3G
537 #define TIM_EVENTSOURCE_CC4 TIM_EGR_CC4G
538 #define TIM_EVENTSOURCE_COM TIM_EGR_COMG
539 #define TIM_EVENTSOURCE_TRIGGER TIM_EGR_TG
540 #define TIM_EVENTSOURCE_BREAK TIM_EGR_BG
541 #define TIM_EVENTSOURCE_BREAK2 TIM_EGR_B2G
542 /**
543 * @}
544 */
545
546 /** @defgroup TIM_Flag_definition TIM Flag definition
547 * @{
548 */
549 #define TIM_FLAG_UPDATE (TIM_SR_UIF)
550 #define TIM_FLAG_CC1 (TIM_SR_CC1IF)
551 #define TIM_FLAG_CC2 (TIM_SR_CC2IF)
552 #define TIM_FLAG_CC3 (TIM_SR_CC3IF)
553 #define TIM_FLAG_CC4 (TIM_SR_CC4IF)
554 #define TIM_FLAG_COM (TIM_SR_COMIF)
555 #define TIM_FLAG_TRIGGER (TIM_SR_TIF)
556 #define TIM_FLAG_BREAK (TIM_SR_BIF)
557 #define TIM_FLAG_BREAK2 (TIM_SR_B2IF)
558 #define TIM_FLAG_CC1OF (TIM_SR_CC1OF)
559 #define TIM_FLAG_CC2OF (TIM_SR_CC2OF)
560 #define TIM_FLAG_CC3OF (TIM_SR_CC3OF)
561 #define TIM_FLAG_CC4OF (TIM_SR_CC4OF)
562 /**
563 * @}
564 */
565
566 /** @defgroup TIM_Clock_Source TIM Clock Source
567 * @{
568 */
569 #define TIM_CLOCKSOURCE_ETRMODE2 (TIM_SMCR_ETPS_1)
570 #define TIM_CLOCKSOURCE_INTERNAL (TIM_SMCR_ETPS_0)
571 #define TIM_CLOCKSOURCE_ITR0 ((uint32_t)0x0000U)
572 #define TIM_CLOCKSOURCE_ITR1 (TIM_SMCR_TS_0)
573 #define TIM_CLOCKSOURCE_ITR2 (TIM_SMCR_TS_1)
574 #define TIM_CLOCKSOURCE_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1)
575 #define TIM_CLOCKSOURCE_TI1ED (TIM_SMCR_TS_2)
576 #define TIM_CLOCKSOURCE_TI1 (TIM_SMCR_TS_0 | TIM_SMCR_TS_2)
577 #define TIM_CLOCKSOURCE_TI2 (TIM_SMCR_TS_1 | TIM_SMCR_TS_2)
578 #define TIM_CLOCKSOURCE_ETRMODE1 (TIM_SMCR_TS)
579 /**
580 * @}
581 */
582
583 /** @defgroup TIM_Clock_Polarity TIM Clock Polarity
584 * @{
585 */
586 #define TIM_CLOCKPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx clock sources */
587 #define TIM_CLOCKPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx clock sources */
588 #define TIM_CLOCKPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIx clock sources */
589 #define TIM_CLOCKPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIx clock sources */
590 #define TIM_CLOCKPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIx clock sources */
591 /**
592 * @}
593 */
594
595 /** @defgroup TIM_Clock_Prescaler TIM Clock Prescaler
596 * @{
597 */
598 #define TIM_CLOCKPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
599 #define TIM_CLOCKPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Clock: Capture performed once every 2 events. */
600 #define TIM_CLOCKPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Clock: Capture performed once every 4 events. */
601 #define TIM_CLOCKPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Clock: Capture performed once every 8 events. */
602 /**
603 * @}
604 */
605
606 /** @defgroup TIM_ClearInput_Polarity TIM Clear Input Polarity
607 * @{
608 */
609 #define TIM_CLEARINPUTPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx pin */
610 #define TIM_CLEARINPUTPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx pin */
611 /**
612 * @}
613 */
614
615 /** @defgroup TIM_ClearInput_Prescaler TIM Clear Input Prescaler
616 * @{
617 */
618 #define TIM_CLEARINPUTPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
619 #define TIM_CLEARINPUTPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR pin: Capture performed once every 2 events. */
620 #define TIM_CLEARINPUTPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR pin: Capture performed once every 4 events. */
621 #define TIM_CLEARINPUTPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR pin: Capture performed once every 8 events. */
622 /**
623 * @}
624 */
625
626 /** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state TIM OSSR OffState Selection for Run mode state
627 * @{
628 */
629 #define TIM_OSSR_ENABLE (TIM_BDTR_OSSR)
630 #define TIM_OSSR_DISABLE ((uint32_t)0x0000U)
631 /**
632 * @}
633 */
634
635 /** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state TIM OSSI OffState Selection for Idle mode state
636 * @{
637 */
638 #define TIM_OSSI_ENABLE (TIM_BDTR_OSSI)
639 #define TIM_OSSI_DISABLE ((uint32_t)0x0000U)
640 /**
641 * @}
642 */
643
644 /** @defgroup TIM_Lock_level TIM Lock level
645 * @{
646 */
647 #define TIM_LOCKLEVEL_OFF ((uint32_t)0x0000U)
648 #define TIM_LOCKLEVEL_1 (TIM_BDTR_LOCK_0)
649 #define TIM_LOCKLEVEL_2 (TIM_BDTR_LOCK_1)
650 #define TIM_LOCKLEVEL_3 (TIM_BDTR_LOCK)
651 /**
652 * @}
653 */
654 /** @defgroup TIM_Break_Input_enable_disable TIM Break Input State
655 * @{
656 */
657 #define TIM_BREAK_ENABLE (TIM_BDTR_BKE)
658 #define TIM_BREAK_DISABLE ((uint32_t)0x0000U)
659 /**
660 * @}
661 */
662
663 /** @defgroup TIM_Break_Polarity TIM Break Polarity
664 * @{
665 */
666 #define TIM_BREAKPOLARITY_LOW ((uint32_t)0x0000U)
667 #define TIM_BREAKPOLARITY_HIGH (TIM_BDTR_BKP)
668 /**
669 * @}
670 */
671
672 /** @defgroup TIM_AOE_Bit_Set_Reset TIM AOE Bit State
673 * @{
674 */
675 #define TIM_AUTOMATICOUTPUT_ENABLE (TIM_BDTR_AOE)
676 #define TIM_AUTOMATICOUTPUT_DISABLE ((uint32_t)0x0000U)
677 /**
678 * @}
679 */
680
681 /** @defgroup TIM_Master_Mode_Selection TIM Master Mode Selection
682 * @{
683 */
684 #define TIM_TRGO_RESET ((uint32_t)0x0000U)
685 #define TIM_TRGO_ENABLE (TIM_CR2_MMS_0)
686 #define TIM_TRGO_UPDATE (TIM_CR2_MMS_1)
687 #define TIM_TRGO_OC1 ((TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
688 #define TIM_TRGO_OC1REF (TIM_CR2_MMS_2)
689 #define TIM_TRGO_OC2REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_0))
690 #define TIM_TRGO_OC3REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1))
691 #define TIM_TRGO_OC4REF ((TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0))
692 /**
693 * @}
694 */
695
696 /** @defgroup TIM_Master_Slave_Mode TIM Master Slave Mode
697 * @{
698 */
699 #define TIM_MASTERSLAVEMODE_ENABLE ((uint32_t)0x0080)
700 #define TIM_MASTERSLAVEMODE_DISABLE ((uint32_t)0x0000U)
701 /**
702 * @}
703 */
704
705 /** @defgroup TIM_Trigger_Selection TIM Trigger Selection
706 * @{
707 */
708 #define TIM_TS_ITR0 ((uint32_t)0x0000U)
709 #define TIM_TS_ITR1 ((uint32_t)0x0010U)
710 #define TIM_TS_ITR2 ((uint32_t)0x0020U)
711 #define TIM_TS_ITR3 ((uint32_t)0x0030U)
712 #define TIM_TS_TI1F_ED ((uint32_t)0x0040U)
713 #define TIM_TS_TI1FP1 ((uint32_t)0x0050U)
714 #define TIM_TS_TI2FP2 ((uint32_t)0x0060U)
715 #define TIM_TS_ETRF ((uint32_t)0x0070U)
716 #define TIM_TS_NONE ((uint32_t)0xFFFFU)
717 /**
718 * @}
719 */
720
721 /** @defgroup TIM_Trigger_Polarity TIM Trigger Polarity
722 * @{
723 */
724 #define TIM_TRIGGERPOLARITY_INVERTED TIM_ETRPOLARITY_INVERTED /*!< Polarity for ETRx trigger sources */
725 #define TIM_TRIGGERPOLARITY_NONINVERTED TIM_ETRPOLARITY_NONINVERTED /*!< Polarity for ETRx trigger sources */
726 #define TIM_TRIGGERPOLARITY_RISING TIM_INPUTCHANNELPOLARITY_RISING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
727 #define TIM_TRIGGERPOLARITY_FALLING TIM_INPUTCHANNELPOLARITY_FALLING /*!< Polarity for TIxFPx or TI1_ED trigger sources */
728 #define TIM_TRIGGERPOLARITY_BOTHEDGE TIM_INPUTCHANNELPOLARITY_BOTHEDGE /*!< Polarity for TIxFPx or TI1_ED trigger sources */
729 /**
730 * @}
731 */
732
733 /** @defgroup TIM_Trigger_Prescaler TIM Trigger Prescaler
734 * @{
735 */
736 #define TIM_TRIGGERPRESCALER_DIV1 TIM_ETRPRESCALER_DIV1 /*!< No prescaler is used */
737 #define TIM_TRIGGERPRESCALER_DIV2 TIM_ETRPRESCALER_DIV2 /*!< Prescaler for External ETR Trigger: Capture performed once every 2 events. */
738 #define TIM_TRIGGERPRESCALER_DIV4 TIM_ETRPRESCALER_DIV4 /*!< Prescaler for External ETR Trigger: Capture performed once every 4 events. */
739 #define TIM_TRIGGERPRESCALER_DIV8 TIM_ETRPRESCALER_DIV8 /*!< Prescaler for External ETR Trigger: Capture performed once every 8 events. */
740 /**
741 * @}
742 */
743
744
745 /** @defgroup TIM_TI1_Selection TIM TI1 Selection
746 * @{
747 */
748 #define TIM_TI1SELECTION_CH1 ((uint32_t)0x0000U)
749 #define TIM_TI1SELECTION_XORCOMBINATION (TIM_CR2_TI1S)
750 /**
751 * @}
752 */
753
754 /** @defgroup TIM_DMA_Base_address TIM DMA Base address
755 * @{
756 */
757 #define TIM_DMABASE_CR1 (0x00000000U)
758 #define TIM_DMABASE_CR2 (0x00000001U)
759 #define TIM_DMABASE_SMCR (0x00000002U)
760 #define TIM_DMABASE_DIER (0x00000003U)
761 #define TIM_DMABASE_SR (0x00000004U)
762 #define TIM_DMABASE_EGR (0x00000005U)
763 #define TIM_DMABASE_CCMR1 (0x00000006U)
764 #define TIM_DMABASE_CCMR2 (0x00000007U)
765 #define TIM_DMABASE_CCER (0x00000008U)
766 #define TIM_DMABASE_CNT (0x00000009U)
767 #define TIM_DMABASE_PSC (0x0000000AU)
768 #define TIM_DMABASE_ARR (0x0000000BU)
769 #define TIM_DMABASE_RCR (0x0000000CU)
770 #define TIM_DMABASE_CCR1 (0x0000000DU)
771 #define TIM_DMABASE_CCR2 (0x0000000EU)
772 #define TIM_DMABASE_CCR3 (0x0000000FU)
773 #define TIM_DMABASE_CCR4 (0x00000010U)
774 #define TIM_DMABASE_BDTR (0x00000011U)
775 #define TIM_DMABASE_DCR (0x00000012U)
776 #define TIM_DMABASE_OR (0x00000013U)
777 /**
778 * @}
779 */
780
781 /** @defgroup TIM_DMA_Burst_Length TIM DMA Burst Length
782 * @{
783 */
784 #define TIM_DMABURSTLENGTH_1TRANSFER (0x00000000U)
785 #define TIM_DMABURSTLENGTH_2TRANSFERS (0x00000100U)
786 #define TIM_DMABURSTLENGTH_3TRANSFERS (0x00000200U)
787 #define TIM_DMABURSTLENGTH_4TRANSFERS (0x00000300U)
788 #define TIM_DMABURSTLENGTH_5TRANSFERS (0x00000400U)
789 #define TIM_DMABURSTLENGTH_6TRANSFERS (0x00000500U)
790 #define TIM_DMABURSTLENGTH_7TRANSFERS (0x00000600U)
791 #define TIM_DMABURSTLENGTH_8TRANSFERS (0x00000700U)
792 #define TIM_DMABURSTLENGTH_9TRANSFERS (0x00000800U)
793 #define TIM_DMABURSTLENGTH_10TRANSFERS (0x00000900U)
794 #define TIM_DMABURSTLENGTH_11TRANSFERS (0x00000A00U)
795 #define TIM_DMABURSTLENGTH_12TRANSFERS (0x00000B00U)
796 #define TIM_DMABURSTLENGTH_13TRANSFERS (0x00000C00U)
797 #define TIM_DMABURSTLENGTH_14TRANSFERS (0x00000D00U)
798 #define TIM_DMABURSTLENGTH_15TRANSFERS (0x00000E00U)
799 #define TIM_DMABURSTLENGTH_16TRANSFERS (0x00000F00U)
800 #define TIM_DMABURSTLENGTH_17TRANSFERS (0x00001000U)
801 #define TIM_DMABURSTLENGTH_18TRANSFERS (0x00001100U)
802 /**
803 * @}
804 */
805
806 /** @defgroup DMA_Handle_index DMA Handle index
807 * @{
808 */
809 #define TIM_DMA_ID_UPDATE ((uint16_t) 0x0U) /*!< Index of the DMA handle used for Update DMA requests */
810 #define TIM_DMA_ID_CC1 ((uint16_t) 0x1U) /*!< Index of the DMA handle used for Capture/Compare 1 DMA requests */
811 #define TIM_DMA_ID_CC2 ((uint16_t) 0x2U) /*!< Index of the DMA handle used for Capture/Compare 2 DMA requests */
812 #define TIM_DMA_ID_CC3 ((uint16_t) 0x3U) /*!< Index of the DMA handle used for Capture/Compare 3 DMA requests */
813 #define TIM_DMA_ID_CC4 ((uint16_t) 0x4U) /*!< Index of the DMA handle used for Capture/Compare 4 DMA requests */
814 #define TIM_DMA_ID_COMMUTATION ((uint16_t) 0x5U) /*!< Index of the DMA handle used for Commutation DMA requests */
815 #define TIM_DMA_ID_TRIGGER ((uint16_t) 0x6U) /*!< Index of the DMA handle used for Trigger DMA requests */
816 /**
817 * @}
818 */
819
820 /** @defgroup Channel_CC_State Channel CC State
821 * @{
822 */
823 #define TIM_CCx_ENABLE ((uint32_t)0x0001U)
824 #define TIM_CCx_DISABLE ((uint32_t)0x0000U)
825 #define TIM_CCxN_ENABLE ((uint32_t)0x0004U)
826 #define TIM_CCxN_DISABLE ((uint32_t)0x0000U)
827 /**
828 * @}
829 */
830
831 /**
832 * @}
833 */
834
835 /* Exported macro ------------------------------------------------------------*/
836 /** @defgroup TIM_Exported_Macros TIM Exported Macros
837 * @{
838 */
839 /** @brief Reset TIM handle state
840 * @param __HANDLE__: TIM handle
841 * @retval None
842 */
843 #define __HAL_TIM_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_TIM_STATE_RESET)
844
845 /**
846 * @brief Enable the TIM peripheral.
847 * @param __HANDLE__: TIM handle
848 * @retval None
849 */
850 #define __HAL_TIM_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_CEN))
851
852 /**
853 * @brief Enable the TIM update source request.
854 * @param __HANDLE__: TIM handle
855 * @retval None
856 */
857 #define __HAL_TIM_URS_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1|=(TIM_CR1_URS))
858
859 /**
860 * @brief Enable the TIM main Output.
861 * @param __HANDLE__: TIM handle
862 * @retval None
863 */
864 #define __HAL_TIM_MOE_ENABLE(__HANDLE__) ((__HANDLE__)->Instance->BDTR|=(TIM_BDTR_MOE))
865
866
867 /* The counter of a timer instance is disabled only if all the CCx and CCxN
868 channels have been disabled */
869 #define TIM_CCER_CCxE_MASK ((uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E | TIM_CCER_CC3E | TIM_CCER_CC4E))
870 #define TIM_CCER_CCxNE_MASK ((uint32_t)(TIM_CCER_CC1NE | TIM_CCER_CC2NE | TIM_CCER_CC3NE))
871
872 /**
873 * @brief Disable the TIM peripheral.
874 * @param __HANDLE__: TIM handle
875 * @retval None
876 */
877 #define __HAL_TIM_DISABLE(__HANDLE__) \
878 do { \
879 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
880 { \
881 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
882 { \
883 (__HANDLE__)->Instance->CR1 &= ~(TIM_CR1_CEN); \
884 } \
885 } \
886 } while(0)
887
888 /**
889 * @brief Disable the TIM update source request.
890 * @param __HANDLE__: TIM handle
891 * @retval None
892 */
893 #define __HAL_TIM_URS_DISABLE(__HANDLE__) ((__HANDLE__)->Instance->CR1&=~(TIM_CR1_URS))
894
895
896 /* The Main Output of a timer instance is disabled only if all the CCx and CCxN
897 channels have been disabled */
898 /**
899 * @brief Disable the TIM main Output.
900 * @param __HANDLE__: TIM handle
901 * @retval None
902 */
903 #define __HAL_TIM_MOE_DISABLE(__HANDLE__) \
904 do { \
905 if (((__HANDLE__)->Instance->CCER & TIM_CCER_CCxE_MASK) == 0) \
906 { \
907 if(((__HANDLE__)->Instance->CCER & TIM_CCER_CCxNE_MASK) == 0) \
908 { \
909 (__HANDLE__)->Instance->BDTR &= ~(TIM_BDTR_MOE); \
910 } \
911 } \
912 } while(0)
913
914 #define __HAL_TIM_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER |= (__INTERRUPT__))
915 #define __HAL_TIM_ENABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER |= (__DMA__))
916 #define __HAL_TIM_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DIER &= ~(__INTERRUPT__))
917 #define __HAL_TIM_DISABLE_DMA(__HANDLE__, __DMA__) ((__HANDLE__)->Instance->DIER &= ~(__DMA__))
918 #define __HAL_TIM_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->SR &(__FLAG__)) == (__FLAG__))
919 #define __HAL_TIM_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->SR = ~(__FLAG__))
920
921 #define __HAL_TIM_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) ((((__HANDLE__)->Instance->DIER & (__INTERRUPT__)) == (__INTERRUPT__)) ? SET : RESET)
922 #define __HAL_TIM_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->SR = ~(__INTERRUPT__))
923
924 #define __HAL_TIM_IS_TIM_COUNTING_DOWN(__HANDLE__) (((__HANDLE__)->Instance->CR1 &(TIM_CR1_DIR)) == (TIM_CR1_DIR))
925 #define __HAL_TIM_SET_PRESCALER (__HANDLE__, __PRESC__) ((__HANDLE__)->Instance->PSC = (__PRESC__))
926
927 #define TIM_SET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__, __ICPSC__) \
928 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 |= (__ICPSC__)) :\
929 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 |= ((__ICPSC__) << 8)) :\
930 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 |= (__ICPSC__)) :\
931 ((__HANDLE__)->Instance->CCMR2 |= ((__ICPSC__) << 8)))
932
933 #define TIM_RESET_ICPRESCALERVALUE(__HANDLE__, __CHANNEL__) \
934 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC) :\
935 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC) :\
936 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC) :\
937 ((__HANDLE__)->Instance->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC))
938
939 #define TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
940 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER |= (__POLARITY__)) :\
941 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 4)) :\
942 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER |= ((__POLARITY__) << 8)) :\
943 ((__HANDLE__)->Instance->CCER |= (((__POLARITY__) << 12) & TIM_CCER_CC4P)))
944
945 #define TIM_RESET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__) \
946 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP)) :\
947 ((__CHANNEL__) == TIM_CHANNEL_2) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP)) :\
948 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCER &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP)) :\
949 ((__HANDLE__)->Instance->CCER &= (uint16_t)~TIM_CCER_CC4P))
950
951 /**
952 * @brief Sets the TIM Counter Register value on runtime.
953 * @param __HANDLE__: TIM handle.
954 * @param __COUNTER__: specifies the Counter register new value.
955 * @retval None
956 */
957 #define __HAL_TIM_SET_COUNTER(__HANDLE__, __COUNTER__) ((__HANDLE__)->Instance->CNT = (__COUNTER__))
958
959 /**
960 * @brief Gets the TIM Counter Register value on runtime.
961 * @param __HANDLE__: TIM handle.
962 * @retval None
963 */
964 #define __HAL_TIM_GET_COUNTER(__HANDLE__) ((__HANDLE__)->Instance->CNT)
965
966 /**
967 * @brief Sets the TIM Autoreload Register value on runtime without calling
968 * another time any Init function.
969 * @param __HANDLE__: TIM handle.
970 * @param __AUTORELOAD__: specifies the Counter register new value.
971 * @retval None
972 */
973 #define __HAL_TIM_SET_AUTORELOAD(__HANDLE__, __AUTORELOAD__) \
974 do{ \
975 (__HANDLE__)->Instance->ARR = (__AUTORELOAD__); \
976 (__HANDLE__)->Init.Period = (__AUTORELOAD__); \
977 } while(0)
978 /**
979 * @brief Gets the TIM Autoreload Register value on runtime
980 * @param __HANDLE__: TIM handle.
981 * @retval None
982 */
983 #define __HAL_TIM_GET_AUTORELOAD(__HANDLE__) ((__HANDLE__)->Instance->ARR)
984
985 /**
986 * @brief Sets the TIM Clock Division value on runtime without calling
987 * another time any Init function.
988 * @param __HANDLE__: TIM handle.
989 * @param __CKD__: specifies the clock division value.
990 * This parameter can be one of the following value:
991 * @arg TIM_CLOCKDIVISION_DIV1
992 * @arg TIM_CLOCKDIVISION_DIV2
993 * @arg TIM_CLOCKDIVISION_DIV4
994 * @retval None
995 */
996 #define __HAL_TIM_SET_CLOCKDIVISION(__HANDLE__, __CKD__) \
997 do{ \
998 (__HANDLE__)->Instance->CR1 &= (uint16_t)(~TIM_CR1_CKD); \
999 (__HANDLE__)->Instance->CR1 |= (__CKD__); \
1000 (__HANDLE__)->Init.ClockDivision = (__CKD__); \
1001 } while(0)
1002 /**
1003 * @brief Gets the TIM Clock Division value on runtime
1004 * @param __HANDLE__: TIM handle.
1005 * @retval None
1006 */
1007 #define __HAL_TIM_GET_CLOCKDIVISION(__HANDLE__) ((__HANDLE__)->Instance->CR1 & TIM_CR1_CKD)
1008
1009 /**
1010 * @brief Sets the TIM Input Capture prescaler on runtime without calling
1011 * another time HAL_TIM_IC_ConfigChannel() function.
1012 * @param __HANDLE__: TIM handle.
1013 * @param __CHANNEL__ : TIM Channels to be configured.
1014 * This parameter can be one of the following values:
1015 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1016 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1017 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1018 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1019 * @param __ICPSC__: specifies the Input Capture4 prescaler new value.
1020 * This parameter can be one of the following values:
1021 * @arg TIM_ICPSC_DIV1: no prescaler
1022 * @arg TIM_ICPSC_DIV2: capture is done once every 2 events
1023 * @arg TIM_ICPSC_DIV4: capture is done once every 4 events
1024 * @arg TIM_ICPSC_DIV8: capture is done once every 8 events
1025 * @retval None
1026 */
1027 #define __HAL_TIM_SET_ICPRESCALER(__HANDLE__, __CHANNEL__, __ICPSC__) \
1028 do{ \
1029 TIM_RESET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__)); \
1030 TIM_SET_ICPRESCALERVALUE((__HANDLE__), (__CHANNEL__), (__ICPSC__)); \
1031 } while(0)
1032
1033 /**
1034 * @brief Gets the TIM Input Capture prescaler on runtime
1035 * @param __HANDLE__: TIM handle.
1036 * @param __CHANNEL__ : TIM Channels to be configured.
1037 * This parameter can be one of the following values:
1038 * @arg TIM_CHANNEL_1: get input capture 1 prescaler value
1039 * @arg TIM_CHANNEL_2: get input capture 2 prescaler value
1040 * @arg TIM_CHANNEL_3: get input capture 3 prescaler value
1041 * @arg TIM_CHANNEL_4: get input capture 4 prescaler value
1042 * @retval None
1043 */
1044 #define __HAL_TIM_GET_ICPRESCALER(__HANDLE__, __CHANNEL__) \
1045 (((__CHANNEL__) == TIM_CHANNEL_1) ? ((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC1PSC) :\
1046 ((__CHANNEL__) == TIM_CHANNEL_2) ? (((__HANDLE__)->Instance->CCMR1 & TIM_CCMR1_IC2PSC) >> 8) :\
1047 ((__CHANNEL__) == TIM_CHANNEL_3) ? ((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC3PSC) :\
1048 (((__HANDLE__)->Instance->CCMR2 & TIM_CCMR2_IC4PSC)) >> 8)
1049
1050 /**
1051 * @brief Sets the TIM Capture x input polarity on runtime.
1052 * @param __HANDLE__: TIM handle.
1053 * @param __CHANNEL__: TIM Channels to be configured.
1054 * This parameter can be one of the following values:
1055 * @arg TIM_CHANNEL_1: TIM Channel 1 selected
1056 * @arg TIM_CHANNEL_2: TIM Channel 2 selected
1057 * @arg TIM_CHANNEL_3: TIM Channel 3 selected
1058 * @arg TIM_CHANNEL_4: TIM Channel 4 selected
1059 * @param __POLARITY__: Polarity for TIx source
1060 * @arg TIM_INPUTCHANNELPOLARITY_RISING: Rising Edge
1061 * @arg TIM_INPUTCHANNELPOLARITY_FALLING: Falling Edge
1062 * @arg TIM_INPUTCHANNELPOLARITY_BOTHEDGE: Rising and Falling Edge
1063 * @note The polarity TIM_INPUTCHANNELPOLARITY_BOTHEDGE is not authorized for TIM Channel 4.
1064 * @retval None
1065 */
1066 #define __HAL_TIM_SET_CAPTUREPOLARITY(__HANDLE__, __CHANNEL__, __POLARITY__) \
1067 do{ \
1068 TIM_RESET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__)); \
1069 TIM_SET_CAPTUREPOLARITY((__HANDLE__), (__CHANNEL__), (__POLARITY__)); \
1070 }while(0)
1071
1072 /**
1073 * @}
1074 */
1075
1076 /* Include TIM HAL Extension module */
1077 #include "stm32f7xx_hal_tim_ex.h"
1078
1079 /* Exported functions --------------------------------------------------------*/
1080 /** @addtogroup TIM_Exported_Functions
1081 * @{
1082 */
1083
1084 /** @addtogroup TIM_Exported_Functions_Group1
1085 * @{
1086 */
1087
1088 /* Time Base functions ********************************************************/
1089 HAL_StatusTypeDef HAL_TIM_Base_Init(TIM_HandleTypeDef *htim);
1090 HAL_StatusTypeDef HAL_TIM_Base_DeInit(TIM_HandleTypeDef *htim);
1091 void HAL_TIM_Base_MspInit(TIM_HandleTypeDef *htim);
1092 void HAL_TIM_Base_MspDeInit(TIM_HandleTypeDef *htim);
1093 /* Blocking mode: Polling */
1094 HAL_StatusTypeDef HAL_TIM_Base_Start(TIM_HandleTypeDef *htim);
1095 HAL_StatusTypeDef HAL_TIM_Base_Stop(TIM_HandleTypeDef *htim);
1096 /* Non-Blocking mode: Interrupt */
1097 HAL_StatusTypeDef HAL_TIM_Base_Start_IT(TIM_HandleTypeDef *htim);
1098 HAL_StatusTypeDef HAL_TIM_Base_Stop_IT(TIM_HandleTypeDef *htim);
1099 /* Non-Blocking mode: DMA */
1100 HAL_StatusTypeDef HAL_TIM_Base_Start_DMA(TIM_HandleTypeDef *htim, uint32_t *pData, uint16_t Length);
1101 HAL_StatusTypeDef HAL_TIM_Base_Stop_DMA(TIM_HandleTypeDef *htim);
1102 /**
1103 * @}
1104 */
1105
1106 /** @addtogroup TIM_Exported_Functions_Group2
1107 * @{
1108 */
1109 /* Timer Output Compare functions **********************************************/
1110 HAL_StatusTypeDef HAL_TIM_OC_Init(TIM_HandleTypeDef *htim);
1111 HAL_StatusTypeDef HAL_TIM_OC_DeInit(TIM_HandleTypeDef *htim);
1112 void HAL_TIM_OC_MspInit(TIM_HandleTypeDef *htim);
1113 void HAL_TIM_OC_MspDeInit(TIM_HandleTypeDef *htim);
1114 /* Blocking mode: Polling */
1115 HAL_StatusTypeDef HAL_TIM_OC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1116 HAL_StatusTypeDef HAL_TIM_OC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1117 /* Non-Blocking mode: Interrupt */
1118 HAL_StatusTypeDef HAL_TIM_OC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1119 HAL_StatusTypeDef HAL_TIM_OC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1120 /* Non-Blocking mode: DMA */
1121 HAL_StatusTypeDef HAL_TIM_OC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1122 HAL_StatusTypeDef HAL_TIM_OC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1123
1124 /**
1125 * @}
1126 */
1127
1128 /** @addtogroup TIM_Exported_Functions_Group3
1129 * @{
1130 */
1131 /* Timer PWM functions *********************************************************/
1132 HAL_StatusTypeDef HAL_TIM_PWM_Init(TIM_HandleTypeDef *htim);
1133 HAL_StatusTypeDef HAL_TIM_PWM_DeInit(TIM_HandleTypeDef *htim);
1134 void HAL_TIM_PWM_MspInit(TIM_HandleTypeDef *htim);
1135 void HAL_TIM_PWM_MspDeInit(TIM_HandleTypeDef *htim);
1136 /* Blocking mode: Polling */
1137 HAL_StatusTypeDef HAL_TIM_PWM_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1138 HAL_StatusTypeDef HAL_TIM_PWM_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1139 /* Non-Blocking mode: Interrupt */
1140 HAL_StatusTypeDef HAL_TIM_PWM_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1141 HAL_StatusTypeDef HAL_TIM_PWM_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1142 /* Non-Blocking mode: DMA */
1143 HAL_StatusTypeDef HAL_TIM_PWM_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1144 HAL_StatusTypeDef HAL_TIM_PWM_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1145
1146 /**
1147 * @}
1148 */
1149
1150 /** @addtogroup TIM_Exported_Functions_Group4
1151 * @{
1152 */
1153 /* Timer Input Capture functions ***********************************************/
1154 HAL_StatusTypeDef HAL_TIM_IC_Init(TIM_HandleTypeDef *htim);
1155 HAL_StatusTypeDef HAL_TIM_IC_DeInit(TIM_HandleTypeDef *htim);
1156 void HAL_TIM_IC_MspInit(TIM_HandleTypeDef *htim);
1157 void HAL_TIM_IC_MspDeInit(TIM_HandleTypeDef *htim);
1158 /* Blocking mode: Polling */
1159 HAL_StatusTypeDef HAL_TIM_IC_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1160 HAL_StatusTypeDef HAL_TIM_IC_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1161 /* Non-Blocking mode: Interrupt */
1162 HAL_StatusTypeDef HAL_TIM_IC_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1163 HAL_StatusTypeDef HAL_TIM_IC_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1164 /* Non-Blocking mode: DMA */
1165 HAL_StatusTypeDef HAL_TIM_IC_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData, uint16_t Length);
1166 HAL_StatusTypeDef HAL_TIM_IC_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1167
1168 /**
1169 * @}
1170 */
1171
1172 /** @addtogroup TIM_Exported_Functions_Group5
1173 * @{
1174 */
1175 /* Timer One Pulse functions ***************************************************/
1176 HAL_StatusTypeDef HAL_TIM_OnePulse_Init(TIM_HandleTypeDef *htim, uint32_t OnePulseMode);
1177 HAL_StatusTypeDef HAL_TIM_OnePulse_DeInit(TIM_HandleTypeDef *htim);
1178 void HAL_TIM_OnePulse_MspInit(TIM_HandleTypeDef *htim);
1179 void HAL_TIM_OnePulse_MspDeInit(TIM_HandleTypeDef *htim);
1180 /* Blocking mode: Polling */
1181 HAL_StatusTypeDef HAL_TIM_OnePulse_Start(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1182 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1183
1184 /* Non-Blocking mode: Interrupt */
1185 HAL_StatusTypeDef HAL_TIM_OnePulse_Start_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1186 HAL_StatusTypeDef HAL_TIM_OnePulse_Stop_IT(TIM_HandleTypeDef *htim, uint32_t OutputChannel);
1187
1188 /**
1189 * @}
1190 */
1191
1192 /** @addtogroup TIM_Exported_Functions_Group6
1193 * @{
1194 */
1195 /* Timer Encoder functions *****************************************************/
1196 HAL_StatusTypeDef HAL_TIM_Encoder_Init(TIM_HandleTypeDef *htim, TIM_Encoder_InitTypeDef* sConfig);
1197 HAL_StatusTypeDef HAL_TIM_Encoder_DeInit(TIM_HandleTypeDef *htim);
1198 void HAL_TIM_Encoder_MspInit(TIM_HandleTypeDef *htim);
1199 void HAL_TIM_Encoder_MspDeInit(TIM_HandleTypeDef *htim);
1200 /* Blocking mode: Polling */
1201 HAL_StatusTypeDef HAL_TIM_Encoder_Start(TIM_HandleTypeDef *htim, uint32_t Channel);
1202 HAL_StatusTypeDef HAL_TIM_Encoder_Stop(TIM_HandleTypeDef *htim, uint32_t Channel);
1203 /* Non-Blocking mode: Interrupt */
1204 HAL_StatusTypeDef HAL_TIM_Encoder_Start_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1205 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_IT(TIM_HandleTypeDef *htim, uint32_t Channel);
1206 /* Non-Blocking mode: DMA */
1207 HAL_StatusTypeDef HAL_TIM_Encoder_Start_DMA(TIM_HandleTypeDef *htim, uint32_t Channel, uint32_t *pData1, uint32_t *pData2, uint16_t Length);
1208 HAL_StatusTypeDef HAL_TIM_Encoder_Stop_DMA(TIM_HandleTypeDef *htim, uint32_t Channel);
1209
1210 /**
1211 * @}
1212 */
1213
1214 /** @addtogroup TIM_Exported_Functions_Group7
1215 * @{
1216 */
1217 /* Interrupt Handler functions **********************************************/
1218 void HAL_TIM_IRQHandler(TIM_HandleTypeDef *htim);
1219
1220 /**
1221 * @}
1222 */
1223
1224 /** @addtogroup TIM_Exported_Functions_Group8
1225 * @{
1226 */
1227 /* Control functions *********************************************************/
1228 HAL_StatusTypeDef HAL_TIM_OC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1229 HAL_StatusTypeDef HAL_TIM_PWM_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OC_InitTypeDef* sConfig, uint32_t Channel);
1230 HAL_StatusTypeDef HAL_TIM_IC_ConfigChannel(TIM_HandleTypeDef *htim, TIM_IC_InitTypeDef* sConfig, uint32_t Channel);
1231 HAL_StatusTypeDef HAL_TIM_OnePulse_ConfigChannel(TIM_HandleTypeDef *htim, TIM_OnePulse_InitTypeDef* sConfig, uint32_t OutputChannel, uint32_t InputChannel);
1232 HAL_StatusTypeDef HAL_TIM_ConfigOCrefClear(TIM_HandleTypeDef *htim, TIM_ClearInputConfigTypeDef * sClearInputConfig, uint32_t Channel);
1233 HAL_StatusTypeDef HAL_TIM_ConfigClockSource(TIM_HandleTypeDef *htim, TIM_ClockConfigTypeDef * sClockSourceConfig);
1234 HAL_StatusTypeDef HAL_TIM_ConfigTI1Input(TIM_HandleTypeDef *htim, uint32_t TI1_Selection);
1235 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1236 HAL_StatusTypeDef HAL_TIM_SlaveConfigSynchronization_IT(TIM_HandleTypeDef *htim, TIM_SlaveConfigTypeDef * sSlaveConfig);
1237 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1238 uint32_t *BurstBuffer, uint32_t BurstLength);
1239 HAL_StatusTypeDef HAL_TIM_DMABurst_WriteStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1240 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStart(TIM_HandleTypeDef *htim, uint32_t BurstBaseAddress, uint32_t BurstRequestSrc, \
1241 uint32_t *BurstBuffer, uint32_t BurstLength);
1242 HAL_StatusTypeDef HAL_TIM_DMABurst_ReadStop(TIM_HandleTypeDef *htim, uint32_t BurstRequestSrc);
1243 HAL_StatusTypeDef HAL_TIM_GenerateEvent(TIM_HandleTypeDef *htim, uint32_t EventSource);
1244 uint32_t HAL_TIM_ReadCapturedValue(TIM_HandleTypeDef *htim, uint32_t Channel);
1245
1246 /**
1247 * @}
1248 */
1249
1250 /** @addtogroup TIM_Exported_Functions_Group9
1251 * @{
1252 */
1253 /* Callback in non blocking modes (Interrupt and DMA) *************************/
1254 void HAL_TIM_PeriodElapsedCallback(TIM_HandleTypeDef *htim);
1255 void HAL_TIM_OC_DelayElapsedCallback(TIM_HandleTypeDef *htim);
1256 void HAL_TIM_IC_CaptureCallback(TIM_HandleTypeDef *htim);
1257 void HAL_TIM_PWM_PulseFinishedCallback(TIM_HandleTypeDef *htim);
1258 void HAL_TIM_TriggerCallback(TIM_HandleTypeDef *htim);
1259 void HAL_TIM_ErrorCallback(TIM_HandleTypeDef *htim);
1260
1261 /**
1262 * @}
1263 */
1264
1265 /** @addtogroup TIM_Exported_Functions_Group10
1266 * @{
1267 */
1268 /* Peripheral State functions **************************************************/
1269 HAL_TIM_StateTypeDef HAL_TIM_Base_GetState(TIM_HandleTypeDef *htim);
1270 HAL_TIM_StateTypeDef HAL_TIM_OC_GetState(TIM_HandleTypeDef *htim);
1271 HAL_TIM_StateTypeDef HAL_TIM_PWM_GetState(TIM_HandleTypeDef *htim);
1272 HAL_TIM_StateTypeDef HAL_TIM_IC_GetState(TIM_HandleTypeDef *htim);
1273 HAL_TIM_StateTypeDef HAL_TIM_OnePulse_GetState(TIM_HandleTypeDef *htim);
1274 HAL_TIM_StateTypeDef HAL_TIM_Encoder_GetState(TIM_HandleTypeDef *htim);
1275
1276 /**
1277 * @}
1278 */
1279
1280 /**
1281 * @}
1282 */
1283
1284 /* Private macros ------------------------------------------------------------*/
1285 /** @defgroup TIM_Private_Macros TIM Private Macros
1286 * @{
1287 */
1288
1289 /** @defgroup TIM_IS_TIM_Definitions TIM Private macros to check input parameters
1290 * @{
1291 */
1292 #define IS_TIM_COUNTER_MODE(__MODE__) (((__MODE__) == TIM_COUNTERMODE_UP) || \
1293 ((__MODE__) == TIM_COUNTERMODE_DOWN) || \
1294 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED1) || \
1295 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED2) || \
1296 ((__MODE__) == TIM_COUNTERMODE_CENTERALIGNED3))
1297
1298 #define IS_TIM_CLOCKDIVISION_DIV(__DIV__) (((__DIV__) == TIM_CLOCKDIVISION_DIV1) || \
1299 ((__DIV__) == TIM_CLOCKDIVISION_DIV2) || \
1300 ((__DIV__) == TIM_CLOCKDIVISION_DIV4))
1301
1302 #define IS_TIM_AUTORELOAD_PRELOAD(PRELOAD) (((PRELOAD) == TIM_AUTORELOAD_PRELOAD_DISABLE) || \
1303 ((PRELOAD) == TIM_AUTORELOAD_PRELOAD_ENABLE))
1304
1305 #define IS_TIM_FAST_STATE(__STATE__) (((__STATE__) == TIM_OCFAST_DISABLE) || \
1306 ((__STATE__) == TIM_OCFAST_ENABLE))
1307
1308 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OUTPUTSTATE_DISABLE) || \
1309 ((STATE) == TIM_OUTPUTSTATE_ENABLE))
1310
1311 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OUTPUTNSTATE_DISABLE) || \
1312 ((STATE) == TIM_OUTPUTNSTATE_ENABLE))
1313
1314 #define IS_TIM_OC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCPOLARITY_HIGH) || \
1315 ((__POLARITY__) == TIM_OCPOLARITY_LOW))
1316
1317 #define IS_TIM_OCN_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_OCNPOLARITY_HIGH) || \
1318 ((__POLARITY__) == TIM_OCNPOLARITY_LOW))
1319
1320 #define IS_TIM_OCIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCIDLESTATE_SET) || \
1321 ((__STATE__) == TIM_OCIDLESTATE_RESET))
1322
1323 #define IS_TIM_OCNIDLE_STATE(__STATE__) (((__STATE__) == TIM_OCNIDLESTATE_SET) || \
1324 ((__STATE__) == TIM_OCNIDLESTATE_RESET))
1325
1326 #define IS_TIM_IC_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_ICPOLARITY_RISING) || \
1327 ((__POLARITY__) == TIM_ICPOLARITY_FALLING) || \
1328 ((__POLARITY__) == TIM_ICPOLARITY_BOTHEDGE))
1329
1330 #define IS_TIM_IC_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_ICSELECTION_DIRECTTI) || \
1331 ((__SELECTION__) == TIM_ICSELECTION_INDIRECTTI) || \
1332 ((__SELECTION__) == TIM_ICSELECTION_TRC))
1333
1334 #define IS_TIM_IC_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_ICPSC_DIV1) || \
1335 ((__PRESCALER__) == TIM_ICPSC_DIV2) || \
1336 ((__PRESCALER__) == TIM_ICPSC_DIV4) || \
1337 ((__PRESCALER__) == TIM_ICPSC_DIV8))
1338
1339 #define IS_TIM_OPM_MODE(__MODE__) (((__MODE__) == TIM_OPMODE_SINGLE) || \
1340 ((__MODE__) == TIM_OPMODE_REPETITIVE))
1341
1342 #define IS_TIM_ENCODER_MODE(__MODE__) (((__MODE__) == TIM_ENCODERMODE_TI1) || \
1343 ((__MODE__) == TIM_ENCODERMODE_TI2) || \
1344 ((__MODE__) == TIM_ENCODERMODE_TI12))
1345
1346 #define IS_TIM_IT(__IT__) ((((__IT__) & 0xFFFFFF00U) == 0x00000000U) && ((__IT__) != 0x00000000U))
1347
1348
1349 #define IS_TIM_GET_IT(__IT__) (((__IT__) == TIM_IT_UPDATE) || \
1350 ((__IT__) == TIM_IT_CC1) || \
1351 ((__IT__) == TIM_IT_CC2) || \
1352 ((__IT__) == TIM_IT_CC3) || \
1353 ((__IT__) == TIM_IT_CC4) || \
1354 ((__IT__) == TIM_IT_COM) || \
1355 ((__IT__) == TIM_IT_TRIGGER) || \
1356 ((__IT__) == TIM_IT_BREAK))
1357
1358 #define IS_TIM_DMA_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFF80FFU) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1359
1360 #define IS_TIM_EVENT_SOURCE(__SOURCE__) ((((__SOURCE__) & 0xFFFFFE00U) == 0x00000000U) && ((__SOURCE__) != 0x00000000U))
1361
1362 #define IS_TIM_FLAG(__FLAG__) (((__FLAG__) == TIM_FLAG_UPDATE) || \
1363 ((__FLAG__) == TIM_FLAG_CC1) || \
1364 ((__FLAG__) == TIM_FLAG_CC2) || \
1365 ((__FLAG__) == TIM_FLAG_CC3) || \
1366 ((__FLAG__) == TIM_FLAG_CC4) || \
1367 ((__FLAG__) == TIM_FLAG_COM) || \
1368 ((__FLAG__) == TIM_FLAG_TRIGGER) || \
1369 ((__FLAG__) == TIM_FLAG_BREAK) || \
1370 ((__FLAG__) == TIM_FLAG_BREAK2) || \
1371 ((__FLAG__) == TIM_FLAG_CC1OF) || \
1372 ((__FLAG__) == TIM_FLAG_CC2OF) || \
1373 ((__FLAG__) == TIM_FLAG_CC3OF) || \
1374 ((__FLAG__) == TIM_FLAG_CC4OF))
1375
1376 #define IS_TIM_CLOCKSOURCE(__CLOCK__) (((__CLOCK__) == TIM_CLOCKSOURCE_INTERNAL) || \
1377 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE2) || \
1378 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR0) || \
1379 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR1) || \
1380 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR2) || \
1381 ((__CLOCK__) == TIM_CLOCKSOURCE_ITR3) || \
1382 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1ED) || \
1383 ((__CLOCK__) == TIM_CLOCKSOURCE_TI1) || \
1384 ((__CLOCK__) == TIM_CLOCKSOURCE_TI2) || \
1385 ((__CLOCK__) == TIM_CLOCKSOURCE_ETRMODE1))
1386
1387 #define IS_TIM_CLOCKPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLOCKPOLARITY_INVERTED) || \
1388 ((__POLARITY__) == TIM_CLOCKPOLARITY_NONINVERTED) || \
1389 ((__POLARITY__) == TIM_CLOCKPOLARITY_RISING) || \
1390 ((__POLARITY__) == TIM_CLOCKPOLARITY_FALLING) || \
1391 ((__POLARITY__) == TIM_CLOCKPOLARITY_BOTHEDGE))
1392
1393 #define IS_TIM_CLOCKPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV1) || \
1394 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV2) || \
1395 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV4) || \
1396 ((__PRESCALER__) == TIM_CLOCKPRESCALER_DIV8))
1397
1398 #define IS_TIM_CLOCKFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1399
1400 #define IS_TIM_CLEARINPUT_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_CLEARINPUTPOLARITY_INVERTED) || \
1401 ((__POLARITY__) == TIM_CLEARINPUTPOLARITY_NONINVERTED))
1402
1403 #define IS_TIM_CLEARINPUT_PRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV1) || \
1404 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV2) || \
1405 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV4) || \
1406 ((__PRESCALER__) == TIM_CLEARINPUTPRESCALER_DIV8))
1407
1408 #define IS_TIM_CLEARINPUT_FILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1409
1410 #define IS_TIM_OSSR_STATE(__STATE__) (((__STATE__) == TIM_OSSR_ENABLE) || \
1411 ((__STATE__) == TIM_OSSR_DISABLE))
1412
1413 #define IS_TIM_OSSI_STATE(__STATE__) (((__STATE__) == TIM_OSSI_ENABLE) || \
1414 ((__STATE__) == TIM_OSSI_DISABLE))
1415
1416 #define IS_TIM_LOCK_LEVEL(__LEVEL__) (((__LEVEL__) == TIM_LOCKLEVEL_OFF) || \
1417 ((__LEVEL__) == TIM_LOCKLEVEL_1) || \
1418 ((__LEVEL__) == TIM_LOCKLEVEL_2) || \
1419 ((__LEVEL__) == TIM_LOCKLEVEL_3))
1420
1421 #define IS_TIM_BREAK_STATE(__STATE__) (((__STATE__) == TIM_BREAK_ENABLE) || \
1422 ((__STATE__) == TIM_BREAK_DISABLE))
1423
1424 #define IS_TIM_BREAK_POLARITY(__POLARITY__) (((__POLARITY__) == TIM_BREAKPOLARITY_LOW) || \
1425 ((__POLARITY__) == TIM_BREAKPOLARITY_HIGH))
1426
1427 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(__STATE__) (((__STATE__) == TIM_AUTOMATICOUTPUT_ENABLE) || \
1428 ((__STATE__) == TIM_AUTOMATICOUTPUT_DISABLE))
1429
1430 #define IS_TIM_TRGO_SOURCE(__SOURCE__) (((__SOURCE__) == TIM_TRGO_RESET) || \
1431 ((__SOURCE__) == TIM_TRGO_ENABLE) || \
1432 ((__SOURCE__) == TIM_TRGO_UPDATE) || \
1433 ((__SOURCE__) == TIM_TRGO_OC1) || \
1434 ((__SOURCE__) == TIM_TRGO_OC1REF) || \
1435 ((__SOURCE__) == TIM_TRGO_OC2REF) || \
1436 ((__SOURCE__) == TIM_TRGO_OC3REF) || \
1437 ((__SOURCE__) == TIM_TRGO_OC4REF))
1438
1439 #define IS_TIM_MSM_STATE(__STATE__) (((__STATE__) == TIM_MASTERSLAVEMODE_ENABLE) || \
1440 ((__STATE__) == TIM_MASTERSLAVEMODE_DISABLE))
1441
1442 #define IS_TIM_TRIGGER_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1443 ((__SELECTION__) == TIM_TS_ITR1) || \
1444 ((__SELECTION__) == TIM_TS_ITR2) || \
1445 ((__SELECTION__) == TIM_TS_ITR3) || \
1446 ((__SELECTION__) == TIM_TS_TI1F_ED) || \
1447 ((__SELECTION__) == TIM_TS_TI1FP1) || \
1448 ((__SELECTION__) == TIM_TS_TI2FP2) || \
1449 ((__SELECTION__) == TIM_TS_ETRF))
1450
1451 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
1452 ((SELECTION) == TIM_TS_ITR1) || \
1453 ((SELECTION) == TIM_TS_ITR2) || \
1454 ((SELECTION) == TIM_TS_ITR3))
1455
1456 #define IS_TIM_INTERNAL_TRIGGEREVENT_SELECTION(__SELECTION__) (((__SELECTION__) == TIM_TS_ITR0) || \
1457 ((__SELECTION__) == TIM_TS_ITR1) || \
1458 ((__SELECTION__) == TIM_TS_ITR2) || \
1459 ((__SELECTION__) == TIM_TS_ITR3) || \
1460 ((__SELECTION__) == TIM_TS_NONE))
1461
1462 #define IS_TIM_TRIGGERPOLARITY(__POLARITY__) (((__POLARITY__) == TIM_TRIGGERPOLARITY_INVERTED ) || \
1463 ((__POLARITY__) == TIM_TRIGGERPOLARITY_NONINVERTED) || \
1464 ((__POLARITY__) == TIM_TRIGGERPOLARITY_RISING ) || \
1465 ((__POLARITY__) == TIM_TRIGGERPOLARITY_FALLING ) || \
1466 ((__POLARITY__) == TIM_TRIGGERPOLARITY_BOTHEDGE ))
1467
1468 #define IS_TIM_TRIGGERPRESCALER(__PRESCALER__) (((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV1) || \
1469 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV2) || \
1470 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV4) || \
1471 ((__PRESCALER__) == TIM_TRIGGERPRESCALER_DIV8))
1472
1473 #define IS_TIM_TRIGGERFILTER(__ICFILTER__) ((__ICFILTER__) <= 0xF)
1474
1475 #define IS_TIM_TI1SELECTION(__TI1SELECTION__) (((__TI1SELECTION__) == TIM_TI1SELECTION_CH1) || \
1476 ((__TI1SELECTION__) == TIM_TI1SELECTION_XORCOMBINATION))
1477
1478 #define IS_TIM_DMA_BASE(__BASE__) (((__BASE__) == TIM_DMABASE_CR1) || \
1479 ((__BASE__) == TIM_DMABASE_CR2) || \
1480 ((__BASE__) == TIM_DMABASE_SMCR) || \
1481 ((__BASE__) == TIM_DMABASE_DIER) || \
1482 ((__BASE__) == TIM_DMABASE_SR) || \
1483 ((__BASE__) == TIM_DMABASE_EGR) || \
1484 ((__BASE__) == TIM_DMABASE_CCMR1) || \
1485 ((__BASE__) == TIM_DMABASE_CCMR2) || \
1486 ((__BASE__) == TIM_DMABASE_CCER) || \
1487 ((__BASE__) == TIM_DMABASE_CNT) || \
1488 ((__BASE__) == TIM_DMABASE_PSC) || \
1489 ((__BASE__) == TIM_DMABASE_ARR) || \
1490 ((__BASE__) == TIM_DMABASE_RCR) || \
1491 ((__BASE__) == TIM_DMABASE_CCR1) || \
1492 ((__BASE__) == TIM_DMABASE_CCR2) || \
1493 ((__BASE__) == TIM_DMABASE_CCR3) || \
1494 ((__BASE__) == TIM_DMABASE_CCR4) || \
1495 ((__BASE__) == TIM_DMABASE_BDTR) || \
1496 ((__BASE__) == TIM_DMABASE_DCR) || \
1497 ((__BASE__) == TIM_DMABASE_OR))
1498
1499 #define IS_TIM_DMA_LENGTH(__LENGTH__) (((__LENGTH__) == TIM_DMABURSTLENGTH_1TRANSFER) || \
1500 ((__LENGTH__) == TIM_DMABURSTLENGTH_2TRANSFERS) || \
1501 ((__LENGTH__) == TIM_DMABURSTLENGTH_3TRANSFERS) || \
1502 ((__LENGTH__) == TIM_DMABURSTLENGTH_4TRANSFERS) || \
1503 ((__LENGTH__) == TIM_DMABURSTLENGTH_5TRANSFERS) || \
1504 ((__LENGTH__) == TIM_DMABURSTLENGTH_6TRANSFERS) || \
1505 ((__LENGTH__) == TIM_DMABURSTLENGTH_7TRANSFERS) || \
1506 ((__LENGTH__) == TIM_DMABURSTLENGTH_8TRANSFERS) || \
1507 ((__LENGTH__) == TIM_DMABURSTLENGTH_9TRANSFERS) || \
1508 ((__LENGTH__) == TIM_DMABURSTLENGTH_10TRANSFERS) || \
1509 ((__LENGTH__) == TIM_DMABURSTLENGTH_11TRANSFERS) || \
1510 ((__LENGTH__) == TIM_DMABURSTLENGTH_12TRANSFERS) || \
1511 ((__LENGTH__) == TIM_DMABURSTLENGTH_13TRANSFERS) || \
1512 ((__LENGTH__) == TIM_DMABURSTLENGTH_14TRANSFERS) || \
1513 ((__LENGTH__) == TIM_DMABURSTLENGTH_15TRANSFERS) || \
1514 ((__LENGTH__) == TIM_DMABURSTLENGTH_16TRANSFERS) || \
1515 ((__LENGTH__) == TIM_DMABURSTLENGTH_17TRANSFERS) || \
1516 ((__LENGTH__) == TIM_DMABURSTLENGTH_18TRANSFERS))
1517
1518 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
1519
1520
1521 /**
1522 * @}
1523 */
1524
1525 /**
1526 * @}
1527 */
1528
1529 /* Private functions ---------------------------------------------------------*/
1530 /** @defgroup TIM_Private_Functions TIM Private Functions
1531 * @{
1532 */
1533 void TIM_Base_SetConfig(TIM_TypeDef *TIMx, TIM_Base_InitTypeDef *Structure);
1534 void TIM_TI1_SetConfig(TIM_TypeDef *TIMx, uint32_t TIM_ICPolarity, uint32_t TIM_ICSelection, uint32_t TIM_ICFilter);
1535 void TIM_OC1_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1536 void TIM_OC2_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1537 void TIM_OC3_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1538 void TIM_OC4_SetConfig(TIM_TypeDef *TIMx, TIM_OC_InitTypeDef *OC_Config);
1539 void TIM_ETR_SetConfig(TIM_TypeDef* TIMx, uint32_t TIM_ExtTRGPrescaler, uint32_t TIM_ExtTRGPolarity, uint32_t ExtTRGFilter);
1540
1541 void HAL_TIM_DMADelayPulseCplt(DMA_HandleTypeDef *hdma);
1542 void HAL_TIM_DMAError(DMA_HandleTypeDef *hdma);
1543 void HAL_TIM_DMACaptureCplt(DMA_HandleTypeDef *hdma);
1544 void TIM_CCxChannelCmd(TIM_TypeDef* TIMx, uint32_t Channel, uint32_t ChannelState);
1545 /**
1546 * @}
1547 */
1548
1549 /**
1550 * @}
1551 */
1552
1553 /**
1554 * @}
1555 */
1556
1557 #ifdef __cplusplus
1558 }
1559 #endif
1560
1561 #endif /* __STM32F7xx_HAL_TIM_H */
1562
1563 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software