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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_bus.h
blob2915350f3f98cac03a614f2b31761a5610623708
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_bus.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of BUS LL module.
8
9 @verbatim
10 ##### RCC Limitations #####
11 ==============================================================================
12 [..]
13 A delay between an RCC peripheral clock enable and the effective peripheral
14 enabling should be taken into account in order to manage the peripheral read/write
15 from/to registers.
16 (+) This delay depends on the peripheral mapping.
17 (++) AHB & APB peripherals, 1 dummy read is necessary
18
19 [..]
20 Workarounds:
21 (#) For AHB & APB peripherals, a dummy read to the peripheral register has been
22 inserted in each LL_{BUS}_GRP{x}_EnableClock() function.
23
24 @endverbatim
25 ******************************************************************************
26 * @attention
27 *
28 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
29 *
30 * Redistribution and use in source and binary forms, with or without modification,
31 * are permitted provided that the following conditions are met:
32 * 1. Redistributions of source code must retain the above copyright notice,
33 * this list of conditions and the following disclaimer.
34 * 2. Redistributions in binary form must reproduce the above copyright notice,
35 * this list of conditions and the following disclaimer in the documentation
36 * and/or other materials provided with the distribution.
37 * 3. Neither the name of STMicroelectronics nor the names of its contributors
38 * may be used to endorse or promote products derived from this software
39 * without specific prior written permission.
40 *
41 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
42 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
43 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
44 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
45 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
46 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
47 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
48 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
49 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
50 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
51 *
52 ******************************************************************************
53 */
54
55 /* Define to prevent recursive inclusion -------------------------------------*/
56 #ifndef __STM32F7xx_LL_BUS_H
57 #define __STM32F7xx_LL_BUS_H
58
59 #ifdef __cplusplus
60 extern "C" {
61 #endif
62
63 /* Includes ------------------------------------------------------------------*/
64 #include "stm32f7xx.h"
65
66 /** @addtogroup STM32F7xx_LL_Driver
67 * @{
68 */
69
70 #if defined(RCC)
71
72 /** @defgroup BUS_LL BUS
73 * @{
74 */
75
76 /* Private types -------------------------------------------------------------*/
77 /* Private variables ---------------------------------------------------------*/
78 /* Private constants ---------------------------------------------------------*/
79 /* Private macros ------------------------------------------------------------*/
80 /* Exported types ------------------------------------------------------------*/
81 /* Exported constants --------------------------------------------------------*/
82 /** @defgroup BUS_LL_Exported_Constants BUS Exported Constants
83 * @{
84 */
85
86 /** @defgroup BUS_LL_EC_AHB1_GRP1_PERIPH AHB1 GRP1 PERIPH
87 * @{
88 */
89 #define LL_AHB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
90 #define LL_AHB1_GRP1_PERIPH_GPIOA RCC_AHB1ENR_GPIOAEN
91 #define LL_AHB1_GRP1_PERIPH_GPIOB RCC_AHB1ENR_GPIOBEN
92 #define LL_AHB1_GRP1_PERIPH_GPIOC RCC_AHB1ENR_GPIOCEN
93 #define LL_AHB1_GRP1_PERIPH_GPIOD RCC_AHB1ENR_GPIODEN
94 #define LL_AHB1_GRP1_PERIPH_GPIOE RCC_AHB1ENR_GPIOEEN
95 #define LL_AHB1_GRP1_PERIPH_GPIOF RCC_AHB1ENR_GPIOFEN
96 #define LL_AHB1_GRP1_PERIPH_GPIOG RCC_AHB1ENR_GPIOGEN
97 #define LL_AHB1_GRP1_PERIPH_GPIOH RCC_AHB1ENR_GPIOHEN
98 #define LL_AHB1_GRP1_PERIPH_GPIOI RCC_AHB1ENR_GPIOIEN
99 #if defined(GPIOJ)
100 #define LL_AHB1_GRP1_PERIPH_GPIOJ RCC_AHB1ENR_GPIOJEN
101 #endif /* GPIOJ */
102 #if defined(GPIOK)
103 #define LL_AHB1_GRP1_PERIPH_GPIOK RCC_AHB1ENR_GPIOKEN
104 #endif /* GPIOK */
105 #define LL_AHB1_GRP1_PERIPH_CRC RCC_AHB1ENR_CRCEN
106 #define LL_AHB1_GRP1_PERIPH_BKPSRAM RCC_AHB1ENR_BKPSRAMEN
107 #define LL_AHB1_GRP1_PERIPH_DTCMRAM RCC_AHB1ENR_DTCMRAMEN
108 #define LL_AHB1_GRP1_PERIPH_DMA1 RCC_AHB1ENR_DMA1EN
109 #define LL_AHB1_GRP1_PERIPH_DMA2 RCC_AHB1ENR_DMA2EN
110 #if defined(DMA2D)
111 #define LL_AHB1_GRP1_PERIPH_DMA2D RCC_AHB1ENR_DMA2DEN
112 #endif /* DMA2D */
113 #if defined(ETH)
114 #define LL_AHB1_GRP1_PERIPH_ETHMAC RCC_AHB1ENR_ETHMACEN
115 #define LL_AHB1_GRP1_PERIPH_ETHMACTX RCC_AHB1ENR_ETHMACTXEN
116 #define LL_AHB1_GRP1_PERIPH_ETHMACRX RCC_AHB1ENR_ETHMACRXEN
117 #define LL_AHB1_GRP1_PERIPH_ETHMACPTP RCC_AHB1ENR_ETHMACPTPEN
118 #endif /* ETH */
119 #define LL_AHB1_GRP1_PERIPH_OTGHS RCC_AHB1ENR_OTGHSEN
120 #define LL_AHB1_GRP1_PERIPH_OTGHSULPI RCC_AHB1ENR_OTGHSULPIEN
121 #define LL_AHB1_GRP1_PERIPH_AXI RCC_AHB1LPENR_AXILPEN
122 #define LL_AHB1_GRP1_PERIPH_FLITF RCC_AHB1LPENR_FLITFLPEN
123 #define LL_AHB1_GRP1_PERIPH_SRAM1 RCC_AHB1LPENR_SRAM1LPEN
124 #define LL_AHB1_GRP1_PERIPH_SRAM2 RCC_AHB1LPENR_SRAM2LPEN
125 /**
126 * @}
127 */
128
129 /** @defgroup BUS_LL_EC_AHB2_GRP1_PERIPH AHB2 GRP1 PERIPH
130 * @{
131 */
132 #define LL_AHB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
133 #if defined(DCMI)
134 #define LL_AHB2_GRP1_PERIPH_DCMI RCC_AHB2ENR_DCMIEN
135 #endif /* DCMI */
136 #if defined(JPEG)
137 #define LL_AHB2_GRP1_PERIPH_JPEG RCC_AHB2ENR_JPEGEN
138 #endif /* JPEG */
139 #if defined(CRYP)
140 #define LL_AHB2_GRP1_PERIPH_CRYP RCC_AHB2ENR_CRYPEN
141 #endif /* CRYP */
142 #if defined(AES)
143 #define LL_AHB2_GRP1_PERIPH_AES RCC_AHB2ENR_AESEN
144 #endif /* AES */
145 #if defined(HASH)
146 #define LL_AHB2_GRP1_PERIPH_HASH RCC_AHB2ENR_HASHEN
147 #endif /* HASH */
148 #define LL_AHB2_GRP1_PERIPH_RNG RCC_AHB2ENR_RNGEN
149 #define LL_AHB2_GRP1_PERIPH_OTGFS RCC_AHB2ENR_OTGFSEN
150 /**
151 * @}
152 */
153
154 /** @defgroup BUS_LL_EC_AHB3_GRP1_PERIPH AHB3 GRP1 PERIPH
155 * @{
156 */
157 #define LL_AHB3_GRP1_PERIPH_ALL 0xFFFFFFFFU
158 #define LL_AHB3_GRP1_PERIPH_FMC RCC_AHB3ENR_FMCEN
159 #define LL_AHB3_GRP1_PERIPH_QSPI RCC_AHB3ENR_QSPIEN
160 /**
161 * @}
162 */
163
164 /** @defgroup BUS_LL_EC_APB1_GRP1_PERIPH APB1 GRP1 PERIPH
165 * @{
166 */
167 #define LL_APB1_GRP1_PERIPH_ALL 0xFFFFFFFFU
168 #define LL_APB1_GRP1_PERIPH_TIM2 RCC_APB1ENR_TIM2EN
169 #define LL_APB1_GRP1_PERIPH_TIM3 RCC_APB1ENR_TIM3EN
170 #define LL_APB1_GRP1_PERIPH_TIM4 RCC_APB1ENR_TIM4EN
171 #define LL_APB1_GRP1_PERIPH_TIM5 RCC_APB1ENR_TIM5EN
172 #define LL_APB1_GRP1_PERIPH_TIM6 RCC_APB1ENR_TIM6EN
173 #define LL_APB1_GRP1_PERIPH_TIM7 RCC_APB1ENR_TIM7EN
174 #define LL_APB1_GRP1_PERIPH_TIM12 RCC_APB1ENR_TIM12EN
175 #define LL_APB1_GRP1_PERIPH_TIM13 RCC_APB1ENR_TIM13EN
176 #define LL_APB1_GRP1_PERIPH_TIM14 RCC_APB1ENR_TIM14EN
177 #define LL_APB1_GRP1_PERIPH_LPTIM1 RCC_APB1ENR_LPTIM1EN
178 #define LL_APB1_GRP1_PERIPH_WWDG RCC_APB1ENR_WWDGEN
179 #define LL_APB1_GRP1_PERIPH_SPI2 RCC_APB1ENR_SPI2EN
180 #define LL_APB1_GRP1_PERIPH_SPI3 RCC_APB1ENR_SPI3EN
181 #if defined(SPDIFRX)
182 #define LL_APB1_GRP1_PERIPH_SPDIFRX RCC_APB1ENR_SPDIFRXEN
183 #endif /* SPDIFRX */
184 #define LL_APB1_GRP1_PERIPH_USART2 RCC_APB1ENR_USART2EN
185 #define LL_APB1_GRP1_PERIPH_USART3 RCC_APB1ENR_USART3EN
186 #define LL_APB1_GRP1_PERIPH_UART4 RCC_APB1ENR_UART4EN
187 #define LL_APB1_GRP1_PERIPH_UART5 RCC_APB1ENR_UART5EN
188 #define LL_APB1_GRP1_PERIPH_I2C1 RCC_APB1ENR_I2C1EN
189 #define LL_APB1_GRP1_PERIPH_I2C2 RCC_APB1ENR_I2C2EN
190 #define LL_APB1_GRP1_PERIPH_I2C3 RCC_APB1ENR_I2C3EN
191 #if defined(I2C4)
192 #define LL_APB1_GRP1_PERIPH_I2C4 RCC_APB1ENR_I2C4EN
193 #endif /* I2C4 */
194 #define LL_APB1_GRP1_PERIPH_CAN1 RCC_APB1ENR_CAN1EN
195 #if defined(CAN2)
196 #define LL_APB1_GRP1_PERIPH_CAN2 RCC_APB1ENR_CAN2EN
197 #endif /* CAN2 */
198 #if defined(CAN3)
199 #define LL_APB1_GRP1_PERIPH_CAN3 RCC_APB1ENR_CAN3EN
200 #endif /* CAN3 */
201 #if defined(CEC)
202 #define LL_APB1_GRP1_PERIPH_CEC RCC_APB1ENR_CECEN
203 #endif /* CEC */
204 #define LL_APB1_GRP1_PERIPH_PWR RCC_APB1ENR_PWREN
205 #define LL_APB1_GRP1_PERIPH_DAC1 RCC_APB1ENR_DACEN
206 #define LL_APB1_GRP1_PERIPH_UART7 RCC_APB1ENR_UART7EN
207 #define LL_APB1_GRP1_PERIPH_UART8 RCC_APB1ENR_UART8EN
208 #if defined(RCC_APB1ENR_RTCEN)
209 #define LL_APB1_GRP1_PERIPH_RTCAPB RCC_APB1ENR_RTCEN
210 #endif /* RCC_APB1ENR_RTCEN */
211 /**
212 * @}
213 */
214
215 /** @defgroup BUS_LL_EC_APB2_GRP1_PERIPH APB2 GRP1 PERIPH
216 * @{
217 */
218 #define LL_APB2_GRP1_PERIPH_ALL 0xFFFFFFFFU
219 #define LL_APB2_GRP1_PERIPH_TIM1 RCC_APB2ENR_TIM1EN
220 #define LL_APB2_GRP1_PERIPH_TIM8 RCC_APB2ENR_TIM8EN
221 #define LL_APB2_GRP1_PERIPH_USART1 RCC_APB2ENR_USART1EN
222 #define LL_APB2_GRP1_PERIPH_USART6 RCC_APB2ENR_USART6EN
223 #define LL_APB2_GRP1_PERIPH_ADC1 RCC_APB2ENR_ADC1EN
224 #define LL_APB2_GRP1_PERIPH_ADC2 RCC_APB2ENR_ADC2EN
225 #define LL_APB2_GRP1_PERIPH_ADC3 RCC_APB2ENR_ADC3EN
226 #define LL_APB2_GRP1_PERIPH_SDMMC1 RCC_APB2ENR_SDMMC1EN
227 #if defined(SDMMC2)
228 #define LL_APB2_GRP1_PERIPH_SDMMC2 RCC_APB2ENR_SDMMC2EN
229 #endif /* SDMMC2 */
230 #define LL_APB2_GRP1_PERIPH_SPI1 RCC_APB2ENR_SPI1EN
231 #define LL_APB2_GRP1_PERIPH_SPI4 RCC_APB2ENR_SPI4EN
232 #define LL_APB2_GRP1_PERIPH_SYSCFG RCC_APB2ENR_SYSCFGEN
233 #define LL_APB2_GRP1_PERIPH_TIM9 RCC_APB2ENR_TIM9EN
234 #define LL_APB2_GRP1_PERIPH_TIM10 RCC_APB2ENR_TIM10EN
235 #define LL_APB2_GRP1_PERIPH_TIM11 RCC_APB2ENR_TIM11EN
236 #define LL_APB2_GRP1_PERIPH_SPI5 RCC_APB2ENR_SPI5EN
237 #if defined(SPI6)
238 #define LL_APB2_GRP1_PERIPH_SPI6 RCC_APB2ENR_SPI6EN
239 #endif /* SPI6 */
240 #define LL_APB2_GRP1_PERIPH_SAI1 RCC_APB2ENR_SAI1EN
241 #define LL_APB2_GRP1_PERIPH_SAI2 RCC_APB2ENR_SAI2EN
242 #if defined(LTDC)
243 #define LL_APB2_GRP1_PERIPH_LTDC RCC_APB2ENR_LTDCEN
244 #endif /* LTDC */
245 #if defined(DSI)
246 #define LL_APB2_GRP1_PERIPH_DSI RCC_APB2ENR_DSIEN
247 #endif /* DSI */
248 #if defined(DFSDM1_Channel0)
249 #define LL_APB2_GRP1_PERIPH_DFSDM1 RCC_APB2ENR_DFSDM1EN
250 #endif /* DFSDM1_Channel0 */
251 #if defined(MDIOS)
252 #define LL_APB2_GRP1_PERIPH_MDIO RCC_APB2ENR_MDIOEN
253 #endif /* MDIOS */
254 #if defined(USB_HS_PHYC)
255 #define LL_APB2_GRP1_PERIPH_OTGPHYC RCC_APB2ENR_OTGPHYCEN
256 #endif /* USB_HS_PHYC */
257 #define LL_APB2_GRP1_PERIPH_ADC RCC_APB2RSTR_ADCRST
258 /**
259 * @}
260 */
261
262 /**
263 * @}
264 */
265
266 /* Exported macro ------------------------------------------------------------*/
267 /* Exported functions --------------------------------------------------------*/
268 /** @defgroup BUS_LL_Exported_Functions BUS Exported Functions
269 * @{
270 */
271
272 /** @defgroup BUS_LL_EF_AHB1 AHB1
273 * @{
274 */
275
276 /**
277 * @brief Enable AHB1 peripherals clock.
278 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_EnableClock\n
279 * AHB1ENR GPIOBEN LL_AHB1_GRP1_EnableClock\n
280 * AHB1ENR GPIOCEN LL_AHB1_GRP1_EnableClock\n
281 * AHB1ENR GPIODEN LL_AHB1_GRP1_EnableClock\n
282 * AHB1ENR GPIOEEN LL_AHB1_GRP1_EnableClock\n
283 * AHB1ENR GPIOFEN LL_AHB1_GRP1_EnableClock\n
284 * AHB1ENR GPIOGEN LL_AHB1_GRP1_EnableClock\n
285 * AHB1ENR GPIOHEN LL_AHB1_GRP1_EnableClock\n
286 * AHB1ENR GPIOIEN LL_AHB1_GRP1_EnableClock\n
287 * AHB1ENR GPIOJEN LL_AHB1_GRP1_EnableClock\n
288 * AHB1ENR GPIOKEN LL_AHB1_GRP1_EnableClock\n
289 * AHB1ENR CRCEN LL_AHB1_GRP1_EnableClock\n
290 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_EnableClock\n
291 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_EnableClock\n
292 * AHB1ENR DMA1EN LL_AHB1_GRP1_EnableClock\n
293 * AHB1ENR DMA2EN LL_AHB1_GRP1_EnableClock\n
294 * AHB1ENR DMA2DEN LL_AHB1_GRP1_EnableClock\n
295 * AHB1ENR ETHMACEN LL_AHB1_GRP1_EnableClock\n
296 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_EnableClock\n
297 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_EnableClock\n
298 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_EnableClock\n
299 * AHB1ENR OTGHSEN LL_AHB1_GRP1_EnableClock\n
300 * AHB1ENR OTGHSULPIEN LL_AHB1_GRP1_EnableClock
301 * @param Periphs This parameter can be a combination of the following values:
302 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
303 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
304 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
305 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
306 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
307 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
308 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
309 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
310 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
311 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
312 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
313 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
314 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
315 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
316 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
317 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
318 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
319 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
320 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
321 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
322 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
323 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
324 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
325 *
326 * (*) value not defined in all devices.
327 * @retval None
328 */
329 __STATIC_INLINE void LL_AHB1_GRP1_EnableClock(uint32_t Periphs)
330 {
331 __IO uint32_t tmpreg;
332 SET_BIT(RCC->AHB1ENR, Periphs);
333 /* Delay after an RCC peripheral clock enabling */
334 tmpreg = READ_BIT(RCC->AHB1ENR, Periphs);
335 (void)tmpreg;
336 }
337
338 /**
339 * @brief Check if AHB1 peripheral clock is enabled or not
340 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_IsEnabledClock\n
341 * AHB1ENR GPIOBEN LL_AHB1_GRP1_IsEnabledClock\n
342 * AHB1ENR GPIOCEN LL_AHB1_GRP1_IsEnabledClock\n
343 * AHB1ENR GPIODEN LL_AHB1_GRP1_IsEnabledClock\n
344 * AHB1ENR GPIOEEN LL_AHB1_GRP1_IsEnabledClock\n
345 * AHB1ENR GPIOFEN LL_AHB1_GRP1_IsEnabledClock\n
346 * AHB1ENR GPIOGEN LL_AHB1_GRP1_IsEnabledClock\n
347 * AHB1ENR GPIOHEN LL_AHB1_GRP1_IsEnabledClock\n
348 * AHB1ENR GPIOIEN LL_AHB1_GRP1_IsEnabledClock\n
349 * AHB1ENR GPIOJEN LL_AHB1_GRP1_IsEnabledClock\n
350 * AHB1ENR GPIOKEN LL_AHB1_GRP1_IsEnabledClock\n
351 * AHB1ENR CRCEN LL_AHB1_GRP1_IsEnabledClock\n
352 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_IsEnabledClock\n
353 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_IsEnabledClock\n
354 * AHB1ENR DMA1EN LL_AHB1_GRP1_IsEnabledClock\n
355 * AHB1ENR DMA2EN LL_AHB1_GRP1_IsEnabledClock\n
356 * AHB1ENR DMA2DEN LL_AHB1_GRP1_IsEnabledClock\n
357 * AHB1ENR ETHMACEN LL_AHB1_GRP1_IsEnabledClock\n
358 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_IsEnabledClock\n
359 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_IsEnabledClock\n
360 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_IsEnabledClock\n
361 * AHB1ENR OTGHSEN LL_AHB1_GRP1_IsEnabledClock\n
362 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_IsEnabledClock
363 * @param Periphs This parameter can be a combination of the following values:
364 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
365 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
366 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
367 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
368 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
369 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
370 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
371 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
372 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
373 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
374 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
375 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
376 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
377 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
378 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
379 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
380 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
381 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
382 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
383 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
384 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
385 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
386 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
387 *
388 * (*) value not defined in all devices.
389 * @retval State of Periphs (1 or 0).
390 */
391 __STATIC_INLINE uint32_t LL_AHB1_GRP1_IsEnabledClock(uint32_t Periphs)
392 {
393 return (READ_BIT(RCC->AHB1ENR, Periphs) == Periphs);
394 }
395
396 /**
397 * @brief Disable AHB1 peripherals clock.
398 * @rmtoll AHB1ENR GPIOAEN LL_AHB1_GRP1_DisableClock\n
399 * AHB1ENR GPIOBEN LL_AHB1_GRP1_DisableClock\n
400 * AHB1ENR GPIOCEN LL_AHB1_GRP1_DisableClock\n
401 * AHB1ENR GPIODEN LL_AHB1_GRP1_DisableClock\n
402 * AHB1ENR GPIOEEN LL_AHB1_GRP1_DisableClock\n
403 * AHB1ENR GPIOFEN LL_AHB1_GRP1_DisableClock\n
404 * AHB1ENR GPIOGEN LL_AHB1_GRP1_DisableClock\n
405 * AHB1ENR GPIOHEN LL_AHB1_GRP1_DisableClock\n
406 * AHB1ENR GPIOIEN LL_AHB1_GRP1_DisableClock\n
407 * AHB1ENR GPIOJEN LL_AHB1_GRP1_DisableClock\n
408 * AHB1ENR GPIOKEN LL_AHB1_GRP1_DisableClock\n
409 * AHB1ENR CRCEN LL_AHB1_GRP1_DisableClock\n
410 * AHB1ENR BKPSRAMEN LL_AHB1_GRP1_DisableClock\n
411 * AHB1ENR DTCMRAMEN LL_AHB1_GRP1_DisableClock\n
412 * AHB1ENR DMA1EN LL_AHB1_GRP1_DisableClock\n
413 * AHB1ENR DMA2EN LL_AHB1_GRP1_DisableClock\n
414 * AHB1ENR DMA2DEN LL_AHB1_GRP1_DisableClock\n
415 * AHB1ENR ETHMACEN LL_AHB1_GRP1_DisableClock\n
416 * AHB1ENR ETHMACTXEN LL_AHB1_GRP1_DisableClock\n
417 * AHB1ENR ETHMACRXEN LL_AHB1_GRP1_DisableClock\n
418 * AHB1ENR ETHMACPTPEN LL_AHB1_GRP1_DisableClock\n
419 * AHB1ENR OTGHSEN LL_AHB1_GRP1_DisableClock\n
420 * AHB1ENR OTGHSULPIENDEN LL_AHB1_GRP1_DisableClock
421 * @param Periphs This parameter can be a combination of the following values:
422 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
423 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
424 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
425 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
426 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
427 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
428 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
429 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
430 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
431 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
432 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
433 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
434 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
435 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
436 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
437 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
438 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
439 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
440 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
441 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
442 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
443 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
444 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
445 *
446 * (*) value not defined in all devices.
447 * @retval None
448 */
449 __STATIC_INLINE void LL_AHB1_GRP1_DisableClock(uint32_t Periphs)
450 {
451 CLEAR_BIT(RCC->AHB1ENR, Periphs);
452 }
453
454 /**
455 * @brief Force AHB1 peripherals reset.
456 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ForceReset\n
457 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ForceReset\n
458 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ForceReset\n
459 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ForceReset\n
460 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ForceReset\n
461 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ForceReset\n
462 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ForceReset\n
463 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ForceReset\n
464 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ForceReset\n
465 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ForceReset\n
466 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ForceReset\n
467 * AHB1RSTR CRCRST LL_AHB1_GRP1_ForceReset\n
468 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ForceReset\n
469 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ForceReset\n
470 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ForceReset\n
471 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ForceReset\n
472 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ForceReset
473 * @param Periphs This parameter can be a combination of the following values:
474 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
475 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
476 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
477 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
478 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
479 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
480 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
481 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
482 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
483 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
484 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
485 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
486 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
487 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
488 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
489 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
490 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
491 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
492 *
493 * (*) value not defined in all devices.
494 * @retval None
495 */
496 __STATIC_INLINE void LL_AHB1_GRP1_ForceReset(uint32_t Periphs)
497 {
498 SET_BIT(RCC->AHB1RSTR, Periphs);
499 }
500
501 /**
502 * @brief Release AHB1 peripherals reset.
503 * @rmtoll AHB1RSTR GPIOARST LL_AHB1_GRP1_ReleaseReset\n
504 * AHB1RSTR GPIOBRST LL_AHB1_GRP1_ReleaseReset\n
505 * AHB1RSTR GPIOCRST LL_AHB1_GRP1_ReleaseReset\n
506 * AHB1RSTR GPIODRST LL_AHB1_GRP1_ReleaseReset\n
507 * AHB1RSTR GPIOERST LL_AHB1_GRP1_ReleaseReset\n
508 * AHB1RSTR GPIOFRST LL_AHB1_GRP1_ReleaseReset\n
509 * AHB1RSTR GPIOGRST LL_AHB1_GRP1_ReleaseReset\n
510 * AHB1RSTR GPIOHRST LL_AHB1_GRP1_ReleaseReset\n
511 * AHB1RSTR GPIOIRST LL_AHB1_GRP1_ReleaseReset\n
512 * AHB1RSTR GPIOJRST LL_AHB1_GRP1_ReleaseReset\n
513 * AHB1RSTR GPIOKRST LL_AHB1_GRP1_ReleaseReset\n
514 * AHB1RSTR CRCRST LL_AHB1_GRP1_ReleaseReset\n
515 * AHB1RSTR DMA1RST LL_AHB1_GRP1_ReleaseReset\n
516 * AHB1RSTR DMA2RST LL_AHB1_GRP1_ReleaseReset\n
517 * AHB1RSTR DMA2DRST LL_AHB1_GRP1_ReleaseReset\n
518 * AHB1RSTR ETHMACRST LL_AHB1_GRP1_ReleaseReset\n
519 * AHB1RSTR OTGHSRST LL_AHB1_GRP1_ReleaseReset
520 * @param Periphs This parameter can be a combination of the following values:
521 * @arg @ref LL_AHB1_GRP1_PERIPH_ALL
522 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
523 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
524 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
525 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
526 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
527 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
528 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
529 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
530 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
531 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
532 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
533 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
534 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
535 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
536 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
537 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
538 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
539 *
540 * (*) value not defined in all devices.
541 * @retval None
542 */
543 __STATIC_INLINE void LL_AHB1_GRP1_ReleaseReset(uint32_t Periphs)
544 {
545 CLEAR_BIT(RCC->AHB1RSTR, Periphs);
546 }
547
548 /**
549 * @brief Enable AHB1 peripheral clocks in low-power mode
550 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_EnableClockLowPower\n
551 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_EnableClockLowPower\n
552 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
553 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_EnableClockLowPower\n
554 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_EnableClockLowPower\n
555 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
556 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_EnableClockLowPower\n
557 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_EnableClockLowPower\n
558 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_EnableClockLowPower\n
559 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_EnableClockLowPower\n
560 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_EnableClockLowPower\n
561 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_EnableClockLowPower\n
562 * AHB1LPENR AXILPEN LL_AHB1_GRP1_EnableClockLowPower\n
563 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_EnableClockLowPower\n
564 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
565 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
566 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
567 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_EnableClockLowPower\n
568 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_EnableClockLowPower\n
569 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_EnableClockLowPower\n
570 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_EnableClockLowPower\n
571 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_EnableClockLowPower\n
572 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
573 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_EnableClockLowPower\n
574 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_EnableClockLowPower\n
575 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_EnableClockLowPower\n
576 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_EnableClockLowPower
577 * @param Periphs This parameter can be a combination of the following values:
578 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
579 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
580 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
581 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
582 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
583 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
584 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
585 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
586 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
587 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
588 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
589 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
590 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
591 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
592 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
593 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
594 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
595 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
596 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
597 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
598 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
599 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
600 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
601 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
602 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
603 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
604 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
605 *
606 * (*) value not defined in all devices.
607 * @retval None
608 */
609 __STATIC_INLINE void LL_AHB1_GRP1_EnableClockLowPower(uint32_t Periphs)
610 {
611 __IO uint32_t tmpreg;
612 SET_BIT(RCC->AHB1LPENR, Periphs);
613 /* Delay after an RCC peripheral clock enabling */
614 tmpreg = READ_BIT(RCC->AHB1LPENR, Periphs);
615 (void)tmpreg;
616 }
617
618 /**
619 * @brief Disable AHB1 peripheral clocks in low-power mode
620 * @rmtoll AHB1LPENR GPIOALPEN LL_AHB1_GRP1_DisableClockLowPower\n
621 * AHB1LPENR GPIOBLPEN LL_AHB1_GRP1_DisableClockLowPower\n
622 * AHB1LPENR GPIOCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
623 * AHB1LPENR GPIODLPEN LL_AHB1_GRP1_DisableClockLowPower\n
624 * AHB1LPENR GPIOELPEN LL_AHB1_GRP1_DisableClockLowPower\n
625 * AHB1LPENR GPIOFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
626 * AHB1LPENR GPIOGLPEN LL_AHB1_GRP1_DisableClockLowPower\n
627 * AHB1LPENR GPIOHLPEN LL_AHB1_GRP1_DisableClockLowPower\n
628 * AHB1LPENR GPIOILPEN LL_AHB1_GRP1_DisableClockLowPower\n
629 * AHB1LPENR GPIOJLPEN LL_AHB1_GRP1_DisableClockLowPower\n
630 * AHB1LPENR GPIOKLPEN LL_AHB1_GRP1_DisableClockLowPower\n
631 * AHB1LPENR CRCLPEN LL_AHB1_GRP1_DisableClockLowPower\n
632 * AHB1LPENR AXILPEN LL_AHB1_GRP1_DisableClockLowPower\n
633 * AHB1LPENR FLITFLPEN LL_AHB1_GRP1_DisableClockLowPower\n
634 * AHB1LPENR SRAM1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
635 * AHB1LPENR SRAM2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
636 * AHB1LPENR BKPSRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
637 * AHB1LPENR DTCMRAMLPEN LL_AHB1_GRP1_DisableClockLowPower\n
638 * AHB1LPENR DMA1LPEN LL_AHB1_GRP1_DisableClockLowPower\n
639 * AHB1LPENR DMA2LPEN LL_AHB1_GRP1_DisableClockLowPower\n
640 * AHB1LPENR DMA2DLPEN LL_AHB1_GRP1_DisableClockLowPower\n
641 * AHB1LPENR ETHMACLPEN LL_AHB1_GRP1_DisableClockLowPower\n
642 * AHB1LPENR ETHMACTXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
643 * AHB1LPENR ETHMACRXLPEN LL_AHB1_GRP1_DisableClockLowPower\n
644 * AHB1LPENR ETHMACPTPLPEN LL_AHB1_GRP1_DisableClockLowPower\n
645 * AHB1LPENR OTGHSLPEN LL_AHB1_GRP1_DisableClockLowPower\n
646 * AHB1LPENR OTGHSULPILPEN LL_AHB1_GRP1_DisableClockLowPower
647 * @param Periphs This parameter can be a combination of the following values:
648 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOA
649 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOB
650 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOC
651 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOD
652 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOE
653 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOF
654 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOG
655 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOH
656 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOI
657 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOJ (*)
658 * @arg @ref LL_AHB1_GRP1_PERIPH_GPIOK (*)
659 * @arg @ref LL_AHB1_GRP1_PERIPH_CRC
660 * @arg @ref LL_AHB1_GRP1_PERIPH_AXI
661 * @arg @ref LL_AHB1_GRP1_PERIPH_FLITF
662 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM1
663 * @arg @ref LL_AHB1_GRP1_PERIPH_SRAM2
664 * @arg @ref LL_AHB1_GRP1_PERIPH_BKPSRAM
665 * @arg @ref LL_AHB1_GRP1_PERIPH_DTCMRAM
666 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA1
667 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2
668 * @arg @ref LL_AHB1_GRP1_PERIPH_DMA2D (*)
669 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMAC (*)
670 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACTX (*)
671 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACRX (*)
672 * @arg @ref LL_AHB1_GRP1_PERIPH_ETHMACPTP (*)
673 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHS
674 * @arg @ref LL_AHB1_GRP1_PERIPH_OTGHSULPI
675 *
676 * (*) value not defined in all devices.
677 * @retval None
678 */
679 __STATIC_INLINE void LL_AHB1_GRP1_DisableClockLowPower(uint32_t Periphs)
680 {
681 CLEAR_BIT(RCC->AHB1LPENR, Periphs);
682 }
683
684 /**
685 * @}
686 */
687
688 /** @defgroup BUS_LL_EF_AHB2 AHB2
689 * @{
690 */
691
692 /**
693 * @brief Enable AHB2 peripherals clock.
694 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_EnableClock\n
695 * AHB2ENR JPEGEN LL_AHB2_GRP1_EnableClock\n
696 * AHB2ENR CRYPEN LL_AHB2_GRP1_EnableClock\n
697 * AHB2ENR AESEN LL_AHB2_GRP1_EnableClock\n
698 * AHB2ENR HASHEN LL_AHB2_GRP1_EnableClock\n
699 * AHB2ENR RNGEN LL_AHB2_GRP1_EnableClock\n
700 * AHB2ENR OTGFSEN LL_AHB2_GRP1_EnableClock
701 * @param Periphs This parameter can be a combination of the following values:
702 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
703 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
704 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
705 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
706 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
707 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
708 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
709 *
710 * (*) value not defined in all devices.
711 * @retval None
712 */
713 __STATIC_INLINE void LL_AHB2_GRP1_EnableClock(uint32_t Periphs)
714 {
715 __IO uint32_t tmpreg;
716 SET_BIT(RCC->AHB2ENR, Periphs);
717 /* Delay after an RCC peripheral clock enabling */
718 tmpreg = READ_BIT(RCC->AHB2ENR, Periphs);
719 (void)tmpreg;
720 }
721
722 /**
723 * @brief Check if AHB2 peripheral clock is enabled or not
724 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_IsEnabledClock\n
725 * AHB2ENR JPEGEN LL_AHB2_GRP1_IsEnabledClock\n
726 * AHB2ENR CRYPEN LL_AHB2_GRP1_IsEnabledClock\n
727 * AHB2ENR AESEN LL_AHB2_GRP1_IsEnabledClock\n
728 * AHB2ENR HASHEN LL_AHB2_GRP1_IsEnabledClock\n
729 * AHB2ENR RNGEN LL_AHB2_GRP1_IsEnabledClock\n
730 * AHB2ENR OTGFSEN LL_AHB2_GRP1_IsEnabledClock
731 * @param Periphs This parameter can be a combination of the following values:
732 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
733 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
734 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
735 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
736 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
737 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
738 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
739 *
740 * (*) value not defined in all devices.
741 * @retval State of Periphs (1 or 0).
742 */
743 __STATIC_INLINE uint32_t LL_AHB2_GRP1_IsEnabledClock(uint32_t Periphs)
744 {
745 return (READ_BIT(RCC->AHB2ENR, Periphs) == Periphs);
746 }
747
748 /**
749 * @brief Disable AHB2 peripherals clock.
750 * @rmtoll AHB2ENR DCMIEN LL_AHB2_GRP1_DisableClock\n
751 * AHB2ENR JPEGEN LL_AHB2_GRP1_DisableClock\n
752 * AHB2ENR CRYPEN LL_AHB2_GRP1_DisableClock\n
753 * AHB2ENR AESEN LL_AHB2_GRP1_DisableClock\n
754 * AHB2ENR HASHEN LL_AHB2_GRP1_DisableClock\n
755 * AHB2ENR RNGEN LL_AHB2_GRP1_DisableClock\n
756 * AHB2ENR OTGFSEN LL_AHB2_GRP1_DisableClock
757 * @param Periphs This parameter can be a combination of the following values:
758 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
759 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
760 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
761 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
762 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
763 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
764 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
765 *
766 * (*) value not defined in all devices.
767 * @retval None
768 */
769 __STATIC_INLINE void LL_AHB2_GRP1_DisableClock(uint32_t Periphs)
770 {
771 CLEAR_BIT(RCC->AHB2ENR, Periphs);
772 }
773
774 /**
775 * @brief Force AHB2 peripherals reset.
776 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ForceReset\n
777 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ForceReset\n
778 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ForceReset\n
779 * AHB2RSTR AESRST LL_AHB2_GRP1_ForceReset\n
780 * AHB2RSTR HASHRST LL_AHB2_GRP1_ForceReset\n
781 * AHB2RSTR RNGRST LL_AHB2_GRP1_ForceReset\n
782 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ForceReset
783 * @param Periphs This parameter can be a combination of the following values:
784 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
785 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
786 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
787 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
788 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
789 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
790 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
791 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
792 *
793 * (*) value not defined in all devices.
794 * @retval None
795 */
796 __STATIC_INLINE void LL_AHB2_GRP1_ForceReset(uint32_t Periphs)
797 {
798 SET_BIT(RCC->AHB2RSTR, Periphs);
799 }
800
801 /**
802 * @brief Release AHB2 peripherals reset.
803 * @rmtoll AHB2RSTR DCMIRST LL_AHB2_GRP1_ReleaseReset\n
804 * AHB2RSTR JPEGRST LL_AHB2_GRP1_ReleaseReset\n
805 * AHB2RSTR CRYPRST LL_AHB2_GRP1_ReleaseReset\n
806 * AHB2RSTR AESRST LL_AHB2_GRP1_ReleaseReset\n
807 * AHB2RSTR HASHRST LL_AHB2_GRP1_ReleaseReset\n
808 * AHB2RSTR RNGRST LL_AHB2_GRP1_ReleaseReset\n
809 * AHB2RSTR OTGFSRST LL_AHB2_GRP1_ReleaseReset
810 * @param Periphs This parameter can be a combination of the following values:
811 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
812 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
813 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
814 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
815 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
816 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
817 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
818 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
819 *
820 * (*) value not defined in all devices.
821 * @retval None
822 */
823 __STATIC_INLINE void LL_AHB2_GRP1_ReleaseReset(uint32_t Periphs)
824 {
825 CLEAR_BIT(RCC->AHB2RSTR, Periphs);
826 }
827
828 /**
829 * @brief Enable AHB2 peripheral clocks in low-power mode
830 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_EnableClockLowPower\n
831 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
832 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_EnableClockLowPower\n
833 * AHB2LPENR AESLPEN LL_AHB2_GRP1_EnableClockLowPower\n
834 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_EnableClockLowPower\n
835 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_EnableClockLowPower\n
836 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_EnableClockLowPower
837 * @param Periphs This parameter can be a combination of the following values:
838 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
839 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
840 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
841 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
842 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
843 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
844 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
845 *
846 * (*) value not defined in all devices.
847 * @retval None
848 */
849 __STATIC_INLINE void LL_AHB2_GRP1_EnableClockLowPower(uint32_t Periphs)
850 {
851 __IO uint32_t tmpreg;
852 SET_BIT(RCC->AHB2LPENR, Periphs);
853 /* Delay after an RCC peripheral clock enabling */
854 tmpreg = READ_BIT(RCC->AHB2LPENR, Periphs);
855 (void)tmpreg;
856 }
857
858 /**
859 * @brief Disable AHB2 peripheral clocks in low-power mode
860 * @rmtoll AHB2LPENR DCMILPEN LL_AHB2_GRP1_DisableClockLowPower\n
861 * AHB2LPENR JPEGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
862 * AHB2LPENR CRYPLPEN LL_AHB2_GRP1_DisableClockLowPower\n
863 * AHB2LPENR AESLPEN LL_AHB2_GRP1_DisableClockLowPower\n
864 * AHB2LPENR HASHLPEN LL_AHB2_GRP1_DisableClockLowPower\n
865 * AHB2LPENR RNGLPEN LL_AHB2_GRP1_DisableClockLowPower\n
866 * AHB2LPENR OTGFSLPEN LL_AHB2_GRP1_DisableClockLowPower
867 * @param Periphs This parameter can be a combination of the following values:
868 * @arg @ref LL_AHB2_GRP1_PERIPH_DCMI (*)
869 * @arg @ref LL_AHB2_GRP1_PERIPH_JPEG (*)
870 * @arg @ref LL_AHB2_GRP1_PERIPH_CRYP (*)
871 * @arg @ref LL_AHB2_GRP1_PERIPH_AES (*)
872 * @arg @ref LL_AHB2_GRP1_PERIPH_HASH (*)
873 * @arg @ref LL_AHB2_GRP1_PERIPH_RNG
874 * @arg @ref LL_AHB2_GRP1_PERIPH_OTGFS
875 *
876 * (*) value not defined in all devices.
877 * @retval None
878 */
879 __STATIC_INLINE void LL_AHB2_GRP1_DisableClockLowPower(uint32_t Periphs)
880 {
881 CLEAR_BIT(RCC->AHB2LPENR, Periphs);
882 }
883
884 /**
885 * @}
886 */
887
888 /** @defgroup BUS_LL_EF_AHB3 AHB3
889 * @{
890 */
891
892 /**
893 * @brief Enable AHB3 peripherals clock.
894 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_EnableClock\n
895 * AHB3ENR QSPIEN LL_AHB3_GRP1_EnableClock
896 * @param Periphs This parameter can be a combination of the following values:
897 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
898 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
899 *
900 * (*) value not defined in all devices.
901 * @retval None
902 */
903 __STATIC_INLINE void LL_AHB3_GRP1_EnableClock(uint32_t Periphs)
904 {
905 __IO uint32_t tmpreg;
906 SET_BIT(RCC->AHB3ENR, Periphs);
907 /* Delay after an RCC peripheral clock enabling */
908 tmpreg = READ_BIT(RCC->AHB3ENR, Periphs);
909 (void)tmpreg;
910 }
911
912 /**
913 * @brief Check if AHB3 peripheral clock is enabled or not
914 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_IsEnabledClock\n
915 * AHB3ENR QSPIEN LL_AHB3_GRP1_IsEnabledClock
916 * @param Periphs This parameter can be a combination of the following values:
917 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
918 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
919 *
920 * (*) value not defined in all devices.
921 * @retval State of Periphs (1 or 0).
922 */
923 __STATIC_INLINE uint32_t LL_AHB3_GRP1_IsEnabledClock(uint32_t Periphs)
924 {
925 return (READ_BIT(RCC->AHB3ENR, Periphs) == Periphs);
926 }
927
928 /**
929 * @brief Disable AHB3 peripherals clock.
930 * @rmtoll AHB3ENR FMCEN LL_AHB3_GRP1_DisableClock\n
931 * AHB3ENR QSPIEN LL_AHB3_GRP1_DisableClock
932 * @param Periphs This parameter can be a combination of the following values:
933 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
934 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
935 *
936 * (*) value not defined in all devices.
937 * @retval None
938 */
939 __STATIC_INLINE void LL_AHB3_GRP1_DisableClock(uint32_t Periphs)
940 {
941 CLEAR_BIT(RCC->AHB3ENR, Periphs);
942 }
943
944 /**
945 * @brief Force AHB3 peripherals reset.
946 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ForceReset\n
947 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ForceReset
948 * @param Periphs This parameter can be a combination of the following values:
949 * @arg @ref LL_AHB3_GRP1_PERIPH_ALL
950 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
951 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
952 *
953 * (*) value not defined in all devices.
954 * @retval None
955 */
956 __STATIC_INLINE void LL_AHB3_GRP1_ForceReset(uint32_t Periphs)
957 {
958 SET_BIT(RCC->AHB3RSTR, Periphs);
959 }
960
961 /**
962 * @brief Release AHB3 peripherals reset.
963 * @rmtoll AHB3RSTR FMCRST LL_AHB3_GRP1_ReleaseReset\n
964 * AHB3RSTR QSPIRST LL_AHB3_GRP1_ReleaseReset
965 * @param Periphs This parameter can be a combination of the following values:
966 * @arg @ref LL_AHB2_GRP1_PERIPH_ALL
967 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
968 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
969 *
970 * (*) value not defined in all devices.
971 * @retval None
972 */
973 __STATIC_INLINE void LL_AHB3_GRP1_ReleaseReset(uint32_t Periphs)
974 {
975 CLEAR_BIT(RCC->AHB3RSTR, Periphs);
976 }
977
978 /**
979 * @brief Enable AHB3 peripheral clocks in low-power mode
980 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_EnableClockLowPower\n
981 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_EnableClockLowPower
982 * @param Periphs This parameter can be a combination of the following values:
983 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
984 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
985 *
986 * (*) value not defined in all devices.
987 * @retval None
988 */
989 __STATIC_INLINE void LL_AHB3_GRP1_EnableClockLowPower(uint32_t Periphs)
990 {
991 __IO uint32_t tmpreg;
992 SET_BIT(RCC->AHB3LPENR, Periphs);
993 /* Delay after an RCC peripheral clock enabling */
994 tmpreg = READ_BIT(RCC->AHB3LPENR, Periphs);
995 (void)tmpreg;
996 }
997
998 /**
999 * @brief Disable AHB3 peripheral clocks in low-power mode
1000 * @rmtoll AHB3LPENR FMCLPEN LL_AHB3_GRP1_DisableClockLowPower\n
1001 * AHB3LPENR QSPILPEN LL_AHB3_GRP1_DisableClockLowPower
1002 * @param Periphs This parameter can be a combination of the following values:
1003 * @arg @ref LL_AHB3_GRP1_PERIPH_FMC (*)
1004 * @arg @ref LL_AHB3_GRP1_PERIPH_QSPI
1005 *
1006 * (*) value not defined in all devices.
1007 * @retval None
1008 */
1009 __STATIC_INLINE void LL_AHB3_GRP1_DisableClockLowPower(uint32_t Periphs)
1010 {
1011 CLEAR_BIT(RCC->AHB3LPENR, Periphs);
1012 }
1013
1014 /**
1015 * @}
1016 */
1017
1018 /** @defgroup BUS_LL_EF_APB1 APB1
1019 * @{
1020 */
1021
1022 /**
1023 * @brief Enable APB1 peripherals clock.
1024 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_EnableClock\n
1025 * APB1ENR TIM3EN LL_APB1_GRP1_EnableClock\n
1026 * APB1ENR TIM4EN LL_APB1_GRP1_EnableClock\n
1027 * APB1ENR TIM5EN LL_APB1_GRP1_EnableClock\n
1028 * APB1ENR TIM6EN LL_APB1_GRP1_EnableClock\n
1029 * APB1ENR TIM7EN LL_APB1_GRP1_EnableClock\n
1030 * APB1ENR TIM12EN LL_APB1_GRP1_EnableClock\n
1031 * APB1ENR TIM13EN LL_APB1_GRP1_EnableClock\n
1032 * APB1ENR TIM14EN LL_APB1_GRP1_EnableClock\n
1033 * APB1ENR LPTIM1EN LL_APB1_GRP1_EnableClock\n
1034 * APB1ENR WWDGEN LL_APB1_GRP1_EnableClock\n
1035 * APB1ENR SPI2EN LL_APB1_GRP1_EnableClock\n
1036 * APB1ENR SPI3EN LL_APB1_GRP1_EnableClock\n
1037 * APB1ENR SPDIFRXEN LL_APB1_GRP1_EnableClock\n
1038 * APB1ENR USART2EN LL_APB1_GRP1_EnableClock\n
1039 * APB1ENR USART3EN LL_APB1_GRP1_EnableClock\n
1040 * APB1ENR UART4EN LL_APB1_GRP1_EnableClock\n
1041 * APB1ENR UART5EN LL_APB1_GRP1_EnableClock\n
1042 * APB1ENR I2C1EN LL_APB1_GRP1_EnableClock\n
1043 * APB1ENR I2C2EN LL_APB1_GRP1_EnableClock\n
1044 * APB1ENR I2C3EN LL_APB1_GRP1_EnableClock\n
1045 * APB1ENR I2C4EN LL_APB1_GRP1_EnableClock\n
1046 * APB1ENR CAN1EN LL_APB1_GRP1_EnableClock\n
1047 * APB1ENR CAN2EN LL_APB1_GRP1_EnableClock\n
1048 * APB1ENR CAN3EN LL_APB1_GRP1_EnableClock\n
1049 * APB1ENR CECEN LL_APB1_GRP1_EnableClock\n
1050 * APB1ENR PWREN LL_APB1_GRP1_EnableClock\n
1051 * APB1ENR DACEN LL_APB1_GRP1_EnableClock\n
1052 * APB1ENR UART7EN LL_APB1_GRP1_EnableClock\n
1053 * APB1ENR UART8EN LL_APB1_GRP1_EnableClock\n
1054 * APB1ENR RTCEN LL_APB1_GRP1_EnableClock
1055 * @param Periphs This parameter can be a combination of the following values:
1056 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1057 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1058 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1059 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1060 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1061 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1062 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1063 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1064 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1065 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1066 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1067 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1068 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1069 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1070 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1071 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1072 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1073 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1074 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1075 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1076 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1077 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1078 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1079 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1080 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1081 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1082 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1083 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1084 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1085 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1086 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1087 *
1088 * (*) value not defined in all devices.
1089 * @retval None
1090 */
1091 __STATIC_INLINE void LL_APB1_GRP1_EnableClock(uint32_t Periphs)
1092 {
1093 __IO uint32_t tmpreg;
1094 SET_BIT(RCC->APB1ENR, Periphs);
1095 /* Delay after an RCC peripheral clock enabling */
1096 tmpreg = READ_BIT(RCC->APB1ENR, Periphs);
1097 (void)tmpreg;
1098 }
1099
1100 /**
1101 * @brief Check if APB1 peripheral clock is enabled or not
1102 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_IsEnabledClock\n
1103 * APB1ENR TIM3EN LL_APB1_GRP1_IsEnabledClock\n
1104 * APB1ENR TIM4EN LL_APB1_GRP1_IsEnabledClock\n
1105 * APB1ENR TIM5EN LL_APB1_GRP1_IsEnabledClock\n
1106 * APB1ENR TIM6EN LL_APB1_GRP1_IsEnabledClock\n
1107 * APB1ENR TIM7EN LL_APB1_GRP1_IsEnabledClock\n
1108 * APB1ENR TIM12EN LL_APB1_GRP1_IsEnabledClock\n
1109 * APB1ENR TIM13EN LL_APB1_GRP1_IsEnabledClock\n
1110 * APB1ENR TIM14EN LL_APB1_GRP1_IsEnabledClock\n
1111 * APB1ENR LPTIM1EN LL_APB1_GRP1_IsEnabledClock\n
1112 * APB1ENR WWDGEN LL_APB1_GRP1_IsEnabledClock\n
1113 * APB1ENR SPI2EN LL_APB1_GRP1_IsEnabledClock\n
1114 * APB1ENR SPI3EN LL_APB1_GRP1_IsEnabledClock\n
1115 * APB1ENR SPDIFRXEN LL_APB1_GRP1_IsEnabledClock\n
1116 * APB1ENR USART2EN LL_APB1_GRP1_IsEnabledClock\n
1117 * APB1ENR USART3EN LL_APB1_GRP1_IsEnabledClock\n
1118 * APB1ENR UART4EN LL_APB1_GRP1_IsEnabledClock\n
1119 * APB1ENR UART5EN LL_APB1_GRP1_IsEnabledClock\n
1120 * APB1ENR I2C1EN LL_APB1_GRP1_IsEnabledClock\n
1121 * APB1ENR I2C2EN LL_APB1_GRP1_IsEnabledClock\n
1122 * APB1ENR I2C3EN LL_APB1_GRP1_IsEnabledClock\n
1123 * APB1ENR I2C4EN LL_APB1_GRP1_IsEnabledClock\n
1124 * APB1ENR CAN1EN LL_APB1_GRP1_IsEnabledClock\n
1125 * APB1ENR CAN2EN LL_APB1_GRP1_IsEnabledClock\n
1126 * APB1ENR CAN3EN LL_APB1_GRP1_IsEnabledClock\n
1127 * APB1ENR CECEN LL_APB1_GRP1_IsEnabledClock\n
1128 * APB1ENR PWREN LL_APB1_GRP1_IsEnabledClock\n
1129 * APB1ENR DACEN LL_APB1_GRP1_IsEnabledClock\n
1130 * APB1ENR UART7EN LL_APB1_GRP1_IsEnabledClock\n
1131 * APB1ENR UART8EN LL_APB1_GRP1_IsEnabledClock\n
1132 * APB1ENR RTCEN LL_APB1_GRP1_IsEnabledClock
1133 * @param Periphs This parameter can be a combination of the following values:
1134 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1135 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1136 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1137 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1138 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1139 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1140 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1141 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1142 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1143 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1144 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1145 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1146 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1147 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1148 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1149 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1150 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1151 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1152 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1153 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1154 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1155 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1156 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1157 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1158 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1159 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1160 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1161 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1162 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1163 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1164 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1165 *
1166 * (*) value not defined in all devices.
1167 * @retval State of Periphs (1 or 0).
1168 */
1169 __STATIC_INLINE uint32_t LL_APB1_GRP1_IsEnabledClock(uint32_t Periphs)
1170 {
1171 return (READ_BIT(RCC->APB1ENR, Periphs) == Periphs);
1172 }
1173
1174 /**
1175 * @brief Disable APB1 peripherals clock.
1176 * @rmtoll APB1ENR TIM2EN LL_APB1_GRP1_DisableClock\n
1177 * APB1ENR TIM3EN LL_APB1_GRP1_DisableClock\n
1178 * APB1ENR TIM4EN LL_APB1_GRP1_DisableClock\n
1179 * APB1ENR TIM5EN LL_APB1_GRP1_DisableClock\n
1180 * APB1ENR TIM6EN LL_APB1_GRP1_DisableClock\n
1181 * APB1ENR TIM7EN LL_APB1_GRP1_DisableClock\n
1182 * APB1ENR TIM12EN LL_APB1_GRP1_DisableClock\n
1183 * APB1ENR TIM13EN LL_APB1_GRP1_DisableClock\n
1184 * APB1ENR TIM14EN LL_APB1_GRP1_DisableClock\n
1185 * APB1ENR LPTIM1EN LL_APB1_GRP1_DisableClock\n
1186 * APB1ENR WWDGEN LL_APB1_GRP1_DisableClock\n
1187 * APB1ENR SPI2EN LL_APB1_GRP1_DisableClock\n
1188 * APB1ENR SPI3EN LL_APB1_GRP1_DisableClock\n
1189 * APB1ENR SPDIFRXEN LL_APB1_GRP1_DisableClock\n
1190 * APB1ENR USART2EN LL_APB1_GRP1_DisableClock\n
1191 * APB1ENR USART3EN LL_APB1_GRP1_DisableClock\n
1192 * APB1ENR UART4EN LL_APB1_GRP1_DisableClock\n
1193 * APB1ENR UART5EN LL_APB1_GRP1_DisableClock\n
1194 * APB1ENR I2C1EN LL_APB1_GRP1_DisableClock\n
1195 * APB1ENR I2C2EN LL_APB1_GRP1_DisableClock\n
1196 * APB1ENR I2C3EN LL_APB1_GRP1_DisableClock\n
1197 * APB1ENR I2C4EN LL_APB1_GRP1_DisableClock\n
1198 * APB1ENR CAN1EN LL_APB1_GRP1_DisableClock\n
1199 * APB1ENR CAN2EN LL_APB1_GRP1_DisableClock\n
1200 * APB1ENR CAN3EN LL_APB1_GRP1_DisableClock\n
1201 * APB1ENR CECEN LL_APB1_GRP1_DisableClock\n
1202 * APB1ENR PWREN LL_APB1_GRP1_DisableClock\n
1203 * APB1ENR DACEN LL_APB1_GRP1_DisableClock\n
1204 * APB1ENR UART7EN LL_APB1_GRP1_DisableClock\n
1205 * APB1ENR UART8EN LL_APB1_GRP1_DisableClock\n
1206 * APB1ENR RTCEN LL_APB1_GRP1_DisableClock
1207 * @param Periphs This parameter can be a combination of the following values:
1208 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1209 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1210 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1211 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1212 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1213 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1214 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1215 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1216 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1217 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1218 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1219 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1220 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1221 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1222 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1223 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1224 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1225 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1226 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1227 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1228 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1229 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1230 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1231 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1232 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1233 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1234 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1235 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1236 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1237 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1238 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1239 *
1240 * (*) value not defined in all devices.
1241 * @retval None
1242 */
1243 __STATIC_INLINE void LL_APB1_GRP1_DisableClock(uint32_t Periphs)
1244 {
1245 CLEAR_BIT(RCC->APB1ENR, Periphs);
1246 }
1247
1248 /**
1249 * @brief Force APB1 peripherals reset.
1250 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ForceReset\n
1251 * APB1RSTR TIM3RST LL_APB1_GRP1_ForceReset\n
1252 * APB1RSTR TIM4RST LL_APB1_GRP1_ForceReset\n
1253 * APB1RSTR TIM5RST LL_APB1_GRP1_ForceReset\n
1254 * APB1RSTR TIM6RST LL_APB1_GRP1_ForceReset\n
1255 * APB1RSTR TIM7RST LL_APB1_GRP1_ForceReset\n
1256 * APB1RSTR TIM12RST LL_APB1_GRP1_ForceReset\n
1257 * APB1RSTR TIM13RST LL_APB1_GRP1_ForceReset\n
1258 * APB1RSTR TIM14RST LL_APB1_GRP1_ForceReset\n
1259 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ForceReset\n
1260 * APB1RSTR WWDGRST LL_APB1_GRP1_ForceReset\n
1261 * APB1RSTR SPI2RST LL_APB1_GRP1_ForceReset\n
1262 * APB1RSTR SPI3RST LL_APB1_GRP1_ForceReset\n
1263 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ForceReset\n
1264 * APB1RSTR USART2RST LL_APB1_GRP1_ForceReset\n
1265 * APB1RSTR USART3RST LL_APB1_GRP1_ForceReset\n
1266 * APB1RSTR UART4RST LL_APB1_GRP1_ForceReset\n
1267 * APB1RSTR UART5RST LL_APB1_GRP1_ForceReset\n
1268 * APB1RSTR I2C1RST LL_APB1_GRP1_ForceReset\n
1269 * APB1RSTR I2C2RST LL_APB1_GRP1_ForceReset\n
1270 * APB1RSTR I2C3RST LL_APB1_GRP1_ForceReset\n
1271 * APB1RSTR I2C4RST LL_APB1_GRP1_ForceReset\n
1272 * APB1RSTR CAN1RST LL_APB1_GRP1_ForceReset\n
1273 * APB1RSTR CAN2RST LL_APB1_GRP1_ForceReset\n
1274 * APB1RSTR CAN3RST LL_APB1_GRP1_ForceReset\n
1275 * APB1RSTR CECRST LL_APB1_GRP1_ForceReset\n
1276 * APB1RSTR PWRRST LL_APB1_GRP1_ForceReset\n
1277 * APB1RSTR DACRST LL_APB1_GRP1_ForceReset\n
1278 * APB1RSTR UART7RST LL_APB1_GRP1_ForceReset\n
1279 * APB1RSTR UART8RST LL_APB1_GRP1_ForceReset
1280 * @param Periphs This parameter can be a combination of the following values:
1281 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1282 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1283 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1284 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1285 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1286 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1287 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1288 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1289 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1290 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1291 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1292 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1293 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1294 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1295 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1296 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1297 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1298 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1299 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1300 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1301 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1302 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1303 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1304 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1305 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1306 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1307 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1308 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1309 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1310 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1311 *
1312 * (*) value not defined in all devices.
1313 * @retval None
1314 */
1315 __STATIC_INLINE void LL_APB1_GRP1_ForceReset(uint32_t Periphs)
1316 {
1317 SET_BIT(RCC->APB1RSTR, Periphs);
1318 }
1319
1320 /**
1321 * @brief Release APB1 peripherals reset.
1322 * @rmtoll APB1RSTR TIM2RST LL_APB1_GRP1_ReleaseReset\n
1323 * APB1RSTR TIM3RST LL_APB1_GRP1_ReleaseReset\n
1324 * APB1RSTR TIM4RST LL_APB1_GRP1_ReleaseReset\n
1325 * APB1RSTR TIM5RST LL_APB1_GRP1_ReleaseReset\n
1326 * APB1RSTR TIM6RST LL_APB1_GRP1_ReleaseReset\n
1327 * APB1RSTR TIM7RST LL_APB1_GRP1_ReleaseReset\n
1328 * APB1RSTR TIM12RST LL_APB1_GRP1_ReleaseReset\n
1329 * APB1RSTR TIM13RST LL_APB1_GRP1_ReleaseReset\n
1330 * APB1RSTR TIM14RST LL_APB1_GRP1_ReleaseReset\n
1331 * APB1RSTR LPTIM1RST LL_APB1_GRP1_ReleaseReset\n
1332 * APB1RSTR WWDGRST LL_APB1_GRP1_ReleaseReset\n
1333 * APB1RSTR SPI2RST LL_APB1_GRP1_ReleaseReset\n
1334 * APB1RSTR SPI3RST LL_APB1_GRP1_ReleaseReset\n
1335 * APB1RSTR SPDIFRXRST LL_APB1_GRP1_ReleaseReset\n
1336 * APB1RSTR USART2RST LL_APB1_GRP1_ReleaseReset\n
1337 * APB1RSTR USART3RST LL_APB1_GRP1_ReleaseReset\n
1338 * APB1RSTR UART4RST LL_APB1_GRP1_ReleaseReset\n
1339 * APB1RSTR UART5RST LL_APB1_GRP1_ReleaseReset\n
1340 * APB1RSTR I2C1RST LL_APB1_GRP1_ReleaseReset\n
1341 * APB1RSTR I2C2RST LL_APB1_GRP1_ReleaseReset\n
1342 * APB1RSTR I2C3RST LL_APB1_GRP1_ReleaseReset\n
1343 * APB1RSTR I2C4RST LL_APB1_GRP1_ReleaseReset\n
1344 * APB1RSTR CAN1RST LL_APB1_GRP1_ReleaseReset\n
1345 * APB1RSTR CAN2RST LL_APB1_GRP1_ReleaseReset\n
1346 * APB1RSTR CAN3RST LL_APB1_GRP1_ReleaseReset\n
1347 * APB1RSTR CECRST LL_APB1_GRP1_ReleaseReset\n
1348 * APB1RSTR PWRRST LL_APB1_GRP1_ReleaseReset\n
1349 * APB1RSTR DACRST LL_APB1_GRP1_ReleaseReset\n
1350 * APB1RSTR UART7RST LL_APB1_GRP1_ReleaseReset\n
1351 * APB1RSTR UART8RST LL_APB1_GRP1_ReleaseReset
1352 * @param Periphs This parameter can be a combination of the following values:
1353 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1354 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1355 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1356 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1357 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1358 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1359 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1360 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1361 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1362 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1363 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1364 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1365 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1366 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1367 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1368 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1369 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1370 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1371 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1372 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1373 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1374 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1375 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1376 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1377 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1378 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1379 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1380 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1381 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1382 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1383 *
1384 * (*) value not defined in all devices.
1385 * @retval None
1386 */
1387 __STATIC_INLINE void LL_APB1_GRP1_ReleaseReset(uint32_t Periphs)
1388 {
1389 CLEAR_BIT(RCC->APB1RSTR, Periphs);
1390 }
1391
1392 /**
1393 * @brief Enable APB1 peripheral clocks in low-power mode
1394 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1395 * APB1LPENR TIM3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1396 * APB1LPENR TIM4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1397 * APB1LPENR TIM5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1398 * APB1LPENR TIM6LPEN LL_APB1_GRP1_EnableClockLowPower\n
1399 * APB1LPENR TIM7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1400 * APB1LPENR TIM12LPEN LL_APB1_GRP1_EnableClockLowPower\n
1401 * APB1LPENR TIM13LPEN LL_APB1_GRP1_EnableClockLowPower\n
1402 * APB1LPENR TIM14LPEN LL_APB1_GRP1_EnableClockLowPower\n
1403 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1404 * APB1LPENR WWDGLPEN LL_APB1_GRP1_EnableClockLowPower\n
1405 * APB1LPENR SPI2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1406 * APB1LPENR SPI3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1407 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_EnableClockLowPower\n
1408 * APB1LPENR USART2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1409 * APB1LPENR USART3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1410 * APB1LPENR UART4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1411 * APB1LPENR UART5LPEN LL_APB1_GRP1_EnableClockLowPower\n
1412 * APB1LPENR I2C1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1413 * APB1LPENR I2C2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1414 * APB1LPENR I2C3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1415 * APB1LPENR I2C4LPEN LL_APB1_GRP1_EnableClockLowPower\n
1416 * APB1LPENR CAN1LPEN LL_APB1_GRP1_EnableClockLowPower\n
1417 * APB1LPENR CAN2LPEN LL_APB1_GRP1_EnableClockLowPower\n
1418 * APB1LPENR CAN3LPEN LL_APB1_GRP1_EnableClockLowPower\n
1419 * APB1LPENR CECLPEN LL_APB1_GRP1_EnableClockLowPower\n
1420 * APB1LPENR PWRLPEN LL_APB1_GRP1_EnableClockLowPower\n
1421 * APB1LPENR DACLPEN LL_APB1_GRP1_EnableClockLowPower\n
1422 * APB1LPENR UART7LPEN LL_APB1_GRP1_EnableClockLowPower\n
1423 * APB1LPENR UART8LPEN LL_APB1_GRP1_EnableClockLowPower\n
1424 * APB1LPENR RTCLPEN LL_APB1_GRP1_EnableClockLowPower
1425 * @param Periphs This parameter can be a combination of the following values:
1426 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1427 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1428 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1429 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1430 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1431 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1432 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1433 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1434 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1435 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1436 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1437 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1438 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1439 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1440 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1441 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1442 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1443 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1444 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1445 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1446 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1447 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1448 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1449 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1450 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1451 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1452 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1453 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1454 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1455 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1456 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1457 *
1458 * (*) value not defined in all devices.
1459 * @retval None
1460 */
1461 __STATIC_INLINE void LL_APB1_GRP1_EnableClockLowPower(uint32_t Periphs)
1462 {
1463 __IO uint32_t tmpreg;
1464 SET_BIT(RCC->APB1LPENR, Periphs);
1465 /* Delay after an RCC peripheral clock enabling */
1466 tmpreg = READ_BIT(RCC->APB1LPENR, Periphs);
1467 (void)tmpreg;
1468 }
1469
1470 /**
1471 * @brief Disable APB1 peripheral clocks in low-power mode
1472 * @rmtoll APB1LPENR TIM2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1473 * APB1LPENR TIM3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1474 * APB1LPENR TIM4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1475 * APB1LPENR TIM5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1476 * APB1LPENR TIM6LPEN LL_APB1_GRP1_DisableClockLowPower\n
1477 * APB1LPENR TIM7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1478 * APB1LPENR TIM12LPEN LL_APB1_GRP1_DisableClockLowPower\n
1479 * APB1LPENR TIM13LPEN LL_APB1_GRP1_DisableClockLowPower\n
1480 * APB1LPENR TIM14LPEN LL_APB1_GRP1_DisableClockLowPower\n
1481 * APB1LPENR LPTIM1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1482 * APB1LPENR WWDGLPEN LL_APB1_GRP1_DisableClockLowPower\n
1483 * APB1LPENR SPI2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1484 * APB1LPENR SPI3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1485 * APB1LPENR SPDIFRXLPEN LL_APB1_GRP1_DisableClockLowPower\n
1486 * APB1LPENR USART2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1487 * APB1LPENR USART3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1488 * APB1LPENR UART4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1489 * APB1LPENR UART5LPEN LL_APB1_GRP1_DisableClockLowPower\n
1490 * APB1LPENR I2C1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1491 * APB1LPENR I2C2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1492 * APB1LPENR I2C3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1493 * APB1LPENR I2C4LPEN LL_APB1_GRP1_DisableClockLowPower\n
1494 * APB1LPENR CAN1LPEN LL_APB1_GRP1_DisableClockLowPower\n
1495 * APB1LPENR CAN2LPEN LL_APB1_GRP1_DisableClockLowPower\n
1496 * APB1LPENR CAN3LPEN LL_APB1_GRP1_DisableClockLowPower\n
1497 * APB1LPENR CECLPEN LL_APB1_GRP1_DisableClockLowPower\n
1498 * APB1LPENR PWRLPEN LL_APB1_GRP1_DisableClockLowPower\n
1499 * APB1LPENR DACLPEN LL_APB1_GRP1_DisableClockLowPower\n
1500 * APB1LPENR UART7LPEN LL_APB1_GRP1_DisableClockLowPower\n
1501 * APB1LPENR UART8LPEN LL_APB1_GRP1_DisableClockLowPower\n
1502 * APB1LPENR RTCLPEN LL_APB1_GRP1_DisableClockLowPower
1503 * @param Periphs This parameter can be a combination of the following values:
1504 * @arg @ref LL_APB1_GRP1_PERIPH_TIM2
1505 * @arg @ref LL_APB1_GRP1_PERIPH_TIM3
1506 * @arg @ref LL_APB1_GRP1_PERIPH_TIM4
1507 * @arg @ref LL_APB1_GRP1_PERIPH_TIM5
1508 * @arg @ref LL_APB1_GRP1_PERIPH_TIM6
1509 * @arg @ref LL_APB1_GRP1_PERIPH_TIM7
1510 * @arg @ref LL_APB1_GRP1_PERIPH_TIM12
1511 * @arg @ref LL_APB1_GRP1_PERIPH_TIM13
1512 * @arg @ref LL_APB1_GRP1_PERIPH_TIM14
1513 * @arg @ref LL_APB1_GRP1_PERIPH_LPTIM1
1514 * @arg @ref LL_APB1_GRP1_PERIPH_WWDG
1515 * @arg @ref LL_APB1_GRP1_PERIPH_SPI2
1516 * @arg @ref LL_APB1_GRP1_PERIPH_SPI3
1517 * @arg @ref LL_APB1_GRP1_PERIPH_SPDIFRX (*)
1518 * @arg @ref LL_APB1_GRP1_PERIPH_USART2
1519 * @arg @ref LL_APB1_GRP1_PERIPH_USART3
1520 * @arg @ref LL_APB1_GRP1_PERIPH_UART4
1521 * @arg @ref LL_APB1_GRP1_PERIPH_UART5
1522 * @arg @ref LL_APB1_GRP1_PERIPH_I2C1
1523 * @arg @ref LL_APB1_GRP1_PERIPH_I2C2
1524 * @arg @ref LL_APB1_GRP1_PERIPH_I2C3
1525 * @arg @ref LL_APB1_GRP1_PERIPH_I2C4 (*)
1526 * @arg @ref LL_APB1_GRP1_PERIPH_CAN1
1527 * @arg @ref LL_APB1_GRP1_PERIPH_CAN2 (*)
1528 * @arg @ref LL_APB1_GRP1_PERIPH_CAN3 (*)
1529 * @arg @ref LL_APB1_GRP1_PERIPH_CEC (*)
1530 * @arg @ref LL_APB1_GRP1_PERIPH_PWR
1531 * @arg @ref LL_APB1_GRP1_PERIPH_DAC1
1532 * @arg @ref LL_APB1_GRP1_PERIPH_UART7
1533 * @arg @ref LL_APB1_GRP1_PERIPH_UART8
1534 * @arg @ref LL_APB1_GRP1_PERIPH_RTCAPB (*)
1535 *
1536 * (*) value not defined in all devices.
1537 * @retval None
1538 */
1539 __STATIC_INLINE void LL_APB1_GRP1_DisableClockLowPower(uint32_t Periphs)
1540 {
1541 CLEAR_BIT(RCC->APB1LPENR, Periphs);
1542 }
1543
1544 /**
1545 * @}
1546 */
1547
1548 /** @defgroup BUS_LL_EF_APB2 APB2
1549 * @{
1550 */
1551
1552 /**
1553 * @brief Enable APB2 peripherals clock.
1554 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_EnableClock\n
1555 * APB2ENR TIM8EN LL_APB2_GRP1_EnableClock\n
1556 * APB2ENR USART1EN LL_APB2_GRP1_EnableClock\n
1557 * APB2ENR USART6EN LL_APB2_GRP1_EnableClock\n
1558 * APB2ENR ADC1EN LL_APB2_GRP1_EnableClock\n
1559 * APB2ENR ADC2EN LL_APB2_GRP1_EnableClock\n
1560 * APB2ENR ADC3EN LL_APB2_GRP1_EnableClock\n
1561 * APB2ENR SDMMC1EN LL_APB2_GRP1_EnableClock\n
1562 * APB2ENR SDMMC2EN LL_APB2_GRP1_EnableClock\n
1563 * APB2ENR SPI1EN LL_APB2_GRP1_EnableClock\n
1564 * APB2ENR SPI4EN LL_APB2_GRP1_EnableClock\n
1565 * APB2ENR SYSCFGEN LL_APB2_GRP1_EnableClock\n
1566 * APB2ENR TIM9EN LL_APB2_GRP1_EnableClock\n
1567 * APB2ENR TIM10EN LL_APB2_GRP1_EnableClock\n
1568 * APB2ENR TIM11EN LL_APB2_GRP1_EnableClock\n
1569 * APB2ENR SPI5EN LL_APB2_GRP1_EnableClock\n
1570 * APB2ENR SPI6EN LL_APB2_GRP1_EnableClock\n
1571 * APB2ENR SAI1EN LL_APB2_GRP1_EnableClock\n
1572 * APB2ENR SAI2EN LL_APB2_GRP1_EnableClock\n
1573 * APB2ENR LTDCEN LL_APB2_GRP1_EnableClock\n
1574 * APB2ENR DSIEN LL_APB2_GRP1_EnableClock\n
1575 * APB2ENR DFSDM1EN LL_APB2_GRP1_EnableClock\n
1576 * APB2ENR MDIOEN LL_APB2_GRP1_EnableClock\n
1577 * APB2ENR OTGPHYCEN LL_APB2_GRP1_EnableClock
1578 * @param Periphs This parameter can be a combination of the following values:
1579 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1580 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1581 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1582 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1583 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1584 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1585 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1586 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1587 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1588 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1589 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1590 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1591 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1592 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1593 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1594 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1595 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1596 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1597 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1598 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1599 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1600 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1601 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1602 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1603 *
1604 * (*) value not defined in all devices.
1605 * @retval None
1606 */
1607 __STATIC_INLINE void LL_APB2_GRP1_EnableClock(uint32_t Periphs)
1608 {
1609 __IO uint32_t tmpreg;
1610 SET_BIT(RCC->APB2ENR, Periphs);
1611 /* Delay after an RCC peripheral clock enabling */
1612 tmpreg = READ_BIT(RCC->APB2ENR, Periphs);
1613 (void)tmpreg;
1614 }
1615
1616 /**
1617 * @brief Check if APB2 peripheral clock is enabled or not
1618 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_IsEnabledClock\n
1619 * APB2ENR TIM8EN LL_APB2_GRP1_IsEnabledClock\n
1620 * APB2ENR USART1EN LL_APB2_GRP1_IsEnabledClock\n
1621 * APB2ENR USART6EN LL_APB2_GRP1_IsEnabledClock\n
1622 * APB2ENR ADC1EN LL_APB2_GRP1_IsEnabledClock\n
1623 * APB2ENR ADC2EN LL_APB2_GRP1_IsEnabledClock\n
1624 * APB2ENR ADC3EN LL_APB2_GRP1_IsEnabledClock\n
1625 * APB2ENR SDMMC1EN LL_APB2_GRP1_IsEnabledClock\n
1626 * APB2ENR SDMMC2EN LL_APB2_GRP1_IsEnabledClock\n
1627 * APB2ENR SPI1EN LL_APB2_GRP1_IsEnabledClock\n
1628 * APB2ENR SPI4EN LL_APB2_GRP1_IsEnabledClock\n
1629 * APB2ENR SYSCFGEN LL_APB2_GRP1_IsEnabledClock\n
1630 * APB2ENR TIM9EN LL_APB2_GRP1_IsEnabledClock\n
1631 * APB2ENR TIM10EN LL_APB2_GRP1_IsEnabledClock\n
1632 * APB2ENR TIM11EN LL_APB2_GRP1_IsEnabledClock\n
1633 * APB2ENR SPI5EN LL_APB2_GRP1_IsEnabledClock\n
1634 * APB2ENR SPI6EN LL_APB2_GRP1_IsEnabledClock\n
1635 * APB2ENR SAI1EN LL_APB2_GRP1_IsEnabledClock\n
1636 * APB2ENR SAI2EN LL_APB2_GRP1_IsEnabledClock\n
1637 * APB2ENR LTDCEN LL_APB2_GRP1_IsEnabledClock\n
1638 * APB2ENR DSIEN LL_APB2_GRP1_IsEnabledClock\n
1639 * APB2ENR DFSDM1EN LL_APB2_GRP1_IsEnabledClock\n
1640 * APB2ENR MDIOEN LL_APB2_GRP1_IsEnabledClock\n
1641 * APB2ENR OTGPHYCEN LL_APB2_GRP1_IsEnabledClock
1642 * @param Periphs This parameter can be a combination of the following values:
1643 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1644 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1645 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1646 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1647 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1648 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1649 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1650 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1651 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1652 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1653 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1654 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1655 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1656 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1657 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1658 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1659 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1660 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1661 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1662 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1663 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1664 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1665 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1666 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1667 *
1668 * (*) value not defined in all devices.
1669 * @retval State of Periphs (1 or 0).
1670 */
1671 __STATIC_INLINE uint32_t LL_APB2_GRP1_IsEnabledClock(uint32_t Periphs)
1672 {
1673 return (READ_BIT(RCC->APB2ENR, Periphs) == Periphs);
1674 }
1675
1676 /**
1677 * @brief Disable APB2 peripherals clock.
1678 * @rmtoll APB2ENR TIM1EN LL_APB2_GRP1_DisableClock\n
1679 * APB2ENR TIM8EN LL_APB2_GRP1_DisableClock\n
1680 * APB2ENR USART1EN LL_APB2_GRP1_DisableClock\n
1681 * APB2ENR USART6EN LL_APB2_GRP1_DisableClock\n
1682 * APB2ENR ADC1EN LL_APB2_GRP1_DisableClock\n
1683 * APB2ENR ADC2EN LL_APB2_GRP1_DisableClock\n
1684 * APB2ENR ADC3EN LL_APB2_GRP1_DisableClock\n
1685 * APB2ENR SDMMC1EN LL_APB2_GRP1_DisableClock\n
1686 * APB2ENR SDMMC2EN LL_APB2_GRP1_DisableClock\n
1687 * APB2ENR SPI1EN LL_APB2_GRP1_DisableClock\n
1688 * APB2ENR SPI4EN LL_APB2_GRP1_DisableClock\n
1689 * APB2ENR SYSCFGEN LL_APB2_GRP1_DisableClock\n
1690 * APB2ENR TIM9EN LL_APB2_GRP1_DisableClock\n
1691 * APB2ENR TIM10EN LL_APB2_GRP1_DisableClock\n
1692 * APB2ENR TIM11EN LL_APB2_GRP1_DisableClock\n
1693 * APB2ENR SPI5EN LL_APB2_GRP1_DisableClock\n
1694 * APB2ENR SPI6EN LL_APB2_GRP1_DisableClock\n
1695 * APB2ENR SAI1EN LL_APB2_GRP1_DisableClock\n
1696 * APB2ENR SAI2EN LL_APB2_GRP1_DisableClock\n
1697 * APB2ENR LTDCEN LL_APB2_GRP1_DisableClock\n
1698 * APB2ENR DSIEN LL_APB2_GRP1_DisableClock\n
1699 * APB2ENR DFSDM1EN LL_APB2_GRP1_DisableClock\n
1700 * APB2ENR MDIOEN LL_APB2_GRP1_DisableClock\n
1701 * APB2ENR OTGPHYCEN LL_APB2_GRP1_DisableClock
1702 * @param Periphs This parameter can be a combination of the following values:
1703 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1704 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1705 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1706 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1707 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1708 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1709 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1710 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1711 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1712 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1713 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1714 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1715 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1716 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1717 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1718 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1719 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1720 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1721 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1722 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1723 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1724 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1725 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1726 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1727 *
1728 * (*) value not defined in all devices.
1729 * @retval None
1730 */
1731 __STATIC_INLINE void LL_APB2_GRP1_DisableClock(uint32_t Periphs)
1732 {
1733 CLEAR_BIT(RCC->APB2ENR, Periphs);
1734 }
1735
1736 /**
1737 * @brief Force APB2 peripherals reset.
1738 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ForceReset\n
1739 * APB2RSTR TIM8RST LL_APB2_GRP1_ForceReset\n
1740 * APB2RSTR USART1RST LL_APB2_GRP1_ForceReset\n
1741 * APB2RSTR USART6RST LL_APB2_GRP1_ForceReset\n
1742 * APB2RSTR ADCRST LL_APB2_GRP1_ForceReset\n
1743 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ForceReset\n
1744 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ForceReset\n
1745 * APB2RSTR SPI1RST LL_APB2_GRP1_ForceReset\n
1746 * APB2RSTR SPI4RST LL_APB2_GRP1_ForceReset\n
1747 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ForceReset\n
1748 * APB2RSTR TIM9RST LL_APB2_GRP1_ForceReset\n
1749 * APB2RSTR TIM10RST LL_APB2_GRP1_ForceReset\n
1750 * APB2RSTR TIM11RST LL_APB2_GRP1_ForceReset\n
1751 * APB2RSTR SPI5RST LL_APB2_GRP1_ForceReset\n
1752 * APB2RSTR SPI6RST LL_APB2_GRP1_ForceReset\n
1753 * APB2RSTR SAI1RST LL_APB2_GRP1_ForceReset\n
1754 * APB2RSTR SAI2RST LL_APB2_GRP1_ForceReset\n
1755 * APB2RSTR LTDCRST LL_APB2_GRP1_ForceReset\n
1756 * APB2RSTR DSIRST LL_APB2_GRP1_ForceReset\n
1757 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ForceReset\n
1758 * APB2RSTR MDIORST LL_APB2_GRP1_ForceReset\n
1759 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ForceReset
1760 * @param Periphs This parameter can be a combination of the following values:
1761 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1762 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1763 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1764 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1765 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1766 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1767 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1768 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1769 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1770 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1771 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1772 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1773 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1774 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1775 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1776 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1777 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1778 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1779 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1780 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1781 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1782 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1783 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1784 *
1785 * (*) value not defined in all devices.
1786 * @retval None
1787 */
1788 __STATIC_INLINE void LL_APB2_GRP1_ForceReset(uint32_t Periphs)
1789 {
1790 SET_BIT(RCC->APB2RSTR, Periphs);
1791 }
1792
1793 /**
1794 * @brief Release APB2 peripherals reset.
1795 * @rmtoll APB2RSTR TIM1RST LL_APB2_GRP1_ReleaseReset\n
1796 * APB2RSTR TIM8RST LL_APB2_GRP1_ReleaseReset\n
1797 * APB2RSTR USART1RST LL_APB2_GRP1_ReleaseReset\n
1798 * APB2RSTR USART6RST LL_APB2_GRP1_ReleaseReset\n
1799 * APB2RSTR ADCRST LL_APB2_GRP1_ReleaseReset\n
1800 * APB2RSTR SDMMC1RST LL_APB2_GRP1_ReleaseReset\n
1801 * APB2RSTR SDMMC2RST LL_APB2_GRP1_ReleaseReset\n
1802 * APB2RSTR SPI1RST LL_APB2_GRP1_ReleaseReset\n
1803 * APB2RSTR SPI4RST LL_APB2_GRP1_ReleaseReset\n
1804 * APB2RSTR SYSCFGRST LL_APB2_GRP1_ReleaseReset\n
1805 * APB2RSTR TIM9RST LL_APB2_GRP1_ReleaseReset\n
1806 * APB2RSTR TIM10RST LL_APB2_GRP1_ReleaseReset\n
1807 * APB2RSTR TIM11RST LL_APB2_GRP1_ReleaseReset\n
1808 * APB2RSTR SPI5RST LL_APB2_GRP1_ReleaseReset\n
1809 * APB2RSTR SPI6RST LL_APB2_GRP1_ReleaseReset\n
1810 * APB2RSTR SAI1RST LL_APB2_GRP1_ReleaseReset\n
1811 * APB2RSTR SAI2RST LL_APB2_GRP1_ReleaseReset\n
1812 * APB2RSTR LTDCRST LL_APB2_GRP1_ReleaseReset\n
1813 * APB2RSTR DSIRST LL_APB2_GRP1_ReleaseReset\n
1814 * APB2RSTR DFSDM1RST LL_APB2_GRP1_ReleaseReset\n
1815 * APB2RSTR MDIORST LL_APB2_GRP1_ReleaseReset\n
1816 * APB2RSTR OTGPHYCRST LL_APB2_GRP1_ReleaseReset
1817 * @param Periphs This parameter can be a combination of the following values:
1818 * @arg @ref LL_APB2_GRP1_PERIPH_ALL
1819 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1820 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1821 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1822 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1823 * @arg @ref LL_APB2_GRP1_PERIPH_ADC
1824 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1825 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1826 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1827 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1828 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1829 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1830 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1831 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1832 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1833 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1834 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1835 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1836 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1837 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1838 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1839 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1840 * @arg @ref LL_APB2_GRP1_PERIPH_OTGPHYC (*)
1841 *
1842 * (*) value not defined in all devices.
1843 * @retval None
1844 */
1845 __STATIC_INLINE void LL_APB2_GRP1_ReleaseReset(uint32_t Periphs)
1846 {
1847 CLEAR_BIT(RCC->APB2RSTR, Periphs);
1848 }
1849
1850 /**
1851 * @brief Enable APB2 peripheral clocks in low-power mode
1852 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1853 * APB2LPENR TIM8LPEN LL_APB2_GRP1_EnableClockLowPower\n
1854 * APB2LPENR USART1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1855 * APB2LPENR USART6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1856 * APB2LPENR ADC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1857 * APB2LPENR ADC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1858 * APB2LPENR ADC3LPEN LL_APB2_GRP1_EnableClockLowPower\n
1859 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1860 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1861 * APB2LPENR SPI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1862 * APB2LPENR SPI4LPEN LL_APB2_GRP1_EnableClockLowPower\n
1863 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_EnableClockLowPower\n
1864 * APB2LPENR TIM9LPEN LL_APB2_GRP1_EnableClockLowPower\n
1865 * APB2LPENR TIM10LPEN LL_APB2_GRP1_EnableClockLowPower\n
1866 * APB2LPENR TIM11LPEN LL_APB2_GRP1_EnableClockLowPower\n
1867 * APB2LPENR SPI5LPEN LL_APB2_GRP1_EnableClockLowPower\n
1868 * APB2LPENR SPI6LPEN LL_APB2_GRP1_EnableClockLowPower\n
1869 * APB2LPENR SAI1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1870 * APB2LPENR SAI2LPEN LL_APB2_GRP1_EnableClockLowPower\n
1871 * APB2LPENR LTDCLPEN LL_APB2_GRP1_EnableClockLowPower\n
1872 * APB2LPENR DSILPEN LL_APB2_GRP1_EnableClockLowPower\n
1873 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_EnableClockLowPower\n
1874 * APB2LPENR MDIOLPEN LL_APB2_GRP1_EnableClockLowPower
1875 * @param Periphs This parameter can be a combination of the following values:
1876 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1877 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1878 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1879 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1880 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1881 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1882 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1883 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1884 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC2 (*)
1885 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1886 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1887 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1888 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1889 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1890 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1891 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1892 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1893 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1894 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1895 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1896 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1897 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1898 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1899 *
1900 * (*) value not defined in all devices.
1901 * @retval None
1902 */
1903 __STATIC_INLINE void LL_APB2_GRP1_EnableClockLowPower(uint32_t Periphs)
1904 {
1905 __IO uint32_t tmpreg;
1906 SET_BIT(RCC->APB2LPENR, Periphs);
1907 /* Delay after an RCC peripheral clock enabling */
1908 tmpreg = READ_BIT(RCC->APB2LPENR, Periphs);
1909 (void)tmpreg;
1910 }
1911
1912 /**
1913 * @brief Disable APB2 peripheral clocks in low-power mode
1914 * @rmtoll APB2LPENR TIM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1915 * APB2LPENR TIM8LPEN LL_APB2_GRP1_DisableClockLowPower\n
1916 * APB2LPENR USART1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1917 * APB2LPENR USART6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1918 * APB2LPENR ADC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1919 * APB2LPENR ADC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1920 * APB2LPENR ADC3LPEN LL_APB2_GRP1_DisableClockLowPower\n
1921 * APB2LPENR SDMMC1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1922 * APB2LPENR SDMMC2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1923 * APB2LPENR SPI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1924 * APB2LPENR SPI4LPEN LL_APB2_GRP1_DisableClockLowPower\n
1925 * APB2LPENR SYSCFGLPEN LL_APB2_GRP1_DisableClockLowPower\n
1926 * APB2LPENR TIM9LPEN LL_APB2_GRP1_DisableClockLowPower\n
1927 * APB2LPENR TIM10LPEN LL_APB2_GRP1_DisableClockLowPower\n
1928 * APB2LPENR TIM11LPEN LL_APB2_GRP1_DisableClockLowPower\n
1929 * APB2LPENR SPI5LPEN LL_APB2_GRP1_DisableClockLowPower\n
1930 * APB2LPENR SPI6LPEN LL_APB2_GRP1_DisableClockLowPower\n
1931 * APB2LPENR SAI1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1932 * APB2LPENR SAI2LPEN LL_APB2_GRP1_DisableClockLowPower\n
1933 * APB2LPENR LTDCLPEN LL_APB2_GRP1_DisableClockLowPower\n
1934 * APB2LPENR DSILPEN LL_APB2_GRP1_DisableClockLowPower\n
1935 * APB2LPENR DFSDM1LPEN LL_APB2_GRP1_DisableClockLowPower\n
1936 * APB2LPENR MDIOLPEN LL_APB2_GRP1_DisableClockLowPower
1937 * @param Periphs This parameter can be a combination of the following values:
1938 * @arg @ref LL_APB2_GRP1_PERIPH_TIM1
1939 * @arg @ref LL_APB2_GRP1_PERIPH_TIM8
1940 * @arg @ref LL_APB2_GRP1_PERIPH_USART1
1941 * @arg @ref LL_APB2_GRP1_PERIPH_USART6
1942 * @arg @ref LL_APB2_GRP1_PERIPH_ADC1
1943 * @arg @ref LL_APB2_GRP1_PERIPH_ADC2
1944 * @arg @ref LL_APB2_GRP1_PERIPH_ADC3
1945 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1
1946 * @arg @ref LL_APB2_GRP1_PERIPH_SDMMC1 (*)
1947 * @arg @ref LL_APB2_GRP1_PERIPH_SPI1
1948 * @arg @ref LL_APB2_GRP1_PERIPH_SPI4
1949 * @arg @ref LL_APB2_GRP1_PERIPH_SYSCFG
1950 * @arg @ref LL_APB2_GRP1_PERIPH_TIM9
1951 * @arg @ref LL_APB2_GRP1_PERIPH_TIM10
1952 * @arg @ref LL_APB2_GRP1_PERIPH_TIM11
1953 * @arg @ref LL_APB2_GRP1_PERIPH_SPI5
1954 * @arg @ref LL_APB2_GRP1_PERIPH_SPI6 (*)
1955 * @arg @ref LL_APB2_GRP1_PERIPH_SAI1
1956 * @arg @ref LL_APB2_GRP1_PERIPH_SAI2
1957 * @arg @ref LL_APB2_GRP1_PERIPH_LTDC (*)
1958 * @arg @ref LL_APB2_GRP1_PERIPH_DSI (*)
1959 * @arg @ref LL_APB2_GRP1_PERIPH_DFSDM1 (*)
1960 * @arg @ref LL_APB2_GRP1_PERIPH_MDIO (*)
1961 *
1962 * (*) value not defined in all devices.
1963 * @retval None
1964 */
1965 __STATIC_INLINE void LL_APB2_GRP1_DisableClockLowPower(uint32_t Periphs)
1966 {
1967 CLEAR_BIT(RCC->APB2LPENR, Periphs);
1968 }
1969
1970 /**
1971 * @}
1972 */
1973
1974 /**
1975 * @}
1976 */
1977
1978 /**
1979 * @}
1980 */
1981
1982 #endif /* defined(RCC) */
1983
1984 /**
1985 * @}
1986 */
1987
1988 #ifdef __cplusplus
1989 }
1990 #endif
1991
1992 #endif /* __STM32F7xx_LL_BUS_H */
1993
1994 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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