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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_dma.h
blob7907ab1fbad19575a7ba7d3636e503b4b654b112
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of DMA LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_DMA_H
40 #define __STM32F7xx_LL_DMA_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DMA1) || defined (DMA2)
54
55 /** @defgroup DMA_LL DMA
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
62 * @{
63 */
64 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
65 static const uint8_t STREAM_OFFSET_TAB[] =
66 {
67 (uint8_t)(DMA1_Stream0_BASE - DMA1_BASE),
68 (uint8_t)(DMA1_Stream1_BASE - DMA1_BASE),
69 (uint8_t)(DMA1_Stream2_BASE - DMA1_BASE),
70 (uint8_t)(DMA1_Stream3_BASE - DMA1_BASE),
71 (uint8_t)(DMA1_Stream4_BASE - DMA1_BASE),
72 (uint8_t)(DMA1_Stream5_BASE - DMA1_BASE),
73 (uint8_t)(DMA1_Stream6_BASE - DMA1_BASE),
74 (uint8_t)(DMA1_Stream7_BASE - DMA1_BASE)
75 };
76
77 /**
78 * @}
79 */
80
81 /* Private constants ---------------------------------------------------------*/
82 /** @defgroup DMA_LL_Private_Constants DMA Private Constants
83 * @{
84 */
85 #if defined(DMA_SxCR_CHSEL_3)
86 #define DMA_CHANNEL_SELECTION_8_15
87 #endif /* DMA_SxCR_CHSEL_3 */
88 /**
89 * @}
90 */
91
92
93 /* Private macros ------------------------------------------------------------*/
94 /* Exported types ------------------------------------------------------------*/
95 #if defined(USE_FULL_LL_DRIVER)
96 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
97 * @{
98 */
99 typedef struct
100 {
101 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for DMA transfer
102 or as Source base address in case of memory to memory transfer direction.
103
104 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
105
106 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
107 or as Destination base address in case of memory to memory transfer direction.
108
109 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
110
111 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
112 from memory to memory or from peripheral to memory.
113 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
114
115 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
116
117 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
118 This parameter can be a value of @ref DMA_LL_EC_MODE
119 @note The circular buffer mode cannot be used if the memory to memory
120 data transfer direction is configured on the selected Stream
121
122 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
123
124 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
125 is incremented or not.
126 This parameter can be a value of @ref DMA_LL_EC_PERIPH
127
128 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
129
130 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
131 is incremented or not.
132 This parameter can be a value of @ref DMA_LL_EC_MEMORY
133
134 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
135
136 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
137 in case of memory to memory transfer direction.
138 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
139
140 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
141
142 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
143 in case of memory to memory transfer direction.
144 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
145
146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
147
148 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
149 The data unit is equal to the source buffer configuration set in PeripheralSize
150 or MemorySize parameters depending in the transfer direction.
151 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
152
153 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
154
155 uint32_t Channel; /*!< Specifies the peripheral channel.
156 This parameter can be a value of @ref DMA_LL_EC_CHANNEL
157
158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetChannelSelection(). */
159
160 uint32_t Priority; /*!< Specifies the channel priority level.
161 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
162
163 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
164
165 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
166 This parameter can be a value of @ref DMA_LL_FIFOMODE
167 @note The Direct mode (FIFO mode disabled) cannot be used if the
168 memory-to-memory data transfer is configured on the selected stream
169
170 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
171
172 uint32_t FIFOThreshold; /*!< Specifies the FIFO threshold level.
173 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
174
175 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
176
177 uint32_t MemBurst; /*!< Specifies the Burst transfer configuration for the memory transfers.
178 It specifies the amount of data to be transferred in a single non interruptible
179 transaction.
180 This parameter can be a value of @ref DMA_LL_EC_MBURST
181 @note The burst mode is possible only if the address Increment mode is enabled.
182
183 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
184
185 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
186 It specifies the amount of data to be transferred in a single non interruptible
187 transaction.
188 This parameter can be a value of @ref DMA_LL_EC_PBURST
189 @note The burst mode is possible only if the address Increment mode is enabled.
190
191 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
192
193 } LL_DMA_InitTypeDef;
194 /**
195 * @}
196 */
197 #endif /*USE_FULL_LL_DRIVER*/
198 /* Exported constants --------------------------------------------------------*/
199 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
200 * @{
201 */
202
203 /** @defgroup DMA_LL_EC_STREAM STREAM
204 * @{
205 */
206 #define LL_DMA_STREAM_0 0x00000000U
207 #define LL_DMA_STREAM_1 0x00000001U
208 #define LL_DMA_STREAM_2 0x00000002U
209 #define LL_DMA_STREAM_3 0x00000003U
210 #define LL_DMA_STREAM_4 0x00000004U
211 #define LL_DMA_STREAM_5 0x00000005U
212 #define LL_DMA_STREAM_6 0x00000006U
213 #define LL_DMA_STREAM_7 0x00000007U
214 #define LL_DMA_STREAM_ALL 0xFFFF0000U
215 /**
216 * @}
217 */
218
219 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
220 * @{
221 */
222 #define LL_DMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
223 #define LL_DMA_DIRECTION_MEMORY_TO_PERIPH DMA_SxCR_DIR_0 /*!< Memory to peripheral direction */
224 #define LL_DMA_DIRECTION_MEMORY_TO_MEMORY DMA_SxCR_DIR_1 /*!< Memory to memory direction */
225 /**
226 * @}
227 */
228
229 /** @defgroup DMA_LL_EC_MODE MODE
230 * @{
231 */
232 #define LL_DMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
233 #define LL_DMA_MODE_CIRCULAR DMA_SxCR_CIRC /*!< Circular Mode */
234 #define LL_DMA_MODE_PFCTRL DMA_SxCR_PFCTRL /*!< Peripheral flow control mode */
235 /**
236 * @}
237 */
238
239 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
240 * @{
241 */
242 #define LL_DMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
243 #define LL_DMA_DOUBLEBUFFER_MODE_ENABLE DMA_SxCR_DBM /*!< Enable double buffering mode */
244 /**
245 * @}
246 */
247
248 /** @defgroup DMA_LL_EC_PERIPH PERIPH
249 * @{
250 */
251 #define LL_DMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
252 #define LL_DMA_PERIPH_INCREMENT DMA_SxCR_PINC /*!< Peripheral increment mode Enable */
253 /**
254 * @}
255 */
256
257 /** @defgroup DMA_LL_EC_MEMORY MEMORY
258 * @{
259 */
260 #define LL_DMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
261 #define LL_DMA_MEMORY_INCREMENT DMA_SxCR_MINC /*!< Memory increment mode Enable */
262 /**
263 * @}
264 */
265
266 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
267 * @{
268 */
269 #define LL_DMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
270 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
271 #define LL_DMA_PDATAALIGN_WORD DMA_SxCR_PSIZE_1 /*!< Peripheral data alignment : Word */
272 /**
273 * @}
274 */
275
276 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
277 * @{
278 */
279 #define LL_DMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
280 #define LL_DMA_MDATAALIGN_HALFWORD DMA_SxCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
281 #define LL_DMA_MDATAALIGN_WORD DMA_SxCR_MSIZE_1 /*!< Memory data alignment : Word */
282 /**
283 * @}
284 */
285
286 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
287 * @{
288 */
289 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
290 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
291 /**
292 * @}
293 */
294
295 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
296 * @{
297 */
298 #define LL_DMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
299 #define LL_DMA_PRIORITY_MEDIUM DMA_SxCR_PL_0 /*!< Priority level : Medium */
300 #define LL_DMA_PRIORITY_HIGH DMA_SxCR_PL_1 /*!< Priority level : High */
301 #define LL_DMA_PRIORITY_VERYHIGH DMA_SxCR_PL /*!< Priority level : Very_High */
302 /**
303 * @}
304 */
305
306 /** @defgroup DMA_LL_EC_CHANNEL CHANNEL
307 * @{
308 */
309 #define LL_DMA_CHANNEL_0 0x00000000U /* Select Channel0 of DMA Instance */
310 #define LL_DMA_CHANNEL_1 DMA_SxCR_CHSEL_0 /* Select Channel1 of DMA Instance */
311 #define LL_DMA_CHANNEL_2 DMA_SxCR_CHSEL_1 /* Select Channel2 of DMA Instance */
312 #define LL_DMA_CHANNEL_3 (DMA_SxCR_CHSEL_0 | DMA_SxCR_CHSEL_1) /* Select Channel3 of DMA Instance */
313 #define LL_DMA_CHANNEL_4 DMA_SxCR_CHSEL_2 /* Select Channel4 of DMA Instance */
314 #define LL_DMA_CHANNEL_5 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel5 of DMA Instance */
315 #define LL_DMA_CHANNEL_6 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel6 of DMA Instance */
316 #define LL_DMA_CHANNEL_7 (DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel7 of DMA Instance */
317 #if defined(DMA_CHANNEL_SELECTION_8_15)
318 #define LL_DMA_CHANNEL_8 DMA_SxCR_CHSEL_3 /* Select Channel8 of DMA Instance */
319 #define LL_DMA_CHANNEL_9 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_0) /* Select Channel9 of DMA Instance */
320 #define LL_DMA_CHANNEL_10 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1) /* Select Channel10 of DMA Instance */
321 #define LL_DMA_CHANNEL_11 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_1 | DMA_SxCR_CHSEL_0) /* Select Channel11 of DMA Instance */
322 #define LL_DMA_CHANNEL_12 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2) /* Select Channel12 of DMA Instance */
323 #define LL_DMA_CHANNEL_13 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_0) /* Select Channel13 of DMA Instance */
324 #define LL_DMA_CHANNEL_14 (DMA_SxCR_CHSEL_3 | DMA_SxCR_CHSEL_2 | DMA_SxCR_CHSEL_1) /* Select Channel14 of DMA Instance */
325 #define LL_DMA_CHANNEL_15 DMA_SxCR_CHSEL /* Select Channel15 of DMA Instance */
326 #endif /* DMA_CHANNEL_SELECTION_8_15 */
327 /**
328 * @}
329 */
330
331 /** @defgroup DMA_LL_EC_MBURST MBURST
332 * @{
333 */
334 #define LL_DMA_MBURST_SINGLE 0x00000000U /*!< Memory burst single transfer configuration */
335 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
336 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
337 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
338 /**
339 * @}
340 */
341
342 /** @defgroup DMA_LL_EC_PBURST PBURST
343 * @{
344 */
345 #define LL_DMA_PBURST_SINGLE 0x00000000U /*!< Peripheral burst single transfer configuration */
346 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
347 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
348 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
349 /**
350 * @}
351 */
352
353 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
354 * @{
355 */
356 #define LL_DMA_FIFOMODE_DISABLE 0x00000000U /*!< FIFO mode disable (direct mode is enabled) */
357 #define LL_DMA_FIFOMODE_ENABLE DMA_SxFCR_DMDIS /*!< FIFO mode enable */
358 /**
359 * @}
360 */
361
362 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
363 * @{
364 */
365 #define LL_DMA_FIFOSTATUS_0_25 0x00000000U /*!< 0 < fifo_level < 1/4 */
366 #define LL_DMA_FIFOSTATUS_25_50 DMA_SxFCR_FS_0 /*!< 1/4 < fifo_level < 1/2 */
367 #define LL_DMA_FIFOSTATUS_50_75 DMA_SxFCR_FS_1 /*!< 1/2 < fifo_level < 3/4 */
368 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
369 #define LL_DMA_FIFOSTATUS_EMPTY DMA_SxFCR_FS_2 /*!< FIFO is empty */
370 #define LL_DMA_FIFOSTATUS_FULL (DMA_SxFCR_FS_2 | DMA_SxFCR_FS_0) /*!< FIFO is full */
371 /**
372 * @}
373 */
374
375 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
376 * @{
377 */
378 #define LL_DMA_FIFOTHRESHOLD_1_4 0x00000000U /*!< FIFO threshold 1 quart full configuration */
379 #define LL_DMA_FIFOTHRESHOLD_1_2 DMA_SxFCR_FTH_0 /*!< FIFO threshold half full configuration */
380 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
381 #define LL_DMA_FIFOTHRESHOLD_FULL DMA_SxFCR_FTH /*!< FIFO threshold full configuration */
382 /**
383 * @}
384 */
385
386 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
387 * @{
388 */
389 #define LL_DMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
390 #define LL_DMA_CURRENTTARGETMEM1 DMA_SxCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
391 /**
392 * @}
393 */
394
395 /**
396 * @}
397 */
398
399 /* Exported macro ------------------------------------------------------------*/
400 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
401 * @{
402 */
403
404 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
405 * @{
406 */
407 /**
408 * @brief Write a value in DMA register
409 * @param __INSTANCE__ DMA Instance
410 * @param __REG__ Register to be written
411 * @param __VALUE__ Value to be written in the register
412 * @retval None
413 */
414 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
415
416 /**
417 * @brief Read a value in DMA register
418 * @param __INSTANCE__ DMA Instance
419 * @param __REG__ Register to be read
420 * @retval Register value
421 */
422 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
423 /**
424 * @}
425 */
426
427 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
428 * @{
429 */
430 /**
431 * @brief Convert DMAx_Streamy into DMAx
432 * @param __STREAM_INSTANCE__ DMAx_Streamy
433 * @retval DMAx
434 */
435 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
436 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
437
438 /**
439 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
440 * @param __STREAM_INSTANCE__ DMAx_Streamy
441 * @retval LL_DMA_CHANNEL_y
442 */
443 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
444 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
445 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
446 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
447 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
448 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
449 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
450 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
451 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
452 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
453 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
454 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
455 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
456 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
457 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
458 LL_DMA_STREAM_7)
459
460 /**
461 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
462 * @param __DMA_INSTANCE__ DMAx
463 * @param __STREAM__ LL_DMA_STREAM_y
464 * @retval DMAx_Streamy
465 */
466 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
467 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
468 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
469 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
470 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
471 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
472 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
473 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
474 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
475 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
476 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
477 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
478 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
479 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
480 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
481 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
482 DMA2_Stream7)
483
484 /**
485 * @}
486 */
487
488 /**
489 * @}
490 */
491
492
493 /* Exported functions --------------------------------------------------------*/
494 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
495 * @{
496 */
497
498 /** @defgroup DMA_LL_EF_Configuration Configuration
499 * @{
500 */
501 /**
502 * @brief Enable DMA stream.
503 * @rmtoll CR EN LL_DMA_EnableStream
504 * @param DMAx DMAx Instance
505 * @param Stream This parameter can be one of the following values:
506 * @arg @ref LL_DMA_STREAM_0
507 * @arg @ref LL_DMA_STREAM_1
508 * @arg @ref LL_DMA_STREAM_2
509 * @arg @ref LL_DMA_STREAM_3
510 * @arg @ref LL_DMA_STREAM_4
511 * @arg @ref LL_DMA_STREAM_5
512 * @arg @ref LL_DMA_STREAM_6
513 * @arg @ref LL_DMA_STREAM_7
514 * @retval None
515 */
516 __STATIC_INLINE void LL_DMA_EnableStream(DMA_TypeDef *DMAx, uint32_t Stream)
517 {
518 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
519 }
520
521 /**
522 * @brief Disable DMA stream.
523 * @rmtoll CR EN LL_DMA_DisableStream
524 * @param DMAx DMAx Instance
525 * @param Stream This parameter can be one of the following values:
526 * @arg @ref LL_DMA_STREAM_0
527 * @arg @ref LL_DMA_STREAM_1
528 * @arg @ref LL_DMA_STREAM_2
529 * @arg @ref LL_DMA_STREAM_3
530 * @arg @ref LL_DMA_STREAM_4
531 * @arg @ref LL_DMA_STREAM_5
532 * @arg @ref LL_DMA_STREAM_6
533 * @arg @ref LL_DMA_STREAM_7
534 * @retval None
535 */
536 __STATIC_INLINE void LL_DMA_DisableStream(DMA_TypeDef *DMAx, uint32_t Stream)
537 {
538 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN);
539 }
540
541 /**
542 * @brief Check if DMA stream is enabled or disabled.
543 * @rmtoll CR EN LL_DMA_IsEnabledStream
544 * @param DMAx DMAx Instance
545 * @param Stream This parameter can be one of the following values:
546 * @arg @ref LL_DMA_STREAM_0
547 * @arg @ref LL_DMA_STREAM_1
548 * @arg @ref LL_DMA_STREAM_2
549 * @arg @ref LL_DMA_STREAM_3
550 * @arg @ref LL_DMA_STREAM_4
551 * @arg @ref LL_DMA_STREAM_5
552 * @arg @ref LL_DMA_STREAM_6
553 * @arg @ref LL_DMA_STREAM_7
554 * @retval State of bit (1 or 0).
555 */
556 __STATIC_INLINE uint32_t LL_DMA_IsEnabledStream(DMA_TypeDef *DMAx, uint32_t Stream)
557 {
558 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN));
559 }
560
561 /**
562 * @brief Configure all parameters linked to DMA transfer.
563 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
564 * CR CIRC LL_DMA_ConfigTransfer\n
565 * CR PINC LL_DMA_ConfigTransfer\n
566 * CR MINC LL_DMA_ConfigTransfer\n
567 * CR PSIZE LL_DMA_ConfigTransfer\n
568 * CR MSIZE LL_DMA_ConfigTransfer\n
569 * CR PL LL_DMA_ConfigTransfer\n
570 * CR PFCTRL LL_DMA_ConfigTransfer
571 * @param DMAx DMAx Instance
572 * @param Stream This parameter can be one of the following values:
573 * @arg @ref LL_DMA_STREAM_0
574 * @arg @ref LL_DMA_STREAM_1
575 * @arg @ref LL_DMA_STREAM_2
576 * @arg @ref LL_DMA_STREAM_3
577 * @arg @ref LL_DMA_STREAM_4
578 * @arg @ref LL_DMA_STREAM_5
579 * @arg @ref LL_DMA_STREAM_6
580 * @arg @ref LL_DMA_STREAM_7
581 * @param Configuration This parameter must be a combination of all the following values:
582 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
583 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
584 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
585 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
586 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
587 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
588 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
589 *@retval None
590 */
591 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
592 {
593 MODIFY_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR,
594 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
595 Configuration);
596 }
597
598 /**
599 * @brief Set Data transfer direction (read from peripheral or from memory).
600 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
601 * @param DMAx DMAx Instance
602 * @param Stream This parameter can be one of the following values:
603 * @arg @ref LL_DMA_STREAM_0
604 * @arg @ref LL_DMA_STREAM_1
605 * @arg @ref LL_DMA_STREAM_2
606 * @arg @ref LL_DMA_STREAM_3
607 * @arg @ref LL_DMA_STREAM_4
608 * @arg @ref LL_DMA_STREAM_5
609 * @arg @ref LL_DMA_STREAM_6
610 * @arg @ref LL_DMA_STREAM_7
611 * @param Direction This parameter can be one of the following values:
612 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
613 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
614 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
615 * @retval None
616 */
617 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
618 {
619 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR, Direction);
620 }
621
622 /**
623 * @brief Get Data transfer direction (read from peripheral or from memory).
624 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
625 * @param DMAx DMAx Instance
626 * @param Stream This parameter can be one of the following values:
627 * @arg @ref LL_DMA_STREAM_0
628 * @arg @ref LL_DMA_STREAM_1
629 * @arg @ref LL_DMA_STREAM_2
630 * @arg @ref LL_DMA_STREAM_3
631 * @arg @ref LL_DMA_STREAM_4
632 * @arg @ref LL_DMA_STREAM_5
633 * @arg @ref LL_DMA_STREAM_6
634 * @arg @ref LL_DMA_STREAM_7
635 * @retval Returned value can be one of the following values:
636 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
637 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
638 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
639 */
640 __STATIC_INLINE uint32_t LL_DMA_GetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream)
641 {
642 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DIR));
643 }
644
645 /**
646 * @brief Set DMA mode normal, circular or peripheral flow control.
647 * @rmtoll CR CIRC LL_DMA_SetMode\n
648 * CR PFCTRL LL_DMA_SetMode
649 * @param DMAx DMAx Instance
650 * @param Stream This parameter can be one of the following values:
651 * @arg @ref LL_DMA_STREAM_0
652 * @arg @ref LL_DMA_STREAM_1
653 * @arg @ref LL_DMA_STREAM_2
654 * @arg @ref LL_DMA_STREAM_3
655 * @arg @ref LL_DMA_STREAM_4
656 * @arg @ref LL_DMA_STREAM_5
657 * @arg @ref LL_DMA_STREAM_6
658 * @arg @ref LL_DMA_STREAM_7
659 * @param Mode This parameter can be one of the following values:
660 * @arg @ref LL_DMA_MODE_NORMAL
661 * @arg @ref LL_DMA_MODE_CIRCULAR
662 * @arg @ref LL_DMA_MODE_PFCTRL
663 * @retval None
664 */
665 __STATIC_INLINE void LL_DMA_SetMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mode)
666 {
667 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
668 }
669
670 /**
671 * @brief Get DMA mode normal, circular or peripheral flow control.
672 * @rmtoll CR CIRC LL_DMA_GetMode\n
673 * CR PFCTRL LL_DMA_GetMode
674 * @param DMAx DMAx Instance
675 * @param Stream This parameter can be one of the following values:
676 * @arg @ref LL_DMA_STREAM_0
677 * @arg @ref LL_DMA_STREAM_1
678 * @arg @ref LL_DMA_STREAM_2
679 * @arg @ref LL_DMA_STREAM_3
680 * @arg @ref LL_DMA_STREAM_4
681 * @arg @ref LL_DMA_STREAM_5
682 * @arg @ref LL_DMA_STREAM_6
683 * @arg @ref LL_DMA_STREAM_7
684 * @retval Returned value can be one of the following values:
685 * @arg @ref LL_DMA_MODE_NORMAL
686 * @arg @ref LL_DMA_MODE_CIRCULAR
687 * @arg @ref LL_DMA_MODE_PFCTRL
688 */
689 __STATIC_INLINE uint32_t LL_DMA_GetMode(DMA_TypeDef *DMAx, uint32_t Stream)
690 {
691 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
692 }
693
694 /**
695 * @brief Set Peripheral increment mode.
696 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
697 * @param DMAx DMAx Instance
698 * @param Stream This parameter can be one of the following values:
699 * @arg @ref LL_DMA_STREAM_0
700 * @arg @ref LL_DMA_STREAM_1
701 * @arg @ref LL_DMA_STREAM_2
702 * @arg @ref LL_DMA_STREAM_3
703 * @arg @ref LL_DMA_STREAM_4
704 * @arg @ref LL_DMA_STREAM_5
705 * @arg @ref LL_DMA_STREAM_6
706 * @arg @ref LL_DMA_STREAM_7
707 * @param IncrementMode This parameter can be one of the following values:
708 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
709 * @arg @ref LL_DMA_PERIPH_INCREMENT
710 * @retval None
711 */
712 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
713 {
714 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC, IncrementMode);
715 }
716
717 /**
718 * @brief Get Peripheral increment mode.
719 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
720 * @param DMAx DMAx Instance
721 * @param Stream This parameter can be one of the following values:
722 * @arg @ref LL_DMA_STREAM_0
723 * @arg @ref LL_DMA_STREAM_1
724 * @arg @ref LL_DMA_STREAM_2
725 * @arg @ref LL_DMA_STREAM_3
726 * @arg @ref LL_DMA_STREAM_4
727 * @arg @ref LL_DMA_STREAM_5
728 * @arg @ref LL_DMA_STREAM_6
729 * @arg @ref LL_DMA_STREAM_7
730 * @retval Returned value can be one of the following values:
731 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
732 * @arg @ref LL_DMA_PERIPH_INCREMENT
733 */
734 __STATIC_INLINE uint32_t LL_DMA_GetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
735 {
736 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINC));
737 }
738
739 /**
740 * @brief Set Memory increment mode.
741 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
742 * @param DMAx DMAx Instance
743 * @param Stream This parameter can be one of the following values:
744 * @arg @ref LL_DMA_STREAM_0
745 * @arg @ref LL_DMA_STREAM_1
746 * @arg @ref LL_DMA_STREAM_2
747 * @arg @ref LL_DMA_STREAM_3
748 * @arg @ref LL_DMA_STREAM_4
749 * @arg @ref LL_DMA_STREAM_5
750 * @arg @ref LL_DMA_STREAM_6
751 * @arg @ref LL_DMA_STREAM_7
752 * @param IncrementMode This parameter can be one of the following values:
753 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
754 * @arg @ref LL_DMA_MEMORY_INCREMENT
755 * @retval None
756 */
757 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
758 {
759 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC, IncrementMode);
760 }
761
762 /**
763 * @brief Get Memory increment mode.
764 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
765 * @param DMAx DMAx Instance
766 * @param Stream This parameter can be one of the following values:
767 * @arg @ref LL_DMA_STREAM_0
768 * @arg @ref LL_DMA_STREAM_1
769 * @arg @ref LL_DMA_STREAM_2
770 * @arg @ref LL_DMA_STREAM_3
771 * @arg @ref LL_DMA_STREAM_4
772 * @arg @ref LL_DMA_STREAM_5
773 * @arg @ref LL_DMA_STREAM_6
774 * @arg @ref LL_DMA_STREAM_7
775 * @retval Returned value can be one of the following values:
776 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
777 * @arg @ref LL_DMA_MEMORY_INCREMENT
778 */
779 __STATIC_INLINE uint32_t LL_DMA_GetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream)
780 {
781 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MINC));
782 }
783
784 /**
785 * @brief Set Peripheral size.
786 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
787 * @param DMAx DMAx Instance
788 * @param Stream This parameter can be one of the following values:
789 * @arg @ref LL_DMA_STREAM_0
790 * @arg @ref LL_DMA_STREAM_1
791 * @arg @ref LL_DMA_STREAM_2
792 * @arg @ref LL_DMA_STREAM_3
793 * @arg @ref LL_DMA_STREAM_4
794 * @arg @ref LL_DMA_STREAM_5
795 * @arg @ref LL_DMA_STREAM_6
796 * @arg @ref LL_DMA_STREAM_7
797 * @param Size This parameter can be one of the following values:
798 * @arg @ref LL_DMA_PDATAALIGN_BYTE
799 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
800 * @arg @ref LL_DMA_PDATAALIGN_WORD
801 * @retval None
802 */
803 __STATIC_INLINE void LL_DMA_SetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
804 {
805 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE, Size);
806 }
807
808 /**
809 * @brief Get Peripheral size.
810 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
811 * @param DMAx DMAx Instance
812 * @param Stream This parameter can be one of the following values:
813 * @arg @ref LL_DMA_STREAM_0
814 * @arg @ref LL_DMA_STREAM_1
815 * @arg @ref LL_DMA_STREAM_2
816 * @arg @ref LL_DMA_STREAM_3
817 * @arg @ref LL_DMA_STREAM_4
818 * @arg @ref LL_DMA_STREAM_5
819 * @arg @ref LL_DMA_STREAM_6
820 * @arg @ref LL_DMA_STREAM_7
821 * @retval Returned value can be one of the following values:
822 * @arg @ref LL_DMA_PDATAALIGN_BYTE
823 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
824 * @arg @ref LL_DMA_PDATAALIGN_WORD
825 */
826 __STATIC_INLINE uint32_t LL_DMA_GetPeriphSize(DMA_TypeDef *DMAx, uint32_t Stream)
827 {
828 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PSIZE));
829 }
830
831 /**
832 * @brief Set Memory size.
833 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
834 * @param DMAx DMAx Instance
835 * @param Stream This parameter can be one of the following values:
836 * @arg @ref LL_DMA_STREAM_0
837 * @arg @ref LL_DMA_STREAM_1
838 * @arg @ref LL_DMA_STREAM_2
839 * @arg @ref LL_DMA_STREAM_3
840 * @arg @ref LL_DMA_STREAM_4
841 * @arg @ref LL_DMA_STREAM_5
842 * @arg @ref LL_DMA_STREAM_6
843 * @arg @ref LL_DMA_STREAM_7
844 * @param Size This parameter can be one of the following values:
845 * @arg @ref LL_DMA_MDATAALIGN_BYTE
846 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
847 * @arg @ref LL_DMA_MDATAALIGN_WORD
848 * @retval None
849 */
850 __STATIC_INLINE void LL_DMA_SetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Size)
851 {
852 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE, Size);
853 }
854
855 /**
856 * @brief Get Memory size.
857 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
858 * @param DMAx DMAx Instance
859 * @param Stream This parameter can be one of the following values:
860 * @arg @ref LL_DMA_STREAM_0
861 * @arg @ref LL_DMA_STREAM_1
862 * @arg @ref LL_DMA_STREAM_2
863 * @arg @ref LL_DMA_STREAM_3
864 * @arg @ref LL_DMA_STREAM_4
865 * @arg @ref LL_DMA_STREAM_5
866 * @arg @ref LL_DMA_STREAM_6
867 * @arg @ref LL_DMA_STREAM_7
868 * @retval Returned value can be one of the following values:
869 * @arg @ref LL_DMA_MDATAALIGN_BYTE
870 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
871 * @arg @ref LL_DMA_MDATAALIGN_WORD
872 */
873 __STATIC_INLINE uint32_t LL_DMA_GetMemorySize(DMA_TypeDef *DMAx, uint32_t Stream)
874 {
875 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MSIZE));
876 }
877
878 /**
879 * @brief Set Peripheral increment offset size.
880 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
881 * @param DMAx DMAx Instance
882 * @param Stream This parameter can be one of the following values:
883 * @arg @ref LL_DMA_STREAM_0
884 * @arg @ref LL_DMA_STREAM_1
885 * @arg @ref LL_DMA_STREAM_2
886 * @arg @ref LL_DMA_STREAM_3
887 * @arg @ref LL_DMA_STREAM_4
888 * @arg @ref LL_DMA_STREAM_5
889 * @arg @ref LL_DMA_STREAM_6
890 * @arg @ref LL_DMA_STREAM_7
891 * @param OffsetSize This parameter can be one of the following values:
892 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
893 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
894 * @retval None
895 */
896 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
897 {
898 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS, OffsetSize);
899 }
900
901 /**
902 * @brief Get Peripheral increment offset size.
903 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
904 * @param DMAx DMAx Instance
905 * @param Stream This parameter can be one of the following values:
906 * @arg @ref LL_DMA_STREAM_0
907 * @arg @ref LL_DMA_STREAM_1
908 * @arg @ref LL_DMA_STREAM_2
909 * @arg @ref LL_DMA_STREAM_3
910 * @arg @ref LL_DMA_STREAM_4
911 * @arg @ref LL_DMA_STREAM_5
912 * @arg @ref LL_DMA_STREAM_6
913 * @arg @ref LL_DMA_STREAM_7
914 * @retval Returned value can be one of the following values:
915 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
916 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
917 */
918 __STATIC_INLINE uint32_t LL_DMA_GetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream)
919 {
920 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PINCOS));
921 }
922
923 /**
924 * @brief Set Stream priority level.
925 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
926 * @param DMAx DMAx Instance
927 * @param Stream This parameter can be one of the following values:
928 * @arg @ref LL_DMA_STREAM_0
929 * @arg @ref LL_DMA_STREAM_1
930 * @arg @ref LL_DMA_STREAM_2
931 * @arg @ref LL_DMA_STREAM_3
932 * @arg @ref LL_DMA_STREAM_4
933 * @arg @ref LL_DMA_STREAM_5
934 * @arg @ref LL_DMA_STREAM_6
935 * @arg @ref LL_DMA_STREAM_7
936 * @param Priority This parameter can be one of the following values:
937 * @arg @ref LL_DMA_PRIORITY_LOW
938 * @arg @ref LL_DMA_PRIORITY_MEDIUM
939 * @arg @ref LL_DMA_PRIORITY_HIGH
940 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
941 * @retval None
942 */
943 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
944 {
945 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL, Priority);
946 }
947
948 /**
949 * @brief Get Stream priority level.
950 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
951 * @param DMAx DMAx Instance
952 * @param Stream This parameter can be one of the following values:
953 * @arg @ref LL_DMA_STREAM_0
954 * @arg @ref LL_DMA_STREAM_1
955 * @arg @ref LL_DMA_STREAM_2
956 * @arg @ref LL_DMA_STREAM_3
957 * @arg @ref LL_DMA_STREAM_4
958 * @arg @ref LL_DMA_STREAM_5
959 * @arg @ref LL_DMA_STREAM_6
960 * @arg @ref LL_DMA_STREAM_7
961 * @retval Returned value can be one of the following values:
962 * @arg @ref LL_DMA_PRIORITY_LOW
963 * @arg @ref LL_DMA_PRIORITY_MEDIUM
964 * @arg @ref LL_DMA_PRIORITY_HIGH
965 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
966 */
967 __STATIC_INLINE uint32_t LL_DMA_GetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream)
968 {
969 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PL));
970 }
971
972 /**
973 * @brief Set Number of data to transfer.
974 * @rmtoll NDTR NDT LL_DMA_SetDataLength
975 * @note This action has no effect if
976 * stream is enabled.
977 * @param DMAx DMAx Instance
978 * @param Stream This parameter can be one of the following values:
979 * @arg @ref LL_DMA_STREAM_0
980 * @arg @ref LL_DMA_STREAM_1
981 * @arg @ref LL_DMA_STREAM_2
982 * @arg @ref LL_DMA_STREAM_3
983 * @arg @ref LL_DMA_STREAM_4
984 * @arg @ref LL_DMA_STREAM_5
985 * @arg @ref LL_DMA_STREAM_6
986 * @arg @ref LL_DMA_STREAM_7
987 * @param NbData Between 0 to 0xFFFFFFFF
988 * @retval None
989 */
990 __STATIC_INLINE void LL_DMA_SetDataLength(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t NbData)
991 {
992 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT, NbData);
993 }
994
995 /**
996 * @brief Get Number of data to transfer.
997 * @rmtoll NDTR NDT LL_DMA_GetDataLength
998 * @note Once the stream is enabled, the return value indicate the
999 * remaining bytes to be transmitted.
1000 * @param DMAx DMAx Instance
1001 * @param Stream This parameter can be one of the following values:
1002 * @arg @ref LL_DMA_STREAM_0
1003 * @arg @ref LL_DMA_STREAM_1
1004 * @arg @ref LL_DMA_STREAM_2
1005 * @arg @ref LL_DMA_STREAM_3
1006 * @arg @ref LL_DMA_STREAM_4
1007 * @arg @ref LL_DMA_STREAM_5
1008 * @arg @ref LL_DMA_STREAM_6
1009 * @arg @ref LL_DMA_STREAM_7
1010 * @retval Between 0 to 0xFFFFFFFF
1011 */
1012 __STATIC_INLINE uint32_t LL_DMA_GetDataLength(DMA_TypeDef* DMAx, uint32_t Stream)
1013 {
1014 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->NDTR, DMA_SxNDT));
1015 }
1016
1017 /**
1018 * @brief Select Channel number associated to the Stream.
1019 * @rmtoll CR CHSEL LL_DMA_SetChannelSelection
1020 * @param DMAx DMAx Instance
1021 * @param Stream This parameter can be one of the following values:
1022 * @arg @ref LL_DMA_STREAM_0
1023 * @arg @ref LL_DMA_STREAM_1
1024 * @arg @ref LL_DMA_STREAM_2
1025 * @arg @ref LL_DMA_STREAM_3
1026 * @arg @ref LL_DMA_STREAM_4
1027 * @arg @ref LL_DMA_STREAM_5
1028 * @arg @ref LL_DMA_STREAM_6
1029 * @arg @ref LL_DMA_STREAM_7
1030 * @param Channel This parameter can be one of the following values:
1031 * @arg @ref LL_DMA_CHANNEL_0
1032 * @arg @ref LL_DMA_CHANNEL_1
1033 * @arg @ref LL_DMA_CHANNEL_2
1034 * @arg @ref LL_DMA_CHANNEL_3
1035 * @arg @ref LL_DMA_CHANNEL_4
1036 * @arg @ref LL_DMA_CHANNEL_5
1037 * @arg @ref LL_DMA_CHANNEL_6
1038 * @arg @ref LL_DMA_CHANNEL_7
1039 * @arg @ref LL_DMA_CHANNEL_8 (*)
1040 * @arg @ref LL_DMA_CHANNEL_9 (*)
1041 * @arg @ref LL_DMA_CHANNEL_10 (*)
1042 * @arg @ref LL_DMA_CHANNEL_11 (*)
1043 * @arg @ref LL_DMA_CHANNEL_12 (*)
1044 * @arg @ref LL_DMA_CHANNEL_13 (*)
1045 * @arg @ref LL_DMA_CHANNEL_14 (*)
1046 * @arg @ref LL_DMA_CHANNEL_15 (*)
1047 *
1048 * (*) value not defined in all devices.
1049 * @retval None
1050 */
1051 __STATIC_INLINE void LL_DMA_SetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Channel)
1052 {
1053 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL, Channel);
1054 }
1055
1056 /**
1057 * @brief Get the Channel number associated to the Stream.
1058 * @rmtoll CR CHSEL LL_DMA_GetChannelSelection
1059 * @param DMAx DMAx Instance
1060 * @param Stream This parameter can be one of the following values:
1061 * @arg @ref LL_DMA_STREAM_0
1062 * @arg @ref LL_DMA_STREAM_1
1063 * @arg @ref LL_DMA_STREAM_2
1064 * @arg @ref LL_DMA_STREAM_3
1065 * @arg @ref LL_DMA_STREAM_4
1066 * @arg @ref LL_DMA_STREAM_5
1067 * @arg @ref LL_DMA_STREAM_6
1068 * @arg @ref LL_DMA_STREAM_7
1069 * @retval Returned value can be one of the following values:
1070 * @arg @ref LL_DMA_CHANNEL_0
1071 * @arg @ref LL_DMA_CHANNEL_1
1072 * @arg @ref LL_DMA_CHANNEL_2
1073 * @arg @ref LL_DMA_CHANNEL_3
1074 * @arg @ref LL_DMA_CHANNEL_4
1075 * @arg @ref LL_DMA_CHANNEL_5
1076 * @arg @ref LL_DMA_CHANNEL_6
1077 * @arg @ref LL_DMA_CHANNEL_7
1078 * @arg @ref LL_DMA_CHANNEL_8 (*)
1079 * @arg @ref LL_DMA_CHANNEL_9 (*)
1080 * @arg @ref LL_DMA_CHANNEL_10 (*)
1081 * @arg @ref LL_DMA_CHANNEL_11 (*)
1082 * @arg @ref LL_DMA_CHANNEL_12 (*)
1083 * @arg @ref LL_DMA_CHANNEL_13 (*)
1084 * @arg @ref LL_DMA_CHANNEL_14 (*)
1085 * @arg @ref LL_DMA_CHANNEL_15 (*)
1086 *
1087 * (*) value not defined in all devices.
1088 */
1089 __STATIC_INLINE uint32_t LL_DMA_GetChannelSelection(DMA_TypeDef *DMAx, uint32_t Stream)
1090 {
1091 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CHSEL));
1092 }
1093
1094 /**
1095 * @brief Set Memory burst transfer configuration.
1096 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1097 * @param DMAx DMAx Instance
1098 * @param Stream This parameter can be one of the following values:
1099 * @arg @ref LL_DMA_STREAM_0
1100 * @arg @ref LL_DMA_STREAM_1
1101 * @arg @ref LL_DMA_STREAM_2
1102 * @arg @ref LL_DMA_STREAM_3
1103 * @arg @ref LL_DMA_STREAM_4
1104 * @arg @ref LL_DMA_STREAM_5
1105 * @arg @ref LL_DMA_STREAM_6
1106 * @arg @ref LL_DMA_STREAM_7
1107 * @param Mburst This parameter can be one of the following values:
1108 * @arg @ref LL_DMA_MBURST_SINGLE
1109 * @arg @ref LL_DMA_MBURST_INC4
1110 * @arg @ref LL_DMA_MBURST_INC8
1111 * @arg @ref LL_DMA_MBURST_INC16
1112 * @retval None
1113 */
1114 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1115 {
1116 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST, Mburst);
1117 }
1118
1119 /**
1120 * @brief Get Memory burst transfer configuration.
1121 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1122 * @param DMAx DMAx Instance
1123 * @param Stream This parameter can be one of the following values:
1124 * @arg @ref LL_DMA_STREAM_0
1125 * @arg @ref LL_DMA_STREAM_1
1126 * @arg @ref LL_DMA_STREAM_2
1127 * @arg @ref LL_DMA_STREAM_3
1128 * @arg @ref LL_DMA_STREAM_4
1129 * @arg @ref LL_DMA_STREAM_5
1130 * @arg @ref LL_DMA_STREAM_6
1131 * @arg @ref LL_DMA_STREAM_7
1132 * @retval Returned value can be one of the following values:
1133 * @arg @ref LL_DMA_MBURST_SINGLE
1134 * @arg @ref LL_DMA_MBURST_INC4
1135 * @arg @ref LL_DMA_MBURST_INC8
1136 * @arg @ref LL_DMA_MBURST_INC16
1137 */
1138 __STATIC_INLINE uint32_t LL_DMA_GetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1139 {
1140 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_MBURST));
1141 }
1142
1143 /**
1144 * @brief Set Peripheral burst transfer configuration.
1145 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1146 * @param DMAx DMAx Instance
1147 * @param Stream This parameter can be one of the following values:
1148 * @arg @ref LL_DMA_STREAM_0
1149 * @arg @ref LL_DMA_STREAM_1
1150 * @arg @ref LL_DMA_STREAM_2
1151 * @arg @ref LL_DMA_STREAM_3
1152 * @arg @ref LL_DMA_STREAM_4
1153 * @arg @ref LL_DMA_STREAM_5
1154 * @arg @ref LL_DMA_STREAM_6
1155 * @arg @ref LL_DMA_STREAM_7
1156 * @param Pburst This parameter can be one of the following values:
1157 * @arg @ref LL_DMA_PBURST_SINGLE
1158 * @arg @ref LL_DMA_PBURST_INC4
1159 * @arg @ref LL_DMA_PBURST_INC8
1160 * @arg @ref LL_DMA_PBURST_INC16
1161 * @retval None
1162 */
1163 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1164 {
1165 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST, Pburst);
1166 }
1167
1168 /**
1169 * @brief Get Peripheral burst transfer configuration.
1170 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1171 * @param DMAx DMAx Instance
1172 * @param Stream This parameter can be one of the following values:
1173 * @arg @ref LL_DMA_STREAM_0
1174 * @arg @ref LL_DMA_STREAM_1
1175 * @arg @ref LL_DMA_STREAM_2
1176 * @arg @ref LL_DMA_STREAM_3
1177 * @arg @ref LL_DMA_STREAM_4
1178 * @arg @ref LL_DMA_STREAM_5
1179 * @arg @ref LL_DMA_STREAM_6
1180 * @arg @ref LL_DMA_STREAM_7
1181 * @retval Returned value can be one of the following values:
1182 * @arg @ref LL_DMA_PBURST_SINGLE
1183 * @arg @ref LL_DMA_PBURST_INC4
1184 * @arg @ref LL_DMA_PBURST_INC8
1185 * @arg @ref LL_DMA_PBURST_INC16
1186 */
1187 __STATIC_INLINE uint32_t LL_DMA_GetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream)
1188 {
1189 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_PBURST));
1190 }
1191
1192 /**
1193 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1194 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1195 * @param DMAx DMAx Instance
1196 * @param Stream This parameter can be one of the following values:
1197 * @arg @ref LL_DMA_STREAM_0
1198 * @arg @ref LL_DMA_STREAM_1
1199 * @arg @ref LL_DMA_STREAM_2
1200 * @arg @ref LL_DMA_STREAM_3
1201 * @arg @ref LL_DMA_STREAM_4
1202 * @arg @ref LL_DMA_STREAM_5
1203 * @arg @ref LL_DMA_STREAM_6
1204 * @arg @ref LL_DMA_STREAM_7
1205 * @param CurrentMemory This parameter can be one of the following values:
1206 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1207 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1208 * @retval None
1209 */
1210 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1211 {
1212 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT, CurrentMemory);
1213 }
1214
1215 /**
1216 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1217 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1218 * @param DMAx DMAx Instance
1219 * @param Stream This parameter can be one of the following values:
1220 * @arg @ref LL_DMA_STREAM_0
1221 * @arg @ref LL_DMA_STREAM_1
1222 * @arg @ref LL_DMA_STREAM_2
1223 * @arg @ref LL_DMA_STREAM_3
1224 * @arg @ref LL_DMA_STREAM_4
1225 * @arg @ref LL_DMA_STREAM_5
1226 * @arg @ref LL_DMA_STREAM_6
1227 * @arg @ref LL_DMA_STREAM_7
1228 * @retval Returned value can be one of the following values:
1229 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1230 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1231 */
1232 __STATIC_INLINE uint32_t LL_DMA_GetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream)
1233 {
1234 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_CT));
1235 }
1236
1237 /**
1238 * @brief Enable the double buffer mode.
1239 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1240 * @param DMAx DMAx Instance
1241 * @param Stream This parameter can be one of the following values:
1242 * @arg @ref LL_DMA_STREAM_0
1243 * @arg @ref LL_DMA_STREAM_1
1244 * @arg @ref LL_DMA_STREAM_2
1245 * @arg @ref LL_DMA_STREAM_3
1246 * @arg @ref LL_DMA_STREAM_4
1247 * @arg @ref LL_DMA_STREAM_5
1248 * @arg @ref LL_DMA_STREAM_6
1249 * @arg @ref LL_DMA_STREAM_7
1250 * @retval None
1251 */
1252 __STATIC_INLINE void LL_DMA_EnableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1253 {
1254 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1255 }
1256
1257 /**
1258 * @brief Disable the double buffer mode.
1259 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1260 * @param DMAx DMAx Instance
1261 * @param Stream This parameter can be one of the following values:
1262 * @arg @ref LL_DMA_STREAM_0
1263 * @arg @ref LL_DMA_STREAM_1
1264 * @arg @ref LL_DMA_STREAM_2
1265 * @arg @ref LL_DMA_STREAM_3
1266 * @arg @ref LL_DMA_STREAM_4
1267 * @arg @ref LL_DMA_STREAM_5
1268 * @arg @ref LL_DMA_STREAM_6
1269 * @arg @ref LL_DMA_STREAM_7
1270 * @retval None
1271 */
1272 __STATIC_INLINE void LL_DMA_DisableDoubleBufferMode(DMA_TypeDef *DMAx, uint32_t Stream)
1273 {
1274 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DBM);
1275 }
1276
1277 /**
1278 * @brief Get FIFO status.
1279 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1280 * @param DMAx DMAx Instance
1281 * @param Stream This parameter can be one of the following values:
1282 * @arg @ref LL_DMA_STREAM_0
1283 * @arg @ref LL_DMA_STREAM_1
1284 * @arg @ref LL_DMA_STREAM_2
1285 * @arg @ref LL_DMA_STREAM_3
1286 * @arg @ref LL_DMA_STREAM_4
1287 * @arg @ref LL_DMA_STREAM_5
1288 * @arg @ref LL_DMA_STREAM_6
1289 * @arg @ref LL_DMA_STREAM_7
1290 * @retval Returned value can be one of the following values:
1291 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1292 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1293 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1294 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1295 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1296 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1297 */
1298 __STATIC_INLINE uint32_t LL_DMA_GetFIFOStatus(DMA_TypeDef *DMAx, uint32_t Stream)
1299 {
1300 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FS));
1301 }
1302
1303 /**
1304 * @brief Disable Fifo mode.
1305 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1306 * @param DMAx DMAx Instance
1307 * @param Stream This parameter can be one of the following values:
1308 * @arg @ref LL_DMA_STREAM_0
1309 * @arg @ref LL_DMA_STREAM_1
1310 * @arg @ref LL_DMA_STREAM_2
1311 * @arg @ref LL_DMA_STREAM_3
1312 * @arg @ref LL_DMA_STREAM_4
1313 * @arg @ref LL_DMA_STREAM_5
1314 * @arg @ref LL_DMA_STREAM_6
1315 * @arg @ref LL_DMA_STREAM_7
1316 * @retval None
1317 */
1318 __STATIC_INLINE void LL_DMA_DisableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1319 {
1320 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1321 }
1322
1323 /**
1324 * @brief Enable Fifo mode.
1325 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1326 * @param DMAx DMAx Instance
1327 * @param Stream This parameter can be one of the following values:
1328 * @arg @ref LL_DMA_STREAM_0
1329 * @arg @ref LL_DMA_STREAM_1
1330 * @arg @ref LL_DMA_STREAM_2
1331 * @arg @ref LL_DMA_STREAM_3
1332 * @arg @ref LL_DMA_STREAM_4
1333 * @arg @ref LL_DMA_STREAM_5
1334 * @arg @ref LL_DMA_STREAM_6
1335 * @arg @ref LL_DMA_STREAM_7
1336 * @retval None
1337 */
1338 __STATIC_INLINE void LL_DMA_EnableFifoMode(DMA_TypeDef *DMAx, uint32_t Stream)
1339 {
1340 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_DMDIS);
1341 }
1342
1343 /**
1344 * @brief Select FIFO threshold.
1345 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1346 * @param DMAx DMAx Instance
1347 * @param Stream This parameter can be one of the following values:
1348 * @arg @ref LL_DMA_STREAM_0
1349 * @arg @ref LL_DMA_STREAM_1
1350 * @arg @ref LL_DMA_STREAM_2
1351 * @arg @ref LL_DMA_STREAM_3
1352 * @arg @ref LL_DMA_STREAM_4
1353 * @arg @ref LL_DMA_STREAM_5
1354 * @arg @ref LL_DMA_STREAM_6
1355 * @arg @ref LL_DMA_STREAM_7
1356 * @param Threshold This parameter can be one of the following values:
1357 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1358 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1359 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1360 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1361 * @retval None
1362 */
1363 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1364 {
1365 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH, Threshold);
1366 }
1367
1368 /**
1369 * @brief Get FIFO threshold.
1370 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1371 * @param DMAx DMAx Instance
1372 * @param Stream This parameter can be one of the following values:
1373 * @arg @ref LL_DMA_STREAM_0
1374 * @arg @ref LL_DMA_STREAM_1
1375 * @arg @ref LL_DMA_STREAM_2
1376 * @arg @ref LL_DMA_STREAM_3
1377 * @arg @ref LL_DMA_STREAM_4
1378 * @arg @ref LL_DMA_STREAM_5
1379 * @arg @ref LL_DMA_STREAM_6
1380 * @arg @ref LL_DMA_STREAM_7
1381 * @retval Returned value can be one of the following values:
1382 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1383 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1384 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1385 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1386 */
1387 __STATIC_INLINE uint32_t LL_DMA_GetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream)
1388 {
1389 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH));
1390 }
1391
1392 /**
1393 * @brief Configure the FIFO .
1394 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1395 * FCR DMDIS LL_DMA_ConfigFifo
1396 * @param DMAx DMAx Instance
1397 * @param Stream This parameter can be one of the following values:
1398 * @arg @ref LL_DMA_STREAM_0
1399 * @arg @ref LL_DMA_STREAM_1
1400 * @arg @ref LL_DMA_STREAM_2
1401 * @arg @ref LL_DMA_STREAM_3
1402 * @arg @ref LL_DMA_STREAM_4
1403 * @arg @ref LL_DMA_STREAM_5
1404 * @arg @ref LL_DMA_STREAM_6
1405 * @arg @ref LL_DMA_STREAM_7
1406 * @param FifoMode This parameter can be one of the following values:
1407 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1408 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1409 * @param FifoThreshold This parameter can be one of the following values:
1410 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1411 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1412 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1413 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1414 * @retval None
1415 */
1416 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1417 {
1418 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FTH|DMA_SxFCR_DMDIS, FifoMode|FifoThreshold);
1419 }
1420
1421 /**
1422 * @brief Configure the Source and Destination addresses.
1423 * @note This API must not be called when the DMA stream is enabled.
1424 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1425 * PAR PA LL_DMA_ConfigAddresses
1426 * @param DMAx DMAx Instance
1427 * @param Stream This parameter can be one of the following values:
1428 * @arg @ref LL_DMA_STREAM_0
1429 * @arg @ref LL_DMA_STREAM_1
1430 * @arg @ref LL_DMA_STREAM_2
1431 * @arg @ref LL_DMA_STREAM_3
1432 * @arg @ref LL_DMA_STREAM_4
1433 * @arg @ref LL_DMA_STREAM_5
1434 * @arg @ref LL_DMA_STREAM_6
1435 * @arg @ref LL_DMA_STREAM_7
1436 * @param SrcAddress Between 0 to 0xFFFFFFFF
1437 * @param DstAddress Between 0 to 0xFFFFFFFF
1438 * @param Direction This parameter can be one of the following values:
1439 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1440 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1441 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1442 * @retval None
1443 */
1444 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1445 {
1446 /* Direction Memory to Periph */
1447 if (Direction == LL_DMA_DIRECTION_MEMORY_TO_PERIPH)
1448 {
1449 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, SrcAddress);
1450 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, DstAddress);
1451 }
1452 /* Direction Periph to Memory and Memory to Memory */
1453 else
1454 {
1455 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, SrcAddress);
1456 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, DstAddress);
1457 }
1458 }
1459
1460 /**
1461 * @brief Set the Memory address.
1462 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1463 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1464 * @note This API must not be called when the DMA channel is enabled.
1465 * @param DMAx DMAx Instance
1466 * @param Stream This parameter can be one of the following values:
1467 * @arg @ref LL_DMA_STREAM_0
1468 * @arg @ref LL_DMA_STREAM_1
1469 * @arg @ref LL_DMA_STREAM_2
1470 * @arg @ref LL_DMA_STREAM_3
1471 * @arg @ref LL_DMA_STREAM_4
1472 * @arg @ref LL_DMA_STREAM_5
1473 * @arg @ref LL_DMA_STREAM_6
1474 * @arg @ref LL_DMA_STREAM_7
1475 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1476 * @retval None
1477 */
1478 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1479 {
1480 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1481 }
1482
1483 /**
1484 * @brief Set the Peripheral address.
1485 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1486 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1487 * @note This API must not be called when the DMA channel is enabled.
1488 * @param DMAx DMAx Instance
1489 * @param Stream This parameter can be one of the following values:
1490 * @arg @ref LL_DMA_STREAM_0
1491 * @arg @ref LL_DMA_STREAM_1
1492 * @arg @ref LL_DMA_STREAM_2
1493 * @arg @ref LL_DMA_STREAM_3
1494 * @arg @ref LL_DMA_STREAM_4
1495 * @arg @ref LL_DMA_STREAM_5
1496 * @arg @ref LL_DMA_STREAM_6
1497 * @arg @ref LL_DMA_STREAM_7
1498 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1499 * @retval None
1500 */
1501 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t PeriphAddress)
1502 {
1503 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, PeriphAddress);
1504 }
1505
1506 /**
1507 * @brief Get the Memory address.
1508 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1509 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1510 * @param DMAx DMAx Instance
1511 * @param Stream This parameter can be one of the following values:
1512 * @arg @ref LL_DMA_STREAM_0
1513 * @arg @ref LL_DMA_STREAM_1
1514 * @arg @ref LL_DMA_STREAM_2
1515 * @arg @ref LL_DMA_STREAM_3
1516 * @arg @ref LL_DMA_STREAM_4
1517 * @arg @ref LL_DMA_STREAM_5
1518 * @arg @ref LL_DMA_STREAM_6
1519 * @arg @ref LL_DMA_STREAM_7
1520 * @retval Between 0 to 0xFFFFFFFF
1521 */
1522 __STATIC_INLINE uint32_t LL_DMA_GetMemoryAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1523 {
1524 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1525 }
1526
1527 /**
1528 * @brief Get the Peripheral address.
1529 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1530 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1531 * @param DMAx DMAx Instance
1532 * @param Stream This parameter can be one of the following values:
1533 * @arg @ref LL_DMA_STREAM_0
1534 * @arg @ref LL_DMA_STREAM_1
1535 * @arg @ref LL_DMA_STREAM_2
1536 * @arg @ref LL_DMA_STREAM_3
1537 * @arg @ref LL_DMA_STREAM_4
1538 * @arg @ref LL_DMA_STREAM_5
1539 * @arg @ref LL_DMA_STREAM_6
1540 * @arg @ref LL_DMA_STREAM_7
1541 * @retval Between 0 to 0xFFFFFFFF
1542 */
1543 __STATIC_INLINE uint32_t LL_DMA_GetPeriphAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1544 {
1545 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1546 }
1547
1548 /**
1549 * @brief Set the Memory to Memory Source address.
1550 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1551 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1552 * @note This API must not be called when the DMA channel is enabled.
1553 * @param DMAx DMAx Instance
1554 * @param Stream This parameter can be one of the following values:
1555 * @arg @ref LL_DMA_STREAM_0
1556 * @arg @ref LL_DMA_STREAM_1
1557 * @arg @ref LL_DMA_STREAM_2
1558 * @arg @ref LL_DMA_STREAM_3
1559 * @arg @ref LL_DMA_STREAM_4
1560 * @arg @ref LL_DMA_STREAM_5
1561 * @arg @ref LL_DMA_STREAM_6
1562 * @arg @ref LL_DMA_STREAM_7
1563 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1564 * @retval None
1565 */
1566 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1567 {
1568 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR, MemoryAddress);
1569 }
1570
1571 /**
1572 * @brief Set the Memory to Memory Destination address.
1573 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1574 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1575 * @note This API must not be called when the DMA channel is enabled.
1576 * @param DMAx DMAx Instance
1577 * @param Stream This parameter can be one of the following values:
1578 * @arg @ref LL_DMA_STREAM_0
1579 * @arg @ref LL_DMA_STREAM_1
1580 * @arg @ref LL_DMA_STREAM_2
1581 * @arg @ref LL_DMA_STREAM_3
1582 * @arg @ref LL_DMA_STREAM_4
1583 * @arg @ref LL_DMA_STREAM_5
1584 * @arg @ref LL_DMA_STREAM_6
1585 * @arg @ref LL_DMA_STREAM_7
1586 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1587 * @retval None
1588 */
1589 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream, uint32_t MemoryAddress)
1590 {
1591 WRITE_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR, MemoryAddress);
1592 }
1593
1594 /**
1595 * @brief Get the Memory to Memory Source address.
1596 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1597 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1598 * @param DMAx DMAx Instance
1599 * @param Stream This parameter can be one of the following values:
1600 * @arg @ref LL_DMA_STREAM_0
1601 * @arg @ref LL_DMA_STREAM_1
1602 * @arg @ref LL_DMA_STREAM_2
1603 * @arg @ref LL_DMA_STREAM_3
1604 * @arg @ref LL_DMA_STREAM_4
1605 * @arg @ref LL_DMA_STREAM_5
1606 * @arg @ref LL_DMA_STREAM_6
1607 * @arg @ref LL_DMA_STREAM_7
1608 * @retval Between 0 to 0xFFFFFFFF
1609 */
1610 __STATIC_INLINE uint32_t LL_DMA_GetM2MSrcAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1611 {
1612 return (READ_REG(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->PAR));
1613 }
1614
1615 /**
1616 * @brief Get the Memory to Memory Destination address.
1617 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1618 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1619 * @param DMAx DMAx Instance
1620 * @param Stream This parameter can be one of the following values:
1621 * @arg @ref LL_DMA_STREAM_0
1622 * @arg @ref LL_DMA_STREAM_1
1623 * @arg @ref LL_DMA_STREAM_2
1624 * @arg @ref LL_DMA_STREAM_3
1625 * @arg @ref LL_DMA_STREAM_4
1626 * @arg @ref LL_DMA_STREAM_5
1627 * @arg @ref LL_DMA_STREAM_6
1628 * @arg @ref LL_DMA_STREAM_7
1629 * @retval Between 0 to 0xFFFFFFFF
1630 */
1631 __STATIC_INLINE uint32_t LL_DMA_GetM2MDstAddress(DMA_TypeDef* DMAx, uint32_t Stream)
1632 {
1633 return (READ_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M0AR));
1634 }
1635
1636 /**
1637 * @brief Set Memory 1 address (used in case of Double buffer mode).
1638 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1639 * @param DMAx DMAx Instance
1640 * @param Stream This parameter can be one of the following values:
1641 * @arg @ref LL_DMA_STREAM_0
1642 * @arg @ref LL_DMA_STREAM_1
1643 * @arg @ref LL_DMA_STREAM_2
1644 * @arg @ref LL_DMA_STREAM_3
1645 * @arg @ref LL_DMA_STREAM_4
1646 * @arg @ref LL_DMA_STREAM_5
1647 * @arg @ref LL_DMA_STREAM_6
1648 * @arg @ref LL_DMA_STREAM_7
1649 * @param Address Between 0 to 0xFFFFFFFF
1650 * @retval None
1651 */
1652 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1653 {
1654 MODIFY_REG(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR, DMA_SxM1AR_M1A, Address);
1655 }
1656
1657 /**
1658 * @brief Get Memory 1 address (used in case of Double buffer mode).
1659 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1660 * @param DMAx DMAx Instance
1661 * @param Stream This parameter can be one of the following values:
1662 * @arg @ref LL_DMA_STREAM_0
1663 * @arg @ref LL_DMA_STREAM_1
1664 * @arg @ref LL_DMA_STREAM_2
1665 * @arg @ref LL_DMA_STREAM_3
1666 * @arg @ref LL_DMA_STREAM_4
1667 * @arg @ref LL_DMA_STREAM_5
1668 * @arg @ref LL_DMA_STREAM_6
1669 * @arg @ref LL_DMA_STREAM_7
1670 * @retval Between 0 to 0xFFFFFFFF
1671 */
1672 __STATIC_INLINE uint32_t LL_DMA_GetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream)
1673 {
1674 return (((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->M1AR);
1675 }
1676
1677 /**
1678 * @}
1679 */
1680
1681 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1682 * @{
1683 */
1684
1685 /**
1686 * @brief Get Stream 0 half transfer flag.
1687 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1688 * @param DMAx DMAx Instance
1689 * @retval State of bit (1 or 0).
1690 */
1691 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT0(DMA_TypeDef *DMAx)
1692 {
1693 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF0)==(DMA_LISR_HTIF0));
1694 }
1695
1696 /**
1697 * @brief Get Stream 1 half transfer flag.
1698 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1699 * @param DMAx DMAx Instance
1700 * @retval State of bit (1 or 0).
1701 */
1702 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT1(DMA_TypeDef *DMAx)
1703 {
1704 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF1)==(DMA_LISR_HTIF1));
1705 }
1706
1707 /**
1708 * @brief Get Stream 2 half transfer flag.
1709 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1710 * @param DMAx DMAx Instance
1711 * @retval State of bit (1 or 0).
1712 */
1713 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT2(DMA_TypeDef *DMAx)
1714 {
1715 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF2)==(DMA_LISR_HTIF2));
1716 }
1717
1718 /**
1719 * @brief Get Stream 3 half transfer flag.
1720 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1721 * @param DMAx DMAx Instance
1722 * @retval State of bit (1 or 0).
1723 */
1724 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT3(DMA_TypeDef *DMAx)
1725 {
1726 return (READ_BIT(DMAx->LISR ,DMA_LISR_HTIF3)==(DMA_LISR_HTIF3));
1727 }
1728
1729 /**
1730 * @brief Get Stream 4 half transfer flag.
1731 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1732 * @param DMAx DMAx Instance
1733 * @retval State of bit (1 or 0).
1734 */
1735 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT4(DMA_TypeDef *DMAx)
1736 {
1737 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF4)==(DMA_HISR_HTIF4));
1738 }
1739
1740 /**
1741 * @brief Get Stream 5 half transfer flag.
1742 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
1743 * @param DMAx DMAx Instance
1744 * @retval State of bit (1 or 0).
1745 */
1746 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT5(DMA_TypeDef *DMAx)
1747 {
1748 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF5)==(DMA_HISR_HTIF5));
1749 }
1750
1751 /**
1752 * @brief Get Stream 6 half transfer flag.
1753 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
1754 * @param DMAx DMAx Instance
1755 * @retval State of bit (1 or 0).
1756 */
1757 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT6(DMA_TypeDef *DMAx)
1758 {
1759 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF6)==(DMA_HISR_HTIF6));
1760 }
1761
1762 /**
1763 * @brief Get Stream 7 half transfer flag.
1764 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
1765 * @param DMAx DMAx Instance
1766 * @retval State of bit (1 or 0).
1767 */
1768 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_HT7(DMA_TypeDef *DMAx)
1769 {
1770 return (READ_BIT(DMAx->HISR ,DMA_HISR_HTIF7)==(DMA_HISR_HTIF7));
1771 }
1772
1773 /**
1774 * @brief Get Stream 0 transfer complete flag.
1775 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
1776 * @param DMAx DMAx Instance
1777 * @retval State of bit (1 or 0).
1778 */
1779 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC0(DMA_TypeDef *DMAx)
1780 {
1781 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF0)==(DMA_LISR_TCIF0));
1782 }
1783
1784 /**
1785 * @brief Get Stream 1 transfer complete flag.
1786 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
1787 * @param DMAx DMAx Instance
1788 * @retval State of bit (1 or 0).
1789 */
1790 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC1(DMA_TypeDef *DMAx)
1791 {
1792 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF1)==(DMA_LISR_TCIF1));
1793 }
1794
1795 /**
1796 * @brief Get Stream 2 transfer complete flag.
1797 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
1798 * @param DMAx DMAx Instance
1799 * @retval State of bit (1 or 0).
1800 */
1801 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC2(DMA_TypeDef *DMAx)
1802 {
1803 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF2)==(DMA_LISR_TCIF2));
1804 }
1805
1806 /**
1807 * @brief Get Stream 3 transfer complete flag.
1808 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
1809 * @param DMAx DMAx Instance
1810 * @retval State of bit (1 or 0).
1811 */
1812 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC3(DMA_TypeDef *DMAx)
1813 {
1814 return (READ_BIT(DMAx->LISR ,DMA_LISR_TCIF3)==(DMA_LISR_TCIF3));
1815 }
1816
1817 /**
1818 * @brief Get Stream 4 transfer complete flag.
1819 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
1820 * @param DMAx DMAx Instance
1821 * @retval State of bit (1 or 0).
1822 */
1823 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC4(DMA_TypeDef *DMAx)
1824 {
1825 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF4)==(DMA_HISR_TCIF4));
1826 }
1827
1828 /**
1829 * @brief Get Stream 5 transfer complete flag.
1830 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
1831 * @param DMAx DMAx Instance
1832 * @retval State of bit (1 or 0).
1833 */
1834 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC5(DMA_TypeDef *DMAx)
1835 {
1836 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF5)==(DMA_HISR_TCIF5));
1837 }
1838
1839 /**
1840 * @brief Get Stream 6 transfer complete flag.
1841 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
1842 * @param DMAx DMAx Instance
1843 * @retval State of bit (1 or 0).
1844 */
1845 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC6(DMA_TypeDef *DMAx)
1846 {
1847 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF6)==(DMA_HISR_TCIF6));
1848 }
1849
1850 /**
1851 * @brief Get Stream 7 transfer complete flag.
1852 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
1853 * @param DMAx DMAx Instance
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TC7(DMA_TypeDef *DMAx)
1857 {
1858 return (READ_BIT(DMAx->HISR ,DMA_HISR_TCIF7)==(DMA_HISR_TCIF7));
1859 }
1860
1861 /**
1862 * @brief Get Stream 0 transfer error flag.
1863 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
1864 * @param DMAx DMAx Instance
1865 * @retval State of bit (1 or 0).
1866 */
1867 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE0(DMA_TypeDef *DMAx)
1868 {
1869 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF0)==(DMA_LISR_TEIF0));
1870 }
1871
1872 /**
1873 * @brief Get Stream 1 transfer error flag.
1874 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
1875 * @param DMAx DMAx Instance
1876 * @retval State of bit (1 or 0).
1877 */
1878 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE1(DMA_TypeDef *DMAx)
1879 {
1880 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF1)==(DMA_LISR_TEIF1));
1881 }
1882
1883 /**
1884 * @brief Get Stream 2 transfer error flag.
1885 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
1886 * @param DMAx DMAx Instance
1887 * @retval State of bit (1 or 0).
1888 */
1889 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE2(DMA_TypeDef *DMAx)
1890 {
1891 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF2)==(DMA_LISR_TEIF2));
1892 }
1893
1894 /**
1895 * @brief Get Stream 3 transfer error flag.
1896 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
1897 * @param DMAx DMAx Instance
1898 * @retval State of bit (1 or 0).
1899 */
1900 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE3(DMA_TypeDef *DMAx)
1901 {
1902 return (READ_BIT(DMAx->LISR ,DMA_LISR_TEIF3)==(DMA_LISR_TEIF3));
1903 }
1904
1905 /**
1906 * @brief Get Stream 4 transfer error flag.
1907 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
1908 * @param DMAx DMAx Instance
1909 * @retval State of bit (1 or 0).
1910 */
1911 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE4(DMA_TypeDef *DMAx)
1912 {
1913 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF4)==(DMA_HISR_TEIF4));
1914 }
1915
1916 /**
1917 * @brief Get Stream 5 transfer error flag.
1918 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
1919 * @param DMAx DMAx Instance
1920 * @retval State of bit (1 or 0).
1921 */
1922 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE5(DMA_TypeDef *DMAx)
1923 {
1924 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF5)==(DMA_HISR_TEIF5));
1925 }
1926
1927 /**
1928 * @brief Get Stream 6 transfer error flag.
1929 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
1930 * @param DMAx DMAx Instance
1931 * @retval State of bit (1 or 0).
1932 */
1933 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE6(DMA_TypeDef *DMAx)
1934 {
1935 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF6)==(DMA_HISR_TEIF6));
1936 }
1937
1938 /**
1939 * @brief Get Stream 7 transfer error flag.
1940 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
1941 * @param DMAx DMAx Instance
1942 * @retval State of bit (1 or 0).
1943 */
1944 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_TE7(DMA_TypeDef *DMAx)
1945 {
1946 return (READ_BIT(DMAx->HISR ,DMA_HISR_TEIF7)==(DMA_HISR_TEIF7));
1947 }
1948
1949 /**
1950 * @brief Get Stream 0 direct mode error flag.
1951 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
1952 * @param DMAx DMAx Instance
1953 * @retval State of bit (1 or 0).
1954 */
1955 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME0(DMA_TypeDef *DMAx)
1956 {
1957 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF0)==(DMA_LISR_DMEIF0));
1958 }
1959
1960 /**
1961 * @brief Get Stream 1 direct mode error flag.
1962 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
1963 * @param DMAx DMAx Instance
1964 * @retval State of bit (1 or 0).
1965 */
1966 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME1(DMA_TypeDef *DMAx)
1967 {
1968 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF1)==(DMA_LISR_DMEIF1));
1969 }
1970
1971 /**
1972 * @brief Get Stream 2 direct mode error flag.
1973 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
1974 * @param DMAx DMAx Instance
1975 * @retval State of bit (1 or 0).
1976 */
1977 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME2(DMA_TypeDef *DMAx)
1978 {
1979 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF2)==(DMA_LISR_DMEIF2));
1980 }
1981
1982 /**
1983 * @brief Get Stream 3 direct mode error flag.
1984 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
1985 * @param DMAx DMAx Instance
1986 * @retval State of bit (1 or 0).
1987 */
1988 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME3(DMA_TypeDef *DMAx)
1989 {
1990 return (READ_BIT(DMAx->LISR ,DMA_LISR_DMEIF3)==(DMA_LISR_DMEIF3));
1991 }
1992
1993 /**
1994 * @brief Get Stream 4 direct mode error flag.
1995 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
1996 * @param DMAx DMAx Instance
1997 * @retval State of bit (1 or 0).
1998 */
1999 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME4(DMA_TypeDef *DMAx)
2000 {
2001 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF4)==(DMA_HISR_DMEIF4));
2002 }
2003
2004 /**
2005 * @brief Get Stream 5 direct mode error flag.
2006 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2007 * @param DMAx DMAx Instance
2008 * @retval State of bit (1 or 0).
2009 */
2010 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME5(DMA_TypeDef *DMAx)
2011 {
2012 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF5)==(DMA_HISR_DMEIF5));
2013 }
2014
2015 /**
2016 * @brief Get Stream 6 direct mode error flag.
2017 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2018 * @param DMAx DMAx Instance
2019 * @retval State of bit (1 or 0).
2020 */
2021 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME6(DMA_TypeDef *DMAx)
2022 {
2023 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF6)==(DMA_HISR_DMEIF6));
2024 }
2025
2026 /**
2027 * @brief Get Stream 7 direct mode error flag.
2028 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2029 * @param DMAx DMAx Instance
2030 * @retval State of bit (1 or 0).
2031 */
2032 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_DME7(DMA_TypeDef *DMAx)
2033 {
2034 return (READ_BIT(DMAx->HISR ,DMA_HISR_DMEIF7)==(DMA_HISR_DMEIF7));
2035 }
2036
2037 /**
2038 * @brief Get Stream 0 FIFO error flag.
2039 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2040 * @param DMAx DMAx Instance
2041 * @retval State of bit (1 or 0).
2042 */
2043 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE0(DMA_TypeDef *DMAx)
2044 {
2045 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF0)==(DMA_LISR_FEIF0));
2046 }
2047
2048 /**
2049 * @brief Get Stream 1 FIFO error flag.
2050 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2051 * @param DMAx DMAx Instance
2052 * @retval State of bit (1 or 0).
2053 */
2054 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE1(DMA_TypeDef *DMAx)
2055 {
2056 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF1)==(DMA_LISR_FEIF1));
2057 }
2058
2059 /**
2060 * @brief Get Stream 2 FIFO error flag.
2061 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2062 * @param DMAx DMAx Instance
2063 * @retval State of bit (1 or 0).
2064 */
2065 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE2(DMA_TypeDef *DMAx)
2066 {
2067 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF2)==(DMA_LISR_FEIF2));
2068 }
2069
2070 /**
2071 * @brief Get Stream 3 FIFO error flag.
2072 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2073 * @param DMAx DMAx Instance
2074 * @retval State of bit (1 or 0).
2075 */
2076 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE3(DMA_TypeDef *DMAx)
2077 {
2078 return (READ_BIT(DMAx->LISR ,DMA_LISR_FEIF3)==(DMA_LISR_FEIF3));
2079 }
2080
2081 /**
2082 * @brief Get Stream 4 FIFO error flag.
2083 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2084 * @param DMAx DMAx Instance
2085 * @retval State of bit (1 or 0).
2086 */
2087 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE4(DMA_TypeDef *DMAx)
2088 {
2089 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF4)==(DMA_HISR_FEIF4));
2090 }
2091
2092 /**
2093 * @brief Get Stream 5 FIFO error flag.
2094 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2095 * @param DMAx DMAx Instance
2096 * @retval State of bit (1 or 0).
2097 */
2098 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE5(DMA_TypeDef *DMAx)
2099 {
2100 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF5)==(DMA_HISR_FEIF5));
2101 }
2102
2103 /**
2104 * @brief Get Stream 6 FIFO error flag.
2105 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2106 * @param DMAx DMAx Instance
2107 * @retval State of bit (1 or 0).
2108 */
2109 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE6(DMA_TypeDef *DMAx)
2110 {
2111 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF6)==(DMA_HISR_FEIF6));
2112 }
2113
2114 /**
2115 * @brief Get Stream 7 FIFO error flag.
2116 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2117 * @param DMAx DMAx Instance
2118 * @retval State of bit (1 or 0).
2119 */
2120 __STATIC_INLINE uint32_t LL_DMA_IsActiveFlag_FE7(DMA_TypeDef *DMAx)
2121 {
2122 return (READ_BIT(DMAx->HISR ,DMA_HISR_FEIF7)==(DMA_HISR_FEIF7));
2123 }
2124
2125 /**
2126 * @brief Clear Stream 0 half transfer flag.
2127 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2128 * @param DMAx DMAx Instance
2129 * @retval None
2130 */
2131 __STATIC_INLINE void LL_DMA_ClearFlag_HT0(DMA_TypeDef *DMAx)
2132 {
2133 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF0);
2134 }
2135
2136 /**
2137 * @brief Clear Stream 1 half transfer flag.
2138 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2139 * @param DMAx DMAx Instance
2140 * @retval None
2141 */
2142 __STATIC_INLINE void LL_DMA_ClearFlag_HT1(DMA_TypeDef *DMAx)
2143 {
2144 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF1);
2145 }
2146
2147 /**
2148 * @brief Clear Stream 2 half transfer flag.
2149 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2150 * @param DMAx DMAx Instance
2151 * @retval None
2152 */
2153 __STATIC_INLINE void LL_DMA_ClearFlag_HT2(DMA_TypeDef *DMAx)
2154 {
2155 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF2);
2156 }
2157
2158 /**
2159 * @brief Clear Stream 3 half transfer flag.
2160 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2161 * @param DMAx DMAx Instance
2162 * @retval None
2163 */
2164 __STATIC_INLINE void LL_DMA_ClearFlag_HT3(DMA_TypeDef *DMAx)
2165 {
2166 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CHTIF3);
2167 }
2168
2169 /**
2170 * @brief Clear Stream 4 half transfer flag.
2171 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2172 * @param DMAx DMAx Instance
2173 * @retval None
2174 */
2175 __STATIC_INLINE void LL_DMA_ClearFlag_HT4(DMA_TypeDef *DMAx)
2176 {
2177 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF4);
2178 }
2179
2180 /**
2181 * @brief Clear Stream 5 half transfer flag.
2182 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2183 * @param DMAx DMAx Instance
2184 * @retval None
2185 */
2186 __STATIC_INLINE void LL_DMA_ClearFlag_HT5(DMA_TypeDef *DMAx)
2187 {
2188 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF5);
2189 }
2190
2191 /**
2192 * @brief Clear Stream 6 half transfer flag.
2193 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2194 * @param DMAx DMAx Instance
2195 * @retval None
2196 */
2197 __STATIC_INLINE void LL_DMA_ClearFlag_HT6(DMA_TypeDef *DMAx)
2198 {
2199 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF6);
2200 }
2201
2202 /**
2203 * @brief Clear Stream 7 half transfer flag.
2204 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2205 * @param DMAx DMAx Instance
2206 * @retval None
2207 */
2208 __STATIC_INLINE void LL_DMA_ClearFlag_HT7(DMA_TypeDef *DMAx)
2209 {
2210 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CHTIF7);
2211 }
2212
2213 /**
2214 * @brief Clear Stream 0 transfer complete flag.
2215 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2216 * @param DMAx DMAx Instance
2217 * @retval None
2218 */
2219 __STATIC_INLINE void LL_DMA_ClearFlag_TC0(DMA_TypeDef *DMAx)
2220 {
2221 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF0);
2222 }
2223
2224 /**
2225 * @brief Clear Stream 1 transfer complete flag.
2226 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2227 * @param DMAx DMAx Instance
2228 * @retval None
2229 */
2230 __STATIC_INLINE void LL_DMA_ClearFlag_TC1(DMA_TypeDef *DMAx)
2231 {
2232 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF1);
2233 }
2234
2235 /**
2236 * @brief Clear Stream 2 transfer complete flag.
2237 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2238 * @param DMAx DMAx Instance
2239 * @retval None
2240 */
2241 __STATIC_INLINE void LL_DMA_ClearFlag_TC2(DMA_TypeDef *DMAx)
2242 {
2243 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF2);
2244 }
2245
2246 /**
2247 * @brief Clear Stream 3 transfer complete flag.
2248 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2249 * @param DMAx DMAx Instance
2250 * @retval None
2251 */
2252 __STATIC_INLINE void LL_DMA_ClearFlag_TC3(DMA_TypeDef *DMAx)
2253 {
2254 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTCIF3);
2255 }
2256
2257 /**
2258 * @brief Clear Stream 4 transfer complete flag.
2259 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2260 * @param DMAx DMAx Instance
2261 * @retval None
2262 */
2263 __STATIC_INLINE void LL_DMA_ClearFlag_TC4(DMA_TypeDef *DMAx)
2264 {
2265 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF4);
2266 }
2267
2268 /**
2269 * @brief Clear Stream 5 transfer complete flag.
2270 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2271 * @param DMAx DMAx Instance
2272 * @retval None
2273 */
2274 __STATIC_INLINE void LL_DMA_ClearFlag_TC5(DMA_TypeDef *DMAx)
2275 {
2276 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF5);
2277 }
2278
2279 /**
2280 * @brief Clear Stream 6 transfer complete flag.
2281 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2282 * @param DMAx DMAx Instance
2283 * @retval None
2284 */
2285 __STATIC_INLINE void LL_DMA_ClearFlag_TC6(DMA_TypeDef *DMAx)
2286 {
2287 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF6);
2288 }
2289
2290 /**
2291 * @brief Clear Stream 7 transfer complete flag.
2292 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2293 * @param DMAx DMAx Instance
2294 * @retval None
2295 */
2296 __STATIC_INLINE void LL_DMA_ClearFlag_TC7(DMA_TypeDef *DMAx)
2297 {
2298 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTCIF7);
2299 }
2300
2301 /**
2302 * @brief Clear Stream 0 transfer error flag.
2303 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2304 * @param DMAx DMAx Instance
2305 * @retval None
2306 */
2307 __STATIC_INLINE void LL_DMA_ClearFlag_TE0(DMA_TypeDef *DMAx)
2308 {
2309 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF0);
2310 }
2311
2312 /**
2313 * @brief Clear Stream 1 transfer error flag.
2314 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2315 * @param DMAx DMAx Instance
2316 * @retval None
2317 */
2318 __STATIC_INLINE void LL_DMA_ClearFlag_TE1(DMA_TypeDef *DMAx)
2319 {
2320 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF1);
2321 }
2322
2323 /**
2324 * @brief Clear Stream 2 transfer error flag.
2325 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2326 * @param DMAx DMAx Instance
2327 * @retval None
2328 */
2329 __STATIC_INLINE void LL_DMA_ClearFlag_TE2(DMA_TypeDef *DMAx)
2330 {
2331 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF2);
2332 }
2333
2334 /**
2335 * @brief Clear Stream 3 transfer error flag.
2336 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2337 * @param DMAx DMAx Instance
2338 * @retval None
2339 */
2340 __STATIC_INLINE void LL_DMA_ClearFlag_TE3(DMA_TypeDef *DMAx)
2341 {
2342 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CTEIF3);
2343 }
2344
2345 /**
2346 * @brief Clear Stream 4 transfer error flag.
2347 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2348 * @param DMAx DMAx Instance
2349 * @retval None
2350 */
2351 __STATIC_INLINE void LL_DMA_ClearFlag_TE4(DMA_TypeDef *DMAx)
2352 {
2353 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF4);
2354 }
2355
2356 /**
2357 * @brief Clear Stream 5 transfer error flag.
2358 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2359 * @param DMAx DMAx Instance
2360 * @retval None
2361 */
2362 __STATIC_INLINE void LL_DMA_ClearFlag_TE5(DMA_TypeDef *DMAx)
2363 {
2364 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF5);
2365 }
2366
2367 /**
2368 * @brief Clear Stream 6 transfer error flag.
2369 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2370 * @param DMAx DMAx Instance
2371 * @retval None
2372 */
2373 __STATIC_INLINE void LL_DMA_ClearFlag_TE6(DMA_TypeDef *DMAx)
2374 {
2375 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF6);
2376 }
2377
2378 /**
2379 * @brief Clear Stream 7 transfer error flag.
2380 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2381 * @param DMAx DMAx Instance
2382 * @retval None
2383 */
2384 __STATIC_INLINE void LL_DMA_ClearFlag_TE7(DMA_TypeDef *DMAx)
2385 {
2386 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CTEIF7);
2387 }
2388
2389 /**
2390 * @brief Clear Stream 0 direct mode error flag.
2391 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2392 * @param DMAx DMAx Instance
2393 * @retval None
2394 */
2395 __STATIC_INLINE void LL_DMA_ClearFlag_DME0(DMA_TypeDef *DMAx)
2396 {
2397 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF0);
2398 }
2399
2400 /**
2401 * @brief Clear Stream 1 direct mode error flag.
2402 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2403 * @param DMAx DMAx Instance
2404 * @retval None
2405 */
2406 __STATIC_INLINE void LL_DMA_ClearFlag_DME1(DMA_TypeDef *DMAx)
2407 {
2408 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF1);
2409 }
2410
2411 /**
2412 * @brief Clear Stream 2 direct mode error flag.
2413 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2414 * @param DMAx DMAx Instance
2415 * @retval None
2416 */
2417 __STATIC_INLINE void LL_DMA_ClearFlag_DME2(DMA_TypeDef *DMAx)
2418 {
2419 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF2);
2420 }
2421
2422 /**
2423 * @brief Clear Stream 3 direct mode error flag.
2424 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2425 * @param DMAx DMAx Instance
2426 * @retval None
2427 */
2428 __STATIC_INLINE void LL_DMA_ClearFlag_DME3(DMA_TypeDef *DMAx)
2429 {
2430 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CDMEIF3);
2431 }
2432
2433 /**
2434 * @brief Clear Stream 4 direct mode error flag.
2435 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2436 * @param DMAx DMAx Instance
2437 * @retval None
2438 */
2439 __STATIC_INLINE void LL_DMA_ClearFlag_DME4(DMA_TypeDef *DMAx)
2440 {
2441 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF4);
2442 }
2443
2444 /**
2445 * @brief Clear Stream 5 direct mode error flag.
2446 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2447 * @param DMAx DMAx Instance
2448 * @retval None
2449 */
2450 __STATIC_INLINE void LL_DMA_ClearFlag_DME5(DMA_TypeDef *DMAx)
2451 {
2452 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF5);
2453 }
2454
2455 /**
2456 * @brief Clear Stream 6 direct mode error flag.
2457 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2458 * @param DMAx DMAx Instance
2459 * @retval None
2460 */
2461 __STATIC_INLINE void LL_DMA_ClearFlag_DME6(DMA_TypeDef *DMAx)
2462 {
2463 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF6);
2464 }
2465
2466 /**
2467 * @brief Clear Stream 7 direct mode error flag.
2468 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2469 * @param DMAx DMAx Instance
2470 * @retval None
2471 */
2472 __STATIC_INLINE void LL_DMA_ClearFlag_DME7(DMA_TypeDef *DMAx)
2473 {
2474 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CDMEIF7);
2475 }
2476
2477 /**
2478 * @brief Clear Stream 0 FIFO error flag.
2479 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2480 * @param DMAx DMAx Instance
2481 * @retval None
2482 */
2483 __STATIC_INLINE void LL_DMA_ClearFlag_FE0(DMA_TypeDef *DMAx)
2484 {
2485 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF0);
2486 }
2487
2488 /**
2489 * @brief Clear Stream 1 FIFO error flag.
2490 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2491 * @param DMAx DMAx Instance
2492 * @retval None
2493 */
2494 __STATIC_INLINE void LL_DMA_ClearFlag_FE1(DMA_TypeDef *DMAx)
2495 {
2496 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF1);
2497 }
2498
2499 /**
2500 * @brief Clear Stream 2 FIFO error flag.
2501 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2502 * @param DMAx DMAx Instance
2503 * @retval None
2504 */
2505 __STATIC_INLINE void LL_DMA_ClearFlag_FE2(DMA_TypeDef *DMAx)
2506 {
2507 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF2);
2508 }
2509
2510 /**
2511 * @brief Clear Stream 3 FIFO error flag.
2512 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2513 * @param DMAx DMAx Instance
2514 * @retval None
2515 */
2516 __STATIC_INLINE void LL_DMA_ClearFlag_FE3(DMA_TypeDef *DMAx)
2517 {
2518 SET_BIT(DMAx->LIFCR , DMA_LIFCR_CFEIF3);
2519 }
2520
2521 /**
2522 * @brief Clear Stream 4 FIFO error flag.
2523 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2524 * @param DMAx DMAx Instance
2525 * @retval None
2526 */
2527 __STATIC_INLINE void LL_DMA_ClearFlag_FE4(DMA_TypeDef *DMAx)
2528 {
2529 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF4);
2530 }
2531
2532 /**
2533 * @brief Clear Stream 5 FIFO error flag.
2534 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2535 * @param DMAx DMAx Instance
2536 * @retval None
2537 */
2538 __STATIC_INLINE void LL_DMA_ClearFlag_FE5(DMA_TypeDef *DMAx)
2539 {
2540 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF5);
2541 }
2542
2543 /**
2544 * @brief Clear Stream 6 FIFO error flag.
2545 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2546 * @param DMAx DMAx Instance
2547 * @retval None
2548 */
2549 __STATIC_INLINE void LL_DMA_ClearFlag_FE6(DMA_TypeDef *DMAx)
2550 {
2551 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF6);
2552 }
2553
2554 /**
2555 * @brief Clear Stream 7 FIFO error flag.
2556 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2557 * @param DMAx DMAx Instance
2558 * @retval None
2559 */
2560 __STATIC_INLINE void LL_DMA_ClearFlag_FE7(DMA_TypeDef *DMAx)
2561 {
2562 SET_BIT(DMAx->HIFCR , DMA_HIFCR_CFEIF7);
2563 }
2564
2565 /**
2566 * @}
2567 */
2568
2569 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2570 * @{
2571 */
2572
2573 /**
2574 * @brief Enable Half transfer interrupt.
2575 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2576 * @param DMAx DMAx Instance
2577 * @param Stream This parameter can be one of the following values:
2578 * @arg @ref LL_DMA_STREAM_0
2579 * @arg @ref LL_DMA_STREAM_1
2580 * @arg @ref LL_DMA_STREAM_2
2581 * @arg @ref LL_DMA_STREAM_3
2582 * @arg @ref LL_DMA_STREAM_4
2583 * @arg @ref LL_DMA_STREAM_5
2584 * @arg @ref LL_DMA_STREAM_6
2585 * @arg @ref LL_DMA_STREAM_7
2586 * @retval None
2587 */
2588 __STATIC_INLINE void LL_DMA_EnableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2589 {
2590 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2591 }
2592
2593 /**
2594 * @brief Enable Transfer error interrupt.
2595 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2596 * @param DMAx DMAx Instance
2597 * @param Stream This parameter can be one of the following values:
2598 * @arg @ref LL_DMA_STREAM_0
2599 * @arg @ref LL_DMA_STREAM_1
2600 * @arg @ref LL_DMA_STREAM_2
2601 * @arg @ref LL_DMA_STREAM_3
2602 * @arg @ref LL_DMA_STREAM_4
2603 * @arg @ref LL_DMA_STREAM_5
2604 * @arg @ref LL_DMA_STREAM_6
2605 * @arg @ref LL_DMA_STREAM_7
2606 * @retval None
2607 */
2608 __STATIC_INLINE void LL_DMA_EnableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2609 {
2610 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2611 }
2612
2613 /**
2614 * @brief Enable Transfer complete interrupt.
2615 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2616 * @param DMAx DMAx Instance
2617 * @param Stream This parameter can be one of the following values:
2618 * @arg @ref LL_DMA_STREAM_0
2619 * @arg @ref LL_DMA_STREAM_1
2620 * @arg @ref LL_DMA_STREAM_2
2621 * @arg @ref LL_DMA_STREAM_3
2622 * @arg @ref LL_DMA_STREAM_4
2623 * @arg @ref LL_DMA_STREAM_5
2624 * @arg @ref LL_DMA_STREAM_6
2625 * @arg @ref LL_DMA_STREAM_7
2626 * @retval None
2627 */
2628 __STATIC_INLINE void LL_DMA_EnableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2629 {
2630 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2631 }
2632
2633 /**
2634 * @brief Enable Direct mode error interrupt.
2635 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2636 * @param DMAx DMAx Instance
2637 * @param Stream This parameter can be one of the following values:
2638 * @arg @ref LL_DMA_STREAM_0
2639 * @arg @ref LL_DMA_STREAM_1
2640 * @arg @ref LL_DMA_STREAM_2
2641 * @arg @ref LL_DMA_STREAM_3
2642 * @arg @ref LL_DMA_STREAM_4
2643 * @arg @ref LL_DMA_STREAM_5
2644 * @arg @ref LL_DMA_STREAM_6
2645 * @arg @ref LL_DMA_STREAM_7
2646 * @retval None
2647 */
2648 __STATIC_INLINE void LL_DMA_EnableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2649 {
2650 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2651 }
2652
2653 /**
2654 * @brief Enable FIFO error interrupt.
2655 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2656 * @param DMAx DMAx Instance
2657 * @param Stream This parameter can be one of the following values:
2658 * @arg @ref LL_DMA_STREAM_0
2659 * @arg @ref LL_DMA_STREAM_1
2660 * @arg @ref LL_DMA_STREAM_2
2661 * @arg @ref LL_DMA_STREAM_3
2662 * @arg @ref LL_DMA_STREAM_4
2663 * @arg @ref LL_DMA_STREAM_5
2664 * @arg @ref LL_DMA_STREAM_6
2665 * @arg @ref LL_DMA_STREAM_7
2666 * @retval None
2667 */
2668 __STATIC_INLINE void LL_DMA_EnableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2669 {
2670 SET_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2671 }
2672
2673 /**
2674 * @brief Disable Half transfer interrupt.
2675 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2676 * @param DMAx DMAx Instance
2677 * @param Stream This parameter can be one of the following values:
2678 * @arg @ref LL_DMA_STREAM_0
2679 * @arg @ref LL_DMA_STREAM_1
2680 * @arg @ref LL_DMA_STREAM_2
2681 * @arg @ref LL_DMA_STREAM_3
2682 * @arg @ref LL_DMA_STREAM_4
2683 * @arg @ref LL_DMA_STREAM_5
2684 * @arg @ref LL_DMA_STREAM_6
2685 * @arg @ref LL_DMA_STREAM_7
2686 * @retval None
2687 */
2688 __STATIC_INLINE void LL_DMA_DisableIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2689 {
2690 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE);
2691 }
2692
2693 /**
2694 * @brief Disable Transfer error interrupt.
2695 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2696 * @param DMAx DMAx Instance
2697 * @param Stream This parameter can be one of the following values:
2698 * @arg @ref LL_DMA_STREAM_0
2699 * @arg @ref LL_DMA_STREAM_1
2700 * @arg @ref LL_DMA_STREAM_2
2701 * @arg @ref LL_DMA_STREAM_3
2702 * @arg @ref LL_DMA_STREAM_4
2703 * @arg @ref LL_DMA_STREAM_5
2704 * @arg @ref LL_DMA_STREAM_6
2705 * @arg @ref LL_DMA_STREAM_7
2706 * @retval None
2707 */
2708 __STATIC_INLINE void LL_DMA_DisableIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2709 {
2710 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE);
2711 }
2712
2713 /**
2714 * @brief Disable Transfer complete interrupt.
2715 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2716 * @param DMAx DMAx Instance
2717 * @param Stream This parameter can be one of the following values:
2718 * @arg @ref LL_DMA_STREAM_0
2719 * @arg @ref LL_DMA_STREAM_1
2720 * @arg @ref LL_DMA_STREAM_2
2721 * @arg @ref LL_DMA_STREAM_3
2722 * @arg @ref LL_DMA_STREAM_4
2723 * @arg @ref LL_DMA_STREAM_5
2724 * @arg @ref LL_DMA_STREAM_6
2725 * @arg @ref LL_DMA_STREAM_7
2726 * @retval None
2727 */
2728 __STATIC_INLINE void LL_DMA_DisableIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2729 {
2730 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE);
2731 }
2732
2733 /**
2734 * @brief Disable Direct mode error interrupt.
2735 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
2736 * @param DMAx DMAx Instance
2737 * @param Stream This parameter can be one of the following values:
2738 * @arg @ref LL_DMA_STREAM_0
2739 * @arg @ref LL_DMA_STREAM_1
2740 * @arg @ref LL_DMA_STREAM_2
2741 * @arg @ref LL_DMA_STREAM_3
2742 * @arg @ref LL_DMA_STREAM_4
2743 * @arg @ref LL_DMA_STREAM_5
2744 * @arg @ref LL_DMA_STREAM_6
2745 * @arg @ref LL_DMA_STREAM_7
2746 * @retval None
2747 */
2748 __STATIC_INLINE void LL_DMA_DisableIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2749 {
2750 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE);
2751 }
2752
2753 /**
2754 * @brief Disable FIFO error interrupt.
2755 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
2756 * @param DMAx DMAx Instance
2757 * @param Stream This parameter can be one of the following values:
2758 * @arg @ref LL_DMA_STREAM_0
2759 * @arg @ref LL_DMA_STREAM_1
2760 * @arg @ref LL_DMA_STREAM_2
2761 * @arg @ref LL_DMA_STREAM_3
2762 * @arg @ref LL_DMA_STREAM_4
2763 * @arg @ref LL_DMA_STREAM_5
2764 * @arg @ref LL_DMA_STREAM_6
2765 * @arg @ref LL_DMA_STREAM_7
2766 * @retval None
2767 */
2768 __STATIC_INLINE void LL_DMA_DisableIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2769 {
2770 CLEAR_BIT(((DMA_Stream_TypeDef *)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE);
2771 }
2772
2773 /**
2774 * @brief Check if Half transfer interrup is enabled.
2775 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
2776 * @param DMAx DMAx Instance
2777 * @param Stream This parameter can be one of the following values:
2778 * @arg @ref LL_DMA_STREAM_0
2779 * @arg @ref LL_DMA_STREAM_1
2780 * @arg @ref LL_DMA_STREAM_2
2781 * @arg @ref LL_DMA_STREAM_3
2782 * @arg @ref LL_DMA_STREAM_4
2783 * @arg @ref LL_DMA_STREAM_5
2784 * @arg @ref LL_DMA_STREAM_6
2785 * @arg @ref LL_DMA_STREAM_7
2786 * @retval State of bit (1 or 0).
2787 */
2788 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_HT(DMA_TypeDef *DMAx, uint32_t Stream)
2789 {
2790 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE);
2791 }
2792
2793 /**
2794 * @brief Check if Transfer error nterrup is enabled.
2795 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
2796 * @param DMAx DMAx Instance
2797 * @param Stream This parameter can be one of the following values:
2798 * @arg @ref LL_DMA_STREAM_0
2799 * @arg @ref LL_DMA_STREAM_1
2800 * @arg @ref LL_DMA_STREAM_2
2801 * @arg @ref LL_DMA_STREAM_3
2802 * @arg @ref LL_DMA_STREAM_4
2803 * @arg @ref LL_DMA_STREAM_5
2804 * @arg @ref LL_DMA_STREAM_6
2805 * @arg @ref LL_DMA_STREAM_7
2806 * @retval State of bit (1 or 0).
2807 */
2808 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TE(DMA_TypeDef *DMAx, uint32_t Stream)
2809 {
2810 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE);
2811 }
2812
2813 /**
2814 * @brief Check if Transfer complete interrup is enabled.
2815 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
2816 * @param DMAx DMAx Instance
2817 * @param Stream This parameter can be one of the following values:
2818 * @arg @ref LL_DMA_STREAM_0
2819 * @arg @ref LL_DMA_STREAM_1
2820 * @arg @ref LL_DMA_STREAM_2
2821 * @arg @ref LL_DMA_STREAM_3
2822 * @arg @ref LL_DMA_STREAM_4
2823 * @arg @ref LL_DMA_STREAM_5
2824 * @arg @ref LL_DMA_STREAM_6
2825 * @arg @ref LL_DMA_STREAM_7
2826 * @retval State of bit (1 or 0).
2827 */
2828 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_TC(DMA_TypeDef *DMAx, uint32_t Stream)
2829 {
2830 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE);
2831 }
2832
2833 /**
2834 * @brief Check if Direct mode error interrupt is enabled.
2835 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
2836 * @param DMAx DMAx Instance
2837 * @param Stream This parameter can be one of the following values:
2838 * @arg @ref LL_DMA_STREAM_0
2839 * @arg @ref LL_DMA_STREAM_1
2840 * @arg @ref LL_DMA_STREAM_2
2841 * @arg @ref LL_DMA_STREAM_3
2842 * @arg @ref LL_DMA_STREAM_4
2843 * @arg @ref LL_DMA_STREAM_5
2844 * @arg @ref LL_DMA_STREAM_6
2845 * @arg @ref LL_DMA_STREAM_7
2846 * @retval State of bit (1 or 0).
2847 */
2848 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_DME(DMA_TypeDef *DMAx, uint32_t Stream)
2849 {
2850 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE);
2851 }
2852
2853 /**
2854 * @brief Check if FIFO error interrup is enabled.
2855 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
2856 * @param DMAx DMAx Instance
2857 * @param Stream This parameter can be one of the following values:
2858 * @arg @ref LL_DMA_STREAM_0
2859 * @arg @ref LL_DMA_STREAM_1
2860 * @arg @ref LL_DMA_STREAM_2
2861 * @arg @ref LL_DMA_STREAM_3
2862 * @arg @ref LL_DMA_STREAM_4
2863 * @arg @ref LL_DMA_STREAM_5
2864 * @arg @ref LL_DMA_STREAM_6
2865 * @arg @ref LL_DMA_STREAM_7
2866 * @retval State of bit (1 or 0).
2867 */
2868 __STATIC_INLINE uint32_t LL_DMA_IsEnabledIT_FE(DMA_TypeDef *DMAx, uint32_t Stream)
2869 {
2870 return (READ_BIT(((DMA_Stream_TypeDef*)((uint32_t)((uint32_t)DMAx + STREAM_OFFSET_TAB[Stream])))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE);
2871 }
2872
2873 /**
2874 * @}
2875 */
2876
2877 #if defined(USE_FULL_LL_DRIVER)
2878 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
2879 * @{
2880 */
2881
2882 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct);
2883 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream);
2884 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct);
2885
2886 /**
2887 * @}
2888 */
2889 #endif /* USE_FULL_LL_DRIVER */
2890
2891 /**
2892 * @}
2893 */
2894
2895 /**
2896 * @}
2897 */
2898
2899 #endif /* DMA1 || DMA2 */
2900
2901 /**
2902 * @}
2903 */
2904
2905 #ifdef __cplusplus
2906 }
2907 #endif
2908
2909 #endif /* __STM32F7xx_LL_DMA_H */
2910
2911 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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