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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_dma2d.h
blob1d0a74ff0e22065fd5ac194f0a2ccbe14e3e3c0e
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of DMA2D LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_DMA2D_H
40 #define __STM32F7xx_LL_DMA2D_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (DMA2D)
54
55 /** @defgroup DMA2D_LL DMA2D
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63 #if defined(USE_FULL_LL_DRIVER)
64 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
65 * @{
66 */
67
68 /**
69 * @}
70 */
71 #endif /*USE_FULL_LL_DRIVER*/
72
73 /* Exported types ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
76 * @{
77 */
78
79 /**
80 * @brief LL DMA2D Init Structure Definition
81 */
82 typedef struct
83 {
84 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
85 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
86
87 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetMode().*/
88
89 uint32_t ColorMode; /*!< Specifies the color format of the output image.
90 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
91
92 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
93
94 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
95 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
97 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
98 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
99 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
100
101 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
102 function @ref LL_DMA2D_ConfigOutputColor(). */
103
104 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
105 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
106 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
107 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
108 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
109 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
110
111 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
112 function @ref LL_DMA2D_ConfigOutputColor(). */
113
114 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
115 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
116 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
117 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
118 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
119 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
122 function @ref LL_DMA2D_ConfigOutputColor(). */
123
124 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
125 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
126 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
127 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
128 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
129
130 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
131 function @ref LL_DMA2D_ConfigOutputColor(). */
132
133 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
134 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
135
136 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
137
138 uint32_t LineOffset; /*!< Specifies the output line offset value.
139 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
140
141 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetLineOffset(). */
142
143 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
144 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
145
146 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
147
148 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transfered.
149 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
150
151 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
152
153 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
154 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
155 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
156
157 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
158
159 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
160 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
161
162 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
163 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
164
165 } LL_DMA2D_InitTypeDef;
166
167 /**
168 * @brief LL DMA2D Layer Configuration Structure Definition
169 */
170 typedef struct
171 {
172 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
173 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
174
175 This parameter can be modified afterwards using unitary functions
176 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
177 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
178
179 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
180 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
181
182 This parameter can be modified afterwards using unitary functions
183 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
184 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
185
186 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
187 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
188
189 This parameter can be modified afterwards using unitary functions
190 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
191 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
192
193 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
194 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
195
196 This parameter can be modified afterwards using unitary functions
197 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
198 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
199
200 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
201 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
202
203 This parameter can be modified afterwards using unitary functions
204 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
205 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
206
207 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
208 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
209
210 This parameter can be modified afterwards using unitary functions
211 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
212 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
213
214 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
215 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
216
217 This parameter can be modified afterwards using unitary functions
218 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
219 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
220
221 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
222 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
223
224 This parameter can be modified afterwards using unitary functions
225 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
226 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
227
228 uint32_t Green; /*!< Specifies the foreground or background Green color value.
229 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
230
231 This parameter can be modified afterwards using unitary functions
232 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
233 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
234
235 uint32_t Red; /*!< Specifies the foreground or background Red color value.
236 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
237
238 This parameter can be modified afterwards using unitary functions
239 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
240 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
241
242 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
243 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
244
245 This parameter can be modified afterwards using unitary functions
246 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
247 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
248
249 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
250 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
251 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
252
253 This parameter can be modified afterwards using unitary functions
254 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
255 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
256
257 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
258 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
259
260 This parameter can be modified afterwards using unitary functions
261 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
262 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
263 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
264
265 } LL_DMA2D_LayerCfgTypeDef;
266
267 /**
268 * @brief LL DMA2D Output Color Structure Definition
269 */
270 typedef struct
271 {
272 uint32_t ColorMode; /*!< Specifies the color format of the output image.
273 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
274
275 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColorMode(). */
276
277 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
278 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
279 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
280 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
281 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
282 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
283
284 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
285 function @ref LL_DMA2D_ConfigOutputColor(). */
286
287 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
288 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
289 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
290 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
291 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
292 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
293
294 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
295 function @ref LL_DMA2D_ConfigOutputColor(). */
296
297 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
298 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
299 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
300 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
301 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
302 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
303
304 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
305 function @ref LL_DMA2D_ConfigOutputColor(). */
306
307 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
308 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
309 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
310 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
311 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
312
313 This parameter can be modified afterwards using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
314 function @ref LL_DMA2D_ConfigOutputColor(). */
315
316 } LL_DMA2D_ColorTypeDef;
317
318 /**
319 * @}
320 */
321 #endif /* USE_FULL_LL_DRIVER */
322
323 /* Exported constants --------------------------------------------------------*/
324 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
325 * @{
326 */
327
328 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
329 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
330 * @{
331 */
332 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
333 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
334 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
335 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
336 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
337 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
338 /**
339 * @}
340 */
341
342 /** @defgroup DMA2D_LL_EC_IT IT Defines
343 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
344 * @{
345 */
346 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
347 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
348 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
349 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
350 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
351 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
352 /**
353 * @}
354 */
355
356 /** @defgroup DMA2D_LL_EC_MODE Mode
357 * @{
358 */
359 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
360 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
361 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
362 #define LL_DMA2D_MODE_R2M DMA2D_CR_MODE /*!< DMA2D register to memory transfer mode */
363 /**
364 * @}
365 */
366
367 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
368 * @{
369 */
370 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
371 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
372 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
373 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
374 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
375 /**
376 * @}
377 */
378
379 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
380 * @{
381 */
382 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
383 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
384 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
385 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
386 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
387 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
388 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
389 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
390 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
391 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
392 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
393 /**
394 * @}
395 */
396
397 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
398 * @{
399 */
400 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
401 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by programmed alpha value */
402 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by programmed alpha value
403 with original alpha channel value */
404 /**
405 * @}
406 */
407
408 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
409 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
410 * @{
411 */
412 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
413 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
414 /**
415 * @}
416 */
417
418 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
419 * @{
420 */
421 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
422 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
423 /**
424 * @}
425 */
426
427 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
428 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
429 * @{
430 */
431 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
432 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
433 /**
434 * @}
435 */
436
437 /**
438 * @}
439 */
440
441 /* Exported macro ------------------------------------------------------------*/
442 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
443 * @{
444 */
445
446 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
447 * @{
448 */
449
450 /**
451 * @brief Write a value in DMA2D register.
452 * @param __INSTANCE__ DMA2D Instance
453 * @param __REG__ Register to be written
454 * @param __VALUE__ Value to be written in the register
455 * @retval None
456 */
457 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
458
459 /**
460 * @brief Read a value in DMA2D register.
461 * @param __INSTANCE__ DMA2D Instance
462 * @param __REG__ Register to be read
463 * @retval Register value
464 */
465 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
466 /**
467 * @}
468 */
469
470 /**
471 * @}
472 */
473
474 /* Exported functions --------------------------------------------------------*/
475 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
476 * @{
477 */
478
479 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
480 * @{
481 */
482
483 /**
484 * @brief Start a DMA2D transfer.
485 * @rmtoll CR START LL_DMA2D_Start
486 * @param DMA2Dx DMA2D Instance
487 * @retval None
488 */
489 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
490 {
491 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
492 }
493
494 /**
495 * @brief Indicate if a DMA2D transfer is ongoing.
496 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
497 * @param DMA2Dx DMA2D Instance
498 * @retval State of bit (1 or 0).
499 */
500 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(DMA2D_TypeDef *DMA2Dx)
501 {
502 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START));
503 }
504
505 /**
506 * @brief Suspend DMA2D transfer.
507 * @note This API can be used to suspend automatic foreground or background CLUT loading.
508 * @rmtoll CR SUSP LL_DMA2D_Suspend
509 * @param DMA2Dx DMA2D Instance
510 * @retval None
511 */
512 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
513 {
514 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
515 }
516
517 /**
518 * @brief Resume DMA2D transfer.
519 * @note This API can be used to resume automatic foreground or background CLUT loading.
520 * @rmtoll CR SUSP LL_DMA2D_Resume
521 * @param DMA2Dx DMA2D Instance
522 * @retval None
523 */
524 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
525 {
526 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
527 }
528
529 /**
530 * @brief Indicate if DMA2D transfer is suspended.
531 * @note This API can be used to indicate whether or not automatic foreground or
532 * background CLUT loading is suspended.
533 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
534 * @param DMA2Dx DMA2D Instance
535 * @retval State of bit (1 or 0).
536 */
537 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(DMA2D_TypeDef *DMA2Dx)
538 {
539 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP));
540 }
541
542 /**
543 * @brief Abort DMA2D transfer.
544 * @note This API can be used to abort automatic foreground or background CLUT loading.
545 * @rmtoll CR ABORT LL_DMA2D_Abort
546 * @param DMA2Dx DMA2D Instance
547 * @retval None
548 */
549 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
550 {
551 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
552 }
553
554 /**
555 * @brief Indicate if DMA2D transfer is aborted.
556 * @note This API can be used to indicate whether or not automatic foreground or
557 * background CLUT loading is aborted.
558 * @rmtoll CR ABORT LL_DMA2D_IsAborted
559 * @param DMA2Dx DMA2D Instance
560 * @retval State of bit (1 or 0).
561 */
562 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(DMA2D_TypeDef *DMA2Dx)
563 {
564 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT));
565 }
566
567 /**
568 * @brief Set DMA2D mode.
569 * @rmtoll CR MODE LL_DMA2D_SetMode
570 * @param DMA2Dx DMA2D Instance
571 * @param Mode This parameter can be one of the following values:
572 * @arg @ref LL_DMA2D_MODE_M2M
573 * @arg @ref LL_DMA2D_MODE_M2M_PFC
574 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
575 * @arg @ref LL_DMA2D_MODE_R2M
576 * @retval None
577 */
578 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
579 {
580 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
581 }
582
583 /**
584 * @brief Return DMA2D mode
585 * @rmtoll CR MODE LL_DMA2D_GetMode
586 * @param DMA2Dx DMA2D Instance
587 * @retval Returned value can be one of the following values:
588 * @arg @ref LL_DMA2D_MODE_M2M
589 * @arg @ref LL_DMA2D_MODE_M2M_PFC
590 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
591 * @arg @ref LL_DMA2D_MODE_R2M
592 */
593 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(DMA2D_TypeDef *DMA2Dx)
594 {
595 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
596 }
597
598 /**
599 * @brief Set DMA2D output color mode.
600 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
601 * @param DMA2Dx DMA2D Instance
602 * @param ColorMode This parameter can be one of the following values:
603 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
604 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
605 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
606 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
607 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
608 * @retval None
609 */
610 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
611 {
612 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
613 }
614
615 /**
616 * @brief Return DMA2D output color mode.
617 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
618 * @param DMA2Dx DMA2D Instance
619 * @retval Returned value can be one of the following values:
620 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
621 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
622 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
623 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
624 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
625 */
626 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(DMA2D_TypeDef *DMA2Dx)
627 {
628 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
629 }
630
631 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
632 /**
633 * @brief Set DMA2D output Red Blue swap mode.
634 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
635 * @param DMA2Dx DMA2D Instance
636 * @param RBSwapMode This parameter can be one of the following values:
637 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
638 * @arg @ref LL_DMA2D_RB_MODE_SWAP
639 * @retval None
640 */
641 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
642 {
643 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
644 }
645
646 /**
647 * @brief Return DMA2D output Red Blue swap mode.
648 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
649 * @param DMA2Dx DMA2D Instance
650 * @retval Returned value can be one of the following values:
651 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
652 * @arg @ref LL_DMA2D_RB_MODE_SWAP
653 */
654 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx)
655 {
656 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
657 }
658
659 /**
660 * @brief Set DMA2D output alpha inversion mode.
661 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
662 * @param DMA2Dx DMA2D Instance
663 * @param AlphaInversionMode This parameter can be one of the following values:
664 * @arg @ref LL_DMA2D_ALPHA_REGULAR
665 * @arg @ref LL_DMA2D_ALPHA_INVERTED
666 * @retval None
667 */
668 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
669 {
670 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
671 }
672
673 /**
674 * @brief Return DMA2D output alpha inversion mode.
675 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
676 * @param DMA2Dx DMA2D Instance
677 * @retval Returned value can be one of the following values:
678 * @arg @ref LL_DMA2D_ALPHA_REGULAR
679 * @arg @ref LL_DMA2D_ALPHA_INVERTED
680 */
681 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
682 {
683 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
684 }
685
686 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
687
688 /**
689 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
690 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
691 * @param DMA2Dx DMA2D Instance
692 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FFF
693 * @retval None
694 */
695 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
696 {
697 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
698 }
699
700 /**
701 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
702 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
703 * @param DMA2Dx DMA2D Instance
704 * @retval Line offset value between Min_Data=0 and Max_Data=0x3FFF
705 */
706 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
707 {
708 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
709 }
710
711 /**
712 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
713 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
714 * @param DMA2Dx DMA2D Instance
715 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
716 * @retval None
717 */
718 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
719 {
720 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
721 }
722
723 /**
724 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
725 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
726 * @param DMA2Dx DMA2D Instance
727 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
728 */
729 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx)
730 {
731 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
732 }
733
734 /**
735 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
736 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
737 * @param DMA2Dx DMA2D Instance
738 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
739 * @retval None
740 */
741 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
742 {
743 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
744 }
745
746 /**
747 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
748 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
749 * @param DMA2Dx DMA2D Instance
750 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
751 */
752 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(DMA2D_TypeDef *DMA2Dx)
753 {
754 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
755 }
756
757 /**
758 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
759 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
760 * @param DMA2Dx DMA2D Instance
761 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
762 * @retval None
763 */
764 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
765 {
766 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
767 }
768
769 /**
770 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
771 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
772 * @param DMA2Dx DMA2D Instance
773 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
774 */
775 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(DMA2D_TypeDef *DMA2Dx)
776 {
777 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
778 }
779
780 /**
781 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
782 * @note Output color format depends on output color mode, ARGB8888, RGB888,
783 * RGB565, ARGB1555 or ARGB4444.
784 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
785 * with respect to color mode is not done by the user code.
786 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
787 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
788 * OCOLR RED LL_DMA2D_SetOutputColor\n
789 * OCOLR ALPHA LL_DMA2D_SetOutputColor
790 * @param DMA2Dx DMA2D Instance
791 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
792 * @retval None
793 */
794 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
795 {
796 MODIFY_REG(DMA2Dx->OCOLR, (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1), \
797 OutputColor);
798 }
799
800 /**
801 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
802 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
803 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
804 * as set by @ref LL_DMA2D_SetOutputColorMode.
805 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
806 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
807 * OCOLR RED LL_DMA2D_GetOutputColor\n
808 * OCOLR ALPHA LL_DMA2D_GetOutputColor
809 * @param DMA2Dx DMA2D Instance
810 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
811 */
812 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(DMA2D_TypeDef *DMA2Dx)
813 {
814 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
815 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
816 }
817
818 /**
819 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
820 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
821 * @param DMA2Dx DMA2D Instance
822 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
823 * @retval None
824 */
825 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
826 {
827 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
828 }
829
830 /**
831 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
832 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
833 * @param DMA2Dx DMA2D Instance
834 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
835 */
836 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(DMA2D_TypeDef *DMA2Dx)
837 {
838 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
839 }
840
841 /**
842 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
843 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
844 * @param DMA2Dx DMA2D Instance
845 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
846 * @retval None
847 */
848 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
849 {
850 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
851 }
852
853 /**
854 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
855 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
856 * @param DMA2Dx DMA2D Instance
857 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
858 */
859 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(DMA2D_TypeDef *DMA2Dx)
860 {
861 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
862 }
863
864 /**
865 * @brief Enable DMA2D dead time functionality.
866 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
867 * @param DMA2Dx DMA2D Instance
868 * @retval None
869 */
870 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
871 {
872 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
873 }
874
875 /**
876 * @brief Disable DMA2D dead time functionality.
877 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
878 * @param DMA2Dx DMA2D Instance
879 * @retval None
880 */
881 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
882 {
883 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
884 }
885
886 /**
887 * @brief Indicate if DMA2D dead time functionality is enabled.
888 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
889 * @param DMA2Dx DMA2D Instance
890 * @retval State of bit (1 or 0).
891 */
892 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(DMA2D_TypeDef *DMA2Dx)
893 {
894 return (READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN));
895 }
896
897 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
898 * @{
899 */
900
901 /**
902 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
903 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
904 * @param DMA2Dx DMA2D Instance
905 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
906 * @retval None
907 */
908 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
909 {
910 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
911 }
912
913 /**
914 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
915 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
916 * @param DMA2Dx DMA2D Instance
917 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
918 */
919 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
920 {
921 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
922 }
923
924 /**
925 * @brief Enable DMA2D foreground CLUT loading.
926 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
927 * @param DMA2Dx DMA2D Instance
928 * @retval None
929 */
930 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
931 {
932 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
933 }
934
935 /**
936 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
937 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
938 * @param DMA2Dx DMA2D Instance
939 * @retval State of bit (1 or 0).
940 */
941 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
942 {
943 return (READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START));
944 }
945
946 /**
947 * @brief Set DMA2D foreground color mode.
948 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
949 * @param DMA2Dx DMA2D Instance
950 * @param ColorMode This parameter can be one of the following values:
951 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
952 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
953 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
954 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
955 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
956 * @arg @ref LL_DMA2D_INPUT_MODE_L8
957 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
958 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
959 * @arg @ref LL_DMA2D_INPUT_MODE_L4
960 * @arg @ref LL_DMA2D_INPUT_MODE_A8
961 * @arg @ref LL_DMA2D_INPUT_MODE_A4
962 * @retval None
963 */
964 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
965 {
966 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
967 }
968
969 /**
970 * @brief Return DMA2D foreground color mode.
971 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
972 * @param DMA2Dx DMA2D Instance
973 * @retval Returned value can be one of the following values:
974 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
975 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
976 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
977 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
978 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
979 * @arg @ref LL_DMA2D_INPUT_MODE_L8
980 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
981 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
982 * @arg @ref LL_DMA2D_INPUT_MODE_L4
983 * @arg @ref LL_DMA2D_INPUT_MODE_A8
984 * @arg @ref LL_DMA2D_INPUT_MODE_A4
985 */
986 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
987 {
988 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
989 }
990
991 /**
992 * @brief Set DMA2D foreground alpha mode.
993 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
994 * @param DMA2Dx DMA2D Instance
995 * @param AphaMode This parameter can be one of the following values:
996 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
997 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
998 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
999 * @retval None
1000 */
1001 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1002 {
1003 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1004 }
1005
1006 /**
1007 * @brief Return DMA2D foreground alpha mode.
1008 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1009 * @param DMA2Dx DMA2D Instance
1010 * @retval Returned value can be one of the following values:
1011 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1012 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1013 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1014 */
1015 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1016 {
1017 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1018 }
1019
1020 /**
1021 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1022 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1023 * @param DMA2Dx DMA2D Instance
1024 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1025 * @retval None
1026 */
1027 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1028 {
1029 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1030 }
1031
1032 /**
1033 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1034 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1035 * @param DMA2Dx DMA2D Instance
1036 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1037 */
1038 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1039 {
1040 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1041 }
1042
1043 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1044 /**
1045 * @brief Set DMA2D foreground Red Blue swap mode.
1046 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1047 * @param DMA2Dx DMA2D Instance
1048 * @param RBSwapMode This parameter can be one of the following values:
1049 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1050 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1051 * @retval None
1052 */
1053 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1054 {
1055 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1056 }
1057
1058 /**
1059 * @brief Return DMA2D foreground Red Blue swap mode.
1060 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1061 * @param DMA2Dx DMA2D Instance
1062 * @retval Returned value can be one of the following values:
1063 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1064 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1065 */
1066 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1067 {
1068 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1069 }
1070
1071 /**
1072 * @brief Set DMA2D foreground alpha inversion mode.
1073 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1074 * @param DMA2Dx DMA2D Instance
1075 * @param AlphaInversionMode This parameter can be one of the following values:
1076 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1077 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1078 * @retval None
1079 */
1080 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1081 {
1082 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1083 }
1084
1085 /**
1086 * @brief Return DMA2D foreground alpha inversion mode.
1087 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1088 * @param DMA2Dx DMA2D Instance
1089 * @retval Returned value can be one of the following values:
1090 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1091 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1092 */
1093 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1094 {
1095 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1096 }
1097
1098 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1099
1100 /**
1101 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1102 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1103 * @param DMA2Dx DMA2D Instance
1104 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1105 * @retval None
1106 */
1107 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1108 {
1109 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1110 }
1111
1112 /**
1113 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1114 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1115 * @param DMA2Dx DMA2D Instance
1116 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1117 */
1118 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1119 {
1120 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1121 }
1122
1123 /**
1124 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1125 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1126 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1127 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1128 * @param DMA2Dx DMA2D Instance
1129 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1130 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1131 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1132 * @retval None
1133 */
1134 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1135 {
1136 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1137 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1138 }
1139
1140 /**
1141 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1142 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1143 * @param DMA2Dx DMA2D Instance
1144 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1145 * @retval None
1146 */
1147 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1148 {
1149 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1150 }
1151
1152 /**
1153 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1154 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1155 * @param DMA2Dx DMA2D Instance
1156 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1157 */
1158 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1159 {
1160 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1161 }
1162
1163 /**
1164 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1165 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1166 * @param DMA2Dx DMA2D Instance
1167 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1168 * @retval None
1169 */
1170 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1171 {
1172 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1173 }
1174
1175 /**
1176 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1177 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1178 * @param DMA2Dx DMA2D Instance
1179 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1180 */
1181 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1182 {
1183 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1184 }
1185
1186 /**
1187 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1188 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1189 * @param DMA2Dx DMA2D Instance
1190 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1191 * @retval None
1192 */
1193 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1194 {
1195 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1196 }
1197
1198 /**
1199 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1200 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1201 * @param DMA2Dx DMA2D Instance
1202 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1203 */
1204 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1205 {
1206 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1207 }
1208
1209 /**
1210 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1211 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1212 * @param DMA2Dx DMA2D Instance
1213 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1214 * @retval None
1215 */
1216 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1217 {
1218 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1219 }
1220
1221 /**
1222 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1223 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1224 * @param DMA2Dx DMA2D Instance
1225 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1226 */
1227 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1228 {
1229 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1230 }
1231
1232 /**
1233 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1234 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1235 * @param DMA2Dx DMA2D Instance
1236 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1237 * @retval None
1238 */
1239 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1240 {
1241 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1242 }
1243
1244 /**
1245 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1246 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1247 * @param DMA2Dx DMA2D Instance
1248 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1249 */
1250 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1251 {
1252 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1253 }
1254
1255 /**
1256 * @brief Set DMA2D foreground CLUT color mode.
1257 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1258 * @param DMA2Dx DMA2D Instance
1259 * @param CLUTColorMode This parameter can be one of the following values:
1260 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1261 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1262 * @retval None
1263 */
1264 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1265 {
1266 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1267 }
1268
1269 /**
1270 * @brief Return DMA2D foreground CLUT color mode.
1271 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1272 * @param DMA2Dx DMA2D Instance
1273 * @retval Returned value can be one of the following values:
1274 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1275 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1276 */
1277 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1278 {
1279 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1280 }
1281
1282 /**
1283 * @}
1284 */
1285
1286 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1287 * @{
1288 */
1289
1290 /**
1291 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1292 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1293 * @param DMA2Dx DMA2D Instance
1294 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1295 * @retval None
1296 */
1297 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1298 {
1299 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1300 }
1301
1302 /**
1303 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1304 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1305 * @param DMA2Dx DMA2D Instance
1306 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1307 */
1308 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(DMA2D_TypeDef *DMA2Dx)
1309 {
1310 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1311 }
1312
1313 /**
1314 * @brief Enable DMA2D background CLUT loading.
1315 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1316 * @param DMA2Dx DMA2D Instance
1317 * @retval None
1318 */
1319 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1320 {
1321 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1322 }
1323
1324 /**
1325 * @brief Indicate if DMA2D background CLUT loading is enabled.
1326 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1327 * @param DMA2Dx DMA2D Instance
1328 * @retval State of bit (1 or 0).
1329 */
1330 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1331 {
1332 return (READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START));
1333 }
1334
1335 /**
1336 * @brief Set DMA2D background color mode.
1337 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1338 * @param DMA2Dx DMA2D Instance
1339 * @param ColorMode This parameter can be one of the following values:
1340 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1341 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1342 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1343 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1344 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1345 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1346 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1347 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1348 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1349 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1350 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1351 * @retval None
1352 */
1353 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1354 {
1355 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1356 }
1357
1358 /**
1359 * @brief Return DMA2D background color mode.
1360 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1361 * @param DMA2Dx DMA2D Instance
1362 * @retval Returned value can be one of the following values:
1363 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1364 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1365 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1366 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1367 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1368 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1369 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1370 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1371 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1372 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1373 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1374 */
1375 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(DMA2D_TypeDef *DMA2Dx)
1376 {
1377 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1378 }
1379
1380 /**
1381 * @brief Set DMA2D background alpha mode.
1382 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1383 * @param DMA2Dx DMA2D Instance
1384 * @param AphaMode This parameter can be one of the following values:
1385 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1386 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1387 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1388 * @retval None
1389 */
1390 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1391 {
1392 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1393 }
1394
1395 /**
1396 * @brief Return DMA2D background alpha mode.
1397 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1398 * @param DMA2Dx DMA2D Instance
1399 * @retval Returned value can be one of the following values:
1400 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1401 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1402 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1403 */
1404 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(DMA2D_TypeDef *DMA2Dx)
1405 {
1406 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1407 }
1408
1409 /**
1410 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1411 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1412 * @param DMA2Dx DMA2D Instance
1413 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1414 * @retval None
1415 */
1416 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1417 {
1418 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1419 }
1420
1421 /**
1422 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1423 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1424 * @param DMA2Dx DMA2D Instance
1425 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1426 */
1427 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(DMA2D_TypeDef *DMA2Dx)
1428 {
1429 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1430 }
1431
1432 #if defined(DMA2D_ALPHA_INV_RB_SWAP_SUPPORT)
1433 /**
1434 * @brief Set DMA2D background Red Blue swap mode.
1435 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1436 * @param DMA2Dx DMA2D Instance
1437 * @param RBSwapMode This parameter can be one of the following values:
1438 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1439 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1440 * @retval None
1441 */
1442 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1443 {
1444 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1445 }
1446
1447 /**
1448 * @brief Return DMA2D background Red Blue swap mode.
1449 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1450 * @param DMA2Dx DMA2D Instance
1451 * @retval Returned value can be one of the following values:
1452 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1453 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1454 */
1455 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(DMA2D_TypeDef *DMA2Dx)
1456 {
1457 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1458 }
1459
1460 /**
1461 * @brief Set DMA2D background alpha inversion mode.
1462 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1463 * @param DMA2Dx DMA2D Instance
1464 * @param AlphaInversionMode This parameter can be one of the following values:
1465 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1466 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1467 * @retval None
1468 */
1469 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1470 {
1471 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1472 }
1473
1474 /**
1475 * @brief Return DMA2D background alpha inversion mode.
1476 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1477 * @param DMA2Dx DMA2D Instance
1478 * @retval Returned value can be one of the following values:
1479 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1480 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1481 */
1482 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(DMA2D_TypeDef *DMA2Dx)
1483 {
1484 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1485 }
1486
1487 #endif /* DMA2D_ALPHA_INV_RB_SWAP_SUPPORT */
1488
1489 /**
1490 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1491 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1492 * @param DMA2Dx DMA2D Instance
1493 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1494 * @retval None
1495 */
1496 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1497 {
1498 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1499 }
1500
1501 /**
1502 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1503 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1504 * @param DMA2Dx DMA2D Instance
1505 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1506 */
1507 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(DMA2D_TypeDef *DMA2Dx)
1508 {
1509 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1510 }
1511
1512 /**
1513 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1514 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1515 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1516 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1517 * @param DMA2Dx DMA2D Instance
1518 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1519 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1520 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1521 * @retval None
1522 */
1523 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1524 {
1525 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1526 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1527 }
1528
1529 /**
1530 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1531 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1532 * @param DMA2Dx DMA2D Instance
1533 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1534 * @retval None
1535 */
1536 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1537 {
1538 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1539 }
1540
1541 /**
1542 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1543 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1544 * @param DMA2Dx DMA2D Instance
1545 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1546 */
1547 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(DMA2D_TypeDef *DMA2Dx)
1548 {
1549 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1550 }
1551
1552 /**
1553 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1554 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1555 * @param DMA2Dx DMA2D Instance
1556 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1557 * @retval None
1558 */
1559 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1560 {
1561 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1562 }
1563
1564 /**
1565 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1566 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1567 * @param DMA2Dx DMA2D Instance
1568 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1569 */
1570 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(DMA2D_TypeDef *DMA2Dx)
1571 {
1572 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1573 }
1574
1575 /**
1576 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1577 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1578 * @param DMA2Dx DMA2D Instance
1579 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1580 * @retval None
1581 */
1582 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1583 {
1584 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1585 }
1586
1587 /**
1588 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1589 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1590 * @param DMA2Dx DMA2D Instance
1591 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1592 */
1593 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(DMA2D_TypeDef *DMA2Dx)
1594 {
1595 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1596 }
1597
1598 /**
1599 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1600 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1601 * @param DMA2Dx DMA2D Instance
1602 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1603 * @retval None
1604 */
1605 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1606 {
1607 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1608 }
1609
1610 /**
1611 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1612 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1613 * @param DMA2Dx DMA2D Instance
1614 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1615 */
1616 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx)
1617 {
1618 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1619 }
1620
1621 /**
1622 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1623 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1624 * @param DMA2Dx DMA2D Instance
1625 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1626 * @retval None
1627 */
1628 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1629 {
1630 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1631 }
1632
1633 /**
1634 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1635 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1636 * @param DMA2Dx DMA2D Instance
1637 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1638 */
1639 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(DMA2D_TypeDef *DMA2Dx)
1640 {
1641 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1642 }
1643
1644 /**
1645 * @brief Set DMA2D background CLUT color mode.
1646 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1647 * @param DMA2Dx DMA2D Instance
1648 * @param CLUTColorMode This parameter can be one of the following values:
1649 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1650 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1654 {
1655 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1656 }
1657
1658 /**
1659 * @brief Return DMA2D background CLUT color mode.
1660 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1661 * @param DMA2Dx DMA2D Instance
1662 * @retval Returned value can be one of the following values:
1663 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1664 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1665 */
1666 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(DMA2D_TypeDef *DMA2Dx)
1667 {
1668 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1669 }
1670
1671 /**
1672 * @}
1673 */
1674
1675 /**
1676 * @}
1677 */
1678
1679
1680 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1681 * @{
1682 */
1683
1684 /**
1685 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1686 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1687 * @param DMA2Dx DMA2D Instance
1688 * @retval State of bit (1 or 0).
1689 */
1690 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(DMA2D_TypeDef *DMA2Dx)
1691 {
1692 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF));
1693 }
1694
1695 /**
1696 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1697 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1698 * @param DMA2Dx DMA2D Instance
1699 * @retval State of bit (1 or 0).
1700 */
1701 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1702 {
1703 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF));
1704 }
1705
1706 /**
1707 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1708 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1709 * @param DMA2Dx DMA2D Instance
1710 * @retval State of bit (1 or 0).
1711 */
1712 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1713 {
1714 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF));
1715 }
1716
1717 /**
1718 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1719 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1720 * @param DMA2Dx DMA2D Instance
1721 * @retval State of bit (1 or 0).
1722 */
1723 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(DMA2D_TypeDef *DMA2Dx)
1724 {
1725 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF));
1726 }
1727
1728 /**
1729 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1730 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1731 * @param DMA2Dx DMA2D Instance
1732 * @retval State of bit (1 or 0).
1733 */
1734 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(DMA2D_TypeDef *DMA2Dx)
1735 {
1736 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF));
1737 }
1738
1739 /**
1740 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1741 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1742 * @param DMA2Dx DMA2D Instance
1743 * @retval State of bit (1 or 0).
1744 */
1745 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(DMA2D_TypeDef *DMA2Dx)
1746 {
1747 return (READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF));
1748 }
1749
1750 /**
1751 * @brief Clear DMA2D Configuration Error Interrupt Flag
1752 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1753 * @param DMA2Dx DMA2D Instance
1754 * @retval None
1755 */
1756 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1757 {
1758 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1759 }
1760
1761 /**
1762 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1763 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1764 * @param DMA2Dx DMA2D Instance
1765 * @retval None
1766 */
1767 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1768 {
1769 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1770 }
1771
1772 /**
1773 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1774 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1775 * @param DMA2Dx DMA2D Instance
1776 * @retval None
1777 */
1778 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1779 {
1780 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1781 }
1782
1783 /**
1784 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1785 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1786 * @param DMA2Dx DMA2D Instance
1787 * @retval None
1788 */
1789 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1790 {
1791 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1792 }
1793
1794 /**
1795 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1796 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1797 * @param DMA2Dx DMA2D Instance
1798 * @retval None
1799 */
1800 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1801 {
1802 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1803 }
1804
1805 /**
1806 * @brief Clear DMA2D Transfer Error Interrupt Flag
1807 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1808 * @param DMA2Dx DMA2D Instance
1809 * @retval None
1810 */
1811 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1812 {
1813 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1814 }
1815
1816 /**
1817 * @}
1818 */
1819
1820 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1821 * @{
1822 */
1823
1824 /**
1825 * @brief Enable Configuration Error Interrupt
1826 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1827 * @param DMA2Dx DMA2D Instance
1828 * @retval None
1829 */
1830 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1831 {
1832 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1833 }
1834
1835 /**
1836 * @brief Enable CLUT Transfer Complete Interrupt
1837 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
1838 * @param DMA2Dx DMA2D Instance
1839 * @retval None
1840 */
1841 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1842 {
1843 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1844 }
1845
1846 /**
1847 * @brief Enable CLUT Access Error Interrupt
1848 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
1849 * @param DMA2Dx DMA2D Instance
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1853 {
1854 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1855 }
1856
1857 /**
1858 * @brief Enable Transfer Watermark Interrupt
1859 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
1860 * @param DMA2Dx DMA2D Instance
1861 * @retval None
1862 */
1863 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
1864 {
1865 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1866 }
1867
1868 /**
1869 * @brief Enable Transfer Complete Interrupt
1870 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
1871 * @param DMA2Dx DMA2D Instance
1872 * @retval None
1873 */
1874 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
1875 {
1876 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1877 }
1878
1879 /**
1880 * @brief Enable Transfer Error Interrupt
1881 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
1882 * @param DMA2Dx DMA2D Instance
1883 * @retval None
1884 */
1885 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
1886 {
1887 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1888 }
1889
1890 /**
1891 * @brief Disable Configuration Error Interrupt
1892 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
1893 * @param DMA2Dx DMA2D Instance
1894 * @retval None
1895 */
1896 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
1897 {
1898 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1899 }
1900
1901 /**
1902 * @brief Disable CLUT Transfer Complete Interrupt
1903 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
1904 * @param DMA2Dx DMA2D Instance
1905 * @retval None
1906 */
1907 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
1908 {
1909 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
1910 }
1911
1912 /**
1913 * @brief Disable CLUT Access Error Interrupt
1914 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
1915 * @param DMA2Dx DMA2D Instance
1916 * @retval None
1917 */
1918 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
1919 {
1920 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
1921 }
1922
1923 /**
1924 * @brief Disable Transfer Watermark Interrupt
1925 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
1926 * @param DMA2Dx DMA2D Instance
1927 * @retval None
1928 */
1929 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
1930 {
1931 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
1932 }
1933
1934 /**
1935 * @brief Disable Transfer Complete Interrupt
1936 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
1937 * @param DMA2Dx DMA2D Instance
1938 * @retval None
1939 */
1940 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
1941 {
1942 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
1943 }
1944
1945 /**
1946 * @brief Disable Transfer Error Interrupt
1947 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
1948 * @param DMA2Dx DMA2D Instance
1949 * @retval None
1950 */
1951 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
1952 {
1953 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
1954 }
1955
1956 /**
1957 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
1958 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
1959 * @param DMA2Dx DMA2D Instance
1960 * @retval State of bit (1 or 0).
1961 */
1962 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(DMA2D_TypeDef *DMA2Dx)
1963 {
1964 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE));
1965 }
1966
1967 /**
1968 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
1969 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
1970 * @param DMA2Dx DMA2D Instance
1971 * @retval State of bit (1 or 0).
1972 */
1973 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(DMA2D_TypeDef *DMA2Dx)
1974 {
1975 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE));
1976 }
1977
1978 /**
1979 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
1980 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
1981 * @param DMA2Dx DMA2D Instance
1982 * @retval State of bit (1 or 0).
1983 */
1984 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(DMA2D_TypeDef *DMA2Dx)
1985 {
1986 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE));
1987 }
1988
1989 /**
1990 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
1991 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
1992 * @param DMA2Dx DMA2D Instance
1993 * @retval State of bit (1 or 0).
1994 */
1995 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(DMA2D_TypeDef *DMA2Dx)
1996 {
1997 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE));
1998 }
1999
2000 /**
2001 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2002 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2003 * @param DMA2Dx DMA2D Instance
2004 * @retval State of bit (1 or 0).
2005 */
2006 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(DMA2D_TypeDef *DMA2Dx)
2007 {
2008 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE));
2009 }
2010
2011 /**
2012 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2013 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2014 * @param DMA2Dx DMA2D Instance
2015 * @retval State of bit (1 or 0).
2016 */
2017 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(DMA2D_TypeDef *DMA2Dx)
2018 {
2019 return (READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE));
2020 }
2021
2022
2023
2024 /**
2025 * @}
2026 */
2027
2028 #if defined(USE_FULL_LL_DRIVER)
2029 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2030 * @{
2031 */
2032
2033 ErrorStatus LL_DMA2D_DeInit(DMA2D_TypeDef *DMA2Dx);
2034 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2035 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2036 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2037 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2038 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2039 uint32_t LL_DMA2D_GetOutputBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2040 uint32_t LL_DMA2D_GetOutputGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2041 uint32_t LL_DMA2D_GetOutputRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2042 uint32_t LL_DMA2D_GetOutputAlphaColor(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2043 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2044
2045 /**
2046 * @}
2047 */
2048 #endif /* USE_FULL_LL_DRIVER */
2049
2050 /**
2051 * @}
2052 */
2053
2054 /**
2055 * @}
2056 */
2057
2058 #endif /* defined (DMA2D) */
2059
2060 /**
2061 * @}
2062 */
2063
2064 #ifdef __cplusplus
2065 }
2066 #endif
2067
2068 #endif /* __STM32F7xx_LL_DMA2D_H */
2069
2070 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software