?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_fmc.h
blobdd409acaac4626128a9222abacab914ba60c8ea2
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_fmc.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of FMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_FMC_H
40 #define __STM32F7xx_LL_FMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_HAL_Driver
50 * @{
51 */
52
53 /** @addtogroup FMC_LL
54 * @{
55 */
56
57 /** @addtogroup FMC_LL_Private_Macros
58 * @{
59 */
60 #define IS_FMC_NORSRAM_BANK(BANK) (((BANK) == FMC_NORSRAM_BANK1) || \
61 ((BANK) == FMC_NORSRAM_BANK2) || \
62 ((BANK) == FMC_NORSRAM_BANK3) || \
63 ((BANK) == FMC_NORSRAM_BANK4))
64
65 #define IS_FMC_MUX(__MUX__) (((__MUX__) == FMC_DATA_ADDRESS_MUX_DISABLE) || \
66 ((__MUX__) == FMC_DATA_ADDRESS_MUX_ENABLE))
67
68 #define IS_FMC_MEMORY(__MEMORY__) (((__MEMORY__) == FMC_MEMORY_TYPE_SRAM) || \
69 ((__MEMORY__) == FMC_MEMORY_TYPE_PSRAM)|| \
70 ((__MEMORY__) == FMC_MEMORY_TYPE_NOR))
71
72 #define IS_FMC_NORSRAM_MEMORY_WIDTH(__WIDTH__) (((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_8) || \
73 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_16) || \
74 ((__WIDTH__) == FMC_NORSRAM_MEM_BUS_WIDTH_32))
75
76 #define IS_FMC_ACCESS_MODE(__MODE__) (((__MODE__) == FMC_ACCESS_MODE_A) || \
77 ((__MODE__) == FMC_ACCESS_MODE_B) || \
78 ((__MODE__) == FMC_ACCESS_MODE_C) || \
79 ((__MODE__) == FMC_ACCESS_MODE_D))
80
81 #define IS_FMC_NAND_BANK(BANK) ((BANK) == FMC_NAND_BANK3)
82
83 #define IS_FMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FMC_NAND_WAIT_FEATURE_DISABLE) || \
84 ((FEATURE) == FMC_NAND_WAIT_FEATURE_ENABLE))
85
86 #define IS_FMC_NAND_MEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_8) || \
87 ((WIDTH) == FMC_NAND_MEM_BUS_WIDTH_16))
88
89 #define IS_FMC_ECC_STATE(STATE) (((STATE) == FMC_NAND_ECC_DISABLE) || \
90 ((STATE) == FMC_NAND_ECC_ENABLE))
91
92 #define IS_FMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FMC_NAND_ECC_PAGE_SIZE_256BYTE) || \
93 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_512BYTE) || \
94 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_1024BYTE) || \
95 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_2048BYTE) || \
96 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_4096BYTE) || \
97 ((SIZE) == FMC_NAND_ECC_PAGE_SIZE_8192BYTE))
98
99 #define IS_FMC_SDMEMORY_WIDTH(WIDTH) (((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_8) || \
100 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_16) || \
101 ((WIDTH) == FMC_SDRAM_MEM_BUS_WIDTH_32))
102
103 #define IS_FMC_WRITE_PROTECTION(__WRITE__) (((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_DISABLE) || \
104 ((__WRITE__) == FMC_SDRAM_WRITE_PROTECTION_ENABLE))
105
106 #define IS_FMC_SDCLOCK_PERIOD(__PERIOD__) (((__PERIOD__) == FMC_SDRAM_CLOCK_DISABLE) || \
107 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_2) || \
108 ((__PERIOD__) == FMC_SDRAM_CLOCK_PERIOD_3))
109
110 #define IS_FMC_READ_BURST(__RBURST__) (((__RBURST__) == FMC_SDRAM_RBURST_DISABLE) || \
111 ((__RBURST__) == FMC_SDRAM_RBURST_ENABLE))
112
113 #define IS_FMC_READPIPE_DELAY(__DELAY__) (((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_0) || \
114 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_1) || \
115 ((__DELAY__) == FMC_SDRAM_RPIPE_DELAY_2))
116
117 #define IS_FMC_COMMAND_MODE(__COMMAND__) (((__COMMAND__) == FMC_SDRAM_CMD_NORMAL_MODE) || \
118 ((__COMMAND__) == FMC_SDRAM_CMD_CLK_ENABLE) || \
119 ((__COMMAND__) == FMC_SDRAM_CMD_PALL) || \
120 ((__COMMAND__) == FMC_SDRAM_CMD_AUTOREFRESH_MODE) || \
121 ((__COMMAND__) == FMC_SDRAM_CMD_LOAD_MODE) || \
122 ((__COMMAND__) == FMC_SDRAM_CMD_SELFREFRESH_MODE) || \
123 ((__COMMAND__) == FMC_SDRAM_CMD_POWERDOWN_MODE))
124
125 #define IS_FMC_COMMAND_TARGET(__TARGET__) (((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1) || \
126 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK2) || \
127 ((__TARGET__) == FMC_SDRAM_CMD_TARGET_BANK1_2))
128
129 /** @defgroup FMC_TCLR_Setup_Time FMC TCLR Setup Time
130 * @{
131 */
132 #define IS_FMC_TCLR_TIME(__TIME__) ((__TIME__) <= 255)
133 /**
134 * @}
135 */
136
137 /** @defgroup FMC_TAR_Setup_Time FMC TAR Setup Time
138 * @{
139 */
140 #define IS_FMC_TAR_TIME(TIME) ((TIME) <= 255)
141 /**
142 * @}
143 */
144
145 /** @defgroup FMC_Setup_Time FMC Setup Time
146 * @{
147 */
148 #define IS_FMC_SETUP_TIME(TIME) ((TIME) <= 254)
149 /**
150 * @}
151 */
152
153 /** @defgroup FMC_Wait_Setup_Time FMC Wait Setup Time
154 * @{
155 */
156 #define IS_FMC_WAIT_TIME(TIME) ((TIME) <= 254)
157 /**
158 * @}
159 */
160
161 /** @defgroup FMC_Hold_Setup_Time FMC Hold Setup Time
162 * @{
163 */
164 #define IS_FMC_HOLD_TIME(TIME) ((TIME) <= 254)
165 /**
166 * @}
167 */
168
169 /** @defgroup FMC_HiZ_Setup_Time FMC HiZ Setup Time
170 * @{
171 */
172 #define IS_FMC_HIZ_TIME(TIME) ((TIME) <= 254)
173 /**
174 * @}
175 */
176
177 #define IS_FMC_BURSTMODE(__STATE__) (((__STATE__) == FMC_BURST_ACCESS_MODE_DISABLE) || \
178 ((__STATE__) == FMC_BURST_ACCESS_MODE_ENABLE))
179
180 #define IS_FMC_WAIT_POLARITY(__POLARITY__) (((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_LOW) || \
181 ((__POLARITY__) == FMC_WAIT_SIGNAL_POLARITY_HIGH))
182
183 #define IS_FMC_WAIT_SIGNAL_ACTIVE(__ACTIVE__) (((__ACTIVE__) == FMC_WAIT_TIMING_BEFORE_WS) || \
184 ((__ACTIVE__) == FMC_WAIT_TIMING_DURING_WS))
185
186 #define IS_FMC_WRITE_OPERATION(__OPERATION__) (((__OPERATION__) == FMC_WRITE_OPERATION_DISABLE) || \
187 ((__OPERATION__) == FMC_WRITE_OPERATION_ENABLE))
188
189 #define IS_FMC_WAITE_SIGNAL(__SIGNAL__) (((__SIGNAL__) == FMC_WAIT_SIGNAL_DISABLE) || \
190 ((__SIGNAL__) == FMC_WAIT_SIGNAL_ENABLE))
191
192 #define IS_FMC_EXTENDED_MODE(__MODE__) (((__MODE__) == FMC_EXTENDED_MODE_DISABLE) || \
193 ((__MODE__) == FMC_EXTENDED_MODE_ENABLE))
194
195 #define IS_FMC_ASYNWAIT(__STATE__) (((__STATE__) == FMC_ASYNCHRONOUS_WAIT_DISABLE) || \
196 ((__STATE__) == FMC_ASYNCHRONOUS_WAIT_ENABLE))
197
198 /** @defgroup FMC_Data_Latency FMC Data Latency
199 * @{
200 */
201 #define IS_FMC_DATA_LATENCY(__LATENCY__) (((__LATENCY__) > 1) && ((__LATENCY__) <= 17))
202 /**
203 * @}
204 */
205
206 #define IS_FMC_WRITE_BURST(__BURST__) (((__BURST__) == FMC_WRITE_BURST_DISABLE) || \
207 ((__BURST__) == FMC_WRITE_BURST_ENABLE))
208
209 #define IS_FMC_CONTINOUS_CLOCK(CCLOCK) (((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ONLY) || \
210 ((CCLOCK) == FMC_CONTINUOUS_CLOCK_SYNC_ASYNC))
211
212
213 /** @defgroup FMC_Address_Setup_Time FMC Address Setup Time
214 * @{
215 */
216 #define IS_FMC_ADDRESS_SETUP_TIME(__TIME__) ((__TIME__) <= 15)
217 /**
218 * @}
219 */
220
221 /** @defgroup FMC_Address_Hold_Time FMC Address Hold Time
222 * @{
223 */
224 #define IS_FMC_ADDRESS_HOLD_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 15))
225 /**
226 * @}
227 */
228
229 /** @defgroup FMC_Data_Setup_Time FMC Data Setup Time
230 * @{
231 */
232 #define IS_FMC_DATASETUP_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 255))
233 /**
234 * @}
235 */
236
237 /** @defgroup FMC_Bus_Turn_around_Duration FMC Bus Turn around Duration
238 * @{
239 */
240 #define IS_FMC_TURNAROUND_TIME(__TIME__) ((__TIME__) <= 15)
241 /**
242 * @}
243 */
244
245 /** @defgroup FMC_CLK_Division FMC CLK Division
246 * @{
247 */
248 #define IS_FMC_CLK_DIV(DIV) (((DIV) > 1) && ((DIV) <= 16))
249 /**
250 * @}
251 */
252
253 /** @defgroup FMC_SDRAM_LoadToActive_Delay FMC SDRAM LoadToActive Delay
254 * @{
255 */
256 #define IS_FMC_LOADTOACTIVE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
257 /**
258 * @}
259 */
260
261 /** @defgroup FMC_SDRAM_ExitSelfRefresh_Delay FMC SDRAM ExitSelfRefresh Delay
262 * @{
263 */
264 #define IS_FMC_EXITSELFREFRESH_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
265 /**
266 * @}
267 */
268
269 /** @defgroup FMC_SDRAM_SelfRefresh_Time FMC SDRAM SelfRefresh Time
270 * @{
271 */
272 #define IS_FMC_SELFREFRESH_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
273 /**
274 * @}
275 */
276
277 /** @defgroup FMC_SDRAM_RowCycle_Delay FMC SDRAM RowCycle Delay
278 * @{
279 */
280 #define IS_FMC_ROWCYCLE_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
281 /**
282 * @}
283 */
284
285 /** @defgroup FMC_SDRAM_Write_Recovery_Time FMC SDRAM Write Recovery Time
286 * @{
287 */
288 #define IS_FMC_WRITE_RECOVERY_TIME(__TIME__) (((__TIME__) > 0) && ((__TIME__) <= 16))
289 /**
290 * @}
291 */
292
293 /** @defgroup FMC_SDRAM_RP_Delay FMC SDRAM RP Delay
294 * @{
295 */
296 #define IS_FMC_RP_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
297 /**
298 * @}
299 */
300
301 /** @defgroup FMC_SDRAM_RCD_Delay FMC SDRAM RCD Delay
302 * @{
303 */
304 #define IS_FMC_RCD_DELAY(__DELAY__) (((__DELAY__) > 0) && ((__DELAY__) <= 16))
305 /**
306 * @}
307 */
308
309 /** @defgroup FMC_SDRAM_AutoRefresh_Number FMC SDRAM AutoRefresh Number
310 * @{
311 */
312 #define IS_FMC_AUTOREFRESH_NUMBER(__NUMBER__) (((__NUMBER__) > 0) && ((__NUMBER__) <= 16))
313 /**
314 * @}
315 */
316
317 /** @defgroup FMC_SDRAM_ModeRegister_Definition FMC SDRAM ModeRegister Definition
318 * @{
319 */
320 #define IS_FMC_MODE_REGISTER(__CONTENT__) ((__CONTENT__) <= 8191)
321 /**
322 * @}
323 */
324
325 /** @defgroup FMC_SDRAM_Refresh_rate FMC SDRAM Refresh rate
326 * @{
327 */
328 #define IS_FMC_REFRESH_RATE(__RATE__) ((__RATE__) <= 8191)
329 /**
330 * @}
331 */
332
333 /** @defgroup FMC_NORSRAM_Device_Instance FMC NORSRAM Device Instance
334 * @{
335 */
336 #define IS_FMC_NORSRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_DEVICE)
337 /**
338 * @}
339 */
340
341 /** @defgroup FMC_NORSRAM_EXTENDED_Device_Instance FMC NORSRAM EXTENDED Device Instance
342 * @{
343 */
344 #define IS_FMC_NORSRAM_EXTENDED_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NORSRAM_EXTENDED_DEVICE)
345 /**
346 * @}
347 */
348
349 /** @defgroup FMC_NAND_Device_Instance FMC NAND Device Instance
350 * @{
351 */
352 #define IS_FMC_NAND_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_NAND_DEVICE)
353 /**
354 * @}
355 */
356
357 /** @defgroup FMC_SDRAM_Device_Instance FMC SDRAM Device Instance
358 * @{
359 */
360 #define IS_FMC_SDRAM_DEVICE(__INSTANCE__) ((__INSTANCE__) == FMC_SDRAM_DEVICE)
361 /**
362 * @}
363 */
364
365 #define IS_FMC_SDRAM_BANK(BANK) (((BANK) == FMC_SDRAM_BANK1) || \
366 ((BANK) == FMC_SDRAM_BANK2))
367
368 #define IS_FMC_COLUMNBITS_NUMBER(COLUMN) (((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_8) || \
369 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_9) || \
370 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_10) || \
371 ((COLUMN) == FMC_SDRAM_COLUMN_BITS_NUM_11))
372
373 #define IS_FMC_ROWBITS_NUMBER(ROW) (((ROW) == FMC_SDRAM_ROW_BITS_NUM_11) || \
374 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_12) || \
375 ((ROW) == FMC_SDRAM_ROW_BITS_NUM_13))
376
377 #define IS_FMC_INTERNALBANK_NUMBER(NUMBER) (((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_2) || \
378 ((NUMBER) == FMC_SDRAM_INTERN_BANKS_NUM_4))
379
380
381 #define IS_FMC_CAS_LATENCY(LATENCY) (((LATENCY) == FMC_SDRAM_CAS_LATENCY_1) || \
382 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_2) || \
383 ((LATENCY) == FMC_SDRAM_CAS_LATENCY_3))
384
385 #define IS_FMC_PAGESIZE(__SIZE__) (((__SIZE__) == FMC_PAGE_SIZE_NONE) || \
386 ((__SIZE__) == FMC_PAGE_SIZE_128) || \
387 ((__SIZE__) == FMC_PAGE_SIZE_256) || \
388 ((__SIZE__) == FMC_PAGE_SIZE_512) || \
389 ((__SIZE__) == FMC_PAGE_SIZE_1024))
390
391 #define IS_FMC_WRITE_FIFO(__FIFO__) (((__FIFO__) == FMC_WRITE_FIFO_DISABLE) || \
392 ((__FIFO__) == FMC_WRITE_FIFO_ENABLE))
393 /**
394 * @}
395 */
396
397 /* Exported typedef ----------------------------------------------------------*/
398 /** @defgroup FMC_Exported_typedef FMC Low Layer Exported Types
399 * @{
400 */
401 #define FMC_NORSRAM_TypeDef FMC_Bank1_TypeDef
402 #define FMC_NORSRAM_EXTENDED_TypeDef FMC_Bank1E_TypeDef
403 #define FMC_NAND_TypeDef FMC_Bank3_TypeDef
404 #define FMC_SDRAM_TypeDef FMC_Bank5_6_TypeDef
405
406 #define FMC_NORSRAM_DEVICE FMC_Bank1
407 #define FMC_NORSRAM_EXTENDED_DEVICE FMC_Bank1E
408 #define FMC_NAND_DEVICE FMC_Bank3
409 #define FMC_SDRAM_DEVICE FMC_Bank5_6
410
411 /**
412 * @brief FMC NORSRAM Configuration Structure definition
413 */
414 typedef struct
415 {
416 uint32_t NSBank; /*!< Specifies the NORSRAM memory device that will be used.
417 This parameter can be a value of @ref FMC_NORSRAM_Bank */
418
419 uint32_t DataAddressMux; /*!< Specifies whether the address and data values are
420 multiplexed on the data bus or not.
421 This parameter can be a value of @ref FMC_Data_Address_Bus_Multiplexing */
422
423 uint32_t MemoryType; /*!< Specifies the type of external memory attached to
424 the corresponding memory device.
425 This parameter can be a value of @ref FMC_Memory_Type */
426
427 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
428 This parameter can be a value of @ref FMC_NORSRAM_Data_Width */
429
430 uint32_t BurstAccessMode; /*!< Enables or disables the burst access mode for Flash memory,
431 valid only with synchronous burst Flash memories.
432 This parameter can be a value of @ref FMC_Burst_Access_Mode */
433
434 uint32_t WaitSignalPolarity; /*!< Specifies the wait signal polarity, valid only when accessing
435 the Flash memory in burst mode.
436 This parameter can be a value of @ref FMC_Wait_Signal_Polarity */
437
438 uint32_t WaitSignalActive; /*!< Specifies if the wait signal is asserted by the memory one
439 clock cycle before the wait state or during the wait state,
440 valid only when accessing memories in burst mode.
441 This parameter can be a value of @ref FMC_Wait_Timing */
442
443 uint32_t WriteOperation; /*!< Enables or disables the write operation in the selected device by the FMC.
444 This parameter can be a value of @ref FMC_Write_Operation */
445
446 uint32_t WaitSignal; /*!< Enables or disables the wait state insertion via wait
447 signal, valid for Flash memory access in burst mode.
448 This parameter can be a value of @ref FMC_Wait_Signal */
449
450 uint32_t ExtendedMode; /*!< Enables or disables the extended mode.
451 This parameter can be a value of @ref FMC_Extended_Mode */
452
453 uint32_t AsynchronousWait; /*!< Enables or disables wait signal during asynchronous transfers,
454 valid only with asynchronous Flash memories.
455 This parameter can be a value of @ref FMC_AsynchronousWait */
456
457 uint32_t WriteBurst; /*!< Enables or disables the write burst operation.
458 This parameter can be a value of @ref FMC_Write_Burst */
459
460 uint32_t ContinuousClock; /*!< Enables or disables the FMC clock output to external memory devices.
461 This parameter is only enabled through the FMC_BCR1 register, and don't care
462 through FMC_BCR2..4 registers.
463 This parameter can be a value of @ref FMC_Continous_Clock */
464
465 uint32_t WriteFifo; /*!< Enables or disables the write FIFO used by the FMC controller.
466 This parameter is only enabled through the FMC_BCR1 register, and don't care
467 through FMC_BCR2..4 registers.
468 This parameter can be a value of @ref FMC_Write_FIFO */
469
470 uint32_t PageSize; /*!< Specifies the memory page size.
471 This parameter can be a value of @ref FMC_Page_Size */
472
473 }FMC_NORSRAM_InitTypeDef;
474
475 /**
476 * @brief FMC NORSRAM Timing parameters structure definition
477 */
478 typedef struct
479 {
480 uint32_t AddressSetupTime; /*!< Defines the number of HCLK cycles to configure
481 the duration of the address setup time.
482 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
483 @note This parameter is not used with synchronous NOR Flash memories. */
484
485 uint32_t AddressHoldTime; /*!< Defines the number of HCLK cycles to configure
486 the duration of the address hold time.
487 This parameter can be a value between Min_Data = 1 and Max_Data = 15.
488 @note This parameter is not used with synchronous NOR Flash memories. */
489
490 uint32_t DataSetupTime; /*!< Defines the number of HCLK cycles to configure
491 the duration of the data setup time.
492 This parameter can be a value between Min_Data = 1 and Max_Data = 255.
493 @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed
494 NOR Flash memories. */
495
496 uint32_t BusTurnAroundDuration; /*!< Defines the number of HCLK cycles to configure
497 the duration of the bus turnaround.
498 This parameter can be a value between Min_Data = 0 and Max_Data = 15.
499 @note This parameter is only used for multiplexed NOR Flash memories. */
500
501 uint32_t CLKDivision; /*!< Defines the period of CLK clock output signal, expressed in number of
502 HCLK cycles. This parameter can be a value between Min_Data = 2 and Max_Data = 16.
503 @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM
504 accesses. */
505
506 uint32_t DataLatency; /*!< Defines the number of memory clock cycles to issue
507 to the memory before getting the first data.
508 The parameter value depends on the memory type as shown below:
509 - It must be set to 0 in case of a CRAM
510 - It is don't care in asynchronous NOR, SRAM or ROM accesses
511 - It may assume a value between Min_Data = 2 and Max_Data = 17 in NOR Flash memories
512 with synchronous burst mode enable */
513
514 uint32_t AccessMode; /*!< Specifies the asynchronous access mode.
515 This parameter can be a value of @ref FMC_Access_Mode */
516 }FMC_NORSRAM_TimingTypeDef;
517
518 /**
519 * @brief FMC NAND Configuration Structure definition
520 */
521 typedef struct
522 {
523 uint32_t NandBank; /*!< Specifies the NAND memory device that will be used.
524 This parameter can be a value of @ref FMC_NAND_Bank */
525
526 uint32_t Waitfeature; /*!< Enables or disables the Wait feature for the NAND Memory device.
527 This parameter can be any value of @ref FMC_Wait_feature */
528
529 uint32_t MemoryDataWidth; /*!< Specifies the external memory device width.
530 This parameter can be any value of @ref FMC_NAND_Data_Width */
531
532 uint32_t EccComputation; /*!< Enables or disables the ECC computation.
533 This parameter can be any value of @ref FMC_ECC */
534
535 uint32_t ECCPageSize; /*!< Defines the page size for the extended ECC.
536 This parameter can be any value of @ref FMC_ECC_Page_Size */
537
538 uint32_t TCLRSetupTime; /*!< Defines the number of HCLK cycles to configure the
539 delay between CLE low and RE low.
540 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
541
542 uint32_t TARSetupTime; /*!< Defines the number of HCLK cycles to configure the
543 delay between ALE low and RE low.
544 This parameter can be a number between Min_Data = 0 and Max_Data = 255 */
545 }FMC_NAND_InitTypeDef;
546
547 /**
548 * @brief FMC NAND Timing parameters structure definition
549 */
550 typedef struct
551 {
552 uint32_t SetupTime; /*!< Defines the number of HCLK cycles to setup address before
553 the command assertion for NAND-Flash read or write access
554 to common/Attribute or I/O memory space (depending on
555 the memory space timing to be configured).
556 This parameter can be a value between Min_Data = 0 and Max_Data = 254 */
557
558 uint32_t WaitSetupTime; /*!< Defines the minimum number of HCLK cycles to assert the
559 command for NAND-Flash read or write access to
560 common/Attribute or I/O memory space (depending on the
561 memory space timing to be configured).
562 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
563
564 uint32_t HoldSetupTime; /*!< Defines the number of HCLK clock cycles to hold address
565 (and data for write access) after the command de-assertion
566 for NAND-Flash read or write access to common/Attribute
567 or I/O memory space (depending on the memory space timing
568 to be configured).
569 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
570
571 uint32_t HiZSetupTime; /*!< Defines the number of HCLK clock cycles during which the
572 data bus is kept in HiZ after the start of a NAND-Flash
573 write access to common/Attribute or I/O memory space (depending
574 on the memory space timing to be configured).
575 This parameter can be a number between Min_Data = 0 and Max_Data = 254 */
576 }FMC_NAND_PCC_TimingTypeDef;
577
578 /**
579 * @brief FMC SDRAM Configuration Structure definition
580 */
581 typedef struct
582 {
583 uint32_t SDBank; /*!< Specifies the SDRAM memory device that will be used.
584 This parameter can be a value of @ref FMC_SDRAM_Bank */
585
586 uint32_t ColumnBitsNumber; /*!< Defines the number of bits of column address.
587 This parameter can be a value of @ref FMC_SDRAM_Column_Bits_number. */
588
589 uint32_t RowBitsNumber; /*!< Defines the number of bits of column address.
590 This parameter can be a value of @ref FMC_SDRAM_Row_Bits_number. */
591
592 uint32_t MemoryDataWidth; /*!< Defines the memory device width.
593 This parameter can be a value of @ref FMC_SDRAM_Memory_Bus_Width. */
594
595 uint32_t InternalBankNumber; /*!< Defines the number of the device's internal banks.
596 This parameter can be of @ref FMC_SDRAM_Internal_Banks_Number. */
597
598 uint32_t CASLatency; /*!< Defines the SDRAM CAS latency in number of memory clock cycles.
599 This parameter can be a value of @ref FMC_SDRAM_CAS_Latency. */
600
601 uint32_t WriteProtection; /*!< Enables the SDRAM device to be accessed in write mode.
602 This parameter can be a value of @ref FMC_SDRAM_Write_Protection. */
603
604 uint32_t SDClockPeriod; /*!< Define the SDRAM Clock Period for both SDRAM devices and they allow
605 to disable the clock before changing frequency.
606 This parameter can be a value of @ref FMC_SDRAM_Clock_Period. */
607
608 uint32_t ReadBurst; /*!< This bit enable the SDRAM controller to anticipate the next read
609 commands during the CAS latency and stores data in the Read FIFO.
610 This parameter can be a value of @ref FMC_SDRAM_Read_Burst. */
611
612 uint32_t ReadPipeDelay; /*!< Define the delay in system clock cycles on read data path.
613 This parameter can be a value of @ref FMC_SDRAM_Read_Pipe_Delay. */
614 }FMC_SDRAM_InitTypeDef;
615
616 /**
617 * @brief FMC SDRAM Timing parameters structure definition
618 */
619 typedef struct
620 {
621 uint32_t LoadToActiveDelay; /*!< Defines the delay between a Load Mode Register command and
622 an active or Refresh command in number of memory clock cycles.
623 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
624
625 uint32_t ExitSelfRefreshDelay; /*!< Defines the delay from releasing the self refresh command to
626 issuing the Activate command in number of memory clock cycles.
627 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
628
629 uint32_t SelfRefreshTime; /*!< Defines the minimum Self Refresh period in number of memory clock
630 cycles.
631 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
632
633 uint32_t RowCycleDelay; /*!< Defines the delay between the Refresh command and the Activate command
634 and the delay between two consecutive Refresh commands in number of
635 memory clock cycles.
636 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
637
638 uint32_t WriteRecoveryTime; /*!< Defines the Write recovery Time in number of memory clock cycles.
639 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
640
641 uint32_t RPDelay; /*!< Defines the delay between a Precharge Command and an other command
642 in number of memory clock cycles.
643 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
644
645 uint32_t RCDDelay; /*!< Defines the delay between the Activate Command and a Read/Write
646 command in number of memory clock cycles.
647 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
648 }FMC_SDRAM_TimingTypeDef;
649
650 /**
651 * @brief SDRAM command parameters structure definition
652 */
653 typedef struct
654 {
655 uint32_t CommandMode; /*!< Defines the command issued to the SDRAM device.
656 This parameter can be a value of @ref FMC_SDRAM_Command_Mode. */
657
658 uint32_t CommandTarget; /*!< Defines which device (1 or 2) the command will be issued to.
659 This parameter can be a value of @ref FMC_SDRAM_Command_Target. */
660
661 uint32_t AutoRefreshNumber; /*!< Defines the number of consecutive auto refresh command issued
662 in auto refresh mode.
663 This parameter can be a value between Min_Data = 1 and Max_Data = 16 */
664 uint32_t ModeRegisterDefinition; /*!< Defines the SDRAM Mode register content */
665 }FMC_SDRAM_CommandTypeDef;
666 /**
667 * @}
668 */
669
670 /* Exported constants --------------------------------------------------------*/
671 /** @addtogroup FMC_LL_Exported_Constants FMC Low Layer Exported Constants
672 * @{
673 */
674
675 /** @defgroup FMC_LL_NOR_SRAM_Controller FMC NOR/SRAM Controller
676 * @{
677 */
678
679 /** @defgroup FMC_NORSRAM_Bank FMC NOR/SRAM Bank
680 * @{
681 */
682 #define FMC_NORSRAM_BANK1 ((uint32_t)0x00000000U)
683 #define FMC_NORSRAM_BANK2 ((uint32_t)0x00000002U)
684 #define FMC_NORSRAM_BANK3 ((uint32_t)0x00000004U)
685 #define FMC_NORSRAM_BANK4 ((uint32_t)0x00000006U)
686 /**
687 * @}
688 */
689
690 /** @defgroup FMC_Data_Address_Bus_Multiplexing FMC Data Address Bus Multiplexing
691 * @{
692 */
693 #define FMC_DATA_ADDRESS_MUX_DISABLE ((uint32_t)0x00000000U)
694 #define FMC_DATA_ADDRESS_MUX_ENABLE ((uint32_t)0x00000002U)
695 /**
696 * @}
697 */
698
699 /** @defgroup FMC_Memory_Type FMC Memory Type
700 * @{
701 */
702 #define FMC_MEMORY_TYPE_SRAM ((uint32_t)0x00000000U)
703 #define FMC_MEMORY_TYPE_PSRAM ((uint32_t)0x00000004U)
704 #define FMC_MEMORY_TYPE_NOR ((uint32_t)0x00000008U)
705 /**
706 * @}
707 */
708
709 /** @defgroup FMC_NORSRAM_Data_Width FMC NORSRAM Data Width
710 * @{
711 */
712 #define FMC_NORSRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
713 #define FMC_NORSRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
714 #define FMC_NORSRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
715 /**
716 * @}
717 */
718
719 /** @defgroup FMC_NORSRAM_Flash_Access FMC NOR/SRAM Flash Access
720 * @{
721 */
722 #define FMC_NORSRAM_FLASH_ACCESS_ENABLE ((uint32_t)0x00000040U)
723 #define FMC_NORSRAM_FLASH_ACCESS_DISABLE ((uint32_t)0x00000000U)
724 /**
725 * @}
726 */
727
728 /** @defgroup FMC_Burst_Access_Mode FMC Burst Access Mode
729 * @{
730 */
731 #define FMC_BURST_ACCESS_MODE_DISABLE ((uint32_t)0x00000000U)
732 #define FMC_BURST_ACCESS_MODE_ENABLE ((uint32_t)0x00000100U)
733 /**
734 * @}
735 */
736
737 /** @defgroup FMC_Wait_Signal_Polarity FMC Wait Signal Polarity
738 * @{
739 */
740 #define FMC_WAIT_SIGNAL_POLARITY_LOW ((uint32_t)0x00000000U)
741 #define FMC_WAIT_SIGNAL_POLARITY_HIGH ((uint32_t)0x00000200U)
742 /**
743 * @}
744 */
745
746 /** @defgroup FMC_Wait_Timing FMC Wait Timing
747 * @{
748 */
749 #define FMC_WAIT_TIMING_BEFORE_WS ((uint32_t)0x00000000U)
750 #define FMC_WAIT_TIMING_DURING_WS ((uint32_t)0x00000800U)
751 /**
752 * @}
753 */
754
755 /** @defgroup FMC_Write_Operation FMC Write Operation
756 * @{
757 */
758 #define FMC_WRITE_OPERATION_DISABLE ((uint32_t)0x00000000U)
759 #define FMC_WRITE_OPERATION_ENABLE ((uint32_t)0x00001000U)
760 /**
761 * @}
762 */
763
764 /** @defgroup FMC_Wait_Signal FMC Wait Signal
765 * @{
766 */
767 #define FMC_WAIT_SIGNAL_DISABLE ((uint32_t)0x00000000U)
768 #define FMC_WAIT_SIGNAL_ENABLE ((uint32_t)0x00002000U)
769 /**
770 * @}
771 */
772
773 /** @defgroup FMC_Extended_Mode FMC Extended Mode
774 * @{
775 */
776 #define FMC_EXTENDED_MODE_DISABLE ((uint32_t)0x00000000U)
777 #define FMC_EXTENDED_MODE_ENABLE ((uint32_t)0x00004000U)
778 /**
779 * @}
780 */
781
782 /** @defgroup FMC_AsynchronousWait FMC Asynchronous Wait
783 * @{
784 */
785 #define FMC_ASYNCHRONOUS_WAIT_DISABLE ((uint32_t)0x00000000U)
786 #define FMC_ASYNCHRONOUS_WAIT_ENABLE ((uint32_t)0x00008000U)
787 /**
788 * @}
789 */
790
791 /** @defgroup FMC_Page_Size FMC Page Size
792 * @{
793 */
794 #define FMC_PAGE_SIZE_NONE ((uint32_t)0x00000000U)
795 #define FMC_PAGE_SIZE_128 ((uint32_t)FMC_BCR1_CPSIZE_0)
796 #define FMC_PAGE_SIZE_256 ((uint32_t)FMC_BCR1_CPSIZE_1)
797 #define FMC_PAGE_SIZE_512 ((uint32_t)(FMC_BCR1_CPSIZE_0 | FMC_BCR1_CPSIZE_1))
798 #define FMC_PAGE_SIZE_1024 ((uint32_t)FMC_BCR1_CPSIZE_2)
799 /**
800 * @}
801 */
802
803 /** @defgroup FMC_Write_Burst FMC Write Burst
804 * @{
805 */
806 #define FMC_WRITE_BURST_DISABLE ((uint32_t)0x00000000U)
807 #define FMC_WRITE_BURST_ENABLE ((uint32_t)0x00080000U)
808 /**
809 * @}
810 */
811
812 /** @defgroup FMC_Continous_Clock FMC Continuous Clock
813 * @{
814 */
815 #define FMC_CONTINUOUS_CLOCK_SYNC_ONLY ((uint32_t)0x00000000U)
816 #define FMC_CONTINUOUS_CLOCK_SYNC_ASYNC ((uint32_t)0x00100000U)
817 /**
818 * @}
819 */
820
821 /** @defgroup FMC_Write_FIFO FMC Write FIFO
822 * @{
823 */
824 #define FMC_WRITE_FIFO_DISABLE ((uint32_t)FMC_BCR1_WFDIS)
825 #define FMC_WRITE_FIFO_ENABLE ((uint32_t)0x00000000U)
826 /**
827 * @}
828 */
829
830 /** @defgroup FMC_Access_Mode FMC Access Mode
831 * @{
832 */
833 #define FMC_ACCESS_MODE_A ((uint32_t)0x00000000U)
834 #define FMC_ACCESS_MODE_B ((uint32_t)0x10000000U)
835 #define FMC_ACCESS_MODE_C ((uint32_t)0x20000000U)
836 #define FMC_ACCESS_MODE_D ((uint32_t)0x30000000)
837 /**
838 * @}
839 */
840
841 /**
842 * @}
843 */
844
845 /** @defgroup FMC_LL_NAND_Controller FMC NAND Controller
846 * @{
847 */
848 /** @defgroup FMC_NAND_Bank FMC NAND Bank
849 * @{
850 */
851 #define FMC_NAND_BANK3 ((uint32_t)0x00000100U)
852 /**
853 * @}
854 */
855
856 /** @defgroup FMC_Wait_feature FMC Wait feature
857 * @{
858 */
859 #define FMC_NAND_WAIT_FEATURE_DISABLE ((uint32_t)0x00000000U)
860 #define FMC_NAND_WAIT_FEATURE_ENABLE ((uint32_t)0x00000002U)
861 /**
862 * @}
863 */
864
865 /** @defgroup FMC_PCR_Memory_Type FMC PCR Memory Type
866 * @{
867 */
868 #define FMC_PCR_MEMORY_TYPE_NAND ((uint32_t)0x00000008U)
869 /**
870 * @}
871 */
872
873 /** @defgroup FMC_NAND_Data_Width FMC NAND Data Width
874 * @{
875 */
876 #define FMC_NAND_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
877 #define FMC_NAND_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
878 /**
879 * @}
880 */
881
882 /** @defgroup FMC_ECC FMC ECC
883 * @{
884 */
885 #define FMC_NAND_ECC_DISABLE ((uint32_t)0x00000000U)
886 #define FMC_NAND_ECC_ENABLE ((uint32_t)0x00000040U)
887 /**
888 * @}
889 */
890
891 /** @defgroup FMC_ECC_Page_Size FMC ECC Page Size
892 * @{
893 */
894 #define FMC_NAND_ECC_PAGE_SIZE_256BYTE ((uint32_t)0x00000000U)
895 #define FMC_NAND_ECC_PAGE_SIZE_512BYTE ((uint32_t)0x00020000U)
896 #define FMC_NAND_ECC_PAGE_SIZE_1024BYTE ((uint32_t)0x00040000U)
897 #define FMC_NAND_ECC_PAGE_SIZE_2048BYTE ((uint32_t)0x00060000U)
898 #define FMC_NAND_ECC_PAGE_SIZE_4096BYTE ((uint32_t)0x00080000U)
899 #define FMC_NAND_ECC_PAGE_SIZE_8192BYTE ((uint32_t)0x000A0000U)
900 /**
901 * @}
902 */
903
904 /**
905 * @}
906 */
907
908 /** @defgroup FMC_LL_SDRAM_Controller FMC SDRAM Controller
909 * @{
910 */
911 /** @defgroup FMC_SDRAM_Bank FMC SDRAM Bank
912 * @{
913 */
914 #define FMC_SDRAM_BANK1 ((uint32_t)0x00000000U)
915 #define FMC_SDRAM_BANK2 ((uint32_t)0x00000001U)
916 /**
917 * @}
918 */
919
920 /** @defgroup FMC_SDRAM_Column_Bits_number FMC SDRAM Column Bits number
921 * @{
922 */
923 #define FMC_SDRAM_COLUMN_BITS_NUM_8 ((uint32_t)0x00000000U)
924 #define FMC_SDRAM_COLUMN_BITS_NUM_9 ((uint32_t)0x00000001U)
925 #define FMC_SDRAM_COLUMN_BITS_NUM_10 ((uint32_t)0x00000002U)
926 #define FMC_SDRAM_COLUMN_BITS_NUM_11 ((uint32_t)0x00000003U)
927 /**
928 * @}
929 */
930
931 /** @defgroup FMC_SDRAM_Row_Bits_number FMC SDRAM Row Bits number
932 * @{
933 */
934 #define FMC_SDRAM_ROW_BITS_NUM_11 ((uint32_t)0x00000000U)
935 #define FMC_SDRAM_ROW_BITS_NUM_12 ((uint32_t)0x00000004U)
936 #define FMC_SDRAM_ROW_BITS_NUM_13 ((uint32_t)0x00000008U)
937 /**
938 * @}
939 */
940
941 /** @defgroup FMC_SDRAM_Memory_Bus_Width FMC SDRAM Memory Bus Width
942 * @{
943 */
944 #define FMC_SDRAM_MEM_BUS_WIDTH_8 ((uint32_t)0x00000000U)
945 #define FMC_SDRAM_MEM_BUS_WIDTH_16 ((uint32_t)0x00000010U)
946 #define FMC_SDRAM_MEM_BUS_WIDTH_32 ((uint32_t)0x00000020U)
947 /**
948 * @}
949 */
950
951 /** @defgroup FMC_SDRAM_Internal_Banks_Number FMC SDRAM Internal Banks Number
952 * @{
953 */
954 #define FMC_SDRAM_INTERN_BANKS_NUM_2 ((uint32_t)0x00000000U)
955 #define FMC_SDRAM_INTERN_BANKS_NUM_4 ((uint32_t)0x00000040U)
956 /**
957 * @}
958 */
959
960 /** @defgroup FMC_SDRAM_CAS_Latency FMC SDRAM CAS Latency
961 * @{
962 */
963 #define FMC_SDRAM_CAS_LATENCY_1 ((uint32_t)0x00000080U)
964 #define FMC_SDRAM_CAS_LATENCY_2 ((uint32_t)0x00000100U)
965 #define FMC_SDRAM_CAS_LATENCY_3 ((uint32_t)0x00000180)
966 /**
967 * @}
968 */
969
970 /** @defgroup FMC_SDRAM_Write_Protection FMC SDRAM Write Protection
971 * @{
972 */
973 #define FMC_SDRAM_WRITE_PROTECTION_DISABLE ((uint32_t)0x00000000U)
974 #define FMC_SDRAM_WRITE_PROTECTION_ENABLE ((uint32_t)0x00000200U)
975 /**
976 * @}
977 */
978
979 /** @defgroup FMC_SDRAM_Clock_Period FMC SDRAM Clock Period
980 * @{
981 */
982 #define FMC_SDRAM_CLOCK_DISABLE ((uint32_t)0x00000000U)
983 #define FMC_SDRAM_CLOCK_PERIOD_2 ((uint32_t)0x00000800U)
984 #define FMC_SDRAM_CLOCK_PERIOD_3 ((uint32_t)0x00000C00)
985 /**
986 * @}
987 */
988
989 /** @defgroup FMC_SDRAM_Read_Burst FMC SDRAM Read Burst
990 * @{
991 */
992 #define FMC_SDRAM_RBURST_DISABLE ((uint32_t)0x00000000U)
993 #define FMC_SDRAM_RBURST_ENABLE ((uint32_t)0x00001000U)
994 /**
995 * @}
996 */
997
998 /** @defgroup FMC_SDRAM_Read_Pipe_Delay FMC SDRAM Read Pipe Delay
999 * @{
1000 */
1001 #define FMC_SDRAM_RPIPE_DELAY_0 ((uint32_t)0x00000000U)
1002 #define FMC_SDRAM_RPIPE_DELAY_1 ((uint32_t)0x00002000U)
1003 #define FMC_SDRAM_RPIPE_DELAY_2 ((uint32_t)0x00004000U)
1004 /**
1005 * @}
1006 */
1007
1008 /** @defgroup FMC_SDRAM_Command_Mode FMC SDRAM Command Mode
1009 * @{
1010 */
1011 #define FMC_SDRAM_CMD_NORMAL_MODE ((uint32_t)0x00000000U)
1012 #define FMC_SDRAM_CMD_CLK_ENABLE ((uint32_t)0x00000001U)
1013 #define FMC_SDRAM_CMD_PALL ((uint32_t)0x00000002U)
1014 #define FMC_SDRAM_CMD_AUTOREFRESH_MODE ((uint32_t)0x00000003U)
1015 #define FMC_SDRAM_CMD_LOAD_MODE ((uint32_t)0x00000004U)
1016 #define FMC_SDRAM_CMD_SELFREFRESH_MODE ((uint32_t)0x00000005U)
1017 #define FMC_SDRAM_CMD_POWERDOWN_MODE ((uint32_t)0x00000006U)
1018 /**
1019 * @}
1020 */
1021
1022 /** @defgroup FMC_SDRAM_Command_Target FMC SDRAM Command Target
1023 * @{
1024 */
1025 #define FMC_SDRAM_CMD_TARGET_BANK2 FMC_SDCMR_CTB2
1026 #define FMC_SDRAM_CMD_TARGET_BANK1 FMC_SDCMR_CTB1
1027 #define FMC_SDRAM_CMD_TARGET_BANK1_2 ((uint32_t)0x00000018U)
1028 /**
1029 * @}
1030 */
1031
1032 /** @defgroup FMC_SDRAM_Mode_Status FMC SDRAM Mode Status
1033 * @{
1034 */
1035 #define FMC_SDRAM_NORMAL_MODE ((uint32_t)0x00000000U)
1036 #define FMC_SDRAM_SELF_REFRESH_MODE FMC_SDSR_MODES1_0
1037 #define FMC_SDRAM_POWER_DOWN_MODE FMC_SDSR_MODES1_1
1038 /**
1039 * @}
1040 */
1041
1042 /**
1043 * @}
1044 */
1045
1046 /** @defgroup FMC_LL_Interrupt_definition FMC Low Layer Interrupt definition
1047 * @{
1048 */
1049 #define FMC_IT_RISING_EDGE ((uint32_t)0x00000008U)
1050 #define FMC_IT_LEVEL ((uint32_t)0x00000010U)
1051 #define FMC_IT_FALLING_EDGE ((uint32_t)0x00000020U)
1052 #define FMC_IT_REFRESH_ERROR ((uint32_t)0x00004000U)
1053 /**
1054 * @}
1055 */
1056
1057 /** @defgroup FMC_LL_Flag_definition FMC Low Layer Flag definition
1058 * @{
1059 */
1060 #define FMC_FLAG_RISING_EDGE ((uint32_t)0x00000001U)
1061 #define FMC_FLAG_LEVEL ((uint32_t)0x00000002U)
1062 #define FMC_FLAG_FALLING_EDGE ((uint32_t)0x00000004U)
1063 #define FMC_FLAG_FEMPT ((uint32_t)0x00000040U)
1064 #define FMC_SDRAM_FLAG_REFRESH_IT FMC_SDSR_RE
1065 #define FMC_SDRAM_FLAG_BUSY FMC_SDSR_BUSY
1066 #define FMC_SDRAM_FLAG_REFRESH_ERROR FMC_SDRTR_CRE
1067 /**
1068 * @}
1069 */
1070 /**
1071 * @}
1072 */
1073
1074 /**
1075 * @}
1076 */
1077
1078 /* Private macro -------------------------------------------------------------*/
1079 /** @defgroup FMC_LL_Private_Macros FMC_LL Private Macros
1080 * @{
1081 */
1082
1083 /** @defgroup FMC_LL_NOR_Macros FMC NOR/SRAM Macros
1084 * @brief macros to handle NOR device enable/disable and read/write operations
1085 * @{
1086 */
1087
1088 /**
1089 * @brief Enable the NORSRAM device access.
1090 * @param __INSTANCE__: FMC_NORSRAM Instance
1091 * @param __BANK__: FMC_NORSRAM Bank
1092 * @retval None
1093 */
1094 #define __FMC_NORSRAM_ENABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] |= FMC_BCR1_MBKEN)
1095
1096 /**
1097 * @brief Disable the NORSRAM device access.
1098 * @param __INSTANCE__: FMC_NORSRAM Instance
1099 * @param __BANK__: FMC_NORSRAM Bank
1100 * @retval None
1101 */
1102 #define __FMC_NORSRAM_DISABLE(__INSTANCE__, __BANK__) ((__INSTANCE__)->BTCR[(__BANK__)] &= ~FMC_BCR1_MBKEN)
1103
1104 /**
1105 * @}
1106 */
1107
1108 /** @defgroup FMC_LL_NAND_Macros FMC NAND Macros
1109 * @brief macros to handle NAND device enable/disable
1110 * @{
1111 */
1112
1113 /**
1114 * @brief Enable the NAND device access.
1115 * @param __INSTANCE__: FMC_NAND Instance
1116 * @retval None
1117 */
1118 #define __FMC_NAND_ENABLE(__INSTANCE__) ((__INSTANCE__)->PCR |= FMC_PCR_PBKEN)
1119
1120 /**
1121 * @brief Disable the NAND device access.
1122 * @param __INSTANCE__: FMC_NAND Instance
1123 * @retval None
1124 */
1125 #define __FMC_NAND_DISABLE(__INSTANCE__) ((__INSTANCE__)->PCR &= ~FMC_PCR_PBKEN)
1126
1127 /**
1128 * @}
1129 */
1130
1131 /** @defgroup FMC_Interrupt FMC Interrupt
1132 * @brief macros to handle FMC interrupts
1133 * @{
1134 */
1135
1136 /**
1137 * @brief Enable the NAND device interrupt.
1138 * @param __INSTANCE__: FMC_NAND instance
1139 * @param __INTERRUPT__: FMC_NAND interrupt
1140 * This parameter can be any combination of the following values:
1141 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1142 * @arg FMC_IT_LEVEL: Interrupt level.
1143 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1144 * @retval None
1145 */
1146 #define __FMC_NAND_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR |= (__INTERRUPT__))
1147
1148 /**
1149 * @brief Disable the NAND device interrupt.
1150 * @param __INSTANCE__: FMC_NAND Instance
1151 * @param __INTERRUPT__: FMC_NAND interrupt
1152 * This parameter can be any combination of the following values:
1153 * @arg FMC_IT_RISING_EDGE: Interrupt rising edge.
1154 * @arg FMC_IT_LEVEL: Interrupt level.
1155 * @arg FMC_IT_FALLING_EDGE: Interrupt falling edge.
1156 * @retval None
1157 */
1158 #define __FMC_NAND_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SR &= ~(__INTERRUPT__))
1159
1160 /**
1161 * @brief Get flag status of the NAND device.
1162 * @param __INSTANCE__: FMC_NAND Instance
1163 * @param __BANK__: FMC_NAND Bank
1164 * @param __FLAG__: FMC_NAND flag
1165 * This parameter can be any combination of the following values:
1166 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1167 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1168 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1169 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1170 * @retval The state of FLAG (SET or RESET).
1171 */
1172 #define __FMC_NAND_GET_FLAG(__INSTANCE__, __BANK__, __FLAG__) (((__INSTANCE__)->SR &(__FLAG__)) == (__FLAG__))
1173
1174 /**
1175 * @brief Clear flag status of the NAND device.
1176 * @param __INSTANCE__: FMC_NAND Instance
1177 * @param __FLAG__: FMC_NAND flag
1178 * This parameter can be any combination of the following values:
1179 * @arg FMC_FLAG_RISING_EDGE: Interrupt rising edge flag.
1180 * @arg FMC_FLAG_LEVEL: Interrupt level edge flag.
1181 * @arg FMC_FLAG_FALLING_EDGE: Interrupt falling edge flag.
1182 * @arg FMC_FLAG_FEMPT: FIFO empty flag.
1183 * @retval None
1184 */
1185 #define __FMC_NAND_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SR &= ~(__FLAG__))
1186
1187 /**
1188 * @brief Enable the SDRAM device interrupt.
1189 * @param __INSTANCE__: FMC_SDRAM instance
1190 * @param __INTERRUPT__: FMC_SDRAM interrupt
1191 * This parameter can be any combination of the following values:
1192 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1193 * @retval None
1194 */
1195 #define __FMC_SDRAM_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR |= (__INTERRUPT__))
1196
1197 /**
1198 * @brief Disable the SDRAM device interrupt.
1199 * @param __INSTANCE__: FMC_SDRAM instance
1200 * @param __INTERRUPT__: FMC_SDRAM interrupt
1201 * This parameter can be any combination of the following values:
1202 * @arg FMC_IT_REFRESH_ERROR: Interrupt refresh error
1203 * @retval None
1204 */
1205 #define __FMC_SDRAM_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->SDRTR &= ~(__INTERRUPT__))
1206
1207 /**
1208 * @brief Get flag status of the SDRAM device.
1209 * @param __INSTANCE__: FMC_SDRAM instance
1210 * @param __FLAG__: FMC_SDRAM flag
1211 * This parameter can be any combination of the following values:
1212 * @arg FMC_SDRAM_FLAG_REFRESH_IT: Interrupt refresh error.
1213 * @arg FMC_SDRAM_FLAG_BUSY: SDRAM busy flag.
1214 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR: Refresh error flag.
1215 * @retval The state of FLAG (SET or RESET).
1216 */
1217 #define __FMC_SDRAM_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->SDSR &(__FLAG__)) == (__FLAG__))
1218
1219 /**
1220 * @brief Clear flag status of the SDRAM device.
1221 * @param __INSTANCE__: FMC_SDRAM instance
1222 * @param __FLAG__: FMC_SDRAM flag
1223 * This parameter can be any combination of the following values:
1224 * @arg FMC_SDRAM_FLAG_REFRESH_ERROR
1225 * @retval None
1226 */
1227 #define __FMC_SDRAM_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->SDRTR |= (__FLAG__))
1228 /**
1229 * @}
1230 */
1231
1232 /**
1233 * @}
1234 */
1235
1236 /* Private functions ---------------------------------------------------------*/
1237 /** @defgroup FMC_LL_Private_Functions FMC LL Private Functions
1238 * @{
1239 */
1240
1241 /** @defgroup FMC_LL_NORSRAM NOR SRAM
1242 * @{
1243 */
1244 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group1 NOR SRAM Initialization/de-initialization functions
1245 * @{
1246 */
1247 HAL_StatusTypeDef FMC_NORSRAM_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_InitTypeDef *Init);
1248 HAL_StatusTypeDef FMC_NORSRAM_Timing_Init(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank);
1249 HAL_StatusTypeDef FMC_NORSRAM_Extended_Timing_Init(FMC_NORSRAM_EXTENDED_TypeDef *Device, FMC_NORSRAM_TimingTypeDef *Timing, uint32_t Bank, uint32_t ExtendedMode);
1250 HAL_StatusTypeDef FMC_NORSRAM_DeInit(FMC_NORSRAM_TypeDef *Device, FMC_NORSRAM_EXTENDED_TypeDef *ExDevice, uint32_t Bank);
1251 /**
1252 * @}
1253 */
1254
1255 /** @defgroup FMC_LL_NORSRAM_Private_Functions_Group2 NOR SRAM Control functions
1256 * @{
1257 */
1258 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Enable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1259 HAL_StatusTypeDef FMC_NORSRAM_WriteOperation_Disable(FMC_NORSRAM_TypeDef *Device, uint32_t Bank);
1260 /**
1261 * @}
1262 */
1263 /**
1264 * @}
1265 */
1266
1267 /** @defgroup FMC_LL_NAND NAND
1268 * @{
1269 */
1270 /** @defgroup FMC_LL_NAND_Private_Functions_Group1 NAND Initialization/de-initialization functions
1271 * @{
1272 */
1273 HAL_StatusTypeDef FMC_NAND_Init(FMC_NAND_TypeDef *Device, FMC_NAND_InitTypeDef *Init);
1274 HAL_StatusTypeDef FMC_NAND_CommonSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1275 HAL_StatusTypeDef FMC_NAND_AttributeSpace_Timing_Init(FMC_NAND_TypeDef *Device, FMC_NAND_PCC_TimingTypeDef *Timing, uint32_t Bank);
1276 HAL_StatusTypeDef FMC_NAND_DeInit(FMC_NAND_TypeDef *Device, uint32_t Bank);
1277 /**
1278 * @}
1279 */
1280
1281 /** @defgroup FMC_LL_NAND_Private_Functions_Group2 NAND Control functions
1282 * @{
1283 */
1284 HAL_StatusTypeDef FMC_NAND_ECC_Enable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1285 HAL_StatusTypeDef FMC_NAND_ECC_Disable(FMC_NAND_TypeDef *Device, uint32_t Bank);
1286 HAL_StatusTypeDef FMC_NAND_GetECC(FMC_NAND_TypeDef *Device, uint32_t *ECCval, uint32_t Bank, uint32_t Timeout);
1287 /**
1288 * @}
1289 */
1290
1291 /** @defgroup FMC_LL_SDRAM SDRAM
1292 * @{
1293 */
1294 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group1 SDRAM Initialization/de-initialization functions
1295 * @{
1296 */
1297 HAL_StatusTypeDef FMC_SDRAM_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_InitTypeDef *Init);
1298 HAL_StatusTypeDef FMC_SDRAM_Timing_Init(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_TimingTypeDef *Timing, uint32_t Bank);
1299 HAL_StatusTypeDef FMC_SDRAM_DeInit(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1300
1301 /**
1302 * @}
1303 */
1304
1305 /** @defgroup FMC_LL_SDRAM_Private_Functions_Group2 SDRAM Control functions
1306 * @{
1307 */
1308 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Enable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1309 HAL_StatusTypeDef FMC_SDRAM_WriteProtection_Disable(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1310 HAL_StatusTypeDef FMC_SDRAM_SendCommand(FMC_SDRAM_TypeDef *Device, FMC_SDRAM_CommandTypeDef *Command, uint32_t Timeout);
1311 HAL_StatusTypeDef FMC_SDRAM_ProgramRefreshRate(FMC_SDRAM_TypeDef *Device, uint32_t RefreshRate);
1312 HAL_StatusTypeDef FMC_SDRAM_SetAutoRefreshNumber(FMC_SDRAM_TypeDef *Device, uint32_t AutoRefreshNumber);
1313 uint32_t FMC_SDRAM_GetModeStatus(FMC_SDRAM_TypeDef *Device, uint32_t Bank);
1314 /**
1315 * @}
1316 */
1317
1318 /**
1319 * @}
1320 */
1321
1322 /**
1323 * @}
1324 */
1325
1326 /**
1327 * @}
1328 */
1329
1330 /**
1331 * @}
1332 */
1333 #ifdef __cplusplus
1334 }
1335 #endif
1336
1337 #endif /* __STM32F7xx_LL_FMC_H */
1338
1339 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software