?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_i2c.h
blob791db20c05136de56a4d5b57e64b649bda742112
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_i2c.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of I2C LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_I2C_H
40 #define __STM32F7xx_LL_I2C_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (I2C1) || defined (I2C2) || defined (I2C3) || defined (I2C4)
54
55 /** @defgroup I2C_LL I2C
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61
62 /* Private constants ---------------------------------------------------------*/
63 /** @defgroup I2C_LL_Private_Constants I2C Private Constants
64 * @{
65 */
66 /**
67 * @}
68 */
69
70 /* Private macros ------------------------------------------------------------*/
71 #if defined(USE_FULL_LL_DRIVER)
72 /** @defgroup I2C_LL_Private_Macros I2C Private Macros
73 * @{
74 */
75 /**
76 * @}
77 */
78 #endif /*USE_FULL_LL_DRIVER*/
79
80 /* Exported types ------------------------------------------------------------*/
81 #if defined(USE_FULL_LL_DRIVER)
82 /** @defgroup I2C_LL_ES_INIT I2C Exported Init structure
83 * @{
84 */
85 typedef struct
86 {
87 uint32_t PeripheralMode; /*!< Specifies the peripheral mode.
88 This parameter can be a value of @ref I2C_LL_EC_PERIPHERAL_MODE
89
90 This feature can be modified afterwards using unitary function @ref LL_I2C_SetMode(). */
91
92 uint32_t Timing; /*!< Specifies the SDA setup, hold time and the SCL high, low period values.
93 This parameter must be set by referring to the STM32CubeMX Tool and
94 the helper macro @ref __LL_I2C_CONVERT_TIMINGS()
95
96 This feature can be modified afterwards using unitary function @ref LL_I2C_SetTiming(). */
97
98 uint32_t AnalogFilter; /*!< Enables or disables analog noise filter.
99 This parameter can be a value of @ref I2C_LL_EC_ANALOGFILTER_SELECTION
100
101 This feature can be modified afterwards using unitary functions @ref LL_I2C_EnableAnalogFilter() or LL_I2C_DisableAnalogFilter(). */
102
103 uint32_t DigitalFilter; /*!< Configures the digital noise filter.
104 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0x0F
105
106 This feature can be modified afterwards using unitary function @ref LL_I2C_SetDigitalFilter(). */
107
108 uint32_t OwnAddress1; /*!< Specifies the device own address 1.
109 This parameter must be a value between Min_Data = 0x00 and Max_Data = 0x3FF
110
111 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
112
113 uint32_t TypeAcknowledge; /*!< Specifies the ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
114 This parameter can be a value of @ref I2C_LL_EC_I2C_ACKNOWLEDGE
115
116 This feature can be modified afterwards using unitary function @ref LL_I2C_AcknowledgeNextData(). */
117
118 uint32_t OwnAddrSize; /*!< Specifies the device own address 1 size (7-bit or 10-bit).
119 This parameter can be a value of @ref I2C_LL_EC_OWNADDRESS1
120
121 This feature can be modified afterwards using unitary function @ref LL_I2C_SetOwnAddress1(). */
122 } LL_I2C_InitTypeDef;
123 /**
124 * @}
125 */
126 #endif /*USE_FULL_LL_DRIVER*/
127
128 /* Exported constants --------------------------------------------------------*/
129 /** @defgroup I2C_LL_Exported_Constants I2C Exported Constants
130 * @{
131 */
132
133 /** @defgroup I2C_LL_EC_CLEAR_FLAG Clear Flags Defines
134 * @brief Flags defines which can be used with LL_I2C_WriteReg function
135 * @{
136 */
137 #define LL_I2C_ICR_ADDRCF I2C_ICR_ADDRCF /*!< Address Matched flag */
138 #define LL_I2C_ICR_NACKCF I2C_ICR_NACKCF /*!< Not Acknowledge flag */
139 #define LL_I2C_ICR_STOPCF I2C_ICR_STOPCF /*!< Stop detection flag */
140 #define LL_I2C_ICR_BERRCF I2C_ICR_BERRCF /*!< Bus error flag */
141 #define LL_I2C_ICR_ARLOCF I2C_ICR_ARLOCF /*!< Arbitration Lost flag */
142 #define LL_I2C_ICR_OVRCF I2C_ICR_OVRCF /*!< Overrun/Underrun flag */
143 #define LL_I2C_ICR_PECCF I2C_ICR_PECCF /*!< PEC error flag */
144 #define LL_I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF /*!< Timeout detection flag */
145 #define LL_I2C_ICR_ALERTCF I2C_ICR_ALERTCF /*!< Alert flag */
146 /**
147 * @}
148 */
149
150 /** @defgroup I2C_LL_EC_GET_FLAG Get Flags Defines
151 * @brief Flags defines which can be used with LL_I2C_ReadReg function
152 * @{
153 */
154 #define LL_I2C_ISR_TXE I2C_ISR_TXE /*!< Transmit data register empty */
155 #define LL_I2C_ISR_TXIS I2C_ISR_TXIS /*!< Transmit interrupt status */
156 #define LL_I2C_ISR_RXNE I2C_ISR_RXNE /*!< Receive data register not empty */
157 #define LL_I2C_ISR_ADDR I2C_ISR_ADDR /*!< Address matched (slave mode) */
158 #define LL_I2C_ISR_NACKF I2C_ISR_NACKF /*!< Not Acknowledge received flag */
159 #define LL_I2C_ISR_STOPF I2C_ISR_STOPF /*!< Stop detection flag */
160 #define LL_I2C_ISR_TC I2C_ISR_TC /*!< Transfer Complete (master mode) */
161 #define LL_I2C_ISR_TCR I2C_ISR_TCR /*!< Transfer Complete Reload */
162 #define LL_I2C_ISR_BERR I2C_ISR_BERR /*!< Bus error */
163 #define LL_I2C_ISR_ARLO I2C_ISR_ARLO /*!< Arbitration lost */
164 #define LL_I2C_ISR_OVR I2C_ISR_OVR /*!< Overrun/Underrun (slave mode) */
165 #define LL_I2C_ISR_PECERR I2C_ISR_PECERR /*!< PEC Error in reception (SMBus mode) */
166 #define LL_I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT /*!< Timeout detection flag (SMBus mode) */
167 #define LL_I2C_ISR_ALERT I2C_ISR_ALERT /*!< SMBus alert (SMBus mode) */
168 #define LL_I2C_ISR_BUSY I2C_ISR_BUSY /*!< Bus busy */
169 /**
170 * @}
171 */
172
173 /** @defgroup I2C_LL_EC_IT IT Defines
174 * @brief IT defines which can be used with LL_I2C_ReadReg and LL_I2C_WriteReg functions
175 * @{
176 */
177 #define LL_I2C_CR1_TXIE I2C_CR1_TXIE /*!< TX Interrupt enable */
178 #define LL_I2C_CR1_RXIE I2C_CR1_RXIE /*!< RX Interrupt enable */
179 #define LL_I2C_CR1_ADDRIE I2C_CR1_ADDRIE /*!< Address match Interrupt enable (slave only) */
180 #define LL_I2C_CR1_NACKIE I2C_CR1_NACKIE /*!< Not acknowledge received Interrupt enable */
181 #define LL_I2C_CR1_STOPIE I2C_CR1_STOPIE /*!< STOP detection Interrupt enable */
182 #define LL_I2C_CR1_TCIE I2C_CR1_TCIE /*!< Transfer Complete interrupt enable */
183 #define LL_I2C_CR1_ERRIE I2C_CR1_ERRIE /*!< Error interrupts enable */
184 /**
185 * @}
186 */
187
188 /** @defgroup I2C_LL_EC_PERIPHERAL_MODE Peripheral Mode
189 * @{
190 */
191 #define LL_I2C_MODE_I2C 0x00000000U /*!< I2C Master or Slave mode */
192 #define LL_I2C_MODE_SMBUS_HOST I2C_CR1_SMBHEN /*!< SMBus Host address acknowledge */
193 #define LL_I2C_MODE_SMBUS_DEVICE 0x00000000U /*!< SMBus Device default mode (Default address not acknowledge) */
194 #define LL_I2C_MODE_SMBUS_DEVICE_ARP I2C_CR1_SMBDEN /*!< SMBus Device Default address acknowledge */
195 /**
196 * @}
197 */
198
199 /** @defgroup I2C_LL_EC_ANALOGFILTER_SELECTION Analog Filter Selection
200 * @{
201 */
202 #define LL_I2C_ANALOGFILTER_ENABLE 0x00000000U /*!< Analog filter is enabled. */
203 #define LL_I2C_ANALOGFILTER_DISABLE I2C_CR1_ANFOFF /*!< Analog filter is disabled. */
204 /**
205 * @}
206 */
207
208 /** @defgroup I2C_LL_EC_ADDRESSING_MODE Master Addressing Mode
209 * @{
210 */
211 #define LL_I2C_ADDRESSING_MODE_7BIT 0x00000000U /*!< Master operates in 7-bit addressing mode. */
212 #define LL_I2C_ADDRESSING_MODE_10BIT I2C_CR2_ADD10 /*!< Master operates in 10-bit addressing mode.*/
213 /**
214 * @}
215 */
216
217 /** @defgroup I2C_LL_EC_OWNADDRESS1 Own Address 1 Length
218 * @{
219 */
220 #define LL_I2C_OWNADDRESS1_7BIT 0x00000000U /*!< Own address 1 is a 7-bit address. */
221 #define LL_I2C_OWNADDRESS1_10BIT I2C_OAR1_OA1MODE /*!< Own address 1 is a 10-bit address.*/
222 /**
223 * @}
224 */
225
226 /** @defgroup I2C_LL_EC_OWNADDRESS2 Own Address 2 Masks
227 * @{
228 */
229 #define LL_I2C_OWNADDRESS2_NOMASK I2C_OAR2_OA2NOMASK /*!< Own Address2 No mask. */
230 #define LL_I2C_OWNADDRESS2_MASK01 I2C_OAR2_OA2MASK01 /*!< Only Address2 bits[7:2] are compared. */
231 #define LL_I2C_OWNADDRESS2_MASK02 I2C_OAR2_OA2MASK02 /*!< Only Address2 bits[7:3] are compared. */
232 #define LL_I2C_OWNADDRESS2_MASK03 I2C_OAR2_OA2MASK03 /*!< Only Address2 bits[7:4] are compared. */
233 #define LL_I2C_OWNADDRESS2_MASK04 I2C_OAR2_OA2MASK04 /*!< Only Address2 bits[7:5] are compared. */
234 #define LL_I2C_OWNADDRESS2_MASK05 I2C_OAR2_OA2MASK05 /*!< Only Address2 bits[7:6] are compared. */
235 #define LL_I2C_OWNADDRESS2_MASK06 I2C_OAR2_OA2MASK06 /*!< Only Address2 bits[7] are compared. */
236 #define LL_I2C_OWNADDRESS2_MASK07 I2C_OAR2_OA2MASK07 /*!< No comparison is done. All Address2 are acknowledged.*/
237 /**
238 * @}
239 */
240
241 /** @defgroup I2C_LL_EC_I2C_ACKNOWLEDGE Acknowledge Generation
242 * @{
243 */
244 #define LL_I2C_ACK 0x00000000U /*!< ACK is sent after current received byte. */
245 #define LL_I2C_NACK I2C_CR2_NACK /*!< NACK is sent after current received byte.*/
246 /**
247 * @}
248 */
249
250 /** @defgroup I2C_LL_EC_ADDRSLAVE Slave Address Length
251 * @{
252 */
253 #define LL_I2C_ADDRSLAVE_7BIT 0x00000000U /*!< Slave Address in 7-bit. */
254 #define LL_I2C_ADDRSLAVE_10BIT I2C_CR2_ADD10 /*!< Slave Address in 10-bit.*/
255 /**
256 * @}
257 */
258
259 /** @defgroup I2C_LL_EC_REQUEST Transfer Request Direction
260 * @{
261 */
262 #define LL_I2C_REQUEST_WRITE 0x00000000U /*!< Master request a write transfer. */
263 #define LL_I2C_REQUEST_READ I2C_CR2_RD_WRN /*!< Master request a read transfer. */
264 /**
265 * @}
266 */
267
268 /** @defgroup I2C_LL_EC_MODE Transfer End Mode
269 * @{
270 */
271 #define LL_I2C_MODE_RELOAD I2C_CR2_RELOAD /*!< Enable I2C Reload mode. */
272 #define LL_I2C_MODE_AUTOEND I2C_CR2_AUTOEND /*!< Enable I2C Automatic end mode with no HW PEC comparison. */
273 #define LL_I2C_MODE_SOFTEND 0x00000000U /*!< Enable I2C Software end mode with no HW PEC comparison. */
274 #define LL_I2C_MODE_SMBUS_RELOAD LL_I2C_MODE_RELOAD /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
275 #define LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC LL_I2C_MODE_AUTOEND /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
276 #define LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC LL_I2C_MODE_SOFTEND /*!< Enable SMBUS Software end mode with HW PEC comparison. */
277 #define LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC (uint32_t)(LL_I2C_MODE_AUTOEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Automatic end mode with HW PEC comparison. */
278 #define LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC (uint32_t)(LL_I2C_MODE_SOFTEND | I2C_CR2_PECBYTE) /*!< Enable SMBUS Software end mode with HW PEC comparison. */
279 /**
280 * @}
281 */
282
283 /** @defgroup I2C_LL_EC_GENERATE Start And Stop Generation
284 * @{
285 */
286 #define LL_I2C_GENERATE_NOSTARTSTOP 0x00000000U /*!< Don't Generate Stop and Start condition. */
287 #define LL_I2C_GENERATE_STOP I2C_CR2_STOP /*!< Generate Stop condition (Size should be set to 0). */
288 #define LL_I2C_GENERATE_START_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Start for read request. */
289 #define LL_I2C_GENERATE_START_WRITE I2C_CR2_START /*!< Generate Start for write request. */
290 #define LL_I2C_GENERATE_RESTART_7BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN) /*!< Generate Restart for read request, slave 7Bit address. */
291 #define LL_I2C_GENERATE_RESTART_7BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 7Bit address. */
292 #define LL_I2C_GENERATE_RESTART_10BIT_READ (uint32_t)(I2C_CR2_START | I2C_CR2_RD_WRN | I2C_CR2_HEAD10R) /*!< Generate Restart for read request, slave 10Bit address. */
293 #define LL_I2C_GENERATE_RESTART_10BIT_WRITE I2C_CR2_START /*!< Generate Restart for write request, slave 10Bit address.*/
294 /**
295 * @}
296 */
297
298 /** @defgroup I2C_LL_EC_DIRECTION Read Write Direction
299 * @{
300 */
301 #define LL_I2C_DIRECTION_WRITE 0x00000000U /*!< Write transfer request by master, slave enters receiver mode. */
302 #define LL_I2C_DIRECTION_READ I2C_ISR_DIR /*!< Read transfer request by master, slave enters transmitter mode.*/
303 /**
304 * @}
305 */
306
307 /** @defgroup I2C_LL_EC_DMA_REG_DATA DMA Register Data
308 * @{
309 */
310 #define LL_I2C_DMA_REG_DATA_TRANSMIT 0x00000000U /*!< Get address of data register used for transmission */
311 #define LL_I2C_DMA_REG_DATA_RECEIVE 0x00000001U /*!< Get address of data register used for reception */
312 /**
313 * @}
314 */
315
316 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUTA_MODE SMBus TimeoutA Mode SCL SDA Timeout
317 * @{
318 */
319 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW 0x00000000U /*!< TimeoutA is used to detect SCL low level timeout. */
320 #define LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH I2C_TIMEOUTR_TIDLE /*!< TimeoutA is used to detect both SCL and SDA high level timeout.*/
321 /**
322 * @}
323 */
324
325 /** @defgroup I2C_LL_EC_SMBUS_TIMEOUT_SELECTION SMBus Timeout Selection
326 * @{
327 */
328 #define LL_I2C_SMBUS_TIMEOUTA I2C_TIMEOUTR_TIMOUTEN /*!< TimeoutA enable bit */
329 #define LL_I2C_SMBUS_TIMEOUTB I2C_TIMEOUTR_TEXTEN /*!< TimeoutB (extended clock) enable bit */
330 #define LL_I2C_SMBUS_ALL_TIMEOUT (uint32_t)(I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN) /*!< TimeoutA and TimeoutB (extended clock) enable bits */
331 /**
332 * @}
333 */
334
335 /**
336 * @}
337 */
338
339 /* Exported macro ------------------------------------------------------------*/
340 /** @defgroup I2C_LL_Exported_Macros I2C Exported Macros
341 * @{
342 */
343
344 /** @defgroup I2C_LL_EM_WRITE_READ Common Write and read registers Macros
345 * @{
346 */
347
348 /**
349 * @brief Write a value in I2C register
350 * @param __INSTANCE__ I2C Instance
351 * @param __REG__ Register to be written
352 * @param __VALUE__ Value to be written in the register
353 * @retval None
354 */
355 #define LL_I2C_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
356
357 /**
358 * @brief Read a value in I2C register
359 * @param __INSTANCE__ I2C Instance
360 * @param __REG__ Register to be read
361 * @retval Register value
362 */
363 #define LL_I2C_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
364 /**
365 * @}
366 */
367
368 /** @defgroup I2C_LL_EM_CONVERT_TIMINGS Convert SDA SCL timings
369 * @{
370 */
371 /**
372 * @brief Configure the SDA setup, hold time and the SCL high, low period.
373 * @param __PRESCALER__ This parameter must be a value between Min_Data=0 and Max_Data=0xF.
374 * @param __DATA_SETUP_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tscldel = (SCLDEL+1)xtpresc)
375 * @param __DATA_HOLD_TIME__ This parameter must be a value between Min_Data=0 and Max_Data=0xF. (tsdadel = SDADELxtpresc)
376 * @param __CLOCK_HIGH_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tsclh = (SCLH+1)xtpresc)
377 * @param __CLOCK_LOW_PERIOD__ This parameter must be a value between Min_Data=0 and Max_Data=0xFF. (tscll = (SCLL+1)xtpresc)
378 * @retval Value between Min_Data=0 and Max_Data=0xFFFFFFFF
379 */
380 #define __LL_I2C_CONVERT_TIMINGS(__PRESCALER__, __DATA_SETUP_TIME__, __DATA_HOLD_TIME__, __CLOCK_HIGH_PERIOD__, __CLOCK_LOW_PERIOD__) \
381 ((((uint32_t)(__PRESCALER__) << I2C_TIMINGR_PRESC_Pos) & I2C_TIMINGR_PRESC) | \
382 (((uint32_t)(__DATA_SETUP_TIME__) << I2C_TIMINGR_SCLDEL_Pos) & I2C_TIMINGR_SCLDEL) | \
383 (((uint32_t)(__DATA_HOLD_TIME__) << I2C_TIMINGR_SDADEL_Pos) & I2C_TIMINGR_SDADEL) | \
384 (((uint32_t)(__CLOCK_HIGH_PERIOD__) << I2C_TIMINGR_SCLH_Pos) & I2C_TIMINGR_SCLH) | \
385 (((uint32_t)(__CLOCK_LOW_PERIOD__) << I2C_TIMINGR_SCLL_Pos) & I2C_TIMINGR_SCLL))
386 /**
387 * @}
388 */
389
390 /**
391 * @}
392 */
393
394 /* Exported functions --------------------------------------------------------*/
395 /** @defgroup I2C_LL_Exported_Functions I2C Exported Functions
396 * @{
397 */
398
399 /** @defgroup I2C_LL_EF_Configuration Configuration
400 * @{
401 */
402
403 /**
404 * @brief Enable I2C peripheral (PE = 1).
405 * @rmtoll CR1 PE LL_I2C_Enable
406 * @param I2Cx I2C Instance.
407 * @retval None
408 */
409 __STATIC_INLINE void LL_I2C_Enable(I2C_TypeDef *I2Cx)
410 {
411 SET_BIT(I2Cx->CR1, I2C_CR1_PE);
412 }
413
414 /**
415 * @brief Disable I2C peripheral (PE = 0).
416 * @note When PE = 0, the I2C SCL and SDA lines are released.
417 * Internal state machines and status bits are put back to their reset value.
418 * When cleared, PE must be kept low for at least 3 APB clock cycles.
419 * @rmtoll CR1 PE LL_I2C_Disable
420 * @param I2Cx I2C Instance.
421 * @retval None
422 */
423 __STATIC_INLINE void LL_I2C_Disable(I2C_TypeDef *I2Cx)
424 {
425 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PE);
426 }
427
428 /**
429 * @brief Check if the I2C peripheral is enabled or disabled.
430 * @rmtoll CR1 PE LL_I2C_IsEnabled
431 * @param I2Cx I2C Instance.
432 * @retval State of bit (1 or 0).
433 */
434 __STATIC_INLINE uint32_t LL_I2C_IsEnabled(I2C_TypeDef *I2Cx)
435 {
436 return (READ_BIT(I2Cx->CR1, I2C_CR1_PE) == (I2C_CR1_PE));
437 }
438
439 /**
440 * @brief Configure Noise Filters (Analog and Digital).
441 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
442 * The filters can only be programmed when the I2C is disabled (PE = 0).
443 * @rmtoll CR1 ANFOFF LL_I2C_ConfigFilters\n
444 * CR1 DNF LL_I2C_ConfigFilters
445 * @param I2Cx I2C Instance.
446 * @param AnalogFilter This parameter can be one of the following values:
447 * @arg @ref LL_I2C_ANALOGFILTER_ENABLE
448 * @arg @ref LL_I2C_ANALOGFILTER_DISABLE
449 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
450 * This parameter is used to configure the digital noise filter on SDA and SCL input.
451 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
452 * @retval None
453 */
454 __STATIC_INLINE void LL_I2C_ConfigFilters(I2C_TypeDef *I2Cx, uint32_t AnalogFilter, uint32_t DigitalFilter)
455 {
456 MODIFY_REG(I2Cx->CR1, I2C_CR1_ANFOFF | I2C_CR1_DNF, AnalogFilter | (DigitalFilter << I2C_CR1_DNF_Pos));
457 }
458
459 /**
460 * @brief Configure Digital Noise Filter.
461 * @note If the analog filter is also enabled, the digital filter is added to analog filter.
462 * This filter can only be programmed when the I2C is disabled (PE = 0).
463 * @rmtoll CR1 DNF LL_I2C_SetDigitalFilter
464 * @param I2Cx I2C Instance.
465 * @param DigitalFilter This parameter must be a value between Min_Data=0x00 (Digital filter disabled) and Max_Data=0x0F (Digital filter enabled and filtering capability up to 15*ti2cclk).
466 * This parameter is used to configure the digital noise filter on SDA and SCL input.
467 * The digital filter will filter spikes with a length of up to DNF[3:0]*ti2cclk.
468 * @retval None
469 */
470 __STATIC_INLINE void LL_I2C_SetDigitalFilter(I2C_TypeDef *I2Cx, uint32_t DigitalFilter)
471 {
472 MODIFY_REG(I2Cx->CR1, I2C_CR1_DNF, DigitalFilter << I2C_CR1_DNF_Pos);
473 }
474
475 /**
476 * @brief Get the current Digital Noise Filter configuration.
477 * @rmtoll CR1 DNF LL_I2C_GetDigitalFilter
478 * @param I2Cx I2C Instance.
479 * @retval Value between Min_Data=0x0 and Max_Data=0xF
480 */
481 __STATIC_INLINE uint32_t LL_I2C_GetDigitalFilter(I2C_TypeDef *I2Cx)
482 {
483 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_DNF) >> I2C_CR1_DNF_Pos);
484 }
485
486 /**
487 * @brief Enable Analog Noise Filter.
488 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
489 * @rmtoll CR1 ANFOFF LL_I2C_EnableAnalogFilter
490 * @param I2Cx I2C Instance.
491 * @retval None
492 */
493 __STATIC_INLINE void LL_I2C_EnableAnalogFilter(I2C_TypeDef *I2Cx)
494 {
495 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
496 }
497
498 /**
499 * @brief Disable Analog Noise Filter.
500 * @note This filter can only be programmed when the I2C is disabled (PE = 0).
501 * @rmtoll CR1 ANFOFF LL_I2C_DisableAnalogFilter
502 * @param I2Cx I2C Instance.
503 * @retval None
504 */
505 __STATIC_INLINE void LL_I2C_DisableAnalogFilter(I2C_TypeDef *I2Cx)
506 {
507 SET_BIT(I2Cx->CR1, I2C_CR1_ANFOFF);
508 }
509
510 /**
511 * @brief Check if Analog Noise Filter is enabled or disabled.
512 * @rmtoll CR1 ANFOFF LL_I2C_IsEnabledAnalogFilter
513 * @param I2Cx I2C Instance.
514 * @retval State of bit (1 or 0).
515 */
516 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAnalogFilter(I2C_TypeDef *I2Cx)
517 {
518 return (READ_BIT(I2Cx->CR1, I2C_CR1_ANFOFF) != (I2C_CR1_ANFOFF));
519 }
520
521 /**
522 * @brief Enable DMA transmission requests.
523 * @rmtoll CR1 TXDMAEN LL_I2C_EnableDMAReq_TX
524 * @param I2Cx I2C Instance.
525 * @retval None
526 */
527 __STATIC_INLINE void LL_I2C_EnableDMAReq_TX(I2C_TypeDef *I2Cx)
528 {
529 SET_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
530 }
531
532 /**
533 * @brief Disable DMA transmission requests.
534 * @rmtoll CR1 TXDMAEN LL_I2C_DisableDMAReq_TX
535 * @param I2Cx I2C Instance.
536 * @retval None
537 */
538 __STATIC_INLINE void LL_I2C_DisableDMAReq_TX(I2C_TypeDef *I2Cx)
539 {
540 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN);
541 }
542
543 /**
544 * @brief Check if DMA transmission requests are enabled or disabled.
545 * @rmtoll CR1 TXDMAEN LL_I2C_IsEnabledDMAReq_TX
546 * @param I2Cx I2C Instance.
547 * @retval State of bit (1 or 0).
548 */
549 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_TX(I2C_TypeDef *I2Cx)
550 {
551 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXDMAEN) == (I2C_CR1_TXDMAEN));
552 }
553
554 /**
555 * @brief Enable DMA reception requests.
556 * @rmtoll CR1 RXDMAEN LL_I2C_EnableDMAReq_RX
557 * @param I2Cx I2C Instance.
558 * @retval None
559 */
560 __STATIC_INLINE void LL_I2C_EnableDMAReq_RX(I2C_TypeDef *I2Cx)
561 {
562 SET_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
563 }
564
565 /**
566 * @brief Disable DMA reception requests.
567 * @rmtoll CR1 RXDMAEN LL_I2C_DisableDMAReq_RX
568 * @param I2Cx I2C Instance.
569 * @retval None
570 */
571 __STATIC_INLINE void LL_I2C_DisableDMAReq_RX(I2C_TypeDef *I2Cx)
572 {
573 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN);
574 }
575
576 /**
577 * @brief Check if DMA reception requests are enabled or disabled.
578 * @rmtoll CR1 RXDMAEN LL_I2C_IsEnabledDMAReq_RX
579 * @param I2Cx I2C Instance.
580 * @retval State of bit (1 or 0).
581 */
582 __STATIC_INLINE uint32_t LL_I2C_IsEnabledDMAReq_RX(I2C_TypeDef *I2Cx)
583 {
584 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXDMAEN) == (I2C_CR1_RXDMAEN));
585 }
586
587 /**
588 * @brief Get the data register address used for DMA transfer
589 * @rmtoll TXDR TXDATA LL_I2C_DMA_GetRegAddr\n
590 * RXDR RXDATA LL_I2C_DMA_GetRegAddr
591 * @param I2Cx I2C Instance
592 * @param Direction This parameter can be one of the following values:
593 * @arg @ref LL_I2C_DMA_REG_DATA_TRANSMIT
594 * @arg @ref LL_I2C_DMA_REG_DATA_RECEIVE
595 * @retval Address of data register
596 */
597 __STATIC_INLINE uint32_t LL_I2C_DMA_GetRegAddr(I2C_TypeDef *I2Cx, uint32_t Direction)
598 {
599 register uint32_t data_reg_addr = 0U;
600
601 if (Direction == LL_I2C_DMA_REG_DATA_TRANSMIT)
602 {
603 /* return address of TXDR register */
604 data_reg_addr = (uint32_t) & (I2Cx->TXDR);
605 }
606 else
607 {
608 /* return address of RXDR register */
609 data_reg_addr = (uint32_t) & (I2Cx->RXDR);
610 }
611
612 return data_reg_addr;
613 }
614
615 /**
616 * @brief Enable Clock stretching.
617 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
618 * @rmtoll CR1 NOSTRETCH LL_I2C_EnableClockStretching
619 * @param I2Cx I2C Instance.
620 * @retval None
621 */
622 __STATIC_INLINE void LL_I2C_EnableClockStretching(I2C_TypeDef *I2Cx)
623 {
624 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
625 }
626
627 /**
628 * @brief Disable Clock stretching.
629 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
630 * @rmtoll CR1 NOSTRETCH LL_I2C_DisableClockStretching
631 * @param I2Cx I2C Instance.
632 * @retval None
633 */
634 __STATIC_INLINE void LL_I2C_DisableClockStretching(I2C_TypeDef *I2Cx)
635 {
636 SET_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH);
637 }
638
639 /**
640 * @brief Check if Clock stretching is enabled or disabled.
641 * @rmtoll CR1 NOSTRETCH LL_I2C_IsEnabledClockStretching
642 * @param I2Cx I2C Instance.
643 * @retval State of bit (1 or 0).
644 */
645 __STATIC_INLINE uint32_t LL_I2C_IsEnabledClockStretching(I2C_TypeDef *I2Cx)
646 {
647 return (READ_BIT(I2Cx->CR1, I2C_CR1_NOSTRETCH) != (I2C_CR1_NOSTRETCH));
648 }
649
650 /**
651 * @brief Enable hardware byte control in slave mode.
652 * @rmtoll CR1 SBC LL_I2C_EnableSlaveByteControl
653 * @param I2Cx I2C Instance.
654 * @retval None
655 */
656 __STATIC_INLINE void LL_I2C_EnableSlaveByteControl(I2C_TypeDef *I2Cx)
657 {
658 SET_BIT(I2Cx->CR1, I2C_CR1_SBC);
659 }
660
661 /**
662 * @brief Disable hardware byte control in slave mode.
663 * @rmtoll CR1 SBC LL_I2C_DisableSlaveByteControl
664 * @param I2Cx I2C Instance.
665 * @retval None
666 */
667 __STATIC_INLINE void LL_I2C_DisableSlaveByteControl(I2C_TypeDef *I2Cx)
668 {
669 CLEAR_BIT(I2Cx->CR1, I2C_CR1_SBC);
670 }
671
672 /**
673 * @brief Check if hardware byte control in slave mode is enabled or disabled.
674 * @rmtoll CR1 SBC LL_I2C_IsEnabledSlaveByteControl
675 * @param I2Cx I2C Instance.
676 * @retval State of bit (1 or 0).
677 */
678 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSlaveByteControl(I2C_TypeDef *I2Cx)
679 {
680 return (READ_BIT(I2Cx->CR1, I2C_CR1_SBC) == (I2C_CR1_SBC));
681 }
682
683
684 /**
685 * @brief Enable General Call.
686 * @note When enabled the Address 0x00 is ACKed.
687 * @rmtoll CR1 GCEN LL_I2C_EnableGeneralCall
688 * @param I2Cx I2C Instance.
689 * @retval None
690 */
691 __STATIC_INLINE void LL_I2C_EnableGeneralCall(I2C_TypeDef *I2Cx)
692 {
693 SET_BIT(I2Cx->CR1, I2C_CR1_GCEN);
694 }
695
696 /**
697 * @brief Disable General Call.
698 * @note When disabled the Address 0x00 is NACKed.
699 * @rmtoll CR1 GCEN LL_I2C_DisableGeneralCall
700 * @param I2Cx I2C Instance.
701 * @retval None
702 */
703 __STATIC_INLINE void LL_I2C_DisableGeneralCall(I2C_TypeDef *I2Cx)
704 {
705 CLEAR_BIT(I2Cx->CR1, I2C_CR1_GCEN);
706 }
707
708 /**
709 * @brief Check if General Call is enabled or disabled.
710 * @rmtoll CR1 GCEN LL_I2C_IsEnabledGeneralCall
711 * @param I2Cx I2C Instance.
712 * @retval State of bit (1 or 0).
713 */
714 __STATIC_INLINE uint32_t LL_I2C_IsEnabledGeneralCall(I2C_TypeDef *I2Cx)
715 {
716 return (READ_BIT(I2Cx->CR1, I2C_CR1_GCEN) == (I2C_CR1_GCEN));
717 }
718
719 /**
720 * @brief Configure the Master to operate in 7-bit or 10-bit addressing mode.
721 * @note Changing this bit is not allowed, when the START bit is set.
722 * @rmtoll CR2 ADD10 LL_I2C_SetMasterAddressingMode
723 * @param I2Cx I2C Instance.
724 * @param AddressingMode This parameter can be one of the following values:
725 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
726 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
727 * @retval None
728 */
729 __STATIC_INLINE void LL_I2C_SetMasterAddressingMode(I2C_TypeDef *I2Cx, uint32_t AddressingMode)
730 {
731 MODIFY_REG(I2Cx->CR2, I2C_CR2_ADD10, AddressingMode);
732 }
733
734 /**
735 * @brief Get the Master addressing mode.
736 * @rmtoll CR2 ADD10 LL_I2C_GetMasterAddressingMode
737 * @param I2Cx I2C Instance.
738 * @retval Returned value can be one of the following values:
739 * @arg @ref LL_I2C_ADDRESSING_MODE_7BIT
740 * @arg @ref LL_I2C_ADDRESSING_MODE_10BIT
741 */
742 __STATIC_INLINE uint32_t LL_I2C_GetMasterAddressingMode(I2C_TypeDef *I2Cx)
743 {
744 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_ADD10));
745 }
746
747 /**
748 * @brief Set the Own Address1.
749 * @rmtoll OAR1 OA1 LL_I2C_SetOwnAddress1\n
750 * OAR1 OA1MODE LL_I2C_SetOwnAddress1
751 * @param I2Cx I2C Instance.
752 * @param OwnAddress1 This parameter must be a value between Min_Data=0 and Max_Data=0x3FF.
753 * @param OwnAddrSize This parameter can be one of the following values:
754 * @arg @ref LL_I2C_OWNADDRESS1_7BIT
755 * @arg @ref LL_I2C_OWNADDRESS1_10BIT
756 * @retval None
757 */
758 __STATIC_INLINE void LL_I2C_SetOwnAddress1(I2C_TypeDef *I2Cx, uint32_t OwnAddress1, uint32_t OwnAddrSize)
759 {
760 MODIFY_REG(I2Cx->OAR1, I2C_OAR1_OA1 | I2C_OAR1_OA1MODE, OwnAddress1 | OwnAddrSize);
761 }
762
763 /**
764 * @brief Enable acknowledge on Own Address1 match address.
765 * @rmtoll OAR1 OA1EN LL_I2C_EnableOwnAddress1
766 * @param I2Cx I2C Instance.
767 * @retval None
768 */
769 __STATIC_INLINE void LL_I2C_EnableOwnAddress1(I2C_TypeDef *I2Cx)
770 {
771 SET_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
772 }
773
774 /**
775 * @brief Disable acknowledge on Own Address1 match address.
776 * @rmtoll OAR1 OA1EN LL_I2C_DisableOwnAddress1
777 * @param I2Cx I2C Instance.
778 * @retval None
779 */
780 __STATIC_INLINE void LL_I2C_DisableOwnAddress1(I2C_TypeDef *I2Cx)
781 {
782 CLEAR_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN);
783 }
784
785 /**
786 * @brief Check if Own Address1 acknowledge is enabled or disabled.
787 * @rmtoll OAR1 OA1EN LL_I2C_IsEnabledOwnAddress1
788 * @param I2Cx I2C Instance.
789 * @retval State of bit (1 or 0).
790 */
791 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress1(I2C_TypeDef *I2Cx)
792 {
793 return (READ_BIT(I2Cx->OAR1, I2C_OAR1_OA1EN) == (I2C_OAR1_OA1EN));
794 }
795
796 /**
797 * @brief Set the 7bits Own Address2.
798 * @note This action has no effect if own address2 is enabled.
799 * @rmtoll OAR2 OA2 LL_I2C_SetOwnAddress2\n
800 * OAR2 OA2MSK LL_I2C_SetOwnAddress2
801 * @param I2Cx I2C Instance.
802 * @param OwnAddress2 Value between Min_Data=0 and Max_Data=0x7F.
803 * @param OwnAddrMask This parameter can be one of the following values:
804 * @arg @ref LL_I2C_OWNADDRESS2_NOMASK
805 * @arg @ref LL_I2C_OWNADDRESS2_MASK01
806 * @arg @ref LL_I2C_OWNADDRESS2_MASK02
807 * @arg @ref LL_I2C_OWNADDRESS2_MASK03
808 * @arg @ref LL_I2C_OWNADDRESS2_MASK04
809 * @arg @ref LL_I2C_OWNADDRESS2_MASK05
810 * @arg @ref LL_I2C_OWNADDRESS2_MASK06
811 * @arg @ref LL_I2C_OWNADDRESS2_MASK07
812 * @retval None
813 */
814 __STATIC_INLINE void LL_I2C_SetOwnAddress2(I2C_TypeDef *I2Cx, uint32_t OwnAddress2, uint32_t OwnAddrMask)
815 {
816 MODIFY_REG(I2Cx->OAR2, I2C_OAR2_OA2 | I2C_OAR2_OA2MSK, OwnAddress2 | OwnAddrMask);
817 }
818
819 /**
820 * @brief Enable acknowledge on Own Address2 match address.
821 * @rmtoll OAR2 OA2EN LL_I2C_EnableOwnAddress2
822 * @param I2Cx I2C Instance.
823 * @retval None
824 */
825 __STATIC_INLINE void LL_I2C_EnableOwnAddress2(I2C_TypeDef *I2Cx)
826 {
827 SET_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
828 }
829
830 /**
831 * @brief Disable acknowledge on Own Address2 match address.
832 * @rmtoll OAR2 OA2EN LL_I2C_DisableOwnAddress2
833 * @param I2Cx I2C Instance.
834 * @retval None
835 */
836 __STATIC_INLINE void LL_I2C_DisableOwnAddress2(I2C_TypeDef *I2Cx)
837 {
838 CLEAR_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN);
839 }
840
841 /**
842 * @brief Check if Own Address1 acknowledge is enabled or disabled.
843 * @rmtoll OAR2 OA2EN LL_I2C_IsEnabledOwnAddress2
844 * @param I2Cx I2C Instance.
845 * @retval State of bit (1 or 0).
846 */
847 __STATIC_INLINE uint32_t LL_I2C_IsEnabledOwnAddress2(I2C_TypeDef *I2Cx)
848 {
849 return (READ_BIT(I2Cx->OAR2, I2C_OAR2_OA2EN) == (I2C_OAR2_OA2EN));
850 }
851
852 /**
853 * @brief Configure the SDA setup, hold time and the SCL high, low period.
854 * @note This bit can only be programmed when the I2C is disabled (PE = 0).
855 * @rmtoll TIMINGR TIMINGR LL_I2C_SetTiming
856 * @param I2Cx I2C Instance.
857 * @param Timing This parameter must be a value between Min_Data=0 and Max_Data=0xFFFFFFFF.
858 * @note This parameter is computed with the STM32CubeMX Tool.
859 * @retval None
860 */
861 __STATIC_INLINE void LL_I2C_SetTiming(I2C_TypeDef *I2Cx, uint32_t Timing)
862 {
863 WRITE_REG(I2Cx->TIMINGR, Timing);
864 }
865
866 /**
867 * @brief Get the Timing Prescaler setting.
868 * @rmtoll TIMINGR PRESC LL_I2C_GetTimingPrescaler
869 * @param I2Cx I2C Instance.
870 * @retval Value between Min_Data=0x0 and Max_Data=0xF
871 */
872 __STATIC_INLINE uint32_t LL_I2C_GetTimingPrescaler(I2C_TypeDef *I2Cx)
873 {
874 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_PRESC) >> I2C_TIMINGR_PRESC_Pos);
875 }
876
877 /**
878 * @brief Get the SCL low period setting.
879 * @rmtoll TIMINGR SCLL LL_I2C_GetClockLowPeriod
880 * @param I2Cx I2C Instance.
881 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
882 */
883 __STATIC_INLINE uint32_t LL_I2C_GetClockLowPeriod(I2C_TypeDef *I2Cx)
884 {
885 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLL) >> I2C_TIMINGR_SCLL_Pos);
886 }
887
888 /**
889 * @brief Get the SCL high period setting.
890 * @rmtoll TIMINGR SCLH LL_I2C_GetClockHighPeriod
891 * @param I2Cx I2C Instance.
892 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
893 */
894 __STATIC_INLINE uint32_t LL_I2C_GetClockHighPeriod(I2C_TypeDef *I2Cx)
895 {
896 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLH) >> I2C_TIMINGR_SCLH_Pos);
897 }
898
899 /**
900 * @brief Get the SDA hold time.
901 * @rmtoll TIMINGR SDADEL LL_I2C_GetDataHoldTime
902 * @param I2Cx I2C Instance.
903 * @retval Value between Min_Data=0x0 and Max_Data=0xF
904 */
905 __STATIC_INLINE uint32_t LL_I2C_GetDataHoldTime(I2C_TypeDef *I2Cx)
906 {
907 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SDADEL) >> I2C_TIMINGR_SDADEL_Pos);
908 }
909
910 /**
911 * @brief Get the SDA setup time.
912 * @rmtoll TIMINGR SCLDEL LL_I2C_GetDataSetupTime
913 * @param I2Cx I2C Instance.
914 * @retval Value between Min_Data=0x0 and Max_Data=0xF
915 */
916 __STATIC_INLINE uint32_t LL_I2C_GetDataSetupTime(I2C_TypeDef *I2Cx)
917 {
918 return (uint32_t)(READ_BIT(I2Cx->TIMINGR, I2C_TIMINGR_SCLDEL) >> I2C_TIMINGR_SCLDEL_Pos);
919 }
920
921 /**
922 * @brief Configure peripheral mode.
923 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
924 * SMBus feature is supported by the I2Cx Instance.
925 * @rmtoll CR1 SMBHEN LL_I2C_SetMode\n
926 * CR1 SMBDEN LL_I2C_SetMode
927 * @param I2Cx I2C Instance.
928 * @param PeripheralMode This parameter can be one of the following values:
929 * @arg @ref LL_I2C_MODE_I2C
930 * @arg @ref LL_I2C_MODE_SMBUS_HOST
931 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
932 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
933 * @retval None
934 */
935 __STATIC_INLINE void LL_I2C_SetMode(I2C_TypeDef *I2Cx, uint32_t PeripheralMode)
936 {
937 MODIFY_REG(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN, PeripheralMode);
938 }
939
940 /**
941 * @brief Get peripheral mode.
942 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
943 * SMBus feature is supported by the I2Cx Instance.
944 * @rmtoll CR1 SMBHEN LL_I2C_GetMode\n
945 * CR1 SMBDEN LL_I2C_GetMode
946 * @param I2Cx I2C Instance.
947 * @retval Returned value can be one of the following values:
948 * @arg @ref LL_I2C_MODE_I2C
949 * @arg @ref LL_I2C_MODE_SMBUS_HOST
950 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE
951 * @arg @ref LL_I2C_MODE_SMBUS_DEVICE_ARP
952 */
953 __STATIC_INLINE uint32_t LL_I2C_GetMode(I2C_TypeDef *I2Cx)
954 {
955 return (uint32_t)(READ_BIT(I2Cx->CR1, I2C_CR1_SMBHEN | I2C_CR1_SMBDEN));
956 }
957
958 /**
959 * @brief Enable SMBus alert (Host or Device mode)
960 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
961 * SMBus feature is supported by the I2Cx Instance.
962 * @note SMBus Device mode:
963 * - SMBus Alert pin is drived low and
964 * Alert Response Address Header acknowledge is enabled.
965 * SMBus Host mode:
966 * - SMBus Alert pin management is supported.
967 * @rmtoll CR1 ALERTEN LL_I2C_EnableSMBusAlert
968 * @param I2Cx I2C Instance.
969 * @retval None
970 */
971 __STATIC_INLINE void LL_I2C_EnableSMBusAlert(I2C_TypeDef *I2Cx)
972 {
973 SET_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
974 }
975
976 /**
977 * @brief Disable SMBus alert (Host or Device mode)
978 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
979 * SMBus feature is supported by the I2Cx Instance.
980 * @note SMBus Device mode:
981 * - SMBus Alert pin is not drived (can be used as a standard GPIO) and
982 * Alert Response Address Header acknowledge is disabled.
983 * SMBus Host mode:
984 * - SMBus Alert pin management is not supported.
985 * @rmtoll CR1 ALERTEN LL_I2C_DisableSMBusAlert
986 * @param I2Cx I2C Instance.
987 * @retval None
988 */
989 __STATIC_INLINE void LL_I2C_DisableSMBusAlert(I2C_TypeDef *I2Cx)
990 {
991 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ALERTEN);
992 }
993
994 /**
995 * @brief Check if SMBus alert (Host or Device mode) is enabled or disabled.
996 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
997 * SMBus feature is supported by the I2Cx Instance.
998 * @rmtoll CR1 ALERTEN LL_I2C_IsEnabledSMBusAlert
999 * @param I2Cx I2C Instance.
1000 * @retval State of bit (1 or 0).
1001 */
1002 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusAlert(I2C_TypeDef *I2Cx)
1003 {
1004 return (READ_BIT(I2Cx->CR1, I2C_CR1_ALERTEN) == (I2C_CR1_ALERTEN));
1005 }
1006
1007 /**
1008 * @brief Enable SMBus Packet Error Calculation (PEC).
1009 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1010 * SMBus feature is supported by the I2Cx Instance.
1011 * @rmtoll CR1 PECEN LL_I2C_EnableSMBusPEC
1012 * @param I2Cx I2C Instance.
1013 * @retval None
1014 */
1015 __STATIC_INLINE void LL_I2C_EnableSMBusPEC(I2C_TypeDef *I2Cx)
1016 {
1017 SET_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1018 }
1019
1020 /**
1021 * @brief Disable SMBus Packet Error Calculation (PEC).
1022 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1023 * SMBus feature is supported by the I2Cx Instance.
1024 * @rmtoll CR1 PECEN LL_I2C_DisableSMBusPEC
1025 * @param I2Cx I2C Instance.
1026 * @retval None
1027 */
1028 __STATIC_INLINE void LL_I2C_DisableSMBusPEC(I2C_TypeDef *I2Cx)
1029 {
1030 CLEAR_BIT(I2Cx->CR1, I2C_CR1_PECEN);
1031 }
1032
1033 /**
1034 * @brief Check if SMBus Packet Error Calculation (PEC) is enabled or disabled.
1035 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1036 * SMBus feature is supported by the I2Cx Instance.
1037 * @rmtoll CR1 PECEN LL_I2C_IsEnabledSMBusPEC
1038 * @param I2Cx I2C Instance.
1039 * @retval State of bit (1 or 0).
1040 */
1041 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPEC(I2C_TypeDef *I2Cx)
1042 {
1043 return (READ_BIT(I2Cx->CR1, I2C_CR1_PECEN) == (I2C_CR1_PECEN));
1044 }
1045
1046 /**
1047 * @brief Configure the SMBus Clock Timeout.
1048 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1049 * SMBus feature is supported by the I2Cx Instance.
1050 * @note This configuration can only be programmed when associated Timeout is disabled (TimeoutA and/orTimeoutB).
1051 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_ConfigSMBusTimeout\n
1052 * TIMEOUTR TIDLE LL_I2C_ConfigSMBusTimeout\n
1053 * TIMEOUTR TIMEOUTB LL_I2C_ConfigSMBusTimeout
1054 * @param I2Cx I2C Instance.
1055 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1056 * @param TimeoutAMode This parameter can be one of the following values:
1057 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1058 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1059 * @param TimeoutB
1060 * @retval None
1061 */
1062 __STATIC_INLINE void LL_I2C_ConfigSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t TimeoutA, uint32_t TimeoutAMode,
1063 uint32_t TimeoutB)
1064 {
1065 MODIFY_REG(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA | I2C_TIMEOUTR_TIDLE | I2C_TIMEOUTR_TIMEOUTB,
1066 TimeoutA | TimeoutAMode | (TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos));
1067 }
1068
1069 /**
1070 * @brief Configure the SMBus Clock TimeoutA (SCL low timeout or SCL and SDA high timeout depends on TimeoutA mode).
1071 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1072 * SMBus feature is supported by the I2Cx Instance.
1073 * @note These bits can only be programmed when TimeoutA is disabled.
1074 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_SetSMBusTimeoutA
1075 * @param I2Cx I2C Instance.
1076 * @param TimeoutA This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1077 * @retval None
1078 */
1079 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutA(I2C_TypeDef *I2Cx, uint32_t TimeoutA)
1080 {
1081 WRITE_REG(I2Cx->TIMEOUTR, TimeoutA);
1082 }
1083
1084 /**
1085 * @brief Get the SMBus Clock TimeoutA setting.
1086 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1087 * SMBus feature is supported by the I2Cx Instance.
1088 * @rmtoll TIMEOUTR TIMEOUTA LL_I2C_GetSMBusTimeoutA
1089 * @param I2Cx I2C Instance.
1090 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1091 */
1092 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutA(I2C_TypeDef *I2Cx)
1093 {
1094 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTA));
1095 }
1096
1097 /**
1098 * @brief Set the SMBus Clock TimeoutA mode.
1099 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1100 * SMBus feature is supported by the I2Cx Instance.
1101 * @note This bit can only be programmed when TimeoutA is disabled.
1102 * @rmtoll TIMEOUTR TIDLE LL_I2C_SetSMBusTimeoutAMode
1103 * @param I2Cx I2C Instance.
1104 * @param TimeoutAMode This parameter can be one of the following values:
1105 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1106 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1107 * @retval None
1108 */
1109 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutAMode(I2C_TypeDef *I2Cx, uint32_t TimeoutAMode)
1110 {
1111 WRITE_REG(I2Cx->TIMEOUTR, TimeoutAMode);
1112 }
1113
1114 /**
1115 * @brief Get the SMBus Clock TimeoutA mode.
1116 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1117 * SMBus feature is supported by the I2Cx Instance.
1118 * @rmtoll TIMEOUTR TIDLE LL_I2C_GetSMBusTimeoutAMode
1119 * @param I2Cx I2C Instance.
1120 * @retval Returned value can be one of the following values:
1121 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SCL_LOW
1122 * @arg @ref LL_I2C_SMBUS_TIMEOUTA_MODE_SDA_SCL_HIGH
1123 */
1124 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutAMode(I2C_TypeDef *I2Cx)
1125 {
1126 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIDLE));
1127 }
1128
1129 /**
1130 * @brief Configure the SMBus Extended Cumulative Clock TimeoutB (Master or Slave mode).
1131 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1132 * SMBus feature is supported by the I2Cx Instance.
1133 * @note These bits can only be programmed when TimeoutB is disabled.
1134 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_SetSMBusTimeoutB
1135 * @param I2Cx I2C Instance.
1136 * @param TimeoutB This parameter must be a value between Min_Data=0 and Max_Data=0xFFF.
1137 * @retval None
1138 */
1139 __STATIC_INLINE void LL_I2C_SetSMBusTimeoutB(I2C_TypeDef *I2Cx, uint32_t TimeoutB)
1140 {
1141 WRITE_REG(I2Cx->TIMEOUTR, TimeoutB << I2C_TIMEOUTR_TIMEOUTB_Pos);
1142 }
1143
1144 /**
1145 * @brief Get the SMBus Extented Cumulative Clock TimeoutB setting.
1146 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1147 * SMBus feature is supported by the I2Cx Instance.
1148 * @rmtoll TIMEOUTR TIMEOUTB LL_I2C_GetSMBusTimeoutB
1149 * @param I2Cx I2C Instance.
1150 * @retval Value between Min_Data=0 and Max_Data=0xFFF
1151 */
1152 __STATIC_INLINE uint32_t LL_I2C_GetSMBusTimeoutB(I2C_TypeDef *I2Cx)
1153 {
1154 return (uint32_t)(READ_BIT(I2Cx->TIMEOUTR, I2C_TIMEOUTR_TIMEOUTB) >> I2C_TIMEOUTR_TIMEOUTB_Pos);
1155 }
1156
1157 /**
1158 * @brief Enable the SMBus Clock Timeout.
1159 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1160 * SMBus feature is supported by the I2Cx Instance.
1161 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_EnableSMBusTimeout\n
1162 * TIMEOUTR TEXTEN LL_I2C_EnableSMBusTimeout
1163 * @param I2Cx I2C Instance.
1164 * @param ClockTimeout This parameter can be one of the following values:
1165 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1166 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1167 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1168 * @retval None
1169 */
1170 __STATIC_INLINE void LL_I2C_EnableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1171 {
1172 SET_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1173 }
1174
1175 /**
1176 * @brief Disable the SMBus Clock Timeout.
1177 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1178 * SMBus feature is supported by the I2Cx Instance.
1179 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_DisableSMBusTimeout\n
1180 * TIMEOUTR TEXTEN LL_I2C_DisableSMBusTimeout
1181 * @param I2Cx I2C Instance.
1182 * @param ClockTimeout This parameter can be one of the following values:
1183 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1184 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1185 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1186 * @retval None
1187 */
1188 __STATIC_INLINE void LL_I2C_DisableSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1189 {
1190 CLEAR_BIT(I2Cx->TIMEOUTR, ClockTimeout);
1191 }
1192
1193 /**
1194 * @brief Check if the SMBus Clock Timeout is enabled or disabled.
1195 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1196 * SMBus feature is supported by the I2Cx Instance.
1197 * @rmtoll TIMEOUTR TIMOUTEN LL_I2C_IsEnabledSMBusTimeout\n
1198 * TIMEOUTR TEXTEN LL_I2C_IsEnabledSMBusTimeout
1199 * @param I2Cx I2C Instance.
1200 * @param ClockTimeout This parameter can be one of the following values:
1201 * @arg @ref LL_I2C_SMBUS_TIMEOUTA
1202 * @arg @ref LL_I2C_SMBUS_TIMEOUTB
1203 * @arg @ref LL_I2C_SMBUS_ALL_TIMEOUT
1204 * @retval State of bit (1 or 0).
1205 */
1206 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusTimeout(I2C_TypeDef *I2Cx, uint32_t ClockTimeout)
1207 {
1208 return (READ_BIT(I2Cx->TIMEOUTR, (I2C_TIMEOUTR_TIMOUTEN | I2C_TIMEOUTR_TEXTEN)) == (ClockTimeout));
1209 }
1210
1211 /**
1212 * @}
1213 */
1214
1215 /** @defgroup I2C_LL_EF_IT_Management IT_Management
1216 * @{
1217 */
1218
1219 /**
1220 * @brief Enable TXIS interrupt.
1221 * @rmtoll CR1 TXIE LL_I2C_EnableIT_TX
1222 * @param I2Cx I2C Instance.
1223 * @retval None
1224 */
1225 __STATIC_INLINE void LL_I2C_EnableIT_TX(I2C_TypeDef *I2Cx)
1226 {
1227 SET_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1228 }
1229
1230 /**
1231 * @brief Disable TXIS interrupt.
1232 * @rmtoll CR1 TXIE LL_I2C_DisableIT_TX
1233 * @param I2Cx I2C Instance.
1234 * @retval None
1235 */
1236 __STATIC_INLINE void LL_I2C_DisableIT_TX(I2C_TypeDef *I2Cx)
1237 {
1238 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TXIE);
1239 }
1240
1241 /**
1242 * @brief Check if the TXIS Interrupt is enabled or disabled.
1243 * @rmtoll CR1 TXIE LL_I2C_IsEnabledIT_TX
1244 * @param I2Cx I2C Instance.
1245 * @retval State of bit (1 or 0).
1246 */
1247 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TX(I2C_TypeDef *I2Cx)
1248 {
1249 return (READ_BIT(I2Cx->CR1, I2C_CR1_TXIE) == (I2C_CR1_TXIE));
1250 }
1251
1252 /**
1253 * @brief Enable RXNE interrupt.
1254 * @rmtoll CR1 RXIE LL_I2C_EnableIT_RX
1255 * @param I2Cx I2C Instance.
1256 * @retval None
1257 */
1258 __STATIC_INLINE void LL_I2C_EnableIT_RX(I2C_TypeDef *I2Cx)
1259 {
1260 SET_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1261 }
1262
1263 /**
1264 * @brief Disable RXNE interrupt.
1265 * @rmtoll CR1 RXIE LL_I2C_DisableIT_RX
1266 * @param I2Cx I2C Instance.
1267 * @retval None
1268 */
1269 __STATIC_INLINE void LL_I2C_DisableIT_RX(I2C_TypeDef *I2Cx)
1270 {
1271 CLEAR_BIT(I2Cx->CR1, I2C_CR1_RXIE);
1272 }
1273
1274 /**
1275 * @brief Check if the RXNE Interrupt is enabled or disabled.
1276 * @rmtoll CR1 RXIE LL_I2C_IsEnabledIT_RX
1277 * @param I2Cx I2C Instance.
1278 * @retval State of bit (1 or 0).
1279 */
1280 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_RX(I2C_TypeDef *I2Cx)
1281 {
1282 return (READ_BIT(I2Cx->CR1, I2C_CR1_RXIE) == (I2C_CR1_RXIE));
1283 }
1284
1285 /**
1286 * @brief Enable Address match interrupt (slave mode only).
1287 * @rmtoll CR1 ADDRIE LL_I2C_EnableIT_ADDR
1288 * @param I2Cx I2C Instance.
1289 * @retval None
1290 */
1291 __STATIC_INLINE void LL_I2C_EnableIT_ADDR(I2C_TypeDef *I2Cx)
1292 {
1293 SET_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1294 }
1295
1296 /**
1297 * @brief Disable Address match interrupt (slave mode only).
1298 * @rmtoll CR1 ADDRIE LL_I2C_DisableIT_ADDR
1299 * @param I2Cx I2C Instance.
1300 * @retval None
1301 */
1302 __STATIC_INLINE void LL_I2C_DisableIT_ADDR(I2C_TypeDef *I2Cx)
1303 {
1304 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ADDRIE);
1305 }
1306
1307 /**
1308 * @brief Check if Address match interrupt is enabled or disabled.
1309 * @rmtoll CR1 ADDRIE LL_I2C_IsEnabledIT_ADDR
1310 * @param I2Cx I2C Instance.
1311 * @retval State of bit (1 or 0).
1312 */
1313 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ADDR(I2C_TypeDef *I2Cx)
1314 {
1315 return (READ_BIT(I2Cx->CR1, I2C_CR1_ADDRIE) == (I2C_CR1_ADDRIE));
1316 }
1317
1318 /**
1319 * @brief Enable Not acknowledge received interrupt.
1320 * @rmtoll CR1 NACKIE LL_I2C_EnableIT_NACK
1321 * @param I2Cx I2C Instance.
1322 * @retval None
1323 */
1324 __STATIC_INLINE void LL_I2C_EnableIT_NACK(I2C_TypeDef *I2Cx)
1325 {
1326 SET_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1327 }
1328
1329 /**
1330 * @brief Disable Not acknowledge received interrupt.
1331 * @rmtoll CR1 NACKIE LL_I2C_DisableIT_NACK
1332 * @param I2Cx I2C Instance.
1333 * @retval None
1334 */
1335 __STATIC_INLINE void LL_I2C_DisableIT_NACK(I2C_TypeDef *I2Cx)
1336 {
1337 CLEAR_BIT(I2Cx->CR1, I2C_CR1_NACKIE);
1338 }
1339
1340 /**
1341 * @brief Check if Not acknowledge received interrupt is enabled or disabled.
1342 * @rmtoll CR1 NACKIE LL_I2C_IsEnabledIT_NACK
1343 * @param I2Cx I2C Instance.
1344 * @retval State of bit (1 or 0).
1345 */
1346 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_NACK(I2C_TypeDef *I2Cx)
1347 {
1348 return (READ_BIT(I2Cx->CR1, I2C_CR1_NACKIE) == (I2C_CR1_NACKIE));
1349 }
1350
1351 /**
1352 * @brief Enable STOP detection interrupt.
1353 * @rmtoll CR1 STOPIE LL_I2C_EnableIT_STOP
1354 * @param I2Cx I2C Instance.
1355 * @retval None
1356 */
1357 __STATIC_INLINE void LL_I2C_EnableIT_STOP(I2C_TypeDef *I2Cx)
1358 {
1359 SET_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1360 }
1361
1362 /**
1363 * @brief Disable STOP detection interrupt.
1364 * @rmtoll CR1 STOPIE LL_I2C_DisableIT_STOP
1365 * @param I2Cx I2C Instance.
1366 * @retval None
1367 */
1368 __STATIC_INLINE void LL_I2C_DisableIT_STOP(I2C_TypeDef *I2Cx)
1369 {
1370 CLEAR_BIT(I2Cx->CR1, I2C_CR1_STOPIE);
1371 }
1372
1373 /**
1374 * @brief Check if STOP detection interrupt is enabled or disabled.
1375 * @rmtoll CR1 STOPIE LL_I2C_IsEnabledIT_STOP
1376 * @param I2Cx I2C Instance.
1377 * @retval State of bit (1 or 0).
1378 */
1379 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_STOP(I2C_TypeDef *I2Cx)
1380 {
1381 return (READ_BIT(I2Cx->CR1, I2C_CR1_STOPIE) == (I2C_CR1_STOPIE));
1382 }
1383
1384 /**
1385 * @brief Enable Transfer Complete interrupt.
1386 * @note Any of these events will generate interrupt :
1387 * Transfer Complete (TC)
1388 * Transfer Complete Reload (TCR)
1389 * @rmtoll CR1 TCIE LL_I2C_EnableIT_TC
1390 * @param I2Cx I2C Instance.
1391 * @retval None
1392 */
1393 __STATIC_INLINE void LL_I2C_EnableIT_TC(I2C_TypeDef *I2Cx)
1394 {
1395 SET_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1396 }
1397
1398 /**
1399 * @brief Disable Transfer Complete interrupt.
1400 * @note Any of these events will generate interrupt :
1401 * Transfer Complete (TC)
1402 * Transfer Complete Reload (TCR)
1403 * @rmtoll CR1 TCIE LL_I2C_DisableIT_TC
1404 * @param I2Cx I2C Instance.
1405 * @retval None
1406 */
1407 __STATIC_INLINE void LL_I2C_DisableIT_TC(I2C_TypeDef *I2Cx)
1408 {
1409 CLEAR_BIT(I2Cx->CR1, I2C_CR1_TCIE);
1410 }
1411
1412 /**
1413 * @brief Check if Transfer Complete interrupt is enabled or disabled.
1414 * @rmtoll CR1 TCIE LL_I2C_IsEnabledIT_TC
1415 * @param I2Cx I2C Instance.
1416 * @retval State of bit (1 or 0).
1417 */
1418 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_TC(I2C_TypeDef *I2Cx)
1419 {
1420 return (READ_BIT(I2Cx->CR1, I2C_CR1_TCIE) == (I2C_CR1_TCIE));
1421 }
1422
1423 /**
1424 * @brief Enable Error interrupts.
1425 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1426 * SMBus feature is supported by the I2Cx Instance.
1427 * @note Any of these errors will generate interrupt :
1428 * Arbitration Loss (ARLO)
1429 * Bus Error detection (BERR)
1430 * Overrun/Underrun (OVR)
1431 * SMBus Timeout detection (TIMEOUT)
1432 * SMBus PEC error detection (PECERR)
1433 * SMBus Alert pin event detection (ALERT)
1434 * @rmtoll CR1 ERRIE LL_I2C_EnableIT_ERR
1435 * @param I2Cx I2C Instance.
1436 * @retval None
1437 */
1438 __STATIC_INLINE void LL_I2C_EnableIT_ERR(I2C_TypeDef *I2Cx)
1439 {
1440 SET_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1441 }
1442
1443 /**
1444 * @brief Disable Error interrupts.
1445 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1446 * SMBus feature is supported by the I2Cx Instance.
1447 * @note Any of these errors will generate interrupt :
1448 * Arbitration Loss (ARLO)
1449 * Bus Error detection (BERR)
1450 * Overrun/Underrun (OVR)
1451 * SMBus Timeout detection (TIMEOUT)
1452 * SMBus PEC error detection (PECERR)
1453 * SMBus Alert pin event detection (ALERT)
1454 * @rmtoll CR1 ERRIE LL_I2C_DisableIT_ERR
1455 * @param I2Cx I2C Instance.
1456 * @retval None
1457 */
1458 __STATIC_INLINE void LL_I2C_DisableIT_ERR(I2C_TypeDef *I2Cx)
1459 {
1460 CLEAR_BIT(I2Cx->CR1, I2C_CR1_ERRIE);
1461 }
1462
1463 /**
1464 * @brief Check if Error interrupts are enabled or disabled.
1465 * @rmtoll CR1 ERRIE LL_I2C_IsEnabledIT_ERR
1466 * @param I2Cx I2C Instance.
1467 * @retval State of bit (1 or 0).
1468 */
1469 __STATIC_INLINE uint32_t LL_I2C_IsEnabledIT_ERR(I2C_TypeDef *I2Cx)
1470 {
1471 return (READ_BIT(I2Cx->CR1, I2C_CR1_ERRIE) == (I2C_CR1_ERRIE));
1472 }
1473
1474 /**
1475 * @}
1476 */
1477
1478 /** @defgroup I2C_LL_EF_FLAG_management FLAG_management
1479 * @{
1480 */
1481
1482 /**
1483 * @brief Indicate the status of Transmit data register empty flag.
1484 * @note RESET: When next data is written in Transmit data register.
1485 * SET: When Transmit data register is empty.
1486 * @rmtoll ISR TXE LL_I2C_IsActiveFlag_TXE
1487 * @param I2Cx I2C Instance.
1488 * @retval State of bit (1 or 0).
1489 */
1490 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXE(I2C_TypeDef *I2Cx)
1491 {
1492 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXE) == (I2C_ISR_TXE));
1493 }
1494
1495 /**
1496 * @brief Indicate the status of Transmit interrupt flag.
1497 * @note RESET: When next data is written in Transmit data register.
1498 * SET: When Transmit data register is empty.
1499 * @rmtoll ISR TXIS LL_I2C_IsActiveFlag_TXIS
1500 * @param I2Cx I2C Instance.
1501 * @retval State of bit (1 or 0).
1502 */
1503 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TXIS(I2C_TypeDef *I2Cx)
1504 {
1505 return (READ_BIT(I2Cx->ISR, I2C_ISR_TXIS) == (I2C_ISR_TXIS));
1506 }
1507
1508 /**
1509 * @brief Indicate the status of Receive data register not empty flag.
1510 * @note RESET: When Receive data register is read.
1511 * SET: When the received data is copied in Receive data register.
1512 * @rmtoll ISR RXNE LL_I2C_IsActiveFlag_RXNE
1513 * @param I2Cx I2C Instance.
1514 * @retval State of bit (1 or 0).
1515 */
1516 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_RXNE(I2C_TypeDef *I2Cx)
1517 {
1518 return (READ_BIT(I2Cx->ISR, I2C_ISR_RXNE) == (I2C_ISR_RXNE));
1519 }
1520
1521 /**
1522 * @brief Indicate the status of Address matched flag (slave mode).
1523 * @note RESET: Clear default value.
1524 * SET: When the received slave address matched with one of the enabled slave address.
1525 * @rmtoll ISR ADDR LL_I2C_IsActiveFlag_ADDR
1526 * @param I2Cx I2C Instance.
1527 * @retval State of bit (1 or 0).
1528 */
1529 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ADDR(I2C_TypeDef *I2Cx)
1530 {
1531 return (READ_BIT(I2Cx->ISR, I2C_ISR_ADDR) == (I2C_ISR_ADDR));
1532 }
1533
1534 /**
1535 * @brief Indicate the status of Not Acknowledge received flag.
1536 * @note RESET: Clear default value.
1537 * SET: When a NACK is received after a byte transmission.
1538 * @rmtoll ISR NACKF LL_I2C_IsActiveFlag_NACK
1539 * @param I2Cx I2C Instance.
1540 * @retval State of bit (1 or 0).
1541 */
1542 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_NACK(I2C_TypeDef *I2Cx)
1543 {
1544 return (READ_BIT(I2Cx->ISR, I2C_ISR_NACKF) == (I2C_ISR_NACKF));
1545 }
1546
1547 /**
1548 * @brief Indicate the status of Stop detection flag.
1549 * @note RESET: Clear default value.
1550 * SET: When a Stop condition is detected.
1551 * @rmtoll ISR STOPF LL_I2C_IsActiveFlag_STOP
1552 * @param I2Cx I2C Instance.
1553 * @retval State of bit (1 or 0).
1554 */
1555 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_STOP(I2C_TypeDef *I2Cx)
1556 {
1557 return (READ_BIT(I2Cx->ISR, I2C_ISR_STOPF) == (I2C_ISR_STOPF));
1558 }
1559
1560 /**
1561 * @brief Indicate the status of Transfer complete flag (master mode).
1562 * @note RESET: Clear default value.
1563 * SET: When RELOAD=0, AUTOEND=0 and NBYTES date have been transferred.
1564 * @rmtoll ISR TC LL_I2C_IsActiveFlag_TC
1565 * @param I2Cx I2C Instance.
1566 * @retval State of bit (1 or 0).
1567 */
1568 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TC(I2C_TypeDef *I2Cx)
1569 {
1570 return (READ_BIT(I2Cx->ISR, I2C_ISR_TC) == (I2C_ISR_TC));
1571 }
1572
1573 /**
1574 * @brief Indicate the status of Transfer complete flag (master mode).
1575 * @note RESET: Clear default value.
1576 * SET: When RELOAD=1 and NBYTES date have been transferred.
1577 * @rmtoll ISR TCR LL_I2C_IsActiveFlag_TCR
1578 * @param I2Cx I2C Instance.
1579 * @retval State of bit (1 or 0).
1580 */
1581 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_TCR(I2C_TypeDef *I2Cx)
1582 {
1583 return (READ_BIT(I2Cx->ISR, I2C_ISR_TCR) == (I2C_ISR_TCR));
1584 }
1585
1586 /**
1587 * @brief Indicate the status of Bus error flag.
1588 * @note RESET: Clear default value.
1589 * SET: When a misplaced Start or Stop condition is detected.
1590 * @rmtoll ISR BERR LL_I2C_IsActiveFlag_BERR
1591 * @param I2Cx I2C Instance.
1592 * @retval State of bit (1 or 0).
1593 */
1594 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BERR(I2C_TypeDef *I2Cx)
1595 {
1596 return (READ_BIT(I2Cx->ISR, I2C_ISR_BERR) == (I2C_ISR_BERR));
1597 }
1598
1599 /**
1600 * @brief Indicate the status of Arbitration lost flag.
1601 * @note RESET: Clear default value.
1602 * SET: When arbitration lost.
1603 * @rmtoll ISR ARLO LL_I2C_IsActiveFlag_ARLO
1604 * @param I2Cx I2C Instance.
1605 * @retval State of bit (1 or 0).
1606 */
1607 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_ARLO(I2C_TypeDef *I2Cx)
1608 {
1609 return (READ_BIT(I2Cx->ISR, I2C_ISR_ARLO) == (I2C_ISR_ARLO));
1610 }
1611
1612 /**
1613 * @brief Indicate the status of Overrun/Underrun flag (slave mode).
1614 * @note RESET: Clear default value.
1615 * SET: When an overrun/underrun error occurs (Clock Stretching Disabled).
1616 * @rmtoll ISR OVR LL_I2C_IsActiveFlag_OVR
1617 * @param I2Cx I2C Instance.
1618 * @retval State of bit (1 or 0).
1619 */
1620 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_OVR(I2C_TypeDef *I2Cx)
1621 {
1622 return (READ_BIT(I2Cx->ISR, I2C_ISR_OVR) == (I2C_ISR_OVR));
1623 }
1624
1625 /**
1626 * @brief Indicate the status of SMBus PEC error flag in reception.
1627 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1628 * SMBus feature is supported by the I2Cx Instance.
1629 * @note RESET: Clear default value.
1630 * SET: When the received PEC does not match with the PEC register content.
1631 * @rmtoll ISR PECERR LL_I2C_IsActiveSMBusFlag_PECERR
1632 * @param I2Cx I2C Instance.
1633 * @retval State of bit (1 or 0).
1634 */
1635 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1636 {
1637 return (READ_BIT(I2Cx->ISR, I2C_ISR_PECERR) == (I2C_ISR_PECERR));
1638 }
1639
1640 /**
1641 * @brief Indicate the status of SMBus Timeout detection flag.
1642 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1643 * SMBus feature is supported by the I2Cx Instance.
1644 * @note RESET: Clear default value.
1645 * SET: When a timeout or extended clock timeout occurs.
1646 * @rmtoll ISR TIMEOUT LL_I2C_IsActiveSMBusFlag_TIMEOUT
1647 * @param I2Cx I2C Instance.
1648 * @retval State of bit (1 or 0).
1649 */
1650 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1651 {
1652 return (READ_BIT(I2Cx->ISR, I2C_ISR_TIMEOUT) == (I2C_ISR_TIMEOUT));
1653 }
1654
1655 /**
1656 * @brief Indicate the status of SMBus alert flag.
1657 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1658 * SMBus feature is supported by the I2Cx Instance.
1659 * @note RESET: Clear default value.
1660 * SET: When SMBus host configuration, SMBus alert enabled and
1661 * a falling edge event occurs on SMBA pin.
1662 * @rmtoll ISR ALERT LL_I2C_IsActiveSMBusFlag_ALERT
1663 * @param I2Cx I2C Instance.
1664 * @retval State of bit (1 or 0).
1665 */
1666 __STATIC_INLINE uint32_t LL_I2C_IsActiveSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1667 {
1668 return (READ_BIT(I2Cx->ISR, I2C_ISR_ALERT) == (I2C_ISR_ALERT));
1669 }
1670
1671 /**
1672 * @brief Indicate the status of Bus Busy flag.
1673 * @note RESET: Clear default value.
1674 * SET: When a Start condition is detected.
1675 * @rmtoll ISR BUSY LL_I2C_IsActiveFlag_BUSY
1676 * @param I2Cx I2C Instance.
1677 * @retval State of bit (1 or 0).
1678 */
1679 __STATIC_INLINE uint32_t LL_I2C_IsActiveFlag_BUSY(I2C_TypeDef *I2Cx)
1680 {
1681 return (READ_BIT(I2Cx->ISR, I2C_ISR_BUSY) == (I2C_ISR_BUSY));
1682 }
1683
1684 /**
1685 * @brief Clear Address Matched flag.
1686 * @rmtoll ICR ADDRCF LL_I2C_ClearFlag_ADDR
1687 * @param I2Cx I2C Instance.
1688 * @retval None
1689 */
1690 __STATIC_INLINE void LL_I2C_ClearFlag_ADDR(I2C_TypeDef *I2Cx)
1691 {
1692 SET_BIT(I2Cx->ICR, I2C_ICR_ADDRCF);
1693 }
1694
1695 /**
1696 * @brief Clear Not Acknowledge flag.
1697 * @rmtoll ICR NACKCF LL_I2C_ClearFlag_NACK
1698 * @param I2Cx I2C Instance.
1699 * @retval None
1700 */
1701 __STATIC_INLINE void LL_I2C_ClearFlag_NACK(I2C_TypeDef *I2Cx)
1702 {
1703 SET_BIT(I2Cx->ICR, I2C_ICR_NACKCF);
1704 }
1705
1706 /**
1707 * @brief Clear Stop detection flag.
1708 * @rmtoll ICR STOPCF LL_I2C_ClearFlag_STOP
1709 * @param I2Cx I2C Instance.
1710 * @retval None
1711 */
1712 __STATIC_INLINE void LL_I2C_ClearFlag_STOP(I2C_TypeDef *I2Cx)
1713 {
1714 SET_BIT(I2Cx->ICR, I2C_ICR_STOPCF);
1715 }
1716
1717 /**
1718 * @brief Clear Transmit data register empty flag (TXE).
1719 * @note This bit can be clear by software in order to flush the transmit data register (TXDR).
1720 * @rmtoll ISR TXE LL_I2C_ClearFlag_TXE
1721 * @param I2Cx I2C Instance.
1722 * @retval None
1723 */
1724 __STATIC_INLINE void LL_I2C_ClearFlag_TXE(I2C_TypeDef *I2Cx)
1725 {
1726 WRITE_REG(I2Cx->ISR, I2C_ISR_TXE);
1727 }
1728
1729 /**
1730 * @brief Clear Bus error flag.
1731 * @rmtoll ICR BERRCF LL_I2C_ClearFlag_BERR
1732 * @param I2Cx I2C Instance.
1733 * @retval None
1734 */
1735 __STATIC_INLINE void LL_I2C_ClearFlag_BERR(I2C_TypeDef *I2Cx)
1736 {
1737 SET_BIT(I2Cx->ICR, I2C_ICR_BERRCF);
1738 }
1739
1740 /**
1741 * @brief Clear Arbitration lost flag.
1742 * @rmtoll ICR ARLOCF LL_I2C_ClearFlag_ARLO
1743 * @param I2Cx I2C Instance.
1744 * @retval None
1745 */
1746 __STATIC_INLINE void LL_I2C_ClearFlag_ARLO(I2C_TypeDef *I2Cx)
1747 {
1748 SET_BIT(I2Cx->ICR, I2C_ICR_ARLOCF);
1749 }
1750
1751 /**
1752 * @brief Clear Overrun/Underrun flag.
1753 * @rmtoll ICR OVRCF LL_I2C_ClearFlag_OVR
1754 * @param I2Cx I2C Instance.
1755 * @retval None
1756 */
1757 __STATIC_INLINE void LL_I2C_ClearFlag_OVR(I2C_TypeDef *I2Cx)
1758 {
1759 SET_BIT(I2Cx->ICR, I2C_ICR_OVRCF);
1760 }
1761
1762 /**
1763 * @brief Clear SMBus PEC error flag.
1764 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1765 * SMBus feature is supported by the I2Cx Instance.
1766 * @rmtoll ICR PECCF LL_I2C_ClearSMBusFlag_PECERR
1767 * @param I2Cx I2C Instance.
1768 * @retval None
1769 */
1770 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_PECERR(I2C_TypeDef *I2Cx)
1771 {
1772 SET_BIT(I2Cx->ICR, I2C_ICR_PECCF);
1773 }
1774
1775 /**
1776 * @brief Clear SMBus Timeout detection flag.
1777 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1778 * SMBus feature is supported by the I2Cx Instance.
1779 * @rmtoll ICR TIMOUTCF LL_I2C_ClearSMBusFlag_TIMEOUT
1780 * @param I2Cx I2C Instance.
1781 * @retval None
1782 */
1783 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_TIMEOUT(I2C_TypeDef *I2Cx)
1784 {
1785 SET_BIT(I2Cx->ICR, I2C_ICR_TIMOUTCF);
1786 }
1787
1788 /**
1789 * @brief Clear SMBus Alert flag.
1790 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
1791 * SMBus feature is supported by the I2Cx Instance.
1792 * @rmtoll ICR ALERTCF LL_I2C_ClearSMBusFlag_ALERT
1793 * @param I2Cx I2C Instance.
1794 * @retval None
1795 */
1796 __STATIC_INLINE void LL_I2C_ClearSMBusFlag_ALERT(I2C_TypeDef *I2Cx)
1797 {
1798 SET_BIT(I2Cx->ICR, I2C_ICR_ALERTCF);
1799 }
1800
1801 /**
1802 * @}
1803 */
1804
1805 /** @defgroup I2C_LL_EF_Data_Management Data_Management
1806 * @{
1807 */
1808
1809 /**
1810 * @brief Enable automatic STOP condition generation (master mode).
1811 * @note Automatic end mode : a STOP condition is automatically sent when NBYTES data are transferred.
1812 * This bit has no effect in slave mode or when RELOAD bit is set.
1813 * @rmtoll CR2 AUTOEND LL_I2C_EnableAutoEndMode
1814 * @param I2Cx I2C Instance.
1815 * @retval None
1816 */
1817 __STATIC_INLINE void LL_I2C_EnableAutoEndMode(I2C_TypeDef *I2Cx)
1818 {
1819 SET_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1820 }
1821
1822 /**
1823 * @brief Disable automatic STOP condition generation (master mode).
1824 * @note Software end mode : TC flag is set when NBYTES data are transferre, stretching SCL low.
1825 * @rmtoll CR2 AUTOEND LL_I2C_DisableAutoEndMode
1826 * @param I2Cx I2C Instance.
1827 * @retval None
1828 */
1829 __STATIC_INLINE void LL_I2C_DisableAutoEndMode(I2C_TypeDef *I2Cx)
1830 {
1831 CLEAR_BIT(I2Cx->CR2, I2C_CR2_AUTOEND);
1832 }
1833
1834 /**
1835 * @brief Check if automatic STOP condition is enabled or disabled.
1836 * @rmtoll CR2 AUTOEND LL_I2C_IsEnabledAutoEndMode
1837 * @param I2Cx I2C Instance.
1838 * @retval State of bit (1 or 0).
1839 */
1840 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAutoEndMode(I2C_TypeDef *I2Cx)
1841 {
1842 return (READ_BIT(I2Cx->CR2, I2C_CR2_AUTOEND) == (I2C_CR2_AUTOEND));
1843 }
1844
1845 /**
1846 * @brief Enable reload mode (master mode).
1847 * @note The transfer is not completed after the NBYTES data transfer, NBYTES will be reloaded when TCR flag is set.
1848 * @rmtoll CR2 RELOAD LL_I2C_EnableReloadMode
1849 * @param I2Cx I2C Instance.
1850 * @retval None
1851 */
1852 __STATIC_INLINE void LL_I2C_EnableReloadMode(I2C_TypeDef *I2Cx)
1853 {
1854 SET_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1855 }
1856
1857 /**
1858 * @brief Disable reload mode (master mode).
1859 * @note The transfer is completed after the NBYTES data transfer(STOP or RESTART will follow).
1860 * @rmtoll CR2 RELOAD LL_I2C_DisableReloadMode
1861 * @param I2Cx I2C Instance.
1862 * @retval None
1863 */
1864 __STATIC_INLINE void LL_I2C_DisableReloadMode(I2C_TypeDef *I2Cx)
1865 {
1866 CLEAR_BIT(I2Cx->CR2, I2C_CR2_RELOAD);
1867 }
1868
1869 /**
1870 * @brief Check if reload mode is enabled or disabled.
1871 * @rmtoll CR2 RELOAD LL_I2C_IsEnabledReloadMode
1872 * @param I2Cx I2C Instance.
1873 * @retval State of bit (1 or 0).
1874 */
1875 __STATIC_INLINE uint32_t LL_I2C_IsEnabledReloadMode(I2C_TypeDef *I2Cx)
1876 {
1877 return (READ_BIT(I2Cx->CR2, I2C_CR2_RELOAD) == (I2C_CR2_RELOAD));
1878 }
1879
1880 /**
1881 * @brief Configure the number of bytes for transfer.
1882 * @note Changing these bits when START bit is set is not allowed.
1883 * @rmtoll CR2 NBYTES LL_I2C_SetTransferSize
1884 * @param I2Cx I2C Instance.
1885 * @param TransferSize This parameter must be a value between Min_Data=0x00 and Max_Data=0xFF.
1886 * @retval None
1887 */
1888 __STATIC_INLINE void LL_I2C_SetTransferSize(I2C_TypeDef *I2Cx, uint32_t TransferSize)
1889 {
1890 MODIFY_REG(I2Cx->CR2, I2C_CR2_NBYTES, TransferSize << I2C_CR2_NBYTES_Pos);
1891 }
1892
1893 /**
1894 * @brief Get the number of bytes configured for transfer.
1895 * @rmtoll CR2 NBYTES LL_I2C_GetTransferSize
1896 * @param I2Cx I2C Instance.
1897 * @retval Value between Min_Data=0x0 and Max_Data=0xFF
1898 */
1899 __STATIC_INLINE uint32_t LL_I2C_GetTransferSize(I2C_TypeDef *I2Cx)
1900 {
1901 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_NBYTES) >> I2C_CR2_NBYTES_Pos);
1902 }
1903
1904 /**
1905 * @brief Prepare the generation of a ACKnowledge or Non ACKnowledge condition after the address receive match code or next received byte.
1906 * @note Usage in Slave mode only.
1907 * @rmtoll CR2 NACK LL_I2C_AcknowledgeNextData
1908 * @param I2Cx I2C Instance.
1909 * @param TypeAcknowledge This parameter can be one of the following values:
1910 * @arg @ref LL_I2C_ACK
1911 * @arg @ref LL_I2C_NACK
1912 * @retval None
1913 */
1914 __STATIC_INLINE void LL_I2C_AcknowledgeNextData(I2C_TypeDef *I2Cx, uint32_t TypeAcknowledge)
1915 {
1916 MODIFY_REG(I2Cx->CR2, I2C_CR2_NACK, TypeAcknowledge);
1917 }
1918
1919 /**
1920 * @brief Generate a START or RESTART condition
1921 * @note The START bit can be set even if bus is BUSY or I2C is in slave mode.
1922 * This action has no effect when RELOAD is set.
1923 * @rmtoll CR2 START LL_I2C_GenerateStartCondition
1924 * @param I2Cx I2C Instance.
1925 * @retval None
1926 */
1927 __STATIC_INLINE void LL_I2C_GenerateStartCondition(I2C_TypeDef *I2Cx)
1928 {
1929 SET_BIT(I2Cx->CR2, I2C_CR2_START);
1930 }
1931
1932 /**
1933 * @brief Generate a STOP condition after the current byte transfer (master mode).
1934 * @rmtoll CR2 STOP LL_I2C_GenerateStopCondition
1935 * @param I2Cx I2C Instance.
1936 * @retval None
1937 */
1938 __STATIC_INLINE void LL_I2C_GenerateStopCondition(I2C_TypeDef *I2Cx)
1939 {
1940 SET_BIT(I2Cx->CR2, I2C_CR2_STOP);
1941 }
1942
1943 /**
1944 * @brief Enable automatic RESTART Read request condition for 10bit address header (master mode).
1945 * @note The master sends the complete 10bit slave address read sequence :
1946 * Start + 2 bytes 10bit address in Write direction + Restart + first 7 bits of 10bit address in Read direction.
1947 * @rmtoll CR2 HEAD10R LL_I2C_EnableAuto10BitRead
1948 * @param I2Cx I2C Instance.
1949 * @retval None
1950 */
1951 __STATIC_INLINE void LL_I2C_EnableAuto10BitRead(I2C_TypeDef *I2Cx)
1952 {
1953 CLEAR_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1954 }
1955
1956 /**
1957 * @brief Disable automatic RESTART Read request condition for 10bit address header (master mode).
1958 * @note The master only sends the first 7 bits of 10bit address in Read direction.
1959 * @rmtoll CR2 HEAD10R LL_I2C_DisableAuto10BitRead
1960 * @param I2Cx I2C Instance.
1961 * @retval None
1962 */
1963 __STATIC_INLINE void LL_I2C_DisableAuto10BitRead(I2C_TypeDef *I2Cx)
1964 {
1965 SET_BIT(I2Cx->CR2, I2C_CR2_HEAD10R);
1966 }
1967
1968 /**
1969 * @brief Check if automatic RESTART Read request condition for 10bit address header is enabled or disabled.
1970 * @rmtoll CR2 HEAD10R LL_I2C_IsEnabledAuto10BitRead
1971 * @param I2Cx I2C Instance.
1972 * @retval State of bit (1 or 0).
1973 */
1974 __STATIC_INLINE uint32_t LL_I2C_IsEnabledAuto10BitRead(I2C_TypeDef *I2Cx)
1975 {
1976 return (READ_BIT(I2Cx->CR2, I2C_CR2_HEAD10R) != (I2C_CR2_HEAD10R));
1977 }
1978
1979 /**
1980 * @brief Configure the transfer direction (master mode).
1981 * @note Changing these bits when START bit is set is not allowed.
1982 * @rmtoll CR2 RD_WRN LL_I2C_SetTransferRequest
1983 * @param I2Cx I2C Instance.
1984 * @param TransferRequest This parameter can be one of the following values:
1985 * @arg @ref LL_I2C_REQUEST_WRITE
1986 * @arg @ref LL_I2C_REQUEST_READ
1987 * @retval None
1988 */
1989 __STATIC_INLINE void LL_I2C_SetTransferRequest(I2C_TypeDef *I2Cx, uint32_t TransferRequest)
1990 {
1991 MODIFY_REG(I2Cx->CR2, I2C_CR2_RD_WRN, TransferRequest);
1992 }
1993
1994 /**
1995 * @brief Get the transfer direction requested (master mode).
1996 * @rmtoll CR2 RD_WRN LL_I2C_GetTransferRequest
1997 * @param I2Cx I2C Instance.
1998 * @retval Returned value can be one of the following values:
1999 * @arg @ref LL_I2C_REQUEST_WRITE
2000 * @arg @ref LL_I2C_REQUEST_READ
2001 */
2002 __STATIC_INLINE uint32_t LL_I2C_GetTransferRequest(I2C_TypeDef *I2Cx)
2003 {
2004 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_RD_WRN));
2005 }
2006
2007 /**
2008 * @brief Configure the slave address for transfer (master mode).
2009 * @note Changing these bits when START bit is set is not allowed.
2010 * @rmtoll CR2 SADD LL_I2C_SetSlaveAddr
2011 * @param I2Cx I2C Instance.
2012 * @param SlaveAddr This parameter must be a value between Min_Data=0x00 and Max_Data=0x3F.
2013 * @retval None
2014 */
2015 __STATIC_INLINE void LL_I2C_SetSlaveAddr(I2C_TypeDef *I2Cx, uint32_t SlaveAddr)
2016 {
2017 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD, SlaveAddr);
2018 }
2019
2020 /**
2021 * @brief Get the slave address programmed for transfer.
2022 * @rmtoll CR2 SADD LL_I2C_GetSlaveAddr
2023 * @param I2Cx I2C Instance.
2024 * @retval Value between Min_Data=0x0 and Max_Data=0x3F
2025 */
2026 __STATIC_INLINE uint32_t LL_I2C_GetSlaveAddr(I2C_TypeDef *I2Cx)
2027 {
2028 return (uint32_t)(READ_BIT(I2Cx->CR2, I2C_CR2_SADD));
2029 }
2030
2031 /**
2032 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
2033 * @rmtoll CR2 SADD LL_I2C_HandleTransfer\n
2034 * CR2 ADD10 LL_I2C_HandleTransfer\n
2035 * CR2 RD_WRN LL_I2C_HandleTransfer\n
2036 * CR2 START LL_I2C_HandleTransfer\n
2037 * CR2 STOP LL_I2C_HandleTransfer\n
2038 * CR2 RELOAD LL_I2C_HandleTransfer\n
2039 * CR2 NBYTES LL_I2C_HandleTransfer\n
2040 * CR2 AUTOEND LL_I2C_HandleTransfer\n
2041 * CR2 HEAD10R LL_I2C_HandleTransfer
2042 * @param I2Cx I2C Instance.
2043 * @param SlaveAddr Specifies the slave address to be programmed.
2044 * @param SlaveAddrSize This parameter can be one of the following values:
2045 * @arg @ref LL_I2C_ADDRSLAVE_7BIT
2046 * @arg @ref LL_I2C_ADDRSLAVE_10BIT
2047 * @param TransferSize Specifies the number of bytes to be programmed.
2048 * This parameter must be a value between Min_Data=0 and Max_Data=255.
2049 * @param EndMode This parameter can be one of the following values:
2050 * @arg @ref LL_I2C_MODE_RELOAD
2051 * @arg @ref LL_I2C_MODE_AUTOEND
2052 * @arg @ref LL_I2C_MODE_SOFTEND
2053 * @arg @ref LL_I2C_MODE_SMBUS_RELOAD
2054 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_NO_PEC
2055 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_NO_PEC
2056 * @arg @ref LL_I2C_MODE_SMBUS_AUTOEND_WITH_PEC
2057 * @arg @ref LL_I2C_MODE_SMBUS_SOFTEND_WITH_PEC
2058 * @param Request This parameter can be one of the following values:
2059 * @arg @ref LL_I2C_GENERATE_NOSTARTSTOP
2060 * @arg @ref LL_I2C_GENERATE_STOP
2061 * @arg @ref LL_I2C_GENERATE_START_READ
2062 * @arg @ref LL_I2C_GENERATE_START_WRITE
2063 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_READ
2064 * @arg @ref LL_I2C_GENERATE_RESTART_7BIT_WRITE
2065 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_READ
2066 * @arg @ref LL_I2C_GENERATE_RESTART_10BIT_WRITE
2067 * @retval None
2068 */
2069 __STATIC_INLINE void LL_I2C_HandleTransfer(I2C_TypeDef *I2Cx, uint32_t SlaveAddr, uint32_t SlaveAddrSize,
2070 uint32_t TransferSize, uint32_t EndMode, uint32_t Request)
2071 {
2072 MODIFY_REG(I2Cx->CR2, I2C_CR2_SADD | I2C_CR2_ADD10 | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP | I2C_CR2_RELOAD |
2073 I2C_CR2_NBYTES | I2C_CR2_AUTOEND | I2C_CR2_HEAD10R,
2074 SlaveAddr | SlaveAddrSize | TransferSize << I2C_CR2_NBYTES_Pos | EndMode | Request);
2075 }
2076
2077 /**
2078 * @brief Indicate the value of transfer direction (slave mode).
2079 * @note RESET: Write transfer, Slave enters in receiver mode.
2080 * SET: Read transfer, Slave enters in transmitter mode.
2081 * @rmtoll ISR DIR LL_I2C_GetTransferDirection
2082 * @param I2Cx I2C Instance.
2083 * @retval Returned value can be one of the following values:
2084 * @arg @ref LL_I2C_DIRECTION_WRITE
2085 * @arg @ref LL_I2C_DIRECTION_READ
2086 */
2087 __STATIC_INLINE uint32_t LL_I2C_GetTransferDirection(I2C_TypeDef *I2Cx)
2088 {
2089 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_DIR));
2090 }
2091
2092 /**
2093 * @brief Return the slave matched address.
2094 * @rmtoll ISR ADDCODE LL_I2C_GetAddressMatchCode
2095 * @param I2Cx I2C Instance.
2096 * @retval Value between Min_Data=0x00 and Max_Data=0x3F
2097 */
2098 __STATIC_INLINE uint32_t LL_I2C_GetAddressMatchCode(I2C_TypeDef *I2Cx)
2099 {
2100 return (uint32_t)(READ_BIT(I2Cx->ISR, I2C_ISR_ADDCODE) >> I2C_ISR_ADDCODE_Pos << 1);
2101 }
2102
2103 /**
2104 * @brief Enable internal comparison of the SMBus Packet Error byte (transmission or reception mode).
2105 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2106 * SMBus feature is supported by the I2Cx Instance.
2107 * @note This feature is cleared by hardware when the PEC byte is transferred, or when a STOP condition or an Address Matched is received.
2108 * This bit has no effect when RELOAD bit is set.
2109 * This bit has no effect in device mode when SBC bit is not set.
2110 * @rmtoll CR2 PECBYTE LL_I2C_EnableSMBusPECCompare
2111 * @param I2Cx I2C Instance.
2112 * @retval None
2113 */
2114 __STATIC_INLINE void LL_I2C_EnableSMBusPECCompare(I2C_TypeDef *I2Cx)
2115 {
2116 SET_BIT(I2Cx->CR2, I2C_CR2_PECBYTE);
2117 }
2118
2119 /**
2120 * @brief Check if the SMBus Packet Error byte internal comparison is requested or not.
2121 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2122 * SMBus feature is supported by the I2Cx Instance.
2123 * @rmtoll CR2 PECBYTE LL_I2C_IsEnabledSMBusPECCompare
2124 * @param I2Cx I2C Instance.
2125 * @retval State of bit (1 or 0).
2126 */
2127 __STATIC_INLINE uint32_t LL_I2C_IsEnabledSMBusPECCompare(I2C_TypeDef *I2Cx)
2128 {
2129 return (READ_BIT(I2Cx->CR2, I2C_CR2_PECBYTE) == (I2C_CR2_PECBYTE));
2130 }
2131
2132 /**
2133 * @brief Get the SMBus Packet Error byte calculated.
2134 * @note Macro @ref IS_SMBUS_ALL_INSTANCE(I2Cx) can be used to check whether or not
2135 * SMBus feature is supported by the I2Cx Instance.
2136 * @rmtoll PECR PEC LL_I2C_GetSMBusPEC
2137 * @param I2Cx I2C Instance.
2138 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2139 */
2140 __STATIC_INLINE uint32_t LL_I2C_GetSMBusPEC(I2C_TypeDef *I2Cx)
2141 {
2142 return (uint32_t)(READ_BIT(I2Cx->PECR, I2C_PECR_PEC));
2143 }
2144
2145 /**
2146 * @brief Read Receive Data register.
2147 * @rmtoll RXDR RXDATA LL_I2C_ReceiveData8
2148 * @param I2Cx I2C Instance.
2149 * @retval Value between Min_Data=0x00 and Max_Data=0xFF
2150 */
2151 __STATIC_INLINE uint8_t LL_I2C_ReceiveData8(I2C_TypeDef *I2Cx)
2152 {
2153 return (uint8_t)(READ_BIT(I2Cx->RXDR, I2C_RXDR_RXDATA));
2154 }
2155
2156 /**
2157 * @brief Write in Transmit Data Register .
2158 * @rmtoll TXDR TXDATA LL_I2C_TransmitData8
2159 * @param I2Cx I2C Instance.
2160 * @param Data Value between Min_Data=0x00 and Max_Data=0xFF
2161 * @retval None
2162 */
2163 __STATIC_INLINE void LL_I2C_TransmitData8(I2C_TypeDef *I2Cx, uint8_t Data)
2164 {
2165 WRITE_REG(I2Cx->TXDR, Data);
2166 }
2167
2168 /**
2169 * @}
2170 */
2171
2172 #if defined(USE_FULL_LL_DRIVER)
2173 /** @defgroup I2C_LL_EF_Init Initialization and de-initialization functions
2174 * @{
2175 */
2176
2177 uint32_t LL_I2C_Init(I2C_TypeDef *I2Cx, LL_I2C_InitTypeDef *I2C_InitStruct);
2178 uint32_t LL_I2C_DeInit(I2C_TypeDef *I2Cx);
2179 void LL_I2C_StructInit(LL_I2C_InitTypeDef *I2C_InitStruct);
2180
2181
2182 /**
2183 * @}
2184 */
2185 #endif /* USE_FULL_LL_DRIVER */
2186
2187 /**
2188 * @}
2189 */
2190
2191 /**
2192 * @}
2193 */
2194
2195 #endif /* I2C1 || I2C2 || I2C3 || I2C4 */
2196
2197 /**
2198 * @}
2199 */
2200
2201 #ifdef __cplusplus
2202 }
2203 #endif
2204
2205 #endif /* __STM32F7xx_LL_I2C_H */
2206
2207 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software