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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_rcc.h
blobb9c9db88f96f692d4c88739a489ba097382784c0
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of RCC LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_RCC_H
40 #define __STM32F7xx_LL_RCC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined(RCC)
54
55 /** @defgroup RCC_LL RCC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
62 * @{
63 */
64
65 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
66 static const uint8_t aRCC_PLLSAIDIVRPrescTable[4] = {2, 4, 8, 16};
67 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
68
69 /**
70 * @}
71 */
72 /* Private constants ---------------------------------------------------------*/
73 /* Private macros ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
76 * @{
77 */
78 /**
79 * @}
80 */
81 #endif /*USE_FULL_LL_DRIVER*/
82 /* Exported types ------------------------------------------------------------*/
83 #if defined(USE_FULL_LL_DRIVER)
84 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
85 * @{
86 */
87
88 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
89 * @{
90 */
91
92 /**
93 * @brief RCC Clocks Frequency Structure
94 */
95 typedef struct
96 {
97 uint32_t SYSCLK_Frequency; /*!< SYSCLK clock frequency */
98 uint32_t HCLK_Frequency; /*!< HCLK clock frequency */
99 uint32_t PCLK1_Frequency; /*!< PCLK1 clock frequency */
100 uint32_t PCLK2_Frequency; /*!< PCLK2 clock frequency */
101 } LL_RCC_ClocksTypeDef;
102
103 /**
104 * @}
105 */
106
107 /**
108 * @}
109 */
110 #endif /* USE_FULL_LL_DRIVER */
111
112 /* Exported constants --------------------------------------------------------*/
113 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
114 * @{
115 */
116
117 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
118 * @brief Defines used to adapt values of different oscillators
119 * @note These values could be modified in the user environment according to
120 * HW set-up.
121 * @{
122 */
123 #if !defined (HSE_VALUE)
124 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
125 #endif /* HSE_VALUE */
126
127 #if !defined (HSI_VALUE)
128 #define HSI_VALUE 16000000U /*!< Value of the HSI oscillator in Hz */
129 #endif /* HSI_VALUE */
130
131 #if !defined (LSE_VALUE)
132 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
133 #endif /* LSE_VALUE */
134
135 #if !defined (LSI_VALUE)
136 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
137 #endif /* LSI_VALUE */
138
139 #if !defined (EXTERNAL_CLOCK_VALUE)
140 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
141 #endif /* EXTERNAL_CLOCK_VALUE */
142 /**
143 * @}
144 */
145
146 /** @defgroup RCC_LL_EC_CLEAR_FLAG Clear Flags Defines
147 * @brief Flags defines which can be used with LL_RCC_WriteReg function
148 * @{
149 */
150 #define LL_RCC_CIR_LSIRDYC RCC_CIR_LSIRDYC /*!< LSI Ready Interrupt Clear */
151 #define LL_RCC_CIR_LSERDYC RCC_CIR_LSERDYC /*!< LSE Ready Interrupt Clear */
152 #define LL_RCC_CIR_HSIRDYC RCC_CIR_HSIRDYC /*!< HSI Ready Interrupt Clear */
153 #define LL_RCC_CIR_HSERDYC RCC_CIR_HSERDYC /*!< HSE Ready Interrupt Clear */
154 #define LL_RCC_CIR_PLLRDYC RCC_CIR_PLLRDYC /*!< PLL Ready Interrupt Clear */
155 #define LL_RCC_CIR_PLLI2SRDYC RCC_CIR_PLLI2SRDYC /*!< PLLI2S Ready Interrupt Clear */
156 #define LL_RCC_CIR_PLLSAIRDYC RCC_CIR_PLLSAIRDYC /*!< PLLSAI Ready Interrupt Clear */
157 #define LL_RCC_CIR_CSSC RCC_CIR_CSSC /*!< Clock Security System Interrupt Clear */
158 /**
159 * @}
160 */
161
162 /** @defgroup RCC_LL_EC_GET_FLAG Get Flags Defines
163 * @brief Flags defines which can be used with LL_RCC_ReadReg function
164 * @{
165 */
166 #define LL_RCC_CIR_LSIRDYF RCC_CIR_LSIRDYF /*!< LSI Ready Interrupt flag */
167 #define LL_RCC_CIR_LSERDYF RCC_CIR_LSERDYF /*!< LSE Ready Interrupt flag */
168 #define LL_RCC_CIR_HSIRDYF RCC_CIR_HSIRDYF /*!< HSI Ready Interrupt flag */
169 #define LL_RCC_CIR_HSERDYF RCC_CIR_HSERDYF /*!< HSE Ready Interrupt flag */
170 #define LL_RCC_CIR_PLLRDYF RCC_CIR_PLLRDYF /*!< PLL Ready Interrupt flag */
171 #define LL_RCC_CIR_PLLI2SRDYF RCC_CIR_PLLI2SRDYF /*!< PLLI2S Ready Interrupt flag */
172 #define LL_RCC_CIR_PLLSAIRDYF RCC_CIR_PLLSAIRDYF /*!< PLLSAI Ready Interrupt flag */
173 #define LL_RCC_CIR_CSSF RCC_CIR_CSSF /*!< Clock Security System Interrupt flag */
174 #define LL_RCC_CSR_LPWRRSTF RCC_CSR_LPWRRSTF /*!< Low-Power reset flag */
175 #define LL_RCC_CSR_PINRSTF RCC_CSR_PINRSTF /*!< PIN reset flag */
176 #define LL_RCC_CSR_PORRSTF RCC_CSR_PORRSTF /*!< POR/PDR reset flag */
177 #define LL_RCC_CSR_SFTRSTF RCC_CSR_SFTRSTF /*!< Software Reset flag */
178 #define LL_RCC_CSR_IWDGRSTF RCC_CSR_IWDGRSTF /*!< Independent Watchdog reset flag */
179 #define LL_RCC_CSR_WWDGRSTF RCC_CSR_WWDGRSTF /*!< Window watchdog reset flag */
180 #define LL_RCC_CSR_BORRSTF RCC_CSR_BORRSTF /*!< BOR reset flag */
181 /**
182 * @}
183 */
184
185 /** @defgroup RCC_LL_EC_IT IT Defines
186 * @brief IT defines which can be used with LL_RCC_ReadReg and LL_RCC_WriteReg functions
187 * @{
188 */
189 #define LL_RCC_CIR_LSIRDYIE RCC_CIR_LSIRDYIE /*!< LSI Ready Interrupt Enable */
190 #define LL_RCC_CIR_LSERDYIE RCC_CIR_LSERDYIE /*!< LSE Ready Interrupt Enable */
191 #define LL_RCC_CIR_HSIRDYIE RCC_CIR_HSIRDYIE /*!< HSI Ready Interrupt Enable */
192 #define LL_RCC_CIR_HSERDYIE RCC_CIR_HSERDYIE /*!< HSE Ready Interrupt Enable */
193 #define LL_RCC_CIR_PLLRDYIE RCC_CIR_PLLRDYIE /*!< PLL Ready Interrupt Enable */
194 #define LL_RCC_CIR_PLLI2SRDYIE RCC_CIR_PLLI2SRDYIE /*!< PLLI2S Ready Interrupt Enable */
195 #define LL_RCC_CIR_PLLSAIRDYIE RCC_CIR_PLLSAIRDYIE /*!< PLLSAI Ready Interrupt Enable */
196 /**
197 * @}
198 */
199
200 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
201 * @{
202 */
203 #define LL_RCC_LSEDRIVE_LOW 0x00000000U /*!< Xtal mode lower driving capability */
204 #define LL_RCC_LSEDRIVE_MEDIUMHIGH RCC_BDCR_LSEDRV_0 /*!< Xtal mode medium high driving capability */
205 #define LL_RCC_LSEDRIVE_MEDIUMLOW RCC_BDCR_LSEDRV_1 /*!< Xtal mode medium low driving capability */
206 #define LL_RCC_LSEDRIVE_HIGH RCC_BDCR_LSEDRV /*!< Xtal mode higher driving capability */
207 /**
208 * @}
209 */
210
211 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
212 * @{
213 */
214 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI /*!< HSI selection as system clock */
215 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE /*!< HSE selection as system clock */
216 #define LL_RCC_SYS_CLKSOURCE_PLL RCC_CFGR_SW_PLL /*!< PLL selection as system clock */
217 /**
218 * @}
219 */
220
221 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
222 * @{
223 */
224 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
225 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL RCC_CFGR_SWS_PLL /*!< PLL used as system clock */
227 /**
228 * @}
229 */
230
231 /** @defgroup RCC_LL_EC_SYSCLK_DIV AHB prescaler
232 * @{
233 */
234 #define LL_RCC_SYSCLK_DIV_1 RCC_CFGR_HPRE_DIV1 /*!< SYSCLK not divided */
235 #define LL_RCC_SYSCLK_DIV_2 RCC_CFGR_HPRE_DIV2 /*!< SYSCLK divided by 2 */
236 #define LL_RCC_SYSCLK_DIV_4 RCC_CFGR_HPRE_DIV4 /*!< SYSCLK divided by 4 */
237 #define LL_RCC_SYSCLK_DIV_8 RCC_CFGR_HPRE_DIV8 /*!< SYSCLK divided by 8 */
238 #define LL_RCC_SYSCLK_DIV_16 RCC_CFGR_HPRE_DIV16 /*!< SYSCLK divided by 16 */
239 #define LL_RCC_SYSCLK_DIV_64 RCC_CFGR_HPRE_DIV64 /*!< SYSCLK divided by 64 */
240 #define LL_RCC_SYSCLK_DIV_128 RCC_CFGR_HPRE_DIV128 /*!< SYSCLK divided by 128 */
241 #define LL_RCC_SYSCLK_DIV_256 RCC_CFGR_HPRE_DIV256 /*!< SYSCLK divided by 256 */
242 #define LL_RCC_SYSCLK_DIV_512 RCC_CFGR_HPRE_DIV512 /*!< SYSCLK divided by 512 */
243 /**
244 * @}
245 */
246
247 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
248 * @{
249 */
250 #define LL_RCC_APB1_DIV_1 RCC_CFGR_PPRE1_DIV1 /*!< HCLK not divided */
251 #define LL_RCC_APB1_DIV_2 RCC_CFGR_PPRE1_DIV2 /*!< HCLK divided by 2 */
252 #define LL_RCC_APB1_DIV_4 RCC_CFGR_PPRE1_DIV4 /*!< HCLK divided by 4 */
253 #define LL_RCC_APB1_DIV_8 RCC_CFGR_PPRE1_DIV8 /*!< HCLK divided by 8 */
254 #define LL_RCC_APB1_DIV_16 RCC_CFGR_PPRE1_DIV16 /*!< HCLK divided by 16 */
255 /**
256 * @}
257 */
258 /** @defgroup RCC_LL_EC_APB2_DIV APB high-speed prescaler (APB2)
259 * @{
260 */
261 #define LL_RCC_APB2_DIV_1 RCC_CFGR_PPRE2_DIV1 /*!< HCLK not divided */
262 #define LL_RCC_APB2_DIV_2 RCC_CFGR_PPRE2_DIV2 /*!< HCLK divided by 2 */
263 #define LL_RCC_APB2_DIV_4 RCC_CFGR_PPRE2_DIV4 /*!< HCLK divided by 4 */
264 #define LL_RCC_APB2_DIV_8 RCC_CFGR_PPRE2_DIV8 /*!< HCLK divided by 8 */
265 #define LL_RCC_APB2_DIV_16 RCC_CFGR_PPRE2_DIV16 /*!< HCLK divided by 16 */
266 /**
267 * @}
268 */
269
270 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
271 * @{
272 */
273 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)(RCC_CFGR_MCO1|0x00000000U) /*!< HSI selection as MCO1 source */
274 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_0 >> 16U)) /*!< LSE selection as MCO1 source */
275 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)(RCC_CFGR_MCO1|(RCC_CFGR_MCO1_1 >> 16U)) /*!< HSE selection as MCO1 source */
276 #define LL_RCC_MCO1SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO1|((RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0) >> 16U)) /*!< PLLCLK selection as MCO1 source */
277 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)(RCC_CFGR_MCO2|0x00000000U) /*!< SYSCLK selection as MCO2 source */
278 #define LL_RCC_MCO2SOURCE_PLLI2S (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_0 >> 16U)) /*!< PLLI2S selection as MCO2 source */
279 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)(RCC_CFGR_MCO2|(RCC_CFGR_MCO2_1 >> 16U)) /*!< HSE selection as MCO2 source */
280 #define LL_RCC_MCO2SOURCE_PLLCLK (uint32_t)(RCC_CFGR_MCO2|((RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0) >> 16U)) /*!< PLLCLK selection as MCO2 source */
281 /**
282 * @}
283 */
284
285 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
286 * @{
287 */
288 #define LL_RCC_MCO1_DIV_1 (uint32_t)(RCC_CFGR_MCO1PRE|0x00000000U) /*!< MCO1 not divided */
289 #define LL_RCC_MCO1_DIV_2 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE_2 >> 16U)) /*!< MCO1 divided by 2 */
290 #define LL_RCC_MCO1_DIV_3 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_0) >> 16U)) /*!< MCO1 divided by 3 */
291 #define LL_RCC_MCO1_DIV_4 (uint32_t)(RCC_CFGR_MCO1PRE|((RCC_CFGR_MCO1PRE_2|RCC_CFGR_MCO1PRE_1) >> 16U)) /*!< MCO1 divided by 4 */
292 #define LL_RCC_MCO1_DIV_5 (uint32_t)(RCC_CFGR_MCO1PRE|(RCC_CFGR_MCO1PRE >> 16U)) /*!< MCO1 divided by 5 */
293 #define LL_RCC_MCO2_DIV_1 (uint32_t)(RCC_CFGR_MCO2PRE|0x00000000U) /*!< MCO2 not divided */
294 #define LL_RCC_MCO2_DIV_2 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE_2 >> 16U)) /*!< MCO2 divided by 2 */
295 #define LL_RCC_MCO2_DIV_3 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_0) >> 16U)) /*!< MCO2 divided by 3 */
296 #define LL_RCC_MCO2_DIV_4 (uint32_t)(RCC_CFGR_MCO2PRE|((RCC_CFGR_MCO2PRE_2|RCC_CFGR_MCO2PRE_1) >> 16U)) /*!< MCO2 divided by 4 */
297 #define LL_RCC_MCO2_DIV_5 (uint32_t)(RCC_CFGR_MCO2PRE|(RCC_CFGR_MCO2PRE >> 16U)) /*!< MCO2 divided by 5 */
298 /**
299 * @}
300 */
301
302 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
303 * @{
304 */
305 #define LL_RCC_RTC_NOCLOCK 0x00000000U /*!< HSE not divided */
306 #define LL_RCC_RTC_HSE_DIV_2 RCC_CFGR_RTCPRE_1 /*!< HSE clock divided by 2 */
307 #define LL_RCC_RTC_HSE_DIV_3 (RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 3 */
308 #define LL_RCC_RTC_HSE_DIV_4 RCC_CFGR_RTCPRE_2 /*!< HSE clock divided by 4 */
309 #define LL_RCC_RTC_HSE_DIV_5 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 5 */
310 #define LL_RCC_RTC_HSE_DIV_6 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 6 */
311 #define LL_RCC_RTC_HSE_DIV_7 (RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 7 */
312 #define LL_RCC_RTC_HSE_DIV_8 RCC_CFGR_RTCPRE_3 /*!< HSE clock divided by 8 */
313 #define LL_RCC_RTC_HSE_DIV_9 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 9 */
314 #define LL_RCC_RTC_HSE_DIV_10 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 10 */
315 #define LL_RCC_RTC_HSE_DIV_11 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 11 */
316 #define LL_RCC_RTC_HSE_DIV_12 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 12 */
317 #define LL_RCC_RTC_HSE_DIV_13 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 13 */
318 #define LL_RCC_RTC_HSE_DIV_14 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 14 */
319 #define LL_RCC_RTC_HSE_DIV_15 (RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 15 */
320 #define LL_RCC_RTC_HSE_DIV_16 RCC_CFGR_RTCPRE_4 /*!< HSE clock divided by 16 */
321 #define LL_RCC_RTC_HSE_DIV_17 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 17 */
322 #define LL_RCC_RTC_HSE_DIV_18 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 18 */
323 #define LL_RCC_RTC_HSE_DIV_19 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 19 */
324 #define LL_RCC_RTC_HSE_DIV_20 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 20 */
325 #define LL_RCC_RTC_HSE_DIV_21 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 21 */
326 #define LL_RCC_RTC_HSE_DIV_22 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 22 */
327 #define LL_RCC_RTC_HSE_DIV_23 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 23 */
328 #define LL_RCC_RTC_HSE_DIV_24 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3) /*!< HSE clock divided by 24 */
329 #define LL_RCC_RTC_HSE_DIV_25 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 25 */
330 #define LL_RCC_RTC_HSE_DIV_26 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 26 */
331 #define LL_RCC_RTC_HSE_DIV_27 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 27 */
332 #define LL_RCC_RTC_HSE_DIV_28 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2) /*!< HSE clock divided by 28 */
333 #define LL_RCC_RTC_HSE_DIV_29 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 29 */
334 #define LL_RCC_RTC_HSE_DIV_30 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1) /*!< HSE clock divided by 30 */
335 #define LL_RCC_RTC_HSE_DIV_31 (RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0) /*!< HSE clock divided by 31 */
336 /**
337 * @}
338 */
339
340 #if defined(USE_FULL_LL_DRIVER)
341 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
342 * @{
343 */
344 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
345 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
346 /**
347 * @}
348 */
349 #endif /* USE_FULL_LL_DRIVER */
350
351 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
352 * @{
353 */
354 #define LL_RCC_USART1_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART1 clock source */
355 #define LL_RCC_USART1_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_0) /*!< SYSCLK clock used as USART1 clock source */
356 #define LL_RCC_USART1_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL_1) /*!< HSI clock used as USART1 clock source */
357 #define LL_RCC_USART1_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART1SEL << 16U) | RCC_DCKCFGR2_USART1SEL) /*!< LSE clock used as USART1 clock source */
358 #define LL_RCC_USART2_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART2 clock source */
359 #define LL_RCC_USART2_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_0) /*!< SYSCLK clock used as USART2 clock source */
360 #define LL_RCC_USART2_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL_1) /*!< HSI clock used as USART2 clock source */
361 #define LL_RCC_USART2_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART2SEL << 16U) | RCC_DCKCFGR2_USART2SEL) /*!< LSE clock used as USART2 clock source */
362 #define LL_RCC_USART3_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as USART3 clock source */
363 #define LL_RCC_USART3_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_0) /*!< SYSCLK clock used as USART3 clock source */
364 #define LL_RCC_USART3_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL_1) /*!< HSI clock used as USART3 clock source */
365 #define LL_RCC_USART3_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART3SEL << 16U) | RCC_DCKCFGR2_USART3SEL) /*!< LSE clock used as USART3 clock source */
366 #define LL_RCC_USART6_CLKSOURCE_PCLK2 (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | 0x00000000U) /*!< PCLK2 clock used as USART6 clock source */
367 #define LL_RCC_USART6_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_0) /*!< SYSCLK clock used as USART6 clock source */
368 #define LL_RCC_USART6_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL_1) /*!< HSI clock used as USART6 clock source */
369 #define LL_RCC_USART6_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_USART6SEL << 16U) | RCC_DCKCFGR2_USART6SEL) /*!< LSE clock used as USART6 clock source */
370 /**
371 * @}
372 */
373
374 /** @defgroup RCC_LL_EC_UARTx_CLKSOURCE Peripheral UART clock source selection
375 * @{
376 */
377 #define LL_RCC_UART4_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART4 clock source */
378 #define LL_RCC_UART4_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_0) /*!< SYSCLK clock used as UART4 clock source */
379 #define LL_RCC_UART4_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL_1) /*!< HSI clock used as UART4 clock source */
380 #define LL_RCC_UART4_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART4SEL << 16U) | RCC_DCKCFGR2_UART4SEL) /*!< LSE clock used as UART4 clock source */
381 #define LL_RCC_UART5_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART5 clock source */
382 #define LL_RCC_UART5_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_0) /*!< SYSCLK clock used as UART5 clock source */
383 #define LL_RCC_UART5_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL_1) /*!< HSI clock used as UART5 clock source */
384 #define LL_RCC_UART5_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART5SEL << 16U) | RCC_DCKCFGR2_UART5SEL) /*!< LSE clock used as UART5 clock source */
385 #define LL_RCC_UART7_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART7 clock source */
386 #define LL_RCC_UART7_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_0) /*!< SYSCLK clock used as UART7 clock source */
387 #define LL_RCC_UART7_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL_1) /*!< HSI clock used as UART7 clock source */
388 #define LL_RCC_UART7_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART7SEL << 16U) | RCC_DCKCFGR2_UART7SEL) /*!< LSE clock used as UART7 clock source */
389 #define LL_RCC_UART8_CLKSOURCE_PCLK1 (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | 0x00000000U) /*!< PCLK1 clock used as UART8 clock source */
390 #define LL_RCC_UART8_CLKSOURCE_SYSCLK (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_0) /*!< SYSCLK clock used as UART8 clock source */
391 #define LL_RCC_UART8_CLKSOURCE_HSI (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL_1) /*!< HSI clock used as UART8 clock source */
392 #define LL_RCC_UART8_CLKSOURCE_LSE (uint32_t)((RCC_DCKCFGR2_UART8SEL << 16U) | RCC_DCKCFGR2_UART8SEL) /*!< LSE clock used as UART8 clock source */
393 /**
394 * @}
395 */
396
397 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
398 * @{
399 */
400 #define LL_RCC_I2C1_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C1SEL|0x00000000U) /*!< PCLK1 clock used as I2C1 clock source */
401 #define LL_RCC_I2C1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C1 clock source */
402 #define LL_RCC_I2C1_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C1SEL|(RCC_DCKCFGR2_I2C1SEL_1 >> 16U)) /*!< HSI clock used as I2C1 clock source */
403 #define LL_RCC_I2C2_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C2SEL|0x00000000U) /*!< PCLK1 clock used as I2C2 clock source */
404 #define LL_RCC_I2C2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C2 clock source */
405 #define LL_RCC_I2C2_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C2SEL|(RCC_DCKCFGR2_I2C2SEL_1 >> 16U)) /*!< HSI clock used as I2C2 clock source */
406 #define LL_RCC_I2C3_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C3SEL|0x00000000U) /*!< PCLK1 clock used as I2C3 clock source */
407 #define LL_RCC_I2C3_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C3 clock source */
408 #define LL_RCC_I2C3_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C3SEL|(RCC_DCKCFGR2_I2C3SEL_1 >> 16U)) /*!< HSI clock used as I2C3 clock source */
409 #if defined(I2C4)
410 #define LL_RCC_I2C4_CLKSOURCE_PCLK1 (uint32_t)(RCC_DCKCFGR2_I2C4SEL|0x00000000U) /*!< PCLK1 clock used as I2C4 clock source */
411 #define LL_RCC_I2C4_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_0 >> 16U)) /*!< SYSCLK clock used as I2C4 clock source */
412 #define LL_RCC_I2C4_CLKSOURCE_HSI (uint32_t)(RCC_DCKCFGR2_I2C4SEL|(RCC_DCKCFGR2_I2C4SEL_1 >> 16U)) /*!< HSI clock used as I2C4 clock source */
413 #endif /* I2C4 */
414 /**
415 * @}
416 */
417
418 /** @defgroup RCC_LL_EC_LPTIM1_CLKSOURCE Peripheral LPTIM clock source selection
419 * @{
420 */
421 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 0x00000000U /*!< PCLK1 clock used as LPTIM1 clock */
422 #define LL_RCC_LPTIM1_CLKSOURCE_LSI RCC_DCKCFGR2_LPTIM1SEL_0 /*!< LSI oscillator clock used as LPTIM1 clock */
423 #define LL_RCC_LPTIM1_CLKSOURCE_HSI RCC_DCKCFGR2_LPTIM1SEL_1 /*!< HSI oscillator clock used as LPTIM1 clock */
424 #define LL_RCC_LPTIM1_CLKSOURCE_LSE (uint32_t)(RCC_DCKCFGR2_LPTIM1SEL_1 | RCC_DCKCFGR2_LPTIM1SEL_0) /*!< LSE oscillator clock used as LPTIM1 clock */
425 /**
426 * @}
427 */
428
429 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
430 * @{
431 */
432 #define LL_RCC_SAI1_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI1SEL | 0x00000000U) /*!< PLLSAI clock used as SAI1 clock source */
433 #define LL_RCC_SAI1_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI1 clock source */
434 #define LL_RCC_SAI1_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL_1 >> 16U)) /*!< External pin clock used as SAI1 clock source */
435 #if defined(RCC_SAI1SEL_PLLSRC_SUPPORT)
436 #define LL_RCC_SAI1_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI1SEL | (RCC_DCKCFGR1_SAI1SEL >> 16U)) /*!< Main source clock used as SAI1 clock source */
437 #endif /* RCC_SAI1SEL_PLLSRC_SUPPORT */
438 #define LL_RCC_SAI2_CLKSOURCE_PLLSAI (uint32_t)(RCC_DCKCFGR1_SAI2SEL | 0x00000000U) /*!< PLLSAI clock used as SAI2 clock source */
439 #define LL_RCC_SAI2_CLKSOURCE_PLLI2S (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_0 >> 16U)) /*!< PLLI2S clock used as SAI2 clock source */
440 #define LL_RCC_SAI2_CLKSOURCE_PIN (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL_1 >> 16U)) /*!< External pin clock used as SAI2 clock source */
441 #if defined(RCC_SAI2SEL_PLLSRC_SUPPORT)
442 #define LL_RCC_SAI2_CLKSOURCE_PLLSRC (uint32_t)(RCC_DCKCFGR1_SAI2SEL | (RCC_DCKCFGR1_SAI2SEL >> 16U)) /*!< Main source clock used as SAI2 clock source */
443 #endif /* RCC_SAI2SEL_PLLSRC_SUPPORT */
444 /**
445 * @}
446 */
447
448 /** @defgroup RCC_LL_EC_SDMMCx_CLKSOURCE Peripheral SDMMC clock source selection
449 * @{
450 */
451 #define LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC1 clock */
452 #define LL_RCC_SDMMC1_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC1SEL | (RCC_DCKCFGR2_SDMMC1SEL >> 16U)) /*!< System clock clock used as SDMMC1 clock */
453 #if defined(SDMMC2)
454 #define LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | 0x00000000U) /*!< PLL 48M domain clock used as SDMMC2 clock */
455 #define LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (uint32_t)(RCC_DCKCFGR2_SDMMC2SEL | (RCC_DCKCFGR2_SDMMC2SEL >> 16U)) /*!< System clock clock used as SDMMC2 clock */
456 #endif /* SDMMC2 */
457 /**
458 * @}
459 */
460
461 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
462 * @{
463 */
464 #define LL_RCC_RNG_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as RNG clock source */
465 #define LL_RCC_RNG_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI clock used as RNG clock source */
466 /**
467 * @}
468 */
469
470 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
471 * @{
472 */
473 #define LL_RCC_USB_CLKSOURCE_PLL 0x00000000U /*!< PLL clock used as USB clock source */
474 #define LL_RCC_USB_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI1 clock used as USB clock source */
475 /**
476 * @}
477 */
478
479 #if defined(DSI)
480 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
481 * @{
482 */
483 #define LL_RCC_DSI_CLKSOURCE_PHY 0x00000000U /*!< DSI-PHY clock used as DSI byte lane clock source */
484 #define LL_RCC_DSI_CLKSOURCE_PLL RCC_DCKCFGR2_DSISEL /*!< PLL clock used as DSI byte lane clock source */
485 /**
486 * @}
487 */
488 #endif /* DSI */
489
490 #if defined(CEC)
491 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
492 * @{
493 */
494 #define LL_RCC_CEC_CLKSOURCE_LSE 0x00000000U /*!< LSE oscillator clock used as CEC clock */
495 #define LL_RCC_CEC_CLKSOURCE_HSI_DIV488 RCC_DCKCFGR2_CECSEL /*!< HSI oscillator clock divided by 488 used as CEC clock */
496 /**
497 * @}
498 */
499 #endif /* CEC */
500
501 /** @defgroup RCC_LL_EC_I2S1_CLKSOURCE Peripheral I2S clock source selection
502 * @{
503 */
504 #define LL_RCC_I2S1_CLKSOURCE_PLLI2S 0x00000000U /*!< I2S oscillator clock used as I2S1 clock */
505 #define LL_RCC_I2S1_CLKSOURCE_PIN RCC_CFGR_I2SSRC /*!< External pin clock used as I2S1 clock */
506 /**
507 * @}
508 */
509
510 /** @defgroup RCC_LL_EC_CK48M_CLKSOURCE Peripheral 48Mhz domain clock source selection
511 * @{
512 */
513 #define LL_RCC_CK48M_CLKSOURCE_PLL 0x00000000U /*!< PLL oscillator clock used as 48Mhz domain clock */
514 #define LL_RCC_CK48M_CLKSOURCE_PLLSAI RCC_DCKCFGR2_CK48MSEL /*!< PLLSAI oscillator clock used as 48Mhz domain clock */
515 /**
516 * @}
517 */
518
519 #if defined(DFSDM1_Channel0)
520 /** @defgroup RCC_LL_EC_DFSDM1_AUDIO_CLKSOURCE Peripheral DFSDM Audio clock source selection
521 * @{
522 */
523 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1 0x00000000U /*!< SAI1 clock used as DFSDM1 Audio clock */
524 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2 RCC_DCKCFGR1_ADFSDM1SEL /*!< SAI2 clock used as DFSDM1 Audio clock */
525 /**
526 * @}
527 */
528
529 /** @defgroup RCC_LL_EC_DFSDM1_CLKSOURCE Peripheral DFSDM clock source selection
530 * @{
531 */
532 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 0x00000000U /*!< PCLK2 clock used as DFSDM1 clock */
533 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK RCC_DCKCFGR1_DFSDM1SEL /*!< System clock used as DFSDM1 clock */
534 /**
535 * @}
536 */
537 #endif /* DFSDM1_Channel0 */
538
539 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
540 * @{
541 */
542 #define LL_RCC_USART1_CLKSOURCE RCC_DCKCFGR2_USART1SEL /*!< USART1 Clock source selection */
543 #define LL_RCC_USART2_CLKSOURCE RCC_DCKCFGR2_USART2SEL /*!< USART2 Clock source selection */
544 #define LL_RCC_USART3_CLKSOURCE RCC_DCKCFGR2_USART3SEL /*!< USART3 Clock source selection */
545 #define LL_RCC_USART6_CLKSOURCE RCC_DCKCFGR2_USART6SEL /*!< USART6 Clock source selection */
546 /**
547 * @}
548 */
549
550 /** @defgroup RCC_LL_EC_UARTx Peripheral UART get clock source
551 * @{
552 */
553 #define LL_RCC_UART4_CLKSOURCE RCC_DCKCFGR2_UART4SEL /*!< UART4 Clock source selection */
554 #define LL_RCC_UART5_CLKSOURCE RCC_DCKCFGR2_UART5SEL /*!< UART5 Clock source selection */
555 #define LL_RCC_UART7_CLKSOURCE RCC_DCKCFGR2_UART7SEL /*!< UART7 Clock source selection */
556 #define LL_RCC_UART8_CLKSOURCE RCC_DCKCFGR2_UART8SEL /*!< UART8 Clock source selection */
557 /**
558 * @}
559 */
560
561 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
562 * @{
563 */
564 #define LL_RCC_I2C1_CLKSOURCE RCC_DCKCFGR2_I2C1SEL /*!< I2C1 Clock source selection */
565 #define LL_RCC_I2C2_CLKSOURCE RCC_DCKCFGR2_I2C2SEL /*!< I2C2 Clock source selection */
566 #define LL_RCC_I2C3_CLKSOURCE RCC_DCKCFGR2_I2C3SEL /*!< I2C3 Clock source selection */
567 #if defined(I2C4)
568 #define LL_RCC_I2C4_CLKSOURCE RCC_DCKCFGR2_I2C4SEL /*!< I2C4 Clock source selection */
569 #endif /* I2C4 */
570 /**
571 * @}
572 */
573
574 /** @defgroup RCC_LL_EC_LPTIM1 Peripheral LPTIM get clock source
575 * @{
576 */
577 #define LL_RCC_LPTIM1_CLKSOURCE RCC_DCKCFGR2_LPTIM1SEL /*!< LPTIM1 Clock source selection */
578 /**
579 * @}
580 */
581
582 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
583 * @{
584 */
585 #define LL_RCC_SAI1_CLKSOURCE RCC_DCKCFGR1_SAI1SEL /*!< SAI1 Clock source selection */
586 #define LL_RCC_SAI2_CLKSOURCE RCC_DCKCFGR1_SAI2SEL /*!< SAI2 Clock source selection */
587 /**
588 * @}
589 */
590
591 /** @defgroup RCC_LL_EC_SDMMCx Peripheral SDMMC get clock source
592 * @{
593 */
594 #define LL_RCC_SDMMC1_CLKSOURCE RCC_DCKCFGR2_SDMMC1SEL /*!< SDMMC1 Clock source selection */
595 #if defined(SDMMC2)
596 #define LL_RCC_SDMMC2_CLKSOURCE RCC_DCKCFGR2_SDMMC2SEL /*!< SDMMC2 Clock source selection */
597 #endif /* SDMMC2 */
598 /**
599 * @}
600 */
601
602 /** @defgroup RCC_LL_EC_CK48M Peripheral CK48M get clock source
603 * @{
604 */
605 #define LL_RCC_CK48M_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< CK48M Domain clock source selection */
606 /**
607 * @}
608 */
609
610 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
611 * @{
612 */
613 #define LL_RCC_RNG_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< RNG Clock source selection */
614 /**
615 * @}
616 */
617
618 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
619 * @{
620 */
621 #define LL_RCC_USB_CLKSOURCE RCC_DCKCFGR2_CK48MSEL /*!< USB Clock source selection */
622 /**
623 * @}
624 */
625
626 #if defined(CEC)
627 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
628 * @{
629 */
630 #define LL_RCC_CEC_CLKSOURCE RCC_DCKCFGR2_CECSEL /*!< CEC Clock source selection */
631 /**
632 * @}
633 */
634 #endif /* CEC */
635
636 /** @defgroup RCC_LL_EC_I2S1 Peripheral I2S get clock source
637 * @{
638 */
639 #define LL_RCC_I2S1_CLKSOURCE RCC_CFGR_I2SSRC /*!< I2S Clock source selection */
640 /**
641 * @}
642 */
643 #if defined(DFSDM1_Channel0)
644 /** @defgroup RCC_LL_EC_DFSDM_AUDIO Peripheral DFSDM Audio get clock source
645 * @{
646 */
647 #define LL_RCC_DFSDM1_AUDIO_CLKSOURCE RCC_DCKCFGR1_ADFSDM1SEL /*!< DFSDM Audio Clock source selection */
648 /**
649 * @}
650 */
651
652 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
653 * @{
654 */
655 #define LL_RCC_DFSDM1_CLKSOURCE RCC_DCKCFGR1_DFSDM1SEL /*!< DFSDM Clock source selection */
656 /**
657 * @}
658 */
659 #endif /* DFSDM1_Channel0 */
660
661 #if defined(DSI)
662 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
663 * @{
664 */
665 #define LL_RCC_DSI_CLKSOURCE RCC_DCKCFGR2_DSISEL /*!< DSI Clock source selection */
666 /**
667 * @}
668 */
669 #endif /* DSI */
670
671 #if defined(LTDC)
672 /** @defgroup RCC_LL_EC_LTDC Peripheral LTDC get clock source
673 * @{
674 */
675 #define LL_RCC_LTDC_CLKSOURCE RCC_DCKCFGR1_PLLSAIDIVR /*!< LTDC Clock source selection */
676 /**
677 * @}
678 */
679 #endif /* LTDC */
680
681 #if defined(SPDIFRX)
682 /** @defgroup RCC_LL_EC_SPDIFRX Peripheral SPDIFRX get clock source
683 * @{
684 */
685 #define LL_RCC_SPDIFRX1_CLKSOURCE RCC_PLLI2SCFGR_PLLI2SP /*!< SPDIFRX Clock source selection */
686 /**
687 * @}
688 */
689 #endif /* SPDIFRX */
690
691 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
692 * @{
693 */
694 #define LL_RCC_RTC_CLKSOURCE_NONE 0x00000000U /*!< No clock used as RTC clock */
695 #define LL_RCC_RTC_CLKSOURCE_LSE RCC_BDCR_RTCSEL_0 /*!< LSE oscillator clock used as RTC clock */
696 #define LL_RCC_RTC_CLKSOURCE_LSI RCC_BDCR_RTCSEL_1 /*!< LSI oscillator clock used as RTC clock */
697 #define LL_RCC_RTC_CLKSOURCE_HSE RCC_BDCR_RTCSEL /*!< HSE oscillator clock divided by HSE prescaler used as RTC clock */
698 /**
699 * @}
700 */
701
702 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
703 * @{
704 */
705 #define LL_RCC_TIM_PRESCALER_TWICE 0x00000000U /*!< Timers clock to twice PCLK */
706 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES RCC_DCKCFGR1_TIMPRE /*!< Timers clock to four time PCLK */
707 /**
708 * @}
709 */
710
711 /** @defgroup RCC_LL_EC_PLLSOURCE PLL, PLLI2S and PLLSAI entry clock source
712 * @{
713 */
714 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCFGR_PLLSRC_HSI /*!< HSI16 clock selected as PLL entry clock source */
715 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCFGR_PLLSRC_HSE /*!< HSE clock selected as PLL entry clock source */
716 /**
717 * @}
718 */
719
720 /** @defgroup RCC_LL_EC_PLLM_DIV PLL, PLLI2S and PLLSAI division factor
721 * @{
722 */
723 #define LL_RCC_PLLM_DIV_2 (RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 2 */
724 #define LL_RCC_PLLM_DIV_3 (RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 3 */
725 #define LL_RCC_PLLM_DIV_4 (RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 4 */
726 #define LL_RCC_PLLM_DIV_5 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 5 */
727 #define LL_RCC_PLLM_DIV_6 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 6 */
728 #define LL_RCC_PLLM_DIV_7 (RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 7 */
729 #define LL_RCC_PLLM_DIV_8 (RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 8 */
730 #define LL_RCC_PLLM_DIV_9 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 9 */
731 #define LL_RCC_PLLM_DIV_10 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 10 */
732 #define LL_RCC_PLLM_DIV_11 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 11 */
733 #define LL_RCC_PLLM_DIV_12 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 12 */
734 #define LL_RCC_PLLM_DIV_13 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 13 */
735 #define LL_RCC_PLLM_DIV_14 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 14 */
736 #define LL_RCC_PLLM_DIV_15 (RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 15 */
737 #define LL_RCC_PLLM_DIV_16 (RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 16 */
738 #define LL_RCC_PLLM_DIV_17 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 17 */
739 #define LL_RCC_PLLM_DIV_18 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 18 */
740 #define LL_RCC_PLLM_DIV_19 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 19 */
741 #define LL_RCC_PLLM_DIV_20 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 20 */
742 #define LL_RCC_PLLM_DIV_21 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 21 */
743 #define LL_RCC_PLLM_DIV_22 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 22 */
744 #define LL_RCC_PLLM_DIV_23 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 23 */
745 #define LL_RCC_PLLM_DIV_24 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 24 */
746 #define LL_RCC_PLLM_DIV_25 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 25 */
747 #define LL_RCC_PLLM_DIV_26 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 26 */
748 #define LL_RCC_PLLM_DIV_27 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 27 */
749 #define LL_RCC_PLLM_DIV_28 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 28 */
750 #define LL_RCC_PLLM_DIV_29 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 29 */
751 #define LL_RCC_PLLM_DIV_30 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 30 */
752 #define LL_RCC_PLLM_DIV_31 (RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 31 */
753 #define LL_RCC_PLLM_DIV_32 (RCC_PLLCFGR_PLLM_5) /*!< PLL, PLLI2S and PLLSAI division factor by 32 */
754 #define LL_RCC_PLLM_DIV_33 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 33 */
755 #define LL_RCC_PLLM_DIV_34 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 34 */
756 #define LL_RCC_PLLM_DIV_35 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 35 */
757 #define LL_RCC_PLLM_DIV_36 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 36 */
758 #define LL_RCC_PLLM_DIV_37 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 37 */
759 #define LL_RCC_PLLM_DIV_38 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 38 */
760 #define LL_RCC_PLLM_DIV_39 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 39 */
761 #define LL_RCC_PLLM_DIV_40 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 40 */
762 #define LL_RCC_PLLM_DIV_41 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 41 */
763 #define LL_RCC_PLLM_DIV_42 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 42 */
764 #define LL_RCC_PLLM_DIV_43 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 43 */
765 #define LL_RCC_PLLM_DIV_44 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 44 */
766 #define LL_RCC_PLLM_DIV_45 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 45 */
767 #define LL_RCC_PLLM_DIV_46 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 46 */
768 #define LL_RCC_PLLM_DIV_47 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 47 */
769 #define LL_RCC_PLLM_DIV_48 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4) /*!< PLL, PLLI2S and PLLSAI division factor by 48 */
770 #define LL_RCC_PLLM_DIV_49 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 49 */
771 #define LL_RCC_PLLM_DIV_50 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 50 */
772 #define LL_RCC_PLLM_DIV_51 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 51 */
773 #define LL_RCC_PLLM_DIV_52 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 52 */
774 #define LL_RCC_PLLM_DIV_53 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 53 */
775 #define LL_RCC_PLLM_DIV_54 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 54 */
776 #define LL_RCC_PLLM_DIV_55 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 55 */
777 #define LL_RCC_PLLM_DIV_56 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3) /*!< PLL, PLLI2S and PLLSAI division factor by 56 */
778 #define LL_RCC_PLLM_DIV_57 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 57 */
779 #define LL_RCC_PLLM_DIV_58 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 58 */
780 #define LL_RCC_PLLM_DIV_59 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 59 */
781 #define LL_RCC_PLLM_DIV_60 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2) /*!< PLL, PLLI2S and PLLSAI division factor by 60 */
782 #define LL_RCC_PLLM_DIV_61 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 61 */
783 #define LL_RCC_PLLM_DIV_62 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1) /*!< PLL, PLLI2S and PLLSAI division factor by 62 */
784 #define LL_RCC_PLLM_DIV_63 (RCC_PLLCFGR_PLLM_5 | RCC_PLLCFGR_PLLM_4 | RCC_PLLCFGR_PLLM_3 | RCC_PLLCFGR_PLLM_2 | RCC_PLLCFGR_PLLM_1 | RCC_PLLCFGR_PLLM_0) /*!< PLL, PLLI2S and PLLSAI division factor by 63 */
785 /**
786 * @}
787 */
788
789 #if defined(RCC_PLLCFGR_PLLR)
790 /** @defgroup RCC_LL_EC_PLLR_DIV PLL division factor (PLLR)
791 * @{
792 */
793 #define LL_RCC_PLLR_DIV_2 (RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 2 */
794 #define LL_RCC_PLLR_DIV_3 (RCC_PLLCFGR_PLLR_1|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 3 */
795 #define LL_RCC_PLLR_DIV_4 (RCC_PLLCFGR_PLLR_2) /*!< Main PLL division factor for PLLCLK (system clock) by 4 */
796 #define LL_RCC_PLLR_DIV_5 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_0) /*!< Main PLL division factor for PLLCLK (system clock) by 5 */
797 #define LL_RCC_PLLR_DIV_6 (RCC_PLLCFGR_PLLR_2|RCC_PLLCFGR_PLLR_1) /*!< Main PLL division factor for PLLCLK (system clock) by 6 */
798 #define LL_RCC_PLLR_DIV_7 (RCC_PLLCFGR_PLLR) /*!< Main PLL division factor for PLLCLK (system clock) by 7 */
799 /**
800 * @}
801 */
802 #endif /* RCC_PLLCFGR_PLLR */
803
804 /** @defgroup RCC_LL_EC_PLLP_DIV PLL division factor (PLLP)
805 * @{
806 */
807 #define LL_RCC_PLLP_DIV_2 0x00000000U /*!< Main PLL division factor for PLLP output by 2 */
808 #define LL_RCC_PLLP_DIV_4 RCC_PLLCFGR_PLLP_0 /*!< Main PLL division factor for PLLP output by 4 */
809 #define LL_RCC_PLLP_DIV_6 RCC_PLLCFGR_PLLP_1 /*!< Main PLL division factor for PLLP output by 6 */
810 #define LL_RCC_PLLP_DIV_8 (RCC_PLLCFGR_PLLP_1 | RCC_PLLCFGR_PLLP_0) /*!< Main PLL division factor for PLLP output by 8 */
811 /**
812 * @}
813 */
814
815 /** @defgroup RCC_LL_EC_PLLQ_DIV PLL division factor (PLLQ)
816 * @{
817 */
818 #define LL_RCC_PLLQ_DIV_2 RCC_PLLCFGR_PLLQ_1 /*!< Main PLL division factor for PLLQ output by 2 */
819 #define LL_RCC_PLLQ_DIV_3 (RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 3 */
820 #define LL_RCC_PLLQ_DIV_4 RCC_PLLCFGR_PLLQ_2 /*!< Main PLL division factor for PLLQ output by 4 */
821 #define LL_RCC_PLLQ_DIV_5 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 5 */
822 #define LL_RCC_PLLQ_DIV_6 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 6 */
823 #define LL_RCC_PLLQ_DIV_7 (RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 7 */
824 #define LL_RCC_PLLQ_DIV_8 RCC_PLLCFGR_PLLQ_3 /*!< Main PLL division factor for PLLQ output by 8 */
825 #define LL_RCC_PLLQ_DIV_9 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 9 */
826 #define LL_RCC_PLLQ_DIV_10 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 10 */
827 #define LL_RCC_PLLQ_DIV_11 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 11 */
828 #define LL_RCC_PLLQ_DIV_12 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2) /*!< Main PLL division factor for PLLQ output by 12 */
829 #define LL_RCC_PLLQ_DIV_13 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 13 */
830 #define LL_RCC_PLLQ_DIV_14 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1) /*!< Main PLL division factor for PLLQ output by 14 */
831 #define LL_RCC_PLLQ_DIV_15 (RCC_PLLCFGR_PLLQ_3|RCC_PLLCFGR_PLLQ_2|RCC_PLLCFGR_PLLQ_1|RCC_PLLCFGR_PLLQ_0) /*!< Main PLL division factor for PLLQ output by 15 */
832 /**
833 * @}
834 */
835
836 /** @defgroup RCC_LL_EC_PLL_SPRE_SEL PLL Spread Spectrum Selection
837 * @{
838 */
839 #define LL_RCC_SPREAD_SELECT_CENTER 0x00000000U /*!< PLL center spread spectrum selection */
840 #define LL_RCC_SPREAD_SELECT_DOWN RCC_SSCGR_SPREADSEL /*!< PLL down spread spectrum selection */
841 /**
842 * @}
843 */
844
845 /** @defgroup RCC_LL_EC_PLLI2SQ PLLI2SQ division factor (PLLI2SQ)
846 * @{
847 */
848 #define LL_RCC_PLLI2SQ_DIV_2 RCC_PLLI2SCFGR_PLLI2SQ_1 /*!< PLLI2S division factor for PLLI2SQ output by 2 */
849 #define LL_RCC_PLLI2SQ_DIV_3 (RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 3 */
850 #define LL_RCC_PLLI2SQ_DIV_4 RCC_PLLI2SCFGR_PLLI2SQ_2 /*!< PLLI2S division factor for PLLI2SQ output by 4 */
851 #define LL_RCC_PLLI2SQ_DIV_5 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 5 */
852 #define LL_RCC_PLLI2SQ_DIV_6 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 6 */
853 #define LL_RCC_PLLI2SQ_DIV_7 (RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 7 */
854 #define LL_RCC_PLLI2SQ_DIV_8 RCC_PLLI2SCFGR_PLLI2SQ_3 /*!< PLLI2S division factor for PLLI2SQ output by 8 */
855 #define LL_RCC_PLLI2SQ_DIV_9 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 9 */
856 #define LL_RCC_PLLI2SQ_DIV_10 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 10 */
857 #define LL_RCC_PLLI2SQ_DIV_11 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 11 */
858 #define LL_RCC_PLLI2SQ_DIV_12 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2) /*!< PLLI2S division factor for PLLI2SQ output by 12 */
859 #define LL_RCC_PLLI2SQ_DIV_13 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 13 */
860 #define LL_RCC_PLLI2SQ_DIV_14 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1) /*!< PLLI2S division factor for PLLI2SQ output by 14 */
861 #define LL_RCC_PLLI2SQ_DIV_15 (RCC_PLLI2SCFGR_PLLI2SQ_3 | RCC_PLLI2SCFGR_PLLI2SQ_2 | RCC_PLLI2SCFGR_PLLI2SQ_1 | RCC_PLLI2SCFGR_PLLI2SQ_0) /*!< PLLI2S division factor for PLLI2SQ output by 15 */
862 /**
863 * @}
864 */
865
866 /** @defgroup RCC_LL_EC_PLLI2SDIVQ PLLI2SDIVQ division factor (PLLI2SDIVQ)
867 * @{
868 */
869 #define LL_RCC_PLLI2SDIVQ_DIV_1 0x00000000U /*!< PLLI2S division factor for PLLI2SDIVQ output by 1 */
870 #define LL_RCC_PLLI2SDIVQ_DIV_2 RCC_DCKCFGR1_PLLI2SDIVQ_0 /*!< PLLI2S division factor for PLLI2SDIVQ output by 2 */
871 #define LL_RCC_PLLI2SDIVQ_DIV_3 RCC_DCKCFGR1_PLLI2SDIVQ_1 /*!< PLLI2S division factor for PLLI2SDIVQ output by 3 */
872 #define LL_RCC_PLLI2SDIVQ_DIV_4 (RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 4 */
873 #define LL_RCC_PLLI2SDIVQ_DIV_5 RCC_DCKCFGR1_PLLI2SDIVQ_2 /*!< PLLI2S division factor for PLLI2SDIVQ output by 5 */
874 #define LL_RCC_PLLI2SDIVQ_DIV_6 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 6 */
875 #define LL_RCC_PLLI2SDIVQ_DIV_7 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 7 */
876 #define LL_RCC_PLLI2SDIVQ_DIV_8 (RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 8 */
877 #define LL_RCC_PLLI2SDIVQ_DIV_9 RCC_DCKCFGR1_PLLI2SDIVQ_3 /*!< PLLI2S division factor for PLLI2SDIVQ output by 9 */
878 #define LL_RCC_PLLI2SDIVQ_DIV_10 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 10 */
879 #define LL_RCC_PLLI2SDIVQ_DIV_11 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 11 */
880 #define LL_RCC_PLLI2SDIVQ_DIV_12 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 12 */
881 #define LL_RCC_PLLI2SDIVQ_DIV_13 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 13 */
882 #define LL_RCC_PLLI2SDIVQ_DIV_14 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 14 */
883 #define LL_RCC_PLLI2SDIVQ_DIV_15 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 15 */
884 #define LL_RCC_PLLI2SDIVQ_DIV_16 (RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 16 */
885 #define LL_RCC_PLLI2SDIVQ_DIV_17 RCC_DCKCFGR1_PLLI2SDIVQ_4 /*!< PLLI2S division factor for PLLI2SDIVQ output by 17 */
886 #define LL_RCC_PLLI2SDIVQ_DIV_18 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 18 */
887 #define LL_RCC_PLLI2SDIVQ_DIV_19 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 19 */
888 #define LL_RCC_PLLI2SDIVQ_DIV_20 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 20 */
889 #define LL_RCC_PLLI2SDIVQ_DIV_21 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 21 */
890 #define LL_RCC_PLLI2SDIVQ_DIV_22 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 22 */
891 #define LL_RCC_PLLI2SDIVQ_DIV_23 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 23 */
892 #define LL_RCC_PLLI2SDIVQ_DIV_24 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 24 */
893 #define LL_RCC_PLLI2SDIVQ_DIV_25 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3) /*!< PLLI2S division factor for PLLI2SDIVQ output by 25 */
894 #define LL_RCC_PLLI2SDIVQ_DIV_26 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 26 */
895 #define LL_RCC_PLLI2SDIVQ_DIV_27 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 27 */
896 #define LL_RCC_PLLI2SDIVQ_DIV_28 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 28 */
897 #define LL_RCC_PLLI2SDIVQ_DIV_29 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2) /*!< PLLI2S division factor for PLLI2SDIVQ output by 29 */
898 #define LL_RCC_PLLI2SDIVQ_DIV_30 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 30 */
899 #define LL_RCC_PLLI2SDIVQ_DIV_31 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1) /*!< PLLI2S division factor for PLLI2SDIVQ output by 31 */
900 #define LL_RCC_PLLI2SDIVQ_DIV_32 (RCC_DCKCFGR1_PLLI2SDIVQ_4 | RCC_DCKCFGR1_PLLI2SDIVQ_3 | RCC_DCKCFGR1_PLLI2SDIVQ_2 | RCC_DCKCFGR1_PLLI2SDIVQ_1 | RCC_DCKCFGR1_PLLI2SDIVQ_0) /*!< PLLI2S division factor for PLLI2SDIVQ output by 32 */
901 /**
902 * @}
903 */
904
905 /** @defgroup RCC_LL_EC_PLLI2SR PLLI2SR division factor (PLLI2SR)
906 * @{
907 */
908 #define LL_RCC_PLLI2SR_DIV_2 RCC_PLLI2SCFGR_PLLI2SR_1 /*!< PLLI2S division factor for PLLI2SR output by 2 */
909 #define LL_RCC_PLLI2SR_DIV_3 (RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 3 */
910 #define LL_RCC_PLLI2SR_DIV_4 RCC_PLLI2SCFGR_PLLI2SR_2 /*!< PLLI2S division factor for PLLI2SR output by 4 */
911 #define LL_RCC_PLLI2SR_DIV_5 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 5 */
912 #define LL_RCC_PLLI2SR_DIV_6 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1) /*!< PLLI2S division factor for PLLI2SR output by 6 */
913 #define LL_RCC_PLLI2SR_DIV_7 (RCC_PLLI2SCFGR_PLLI2SR_2 | RCC_PLLI2SCFGR_PLLI2SR_1 | RCC_PLLI2SCFGR_PLLI2SR_0) /*!< PLLI2S division factor for PLLI2SR output by 7 */
914 /**
915 * @}
916 */
917
918 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
919 /** @defgroup RCC_LL_EC_PLLI2SP PLLI2SP division factor (PLLI2SP)
920 * @{
921 */
922 #define LL_RCC_PLLI2SP_DIV_2 0x00000000U /*!< PLLI2S division factor for PLLI2SP output by 2 */
923 #define LL_RCC_PLLI2SP_DIV_4 RCC_PLLI2SCFGR_PLLI2SP_0 /*!< PLLI2S division factor for PLLI2SP output by 4 */
924 #define LL_RCC_PLLI2SP_DIV_6 RCC_PLLI2SCFGR_PLLI2SP_1 /*!< PLLI2S division factor for PLLI2SP output by 6 */
925 #define LL_RCC_PLLI2SP_DIV_8 (RCC_PLLI2SCFGR_PLLI2SP_1 | RCC_PLLI2SCFGR_PLLI2SP_0) /*!< PLLI2S division factor for PLLI2SP output by 8 */
926 /**
927 * @}
928 */
929 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
930
931 /** @defgroup RCC_LL_EC_PLLSAIQ PLLSAIQ division factor (PLLSAIQ)
932 * @{
933 */
934 #define LL_RCC_PLLSAIQ_DIV_2 RCC_PLLSAICFGR_PLLSAIQ_1 /*!< PLLSAI division factor for PLLSAIQ output by 2 */
935 #define LL_RCC_PLLSAIQ_DIV_3 (RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 3 */
936 #define LL_RCC_PLLSAIQ_DIV_4 RCC_PLLSAICFGR_PLLSAIQ_2 /*!< PLLSAI division factor for PLLSAIQ output by 4 */
937 #define LL_RCC_PLLSAIQ_DIV_5 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 5 */
938 #define LL_RCC_PLLSAIQ_DIV_6 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 6 */
939 #define LL_RCC_PLLSAIQ_DIV_7 (RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 7 */
940 #define LL_RCC_PLLSAIQ_DIV_8 RCC_PLLSAICFGR_PLLSAIQ_3 /*!< PLLSAI division factor for PLLSAIQ output by 8 */
941 #define LL_RCC_PLLSAIQ_DIV_9 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 9 */
942 #define LL_RCC_PLLSAIQ_DIV_10 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 10 */
943 #define LL_RCC_PLLSAIQ_DIV_11 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 11 */
944 #define LL_RCC_PLLSAIQ_DIV_12 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2) /*!< PLLSAI division factor for PLLSAIQ output by 12 */
945 #define LL_RCC_PLLSAIQ_DIV_13 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 13 */
946 #define LL_RCC_PLLSAIQ_DIV_14 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1) /*!< PLLSAI division factor for PLLSAIQ output by 14 */
947 #define LL_RCC_PLLSAIQ_DIV_15 (RCC_PLLSAICFGR_PLLSAIQ_3 | RCC_PLLSAICFGR_PLLSAIQ_2 | RCC_PLLSAICFGR_PLLSAIQ_1 | RCC_PLLSAICFGR_PLLSAIQ_0) /*!< PLLSAI division factor for PLLSAIQ output by 15 */
948 /**
949 * @}
950 */
951
952 /** @defgroup RCC_LL_EC_PLLSAIDIVQ PLLSAIDIVQ division factor (PLLSAIDIVQ)
953 * @{
954 */
955 #define LL_RCC_PLLSAIDIVQ_DIV_1 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVQ output by 1 */
956 #define LL_RCC_PLLSAIDIVQ_DIV_2 RCC_DCKCFGR1_PLLSAIDIVQ_0 /*!< PLLSAI division factor for PLLSAIDIVQ output by 2 */
957 #define LL_RCC_PLLSAIDIVQ_DIV_3 RCC_DCKCFGR1_PLLSAIDIVQ_1 /*!< PLLSAI division factor for PLLSAIDIVQ output by 3 */
958 #define LL_RCC_PLLSAIDIVQ_DIV_4 (RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 4 */
959 #define LL_RCC_PLLSAIDIVQ_DIV_5 RCC_DCKCFGR1_PLLSAIDIVQ_2 /*!< PLLSAI division factor for PLLSAIDIVQ output by 5 */
960 #define LL_RCC_PLLSAIDIVQ_DIV_6 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 6 */
961 #define LL_RCC_PLLSAIDIVQ_DIV_7 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 7 */
962 #define LL_RCC_PLLSAIDIVQ_DIV_8 (RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 8 */
963 #define LL_RCC_PLLSAIDIVQ_DIV_9 RCC_DCKCFGR1_PLLSAIDIVQ_3 /*!< PLLSAI division factor for PLLSAIDIVQ output by 9 */
964 #define LL_RCC_PLLSAIDIVQ_DIV_10 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 10 */
965 #define LL_RCC_PLLSAIDIVQ_DIV_11 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 11 */
966 #define LL_RCC_PLLSAIDIVQ_DIV_12 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 12 */
967 #define LL_RCC_PLLSAIDIVQ_DIV_13 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 13 */
968 #define LL_RCC_PLLSAIDIVQ_DIV_14 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 14 */
969 #define LL_RCC_PLLSAIDIVQ_DIV_15 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 15 */
970 #define LL_RCC_PLLSAIDIVQ_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 16 */
971 #define LL_RCC_PLLSAIDIVQ_DIV_17 RCC_DCKCFGR1_PLLSAIDIVQ_4 /*!< PLLSAI division factor for PLLSAIDIVQ output by 17 */
972 #define LL_RCC_PLLSAIDIVQ_DIV_18 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 18 */
973 #define LL_RCC_PLLSAIDIVQ_DIV_19 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 19 */
974 #define LL_RCC_PLLSAIDIVQ_DIV_20 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 20 */
975 #define LL_RCC_PLLSAIDIVQ_DIV_21 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 21 */
976 #define LL_RCC_PLLSAIDIVQ_DIV_22 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 22 */
977 #define LL_RCC_PLLSAIDIVQ_DIV_23 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 23 */
978 #define LL_RCC_PLLSAIDIVQ_DIV_24 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 24 */
979 #define LL_RCC_PLLSAIDIVQ_DIV_25 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3) /*!< PLLSAI division factor for PLLSAIDIVQ output by 25 */
980 #define LL_RCC_PLLSAIDIVQ_DIV_26 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 26 */
981 #define LL_RCC_PLLSAIDIVQ_DIV_27 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 27 */
982 #define LL_RCC_PLLSAIDIVQ_DIV_28 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 28 */
983 #define LL_RCC_PLLSAIDIVQ_DIV_29 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2) /*!< PLLSAI division factor for PLLSAIDIVQ output by 29 */
984 #define LL_RCC_PLLSAIDIVQ_DIV_30 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 30 */
985 #define LL_RCC_PLLSAIDIVQ_DIV_31 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1) /*!< PLLSAI division factor for PLLSAIDIVQ output by 31 */
986 #define LL_RCC_PLLSAIDIVQ_DIV_32 (RCC_DCKCFGR1_PLLSAIDIVQ_4 | RCC_DCKCFGR1_PLLSAIDIVQ_3 | RCC_DCKCFGR1_PLLSAIDIVQ_2 | RCC_DCKCFGR1_PLLSAIDIVQ_1 | RCC_DCKCFGR1_PLLSAIDIVQ_0) /*!< PLLSAI division factor for PLLSAIDIVQ output by 32 */
987 /**
988 * @}
989 */
990
991 #if defined(RCC_PLLSAICFGR_PLLSAIR)
992 /** @defgroup RCC_LL_EC_PLLSAIR PLLSAIR division factor (PLLSAIR)
993 * @{
994 */
995 #define LL_RCC_PLLSAIR_DIV_2 RCC_PLLSAICFGR_PLLSAIR_1 /*!< PLLSAI division factor for PLLSAIR output by 2 */
996 #define LL_RCC_PLLSAIR_DIV_3 (RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 3 */
997 #define LL_RCC_PLLSAIR_DIV_4 RCC_PLLSAICFGR_PLLSAIR_2 /*!< PLLSAI division factor for PLLSAIR output by 4 */
998 #define LL_RCC_PLLSAIR_DIV_5 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 5 */
999 #define LL_RCC_PLLSAIR_DIV_6 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1) /*!< PLLSAI division factor for PLLSAIR output by 6 */
1000 #define LL_RCC_PLLSAIR_DIV_7 (RCC_PLLSAICFGR_PLLSAIR_2 | RCC_PLLSAICFGR_PLLSAIR_1 | RCC_PLLSAICFGR_PLLSAIR_0) /*!< PLLSAI division factor for PLLSAIR output by 7 */
1001 /**
1002 * @}
1003 */
1004 #endif /* RCC_PLLSAICFGR_PLLSAIR */
1005
1006 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
1007 /** @defgroup RCC_LL_EC_PLLSAIDIVR PLLSAIDIVR division factor (PLLSAIDIVR)
1008 * @{
1009 */
1010 #define LL_RCC_PLLSAIDIVR_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIDIVR output by 2 */
1011 #define LL_RCC_PLLSAIDIVR_DIV_4 RCC_DCKCFGR1_PLLSAIDIVR_0 /*!< PLLSAI division factor for PLLSAIDIVR output by 4 */
1012 #define LL_RCC_PLLSAIDIVR_DIV_8 RCC_DCKCFGR1_PLLSAIDIVR_1 /*!< PLLSAI division factor for PLLSAIDIVR output by 8 */
1013 #define LL_RCC_PLLSAIDIVR_DIV_16 (RCC_DCKCFGR1_PLLSAIDIVR_1 | RCC_DCKCFGR1_PLLSAIDIVR_0) /*!< PLLSAI division factor for PLLSAIDIVR output by 16 */
1014 /**
1015 * @}
1016 */
1017 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
1018
1019 /** @defgroup RCC_LL_EC_PLLSAIP PLLSAIP division factor (PLLSAIP)
1020 * @{
1021 */
1022 #define LL_RCC_PLLSAIP_DIV_2 0x00000000U /*!< PLLSAI division factor for PLLSAIP output by 2 */
1023 #define LL_RCC_PLLSAIP_DIV_4 RCC_PLLSAICFGR_PLLSAIP_0 /*!< PLLSAI division factor for PLLSAIP output by 4 */
1024 #define LL_RCC_PLLSAIP_DIV_6 RCC_PLLSAICFGR_PLLSAIP_1 /*!< PLLSAI division factor for PLLSAIP output by 6 */
1025 #define LL_RCC_PLLSAIP_DIV_8 (RCC_PLLSAICFGR_PLLSAIP_1 | RCC_PLLSAICFGR_PLLSAIP_0) /*!< PLLSAI division factor for PLLSAIP output by 8 */
1026 /**
1027 * @}
1028 */
1029
1030 /**
1031 * @}
1032 */
1033
1034 /* Exported macro ------------------------------------------------------------*/
1035 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1036 * @{
1037 */
1038
1039 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1040 * @{
1041 */
1042
1043 /**
1044 * @brief Write a value in RCC register
1045 * @param __REG__ Register to be written
1046 * @param __VALUE__ Value to be written in the register
1047 * @retval None
1048 */
1049 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1050
1051 /**
1052 * @brief Read a value in RCC register
1053 * @param __REG__ Register to be read
1054 * @retval Register value
1055 */
1056 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1057 /**
1058 * @}
1059 */
1060
1061 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1062 * @{
1063 */
1064
1065 /**
1066 * @brief Helper macro to calculate the PLLCLK frequency on system domain
1067 * @note ex: @ref __LL_RCC_CALC_PLLCLK_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1068 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetP ());
1069 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1070 * @param __PLLM__ This parameter can be one of the following values:
1071 * @arg @ref LL_RCC_PLLM_DIV_2
1072 * @arg @ref LL_RCC_PLLM_DIV_3
1073 * @arg @ref LL_RCC_PLLM_DIV_4
1074 * @arg @ref LL_RCC_PLLM_DIV_5
1075 * @arg @ref LL_RCC_PLLM_DIV_6
1076 * @arg @ref LL_RCC_PLLM_DIV_7
1077 * @arg @ref LL_RCC_PLLM_DIV_8
1078 * @arg @ref LL_RCC_PLLM_DIV_9
1079 * @arg @ref LL_RCC_PLLM_DIV_10
1080 * @arg @ref LL_RCC_PLLM_DIV_11
1081 * @arg @ref LL_RCC_PLLM_DIV_12
1082 * @arg @ref LL_RCC_PLLM_DIV_13
1083 * @arg @ref LL_RCC_PLLM_DIV_14
1084 * @arg @ref LL_RCC_PLLM_DIV_15
1085 * @arg @ref LL_RCC_PLLM_DIV_16
1086 * @arg @ref LL_RCC_PLLM_DIV_17
1087 * @arg @ref LL_RCC_PLLM_DIV_18
1088 * @arg @ref LL_RCC_PLLM_DIV_19
1089 * @arg @ref LL_RCC_PLLM_DIV_20
1090 * @arg @ref LL_RCC_PLLM_DIV_21
1091 * @arg @ref LL_RCC_PLLM_DIV_22
1092 * @arg @ref LL_RCC_PLLM_DIV_23
1093 * @arg @ref LL_RCC_PLLM_DIV_24
1094 * @arg @ref LL_RCC_PLLM_DIV_25
1095 * @arg @ref LL_RCC_PLLM_DIV_26
1096 * @arg @ref LL_RCC_PLLM_DIV_27
1097 * @arg @ref LL_RCC_PLLM_DIV_28
1098 * @arg @ref LL_RCC_PLLM_DIV_29
1099 * @arg @ref LL_RCC_PLLM_DIV_30
1100 * @arg @ref LL_RCC_PLLM_DIV_31
1101 * @arg @ref LL_RCC_PLLM_DIV_32
1102 * @arg @ref LL_RCC_PLLM_DIV_33
1103 * @arg @ref LL_RCC_PLLM_DIV_34
1104 * @arg @ref LL_RCC_PLLM_DIV_35
1105 * @arg @ref LL_RCC_PLLM_DIV_36
1106 * @arg @ref LL_RCC_PLLM_DIV_37
1107 * @arg @ref LL_RCC_PLLM_DIV_38
1108 * @arg @ref LL_RCC_PLLM_DIV_39
1109 * @arg @ref LL_RCC_PLLM_DIV_40
1110 * @arg @ref LL_RCC_PLLM_DIV_41
1111 * @arg @ref LL_RCC_PLLM_DIV_42
1112 * @arg @ref LL_RCC_PLLM_DIV_43
1113 * @arg @ref LL_RCC_PLLM_DIV_44
1114 * @arg @ref LL_RCC_PLLM_DIV_45
1115 * @arg @ref LL_RCC_PLLM_DIV_46
1116 * @arg @ref LL_RCC_PLLM_DIV_47
1117 * @arg @ref LL_RCC_PLLM_DIV_48
1118 * @arg @ref LL_RCC_PLLM_DIV_49
1119 * @arg @ref LL_RCC_PLLM_DIV_50
1120 * @arg @ref LL_RCC_PLLM_DIV_51
1121 * @arg @ref LL_RCC_PLLM_DIV_52
1122 * @arg @ref LL_RCC_PLLM_DIV_53
1123 * @arg @ref LL_RCC_PLLM_DIV_54
1124 * @arg @ref LL_RCC_PLLM_DIV_55
1125 * @arg @ref LL_RCC_PLLM_DIV_56
1126 * @arg @ref LL_RCC_PLLM_DIV_57
1127 * @arg @ref LL_RCC_PLLM_DIV_58
1128 * @arg @ref LL_RCC_PLLM_DIV_59
1129 * @arg @ref LL_RCC_PLLM_DIV_60
1130 * @arg @ref LL_RCC_PLLM_DIV_61
1131 * @arg @ref LL_RCC_PLLM_DIV_62
1132 * @arg @ref LL_RCC_PLLM_DIV_63
1133 * @param __PLLN__ Between 50 and 432
1134 * @param __PLLP__ This parameter can be one of the following values:
1135 * @arg @ref LL_RCC_PLLP_DIV_2
1136 * @arg @ref LL_RCC_PLLP_DIV_4
1137 * @arg @ref LL_RCC_PLLP_DIV_6
1138 * @arg @ref LL_RCC_PLLP_DIV_8
1139 * @retval PLL clock frequency (in Hz)
1140 */
1141 #define __LL_RCC_CALC_PLLCLK_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLP__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1142 ((((__PLLP__) >> RCC_PLLCFGR_PLLP_Pos ) + 1U) * 2U))
1143
1144 /**
1145 * @brief Helper macro to calculate the PLLCLK frequency used on 48M domain
1146 * @note ex: @ref __LL_RCC_CALC_PLLCLK_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1147 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetQ ());
1148 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1149 * @param __PLLM__ This parameter can be one of the following values:
1150 * @arg @ref LL_RCC_PLLM_DIV_2
1151 * @arg @ref LL_RCC_PLLM_DIV_3
1152 * @arg @ref LL_RCC_PLLM_DIV_4
1153 * @arg @ref LL_RCC_PLLM_DIV_5
1154 * @arg @ref LL_RCC_PLLM_DIV_6
1155 * @arg @ref LL_RCC_PLLM_DIV_7
1156 * @arg @ref LL_RCC_PLLM_DIV_8
1157 * @arg @ref LL_RCC_PLLM_DIV_9
1158 * @arg @ref LL_RCC_PLLM_DIV_10
1159 * @arg @ref LL_RCC_PLLM_DIV_11
1160 * @arg @ref LL_RCC_PLLM_DIV_12
1161 * @arg @ref LL_RCC_PLLM_DIV_13
1162 * @arg @ref LL_RCC_PLLM_DIV_14
1163 * @arg @ref LL_RCC_PLLM_DIV_15
1164 * @arg @ref LL_RCC_PLLM_DIV_16
1165 * @arg @ref LL_RCC_PLLM_DIV_17
1166 * @arg @ref LL_RCC_PLLM_DIV_18
1167 * @arg @ref LL_RCC_PLLM_DIV_19
1168 * @arg @ref LL_RCC_PLLM_DIV_20
1169 * @arg @ref LL_RCC_PLLM_DIV_21
1170 * @arg @ref LL_RCC_PLLM_DIV_22
1171 * @arg @ref LL_RCC_PLLM_DIV_23
1172 * @arg @ref LL_RCC_PLLM_DIV_24
1173 * @arg @ref LL_RCC_PLLM_DIV_25
1174 * @arg @ref LL_RCC_PLLM_DIV_26
1175 * @arg @ref LL_RCC_PLLM_DIV_27
1176 * @arg @ref LL_RCC_PLLM_DIV_28
1177 * @arg @ref LL_RCC_PLLM_DIV_29
1178 * @arg @ref LL_RCC_PLLM_DIV_30
1179 * @arg @ref LL_RCC_PLLM_DIV_31
1180 * @arg @ref LL_RCC_PLLM_DIV_32
1181 * @arg @ref LL_RCC_PLLM_DIV_33
1182 * @arg @ref LL_RCC_PLLM_DIV_34
1183 * @arg @ref LL_RCC_PLLM_DIV_35
1184 * @arg @ref LL_RCC_PLLM_DIV_36
1185 * @arg @ref LL_RCC_PLLM_DIV_37
1186 * @arg @ref LL_RCC_PLLM_DIV_38
1187 * @arg @ref LL_RCC_PLLM_DIV_39
1188 * @arg @ref LL_RCC_PLLM_DIV_40
1189 * @arg @ref LL_RCC_PLLM_DIV_41
1190 * @arg @ref LL_RCC_PLLM_DIV_42
1191 * @arg @ref LL_RCC_PLLM_DIV_43
1192 * @arg @ref LL_RCC_PLLM_DIV_44
1193 * @arg @ref LL_RCC_PLLM_DIV_45
1194 * @arg @ref LL_RCC_PLLM_DIV_46
1195 * @arg @ref LL_RCC_PLLM_DIV_47
1196 * @arg @ref LL_RCC_PLLM_DIV_48
1197 * @arg @ref LL_RCC_PLLM_DIV_49
1198 * @arg @ref LL_RCC_PLLM_DIV_50
1199 * @arg @ref LL_RCC_PLLM_DIV_51
1200 * @arg @ref LL_RCC_PLLM_DIV_52
1201 * @arg @ref LL_RCC_PLLM_DIV_53
1202 * @arg @ref LL_RCC_PLLM_DIV_54
1203 * @arg @ref LL_RCC_PLLM_DIV_55
1204 * @arg @ref LL_RCC_PLLM_DIV_56
1205 * @arg @ref LL_RCC_PLLM_DIV_57
1206 * @arg @ref LL_RCC_PLLM_DIV_58
1207 * @arg @ref LL_RCC_PLLM_DIV_59
1208 * @arg @ref LL_RCC_PLLM_DIV_60
1209 * @arg @ref LL_RCC_PLLM_DIV_61
1210 * @arg @ref LL_RCC_PLLM_DIV_62
1211 * @arg @ref LL_RCC_PLLM_DIV_63
1212 * @param __PLLN__ Between 50 and 432
1213 * @param __PLLQ__ This parameter can be one of the following values:
1214 * @arg @ref LL_RCC_PLLQ_DIV_2
1215 * @arg @ref LL_RCC_PLLQ_DIV_3
1216 * @arg @ref LL_RCC_PLLQ_DIV_4
1217 * @arg @ref LL_RCC_PLLQ_DIV_5
1218 * @arg @ref LL_RCC_PLLQ_DIV_6
1219 * @arg @ref LL_RCC_PLLQ_DIV_7
1220 * @arg @ref LL_RCC_PLLQ_DIV_8
1221 * @arg @ref LL_RCC_PLLQ_DIV_9
1222 * @arg @ref LL_RCC_PLLQ_DIV_10
1223 * @arg @ref LL_RCC_PLLQ_DIV_11
1224 * @arg @ref LL_RCC_PLLQ_DIV_12
1225 * @arg @ref LL_RCC_PLLQ_DIV_13
1226 * @arg @ref LL_RCC_PLLQ_DIV_14
1227 * @arg @ref LL_RCC_PLLQ_DIV_15
1228 * @retval PLL clock frequency (in Hz)
1229 */
1230 #define __LL_RCC_CALC_PLLCLK_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLQ__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1231 ((__PLLQ__) >> RCC_PLLCFGR_PLLQ_Pos ))
1232
1233 #if defined(DSI)
1234 /**
1235 * @brief Helper macro to calculate the PLLCLK frequency used on DSI
1236 * @note ex: @ref __LL_RCC_CALC_PLLCLK_DSI_FREQ (HSE_VALUE, @ref LL_RCC_PLL_GetDivider (),
1237 * @ref LL_RCC_PLL_GetN (), @ref LL_RCC_PLL_GetR ());
1238 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1239 * @param __PLLM__ This parameter can be one of the following values:
1240 * @arg @ref LL_RCC_PLLM_DIV_2
1241 * @arg @ref LL_RCC_PLLM_DIV_3
1242 * @arg @ref LL_RCC_PLLM_DIV_4
1243 * @arg @ref LL_RCC_PLLM_DIV_5
1244 * @arg @ref LL_RCC_PLLM_DIV_6
1245 * @arg @ref LL_RCC_PLLM_DIV_7
1246 * @arg @ref LL_RCC_PLLM_DIV_8
1247 * @arg @ref LL_RCC_PLLM_DIV_9
1248 * @arg @ref LL_RCC_PLLM_DIV_10
1249 * @arg @ref LL_RCC_PLLM_DIV_11
1250 * @arg @ref LL_RCC_PLLM_DIV_12
1251 * @arg @ref LL_RCC_PLLM_DIV_13
1252 * @arg @ref LL_RCC_PLLM_DIV_14
1253 * @arg @ref LL_RCC_PLLM_DIV_15
1254 * @arg @ref LL_RCC_PLLM_DIV_16
1255 * @arg @ref LL_RCC_PLLM_DIV_17
1256 * @arg @ref LL_RCC_PLLM_DIV_18
1257 * @arg @ref LL_RCC_PLLM_DIV_19
1258 * @arg @ref LL_RCC_PLLM_DIV_20
1259 * @arg @ref LL_RCC_PLLM_DIV_21
1260 * @arg @ref LL_RCC_PLLM_DIV_22
1261 * @arg @ref LL_RCC_PLLM_DIV_23
1262 * @arg @ref LL_RCC_PLLM_DIV_24
1263 * @arg @ref LL_RCC_PLLM_DIV_25
1264 * @arg @ref LL_RCC_PLLM_DIV_26
1265 * @arg @ref LL_RCC_PLLM_DIV_27
1266 * @arg @ref LL_RCC_PLLM_DIV_28
1267 * @arg @ref LL_RCC_PLLM_DIV_29
1268 * @arg @ref LL_RCC_PLLM_DIV_30
1269 * @arg @ref LL_RCC_PLLM_DIV_31
1270 * @arg @ref LL_RCC_PLLM_DIV_32
1271 * @arg @ref LL_RCC_PLLM_DIV_33
1272 * @arg @ref LL_RCC_PLLM_DIV_34
1273 * @arg @ref LL_RCC_PLLM_DIV_35
1274 * @arg @ref LL_RCC_PLLM_DIV_36
1275 * @arg @ref LL_RCC_PLLM_DIV_37
1276 * @arg @ref LL_RCC_PLLM_DIV_38
1277 * @arg @ref LL_RCC_PLLM_DIV_39
1278 * @arg @ref LL_RCC_PLLM_DIV_40
1279 * @arg @ref LL_RCC_PLLM_DIV_41
1280 * @arg @ref LL_RCC_PLLM_DIV_42
1281 * @arg @ref LL_RCC_PLLM_DIV_43
1282 * @arg @ref LL_RCC_PLLM_DIV_44
1283 * @arg @ref LL_RCC_PLLM_DIV_45
1284 * @arg @ref LL_RCC_PLLM_DIV_46
1285 * @arg @ref LL_RCC_PLLM_DIV_47
1286 * @arg @ref LL_RCC_PLLM_DIV_48
1287 * @arg @ref LL_RCC_PLLM_DIV_49
1288 * @arg @ref LL_RCC_PLLM_DIV_50
1289 * @arg @ref LL_RCC_PLLM_DIV_51
1290 * @arg @ref LL_RCC_PLLM_DIV_52
1291 * @arg @ref LL_RCC_PLLM_DIV_53
1292 * @arg @ref LL_RCC_PLLM_DIV_54
1293 * @arg @ref LL_RCC_PLLM_DIV_55
1294 * @arg @ref LL_RCC_PLLM_DIV_56
1295 * @arg @ref LL_RCC_PLLM_DIV_57
1296 * @arg @ref LL_RCC_PLLM_DIV_58
1297 * @arg @ref LL_RCC_PLLM_DIV_59
1298 * @arg @ref LL_RCC_PLLM_DIV_60
1299 * @arg @ref LL_RCC_PLLM_DIV_61
1300 * @arg @ref LL_RCC_PLLM_DIV_62
1301 * @arg @ref LL_RCC_PLLM_DIV_63
1302 * @param __PLLN__ Between 50 and 432
1303 * @param __PLLR__ This parameter can be one of the following values:
1304 * @arg @ref LL_RCC_PLLR_DIV_2
1305 * @arg @ref LL_RCC_PLLR_DIV_3
1306 * @arg @ref LL_RCC_PLLR_DIV_4
1307 * @arg @ref LL_RCC_PLLR_DIV_5
1308 * @arg @ref LL_RCC_PLLR_DIV_6
1309 * @arg @ref LL_RCC_PLLR_DIV_7
1310 * @retval PLL clock frequency (in Hz)
1311 */
1312 #define __LL_RCC_CALC_PLLCLK_DSI_FREQ(__INPUTFREQ__, __PLLM__, __PLLN__, __PLLR__) ((__INPUTFREQ__) / (__PLLM__) * (__PLLN__) / \
1313 ((__PLLR__) >> RCC_PLLCFGR_PLLR_Pos ))
1314 #endif /* DSI */
1315
1316 /**
1317 * @brief Helper macro to calculate the PLLSAI frequency used for SAI1 and SAI2 domains
1318 * @note ex: @ref __LL_RCC_CALC_PLLSAI_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1319 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetQ (), @ref LL_RCC_PLLSAI_GetDIVQ ());
1320 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1321 * @param __PLLM__ This parameter can be one of the following values:
1322 * @arg @ref LL_RCC_PLLM_DIV_2
1323 * @arg @ref LL_RCC_PLLM_DIV_3
1324 * @arg @ref LL_RCC_PLLM_DIV_4
1325 * @arg @ref LL_RCC_PLLM_DIV_5
1326 * @arg @ref LL_RCC_PLLM_DIV_6
1327 * @arg @ref LL_RCC_PLLM_DIV_7
1328 * @arg @ref LL_RCC_PLLM_DIV_8
1329 * @arg @ref LL_RCC_PLLM_DIV_9
1330 * @arg @ref LL_RCC_PLLM_DIV_10
1331 * @arg @ref LL_RCC_PLLM_DIV_11
1332 * @arg @ref LL_RCC_PLLM_DIV_12
1333 * @arg @ref LL_RCC_PLLM_DIV_13
1334 * @arg @ref LL_RCC_PLLM_DIV_14
1335 * @arg @ref LL_RCC_PLLM_DIV_15
1336 * @arg @ref LL_RCC_PLLM_DIV_16
1337 * @arg @ref LL_RCC_PLLM_DIV_17
1338 * @arg @ref LL_RCC_PLLM_DIV_18
1339 * @arg @ref LL_RCC_PLLM_DIV_19
1340 * @arg @ref LL_RCC_PLLM_DIV_20
1341 * @arg @ref LL_RCC_PLLM_DIV_21
1342 * @arg @ref LL_RCC_PLLM_DIV_22
1343 * @arg @ref LL_RCC_PLLM_DIV_23
1344 * @arg @ref LL_RCC_PLLM_DIV_24
1345 * @arg @ref LL_RCC_PLLM_DIV_25
1346 * @arg @ref LL_RCC_PLLM_DIV_26
1347 * @arg @ref LL_RCC_PLLM_DIV_27
1348 * @arg @ref LL_RCC_PLLM_DIV_28
1349 * @arg @ref LL_RCC_PLLM_DIV_29
1350 * @arg @ref LL_RCC_PLLM_DIV_30
1351 * @arg @ref LL_RCC_PLLM_DIV_31
1352 * @arg @ref LL_RCC_PLLM_DIV_32
1353 * @arg @ref LL_RCC_PLLM_DIV_33
1354 * @arg @ref LL_RCC_PLLM_DIV_34
1355 * @arg @ref LL_RCC_PLLM_DIV_35
1356 * @arg @ref LL_RCC_PLLM_DIV_36
1357 * @arg @ref LL_RCC_PLLM_DIV_37
1358 * @arg @ref LL_RCC_PLLM_DIV_38
1359 * @arg @ref LL_RCC_PLLM_DIV_39
1360 * @arg @ref LL_RCC_PLLM_DIV_40
1361 * @arg @ref LL_RCC_PLLM_DIV_41
1362 * @arg @ref LL_RCC_PLLM_DIV_42
1363 * @arg @ref LL_RCC_PLLM_DIV_43
1364 * @arg @ref LL_RCC_PLLM_DIV_44
1365 * @arg @ref LL_RCC_PLLM_DIV_45
1366 * @arg @ref LL_RCC_PLLM_DIV_46
1367 * @arg @ref LL_RCC_PLLM_DIV_47
1368 * @arg @ref LL_RCC_PLLM_DIV_48
1369 * @arg @ref LL_RCC_PLLM_DIV_49
1370 * @arg @ref LL_RCC_PLLM_DIV_50
1371 * @arg @ref LL_RCC_PLLM_DIV_51
1372 * @arg @ref LL_RCC_PLLM_DIV_52
1373 * @arg @ref LL_RCC_PLLM_DIV_53
1374 * @arg @ref LL_RCC_PLLM_DIV_54
1375 * @arg @ref LL_RCC_PLLM_DIV_55
1376 * @arg @ref LL_RCC_PLLM_DIV_56
1377 * @arg @ref LL_RCC_PLLM_DIV_57
1378 * @arg @ref LL_RCC_PLLM_DIV_58
1379 * @arg @ref LL_RCC_PLLM_DIV_59
1380 * @arg @ref LL_RCC_PLLM_DIV_60
1381 * @arg @ref LL_RCC_PLLM_DIV_61
1382 * @arg @ref LL_RCC_PLLM_DIV_62
1383 * @arg @ref LL_RCC_PLLM_DIV_63
1384 * @param __PLLSAIN__ Between 50 and 432
1385 * @param __PLLSAIQ__ This parameter can be one of the following values:
1386 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
1387 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
1388 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
1389 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
1390 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
1391 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
1392 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
1393 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
1394 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
1395 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
1396 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
1397 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
1398 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
1399 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
1400 * @param __PLLSAIDIVQ__ This parameter can be one of the following values:
1401 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
1402 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
1403 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
1404 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
1405 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
1406 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
1407 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
1408 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
1409 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
1410 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
1411 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
1412 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
1413 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
1414 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
1415 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
1416 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
1417 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
1418 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
1419 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
1420 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
1421 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
1422 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
1423 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
1424 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
1425 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
1426 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
1427 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
1428 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
1429 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
1430 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
1431 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
1432 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
1433 * @retval PLLSAI clock frequency (in Hz)
1434 */
1435 #define __LL_RCC_CALC_PLLSAI_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIQ__, __PLLSAIDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1436 (((__PLLSAIQ__) >> RCC_PLLSAICFGR_PLLSAIQ_Pos) * (((__PLLSAIDIVQ__) >> RCC_DCKCFGR1_PLLSAIDIVQ_Pos) + 1U)))
1437
1438 /**
1439 * @brief Helper macro to calculate the PLLSAI frequency used on 48Mhz domain
1440 * @note ex: @ref __LL_RCC_CALC_PLLSAI_48M_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1441 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetP ());
1442 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1443 * @param __PLLM__ This parameter can be one of the following values:
1444 * @arg @ref LL_RCC_PLLM_DIV_2
1445 * @arg @ref LL_RCC_PLLM_DIV_3
1446 * @arg @ref LL_RCC_PLLM_DIV_4
1447 * @arg @ref LL_RCC_PLLM_DIV_5
1448 * @arg @ref LL_RCC_PLLM_DIV_6
1449 * @arg @ref LL_RCC_PLLM_DIV_7
1450 * @arg @ref LL_RCC_PLLM_DIV_8
1451 * @arg @ref LL_RCC_PLLM_DIV_9
1452 * @arg @ref LL_RCC_PLLM_DIV_10
1453 * @arg @ref LL_RCC_PLLM_DIV_11
1454 * @arg @ref LL_RCC_PLLM_DIV_12
1455 * @arg @ref LL_RCC_PLLM_DIV_13
1456 * @arg @ref LL_RCC_PLLM_DIV_14
1457 * @arg @ref LL_RCC_PLLM_DIV_15
1458 * @arg @ref LL_RCC_PLLM_DIV_16
1459 * @arg @ref LL_RCC_PLLM_DIV_17
1460 * @arg @ref LL_RCC_PLLM_DIV_18
1461 * @arg @ref LL_RCC_PLLM_DIV_19
1462 * @arg @ref LL_RCC_PLLM_DIV_20
1463 * @arg @ref LL_RCC_PLLM_DIV_21
1464 * @arg @ref LL_RCC_PLLM_DIV_22
1465 * @arg @ref LL_RCC_PLLM_DIV_23
1466 * @arg @ref LL_RCC_PLLM_DIV_24
1467 * @arg @ref LL_RCC_PLLM_DIV_25
1468 * @arg @ref LL_RCC_PLLM_DIV_26
1469 * @arg @ref LL_RCC_PLLM_DIV_27
1470 * @arg @ref LL_RCC_PLLM_DIV_28
1471 * @arg @ref LL_RCC_PLLM_DIV_29
1472 * @arg @ref LL_RCC_PLLM_DIV_30
1473 * @arg @ref LL_RCC_PLLM_DIV_31
1474 * @arg @ref LL_RCC_PLLM_DIV_32
1475 * @arg @ref LL_RCC_PLLM_DIV_33
1476 * @arg @ref LL_RCC_PLLM_DIV_34
1477 * @arg @ref LL_RCC_PLLM_DIV_35
1478 * @arg @ref LL_RCC_PLLM_DIV_36
1479 * @arg @ref LL_RCC_PLLM_DIV_37
1480 * @arg @ref LL_RCC_PLLM_DIV_38
1481 * @arg @ref LL_RCC_PLLM_DIV_39
1482 * @arg @ref LL_RCC_PLLM_DIV_40
1483 * @arg @ref LL_RCC_PLLM_DIV_41
1484 * @arg @ref LL_RCC_PLLM_DIV_42
1485 * @arg @ref LL_RCC_PLLM_DIV_43
1486 * @arg @ref LL_RCC_PLLM_DIV_44
1487 * @arg @ref LL_RCC_PLLM_DIV_45
1488 * @arg @ref LL_RCC_PLLM_DIV_46
1489 * @arg @ref LL_RCC_PLLM_DIV_47
1490 * @arg @ref LL_RCC_PLLM_DIV_48
1491 * @arg @ref LL_RCC_PLLM_DIV_49
1492 * @arg @ref LL_RCC_PLLM_DIV_50
1493 * @arg @ref LL_RCC_PLLM_DIV_51
1494 * @arg @ref LL_RCC_PLLM_DIV_52
1495 * @arg @ref LL_RCC_PLLM_DIV_53
1496 * @arg @ref LL_RCC_PLLM_DIV_54
1497 * @arg @ref LL_RCC_PLLM_DIV_55
1498 * @arg @ref LL_RCC_PLLM_DIV_56
1499 * @arg @ref LL_RCC_PLLM_DIV_57
1500 * @arg @ref LL_RCC_PLLM_DIV_58
1501 * @arg @ref LL_RCC_PLLM_DIV_59
1502 * @arg @ref LL_RCC_PLLM_DIV_60
1503 * @arg @ref LL_RCC_PLLM_DIV_61
1504 * @arg @ref LL_RCC_PLLM_DIV_62
1505 * @arg @ref LL_RCC_PLLM_DIV_63
1506 * @param __PLLSAIN__ Between 50 and 432
1507 * @param __PLLSAIP__ This parameter can be one of the following values:
1508 * @arg @ref LL_RCC_PLLSAIP_DIV_2
1509 * @arg @ref LL_RCC_PLLSAIP_DIV_4
1510 * @arg @ref LL_RCC_PLLSAIP_DIV_6
1511 * @arg @ref LL_RCC_PLLSAIP_DIV_8
1512 * @retval PLLSAI clock frequency (in Hz)
1513 */
1514 #define __LL_RCC_CALC_PLLSAI_48M_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1515 ((((__PLLSAIP__) >> RCC_PLLSAICFGR_PLLSAIP_Pos) + 1U ) * 2U))
1516
1517 #if defined(LTDC)
1518 /**
1519 * @brief Helper macro to calculate the PLLSAI frequency used for LTDC domain
1520 * @note ex: @ref __LL_RCC_CALC_PLLSAI_LTDC_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1521 * @ref LL_RCC_PLLSAI_GetN (), @ref LL_RCC_PLLSAI_GetR (), @ref LL_RCC_PLLSAI_GetDIVR ());
1522 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1523 * @param __PLLM__ This parameter can be one of the following values:
1524 * @arg @ref LL_RCC_PLLM_DIV_2
1525 * @arg @ref LL_RCC_PLLM_DIV_3
1526 * @arg @ref LL_RCC_PLLM_DIV_4
1527 * @arg @ref LL_RCC_PLLM_DIV_5
1528 * @arg @ref LL_RCC_PLLM_DIV_6
1529 * @arg @ref LL_RCC_PLLM_DIV_7
1530 * @arg @ref LL_RCC_PLLM_DIV_8
1531 * @arg @ref LL_RCC_PLLM_DIV_9
1532 * @arg @ref LL_RCC_PLLM_DIV_10
1533 * @arg @ref LL_RCC_PLLM_DIV_11
1534 * @arg @ref LL_RCC_PLLM_DIV_12
1535 * @arg @ref LL_RCC_PLLM_DIV_13
1536 * @arg @ref LL_RCC_PLLM_DIV_14
1537 * @arg @ref LL_RCC_PLLM_DIV_15
1538 * @arg @ref LL_RCC_PLLM_DIV_16
1539 * @arg @ref LL_RCC_PLLM_DIV_17
1540 * @arg @ref LL_RCC_PLLM_DIV_18
1541 * @arg @ref LL_RCC_PLLM_DIV_19
1542 * @arg @ref LL_RCC_PLLM_DIV_20
1543 * @arg @ref LL_RCC_PLLM_DIV_21
1544 * @arg @ref LL_RCC_PLLM_DIV_22
1545 * @arg @ref LL_RCC_PLLM_DIV_23
1546 * @arg @ref LL_RCC_PLLM_DIV_24
1547 * @arg @ref LL_RCC_PLLM_DIV_25
1548 * @arg @ref LL_RCC_PLLM_DIV_26
1549 * @arg @ref LL_RCC_PLLM_DIV_27
1550 * @arg @ref LL_RCC_PLLM_DIV_28
1551 * @arg @ref LL_RCC_PLLM_DIV_29
1552 * @arg @ref LL_RCC_PLLM_DIV_30
1553 * @arg @ref LL_RCC_PLLM_DIV_31
1554 * @arg @ref LL_RCC_PLLM_DIV_32
1555 * @arg @ref LL_RCC_PLLM_DIV_33
1556 * @arg @ref LL_RCC_PLLM_DIV_34
1557 * @arg @ref LL_RCC_PLLM_DIV_35
1558 * @arg @ref LL_RCC_PLLM_DIV_36
1559 * @arg @ref LL_RCC_PLLM_DIV_37
1560 * @arg @ref LL_RCC_PLLM_DIV_38
1561 * @arg @ref LL_RCC_PLLM_DIV_39
1562 * @arg @ref LL_RCC_PLLM_DIV_40
1563 * @arg @ref LL_RCC_PLLM_DIV_41
1564 * @arg @ref LL_RCC_PLLM_DIV_42
1565 * @arg @ref LL_RCC_PLLM_DIV_43
1566 * @arg @ref LL_RCC_PLLM_DIV_44
1567 * @arg @ref LL_RCC_PLLM_DIV_45
1568 * @arg @ref LL_RCC_PLLM_DIV_46
1569 * @arg @ref LL_RCC_PLLM_DIV_47
1570 * @arg @ref LL_RCC_PLLM_DIV_48
1571 * @arg @ref LL_RCC_PLLM_DIV_49
1572 * @arg @ref LL_RCC_PLLM_DIV_50
1573 * @arg @ref LL_RCC_PLLM_DIV_51
1574 * @arg @ref LL_RCC_PLLM_DIV_52
1575 * @arg @ref LL_RCC_PLLM_DIV_53
1576 * @arg @ref LL_RCC_PLLM_DIV_54
1577 * @arg @ref LL_RCC_PLLM_DIV_55
1578 * @arg @ref LL_RCC_PLLM_DIV_56
1579 * @arg @ref LL_RCC_PLLM_DIV_57
1580 * @arg @ref LL_RCC_PLLM_DIV_58
1581 * @arg @ref LL_RCC_PLLM_DIV_59
1582 * @arg @ref LL_RCC_PLLM_DIV_60
1583 * @arg @ref LL_RCC_PLLM_DIV_61
1584 * @arg @ref LL_RCC_PLLM_DIV_62
1585 * @arg @ref LL_RCC_PLLM_DIV_63
1586 * @param __PLLSAIN__ Between 50 and 432
1587 * @param __PLLSAIR__ This parameter can be one of the following values:
1588 * @arg @ref LL_RCC_PLLSAIR_DIV_2
1589 * @arg @ref LL_RCC_PLLSAIR_DIV_3
1590 * @arg @ref LL_RCC_PLLSAIR_DIV_4
1591 * @arg @ref LL_RCC_PLLSAIR_DIV_5
1592 * @arg @ref LL_RCC_PLLSAIR_DIV_6
1593 * @arg @ref LL_RCC_PLLSAIR_DIV_7
1594 * @param __PLLSAIDIVR__ This parameter can be one of the following values:
1595 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
1596 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
1597 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
1598 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
1599 * @retval PLLSAI clock frequency (in Hz)
1600 */
1601 #define __LL_RCC_CALC_PLLSAI_LTDC_FREQ(__INPUTFREQ__, __PLLM__, __PLLSAIN__, __PLLSAIR__, __PLLSAIDIVR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLSAIN__) / \
1602 (((__PLLSAIR__) >> RCC_PLLSAICFGR_PLLSAIR_Pos) * (aRCC_PLLSAIDIVRPrescTable[(__PLLSAIDIVR__) >> RCC_DCKCFGR1_PLLSAIDIVR_Pos])))
1603 #endif /* LTDC */
1604
1605 /**
1606 * @brief Helper macro to calculate the PLLI2S frequency used for SAI1 and SAI2 domains
1607 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SAI_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1608 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetQ (), @ref LL_RCC_PLLI2S_GetDIVQ ());
1609 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1610 * @param __PLLM__ This parameter can be one of the following values:
1611 * @arg @ref LL_RCC_PLLM_DIV_2
1612 * @arg @ref LL_RCC_PLLM_DIV_3
1613 * @arg @ref LL_RCC_PLLM_DIV_4
1614 * @arg @ref LL_RCC_PLLM_DIV_5
1615 * @arg @ref LL_RCC_PLLM_DIV_6
1616 * @arg @ref LL_RCC_PLLM_DIV_7
1617 * @arg @ref LL_RCC_PLLM_DIV_8
1618 * @arg @ref LL_RCC_PLLM_DIV_9
1619 * @arg @ref LL_RCC_PLLM_DIV_10
1620 * @arg @ref LL_RCC_PLLM_DIV_11
1621 * @arg @ref LL_RCC_PLLM_DIV_12
1622 * @arg @ref LL_RCC_PLLM_DIV_13
1623 * @arg @ref LL_RCC_PLLM_DIV_14
1624 * @arg @ref LL_RCC_PLLM_DIV_15
1625 * @arg @ref LL_RCC_PLLM_DIV_16
1626 * @arg @ref LL_RCC_PLLM_DIV_17
1627 * @arg @ref LL_RCC_PLLM_DIV_18
1628 * @arg @ref LL_RCC_PLLM_DIV_19
1629 * @arg @ref LL_RCC_PLLM_DIV_20
1630 * @arg @ref LL_RCC_PLLM_DIV_21
1631 * @arg @ref LL_RCC_PLLM_DIV_22
1632 * @arg @ref LL_RCC_PLLM_DIV_23
1633 * @arg @ref LL_RCC_PLLM_DIV_24
1634 * @arg @ref LL_RCC_PLLM_DIV_25
1635 * @arg @ref LL_RCC_PLLM_DIV_26
1636 * @arg @ref LL_RCC_PLLM_DIV_27
1637 * @arg @ref LL_RCC_PLLM_DIV_28
1638 * @arg @ref LL_RCC_PLLM_DIV_29
1639 * @arg @ref LL_RCC_PLLM_DIV_30
1640 * @arg @ref LL_RCC_PLLM_DIV_31
1641 * @arg @ref LL_RCC_PLLM_DIV_32
1642 * @arg @ref LL_RCC_PLLM_DIV_33
1643 * @arg @ref LL_RCC_PLLM_DIV_34
1644 * @arg @ref LL_RCC_PLLM_DIV_35
1645 * @arg @ref LL_RCC_PLLM_DIV_36
1646 * @arg @ref LL_RCC_PLLM_DIV_37
1647 * @arg @ref LL_RCC_PLLM_DIV_38
1648 * @arg @ref LL_RCC_PLLM_DIV_39
1649 * @arg @ref LL_RCC_PLLM_DIV_40
1650 * @arg @ref LL_RCC_PLLM_DIV_41
1651 * @arg @ref LL_RCC_PLLM_DIV_42
1652 * @arg @ref LL_RCC_PLLM_DIV_43
1653 * @arg @ref LL_RCC_PLLM_DIV_44
1654 * @arg @ref LL_RCC_PLLM_DIV_45
1655 * @arg @ref LL_RCC_PLLM_DIV_46
1656 * @arg @ref LL_RCC_PLLM_DIV_47
1657 * @arg @ref LL_RCC_PLLM_DIV_48
1658 * @arg @ref LL_RCC_PLLM_DIV_49
1659 * @arg @ref LL_RCC_PLLM_DIV_50
1660 * @arg @ref LL_RCC_PLLM_DIV_51
1661 * @arg @ref LL_RCC_PLLM_DIV_52
1662 * @arg @ref LL_RCC_PLLM_DIV_53
1663 * @arg @ref LL_RCC_PLLM_DIV_54
1664 * @arg @ref LL_RCC_PLLM_DIV_55
1665 * @arg @ref LL_RCC_PLLM_DIV_56
1666 * @arg @ref LL_RCC_PLLM_DIV_57
1667 * @arg @ref LL_RCC_PLLM_DIV_58
1668 * @arg @ref LL_RCC_PLLM_DIV_59
1669 * @arg @ref LL_RCC_PLLM_DIV_60
1670 * @arg @ref LL_RCC_PLLM_DIV_61
1671 * @arg @ref LL_RCC_PLLM_DIV_62
1672 * @arg @ref LL_RCC_PLLM_DIV_63
1673 * @param __PLLI2SN__ Between 50 and 432
1674 * @param __PLLI2SQ__ This parameter can be one of the following values:
1675 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
1676 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
1677 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
1678 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
1679 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
1680 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
1681 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
1682 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
1683 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
1684 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
1685 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
1686 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
1687 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
1688 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
1689 * @param __PLLI2SDIVQ__ This parameter can be one of the following values:
1690 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
1691 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
1692 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
1693 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
1694 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
1695 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
1696 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
1697 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
1698 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
1699 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
1700 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
1701 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
1702 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
1703 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
1704 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
1705 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
1706 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
1707 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
1708 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
1709 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
1710 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
1711 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
1712 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
1713 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
1714 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
1715 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
1716 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
1717 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
1718 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
1719 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
1720 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
1721 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
1722 * @retval PLLI2S clock frequency (in Hz)
1723 */
1724 #define __LL_RCC_CALC_PLLI2S_SAI_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SQ__, __PLLI2SDIVQ__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1725 (((__PLLI2SQ__) >> RCC_PLLI2SCFGR_PLLI2SQ_Pos) * (((__PLLI2SDIVQ__) >> RCC_DCKCFGR1_PLLI2SDIVQ_Pos) + 1U)))
1726
1727 #if defined(SPDIFRX)
1728 /**
1729 * @brief Helper macro to calculate the PLLI2S frequency used on SPDIFRX domain
1730 * @note ex: @ref __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1731 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetP ());
1732 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1733 * @param __PLLM__ This parameter can be one of the following values:
1734 * @arg @ref LL_RCC_PLLM_DIV_2
1735 * @arg @ref LL_RCC_PLLM_DIV_3
1736 * @arg @ref LL_RCC_PLLM_DIV_4
1737 * @arg @ref LL_RCC_PLLM_DIV_5
1738 * @arg @ref LL_RCC_PLLM_DIV_6
1739 * @arg @ref LL_RCC_PLLM_DIV_7
1740 * @arg @ref LL_RCC_PLLM_DIV_8
1741 * @arg @ref LL_RCC_PLLM_DIV_9
1742 * @arg @ref LL_RCC_PLLM_DIV_10
1743 * @arg @ref LL_RCC_PLLM_DIV_11
1744 * @arg @ref LL_RCC_PLLM_DIV_12
1745 * @arg @ref LL_RCC_PLLM_DIV_13
1746 * @arg @ref LL_RCC_PLLM_DIV_14
1747 * @arg @ref LL_RCC_PLLM_DIV_15
1748 * @arg @ref LL_RCC_PLLM_DIV_16
1749 * @arg @ref LL_RCC_PLLM_DIV_17
1750 * @arg @ref LL_RCC_PLLM_DIV_18
1751 * @arg @ref LL_RCC_PLLM_DIV_19
1752 * @arg @ref LL_RCC_PLLM_DIV_20
1753 * @arg @ref LL_RCC_PLLM_DIV_21
1754 * @arg @ref LL_RCC_PLLM_DIV_22
1755 * @arg @ref LL_RCC_PLLM_DIV_23
1756 * @arg @ref LL_RCC_PLLM_DIV_24
1757 * @arg @ref LL_RCC_PLLM_DIV_25
1758 * @arg @ref LL_RCC_PLLM_DIV_26
1759 * @arg @ref LL_RCC_PLLM_DIV_27
1760 * @arg @ref LL_RCC_PLLM_DIV_28
1761 * @arg @ref LL_RCC_PLLM_DIV_29
1762 * @arg @ref LL_RCC_PLLM_DIV_30
1763 * @arg @ref LL_RCC_PLLM_DIV_31
1764 * @arg @ref LL_RCC_PLLM_DIV_32
1765 * @arg @ref LL_RCC_PLLM_DIV_33
1766 * @arg @ref LL_RCC_PLLM_DIV_34
1767 * @arg @ref LL_RCC_PLLM_DIV_35
1768 * @arg @ref LL_RCC_PLLM_DIV_36
1769 * @arg @ref LL_RCC_PLLM_DIV_37
1770 * @arg @ref LL_RCC_PLLM_DIV_38
1771 * @arg @ref LL_RCC_PLLM_DIV_39
1772 * @arg @ref LL_RCC_PLLM_DIV_40
1773 * @arg @ref LL_RCC_PLLM_DIV_41
1774 * @arg @ref LL_RCC_PLLM_DIV_42
1775 * @arg @ref LL_RCC_PLLM_DIV_43
1776 * @arg @ref LL_RCC_PLLM_DIV_44
1777 * @arg @ref LL_RCC_PLLM_DIV_45
1778 * @arg @ref LL_RCC_PLLM_DIV_46
1779 * @arg @ref LL_RCC_PLLM_DIV_47
1780 * @arg @ref LL_RCC_PLLM_DIV_48
1781 * @arg @ref LL_RCC_PLLM_DIV_49
1782 * @arg @ref LL_RCC_PLLM_DIV_50
1783 * @arg @ref LL_RCC_PLLM_DIV_51
1784 * @arg @ref LL_RCC_PLLM_DIV_52
1785 * @arg @ref LL_RCC_PLLM_DIV_53
1786 * @arg @ref LL_RCC_PLLM_DIV_54
1787 * @arg @ref LL_RCC_PLLM_DIV_55
1788 * @arg @ref LL_RCC_PLLM_DIV_56
1789 * @arg @ref LL_RCC_PLLM_DIV_57
1790 * @arg @ref LL_RCC_PLLM_DIV_58
1791 * @arg @ref LL_RCC_PLLM_DIV_59
1792 * @arg @ref LL_RCC_PLLM_DIV_60
1793 * @arg @ref LL_RCC_PLLM_DIV_61
1794 * @arg @ref LL_RCC_PLLM_DIV_62
1795 * @arg @ref LL_RCC_PLLM_DIV_63
1796 * @param __PLLI2SN__ Between 50 and 432
1797 * @param __PLLI2SP__ This parameter can be one of the following values:
1798 * @arg @ref LL_RCC_PLLI2SP_DIV_2
1799 * @arg @ref LL_RCC_PLLI2SP_DIV_4
1800 * @arg @ref LL_RCC_PLLI2SP_DIV_6
1801 * @arg @ref LL_RCC_PLLI2SP_DIV_8
1802 * @retval PLLI2S clock frequency (in Hz)
1803 */
1804 #define __LL_RCC_CALC_PLLI2S_SPDIFRX_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SP__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1805 ((((__PLLI2SP__) >> RCC_PLLI2SCFGR_PLLI2SP_Pos) + 1U) * 2U))
1806 #endif /* SPDIFRX */
1807
1808 /**
1809 * @brief Helper macro to calculate the PLLI2S frequency used for I2S domain
1810 * @note ex: @ref __LL_RCC_CALC_PLLI2S_I2S_FREQ (HSE_VALUE,@ref LL_RCC_PLL_GetDivider (),
1811 * @ref LL_RCC_PLLI2S_GetN (), @ref LL_RCC_PLLI2S_GetR ());
1812 * @param __INPUTFREQ__ PLL Input frequency (based on HSE/HSI)
1813 * @param __PLLM__ This parameter can be one of the following values:
1814 * @arg @ref LL_RCC_PLLM_DIV_2
1815 * @arg @ref LL_RCC_PLLM_DIV_3
1816 * @arg @ref LL_RCC_PLLM_DIV_4
1817 * @arg @ref LL_RCC_PLLM_DIV_5
1818 * @arg @ref LL_RCC_PLLM_DIV_6
1819 * @arg @ref LL_RCC_PLLM_DIV_7
1820 * @arg @ref LL_RCC_PLLM_DIV_8
1821 * @arg @ref LL_RCC_PLLM_DIV_9
1822 * @arg @ref LL_RCC_PLLM_DIV_10
1823 * @arg @ref LL_RCC_PLLM_DIV_11
1824 * @arg @ref LL_RCC_PLLM_DIV_12
1825 * @arg @ref LL_RCC_PLLM_DIV_13
1826 * @arg @ref LL_RCC_PLLM_DIV_14
1827 * @arg @ref LL_RCC_PLLM_DIV_15
1828 * @arg @ref LL_RCC_PLLM_DIV_16
1829 * @arg @ref LL_RCC_PLLM_DIV_17
1830 * @arg @ref LL_RCC_PLLM_DIV_18
1831 * @arg @ref LL_RCC_PLLM_DIV_19
1832 * @arg @ref LL_RCC_PLLM_DIV_20
1833 * @arg @ref LL_RCC_PLLM_DIV_21
1834 * @arg @ref LL_RCC_PLLM_DIV_22
1835 * @arg @ref LL_RCC_PLLM_DIV_23
1836 * @arg @ref LL_RCC_PLLM_DIV_24
1837 * @arg @ref LL_RCC_PLLM_DIV_25
1838 * @arg @ref LL_RCC_PLLM_DIV_26
1839 * @arg @ref LL_RCC_PLLM_DIV_27
1840 * @arg @ref LL_RCC_PLLM_DIV_28
1841 * @arg @ref LL_RCC_PLLM_DIV_29
1842 * @arg @ref LL_RCC_PLLM_DIV_30
1843 * @arg @ref LL_RCC_PLLM_DIV_31
1844 * @arg @ref LL_RCC_PLLM_DIV_32
1845 * @arg @ref LL_RCC_PLLM_DIV_33
1846 * @arg @ref LL_RCC_PLLM_DIV_34
1847 * @arg @ref LL_RCC_PLLM_DIV_35
1848 * @arg @ref LL_RCC_PLLM_DIV_36
1849 * @arg @ref LL_RCC_PLLM_DIV_37
1850 * @arg @ref LL_RCC_PLLM_DIV_38
1851 * @arg @ref LL_RCC_PLLM_DIV_39
1852 * @arg @ref LL_RCC_PLLM_DIV_40
1853 * @arg @ref LL_RCC_PLLM_DIV_41
1854 * @arg @ref LL_RCC_PLLM_DIV_42
1855 * @arg @ref LL_RCC_PLLM_DIV_43
1856 * @arg @ref LL_RCC_PLLM_DIV_44
1857 * @arg @ref LL_RCC_PLLM_DIV_45
1858 * @arg @ref LL_RCC_PLLM_DIV_46
1859 * @arg @ref LL_RCC_PLLM_DIV_47
1860 * @arg @ref LL_RCC_PLLM_DIV_48
1861 * @arg @ref LL_RCC_PLLM_DIV_49
1862 * @arg @ref LL_RCC_PLLM_DIV_50
1863 * @arg @ref LL_RCC_PLLM_DIV_51
1864 * @arg @ref LL_RCC_PLLM_DIV_52
1865 * @arg @ref LL_RCC_PLLM_DIV_53
1866 * @arg @ref LL_RCC_PLLM_DIV_54
1867 * @arg @ref LL_RCC_PLLM_DIV_55
1868 * @arg @ref LL_RCC_PLLM_DIV_56
1869 * @arg @ref LL_RCC_PLLM_DIV_57
1870 * @arg @ref LL_RCC_PLLM_DIV_58
1871 * @arg @ref LL_RCC_PLLM_DIV_59
1872 * @arg @ref LL_RCC_PLLM_DIV_60
1873 * @arg @ref LL_RCC_PLLM_DIV_61
1874 * @arg @ref LL_RCC_PLLM_DIV_62
1875 * @arg @ref LL_RCC_PLLM_DIV_63
1876 * @param __PLLI2SN__ Between 50 and 432
1877 * @param __PLLI2SR__ This parameter can be one of the following values:
1878 * @arg @ref LL_RCC_PLLI2SR_DIV_2
1879 * @arg @ref LL_RCC_PLLI2SR_DIV_3
1880 * @arg @ref LL_RCC_PLLI2SR_DIV_4
1881 * @arg @ref LL_RCC_PLLI2SR_DIV_5
1882 * @arg @ref LL_RCC_PLLI2SR_DIV_6
1883 * @arg @ref LL_RCC_PLLI2SR_DIV_7
1884 * @retval PLLI2S clock frequency (in Hz)
1885 */
1886 #define __LL_RCC_CALC_PLLI2S_I2S_FREQ(__INPUTFREQ__, __PLLM__, __PLLI2SN__, __PLLI2SR__) (((__INPUTFREQ__) / (__PLLM__)) * (__PLLI2SN__) / \
1887 ((__PLLI2SR__) >> RCC_PLLI2SCFGR_PLLI2SR_Pos))
1888
1889 /**
1890 * @brief Helper macro to calculate the HCLK frequency
1891 * @param __SYSCLKFREQ__ SYSCLK frequency (based on HSE/HSI/PLLCLK)
1892 * @param __AHBPRESCALER__ This parameter can be one of the following values:
1893 * @arg @ref LL_RCC_SYSCLK_DIV_1
1894 * @arg @ref LL_RCC_SYSCLK_DIV_2
1895 * @arg @ref LL_RCC_SYSCLK_DIV_4
1896 * @arg @ref LL_RCC_SYSCLK_DIV_8
1897 * @arg @ref LL_RCC_SYSCLK_DIV_16
1898 * @arg @ref LL_RCC_SYSCLK_DIV_64
1899 * @arg @ref LL_RCC_SYSCLK_DIV_128
1900 * @arg @ref LL_RCC_SYSCLK_DIV_256
1901 * @arg @ref LL_RCC_SYSCLK_DIV_512
1902 * @retval HCLK clock frequency (in Hz)
1903 */
1904 #define __LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __AHBPRESCALER__) ((__SYSCLKFREQ__) >> AHBPrescTable[((__AHBPRESCALER__) & RCC_CFGR_HPRE) >> RCC_CFGR_HPRE_Pos])
1905
1906 /**
1907 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1908 * @param __HCLKFREQ__ HCLK frequency
1909 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1910 * @arg @ref LL_RCC_APB1_DIV_1
1911 * @arg @ref LL_RCC_APB1_DIV_2
1912 * @arg @ref LL_RCC_APB1_DIV_4
1913 * @arg @ref LL_RCC_APB1_DIV_8
1914 * @arg @ref LL_RCC_APB1_DIV_16
1915 * @retval PCLK1 clock frequency (in Hz)
1916 */
1917 #define __LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB1PRESCALER__) >> RCC_CFGR_PPRE1_Pos])
1918
1919 /**
1920 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1921 * @param __HCLKFREQ__ HCLK frequency
1922 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1923 * @arg @ref LL_RCC_APB2_DIV_1
1924 * @arg @ref LL_RCC_APB2_DIV_2
1925 * @arg @ref LL_RCC_APB2_DIV_4
1926 * @arg @ref LL_RCC_APB2_DIV_8
1927 * @arg @ref LL_RCC_APB2_DIV_16
1928 * @retval PCLK2 clock frequency (in Hz)
1929 */
1930 #define __LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> APBPrescTable[(__APB2PRESCALER__) >> RCC_CFGR_PPRE2_Pos])
1931
1932 /**
1933 * @}
1934 */
1935
1936 /**
1937 * @}
1938 */
1939
1940 /* Exported functions --------------------------------------------------------*/
1941 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1942 * @{
1943 */
1944
1945 /** @defgroup RCC_LL_EF_HSE HSE
1946 * @{
1947 */
1948
1949 /**
1950 * @brief Enable the Clock Security System.
1951 * @rmtoll CR CSSON LL_RCC_HSE_EnableCSS
1952 * @retval None
1953 */
1954 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1955 {
1956 SET_BIT(RCC->CR, RCC_CR_CSSON);
1957 }
1958
1959 /**
1960 * @brief Enable HSE external oscillator (HSE Bypass)
1961 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1962 * @retval None
1963 */
1964 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1965 {
1966 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1967 }
1968
1969 /**
1970 * @brief Disable HSE external oscillator (HSE Bypass)
1971 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1972 * @retval None
1973 */
1974 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1975 {
1976 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1977 }
1978
1979 /**
1980 * @brief Enable HSE crystal oscillator (HSE ON)
1981 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1982 * @retval None
1983 */
1984 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1985 {
1986 SET_BIT(RCC->CR, RCC_CR_HSEON);
1987 }
1988
1989 /**
1990 * @brief Disable HSE crystal oscillator (HSE ON)
1991 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1992 * @retval None
1993 */
1994 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1995 {
1996 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1997 }
1998
1999 /**
2000 * @brief Check if HSE oscillator Ready
2001 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
2002 * @retval State of bit (1 or 0).
2003 */
2004 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
2005 {
2006 return (READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY));
2007 }
2008
2009 /**
2010 * @}
2011 */
2012
2013 /** @defgroup RCC_LL_EF_HSI HSI
2014 * @{
2015 */
2016
2017 /**
2018 * @brief Enable HSI oscillator
2019 * @rmtoll CR HSION LL_RCC_HSI_Enable
2020 * @retval None
2021 */
2022 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
2023 {
2024 SET_BIT(RCC->CR, RCC_CR_HSION);
2025 }
2026
2027 /**
2028 * @brief Disable HSI oscillator
2029 * @rmtoll CR HSION LL_RCC_HSI_Disable
2030 * @retval None
2031 */
2032 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
2033 {
2034 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
2035 }
2036
2037 /**
2038 * @brief Check if HSI clock is ready
2039 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
2040 * @retval State of bit (1 or 0).
2041 */
2042 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
2043 {
2044 return (READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY));
2045 }
2046
2047 /**
2048 * @brief Get HSI Calibration value
2049 * @note When HSITRIM is written, HSICAL is updated with the sum of
2050 * HSITRIM and the factory trim value
2051 * @rmtoll CR HSICAL LL_RCC_HSI_GetCalibration
2052 * @retval Between Min_Data = 0x00 and Max_Data = 0xFF
2053 */
2054 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
2055 {
2056 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSICAL) >> RCC_CR_HSICAL_Pos);
2057 }
2058
2059 /**
2060 * @brief Set HSI Calibration trimming
2061 * @note user-programmable trimming value that is added to the HSICAL
2062 * @note Default value is 16, which, when added to the HSICAL value,
2063 * should trim the HSI to 16 MHz +/- 1 %
2064 * @rmtoll CR HSITRIM LL_RCC_HSI_SetCalibTrimming
2065 * @param Value Between Min_Data = 0 and Max_Data = 31
2066 * @retval None
2067 */
2068 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
2069 {
2070 MODIFY_REG(RCC->CR, RCC_CR_HSITRIM, Value << RCC_CR_HSITRIM_Pos);
2071 }
2072
2073 /**
2074 * @brief Get HSI Calibration trimming
2075 * @rmtoll CR HSITRIM LL_RCC_HSI_GetCalibTrimming
2076 * @retval Between Min_Data = 0 and Max_Data = 31
2077 */
2078 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
2079 {
2080 return (uint32_t)(READ_BIT(RCC->CR, RCC_CR_HSITRIM) >> RCC_CR_HSITRIM_Pos);
2081 }
2082
2083 /**
2084 * @}
2085 */
2086
2087 /** @defgroup RCC_LL_EF_LSE LSE
2088 * @{
2089 */
2090
2091 /**
2092 * @brief Enable Low Speed External (LSE) crystal.
2093 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2094 * @retval None
2095 */
2096 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2097 {
2098 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2099 }
2100
2101 /**
2102 * @brief Disable Low Speed External (LSE) crystal.
2103 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2104 * @retval None
2105 */
2106 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2107 {
2108 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2109 }
2110
2111 /**
2112 * @brief Enable external clock source (LSE bypass).
2113 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2114 * @retval None
2115 */
2116 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2117 {
2118 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2119 }
2120
2121 /**
2122 * @brief Disable external clock source (LSE bypass).
2123 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2124 * @retval None
2125 */
2126 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2127 {
2128 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2129 }
2130
2131 /**
2132 * @brief Set LSE oscillator drive capability
2133 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2134 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2135 * @param LSEDrive This parameter can be one of the following values:
2136 * @arg @ref LL_RCC_LSEDRIVE_LOW
2137 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2138 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2139 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2140 * @retval None
2141 */
2142 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2143 {
2144 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2145 }
2146
2147 /**
2148 * @brief Get LSE oscillator drive capability
2149 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2150 * @retval Returned value can be one of the following values:
2151 * @arg @ref LL_RCC_LSEDRIVE_LOW
2152 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2153 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2154 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2155 */
2156 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2157 {
2158 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2159 }
2160
2161 /**
2162 * @brief Check if LSE oscillator Ready
2163 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2164 * @retval State of bit (1 or 0).
2165 */
2166 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2167 {
2168 return (READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY));
2169 }
2170
2171 /**
2172 * @}
2173 */
2174
2175 /** @defgroup RCC_LL_EF_LSI LSI
2176 * @{
2177 */
2178
2179 /**
2180 * @brief Enable LSI Oscillator
2181 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2182 * @retval None
2183 */
2184 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2185 {
2186 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2187 }
2188
2189 /**
2190 * @brief Disable LSI Oscillator
2191 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2192 * @retval None
2193 */
2194 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2195 {
2196 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2197 }
2198
2199 /**
2200 * @brief Check if LSI is Ready
2201 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2202 * @retval State of bit (1 or 0).
2203 */
2204 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2205 {
2206 return (READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY));
2207 }
2208
2209 /**
2210 * @}
2211 */
2212
2213 /** @defgroup RCC_LL_EF_System System
2214 * @{
2215 */
2216
2217 /**
2218 * @brief Configure the system clock source
2219 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2220 * @param Source This parameter can be one of the following values:
2221 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2222 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2223 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL
2224 * @retval None
2225 */
2226 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2227 {
2228 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2229 }
2230
2231 /**
2232 * @brief Get the system clock source
2233 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2234 * @retval Returned value can be one of the following values:
2235 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2236 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2237 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL
2238 */
2239 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2240 {
2241 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2242 }
2243
2244 /**
2245 * @brief Set AHB prescaler
2246 * @rmtoll CFGR HPRE LL_RCC_SetAHBPrescaler
2247 * @param Prescaler This parameter can be one of the following values:
2248 * @arg @ref LL_RCC_SYSCLK_DIV_1
2249 * @arg @ref LL_RCC_SYSCLK_DIV_2
2250 * @arg @ref LL_RCC_SYSCLK_DIV_4
2251 * @arg @ref LL_RCC_SYSCLK_DIV_8
2252 * @arg @ref LL_RCC_SYSCLK_DIV_16
2253 * @arg @ref LL_RCC_SYSCLK_DIV_64
2254 * @arg @ref LL_RCC_SYSCLK_DIV_128
2255 * @arg @ref LL_RCC_SYSCLK_DIV_256
2256 * @arg @ref LL_RCC_SYSCLK_DIV_512
2257 * @retval None
2258 */
2259 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2260 {
2261 MODIFY_REG(RCC->CFGR, RCC_CFGR_HPRE, Prescaler);
2262 }
2263
2264 /**
2265 * @brief Set APB1 prescaler
2266 * @rmtoll CFGR PPRE1 LL_RCC_SetAPB1Prescaler
2267 * @param Prescaler This parameter can be one of the following values:
2268 * @arg @ref LL_RCC_APB1_DIV_1
2269 * @arg @ref LL_RCC_APB1_DIV_2
2270 * @arg @ref LL_RCC_APB1_DIV_4
2271 * @arg @ref LL_RCC_APB1_DIV_8
2272 * @arg @ref LL_RCC_APB1_DIV_16
2273 * @retval None
2274 */
2275 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2276 {
2277 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE1, Prescaler);
2278 }
2279
2280 /**
2281 * @brief Set APB2 prescaler
2282 * @rmtoll CFGR PPRE2 LL_RCC_SetAPB2Prescaler
2283 * @param Prescaler This parameter can be one of the following values:
2284 * @arg @ref LL_RCC_APB2_DIV_1
2285 * @arg @ref LL_RCC_APB2_DIV_2
2286 * @arg @ref LL_RCC_APB2_DIV_4
2287 * @arg @ref LL_RCC_APB2_DIV_8
2288 * @arg @ref LL_RCC_APB2_DIV_16
2289 * @retval None
2290 */
2291 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2292 {
2293 MODIFY_REG(RCC->CFGR, RCC_CFGR_PPRE2, Prescaler);
2294 }
2295
2296 /**
2297 * @brief Get AHB prescaler
2298 * @rmtoll CFGR HPRE LL_RCC_GetAHBPrescaler
2299 * @retval Returned value can be one of the following values:
2300 * @arg @ref LL_RCC_SYSCLK_DIV_1
2301 * @arg @ref LL_RCC_SYSCLK_DIV_2
2302 * @arg @ref LL_RCC_SYSCLK_DIV_4
2303 * @arg @ref LL_RCC_SYSCLK_DIV_8
2304 * @arg @ref LL_RCC_SYSCLK_DIV_16
2305 * @arg @ref LL_RCC_SYSCLK_DIV_64
2306 * @arg @ref LL_RCC_SYSCLK_DIV_128
2307 * @arg @ref LL_RCC_SYSCLK_DIV_256
2308 * @arg @ref LL_RCC_SYSCLK_DIV_512
2309 */
2310 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2311 {
2312 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HPRE));
2313 }
2314
2315 /**
2316 * @brief Get APB1 prescaler
2317 * @rmtoll CFGR PPRE1 LL_RCC_GetAPB1Prescaler
2318 * @retval Returned value can be one of the following values:
2319 * @arg @ref LL_RCC_APB1_DIV_1
2320 * @arg @ref LL_RCC_APB1_DIV_2
2321 * @arg @ref LL_RCC_APB1_DIV_4
2322 * @arg @ref LL_RCC_APB1_DIV_8
2323 * @arg @ref LL_RCC_APB1_DIV_16
2324 */
2325 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2326 {
2327 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE1));
2328 }
2329
2330 /**
2331 * @brief Get APB2 prescaler
2332 * @rmtoll CFGR PPRE2 LL_RCC_GetAPB2Prescaler
2333 * @retval Returned value can be one of the following values:
2334 * @arg @ref LL_RCC_APB2_DIV_1
2335 * @arg @ref LL_RCC_APB2_DIV_2
2336 * @arg @ref LL_RCC_APB2_DIV_4
2337 * @arg @ref LL_RCC_APB2_DIV_8
2338 * @arg @ref LL_RCC_APB2_DIV_16
2339 */
2340 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2341 {
2342 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_PPRE2));
2343 }
2344
2345 /**
2346 * @}
2347 */
2348
2349 /** @defgroup RCC_LL_EF_MCO MCO
2350 * @{
2351 */
2352
2353 /**
2354 * @brief Configure MCOx
2355 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2356 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2357 * CFGR MCO2 LL_RCC_ConfigMCO\n
2358 * CFGR MCO2PRE LL_RCC_ConfigMCO
2359 * @param MCOxSource This parameter can be one of the following values:
2360 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2361 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2362 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2363 * @arg @ref LL_RCC_MCO1SOURCE_PLLCLK
2364 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2365 * @arg @ref LL_RCC_MCO2SOURCE_PLLI2S
2366 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2367 * @arg @ref LL_RCC_MCO2SOURCE_PLLCLK
2368 * @param MCOxPrescaler This parameter can be one of the following values:
2369 * @arg @ref LL_RCC_MCO1_DIV_1
2370 * @arg @ref LL_RCC_MCO1_DIV_2
2371 * @arg @ref LL_RCC_MCO1_DIV_3
2372 * @arg @ref LL_RCC_MCO1_DIV_4
2373 * @arg @ref LL_RCC_MCO1_DIV_5
2374 * @arg @ref LL_RCC_MCO2_DIV_1
2375 * @arg @ref LL_RCC_MCO2_DIV_2
2376 * @arg @ref LL_RCC_MCO2_DIV_3
2377 * @arg @ref LL_RCC_MCO2_DIV_4
2378 * @arg @ref LL_RCC_MCO2_DIV_5
2379 * @retval None
2380 */
2381 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2382 {
2383 MODIFY_REG(RCC->CFGR, (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U), (MCOxSource << 16U) | (MCOxPrescaler << 16U));
2384 }
2385
2386 /**
2387 * @}
2388 */
2389
2390 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2391 * @{
2392 */
2393
2394 /**
2395 * @brief Configure USARTx clock source
2396 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_SetUSARTClockSource\n
2397 * DCKCFGR2 USART2SEL LL_RCC_SetUSARTClockSource\n
2398 * DCKCFGR2 USART3SEL LL_RCC_SetUSARTClockSource\n
2399 * DCKCFGR2 USART6SEL LL_RCC_SetUSARTClockSource
2400 * @param USARTxSource This parameter can be one of the following values:
2401 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2402 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2403 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2404 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2405 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2406 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2407 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2408 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2409 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2410 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2411 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2412 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2413 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2414 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2415 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2416 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2417 * @retval None
2418 */
2419 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t USARTxSource)
2420 {
2421 MODIFY_REG(RCC->DCKCFGR2, (USARTxSource >> 16U), (USARTxSource & 0x0000FFFFU));
2422 }
2423
2424 /**
2425 * @brief Configure UARTx clock source
2426 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_SetUARTClockSource\n
2427 * DCKCFGR2 UART5SEL LL_RCC_SetUARTClockSource\n
2428 * DCKCFGR2 UART7SEL LL_RCC_SetUARTClockSource\n
2429 * DCKCFGR2 UART8SEL LL_RCC_SetUARTClockSource
2430 * @param UARTxSource This parameter can be one of the following values:
2431 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2432 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2433 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2434 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2435 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2436 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2437 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2438 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2439 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2440 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2441 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2442 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2443 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2444 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2445 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2446 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2447 * @retval None
2448 */
2449 __STATIC_INLINE void LL_RCC_SetUARTClockSource(uint32_t UARTxSource)
2450 {
2451 MODIFY_REG(RCC->DCKCFGR2, (UARTxSource >> 16U), (UARTxSource & 0x0000FFFFU));
2452 }
2453
2454 /**
2455 * @brief Configure I2Cx clock source
2456 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_SetI2CClockSource\n
2457 * DCKCFGR2 I2C2SEL LL_RCC_SetI2CClockSource\n
2458 * DCKCFGR2 I2C3SEL LL_RCC_SetI2CClockSource\n
2459 * DCKCFGR2 I2C4SEL LL_RCC_SetI2CClockSource
2460 * @param I2CxSource This parameter can be one of the following values:
2461 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2462 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2463 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2464 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2465 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2466 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2467 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2468 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2469 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2470 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2471 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2472 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2473 *
2474 * (*) value not defined in all devices.
2475 * @retval None
2476 */
2477 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t I2CxSource)
2478 {
2479 MODIFY_REG(RCC->DCKCFGR2, (I2CxSource & 0xFFFF0000U), (I2CxSource << 16U));
2480 }
2481
2482 /**
2483 * @brief Configure LPTIMx clock source
2484 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_SetLPTIMClockSource
2485 * @param LPTIMxSource This parameter can be one of the following values:
2486 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2487 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2488 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2489 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2490 * @retval None
2491 */
2492 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t LPTIMxSource)
2493 {
2494 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL, LPTIMxSource);
2495 }
2496
2497 /**
2498 * @brief Configure SAIx clock source
2499 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_SetSAIClockSource\n
2500 * DCKCFGR1 SAI2SEL LL_RCC_SetSAIClockSource
2501 * @param SAIxSource This parameter can be one of the following values:
2502 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2503 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2504 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2505 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2506 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2507 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2508 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2509 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2510 *
2511 * (*) value not defined in all devices.
2512 * @retval None
2513 */
2514 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t SAIxSource)
2515 {
2516 MODIFY_REG(RCC->DCKCFGR1, (SAIxSource & 0xFFFF0000U), (SAIxSource << 16U));
2517 }
2518
2519 /**
2520 * @brief Configure SDMMC clock source
2521 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_SetSDMMCClockSource\n
2522 * DCKCFGR2 SDMMC2SEL LL_RCC_SetSDMMCClockSource
2523 * @param SDMMCxSource This parameter can be one of the following values:
2524 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2525 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2526 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2527 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2528 *
2529 * (*) value not defined in all devices.
2530 * @retval None
2531 */
2532 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t SDMMCxSource)
2533 {
2534 MODIFY_REG(RCC->DCKCFGR2, (SDMMCxSource & 0xFFFF0000U), (SDMMCxSource << 16U));
2535 }
2536
2537 /**
2538 * @brief Configure 48Mhz domain clock source
2539 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetCK48MClockSource
2540 * @param CK48MxSource This parameter can be one of the following values:
2541 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2542 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2543 * @retval None
2544 */
2545 __STATIC_INLINE void LL_RCC_SetCK48MClockSource(uint32_t CK48MxSource)
2546 {
2547 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, CK48MxSource);
2548 }
2549
2550 /**
2551 * @brief Configure RNG clock source
2552 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetRNGClockSource
2553 * @param RNGxSource This parameter can be one of the following values:
2554 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2555 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2556 * @retval None
2557 */
2558 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t RNGxSource)
2559 {
2560 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, RNGxSource);
2561 }
2562
2563 /**
2564 * @brief Configure USB clock source
2565 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_SetUSBClockSource
2566 * @param USBxSource This parameter can be one of the following values:
2567 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2568 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2569 * @retval None
2570 */
2571 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t USBxSource)
2572 {
2573 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CK48MSEL, USBxSource);
2574 }
2575
2576 #if defined(CEC)
2577 /**
2578 * @brief Configure CEC clock source
2579 * @rmtoll DCKCFGR2 CECSEL LL_RCC_SetCECClockSource
2580 * @param Source This parameter can be one of the following values:
2581 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2582 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2583 * @retval None
2584 */
2585 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t Source)
2586 {
2587 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_CECSEL, Source);
2588 }
2589 #endif /* CEC */
2590
2591 /**
2592 * @brief Configure I2S clock source
2593 * @rmtoll CFGR I2SSRC LL_RCC_SetI2SClockSource
2594 * @param Source This parameter can be one of the following values:
2595 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2596 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2597 * @retval None
2598 */
2599 __STATIC_INLINE void LL_RCC_SetI2SClockSource(uint32_t Source)
2600 {
2601 MODIFY_REG(RCC->CFGR, RCC_CFGR_I2SSRC, Source);
2602 }
2603
2604 #if defined(DSI)
2605 /**
2606 * @brief Configure DSI clock source
2607 * @rmtoll DCKCFGR2 DSISEL LL_RCC_SetDSIClockSource
2608 * @param Source This parameter can be one of the following values:
2609 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2610 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2611 * @retval None
2612 */
2613 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t Source)
2614 {
2615 MODIFY_REG(RCC->DCKCFGR2, RCC_DCKCFGR2_DSISEL, Source);
2616 }
2617 #endif /* DSI */
2618
2619 #if defined(DFSDM1_Channel0)
2620 /**
2621 * @brief Configure DFSDM Audio clock source
2622 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_SetDFSDMAudioClockSource
2623 * @param Source This parameter can be one of the following values:
2624 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2625 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2626 * @retval None
2627 */
2628 __STATIC_INLINE void LL_RCC_SetDFSDMAudioClockSource(uint32_t Source)
2629 {
2630 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_ADFSDM1SEL, Source);
2631 }
2632
2633 /**
2634 * @brief Configure DFSDM Kernel clock source
2635 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_SetDFSDMClockSource
2636 * @param Source This parameter can be one of the following values:
2637 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2638 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2639 * @retval None
2640 */
2641 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t Source)
2642 {
2643 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_DFSDM1SEL, Source);
2644 }
2645 #endif /* DFSDM1_Channel0 */
2646
2647 /**
2648 * @brief Get USARTx clock source
2649 * @rmtoll DCKCFGR2 USART1SEL LL_RCC_GetUSARTClockSource\n
2650 * DCKCFGR2 USART2SEL LL_RCC_GetUSARTClockSource\n
2651 * DCKCFGR2 USART3SEL LL_RCC_GetUSARTClockSource\n
2652 * DCKCFGR2 USART6SEL LL_RCC_GetUSARTClockSource
2653 * @param USARTx This parameter can be one of the following values:
2654 * @arg @ref LL_RCC_USART1_CLKSOURCE
2655 * @arg @ref LL_RCC_USART2_CLKSOURCE
2656 * @arg @ref LL_RCC_USART3_CLKSOURCE
2657 * @arg @ref LL_RCC_USART6_CLKSOURCE
2658 * @retval Returned value can be one of the following values:
2659 * @arg @ref LL_RCC_USART1_CLKSOURCE_PCLK2
2660 * @arg @ref LL_RCC_USART1_CLKSOURCE_SYSCLK
2661 * @arg @ref LL_RCC_USART1_CLKSOURCE_HSI
2662 * @arg @ref LL_RCC_USART1_CLKSOURCE_LSE
2663 * @arg @ref LL_RCC_USART2_CLKSOURCE_PCLK1
2664 * @arg @ref LL_RCC_USART2_CLKSOURCE_SYSCLK
2665 * @arg @ref LL_RCC_USART2_CLKSOURCE_HSI
2666 * @arg @ref LL_RCC_USART2_CLKSOURCE_LSE
2667 * @arg @ref LL_RCC_USART3_CLKSOURCE_PCLK1
2668 * @arg @ref LL_RCC_USART3_CLKSOURCE_SYSCLK
2669 * @arg @ref LL_RCC_USART3_CLKSOURCE_HSI
2670 * @arg @ref LL_RCC_USART3_CLKSOURCE_LSE
2671 * @arg @ref LL_RCC_USART6_CLKSOURCE_PCLK2
2672 * @arg @ref LL_RCC_USART6_CLKSOURCE_SYSCLK
2673 * @arg @ref LL_RCC_USART6_CLKSOURCE_HSI
2674 * @arg @ref LL_RCC_USART6_CLKSOURCE_LSE
2675 */
2676 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t USARTx)
2677 {
2678 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USARTx) | (USARTx << 16U));
2679 }
2680
2681 /**
2682 * @brief Get UARTx clock source
2683 * @rmtoll DCKCFGR2 UART4SEL LL_RCC_GetUARTClockSource\n
2684 * DCKCFGR2 UART5SEL LL_RCC_GetUARTClockSource\n
2685 * DCKCFGR2 UART7SEL LL_RCC_GetUARTClockSource\n
2686 * DCKCFGR2 UART8SEL LL_RCC_GetUARTClockSource
2687 * @param UARTx This parameter can be one of the following values:
2688 * @arg @ref LL_RCC_UART4_CLKSOURCE
2689 * @arg @ref LL_RCC_UART5_CLKSOURCE
2690 * @arg @ref LL_RCC_UART7_CLKSOURCE
2691 * @arg @ref LL_RCC_UART8_CLKSOURCE
2692 * @retval Returned value can be one of the following values:
2693 * @arg @ref LL_RCC_UART4_CLKSOURCE_PCLK1
2694 * @arg @ref LL_RCC_UART4_CLKSOURCE_SYSCLK
2695 * @arg @ref LL_RCC_UART4_CLKSOURCE_HSI
2696 * @arg @ref LL_RCC_UART4_CLKSOURCE_LSE
2697 * @arg @ref LL_RCC_UART5_CLKSOURCE_PCLK1
2698 * @arg @ref LL_RCC_UART5_CLKSOURCE_SYSCLK
2699 * @arg @ref LL_RCC_UART5_CLKSOURCE_HSI
2700 * @arg @ref LL_RCC_UART5_CLKSOURCE_LSE
2701 * @arg @ref LL_RCC_UART7_CLKSOURCE_PCLK1
2702 * @arg @ref LL_RCC_UART7_CLKSOURCE_SYSCLK
2703 * @arg @ref LL_RCC_UART7_CLKSOURCE_HSI
2704 * @arg @ref LL_RCC_UART7_CLKSOURCE_LSE
2705 * @arg @ref LL_RCC_UART8_CLKSOURCE_PCLK1
2706 * @arg @ref LL_RCC_UART8_CLKSOURCE_SYSCLK
2707 * @arg @ref LL_RCC_UART8_CLKSOURCE_HSI
2708 * @arg @ref LL_RCC_UART8_CLKSOURCE_LSE
2709 */
2710 __STATIC_INLINE uint32_t LL_RCC_GetUARTClockSource(uint32_t UARTx)
2711 {
2712 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, UARTx) | (UARTx << 16U));
2713 }
2714
2715 /**
2716 * @brief Get I2Cx clock source
2717 * @rmtoll DCKCFGR2 I2C1SEL LL_RCC_GetI2CClockSource\n
2718 * DCKCFGR2 I2C2SEL LL_RCC_GetI2CClockSource\n
2719 * DCKCFGR2 I2C3SEL LL_RCC_GetI2CClockSource\n
2720 * DCKCFGR2 I2C4SEL LL_RCC_GetI2CClockSource
2721 * @param I2Cx This parameter can be one of the following values:
2722 * @arg @ref LL_RCC_I2C1_CLKSOURCE
2723 * @arg @ref LL_RCC_I2C2_CLKSOURCE
2724 * @arg @ref LL_RCC_I2C3_CLKSOURCE
2725 * @arg @ref LL_RCC_I2C4_CLKSOURCE (*)
2726 * @retval Returned value can be one of the following values:
2727 * @arg @ref LL_RCC_I2C1_CLKSOURCE_PCLK1
2728 * @arg @ref LL_RCC_I2C1_CLKSOURCE_SYSCLK
2729 * @arg @ref LL_RCC_I2C1_CLKSOURCE_HSI
2730 * @arg @ref LL_RCC_I2C2_CLKSOURCE_PCLK1
2731 * @arg @ref LL_RCC_I2C2_CLKSOURCE_SYSCLK
2732 * @arg @ref LL_RCC_I2C2_CLKSOURCE_HSI
2733 * @arg @ref LL_RCC_I2C3_CLKSOURCE_PCLK1
2734 * @arg @ref LL_RCC_I2C3_CLKSOURCE_SYSCLK
2735 * @arg @ref LL_RCC_I2C3_CLKSOURCE_HSI
2736 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK1 (*)
2737 * @arg @ref LL_RCC_I2C4_CLKSOURCE_SYSCLK (*)
2738 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI (*)
2739 *
2740 * (*) value not defined in all devices.
2741 */
2742 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t I2Cx)
2743 {
2744 return (uint32_t)((READ_BIT(RCC->DCKCFGR2, I2Cx) >> 16U) | I2Cx);
2745 }
2746
2747 /**
2748 * @brief Get LPTIMx clock source
2749 * @rmtoll DCKCFGR2 LPTIM1SEL LL_RCC_GetLPTIMClockSource
2750 * @param LPTIMx This parameter can be one of the following values:
2751 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
2752 * @retval Returned value can be one of the following values:
2753 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2754 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2755 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_HSI
2756 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2757 */
2758 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t LPTIMx)
2759 {
2760 (void)LPTIMx;
2761 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RCC_DCKCFGR2_LPTIM1SEL));
2762 }
2763
2764 /**
2765 * @brief Get SAIx clock source
2766 * @rmtoll DCKCFGR1 SAI1SEL LL_RCC_GetSAIClockSource\n
2767 * DCKCFGR1 SAI2SEL LL_RCC_GetSAIClockSource
2768 * @param SAIx This parameter can be one of the following values:
2769 * @arg @ref LL_RCC_SAI1_CLKSOURCE
2770 * @arg @ref LL_RCC_SAI2_CLKSOURCE
2771 * @retval Returned value can be one of the following values:
2772 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSAI
2773 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLI2S
2774 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PIN
2775 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLLSRC (*)
2776 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSAI
2777 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLI2S
2778 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PIN
2779 * @arg @ref LL_RCC_SAI2_CLKSOURCE_PLLSRC (*)
2780 *
2781 * (*) value not defined in all devices.
2782 */
2783 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t SAIx)
2784 {
2785 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, SAIx) >> 16U | SAIx);
2786 }
2787
2788 /**
2789 * @brief Get SDMMCx clock source
2790 * @rmtoll DCKCFGR2 SDMMC1SEL LL_RCC_GetSDMMCClockSource\n
2791 * DCKCFGR2 SDMMC2SEL LL_RCC_GetSDMMCClockSource
2792 * @param SDMMCx This parameter can be one of the following values:
2793 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE
2794 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE (*)
2795 * @retval Returned value can be one of the following values:
2796 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_PLL48CLK
2797 * @arg @ref LL_RCC_SDMMC1_CLKSOURCE_SYSCLK
2798 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_PLL48CLK (*)
2799 * @arg @ref LL_RCC_SDMMC2_CLKSOURCE_SYSCLK (*)
2800 *
2801 * (*) value not defined in all devices.
2802 */
2803 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t SDMMCx)
2804 {
2805 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, SDMMCx) >> 16U | SDMMCx);
2806 }
2807
2808 /**
2809 * @brief Get 48Mhz domain clock source
2810 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetCK48MClockSource
2811 * @param CK48Mx This parameter can be one of the following values:
2812 * @arg @ref LL_RCC_CK48M_CLKSOURCE
2813 * @retval Returned value can be one of the following values:
2814 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLL
2815 * @arg @ref LL_RCC_CK48M_CLKSOURCE_PLLSAI
2816 */
2817 __STATIC_INLINE uint32_t LL_RCC_GetCK48MClockSource(uint32_t CK48Mx)
2818 {
2819 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CK48Mx));
2820 }
2821
2822 /**
2823 * @brief Get RNGx clock source
2824 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetRNGClockSource
2825 * @param RNGx This parameter can be one of the following values:
2826 * @arg @ref LL_RCC_RNG_CLKSOURCE
2827 * @retval Returned value can be one of the following values:
2828 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL
2829 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLLSAI
2830 */
2831 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t RNGx)
2832 {
2833 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, RNGx));
2834 }
2835
2836 /**
2837 * @brief Get USBx clock source
2838 * @rmtoll DCKCFGR2 CK48MSEL LL_RCC_GetUSBClockSource
2839 * @param USBx This parameter can be one of the following values:
2840 * @arg @ref LL_RCC_USB_CLKSOURCE
2841 * @retval Returned value can be one of the following values:
2842 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL
2843 * @arg @ref LL_RCC_USB_CLKSOURCE_PLLSAI
2844 */
2845 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t USBx)
2846 {
2847 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, USBx));
2848 }
2849
2850 #if defined(CEC)
2851 /**
2852 * @brief Get CEC Clock Source
2853 * @rmtoll DCKCFGR2 CECSEL LL_RCC_GetCECClockSource
2854 * @param CECx This parameter can be one of the following values:
2855 * @arg @ref LL_RCC_CEC_CLKSOURCE
2856 * @retval Returned value can be one of the following values:
2857 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
2858 * @arg @ref LL_RCC_CEC_CLKSOURCE_HSI_DIV488
2859 */
2860 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t CECx)
2861 {
2862 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, CECx));
2863 }
2864 #endif /* CEC */
2865
2866 /**
2867 * @brief Get I2S Clock Source
2868 * @rmtoll CFGR I2SSRC LL_RCC_GetI2SClockSource
2869 * @param I2Sx This parameter can be one of the following values:
2870 * @arg @ref LL_RCC_I2S1_CLKSOURCE
2871 * @retval Returned value can be one of the following values:
2872 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PLLI2S
2873 * @arg @ref LL_RCC_I2S1_CLKSOURCE_PIN
2874 */
2875 __STATIC_INLINE uint32_t LL_RCC_GetI2SClockSource(uint32_t I2Sx)
2876 {
2877 return (uint32_t)(READ_BIT(RCC->CFGR, I2Sx));
2878 }
2879
2880 #if defined(DFSDM1_Channel0)
2881 /**
2882 * @brief Get DFSDM Audio Clock Source
2883 * @rmtoll DCKCFGR1 ADFSDM1SEL LL_RCC_GetDFSDMAudioClockSource
2884 * @param DFSDMx This parameter can be one of the following values:
2885 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE
2886 * @retval Returned value can be one of the following values:
2887 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI1
2888 * @arg @ref LL_RCC_DFSDM1_AUDIO_CLKSOURCE_SAI2
2889 */
2890 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMAudioClockSource(uint32_t DFSDMx)
2891 {
2892 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2893 }
2894
2895 /**
2896 * @brief Get DFSDM Audio Clock Source
2897 * @rmtoll DCKCFGR1 DFSDM1SEL LL_RCC_GetDFSDMClockSource
2898 * @param DFSDMx This parameter can be one of the following values:
2899 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
2900 * @retval Returned value can be one of the following values:
2901 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
2902 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
2903 */
2904 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t DFSDMx)
2905 {
2906 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, DFSDMx));
2907 }
2908 #endif /* DFSDM1_Channel0 */
2909
2910 #if defined(DSI)
2911 /**
2912 * @brief Get DSI Clock Source
2913 * @rmtoll DCKCFGR2 DSISEL LL_RCC_GetDSIClockSource
2914 * @param DSIx This parameter can be one of the following values:
2915 * @arg @ref LL_RCC_DSI_CLKSOURCE
2916 * @retval Returned value can be one of the following values:
2917 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
2918 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL
2919 */
2920 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t DSIx)
2921 {
2922 return (uint32_t)(READ_BIT(RCC->DCKCFGR2, DSIx));
2923 }
2924 #endif /* DSI */
2925
2926 /**
2927 * @}
2928 */
2929
2930 /** @defgroup RCC_LL_EF_RTC RTC
2931 * @{
2932 */
2933
2934 /**
2935 * @brief Set RTC Clock Source
2936 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
2937 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
2938 * set). The BDRST bit can be used to reset them.
2939 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
2940 * @param Source This parameter can be one of the following values:
2941 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2942 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2943 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2944 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2945 * @retval None
2946 */
2947 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
2948 {
2949 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
2950 }
2951
2952 /**
2953 * @brief Get RTC Clock Source
2954 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
2955 * @retval Returned value can be one of the following values:
2956 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
2957 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
2958 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
2959 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
2960 */
2961 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
2962 {
2963 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
2964 }
2965
2966 /**
2967 * @brief Enable RTC
2968 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
2969 * @retval None
2970 */
2971 __STATIC_INLINE void LL_RCC_EnableRTC(void)
2972 {
2973 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2974 }
2975
2976 /**
2977 * @brief Disable RTC
2978 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
2979 * @retval None
2980 */
2981 __STATIC_INLINE void LL_RCC_DisableRTC(void)
2982 {
2983 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
2984 }
2985
2986 /**
2987 * @brief Check if RTC has been enabled or not
2988 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
2989 * @retval State of bit (1 or 0).
2990 */
2991 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
2992 {
2993 return (READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN));
2994 }
2995
2996 /**
2997 * @brief Force the Backup domain reset
2998 * @rmtoll BDCR BDRST LL_RCC_ForceBackupDomainReset
2999 * @retval None
3000 */
3001 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
3002 {
3003 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3004 }
3005
3006 /**
3007 * @brief Release the Backup domain reset
3008 * @rmtoll BDCR BDRST LL_RCC_ReleaseBackupDomainReset
3009 * @retval None
3010 */
3011 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
3012 {
3013 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
3014 }
3015
3016 /**
3017 * @brief Set HSE Prescalers for RTC Clock
3018 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
3019 * @param Prescaler This parameter can be one of the following values:
3020 * @arg @ref LL_RCC_RTC_NOCLOCK
3021 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3022 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3023 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3024 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3025 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3026 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3027 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3028 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3029 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3030 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3031 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3032 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3033 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3034 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3035 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3036 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3037 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3038 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3039 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3040 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3041 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3042 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3043 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3044 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3045 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3046 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3047 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3048 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3049 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3050 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3051 * @retval None
3052 */
3053 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
3054 {
3055 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
3056 }
3057
3058 /**
3059 * @brief Get HSE Prescalers for RTC Clock
3060 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
3061 * @retval Returned value can be one of the following values:
3062 * @arg @ref LL_RCC_RTC_NOCLOCK
3063 * @arg @ref LL_RCC_RTC_HSE_DIV_2
3064 * @arg @ref LL_RCC_RTC_HSE_DIV_3
3065 * @arg @ref LL_RCC_RTC_HSE_DIV_4
3066 * @arg @ref LL_RCC_RTC_HSE_DIV_5
3067 * @arg @ref LL_RCC_RTC_HSE_DIV_6
3068 * @arg @ref LL_RCC_RTC_HSE_DIV_7
3069 * @arg @ref LL_RCC_RTC_HSE_DIV_8
3070 * @arg @ref LL_RCC_RTC_HSE_DIV_9
3071 * @arg @ref LL_RCC_RTC_HSE_DIV_10
3072 * @arg @ref LL_RCC_RTC_HSE_DIV_11
3073 * @arg @ref LL_RCC_RTC_HSE_DIV_12
3074 * @arg @ref LL_RCC_RTC_HSE_DIV_13
3075 * @arg @ref LL_RCC_RTC_HSE_DIV_14
3076 * @arg @ref LL_RCC_RTC_HSE_DIV_15
3077 * @arg @ref LL_RCC_RTC_HSE_DIV_16
3078 * @arg @ref LL_RCC_RTC_HSE_DIV_17
3079 * @arg @ref LL_RCC_RTC_HSE_DIV_18
3080 * @arg @ref LL_RCC_RTC_HSE_DIV_19
3081 * @arg @ref LL_RCC_RTC_HSE_DIV_20
3082 * @arg @ref LL_RCC_RTC_HSE_DIV_21
3083 * @arg @ref LL_RCC_RTC_HSE_DIV_22
3084 * @arg @ref LL_RCC_RTC_HSE_DIV_23
3085 * @arg @ref LL_RCC_RTC_HSE_DIV_24
3086 * @arg @ref LL_RCC_RTC_HSE_DIV_25
3087 * @arg @ref LL_RCC_RTC_HSE_DIV_26
3088 * @arg @ref LL_RCC_RTC_HSE_DIV_27
3089 * @arg @ref LL_RCC_RTC_HSE_DIV_28
3090 * @arg @ref LL_RCC_RTC_HSE_DIV_29
3091 * @arg @ref LL_RCC_RTC_HSE_DIV_30
3092 * @arg @ref LL_RCC_RTC_HSE_DIV_31
3093 */
3094 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
3095 {
3096 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
3097 }
3098
3099 /**
3100 * @}
3101 */
3102
3103 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
3104 * @{
3105 */
3106
3107 /**
3108 * @brief Set Timers Clock Prescalers
3109 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_SetTIMPrescaler
3110 * @param Prescaler This parameter can be one of the following values:
3111 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3112 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3113 * @retval None
3114 */
3115 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
3116 {
3117 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE, Prescaler);
3118 }
3119
3120 /**
3121 * @brief Get Timers Clock Prescalers
3122 * @rmtoll DCKCFGR1 TIMPRE LL_RCC_GetTIMPrescaler
3123 * @retval Returned value can be one of the following values:
3124 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
3125 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
3126 */
3127 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
3128 {
3129 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_TIMPRE));
3130 }
3131
3132 /**
3133 * @}
3134 */
3135
3136 /** @defgroup RCC_LL_EF_PLL PLL
3137 * @{
3138 */
3139
3140 /**
3141 * @brief Enable PLL
3142 * @rmtoll CR PLLON LL_RCC_PLL_Enable
3143 * @retval None
3144 */
3145 __STATIC_INLINE void LL_RCC_PLL_Enable(void)
3146 {
3147 SET_BIT(RCC->CR, RCC_CR_PLLON);
3148 }
3149
3150 /**
3151 * @brief Disable PLL
3152 * @note Cannot be disabled if the PLL clock is used as the system clock
3153 * @rmtoll CR PLLON LL_RCC_PLL_Disable
3154 * @retval None
3155 */
3156 __STATIC_INLINE void LL_RCC_PLL_Disable(void)
3157 {
3158 CLEAR_BIT(RCC->CR, RCC_CR_PLLON);
3159 }
3160
3161 /**
3162 * @brief Check if PLL Ready
3163 * @rmtoll CR PLLRDY LL_RCC_PLL_IsReady
3164 * @retval State of bit (1 or 0).
3165 */
3166 __STATIC_INLINE uint32_t LL_RCC_PLL_IsReady(void)
3167 {
3168 return (READ_BIT(RCC->CR, RCC_CR_PLLRDY) == (RCC_CR_PLLRDY));
3169 }
3170
3171 /**
3172 * @brief Configure PLL used for SYSCLK Domain
3173 * @note PLL Source and PLLM Divider can be written only when PLL,
3174 * PLLI2S and PLLSAI are disabled
3175 * @note PLLN/PLLP can be written only when PLL is disabled
3176 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_SYS\n
3177 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_SYS\n
3178 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_SYS\n
3179 * PLLCFGR PLLP LL_RCC_PLL_ConfigDomain_SYS
3180 * @param Source This parameter can be one of the following values:
3181 * @arg @ref LL_RCC_PLLSOURCE_HSI
3182 * @arg @ref LL_RCC_PLLSOURCE_HSE
3183 * @param PLLM This parameter can be one of the following values:
3184 * @arg @ref LL_RCC_PLLM_DIV_2
3185 * @arg @ref LL_RCC_PLLM_DIV_3
3186 * @arg @ref LL_RCC_PLLM_DIV_4
3187 * @arg @ref LL_RCC_PLLM_DIV_5
3188 * @arg @ref LL_RCC_PLLM_DIV_6
3189 * @arg @ref LL_RCC_PLLM_DIV_7
3190 * @arg @ref LL_RCC_PLLM_DIV_8
3191 * @arg @ref LL_RCC_PLLM_DIV_9
3192 * @arg @ref LL_RCC_PLLM_DIV_10
3193 * @arg @ref LL_RCC_PLLM_DIV_11
3194 * @arg @ref LL_RCC_PLLM_DIV_12
3195 * @arg @ref LL_RCC_PLLM_DIV_13
3196 * @arg @ref LL_RCC_PLLM_DIV_14
3197 * @arg @ref LL_RCC_PLLM_DIV_15
3198 * @arg @ref LL_RCC_PLLM_DIV_16
3199 * @arg @ref LL_RCC_PLLM_DIV_17
3200 * @arg @ref LL_RCC_PLLM_DIV_18
3201 * @arg @ref LL_RCC_PLLM_DIV_19
3202 * @arg @ref LL_RCC_PLLM_DIV_20
3203 * @arg @ref LL_RCC_PLLM_DIV_21
3204 * @arg @ref LL_RCC_PLLM_DIV_22
3205 * @arg @ref LL_RCC_PLLM_DIV_23
3206 * @arg @ref LL_RCC_PLLM_DIV_24
3207 * @arg @ref LL_RCC_PLLM_DIV_25
3208 * @arg @ref LL_RCC_PLLM_DIV_26
3209 * @arg @ref LL_RCC_PLLM_DIV_27
3210 * @arg @ref LL_RCC_PLLM_DIV_28
3211 * @arg @ref LL_RCC_PLLM_DIV_29
3212 * @arg @ref LL_RCC_PLLM_DIV_30
3213 * @arg @ref LL_RCC_PLLM_DIV_31
3214 * @arg @ref LL_RCC_PLLM_DIV_32
3215 * @arg @ref LL_RCC_PLLM_DIV_33
3216 * @arg @ref LL_RCC_PLLM_DIV_34
3217 * @arg @ref LL_RCC_PLLM_DIV_35
3218 * @arg @ref LL_RCC_PLLM_DIV_36
3219 * @arg @ref LL_RCC_PLLM_DIV_37
3220 * @arg @ref LL_RCC_PLLM_DIV_38
3221 * @arg @ref LL_RCC_PLLM_DIV_39
3222 * @arg @ref LL_RCC_PLLM_DIV_40
3223 * @arg @ref LL_RCC_PLLM_DIV_41
3224 * @arg @ref LL_RCC_PLLM_DIV_42
3225 * @arg @ref LL_RCC_PLLM_DIV_43
3226 * @arg @ref LL_RCC_PLLM_DIV_44
3227 * @arg @ref LL_RCC_PLLM_DIV_45
3228 * @arg @ref LL_RCC_PLLM_DIV_46
3229 * @arg @ref LL_RCC_PLLM_DIV_47
3230 * @arg @ref LL_RCC_PLLM_DIV_48
3231 * @arg @ref LL_RCC_PLLM_DIV_49
3232 * @arg @ref LL_RCC_PLLM_DIV_50
3233 * @arg @ref LL_RCC_PLLM_DIV_51
3234 * @arg @ref LL_RCC_PLLM_DIV_52
3235 * @arg @ref LL_RCC_PLLM_DIV_53
3236 * @arg @ref LL_RCC_PLLM_DIV_54
3237 * @arg @ref LL_RCC_PLLM_DIV_55
3238 * @arg @ref LL_RCC_PLLM_DIV_56
3239 * @arg @ref LL_RCC_PLLM_DIV_57
3240 * @arg @ref LL_RCC_PLLM_DIV_58
3241 * @arg @ref LL_RCC_PLLM_DIV_59
3242 * @arg @ref LL_RCC_PLLM_DIV_60
3243 * @arg @ref LL_RCC_PLLM_DIV_61
3244 * @arg @ref LL_RCC_PLLM_DIV_62
3245 * @arg @ref LL_RCC_PLLM_DIV_63
3246 * @param PLLN Between 50 and 432
3247 * @param PLLP This parameter can be one of the following values:
3248 * @arg @ref LL_RCC_PLLP_DIV_2
3249 * @arg @ref LL_RCC_PLLP_DIV_4
3250 * @arg @ref LL_RCC_PLLP_DIV_6
3251 * @arg @ref LL_RCC_PLLP_DIV_8
3252 * @retval None
3253 */
3254 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_SYS(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3255 {
3256 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLP,
3257 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLP);
3258 }
3259
3260 /**
3261 * @brief Configure PLL used for 48Mhz domain clock
3262 * @note PLL Source and PLLM Divider can be written only when PLL,
3263 * PLLI2S and PLLSAI are disabled
3264 * @note PLLN/PLLQ can be written only when PLL is disabled
3265 * @note This can be selected for USB, RNG, SDMMC1
3266 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_48M\n
3267 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_48M\n
3268 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_48M\n
3269 * PLLCFGR PLLQ LL_RCC_PLL_ConfigDomain_48M
3270 * @param Source This parameter can be one of the following values:
3271 * @arg @ref LL_RCC_PLLSOURCE_HSI
3272 * @arg @ref LL_RCC_PLLSOURCE_HSE
3273 * @param PLLM This parameter can be one of the following values:
3274 * @arg @ref LL_RCC_PLLM_DIV_2
3275 * @arg @ref LL_RCC_PLLM_DIV_3
3276 * @arg @ref LL_RCC_PLLM_DIV_4
3277 * @arg @ref LL_RCC_PLLM_DIV_5
3278 * @arg @ref LL_RCC_PLLM_DIV_6
3279 * @arg @ref LL_RCC_PLLM_DIV_7
3280 * @arg @ref LL_RCC_PLLM_DIV_8
3281 * @arg @ref LL_RCC_PLLM_DIV_9
3282 * @arg @ref LL_RCC_PLLM_DIV_10
3283 * @arg @ref LL_RCC_PLLM_DIV_11
3284 * @arg @ref LL_RCC_PLLM_DIV_12
3285 * @arg @ref LL_RCC_PLLM_DIV_13
3286 * @arg @ref LL_RCC_PLLM_DIV_14
3287 * @arg @ref LL_RCC_PLLM_DIV_15
3288 * @arg @ref LL_RCC_PLLM_DIV_16
3289 * @arg @ref LL_RCC_PLLM_DIV_17
3290 * @arg @ref LL_RCC_PLLM_DIV_18
3291 * @arg @ref LL_RCC_PLLM_DIV_19
3292 * @arg @ref LL_RCC_PLLM_DIV_20
3293 * @arg @ref LL_RCC_PLLM_DIV_21
3294 * @arg @ref LL_RCC_PLLM_DIV_22
3295 * @arg @ref LL_RCC_PLLM_DIV_23
3296 * @arg @ref LL_RCC_PLLM_DIV_24
3297 * @arg @ref LL_RCC_PLLM_DIV_25
3298 * @arg @ref LL_RCC_PLLM_DIV_26
3299 * @arg @ref LL_RCC_PLLM_DIV_27
3300 * @arg @ref LL_RCC_PLLM_DIV_28
3301 * @arg @ref LL_RCC_PLLM_DIV_29
3302 * @arg @ref LL_RCC_PLLM_DIV_30
3303 * @arg @ref LL_RCC_PLLM_DIV_31
3304 * @arg @ref LL_RCC_PLLM_DIV_32
3305 * @arg @ref LL_RCC_PLLM_DIV_33
3306 * @arg @ref LL_RCC_PLLM_DIV_34
3307 * @arg @ref LL_RCC_PLLM_DIV_35
3308 * @arg @ref LL_RCC_PLLM_DIV_36
3309 * @arg @ref LL_RCC_PLLM_DIV_37
3310 * @arg @ref LL_RCC_PLLM_DIV_38
3311 * @arg @ref LL_RCC_PLLM_DIV_39
3312 * @arg @ref LL_RCC_PLLM_DIV_40
3313 * @arg @ref LL_RCC_PLLM_DIV_41
3314 * @arg @ref LL_RCC_PLLM_DIV_42
3315 * @arg @ref LL_RCC_PLLM_DIV_43
3316 * @arg @ref LL_RCC_PLLM_DIV_44
3317 * @arg @ref LL_RCC_PLLM_DIV_45
3318 * @arg @ref LL_RCC_PLLM_DIV_46
3319 * @arg @ref LL_RCC_PLLM_DIV_47
3320 * @arg @ref LL_RCC_PLLM_DIV_48
3321 * @arg @ref LL_RCC_PLLM_DIV_49
3322 * @arg @ref LL_RCC_PLLM_DIV_50
3323 * @arg @ref LL_RCC_PLLM_DIV_51
3324 * @arg @ref LL_RCC_PLLM_DIV_52
3325 * @arg @ref LL_RCC_PLLM_DIV_53
3326 * @arg @ref LL_RCC_PLLM_DIV_54
3327 * @arg @ref LL_RCC_PLLM_DIV_55
3328 * @arg @ref LL_RCC_PLLM_DIV_56
3329 * @arg @ref LL_RCC_PLLM_DIV_57
3330 * @arg @ref LL_RCC_PLLM_DIV_58
3331 * @arg @ref LL_RCC_PLLM_DIV_59
3332 * @arg @ref LL_RCC_PLLM_DIV_60
3333 * @arg @ref LL_RCC_PLLM_DIV_61
3334 * @arg @ref LL_RCC_PLLM_DIV_62
3335 * @arg @ref LL_RCC_PLLM_DIV_63
3336 * @param PLLN Between 50 and 432
3337 * @param PLLQ This parameter can be one of the following values:
3338 * @arg @ref LL_RCC_PLLQ_DIV_2
3339 * @arg @ref LL_RCC_PLLQ_DIV_3
3340 * @arg @ref LL_RCC_PLLQ_DIV_4
3341 * @arg @ref LL_RCC_PLLQ_DIV_5
3342 * @arg @ref LL_RCC_PLLQ_DIV_6
3343 * @arg @ref LL_RCC_PLLQ_DIV_7
3344 * @arg @ref LL_RCC_PLLQ_DIV_8
3345 * @arg @ref LL_RCC_PLLQ_DIV_9
3346 * @arg @ref LL_RCC_PLLQ_DIV_10
3347 * @arg @ref LL_RCC_PLLQ_DIV_11
3348 * @arg @ref LL_RCC_PLLQ_DIV_12
3349 * @arg @ref LL_RCC_PLLQ_DIV_13
3350 * @arg @ref LL_RCC_PLLQ_DIV_14
3351 * @arg @ref LL_RCC_PLLQ_DIV_15
3352 * @retval None
3353 */
3354 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ)
3355 {
3356 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLQ,
3357 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLQ);
3358 }
3359
3360 #if defined(DSI)
3361 /**
3362 * @brief Configure PLL used for DSI clock
3363 * @note PLL Source and PLLM Divider can be written only when PLL,
3364 * PLLI2S and PLLSAI are disabled
3365 * @note PLLN/PLLR can be written only when PLL is disabled
3366 * @note This can be selected for DSI
3367 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_ConfigDomain_DSI\n
3368 * PLLCFGR PLLM LL_RCC_PLL_ConfigDomain_DSI\n
3369 * PLLCFGR PLLN LL_RCC_PLL_ConfigDomain_DSI\n
3370 * PLLCFGR PLLR LL_RCC_PLL_ConfigDomain_DSI
3371 * @param Source This parameter can be one of the following values:
3372 * @arg @ref LL_RCC_PLLSOURCE_HSI
3373 * @arg @ref LL_RCC_PLLSOURCE_HSE
3374 * @param PLLM This parameter can be one of the following values:
3375 * @arg @ref LL_RCC_PLLM_DIV_2
3376 * @arg @ref LL_RCC_PLLM_DIV_3
3377 * @arg @ref LL_RCC_PLLM_DIV_4
3378 * @arg @ref LL_RCC_PLLM_DIV_5
3379 * @arg @ref LL_RCC_PLLM_DIV_6
3380 * @arg @ref LL_RCC_PLLM_DIV_7
3381 * @arg @ref LL_RCC_PLLM_DIV_8
3382 * @arg @ref LL_RCC_PLLM_DIV_9
3383 * @arg @ref LL_RCC_PLLM_DIV_10
3384 * @arg @ref LL_RCC_PLLM_DIV_11
3385 * @arg @ref LL_RCC_PLLM_DIV_12
3386 * @arg @ref LL_RCC_PLLM_DIV_13
3387 * @arg @ref LL_RCC_PLLM_DIV_14
3388 * @arg @ref LL_RCC_PLLM_DIV_15
3389 * @arg @ref LL_RCC_PLLM_DIV_16
3390 * @arg @ref LL_RCC_PLLM_DIV_17
3391 * @arg @ref LL_RCC_PLLM_DIV_18
3392 * @arg @ref LL_RCC_PLLM_DIV_19
3393 * @arg @ref LL_RCC_PLLM_DIV_20
3394 * @arg @ref LL_RCC_PLLM_DIV_21
3395 * @arg @ref LL_RCC_PLLM_DIV_22
3396 * @arg @ref LL_RCC_PLLM_DIV_23
3397 * @arg @ref LL_RCC_PLLM_DIV_24
3398 * @arg @ref LL_RCC_PLLM_DIV_25
3399 * @arg @ref LL_RCC_PLLM_DIV_26
3400 * @arg @ref LL_RCC_PLLM_DIV_27
3401 * @arg @ref LL_RCC_PLLM_DIV_28
3402 * @arg @ref LL_RCC_PLLM_DIV_29
3403 * @arg @ref LL_RCC_PLLM_DIV_30
3404 * @arg @ref LL_RCC_PLLM_DIV_31
3405 * @arg @ref LL_RCC_PLLM_DIV_32
3406 * @arg @ref LL_RCC_PLLM_DIV_33
3407 * @arg @ref LL_RCC_PLLM_DIV_34
3408 * @arg @ref LL_RCC_PLLM_DIV_35
3409 * @arg @ref LL_RCC_PLLM_DIV_36
3410 * @arg @ref LL_RCC_PLLM_DIV_37
3411 * @arg @ref LL_RCC_PLLM_DIV_38
3412 * @arg @ref LL_RCC_PLLM_DIV_39
3413 * @arg @ref LL_RCC_PLLM_DIV_40
3414 * @arg @ref LL_RCC_PLLM_DIV_41
3415 * @arg @ref LL_RCC_PLLM_DIV_42
3416 * @arg @ref LL_RCC_PLLM_DIV_43
3417 * @arg @ref LL_RCC_PLLM_DIV_44
3418 * @arg @ref LL_RCC_PLLM_DIV_45
3419 * @arg @ref LL_RCC_PLLM_DIV_46
3420 * @arg @ref LL_RCC_PLLM_DIV_47
3421 * @arg @ref LL_RCC_PLLM_DIV_48
3422 * @arg @ref LL_RCC_PLLM_DIV_49
3423 * @arg @ref LL_RCC_PLLM_DIV_50
3424 * @arg @ref LL_RCC_PLLM_DIV_51
3425 * @arg @ref LL_RCC_PLLM_DIV_52
3426 * @arg @ref LL_RCC_PLLM_DIV_53
3427 * @arg @ref LL_RCC_PLLM_DIV_54
3428 * @arg @ref LL_RCC_PLLM_DIV_55
3429 * @arg @ref LL_RCC_PLLM_DIV_56
3430 * @arg @ref LL_RCC_PLLM_DIV_57
3431 * @arg @ref LL_RCC_PLLM_DIV_58
3432 * @arg @ref LL_RCC_PLLM_DIV_59
3433 * @arg @ref LL_RCC_PLLM_DIV_60
3434 * @arg @ref LL_RCC_PLLM_DIV_61
3435 * @arg @ref LL_RCC_PLLM_DIV_62
3436 * @arg @ref LL_RCC_PLLM_DIV_63
3437 * @param PLLN Between 50 and 432
3438 * @param PLLR This parameter can be one of the following values:
3439 * @arg @ref LL_RCC_PLLR_DIV_2
3440 * @arg @ref LL_RCC_PLLR_DIV_3
3441 * @arg @ref LL_RCC_PLLR_DIV_4
3442 * @arg @ref LL_RCC_PLLR_DIV_5
3443 * @arg @ref LL_RCC_PLLR_DIV_6
3444 * @arg @ref LL_RCC_PLLR_DIV_7
3445 * @retval None
3446 */
3447 __STATIC_INLINE void LL_RCC_PLL_ConfigDomain_DSI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
3448 {
3449 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM | RCC_PLLCFGR_PLLN | RCC_PLLCFGR_PLLR,
3450 Source | PLLM | PLLN << RCC_PLLCFGR_PLLN_Pos | PLLR);
3451 }
3452 #endif /* DSI */
3453
3454 /**
3455 * @brief Get Main PLL multiplication factor for VCO
3456 * @rmtoll PLLCFGR PLLN LL_RCC_PLL_GetN
3457 * @retval Between 50 and 432
3458 */
3459 __STATIC_INLINE uint32_t LL_RCC_PLL_GetN(void)
3460 {
3461 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLN) >> RCC_PLLCFGR_PLLN_Pos);
3462 }
3463
3464 /**
3465 * @brief Get Main PLL division factor for PLLP
3466 * @rmtoll PLLCFGR PLLP LL_RCC_PLL_GetP
3467 * @retval Returned value can be one of the following values:
3468 * @arg @ref LL_RCC_PLLP_DIV_2
3469 * @arg @ref LL_RCC_PLLP_DIV_4
3470 * @arg @ref LL_RCC_PLLP_DIV_6
3471 * @arg @ref LL_RCC_PLLP_DIV_8
3472 */
3473 __STATIC_INLINE uint32_t LL_RCC_PLL_GetP(void)
3474 {
3475 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLP));
3476 }
3477
3478 /**
3479 * @brief Get Main PLL division factor for PLLQ
3480 * @note used for PLL48MCLK selected for USB, RNG, SDMMC (48 MHz clock)
3481 * @rmtoll PLLCFGR PLLQ LL_RCC_PLL_GetQ
3482 * @retval Returned value can be one of the following values:
3483 * @arg @ref LL_RCC_PLLQ_DIV_2
3484 * @arg @ref LL_RCC_PLLQ_DIV_3
3485 * @arg @ref LL_RCC_PLLQ_DIV_4
3486 * @arg @ref LL_RCC_PLLQ_DIV_5
3487 * @arg @ref LL_RCC_PLLQ_DIV_6
3488 * @arg @ref LL_RCC_PLLQ_DIV_7
3489 * @arg @ref LL_RCC_PLLQ_DIV_8
3490 * @arg @ref LL_RCC_PLLQ_DIV_9
3491 * @arg @ref LL_RCC_PLLQ_DIV_10
3492 * @arg @ref LL_RCC_PLLQ_DIV_11
3493 * @arg @ref LL_RCC_PLLQ_DIV_12
3494 * @arg @ref LL_RCC_PLLQ_DIV_13
3495 * @arg @ref LL_RCC_PLLQ_DIV_14
3496 * @arg @ref LL_RCC_PLLQ_DIV_15
3497 */
3498 __STATIC_INLINE uint32_t LL_RCC_PLL_GetQ(void)
3499 {
3500 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLQ));
3501 }
3502
3503 #if defined(RCC_PLLCFGR_PLLR)
3504 /**
3505 * @brief Get Main PLL division factor for PLLR
3506 * @note used for PLLCLK (system clock)
3507 * @rmtoll PLLCFGR PLLR LL_RCC_PLL_GetR
3508 * @retval Returned value can be one of the following values:
3509 * @arg @ref LL_RCC_PLLR_DIV_2
3510 * @arg @ref LL_RCC_PLLR_DIV_3
3511 * @arg @ref LL_RCC_PLLR_DIV_4
3512 * @arg @ref LL_RCC_PLLR_DIV_5
3513 * @arg @ref LL_RCC_PLLR_DIV_6
3514 * @arg @ref LL_RCC_PLLR_DIV_7
3515 */
3516 __STATIC_INLINE uint32_t LL_RCC_PLL_GetR(void)
3517 {
3518 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLR));
3519 }
3520 #endif /* RCC_PLLCFGR_PLLR */
3521
3522 /**
3523 * @brief Get the oscillator used as PLL clock source.
3524 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLL_GetMainSource
3525 * @retval Returned value can be one of the following values:
3526 * @arg @ref LL_RCC_PLLSOURCE_HSI
3527 * @arg @ref LL_RCC_PLLSOURCE_HSE
3528 */
3529 __STATIC_INLINE uint32_t LL_RCC_PLL_GetMainSource(void)
3530 {
3531 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC));
3532 }
3533
3534 /**
3535 * @brief Get Division factor for the main PLL and other PLL
3536 * @rmtoll PLLCFGR PLLM LL_RCC_PLL_GetDivider
3537 * @retval Returned value can be one of the following values:
3538 * @arg @ref LL_RCC_PLLM_DIV_2
3539 * @arg @ref LL_RCC_PLLM_DIV_3
3540 * @arg @ref LL_RCC_PLLM_DIV_4
3541 * @arg @ref LL_RCC_PLLM_DIV_5
3542 * @arg @ref LL_RCC_PLLM_DIV_6
3543 * @arg @ref LL_RCC_PLLM_DIV_7
3544 * @arg @ref LL_RCC_PLLM_DIV_8
3545 * @arg @ref LL_RCC_PLLM_DIV_9
3546 * @arg @ref LL_RCC_PLLM_DIV_10
3547 * @arg @ref LL_RCC_PLLM_DIV_11
3548 * @arg @ref LL_RCC_PLLM_DIV_12
3549 * @arg @ref LL_RCC_PLLM_DIV_13
3550 * @arg @ref LL_RCC_PLLM_DIV_14
3551 * @arg @ref LL_RCC_PLLM_DIV_15
3552 * @arg @ref LL_RCC_PLLM_DIV_16
3553 * @arg @ref LL_RCC_PLLM_DIV_17
3554 * @arg @ref LL_RCC_PLLM_DIV_18
3555 * @arg @ref LL_RCC_PLLM_DIV_19
3556 * @arg @ref LL_RCC_PLLM_DIV_20
3557 * @arg @ref LL_RCC_PLLM_DIV_21
3558 * @arg @ref LL_RCC_PLLM_DIV_22
3559 * @arg @ref LL_RCC_PLLM_DIV_23
3560 * @arg @ref LL_RCC_PLLM_DIV_24
3561 * @arg @ref LL_RCC_PLLM_DIV_25
3562 * @arg @ref LL_RCC_PLLM_DIV_26
3563 * @arg @ref LL_RCC_PLLM_DIV_27
3564 * @arg @ref LL_RCC_PLLM_DIV_28
3565 * @arg @ref LL_RCC_PLLM_DIV_29
3566 * @arg @ref LL_RCC_PLLM_DIV_30
3567 * @arg @ref LL_RCC_PLLM_DIV_31
3568 * @arg @ref LL_RCC_PLLM_DIV_32
3569 * @arg @ref LL_RCC_PLLM_DIV_33
3570 * @arg @ref LL_RCC_PLLM_DIV_34
3571 * @arg @ref LL_RCC_PLLM_DIV_35
3572 * @arg @ref LL_RCC_PLLM_DIV_36
3573 * @arg @ref LL_RCC_PLLM_DIV_37
3574 * @arg @ref LL_RCC_PLLM_DIV_38
3575 * @arg @ref LL_RCC_PLLM_DIV_39
3576 * @arg @ref LL_RCC_PLLM_DIV_40
3577 * @arg @ref LL_RCC_PLLM_DIV_41
3578 * @arg @ref LL_RCC_PLLM_DIV_42
3579 * @arg @ref LL_RCC_PLLM_DIV_43
3580 * @arg @ref LL_RCC_PLLM_DIV_44
3581 * @arg @ref LL_RCC_PLLM_DIV_45
3582 * @arg @ref LL_RCC_PLLM_DIV_46
3583 * @arg @ref LL_RCC_PLLM_DIV_47
3584 * @arg @ref LL_RCC_PLLM_DIV_48
3585 * @arg @ref LL_RCC_PLLM_DIV_49
3586 * @arg @ref LL_RCC_PLLM_DIV_50
3587 * @arg @ref LL_RCC_PLLM_DIV_51
3588 * @arg @ref LL_RCC_PLLM_DIV_52
3589 * @arg @ref LL_RCC_PLLM_DIV_53
3590 * @arg @ref LL_RCC_PLLM_DIV_54
3591 * @arg @ref LL_RCC_PLLM_DIV_55
3592 * @arg @ref LL_RCC_PLLM_DIV_56
3593 * @arg @ref LL_RCC_PLLM_DIV_57
3594 * @arg @ref LL_RCC_PLLM_DIV_58
3595 * @arg @ref LL_RCC_PLLM_DIV_59
3596 * @arg @ref LL_RCC_PLLM_DIV_60
3597 * @arg @ref LL_RCC_PLLM_DIV_61
3598 * @arg @ref LL_RCC_PLLM_DIV_62
3599 * @arg @ref LL_RCC_PLLM_DIV_63
3600 */
3601 __STATIC_INLINE uint32_t LL_RCC_PLL_GetDivider(void)
3602 {
3603 return (uint32_t)(READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLLM));
3604 }
3605
3606 /**
3607 * @brief Configure Spread Spectrum used for PLL
3608 * @note These bits must be written before enabling PLL
3609 * @rmtoll SSCGR MODPER LL_RCC_PLL_ConfigSpreadSpectrum\n
3610 * SSCGR INCSTEP LL_RCC_PLL_ConfigSpreadSpectrum\n
3611 * SSCGR SPREADSEL LL_RCC_PLL_ConfigSpreadSpectrum
3612 * @param Mod Between Min_Data=0 and Max_Data=8191
3613 * @param Inc Between Min_Data=0 and Max_Data=32767
3614 * @param Sel This parameter can be one of the following values:
3615 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3616 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3617 * @retval None
3618 */
3619 __STATIC_INLINE void LL_RCC_PLL_ConfigSpreadSpectrum(uint32_t Mod, uint32_t Inc, uint32_t Sel)
3620 {
3621 MODIFY_REG(RCC->SSCGR, RCC_SSCGR_MODPER | RCC_SSCGR_INCSTEP | RCC_SSCGR_SPREADSEL, Mod | (Inc << RCC_SSCGR_INCSTEP_Pos) | Sel);
3622 }
3623
3624 /**
3625 * @brief Get Spread Spectrum Modulation Period for PLL
3626 * @rmtoll SSCGR MODPER LL_RCC_PLL_GetPeriodModulation
3627 * @retval Between Min_Data=0 and Max_Data=8191
3628 */
3629 __STATIC_INLINE uint32_t LL_RCC_PLL_GetPeriodModulation(void)
3630 {
3631 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_MODPER));
3632 }
3633
3634 /**
3635 * @brief Get Spread Spectrum Incrementation Step for PLL
3636 * @note Must be written before enabling PLL
3637 * @rmtoll SSCGR INCSTEP LL_RCC_PLL_GetStepIncrementation
3638 * @retval Between Min_Data=0 and Max_Data=32767
3639 */
3640 __STATIC_INLINE uint32_t LL_RCC_PLL_GetStepIncrementation(void)
3641 {
3642 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_INCSTEP) >> RCC_SSCGR_INCSTEP_Pos);
3643 }
3644
3645 /**
3646 * @brief Get Spread Spectrum Selection for PLL
3647 * @note Must be written before enabling PLL
3648 * @rmtoll SSCGR SPREADSEL LL_RCC_PLL_GetSpreadSelection
3649 * @retval Returned value can be one of the following values:
3650 * @arg @ref LL_RCC_SPREAD_SELECT_CENTER
3651 * @arg @ref LL_RCC_SPREAD_SELECT_DOWN
3652 */
3653 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSpreadSelection(void)
3654 {
3655 return (uint32_t)(READ_BIT(RCC->SSCGR, RCC_SSCGR_SPREADSEL));
3656 }
3657
3658 /**
3659 * @brief Enable Spread Spectrum for PLL.
3660 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Enable
3661 * @retval None
3662 */
3663 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Enable(void)
3664 {
3665 SET_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3666 }
3667
3668 /**
3669 * @brief Disable Spread Spectrum for PLL.
3670 * @rmtoll SSCGR SSCGEN LL_RCC_PLL_SpreadSpectrum_Disable
3671 * @retval None
3672 */
3673 __STATIC_INLINE void LL_RCC_PLL_SpreadSpectrum_Disable(void)
3674 {
3675 CLEAR_BIT(RCC->SSCGR, RCC_SSCGR_SSCGEN);
3676 }
3677
3678 /**
3679 * @}
3680 */
3681
3682 /** @defgroup RCC_LL_EF_PLLI2S PLLI2S
3683 * @{
3684 */
3685
3686 /**
3687 * @brief Enable PLLI2S
3688 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Enable
3689 * @retval None
3690 */
3691 __STATIC_INLINE void LL_RCC_PLLI2S_Enable(void)
3692 {
3693 SET_BIT(RCC->CR, RCC_CR_PLLI2SON);
3694 }
3695
3696 /**
3697 * @brief Disable PLLI2S
3698 * @rmtoll CR PLLI2SON LL_RCC_PLLI2S_Disable
3699 * @retval None
3700 */
3701 __STATIC_INLINE void LL_RCC_PLLI2S_Disable(void)
3702 {
3703 CLEAR_BIT(RCC->CR, RCC_CR_PLLI2SON);
3704 }
3705
3706 /**
3707 * @brief Check if PLLI2S Ready
3708 * @rmtoll CR PLLI2SRDY LL_RCC_PLLI2S_IsReady
3709 * @retval State of bit (1 or 0).
3710 */
3711 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_IsReady(void)
3712 {
3713 return (READ_BIT(RCC->CR, RCC_CR_PLLI2SRDY) == (RCC_CR_PLLI2SRDY));
3714 }
3715
3716 /**
3717 * @brief Configure PLLI2S used for SAI1 and SAI2 domain clock
3718 * @note PLL Source and PLLM Divider can be written only when PLL,
3719 * PLLI2S and PLLSAI are disabled
3720 * @note PLLN/PLLQ can be written only when PLLI2S is disabled
3721 * @note This can be selected for SAI1 and SAI2
3722 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SAI\n
3723 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SAI\n
3724 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SAI\n
3725 * PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_ConfigDomain_SAI\n
3726 * DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_ConfigDomain_SAI
3727 * @param Source This parameter can be one of the following values:
3728 * @arg @ref LL_RCC_PLLSOURCE_HSI
3729 * @arg @ref LL_RCC_PLLSOURCE_HSE
3730 * @param PLLM This parameter can be one of the following values:
3731 * @arg @ref LL_RCC_PLLM_DIV_2
3732 * @arg @ref LL_RCC_PLLM_DIV_3
3733 * @arg @ref LL_RCC_PLLM_DIV_4
3734 * @arg @ref LL_RCC_PLLM_DIV_5
3735 * @arg @ref LL_RCC_PLLM_DIV_6
3736 * @arg @ref LL_RCC_PLLM_DIV_7
3737 * @arg @ref LL_RCC_PLLM_DIV_8
3738 * @arg @ref LL_RCC_PLLM_DIV_9
3739 * @arg @ref LL_RCC_PLLM_DIV_10
3740 * @arg @ref LL_RCC_PLLM_DIV_11
3741 * @arg @ref LL_RCC_PLLM_DIV_12
3742 * @arg @ref LL_RCC_PLLM_DIV_13
3743 * @arg @ref LL_RCC_PLLM_DIV_14
3744 * @arg @ref LL_RCC_PLLM_DIV_15
3745 * @arg @ref LL_RCC_PLLM_DIV_16
3746 * @arg @ref LL_RCC_PLLM_DIV_17
3747 * @arg @ref LL_RCC_PLLM_DIV_18
3748 * @arg @ref LL_RCC_PLLM_DIV_19
3749 * @arg @ref LL_RCC_PLLM_DIV_20
3750 * @arg @ref LL_RCC_PLLM_DIV_21
3751 * @arg @ref LL_RCC_PLLM_DIV_22
3752 * @arg @ref LL_RCC_PLLM_DIV_23
3753 * @arg @ref LL_RCC_PLLM_DIV_24
3754 * @arg @ref LL_RCC_PLLM_DIV_25
3755 * @arg @ref LL_RCC_PLLM_DIV_26
3756 * @arg @ref LL_RCC_PLLM_DIV_27
3757 * @arg @ref LL_RCC_PLLM_DIV_28
3758 * @arg @ref LL_RCC_PLLM_DIV_29
3759 * @arg @ref LL_RCC_PLLM_DIV_30
3760 * @arg @ref LL_RCC_PLLM_DIV_31
3761 * @arg @ref LL_RCC_PLLM_DIV_32
3762 * @arg @ref LL_RCC_PLLM_DIV_33
3763 * @arg @ref LL_RCC_PLLM_DIV_34
3764 * @arg @ref LL_RCC_PLLM_DIV_35
3765 * @arg @ref LL_RCC_PLLM_DIV_36
3766 * @arg @ref LL_RCC_PLLM_DIV_37
3767 * @arg @ref LL_RCC_PLLM_DIV_38
3768 * @arg @ref LL_RCC_PLLM_DIV_39
3769 * @arg @ref LL_RCC_PLLM_DIV_40
3770 * @arg @ref LL_RCC_PLLM_DIV_41
3771 * @arg @ref LL_RCC_PLLM_DIV_42
3772 * @arg @ref LL_RCC_PLLM_DIV_43
3773 * @arg @ref LL_RCC_PLLM_DIV_44
3774 * @arg @ref LL_RCC_PLLM_DIV_45
3775 * @arg @ref LL_RCC_PLLM_DIV_46
3776 * @arg @ref LL_RCC_PLLM_DIV_47
3777 * @arg @ref LL_RCC_PLLM_DIV_48
3778 * @arg @ref LL_RCC_PLLM_DIV_49
3779 * @arg @ref LL_RCC_PLLM_DIV_50
3780 * @arg @ref LL_RCC_PLLM_DIV_51
3781 * @arg @ref LL_RCC_PLLM_DIV_52
3782 * @arg @ref LL_RCC_PLLM_DIV_53
3783 * @arg @ref LL_RCC_PLLM_DIV_54
3784 * @arg @ref LL_RCC_PLLM_DIV_55
3785 * @arg @ref LL_RCC_PLLM_DIV_56
3786 * @arg @ref LL_RCC_PLLM_DIV_57
3787 * @arg @ref LL_RCC_PLLM_DIV_58
3788 * @arg @ref LL_RCC_PLLM_DIV_59
3789 * @arg @ref LL_RCC_PLLM_DIV_60
3790 * @arg @ref LL_RCC_PLLM_DIV_61
3791 * @arg @ref LL_RCC_PLLM_DIV_62
3792 * @arg @ref LL_RCC_PLLM_DIV_63
3793 * @param PLLN Between 50 and 432
3794 * @param PLLQ This parameter can be one of the following values:
3795 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
3796 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
3797 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
3798 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
3799 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
3800 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
3801 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
3802 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
3803 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
3804 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
3805 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
3806 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
3807 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
3808 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
3809 * @param PLLDIVQ This parameter can be one of the following values:
3810 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
3811 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
3812 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
3813 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
3814 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
3815 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
3816 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
3817 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
3818 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
3819 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
3820 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
3821 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
3822 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
3823 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
3824 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
3825 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
3826 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
3827 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
3828 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
3829 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
3830 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
3831 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
3832 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
3833 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
3834 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
3835 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
3836 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
3837 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
3838 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
3839 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
3840 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
3841 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
3842 * @retval None
3843 */
3844 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
3845 {
3846 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3847 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SQ, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLQ);
3848 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ, PLLDIVQ);
3849 }
3850
3851 #if defined(SPDIFRX)
3852 /**
3853 * @brief Configure PLLI2S used for SPDIFRX domain clock
3854 * @note PLL Source and PLLM Divider can be written only when PLL,
3855 * PLLI2S and PLLSAI are disabled
3856 * @note PLLN/PLLP can be written only when PLLI2S is disabled
3857 * @note This can be selected for SPDIFRX
3858 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3859 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3860 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_SPDIFRX\n
3861 * PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_ConfigDomain_SPDIFRX
3862 * @param Source This parameter can be one of the following values:
3863 * @arg @ref LL_RCC_PLLSOURCE_HSI
3864 * @arg @ref LL_RCC_PLLSOURCE_HSE
3865 * @param PLLM This parameter can be one of the following values:
3866 * @arg @ref LL_RCC_PLLM_DIV_2
3867 * @arg @ref LL_RCC_PLLM_DIV_3
3868 * @arg @ref LL_RCC_PLLM_DIV_4
3869 * @arg @ref LL_RCC_PLLM_DIV_5
3870 * @arg @ref LL_RCC_PLLM_DIV_6
3871 * @arg @ref LL_RCC_PLLM_DIV_7
3872 * @arg @ref LL_RCC_PLLM_DIV_8
3873 * @arg @ref LL_RCC_PLLM_DIV_9
3874 * @arg @ref LL_RCC_PLLM_DIV_10
3875 * @arg @ref LL_RCC_PLLM_DIV_11
3876 * @arg @ref LL_RCC_PLLM_DIV_12
3877 * @arg @ref LL_RCC_PLLM_DIV_13
3878 * @arg @ref LL_RCC_PLLM_DIV_14
3879 * @arg @ref LL_RCC_PLLM_DIV_15
3880 * @arg @ref LL_RCC_PLLM_DIV_16
3881 * @arg @ref LL_RCC_PLLM_DIV_17
3882 * @arg @ref LL_RCC_PLLM_DIV_18
3883 * @arg @ref LL_RCC_PLLM_DIV_19
3884 * @arg @ref LL_RCC_PLLM_DIV_20
3885 * @arg @ref LL_RCC_PLLM_DIV_21
3886 * @arg @ref LL_RCC_PLLM_DIV_22
3887 * @arg @ref LL_RCC_PLLM_DIV_23
3888 * @arg @ref LL_RCC_PLLM_DIV_24
3889 * @arg @ref LL_RCC_PLLM_DIV_25
3890 * @arg @ref LL_RCC_PLLM_DIV_26
3891 * @arg @ref LL_RCC_PLLM_DIV_27
3892 * @arg @ref LL_RCC_PLLM_DIV_28
3893 * @arg @ref LL_RCC_PLLM_DIV_29
3894 * @arg @ref LL_RCC_PLLM_DIV_30
3895 * @arg @ref LL_RCC_PLLM_DIV_31
3896 * @arg @ref LL_RCC_PLLM_DIV_32
3897 * @arg @ref LL_RCC_PLLM_DIV_33
3898 * @arg @ref LL_RCC_PLLM_DIV_34
3899 * @arg @ref LL_RCC_PLLM_DIV_35
3900 * @arg @ref LL_RCC_PLLM_DIV_36
3901 * @arg @ref LL_RCC_PLLM_DIV_37
3902 * @arg @ref LL_RCC_PLLM_DIV_38
3903 * @arg @ref LL_RCC_PLLM_DIV_39
3904 * @arg @ref LL_RCC_PLLM_DIV_40
3905 * @arg @ref LL_RCC_PLLM_DIV_41
3906 * @arg @ref LL_RCC_PLLM_DIV_42
3907 * @arg @ref LL_RCC_PLLM_DIV_43
3908 * @arg @ref LL_RCC_PLLM_DIV_44
3909 * @arg @ref LL_RCC_PLLM_DIV_45
3910 * @arg @ref LL_RCC_PLLM_DIV_46
3911 * @arg @ref LL_RCC_PLLM_DIV_47
3912 * @arg @ref LL_RCC_PLLM_DIV_48
3913 * @arg @ref LL_RCC_PLLM_DIV_49
3914 * @arg @ref LL_RCC_PLLM_DIV_50
3915 * @arg @ref LL_RCC_PLLM_DIV_51
3916 * @arg @ref LL_RCC_PLLM_DIV_52
3917 * @arg @ref LL_RCC_PLLM_DIV_53
3918 * @arg @ref LL_RCC_PLLM_DIV_54
3919 * @arg @ref LL_RCC_PLLM_DIV_55
3920 * @arg @ref LL_RCC_PLLM_DIV_56
3921 * @arg @ref LL_RCC_PLLM_DIV_57
3922 * @arg @ref LL_RCC_PLLM_DIV_58
3923 * @arg @ref LL_RCC_PLLM_DIV_59
3924 * @arg @ref LL_RCC_PLLM_DIV_60
3925 * @arg @ref LL_RCC_PLLM_DIV_61
3926 * @arg @ref LL_RCC_PLLM_DIV_62
3927 * @arg @ref LL_RCC_PLLM_DIV_63
3928 * @param PLLN Between 50 and 432
3929 * @param PLLP This parameter can be one of the following values:
3930 * @arg @ref LL_RCC_PLLI2SP_DIV_2
3931 * @arg @ref LL_RCC_PLLI2SP_DIV_4
3932 * @arg @ref LL_RCC_PLLI2SP_DIV_6
3933 * @arg @ref LL_RCC_PLLI2SP_DIV_8
3934 * @retval None
3935 */
3936 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_SPDIFRX(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
3937 {
3938 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
3939 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SP, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLP);
3940 }
3941 #endif /* SPDIFRX */
3942
3943 /**
3944 * @brief Configure PLLI2S used for I2S1 domain clock
3945 * @note PLL Source and PLLM Divider can be written only when PLL,
3946 * PLLI2S and PLLSAI are disabled
3947 * @note PLLN/PLLR can be written only when PLLI2S is disabled
3948 * @note This can be selected for I2S
3949 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLI2S_ConfigDomain_I2S\n
3950 * PLLCFGR PLLM LL_RCC_PLLI2S_ConfigDomain_I2S\n
3951 * PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_ConfigDomain_I2S\n
3952 * PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_ConfigDomain_I2S
3953 * @param Source This parameter can be one of the following values:
3954 * @arg @ref LL_RCC_PLLSOURCE_HSI
3955 * @arg @ref LL_RCC_PLLSOURCE_HSE
3956 * @param PLLM This parameter can be one of the following values:
3957 * @arg @ref LL_RCC_PLLM_DIV_2
3958 * @arg @ref LL_RCC_PLLM_DIV_3
3959 * @arg @ref LL_RCC_PLLM_DIV_4
3960 * @arg @ref LL_RCC_PLLM_DIV_5
3961 * @arg @ref LL_RCC_PLLM_DIV_6
3962 * @arg @ref LL_RCC_PLLM_DIV_7
3963 * @arg @ref LL_RCC_PLLM_DIV_8
3964 * @arg @ref LL_RCC_PLLM_DIV_9
3965 * @arg @ref LL_RCC_PLLM_DIV_10
3966 * @arg @ref LL_RCC_PLLM_DIV_11
3967 * @arg @ref LL_RCC_PLLM_DIV_12
3968 * @arg @ref LL_RCC_PLLM_DIV_13
3969 * @arg @ref LL_RCC_PLLM_DIV_14
3970 * @arg @ref LL_RCC_PLLM_DIV_15
3971 * @arg @ref LL_RCC_PLLM_DIV_16
3972 * @arg @ref LL_RCC_PLLM_DIV_17
3973 * @arg @ref LL_RCC_PLLM_DIV_18
3974 * @arg @ref LL_RCC_PLLM_DIV_19
3975 * @arg @ref LL_RCC_PLLM_DIV_20
3976 * @arg @ref LL_RCC_PLLM_DIV_21
3977 * @arg @ref LL_RCC_PLLM_DIV_22
3978 * @arg @ref LL_RCC_PLLM_DIV_23
3979 * @arg @ref LL_RCC_PLLM_DIV_24
3980 * @arg @ref LL_RCC_PLLM_DIV_25
3981 * @arg @ref LL_RCC_PLLM_DIV_26
3982 * @arg @ref LL_RCC_PLLM_DIV_27
3983 * @arg @ref LL_RCC_PLLM_DIV_28
3984 * @arg @ref LL_RCC_PLLM_DIV_29
3985 * @arg @ref LL_RCC_PLLM_DIV_30
3986 * @arg @ref LL_RCC_PLLM_DIV_31
3987 * @arg @ref LL_RCC_PLLM_DIV_32
3988 * @arg @ref LL_RCC_PLLM_DIV_33
3989 * @arg @ref LL_RCC_PLLM_DIV_34
3990 * @arg @ref LL_RCC_PLLM_DIV_35
3991 * @arg @ref LL_RCC_PLLM_DIV_36
3992 * @arg @ref LL_RCC_PLLM_DIV_37
3993 * @arg @ref LL_RCC_PLLM_DIV_38
3994 * @arg @ref LL_RCC_PLLM_DIV_39
3995 * @arg @ref LL_RCC_PLLM_DIV_40
3996 * @arg @ref LL_RCC_PLLM_DIV_41
3997 * @arg @ref LL_RCC_PLLM_DIV_42
3998 * @arg @ref LL_RCC_PLLM_DIV_43
3999 * @arg @ref LL_RCC_PLLM_DIV_44
4000 * @arg @ref LL_RCC_PLLM_DIV_45
4001 * @arg @ref LL_RCC_PLLM_DIV_46
4002 * @arg @ref LL_RCC_PLLM_DIV_47
4003 * @arg @ref LL_RCC_PLLM_DIV_48
4004 * @arg @ref LL_RCC_PLLM_DIV_49
4005 * @arg @ref LL_RCC_PLLM_DIV_50
4006 * @arg @ref LL_RCC_PLLM_DIV_51
4007 * @arg @ref LL_RCC_PLLM_DIV_52
4008 * @arg @ref LL_RCC_PLLM_DIV_53
4009 * @arg @ref LL_RCC_PLLM_DIV_54
4010 * @arg @ref LL_RCC_PLLM_DIV_55
4011 * @arg @ref LL_RCC_PLLM_DIV_56
4012 * @arg @ref LL_RCC_PLLM_DIV_57
4013 * @arg @ref LL_RCC_PLLM_DIV_58
4014 * @arg @ref LL_RCC_PLLM_DIV_59
4015 * @arg @ref LL_RCC_PLLM_DIV_60
4016 * @arg @ref LL_RCC_PLLM_DIV_61
4017 * @arg @ref LL_RCC_PLLM_DIV_62
4018 * @arg @ref LL_RCC_PLLM_DIV_63
4019 * @param PLLN Between 50 and 432
4020 * @param PLLR This parameter can be one of the following values:
4021 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4022 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4023 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4024 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4025 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4026 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4027 * @retval None
4028 */
4029 __STATIC_INLINE void LL_RCC_PLLI2S_ConfigDomain_I2S(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR)
4030 {
4031 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4032 MODIFY_REG(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN | RCC_PLLI2SCFGR_PLLI2SR, PLLN << RCC_PLLI2SCFGR_PLLI2SN_Pos | PLLR);
4033 }
4034
4035 /**
4036 * @brief Get I2SPLL multiplication factor for VCO
4037 * @rmtoll PLLI2SCFGR PLLI2SN LL_RCC_PLLI2S_GetN
4038 * @retval Between 50 and 432
4039 */
4040 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetN(void)
4041 {
4042 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SN) >> RCC_PLLI2SCFGR_PLLI2SN_Pos);
4043 }
4044
4045 /**
4046 * @brief Get I2SPLL division factor for PLLI2SQ
4047 * @rmtoll PLLI2SCFGR PLLI2SQ LL_RCC_PLLI2S_GetQ
4048 * @retval Returned value can be one of the following values:
4049 * @arg @ref LL_RCC_PLLI2SQ_DIV_2
4050 * @arg @ref LL_RCC_PLLI2SQ_DIV_3
4051 * @arg @ref LL_RCC_PLLI2SQ_DIV_4
4052 * @arg @ref LL_RCC_PLLI2SQ_DIV_5
4053 * @arg @ref LL_RCC_PLLI2SQ_DIV_6
4054 * @arg @ref LL_RCC_PLLI2SQ_DIV_7
4055 * @arg @ref LL_RCC_PLLI2SQ_DIV_8
4056 * @arg @ref LL_RCC_PLLI2SQ_DIV_9
4057 * @arg @ref LL_RCC_PLLI2SQ_DIV_10
4058 * @arg @ref LL_RCC_PLLI2SQ_DIV_11
4059 * @arg @ref LL_RCC_PLLI2SQ_DIV_12
4060 * @arg @ref LL_RCC_PLLI2SQ_DIV_13
4061 * @arg @ref LL_RCC_PLLI2SQ_DIV_14
4062 * @arg @ref LL_RCC_PLLI2SQ_DIV_15
4063 */
4064 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetQ(void)
4065 {
4066 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SQ));
4067 }
4068
4069 /**
4070 * @brief Get I2SPLL division factor for PLLI2SR
4071 * @note used for PLLI2SCLK (I2S clock)
4072 * @rmtoll PLLI2SCFGR PLLI2SR LL_RCC_PLLI2S_GetR
4073 * @retval Returned value can be one of the following values:
4074 * @arg @ref LL_RCC_PLLI2SR_DIV_2
4075 * @arg @ref LL_RCC_PLLI2SR_DIV_3
4076 * @arg @ref LL_RCC_PLLI2SR_DIV_4
4077 * @arg @ref LL_RCC_PLLI2SR_DIV_5
4078 * @arg @ref LL_RCC_PLLI2SR_DIV_6
4079 * @arg @ref LL_RCC_PLLI2SR_DIV_7
4080 */
4081 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetR(void)
4082 {
4083 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SR));
4084 }
4085
4086 #if defined(RCC_PLLI2SCFGR_PLLI2SP)
4087 /**
4088 * @brief Get I2SPLL division factor for PLLI2SP
4089 * @note used for PLLSPDIFRXCLK (SPDIFRX clock)
4090 * @rmtoll PLLI2SCFGR PLLI2SP LL_RCC_PLLI2S_GetP
4091 * @retval Returned value can be one of the following values:
4092 * @arg @ref LL_RCC_PLLI2SP_DIV_2
4093 * @arg @ref LL_RCC_PLLI2SP_DIV_4
4094 * @arg @ref LL_RCC_PLLI2SP_DIV_6
4095 * @arg @ref LL_RCC_PLLI2SP_DIV_8
4096 */
4097 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetP(void)
4098 {
4099 return (uint32_t)(READ_BIT(RCC->PLLI2SCFGR, RCC_PLLI2SCFGR_PLLI2SP));
4100 }
4101 #endif /* RCC_PLLI2SCFGR_PLLI2SP */
4102
4103 /**
4104 * @brief Get I2SPLL division factor for PLLI2SDIVQ
4105 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4106 * @rmtoll DCKCFGR1 PLLI2SDIVQ LL_RCC_PLLI2S_GetDIVQ
4107 * @retval Returned value can be one of the following values:
4108 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_1
4109 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_2
4110 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_3
4111 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_4
4112 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_5
4113 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_6
4114 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_7
4115 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_8
4116 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_9
4117 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_10
4118 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_11
4119 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_12
4120 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_13
4121 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_14
4122 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_15
4123 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_16
4124 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_17
4125 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_18
4126 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_19
4127 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_20
4128 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_21
4129 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_22
4130 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_23
4131 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_24
4132 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_25
4133 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_26
4134 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_27
4135 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_28
4136 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_29
4137 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_30
4138 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_31
4139 * @arg @ref LL_RCC_PLLI2SDIVQ_DIV_32
4140 */
4141 __STATIC_INLINE uint32_t LL_RCC_PLLI2S_GetDIVQ(void)
4142 {
4143 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLI2SDIVQ));
4144 }
4145
4146 /**
4147 * @}
4148 */
4149
4150 /** @defgroup RCC_LL_EF_PLLSAI PLLSAI
4151 * @{
4152 */
4153
4154 /**
4155 * @brief Enable PLLSAI
4156 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Enable
4157 * @retval None
4158 */
4159 __STATIC_INLINE void LL_RCC_PLLSAI_Enable(void)
4160 {
4161 SET_BIT(RCC->CR, RCC_CR_PLLSAION);
4162 }
4163
4164 /**
4165 * @brief Disable PLLSAI
4166 * @rmtoll CR PLLSAION LL_RCC_PLLSAI_Disable
4167 * @retval None
4168 */
4169 __STATIC_INLINE void LL_RCC_PLLSAI_Disable(void)
4170 {
4171 CLEAR_BIT(RCC->CR, RCC_CR_PLLSAION);
4172 }
4173
4174 /**
4175 * @brief Check if PLLSAI Ready
4176 * @rmtoll CR PLLSAIRDY LL_RCC_PLLSAI_IsReady
4177 * @retval State of bit (1 or 0).
4178 */
4179 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_IsReady(void)
4180 {
4181 return (READ_BIT(RCC->CR, RCC_CR_PLLSAIRDY) == (RCC_CR_PLLSAIRDY));
4182 }
4183
4184 /**
4185 * @brief Configure PLLSAI used for SAI1 and SAI2 domain clock
4186 * @note PLL Source and PLLM Divider can be written only when PLL,
4187 * PLLI2S and PLLSAI are disabled
4188 * @note PLLN/PLLQ can be written only when PLLSAI is disabled
4189 * @note This can be selected for SAI1 and SAI2
4190 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_SAI\n
4191 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_SAI\n
4192 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_SAI\n
4193 * PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_ConfigDomain_SAI\n
4194 * DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_ConfigDomain_SAI
4195 * @param Source This parameter can be one of the following values:
4196 * @arg @ref LL_RCC_PLLSOURCE_HSI
4197 * @arg @ref LL_RCC_PLLSOURCE_HSE
4198 * @param PLLM This parameter can be one of the following values:
4199 * @arg @ref LL_RCC_PLLM_DIV_2
4200 * @arg @ref LL_RCC_PLLM_DIV_3
4201 * @arg @ref LL_RCC_PLLM_DIV_4
4202 * @arg @ref LL_RCC_PLLM_DIV_5
4203 * @arg @ref LL_RCC_PLLM_DIV_6
4204 * @arg @ref LL_RCC_PLLM_DIV_7
4205 * @arg @ref LL_RCC_PLLM_DIV_8
4206 * @arg @ref LL_RCC_PLLM_DIV_9
4207 * @arg @ref LL_RCC_PLLM_DIV_10
4208 * @arg @ref LL_RCC_PLLM_DIV_11
4209 * @arg @ref LL_RCC_PLLM_DIV_12
4210 * @arg @ref LL_RCC_PLLM_DIV_13
4211 * @arg @ref LL_RCC_PLLM_DIV_14
4212 * @arg @ref LL_RCC_PLLM_DIV_15
4213 * @arg @ref LL_RCC_PLLM_DIV_16
4214 * @arg @ref LL_RCC_PLLM_DIV_17
4215 * @arg @ref LL_RCC_PLLM_DIV_18
4216 * @arg @ref LL_RCC_PLLM_DIV_19
4217 * @arg @ref LL_RCC_PLLM_DIV_20
4218 * @arg @ref LL_RCC_PLLM_DIV_21
4219 * @arg @ref LL_RCC_PLLM_DIV_22
4220 * @arg @ref LL_RCC_PLLM_DIV_23
4221 * @arg @ref LL_RCC_PLLM_DIV_24
4222 * @arg @ref LL_RCC_PLLM_DIV_25
4223 * @arg @ref LL_RCC_PLLM_DIV_26
4224 * @arg @ref LL_RCC_PLLM_DIV_27
4225 * @arg @ref LL_RCC_PLLM_DIV_28
4226 * @arg @ref LL_RCC_PLLM_DIV_29
4227 * @arg @ref LL_RCC_PLLM_DIV_30
4228 * @arg @ref LL_RCC_PLLM_DIV_31
4229 * @arg @ref LL_RCC_PLLM_DIV_32
4230 * @arg @ref LL_RCC_PLLM_DIV_33
4231 * @arg @ref LL_RCC_PLLM_DIV_34
4232 * @arg @ref LL_RCC_PLLM_DIV_35
4233 * @arg @ref LL_RCC_PLLM_DIV_36
4234 * @arg @ref LL_RCC_PLLM_DIV_37
4235 * @arg @ref LL_RCC_PLLM_DIV_38
4236 * @arg @ref LL_RCC_PLLM_DIV_39
4237 * @arg @ref LL_RCC_PLLM_DIV_40
4238 * @arg @ref LL_RCC_PLLM_DIV_41
4239 * @arg @ref LL_RCC_PLLM_DIV_42
4240 * @arg @ref LL_RCC_PLLM_DIV_43
4241 * @arg @ref LL_RCC_PLLM_DIV_44
4242 * @arg @ref LL_RCC_PLLM_DIV_45
4243 * @arg @ref LL_RCC_PLLM_DIV_46
4244 * @arg @ref LL_RCC_PLLM_DIV_47
4245 * @arg @ref LL_RCC_PLLM_DIV_48
4246 * @arg @ref LL_RCC_PLLM_DIV_49
4247 * @arg @ref LL_RCC_PLLM_DIV_50
4248 * @arg @ref LL_RCC_PLLM_DIV_51
4249 * @arg @ref LL_RCC_PLLM_DIV_52
4250 * @arg @ref LL_RCC_PLLM_DIV_53
4251 * @arg @ref LL_RCC_PLLM_DIV_54
4252 * @arg @ref LL_RCC_PLLM_DIV_55
4253 * @arg @ref LL_RCC_PLLM_DIV_56
4254 * @arg @ref LL_RCC_PLLM_DIV_57
4255 * @arg @ref LL_RCC_PLLM_DIV_58
4256 * @arg @ref LL_RCC_PLLM_DIV_59
4257 * @arg @ref LL_RCC_PLLM_DIV_60
4258 * @arg @ref LL_RCC_PLLM_DIV_61
4259 * @arg @ref LL_RCC_PLLM_DIV_62
4260 * @arg @ref LL_RCC_PLLM_DIV_63
4261 * @param PLLN Between 50 and 432
4262 * @param PLLQ This parameter can be one of the following values:
4263 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4264 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4265 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4266 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4267 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4268 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4269 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4270 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4271 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4272 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4273 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4274 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4275 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4276 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4277 * @param PLLDIVQ This parameter can be one of the following values:
4278 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4279 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4280 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4281 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4282 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4283 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4284 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4285 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4286 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4287 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4288 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4289 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4290 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4291 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4292 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4293 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4294 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4295 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4296 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4297 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4298 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4299 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4300 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4301 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4302 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4303 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4304 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4305 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4306 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4307 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4308 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4309 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4310 * @retval None
4311 */
4312 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_SAI(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLQ, uint32_t PLLDIVQ)
4313 {
4314 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4315 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIQ, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLQ);
4316 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ, PLLDIVQ);
4317 }
4318
4319 /**
4320 * @brief Configure PLLSAI used for 48Mhz domain clock
4321 * @note PLL Source and PLLM Divider can be written only when PLL,
4322 * PLLI2S and PLLSAI are disabled
4323 * @note PLLN/PLLP can be written only when PLLSAI is disabled
4324 * @note This can be selected for USB, RNG, SDMMC1
4325 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_48M\n
4326 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_48M\n
4327 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_48M\n
4328 * PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_ConfigDomain_48M
4329 * @param Source This parameter can be one of the following values:
4330 * @arg @ref LL_RCC_PLLSOURCE_HSI
4331 * @arg @ref LL_RCC_PLLSOURCE_HSE
4332 * @param PLLM This parameter can be one of the following values:
4333 * @arg @ref LL_RCC_PLLM_DIV_2
4334 * @arg @ref LL_RCC_PLLM_DIV_3
4335 * @arg @ref LL_RCC_PLLM_DIV_4
4336 * @arg @ref LL_RCC_PLLM_DIV_5
4337 * @arg @ref LL_RCC_PLLM_DIV_6
4338 * @arg @ref LL_RCC_PLLM_DIV_7
4339 * @arg @ref LL_RCC_PLLM_DIV_8
4340 * @arg @ref LL_RCC_PLLM_DIV_9
4341 * @arg @ref LL_RCC_PLLM_DIV_10
4342 * @arg @ref LL_RCC_PLLM_DIV_11
4343 * @arg @ref LL_RCC_PLLM_DIV_12
4344 * @arg @ref LL_RCC_PLLM_DIV_13
4345 * @arg @ref LL_RCC_PLLM_DIV_14
4346 * @arg @ref LL_RCC_PLLM_DIV_15
4347 * @arg @ref LL_RCC_PLLM_DIV_16
4348 * @arg @ref LL_RCC_PLLM_DIV_17
4349 * @arg @ref LL_RCC_PLLM_DIV_18
4350 * @arg @ref LL_RCC_PLLM_DIV_19
4351 * @arg @ref LL_RCC_PLLM_DIV_20
4352 * @arg @ref LL_RCC_PLLM_DIV_21
4353 * @arg @ref LL_RCC_PLLM_DIV_22
4354 * @arg @ref LL_RCC_PLLM_DIV_23
4355 * @arg @ref LL_RCC_PLLM_DIV_24
4356 * @arg @ref LL_RCC_PLLM_DIV_25
4357 * @arg @ref LL_RCC_PLLM_DIV_26
4358 * @arg @ref LL_RCC_PLLM_DIV_27
4359 * @arg @ref LL_RCC_PLLM_DIV_28
4360 * @arg @ref LL_RCC_PLLM_DIV_29
4361 * @arg @ref LL_RCC_PLLM_DIV_30
4362 * @arg @ref LL_RCC_PLLM_DIV_31
4363 * @arg @ref LL_RCC_PLLM_DIV_32
4364 * @arg @ref LL_RCC_PLLM_DIV_33
4365 * @arg @ref LL_RCC_PLLM_DIV_34
4366 * @arg @ref LL_RCC_PLLM_DIV_35
4367 * @arg @ref LL_RCC_PLLM_DIV_36
4368 * @arg @ref LL_RCC_PLLM_DIV_37
4369 * @arg @ref LL_RCC_PLLM_DIV_38
4370 * @arg @ref LL_RCC_PLLM_DIV_39
4371 * @arg @ref LL_RCC_PLLM_DIV_40
4372 * @arg @ref LL_RCC_PLLM_DIV_41
4373 * @arg @ref LL_RCC_PLLM_DIV_42
4374 * @arg @ref LL_RCC_PLLM_DIV_43
4375 * @arg @ref LL_RCC_PLLM_DIV_44
4376 * @arg @ref LL_RCC_PLLM_DIV_45
4377 * @arg @ref LL_RCC_PLLM_DIV_46
4378 * @arg @ref LL_RCC_PLLM_DIV_47
4379 * @arg @ref LL_RCC_PLLM_DIV_48
4380 * @arg @ref LL_RCC_PLLM_DIV_49
4381 * @arg @ref LL_RCC_PLLM_DIV_50
4382 * @arg @ref LL_RCC_PLLM_DIV_51
4383 * @arg @ref LL_RCC_PLLM_DIV_52
4384 * @arg @ref LL_RCC_PLLM_DIV_53
4385 * @arg @ref LL_RCC_PLLM_DIV_54
4386 * @arg @ref LL_RCC_PLLM_DIV_55
4387 * @arg @ref LL_RCC_PLLM_DIV_56
4388 * @arg @ref LL_RCC_PLLM_DIV_57
4389 * @arg @ref LL_RCC_PLLM_DIV_58
4390 * @arg @ref LL_RCC_PLLM_DIV_59
4391 * @arg @ref LL_RCC_PLLM_DIV_60
4392 * @arg @ref LL_RCC_PLLM_DIV_61
4393 * @arg @ref LL_RCC_PLLM_DIV_62
4394 * @arg @ref LL_RCC_PLLM_DIV_63
4395 * @param PLLN Between 50 and 432
4396 * @param PLLP This parameter can be one of the following values:
4397 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4398 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4399 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4400 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4401 * @retval None
4402 */
4403 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_48M(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP)
4404 {
4405 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4406 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIP, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLP);
4407 }
4408
4409 #if defined(LTDC)
4410 /**
4411 * @brief Configure PLLSAI used for LTDC domain clock
4412 * @note PLL Source and PLLM Divider can be written only when PLL,
4413 * PLLI2S and PLLSAI are disabled
4414 * @note PLLN/PLLR can be written only when PLLSAI is disabled
4415 * @note This can be selected for LTDC
4416 * @rmtoll PLLCFGR PLLSRC LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4417 * PLLCFGR PLLM LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4418 * PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4419 * PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_ConfigDomain_LTDC\n
4420 * DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_ConfigDomain_LTDC
4421 * @param Source This parameter can be one of the following values:
4422 * @arg @ref LL_RCC_PLLSOURCE_HSI
4423 * @arg @ref LL_RCC_PLLSOURCE_HSE
4424 * @param PLLM This parameter can be one of the following values:
4425 * @arg @ref LL_RCC_PLLM_DIV_2
4426 * @arg @ref LL_RCC_PLLM_DIV_3
4427 * @arg @ref LL_RCC_PLLM_DIV_4
4428 * @arg @ref LL_RCC_PLLM_DIV_5
4429 * @arg @ref LL_RCC_PLLM_DIV_6
4430 * @arg @ref LL_RCC_PLLM_DIV_7
4431 * @arg @ref LL_RCC_PLLM_DIV_8
4432 * @arg @ref LL_RCC_PLLM_DIV_9
4433 * @arg @ref LL_RCC_PLLM_DIV_10
4434 * @arg @ref LL_RCC_PLLM_DIV_11
4435 * @arg @ref LL_RCC_PLLM_DIV_12
4436 * @arg @ref LL_RCC_PLLM_DIV_13
4437 * @arg @ref LL_RCC_PLLM_DIV_14
4438 * @arg @ref LL_RCC_PLLM_DIV_15
4439 * @arg @ref LL_RCC_PLLM_DIV_16
4440 * @arg @ref LL_RCC_PLLM_DIV_17
4441 * @arg @ref LL_RCC_PLLM_DIV_18
4442 * @arg @ref LL_RCC_PLLM_DIV_19
4443 * @arg @ref LL_RCC_PLLM_DIV_20
4444 * @arg @ref LL_RCC_PLLM_DIV_21
4445 * @arg @ref LL_RCC_PLLM_DIV_22
4446 * @arg @ref LL_RCC_PLLM_DIV_23
4447 * @arg @ref LL_RCC_PLLM_DIV_24
4448 * @arg @ref LL_RCC_PLLM_DIV_25
4449 * @arg @ref LL_RCC_PLLM_DIV_26
4450 * @arg @ref LL_RCC_PLLM_DIV_27
4451 * @arg @ref LL_RCC_PLLM_DIV_28
4452 * @arg @ref LL_RCC_PLLM_DIV_29
4453 * @arg @ref LL_RCC_PLLM_DIV_30
4454 * @arg @ref LL_RCC_PLLM_DIV_31
4455 * @arg @ref LL_RCC_PLLM_DIV_32
4456 * @arg @ref LL_RCC_PLLM_DIV_33
4457 * @arg @ref LL_RCC_PLLM_DIV_34
4458 * @arg @ref LL_RCC_PLLM_DIV_35
4459 * @arg @ref LL_RCC_PLLM_DIV_36
4460 * @arg @ref LL_RCC_PLLM_DIV_37
4461 * @arg @ref LL_RCC_PLLM_DIV_38
4462 * @arg @ref LL_RCC_PLLM_DIV_39
4463 * @arg @ref LL_RCC_PLLM_DIV_40
4464 * @arg @ref LL_RCC_PLLM_DIV_41
4465 * @arg @ref LL_RCC_PLLM_DIV_42
4466 * @arg @ref LL_RCC_PLLM_DIV_43
4467 * @arg @ref LL_RCC_PLLM_DIV_44
4468 * @arg @ref LL_RCC_PLLM_DIV_45
4469 * @arg @ref LL_RCC_PLLM_DIV_46
4470 * @arg @ref LL_RCC_PLLM_DIV_47
4471 * @arg @ref LL_RCC_PLLM_DIV_48
4472 * @arg @ref LL_RCC_PLLM_DIV_49
4473 * @arg @ref LL_RCC_PLLM_DIV_50
4474 * @arg @ref LL_RCC_PLLM_DIV_51
4475 * @arg @ref LL_RCC_PLLM_DIV_52
4476 * @arg @ref LL_RCC_PLLM_DIV_53
4477 * @arg @ref LL_RCC_PLLM_DIV_54
4478 * @arg @ref LL_RCC_PLLM_DIV_55
4479 * @arg @ref LL_RCC_PLLM_DIV_56
4480 * @arg @ref LL_RCC_PLLM_DIV_57
4481 * @arg @ref LL_RCC_PLLM_DIV_58
4482 * @arg @ref LL_RCC_PLLM_DIV_59
4483 * @arg @ref LL_RCC_PLLM_DIV_60
4484 * @arg @ref LL_RCC_PLLM_DIV_61
4485 * @arg @ref LL_RCC_PLLM_DIV_62
4486 * @arg @ref LL_RCC_PLLM_DIV_63
4487 * @param PLLN Between 50 and 432
4488 * @param PLLR This parameter can be one of the following values:
4489 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4490 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4491 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4492 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4493 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4494 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4495 * @param PLLDIVR This parameter can be one of the following values:
4496 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4497 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4498 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4499 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4500 * @retval None
4501 */
4502 __STATIC_INLINE void LL_RCC_PLLSAI_ConfigDomain_LTDC(uint32_t Source, uint32_t PLLM, uint32_t PLLN, uint32_t PLLR, uint32_t PLLDIVR)
4503 {
4504 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLLSRC | RCC_PLLCFGR_PLLM, Source | PLLM);
4505 MODIFY_REG(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN | RCC_PLLSAICFGR_PLLSAIR, PLLN << RCC_PLLSAICFGR_PLLSAIN_Pos | PLLR);
4506 MODIFY_REG(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR, PLLDIVR);
4507 }
4508 #endif /* LTDC */
4509
4510 /**
4511 * @brief Get SAIPLL multiplication factor for VCO
4512 * @rmtoll PLLSAICFGR PLLSAIN LL_RCC_PLLSAI_GetN
4513 * @retval Between 50 and 432
4514 */
4515 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetN(void)
4516 {
4517 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIN) >> RCC_PLLSAICFGR_PLLSAIN_Pos);
4518 }
4519
4520 /**
4521 * @brief Get SAIPLL division factor for PLLSAIQ
4522 * @rmtoll PLLSAICFGR PLLSAIQ LL_RCC_PLLSAI_GetQ
4523 * @retval Returned value can be one of the following values:
4524 * @arg @ref LL_RCC_PLLSAIQ_DIV_2
4525 * @arg @ref LL_RCC_PLLSAIQ_DIV_3
4526 * @arg @ref LL_RCC_PLLSAIQ_DIV_4
4527 * @arg @ref LL_RCC_PLLSAIQ_DIV_5
4528 * @arg @ref LL_RCC_PLLSAIQ_DIV_6
4529 * @arg @ref LL_RCC_PLLSAIQ_DIV_7
4530 * @arg @ref LL_RCC_PLLSAIQ_DIV_8
4531 * @arg @ref LL_RCC_PLLSAIQ_DIV_9
4532 * @arg @ref LL_RCC_PLLSAIQ_DIV_10
4533 * @arg @ref LL_RCC_PLLSAIQ_DIV_11
4534 * @arg @ref LL_RCC_PLLSAIQ_DIV_12
4535 * @arg @ref LL_RCC_PLLSAIQ_DIV_13
4536 * @arg @ref LL_RCC_PLLSAIQ_DIV_14
4537 * @arg @ref LL_RCC_PLLSAIQ_DIV_15
4538 */
4539 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetQ(void)
4540 {
4541 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIQ));
4542 }
4543
4544 #if defined(RCC_PLLSAICFGR_PLLSAIR)
4545 /**
4546 * @brief Get SAIPLL division factor for PLLSAIR
4547 * @note used for PLLSAICLK (SAI clock)
4548 * @rmtoll PLLSAICFGR PLLSAIR LL_RCC_PLLSAI_GetR
4549 * @retval Returned value can be one of the following values:
4550 * @arg @ref LL_RCC_PLLSAIR_DIV_2
4551 * @arg @ref LL_RCC_PLLSAIR_DIV_3
4552 * @arg @ref LL_RCC_PLLSAIR_DIV_4
4553 * @arg @ref LL_RCC_PLLSAIR_DIV_5
4554 * @arg @ref LL_RCC_PLLSAIR_DIV_6
4555 * @arg @ref LL_RCC_PLLSAIR_DIV_7
4556 */
4557 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetR(void)
4558 {
4559 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIR));
4560 }
4561 #endif /* RCC_PLLSAICFGR_PLLSAIR */
4562
4563 /**
4564 * @brief Get SAIPLL division factor for PLLSAIP
4565 * @note used for PLL48MCLK (48M domain clock)
4566 * @rmtoll PLLSAICFGR PLLSAIP LL_RCC_PLLSAI_GetP
4567 * @retval Returned value can be one of the following values:
4568 * @arg @ref LL_RCC_PLLSAIP_DIV_2
4569 * @arg @ref LL_RCC_PLLSAIP_DIV_4
4570 * @arg @ref LL_RCC_PLLSAIP_DIV_6
4571 * @arg @ref LL_RCC_PLLSAIP_DIV_8
4572 */
4573 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetP(void)
4574 {
4575 return (uint32_t)(READ_BIT(RCC->PLLSAICFGR, RCC_PLLSAICFGR_PLLSAIP));
4576 }
4577
4578 /**
4579 * @brief Get SAIPLL division factor for PLLSAIDIVQ
4580 * @note used PLLSAI1CLK, PLLSAI2CLK selected (SAI1 and SAI2 clock)
4581 * @rmtoll DCKCFGR1 PLLSAIDIVQ LL_RCC_PLLSAI_GetDIVQ
4582 * @retval Returned value can be one of the following values:
4583 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_1
4584 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_2
4585 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_3
4586 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_4
4587 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_5
4588 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_6
4589 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_7
4590 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_8
4591 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_9
4592 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_10
4593 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_11
4594 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_12
4595 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_13
4596 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_14
4597 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_15
4598 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_16
4599 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_17
4600 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_18
4601 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_19
4602 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_20
4603 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_21
4604 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_22
4605 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_23
4606 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_24
4607 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_25
4608 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_26
4609 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_27
4610 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_28
4611 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_29
4612 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_30
4613 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_31
4614 * @arg @ref LL_RCC_PLLSAIDIVQ_DIV_32
4615 */
4616 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVQ(void)
4617 {
4618 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVQ));
4619 }
4620
4621 #if defined(RCC_DCKCFGR1_PLLSAIDIVR)
4622 /**
4623 * @brief Get SAIPLL division factor for PLLSAIDIVR
4624 * @note used for LTDC domain clock
4625 * @rmtoll DCKCFGR1 PLLSAIDIVR LL_RCC_PLLSAI_GetDIVR
4626 * @retval Returned value can be one of the following values:
4627 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_2
4628 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_4
4629 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_8
4630 * @arg @ref LL_RCC_PLLSAIDIVR_DIV_16
4631 */
4632 __STATIC_INLINE uint32_t LL_RCC_PLLSAI_GetDIVR(void)
4633 {
4634 return (uint32_t)(READ_BIT(RCC->DCKCFGR1, RCC_DCKCFGR1_PLLSAIDIVR));
4635 }
4636 #endif /* RCC_DCKCFGR1_PLLSAIDIVR */
4637
4638 /**
4639 * @}
4640 */
4641
4642 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
4643 * @{
4644 */
4645
4646 /**
4647 * @brief Clear LSI ready interrupt flag
4648 * @rmtoll CIR LSIRDYC LL_RCC_ClearFlag_LSIRDY
4649 * @retval None
4650 */
4651 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
4652 {
4653 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYC);
4654 }
4655
4656 /**
4657 * @brief Clear LSE ready interrupt flag
4658 * @rmtoll CIR LSERDYC LL_RCC_ClearFlag_LSERDY
4659 * @retval None
4660 */
4661 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
4662 {
4663 SET_BIT(RCC->CIR, RCC_CIR_LSERDYC);
4664 }
4665
4666 /**
4667 * @brief Clear HSI ready interrupt flag
4668 * @rmtoll CIR HSIRDYC LL_RCC_ClearFlag_HSIRDY
4669 * @retval None
4670 */
4671 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
4672 {
4673 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYC);
4674 }
4675
4676 /**
4677 * @brief Clear HSE ready interrupt flag
4678 * @rmtoll CIR HSERDYC LL_RCC_ClearFlag_HSERDY
4679 * @retval None
4680 */
4681 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
4682 {
4683 SET_BIT(RCC->CIR, RCC_CIR_HSERDYC);
4684 }
4685
4686 /**
4687 * @brief Clear PLL ready interrupt flag
4688 * @rmtoll CIR PLLRDYC LL_RCC_ClearFlag_PLLRDY
4689 * @retval None
4690 */
4691 __STATIC_INLINE void LL_RCC_ClearFlag_PLLRDY(void)
4692 {
4693 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYC);
4694 }
4695
4696 /**
4697 * @brief Clear PLLI2S ready interrupt flag
4698 * @rmtoll CIR PLLI2SRDYC LL_RCC_ClearFlag_PLLI2SRDY
4699 * @retval None
4700 */
4701 __STATIC_INLINE void LL_RCC_ClearFlag_PLLI2SRDY(void)
4702 {
4703 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYC);
4704 }
4705
4706 /**
4707 * @brief Clear PLLSAI ready interrupt flag
4708 * @rmtoll CIR PLLSAIRDYC LL_RCC_ClearFlag_PLLSAIRDY
4709 * @retval None
4710 */
4711 __STATIC_INLINE void LL_RCC_ClearFlag_PLLSAIRDY(void)
4712 {
4713 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYC);
4714 }
4715
4716 /**
4717 * @brief Clear Clock security system interrupt flag
4718 * @rmtoll CIR CSSC LL_RCC_ClearFlag_HSECSS
4719 * @retval None
4720 */
4721 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
4722 {
4723 SET_BIT(RCC->CIR, RCC_CIR_CSSC);
4724 }
4725
4726 /**
4727 * @brief Check if LSI ready interrupt occurred or not
4728 * @rmtoll CIR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
4729 * @retval State of bit (1 or 0).
4730 */
4731 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
4732 {
4733 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYF) == (RCC_CIR_LSIRDYF));
4734 }
4735
4736 /**
4737 * @brief Check if LSE ready interrupt occurred or not
4738 * @rmtoll CIR LSERDYF LL_RCC_IsActiveFlag_LSERDY
4739 * @retval State of bit (1 or 0).
4740 */
4741 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
4742 {
4743 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYF) == (RCC_CIR_LSERDYF));
4744 }
4745
4746 /**
4747 * @brief Check if HSI ready interrupt occurred or not
4748 * @rmtoll CIR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
4749 * @retval State of bit (1 or 0).
4750 */
4751 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
4752 {
4753 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYF) == (RCC_CIR_HSIRDYF));
4754 }
4755
4756 /**
4757 * @brief Check if HSE ready interrupt occurred or not
4758 * @rmtoll CIR HSERDYF LL_RCC_IsActiveFlag_HSERDY
4759 * @retval State of bit (1 or 0).
4760 */
4761 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
4762 {
4763 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYF) == (RCC_CIR_HSERDYF));
4764 }
4765
4766 /**
4767 * @brief Check if PLL ready interrupt occurred or not
4768 * @rmtoll CIR PLLRDYF LL_RCC_IsActiveFlag_PLLRDY
4769 * @retval State of bit (1 or 0).
4770 */
4771 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLRDY(void)
4772 {
4773 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYF) == (RCC_CIR_PLLRDYF));
4774 }
4775
4776 /**
4777 * @brief Check if PLLI2S ready interrupt occurred or not
4778 * @rmtoll CIR PLLI2SRDYF LL_RCC_IsActiveFlag_PLLI2SRDY
4779 * @retval State of bit (1 or 0).
4780 */
4781 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLI2SRDY(void)
4782 {
4783 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYF) == (RCC_CIR_PLLI2SRDYF));
4784 }
4785
4786 /**
4787 * @brief Check if PLLSAI ready interrupt occurred or not
4788 * @rmtoll CIR PLLSAIRDYF LL_RCC_IsActiveFlag_PLLSAIRDY
4789 * @retval State of bit (1 or 0).
4790 */
4791 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLLSAIRDY(void)
4792 {
4793 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYF) == (RCC_CIR_PLLSAIRDYF));
4794 }
4795
4796 /**
4797 * @brief Check if Clock security system interrupt occurred or not
4798 * @rmtoll CIR CSSF LL_RCC_IsActiveFlag_HSECSS
4799 * @retval State of bit (1 or 0).
4800 */
4801 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
4802 {
4803 return (READ_BIT(RCC->CIR, RCC_CIR_CSSF) == (RCC_CIR_CSSF));
4804 }
4805
4806 /**
4807 * @brief Check if RCC flag Independent Watchdog reset is set or not.
4808 * @rmtoll CSR IWDGRSTF LL_RCC_IsActiveFlag_IWDGRST
4809 * @retval State of bit (1 or 0).
4810 */
4811 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDGRST(void)
4812 {
4813 return (READ_BIT(RCC->CSR, RCC_CSR_IWDGRSTF) == (RCC_CSR_IWDGRSTF));
4814 }
4815
4816 /**
4817 * @brief Check if RCC flag Low Power reset is set or not.
4818 * @rmtoll CSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST
4819 * @retval State of bit (1 or 0).
4820 */
4821 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
4822 {
4823 return (READ_BIT(RCC->CSR, RCC_CSR_LPWRRSTF) == (RCC_CSR_LPWRRSTF));
4824 }
4825
4826 /**
4827 * @brief Check if RCC flag Pin reset is set or not.
4828 * @rmtoll CSR PINRSTF LL_RCC_IsActiveFlag_PINRST
4829 * @retval State of bit (1 or 0).
4830 */
4831 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
4832 {
4833 return (READ_BIT(RCC->CSR, RCC_CSR_PINRSTF) == (RCC_CSR_PINRSTF));
4834 }
4835
4836 /**
4837 * @brief Check if RCC flag POR/PDR reset is set or not.
4838 * @rmtoll CSR PORRSTF LL_RCC_IsActiveFlag_PORRST
4839 * @retval State of bit (1 or 0).
4840 */
4841 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
4842 {
4843 return (READ_BIT(RCC->CSR, RCC_CSR_PORRSTF) == (RCC_CSR_PORRSTF));
4844 }
4845
4846 /**
4847 * @brief Check if RCC flag Software reset is set or not.
4848 * @rmtoll CSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST
4849 * @retval State of bit (1 or 0).
4850 */
4851 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
4852 {
4853 return (READ_BIT(RCC->CSR, RCC_CSR_SFTRSTF) == (RCC_CSR_SFTRSTF));
4854 }
4855
4856 /**
4857 * @brief Check if RCC flag Window Watchdog reset is set or not.
4858 * @rmtoll CSR WWDGRSTF LL_RCC_IsActiveFlag_WWDGRST
4859 * @retval State of bit (1 or 0).
4860 */
4861 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDGRST(void)
4862 {
4863 return (READ_BIT(RCC->CSR, RCC_CSR_WWDGRSTF) == (RCC_CSR_WWDGRSTF));
4864 }
4865
4866 /**
4867 * @brief Check if RCC flag BOR reset is set or not.
4868 * @rmtoll CSR BORRSTF LL_RCC_IsActiveFlag_BORRST
4869 * @retval State of bit (1 or 0).
4870 */
4871 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
4872 {
4873 return (READ_BIT(RCC->CSR, RCC_CSR_BORRSTF) == (RCC_CSR_BORRSTF));
4874 }
4875
4876 /**
4877 * @brief Set RMVF bit to clear the reset flags.
4878 * @rmtoll CSR RMVF LL_RCC_ClearResetFlags
4879 * @retval None
4880 */
4881 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
4882 {
4883 SET_BIT(RCC->CSR, RCC_CSR_RMVF);
4884 }
4885
4886 /**
4887 * @}
4888 */
4889
4890 /** @defgroup RCC_LL_EF_IT_Management IT Management
4891 * @{
4892 */
4893
4894 /**
4895 * @brief Enable LSI ready interrupt
4896 * @rmtoll CIR LSIRDYIE LL_RCC_EnableIT_LSIRDY
4897 * @retval None
4898 */
4899 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
4900 {
4901 SET_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4902 }
4903
4904 /**
4905 * @brief Enable LSE ready interrupt
4906 * @rmtoll CIR LSERDYIE LL_RCC_EnableIT_LSERDY
4907 * @retval None
4908 */
4909 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
4910 {
4911 SET_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4912 }
4913
4914 /**
4915 * @brief Enable HSI ready interrupt
4916 * @rmtoll CIR HSIRDYIE LL_RCC_EnableIT_HSIRDY
4917 * @retval None
4918 */
4919 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
4920 {
4921 SET_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4922 }
4923
4924 /**
4925 * @brief Enable HSE ready interrupt
4926 * @rmtoll CIR HSERDYIE LL_RCC_EnableIT_HSERDY
4927 * @retval None
4928 */
4929 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
4930 {
4931 SET_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
4932 }
4933
4934 /**
4935 * @brief Enable PLL ready interrupt
4936 * @rmtoll CIR PLLRDYIE LL_RCC_EnableIT_PLLRDY
4937 * @retval None
4938 */
4939 __STATIC_INLINE void LL_RCC_EnableIT_PLLRDY(void)
4940 {
4941 SET_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
4942 }
4943
4944 /**
4945 * @brief Enable PLLI2S ready interrupt
4946 * @rmtoll CIR PLLI2SRDYIE LL_RCC_EnableIT_PLLI2SRDY
4947 * @retval None
4948 */
4949 __STATIC_INLINE void LL_RCC_EnableIT_PLLI2SRDY(void)
4950 {
4951 SET_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
4952 }
4953
4954 /**
4955 * @brief Enable PLLSAI ready interrupt
4956 * @rmtoll CIR PLLSAIRDYIE LL_RCC_EnableIT_PLLSAIRDY
4957 * @retval None
4958 */
4959 __STATIC_INLINE void LL_RCC_EnableIT_PLLSAIRDY(void)
4960 {
4961 SET_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
4962 }
4963
4964 /**
4965 * @brief Disable LSI ready interrupt
4966 * @rmtoll CIR LSIRDYIE LL_RCC_DisableIT_LSIRDY
4967 * @retval None
4968 */
4969 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
4970 {
4971 CLEAR_BIT(RCC->CIR, RCC_CIR_LSIRDYIE);
4972 }
4973
4974 /**
4975 * @brief Disable LSE ready interrupt
4976 * @rmtoll CIR LSERDYIE LL_RCC_DisableIT_LSERDY
4977 * @retval None
4978 */
4979 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
4980 {
4981 CLEAR_BIT(RCC->CIR, RCC_CIR_LSERDYIE);
4982 }
4983
4984 /**
4985 * @brief Disable HSI ready interrupt
4986 * @rmtoll CIR HSIRDYIE LL_RCC_DisableIT_HSIRDY
4987 * @retval None
4988 */
4989 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
4990 {
4991 CLEAR_BIT(RCC->CIR, RCC_CIR_HSIRDYIE);
4992 }
4993
4994 /**
4995 * @brief Disable HSE ready interrupt
4996 * @rmtoll CIR HSERDYIE LL_RCC_DisableIT_HSERDY
4997 * @retval None
4998 */
4999 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
5000 {
5001 CLEAR_BIT(RCC->CIR, RCC_CIR_HSERDYIE);
5002 }
5003
5004 /**
5005 * @brief Disable PLL ready interrupt
5006 * @rmtoll CIR PLLRDYIE LL_RCC_DisableIT_PLLRDY
5007 * @retval None
5008 */
5009 __STATIC_INLINE void LL_RCC_DisableIT_PLLRDY(void)
5010 {
5011 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLRDYIE);
5012 }
5013
5014 /**
5015 * @brief Disable PLLI2S ready interrupt
5016 * @rmtoll CIR PLLI2SRDYIE LL_RCC_DisableIT_PLLI2SRDY
5017 * @retval None
5018 */
5019 __STATIC_INLINE void LL_RCC_DisableIT_PLLI2SRDY(void)
5020 {
5021 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE);
5022 }
5023
5024 /**
5025 * @brief Disable PLLSAI ready interrupt
5026 * @rmtoll CIR PLLSAIRDYIE LL_RCC_DisableIT_PLLSAIRDY
5027 * @retval None
5028 */
5029 __STATIC_INLINE void LL_RCC_DisableIT_PLLSAIRDY(void)
5030 {
5031 CLEAR_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE);
5032 }
5033
5034 /**
5035 * @brief Checks if LSI ready interrupt source is enabled or disabled.
5036 * @rmtoll CIR LSIRDYIE LL_RCC_IsEnabledIT_LSIRDY
5037 * @retval State of bit (1 or 0).
5038 */
5039 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSIRDY(void)
5040 {
5041 return (READ_BIT(RCC->CIR, RCC_CIR_LSIRDYIE) == (RCC_CIR_LSIRDYIE));
5042 }
5043
5044 /**
5045 * @brief Checks if LSE ready interrupt source is enabled or disabled.
5046 * @rmtoll CIR LSERDYIE LL_RCC_IsEnabledIT_LSERDY
5047 * @retval State of bit (1 or 0).
5048 */
5049 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_LSERDY(void)
5050 {
5051 return (READ_BIT(RCC->CIR, RCC_CIR_LSERDYIE) == (RCC_CIR_LSERDYIE));
5052 }
5053
5054 /**
5055 * @brief Checks if HSI ready interrupt source is enabled or disabled.
5056 * @rmtoll CIR HSIRDYIE LL_RCC_IsEnabledIT_HSIRDY
5057 * @retval State of bit (1 or 0).
5058 */
5059 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSIRDY(void)
5060 {
5061 return (READ_BIT(RCC->CIR, RCC_CIR_HSIRDYIE) == (RCC_CIR_HSIRDYIE));
5062 }
5063
5064 /**
5065 * @brief Checks if HSE ready interrupt source is enabled or disabled.
5066 * @rmtoll CIR HSERDYIE LL_RCC_IsEnabledIT_HSERDY
5067 * @retval State of bit (1 or 0).
5068 */
5069 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_HSERDY(void)
5070 {
5071 return (READ_BIT(RCC->CIR, RCC_CIR_HSERDYIE) == (RCC_CIR_HSERDYIE));
5072 }
5073
5074 /**
5075 * @brief Checks if PLL ready interrupt source is enabled or disabled.
5076 * @rmtoll CIR PLLRDYIE LL_RCC_IsEnabledIT_PLLRDY
5077 * @retval State of bit (1 or 0).
5078 */
5079 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLRDY(void)
5080 {
5081 return (READ_BIT(RCC->CIR, RCC_CIR_PLLRDYIE) == (RCC_CIR_PLLRDYIE));
5082 }
5083
5084 /**
5085 * @brief Checks if PLLI2S ready interrupt source is enabled or disabled.
5086 * @rmtoll CIR PLLI2SRDYIE LL_RCC_IsEnabledIT_PLLI2SRDY
5087 * @retval State of bit (1 or 0).
5088 */
5089 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLI2SRDY(void)
5090 {
5091 return (READ_BIT(RCC->CIR, RCC_CIR_PLLI2SRDYIE) == (RCC_CIR_PLLI2SRDYIE));
5092 }
5093
5094 /**
5095 * @brief Checks if PLLSAI ready interrupt source is enabled or disabled.
5096 * @rmtoll CIR PLLSAIRDYIE LL_RCC_IsEnabledIT_PLLSAIRDY
5097 * @retval State of bit (1 or 0).
5098 */
5099 __STATIC_INLINE uint32_t LL_RCC_IsEnabledIT_PLLSAIRDY(void)
5100 {
5101 return (READ_BIT(RCC->CIR, RCC_CIR_PLLSAIRDYIE) == (RCC_CIR_PLLSAIRDYIE));
5102 }
5103
5104 /**
5105 * @}
5106 */
5107
5108 #if defined(USE_FULL_LL_DRIVER)
5109 /** @defgroup RCC_LL_EF_Init De-initialization function
5110 * @{
5111 */
5112 ErrorStatus LL_RCC_DeInit(void);
5113 /**
5114 * @}
5115 */
5116
5117 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
5118 * @{
5119 */
5120 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
5121 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
5122 uint32_t LL_RCC_GetUARTClockFreq(uint32_t UARTxSource);
5123 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
5124 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
5125 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
5126 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
5127 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
5128 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
5129 #if defined(DFSDM1_Channel0)
5130 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
5131 uint32_t LL_RCC_GetDFSDMAudioClockFreq(uint32_t DFSDMxSource);
5132 #endif /* DFSDM1_Channel0 */
5133 uint32_t LL_RCC_GetI2SClockFreq(uint32_t I2SxSource);
5134 #if defined(CEC)
5135 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
5136 #endif /* CEC */
5137 #if defined(LTDC)
5138 uint32_t LL_RCC_GetLTDCClockFreq(uint32_t LTDCxSource);
5139 #endif /* LTDC */
5140 #if defined(SPDIFRX)
5141 uint32_t LL_RCC_GetSPDIFRXClockFreq(uint32_t SPDIFRXxSource);
5142 #endif /* SPDIFRX */
5143 #if defined(DSI)
5144 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
5145 #endif /* DSI */
5146 /**
5147 * @}
5148 */
5149 #endif /* USE_FULL_LL_DRIVER */
5150
5151 /**
5152 * @}
5153 */
5154
5155 /**
5156 * @}
5157 */
5158
5159 #endif /* defined(RCC) */
5160
5161 /**
5162 * @}
5163 */
5164
5165 #ifdef __cplusplus
5166 }
5167 #endif
5168
5169 #endif /* __STM32F7xx_LL_RCC_H */
5170
5171 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software