?  search:
summary | log | graphiclog1 | graphiclog2 | commit | commitdiff | tree | refs | edit | fork
blame | history | raw | HEAD
Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_sdmmc.h
blob81fbb0d96806c084ef2cafa7b2bb3ee318b7d028
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_sdmmc.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of SDMMC HAL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_SDMMC_H
40 #define __STM32F7xx_LL_SDMMC_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx_hal_def.h"
48
49 /** @addtogroup STM32F7xx_Driver
50 * @{
51 */
52
53 /** @addtogroup SDMMC_LL
54 * @{
55 */
56
57 /* Exported types ------------------------------------------------------------*/
58 /** @defgroup SDMMC_LL_Exported_Types SDMMC_LL Exported Types
59 * @{
60 */
61
62 /**
63 * @brief SDMMC Configuration Structure definition
64 */
65 typedef struct
66 {
67 uint32_t ClockEdge; /*!< Specifies the clock transition on which the bit capture is made.
68 This parameter can be a value of @ref SDMMC_LL_Clock_Edge */
69
70 uint32_t ClockBypass; /*!< Specifies whether the SDMMC Clock divider bypass is
71 enabled or disabled.
72 This parameter can be a value of @ref SDMMC_LL_Clock_Bypass */
73
74 uint32_t ClockPowerSave; /*!< Specifies whether SDMMC Clock output is enabled or
75 disabled when the bus is idle.
76 This parameter can be a value of @ref SDMMC_LL_Clock_Power_Save */
77
78 uint32_t BusWide; /*!< Specifies the SDMMC bus width.
79 This parameter can be a value of @ref SDMMC_LL_Bus_Wide */
80
81 uint32_t HardwareFlowControl; /*!< Specifies whether the SDMMC hardware flow control is enabled or disabled.
82 This parameter can be a value of @ref SDMMC_LL_Hardware_Flow_Control */
83
84 uint32_t ClockDiv; /*!< Specifies the clock frequency of the SDMMC controller.
85 This parameter can be a value between Min_Data = 0 and Max_Data = 255 */
86
87 }SDMMC_InitTypeDef;
88
89
90 /**
91 * @brief SDMMC Command Control structure
92 */
93 typedef struct
94 {
95 uint32_t Argument; /*!< Specifies the SDMMC command argument which is sent
96 to a card as part of a command message. If a command
97 contains an argument, it must be loaded into this register
98 before writing the command to the command register. */
99
100 uint32_t CmdIndex; /*!< Specifies the SDMMC command index. It must be Min_Data = 0 and
101 Max_Data = 64 */
102
103 uint32_t Response; /*!< Specifies the SDMMC response type.
104 This parameter can be a value of @ref SDMMC_LL_Response_Type */
105
106 uint32_t WaitForInterrupt; /*!< Specifies whether SDMMC wait for interrupt request is
107 enabled or disabled.
108 This parameter can be a value of @ref SDMMC_LL_Wait_Interrupt_State */
109
110 uint32_t CPSM; /*!< Specifies whether SDMMC Command path state machine (CPSM)
111 is enabled or disabled.
112 This parameter can be a value of @ref SDMMC_LL_CPSM_State */
113 }SDMMC_CmdInitTypeDef;
114
115
116 /**
117 * @brief SDMMC Data Control structure
118 */
119 typedef struct
120 {
121 uint32_t DataTimeOut; /*!< Specifies the data timeout period in card bus clock periods. */
122
123 uint32_t DataLength; /*!< Specifies the number of data bytes to be transferred. */
124
125 uint32_t DataBlockSize; /*!< Specifies the data block size for block transfer.
126 This parameter can be a value of @ref SDMMC_LL_Data_Block_Size */
127
128 uint32_t TransferDir; /*!< Specifies the data transfer direction, whether the transfer
129 is a read or write.
130 This parameter can be a value of @ref SDMMC_LL_Transfer_Direction */
131
132 uint32_t TransferMode; /*!< Specifies whether data transfer is in stream or block mode.
133 This parameter can be a value of @ref SDMMC_LL_Transfer_Type */
134
135 uint32_t DPSM; /*!< Specifies whether SDMMC Data path state machine (DPSM)
136 is enabled or disabled.
137 This parameter can be a value of @ref SDMMC_LL_DPSM_State */
138 }SDMMC_DataInitTypeDef;
139
140 /**
141 * @}
142 */
143
144 /* Exported constants --------------------------------------------------------*/
145 /** @defgroup SDMMC_LL_Exported_Constants SDMMC_LL Exported Constants
146 * @{
147 */
148 #define SDMMC_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
149 #define SDMMC_ERROR_CMD_CRC_FAIL ((uint32_t)0x00000001U) /*!< Command response received (but CRC check failed) */
150 #define SDMMC_ERROR_DATA_CRC_FAIL ((uint32_t)0x00000002U) /*!< Data block sent/received (CRC check failed) */
151 #define SDMMC_ERROR_CMD_RSP_TIMEOUT ((uint32_t)0x00000004U) /*!< Command response timeout */
152 #define SDMMC_ERROR_DATA_TIMEOUT ((uint32_t)0x00000008U) /*!< Data timeout */
153 #define SDMMC_ERROR_TX_UNDERRUN ((uint32_t)0x00000010U) /*!< Transmit FIFO underrun */
154 #define SDMMC_ERROR_RX_OVERRUN ((uint32_t)0x00000020U) /*!< Receive FIFO overrun */
155 #define SDMMC_ERROR_ADDR_MISALIGNED ((uint32_t)0x00000040U) /*!< Misaligned address */
156 #define SDMMC_ERROR_BLOCK_LEN_ERR ((uint32_t)0x00000080U) /*!< Transferred block length is not allowed for the card or the
157 number of transferred bytes does not match the block length */
158 #define SDMMC_ERROR_ERASE_SEQ_ERR ((uint32_t)0x00000100U) /*!< An error in the sequence of erase command occurs */
159 #define SDMMC_ERROR_BAD_ERASE_PARAM ((uint32_t)0x00000200U) /*!< An invalid selection for erase groups */
160 #define SDMMC_ERROR_WRITE_PROT_VIOLATION ((uint32_t)0x00000400U) /*!< Attempt to program a write protect block */
161 #define SDMMC_ERROR_LOCK_UNLOCK_FAILED ((uint32_t)0x00000800U) /*!< Sequence or password error has been detected in unlock
162 command or if there was an attempt to access a locked card */
163 #define SDMMC_ERROR_COM_CRC_FAILED ((uint32_t)0x00001000U) /*!< CRC check of the previous command failed */
164 #define SDMMC_ERROR_ILLEGAL_CMD ((uint32_t)0x00002000U) /*!< Command is not legal for the card state */
165 #define SDMMC_ERROR_CARD_ECC_FAILED ((uint32_t)0x00004000U) /*!< Card internal ECC was applied but failed to correct the data */
166 #define SDMMC_ERROR_CC_ERR ((uint32_t)0x00008000U) /*!< Internal card controller error */
167 #define SDMMC_ERROR_GENERAL_UNKNOWN_ERR ((uint32_t)0x00010000U) /*!< General or unknown error */
168 #define SDMMC_ERROR_STREAM_READ_UNDERRUN ((uint32_t)0x00020000U) /*!< The card could not sustain data reading in stream rmode */
169 #define SDMMC_ERROR_STREAM_WRITE_OVERRUN ((uint32_t)0x00040000U) /*!< The card could not sustain data programming in stream mode */
170 #define SDMMC_ERROR_CID_CSD_OVERWRITE ((uint32_t)0x00080000U) /*!< CID/CSD overwrite error */
171 #define SDMMC_ERROR_WP_ERASE_SKIP ((uint32_t)0x00100000U) /*!< Only partial address space was erased */
172 #define SDMMC_ERROR_CARD_ECC_DISABLED ((uint32_t)0x00200000U) /*!< Command has been executed without using internal ECC */
173 #define SDMMC_ERROR_ERASE_RESET ((uint32_t)0x00400000U) /*!< Erase sequence was cleared before executing because an out
174 of erase sequence command was received */
175 #define SDMMC_ERROR_AKE_SEQ_ERR ((uint32_t)0x00800000U) /*!< Error in sequence of authentication */
176 #define SDMMC_ERROR_INVALID_VOLTRANGE ((uint32_t)0x01000000U) /*!< Error in case of invalid voltage range */
177 #define SDMMC_ERROR_ADDR_OUT_OF_RANGE ((uint32_t)0x02000000U) /*!< Error when addressed block is out of range */
178 #define SDMMC_ERROR_REQUEST_NOT_APPLICABLE ((uint32_t)0x04000000U) /*!< Error when command request is not applicable */
179 #define SDMMC_ERROR_INVALID_PARAMETER ((uint32_t)0x08000000U) /*!< the used parameter is not valid */
180 #define SDMMC_ERROR_UNSUPPORTED_FEATURE ((uint32_t)0x10000000U) /*!< Error when feature is not insupported */
181 #define SDMMC_ERROR_BUSY ((uint32_t)0x20000000U) /*!< Error when transfer process is busy */
182 #define SDMMC_ERROR_DMA ((uint32_t)0x40000000U) /*!< Error while DMA transfer */
183 #define SDMMC_ERROR_TIMEOUT ((uint32_t)0x80000000U) /*!< Timeout error */
184
185 /**
186 * @brief SDMMC Commands Index
187 */
188 #define SDMMC_CMD_GO_IDLE_STATE ((uint8_t)0U) /*!< Resets the SD memory card. */
189 #define SDMMC_CMD_SEND_OP_COND ((uint8_t)1U) /*!< Sends host capacity support information and activates the card's initialization process. */
190 #define SDMMC_CMD_ALL_SEND_CID ((uint8_t)2U) /*!< Asks any card connected to the host to send the CID numbers on the CMD line. */
191 #define SDMMC_CMD_SET_REL_ADDR ((uint8_t)3U) /*!< Asks the card to publish a new relative address (RCA). */
192 #define SDMMC_CMD_SET_DSR ((uint8_t)4U) /*!< Programs the DSR of all cards. */
193 #define SDMMC_CMD_SDMMC_SEN_OP_COND ((uint8_t)5U) /*!< Sends host capacity support information (HCS) and asks the accessed card to send its
194 operating condition register (OCR) content in the response on the CMD line. */
195 #define SDMMC_CMD_HS_SWITCH ((uint8_t)6U) /*!< Checks switchable function (mode 0) and switch card function (mode 1). */
196 #define SDMMC_CMD_SEL_DESEL_CARD ((uint8_t)7U) /*!< Selects the card by its own relative address and gets deselected by any other address */
197 #define SDMMC_CMD_HS_SEND_EXT_CSD ((uint8_t)8U) /*!< Sends SD Memory Card interface condition, which includes host supply voltage information
198 and asks the card whether card supports voltage. */
199 #define SDMMC_CMD_SEND_CSD ((uint8_t)9U) /*!< Addressed card sends its card specific data (CSD) on the CMD line. */
200 #define SDMMC_CMD_SEND_CID ((uint8_t)10U) /*!< Addressed card sends its card identification (CID) on the CMD line. */
201 #define SDMMC_CMD_READ_DAT_UNTIL_STOP ((uint8_t)11U) /*!< SD card doesn't support it. */
202 #define SDMMC_CMD_STOP_TRANSMISSION ((uint8_t)12U) /*!< Forces the card to stop transmission. */
203 #define SDMMC_CMD_SEND_STATUS ((uint8_t)13U) /*!< Addressed card sends its status register. */
204 #define SDMMC_CMD_HS_BUSTEST_READ ((uint8_t)14U) /*!< Reserved */
205 #define SDMMC_CMD_GO_INACTIVE_STATE ((uint8_t)15U) /*!< Sends an addressed card into the inactive state. */
206 #define SDMMC_CMD_SET_BLOCKLEN ((uint8_t)16U) /*!< Sets the block length (in bytes for SDSC) for all following block commands
207 (read, write, lock). Default block length is fixed to 512 Bytes. Not effective
208 for SDHS and SDXC. */
209 #define SDMMC_CMD_READ_SINGLE_BLOCK ((uint8_t)17U) /*!< Reads single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
210 fixed 512 bytes in case of SDHC and SDXC. */
211 #define SDMMC_CMD_READ_MULT_BLOCK ((uint8_t)18U) /*!< Continuously transfers data blocks from card to host until interrupted by
212 STOP_TRANSMISSION command. */
213 #define SDMMC_CMD_HS_BUSTEST_WRITE ((uint8_t)19U) /*!< 64 bytes tuning pattern is sent for SDR50 and SDR104. */
214 #define SDMMC_CMD_WRITE_DAT_UNTIL_STOP ((uint8_t)20U) /*!< Speed class control command. */
215 #define SDMMC_CMD_SET_BLOCK_COUNT ((uint8_t)23U) /*!< Specify block count for CMD18 and CMD25. */
216 #define SDMMC_CMD_WRITE_SINGLE_BLOCK ((uint8_t)24U) /*!< Writes single block of size selected by SET_BLOCKLEN in case of SDSC, and a block of
217 fixed 512 bytes in case of SDHC and SDXC. */
218 #define SDMMC_CMD_WRITE_MULT_BLOCK ((uint8_t)25U) /*!< Continuously writes blocks of data until a STOP_TRANSMISSION follows. */
219 #define SDMMC_CMD_PROG_CID ((uint8_t)26U) /*!< Reserved for manufacturers. */
220 #define SDMMC_CMD_PROG_CSD ((uint8_t)27U) /*!< Programming of the programmable bits of the CSD. */
221 #define SDMMC_CMD_SET_WRITE_PROT ((uint8_t)28U) /*!< Sets the write protection bit of the addressed group. */
222 #define SDMMC_CMD_CLR_WRITE_PROT ((uint8_t)29U) /*!< Clears the write protection bit of the addressed group. */
223 #define SDMMC_CMD_SEND_WRITE_PROT ((uint8_t)30U) /*!< Asks the card to send the status of the write protection bits. */
224 #define SDMMC_CMD_SD_ERASE_GRP_START ((uint8_t)32U) /*!< Sets the address of the first write block to be erased. (For SD card only). */
225 #define SDMMC_CMD_SD_ERASE_GRP_END ((uint8_t)33U) /*!< Sets the address of the last write block of the continuous range to be erased. */
226 #define SDMMC_CMD_ERASE_GRP_START ((uint8_t)35U) /*!< Sets the address of the first write block to be erased. Reserved for each command
227 system set by switch function command (CMD6). */
228 #define SDMMC_CMD_ERASE_GRP_END ((uint8_t)36U) /*!< Sets the address of the last write block of the continuous range to be erased.
229 Reserved for each command system set by switch function command (CMD6). */
230 #define SDMMC_CMD_ERASE ((uint8_t)38U) /*!< Reserved for SD security applications. */
231 #define SDMMC_CMD_FAST_IO ((uint8_t)39U) /*!< SD card doesn't support it (Reserved). */
232 #define SDMMC_CMD_GO_IRQ_STATE ((uint8_t)40U) /*!< SD card doesn't support it (Reserved). */
233 #define SDMMC_CMD_LOCK_UNLOCK ((uint8_t)42U) /*!< Sets/resets the password or lock/unlock the card. The size of the data block is set by
234 the SET_BLOCK_LEN command. */
235 #define SDMMC_CMD_APP_CMD ((uint8_t)55U) /*!< Indicates to the card that the next command is an application specific command rather
236 than a standard command. */
237 #define SDMMC_CMD_GEN_CMD ((uint8_t)56U) /*!< Used either to transfer a data block to the card or to get a data block from the card
238 for general purpose/application specific commands. */
239 #define SDMMC_CMD_NO_CMD ((uint8_t)64U) /*!< No command */
240
241 /**
242 * @brief Following commands are SD Card Specific commands.
243 * SDMMC_APP_CMD should be sent before sending these commands.
244 */
245 #define SDMMC_CMD_APP_SD_SET_BUSWIDTH ((uint8_t)6U) /*!< (ACMD6) Defines the data bus width to be used for data transfer. The allowed data bus
246 widths are given in SCR register. */
247 #define SDMMC_CMD_SD_APP_STATUS ((uint8_t)13U) /*!< (ACMD13) Sends the SD status. */
248 #define SDMMC_CMD_SD_APP_SEND_NUM_WRITE_BLOCKS ((uint8_t)22U) /*!< (ACMD22) Sends the number of the written (without errors) write blocks. Responds with
249 32bit+CRC data block. */
250 #define SDMMC_CMD_SD_APP_OP_COND ((uint8_t)41U) /*!< (ACMD41) Sends host capacity support information (HCS) and asks the accessed card to
251 send its operating condition register (OCR) content in the response on the CMD line. */
252 #define SDMMC_CMD_SD_APP_SET_CLR_CARD_DETECT ((uint8_t)42U) /*!< (ACMD42) Connect/Disconnect the 50 KOhm pull-up resistor on CD/DAT3 (pin 1) of the card */
253 #define SDMMC_CMD_SD_APP_SEND_SCR ((uint8_t)51U) /*!< Reads the SD Configuration Register (SCR). */
254 #define SDMMC_CMD_SDMMC_RW_DIRECT ((uint8_t)52U) /*!< For SD I/O card only, reserved for security specification. */
255 #define SDMMC_CMD_SDMMC_RW_EXTENDED ((uint8_t)53U) /*!< For SD I/O card only, reserved for security specification. */
256
257 /**
258 * @brief Following commands are SD Card Specific security commands.
259 * SDMMC_CMD_APP_CMD should be sent before sending these commands.
260 */
261 #define SDMMC_CMD_SD_APP_GET_MKB ((uint8_t)43U)
262 #define SDMMC_CMD_SD_APP_GET_MID ((uint8_t)44U)
263 #define SDMMC_CMD_SD_APP_SET_CER_RN1 ((uint8_t)45U)
264 #define SDMMC_CMD_SD_APP_GET_CER_RN2 ((uint8_t)46U)
265 #define SDMMC_CMD_SD_APP_SET_CER_RES2 ((uint8_t)47U)
266 #define SDMMC_CMD_SD_APP_GET_CER_RES1 ((uint8_t)48U)
267 #define SDMMC_CMD_SD_APP_SECURE_READ_MULTIPLE_BLOCK ((uint8_t)18U)
268 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MULTIPLE_BLOCK ((uint8_t)25U)
269 #define SDMMC_CMD_SD_APP_SECURE_ERASE ((uint8_t)38U)
270 #define SDMMC_CMD_SD_APP_CHANGE_SECURE_AREA ((uint8_t)49U)
271 #define SDMMC_CMD_SD_APP_SECURE_WRITE_MKB ((uint8_t)48U)
272
273 /**
274 * @brief Masks for errors Card Status R1 (OCR Register)
275 */
276 #define SDMMC_OCR_ADDR_OUT_OF_RANGE ((uint32_t)0x80000000U)
277 #define SDMMC_OCR_ADDR_MISALIGNED ((uint32_t)0x40000000U)
278 #define SDMMC_OCR_BLOCK_LEN_ERR ((uint32_t)0x20000000U)
279 #define SDMMC_OCR_ERASE_SEQ_ERR ((uint32_t)0x10000000U)
280 #define SDMMC_OCR_BAD_ERASE_PARAM ((uint32_t)0x08000000U)
281 #define SDMMC_OCR_WRITE_PROT_VIOLATION ((uint32_t)0x04000000U)
282 #define SDMMC_OCR_LOCK_UNLOCK_FAILED ((uint32_t)0x01000000U)
283 #define SDMMC_OCR_COM_CRC_FAILED ((uint32_t)0x00800000U)
284 #define SDMMC_OCR_ILLEGAL_CMD ((uint32_t)0x00400000U)
285 #define SDMMC_OCR_CARD_ECC_FAILED ((uint32_t)0x00200000U)
286 #define SDMMC_OCR_CC_ERROR ((uint32_t)0x00100000U)
287 #define SDMMC_OCR_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00080000U)
288 #define SDMMC_OCR_STREAM_READ_UNDERRUN ((uint32_t)0x00040000U)
289 #define SDMMC_OCR_STREAM_WRITE_OVERRUN ((uint32_t)0x00020000U)
290 #define SDMMC_OCR_CID_CSD_OVERWRITE ((uint32_t)0x00010000U)
291 #define SDMMC_OCR_WP_ERASE_SKIP ((uint32_t)0x00008000U)
292 #define SDMMC_OCR_CARD_ECC_DISABLED ((uint32_t)0x00004000U)
293 #define SDMMC_OCR_ERASE_RESET ((uint32_t)0x00002000U)
294 #define SDMMC_OCR_AKE_SEQ_ERROR ((uint32_t)0x00000008U)
295 #define SDMMC_OCR_ERRORBITS ((uint32_t)0xFDFFE008U)
296
297 /**
298 * @brief Masks for R6 Response
299 */
300 #define SDMMC_R6_GENERAL_UNKNOWN_ERROR ((uint32_t)0x00002000U)
301 #define SDMMC_R6_ILLEGAL_CMD ((uint32_t)0x00004000U)
302 #define SDMMC_R6_COM_CRC_FAILED ((uint32_t)0x00008000U)
303
304 #define SDMMC_VOLTAGE_WINDOW_SD ((uint32_t)0x80100000U)
305 #define SDMMC_HIGH_CAPACITY ((uint32_t)0x40000000U)
306 #define SDMMC_STD_CAPACITY ((uint32_t)0x00000000U)
307 #define SDMMC_CHECK_PATTERN ((uint32_t)0x000001AAU)
308
309 #define SDMMC_MAX_VOLT_TRIAL ((uint32_t)0x0000FFFFU)
310
311 #define SDMMC_MAX_TRIAL ((uint32_t)0x0000FFFFU)
312
313 #define SDMMC_ALLZERO ((uint32_t)0x00000000U)
314
315 #define SDMMC_WIDE_BUS_SUPPORT ((uint32_t)0x00040000U)
316 #define SDMMC_SINGLE_BUS_SUPPORT ((uint32_t)0x00010000U)
317 #define SDMMC_CARD_LOCKED ((uint32_t)0x02000000U)
318
319 #define SDMMC_DATATIMEOUT ((uint32_t)0xFFFFFFFFU)
320
321 #define SDMMC_0TO7BITS ((uint32_t)0x000000FFU)
322 #define SDMMC_8TO15BITS ((uint32_t)0x0000FF00U)
323 #define SDMMC_16TO23BITS ((uint32_t)0x00FF0000U)
324 #define SDMMC_24TO31BITS ((uint32_t)0xFF000000U)
325 #define SDMMC_MAX_DATA_LENGTH ((uint32_t)0x01FFFFFFU)
326
327 #define SDMMC_HALFFIFO ((uint32_t)0x00000008U)
328 #define SDMMC_HALFFIFOBYTES ((uint32_t)0x00000020U)
329
330 /**
331 * @brief Command Class supported
332 */
333 #define SDMMC_CCCC_ERASE ((uint32_t)0x00000020U)
334
335 #define SDMMC_CMDTIMEOUT ((uint32_t)5000U) /* Command send and response timeout */
336 #define SDMMC_MAXERASETIMEOUT ((uint32_t)63000U) /* Max erase Timeout 63 s */
337
338
339 /** @defgroup SDMMC_LL_Clock_Edge Clock Edge
340 * @{
341 */
342 #define SDMMC_CLOCK_EDGE_RISING ((uint32_t)0x00000000U)
343 #define SDMMC_CLOCK_EDGE_FALLING SDMMC_CLKCR_NEGEDGE
344
345 #define IS_SDMMC_CLOCK_EDGE(EDGE) (((EDGE) == SDMMC_CLOCK_EDGE_RISING) || \
346 ((EDGE) == SDMMC_CLOCK_EDGE_FALLING))
347 /**
348 * @}
349 */
350
351 /** @defgroup SDMMC_LL_Clock_Bypass Clock Bypass
352 * @{
353 */
354 #define SDMMC_CLOCK_BYPASS_DISABLE ((uint32_t)0x00000000U)
355 #define SDMMC_CLOCK_BYPASS_ENABLE SDMMC_CLKCR_BYPASS
356
357 #define IS_SDMMC_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDMMC_CLOCK_BYPASS_DISABLE) || \
358 ((BYPASS) == SDMMC_CLOCK_BYPASS_ENABLE))
359 /**
360 * @}
361 */
362
363 /** @defgroup SDMMC_LL_Clock_Power_Save Clock Power Saving
364 * @{
365 */
366 #define SDMMC_CLOCK_POWER_SAVE_DISABLE ((uint32_t)0x00000000U)
367 #define SDMMC_CLOCK_POWER_SAVE_ENABLE SDMMC_CLKCR_PWRSAV
368
369 #define IS_SDMMC_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDMMC_CLOCK_POWER_SAVE_DISABLE) || \
370 ((SAVE) == SDMMC_CLOCK_POWER_SAVE_ENABLE))
371 /**
372 * @}
373 */
374
375 /** @defgroup SDMMC_LL_Bus_Wide Bus Width
376 * @{
377 */
378 #define SDMMC_BUS_WIDE_1B ((uint32_t)0x00000000U)
379 #define SDMMC_BUS_WIDE_4B SDMMC_CLKCR_WIDBUS_0
380 #define SDMMC_BUS_WIDE_8B SDMMC_CLKCR_WIDBUS_1
381
382 #define IS_SDMMC_BUS_WIDE(WIDE) (((WIDE) == SDMMC_BUS_WIDE_1B) || \
383 ((WIDE) == SDMMC_BUS_WIDE_4B) || \
384 ((WIDE) == SDMMC_BUS_WIDE_8B))
385 /**
386 * @}
387 */
388
389 /** @defgroup SDMMC_LL_Hardware_Flow_Control Hardware Flow Control
390 * @{
391 */
392 #define SDMMC_HARDWARE_FLOW_CONTROL_DISABLE ((uint32_t)0x00000000U)
393 #define SDMMC_HARDWARE_FLOW_CONTROL_ENABLE SDMMC_CLKCR_HWFC_EN
394
395 #define IS_SDMMC_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_DISABLE) || \
396 ((CONTROL) == SDMMC_HARDWARE_FLOW_CONTROL_ENABLE))
397 /**
398 * @}
399 */
400
401 /** @defgroup SDMMC_LL_Clock_Division Clock Division
402 * @{
403 */
404 #define IS_SDMMC_CLKDIV(DIV) ((DIV) <= 0xFF)
405 /**
406 * @}
407 */
408
409 /** @defgroup SDMMC_LL_Command_Index Command Index
410 * @{
411 */
412 #define IS_SDMMC_CMD_INDEX(INDEX) ((INDEX) < 0x40)
413 /**
414 * @}
415 */
416
417 /** @defgroup SDMMC_LL_Response_Type Response Type
418 * @{
419 */
420 #define SDMMC_RESPONSE_NO ((uint32_t)0x00000000U)
421 #define SDMMC_RESPONSE_SHORT SDMMC_CMD_WAITRESP_0
422 #define SDMMC_RESPONSE_LONG SDMMC_CMD_WAITRESP
423
424 #define IS_SDMMC_RESPONSE(RESPONSE) (((RESPONSE) == SDMMC_RESPONSE_NO) || \
425 ((RESPONSE) == SDMMC_RESPONSE_SHORT) || \
426 ((RESPONSE) == SDMMC_RESPONSE_LONG))
427 /**
428 * @}
429 */
430
431 /** @defgroup SDMMC_LL_Wait_Interrupt_State Wait Interrupt
432 * @{
433 */
434 #define SDMMC_WAIT_NO ((uint32_t)0x00000000U)
435 #define SDMMC_WAIT_IT SDMMC_CMD_WAITINT
436 #define SDMMC_WAIT_PEND SDMMC_CMD_WAITPEND
437
438 #define IS_SDMMC_WAIT(WAIT) (((WAIT) == SDMMC_WAIT_NO) || \
439 ((WAIT) == SDMMC_WAIT_IT) || \
440 ((WAIT) == SDMMC_WAIT_PEND))
441 /**
442 * @}
443 */
444
445 /** @defgroup SDMMC_LL_CPSM_State CPSM State
446 * @{
447 */
448 #define SDMMC_CPSM_DISABLE ((uint32_t)0x00000000U)
449 #define SDMMC_CPSM_ENABLE SDMMC_CMD_CPSMEN
450
451 #define IS_SDMMC_CPSM(CPSM) (((CPSM) == SDMMC_CPSM_DISABLE) || \
452 ((CPSM) == SDMMC_CPSM_ENABLE))
453 /**
454 * @}
455 */
456
457 /** @defgroup SDMMC_LL_Response_Registers Response Register
458 * @{
459 */
460 #define SDMMC_RESP1 ((uint32_t)0x00000000U)
461 #define SDMMC_RESP2 ((uint32_t)0x00000004U)
462 #define SDMMC_RESP3 ((uint32_t)0x00000008U)
463 #define SDMMC_RESP4 ((uint32_t)0x0000000C)
464
465 #define IS_SDMMC_RESP(RESP) (((RESP) == SDMMC_RESP1) || \
466 ((RESP) == SDMMC_RESP2) || \
467 ((RESP) == SDMMC_RESP3) || \
468 ((RESP) == SDMMC_RESP4))
469 /**
470 * @}
471 */
472
473 /** @defgroup SDMMC_LL_Data_Length Data Lenght
474 * @{
475 */
476 #define IS_SDMMC_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
477 /**
478 * @}
479 */
480
481 /** @defgroup SDMMC_LL_Data_Block_Size Data Block Size
482 * @{
483 */
484 #define SDMMC_DATABLOCK_SIZE_1B ((uint32_t)0x00000000U)
485 #define SDMMC_DATABLOCK_SIZE_2B SDMMC_DCTRL_DBLOCKSIZE_0
486 #define SDMMC_DATABLOCK_SIZE_4B SDMMC_DCTRL_DBLOCKSIZE_1
487 #define SDMMC_DATABLOCK_SIZE_8B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1)
488 #define SDMMC_DATABLOCK_SIZE_16B SDMMC_DCTRL_DBLOCKSIZE_2
489 #define SDMMC_DATABLOCK_SIZE_32B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2)
490 #define SDMMC_DATABLOCK_SIZE_64B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
491 #define SDMMC_DATABLOCK_SIZE_128B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2)
492 #define SDMMC_DATABLOCK_SIZE_256B SDMMC_DCTRL_DBLOCKSIZE_3
493 #define SDMMC_DATABLOCK_SIZE_512B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_3)
494 #define SDMMC_DATABLOCK_SIZE_1024B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
495 #define SDMMC_DATABLOCK_SIZE_2048B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_3)
496 #define SDMMC_DATABLOCK_SIZE_4096B (SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
497 #define SDMMC_DATABLOCK_SIZE_8192B (SDMMC_DCTRL_DBLOCKSIZE_0|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
498 #define SDMMC_DATABLOCK_SIZE_16384B (SDMMC_DCTRL_DBLOCKSIZE_1|SDMMC_DCTRL_DBLOCKSIZE_2|SDMMC_DCTRL_DBLOCKSIZE_3)
499
500 #define IS_SDMMC_BLOCK_SIZE(SIZE) (((SIZE) == SDMMC_DATABLOCK_SIZE_1B) || \
501 ((SIZE) == SDMMC_DATABLOCK_SIZE_2B) || \
502 ((SIZE) == SDMMC_DATABLOCK_SIZE_4B) || \
503 ((SIZE) == SDMMC_DATABLOCK_SIZE_8B) || \
504 ((SIZE) == SDMMC_DATABLOCK_SIZE_16B) || \
505 ((SIZE) == SDMMC_DATABLOCK_SIZE_32B) || \
506 ((SIZE) == SDMMC_DATABLOCK_SIZE_64B) || \
507 ((SIZE) == SDMMC_DATABLOCK_SIZE_128B) || \
508 ((SIZE) == SDMMC_DATABLOCK_SIZE_256B) || \
509 ((SIZE) == SDMMC_DATABLOCK_SIZE_512B) || \
510 ((SIZE) == SDMMC_DATABLOCK_SIZE_1024B) || \
511 ((SIZE) == SDMMC_DATABLOCK_SIZE_2048B) || \
512 ((SIZE) == SDMMC_DATABLOCK_SIZE_4096B) || \
513 ((SIZE) == SDMMC_DATABLOCK_SIZE_8192B) || \
514 ((SIZE) == SDMMC_DATABLOCK_SIZE_16384B))
515 /**
516 * @}
517 */
518
519 /** @defgroup SDMMC_LL_Transfer_Direction Transfer Direction
520 * @{
521 */
522 #define SDMMC_TRANSFER_DIR_TO_CARD ((uint32_t)0x00000000U)
523 #define SDMMC_TRANSFER_DIR_TO_SDMMC SDMMC_DCTRL_DTDIR
524
525 #define IS_SDMMC_TRANSFER_DIR(DIR) (((DIR) == SDMMC_TRANSFER_DIR_TO_CARD) || \
526 ((DIR) == SDMMC_TRANSFER_DIR_TO_SDMMC))
527 /**
528 * @}
529 */
530
531 /** @defgroup SDMMC_LL_Transfer_Type Transfer Type
532 * @{
533 */
534 #define SDMMC_TRANSFER_MODE_BLOCK ((uint32_t)0x00000000U)
535 #define SDMMC_TRANSFER_MODE_STREAM SDMMC_DCTRL_DTMODE
536
537 #define IS_SDMMC_TRANSFER_MODE(MODE) (((MODE) == SDMMC_TRANSFER_MODE_BLOCK) || \
538 ((MODE) == SDMMC_TRANSFER_MODE_STREAM))
539 /**
540 * @}
541 */
542
543 /** @defgroup SDMMC_LL_DPSM_State DPSM State
544 * @{
545 */
546 #define SDMMC_DPSM_DISABLE ((uint32_t)0x00000000U)
547 #define SDMMC_DPSM_ENABLE SDMMC_DCTRL_DTEN
548
549 #define IS_SDMMC_DPSM(DPSM) (((DPSM) == SDMMC_DPSM_DISABLE) ||\
550 ((DPSM) == SDMMC_DPSM_ENABLE))
551 /**
552 * @}
553 */
554
555 /** @defgroup SDMMC_LL_Read_Wait_Mode Read Wait Mode
556 * @{
557 */
558 #define SDMMC_READ_WAIT_MODE_DATA2 ((uint32_t)0x00000000U)
559 #define SDMMC_READ_WAIT_MODE_CLK (SDMMC_DCTRL_RWMOD)
560
561 #define IS_SDMMC_READWAIT_MODE(MODE) (((MODE) == SDMMC_READ_WAIT_MODE_CLK) || \
562 ((MODE) == SDMMC_READ_WAIT_MODE_DATA2))
563 /**
564 * @}
565 */
566
567 /** @defgroup SDMMC_LL_Interrupt_sources Interrupt Sources
568 * @{
569 */
570 #define SDMMC_IT_CCRCFAIL SDMMC_STA_CCRCFAIL
571 #define SDMMC_IT_DCRCFAIL SDMMC_STA_DCRCFAIL
572 #define SDMMC_IT_CTIMEOUT SDMMC_STA_CTIMEOUT
573 #define SDMMC_IT_DTIMEOUT SDMMC_STA_DTIMEOUT
574 #define SDMMC_IT_TXUNDERR SDMMC_STA_TXUNDERR
575 #define SDMMC_IT_RXOVERR SDMMC_STA_RXOVERR
576 #define SDMMC_IT_CMDREND SDMMC_STA_CMDREND
577 #define SDMMC_IT_CMDSENT SDMMC_STA_CMDSENT
578 #define SDMMC_IT_DATAEND SDMMC_STA_DATAEND
579 #define SDMMC_IT_DBCKEND SDMMC_STA_DBCKEND
580 #define SDMMC_IT_CMDACT SDMMC_STA_CMDACT
581 #define SDMMC_IT_TXACT SDMMC_STA_TXACT
582 #define SDMMC_IT_RXACT SDMMC_STA_RXACT
583 #define SDMMC_IT_TXFIFOHE SDMMC_STA_TXFIFOHE
584 #define SDMMC_IT_RXFIFOHF SDMMC_STA_RXFIFOHF
585 #define SDMMC_IT_TXFIFOF SDMMC_STA_TXFIFOF
586 #define SDMMC_IT_RXFIFOF SDMMC_STA_RXFIFOF
587 #define SDMMC_IT_TXFIFOE SDMMC_STA_TXFIFOE
588 #define SDMMC_IT_RXFIFOE SDMMC_STA_RXFIFOE
589 #define SDMMC_IT_TXDAVL SDMMC_STA_TXDAVL
590 #define SDMMC_IT_RXDAVL SDMMC_STA_RXDAVL
591 #define SDMMC_IT_SDIOIT SDMMC_STA_SDIOIT
592 /**
593 * @}
594 */
595
596 /** @defgroup SDMMC_LL_Flags Flags
597 * @{
598 */
599 #define SDMMC_FLAG_CCRCFAIL SDMMC_STA_CCRCFAIL
600 #define SDMMC_FLAG_DCRCFAIL SDMMC_STA_DCRCFAIL
601 #define SDMMC_FLAG_CTIMEOUT SDMMC_STA_CTIMEOUT
602 #define SDMMC_FLAG_DTIMEOUT SDMMC_STA_DTIMEOUT
603 #define SDMMC_FLAG_TXUNDERR SDMMC_STA_TXUNDERR
604 #define SDMMC_FLAG_RXOVERR SDMMC_STA_RXOVERR
605 #define SDMMC_FLAG_CMDREND SDMMC_STA_CMDREND
606 #define SDMMC_FLAG_CMDSENT SDMMC_STA_CMDSENT
607 #define SDMMC_FLAG_DATAEND SDMMC_STA_DATAEND
608 #define SDMMC_FLAG_DBCKEND SDMMC_STA_DBCKEND
609 #define SDMMC_FLAG_CMDACT SDMMC_STA_CMDACT
610 #define SDMMC_FLAG_TXACT SDMMC_STA_TXACT
611 #define SDMMC_FLAG_RXACT SDMMC_STA_RXACT
612 #define SDMMC_FLAG_TXFIFOHE SDMMC_STA_TXFIFOHE
613 #define SDMMC_FLAG_RXFIFOHF SDMMC_STA_RXFIFOHF
614 #define SDMMC_FLAG_TXFIFOF SDMMC_STA_TXFIFOF
615 #define SDMMC_FLAG_RXFIFOF SDMMC_STA_RXFIFOF
616 #define SDMMC_FLAG_TXFIFOE SDMMC_STA_TXFIFOE
617 #define SDMMC_FLAG_RXFIFOE SDMMC_STA_RXFIFOE
618 #define SDMMC_FLAG_TXDAVL SDMMC_STA_TXDAVL
619 #define SDMMC_FLAG_RXDAVL SDMMC_STA_RXDAVL
620 #define SDMMC_FLAG_SDIOIT SDMMC_STA_SDIOIT
621 #define SDMMC_STATIC_FLAGS ((uint32_t)(SDMMC_FLAG_CCRCFAIL | SDMMC_FLAG_DCRCFAIL | SDMMC_FLAG_CTIMEOUT |\
622 SDMMC_FLAG_DTIMEOUT | SDMMC_FLAG_TXUNDERR | SDMMC_FLAG_RXOVERR |\
623 SDMMC_FLAG_CMDREND | SDMMC_FLAG_CMDSENT | SDMMC_FLAG_DATAEND |\
624 SDMMC_FLAG_DBCKEND))
625 /**
626 * @}
627 */
628
629 /**
630 * @}
631 */
632
633 /* Exported macro ------------------------------------------------------------*/
634 /** @defgroup SDMMC_LL_Exported_macros SDMMC_LL Exported Macros
635 * @{
636 */
637
638 /** @defgroup SDMMC_LL_Register Bits And Addresses Definitions
639 * @brief SDMMC_LL registers bit address in the alias region
640 * @{
641 */
642 /* ---------------------- SDMMC registers bit mask --------------------------- */
643 /* --- CLKCR Register ---*/
644 /* CLKCR register clear mask */
645 #define CLKCR_CLEAR_MASK ((uint32_t)(SDMMC_CLKCR_CLKDIV | SDMMC_CLKCR_PWRSAV |\
646 SDMMC_CLKCR_BYPASS | SDMMC_CLKCR_WIDBUS |\
647 SDMMC_CLKCR_NEGEDGE | SDMMC_CLKCR_HWFC_EN))
648
649 /* --- DCTRL Register ---*/
650 /* SDMMC DCTRL Clear Mask */
651 #define DCTRL_CLEAR_MASK ((uint32_t)(SDMMC_DCTRL_DTEN | SDMMC_DCTRL_DTDIR |\
652 SDMMC_DCTRL_DTMODE | SDMMC_DCTRL_DBLOCKSIZE))
653
654 /* --- CMD Register ---*/
655 /* CMD Register clear mask */
656 #define CMD_CLEAR_MASK ((uint32_t)(SDMMC_CMD_CMDINDEX | SDMMC_CMD_WAITRESP |\
657 SDMMC_CMD_WAITINT | SDMMC_CMD_WAITPEND |\
658 SDMMC_CMD_CPSMEN | SDMMC_CMD_SDIOSUSPEND))
659
660 /* SDMMC Initialization Frequency (400KHz max) */
661 #define SDMMC_INIT_CLK_DIV ((uint8_t)0x76)
662
663 /* SDMMC Data Transfer Frequency (25MHz max) */
664 #define SDMMC_TRANSFER_CLK_DIV ((uint8_t)0x0)
665
666 /**
667 * @}
668 */
669
670 /** @defgroup SDMMC_LL_Interrupt_Clock Interrupt And Clock Configuration
671 * @brief macros to handle interrupts and specific clock configurations
672 * @{
673 */
674
675 /**
676 * @brief Enable the SDMMC device.
677 * @param __INSTANCE__: SDMMC Instance
678 * @retval None
679 */
680 #define __SDMMC_ENABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR |= SDMMC_CLKCR_CLKEN)
681
682 /**
683 * @brief Disable the SDMMC device.
684 * @param __INSTANCE__: SDMMC Instance
685 * @retval None
686 */
687 #define __SDMMC_DISABLE(__INSTANCE__) ((__INSTANCE__)->CLKCR &= ~SDMMC_CLKCR_CLKEN)
688
689 /**
690 * @brief Enable the SDMMC DMA transfer.
691 * @param __INSTANCE__: SDMMC Instance
692 * @retval None
693 */
694 #define __SDMMC_DMA_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_DMAEN)
695 /**
696 * @brief Disable the SDMMC DMA transfer.
697 * @param __INSTANCE__: SDMMC Instance
698 * @retval None
699 */
700 #define __SDMMC_DMA_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_DMAEN)
701
702 /**
703 * @brief Enable the SDMMC device interrupt.
704 * @param __INSTANCE__ : Pointer to SDMMC register base
705 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be enabled.
706 * This parameter can be one or a combination of the following values:
707 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
708 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
709 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
710 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
711 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
712 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
713 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
714 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
715 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
716 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
717 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
718 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
719 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
720 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
721 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
722 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
723 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
724 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
725 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
726 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
727 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
728 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
729 * @retval None
730 */
731 #define __SDMMC_ENABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK |= (__INTERRUPT__))
732
733 /**
734 * @brief Disable the SDMMC device interrupt.
735 * @param __INSTANCE__ : Pointer to SDMMC register base
736 * @param __INTERRUPT__ : specifies the SDMMC interrupt sources to be disabled.
737 * This parameter can be one or a combination of the following values:
738 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
739 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
740 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
741 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
742 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
743 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
744 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
745 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
746 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
747 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
748 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
749 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
750 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
751 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
752 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
753 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
754 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
755 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
756 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
757 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
758 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
759 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
760 * @retval None
761 */
762 #define __SDMMC_DISABLE_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->MASK &= ~(__INTERRUPT__))
763
764 /**
765 * @brief Checks whether the specified SDMMC flag is set or not.
766 * @param __INSTANCE__ : Pointer to SDMMC register base
767 * @param __FLAG__: specifies the flag to check.
768 * This parameter can be one of the following values:
769 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
770 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
771 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
772 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
773 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
774 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
775 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
776 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
777 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
778 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
779 * @arg SDMMC_FLAG_CMDACT: Command transfer in progress
780 * @arg SDMMC_FLAG_TXACT: Data transmit in progress
781 * @arg SDMMC_FLAG_RXACT: Data receive in progress
782 * @arg SDMMC_FLAG_TXFIFOHE: Transmit FIFO Half Empty
783 * @arg SDMMC_FLAG_RXFIFOHF: Receive FIFO Half Full
784 * @arg SDMMC_FLAG_TXFIFOF: Transmit FIFO full
785 * @arg SDMMC_FLAG_RXFIFOF: Receive FIFO full
786 * @arg SDMMC_FLAG_TXFIFOE: Transmit FIFO empty
787 * @arg SDMMC_FLAG_RXFIFOE: Receive FIFO empty
788 * @arg SDMMC_FLAG_TXDAVL: Data available in transmit FIFO
789 * @arg SDMMC_FLAG_RXDAVL: Data available in receive FIFO
790 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
791 * @retval The new state of SDMMC_FLAG (SET or RESET).
792 */
793 #define __SDMMC_GET_FLAG(__INSTANCE__, __FLAG__) (((__INSTANCE__)->STA &(__FLAG__)) != RESET)
794
795
796 /**
797 * @brief Clears the SDMMC pending flags.
798 * @param __INSTANCE__ : Pointer to SDMMC register base
799 * @param __FLAG__: specifies the flag to clear.
800 * This parameter can be one or a combination of the following values:
801 * @arg SDMMC_FLAG_CCRCFAIL: Command response received (CRC check failed)
802 * @arg SDMMC_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
803 * @arg SDMMC_FLAG_CTIMEOUT: Command response timeout
804 * @arg SDMMC_FLAG_DTIMEOUT: Data timeout
805 * @arg SDMMC_FLAG_TXUNDERR: Transmit FIFO underrun error
806 * @arg SDMMC_FLAG_RXOVERR: Received FIFO overrun error
807 * @arg SDMMC_FLAG_CMDREND: Command response received (CRC check passed)
808 * @arg SDMMC_FLAG_CMDSENT: Command sent (no response required)
809 * @arg SDMMC_FLAG_DATAEND: Data end (data counter, SDIDCOUNT, is zero)
810 * @arg SDMMC_FLAG_DBCKEND: Data block sent/received (CRC check passed)
811 * @arg SDMMC_FLAG_SDMMCIT: SD I/O interrupt received
812 * @retval None
813 */
814 #define __SDMMC_CLEAR_FLAG(__INSTANCE__, __FLAG__) ((__INSTANCE__)->ICR = (__FLAG__))
815
816 /**
817 * @brief Checks whether the specified SDMMC interrupt has occurred or not.
818 * @param __INSTANCE__ : Pointer to SDMMC register base
819 * @param __INTERRUPT__: specifies the SDMMC interrupt source to check.
820 * This parameter can be one of the following values:
821 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
822 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
823 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
824 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
825 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
826 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
827 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
828 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
829 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDIDCOUNT, is zero) interrupt
830 * @arg SDMMC_IT_DBCKEND: Data block sent/received (CRC check passed) interrupt
831 * @arg SDMMC_IT_CMDACT: Command transfer in progress interrupt
832 * @arg SDMMC_IT_TXACT: Data transmit in progress interrupt
833 * @arg SDMMC_IT_RXACT: Data receive in progress interrupt
834 * @arg SDMMC_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
835 * @arg SDMMC_IT_RXFIFOHF: Receive FIFO Half Full interrupt
836 * @arg SDMMC_IT_TXFIFOF: Transmit FIFO full interrupt
837 * @arg SDMMC_IT_RXFIFOF: Receive FIFO full interrupt
838 * @arg SDMMC_IT_TXFIFOE: Transmit FIFO empty interrupt
839 * @arg SDMMC_IT_RXFIFOE: Receive FIFO empty interrupt
840 * @arg SDMMC_IT_TXDAVL: Data available in transmit FIFO interrupt
841 * @arg SDMMC_IT_RXDAVL: Data available in receive FIFO interrupt
842 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
843 * @retval The new state of SDMMC_IT (SET or RESET).
844 */
845 #define __SDMMC_GET_IT (__INSTANCE__, __INTERRUPT__) (((__INSTANCE__)->STA &(__INTERRUPT__)) == (__INTERRUPT__))
846
847 /**
848 * @brief Clears the SDMMC's interrupt pending bits.
849 * @param __INSTANCE__ : Pointer to SDMMC register base
850 * @param __INTERRUPT__: specifies the interrupt pending bit to clear.
851 * This parameter can be one or a combination of the following values:
852 * @arg SDMMC_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
853 * @arg SDMMC_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
854 * @arg SDMMC_IT_CTIMEOUT: Command response timeout interrupt
855 * @arg SDMMC_IT_DTIMEOUT: Data timeout interrupt
856 * @arg SDMMC_IT_TXUNDERR: Transmit FIFO underrun error interrupt
857 * @arg SDMMC_IT_RXOVERR: Received FIFO overrun error interrupt
858 * @arg SDMMC_IT_CMDREND: Command response received (CRC check passed) interrupt
859 * @arg SDMMC_IT_CMDSENT: Command sent (no response required) interrupt
860 * @arg SDMMC_IT_DATAEND: Data end (data counter, SDMMC_DCOUNT, is zero) interrupt
861 * @arg SDMMC_IT_SDIOIT: SD I/O interrupt received interrupt
862 * @retval None
863 */
864 #define __SDMMC_CLEAR_IT(__INSTANCE__, __INTERRUPT__) ((__INSTANCE__)->ICR = (__INTERRUPT__))
865
866 /**
867 * @brief Enable Start the SD I/O Read Wait operation.
868 * @param __INSTANCE__ : Pointer to SDMMC register base
869 * @retval None
870 */
871 #define __SDMMC_START_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTART)
872
873 /**
874 * @brief Disable Start the SD I/O Read Wait operations.
875 * @param __INSTANCE__ : Pointer to SDMMC register base
876 * @retval None
877 */
878 #define __SDMMC_START_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTART)
879
880 /**
881 * @brief Enable Start the SD I/O Read Wait operation.
882 * @param __INSTANCE__ : Pointer to SDMMC register base
883 * @retval None
884 */
885 #define __SDMMC_STOP_READWAIT_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_RWSTOP)
886
887 /**
888 * @brief Disable Stop the SD I/O Read Wait operations.
889 * @param __INSTANCE__ : Pointer to SDMMC register base
890 * @retval None
891 */
892 #define __SDMMC_STOP_READWAIT_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_RWSTOP)
893
894 /**
895 * @brief Enable the SD I/O Mode Operation.
896 * @param __INSTANCE__ : Pointer to SDMMC register base
897 * @retval None
898 */
899 #define __SDMMC_OPERATION_ENABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL |= SDMMC_DCTRL_SDIOEN)
900
901 /**
902 * @brief Disable the SD I/O Mode Operation.
903 * @param __INSTANCE__ : Pointer to SDMMC register base
904 * @retval None
905 */
906 #define __SDMMC_OPERATION_DISABLE(__INSTANCE__) ((__INSTANCE__)->DCTRL &= ~SDMMC_DCTRL_SDIOEN)
907
908 /**
909 * @brief Enable the SD I/O Suspend command sending.
910 * @param __INSTANCE__ : Pointer to SDMMC register base
911 * @retval None
912 */
913 #define __SDMMC_SUSPEND_CMD_ENABLE(__INSTANCE__) ((__INSTANCE__)->CMD |= SDMMC_CMD_SDIOSUSPEND)
914
915 /**
916 * @brief Disable the SD I/O Suspend command sending.
917 * @param __INSTANCE__ : Pointer to SDMMC register base
918 * @retval None
919 */
920 #define __SDMMC_SUSPEND_CMD_DISABLE(__INSTANCE__) ((__INSTANCE__)->CMD &= ~SDMMC_CMD_SDIOSUSPEND)
921
922 /**
923 * @}
924 */
925
926 /**
927 * @}
928 */
929
930 /* Exported functions --------------------------------------------------------*/
931 /** @addtogroup SDMMC_LL_Exported_Functions
932 * @{
933 */
934
935 /* Initialization/de-initialization functions **********************************/
936 /** @addtogroup HAL_SDMMC_LL_Group1
937 * @{
938 */
939 HAL_StatusTypeDef SDMMC_Init(SDMMC_TypeDef *SDMMCx, SDMMC_InitTypeDef Init);
940 /**
941 * @}
942 */
943
944 /* I/O operation functions *****************************************************/
945 /** @addtogroup HAL_SDMMC_LL_Group2
946 * @{
947 */
948 uint32_t SDMMC_ReadFIFO(SDMMC_TypeDef *SDMMCx);
949 HAL_StatusTypeDef SDMMC_WriteFIFO(SDMMC_TypeDef *SDMMCx, uint32_t *pWriteData);
950 /**
951 * @}
952 */
953
954 /* Peripheral Control functions ************************************************/
955 /** @addtogroup HAL_SDMMC_LL_Group3
956 * @{
957 */
958 HAL_StatusTypeDef SDMMC_PowerState_ON(SDMMC_TypeDef *SDMMCx);
959 HAL_StatusTypeDef SDMMC_PowerState_OFF(SDMMC_TypeDef *SDMMCx);
960 uint32_t SDMMC_GetPowerState(SDMMC_TypeDef *SDMMCx);
961
962 /* Command path state machine (CPSM) management functions */
963 HAL_StatusTypeDef SDMMC_SendCommand(SDMMC_TypeDef *SDMMCx, SDMMC_CmdInitTypeDef *Command);
964 uint8_t SDMMC_GetCommandResponse(SDMMC_TypeDef *SDMMCx);
965 uint32_t SDMMC_GetResponse(SDMMC_TypeDef *SDMMCx, uint32_t Response);
966
967 /* Data path state machine (DPSM) management functions */
968 HAL_StatusTypeDef SDMMC_ConfigData(SDMMC_TypeDef *SDMMCx, SDMMC_DataInitTypeDef* Data);
969 uint32_t SDMMC_GetDataCounter(SDMMC_TypeDef *SDMMCx);
970 uint32_t SDMMC_GetFIFOCount(SDMMC_TypeDef *SDMMCx);
971
972 /* SDMMC Cards mode management functions */
973 HAL_StatusTypeDef SDMMC_SetSDMMCReadWaitMode(SDMMC_TypeDef *SDMMCx, uint32_t SDMMC_ReadWaitMode);
974
975 /* SDMMC Commands management functions */
976 uint32_t SDMMC_CmdBlockLength(SDMMC_TypeDef *SDMMCx, uint32_t BlockSize);
977 uint32_t SDMMC_CmdReadSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
978 uint32_t SDMMC_CmdReadMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t ReadAdd);
979 uint32_t SDMMC_CmdWriteSingleBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
980 uint32_t SDMMC_CmdWriteMultiBlock(SDMMC_TypeDef *SDMMCx, uint32_t WriteAdd);
981 uint32_t SDMMC_CmdEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
982 uint32_t SDMMC_CmdSDEraseStartAdd(SDMMC_TypeDef *SDMMCx, uint32_t StartAdd);
983 uint32_t SDMMC_CmdEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
984 uint32_t SDMMC_CmdSDEraseEndAdd(SDMMC_TypeDef *SDMMCx, uint32_t EndAdd);
985 uint32_t SDMMC_CmdErase(SDMMC_TypeDef *SDMMCx);
986 uint32_t SDMMC_CmdStopTransfer(SDMMC_TypeDef *SDMMCx);
987 uint32_t SDMMC_CmdSelDesel(SDMMC_TypeDef *SDMMCx, uint64_t Addr);
988 uint32_t SDMMC_CmdGoIdleState(SDMMC_TypeDef *SDMMCx);
989 uint32_t SDMMC_CmdOperCond(SDMMC_TypeDef *SDMMCx);
990 uint32_t SDMMC_CmdAppCommand(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
991 uint32_t SDMMC_CmdAppOperCommand(SDMMC_TypeDef *SDMMCx, uint32_t SdType);
992 uint32_t SDMMC_CmdBusWidth(SDMMC_TypeDef *SDMMCx, uint32_t BusWidth);
993 uint32_t SDMMC_CmdSendSCR(SDMMC_TypeDef *SDMMCx);
994 uint32_t SDMMC_CmdSendCID(SDMMC_TypeDef *SDMMCx);
995 uint32_t SDMMC_CmdSendCSD(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
996 uint32_t SDMMC_CmdSetRelAdd(SDMMC_TypeDef *SDMMCx, uint16_t *pRCA);
997 uint32_t SDMMC_CmdSendStatus(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
998 uint32_t SDMMC_CmdStatusRegister(SDMMC_TypeDef *SDMMCx);
999 uint32_t SDMMC_CmdOpCondition(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1000 uint32_t SDMMC_CmdSwitch(SDMMC_TypeDef *SDMMCx, uint32_t Argument);
1001
1002 /**
1003 * @}
1004 */
1005
1006 /**
1007 * @}
1008 */
1009
1010 /**
1011 * @}
1012 */
1013
1014 /**
1015 * @}
1016 */
1017
1018 #ifdef __cplusplus
1019 }
1020 #endif
1021
1022 #endif /* __STM32F7xx_LL_SDMMC_H */
1023
1024 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software