2 ******************************************************************************
3 * @file stm32f7xx_ll_system.h
4 * @author MCD Application Team
7 * @brief Header file of SYSTEM LL module.
9 ==============================================================================
10 ##### How to use this driver #####
11 ==============================================================================
13 The LL SYSTEM driver contains a set of generic APIs that can be
15 (+) Some of the FLASH features need to be handled in the SYSTEM file.
16 (+) Access to DBGCMU registers
17 (+) Access to SYSCFG registers
20 ******************************************************************************
23 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
25 * Redistribution and use in source and binary forms, with or without modification,
26 * are permitted provided that the following conditions are met:
27 * 1. Redistributions of source code must retain the above copyright notice,
28 * this list of conditions and the following disclaimer.
29 * 2. Redistributions in binary form must reproduce the above copyright notice,
30 * this list of conditions and the following disclaimer in the documentation
31 * and/or other materials provided with the distribution.
32 * 3. Neither the name of STMicroelectronics nor the names of its contributors
33 * may be used to endorse or promote products derived from this software
34 * without specific prior written permission.
36 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
37 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
38 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
39 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
40 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
41 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
42 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
43 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
44 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
45 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
47 ******************************************************************************
50 /* Define to prevent recursive inclusion -------------------------------------*/
51 #ifndef __STM32F7xx_LL_SYSTEM_H
52 #define __STM32F7xx_LL_SYSTEM_H
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f7xx.h"
61 /** @addtogroup STM32F7xx_LL_Driver
65 #if defined (FLASH) || defined (SYSCFG) || defined (DBGMCU)
67 /** @defgroup SYSTEM_LL SYSTEM
71 /* Private types -------------------------------------------------------------*/
72 /* Private variables ---------------------------------------------------------*/
74 /* Private constants ---------------------------------------------------------*/
75 /** @defgroup SYSTEM_LL_Private_Constants SYSTEM Private Constants
83 /* Private macros ------------------------------------------------------------*/
85 /* Exported types ------------------------------------------------------------*/
86 /* Exported constants --------------------------------------------------------*/
87 /** @defgroup SYSTEM_LL_Exported_Constants SYSTEM Exported Constants
91 /** @defgroup SYSTEM_LL_EC_REMAP SYSCFG REMAP
94 #define LL_SYSCFG_REMAP_BOOT0 0x00000000U /*!< Boot information after Reset */
95 #define LL_SYSCFG_REMAP_BOOT1 SYSCFG_MEMRMP_MEM_BOOT /*!< Boot information after Reset */
101 #if defined(SYSCFG_MEMRMP_SWP_FB)
102 /** @defgroup SYSTEM_LL_EC_BANKMODE SYSCFG BANK MODE
105 #define LL_SYSCFG_BANKMODE_BANK1 0x00000000U /*!< Flash Bank 1 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000 (TCM)
106 and Flash Bank 2 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000 (TCM)*/
108 #define LL_SYSCFG_BANKMODE_BANK2 SYSCFG_MEMRMP_SWP_FB /*!< Flash Bank 2 base address mapped at 0x0800 0000 (AXI) and 0x0020 0000(TCM)
109 and Flash Bank 1 base address mapped at 0x0810 0000 (AXI) and 0x0030 0000(TCM) */
113 #endif /* SYSCFG_MEMRMP_SWP_FB */
115 #if defined(SYSCFG_PMC_MII_RMII_SEL)
116 /** @defgroup SYSTEM_LL_EC_PMC SYSCFG PMC
119 #define LL_SYSCFG_PMC_ETHMII 0x00000000U /*!< ETH Media MII interface */
120 #define LL_SYSCFG_PMC_ETHRMII (uint32_t)SYSCFG_PMC_MII_RMII_SEL /*!< ETH Media RMII interface */
125 #endif /* SYSCFG_PMC_MII_RMII_SEL */
127 /** @defgroup SYSTEM_LL_EC_I2C_FASTMODEPLUS SYSCFG I2C FASTMODEPLUS
130 #if defined(SYSCFG_PMC_I2C1_FMP)
131 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C1 SYSCFG_PMC_I2C1_FMP /*!< Enable Fast Mode Plus for I2C1 */
132 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 SYSCFG_PMC_I2C2_FMP /*!< Enable Fast Mode Plus for I2C2 */
133 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C3 SYSCFG_PMC_I2C3_FMP /*!< Enable Fast Mode Plus for I2C3 */
134 #endif /* SYSCFG_PMC_I2C1_FMP */
135 #if defined(SYSCFG_PMC_I2C4_FMP)
136 #define LL_SYSCFG_I2C_FASTMODEPLUS_I2C4 SYSCFG_PMC_I2C4_FMP /*!< Enable Fast Mode Plus for I2C4 */
137 #endif /* SYSCFG_PMC_I2C4_FMP */
138 #if defined(SYSCFG_PMC_I2C_PB6_FMP)
139 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB6 SYSCFG_PMC_I2C_PB6_FMP /*!< Enable Fast Mode Plus on PB6 */
140 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB7 SYSCFG_PMC_I2C_PB7_FMP /*!< Enable Fast Mode Plus on PB7 */
141 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB8 SYSCFG_PMC_I2C_PB8_FMP /*!< Enable Fast Mode Plus on PB8 */
142 #define LL_SYSCFG_I2C_FASTMODEPLUS_PB9 SYSCFG_PMC_I2C_PB9_FMP /*!< Enable Fast Mode Plus on PB9 */
143 #endif /* SYSCFG_PMC_I2C_PB6_FMP */
148 /** @defgroup SYSTEM_LL_EC_EXTI_PORT SYSCFG EXTI PORT
151 #define LL_SYSCFG_EXTI_PORTA 0U /*!< EXTI PORT A */
152 #define LL_SYSCFG_EXTI_PORTB 1U /*!< EXTI PORT B */
153 #define LL_SYSCFG_EXTI_PORTC 2U /*!< EXTI PORT C */
154 #define LL_SYSCFG_EXTI_PORTD 3U /*!< EXTI PORT D */
155 #define LL_SYSCFG_EXTI_PORTE 4U /*!< EXTI PORT E */
157 #define LL_SYSCFG_EXTI_PORTF 5U /*!< EXTI PORT F */
160 #define LL_SYSCFG_EXTI_PORTG 6U /*!< EXTI PORT G */
162 #define LL_SYSCFG_EXTI_PORTH 7U /*!< EXTI PORT H */
164 #define LL_SYSCFG_EXTI_PORTI 8U /*!< EXTI PORT I */
167 #define LL_SYSCFG_EXTI_PORTJ 9U /*!< EXTI PORT J */
170 #define LL_SYSCFG_EXTI_PORTK 10U /*!< EXTI PORT k */
176 /** @defgroup SYSTEM_LL_EC_EXTI_LINE SYSCFG EXTI LINE
179 #define LL_SYSCFG_EXTI_LINE0 (0x000FU << 16U | 0U) /*!< EXTI_POSITION_0 | EXTICR[0] */
180 #define LL_SYSCFG_EXTI_LINE1 (0x00F0U << 16U | 0U) /*!< EXTI_POSITION_4 | EXTICR[0] */
181 #define LL_SYSCFG_EXTI_LINE2 (0x0F00U << 16U | 0U) /*!< EXTI_POSITION_8 | EXTICR[0] */
182 #define LL_SYSCFG_EXTI_LINE3 (0xF000U << 16U | 0U) /*!< EXTI_POSITION_12 | EXTICR[0] */
183 #define LL_SYSCFG_EXTI_LINE4 (0x000FU << 16U | 1U) /*!< EXTI_POSITION_0 | EXTICR[1] */
184 #define LL_SYSCFG_EXTI_LINE5 (0x00F0U << 16U | 1U) /*!< EXTI_POSITION_4 | EXTICR[1] */
185 #define LL_SYSCFG_EXTI_LINE6 (0x0F00U << 16U | 1U) /*!< EXTI_POSITION_8 | EXTICR[1] */
186 #define LL_SYSCFG_EXTI_LINE7 (0xF000U << 16U | 1U) /*!< EXTI_POSITION_12 | EXTICR[1] */
187 #define LL_SYSCFG_EXTI_LINE8 (0x000FU << 16U | 2U) /*!< EXTI_POSITION_0 | EXTICR[2] */
188 #define LL_SYSCFG_EXTI_LINE9 (0x00F0U << 16U | 2U) /*!< EXTI_POSITION_4 | EXTICR[2] */
189 #define LL_SYSCFG_EXTI_LINE10 (0x0F00U << 16U | 2U) /*!< EXTI_POSITION_8 | EXTICR[2] */
190 #define LL_SYSCFG_EXTI_LINE11 (0xF000U << 16U | 2U) /*!< EXTI_POSITION_12 | EXTICR[2] */
191 #define LL_SYSCFG_EXTI_LINE12 (0x000FU << 16U | 3U) /*!< EXTI_POSITION_0 | EXTICR[3] */
192 #define LL_SYSCFG_EXTI_LINE13 (0x00F0U << 16U | 3U) /*!< EXTI_POSITION_4 | EXTICR[3] */
193 #define LL_SYSCFG_EXTI_LINE14 (0x0F00U << 16U | 3U) /*!< EXTI_POSITION_8 | EXTICR[3] */
194 #define LL_SYSCFG_EXTI_LINE15 (0xF000U << 16U | 3U) /*!< EXTI_POSITION_12 | EXTICR[3] */
199 /** @defgroup SYSTEM_LL_EC_TIMBREAK SYSCFG TIMER BREAK
202 #if defined(SYSCFG_CBR_CLL)
203 #define LL_SYSCFG_TIMBREAK_LOCKUP SYSCFG_CBR_CLL /*!< Enables and locks the Lockup output (raised during core
204 lockup state) of Cortex-M7 with Break Input of TIMER1, TIMER8 */
205 #define LL_SYSCFG_TIMBREAK_PVD SYSCFG_CBR_PVDL /*!< Enables and locks the PVD connection with TIMER1, TIMER8 Break input.
206 It also locks (write protect) the PVD_EN and PVDSEL[2:0] bits
207 of the power controller */
208 #endif /* SYSCFG_CBR_CLL */
212 /** @defgroup SYSTEM_LL_EC_CMP_PD SYSCFG CMP PD
215 #define LL_SYSCFG_DISABLE_CMP_PD 0x00000000U /*!< I/O compensation cell power-down mode */
216 #define LL_SYSCFG_ENABLE_CMP_PD SYSCFG_CMPCR_CMP_PD /*!< I/O compensation cell enabled */
221 /** @defgroup SYSTEM_LL_EC_TRACE DBGMCU TRACE Pin Assignment
224 #define LL_DBGMCU_TRACE_NONE 0x00000000U /*!< TRACE pins not assigned (default state) */
225 #define LL_DBGMCU_TRACE_ASYNCH DBGMCU_CR_TRACE_IOEN /*!< TRACE pin assignment for Asynchronous Mode */
226 #define LL_DBGMCU_TRACE_SYNCH_SIZE1 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_0) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 1 */
227 #define LL_DBGMCU_TRACE_SYNCH_SIZE2 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE_1) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 2 */
228 #define LL_DBGMCU_TRACE_SYNCH_SIZE4 (DBGMCU_CR_TRACE_IOEN | DBGMCU_CR_TRACE_MODE) /*!< TRACE pin assignment for Synchronous Mode with a TRACEDATA size of 4 */
233 /** @defgroup SYSTEM_LL_EC_APB1_GRP1_STOP_IP DBGMCU APB1 GRP1 STOP IP
236 #define LL_DBGMCU_APB1_GRP1_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP /*!< TIM2 counter stopped when core is halted */
237 #define LL_DBGMCU_APB1_GRP1_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP /*!< TIM3 counter stopped when core is halted */
238 #define LL_DBGMCU_APB1_GRP1_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP /*!< TIM4 counter stopped when core is halted */
239 #define LL_DBGMCU_APB1_GRP1_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP /*!< TIM5 counter stopped when core is halted */
240 #define LL_DBGMCU_APB1_GRP1_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP /*!< TIM6 counter stopped when core is halted */
241 #define LL_DBGMCU_APB1_GRP1_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP /*!< TIM7 counter stopped when core is halted */
242 #define LL_DBGMCU_APB1_GRP1_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP /*!< TIM12 counter stopped when core is halted */
243 #define LL_DBGMCU_APB1_GRP1_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP /*!< TIM13 counter stopped when core is halted */
244 #define LL_DBGMCU_APB1_GRP1_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP /*!< TIM14 counter stopped when core is halted */
245 #define LL_DBGMCU_APB1_GRP1_LPTIM1_STOP DBGMCU_APB1_FZ_DBG_LPTIM1_STOP /*!< LPTIIM1 counter stopped when core is halted */
246 #define LL_DBGMCU_APB1_GRP1_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP /*!< RTC counter stopped when core is halted */
247 #define LL_DBGMCU_APB1_GRP1_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP /*!< Debug Window Watchdog stopped when Core is halted */
248 #define LL_DBGMCU_APB1_GRP1_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP /*!< Debug Independent Watchdog stopped when Core is halted */
249 #define LL_DBGMCU_APB1_GRP1_I2C1_STOP DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT /*!< I2C1 SMBUS timeout mode stopped when Core is halted */
250 #define LL_DBGMCU_APB1_GRP1_I2C2_STOP DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT /*!< I2C2 SMBUS timeout mode stopped when Core is halted */
251 #define LL_DBGMCU_APB1_GRP1_I2C3_STOP DBGMCU_APB1_FZ_DBG_I2C3_SMBUS_TIMEOUT /*!< I2C3 SMBUS timeout mode stopped when Core is halted */
252 #if defined(DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT)
253 #define LL_DBGMCU_APB1_GRP1_I2C4_STOP DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT /*!< I2C4 SMBUS timeout mode stopped when core is halted */
254 #endif /* DBGMCU_APB1_FZ_DBG_I2C4_SMBUS_TIMEOUT */
255 #define LL_DBGMCU_APB1_GRP1_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP /*!< CAN1 debug stopped when Core is halted */
256 #if defined(DBGMCU_APB1_FZ_DBG_CAN2_STOP)
257 #define LL_DBGMCU_APB1_GRP1_CAN2_STOP DBGMCU_APB1_FZ_DBG_CAN2_STOP /*!< CAN2 debug stopped when Core is halted */
258 #endif /* DBGMCU_APB1_FZ_DBG_CAN2_STOP */
259 #if defined(DBGMCU_APB1_FZ_DBG_CAN3_STOP)
260 #define LL_DBGMCU_APB1_GRP1_CAN3_STOP DBGMCU_APB1_FZ_DBG_CAN3_STOP /*!< CAN3 debug stopped when Core is halted */
261 #endif /*DBGMCU_APB1_FZ_DBG_CAN3_STOP*/
266 /** @defgroup SYSTEM_LL_EC_APB2_GRP1_STOP_IP DBGMCU APB2 GRP1 STOP IP
269 #define LL_DBGMCU_APB2_GRP1_TIM1_STOP DBGMCU_APB2_FZ_DBG_TIM1_STOP /*!< TIM1 counter stopped when core is halted */
270 #define LL_DBGMCU_APB2_GRP1_TIM8_STOP DBGMCU_APB2_FZ_DBG_TIM8_STOP /*!< TIM8 counter stopped when core is halted */
271 #define LL_DBGMCU_APB2_GRP1_TIM9_STOP DBGMCU_APB2_FZ_DBG_TIM9_STOP /*!< TIM9 counter stopped when core is halted */
272 #define LL_DBGMCU_APB2_GRP1_TIM10_STOP DBGMCU_APB2_FZ_DBG_TIM10_STOP /*!< TIM10 counter stopped when core is halted */
273 #define LL_DBGMCU_APB2_GRP1_TIM11_STOP DBGMCU_APB2_FZ_DBG_TIM11_STOP /*!< TIM11 counter stopped when core is halted */
278 /** @defgroup SYSTEM_LL_EC_LATENCY FLASH LATENCY
281 #define LL_FLASH_LATENCY_0 FLASH_ACR_LATENCY_0WS /*!< FLASH Zero wait state */
282 #define LL_FLASH_LATENCY_1 FLASH_ACR_LATENCY_1WS /*!< FLASH One wait state */
283 #define LL_FLASH_LATENCY_2 FLASH_ACR_LATENCY_2WS /*!< FLASH Two wait states */
284 #define LL_FLASH_LATENCY_3 FLASH_ACR_LATENCY_3WS /*!< FLASH Three wait states */
285 #define LL_FLASH_LATENCY_4 FLASH_ACR_LATENCY_4WS /*!< FLASH Four wait states */
286 #define LL_FLASH_LATENCY_5 FLASH_ACR_LATENCY_5WS /*!< FLASH five wait state */
287 #define LL_FLASH_LATENCY_6 FLASH_ACR_LATENCY_6WS /*!< FLASH six wait state */
288 #define LL_FLASH_LATENCY_7 FLASH_ACR_LATENCY_7WS /*!< FLASH seven wait states */
289 #define LL_FLASH_LATENCY_8 FLASH_ACR_LATENCY_8WS /*!< FLASH eight wait states */
290 #define LL_FLASH_LATENCY_9 FLASH_ACR_LATENCY_9WS /*!< FLASH nine wait states */
291 #define LL_FLASH_LATENCY_10 FLASH_ACR_LATENCY_10WS /*!< FLASH ten wait states */
292 #define LL_FLASH_LATENCY_11 FLASH_ACR_LATENCY_11WS /*!< FLASH eleven wait states */
293 #define LL_FLASH_LATENCY_12 FLASH_ACR_LATENCY_12WS /*!< FLASH twelve wait states */
294 #define LL_FLASH_LATENCY_13 FLASH_ACR_LATENCY_13WS /*!< FLASH thirteen wait states */
295 #define LL_FLASH_LATENCY_14 FLASH_ACR_LATENCY_14WS /*!< FLASH fourteen wait states */
296 #define LL_FLASH_LATENCY_15 FLASH_ACR_LATENCY_15WS /*!< FLASH fifteen wait states */
305 /* Exported macro ------------------------------------------------------------*/
307 /* Exported functions --------------------------------------------------------*/
308 /** @defgroup SYSTEM_LL_Exported_Functions SYSTEM Exported Functions
312 /** @defgroup SYSTEM_LL_EF_SYSCFG SYSCFG
317 * @brief Enables the FMC Memory Mapping Swapping
318 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_EnableFMCMemorySwapping
319 * @note SDRAM is accessible at 0x60000000 and NOR/RAM
320 * is accessible at 0xC0000000
323 __STATIC_INLINE
void LL_SYSCFG_EnableFMCMemorySwapping(void)
325 SET_BIT(SYSCFG
->MEMRMP
, SYSCFG_MEMRMP_SWP_FMC_0
);
329 * @brief Disables the FMC Memory Mapping Swapping
330 * @rmtoll SYSCFG_MEMRMP SWP_FMC LL_SYSCFG_DisableFMCMemorySwapping
331 * @note SDRAM is accessible at 0xC0000000 (default mapping)
332 * and NOR/RAM is accessible at 0x60000000 (default mapping)
335 __STATIC_INLINE
void LL_SYSCFG_DisableFMCMemorySwapping(void)
337 CLEAR_BIT(SYSCFG
->MEMRMP
, SYSCFG_MEMRMP_SWP_FMC
);
341 * @brief Enables the Compensation Cell
342 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_EnableCompensationCell
343 * @note The I/O compensation cell can be used only when the device supply
344 * voltage ranges from 2.4 to 3.6 V
347 __STATIC_INLINE
void LL_SYSCFG_EnableCompensationCell(void)
349 SET_BIT(SYSCFG
->CMPCR
, SYSCFG_CMPCR_CMP_PD
);
353 * @brief Disables the Compensation Cell
354 * @rmtoll SYSCFG_CMPCR CMP_PD LL_SYSCFG_DisableCompensationCell
355 * @note The I/O compensation cell can be used only when the device supply
356 * voltage ranges from 2.4 to 3.6 V
359 __STATIC_INLINE
void LL_SYSCFG_DisableCompensationCell(void)
361 CLEAR_BIT(SYSCFG
->CMPCR
, SYSCFG_CMPCR_CMP_PD
);
365 * @brief Get Compensation Cell ready Flag
366 * @rmtoll SYSCFG_CMPCR READY LL_SYSCFG_IsActiveFlag_CMPCR
367 * @retval State of bit (1 or 0).
369 __STATIC_INLINE
uint32_t LL_SYSCFG_IsActiveFlag_CMPCR(void)
371 return (READ_BIT(SYSCFG
->CMPCR
, SYSCFG_CMPCR_READY
) == (SYSCFG_CMPCR_READY
));
376 * @brief Get the memory boot mapping as configured by user
377 * @rmtoll SYSCFG_MEMRMP MEM_BOOT LL_SYSCFG_GetRemapMemoryBoot
378 * @retval Returned value can be one of the following values:
379 * @arg @ref LL_SYSCFG_REMAP_BOOT0
380 * @arg @ref LL_SYSCFG_REMAP_BOOT1
382 * (*) value not defined in all devices
384 __STATIC_INLINE
uint32_t LL_SYSCFG_GetRemapMemoryBoot(void)
386 return (uint32_t)(READ_BIT(SYSCFG
->MEMRMP
, SYSCFG_MEMRMP_MEM_BOOT
));
389 #if defined(SYSCFG_PMC_MII_RMII_SEL)
391 * @brief Select Ethernet PHY interface
392 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_SetPHYInterface
393 * @param Interface This parameter can be one of the following values:
394 * @arg @ref LL_SYSCFG_PMC_ETHMII
395 * @arg @ref LL_SYSCFG_PMC_ETHRMII
398 __STATIC_INLINE
void LL_SYSCFG_SetPHYInterface(uint32_t Interface
)
400 MODIFY_REG(SYSCFG
->PMC
, SYSCFG_PMC_MII_RMII_SEL
, Interface
);
404 * @brief Get Ethernet PHY interface
405 * @rmtoll SYSCFG_PMC MII_RMII_SEL LL_SYSCFG_GetPHYInterface
406 * @retval Returned value can be one of the following values:
407 * @arg @ref LL_SYSCFG_PMC_ETHMII
408 * @arg @ref LL_SYSCFG_PMC_ETHRMII
411 __STATIC_INLINE
uint32_t LL_SYSCFG_GetPHYInterface(void)
413 return (uint32_t)(READ_BIT(SYSCFG
->PMC
, SYSCFG_PMC_MII_RMII_SEL
));
415 #endif /* SYSCFG_PMC_MII_RMII_SEL */
418 #if defined(SYSCFG_MEMRMP_SWP_FB)
420 * @brief Select Flash bank mode (Bank flashed at 0x08000000)
421 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_SetFlashBankMode
422 * @param Bank This parameter can be one of the following values:
423 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
424 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
427 __STATIC_INLINE
void LL_SYSCFG_SetFlashBankMode(uint32_t Bank
)
429 MODIFY_REG(SYSCFG
->MEMRMP
, SYSCFG_MEMRMP_SWP_FB
, Bank
);
433 * @brief Get Flash bank mode (Bank flashed at 0x08000000)
434 * @rmtoll SYSCFG_MEMRMP FB_MODE LL_SYSCFG_GetFlashBankMode
435 * @retval Returned value can be one of the following values:
436 * @arg @ref LL_SYSCFG_BANKMODE_BANK1
437 * @arg @ref LL_SYSCFG_BANKMODE_BANK2
439 __STATIC_INLINE
uint32_t LL_SYSCFG_GetFlashBankMode(void)
441 return (uint32_t)(READ_BIT(SYSCFG
->MEMRMP
, SYSCFG_MEMRMP_SWP_FB
));
444 #endif /* SYSCFG_MEMRMP_SWP_FB */
446 #if defined(SYSCFG_PMC_I2C1_FMP)
448 * @brief Enable the I2C fast mode plus driving capability.
449 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_EnableFastModePlus\n
450 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_EnableFastModePlus
451 * @param ConfigFastModePlus This parameter can be a combination of the following values:
452 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
453 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
454 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
455 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
456 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
457 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
458 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
459 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4(*)
461 * (*) value not defined in all devices
464 __STATIC_INLINE
void LL_SYSCFG_EnableFastModePlus(uint32_t ConfigFastModePlus
)
466 SET_BIT(SYSCFG
->PMC
, ConfigFastModePlus
);
470 * @brief Disable the I2C fast mode plus driving capability.
471 * @rmtoll SYSCFG_PMC I2C_PBx_FMP LL_SYSCFG_DisableFastModePlus\n
472 * SYSCFG_PMC I2Cx_FMP LL_SYSCFG_DisableFastModePlus
473 * @param ConfigFastModePlus This parameter can be a combination of the following values:
474 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB6
475 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB7
476 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB8 (*)
477 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_PB9 (*)
478 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C1
479 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C2 (*)
480 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C3
481 * @arg @ref LL_SYSCFG_I2C_FASTMODEPLUS_I2C4
482 * (*) value not defined in all devices
485 __STATIC_INLINE
void LL_SYSCFG_DisableFastModePlus(uint32_t ConfigFastModePlus
)
487 CLEAR_BIT(SYSCFG
->PMC
, ConfigFastModePlus
);
489 #endif /* SYSCFG_PMC_I2C1_FMP */
493 * @brief Configure source input for the EXTI external interrupt.
494 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_SetEXTISource\n
495 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_SetEXTISource\n
496 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_SetEXTISource\n
497 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_SetEXTISource
498 * @param Port This parameter can be one of the following values:
499 * @arg @ref LL_SYSCFG_EXTI_PORTA
500 * @arg @ref LL_SYSCFG_EXTI_PORTB
501 * @arg @ref LL_SYSCFG_EXTI_PORTC
502 * @arg @ref LL_SYSCFG_EXTI_PORTD
503 * @arg @ref LL_SYSCFG_EXTI_PORTE
504 * @arg @ref LL_SYSCFG_EXTI_PORTF
505 * @arg @ref LL_SYSCFG_EXTI_PORTG
506 * @arg @ref LL_SYSCFG_EXTI_PORTH
507 * @arg @ref LL_SYSCFG_EXTI_PORTI
508 * @arg @ref LL_SYSCFG_EXTI_PORTJ
509 * @arg @ref LL_SYSCFG_EXTI_PORTK
511 * (*) value not defined in all devices
512 * @param Line This parameter can be one of the following values:
513 * @arg @ref LL_SYSCFG_EXTI_LINE0
514 * @arg @ref LL_SYSCFG_EXTI_LINE1
515 * @arg @ref LL_SYSCFG_EXTI_LINE2
516 * @arg @ref LL_SYSCFG_EXTI_LINE3
517 * @arg @ref LL_SYSCFG_EXTI_LINE4
518 * @arg @ref LL_SYSCFG_EXTI_LINE5
519 * @arg @ref LL_SYSCFG_EXTI_LINE6
520 * @arg @ref LL_SYSCFG_EXTI_LINE7
521 * @arg @ref LL_SYSCFG_EXTI_LINE8
522 * @arg @ref LL_SYSCFG_EXTI_LINE9
523 * @arg @ref LL_SYSCFG_EXTI_LINE10
524 * @arg @ref LL_SYSCFG_EXTI_LINE11
525 * @arg @ref LL_SYSCFG_EXTI_LINE12
526 * @arg @ref LL_SYSCFG_EXTI_LINE13
527 * @arg @ref LL_SYSCFG_EXTI_LINE14
528 * @arg @ref LL_SYSCFG_EXTI_LINE15
531 __STATIC_INLINE
void LL_SYSCFG_SetEXTISource(uint32_t Port
, uint32_t Line
)
533 MODIFY_REG(SYSCFG
->EXTICR
[Line
& 0xFFU
], (Line
>> 16U), Port
<< POSITION_VAL((Line
>> 16U)));
537 * @brief Get the configured defined for specific EXTI Line
538 * @rmtoll SYSCFG_EXTICR1 EXTIx LL_SYSCFG_GetEXTISource\n
539 * SYSCFG_EXTICR2 EXTIx LL_SYSCFG_GetEXTISource\n
540 * SYSCFG_EXTICR3 EXTIx LL_SYSCFG_GetEXTISource\n
541 * SYSCFG_EXTICR4 EXTIx LL_SYSCFG_GetEXTISource
542 * @param Line This parameter can be one of the following values:
543 * @arg @ref LL_SYSCFG_EXTI_LINE0
544 * @arg @ref LL_SYSCFG_EXTI_LINE1
545 * @arg @ref LL_SYSCFG_EXTI_LINE2
546 * @arg @ref LL_SYSCFG_EXTI_LINE3
547 * @arg @ref LL_SYSCFG_EXTI_LINE4
548 * @arg @ref LL_SYSCFG_EXTI_LINE5
549 * @arg @ref LL_SYSCFG_EXTI_LINE6
550 * @arg @ref LL_SYSCFG_EXTI_LINE7
551 * @arg @ref LL_SYSCFG_EXTI_LINE8
552 * @arg @ref LL_SYSCFG_EXTI_LINE9
553 * @arg @ref LL_SYSCFG_EXTI_LINE10
554 * @arg @ref LL_SYSCFG_EXTI_LINE11
555 * @arg @ref LL_SYSCFG_EXTI_LINE12
556 * @arg @ref LL_SYSCFG_EXTI_LINE13
557 * @arg @ref LL_SYSCFG_EXTI_LINE14
558 * @arg @ref LL_SYSCFG_EXTI_LINE15
559 * @retval Returned value can be one of the following values:
560 * @arg @ref LL_SYSCFG_EXTI_PORTA
561 * @arg @ref LL_SYSCFG_EXTI_PORTB
562 * @arg @ref LL_SYSCFG_EXTI_PORTC
563 * @arg @ref LL_SYSCFG_EXTI_PORTD
564 * @arg @ref LL_SYSCFG_EXTI_PORTE
565 * @arg @ref LL_SYSCFG_EXTI_PORTF
566 * @arg @ref LL_SYSCFG_EXTI_PORTG
567 * @arg @ref LL_SYSCFG_EXTI_PORTH
568 * @arg @ref LL_SYSCFG_EXTI_PORTI
569 * @arg @ref LL_SYSCFG_EXTI_PORTJ
570 * @arg @ref LL_SYSCFG_EXTI_PORTK
571 * (*) value not defined in all devices
573 __STATIC_INLINE
uint32_t LL_SYSCFG_GetEXTISource(uint32_t Line
)
575 return (uint32_t)(READ_BIT(SYSCFG
->EXTICR
[Line
& 0xFFU
], (Line
>> 16U)) >> POSITION_VAL(Line
>> 16U));
578 #if defined(SYSCFG_CBR_CLL)
580 * @brief Set connections to TIM1/8/15/16/17 Break inputs
581 * SYSCFG_CBR CLL LL_SYSCFG_SetTIMBreakInputs\n
582 * SYSCFG_CBR PVDL LL_SYSCFG_SetTIMBreakInputs
583 * @param Break This parameter can be a combination of the following values:
584 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
585 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
588 __STATIC_INLINE
void LL_SYSCFG_SetTIMBreakInputs(uint32_t Break
)
590 MODIFY_REG(SYSCFG
->CBR
, SYSCFG_CBR_CLL
| SYSCFG_CBR_PVDL
, Break
);
594 * @brief Get connections to TIM1/8/15/16/17 Break inputs
595 * SYSCFG_CBR CLL LL_SYSCFG_GetTIMBreakInputs\n
596 * SYSCFG_CBR PVDL LL_SYSCFG_GetTIMBreakInputs
597 * @retval Returned value can be can be a combination of the following values:
598 * @arg @ref LL_SYSCFG_TIMBREAK_LOCKUP
599 * @arg @ref LL_SYSCFG_TIMBREAK_PVD
601 __STATIC_INLINE
uint32_t LL_SYSCFG_GetTIMBreakInputs(void)
603 return (uint32_t)(READ_BIT(SYSCFG
->CBR
, SYSCFG_CBR_CLL
| SYSCFG_CBR_PVDL
));
605 #endif /* SYSCFG_CBR_CLL */
611 /** @defgroup SYSTEM_LL_EF_DBGMCU DBGMCU
616 * @brief Return the device identifier
617 * @note For STM32F75xxx and STM32F74xxx devices, the device ID is 0x449
618 * @note For STM32F77xxx and STM32F76xxx devices, the device ID is 0x451
619 * @note For STM32F72xxx and STM32F73xxx devices, the device ID is 0x452
620 * @rmtoll DBGMCU_IDCODE DEV_ID LL_DBGMCU_GetDeviceID
621 * @retval Values between Min_Data=0x00 and Max_Data=0xFFF
623 __STATIC_INLINE
uint32_t LL_DBGMCU_GetDeviceID(void)
625 return (uint32_t)(READ_BIT(DBGMCU
->IDCODE
, DBGMCU_IDCODE_DEV_ID
));
629 * @brief Return the device revision identifier
630 * @note This field indicates the revision of the device.
631 For example, it is read as RevA -> 0x1000, Cat 2 revZ -> 0x1001
632 * @rmtoll DBGMCU_IDCODE REV_ID LL_DBGMCU_GetRevisionID
633 * @retval Values between Min_Data=0x00 and Max_Data=0xFFFF
635 __STATIC_INLINE
uint32_t LL_DBGMCU_GetRevisionID(void)
637 return (uint32_t)(READ_BIT(DBGMCU
->IDCODE
, DBGMCU_IDCODE_REV_ID
) >> DBGMCU_IDCODE_REV_ID_Pos
);
641 * @brief Enable the Debug Module during SLEEP mode
642 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_EnableDBGSleepMode
645 __STATIC_INLINE
void LL_DBGMCU_EnableDBGSleepMode(void)
647 SET_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_SLEEP
);
651 * @brief Disable the Debug Module during SLEEP mode
652 * @rmtoll DBGMCU_CR DBG_SLEEP LL_DBGMCU_DisableDBGSleepMode
655 __STATIC_INLINE
void LL_DBGMCU_DisableDBGSleepMode(void)
657 CLEAR_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_SLEEP
);
661 * @brief Enable the Debug Module during STOP mode
662 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_EnableDBGStopMode
665 __STATIC_INLINE
void LL_DBGMCU_EnableDBGStopMode(void)
667 SET_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_STOP
);
671 * @brief Disable the Debug Module during STOP mode
672 * @rmtoll DBGMCU_CR DBG_STOP LL_DBGMCU_DisableDBGStopMode
675 __STATIC_INLINE
void LL_DBGMCU_DisableDBGStopMode(void)
677 CLEAR_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_STOP
);
681 * @brief Enable the Debug Module during STANDBY mode
682 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_EnableDBGStandbyMode
685 __STATIC_INLINE
void LL_DBGMCU_EnableDBGStandbyMode(void)
687 SET_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_STANDBY
);
691 * @brief Disable the Debug Module during STANDBY mode
692 * @rmtoll DBGMCU_CR DBG_STANDBY LL_DBGMCU_DisableDBGStandbyMode
695 __STATIC_INLINE
void LL_DBGMCU_DisableDBGStandbyMode(void)
697 CLEAR_BIT(DBGMCU
->CR
, DBGMCU_CR_DBG_STANDBY
);
701 * @brief Set Trace pin assignment control
702 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_SetTracePinAssignment\n
703 * DBGMCU_CR TRACE_MODE LL_DBGMCU_SetTracePinAssignment
704 * @param PinAssignment This parameter can be one of the following values:
705 * @arg @ref LL_DBGMCU_TRACE_NONE
706 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
707 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
708 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
709 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
712 __STATIC_INLINE
void LL_DBGMCU_SetTracePinAssignment(uint32_t PinAssignment
)
714 MODIFY_REG(DBGMCU
->CR
, DBGMCU_CR_TRACE_IOEN
| DBGMCU_CR_TRACE_MODE
, PinAssignment
);
718 * @brief Get Trace pin assignment control
719 * @rmtoll DBGMCU_CR TRACE_IOEN LL_DBGMCU_GetTracePinAssignment\n
720 * DBGMCU_CR TRACE_MODE LL_DBGMCU_GetTracePinAssignment
721 * @retval Returned value can be one of the following values:
722 * @arg @ref LL_DBGMCU_TRACE_NONE
723 * @arg @ref LL_DBGMCU_TRACE_ASYNCH
724 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE1
725 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE2
726 * @arg @ref LL_DBGMCU_TRACE_SYNCH_SIZE4
728 __STATIC_INLINE
uint32_t LL_DBGMCU_GetTracePinAssignment(void)
730 return (uint32_t)(READ_BIT(DBGMCU
->CR
, DBGMCU_CR_TRACE_IOEN
| DBGMCU_CR_TRACE_MODE
));
734 * @brief Freeze APB1 peripherals (group1 peripherals)
735 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
736 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
737 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
738 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
739 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
740 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
741 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
742 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
743 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
744 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
745 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
746 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
747 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
748 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
749 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
750 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
751 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_FreezePeriph\n
752 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
753 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph\n
754 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_FreezePeriph
755 * @param Periphs This parameter can be a combination of the following values:
756 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
757 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
758 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
759 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
760 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
761 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
762 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
763 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
764 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
765 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
766 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
767 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
768 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
769 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
770 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
771 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
772 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
773 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
774 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
775 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
777 * (*) value not defined in all devices.
780 __STATIC_INLINE
void LL_DBGMCU_APB1_GRP1_FreezePeriph(uint32_t Periphs
)
782 SET_BIT(DBGMCU
->APB1FZ
, Periphs
);
786 * @brief Unfreeze APB1 peripherals (group1 peripherals)
787 * @rmtoll DBGMCU_APB1_FZ DBG_TIM2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
788 * DBGMCU_APB1_FZ DBG_TIM3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
789 * DBGMCU_APB1_FZ DBG_TIM4_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
790 * DBGMCU_APB1_FZ DBG_TIM5_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
791 * DBGMCU_APB1_FZ DBG_TIM6_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
792 * DBGMCU_APB1_FZ DBG_TIM7_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
793 * DBGMCU_APB1_FZ DBG_TIM12_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
794 * DBGMCU_APB1_FZ DBG_TIM13_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
795 * DBGMCU_APB1_FZ DBG_TIM14_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
796 * DBGMCU_APB1_FZ DBG_LPTIM1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
797 * DBGMCU_APB1_FZ DBG_RTC_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
798 * DBGMCU_APB1_FZ DBG_WWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
799 * DBGMCU_APB1_FZ DBG_IWDG_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
800 * DBGMCU_APB1_FZ DBG_I2C1_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
801 * DBGMCU_APB1_FZ DBG_I2C2_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
802 * DBGMCU_APB1_FZ DBG_I2C3_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
803 * DBGMCU_APB1_FZ DBG_I2C4_SMBUS_TIMEOUT LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
804 * DBGMCU_APB1_FZ DBG_CAN1_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
805 * DBGMCU_APB1_FZ DBG_CAN2_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph\n
806 * DBGMCU_APB1_FZ DBG_CAN3_STOP LL_DBGMCU_APB1_GRP1_UnFreezePeriph
807 * @param Periphs This parameter can be a combination of the following values:
808 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM2_STOP
809 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM3_STOP
810 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM4_STOP
811 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM5_STOP
812 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM6_STOP
813 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM7_STOP
814 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM12_STOP
815 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM13_STOP
816 * @arg @ref LL_DBGMCU_APB1_GRP1_TIM14_STOP
817 * @arg @ref LL_DBGMCU_APB1_GRP1_LPTIM1_STOP
818 * @arg @ref LL_DBGMCU_APB1_GRP1_RTC_STOP
819 * @arg @ref LL_DBGMCU_APB1_GRP1_WWDG_STOP
820 * @arg @ref LL_DBGMCU_APB1_GRP1_IWDG_STOP
821 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C1_STOP
822 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C2_STOP
823 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C3_STOP
824 * @arg @ref LL_DBGMCU_APB1_GRP1_I2C4_STOP (*)
825 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN1_STOP
826 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN2_STOP (*)
827 * @arg @ref LL_DBGMCU_APB1_GRP1_CAN3_STOP (*)
828 * (*) value not defined in all devices.
831 __STATIC_INLINE
void LL_DBGMCU_APB1_GRP1_UnFreezePeriph(uint32_t Periphs
)
833 CLEAR_BIT(DBGMCU
->APB1FZ
, Periphs
);
837 * @brief Freeze APB2 peripherals
838 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
839 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
840 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
841 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph\n
842 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_FreezePeriph
843 * @param Periphs This parameter can be a combination of the following values:
844 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
845 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
846 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
847 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
848 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
850 * (*) value not defined in all devices.
853 __STATIC_INLINE
void LL_DBGMCU_APB2_GRP1_FreezePeriph(uint32_t Periphs
)
855 SET_BIT(DBGMCU
->APB2FZ
, Periphs
);
859 * @brief Unfreeze APB2 peripherals
860 * @rmtoll DBGMCU_APB2_FZ DBG_TIM1_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
861 * DBGMCU_APB2_FZ DBG_TIM8_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
862 * DBGMCU_APB2_FZ DBG_TIM9_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
863 * DBGMCU_APB2_FZ DBG_TIM10_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph\n
864 * DBGMCU_APB2_FZ DBG_TIM11_STOP LL_DBGMCU_APB2_GRP1_UnFreezePeriph
865 * @param Periphs This parameter can be a combination of the following values:
866 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM1_STOP
867 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM8_STOP
868 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM9_STOP
869 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM10_STOP
870 * @arg @ref LL_DBGMCU_APB2_GRP1_TIM11_STOP
872 * (*) value not defined in all devices.
875 __STATIC_INLINE
void LL_DBGMCU_APB2_GRP1_UnFreezePeriph(uint32_t Periphs
)
877 CLEAR_BIT(DBGMCU
->APB2FZ
, Periphs
);
883 /** @defgroup SYSTEM_LL_EF_FLASH FLASH
888 * @brief Set FLASH Latency
889 * @rmtoll FLASH_ACR LATENCY LL_FLASH_SetLatency
890 * @param Latency This parameter can be one of the following values:
891 * @arg @ref LL_FLASH_LATENCY_0
892 * @arg @ref LL_FLASH_LATENCY_1
893 * @arg @ref LL_FLASH_LATENCY_2
894 * @arg @ref LL_FLASH_LATENCY_3
895 * @arg @ref LL_FLASH_LATENCY_4
896 * @arg @ref LL_FLASH_LATENCY_5
897 * @arg @ref LL_FLASH_LATENCY_6
898 * @arg @ref LL_FLASH_LATENCY_7
899 * @arg @ref LL_FLASH_LATENCY_8
900 * @arg @ref LL_FLASH_LATENCY_9
901 * @arg @ref LL_FLASH_LATENCY_10
902 * @arg @ref LL_FLASH_LATENCY_11
903 * @arg @ref LL_FLASH_LATENCY_12
904 * @arg @ref LL_FLASH_LATENCY_13
905 * @arg @ref LL_FLASH_LATENCY_14
906 * @arg @ref LL_FLASH_LATENCY_15
909 __STATIC_INLINE
void LL_FLASH_SetLatency(uint32_t Latency
)
911 MODIFY_REG(FLASH
->ACR
, FLASH_ACR_LATENCY
, Latency
);
915 * @brief Get FLASH Latency
916 * @rmtoll FLASH_ACR LATENCY LL_FLASH_GetLatency
917 * @retval Returned value can be one of the following values:
918 * @arg @ref LL_FLASH_LATENCY_0
919 * @arg @ref LL_FLASH_LATENCY_1
920 * @arg @ref LL_FLASH_LATENCY_2
921 * @arg @ref LL_FLASH_LATENCY_3
922 * @arg @ref LL_FLASH_LATENCY_4
923 * @arg @ref LL_FLASH_LATENCY_5
924 * @arg @ref LL_FLASH_LATENCY_6
925 * @arg @ref LL_FLASH_LATENCY_7
926 * @arg @ref LL_FLASH_LATENCY_8
927 * @arg @ref LL_FLASH_LATENCY_9
928 * @arg @ref LL_FLASH_LATENCY_10
929 * @arg @ref LL_FLASH_LATENCY_11
930 * @arg @ref LL_FLASH_LATENCY_12
931 * @arg @ref LL_FLASH_LATENCY_13
932 * @arg @ref LL_FLASH_LATENCY_14
933 * @arg @ref LL_FLASH_LATENCY_15
935 __STATIC_INLINE
uint32_t LL_FLASH_GetLatency(void)
937 return (uint32_t)(READ_BIT(FLASH
->ACR
, FLASH_ACR_LATENCY
));
941 * @brief Enable Prefetch
942 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_EnablePrefetch
945 __STATIC_INLINE
void LL_FLASH_EnablePrefetch(void)
947 SET_BIT(FLASH
->ACR
, FLASH_ACR_PRFTEN
);
951 * @brief Disable Prefetch
952 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_DisablePrefetch
955 __STATIC_INLINE
void LL_FLASH_DisablePrefetch(void)
957 CLEAR_BIT(FLASH
->ACR
, FLASH_ACR_PRFTEN
);
961 * @brief Check if Prefetch buffer is enabled
962 * @rmtoll FLASH_ACR PRFTEN LL_FLASH_IsPrefetchEnabled
963 * @retval State of bit (1 or 0).
965 __STATIC_INLINE
uint32_t LL_FLASH_IsPrefetchEnabled(void)
967 return (READ_BIT(FLASH
->ACR
, FLASH_ACR_PRFTEN
) == (FLASH_ACR_PRFTEN
));
973 * @brief Enable ART Accelerator
974 * @rmtoll FLASH_ACR ARTEN LL_FLASH_EnableART
977 __STATIC_INLINE
void LL_FLASH_EnableART(void)
979 SET_BIT(FLASH
->ACR
, FLASH_ACR_ARTEN
);
983 * @brief Disable ART Accelerator
984 * @rmtoll FLASH_ACR ARTEN LL_FLASH_DisableART
987 __STATIC_INLINE
void LL_FLASH_DisableART(void)
989 CLEAR_BIT(FLASH
->ACR
, FLASH_ACR_ARTEN
);
993 * @brief Enable ART Reset
994 * @rmtoll FLASH_ACR ARTRST LL_FLASH_EnableARTReset
997 __STATIC_INLINE
void LL_FLASH_EnableARTReset(void)
999 SET_BIT(FLASH
->ACR
, FLASH_ACR_ARTRST
);
1003 * @brief Disable ART Reset
1004 * @rmtoll FLASH_ACR ARTRST LL_FLASH_DisableARTReset
1007 __STATIC_INLINE
void LL_FLASH_DisableARTReset(void)
1009 CLEAR_BIT(FLASH
->ACR
, FLASH_ACR_ARTRST
);
1024 #endif /* defined (FLASH) || defined (SYSCFG) || defined (DBGMCU) */
1034 #endif /* __STM32F7xx_LL_SYSTEM_H */
1036 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/