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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Inc / stm32f7xx_ll_tim.h
blob476a2154babf83677487f06ba71805e735b28098
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_tim.h
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief Header file of TIM LL module.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37
38 /* Define to prevent recursive inclusion -------------------------------------*/
39 #ifndef __STM32F7xx_LL_TIM_H
40 #define __STM32F7xx_LL_TIM_H
41
42 #ifdef __cplusplus
43 extern "C" {
44 #endif
45
46 /* Includes ------------------------------------------------------------------*/
47 #include "stm32f7xx.h"
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) || defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
54
55 /** @defgroup TIM_LL TIM
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /** @defgroup TIM_LL_Private_Variables TIM Private Variables
62 * @{
63 */
64 static const uint8_t OFFSET_TAB_CCMRx[] =
65 {
66 0x00U, /* 0: TIMx_CH1 */
67 0x00U, /* 1: TIMx_CH1N */
68 0x00U, /* 2: TIMx_CH2 */
69 0x00U, /* 3: TIMx_CH2N */
70 0x04U, /* 4: TIMx_CH3 */
71 0x04U, /* 5: TIMx_CH3N */
72 0x04U, /* 6: TIMx_CH4 */
73 0x3CU, /* 7: TIMx_CH5 */
74 0x3CU /* 8: TIMx_CH6 */
75 };
76
77 static const uint8_t SHIFT_TAB_OCxx[] =
78 {
79 0U, /* 0: OC1M, OC1FE, OC1PE */
80 0U, /* 1: - NA */
81 8U, /* 2: OC2M, OC2FE, OC2PE */
82 0U, /* 3: - NA */
83 0U, /* 4: OC3M, OC3FE, OC3PE */
84 0U, /* 5: - NA */
85 8U, /* 6: OC4M, OC4FE, OC4PE */
86 0U, /* 7: OC5M, OC5FE, OC5PE */
87 8U /* 8: OC6M, OC6FE, OC6PE */
88 };
89
90 static const uint8_t SHIFT_TAB_ICxx[] =
91 {
92 0U, /* 0: CC1S, IC1PSC, IC1F */
93 0U, /* 1: - NA */
94 8U, /* 2: CC2S, IC2PSC, IC2F */
95 0U, /* 3: - NA */
96 0U, /* 4: CC3S, IC3PSC, IC3F */
97 0U, /* 5: - NA */
98 8U, /* 6: CC4S, IC4PSC, IC4F */
99 0U, /* 7: - NA */
100 0U /* 8: - NA */
101 };
102
103 static const uint8_t SHIFT_TAB_CCxP[] =
104 {
105 0U, /* 0: CC1P */
106 2U, /* 1: CC1NP */
107 4U, /* 2: CC2P */
108 6U, /* 3: CC2NP */
109 8U, /* 4: CC3P */
110 10U, /* 5: CC3NP */
111 12U, /* 6: CC4P */
112 16U, /* 7: CC5P */
113 20U /* 8: CC6P */
114 };
115
116 static const uint8_t SHIFT_TAB_OISx[] =
117 {
118 0U, /* 0: OIS1 */
119 1U, /* 1: OIS1N */
120 2U, /* 2: OIS2 */
121 3U, /* 3: OIS2N */
122 4U, /* 4: OIS3 */
123 5U, /* 5: OIS3N */
124 6U, /* 6: OIS4 */
125 8U, /* 7: OIS5 */
126 10U /* 8: OIS6 */
127 };
128 /**
129 * @}
130 */
131
132
133 /* Private constants ---------------------------------------------------------*/
134 /** @defgroup TIM_LL_Private_Constants TIM Private Constants
135 * @{
136 */
137
138 #if defined(TIM_BREAK_INPUT_SUPPORT)
139 /* Defines used for the bit position in the register and perform offsets */
140 #define TIM_POSITION_BRK_SOURCE POSITION_VAL(Source)
141
142 /* Generic bit definitions for TIMx_AF1 register */
143 #define TIMx_AF1_BKINE TIM1_AF1_BKINE /*!< BRK BKINE input enable */
144 #if defined(DFSDM1_Channel0)
145 #define TIMx_AF1_BKDFBKE TIM1_AF1_BKDFBKE /*!< BRK DFSDM1_BREAK[0] enable */
146 #endif /* DFSDM1_Channel0 */
147 #define TIMx_AF1_BKINP TIM1_AF1_BKINP /*!< BRK BKIN input polarity */
148 /* Generic bit definitions for TIMx_AF2 register */
149 #define TIMx_AF2_BK2INE TIM1_AF2_BK2INE /*!< BRK B2KINE input enable */
150 #if defined(DFSDM1_Channel0)
151 #define TIMx_AF2_BK2DFBKE TIM1_AF2_BK2DFBKE /*!< BRK DFSDM_BREAK[0] enable */
152 #endif /* DFSDM1_Channel0 */
153 #define TIMx_AF2_BK2INP TIM1_AF2_BK2INP /*!< BRK BK2IN input polarity */
154 #endif /* TIM_BREAK_INPUT_SUPPORT */
155
156 /* Remap mask definitions */
157 #define TIMx_OR_RMP_SHIFT 16U
158 #define TIMx_OR_RMP_MASK 0x0000FFFFU
159 #define TIM2_OR_RMP_MASK (TIM2_OR_ITR1_RMP << TIMx_OR_RMP_SHIFT)
160 #define TIM5_OR_RMP_MASK (TIM5_OR_TI4_RMP << TIMx_OR_RMP_SHIFT)
161 #define TIM11_OR_RMP_MASK (TIM11_OR_TI1_RMP << TIMx_OR_RMP_SHIFT)
162
163 /* Mask used to set the TDG[x:0] of the DTG bits of the TIMx_BDTR register */
164 #define DT_DELAY_1 ((uint8_t)0x7FU)
165 #define DT_DELAY_2 ((uint8_t)0x3FU)
166 #define DT_DELAY_3 ((uint8_t)0x1FU)
167 #define DT_DELAY_4 ((uint8_t)0x1FU)
168
169 /* Mask used to set the DTG[7:5] bits of the DTG bits of the TIMx_BDTR register */
170 #define DT_RANGE_1 ((uint8_t)0x00U)
171 #define DT_RANGE_2 ((uint8_t)0x80U)
172 #define DT_RANGE_3 ((uint8_t)0xC0U)
173 #define DT_RANGE_4 ((uint8_t)0xE0U)
174
175
176 /**
177 * @}
178 */
179
180 /* Private macros ------------------------------------------------------------*/
181 /** @defgroup TIM_LL_Private_Macros TIM Private Macros
182 * @{
183 */
184 /** @brief Convert channel id into channel index.
185 * @param __CHANNEL__ This parameter can be one of the following values:
186 * @arg @ref LL_TIM_CHANNEL_CH1
187 * @arg @ref LL_TIM_CHANNEL_CH1N
188 * @arg @ref LL_TIM_CHANNEL_CH2
189 * @arg @ref LL_TIM_CHANNEL_CH2N
190 * @arg @ref LL_TIM_CHANNEL_CH3
191 * @arg @ref LL_TIM_CHANNEL_CH3N
192 * @arg @ref LL_TIM_CHANNEL_CH4
193 * @arg @ref LL_TIM_CHANNEL_CH5
194 * @arg @ref LL_TIM_CHANNEL_CH6
195 * @retval none
196 */
197 #define TIM_GET_CHANNEL_INDEX( __CHANNEL__) \
198 (((__CHANNEL__) == LL_TIM_CHANNEL_CH1) ? 0U :\
199 ((__CHANNEL__) == LL_TIM_CHANNEL_CH1N) ? 1U :\
200 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2) ? 2U :\
201 ((__CHANNEL__) == LL_TIM_CHANNEL_CH2N) ? 3U :\
202 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3) ? 4U :\
203 ((__CHANNEL__) == LL_TIM_CHANNEL_CH3N) ? 5U :\
204 ((__CHANNEL__) == LL_TIM_CHANNEL_CH4) ? 6U :\
205 ((__CHANNEL__) == LL_TIM_CHANNEL_CH5) ? 7U : 8U)
206
207 /** @brief Calculate the deadtime sampling period(in ps).
208 * @param __TIMCLK__ timer input clock frequency (in Hz).
209 * @param __CKD__ This parameter can be one of the following values:
210 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
211 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
212 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
213 * @retval none
214 */
215 #define TIM_CALC_DTS(__TIMCLK__, __CKD__) \
216 (((__CKD__) == LL_TIM_CLOCKDIVISION_DIV1) ? ((uint64_t)1000000000000U/(__TIMCLK__)) : \
217 ((__CKD__) == LL_TIM_CLOCKDIVISION_DIV2) ? ((uint64_t)1000000000000U/((__TIMCLK__) >> 1U)) : \
218 ((uint64_t)1000000000000U/((__TIMCLK__) >> 2U)))
219 /**
220 * @}
221 */
222
223
224 /* Exported types ------------------------------------------------------------*/
225 #if defined(USE_FULL_LL_DRIVER)
226 /** @defgroup TIM_LL_ES_INIT TIM Exported Init structure
227 * @{
228 */
229
230 /**
231 * @brief TIM Time Base configuration structure definition.
232 */
233 typedef struct
234 {
235 uint16_t Prescaler; /*!< Specifies the prescaler value used to divide the TIM clock.
236 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
237
238 This feature can be modified afterwards using unitary function @ref LL_TIM_SetPrescaler().*/
239
240 uint32_t CounterMode; /*!< Specifies the counter mode.
241 This parameter can be a value of @ref TIM_LL_EC_COUNTERMODE.
242
243 This feature can be modified afterwards using unitary function @ref LL_TIM_SetCounterMode().*/
244
245 uint32_t Autoreload; /*!< Specifies the auto reload value to be loaded into the active
246 Auto-Reload Register at the next update event.
247 This parameter must be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
248 Some timer instances may support 32 bits counters. In that case this parameter must be a number between 0x0000 and 0xFFFFFFFF.
249
250 This feature can be modified afterwards using unitary function @ref LL_TIM_SetAutoReload().*/
251
252 uint32_t ClockDivision; /*!< Specifies the clock division.
253 This parameter can be a value of @ref TIM_LL_EC_CLOCKDIVISION.
254
255 This feature can be modified afterwards using unitary function @ref LL_TIM_SetClockDivision().*/
256
257 uint8_t RepetitionCounter; /*!< Specifies the repetition counter value. Each time the RCR downcounter
258 reaches zero, an update event is generated and counting restarts
259 from the RCR value (N).
260 This means in PWM mode that (N+1) corresponds to:
261 - the number of PWM periods in edge-aligned mode
262 - the number of half PWM period in center-aligned mode
263 This parameter must be a number between 0x00 and 0xFF.
264
265 This feature can be modified afterwards using unitary function @ref LL_TIM_SetRepetitionCounter().*/
266 } LL_TIM_InitTypeDef;
267
268 /**
269 * @brief TIM Output Compare configuration structure definition.
270 */
271 typedef struct
272 {
273 uint32_t OCMode; /*!< Specifies the output mode.
274 This parameter can be a value of @ref TIM_LL_EC_OCMODE.
275
276 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetMode().*/
277
278 uint32_t OCState; /*!< Specifies the TIM Output Compare state.
279 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
280
281 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
282
283 uint32_t OCNState; /*!< Specifies the TIM complementary Output Compare state.
284 This parameter can be a value of @ref TIM_LL_EC_OCSTATE.
285
286 This feature can be modified afterwards using unitary functions @ref LL_TIM_CC_EnableChannel() or @ref LL_TIM_CC_DisableChannel().*/
287
288 uint32_t CompareValue; /*!< Specifies the Compare value to be loaded into the Capture Compare Register.
289 This parameter can be a number between Min_Data=0x0000 and Max_Data=0xFFFF.
290
291 This feature can be modified afterwards using unitary function LL_TIM_OC_SetCompareCHx (x=1..6).*/
292
293 uint32_t OCPolarity; /*!< Specifies the output polarity.
294 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
295
296 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
297
298 uint32_t OCNPolarity; /*!< Specifies the complementary output polarity.
299 This parameter can be a value of @ref TIM_LL_EC_OCPOLARITY.
300
301 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetPolarity().*/
302
303
304 uint32_t OCIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
305 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
306
307 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
308
309 uint32_t OCNIdleState; /*!< Specifies the TIM Output Compare pin state during Idle state.
310 This parameter can be a value of @ref TIM_LL_EC_OCIDLESTATE.
311
312 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetIdleState().*/
313 } LL_TIM_OC_InitTypeDef;
314
315 /**
316 * @brief TIM Input Capture configuration structure definition.
317 */
318
319 typedef struct
320 {
321
322 uint32_t ICPolarity; /*!< Specifies the active edge of the input signal.
323 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
324
325 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
326
327 uint32_t ICActiveInput; /*!< Specifies the input.
328 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
329
330 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
331
332 uint32_t ICPrescaler; /*!< Specifies the Input Capture Prescaler.
333 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
334
335 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
336
337 uint32_t ICFilter; /*!< Specifies the input capture filter.
338 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
339
340 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
341 } LL_TIM_IC_InitTypeDef;
342
343
344 /**
345 * @brief TIM Encoder interface configuration structure definition.
346 */
347 typedef struct
348 {
349 uint32_t EncoderMode; /*!< Specifies the encoder resolution (x2 or x4).
350 This parameter can be a value of @ref TIM_LL_EC_ENCODERMODE.
351
352 This feature can be modified afterwards using unitary function @ref LL_TIM_SetEncoderMode().*/
353
354 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
355 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
356
357 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
358
359 uint32_t IC1ActiveInput; /*!< Specifies the TI1 input source
360 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
361
362 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
363
364 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
365 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
366
367 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
368
369 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
370 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
371
372 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
373
374 uint32_t IC2Polarity; /*!< Specifies the active edge of TI2 input.
375 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
376
377 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
378
379 uint32_t IC2ActiveInput; /*!< Specifies the TI2 input source
380 This parameter can be a value of @ref TIM_LL_EC_ACTIVEINPUT.
381
382 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetActiveInput().*/
383
384 uint32_t IC2Prescaler; /*!< Specifies the TI2 input prescaler value.
385 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
386
387 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
388
389 uint32_t IC2Filter; /*!< Specifies the TI2 input filter.
390 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
391
392 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
393
394 } LL_TIM_ENCODER_InitTypeDef;
395
396 /**
397 * @brief TIM Hall sensor interface configuration structure definition.
398 */
399 typedef struct
400 {
401
402 uint32_t IC1Polarity; /*!< Specifies the active edge of TI1 input.
403 This parameter can be a value of @ref TIM_LL_EC_IC_POLARITY.
404
405 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPolarity().*/
406
407 uint32_t IC1Prescaler; /*!< Specifies the TI1 input prescaler value.
408 Prescaler must be set to get a maximum counter period longer than the
409 time interval between 2 consecutive changes on the Hall inputs.
410 This parameter can be a value of @ref TIM_LL_EC_ICPSC.
411
412 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetPrescaler().*/
413
414 uint32_t IC1Filter; /*!< Specifies the TI1 input filter.
415 This parameter can be a value of @ref TIM_LL_EC_IC_FILTER.
416
417 This feature can be modified afterwards using unitary function @ref LL_TIM_IC_SetFilter().*/
418
419 uint32_t CommutationDelay; /*!< Specifies the compare value to be loaded into the Capture Compare Register.
420 A positive pulse (TRGO event) is generated with a programmable delay every time
421 a change occurs on the Hall inputs.
422 This parameter can be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
423
424 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetCompareCH2().*/
425 } LL_TIM_HALLSENSOR_InitTypeDef;
426
427 /**
428 * @brief BDTR (Break and Dead Time) structure definition
429 */
430 typedef struct
431 {
432 uint32_t OSSRState; /*!< Specifies the Off-State selection used in Run mode.
433 This parameter can be a value of @ref TIM_LL_EC_OSSR
434
435 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
436
437 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
438
439 uint32_t OSSIState; /*!< Specifies the Off-State used in Idle state.
440 This parameter can be a value of @ref TIM_LL_EC_OSSI
441
442 This feature can be modified afterwards using unitary function @ref LL_TIM_SetOffStates()
443
444 @note This bit-field cannot be modified as long as LOCK level 2 has been programmed. */
445
446 uint32_t LockLevel; /*!< Specifies the LOCK level parameters.
447 This parameter can be a value of @ref TIM_LL_EC_LOCKLEVEL
448
449 @note The LOCK bits can be written only once after the reset. Once the TIMx_BDTR register
450 has been written, their content is frozen until the next reset.*/
451
452 uint8_t DeadTime; /*!< Specifies the delay time between the switching-off and the
453 switching-on of the outputs.
454 This parameter can be a number between Min_Data = 0x00 and Max_Data = 0xFF.
455
456 This feature can be modified afterwards using unitary function @ref LL_TIM_OC_SetDeadTime()
457
458 @note This bit-field can not be modified as long as LOCK level 1, 2 or 3 has been programmed. */
459
460 uint16_t BreakState; /*!< Specifies whether the TIM Break input is enabled or not.
461 This parameter can be a value of @ref TIM_LL_EC_BREAK_ENABLE
462
463 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK() or @ref LL_TIM_DisableBRK()
464
465 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
466
467 uint32_t BreakPolarity; /*!< Specifies the TIM Break Input pin polarity.
468 This parameter can be a value of @ref TIM_LL_EC_BREAK_POLARITY
469
470 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
471
472 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
473
474 uint32_t BreakFilter; /*!< Specifies the TIM Break Filter.
475 This parameter can be a value of @ref TIM_LL_EC_BREAK_FILTER
476
477 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK()
478
479 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
480
481 uint32_t Break2State; /*!< Specifies whether the TIM Break2 input is enabled or not.
482 This parameter can be a value of @ref TIM_LL_EC_BREAK2_ENABLE
483
484 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableBRK2() or @ref LL_TIM_DisableBRK2()
485
486 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
487
488 uint32_t Break2Polarity; /*!< Specifies the TIM Break2 Input pin polarity.
489 This parameter can be a value of @ref TIM_LL_EC_BREAK2_POLARITY
490
491 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
492
493 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
494
495 uint32_t Break2Filter; /*!< Specifies the TIM Break2 Filter.
496 This parameter can be a value of @ref TIM_LL_EC_BREAK2_FILTER
497
498 This feature can be modified afterwards using unitary function @ref LL_TIM_ConfigBRK2()
499
500 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
501
502 uint32_t AutomaticOutput; /*!< Specifies whether the TIM Automatic Output feature is enabled or not.
503 This parameter can be a value of @ref TIM_LL_EC_AUTOMATICOUTPUT_ENABLE
504
505 This feature can be modified afterwards using unitary functions @ref LL_TIM_EnableAutomaticOutput() or @ref LL_TIM_DisableAutomaticOutput()
506
507 @note This bit-field can not be modified as long as LOCK level 1 has been programmed. */
508 } LL_TIM_BDTR_InitTypeDef;
509
510 /**
511 * @}
512 */
513 #endif /* USE_FULL_LL_DRIVER */
514
515 /* Exported constants --------------------------------------------------------*/
516 /** @defgroup TIM_LL_Exported_Constants TIM Exported Constants
517 * @{
518 */
519
520 /** @defgroup TIM_LL_EC_GET_FLAG Get Flags Defines
521 * @brief Flags defines which can be used with LL_TIM_ReadReg function.
522 * @{
523 */
524 #define LL_TIM_SR_UIF TIM_SR_UIF /*!< Update interrupt flag */
525 #define LL_TIM_SR_CC1IF TIM_SR_CC1IF /*!< Capture/compare 1 interrupt flag */
526 #define LL_TIM_SR_CC2IF TIM_SR_CC2IF /*!< Capture/compare 2 interrupt flag */
527 #define LL_TIM_SR_CC3IF TIM_SR_CC3IF /*!< Capture/compare 3 interrupt flag */
528 #define LL_TIM_SR_CC4IF TIM_SR_CC4IF /*!< Capture/compare 4 interrupt flag */
529 #define LL_TIM_SR_CC5IF TIM_SR_CC5IF /*!< Capture/compare 5 interrupt flag */
530 #define LL_TIM_SR_CC6IF TIM_SR_CC6IF /*!< Capture/compare 6 interrupt flag */
531 #define LL_TIM_SR_COMIF TIM_SR_COMIF /*!< COM interrupt flag */
532 #define LL_TIM_SR_TIF TIM_SR_TIF /*!< Trigger interrupt flag */
533 #define LL_TIM_SR_BIF TIM_SR_BIF /*!< Break interrupt flag */
534 #define LL_TIM_SR_B2IF TIM_SR_B2IF /*!< Second break interrupt flag */
535 #define LL_TIM_SR_CC1OF TIM_SR_CC1OF /*!< Capture/Compare 1 overcapture flag */
536 #define LL_TIM_SR_CC2OF TIM_SR_CC2OF /*!< Capture/Compare 2 overcapture flag */
537 #define LL_TIM_SR_CC3OF TIM_SR_CC3OF /*!< Capture/Compare 3 overcapture flag */
538 #define LL_TIM_SR_CC4OF TIM_SR_CC4OF /*!< Capture/Compare 4 overcapture flag */
539 #define LL_TIM_SR_SBIF TIM_SR_SBIF /*!< System Break interrupt flag */
540 /**
541 * @}
542 */
543
544 #if defined(USE_FULL_LL_DRIVER)
545 /** @defgroup TIM_LL_EC_BREAK_ENABLE Break Enable
546 * @{
547 */
548 #define LL_TIM_BREAK_DISABLE 0x00000000U /*!< Break function disabled */
549 #define LL_TIM_BREAK_ENABLE TIM_BDTR_BKE /*!< Break function enabled */
550 /**
551 * @}
552 */
553
554 /** @defgroup TIM_LL_EC_BREAK2_ENABLE Break2 Enable
555 * @{
556 */
557 #define LL_TIM_BREAK2_DISABLE 0x00000000U /*!< Break2 function disabled */
558 #define LL_TIM_BREAK2_ENABLE TIM_BDTR_BK2E /*!< Break2 function enabled */
559 /**
560 * @}
561 */
562
563 /** @defgroup TIM_LL_EC_AUTOMATICOUTPUT_ENABLE Automatic output enable
564 * @{
565 */
566 #define LL_TIM_AUTOMATICOUTPUT_DISABLE 0x00000000U /*!< MOE can be set only by software */
567 #define LL_TIM_AUTOMATICOUTPUT_ENABLE TIM_BDTR_AOE /*!< MOE can be set by software or automatically at the next update event */
568 /**
569 * @}
570 */
571 #endif /* USE_FULL_LL_DRIVER */
572
573 /** @defgroup TIM_LL_EC_IT IT Defines
574 * @brief IT defines which can be used with LL_TIM_ReadReg and LL_TIM_WriteReg functions.
575 * @{
576 */
577 #define LL_TIM_DIER_UIE TIM_DIER_UIE /*!< Update interrupt enable */
578 #define LL_TIM_DIER_CC1IE TIM_DIER_CC1IE /*!< Capture/compare 1 interrupt enable */
579 #define LL_TIM_DIER_CC2IE TIM_DIER_CC2IE /*!< Capture/compare 2 interrupt enable */
580 #define LL_TIM_DIER_CC3IE TIM_DIER_CC3IE /*!< Capture/compare 3 interrupt enable */
581 #define LL_TIM_DIER_CC4IE TIM_DIER_CC4IE /*!< Capture/compare 4 interrupt enable */
582 #define LL_TIM_DIER_COMIE TIM_DIER_COMIE /*!< COM interrupt enable */
583 #define LL_TIM_DIER_TIE TIM_DIER_TIE /*!< Trigger interrupt enable */
584 #define LL_TIM_DIER_BIE TIM_DIER_BIE /*!< Break interrupt enable */
585 /**
586 * @}
587 */
588
589 /** @defgroup TIM_LL_EC_UPDATESOURCE Update Source
590 * @{
591 */
592 #define LL_TIM_UPDATESOURCE_REGULAR 0x00000000U /*!< Counter overflow/underflow, Setting the UG bit or Update generation through the slave mode controller generates an update request */
593 #define LL_TIM_UPDATESOURCE_COUNTER TIM_CR1_URS /*!< Only counter overflow/underflow generates an update request */
594 /**
595 * @}
596 */
597
598 /** @defgroup TIM_LL_EC_ONEPULSEMODE One Pulse Mode
599 * @{
600 */
601 #define LL_TIM_ONEPULSEMODE_SINGLE TIM_CR1_OPM /*!< Counter is not stopped at update event */
602 #define LL_TIM_ONEPULSEMODE_REPETITIVE 0x00000000U /*!< Counter stops counting at the next update event */
603 /**
604 * @}
605 */
606
607 /** @defgroup TIM_LL_EC_COUNTERMODE Counter Mode
608 * @{
609 */
610 #define LL_TIM_COUNTERMODE_UP 0x00000000U /*!<Counter used as upcounter */
611 #define LL_TIM_COUNTERMODE_DOWN TIM_CR1_DIR /*!< Counter used as downcounter */
612 #define LL_TIM_COUNTERMODE_CENTER_UP TIM_CR1_CMS_0 /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting down. */
613 #define LL_TIM_COUNTERMODE_CENTER_DOWN TIM_CR1_CMS_1 /*!<The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up */
614 #define LL_TIM_COUNTERMODE_CENTER_UP_DOWN TIM_CR1_CMS /*!< The counter counts up and down alternatively. Output compare interrupt flags of output channels are set only when the counter is counting up or down. */
615 /**
616 * @}
617 */
618
619 /** @defgroup TIM_LL_EC_CLOCKDIVISION Clock Division
620 * @{
621 */
622 #define LL_TIM_CLOCKDIVISION_DIV1 0x00000000U /*!< tDTS=tCK_INT */
623 #define LL_TIM_CLOCKDIVISION_DIV2 TIM_CR1_CKD_0 /*!< tDTS=2*tCK_INT */
624 #define LL_TIM_CLOCKDIVISION_DIV4 TIM_CR1_CKD_1 /*!< tDTS=4*tCK_INT */
625 /**
626 * @}
627 */
628
629 /** @defgroup TIM_LL_EC_COUNTERDIRECTION Counter Direction
630 * @{
631 */
632 #define LL_TIM_COUNTERDIRECTION_UP 0x00000000U /*!< Timer counter counts up */
633 #define LL_TIM_COUNTERDIRECTION_DOWN TIM_CR1_DIR /*!< Timer counter counts down */
634 /**
635 * @}
636 */
637
638 /** @defgroup TIM_LL_EC_CCUPDATESOURCE Capture Compare Update Source
639 * @{
640 */
641 #define LL_TIM_CCUPDATESOURCE_COMG_ONLY 0x00000000U /*!< Capture/compare control bits are updated by setting the COMG bit only */
642 #define LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI TIM_CR2_CCUS /*!< Capture/compare control bits are updated by setting the COMG bit or when a rising edge occurs on trigger input (TRGI) */
643 /**
644 * @}
645 */
646
647 /** @defgroup TIM_LL_EC_CCDMAREQUEST Capture Compare DMA Request
648 * @{
649 */
650 #define LL_TIM_CCDMAREQUEST_CC 0x00000000U /*!< CCx DMA request sent when CCx event occurs */
651 #define LL_TIM_CCDMAREQUEST_UPDATE TIM_CR2_CCDS /*!< CCx DMA requests sent when update event occurs */
652 /**
653 * @}
654 */
655
656 /** @defgroup TIM_LL_EC_LOCKLEVEL Lock Level
657 * @{
658 */
659 #define LL_TIM_LOCKLEVEL_OFF 0x00000000U /*!< LOCK OFF - No bit is write protected */
660 #define LL_TIM_LOCKLEVEL_1 TIM_BDTR_LOCK_0 /*!< LOCK Level 1 */
661 #define LL_TIM_LOCKLEVEL_2 TIM_BDTR_LOCK_1 /*!< LOCK Level 2 */
662 #define LL_TIM_LOCKLEVEL_3 TIM_BDTR_LOCK /*!< LOCK Level 3 */
663 /**
664 * @}
665 */
666
667 /** @defgroup TIM_LL_EC_CHANNEL Channel
668 * @{
669 */
670 #define LL_TIM_CHANNEL_CH1 TIM_CCER_CC1E /*!< Timer input/output channel 1 */
671 #define LL_TIM_CHANNEL_CH1N TIM_CCER_CC1NE /*!< Timer complementary output channel 1 */
672 #define LL_TIM_CHANNEL_CH2 TIM_CCER_CC2E /*!< Timer input/output channel 2 */
673 #define LL_TIM_CHANNEL_CH2N TIM_CCER_CC2NE /*!< Timer complementary output channel 2 */
674 #define LL_TIM_CHANNEL_CH3 TIM_CCER_CC3E /*!< Timer input/output channel 3 */
675 #define LL_TIM_CHANNEL_CH3N TIM_CCER_CC3NE /*!< Timer complementary output channel 3 */
676 #define LL_TIM_CHANNEL_CH4 TIM_CCER_CC4E /*!< Timer input/output channel 4 */
677 #define LL_TIM_CHANNEL_CH5 TIM_CCER_CC5E /*!< Timer output channel 5 */
678 #define LL_TIM_CHANNEL_CH6 TIM_CCER_CC6E /*!< Timer output channel 6 */
679 /**
680 * @}
681 */
682
683 #if defined(USE_FULL_LL_DRIVER)
684 /** @defgroup TIM_LL_EC_OCSTATE Output Configuration State
685 * @{
686 */
687 #define LL_TIM_OCSTATE_DISABLE 0x00000000U /*!< OCx is not active */
688 #define LL_TIM_OCSTATE_ENABLE TIM_CCER_CC1E /*!< OCx signal is output on the corresponding output pin */
689 /**
690 * @}
691 */
692 #endif /* USE_FULL_LL_DRIVER */
693
694 /** @defgroup TIM_LL_EC_OCMODE Output Configuration Mode
695 * @{
696 */
697 #define LL_TIM_OCMODE_FROZEN 0x00000000U /*!<The comparison between the output compare register TIMx_CCRy and the counter TIMx_CNT has no effect on the output channel level */
698 #define LL_TIM_OCMODE_ACTIVE TIM_CCMR1_OC1M_0 /*!<OCyREF is forced high on compare match*/
699 #define LL_TIM_OCMODE_INACTIVE TIM_CCMR1_OC1M_1 /*!<OCyREF is forced low on compare match*/
700 #define LL_TIM_OCMODE_TOGGLE (TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<OCyREF toggles on compare match*/
701 #define LL_TIM_OCMODE_FORCED_INACTIVE TIM_CCMR1_OC1M_2 /*!<OCyREF is forced low*/
702 #define LL_TIM_OCMODE_FORCED_ACTIVE (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_0) /*!<OCyREF is forced high*/
703 #define LL_TIM_OCMODE_PWM1 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1) /*!<In upcounting, channel y is active as long as TIMx_CNT<TIMx_CCRy else inactive. In downcounting, channel y is inactive as long as TIMx_CNT>TIMx_CCRy else active.*/
704 #define LL_TIM_OCMODE_PWM2 (TIM_CCMR1_OC1M_2 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_0) /*!<In upcounting, channel y is inactive as long as TIMx_CNT<TIMx_CCRy else active. In downcounting, channel y is active as long as TIMx_CNT>TIMx_CCRy else inactive*/
705 #define LL_TIM_OCMODE_RETRIG_OPM1 TIM_CCMR1_OC1M_3 /*!<Retrigerrable OPM mode 1*/
706 #define LL_TIM_OCMODE_RETRIG_OPM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0) /*!<Retrigerrable OPM mode 2*/
707 #define LL_TIM_OCMODE_COMBINED_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 1*/
708 #define LL_TIM_OCMODE_COMBINED_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_0 | TIM_CCMR1_OC1M_2) /*!<Combined PWM mode 2*/
709 #define LL_TIM_OCMODE_ASSYMETRIC_PWM1 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M_1 | TIM_CCMR1_OC1M_2) /*!<Asymmetric PWM mode 1*/
710 #define LL_TIM_OCMODE_ASSYMETRIC_PWM2 (TIM_CCMR1_OC1M_3 | TIM_CCMR1_OC1M) /*!<Asymmetric PWM mode 2*/
711 /**
712 * @}
713 */
714
715 /** @defgroup TIM_LL_EC_OCPOLARITY Output Configuration Polarity
716 * @{
717 */
718 #define LL_TIM_OCPOLARITY_HIGH 0x00000000U /*!< OCxactive high*/
719 #define LL_TIM_OCPOLARITY_LOW TIM_CCER_CC1P /*!< OCxactive low*/
720 /**
721 * @}
722 */
723
724 /** @defgroup TIM_LL_EC_OCIDLESTATE Output Configuration Idle State
725 * @{
726 */
727 #define LL_TIM_OCIDLESTATE_LOW 0x00000000U /*!<OCx=0 (after a dead-time if OC is implemented) when MOE=0*/
728 #define LL_TIM_OCIDLESTATE_HIGH TIM_CR2_OIS1 /*!<OCx=1 (after a dead-time if OC is implemented) when MOE=0*/
729 /**
730 * @}
731 */
732
733 /** @defgroup TIM_LL_EC_GROUPCH5 GROUPCH5
734 * @{
735 */
736 #define LL_TIM_GROUPCH5_NONE 0x00000000U /*!< No effect of OC5REF on OC1REFC, OC2REFC and OC3REFC */
737 #define LL_TIM_GROUPCH5_OC1REFC TIM_CCR5_GC5C1 /*!< OC1REFC is the logical AND of OC1REFC and OC5REF */
738 #define LL_TIM_GROUPCH5_OC2REFC TIM_CCR5_GC5C2 /*!< OC2REFC is the logical AND of OC2REFC and OC5REF */
739 #define LL_TIM_GROUPCH5_OC3REFC TIM_CCR5_GC5C3 /*!< OC3REFC is the logical AND of OC3REFC and OC5REF */
740 /**
741 * @}
742 */
743
744 /** @defgroup TIM_LL_EC_ACTIVEINPUT Active Input Selection
745 * @{
746 */
747 #define LL_TIM_ACTIVEINPUT_DIRECTTI (TIM_CCMR1_CC1S_0 << 16U) /*!< ICx is mapped on TIx */
748 #define LL_TIM_ACTIVEINPUT_INDIRECTTI (TIM_CCMR1_CC1S_1 << 16U) /*!< ICx is mapped on TIy */
749 #define LL_TIM_ACTIVEINPUT_TRC (TIM_CCMR1_CC1S << 16U) /*!< ICx is mapped on TRC */
750 /**
751 * @}
752 */
753
754 /** @defgroup TIM_LL_EC_ICPSC Input Configuration Prescaler
755 * @{
756 */
757 #define LL_TIM_ICPSC_DIV1 0x00000000U /*!< No prescaler, capture is done each time an edge is detected on the capture input */
758 #define LL_TIM_ICPSC_DIV2 (TIM_CCMR1_IC1PSC_0 << 16U) /*!< Capture is done once every 2 events */
759 #define LL_TIM_ICPSC_DIV4 (TIM_CCMR1_IC1PSC_1 << 16U) /*!< Capture is done once every 4 events */
760 #define LL_TIM_ICPSC_DIV8 (TIM_CCMR1_IC1PSC << 16U) /*!< Capture is done once every 8 events */
761 /**
762 * @}
763 */
764
765 /** @defgroup TIM_LL_EC_IC_FILTER Input Configuration Filter
766 * @{
767 */
768 #define LL_TIM_IC_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
769 #define LL_TIM_IC_FILTER_FDIV1_N2 (TIM_CCMR1_IC1F_0 << 16U) /*!< fSAMPLING=fCK_INT, N=2 */
770 #define LL_TIM_IC_FILTER_FDIV1_N4 (TIM_CCMR1_IC1F_1 << 16U) /*!< fSAMPLING=fCK_INT, N=4 */
771 #define LL_TIM_IC_FILTER_FDIV1_N8 ((TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fCK_INT, N=8 */
772 #define LL_TIM_IC_FILTER_FDIV2_N6 (TIM_CCMR1_IC1F_2 << 16U) /*!< fSAMPLING=fDTS/2, N=6 */
773 #define LL_TIM_IC_FILTER_FDIV2_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/2, N=8 */
774 #define LL_TIM_IC_FILTER_FDIV4_N6 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/4, N=6 */
775 #define LL_TIM_IC_FILTER_FDIV4_N8 ((TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/4, N=8 */
776 #define LL_TIM_IC_FILTER_FDIV8_N6 (TIM_CCMR1_IC1F_3 << 16U) /*!< fSAMPLING=fDTS/8, N=6 */
777 #define LL_TIM_IC_FILTER_FDIV8_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/8, N=8 */
778 #define LL_TIM_IC_FILTER_FDIV16_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/16, N=5 */
779 #define LL_TIM_IC_FILTER_FDIV16_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_1 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/16, N=6 */
780 #define LL_TIM_IC_FILTER_FDIV16_N8 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2) << 16U) /*!< fSAMPLING=fDTS/16, N=8 */
781 #define LL_TIM_IC_FILTER_FDIV32_N5 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_0) << 16U) /*!< fSAMPLING=fDTS/32, N=5 */
782 #define LL_TIM_IC_FILTER_FDIV32_N6 ((TIM_CCMR1_IC1F_3 | TIM_CCMR1_IC1F_2 | TIM_CCMR1_IC1F_1) << 16U) /*!< fSAMPLING=fDTS/32, N=6 */
783 #define LL_TIM_IC_FILTER_FDIV32_N8 (TIM_CCMR1_IC1F << 16U) /*!< fSAMPLING=fDTS/32, N=8 */
784 /**
785 * @}
786 */
787
788 /** @defgroup TIM_LL_EC_IC_POLARITY Input Configuration Polarity
789 * @{
790 */
791 #define LL_TIM_IC_POLARITY_RISING 0x00000000U /*!< The circuit is sensitive to TIxFP1 rising edge, TIxFP1 is not inverted */
792 #define LL_TIM_IC_POLARITY_FALLING TIM_CCER_CC1P /*!< The circuit is sensitive to TIxFP1 falling edge, TIxFP1 is inverted */
793 #define LL_TIM_IC_POLARITY_BOTHEDGE (TIM_CCER_CC1P | TIM_CCER_CC1NP) /*!< The circuit is sensitive to both TIxFP1 rising and falling edges, TIxFP1 is not inverted */
794 /**
795 * @}
796 */
797
798 /** @defgroup TIM_LL_EC_CLOCKSOURCE Clock Source
799 * @{
800 */
801 #define LL_TIM_CLOCKSOURCE_INTERNAL 0x00000000U /*!< The timer is clocked by the internal clock provided from the RCC */
802 #define LL_TIM_CLOCKSOURCE_EXT_MODE1 (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Counter counts at each rising or falling edge on a selected inpu t*/
803 #define LL_TIM_CLOCKSOURCE_EXT_MODE2 TIM_SMCR_ECE /*!< Counter counts at each rising or falling edge on the external trigger input ETR */
804 /**
805 * @}
806 */
807
808 /** @defgroup TIM_LL_EC_ENCODERMODE Encoder Mode
809 * @{
810 */
811 #define LL_TIM_ENCODERMODE_X2_TI1 TIM_SMCR_SMS_0 /*!< Encoder mode 1 - Counter counts up/down on TI2FP2 edge depending on TI1FP1 level */
812 #define LL_TIM_ENCODERMODE_X2_TI2 TIM_SMCR_SMS_1 /*!< Encoder mode 2 - Counter counts up/down on TI1FP1 edge depending on TI2FP2 level */
813 #define LL_TIM_ENCODERMODE_X4_TI12 (TIM_SMCR_SMS_1 | TIM_SMCR_SMS_0) /*!< Encoder mode 3 - Counter counts up/down on both TI1FP1 and TI2FP2 edges depending on the level of the other input l */
814 /**
815 * @}
816 */
817
818 /** @defgroup TIM_LL_EC_TRGO Trigger Output
819 * @{
820 */
821 #define LL_TIM_TRGO_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output */
822 #define LL_TIM_TRGO_ENABLE TIM_CR2_MMS_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output */
823 #define LL_TIM_TRGO_UPDATE TIM_CR2_MMS_1 /*!< Update event is used as trigger output */
824 #define LL_TIM_TRGO_CC1IF (TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< CC1 capture or a compare match is used as trigger output */
825 #define LL_TIM_TRGO_OC1REF TIM_CR2_MMS_2 /*!< OC1REF signal is used as trigger output */
826 #define LL_TIM_TRGO_OC2REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_0) /*!< OC2REF signal is used as trigger output */
827 #define LL_TIM_TRGO_OC3REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1) /*!< OC3REF signal is used as trigger output */
828 #define LL_TIM_TRGO_OC4REF (TIM_CR2_MMS_2 | TIM_CR2_MMS_1 | TIM_CR2_MMS_0) /*!< OC4REF signal is used as trigger output */
829 /**
830 * @}
831 */
832
833 /** @defgroup TIM_LL_EC_TRGO2 Trigger Output 2
834 * @{
835 */
836 #define LL_TIM_TRGO2_RESET 0x00000000U /*!< UG bit from the TIMx_EGR register is used as trigger output 2 */
837 #define LL_TIM_TRGO2_ENABLE TIM_CR2_MMS2_0 /*!< Counter Enable signal (CNT_EN) is used as trigger output 2 */
838 #define LL_TIM_TRGO2_UPDATE TIM_CR2_MMS2_1 /*!< Update event is used as trigger output 2 */
839 #define LL_TIM_TRGO2_CC1F (TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< CC1 capture or a compare match is used as trigger output 2 */
840 #define LL_TIM_TRGO2_OC1 TIM_CR2_MMS2_2 /*!< OC1REF signal is used as trigger output 2 */
841 #define LL_TIM_TRGO2_OC2 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC2REF signal is used as trigger output 2 */
842 #define LL_TIM_TRGO2_OC3 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1) /*!< OC3REF signal is used as trigger output 2 */
843 #define LL_TIM_TRGO2_OC4 (TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC4REF signal is used as trigger output 2 */
844 #define LL_TIM_TRGO2_OC5 TIM_CR2_MMS2_3 /*!< OC5REF signal is used as trigger output 2 */
845 #define LL_TIM_TRGO2_OC6 (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_0) /*!< OC6REF signal is used as trigger output 2 */
846 #define LL_TIM_TRGO2_OC4_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1) /*!< OC4REF rising or falling edges are used as trigger output 2 */
847 #define LL_TIM_TRGO2_OC6_RISINGFALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC6REF rising or falling edges are used as trigger output 2 */
848 #define LL_TIM_TRGO2_OC4_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2) /*!< OC4REF or OC6REF rising edges are used as trigger output 2 */
849 #define LL_TIM_TRGO2_OC4_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_0) /*!< OC4REF rising or OC6REF falling edges are used as trigger output 2 */
850 #define LL_TIM_TRGO2_OC5_RISING_OC6_RISING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 |TIM_CR2_MMS2_1) /*!< OC5REF or OC6REF rising edges are used as trigger output 2 */
851 #define LL_TIM_TRGO2_OC5_RISING_OC6_FALLING (TIM_CR2_MMS2_3 | TIM_CR2_MMS2_2 | TIM_CR2_MMS2_1 | TIM_CR2_MMS2_0) /*!< OC5REF rising or OC6REF falling edges are used as trigger output 2 */
852 /**
853 * @}
854 */
855
856 /** @defgroup TIM_LL_EC_SLAVEMODE Slave Mode
857 * @{
858 */
859 #define LL_TIM_SLAVEMODE_DISABLED 0x00000000U /*!< Slave mode disabled */
860 #define LL_TIM_SLAVEMODE_RESET TIM_SMCR_SMS_2 /*!< Reset Mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter */
861 #define LL_TIM_SLAVEMODE_GATED (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_0) /*!< Gated Mode - The counter clock is enabled when the trigger input (TRGI) is high */
862 #define LL_TIM_SLAVEMODE_TRIGGER (TIM_SMCR_SMS_2 | TIM_SMCR_SMS_1) /*!< Trigger Mode - The counter starts at a rising edge of the trigger TRGI */
863 #define LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER TIM_SMCR_SMS_3 /*!< Combined reset + trigger mode - Rising edge of the selected trigger input (TRGI) reinitializes the counter, generates an update of the registers and starts the counter */
864 /**
865 * @}
866 */
867
868 /** @defgroup TIM_LL_EC_TS Trigger Selection
869 * @{
870 */
871 #define LL_TIM_TS_ITR0 0x00000000U /*!< Internal Trigger 0 (ITR0) is used as trigger input */
872 #define LL_TIM_TS_ITR1 TIM_SMCR_TS_0 /*!< Internal Trigger 1 (ITR1) is used as trigger input */
873 #define LL_TIM_TS_ITR2 TIM_SMCR_TS_1 /*!< Internal Trigger 2 (ITR2) is used as trigger input */
874 #define LL_TIM_TS_ITR3 (TIM_SMCR_TS_0 | TIM_SMCR_TS_1) /*!< Internal Trigger 3 (ITR3) is used as trigger input */
875 #define LL_TIM_TS_TI1F_ED TIM_SMCR_TS_2 /*!< TI1 Edge Detector (TI1F_ED) is used as trigger input */
876 #define LL_TIM_TS_TI1FP1 (TIM_SMCR_TS_2 | TIM_SMCR_TS_0) /*!< Filtered Timer Input 1 (TI1FP1) is used as trigger input */
877 #define LL_TIM_TS_TI2FP2 (TIM_SMCR_TS_2 | TIM_SMCR_TS_1) /*!< Filtered Timer Input 2 (TI12P2) is used as trigger input */
878 #define LL_TIM_TS_ETRF (TIM_SMCR_TS_2 | TIM_SMCR_TS_1 | TIM_SMCR_TS_0) /*!< Filtered external Trigger (ETRF) is used as trigger input */
879 /**
880 * @}
881 */
882
883 /** @defgroup TIM_LL_EC_ETR_POLARITY External Trigger Polarity
884 * @{
885 */
886 #define LL_TIM_ETR_POLARITY_NONINVERTED 0x00000000U /*!< ETR is non-inverted, active at high level or rising edge */
887 #define LL_TIM_ETR_POLARITY_INVERTED TIM_SMCR_ETP /*!< ETR is inverted, active at low level or falling edge */
888 /**
889 * @}
890 */
891
892 /** @defgroup TIM_LL_EC_ETR_PRESCALER External Trigger Prescaler
893 * @{
894 */
895 #define LL_TIM_ETR_PRESCALER_DIV1 0x00000000U /*!< ETR prescaler OFF */
896 #define LL_TIM_ETR_PRESCALER_DIV2 TIM_SMCR_ETPS_0 /*!< ETR frequency is divided by 2 */
897 #define LL_TIM_ETR_PRESCALER_DIV4 TIM_SMCR_ETPS_1 /*!< ETR frequency is divided by 4 */
898 #define LL_TIM_ETR_PRESCALER_DIV8 TIM_SMCR_ETPS /*!< ETR frequency is divided by 8 */
899 /**
900 * @}
901 */
902
903 /** @defgroup TIM_LL_EC_ETR_FILTER External Trigger Filter
904 * @{
905 */
906 #define LL_TIM_ETR_FILTER_FDIV1 0x00000000U /*!< No filter, sampling is done at fDTS */
907 #define LL_TIM_ETR_FILTER_FDIV1_N2 TIM_SMCR_ETF_0 /*!< fSAMPLING=fCK_INT, N=2 */
908 #define LL_TIM_ETR_FILTER_FDIV1_N4 TIM_SMCR_ETF_1 /*!< fSAMPLING=fCK_INT, N=4 */
909 #define LL_TIM_ETR_FILTER_FDIV1_N8 (TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fCK_INT, N=8 */
910 #define LL_TIM_ETR_FILTER_FDIV2_N6 TIM_SMCR_ETF_2 /*!< fSAMPLING=fDTS/2, N=6 */
911 #define LL_TIM_ETR_FILTER_FDIV2_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/2, N=8 */
912 #define LL_TIM_ETR_FILTER_FDIV4_N6 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/4, N=6 */
913 #define LL_TIM_ETR_FILTER_FDIV4_N8 (TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/4, N=8 */
914 #define LL_TIM_ETR_FILTER_FDIV8_N6 TIM_SMCR_ETF_3 /*!< fSAMPLING=fDTS/8, N=8 */
915 #define LL_TIM_ETR_FILTER_FDIV8_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=5 */
916 #define LL_TIM_ETR_FILTER_FDIV16_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/16, N=6 */
917 #define LL_TIM_ETR_FILTER_FDIV16_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_1 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/16, N=8 */
918 #define LL_TIM_ETR_FILTER_FDIV16_N8 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2) /*!< fSAMPLING=fDTS/16, N=5 */
919 #define LL_TIM_ETR_FILTER_FDIV32_N5 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_0) /*!< fSAMPLING=fDTS/32, N=5 */
920 #define LL_TIM_ETR_FILTER_FDIV32_N6 (TIM_SMCR_ETF_3 | TIM_SMCR_ETF_2 | TIM_SMCR_ETF_1) /*!< fSAMPLING=fDTS/32, N=6 */
921 #define LL_TIM_ETR_FILTER_FDIV32_N8 TIM_SMCR_ETF /*!< fSAMPLING=fDTS/32, N=8 */
922 /**
923 * @}
924 */
925
926
927 /** @defgroup TIM_LL_EC_BREAK_POLARITY break polarity
928 * @{
929 */
930 #define LL_TIM_BREAK_POLARITY_LOW 0x00000000U /*!< Break input BRK is active low */
931 #define LL_TIM_BREAK_POLARITY_HIGH TIM_BDTR_BKP /*!< Break input BRK is active high */
932 /**
933 * @}
934 */
935
936 /** @defgroup TIM_LL_EC_BREAK_FILTER break filter
937 * @{
938 */
939 #define LL_TIM_BREAK_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
940 #define LL_TIM_BREAK_FILTER_FDIV1_N2 0x00010000U /*!< fSAMPLING=fCK_INT, N=2 */
941 #define LL_TIM_BREAK_FILTER_FDIV1_N4 0x00020000U /*!< fSAMPLING=fCK_INT, N=4 */
942 #define LL_TIM_BREAK_FILTER_FDIV1_N8 0x00030000U /*!< fSAMPLING=fCK_INT, N=8 */
943 #define LL_TIM_BREAK_FILTER_FDIV2_N6 0x00040000U /*!< fSAMPLING=fDTS/2, N=6 */
944 #define LL_TIM_BREAK_FILTER_FDIV2_N8 0x00050000U /*!< fSAMPLING=fDTS/2, N=8 */
945 #define LL_TIM_BREAK_FILTER_FDIV4_N6 0x00060000U /*!< fSAMPLING=fDTS/4, N=6 */
946 #define LL_TIM_BREAK_FILTER_FDIV4_N8 0x00070000U /*!< fSAMPLING=fDTS/4, N=8 */
947 #define LL_TIM_BREAK_FILTER_FDIV8_N6 0x00080000U /*!< fSAMPLING=fDTS/8, N=6 */
948 #define LL_TIM_BREAK_FILTER_FDIV8_N8 0x00090000U /*!< fSAMPLING=fDTS/8, N=8 */
949 #define LL_TIM_BREAK_FILTER_FDIV16_N5 0x000A0000U /*!< fSAMPLING=fDTS/16, N=5 */
950 #define LL_TIM_BREAK_FILTER_FDIV16_N6 0x000B0000U /*!< fSAMPLING=fDTS/16, N=6 */
951 #define LL_TIM_BREAK_FILTER_FDIV16_N8 0x000C0000U /*!< fSAMPLING=fDTS/16, N=8 */
952 #define LL_TIM_BREAK_FILTER_FDIV32_N5 0x000D0000U /*!< fSAMPLING=fDTS/32, N=5 */
953 #define LL_TIM_BREAK_FILTER_FDIV32_N6 0x000E0000U /*!< fSAMPLING=fDTS/32, N=6 */
954 #define LL_TIM_BREAK_FILTER_FDIV32_N8 0x000F0000U /*!< fSAMPLING=fDTS/32, N=8 */
955 /**
956 * @}
957 */
958
959 /** @defgroup TIM_LL_EC_BREAK2_POLARITY BREAK2 POLARITY
960 * @{
961 */
962 #define LL_TIM_BREAK2_POLARITY_LOW 0x00000000U /*!< Break input BRK2 is active low */
963 #define LL_TIM_BREAK2_POLARITY_HIGH TIM_BDTR_BK2P /*!< Break input BRK2 is active high */
964 /**
965 * @}
966 */
967
968 /** @defgroup TIM_LL_EC_BREAK2_FILTER BREAK2 FILTER
969 * @{
970 */
971 #define LL_TIM_BREAK2_FILTER_FDIV1 0x00000000U /*!< No filter, BRK acts asynchronously */
972 #define LL_TIM_BREAK2_FILTER_FDIV1_N2 0x00100000U /*!< fSAMPLING=fCK_INT, N=2 */
973 #define LL_TIM_BREAK2_FILTER_FDIV1_N4 0x00200000U /*!< fSAMPLING=fCK_INT, N=4 */
974 #define LL_TIM_BREAK2_FILTER_FDIV1_N8 0x00300000U /*!< fSAMPLING=fCK_INT, N=8 */
975 #define LL_TIM_BREAK2_FILTER_FDIV2_N6 0x00400000U /*!< fSAMPLING=fDTS/2, N=6 */
976 #define LL_TIM_BREAK2_FILTER_FDIV2_N8 0x00500000U /*!< fSAMPLING=fDTS/2, N=8 */
977 #define LL_TIM_BREAK2_FILTER_FDIV4_N6 0x00600000U /*!< fSAMPLING=fDTS/4, N=6 */
978 #define LL_TIM_BREAK2_FILTER_FDIV4_N8 0x00700000U /*!< fSAMPLING=fDTS/4, N=8 */
979 #define LL_TIM_BREAK2_FILTER_FDIV8_N6 0x00800000U /*!< fSAMPLING=fDTS/8, N=6 */
980 #define LL_TIM_BREAK2_FILTER_FDIV8_N8 0x00900000U /*!< fSAMPLING=fDTS/8, N=8 */
981 #define LL_TIM_BREAK2_FILTER_FDIV16_N5 0x00A00000U /*!< fSAMPLING=fDTS/16, N=5 */
982 #define LL_TIM_BREAK2_FILTER_FDIV16_N6 0x00B00000U /*!< fSAMPLING=fDTS/16, N=6 */
983 #define LL_TIM_BREAK2_FILTER_FDIV16_N8 0x00C00000U /*!< fSAMPLING=fDTS/16, N=8 */
984 #define LL_TIM_BREAK2_FILTER_FDIV32_N5 0x00D00000U /*!< fSAMPLING=fDTS/32, N=5 */
985 #define LL_TIM_BREAK2_FILTER_FDIV32_N6 0x00E00000U /*!< fSAMPLING=fDTS/32, N=6 */
986 #define LL_TIM_BREAK2_FILTER_FDIV32_N8 0x00F00000U /*!< fSAMPLING=fDTS/32, N=8 */
987 /**
988 * @}
989 */
990
991 /** @defgroup TIM_LL_EC_OSSI OSSI
992 * @{
993 */
994 #define LL_TIM_OSSI_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
995 #define LL_TIM_OSSI_ENABLE TIM_BDTR_OSSI /*!< When inactive, OxC/OCxN outputs are first forced with their inactive level then forced to their idle level after the deadtime */
996 /**
997 * @}
998 */
999
1000 /** @defgroup TIM_LL_EC_OSSR OSSR
1001 * @{
1002 */
1003 #define LL_TIM_OSSR_DISABLE 0x00000000U /*!< When inactive, OCx/OCxN outputs are disabled */
1004 #define LL_TIM_OSSR_ENABLE TIM_BDTR_OSSR /*!< When inactive, OC/OCN outputs are enabled with their inactive level as soon as CCxE=1 or CCxNE=1 */
1005 /**
1006 * @}
1007 */
1008
1009 #if defined(TIM_BREAK_INPUT_SUPPORT)
1010 /** @defgroup TIM_LL_EC_BREAK_INPUT BREAK INPUT
1011 * @{
1012 */
1013 #define LL_TIM_BREAK_INPUT_BKIN 0x00000000U /*!< TIMx_BKIN input */
1014 #define LL_TIM_BREAK_INPUT_BKIN2 0x00000004U /*!< TIMx_BKIN2 input */
1015 /**
1016 * @}
1017 */
1018
1019 /** @defgroup TIM_LL_EC_BKIN_SOURCE BKIN SOURCE
1020 * @{
1021 */
1022 #define LL_TIM_BKIN_SOURCE_BKIN TIM1_AF1_BKINE /*!< BKIN input from AF controller */
1023 #define LL_TIM_BKIN_SOURCE_DF1BK TIM1_AF1_BKDF1BKE /*!< internal signal: DFSDM1 break output */
1024 /**
1025 * @}
1026 */
1027
1028 /** @defgroup TIM_LL_EC_BKIN_POLARITY BKIN POLARITY
1029 * @{
1030 */
1031 #define LL_TIM_BKIN_POLARITY_LOW TIM1_AF1_BKINP /*!< BRK BKIN input is active low */
1032 #define LL_TIM_BKIN_POLARITY_HIGH 0x00000000U /*!< BRK BKIN input is active high */
1033 /**
1034 * @}
1035 */
1036 #endif /* TIM_BREAK_INPUT_SUPPORT */
1037
1038 /** @defgroup TIM_LL_EC_DMABURST_BASEADDR DMA Burst Base Address
1039 * @{
1040 */
1041 #define LL_TIM_DMABURST_BASEADDR_CR1 0x00000000U /*!< TIMx_CR1 register is the DMA base address for DMA burst */
1042 #define LL_TIM_DMABURST_BASEADDR_CR2 TIM_DCR_DBA_0 /*!< TIMx_CR2 register is the DMA base address for DMA burst */
1043 #define LL_TIM_DMABURST_BASEADDR_SMCR TIM_DCR_DBA_1 /*!< TIMx_SMCR register is the DMA base address for DMA burst */
1044 #define LL_TIM_DMABURST_BASEADDR_DIER (TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_DIER register is the DMA base address for DMA burst */
1045 #define LL_TIM_DMABURST_BASEADDR_SR TIM_DCR_DBA_2 /*!< TIMx_SR register is the DMA base address for DMA burst */
1046 #define LL_TIM_DMABURST_BASEADDR_EGR (TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_EGR register is the DMA base address for DMA burst */
1047 #define LL_TIM_DMABURST_BASEADDR_CCMR1 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCMR1 register is the DMA base address for DMA burst */
1048 #define LL_TIM_DMABURST_BASEADDR_CCMR2 (TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCMR2 register is the DMA base address for DMA burst */
1049 #define LL_TIM_DMABURST_BASEADDR_CCER TIM_DCR_DBA_3 /*!< TIMx_CCER register is the DMA base address for DMA burst */
1050 #define LL_TIM_DMABURST_BASEADDR_CNT (TIM_DCR_DBA_3 | TIM_DCR_DBA_0) /*!< TIMx_CNT register is the DMA base address for DMA burst */
1051 #define LL_TIM_DMABURST_BASEADDR_PSC (TIM_DCR_DBA_3 | TIM_DCR_DBA_1) /*!< TIMx_PSC register is the DMA base address for DMA burst */
1052 #define LL_TIM_DMABURST_BASEADDR_ARR (TIM_DCR_DBA_3 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_ARR register is the DMA base address for DMA burst */
1053 #define LL_TIM_DMABURST_BASEADDR_RCR (TIM_DCR_DBA_3 | TIM_DCR_DBA_2) /*!< TIMx_RCR register is the DMA base address for DMA burst */
1054 #define LL_TIM_DMABURST_BASEADDR_CCR1 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_CCR1 register is the DMA base address for DMA burst */
1055 #define LL_TIM_DMABURST_BASEADDR_CCR2 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_CCR2 register is the DMA base address for DMA burst */
1056 #define LL_TIM_DMABURST_BASEADDR_CCR3 (TIM_DCR_DBA_3 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR3 register is the DMA base address for DMA burst */
1057 #define LL_TIM_DMABURST_BASEADDR_CCR4 TIM_DCR_DBA_4 /*!< TIMx_CCR4 register is the DMA base address for DMA burst */
1058 #define LL_TIM_DMABURST_BASEADDR_BDTR (TIM_DCR_DBA_4 | TIM_DCR_DBA_0) /*!< TIMx_BDTR register is the DMA base address for DMA burst */
1059 #define LL_TIM_DMABURST_BASEADDR_CCMR3 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1) /*!< TIMx_CCMR3 register is the DMA base address for DMA burst */
1060 #define LL_TIM_DMABURST_BASEADDR_CCR5 (TIM_DCR_DBA_4 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_CCR5 register is the DMA base address for DMA burst */
1061 #define LL_TIM_DMABURST_BASEADDR_CCR6 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2) /*!< TIMx_CCR6 register is the DMA base address for DMA burst */
1062 #define LL_TIM_DMABURST_BASEADDR_OR (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_0) /*!< TIMx_OR register is the DMA base address for DMA burst */
1063 #define LL_TIM_DMABURST_BASEADDR_AF1 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1) /*!< TIMx_AF1 register is the DMA base address for DMA burst */
1064 #define LL_TIM_DMABURST_BASEADDR_AF2 (TIM_DCR_DBA_4 | TIM_DCR_DBA_2 | TIM_DCR_DBA_1 | TIM_DCR_DBA_0) /*!< TIMx_AF2 register is the DMA base address for DMA burst */
1065
1066 /**
1067 * @}
1068 */
1069
1070 /** @defgroup TIM_LL_EC_DMABURST_LENGTH DMA Burst Length
1071 * @{
1072 */
1073 #define LL_TIM_DMABURST_LENGTH_1TRANSFER 0x00000000U /*!< Transfer is done to 1 register starting from the DMA burst base address */
1074 #define LL_TIM_DMABURST_LENGTH_2TRANSFERS TIM_DCR_DBL_0 /*!< Transfer is done to 2 registers starting from the DMA burst base address */
1075 #define LL_TIM_DMABURST_LENGTH_3TRANSFERS TIM_DCR_DBL_1 /*!< Transfer is done to 3 registers starting from the DMA burst base address */
1076 #define LL_TIM_DMABURST_LENGTH_4TRANSFERS (TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 4 registers starting from the DMA burst base address */
1077 #define LL_TIM_DMABURST_LENGTH_5TRANSFERS TIM_DCR_DBL_2 /*!< Transfer is done to 5 registers starting from the DMA burst base address */
1078 #define LL_TIM_DMABURST_LENGTH_6TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 6 registers starting from the DMA burst base address */
1079 #define LL_TIM_DMABURST_LENGTH_7TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 7 registers starting from the DMA burst base address */
1080 #define LL_TIM_DMABURST_LENGTH_8TRANSFERS (TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 1 registers starting from the DMA burst base address */
1081 #define LL_TIM_DMABURST_LENGTH_9TRANSFERS TIM_DCR_DBL_3 /*!< Transfer is done to 9 registers starting from the DMA burst base address */
1082 #define LL_TIM_DMABURST_LENGTH_10TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_0) /*!< Transfer is done to 10 registers starting from the DMA burst base address */
1083 #define LL_TIM_DMABURST_LENGTH_11TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1) /*!< Transfer is done to 11 registers starting from the DMA burst base address */
1084 #define LL_TIM_DMABURST_LENGTH_12TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 12 registers starting from the DMA burst base address */
1085 #define LL_TIM_DMABURST_LENGTH_13TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2) /*!< Transfer is done to 13 registers starting from the DMA burst base address */
1086 #define LL_TIM_DMABURST_LENGTH_14TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_0) /*!< Transfer is done to 14 registers starting from the DMA burst base address */
1087 #define LL_TIM_DMABURST_LENGTH_15TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1) /*!< Transfer is done to 15 registers starting from the DMA burst base address */
1088 #define LL_TIM_DMABURST_LENGTH_16TRANSFERS (TIM_DCR_DBL_3 | TIM_DCR_DBL_2 | TIM_DCR_DBL_1 | TIM_DCR_DBL_0) /*!< Transfer is done to 16 registers starting from the DMA burst base address */
1089 #define LL_TIM_DMABURST_LENGTH_17TRANSFERS TIM_DCR_DBL_4 /*!< Transfer is done to 17 registers starting from the DMA burst base address */
1090 #define LL_TIM_DMABURST_LENGTH_18TRANSFERS (TIM_DCR_DBL_4 | TIM_DCR_DBL_0) /*!< Transfer is done to 18 registers starting from the DMA burst base address */
1091 /**
1092 * @}
1093 */
1094
1095
1096 /** @defgroup TIM_LL_EC_TIM2_ITR1_RMP_TIM8 TIM2 Internal Trigger1 Remap TIM8
1097 * @{
1098 */
1099 #define LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO TIM2_OR_RMP_MASK /*!< TIM2_ITR1 is connected to TIM8_TRGO */
1100 #define LL_TIM_TIM2_ITR1_RMP_ETH_PTP (TIM2_OR_ITR1_RMP_0 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to ETH_PTP */
1101 #define LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF (TIM2_OR_ITR1_RMP_1 | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_FS SOF */
1102 #define LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF (TIM2_OR_ITR1_RMP | TIM2_OR_RMP_MASK) /*!< TIM2_ITR1 is connected to OTG_HS SOF */
1103 /**
1104 * @}
1105 */
1106
1107 /** @defgroup TIM_LL_EC_TIM5_TI4_RMP TIM5 External Input Ch4 Remap
1108 * @{
1109 */
1110 #define LL_TIM_TIM5_TI4_RMP_GPIO TIM5_OR_RMP_MASK /*!< TIM5 channel 4 is connected to GPIO */
1111 #define LL_TIM_TIM5_TI4_RMP_LSI (TIM5_OR_TI4_RMP_0 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSI internal clock */
1112 #define LL_TIM_TIM5_TI4_RMP_LSE (TIM5_OR_TI4_RMP_1 | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to LSE */
1113 #define LL_TIM_TIM5_TI4_RMP_RTC (TIM5_OR_TI4_RMP | TIM5_OR_RMP_MASK) /*!< TIM5 channel 4 is connected to RTC wakeup interrupt */
1114 /**
1115 * @}
1116 */
1117
1118 /** @defgroup TIM_LL_EC_TIM11_TI1_RMP TIM11 External Input Capture 1 Remap
1119 * @{
1120 */
1121 #define LL_TIM_TIM11_TI1_RMP_GPIO TIM11_OR_RMP_MASK /*!< TIM11 channel 1 is connected to GPIO */
1122 #define LL_TIM_TIM11_TI1_RMP_SPDIFRX (TIM11_OR_TI1_RMP_0 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to SPDIFRX */
1123 #define LL_TIM_TIM11_TI1_RMP_HSE (TIM11_OR_TI1_RMP_1 | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to HSE */
1124 #define LL_TIM_TIM11_TI1_RMP_MCO1 (TIM11_OR_TI1_RMP | TIM11_OR_RMP_MASK) /*!< TIM11 channel 1 is connected to MCO1 */
1125 /**
1126 * @}
1127 */
1128
1129 /**
1130 * @}
1131 */
1132
1133
1134 /**
1135 * @}
1136 */
1137
1138 /* Exported macro ------------------------------------------------------------*/
1139 /** @defgroup TIM_LL_Exported_Macros TIM Exported Macros
1140 * @{
1141 */
1142
1143 /** @defgroup TIM_LL_EM_WRITE_READ Common Write and read registers Macros
1144 * @{
1145 */
1146 /**
1147 * @brief Write a value in TIM register.
1148 * @param __INSTANCE__ TIM Instance
1149 * @param __REG__ Register to be written
1150 * @param __VALUE__ Value to be written in the register
1151 * @retval None
1152 */
1153 #define LL_TIM_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
1154
1155 /**
1156 * @brief Read a value in TIM register.
1157 * @param __INSTANCE__ TIM Instance
1158 * @param __REG__ Register to be read
1159 * @retval Register value
1160 */
1161 #define LL_TIM_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
1162 /**
1163 * @}
1164 */
1165
1166 /** @defgroup TIM_LL_EM_Exported_Macros Exported_Macros
1167 * @{
1168 */
1169 /**
1170 * @brief HELPER macro retrieving the UIFCPY flag from the counter value.
1171 * @note ex: @ref __LL_TIM_GETFLAG_UIFCPY (@ref LL_TIM_GetCounter ());
1172 * @note Relevant only if UIF flag remapping has been enabled (UIF status bit is copied
1173 * to TIMx_CNT register bit 31)
1174 * @param __CNT__ Counter value
1175 * @retval UIF status bit
1176 */
1177 #define __LL_TIM_GETFLAG_UIFCPY(__CNT__) \
1178 (READ_BIT((__CNT__), TIM_CNT_UIFCPY) >> TIM_CNT_UIFCPY_Pos)
1179
1180 /**
1181 * @brief HELPER macro calculating DTG[0:7] in the TIMx_BDTR register to achieve the requested dead time duration.
1182 * @note ex: @ref __LL_TIM_CALC_DEADTIME (80000000, @ref LL_TIM_GetClockDivision (), 120);
1183 * @param __TIMCLK__ timer input clock frequency (in Hz)
1184 * @param __CKD__ This parameter can be one of the following values:
1185 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1186 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1187 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1188 * @param __DT__ deadtime duration (in ns)
1189 * @retval DTG[0:7]
1190 */
1191 #define __LL_TIM_CALC_DEADTIME(__TIMCLK__, __CKD__, __DT__) \
1192 ( (((uint64_t)((__DT__)*1000U)) < ((DT_DELAY_1+1U) * TIM_CALC_DTS((__TIMCLK__), (__CKD__)))) ? (uint8_t)(((uint64_t)((__DT__)*1000U) / TIM_CALC_DTS((__TIMCLK__), (__CKD__))) & DT_DELAY_1) : \
1193 (((uint64_t)((__DT__)*1000U)) < (64U + (DT_DELAY_2+1U)) * 2U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_2 | ((uint8_t)((uint8_t)((((uint64_t)((__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 1U) - (uint8_t) 64U) & DT_DELAY_2)) :\
1194 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_3+1U)) * 8U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_3 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 3U) - (uint8_t) 32U) & DT_DELAY_3)) :\
1195 (((uint64_t)((__DT__)*1000U)) < (32U + (DT_DELAY_4+1U)) * 16U * TIM_CALC_DTS((__TIMCLK__), (__CKD__))) ? (uint8_t)(DT_RANGE_4 | ((uint8_t)((uint8_t)(((((uint64_t)(__DT__)*1000U))/ TIM_CALC_DTS((__TIMCLK__), (__CKD__))) >> 4U) - (uint8_t) 32U) & DT_DELAY_4)) :\
1196 0U)
1197
1198 /**
1199 * @brief HELPER macro calculating the prescaler value to achieve the required counter clock frequency.
1200 * @note ex: @ref __LL_TIM_CALC_PSC (80000000, 1000000);
1201 * @param __TIMCLK__ timer input clock frequency (in Hz)
1202 * @param __CNTCLK__ counter clock frequency (in Hz)
1203 * @retval Prescaler value (between Min_Data=0 and Max_Data=65535)
1204 */
1205 #define __LL_TIM_CALC_PSC(__TIMCLK__, __CNTCLK__) \
1206 ((__TIMCLK__) >= (__CNTCLK__)) ? (uint32_t)((__TIMCLK__)/(__CNTCLK__) - 1U) : 0U
1207
1208 /**
1209 * @brief HELPER macro calculating the auto-reload value to achieve the required output signal frequency.
1210 * @note ex: @ref __LL_TIM_CALC_ARR (1000000, @ref LL_TIM_GetPrescaler (), 10000);
1211 * @param __TIMCLK__ timer input clock frequency (in Hz)
1212 * @param __PSC__ prescaler
1213 * @param __FREQ__ output signal frequency (in Hz)
1214 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1215 */
1216 #define __LL_TIM_CALC_ARR(__TIMCLK__, __PSC__, __FREQ__) \
1217 (((__TIMCLK__)/((__PSC__) + 1U)) >= (__FREQ__)) ? ((__TIMCLK__)/((__FREQ__) * ((__PSC__) + 1U)) - 1U) : 0U
1218
1219 /**
1220 * @brief HELPER macro calculating the compare value required to achieve the required timer output compare active/inactive delay.
1221 * @note ex: @ref __LL_TIM_CALC_DELAY (1000000, @ref LL_TIM_GetPrescaler (), 10);
1222 * @param __TIMCLK__ timer input clock frequency (in Hz)
1223 * @param __PSC__ prescaler
1224 * @param __DELAY__ timer output compare active/inactive delay (in us)
1225 * @retval Compare value (between Min_Data=0 and Max_Data=65535)
1226 */
1227 #define __LL_TIM_CALC_DELAY(__TIMCLK__, __PSC__, __DELAY__) \
1228 ((uint32_t)(((uint64_t)(__TIMCLK__) * (uint64_t)(__DELAY__)) \
1229 / ((uint64_t)1000000U * (uint64_t)((__PSC__) + 1U))))
1230
1231 /**
1232 * @brief HELPER macro calculating the auto-reload value to achieve the required pulse duration (when the timer operates in one pulse mode).
1233 * @note ex: @ref __LL_TIM_CALC_PULSE (1000000, @ref LL_TIM_GetPrescaler (), 10, 20);
1234 * @param __TIMCLK__ timer input clock frequency (in Hz)
1235 * @param __PSC__ prescaler
1236 * @param __DELAY__ timer output compare active/inactive delay (in us)
1237 * @param __PULSE__ pulse duration (in us)
1238 * @retval Auto-reload value (between Min_Data=0 and Max_Data=65535)
1239 */
1240 #define __LL_TIM_CALC_PULSE(__TIMCLK__, __PSC__, __DELAY__, __PULSE__) \
1241 ((uint32_t)(__LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__PULSE__)) \
1242 + __LL_TIM_CALC_DELAY((__TIMCLK__), (__PSC__), (__DELAY__))))
1243
1244 /**
1245 * @brief HELPER macro retrieving the ratio of the input capture prescaler
1246 * @note ex: @ref __LL_TIM_GET_ICPSC_RATIO (@ref LL_TIM_IC_GetPrescaler ());
1247 * @param __ICPSC__ This parameter can be one of the following values:
1248 * @arg @ref LL_TIM_ICPSC_DIV1
1249 * @arg @ref LL_TIM_ICPSC_DIV2
1250 * @arg @ref LL_TIM_ICPSC_DIV4
1251 * @arg @ref LL_TIM_ICPSC_DIV8
1252 * @retval Input capture prescaler ratio (1, 2, 4 or 8)
1253 */
1254 #define __LL_TIM_GET_ICPSC_RATIO(__ICPSC__) \
1255 ((uint32_t)(0x01U << (((__ICPSC__) >> 16U) >> TIM_CCMR1_IC1PSC_Pos)))
1256
1257
1258 /**
1259 * @}
1260 */
1261
1262
1263 /**
1264 * @}
1265 */
1266
1267 /* Exported functions --------------------------------------------------------*/
1268 /** @defgroup TIM_LL_Exported_Functions TIM Exported Functions
1269 * @{
1270 */
1271
1272 /** @defgroup TIM_LL_EF_Time_Base Time Base configuration
1273 * @{
1274 */
1275 /**
1276 * @brief Enable timer counter.
1277 * @rmtoll CR1 CEN LL_TIM_EnableCounter
1278 * @param TIMx Timer instance
1279 * @retval None
1280 */
1281 __STATIC_INLINE void LL_TIM_EnableCounter(TIM_TypeDef *TIMx)
1282 {
1283 SET_BIT(TIMx->CR1, TIM_CR1_CEN);
1284 }
1285
1286 /**
1287 * @brief Disable timer counter.
1288 * @rmtoll CR1 CEN LL_TIM_DisableCounter
1289 * @param TIMx Timer instance
1290 * @retval None
1291 */
1292 __STATIC_INLINE void LL_TIM_DisableCounter(TIM_TypeDef *TIMx)
1293 {
1294 CLEAR_BIT(TIMx->CR1, TIM_CR1_CEN);
1295 }
1296
1297 /**
1298 * @brief Indicates whether the timer counter is enabled.
1299 * @rmtoll CR1 CEN LL_TIM_IsEnabledCounter
1300 * @param TIMx Timer instance
1301 * @retval State of bit (1 or 0).
1302 */
1303 __STATIC_INLINE uint32_t LL_TIM_IsEnabledCounter(TIM_TypeDef *TIMx)
1304 {
1305 return (READ_BIT(TIMx->CR1, TIM_CR1_CEN) == (TIM_CR1_CEN));
1306 }
1307
1308 /**
1309 * @brief Enable update event generation.
1310 * @rmtoll CR1 UDIS LL_TIM_EnableUpdateEvent
1311 * @param TIMx Timer instance
1312 * @retval None
1313 */
1314 __STATIC_INLINE void LL_TIM_EnableUpdateEvent(TIM_TypeDef *TIMx)
1315 {
1316 SET_BIT(TIMx->CR1, TIM_CR1_UDIS);
1317 }
1318
1319 /**
1320 * @brief Disable update event generation.
1321 * @rmtoll CR1 UDIS LL_TIM_DisableUpdateEvent
1322 * @param TIMx Timer instance
1323 * @retval None
1324 */
1325 __STATIC_INLINE void LL_TIM_DisableUpdateEvent(TIM_TypeDef *TIMx)
1326 {
1327 CLEAR_BIT(TIMx->CR1, TIM_CR1_UDIS);
1328 }
1329
1330 /**
1331 * @brief Indicates whether update event generation is enabled.
1332 * @rmtoll CR1 UDIS LL_TIM_IsEnabledUpdateEvent
1333 * @param TIMx Timer instance
1334 * @retval State of bit (1 or 0).
1335 */
1336 __STATIC_INLINE uint32_t LL_TIM_IsEnabledUpdateEvent(TIM_TypeDef *TIMx)
1337 {
1338 return (READ_BIT(TIMx->CR1, TIM_CR1_UDIS) == (TIM_CR1_UDIS));
1339 }
1340
1341 /**
1342 * @brief Set update event source
1343 * @note Update event source set to LL_TIM_UPDATESOURCE_REGULAR: any of the following events
1344 * generate an update interrupt or DMA request if enabled:
1345 * - Counter overflow/underflow
1346 * - Setting the UG bit
1347 * - Update generation through the slave mode controller
1348 * @note Update event source set to LL_TIM_UPDATESOURCE_COUNTER: only counter
1349 * overflow/underflow generates an update interrupt or DMA request if enabled.
1350 * @rmtoll CR1 URS LL_TIM_SetUpdateSource
1351 * @param TIMx Timer instance
1352 * @param UpdateSource This parameter can be one of the following values:
1353 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1354 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1355 * @retval None
1356 */
1357 __STATIC_INLINE void LL_TIM_SetUpdateSource(TIM_TypeDef *TIMx, uint32_t UpdateSource)
1358 {
1359 MODIFY_REG(TIMx->CR1, TIM_CR1_URS, UpdateSource);
1360 }
1361
1362 /**
1363 * @brief Get actual event update source
1364 * @rmtoll CR1 URS LL_TIM_GetUpdateSource
1365 * @param TIMx Timer instance
1366 * @retval Returned value can be one of the following values:
1367 * @arg @ref LL_TIM_UPDATESOURCE_REGULAR
1368 * @arg @ref LL_TIM_UPDATESOURCE_COUNTER
1369 */
1370 __STATIC_INLINE uint32_t LL_TIM_GetUpdateSource(TIM_TypeDef *TIMx)
1371 {
1372 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_URS));
1373 }
1374
1375 /**
1376 * @brief Set one pulse mode (one shot v.s. repetitive).
1377 * @rmtoll CR1 OPM LL_TIM_SetOnePulseMode
1378 * @param TIMx Timer instance
1379 * @param OnePulseMode This parameter can be one of the following values:
1380 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1381 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1382 * @retval None
1383 */
1384 __STATIC_INLINE void LL_TIM_SetOnePulseMode(TIM_TypeDef *TIMx, uint32_t OnePulseMode)
1385 {
1386 MODIFY_REG(TIMx->CR1, TIM_CR1_OPM, OnePulseMode);
1387 }
1388
1389 /**
1390 * @brief Get actual one pulse mode.
1391 * @rmtoll CR1 OPM LL_TIM_GetOnePulseMode
1392 * @param TIMx Timer instance
1393 * @retval Returned value can be one of the following values:
1394 * @arg @ref LL_TIM_ONEPULSEMODE_SINGLE
1395 * @arg @ref LL_TIM_ONEPULSEMODE_REPETITIVE
1396 */
1397 __STATIC_INLINE uint32_t LL_TIM_GetOnePulseMode(TIM_TypeDef *TIMx)
1398 {
1399 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_OPM));
1400 }
1401
1402 /**
1403 * @brief Set the timer counter counting mode.
1404 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1405 * check whether or not the counter mode selection feature is supported
1406 * by a timer instance.
1407 * @rmtoll CR1 DIR LL_TIM_SetCounterMode\n
1408 * CR1 CMS LL_TIM_SetCounterMode
1409 * @param TIMx Timer instance
1410 * @param CounterMode This parameter can be one of the following values:
1411 * @arg @ref LL_TIM_COUNTERMODE_UP
1412 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1413 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1414 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1415 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1416 * @retval None
1417 */
1418 __STATIC_INLINE void LL_TIM_SetCounterMode(TIM_TypeDef *TIMx, uint32_t CounterMode)
1419 {
1420 MODIFY_REG(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS, CounterMode);
1421 }
1422
1423 /**
1424 * @brief Get actual counter mode.
1425 * @note Macro @ref IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx) can be used to
1426 * check whether or not the counter mode selection feature is supported
1427 * by a timer instance.
1428 * @rmtoll CR1 DIR LL_TIM_GetCounterMode\n
1429 * CR1 CMS LL_TIM_GetCounterMode
1430 * @param TIMx Timer instance
1431 * @retval Returned value can be one of the following values:
1432 * @arg @ref LL_TIM_COUNTERMODE_UP
1433 * @arg @ref LL_TIM_COUNTERMODE_DOWN
1434 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP
1435 * @arg @ref LL_TIM_COUNTERMODE_CENTER_DOWN
1436 * @arg @ref LL_TIM_COUNTERMODE_CENTER_UP_DOWN
1437 */
1438 __STATIC_INLINE uint32_t LL_TIM_GetCounterMode(TIM_TypeDef *TIMx)
1439 {
1440 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR | TIM_CR1_CMS));
1441 }
1442
1443 /**
1444 * @brief Enable auto-reload (ARR) preload.
1445 * @rmtoll CR1 ARPE LL_TIM_EnableARRPreload
1446 * @param TIMx Timer instance
1447 * @retval None
1448 */
1449 __STATIC_INLINE void LL_TIM_EnableARRPreload(TIM_TypeDef *TIMx)
1450 {
1451 SET_BIT(TIMx->CR1, TIM_CR1_ARPE);
1452 }
1453
1454 /**
1455 * @brief Disable auto-reload (ARR) preload.
1456 * @rmtoll CR1 ARPE LL_TIM_DisableARRPreload
1457 * @param TIMx Timer instance
1458 * @retval None
1459 */
1460 __STATIC_INLINE void LL_TIM_DisableARRPreload(TIM_TypeDef *TIMx)
1461 {
1462 CLEAR_BIT(TIMx->CR1, TIM_CR1_ARPE);
1463 }
1464
1465 /**
1466 * @brief Indicates whether auto-reload (ARR) preload is enabled.
1467 * @rmtoll CR1 ARPE LL_TIM_IsEnabledARRPreload
1468 * @param TIMx Timer instance
1469 * @retval State of bit (1 or 0).
1470 */
1471 __STATIC_INLINE uint32_t LL_TIM_IsEnabledARRPreload(TIM_TypeDef *TIMx)
1472 {
1473 return (READ_BIT(TIMx->CR1, TIM_CR1_ARPE) == (TIM_CR1_ARPE));
1474 }
1475
1476 /**
1477 * @brief Set the division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1478 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1479 * whether or not the clock division feature is supported by the timer
1480 * instance.
1481 * @rmtoll CR1 CKD LL_TIM_SetClockDivision
1482 * @param TIMx Timer instance
1483 * @param ClockDivision This parameter can be one of the following values:
1484 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1485 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1486 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1487 * @retval None
1488 */
1489 __STATIC_INLINE void LL_TIM_SetClockDivision(TIM_TypeDef *TIMx, uint32_t ClockDivision)
1490 {
1491 MODIFY_REG(TIMx->CR1, TIM_CR1_CKD, ClockDivision);
1492 }
1493
1494 /**
1495 * @brief Get the actual division ratio between the timer clock and the sampling clock used by the dead-time generators (when supported) and the digital filters.
1496 * @note Macro @ref IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx) can be used to check
1497 * whether or not the clock division feature is supported by the timer
1498 * instance.
1499 * @rmtoll CR1 CKD LL_TIM_GetClockDivision
1500 * @param TIMx Timer instance
1501 * @retval Returned value can be one of the following values:
1502 * @arg @ref LL_TIM_CLOCKDIVISION_DIV1
1503 * @arg @ref LL_TIM_CLOCKDIVISION_DIV2
1504 * @arg @ref LL_TIM_CLOCKDIVISION_DIV4
1505 */
1506 __STATIC_INLINE uint32_t LL_TIM_GetClockDivision(TIM_TypeDef *TIMx)
1507 {
1508 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_CKD));
1509 }
1510
1511 /**
1512 * @brief Set the counter value.
1513 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1514 * whether or not a timer instance supports a 32 bits counter.
1515 * @rmtoll CNT CNT LL_TIM_SetCounter
1516 * @param TIMx Timer instance
1517 * @param Counter Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1518 * @retval None
1519 */
1520 __STATIC_INLINE void LL_TIM_SetCounter(TIM_TypeDef *TIMx, uint32_t Counter)
1521 {
1522 WRITE_REG(TIMx->CNT, Counter);
1523 }
1524
1525 /**
1526 * @brief Get the counter value.
1527 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1528 * whether or not a timer instance supports a 32 bits counter.
1529 * @rmtoll CNT CNT LL_TIM_GetCounter
1530 * @param TIMx Timer instance
1531 * @retval Counter value (between Min_Data=0 and Max_Data=0xFFFF or 0xFFFFFFFF)
1532 */
1533 __STATIC_INLINE uint32_t LL_TIM_GetCounter(TIM_TypeDef *TIMx)
1534 {
1535 return (uint32_t)(READ_REG(TIMx->CNT));
1536 }
1537
1538 /**
1539 * @brief Get the current direction of the counter
1540 * @rmtoll CR1 DIR LL_TIM_GetDirection
1541 * @param TIMx Timer instance
1542 * @retval Returned value can be one of the following values:
1543 * @arg @ref LL_TIM_COUNTERDIRECTION_UP
1544 * @arg @ref LL_TIM_COUNTERDIRECTION_DOWN
1545 */
1546 __STATIC_INLINE uint32_t LL_TIM_GetDirection(TIM_TypeDef *TIMx)
1547 {
1548 return (uint32_t)(READ_BIT(TIMx->CR1, TIM_CR1_DIR));
1549 }
1550
1551 /**
1552 * @brief Set the prescaler value.
1553 * @note The counter clock frequency CK_CNT is equal to fCK_PSC / (PSC[15:0] + 1).
1554 * @note The prescaler can be changed on the fly as this control register is buffered. The new
1555 * prescaler ratio is taken into account at the next update event.
1556 * @note Helper macro @ref __LL_TIM_CALC_PSC can be used to calculate the Prescaler parameter
1557 * @rmtoll PSC PSC LL_TIM_SetPrescaler
1558 * @param TIMx Timer instance
1559 * @param Prescaler between Min_Data=0 and Max_Data=65535
1560 * @retval None
1561 */
1562 __STATIC_INLINE void LL_TIM_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Prescaler)
1563 {
1564 WRITE_REG(TIMx->PSC, Prescaler);
1565 }
1566
1567 /**
1568 * @brief Get the prescaler value.
1569 * @rmtoll PSC PSC LL_TIM_GetPrescaler
1570 * @param TIMx Timer instance
1571 * @retval Prescaler value between Min_Data=0 and Max_Data=65535
1572 */
1573 __STATIC_INLINE uint32_t LL_TIM_GetPrescaler(TIM_TypeDef *TIMx)
1574 {
1575 return (uint32_t)(READ_REG(TIMx->PSC));
1576 }
1577
1578 /**
1579 * @brief Set the auto-reload value.
1580 * @note The counter is blocked while the auto-reload value is null.
1581 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1582 * whether or not a timer instance supports a 32 bits counter.
1583 * @note Helper macro @ref __LL_TIM_CALC_ARR can be used to calculate the AutoReload parameter
1584 * @rmtoll ARR ARR LL_TIM_SetAutoReload
1585 * @param TIMx Timer instance
1586 * @param AutoReload between Min_Data=0 and Max_Data=65535
1587 * @retval None
1588 */
1589 __STATIC_INLINE void LL_TIM_SetAutoReload(TIM_TypeDef *TIMx, uint32_t AutoReload)
1590 {
1591 WRITE_REG(TIMx->ARR, AutoReload);
1592 }
1593
1594 /**
1595 * @brief Get the auto-reload value.
1596 * @rmtoll ARR ARR LL_TIM_GetAutoReload
1597 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
1598 * whether or not a timer instance supports a 32 bits counter.
1599 * @param TIMx Timer instance
1600 * @retval Auto-reload value
1601 */
1602 __STATIC_INLINE uint32_t LL_TIM_GetAutoReload(TIM_TypeDef *TIMx)
1603 {
1604 return (uint32_t)(READ_REG(TIMx->ARR));
1605 }
1606
1607 /**
1608 * @brief Set the repetition counter value.
1609 * @note For advanced timer instances RepetitionCounter can be up to 65535.
1610 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1611 * whether or not a timer instance supports a repetition counter.
1612 * @rmtoll RCR REP LL_TIM_SetRepetitionCounter
1613 * @param TIMx Timer instance
1614 * @param RepetitionCounter between Min_Data=0 and Max_Data=255
1615 * @retval None
1616 */
1617 __STATIC_INLINE void LL_TIM_SetRepetitionCounter(TIM_TypeDef *TIMx, uint32_t RepetitionCounter)
1618 {
1619 WRITE_REG(TIMx->RCR, RepetitionCounter);
1620 }
1621
1622 /**
1623 * @brief Get the repetition counter value.
1624 * @note Macro @ref IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx) can be used to check
1625 * whether or not a timer instance supports a repetition counter.
1626 * @rmtoll RCR REP LL_TIM_GetRepetitionCounter
1627 * @param TIMx Timer instance
1628 * @retval Repetition counter value
1629 */
1630 __STATIC_INLINE uint32_t LL_TIM_GetRepetitionCounter(TIM_TypeDef *TIMx)
1631 {
1632 return (uint32_t)(READ_REG(TIMx->RCR));
1633 }
1634
1635 /**
1636 * @brief Force a continuous copy of the update interrupt flag (UIF) into the timer counter register (bit 31).
1637 * @note This allows both the counter value and a potential roll-over condition signalled by the UIFCPY flag to be read in an atomic way.
1638 * @rmtoll CR1 UIFREMAP LL_TIM_EnableUIFRemap
1639 * @param TIMx Timer instance
1640 * @retval None
1641 */
1642 __STATIC_INLINE void LL_TIM_EnableUIFRemap(TIM_TypeDef *TIMx)
1643 {
1644 SET_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1645 }
1646
1647 /**
1648 * @brief Disable update interrupt flag (UIF) remapping.
1649 * @rmtoll CR1 UIFREMAP LL_TIM_DisableUIFRemap
1650 * @param TIMx Timer instance
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_TIM_DisableUIFRemap(TIM_TypeDef *TIMx)
1654 {
1655 CLEAR_BIT(TIMx->CR1, TIM_CR1_UIFREMAP);
1656 }
1657
1658 /**
1659 * @}
1660 */
1661
1662 /** @defgroup TIM_LL_EF_Capture_Compare Capture Compare configuration
1663 * @{
1664 */
1665 /**
1666 * @brief Enable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1667 * @note CCxE, CCxNE and OCxM bits are preloaded, after having been written,
1668 * they are updated only when a commutation event (COM) occurs.
1669 * @note Only on channels that have a complementary output.
1670 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1671 * whether or not a timer instance is able to generate a commutation event.
1672 * @rmtoll CR2 CCPC LL_TIM_CC_EnablePreload
1673 * @param TIMx Timer instance
1674 * @retval None
1675 */
1676 __STATIC_INLINE void LL_TIM_CC_EnablePreload(TIM_TypeDef *TIMx)
1677 {
1678 SET_BIT(TIMx->CR2, TIM_CR2_CCPC);
1679 }
1680
1681 /**
1682 * @brief Disable the capture/compare control bits (CCxE, CCxNE and OCxM) preload.
1683 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1684 * whether or not a timer instance is able to generate a commutation event.
1685 * @rmtoll CR2 CCPC LL_TIM_CC_DisablePreload
1686 * @param TIMx Timer instance
1687 * @retval None
1688 */
1689 __STATIC_INLINE void LL_TIM_CC_DisablePreload(TIM_TypeDef *TIMx)
1690 {
1691 CLEAR_BIT(TIMx->CR2, TIM_CR2_CCPC);
1692 }
1693
1694 /**
1695 * @brief Set the updated source of the capture/compare control bits (CCxE, CCxNE and OCxM).
1696 * @note Macro @ref IS_TIM_COMMUTATION_EVENT_INSTANCE(TIMx) can be used to check
1697 * whether or not a timer instance is able to generate a commutation event.
1698 * @rmtoll CR2 CCUS LL_TIM_CC_SetUpdate
1699 * @param TIMx Timer instance
1700 * @param CCUpdateSource This parameter can be one of the following values:
1701 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_ONLY
1702 * @arg @ref LL_TIM_CCUPDATESOURCE_COMG_AND_TRGI
1703 * @retval None
1704 */
1705 __STATIC_INLINE void LL_TIM_CC_SetUpdate(TIM_TypeDef *TIMx, uint32_t CCUpdateSource)
1706 {
1707 MODIFY_REG(TIMx->CR2, TIM_CR2_CCUS, CCUpdateSource);
1708 }
1709
1710 /**
1711 * @brief Set the trigger of the capture/compare DMA request.
1712 * @rmtoll CR2 CCDS LL_TIM_CC_SetDMAReqTrigger
1713 * @param TIMx Timer instance
1714 * @param DMAReqTrigger This parameter can be one of the following values:
1715 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1716 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1717 * @retval None
1718 */
1719 __STATIC_INLINE void LL_TIM_CC_SetDMAReqTrigger(TIM_TypeDef *TIMx, uint32_t DMAReqTrigger)
1720 {
1721 MODIFY_REG(TIMx->CR2, TIM_CR2_CCDS, DMAReqTrigger);
1722 }
1723
1724 /**
1725 * @brief Get actual trigger of the capture/compare DMA request.
1726 * @rmtoll CR2 CCDS LL_TIM_CC_GetDMAReqTrigger
1727 * @param TIMx Timer instance
1728 * @retval Returned value can be one of the following values:
1729 * @arg @ref LL_TIM_CCDMAREQUEST_CC
1730 * @arg @ref LL_TIM_CCDMAREQUEST_UPDATE
1731 */
1732 __STATIC_INLINE uint32_t LL_TIM_CC_GetDMAReqTrigger(TIM_TypeDef *TIMx)
1733 {
1734 return (uint32_t)(READ_BIT(TIMx->CR2, TIM_CR2_CCDS));
1735 }
1736
1737 /**
1738 * @brief Set the lock level to freeze the
1739 * configuration of several capture/compare parameters.
1740 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
1741 * the lock mechanism is supported by a timer instance.
1742 * @rmtoll BDTR LOCK LL_TIM_CC_SetLockLevel
1743 * @param TIMx Timer instance
1744 * @param LockLevel This parameter can be one of the following values:
1745 * @arg @ref LL_TIM_LOCKLEVEL_OFF
1746 * @arg @ref LL_TIM_LOCKLEVEL_1
1747 * @arg @ref LL_TIM_LOCKLEVEL_2
1748 * @arg @ref LL_TIM_LOCKLEVEL_3
1749 * @retval None
1750 */
1751 __STATIC_INLINE void LL_TIM_CC_SetLockLevel(TIM_TypeDef *TIMx, uint32_t LockLevel)
1752 {
1753 MODIFY_REG(TIMx->BDTR, TIM_BDTR_LOCK, LockLevel);
1754 }
1755
1756 /**
1757 * @brief Enable capture/compare channels.
1758 * @rmtoll CCER CC1E LL_TIM_CC_EnableChannel\n
1759 * CCER CC1NE LL_TIM_CC_EnableChannel\n
1760 * CCER CC2E LL_TIM_CC_EnableChannel\n
1761 * CCER CC2NE LL_TIM_CC_EnableChannel\n
1762 * CCER CC3E LL_TIM_CC_EnableChannel\n
1763 * CCER CC3NE LL_TIM_CC_EnableChannel\n
1764 * CCER CC4E LL_TIM_CC_EnableChannel\n
1765 * CCER CC5E LL_TIM_CC_EnableChannel\n
1766 * CCER CC6E LL_TIM_CC_EnableChannel
1767 * @param TIMx Timer instance
1768 * @param Channels This parameter can be a combination of the following values:
1769 * @arg @ref LL_TIM_CHANNEL_CH1
1770 * @arg @ref LL_TIM_CHANNEL_CH1N
1771 * @arg @ref LL_TIM_CHANNEL_CH2
1772 * @arg @ref LL_TIM_CHANNEL_CH2N
1773 * @arg @ref LL_TIM_CHANNEL_CH3
1774 * @arg @ref LL_TIM_CHANNEL_CH3N
1775 * @arg @ref LL_TIM_CHANNEL_CH4
1776 * @arg @ref LL_TIM_CHANNEL_CH5
1777 * @arg @ref LL_TIM_CHANNEL_CH6
1778 * @retval None
1779 */
1780 __STATIC_INLINE void LL_TIM_CC_EnableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1781 {
1782 SET_BIT(TIMx->CCER, Channels);
1783 }
1784
1785 /**
1786 * @brief Disable capture/compare channels.
1787 * @rmtoll CCER CC1E LL_TIM_CC_DisableChannel\n
1788 * CCER CC1NE LL_TIM_CC_DisableChannel\n
1789 * CCER CC2E LL_TIM_CC_DisableChannel\n
1790 * CCER CC2NE LL_TIM_CC_DisableChannel\n
1791 * CCER CC3E LL_TIM_CC_DisableChannel\n
1792 * CCER CC3NE LL_TIM_CC_DisableChannel\n
1793 * CCER CC4E LL_TIM_CC_DisableChannel\n
1794 * CCER CC5E LL_TIM_CC_DisableChannel\n
1795 * CCER CC6E LL_TIM_CC_DisableChannel
1796 * @param TIMx Timer instance
1797 * @param Channels This parameter can be a combination of the following values:
1798 * @arg @ref LL_TIM_CHANNEL_CH1
1799 * @arg @ref LL_TIM_CHANNEL_CH1N
1800 * @arg @ref LL_TIM_CHANNEL_CH2
1801 * @arg @ref LL_TIM_CHANNEL_CH2N
1802 * @arg @ref LL_TIM_CHANNEL_CH3
1803 * @arg @ref LL_TIM_CHANNEL_CH3N
1804 * @arg @ref LL_TIM_CHANNEL_CH4
1805 * @arg @ref LL_TIM_CHANNEL_CH5
1806 * @arg @ref LL_TIM_CHANNEL_CH6
1807 * @retval None
1808 */
1809 __STATIC_INLINE void LL_TIM_CC_DisableChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1810 {
1811 CLEAR_BIT(TIMx->CCER, Channels);
1812 }
1813
1814 /**
1815 * @brief Indicate whether channel(s) is(are) enabled.
1816 * @rmtoll CCER CC1E LL_TIM_CC_IsEnabledChannel\n
1817 * CCER CC1NE LL_TIM_CC_IsEnabledChannel\n
1818 * CCER CC2E LL_TIM_CC_IsEnabledChannel\n
1819 * CCER CC2NE LL_TIM_CC_IsEnabledChannel\n
1820 * CCER CC3E LL_TIM_CC_IsEnabledChannel\n
1821 * CCER CC3NE LL_TIM_CC_IsEnabledChannel\n
1822 * CCER CC4E LL_TIM_CC_IsEnabledChannel\n
1823 * CCER CC5E LL_TIM_CC_IsEnabledChannel\n
1824 * CCER CC6E LL_TIM_CC_IsEnabledChannel
1825 * @param TIMx Timer instance
1826 * @param Channels This parameter can be a combination of the following values:
1827 * @arg @ref LL_TIM_CHANNEL_CH1
1828 * @arg @ref LL_TIM_CHANNEL_CH1N
1829 * @arg @ref LL_TIM_CHANNEL_CH2
1830 * @arg @ref LL_TIM_CHANNEL_CH2N
1831 * @arg @ref LL_TIM_CHANNEL_CH3
1832 * @arg @ref LL_TIM_CHANNEL_CH3N
1833 * @arg @ref LL_TIM_CHANNEL_CH4
1834 * @arg @ref LL_TIM_CHANNEL_CH5
1835 * @arg @ref LL_TIM_CHANNEL_CH6
1836 * @retval State of bit (1 or 0).
1837 */
1838 __STATIC_INLINE uint32_t LL_TIM_CC_IsEnabledChannel(TIM_TypeDef *TIMx, uint32_t Channels)
1839 {
1840 return (READ_BIT(TIMx->CCER, Channels) == (Channels));
1841 }
1842
1843 /**
1844 * @}
1845 */
1846
1847 /** @defgroup TIM_LL_EF_Output_Channel Output channel configuration
1848 * @{
1849 */
1850 /**
1851 * @brief Configure an output channel.
1852 * @rmtoll CCMR1 CC1S LL_TIM_OC_ConfigOutput\n
1853 * CCMR1 CC2S LL_TIM_OC_ConfigOutput\n
1854 * CCMR2 CC3S LL_TIM_OC_ConfigOutput\n
1855 * CCMR2 CC4S LL_TIM_OC_ConfigOutput\n
1856 * CCMR3 CC5S LL_TIM_OC_ConfigOutput\n
1857 * CCMR3 CC6S LL_TIM_OC_ConfigOutput\n
1858 * CCER CC1P LL_TIM_OC_ConfigOutput\n
1859 * CCER CC2P LL_TIM_OC_ConfigOutput\n
1860 * CCER CC3P LL_TIM_OC_ConfigOutput\n
1861 * CCER CC4P LL_TIM_OC_ConfigOutput\n
1862 * CCER CC5P LL_TIM_OC_ConfigOutput\n
1863 * CCER CC6P LL_TIM_OC_ConfigOutput\n
1864 * CR2 OIS1 LL_TIM_OC_ConfigOutput\n
1865 * CR2 OIS2 LL_TIM_OC_ConfigOutput\n
1866 * CR2 OIS3 LL_TIM_OC_ConfigOutput\n
1867 * CR2 OIS4 LL_TIM_OC_ConfigOutput\n
1868 * CR2 OIS5 LL_TIM_OC_ConfigOutput\n
1869 * CR2 OIS6 LL_TIM_OC_ConfigOutput
1870 * @param TIMx Timer instance
1871 * @param Channel This parameter can be one of the following values:
1872 * @arg @ref LL_TIM_CHANNEL_CH1
1873 * @arg @ref LL_TIM_CHANNEL_CH2
1874 * @arg @ref LL_TIM_CHANNEL_CH3
1875 * @arg @ref LL_TIM_CHANNEL_CH4
1876 * @arg @ref LL_TIM_CHANNEL_CH5
1877 * @arg @ref LL_TIM_CHANNEL_CH6
1878 * @param Configuration This parameter must be a combination of all the following values:
1879 * @arg @ref LL_TIM_OCPOLARITY_HIGH or @ref LL_TIM_OCPOLARITY_LOW
1880 * @arg @ref LL_TIM_OCIDLESTATE_LOW or @ref LL_TIM_OCIDLESTATE_HIGH
1881 * @retval None
1882 */
1883 __STATIC_INLINE void LL_TIM_OC_ConfigOutput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
1884 {
1885 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1886 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1887 CLEAR_BIT(*pReg, (TIM_CCMR1_CC1S << SHIFT_TAB_OCxx[iChannel]));
1888 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]),
1889 (Configuration & TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]);
1890 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]),
1891 (Configuration & TIM_CR2_OIS1) << SHIFT_TAB_OISx[iChannel]);
1892 }
1893
1894 /**
1895 * @brief Define the behavior of the output reference signal OCxREF from which
1896 * OCx and OCxN (when relevant) are derived.
1897 * @rmtoll CCMR1 OC1M LL_TIM_OC_SetMode\n
1898 * CCMR1 OC2M LL_TIM_OC_SetMode\n
1899 * CCMR2 OC3M LL_TIM_OC_SetMode\n
1900 * CCMR2 OC4M LL_TIM_OC_SetMode\n
1901 * CCMR3 OC5M LL_TIM_OC_SetMode\n
1902 * CCMR3 OC6M LL_TIM_OC_SetMode
1903 * @param TIMx Timer instance
1904 * @param Channel This parameter can be one of the following values:
1905 * @arg @ref LL_TIM_CHANNEL_CH1
1906 * @arg @ref LL_TIM_CHANNEL_CH2
1907 * @arg @ref LL_TIM_CHANNEL_CH3
1908 * @arg @ref LL_TIM_CHANNEL_CH4
1909 * @arg @ref LL_TIM_CHANNEL_CH5
1910 * @arg @ref LL_TIM_CHANNEL_CH6
1911 * @param Mode This parameter can be one of the following values:
1912 * @arg @ref LL_TIM_OCMODE_FROZEN
1913 * @arg @ref LL_TIM_OCMODE_ACTIVE
1914 * @arg @ref LL_TIM_OCMODE_INACTIVE
1915 * @arg @ref LL_TIM_OCMODE_TOGGLE
1916 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1917 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1918 * @arg @ref LL_TIM_OCMODE_PWM1
1919 * @arg @ref LL_TIM_OCMODE_PWM2
1920 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1921 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1922 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1923 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1924 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
1925 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
1926 * @retval None
1927 */
1928 __STATIC_INLINE void LL_TIM_OC_SetMode(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Mode)
1929 {
1930 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1931 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1932 MODIFY_REG(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel]), Mode << SHIFT_TAB_OCxx[iChannel]);
1933 }
1934
1935 /**
1936 * @brief Get the output compare mode of an output channel.
1937 * @rmtoll CCMR1 OC1M LL_TIM_OC_GetMode\n
1938 * CCMR1 OC2M LL_TIM_OC_GetMode\n
1939 * CCMR2 OC3M LL_TIM_OC_GetMode\n
1940 * CCMR2 OC4M LL_TIM_OC_GetMode\n
1941 * CCMR3 OC5M LL_TIM_OC_GetMode\n
1942 * CCMR3 OC6M LL_TIM_OC_GetMode
1943 * @param TIMx Timer instance
1944 * @param Channel This parameter can be one of the following values:
1945 * @arg @ref LL_TIM_CHANNEL_CH1
1946 * @arg @ref LL_TIM_CHANNEL_CH2
1947 * @arg @ref LL_TIM_CHANNEL_CH3
1948 * @arg @ref LL_TIM_CHANNEL_CH4
1949 * @arg @ref LL_TIM_CHANNEL_CH5
1950 * @arg @ref LL_TIM_CHANNEL_CH6
1951 * @retval Returned value can be one of the following values:
1952 * @arg @ref LL_TIM_OCMODE_FROZEN
1953 * @arg @ref LL_TIM_OCMODE_ACTIVE
1954 * @arg @ref LL_TIM_OCMODE_INACTIVE
1955 * @arg @ref LL_TIM_OCMODE_TOGGLE
1956 * @arg @ref LL_TIM_OCMODE_FORCED_INACTIVE
1957 * @arg @ref LL_TIM_OCMODE_FORCED_ACTIVE
1958 * @arg @ref LL_TIM_OCMODE_PWM1
1959 * @arg @ref LL_TIM_OCMODE_PWM2
1960 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM1
1961 * @arg @ref LL_TIM_OCMODE_RETRIG_OPM2
1962 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM1
1963 * @arg @ref LL_TIM_OCMODE_COMBINED_PWM2
1964 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM1
1965 * @arg @ref LL_TIM_OCMODE_ASSYMETRIC_PWM2
1966 */
1967 __STATIC_INLINE uint32_t LL_TIM_OC_GetMode(TIM_TypeDef *TIMx, uint32_t Channel)
1968 {
1969 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
1970 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
1971 return (READ_BIT(*pReg, ((TIM_CCMR1_OC1M | TIM_CCMR1_CC1S) << SHIFT_TAB_OCxx[iChannel])) >> SHIFT_TAB_OCxx[iChannel]);
1972 }
1973
1974 /**
1975 * @brief Set the polarity of an output channel.
1976 * @rmtoll CCER CC1P LL_TIM_OC_SetPolarity\n
1977 * CCER CC1NP LL_TIM_OC_SetPolarity\n
1978 * CCER CC2P LL_TIM_OC_SetPolarity\n
1979 * CCER CC2NP LL_TIM_OC_SetPolarity\n
1980 * CCER CC3P LL_TIM_OC_SetPolarity\n
1981 * CCER CC3NP LL_TIM_OC_SetPolarity\n
1982 * CCER CC4P LL_TIM_OC_SetPolarity\n
1983 * CCER CC5P LL_TIM_OC_SetPolarity\n
1984 * CCER CC6P LL_TIM_OC_SetPolarity
1985 * @param TIMx Timer instance
1986 * @param Channel This parameter can be one of the following values:
1987 * @arg @ref LL_TIM_CHANNEL_CH1
1988 * @arg @ref LL_TIM_CHANNEL_CH1N
1989 * @arg @ref LL_TIM_CHANNEL_CH2
1990 * @arg @ref LL_TIM_CHANNEL_CH2N
1991 * @arg @ref LL_TIM_CHANNEL_CH3
1992 * @arg @ref LL_TIM_CHANNEL_CH3N
1993 * @arg @ref LL_TIM_CHANNEL_CH4
1994 * @arg @ref LL_TIM_CHANNEL_CH5
1995 * @arg @ref LL_TIM_CHANNEL_CH6
1996 * @param Polarity This parameter can be one of the following values:
1997 * @arg @ref LL_TIM_OCPOLARITY_HIGH
1998 * @arg @ref LL_TIM_OCPOLARITY_LOW
1999 * @retval None
2000 */
2001 __STATIC_INLINE void LL_TIM_OC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Polarity)
2002 {
2003 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2004 MODIFY_REG(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel]), Polarity << SHIFT_TAB_CCxP[iChannel]);
2005 }
2006
2007 /**
2008 * @brief Get the polarity of an output channel.
2009 * @rmtoll CCER CC1P LL_TIM_OC_GetPolarity\n
2010 * CCER CC1NP LL_TIM_OC_GetPolarity\n
2011 * CCER CC2P LL_TIM_OC_GetPolarity\n
2012 * CCER CC2NP LL_TIM_OC_GetPolarity\n
2013 * CCER CC3P LL_TIM_OC_GetPolarity\n
2014 * CCER CC3NP LL_TIM_OC_GetPolarity\n
2015 * CCER CC4P LL_TIM_OC_GetPolarity\n
2016 * CCER CC5P LL_TIM_OC_GetPolarity\n
2017 * CCER CC6P LL_TIM_OC_GetPolarity
2018 * @param TIMx Timer instance
2019 * @param Channel This parameter can be one of the following values:
2020 * @arg @ref LL_TIM_CHANNEL_CH1
2021 * @arg @ref LL_TIM_CHANNEL_CH1N
2022 * @arg @ref LL_TIM_CHANNEL_CH2
2023 * @arg @ref LL_TIM_CHANNEL_CH2N
2024 * @arg @ref LL_TIM_CHANNEL_CH3
2025 * @arg @ref LL_TIM_CHANNEL_CH3N
2026 * @arg @ref LL_TIM_CHANNEL_CH4
2027 * @arg @ref LL_TIM_CHANNEL_CH5
2028 * @arg @ref LL_TIM_CHANNEL_CH6
2029 * @retval Returned value can be one of the following values:
2030 * @arg @ref LL_TIM_OCPOLARITY_HIGH
2031 * @arg @ref LL_TIM_OCPOLARITY_LOW
2032 */
2033 __STATIC_INLINE uint32_t LL_TIM_OC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2034 {
2035 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2036 return (READ_BIT(TIMx->CCER, (TIM_CCER_CC1P << SHIFT_TAB_CCxP[iChannel])) >> SHIFT_TAB_CCxP[iChannel]);
2037 }
2038
2039 /**
2040 * @brief Set the IDLE state of an output channel
2041 * @note This function is significant only for the timer instances
2042 * supporting the break feature. Macro @ref IS_TIM_BREAK_INSTANCE(TIMx)
2043 * can be used to check whether or not a timer instance provides
2044 * a break input.
2045 * @rmtoll CR2 OIS1 LL_TIM_OC_SetIdleState\n
2046 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2047 * CR2 OIS2 LL_TIM_OC_SetIdleState\n
2048 * CR2 OIS2N LL_TIM_OC_SetIdleState\n
2049 * CR2 OIS3 LL_TIM_OC_SetIdleState\n
2050 * CR2 OIS3N LL_TIM_OC_SetIdleState\n
2051 * CR2 OIS4 LL_TIM_OC_SetIdleState\n
2052 * CR2 OIS5 LL_TIM_OC_SetIdleState\n
2053 * CR2 OIS6 LL_TIM_OC_SetIdleState
2054 * @param TIMx Timer instance
2055 * @param Channel This parameter can be one of the following values:
2056 * @arg @ref LL_TIM_CHANNEL_CH1
2057 * @arg @ref LL_TIM_CHANNEL_CH1N
2058 * @arg @ref LL_TIM_CHANNEL_CH2
2059 * @arg @ref LL_TIM_CHANNEL_CH2N
2060 * @arg @ref LL_TIM_CHANNEL_CH3
2061 * @arg @ref LL_TIM_CHANNEL_CH3N
2062 * @arg @ref LL_TIM_CHANNEL_CH4
2063 * @arg @ref LL_TIM_CHANNEL_CH5
2064 * @arg @ref LL_TIM_CHANNEL_CH6
2065 * @param IdleState This parameter can be one of the following values:
2066 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2067 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2068 * @retval None
2069 */
2070 __STATIC_INLINE void LL_TIM_OC_SetIdleState(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t IdleState)
2071 {
2072 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2073 MODIFY_REG(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel]), IdleState << SHIFT_TAB_OISx[iChannel]);
2074 }
2075
2076 /**
2077 * @brief Get the IDLE state of an output channel
2078 * @rmtoll CR2 OIS1 LL_TIM_OC_GetIdleState\n
2079 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2080 * CR2 OIS2 LL_TIM_OC_GetIdleState\n
2081 * CR2 OIS2N LL_TIM_OC_GetIdleState\n
2082 * CR2 OIS3 LL_TIM_OC_GetIdleState\n
2083 * CR2 OIS3N LL_TIM_OC_GetIdleState\n
2084 * CR2 OIS4 LL_TIM_OC_GetIdleState\n
2085 * CR2 OIS5 LL_TIM_OC_GetIdleState\n
2086 * CR2 OIS6 LL_TIM_OC_GetIdleState
2087 * @param TIMx Timer instance
2088 * @param Channel This parameter can be one of the following values:
2089 * @arg @ref LL_TIM_CHANNEL_CH1
2090 * @arg @ref LL_TIM_CHANNEL_CH1N
2091 * @arg @ref LL_TIM_CHANNEL_CH2
2092 * @arg @ref LL_TIM_CHANNEL_CH2N
2093 * @arg @ref LL_TIM_CHANNEL_CH3
2094 * @arg @ref LL_TIM_CHANNEL_CH3N
2095 * @arg @ref LL_TIM_CHANNEL_CH4
2096 * @arg @ref LL_TIM_CHANNEL_CH5
2097 * @arg @ref LL_TIM_CHANNEL_CH6
2098 * @retval Returned value can be one of the following values:
2099 * @arg @ref LL_TIM_OCIDLESTATE_LOW
2100 * @arg @ref LL_TIM_OCIDLESTATE_HIGH
2101 */
2102 __STATIC_INLINE uint32_t LL_TIM_OC_GetIdleState(TIM_TypeDef *TIMx, uint32_t Channel)
2103 {
2104 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2105 return (READ_BIT(TIMx->CR2, (TIM_CR2_OIS1 << SHIFT_TAB_OISx[iChannel])) >> SHIFT_TAB_OISx[iChannel]);
2106 }
2107
2108 /**
2109 * @brief Enable fast mode for the output channel.
2110 * @note Acts only if the channel is configured in PWM1 or PWM2 mode.
2111 * @rmtoll CCMR1 OC1FE LL_TIM_OC_EnableFast\n
2112 * CCMR1 OC2FE LL_TIM_OC_EnableFast\n
2113 * CCMR2 OC3FE LL_TIM_OC_EnableFast\n
2114 * CCMR2 OC4FE LL_TIM_OC_EnableFast\n
2115 * CCMR3 OC5FE LL_TIM_OC_EnableFast\n
2116 * CCMR3 OC6FE LL_TIM_OC_EnableFast
2117 * @param TIMx Timer instance
2118 * @param Channel This parameter can be one of the following values:
2119 * @arg @ref LL_TIM_CHANNEL_CH1
2120 * @arg @ref LL_TIM_CHANNEL_CH2
2121 * @arg @ref LL_TIM_CHANNEL_CH3
2122 * @arg @ref LL_TIM_CHANNEL_CH4
2123 * @arg @ref LL_TIM_CHANNEL_CH5
2124 * @arg @ref LL_TIM_CHANNEL_CH6
2125 * @retval None
2126 */
2127 __STATIC_INLINE void LL_TIM_OC_EnableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2128 {
2129 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2130 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2131 SET_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2132
2133 }
2134
2135 /**
2136 * @brief Disable fast mode for the output channel.
2137 * @rmtoll CCMR1 OC1FE LL_TIM_OC_DisableFast\n
2138 * CCMR1 OC2FE LL_TIM_OC_DisableFast\n
2139 * CCMR2 OC3FE LL_TIM_OC_DisableFast\n
2140 * CCMR2 OC4FE LL_TIM_OC_DisableFast\n
2141 * CCMR3 OC5FE LL_TIM_OC_DisableFast\n
2142 * CCMR3 OC6FE LL_TIM_OC_DisableFast
2143 * @param TIMx Timer instance
2144 * @param Channel This parameter can be one of the following values:
2145 * @arg @ref LL_TIM_CHANNEL_CH1
2146 * @arg @ref LL_TIM_CHANNEL_CH2
2147 * @arg @ref LL_TIM_CHANNEL_CH3
2148 * @arg @ref LL_TIM_CHANNEL_CH4
2149 * @arg @ref LL_TIM_CHANNEL_CH5
2150 * @arg @ref LL_TIM_CHANNEL_CH6
2151 * @retval None
2152 */
2153 __STATIC_INLINE void LL_TIM_OC_DisableFast(TIM_TypeDef *TIMx, uint32_t Channel)
2154 {
2155 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2156 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2157 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel]));
2158
2159 }
2160
2161 /**
2162 * @brief Indicates whether fast mode is enabled for the output channel.
2163 * @rmtoll CCMR1 OC1FE LL_TIM_OC_IsEnabledFast\n
2164 * CCMR1 OC2FE LL_TIM_OC_IsEnabledFast\n
2165 * CCMR2 OC3FE LL_TIM_OC_IsEnabledFast\n
2166 * CCMR2 OC4FE LL_TIM_OC_IsEnabledFast\n
2167 * CCMR3 OC5FE LL_TIM_OC_IsEnabledFast\n
2168 * CCMR3 OC6FE LL_TIM_OC_IsEnabledFast
2169 * @param TIMx Timer instance
2170 * @param Channel This parameter can be one of the following values:
2171 * @arg @ref LL_TIM_CHANNEL_CH1
2172 * @arg @ref LL_TIM_CHANNEL_CH2
2173 * @arg @ref LL_TIM_CHANNEL_CH3
2174 * @arg @ref LL_TIM_CHANNEL_CH4
2175 * @arg @ref LL_TIM_CHANNEL_CH5
2176 * @arg @ref LL_TIM_CHANNEL_CH6
2177 * @retval State of bit (1 or 0).
2178 */
2179 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledFast(TIM_TypeDef *TIMx, uint32_t Channel)
2180 {
2181 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2182 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2183 register uint32_t bitfield = TIM_CCMR1_OC1FE << SHIFT_TAB_OCxx[iChannel];
2184 return (READ_BIT(*pReg, bitfield) == bitfield);
2185 }
2186
2187 /**
2188 * @brief Enable compare register (TIMx_CCRx) preload for the output channel.
2189 * @rmtoll CCMR1 OC1PE LL_TIM_OC_EnablePreload\n
2190 * CCMR1 OC2PE LL_TIM_OC_EnablePreload\n
2191 * CCMR2 OC3PE LL_TIM_OC_EnablePreload\n
2192 * CCMR2 OC4PE LL_TIM_OC_EnablePreload\n
2193 * CCMR3 OC5PE LL_TIM_OC_EnablePreload\n
2194 * CCMR3 OC6PE LL_TIM_OC_EnablePreload
2195 * @param TIMx Timer instance
2196 * @param Channel This parameter can be one of the following values:
2197 * @arg @ref LL_TIM_CHANNEL_CH1
2198 * @arg @ref LL_TIM_CHANNEL_CH2
2199 * @arg @ref LL_TIM_CHANNEL_CH3
2200 * @arg @ref LL_TIM_CHANNEL_CH4
2201 * @arg @ref LL_TIM_CHANNEL_CH5
2202 * @arg @ref LL_TIM_CHANNEL_CH6
2203 * @retval None
2204 */
2205 __STATIC_INLINE void LL_TIM_OC_EnablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2206 {
2207 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2208 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2209 SET_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2210 }
2211
2212 /**
2213 * @brief Disable compare register (TIMx_CCRx) preload for the output channel.
2214 * @rmtoll CCMR1 OC1PE LL_TIM_OC_DisablePreload\n
2215 * CCMR1 OC2PE LL_TIM_OC_DisablePreload\n
2216 * CCMR2 OC3PE LL_TIM_OC_DisablePreload\n
2217 * CCMR2 OC4PE LL_TIM_OC_DisablePreload\n
2218 * CCMR3 OC5PE LL_TIM_OC_DisablePreload\n
2219 * CCMR3 OC6PE LL_TIM_OC_DisablePreload
2220 * @param TIMx Timer instance
2221 * @param Channel This parameter can be one of the following values:
2222 * @arg @ref LL_TIM_CHANNEL_CH1
2223 * @arg @ref LL_TIM_CHANNEL_CH2
2224 * @arg @ref LL_TIM_CHANNEL_CH3
2225 * @arg @ref LL_TIM_CHANNEL_CH4
2226 * @arg @ref LL_TIM_CHANNEL_CH5
2227 * @arg @ref LL_TIM_CHANNEL_CH6
2228 * @retval None
2229 */
2230 __STATIC_INLINE void LL_TIM_OC_DisablePreload(TIM_TypeDef *TIMx, uint32_t Channel)
2231 {
2232 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2233 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2234 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel]));
2235 }
2236
2237 /**
2238 * @brief Indicates whether compare register (TIMx_CCRx) preload is enabled for the output channel.
2239 * @rmtoll CCMR1 OC1PE LL_TIM_OC_IsEnabledPreload\n
2240 * CCMR1 OC2PE LL_TIM_OC_IsEnabledPreload\n
2241 * CCMR2 OC3PE LL_TIM_OC_IsEnabledPreload\n
2242 * CCMR2 OC4PE LL_TIM_OC_IsEnabledPreload\n
2243 * CCMR3 OC5PE LL_TIM_OC_IsEnabledPreload\n
2244 * CCMR3 OC6PE LL_TIM_OC_IsEnabledPreload
2245 * @param TIMx Timer instance
2246 * @param Channel This parameter can be one of the following values:
2247 * @arg @ref LL_TIM_CHANNEL_CH1
2248 * @arg @ref LL_TIM_CHANNEL_CH2
2249 * @arg @ref LL_TIM_CHANNEL_CH3
2250 * @arg @ref LL_TIM_CHANNEL_CH4
2251 * @arg @ref LL_TIM_CHANNEL_CH5
2252 * @arg @ref LL_TIM_CHANNEL_CH6
2253 * @retval State of bit (1 or 0).
2254 */
2255 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledPreload(TIM_TypeDef *TIMx, uint32_t Channel)
2256 {
2257 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2258 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2259 register uint32_t bitfield = TIM_CCMR1_OC1PE << SHIFT_TAB_OCxx[iChannel];
2260 return (READ_BIT(*pReg, bitfield) == bitfield);
2261 }
2262
2263 /**
2264 * @brief Enable clearing the output channel on an external event.
2265 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2266 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2267 * or not a timer instance can clear the OCxREF signal on an external event.
2268 * @rmtoll CCMR1 OC1CE LL_TIM_OC_EnableClear\n
2269 * CCMR1 OC2CE LL_TIM_OC_EnableClear\n
2270 * CCMR2 OC3CE LL_TIM_OC_EnableClear\n
2271 * CCMR2 OC4CE LL_TIM_OC_EnableClear\n
2272 * CCMR3 OC5CE LL_TIM_OC_EnableClear\n
2273 * CCMR3 OC6CE LL_TIM_OC_EnableClear
2274 * @param TIMx Timer instance
2275 * @param Channel This parameter can be one of the following values:
2276 * @arg @ref LL_TIM_CHANNEL_CH1
2277 * @arg @ref LL_TIM_CHANNEL_CH2
2278 * @arg @ref LL_TIM_CHANNEL_CH3
2279 * @arg @ref LL_TIM_CHANNEL_CH4
2280 * @arg @ref LL_TIM_CHANNEL_CH5
2281 * @arg @ref LL_TIM_CHANNEL_CH6
2282 * @retval None
2283 */
2284 __STATIC_INLINE void LL_TIM_OC_EnableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2285 {
2286 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2287 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2288 SET_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2289 }
2290
2291 /**
2292 * @brief Disable clearing the output channel on an external event.
2293 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2294 * or not a timer instance can clear the OCxREF signal on an external event.
2295 * @rmtoll CCMR1 OC1CE LL_TIM_OC_DisableClear\n
2296 * CCMR1 OC2CE LL_TIM_OC_DisableClear\n
2297 * CCMR2 OC3CE LL_TIM_OC_DisableClear\n
2298 * CCMR2 OC4CE LL_TIM_OC_DisableClear\n
2299 * CCMR3 OC5CE LL_TIM_OC_DisableClear\n
2300 * CCMR3 OC6CE LL_TIM_OC_DisableClear
2301 * @param TIMx Timer instance
2302 * @param Channel This parameter can be one of the following values:
2303 * @arg @ref LL_TIM_CHANNEL_CH1
2304 * @arg @ref LL_TIM_CHANNEL_CH2
2305 * @arg @ref LL_TIM_CHANNEL_CH3
2306 * @arg @ref LL_TIM_CHANNEL_CH4
2307 * @arg @ref LL_TIM_CHANNEL_CH5
2308 * @arg @ref LL_TIM_CHANNEL_CH6
2309 * @retval None
2310 */
2311 __STATIC_INLINE void LL_TIM_OC_DisableClear(TIM_TypeDef *TIMx, uint32_t Channel)
2312 {
2313 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2314 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2315 CLEAR_BIT(*pReg, (TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel]));
2316 }
2317
2318 /**
2319 * @brief Indicates clearing the output channel on an external event is enabled for the output channel.
2320 * @note This function enables clearing the output channel on an external event.
2321 * @note This function can only be used in Output compare and PWM modes. It does not work in Forced mode.
2322 * @note Macro @ref IS_TIM_OCXREF_CLEAR_INSTANCE(TIMx) can be used to check whether
2323 * or not a timer instance can clear the OCxREF signal on an external event.
2324 * @rmtoll CCMR1 OC1CE LL_TIM_OC_IsEnabledClear\n
2325 * CCMR1 OC2CE LL_TIM_OC_IsEnabledClear\n
2326 * CCMR2 OC3CE LL_TIM_OC_IsEnabledClear\n
2327 * CCMR2 OC4CE LL_TIM_OC_IsEnabledClear\n
2328 * CCMR3 OC5CE LL_TIM_OC_IsEnabledClear\n
2329 * CCMR3 OC6CE LL_TIM_OC_IsEnabledClear
2330 * @param TIMx Timer instance
2331 * @param Channel This parameter can be one of the following values:
2332 * @arg @ref LL_TIM_CHANNEL_CH1
2333 * @arg @ref LL_TIM_CHANNEL_CH2
2334 * @arg @ref LL_TIM_CHANNEL_CH3
2335 * @arg @ref LL_TIM_CHANNEL_CH4
2336 * @arg @ref LL_TIM_CHANNEL_CH5
2337 * @arg @ref LL_TIM_CHANNEL_CH6
2338 * @retval State of bit (1 or 0).
2339 */
2340 __STATIC_INLINE uint32_t LL_TIM_OC_IsEnabledClear(TIM_TypeDef *TIMx, uint32_t Channel)
2341 {
2342 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2343 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2344 register uint32_t bitfield = TIM_CCMR1_OC1CE << SHIFT_TAB_OCxx[iChannel];
2345 return (READ_BIT(*pReg, bitfield) == bitfield);
2346 }
2347
2348 /**
2349 * @brief Set the dead-time delay (delay inserted between the rising edge of the OCxREF signal and the rising edge if the Ocx and OCxN signals).
2350 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
2351 * dead-time insertion feature is supported by a timer instance.
2352 * @note Helper macro @ref __LL_TIM_CALC_DEADTIME can be used to calculate the DeadTime parameter
2353 * @rmtoll BDTR DTG LL_TIM_OC_SetDeadTime
2354 * @param TIMx Timer instance
2355 * @param DeadTime between Min_Data=0 and Max_Data=255
2356 * @retval None
2357 */
2358 __STATIC_INLINE void LL_TIM_OC_SetDeadTime(TIM_TypeDef *TIMx, uint32_t DeadTime)
2359 {
2360 MODIFY_REG(TIMx->BDTR, TIM_BDTR_DTG, DeadTime);
2361 }
2362
2363 /**
2364 * @brief Set compare value for output channel 1 (TIMx_CCR1).
2365 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2366 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2367 * whether or not a timer instance supports a 32 bits counter.
2368 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2369 * output channel 1 is supported by a timer instance.
2370 * @rmtoll CCR1 CCR1 LL_TIM_OC_SetCompareCH1
2371 * @param TIMx Timer instance
2372 * @param CompareValue between Min_Data=0 and Max_Data=65535
2373 * @retval None
2374 */
2375 __STATIC_INLINE void LL_TIM_OC_SetCompareCH1(TIM_TypeDef *TIMx, uint32_t CompareValue)
2376 {
2377 WRITE_REG(TIMx->CCR1, CompareValue);
2378 }
2379
2380 /**
2381 * @brief Set compare value for output channel 2 (TIMx_CCR2).
2382 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2383 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2384 * whether or not a timer instance supports a 32 bits counter.
2385 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2386 * output channel 2 is supported by a timer instance.
2387 * @rmtoll CCR2 CCR2 LL_TIM_OC_SetCompareCH2
2388 * @param TIMx Timer instance
2389 * @param CompareValue between Min_Data=0 and Max_Data=65535
2390 * @retval None
2391 */
2392 __STATIC_INLINE void LL_TIM_OC_SetCompareCH2(TIM_TypeDef *TIMx, uint32_t CompareValue)
2393 {
2394 WRITE_REG(TIMx->CCR2, CompareValue);
2395 }
2396
2397 /**
2398 * @brief Set compare value for output channel 3 (TIMx_CCR3).
2399 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2400 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2401 * whether or not a timer instance supports a 32 bits counter.
2402 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2403 * output channel is supported by a timer instance.
2404 * @rmtoll CCR3 CCR3 LL_TIM_OC_SetCompareCH3
2405 * @param TIMx Timer instance
2406 * @param CompareValue between Min_Data=0 and Max_Data=65535
2407 * @retval None
2408 */
2409 __STATIC_INLINE void LL_TIM_OC_SetCompareCH3(TIM_TypeDef *TIMx, uint32_t CompareValue)
2410 {
2411 WRITE_REG(TIMx->CCR3, CompareValue);
2412 }
2413
2414 /**
2415 * @brief Set compare value for output channel 4 (TIMx_CCR4).
2416 * @note In 32-bit timer implementations compare value can be between 0x00000000 and 0xFFFFFFFF.
2417 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2418 * whether or not a timer instance supports a 32 bits counter.
2419 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2420 * output channel 4 is supported by a timer instance.
2421 * @rmtoll CCR4 CCR4 LL_TIM_OC_SetCompareCH4
2422 * @param TIMx Timer instance
2423 * @param CompareValue between Min_Data=0 and Max_Data=65535
2424 * @retval None
2425 */
2426 __STATIC_INLINE void LL_TIM_OC_SetCompareCH4(TIM_TypeDef *TIMx, uint32_t CompareValue)
2427 {
2428 WRITE_REG(TIMx->CCR4, CompareValue);
2429 }
2430
2431 /**
2432 * @brief Set compare value for output channel 5 (TIMx_CCR5).
2433 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2434 * output channel 5 is supported by a timer instance.
2435 * @rmtoll CCR5 CCR5 LL_TIM_OC_SetCompareCH5
2436 * @param TIMx Timer instance
2437 * @param CompareValue between Min_Data=0 and Max_Data=65535
2438 * @retval None
2439 */
2440 __STATIC_INLINE void LL_TIM_OC_SetCompareCH5(TIM_TypeDef *TIMx, uint32_t CompareValue)
2441 {
2442 WRITE_REG(TIMx->CCR5, CompareValue);
2443 }
2444
2445 /**
2446 * @brief Set compare value for output channel 6 (TIMx_CCR6).
2447 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2448 * output channel 6 is supported by a timer instance.
2449 * @rmtoll CCR6 CCR6 LL_TIM_OC_SetCompareCH6
2450 * @param TIMx Timer instance
2451 * @param CompareValue between Min_Data=0 and Max_Data=65535
2452 * @retval None
2453 */
2454 __STATIC_INLINE void LL_TIM_OC_SetCompareCH6(TIM_TypeDef *TIMx, uint32_t CompareValue)
2455 {
2456 WRITE_REG(TIMx->CCR6, CompareValue);
2457 }
2458
2459 /**
2460 * @brief Get compare value (TIMx_CCR1) set for output channel 1.
2461 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2462 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2463 * whether or not a timer instance supports a 32 bits counter.
2464 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2465 * output channel 1 is supported by a timer instance.
2466 * @rmtoll CCR1 CCR1 LL_TIM_OC_GetCompareCH1
2467 * @param TIMx Timer instance
2468 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2469 */
2470 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH1(TIM_TypeDef *TIMx)
2471 {
2472 return (uint32_t)(READ_REG(TIMx->CCR1));
2473 }
2474
2475 /**
2476 * @brief Get compare value (TIMx_CCR2) set for output channel 2.
2477 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2478 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2479 * whether or not a timer instance supports a 32 bits counter.
2480 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2481 * output channel 2 is supported by a timer instance.
2482 * @rmtoll CCR2 CCR2 LL_TIM_OC_GetCompareCH2
2483 * @param TIMx Timer instance
2484 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2485 */
2486 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH2(TIM_TypeDef *TIMx)
2487 {
2488 return (uint32_t)(READ_REG(TIMx->CCR2));
2489 }
2490
2491 /**
2492 * @brief Get compare value (TIMx_CCR3) set for output channel 3.
2493 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2494 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2495 * whether or not a timer instance supports a 32 bits counter.
2496 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2497 * output channel 3 is supported by a timer instance.
2498 * @rmtoll CCR3 CCR3 LL_TIM_OC_GetCompareCH3
2499 * @param TIMx Timer instance
2500 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2501 */
2502 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH3(TIM_TypeDef *TIMx)
2503 {
2504 return (uint32_t)(READ_REG(TIMx->CCR3));
2505 }
2506
2507 /**
2508 * @brief Get compare value (TIMx_CCR4) set for output channel 4.
2509 * @note In 32-bit timer implementations returned compare value can be between 0x00000000 and 0xFFFFFFFF.
2510 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2511 * whether or not a timer instance supports a 32 bits counter.
2512 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2513 * output channel 4 is supported by a timer instance.
2514 * @rmtoll CCR4 CCR4 LL_TIM_OC_GetCompareCH4
2515 * @param TIMx Timer instance
2516 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2517 */
2518 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH4(TIM_TypeDef *TIMx)
2519 {
2520 return (uint32_t)(READ_REG(TIMx->CCR4));
2521 }
2522
2523 /**
2524 * @brief Get compare value (TIMx_CCR5) set for output channel 5.
2525 * @note Macro @ref IS_TIM_CC5_INSTANCE(TIMx) can be used to check whether or not
2526 * output channel 5 is supported by a timer instance.
2527 * @rmtoll CCR5 CCR5 LL_TIM_OC_GetCompareCH5
2528 * @param TIMx Timer instance
2529 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2530 */
2531 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH5(TIM_TypeDef *TIMx)
2532 {
2533 return (uint32_t)(READ_REG(TIMx->CCR5));
2534 }
2535
2536 /**
2537 * @brief Get compare value (TIMx_CCR6) set for output channel 6.
2538 * @note Macro @ref IS_TIM_CC6_INSTANCE(TIMx) can be used to check whether or not
2539 * output channel 6 is supported by a timer instance.
2540 * @rmtoll CCR6 CCR6 LL_TIM_OC_GetCompareCH6
2541 * @param TIMx Timer instance
2542 * @retval CompareValue (between Min_Data=0 and Max_Data=65535)
2543 */
2544 __STATIC_INLINE uint32_t LL_TIM_OC_GetCompareCH6(TIM_TypeDef *TIMx)
2545 {
2546 return (uint32_t)(READ_REG(TIMx->CCR6));
2547 }
2548
2549 /**
2550 * @brief Select on which reference signal the OC5REF is combined to.
2551 * @note Macro @ref IS_TIM_COMBINED3PHASEPWM_INSTANCE(TIMx) can be used to check
2552 * whether or not a timer instance supports the combined 3-phase PWM mode.
2553 * @rmtoll CCR5 GC5C3 LL_TIM_SetCH5CombinedChannels\n
2554 * CCR5 GC5C2 LL_TIM_SetCH5CombinedChannels\n
2555 * CCR5 GC5C1 LL_TIM_SetCH5CombinedChannels
2556 * @param TIMx Timer instance
2557 * @param GroupCH5 This parameter can be one of the following values:
2558 * @arg @ref LL_TIM_GROUPCH5_NONE
2559 * @arg @ref LL_TIM_GROUPCH5_OC1REFC
2560 * @arg @ref LL_TIM_GROUPCH5_OC2REFC
2561 * @arg @ref LL_TIM_GROUPCH5_OC3REFC
2562 * @retval None
2563 */
2564 __STATIC_INLINE void LL_TIM_SetCH5CombinedChannels(TIM_TypeDef *TIMx, uint32_t GroupCH5)
2565 {
2566 MODIFY_REG(TIMx->CCR5, TIM_CCR5_CCR5, GroupCH5);
2567 }
2568
2569 /**
2570 * @}
2571 */
2572
2573 /** @defgroup TIM_LL_EF_Input_Channel Input channel configuration
2574 * @{
2575 */
2576 /**
2577 * @brief Configure input channel.
2578 * @rmtoll CCMR1 CC1S LL_TIM_IC_Config\n
2579 * CCMR1 IC1PSC LL_TIM_IC_Config\n
2580 * CCMR1 IC1F LL_TIM_IC_Config\n
2581 * CCMR1 CC2S LL_TIM_IC_Config\n
2582 * CCMR1 IC2PSC LL_TIM_IC_Config\n
2583 * CCMR1 IC2F LL_TIM_IC_Config\n
2584 * CCMR2 CC3S LL_TIM_IC_Config\n
2585 * CCMR2 IC3PSC LL_TIM_IC_Config\n
2586 * CCMR2 IC3F LL_TIM_IC_Config\n
2587 * CCMR2 CC4S LL_TIM_IC_Config\n
2588 * CCMR2 IC4PSC LL_TIM_IC_Config\n
2589 * CCMR2 IC4F LL_TIM_IC_Config\n
2590 * CCER CC1P LL_TIM_IC_Config\n
2591 * CCER CC1NP LL_TIM_IC_Config\n
2592 * CCER CC2P LL_TIM_IC_Config\n
2593 * CCER CC2NP LL_TIM_IC_Config\n
2594 * CCER CC3P LL_TIM_IC_Config\n
2595 * CCER CC3NP LL_TIM_IC_Config\n
2596 * CCER CC4P LL_TIM_IC_Config\n
2597 * CCER CC4NP LL_TIM_IC_Config
2598 * @param TIMx Timer instance
2599 * @param Channel This parameter can be one of the following values:
2600 * @arg @ref LL_TIM_CHANNEL_CH1
2601 * @arg @ref LL_TIM_CHANNEL_CH2
2602 * @arg @ref LL_TIM_CHANNEL_CH3
2603 * @arg @ref LL_TIM_CHANNEL_CH4
2604 * @param Configuration This parameter must be a combination of all the following values:
2605 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI or @ref LL_TIM_ACTIVEINPUT_INDIRECTTI or @ref LL_TIM_ACTIVEINPUT_TRC
2606 * @arg @ref LL_TIM_ICPSC_DIV1 or ... or @ref LL_TIM_ICPSC_DIV8
2607 * @arg @ref LL_TIM_IC_FILTER_FDIV1 or ... or @ref LL_TIM_IC_FILTER_FDIV32_N8
2608 * @arg @ref LL_TIM_IC_POLARITY_RISING or @ref LL_TIM_IC_POLARITY_FALLING or @ref LL_TIM_IC_POLARITY_BOTHEDGE
2609 * @retval None
2610 */
2611 __STATIC_INLINE void LL_TIM_IC_Config(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t Configuration)
2612 {
2613 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2614 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2615 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]),
2616 ((Configuration >> 16U) & (TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC | TIM_CCMR1_CC1S)) << SHIFT_TAB_ICxx[iChannel]);
2617 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2618 (Configuration & (TIM_CCER_CC1NP | TIM_CCER_CC1P)) << SHIFT_TAB_CCxP[iChannel]);
2619 }
2620
2621 /**
2622 * @brief Set the active input.
2623 * @rmtoll CCMR1 CC1S LL_TIM_IC_SetActiveInput\n
2624 * CCMR1 CC2S LL_TIM_IC_SetActiveInput\n
2625 * CCMR2 CC3S LL_TIM_IC_SetActiveInput\n
2626 * CCMR2 CC4S LL_TIM_IC_SetActiveInput
2627 * @param TIMx Timer instance
2628 * @param Channel This parameter can be one of the following values:
2629 * @arg @ref LL_TIM_CHANNEL_CH1
2630 * @arg @ref LL_TIM_CHANNEL_CH2
2631 * @arg @ref LL_TIM_CHANNEL_CH3
2632 * @arg @ref LL_TIM_CHANNEL_CH4
2633 * @param ICActiveInput This parameter can be one of the following values:
2634 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2635 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2636 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2637 * @retval None
2638 */
2639 __STATIC_INLINE void LL_TIM_IC_SetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICActiveInput)
2640 {
2641 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2642 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2643 MODIFY_REG(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel]), (ICActiveInput >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2644 }
2645
2646 /**
2647 * @brief Get the current active input.
2648 * @rmtoll CCMR1 CC1S LL_TIM_IC_GetActiveInput\n
2649 * CCMR1 CC2S LL_TIM_IC_GetActiveInput\n
2650 * CCMR2 CC3S LL_TIM_IC_GetActiveInput\n
2651 * CCMR2 CC4S LL_TIM_IC_GetActiveInput
2652 * @param TIMx Timer instance
2653 * @param Channel This parameter can be one of the following values:
2654 * @arg @ref LL_TIM_CHANNEL_CH1
2655 * @arg @ref LL_TIM_CHANNEL_CH2
2656 * @arg @ref LL_TIM_CHANNEL_CH3
2657 * @arg @ref LL_TIM_CHANNEL_CH4
2658 * @retval Returned value can be one of the following values:
2659 * @arg @ref LL_TIM_ACTIVEINPUT_DIRECTTI
2660 * @arg @ref LL_TIM_ACTIVEINPUT_INDIRECTTI
2661 * @arg @ref LL_TIM_ACTIVEINPUT_TRC
2662 */
2663 __STATIC_INLINE uint32_t LL_TIM_IC_GetActiveInput(TIM_TypeDef *TIMx, uint32_t Channel)
2664 {
2665 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2666 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2667 return ((READ_BIT(*pReg, ((TIM_CCMR1_CC1S) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2668 }
2669
2670 /**
2671 * @brief Set the prescaler of input channel.
2672 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_SetPrescaler\n
2673 * CCMR1 IC2PSC LL_TIM_IC_SetPrescaler\n
2674 * CCMR2 IC3PSC LL_TIM_IC_SetPrescaler\n
2675 * CCMR2 IC4PSC LL_TIM_IC_SetPrescaler
2676 * @param TIMx Timer instance
2677 * @param Channel This parameter can be one of the following values:
2678 * @arg @ref LL_TIM_CHANNEL_CH1
2679 * @arg @ref LL_TIM_CHANNEL_CH2
2680 * @arg @ref LL_TIM_CHANNEL_CH3
2681 * @arg @ref LL_TIM_CHANNEL_CH4
2682 * @param ICPrescaler This parameter can be one of the following values:
2683 * @arg @ref LL_TIM_ICPSC_DIV1
2684 * @arg @ref LL_TIM_ICPSC_DIV2
2685 * @arg @ref LL_TIM_ICPSC_DIV4
2686 * @arg @ref LL_TIM_ICPSC_DIV8
2687 * @retval None
2688 */
2689 __STATIC_INLINE void LL_TIM_IC_SetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPrescaler)
2690 {
2691 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2692 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2693 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel]), (ICPrescaler >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2694 }
2695
2696 /**
2697 * @brief Get the current prescaler value acting on an input channel.
2698 * @rmtoll CCMR1 IC1PSC LL_TIM_IC_GetPrescaler\n
2699 * CCMR1 IC2PSC LL_TIM_IC_GetPrescaler\n
2700 * CCMR2 IC3PSC LL_TIM_IC_GetPrescaler\n
2701 * CCMR2 IC4PSC LL_TIM_IC_GetPrescaler
2702 * @param TIMx Timer instance
2703 * @param Channel This parameter can be one of the following values:
2704 * @arg @ref LL_TIM_CHANNEL_CH1
2705 * @arg @ref LL_TIM_CHANNEL_CH2
2706 * @arg @ref LL_TIM_CHANNEL_CH3
2707 * @arg @ref LL_TIM_CHANNEL_CH4
2708 * @retval Returned value can be one of the following values:
2709 * @arg @ref LL_TIM_ICPSC_DIV1
2710 * @arg @ref LL_TIM_ICPSC_DIV2
2711 * @arg @ref LL_TIM_ICPSC_DIV4
2712 * @arg @ref LL_TIM_ICPSC_DIV8
2713 */
2714 __STATIC_INLINE uint32_t LL_TIM_IC_GetPrescaler(TIM_TypeDef *TIMx, uint32_t Channel)
2715 {
2716 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2717 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2718 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1PSC) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2719 }
2720
2721 /**
2722 * @brief Set the input filter duration.
2723 * @rmtoll CCMR1 IC1F LL_TIM_IC_SetFilter\n
2724 * CCMR1 IC2F LL_TIM_IC_SetFilter\n
2725 * CCMR2 IC3F LL_TIM_IC_SetFilter\n
2726 * CCMR2 IC4F LL_TIM_IC_SetFilter
2727 * @param TIMx Timer instance
2728 * @param Channel This parameter can be one of the following values:
2729 * @arg @ref LL_TIM_CHANNEL_CH1
2730 * @arg @ref LL_TIM_CHANNEL_CH2
2731 * @arg @ref LL_TIM_CHANNEL_CH3
2732 * @arg @ref LL_TIM_CHANNEL_CH4
2733 * @param ICFilter This parameter can be one of the following values:
2734 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2735 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2736 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2737 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2738 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2739 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2740 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2741 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2742 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2743 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2744 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2745 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2746 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2747 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2748 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2749 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2750 * @retval None
2751 */
2752 __STATIC_INLINE void LL_TIM_IC_SetFilter(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICFilter)
2753 {
2754 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2755 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2756 MODIFY_REG(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel]), (ICFilter >> 16U) << SHIFT_TAB_ICxx[iChannel]);
2757 }
2758
2759 /**
2760 * @brief Get the input filter duration.
2761 * @rmtoll CCMR1 IC1F LL_TIM_IC_GetFilter\n
2762 * CCMR1 IC2F LL_TIM_IC_GetFilter\n
2763 * CCMR2 IC3F LL_TIM_IC_GetFilter\n
2764 * CCMR2 IC4F LL_TIM_IC_GetFilter
2765 * @param TIMx Timer instance
2766 * @param Channel This parameter can be one of the following values:
2767 * @arg @ref LL_TIM_CHANNEL_CH1
2768 * @arg @ref LL_TIM_CHANNEL_CH2
2769 * @arg @ref LL_TIM_CHANNEL_CH3
2770 * @arg @ref LL_TIM_CHANNEL_CH4
2771 * @retval Returned value can be one of the following values:
2772 * @arg @ref LL_TIM_IC_FILTER_FDIV1
2773 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N2
2774 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N4
2775 * @arg @ref LL_TIM_IC_FILTER_FDIV1_N8
2776 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N6
2777 * @arg @ref LL_TIM_IC_FILTER_FDIV2_N8
2778 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N6
2779 * @arg @ref LL_TIM_IC_FILTER_FDIV4_N8
2780 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N6
2781 * @arg @ref LL_TIM_IC_FILTER_FDIV8_N8
2782 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N5
2783 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N6
2784 * @arg @ref LL_TIM_IC_FILTER_FDIV16_N8
2785 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N5
2786 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N6
2787 * @arg @ref LL_TIM_IC_FILTER_FDIV32_N8
2788 */
2789 __STATIC_INLINE uint32_t LL_TIM_IC_GetFilter(TIM_TypeDef *TIMx, uint32_t Channel)
2790 {
2791 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2792 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->CCMR1) + OFFSET_TAB_CCMRx[iChannel]));
2793 return ((READ_BIT(*pReg, ((TIM_CCMR1_IC1F) << SHIFT_TAB_ICxx[iChannel])) >> SHIFT_TAB_ICxx[iChannel]) << 16U);
2794 }
2795
2796 /**
2797 * @brief Set the input channel polarity.
2798 * @rmtoll CCER CC1P LL_TIM_IC_SetPolarity\n
2799 * CCER CC1NP LL_TIM_IC_SetPolarity\n
2800 * CCER CC2P LL_TIM_IC_SetPolarity\n
2801 * CCER CC2NP LL_TIM_IC_SetPolarity\n
2802 * CCER CC3P LL_TIM_IC_SetPolarity\n
2803 * CCER CC3NP LL_TIM_IC_SetPolarity\n
2804 * CCER CC4P LL_TIM_IC_SetPolarity\n
2805 * CCER CC4NP LL_TIM_IC_SetPolarity
2806 * @param TIMx Timer instance
2807 * @param Channel This parameter can be one of the following values:
2808 * @arg @ref LL_TIM_CHANNEL_CH1
2809 * @arg @ref LL_TIM_CHANNEL_CH2
2810 * @arg @ref LL_TIM_CHANNEL_CH3
2811 * @arg @ref LL_TIM_CHANNEL_CH4
2812 * @param ICPolarity This parameter can be one of the following values:
2813 * @arg @ref LL_TIM_IC_POLARITY_RISING
2814 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2815 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2816 * @retval None
2817 */
2818 __STATIC_INLINE void LL_TIM_IC_SetPolarity(TIM_TypeDef *TIMx, uint32_t Channel, uint32_t ICPolarity)
2819 {
2820 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2821 MODIFY_REG(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel]),
2822 ICPolarity << SHIFT_TAB_CCxP[iChannel]);
2823 }
2824
2825 /**
2826 * @brief Get the current input channel polarity.
2827 * @rmtoll CCER CC1P LL_TIM_IC_GetPolarity\n
2828 * CCER CC1NP LL_TIM_IC_GetPolarity\n
2829 * CCER CC2P LL_TIM_IC_GetPolarity\n
2830 * CCER CC2NP LL_TIM_IC_GetPolarity\n
2831 * CCER CC3P LL_TIM_IC_GetPolarity\n
2832 * CCER CC3NP LL_TIM_IC_GetPolarity\n
2833 * CCER CC4P LL_TIM_IC_GetPolarity\n
2834 * CCER CC4NP LL_TIM_IC_GetPolarity
2835 * @param TIMx Timer instance
2836 * @param Channel This parameter can be one of the following values:
2837 * @arg @ref LL_TIM_CHANNEL_CH1
2838 * @arg @ref LL_TIM_CHANNEL_CH2
2839 * @arg @ref LL_TIM_CHANNEL_CH3
2840 * @arg @ref LL_TIM_CHANNEL_CH4
2841 * @retval Returned value can be one of the following values:
2842 * @arg @ref LL_TIM_IC_POLARITY_RISING
2843 * @arg @ref LL_TIM_IC_POLARITY_FALLING
2844 * @arg @ref LL_TIM_IC_POLARITY_BOTHEDGE
2845 */
2846 __STATIC_INLINE uint32_t LL_TIM_IC_GetPolarity(TIM_TypeDef *TIMx, uint32_t Channel)
2847 {
2848 register uint8_t iChannel = TIM_GET_CHANNEL_INDEX(Channel);
2849 return (READ_BIT(TIMx->CCER, ((TIM_CCER_CC1NP | TIM_CCER_CC1P) << SHIFT_TAB_CCxP[iChannel])) >>
2850 SHIFT_TAB_CCxP[iChannel]);
2851 }
2852
2853 /**
2854 * @brief Connect the TIMx_CH1, CH2 and CH3 pins to the TI1 input (XOR combination).
2855 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2856 * a timer instance provides an XOR input.
2857 * @rmtoll CR2 TI1S LL_TIM_IC_EnableXORCombination
2858 * @param TIMx Timer instance
2859 * @retval None
2860 */
2861 __STATIC_INLINE void LL_TIM_IC_EnableXORCombination(TIM_TypeDef *TIMx)
2862 {
2863 SET_BIT(TIMx->CR2, TIM_CR2_TI1S);
2864 }
2865
2866 /**
2867 * @brief Disconnect the TIMx_CH1, CH2 and CH3 pins from the TI1 input.
2868 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2869 * a timer instance provides an XOR input.
2870 * @rmtoll CR2 TI1S LL_TIM_IC_DisableXORCombination
2871 * @param TIMx Timer instance
2872 * @retval None
2873 */
2874 __STATIC_INLINE void LL_TIM_IC_DisableXORCombination(TIM_TypeDef *TIMx)
2875 {
2876 CLEAR_BIT(TIMx->CR2, TIM_CR2_TI1S);
2877 }
2878
2879 /**
2880 * @brief Indicates whether the TIMx_CH1, CH2 and CH3 pins are connectected to the TI1 input.
2881 * @note Macro @ref IS_TIM_XOR_INSTANCE(TIMx) can be used to check whether or not
2882 * a timer instance provides an XOR input.
2883 * @rmtoll CR2 TI1S LL_TIM_IC_IsEnabledXORCombination
2884 * @param TIMx Timer instance
2885 * @retval State of bit (1 or 0).
2886 */
2887 __STATIC_INLINE uint32_t LL_TIM_IC_IsEnabledXORCombination(TIM_TypeDef *TIMx)
2888 {
2889 return (READ_BIT(TIMx->CR2, TIM_CR2_TI1S) == (TIM_CR2_TI1S));
2890 }
2891
2892 /**
2893 * @brief Get captured value for input channel 1.
2894 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2895 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2896 * whether or not a timer instance supports a 32 bits counter.
2897 * @note Macro @ref IS_TIM_CC1_INSTANCE(TIMx) can be used to check whether or not
2898 * input channel 1 is supported by a timer instance.
2899 * @rmtoll CCR1 CCR1 LL_TIM_IC_GetCaptureCH1
2900 * @param TIMx Timer instance
2901 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2902 */
2903 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH1(TIM_TypeDef *TIMx)
2904 {
2905 return (uint32_t)(READ_REG(TIMx->CCR1));
2906 }
2907
2908 /**
2909 * @brief Get captured value for input channel 2.
2910 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2911 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2912 * whether or not a timer instance supports a 32 bits counter.
2913 * @note Macro @ref IS_TIM_CC2_INSTANCE(TIMx) can be used to check whether or not
2914 * input channel 2 is supported by a timer instance.
2915 * @rmtoll CCR2 CCR2 LL_TIM_IC_GetCaptureCH2
2916 * @param TIMx Timer instance
2917 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2918 */
2919 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH2(TIM_TypeDef *TIMx)
2920 {
2921 return (uint32_t)(READ_REG(TIMx->CCR2));
2922 }
2923
2924 /**
2925 * @brief Get captured value for input channel 3.
2926 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2927 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2928 * whether or not a timer instance supports a 32 bits counter.
2929 * @note Macro @ref IS_TIM_CC3_INSTANCE(TIMx) can be used to check whether or not
2930 * input channel 3 is supported by a timer instance.
2931 * @rmtoll CCR3 CCR3 LL_TIM_IC_GetCaptureCH3
2932 * @param TIMx Timer instance
2933 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2934 */
2935 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH3(TIM_TypeDef *TIMx)
2936 {
2937 return (uint32_t)(READ_REG(TIMx->CCR3));
2938 }
2939
2940 /**
2941 * @brief Get captured value for input channel 4.
2942 * @note In 32-bit timer implementations returned captured value can be between 0x00000000 and 0xFFFFFFFF.
2943 * @note Macro @ref IS_TIM_32B_COUNTER_INSTANCE(TIMx) can be used to check
2944 * whether or not a timer instance supports a 32 bits counter.
2945 * @note Macro @ref IS_TIM_CC4_INSTANCE(TIMx) can be used to check whether or not
2946 * input channel 4 is supported by a timer instance.
2947 * @rmtoll CCR4 CCR4 LL_TIM_IC_GetCaptureCH4
2948 * @param TIMx Timer instance
2949 * @retval CapturedValue (between Min_Data=0 and Max_Data=65535)
2950 */
2951 __STATIC_INLINE uint32_t LL_TIM_IC_GetCaptureCH4(TIM_TypeDef *TIMx)
2952 {
2953 return (uint32_t)(READ_REG(TIMx->CCR4));
2954 }
2955
2956 /**
2957 * @}
2958 */
2959
2960 /** @defgroup TIM_LL_EF_Clock_Selection Counter clock selection
2961 * @{
2962 */
2963 /**
2964 * @brief Enable external clock mode 2.
2965 * @note When external clock mode 2 is enabled the counter is clocked by any active edge on the ETRF signal.
2966 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2967 * whether or not a timer instance supports external clock mode2.
2968 * @rmtoll SMCR ECE LL_TIM_EnableExternalClock
2969 * @param TIMx Timer instance
2970 * @retval None
2971 */
2972 __STATIC_INLINE void LL_TIM_EnableExternalClock(TIM_TypeDef *TIMx)
2973 {
2974 SET_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2975 }
2976
2977 /**
2978 * @brief Disable external clock mode 2.
2979 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2980 * whether or not a timer instance supports external clock mode2.
2981 * @rmtoll SMCR ECE LL_TIM_DisableExternalClock
2982 * @param TIMx Timer instance
2983 * @retval None
2984 */
2985 __STATIC_INLINE void LL_TIM_DisableExternalClock(TIM_TypeDef *TIMx)
2986 {
2987 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_ECE);
2988 }
2989
2990 /**
2991 * @brief Indicate whether external clock mode 2 is enabled.
2992 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
2993 * whether or not a timer instance supports external clock mode2.
2994 * @rmtoll SMCR ECE LL_TIM_IsEnabledExternalClock
2995 * @param TIMx Timer instance
2996 * @retval State of bit (1 or 0).
2997 */
2998 __STATIC_INLINE uint32_t LL_TIM_IsEnabledExternalClock(TIM_TypeDef *TIMx)
2999 {
3000 return (READ_BIT(TIMx->SMCR, TIM_SMCR_ECE) == (TIM_SMCR_ECE));
3001 }
3002
3003 /**
3004 * @brief Set the clock source of the counter clock.
3005 * @note when selected clock source is external clock mode 1, the timer input
3006 * the external clock is applied is selected by calling the @ref LL_TIM_SetTriggerInput()
3007 * function. This timer input must be configured by calling
3008 * the @ref LL_TIM_IC_Config() function.
3009 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(TIMx) can be used to check
3010 * whether or not a timer instance supports external clock mode1.
3011 * @note Macro @ref IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(TIMx) can be used to check
3012 * whether or not a timer instance supports external clock mode2.
3013 * @rmtoll SMCR SMS LL_TIM_SetClockSource\n
3014 * SMCR ECE LL_TIM_SetClockSource
3015 * @param TIMx Timer instance
3016 * @param ClockSource This parameter can be one of the following values:
3017 * @arg @ref LL_TIM_CLOCKSOURCE_INTERNAL
3018 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE1
3019 * @arg @ref LL_TIM_CLOCKSOURCE_EXT_MODE2
3020 * @retval None
3021 */
3022 __STATIC_INLINE void LL_TIM_SetClockSource(TIM_TypeDef *TIMx, uint32_t ClockSource)
3023 {
3024 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS | TIM_SMCR_ECE, ClockSource);
3025 }
3026
3027 /**
3028 * @brief Set the encoder interface mode.
3029 * @note Macro @ref IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx) can be used to check
3030 * whether or not a timer instance supports the encoder mode.
3031 * @rmtoll SMCR SMS LL_TIM_SetEncoderMode
3032 * @param TIMx Timer instance
3033 * @param EncoderMode This parameter can be one of the following values:
3034 * @arg @ref LL_TIM_ENCODERMODE_X2_TI1
3035 * @arg @ref LL_TIM_ENCODERMODE_X2_TI2
3036 * @arg @ref LL_TIM_ENCODERMODE_X4_TI12
3037 * @retval None
3038 */
3039 __STATIC_INLINE void LL_TIM_SetEncoderMode(TIM_TypeDef *TIMx, uint32_t EncoderMode)
3040 {
3041 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, EncoderMode);
3042 }
3043
3044 /**
3045 * @}
3046 */
3047
3048 /** @defgroup TIM_LL_EF_Timer_Synchronization Timer synchronisation configuration
3049 * @{
3050 */
3051 /**
3052 * @brief Set the trigger output (TRGO) used for timer synchronization .
3053 * @note Macro @ref IS_TIM_MASTER_INSTANCE(TIMx) can be used to check
3054 * whether or not a timer instance can operate as a master timer.
3055 * @rmtoll CR2 MMS LL_TIM_SetTriggerOutput
3056 * @param TIMx Timer instance
3057 * @param TimerSynchronization This parameter can be one of the following values:
3058 * @arg @ref LL_TIM_TRGO_RESET
3059 * @arg @ref LL_TIM_TRGO_ENABLE
3060 * @arg @ref LL_TIM_TRGO_UPDATE
3061 * @arg @ref LL_TIM_TRGO_CC1IF
3062 * @arg @ref LL_TIM_TRGO_OC1REF
3063 * @arg @ref LL_TIM_TRGO_OC2REF
3064 * @arg @ref LL_TIM_TRGO_OC3REF
3065 * @arg @ref LL_TIM_TRGO_OC4REF
3066 * @retval None
3067 */
3068 __STATIC_INLINE void LL_TIM_SetTriggerOutput(TIM_TypeDef *TIMx, uint32_t TimerSynchronization)
3069 {
3070 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS, TimerSynchronization);
3071 }
3072
3073 /**
3074 * @brief Set the trigger output 2 (TRGO2) used for ADC synchronization .
3075 * @note Macro @ref IS_TIM_TRGO2_INSTANCE(TIMx) can be used to check
3076 * whether or not a timer instance can be used for ADC synchronization.
3077 * @rmtoll CR2 MMS2 LL_TIM_SetTriggerOutput2
3078 * @param TIMx Timer Instance
3079 * @param ADCSynchronization This parameter can be one of the following values:
3080 * @arg @ref LL_TIM_TRGO2_RESET
3081 * @arg @ref LL_TIM_TRGO2_ENABLE
3082 * @arg @ref LL_TIM_TRGO2_UPDATE
3083 * @arg @ref LL_TIM_TRGO2_CC1F
3084 * @arg @ref LL_TIM_TRGO2_OC1
3085 * @arg @ref LL_TIM_TRGO2_OC2
3086 * @arg @ref LL_TIM_TRGO2_OC3
3087 * @arg @ref LL_TIM_TRGO2_OC4
3088 * @arg @ref LL_TIM_TRGO2_OC5
3089 * @arg @ref LL_TIM_TRGO2_OC6
3090 * @arg @ref LL_TIM_TRGO2_OC4_RISINGFALLING
3091 * @arg @ref LL_TIM_TRGO2_OC6_RISINGFALLING
3092 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_RISING
3093 * @arg @ref LL_TIM_TRGO2_OC4_RISING_OC6_FALLING
3094 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_RISING
3095 * @arg @ref LL_TIM_TRGO2_OC5_RISING_OC6_FALLING
3096 * @retval None
3097 */
3098 __STATIC_INLINE void LL_TIM_SetTriggerOutput2(TIM_TypeDef *TIMx, uint32_t ADCSynchronization)
3099 {
3100 MODIFY_REG(TIMx->CR2, TIM_CR2_MMS2, ADCSynchronization);
3101 }
3102
3103 /**
3104 * @brief Set the synchronization mode of a slave timer.
3105 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3106 * a timer instance can operate as a slave timer.
3107 * @rmtoll SMCR SMS LL_TIM_SetSlaveMode
3108 * @param TIMx Timer instance
3109 * @param SlaveMode This parameter can be one of the following values:
3110 * @arg @ref LL_TIM_SLAVEMODE_DISABLED
3111 * @arg @ref LL_TIM_SLAVEMODE_RESET
3112 * @arg @ref LL_TIM_SLAVEMODE_GATED
3113 * @arg @ref LL_TIM_SLAVEMODE_TRIGGER
3114 * @arg @ref LL_TIM_SLAVEMODE_COMBINED_RESETTRIGGER
3115 * @retval None
3116 */
3117 __STATIC_INLINE void LL_TIM_SetSlaveMode(TIM_TypeDef *TIMx, uint32_t SlaveMode)
3118 {
3119 MODIFY_REG(TIMx->SMCR, TIM_SMCR_SMS, SlaveMode);
3120 }
3121
3122 /**
3123 * @brief Set the selects the trigger input to be used to synchronize the counter.
3124 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3125 * a timer instance can operate as a slave timer.
3126 * @rmtoll SMCR TS LL_TIM_SetTriggerInput
3127 * @param TIMx Timer instance
3128 * @param TriggerInput This parameter can be one of the following values:
3129 * @arg @ref LL_TIM_TS_ITR0
3130 * @arg @ref LL_TIM_TS_ITR1
3131 * @arg @ref LL_TIM_TS_ITR2
3132 * @arg @ref LL_TIM_TS_ITR3
3133 * @arg @ref LL_TIM_TS_TI1F_ED
3134 * @arg @ref LL_TIM_TS_TI1FP1
3135 * @arg @ref LL_TIM_TS_TI2FP2
3136 * @arg @ref LL_TIM_TS_ETRF
3137 * @retval None
3138 */
3139 __STATIC_INLINE void LL_TIM_SetTriggerInput(TIM_TypeDef *TIMx, uint32_t TriggerInput)
3140 {
3141 MODIFY_REG(TIMx->SMCR, TIM_SMCR_TS, TriggerInput);
3142 }
3143
3144 /**
3145 * @brief Enable the Master/Slave mode.
3146 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3147 * a timer instance can operate as a slave timer.
3148 * @rmtoll SMCR MSM LL_TIM_EnableMasterSlaveMode
3149 * @param TIMx Timer instance
3150 * @retval None
3151 */
3152 __STATIC_INLINE void LL_TIM_EnableMasterSlaveMode(TIM_TypeDef *TIMx)
3153 {
3154 SET_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3155 }
3156
3157 /**
3158 * @brief Disable the Master/Slave mode.
3159 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3160 * a timer instance can operate as a slave timer.
3161 * @rmtoll SMCR MSM LL_TIM_DisableMasterSlaveMode
3162 * @param TIMx Timer instance
3163 * @retval None
3164 */
3165 __STATIC_INLINE void LL_TIM_DisableMasterSlaveMode(TIM_TypeDef *TIMx)
3166 {
3167 CLEAR_BIT(TIMx->SMCR, TIM_SMCR_MSM);
3168 }
3169
3170 /**
3171 * @brief Indicates whether the Master/Slave mode is enabled.
3172 * @note Macro @ref IS_TIM_SLAVE_INSTANCE(TIMx) can be used to check whether or not
3173 * a timer instance can operate as a slave timer.
3174 * @rmtoll SMCR MSM LL_TIM_IsEnabledMasterSlaveMode
3175 * @param TIMx Timer instance
3176 * @retval State of bit (1 or 0).
3177 */
3178 __STATIC_INLINE uint32_t LL_TIM_IsEnabledMasterSlaveMode(TIM_TypeDef *TIMx)
3179 {
3180 return (READ_BIT(TIMx->SMCR, TIM_SMCR_MSM) == (TIM_SMCR_MSM));
3181 }
3182
3183 /**
3184 * @brief Configure the external trigger (ETR) input.
3185 * @note Macro @ref IS_TIM_ETR_INSTANCE(TIMx) can be used to check whether or not
3186 * a timer instance provides an external trigger input.
3187 * @rmtoll SMCR ETP LL_TIM_ConfigETR\n
3188 * SMCR ETPS LL_TIM_ConfigETR\n
3189 * SMCR ETF LL_TIM_ConfigETR
3190 * @param TIMx Timer instance
3191 * @param ETRPolarity This parameter can be one of the following values:
3192 * @arg @ref LL_TIM_ETR_POLARITY_NONINVERTED
3193 * @arg @ref LL_TIM_ETR_POLARITY_INVERTED
3194 * @param ETRPrescaler This parameter can be one of the following values:
3195 * @arg @ref LL_TIM_ETR_PRESCALER_DIV1
3196 * @arg @ref LL_TIM_ETR_PRESCALER_DIV2
3197 * @arg @ref LL_TIM_ETR_PRESCALER_DIV4
3198 * @arg @ref LL_TIM_ETR_PRESCALER_DIV8
3199 * @param ETRFilter This parameter can be one of the following values:
3200 * @arg @ref LL_TIM_ETR_FILTER_FDIV1
3201 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N2
3202 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N4
3203 * @arg @ref LL_TIM_ETR_FILTER_FDIV1_N8
3204 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N6
3205 * @arg @ref LL_TIM_ETR_FILTER_FDIV2_N8
3206 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N6
3207 * @arg @ref LL_TIM_ETR_FILTER_FDIV4_N8
3208 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N6
3209 * @arg @ref LL_TIM_ETR_FILTER_FDIV8_N8
3210 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N5
3211 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N6
3212 * @arg @ref LL_TIM_ETR_FILTER_FDIV16_N8
3213 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N5
3214 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N6
3215 * @arg @ref LL_TIM_ETR_FILTER_FDIV32_N8
3216 * @retval None
3217 */
3218 __STATIC_INLINE void LL_TIM_ConfigETR(TIM_TypeDef *TIMx, uint32_t ETRPolarity, uint32_t ETRPrescaler,
3219 uint32_t ETRFilter)
3220 {
3221 MODIFY_REG(TIMx->SMCR, TIM_SMCR_ETP | TIM_SMCR_ETPS | TIM_SMCR_ETF, ETRPolarity | ETRPrescaler | ETRFilter);
3222 }
3223
3224 /**
3225 * @}
3226 */
3227
3228 /** @defgroup TIM_LL_EF_Break_Function Break function configuration
3229 * @{
3230 */
3231 /**
3232 * @brief Enable the break function.
3233 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3234 * a timer instance provides a break input.
3235 * @rmtoll BDTR BKE LL_TIM_EnableBRK
3236 * @param TIMx Timer instance
3237 * @retval None
3238 */
3239 __STATIC_INLINE void LL_TIM_EnableBRK(TIM_TypeDef *TIMx)
3240 {
3241 SET_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3242 }
3243
3244 /**
3245 * @brief Disable the break function.
3246 * @rmtoll BDTR BKE LL_TIM_DisableBRK
3247 * @param TIMx Timer instance
3248 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3249 * a timer instance provides a break input.
3250 * @retval None
3251 */
3252 __STATIC_INLINE void LL_TIM_DisableBRK(TIM_TypeDef *TIMx)
3253 {
3254 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BKE);
3255 }
3256
3257 /**
3258 * @brief Configure the break input.
3259 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3260 * a timer instance provides a break input.
3261 * @rmtoll BDTR BKP LL_TIM_ConfigBRK\n
3262 * BDTR BKF LL_TIM_ConfigBRK
3263 * @param TIMx Timer instance
3264 * @param BreakPolarity This parameter can be one of the following values:
3265 * @arg @ref LL_TIM_BREAK_POLARITY_LOW
3266 * @arg @ref LL_TIM_BREAK_POLARITY_HIGH
3267 * @param BreakFilter This parameter can be one of the following values:
3268 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1
3269 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N2
3270 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N4
3271 * @arg @ref LL_TIM_BREAK_FILTER_FDIV1_N8
3272 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N6
3273 * @arg @ref LL_TIM_BREAK_FILTER_FDIV2_N8
3274 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N6
3275 * @arg @ref LL_TIM_BREAK_FILTER_FDIV4_N8
3276 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N6
3277 * @arg @ref LL_TIM_BREAK_FILTER_FDIV8_N8
3278 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N5
3279 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N6
3280 * @arg @ref LL_TIM_BREAK_FILTER_FDIV16_N8
3281 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N5
3282 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N6
3283 * @arg @ref LL_TIM_BREAK_FILTER_FDIV32_N8
3284 * @retval None
3285 */
3286 __STATIC_INLINE void LL_TIM_ConfigBRK(TIM_TypeDef *TIMx, uint32_t BreakPolarity, uint32_t BreakFilter)
3287 {
3288 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BKP | TIM_BDTR_BKF, BreakPolarity | BreakFilter);
3289 }
3290
3291 /**
3292 * @brief Enable the break 2 function.
3293 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3294 * a timer instance provides a second break input.
3295 * @rmtoll BDTR BK2E LL_TIM_EnableBRK2
3296 * @param TIMx Timer instance
3297 * @retval None
3298 */
3299 __STATIC_INLINE void LL_TIM_EnableBRK2(TIM_TypeDef *TIMx)
3300 {
3301 SET_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3302 }
3303
3304 /**
3305 * @brief Disable the break 2 function.
3306 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3307 * a timer instance provides a second break input.
3308 * @rmtoll BDTR BK2E LL_TIM_DisableBRK2
3309 * @param TIMx Timer instance
3310 * @retval None
3311 */
3312 __STATIC_INLINE void LL_TIM_DisableBRK2(TIM_TypeDef *TIMx)
3313 {
3314 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_BK2E);
3315 }
3316
3317 /**
3318 * @brief Configure the break 2 input.
3319 * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
3320 * a timer instance provides a second break input.
3321 * @rmtoll BDTR BK2P LL_TIM_ConfigBRK2\n
3322 * BDTR BK2F LL_TIM_ConfigBRK2
3323 * @param TIMx Timer instance
3324 * @param Break2Polarity This parameter can be one of the following values:
3325 * @arg @ref LL_TIM_BREAK2_POLARITY_LOW
3326 * @arg @ref LL_TIM_BREAK2_POLARITY_HIGH
3327 * @param Break2Filter This parameter can be one of the following values:
3328 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1
3329 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N2
3330 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N4
3331 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV1_N8
3332 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N6
3333 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV2_N8
3334 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N6
3335 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV4_N8
3336 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N6
3337 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV8_N8
3338 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N5
3339 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N6
3340 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV16_N8
3341 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N5
3342 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N6
3343 * @arg @ref LL_TIM_BREAK2_FILTER_FDIV32_N8
3344 * @retval None
3345 */
3346 __STATIC_INLINE void LL_TIM_ConfigBRK2(TIM_TypeDef *TIMx, uint32_t Break2Polarity, uint32_t Break2Filter)
3347 {
3348 MODIFY_REG(TIMx->BDTR, TIM_BDTR_BK2P | TIM_BDTR_BK2F, Break2Polarity | Break2Filter);
3349 }
3350
3351 /**
3352 * @brief Select the outputs off state (enabled v.s. disabled) in Idle and Run modes.
3353 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3354 * a timer instance provides a break input.
3355 * @rmtoll BDTR OSSI LL_TIM_SetOffStates\n
3356 * BDTR OSSR LL_TIM_SetOffStates
3357 * @param TIMx Timer instance
3358 * @param OffStateIdle This parameter can be one of the following values:
3359 * @arg @ref LL_TIM_OSSI_DISABLE
3360 * @arg @ref LL_TIM_OSSI_ENABLE
3361 * @param OffStateRun This parameter can be one of the following values:
3362 * @arg @ref LL_TIM_OSSR_DISABLE
3363 * @arg @ref LL_TIM_OSSR_ENABLE
3364 * @retval None
3365 */
3366 __STATIC_INLINE void LL_TIM_SetOffStates(TIM_TypeDef *TIMx, uint32_t OffStateIdle, uint32_t OffStateRun)
3367 {
3368 MODIFY_REG(TIMx->BDTR, TIM_BDTR_OSSI | TIM_BDTR_OSSR, OffStateIdle | OffStateRun);
3369 }
3370
3371 /**
3372 * @brief Enable automatic output (MOE can be set by software or automatically when a break input is active).
3373 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3374 * a timer instance provides a break input.
3375 * @rmtoll BDTR AOE LL_TIM_EnableAutomaticOutput
3376 * @param TIMx Timer instance
3377 * @retval None
3378 */
3379 __STATIC_INLINE void LL_TIM_EnableAutomaticOutput(TIM_TypeDef *TIMx)
3380 {
3381 SET_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3382 }
3383
3384 /**
3385 * @brief Disable automatic output (MOE can be set only by software).
3386 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3387 * a timer instance provides a break input.
3388 * @rmtoll BDTR AOE LL_TIM_DisableAutomaticOutput
3389 * @param TIMx Timer instance
3390 * @retval None
3391 */
3392 __STATIC_INLINE void LL_TIM_DisableAutomaticOutput(TIM_TypeDef *TIMx)
3393 {
3394 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_AOE);
3395 }
3396
3397 /**
3398 * @brief Indicate whether automatic output is enabled.
3399 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3400 * a timer instance provides a break input.
3401 * @rmtoll BDTR AOE LL_TIM_IsEnabledAutomaticOutput
3402 * @param TIMx Timer instance
3403 * @retval State of bit (1 or 0).
3404 */
3405 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAutomaticOutput(TIM_TypeDef *TIMx)
3406 {
3407 return (READ_BIT(TIMx->BDTR, TIM_BDTR_AOE) == (TIM_BDTR_AOE));
3408 }
3409
3410 /**
3411 * @brief Enable the outputs (set the MOE bit in TIMx_BDTR register).
3412 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3413 * software and is reset in case of break or break2 event
3414 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3415 * a timer instance provides a break input.
3416 * @rmtoll BDTR MOE LL_TIM_EnableAllOutputs
3417 * @param TIMx Timer instance
3418 * @retval None
3419 */
3420 __STATIC_INLINE void LL_TIM_EnableAllOutputs(TIM_TypeDef *TIMx)
3421 {
3422 SET_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3423 }
3424
3425 /**
3426 * @brief Disable the outputs (reset the MOE bit in TIMx_BDTR register).
3427 * @note The MOE bit in TIMx_BDTR register allows to enable /disable the outputs by
3428 * software and is reset in case of break or break2 event.
3429 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3430 * a timer instance provides a break input.
3431 * @rmtoll BDTR MOE LL_TIM_DisableAllOutputs
3432 * @param TIMx Timer instance
3433 * @retval None
3434 */
3435 __STATIC_INLINE void LL_TIM_DisableAllOutputs(TIM_TypeDef *TIMx)
3436 {
3437 CLEAR_BIT(TIMx->BDTR, TIM_BDTR_MOE);
3438 }
3439
3440 /**
3441 * @brief Indicates whether outputs are enabled.
3442 * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
3443 * a timer instance provides a break input.
3444 * @rmtoll BDTR MOE LL_TIM_IsEnabledAllOutputs
3445 * @param TIMx Timer instance
3446 * @retval State of bit (1 or 0).
3447 */
3448 __STATIC_INLINE uint32_t LL_TIM_IsEnabledAllOutputs(TIM_TypeDef *TIMx)
3449 {
3450 return (READ_BIT(TIMx->BDTR, TIM_BDTR_MOE) == (TIM_BDTR_MOE));
3451 }
3452
3453 #if defined(TIM_BREAK_INPUT_SUPPORT)
3454 /**
3455 * @brief Enable the signals connected to the designated timer break input.
3456 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3457 * or not a timer instance allows for break input selection.
3458 * @rmtoll AF1 BKINE LL_TIM_EnableBreakInputSource\n
3459 * AF1 BKDFBKE LL_TIM_EnableBreakInputSource\n
3460 * AF2 BK2INE LL_TIM_EnableBreakInputSource\n
3461 * AF2 BK2DFBKE LL_TIM_EnableBreakInputSource
3462 * @param TIMx Timer instance
3463 * @param BreakInput This parameter can be one of the following values:
3464 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3465 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3466 * @param Source This parameter can be one of the following values:
3467 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3468 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3469 * @retval None
3470 */
3471 __STATIC_INLINE void LL_TIM_EnableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3472 {
3473 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3474 SET_BIT(*pReg , Source);
3475 }
3476
3477 /**
3478 * @brief Disable the signals connected to the designated timer break input.
3479 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3480 * or not a timer instance allows for break input selection.
3481 * @rmtoll AF1 BKINE LL_TIM_DisableBreakInputSource\n
3482 * AF1 BKDFBKE LL_TIM_DisableBreakInputSource\n
3483 * AF2 BK2INE LL_TIM_DisableBreakInputSource\n
3484 * AF2 BK2DFBKE LL_TIM_DisableBreakInputSource
3485 * @param TIMx Timer instance
3486 * @param BreakInput This parameter can be one of the following values:
3487 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3488 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3489 * @param Source This parameter can be one of the following values:
3490 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3491 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3492 * @retval None
3493 */
3494 __STATIC_INLINE void LL_TIM_DisableBreakInputSource(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source)
3495 {
3496 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3497 CLEAR_BIT(*pReg, Source);
3498 }
3499
3500 /**
3501 * @brief Set the polarity of the break signal for the timer break input.
3502 * @note Macro @ref IS_TIM_BREAKSOURCE_INSTANCE(TIMx) can be used to check whether
3503 * or not a timer instance allows for break input selection.
3504 * @rmtoll AF1 BKINE LL_TIM_SetBreakInputSourcePolarity\n
3505 * AF1 BKDFBKE LL_TIM_SetBreakInputSourcePolarity\n
3506 * AF2 BK2INE LL_TIM_SetBreakInputSourcePolarity\n
3507 * AF2 BK2DFBKE LL_TIM_SetBreakInputSourcePolarity
3508 * @param TIMx Timer instance
3509 * @param BreakInput This parameter can be one of the following values:
3510 * @arg @ref LL_TIM_BREAK_INPUT_BKIN
3511 * @arg @ref LL_TIM_BREAK_INPUT_BKIN2
3512 * @param Source This parameter can be one of the following values:
3513 * @arg @ref LL_TIM_BKIN_SOURCE_BKIN
3514 * @arg @ref LL_TIM_BKIN_SOURCE_DF1BK
3515 * @param Polarity This parameter can be one of the following values:
3516 * @arg @ref LL_TIM_BKIN_POLARITY_LOW
3517 * @arg @ref LL_TIM_BKIN_POLARITY_HIGH
3518 * @retval None
3519 */
3520 __STATIC_INLINE void LL_TIM_SetBreakInputSourcePolarity(TIM_TypeDef *TIMx, uint32_t BreakInput, uint32_t Source,
3521 uint32_t Polarity)
3522 {
3523 register uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&TIMx->AF1) + BreakInput));
3524 MODIFY_REG(*pReg, (TIMx_AF1_BKINP << (TIM_POSITION_BRK_SOURCE)) , (Polarity << (TIM_POSITION_BRK_SOURCE)));
3525 }
3526 #endif /* TIM_BREAK_INPUT_SUPPORT */
3527 /**
3528 * @}
3529 */
3530
3531 /** @defgroup TIM_LL_EF_DMA_Burst_Mode DMA burst mode configuration
3532 * @{
3533 */
3534 /**
3535 * @brief Configures the timer DMA burst feature.
3536 * @note Macro @ref IS_TIM_DMABURST_INSTANCE(TIMx) can be used to check whether or
3537 * not a timer instance supports the DMA burst mode.
3538 * @rmtoll DCR DBL LL_TIM_ConfigDMABurst\n
3539 * DCR DBA LL_TIM_ConfigDMABurst
3540 * @param TIMx Timer instance
3541 * @param DMABurstBaseAddress This parameter can be one of the following values:
3542 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR1
3543 * @arg @ref LL_TIM_DMABURST_BASEADDR_CR2
3544 * @arg @ref LL_TIM_DMABURST_BASEADDR_SMCR
3545 * @arg @ref LL_TIM_DMABURST_BASEADDR_DIER
3546 * @arg @ref LL_TIM_DMABURST_BASEADDR_SR
3547 * @arg @ref LL_TIM_DMABURST_BASEADDR_EGR
3548 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR1
3549 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR2
3550 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCER
3551 * @arg @ref LL_TIM_DMABURST_BASEADDR_CNT
3552 * @arg @ref LL_TIM_DMABURST_BASEADDR_PSC
3553 * @arg @ref LL_TIM_DMABURST_BASEADDR_ARR
3554 * @arg @ref LL_TIM_DMABURST_BASEADDR_RCR
3555 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR1
3556 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR2
3557 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR3
3558 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR4
3559 * @arg @ref LL_TIM_DMABURST_BASEADDR_BDTR
3560 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCMR3
3561 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR5
3562 * @arg @ref LL_TIM_DMABURST_BASEADDR_CCR6
3563 * @arg @ref LL_TIM_DMABURST_BASEADDR_OR
3564 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF1
3565 * @arg @ref LL_TIM_DMABURST_BASEADDR_AF2
3566 * @param DMABurstLength This parameter can be one of the following values:
3567 * @arg @ref LL_TIM_DMABURST_LENGTH_1TRANSFER
3568 * @arg @ref LL_TIM_DMABURST_LENGTH_2TRANSFERS
3569 * @arg @ref LL_TIM_DMABURST_LENGTH_3TRANSFERS
3570 * @arg @ref LL_TIM_DMABURST_LENGTH_4TRANSFERS
3571 * @arg @ref LL_TIM_DMABURST_LENGTH_5TRANSFERS
3572 * @arg @ref LL_TIM_DMABURST_LENGTH_6TRANSFERS
3573 * @arg @ref LL_TIM_DMABURST_LENGTH_7TRANSFERS
3574 * @arg @ref LL_TIM_DMABURST_LENGTH_8TRANSFERS
3575 * @arg @ref LL_TIM_DMABURST_LENGTH_9TRANSFERS
3576 * @arg @ref LL_TIM_DMABURST_LENGTH_10TRANSFERS
3577 * @arg @ref LL_TIM_DMABURST_LENGTH_11TRANSFERS
3578 * @arg @ref LL_TIM_DMABURST_LENGTH_12TRANSFERS
3579 * @arg @ref LL_TIM_DMABURST_LENGTH_13TRANSFERS
3580 * @arg @ref LL_TIM_DMABURST_LENGTH_14TRANSFERS
3581 * @arg @ref LL_TIM_DMABURST_LENGTH_15TRANSFERS
3582 * @arg @ref LL_TIM_DMABURST_LENGTH_16TRANSFERS
3583 * @arg @ref LL_TIM_DMABURST_LENGTH_17TRANSFERS
3584 * @arg @ref LL_TIM_DMABURST_LENGTH_18TRANSFERS
3585 * @retval None
3586 */
3587 __STATIC_INLINE void LL_TIM_ConfigDMABurst(TIM_TypeDef *TIMx, uint32_t DMABurstBaseAddress, uint32_t DMABurstLength)
3588 {
3589 MODIFY_REG(TIMx->DCR, TIM_DCR_DBL | TIM_DCR_DBA, DMABurstBaseAddress | DMABurstLength);
3590 }
3591
3592 /**
3593 * @}
3594 */
3595
3596 /** @defgroup TIM_LL_EF_Timer_Inputs_Remapping Timer input remapping
3597 * @{
3598 */
3599 /**
3600 * @brief Remap TIM inputs (input channel, internal/external triggers).
3601 * @note Macro @ref IS_TIM_REMAP_INSTANCE(TIMx) can be used to check whether or not
3602 * a some timer inputs can be remapped.
3603 * @rmtoll TIM2_OR ITR1_RMP LL_TIM_SetRemap\n
3604 * TIM5_OR TI4_RMP LL_TIM_SetRemap\n
3605 * TIM11_OR TI1_RMP LL_TIM_SetRemap
3606 * @param TIMx Timer instance
3607 * @param Remap Remap param depends on the TIMx. Description available only
3608 * in CHM version of the User Manual (not in .pdf).
3609 * Otherwise see Reference Manual description of OR registers.
3610 *
3611 * Below description summarizes "Timer Instance" and "Remap" param combinations:
3612 *
3613 * TIM2: one of the following values
3614 *
3615 * ITR1_RMP can be one of the following values
3616 * @arg @ref LL_TIM_TIM2_ITR1_RMP_TIM8_TRGO
3617 * @arg @ref LL_TIM_TIM2_ITR1_RMP_ETH_PTP
3618 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_FS_SOF
3619 * @arg @ref LL_TIM_TIM2_ITR1_RMP_OTG_HS_SOF
3620 *
3621 * TIM5: one of the following values
3622 *
3623 * @arg @ref LL_TIM_TIM5_TI4_RMP_GPIO
3624 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSI
3625 * @arg @ref LL_TIM_TIM5_TI4_RMP_LSE
3626 * @arg @ref LL_TIM_TIM5_TI4_RMP_RTC
3627 *
3628 * TIM11: one of the following values
3629 *
3630 * @arg @ref LL_TIM_TIM11_TI1_RMP_GPIO
3631 * @arg @ref LL_TIM_TIM11_TI1_RMP_SPDIFRX
3632 * @arg @ref LL_TIM_TIM11_TI1_RMP_HSE
3633 * @arg @ref LL_TIM_TIM11_TI1_RMP_MCO1
3634 *
3635 * @retval None
3636 */
3637 __STATIC_INLINE void LL_TIM_SetRemap(TIM_TypeDef *TIMx, uint32_t Remap)
3638 {
3639 MODIFY_REG(TIMx->OR, (Remap >> TIMx_OR_RMP_SHIFT), (Remap & TIMx_OR_RMP_MASK));
3640 }
3641
3642 /**
3643 * @}
3644 */
3645
3646
3647 /** @defgroup TIM_LL_EF_FLAG_Management FLAG-Management
3648 * @{
3649 */
3650 /**
3651 * @brief Clear the update interrupt flag (UIF).
3652 * @rmtoll SR UIF LL_TIM_ClearFlag_UPDATE
3653 * @param TIMx Timer instance
3654 * @retval None
3655 */
3656 __STATIC_INLINE void LL_TIM_ClearFlag_UPDATE(TIM_TypeDef *TIMx)
3657 {
3658 WRITE_REG(TIMx->SR, ~(TIM_SR_UIF));
3659 }
3660
3661 /**
3662 * @brief Indicate whether update interrupt flag (UIF) is set (update interrupt is pending).
3663 * @rmtoll SR UIF LL_TIM_IsActiveFlag_UPDATE
3664 * @param TIMx Timer instance
3665 * @retval State of bit (1 or 0).
3666 */
3667 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_UPDATE(TIM_TypeDef *TIMx)
3668 {
3669 return (READ_BIT(TIMx->SR, TIM_SR_UIF) == (TIM_SR_UIF));
3670 }
3671
3672 /**
3673 * @brief Clear the Capture/Compare 1 interrupt flag (CC1F).
3674 * @rmtoll SR CC1IF LL_TIM_ClearFlag_CC1
3675 * @param TIMx Timer instance
3676 * @retval None
3677 */
3678 __STATIC_INLINE void LL_TIM_ClearFlag_CC1(TIM_TypeDef *TIMx)
3679 {
3680 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1IF));
3681 }
3682
3683 /**
3684 * @brief Indicate whether Capture/Compare 1 interrupt flag (CC1F) is set (Capture/Compare 1 interrupt is pending).
3685 * @rmtoll SR CC1IF LL_TIM_IsActiveFlag_CC1
3686 * @param TIMx Timer instance
3687 * @retval State of bit (1 or 0).
3688 */
3689 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1(TIM_TypeDef *TIMx)
3690 {
3691 return (READ_BIT(TIMx->SR, TIM_SR_CC1IF) == (TIM_SR_CC1IF));
3692 }
3693
3694 /**
3695 * @brief Clear the Capture/Compare 2 interrupt flag (CC2F).
3696 * @rmtoll SR CC2IF LL_TIM_ClearFlag_CC2
3697 * @param TIMx Timer instance
3698 * @retval None
3699 */
3700 __STATIC_INLINE void LL_TIM_ClearFlag_CC2(TIM_TypeDef *TIMx)
3701 {
3702 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2IF));
3703 }
3704
3705 /**
3706 * @brief Indicate whether Capture/Compare 2 interrupt flag (CC2F) is set (Capture/Compare 2 interrupt is pending).
3707 * @rmtoll SR CC2IF LL_TIM_IsActiveFlag_CC2
3708 * @param TIMx Timer instance
3709 * @retval State of bit (1 or 0).
3710 */
3711 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2(TIM_TypeDef *TIMx)
3712 {
3713 return (READ_BIT(TIMx->SR, TIM_SR_CC2IF) == (TIM_SR_CC2IF));
3714 }
3715
3716 /**
3717 * @brief Clear the Capture/Compare 3 interrupt flag (CC3F).
3718 * @rmtoll SR CC3IF LL_TIM_ClearFlag_CC3
3719 * @param TIMx Timer instance
3720 * @retval None
3721 */
3722 __STATIC_INLINE void LL_TIM_ClearFlag_CC3(TIM_TypeDef *TIMx)
3723 {
3724 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3IF));
3725 }
3726
3727 /**
3728 * @brief Indicate whether Capture/Compare 3 interrupt flag (CC3F) is set (Capture/Compare 3 interrupt is pending).
3729 * @rmtoll SR CC3IF LL_TIM_IsActiveFlag_CC3
3730 * @param TIMx Timer instance
3731 * @retval State of bit (1 or 0).
3732 */
3733 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3(TIM_TypeDef *TIMx)
3734 {
3735 return (READ_BIT(TIMx->SR, TIM_SR_CC3IF) == (TIM_SR_CC3IF));
3736 }
3737
3738 /**
3739 * @brief Clear the Capture/Compare 4 interrupt flag (CC4F).
3740 * @rmtoll SR CC4IF LL_TIM_ClearFlag_CC4
3741 * @param TIMx Timer instance
3742 * @retval None
3743 */
3744 __STATIC_INLINE void LL_TIM_ClearFlag_CC4(TIM_TypeDef *TIMx)
3745 {
3746 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4IF));
3747 }
3748
3749 /**
3750 * @brief Indicate whether Capture/Compare 4 interrupt flag (CC4F) is set (Capture/Compare 4 interrupt is pending).
3751 * @rmtoll SR CC4IF LL_TIM_IsActiveFlag_CC4
3752 * @param TIMx Timer instance
3753 * @retval State of bit (1 or 0).
3754 */
3755 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4(TIM_TypeDef *TIMx)
3756 {
3757 return (READ_BIT(TIMx->SR, TIM_SR_CC4IF) == (TIM_SR_CC4IF));
3758 }
3759
3760 /**
3761 * @brief Clear the Capture/Compare 5 interrupt flag (CC5F).
3762 * @rmtoll SR CC5IF LL_TIM_ClearFlag_CC5
3763 * @param TIMx Timer instance
3764 * @retval None
3765 */
3766 __STATIC_INLINE void LL_TIM_ClearFlag_CC5(TIM_TypeDef *TIMx)
3767 {
3768 WRITE_REG(TIMx->SR, ~(TIM_SR_CC5IF));
3769 }
3770
3771 /**
3772 * @brief Indicate whether Capture/Compare 5 interrupt flag (CC5F) is set (Capture/Compare 5 interrupt is pending).
3773 * @rmtoll SR CC5IF LL_TIM_IsActiveFlag_CC5
3774 * @param TIMx Timer instance
3775 * @retval State of bit (1 or 0).
3776 */
3777 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC5(TIM_TypeDef *TIMx)
3778 {
3779 return (READ_BIT(TIMx->SR, TIM_SR_CC5IF) == (TIM_SR_CC5IF));
3780 }
3781
3782 /**
3783 * @brief Clear the Capture/Compare 6 interrupt flag (CC6F).
3784 * @rmtoll SR CC6IF LL_TIM_ClearFlag_CC6
3785 * @param TIMx Timer instance
3786 * @retval None
3787 */
3788 __STATIC_INLINE void LL_TIM_ClearFlag_CC6(TIM_TypeDef *TIMx)
3789 {
3790 WRITE_REG(TIMx->SR, ~(TIM_SR_CC6IF));
3791 }
3792
3793 /**
3794 * @brief Indicate whether Capture/Compare 6 interrupt flag (CC6F) is set (Capture/Compare 6 interrupt is pending).
3795 * @rmtoll SR CC6IF LL_TIM_IsActiveFlag_CC6
3796 * @param TIMx Timer instance
3797 * @retval State of bit (1 or 0).
3798 */
3799 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC6(TIM_TypeDef *TIMx)
3800 {
3801 return (READ_BIT(TIMx->SR, TIM_SR_CC6IF) == (TIM_SR_CC6IF));
3802 }
3803
3804 /**
3805 * @brief Clear the commutation interrupt flag (COMIF).
3806 * @rmtoll SR COMIF LL_TIM_ClearFlag_COM
3807 * @param TIMx Timer instance
3808 * @retval None
3809 */
3810 __STATIC_INLINE void LL_TIM_ClearFlag_COM(TIM_TypeDef *TIMx)
3811 {
3812 WRITE_REG(TIMx->SR, ~(TIM_SR_COMIF));
3813 }
3814
3815 /**
3816 * @brief Indicate whether commutation interrupt flag (COMIF) is set (commutation interrupt is pending).
3817 * @rmtoll SR COMIF LL_TIM_IsActiveFlag_COM
3818 * @param TIMx Timer instance
3819 * @retval State of bit (1 or 0).
3820 */
3821 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_COM(TIM_TypeDef *TIMx)
3822 {
3823 return (READ_BIT(TIMx->SR, TIM_SR_COMIF) == (TIM_SR_COMIF));
3824 }
3825
3826 /**
3827 * @brief Clear the trigger interrupt flag (TIF).
3828 * @rmtoll SR TIF LL_TIM_ClearFlag_TRIG
3829 * @param TIMx Timer instance
3830 * @retval None
3831 */
3832 __STATIC_INLINE void LL_TIM_ClearFlag_TRIG(TIM_TypeDef *TIMx)
3833 {
3834 WRITE_REG(TIMx->SR, ~(TIM_SR_TIF));
3835 }
3836
3837 /**
3838 * @brief Indicate whether trigger interrupt flag (TIF) is set (trigger interrupt is pending).
3839 * @rmtoll SR TIF LL_TIM_IsActiveFlag_TRIG
3840 * @param TIMx Timer instance
3841 * @retval State of bit (1 or 0).
3842 */
3843 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_TRIG(TIM_TypeDef *TIMx)
3844 {
3845 return (READ_BIT(TIMx->SR, TIM_SR_TIF) == (TIM_SR_TIF));
3846 }
3847
3848 /**
3849 * @brief Clear the break interrupt flag (BIF).
3850 * @rmtoll SR BIF LL_TIM_ClearFlag_BRK
3851 * @param TIMx Timer instance
3852 * @retval None
3853 */
3854 __STATIC_INLINE void LL_TIM_ClearFlag_BRK(TIM_TypeDef *TIMx)
3855 {
3856 WRITE_REG(TIMx->SR, ~(TIM_SR_BIF));
3857 }
3858
3859 /**
3860 * @brief Indicate whether break interrupt flag (BIF) is set (break interrupt is pending).
3861 * @rmtoll SR BIF LL_TIM_IsActiveFlag_BRK
3862 * @param TIMx Timer instance
3863 * @retval State of bit (1 or 0).
3864 */
3865 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK(TIM_TypeDef *TIMx)
3866 {
3867 return (READ_BIT(TIMx->SR, TIM_SR_BIF) == (TIM_SR_BIF));
3868 }
3869
3870 /**
3871 * @brief Clear the break 2 interrupt flag (B2IF).
3872 * @rmtoll SR B2IF LL_TIM_ClearFlag_BRK2
3873 * @param TIMx Timer instance
3874 * @retval None
3875 */
3876 __STATIC_INLINE void LL_TIM_ClearFlag_BRK2(TIM_TypeDef *TIMx)
3877 {
3878 WRITE_REG(TIMx->SR, ~(TIM_SR_B2IF));
3879 }
3880
3881 /**
3882 * @brief Indicate whether break 2 interrupt flag (B2IF) is set (break 2 interrupt is pending).
3883 * @rmtoll SR B2IF LL_TIM_IsActiveFlag_BRK2
3884 * @param TIMx Timer instance
3885 * @retval State of bit (1 or 0).
3886 */
3887 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_BRK2(TIM_TypeDef *TIMx)
3888 {
3889 return (READ_BIT(TIMx->SR, TIM_SR_B2IF) == (TIM_SR_B2IF));
3890 }
3891
3892 /**
3893 * @brief Clear the Capture/Compare 1 over-capture interrupt flag (CC1OF).
3894 * @rmtoll SR CC1OF LL_TIM_ClearFlag_CC1OVR
3895 * @param TIMx Timer instance
3896 * @retval None
3897 */
3898 __STATIC_INLINE void LL_TIM_ClearFlag_CC1OVR(TIM_TypeDef *TIMx)
3899 {
3900 WRITE_REG(TIMx->SR, ~(TIM_SR_CC1OF));
3901 }
3902
3903 /**
3904 * @brief Indicate whether Capture/Compare 1 over-capture interrupt flag (CC1OF) is set (Capture/Compare 1 interrupt is pending).
3905 * @rmtoll SR CC1OF LL_TIM_IsActiveFlag_CC1OVR
3906 * @param TIMx Timer instance
3907 * @retval State of bit (1 or 0).
3908 */
3909 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC1OVR(TIM_TypeDef *TIMx)
3910 {
3911 return (READ_BIT(TIMx->SR, TIM_SR_CC1OF) == (TIM_SR_CC1OF));
3912 }
3913
3914 /**
3915 * @brief Clear the Capture/Compare 2 over-capture interrupt flag (CC2OF).
3916 * @rmtoll SR CC2OF LL_TIM_ClearFlag_CC2OVR
3917 * @param TIMx Timer instance
3918 * @retval None
3919 */
3920 __STATIC_INLINE void LL_TIM_ClearFlag_CC2OVR(TIM_TypeDef *TIMx)
3921 {
3922 WRITE_REG(TIMx->SR, ~(TIM_SR_CC2OF));
3923 }
3924
3925 /**
3926 * @brief Indicate whether Capture/Compare 2 over-capture interrupt flag (CC2OF) is set (Capture/Compare 2 over-capture interrupt is pending).
3927 * @rmtoll SR CC2OF LL_TIM_IsActiveFlag_CC2OVR
3928 * @param TIMx Timer instance
3929 * @retval State of bit (1 or 0).
3930 */
3931 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC2OVR(TIM_TypeDef *TIMx)
3932 {
3933 return (READ_BIT(TIMx->SR, TIM_SR_CC2OF) == (TIM_SR_CC2OF));
3934 }
3935
3936 /**
3937 * @brief Clear the Capture/Compare 3 over-capture interrupt flag (CC3OF).
3938 * @rmtoll SR CC3OF LL_TIM_ClearFlag_CC3OVR
3939 * @param TIMx Timer instance
3940 * @retval None
3941 */
3942 __STATIC_INLINE void LL_TIM_ClearFlag_CC3OVR(TIM_TypeDef *TIMx)
3943 {
3944 WRITE_REG(TIMx->SR, ~(TIM_SR_CC3OF));
3945 }
3946
3947 /**
3948 * @brief Indicate whether Capture/Compare 3 over-capture interrupt flag (CC3OF) is set (Capture/Compare 3 over-capture interrupt is pending).
3949 * @rmtoll SR CC3OF LL_TIM_IsActiveFlag_CC3OVR
3950 * @param TIMx Timer instance
3951 * @retval State of bit (1 or 0).
3952 */
3953 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC3OVR(TIM_TypeDef *TIMx)
3954 {
3955 return (READ_BIT(TIMx->SR, TIM_SR_CC3OF) == (TIM_SR_CC3OF));
3956 }
3957
3958 /**
3959 * @brief Clear the Capture/Compare 4 over-capture interrupt flag (CC4OF).
3960 * @rmtoll SR CC4OF LL_TIM_ClearFlag_CC4OVR
3961 * @param TIMx Timer instance
3962 * @retval None
3963 */
3964 __STATIC_INLINE void LL_TIM_ClearFlag_CC4OVR(TIM_TypeDef *TIMx)
3965 {
3966 WRITE_REG(TIMx->SR, ~(TIM_SR_CC4OF));
3967 }
3968
3969 /**
3970 * @brief Indicate whether Capture/Compare 4 over-capture interrupt flag (CC4OF) is set (Capture/Compare 4 over-capture interrupt is pending).
3971 * @rmtoll SR CC4OF LL_TIM_IsActiveFlag_CC4OVR
3972 * @param TIMx Timer instance
3973 * @retval State of bit (1 or 0).
3974 */
3975 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_CC4OVR(TIM_TypeDef *TIMx)
3976 {
3977 return (READ_BIT(TIMx->SR, TIM_SR_CC4OF) == (TIM_SR_CC4OF));
3978 }
3979
3980 /**
3981 * @brief Clear the system break interrupt flag (SBIF).
3982 * @rmtoll SR SBIF LL_TIM_ClearFlag_SYSBRK
3983 * @param TIMx Timer instance
3984 * @retval None
3985 */
3986 __STATIC_INLINE void LL_TIM_ClearFlag_SYSBRK(TIM_TypeDef *TIMx)
3987 {
3988 WRITE_REG(TIMx->SR, ~(TIM_SR_SBIF));
3989 }
3990
3991 /**
3992 * @brief Indicate whether system break interrupt flag (SBIF) is set (system break interrupt is pending).
3993 * @rmtoll SR SBIF LL_TIM_IsActiveFlag_SYSBRK
3994 * @param TIMx Timer instance
3995 * @retval State of bit (1 or 0).
3996 */
3997 __STATIC_INLINE uint32_t LL_TIM_IsActiveFlag_SYSBRK(TIM_TypeDef *TIMx)
3998 {
3999 return (READ_BIT(TIMx->SR, TIM_SR_SBIF) == (TIM_SR_SBIF));
4000 }
4001
4002 /**
4003 * @}
4004 */
4005
4006 /** @defgroup TIM_LL_EF_IT_Management IT-Management
4007 * @{
4008 */
4009 /**
4010 * @brief Enable update interrupt (UIE).
4011 * @rmtoll DIER UIE LL_TIM_EnableIT_UPDATE
4012 * @param TIMx Timer instance
4013 * @retval None
4014 */
4015 __STATIC_INLINE void LL_TIM_EnableIT_UPDATE(TIM_TypeDef *TIMx)
4016 {
4017 SET_BIT(TIMx->DIER, TIM_DIER_UIE);
4018 }
4019
4020 /**
4021 * @brief Disable update interrupt (UIE).
4022 * @rmtoll DIER UIE LL_TIM_DisableIT_UPDATE
4023 * @param TIMx Timer instance
4024 * @retval None
4025 */
4026 __STATIC_INLINE void LL_TIM_DisableIT_UPDATE(TIM_TypeDef *TIMx)
4027 {
4028 CLEAR_BIT(TIMx->DIER, TIM_DIER_UIE);
4029 }
4030
4031 /**
4032 * @brief Indicates whether the update interrupt (UIE) is enabled.
4033 * @rmtoll DIER UIE LL_TIM_IsEnabledIT_UPDATE
4034 * @param TIMx Timer instance
4035 * @retval State of bit (1 or 0).
4036 */
4037 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_UPDATE(TIM_TypeDef *TIMx)
4038 {
4039 return (READ_BIT(TIMx->DIER, TIM_DIER_UIE) == (TIM_DIER_UIE));
4040 }
4041
4042 /**
4043 * @brief Enable capture/compare 1 interrupt (CC1IE).
4044 * @rmtoll DIER CC1IE LL_TIM_EnableIT_CC1
4045 * @param TIMx Timer instance
4046 * @retval None
4047 */
4048 __STATIC_INLINE void LL_TIM_EnableIT_CC1(TIM_TypeDef *TIMx)
4049 {
4050 SET_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4051 }
4052
4053 /**
4054 * @brief Disable capture/compare 1 interrupt (CC1IE).
4055 * @rmtoll DIER CC1IE LL_TIM_DisableIT_CC1
4056 * @param TIMx Timer instance
4057 * @retval None
4058 */
4059 __STATIC_INLINE void LL_TIM_DisableIT_CC1(TIM_TypeDef *TIMx)
4060 {
4061 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1IE);
4062 }
4063
4064 /**
4065 * @brief Indicates whether the capture/compare 1 interrupt (CC1IE) is enabled.
4066 * @rmtoll DIER CC1IE LL_TIM_IsEnabledIT_CC1
4067 * @param TIMx Timer instance
4068 * @retval State of bit (1 or 0).
4069 */
4070 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC1(TIM_TypeDef *TIMx)
4071 {
4072 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1IE) == (TIM_DIER_CC1IE));
4073 }
4074
4075 /**
4076 * @brief Enable capture/compare 2 interrupt (CC2IE).
4077 * @rmtoll DIER CC2IE LL_TIM_EnableIT_CC2
4078 * @param TIMx Timer instance
4079 * @retval None
4080 */
4081 __STATIC_INLINE void LL_TIM_EnableIT_CC2(TIM_TypeDef *TIMx)
4082 {
4083 SET_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4084 }
4085
4086 /**
4087 * @brief Disable capture/compare 2 interrupt (CC2IE).
4088 * @rmtoll DIER CC2IE LL_TIM_DisableIT_CC2
4089 * @param TIMx Timer instance
4090 * @retval None
4091 */
4092 __STATIC_INLINE void LL_TIM_DisableIT_CC2(TIM_TypeDef *TIMx)
4093 {
4094 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2IE);
4095 }
4096
4097 /**
4098 * @brief Indicates whether the capture/compare 2 interrupt (CC2IE) is enabled.
4099 * @rmtoll DIER CC2IE LL_TIM_IsEnabledIT_CC2
4100 * @param TIMx Timer instance
4101 * @retval State of bit (1 or 0).
4102 */
4103 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC2(TIM_TypeDef *TIMx)
4104 {
4105 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2IE) == (TIM_DIER_CC2IE));
4106 }
4107
4108 /**
4109 * @brief Enable capture/compare 3 interrupt (CC3IE).
4110 * @rmtoll DIER CC3IE LL_TIM_EnableIT_CC3
4111 * @param TIMx Timer instance
4112 * @retval None
4113 */
4114 __STATIC_INLINE void LL_TIM_EnableIT_CC3(TIM_TypeDef *TIMx)
4115 {
4116 SET_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4117 }
4118
4119 /**
4120 * @brief Disable capture/compare 3 interrupt (CC3IE).
4121 * @rmtoll DIER CC3IE LL_TIM_DisableIT_CC3
4122 * @param TIMx Timer instance
4123 * @retval None
4124 */
4125 __STATIC_INLINE void LL_TIM_DisableIT_CC3(TIM_TypeDef *TIMx)
4126 {
4127 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3IE);
4128 }
4129
4130 /**
4131 * @brief Indicates whether the capture/compare 3 interrupt (CC3IE) is enabled.
4132 * @rmtoll DIER CC3IE LL_TIM_IsEnabledIT_CC3
4133 * @param TIMx Timer instance
4134 * @retval State of bit (1 or 0).
4135 */
4136 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC3(TIM_TypeDef *TIMx)
4137 {
4138 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3IE) == (TIM_DIER_CC3IE));
4139 }
4140
4141 /**
4142 * @brief Enable capture/compare 4 interrupt (CC4IE).
4143 * @rmtoll DIER CC4IE LL_TIM_EnableIT_CC4
4144 * @param TIMx Timer instance
4145 * @retval None
4146 */
4147 __STATIC_INLINE void LL_TIM_EnableIT_CC4(TIM_TypeDef *TIMx)
4148 {
4149 SET_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4150 }
4151
4152 /**
4153 * @brief Disable capture/compare 4 interrupt (CC4IE).
4154 * @rmtoll DIER CC4IE LL_TIM_DisableIT_CC4
4155 * @param TIMx Timer instance
4156 * @retval None
4157 */
4158 __STATIC_INLINE void LL_TIM_DisableIT_CC4(TIM_TypeDef *TIMx)
4159 {
4160 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4IE);
4161 }
4162
4163 /**
4164 * @brief Indicates whether the capture/compare 4 interrupt (CC4IE) is enabled.
4165 * @rmtoll DIER CC4IE LL_TIM_IsEnabledIT_CC4
4166 * @param TIMx Timer instance
4167 * @retval State of bit (1 or 0).
4168 */
4169 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_CC4(TIM_TypeDef *TIMx)
4170 {
4171 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4IE) == (TIM_DIER_CC4IE));
4172 }
4173
4174 /**
4175 * @brief Enable commutation interrupt (COMIE).
4176 * @rmtoll DIER COMIE LL_TIM_EnableIT_COM
4177 * @param TIMx Timer instance
4178 * @retval None
4179 */
4180 __STATIC_INLINE void LL_TIM_EnableIT_COM(TIM_TypeDef *TIMx)
4181 {
4182 SET_BIT(TIMx->DIER, TIM_DIER_COMIE);
4183 }
4184
4185 /**
4186 * @brief Disable commutation interrupt (COMIE).
4187 * @rmtoll DIER COMIE LL_TIM_DisableIT_COM
4188 * @param TIMx Timer instance
4189 * @retval None
4190 */
4191 __STATIC_INLINE void LL_TIM_DisableIT_COM(TIM_TypeDef *TIMx)
4192 {
4193 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMIE);
4194 }
4195
4196 /**
4197 * @brief Indicates whether the commutation interrupt (COMIE) is enabled.
4198 * @rmtoll DIER COMIE LL_TIM_IsEnabledIT_COM
4199 * @param TIMx Timer instance
4200 * @retval State of bit (1 or 0).
4201 */
4202 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_COM(TIM_TypeDef *TIMx)
4203 {
4204 return (READ_BIT(TIMx->DIER, TIM_DIER_COMIE) == (TIM_DIER_COMIE));
4205 }
4206
4207 /**
4208 * @brief Enable trigger interrupt (TIE).
4209 * @rmtoll DIER TIE LL_TIM_EnableIT_TRIG
4210 * @param TIMx Timer instance
4211 * @retval None
4212 */
4213 __STATIC_INLINE void LL_TIM_EnableIT_TRIG(TIM_TypeDef *TIMx)
4214 {
4215 SET_BIT(TIMx->DIER, TIM_DIER_TIE);
4216 }
4217
4218 /**
4219 * @brief Disable trigger interrupt (TIE).
4220 * @rmtoll DIER TIE LL_TIM_DisableIT_TRIG
4221 * @param TIMx Timer instance
4222 * @retval None
4223 */
4224 __STATIC_INLINE void LL_TIM_DisableIT_TRIG(TIM_TypeDef *TIMx)
4225 {
4226 CLEAR_BIT(TIMx->DIER, TIM_DIER_TIE);
4227 }
4228
4229 /**
4230 * @brief Indicates whether the trigger interrupt (TIE) is enabled.
4231 * @rmtoll DIER TIE LL_TIM_IsEnabledIT_TRIG
4232 * @param TIMx Timer instance
4233 * @retval State of bit (1 or 0).
4234 */
4235 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_TRIG(TIM_TypeDef *TIMx)
4236 {
4237 return (READ_BIT(TIMx->DIER, TIM_DIER_TIE) == (TIM_DIER_TIE));
4238 }
4239
4240 /**
4241 * @brief Enable break interrupt (BIE).
4242 * @rmtoll DIER BIE LL_TIM_EnableIT_BRK
4243 * @param TIMx Timer instance
4244 * @retval None
4245 */
4246 __STATIC_INLINE void LL_TIM_EnableIT_BRK(TIM_TypeDef *TIMx)
4247 {
4248 SET_BIT(TIMx->DIER, TIM_DIER_BIE);
4249 }
4250
4251 /**
4252 * @brief Disable break interrupt (BIE).
4253 * @rmtoll DIER BIE LL_TIM_DisableIT_BRK
4254 * @param TIMx Timer instance
4255 * @retval None
4256 */
4257 __STATIC_INLINE void LL_TIM_DisableIT_BRK(TIM_TypeDef *TIMx)
4258 {
4259 CLEAR_BIT(TIMx->DIER, TIM_DIER_BIE);
4260 }
4261
4262 /**
4263 * @brief Indicates whether the break interrupt (BIE) is enabled.
4264 * @rmtoll DIER BIE LL_TIM_IsEnabledIT_BRK
4265 * @param TIMx Timer instance
4266 * @retval State of bit (1 or 0).
4267 */
4268 __STATIC_INLINE uint32_t LL_TIM_IsEnabledIT_BRK(TIM_TypeDef *TIMx)
4269 {
4270 return (READ_BIT(TIMx->DIER, TIM_DIER_BIE) == (TIM_DIER_BIE));
4271 }
4272
4273 /**
4274 * @}
4275 */
4276
4277 /** @defgroup TIM_LL_EF_DMA_Management DMA-Management
4278 * @{
4279 */
4280 /**
4281 * @brief Enable update DMA request (UDE).
4282 * @rmtoll DIER UDE LL_TIM_EnableDMAReq_UPDATE
4283 * @param TIMx Timer instance
4284 * @retval None
4285 */
4286 __STATIC_INLINE void LL_TIM_EnableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4287 {
4288 SET_BIT(TIMx->DIER, TIM_DIER_UDE);
4289 }
4290
4291 /**
4292 * @brief Disable update DMA request (UDE).
4293 * @rmtoll DIER UDE LL_TIM_DisableDMAReq_UPDATE
4294 * @param TIMx Timer instance
4295 * @retval None
4296 */
4297 __STATIC_INLINE void LL_TIM_DisableDMAReq_UPDATE(TIM_TypeDef *TIMx)
4298 {
4299 CLEAR_BIT(TIMx->DIER, TIM_DIER_UDE);
4300 }
4301
4302 /**
4303 * @brief Indicates whether the update DMA request (UDE) is enabled.
4304 * @rmtoll DIER UDE LL_TIM_IsEnabledDMAReq_UPDATE
4305 * @param TIMx Timer instance
4306 * @retval State of bit (1 or 0).
4307 */
4308 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_UPDATE(TIM_TypeDef *TIMx)
4309 {
4310 return (READ_BIT(TIMx->DIER, TIM_DIER_UDE) == (TIM_DIER_UDE));
4311 }
4312
4313 /**
4314 * @brief Enable capture/compare 1 DMA request (CC1DE).
4315 * @rmtoll DIER CC1DE LL_TIM_EnableDMAReq_CC1
4316 * @param TIMx Timer instance
4317 * @retval None
4318 */
4319 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC1(TIM_TypeDef *TIMx)
4320 {
4321 SET_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4322 }
4323
4324 /**
4325 * @brief Disable capture/compare 1 DMA request (CC1DE).
4326 * @rmtoll DIER CC1DE LL_TIM_DisableDMAReq_CC1
4327 * @param TIMx Timer instance
4328 * @retval None
4329 */
4330 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC1(TIM_TypeDef *TIMx)
4331 {
4332 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC1DE);
4333 }
4334
4335 /**
4336 * @brief Indicates whether the capture/compare 1 DMA request (CC1DE) is enabled.
4337 * @rmtoll DIER CC1DE LL_TIM_IsEnabledDMAReq_CC1
4338 * @param TIMx Timer instance
4339 * @retval State of bit (1 or 0).
4340 */
4341 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC1(TIM_TypeDef *TIMx)
4342 {
4343 return (READ_BIT(TIMx->DIER, TIM_DIER_CC1DE) == (TIM_DIER_CC1DE));
4344 }
4345
4346 /**
4347 * @brief Enable capture/compare 2 DMA request (CC2DE).
4348 * @rmtoll DIER CC2DE LL_TIM_EnableDMAReq_CC2
4349 * @param TIMx Timer instance
4350 * @retval None
4351 */
4352 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC2(TIM_TypeDef *TIMx)
4353 {
4354 SET_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4355 }
4356
4357 /**
4358 * @brief Disable capture/compare 2 DMA request (CC2DE).
4359 * @rmtoll DIER CC2DE LL_TIM_DisableDMAReq_CC2
4360 * @param TIMx Timer instance
4361 * @retval None
4362 */
4363 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC2(TIM_TypeDef *TIMx)
4364 {
4365 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC2DE);
4366 }
4367
4368 /**
4369 * @brief Indicates whether the capture/compare 2 DMA request (CC2DE) is enabled.
4370 * @rmtoll DIER CC2DE LL_TIM_IsEnabledDMAReq_CC2
4371 * @param TIMx Timer instance
4372 * @retval State of bit (1 or 0).
4373 */
4374 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC2(TIM_TypeDef *TIMx)
4375 {
4376 return (READ_BIT(TIMx->DIER, TIM_DIER_CC2DE) == (TIM_DIER_CC2DE));
4377 }
4378
4379 /**
4380 * @brief Enable capture/compare 3 DMA request (CC3DE).
4381 * @rmtoll DIER CC3DE LL_TIM_EnableDMAReq_CC3
4382 * @param TIMx Timer instance
4383 * @retval None
4384 */
4385 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC3(TIM_TypeDef *TIMx)
4386 {
4387 SET_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4388 }
4389
4390 /**
4391 * @brief Disable capture/compare 3 DMA request (CC3DE).
4392 * @rmtoll DIER CC3DE LL_TIM_DisableDMAReq_CC3
4393 * @param TIMx Timer instance
4394 * @retval None
4395 */
4396 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC3(TIM_TypeDef *TIMx)
4397 {
4398 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC3DE);
4399 }
4400
4401 /**
4402 * @brief Indicates whether the capture/compare 3 DMA request (CC3DE) is enabled.
4403 * @rmtoll DIER CC3DE LL_TIM_IsEnabledDMAReq_CC3
4404 * @param TIMx Timer instance
4405 * @retval State of bit (1 or 0).
4406 */
4407 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC3(TIM_TypeDef *TIMx)
4408 {
4409 return (READ_BIT(TIMx->DIER, TIM_DIER_CC3DE) == (TIM_DIER_CC3DE));
4410 }
4411
4412 /**
4413 * @brief Enable capture/compare 4 DMA request (CC4DE).
4414 * @rmtoll DIER CC4DE LL_TIM_EnableDMAReq_CC4
4415 * @param TIMx Timer instance
4416 * @retval None
4417 */
4418 __STATIC_INLINE void LL_TIM_EnableDMAReq_CC4(TIM_TypeDef *TIMx)
4419 {
4420 SET_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4421 }
4422
4423 /**
4424 * @brief Disable capture/compare 4 DMA request (CC4DE).
4425 * @rmtoll DIER CC4DE LL_TIM_DisableDMAReq_CC4
4426 * @param TIMx Timer instance
4427 * @retval None
4428 */
4429 __STATIC_INLINE void LL_TIM_DisableDMAReq_CC4(TIM_TypeDef *TIMx)
4430 {
4431 CLEAR_BIT(TIMx->DIER, TIM_DIER_CC4DE);
4432 }
4433
4434 /**
4435 * @brief Indicates whether the capture/compare 4 DMA request (CC4DE) is enabled.
4436 * @rmtoll DIER CC4DE LL_TIM_IsEnabledDMAReq_CC4
4437 * @param TIMx Timer instance
4438 * @retval State of bit (1 or 0).
4439 */
4440 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_CC4(TIM_TypeDef *TIMx)
4441 {
4442 return (READ_BIT(TIMx->DIER, TIM_DIER_CC4DE) == (TIM_DIER_CC4DE));
4443 }
4444
4445 /**
4446 * @brief Enable commutation DMA request (COMDE).
4447 * @rmtoll DIER COMDE LL_TIM_EnableDMAReq_COM
4448 * @param TIMx Timer instance
4449 * @retval None
4450 */
4451 __STATIC_INLINE void LL_TIM_EnableDMAReq_COM(TIM_TypeDef *TIMx)
4452 {
4453 SET_BIT(TIMx->DIER, TIM_DIER_COMDE);
4454 }
4455
4456 /**
4457 * @brief Disable commutation DMA request (COMDE).
4458 * @rmtoll DIER COMDE LL_TIM_DisableDMAReq_COM
4459 * @param TIMx Timer instance
4460 * @retval None
4461 */
4462 __STATIC_INLINE void LL_TIM_DisableDMAReq_COM(TIM_TypeDef *TIMx)
4463 {
4464 CLEAR_BIT(TIMx->DIER, TIM_DIER_COMDE);
4465 }
4466
4467 /**
4468 * @brief Indicates whether the commutation DMA request (COMDE) is enabled.
4469 * @rmtoll DIER COMDE LL_TIM_IsEnabledDMAReq_COM
4470 * @param TIMx Timer instance
4471 * @retval State of bit (1 or 0).
4472 */
4473 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_COM(TIM_TypeDef *TIMx)
4474 {
4475 return (READ_BIT(TIMx->DIER, TIM_DIER_COMDE) == (TIM_DIER_COMDE));
4476 }
4477
4478 /**
4479 * @brief Enable trigger interrupt (TDE).
4480 * @rmtoll DIER TDE LL_TIM_EnableDMAReq_TRIG
4481 * @param TIMx Timer instance
4482 * @retval None
4483 */
4484 __STATIC_INLINE void LL_TIM_EnableDMAReq_TRIG(TIM_TypeDef *TIMx)
4485 {
4486 SET_BIT(TIMx->DIER, TIM_DIER_TDE);
4487 }
4488
4489 /**
4490 * @brief Disable trigger interrupt (TDE).
4491 * @rmtoll DIER TDE LL_TIM_DisableDMAReq_TRIG
4492 * @param TIMx Timer instance
4493 * @retval None
4494 */
4495 __STATIC_INLINE void LL_TIM_DisableDMAReq_TRIG(TIM_TypeDef *TIMx)
4496 {
4497 CLEAR_BIT(TIMx->DIER, TIM_DIER_TDE);
4498 }
4499
4500 /**
4501 * @brief Indicates whether the trigger interrupt (TDE) is enabled.
4502 * @rmtoll DIER TDE LL_TIM_IsEnabledDMAReq_TRIG
4503 * @param TIMx Timer instance
4504 * @retval State of bit (1 or 0).
4505 */
4506 __STATIC_INLINE uint32_t LL_TIM_IsEnabledDMAReq_TRIG(TIM_TypeDef *TIMx)
4507 {
4508 return (READ_BIT(TIMx->DIER, TIM_DIER_TDE) == (TIM_DIER_TDE));
4509 }
4510
4511 /**
4512 * @}
4513 */
4514
4515 /** @defgroup TIM_LL_EF_EVENT_Management EVENT-Management
4516 * @{
4517 */
4518 /**
4519 * @brief Generate an update event.
4520 * @rmtoll EGR UG LL_TIM_GenerateEvent_UPDATE
4521 * @param TIMx Timer instance
4522 * @retval None
4523 */
4524 __STATIC_INLINE void LL_TIM_GenerateEvent_UPDATE(TIM_TypeDef *TIMx)
4525 {
4526 SET_BIT(TIMx->EGR, TIM_EGR_UG);
4527 }
4528
4529 /**
4530 * @brief Generate Capture/Compare 1 event.
4531 * @rmtoll EGR CC1G LL_TIM_GenerateEvent_CC1
4532 * @param TIMx Timer instance
4533 * @retval None
4534 */
4535 __STATIC_INLINE void LL_TIM_GenerateEvent_CC1(TIM_TypeDef *TIMx)
4536 {
4537 SET_BIT(TIMx->EGR, TIM_EGR_CC1G);
4538 }
4539
4540 /**
4541 * @brief Generate Capture/Compare 2 event.
4542 * @rmtoll EGR CC2G LL_TIM_GenerateEvent_CC2
4543 * @param TIMx Timer instance
4544 * @retval None
4545 */
4546 __STATIC_INLINE void LL_TIM_GenerateEvent_CC2(TIM_TypeDef *TIMx)
4547 {
4548 SET_BIT(TIMx->EGR, TIM_EGR_CC2G);
4549 }
4550
4551 /**
4552 * @brief Generate Capture/Compare 3 event.
4553 * @rmtoll EGR CC3G LL_TIM_GenerateEvent_CC3
4554 * @param TIMx Timer instance
4555 * @retval None
4556 */
4557 __STATIC_INLINE void LL_TIM_GenerateEvent_CC3(TIM_TypeDef *TIMx)
4558 {
4559 SET_BIT(TIMx->EGR, TIM_EGR_CC3G);
4560 }
4561
4562 /**
4563 * @brief Generate Capture/Compare 4 event.
4564 * @rmtoll EGR CC4G LL_TIM_GenerateEvent_CC4
4565 * @param TIMx Timer instance
4566 * @retval None
4567 */
4568 __STATIC_INLINE void LL_TIM_GenerateEvent_CC4(TIM_TypeDef *TIMx)
4569 {
4570 SET_BIT(TIMx->EGR, TIM_EGR_CC4G);
4571 }
4572
4573 /**
4574 * @brief Generate commutation event.
4575 * @rmtoll EGR COMG LL_TIM_GenerateEvent_COM
4576 * @param TIMx Timer instance
4577 * @retval None
4578 */
4579 __STATIC_INLINE void LL_TIM_GenerateEvent_COM(TIM_TypeDef *TIMx)
4580 {
4581 SET_BIT(TIMx->EGR, TIM_EGR_COMG);
4582 }
4583
4584 /**
4585 * @brief Generate trigger event.
4586 * @rmtoll EGR TG LL_TIM_GenerateEvent_TRIG
4587 * @param TIMx Timer instance
4588 * @retval None
4589 */
4590 __STATIC_INLINE void LL_TIM_GenerateEvent_TRIG(TIM_TypeDef *TIMx)
4591 {
4592 SET_BIT(TIMx->EGR, TIM_EGR_TG);
4593 }
4594
4595 /**
4596 * @brief Generate break event.
4597 * @rmtoll EGR BG LL_TIM_GenerateEvent_BRK
4598 * @param TIMx Timer instance
4599 * @retval None
4600 */
4601 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK(TIM_TypeDef *TIMx)
4602 {
4603 SET_BIT(TIMx->EGR, TIM_EGR_BG);
4604 }
4605
4606 /**
4607 * @brief Generate break 2 event.
4608 * @rmtoll EGR B2G LL_TIM_GenerateEvent_BRK2
4609 * @param TIMx Timer instance
4610 * @retval None
4611 */
4612 __STATIC_INLINE void LL_TIM_GenerateEvent_BRK2(TIM_TypeDef *TIMx)
4613 {
4614 SET_BIT(TIMx->EGR, TIM_EGR_B2G);
4615 }
4616
4617 /**
4618 * @}
4619 */
4620
4621 #if defined(USE_FULL_LL_DRIVER)
4622 /** @defgroup TIM_LL_EF_Init Initialisation and deinitialisation functions
4623 * @{
4624 */
4625
4626 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx);
4627 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct);
4628 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct);
4629 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4630 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct);
4631 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
4632 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct);
4633 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4634 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct);
4635 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4636 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct);
4637 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4638 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct);
4639 /**
4640 * @}
4641 */
4642 #endif /* USE_FULL_LL_DRIVER */
4643
4644 /**
4645 * @}
4646 */
4647
4648 /**
4649 * @}
4650 */
4651
4652 #endif /* TIM1 || TIM8 || TIM2 || TIM3 || TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
4653
4654 /**
4655 * @}
4656 */
4657
4658 #ifdef __cplusplus
4659 }
4660 #endif
4661
4662 #endif /* __STM32F7xx_LL_TIM_H */
4663 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software