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Merge pull request #10558 from iNavFlight/MrD_Correct-comments-on-OSD-symbols
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_dma2d.c
blob2ba5010bd6ea9288e75ba7ad2b2b1d5cac70f228
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_dma2d.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief DMA2D HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the DMA2D peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral Control functions
13 * + Peripheral State and Errors functions
14 *
15 @verbatim
16 ==============================================================================
17 ##### How to use this driver #####
18 ==============================================================================
19 [..]
20 (#) Program the required configuration through the following parameters:
21 the transfer mode, the output color mode and the output offset using
22 HAL_DMA2D_Init() function.
23
24 (#) Program the required configuration through the following parameters:
25 the input color mode, the input color, the input alpha value, the alpha mode,
26 the red/blue swap mode, the inverted alpha mode and the input offset using
27 HAL_DMA2D_ConfigLayer() function for foreground or/and background layer.
28
29 *** Polling mode IO operation ***
30 =================================
31 [..]
32 (#) Configure pdata parameter (explained hereafter), destination and data length
33 and enable the transfer using HAL_DMA2D_Start().
34 (#) Wait for end of transfer using HAL_DMA2D_PollForTransfer(), at this stage
35 user can specify the value of timeout according to his end application.
36
37 *** Interrupt mode IO operation ***
38 ===================================
39 [..]
40 (#) Configure pdata parameter, destination and data length and enable
41 the transfer using HAL_DMA2D_Start_IT().
42 (#) Use HAL_DMA2D_IRQHandler() called under DMA2D_IRQHandler() interrupt subroutine.
43 (#) At the end of data transfer HAL_DMA2D_IRQHandler() function is executed and user can
44 add his own function by customization of function pointer XferCpltCallback (member
45 of DMA2D handle structure).
46 (#) In case of error, the HAL_DMA2D_IRQHandler() function will call the callback
47 XferErrorCallback.
48
49 -@- In Register-to-Memory transfer mode, pdata parameter is the register
50 color, in Memory-to-memory or Memory-to-Memory with pixel format
51 conversion pdata is the source address.
52
53 -@- Configure the foreground source address, the background source address,
54 the destination and data length then Enable the transfer using
55 HAL_DMA2D_BlendingStart() in polling mode and HAL_DMA2D_BlendingStart_IT()
56 in interrupt mode.
57
58 -@- HAL_DMA2D_BlendingStart() and HAL_DMA2D_BlendingStart_IT() functions
59 are used if the memory to memory with blending transfer mode is selected.
60
61 (#) Optionally, configure and enable the CLUT using HAL_DMA2D_CLUTLoad() in polling
62 mode or HAL_DMA2D_CLUTLoad_IT() in interrupt mode.
63
64 (#) Optionally, configure the line watermark in using the API HAL_DMA2D_ProgramLineEvent()
65
66 (#) Optionally, configure the dead time value in the AHB clock cycle inserted between two
67 consecutive accesses on the AHB master port in using the API HAL_DMA2D_ConfigDeadTime()
68 and enable/disable the functionality with the APIs HAL_DMA2D_EnableDeadTime() or
69 HAL_DMA2D_DisableDeadTime().
70
71 (#) The transfer can be suspended, resumed and aborted using the following
72 functions: HAL_DMA2D_Suspend(), HAL_DMA2D_Resume(), HAL_DMA2D_Abort().
73
74 (#) The CLUT loading can be suspended, resumed and aborted using the following
75 functions: HAL_DMA2D_CLUTLoading_Suspend(), HAL_DMA2D_CLUTLoading_Resume(),
76 HAL_DMA2D_CLUTLoading_Abort().
77
78 (#) To control the DMA2D state, use the following function: HAL_DMA2D_GetState().
79
80 (#) To read the DMA2D error code, use the following function: HAL_DMA2D_GetError().
81
82 *** DMA2D HAL driver macros list ***
83 =============================================
84 [..]
85 Below the list of most used macros in DMA2D HAL driver :
86
87 (+) __HAL_DMA2D_ENABLE: Enable the DMA2D peripheral.
88 (+) __HAL_DMA2D_GET_FLAG: Get the DMA2D pending flags.
89 (+) __HAL_DMA2D_CLEAR_FLAG: Clear the DMA2D pending flags.
90 (+) __HAL_DMA2D_ENABLE_IT: Enable the specified DMA2D interrupts.
91 (+) __HAL_DMA2D_DISABLE_IT: Disable the specified DMA2D interrupts.
92 (+) __HAL_DMA2D_GET_IT_SOURCE: Check whether the specified DMA2D interrupt is enabled or not.
93
94 [..]
95 (@) You can refer to the DMA2D HAL driver header file for more useful macros
96
97 @endverbatim
98 ******************************************************************************
99 * @attention
100 *
101 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
102 *
103 * Redistribution and use in source and binary forms, with or without modification,
104 * are permitted provided that the following conditions are met:
105 * 1. Redistributions of source code must retain the above copyright notice,
106 * this list of conditions and the following disclaimer.
107 * 2. Redistributions in binary form must reproduce the above copyright notice,
108 * this list of conditions and the following disclaimer in the documentation
109 * and/or other materials provided with the distribution.
110 * 3. Neither the name of STMicroelectronics nor the names of its contributors
111 * may be used to endorse or promote products derived from this software
112 * without specific prior written permission.
113 *
114 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
115 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
116 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
117 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
118 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
119 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
120 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
121 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
122 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
123 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
124 *
125 ******************************************************************************
126 */
127
128 /* Includes ------------------------------------------------------------------*/
129 #include "stm32f7xx_hal.h"
130
131 /** @addtogroup STM32F7xx_HAL_Driver
132 * @{
133 */
134
135 /** @defgroup DMA2D DMA2D
136 * @brief DMA2D HAL module driver
137 * @{
138 */
139
140 #ifdef HAL_DMA2D_MODULE_ENABLED
141 #if defined (DMA2D)
142
143 /* Private types -------------------------------------------------------------*/
144 /* Private define ------------------------------------------------------------*/
145 /** @defgroup DMA2D_Private_Constants DMA2D Private Constants
146 * @{
147 */
148
149 /** @defgroup DMA2D_TimeOut DMA2D Time Out
150 * @{
151 */
152 #define DMA2D_TIMEOUT_ABORT ((uint32_t)1000) /*!< 1s */
153 #define DMA2D_TIMEOUT_SUSPEND ((uint32_t)1000) /*!< 1s */
154 /**
155 * @}
156 */
157
158 /** @defgroup DMA2D_Shifts DMA2D Shifts
159 * @{
160 */
161 #define DMA2D_POSITION_FGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CS) /*!< Required left shift to set foreground CLUT size */
162 #define DMA2D_POSITION_BGPFCCR_CS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CS) /*!< Required left shift to set background CLUT size */
163
164 #define DMA2D_POSITION_FGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_CCM) /*!< Required left shift to set foreground CLUT color mode */
165 #define DMA2D_POSITION_BGPFCCR_CCM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_CCM) /*!< Required left shift to set background CLUT color mode */
166
167 #define DMA2D_POSITION_OPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_OPFCCR_AI) /*!< Required left shift to set output alpha inversion */
168 #define DMA2D_POSITION_FGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AI) /*!< Required left shift to set foreground alpha inversion */
169 #define DMA2D_POSITION_BGPFCCR_AI (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AI) /*!< Required left shift to set background alpha inversion */
170
171 #define DMA2D_POSITION_OPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_OPFCCR_RBS) /*!< Required left shift to set output Red/Blue swap */
172 #define DMA2D_POSITION_FGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_RBS) /*!< Required left shift to set foreground Red/Blue swap */
173 #define DMA2D_POSITION_BGPFCCR_RBS (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_RBS) /*!< Required left shift to set background Red/Blue swap */
174
175 #define DMA2D_POSITION_AMTCR_DT (uint32_t)POSITION_VAL(DMA2D_AMTCR_DT) /*!< Required left shift to set deadtime value */
176
177 #define DMA2D_POSITION_FGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_AM) /*!< Required left shift to set foreground alpha mode */
178 #define DMA2D_POSITION_BGPFCCR_AM (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_AM) /*!< Required left shift to set background alpha mode */
179
180 #define DMA2D_POSITION_FGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_FGPFCCR_ALPHA) /*!< Required left shift to set foreground alpha value */
181 #define DMA2D_POSITION_BGPFCCR_ALPHA (uint32_t)POSITION_VAL(DMA2D_BGPFCCR_ALPHA) /*!< Required left shift to set background alpha value */
182
183 #define DMA2D_POSITION_NLR_PL (uint32_t)POSITION_VAL(DMA2D_NLR_PL) /*!< Required left shift to set pixels per lines value */
184 /**
185 * @}
186 */
187
188 /**
189 * @}
190 */
191
192 /* Private variables ---------------------------------------------------------*/
193 /* Private constants ---------------------------------------------------------*/
194 /* Private macro -------------------------------------------------------------*/
195 /* Private function prototypes -----------------------------------------------*/
196 /** @addtogroup DMA2D_Private_Functions_Prototypes
197 * @{
198 */
199 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height);
200 /**
201 * @}
202 */
203
204 /* Private functions ---------------------------------------------------------*/
205 /* Exported functions --------------------------------------------------------*/
206 /** @defgroup DMA2D_Exported_Functions DMA2D Exported Functions
207 * @{
208 */
209
210 /** @defgroup DMA2D_Exported_Functions_Group1 Initialization and de-initialization functions
211 * @brief Initialization and Configuration functions
212 *
213 @verbatim
214 ===============================================================================
215 ##### Initialization and Configuration functions #####
216 ===============================================================================
217 [..] This section provides functions allowing to:
218 (+) Initialize and configure the DMA2D
219 (+) De-initialize the DMA2D
220
221 @endverbatim
222 * @{
223 */
224
225 /**
226 * @brief Initialize the DMA2D according to the specified
227 * parameters in the DMA2D_InitTypeDef and create the associated handle.
228 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
229 * the configuration information for the DMA2D.
230 * @retval HAL status
231 */
232 HAL_StatusTypeDef HAL_DMA2D_Init(DMA2D_HandleTypeDef *hdma2d)
233 {
234 /* Check the DMA2D peripheral state */
235 if(hdma2d == NULL)
236 {
237 return HAL_ERROR;
238 }
239
240 /* Check the parameters */
241 assert_param(IS_DMA2D_ALL_INSTANCE(hdma2d->Instance));
242 assert_param(IS_DMA2D_MODE(hdma2d->Init.Mode));
243 assert_param(IS_DMA2D_CMODE(hdma2d->Init.ColorMode));
244 assert_param(IS_DMA2D_OFFSET(hdma2d->Init.OutputOffset));
245
246 if(hdma2d->State == HAL_DMA2D_STATE_RESET)
247 {
248 /* Allocate lock resource and initialize it */
249 hdma2d->Lock = HAL_UNLOCKED;
250 /* Init the low level hardware */
251 HAL_DMA2D_MspInit(hdma2d);
252 }
253
254 /* Change DMA2D peripheral state */
255 hdma2d->State = HAL_DMA2D_STATE_BUSY;
256
257 /* DMA2D CR register configuration -------------------------------------------*/
258 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_MODE, hdma2d->Init.Mode);
259
260 /* DMA2D OPFCCR register configuration ---------------------------------------*/
261 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_CM, hdma2d->Init.ColorMode);
262
263 /* DMA2D OOR register configuration ------------------------------------------*/
264 MODIFY_REG(hdma2d->Instance->OOR, DMA2D_OOR_LO, hdma2d->Init.OutputOffset);
265
266 #if defined (DMA2D_OPFCCR_AI)
267 /* DMA2D OPFCCR AI fields setting (Output Alpha Inversion)*/
268 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_AI, (hdma2d->Init.AlphaInverted << DMA2D_POSITION_OPFCCR_AI));
269 #endif /* DMA2D_OPFCCR_AI */
270
271 #if defined (DMA2D_OPFCCR_RBS)
272 MODIFY_REG(hdma2d->Instance->OPFCCR, DMA2D_OPFCCR_RBS,(hdma2d->Init.RedBlueSwap << DMA2D_POSITION_OPFCCR_RBS));
273 #endif /* DMA2D_OPFCCR_RBS */
274
275
276 /* Update error code */
277 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
278
279 /* Initialize the DMA2D state*/
280 hdma2d->State = HAL_DMA2D_STATE_READY;
281
282 return HAL_OK;
283 }
284
285 /**
286 * @brief Deinitializes the DMA2D peripheral registers to their default reset
287 * values.
288 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
289 * the configuration information for the DMA2D.
290 * @retval None
291 */
292
293 HAL_StatusTypeDef HAL_DMA2D_DeInit(DMA2D_HandleTypeDef *hdma2d)
294 {
295
296 /* Check the DMA2D peripheral state */
297 if(hdma2d == NULL)
298 {
299 return HAL_ERROR;
300 }
301
302 /* Before aborting any DMA2D transfer or CLUT loading, check
303 first whether or not DMA2D clock is enabled */
304 if (__HAL_RCC_DMA2D_IS_CLK_ENABLED())
305 {
306 /* Abort DMA2D transfer if any */
307 if ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START)
308 {
309 if (HAL_DMA2D_Abort(hdma2d) != HAL_OK)
310 {
311 /* Issue when aborting DMA2D transfer */
312 return HAL_ERROR;
313 }
314 }
315 else
316 {
317 /* Abort background CLUT loading if any */
318 if ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START)
319 {
320 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 0) != HAL_OK)
321 {
322 /* Issue when aborting background CLUT loading */
323 return HAL_ERROR;
324 }
325 }
326 else
327 {
328 /* Abort foreground CLUT loading if any */
329 if ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START)
330 {
331 if (HAL_DMA2D_CLUTLoading_Abort(hdma2d, 1) != HAL_OK)
332 {
333 /* Issue when aborting foreground CLUT loading */
334 return HAL_ERROR;
335 }
336 }
337 }
338 }
339 }
340
341
342 /* Carry on with de-initialization of low level hardware */
343 HAL_DMA2D_MspDeInit(hdma2d);
344
345 /* Reset DMA2D control registers*/
346 hdma2d->Instance->CR = 0;
347 hdma2d->Instance->FGOR = 0;
348 hdma2d->Instance->BGOR = 0;
349 hdma2d->Instance->FGPFCCR = 0;
350 hdma2d->Instance->BGPFCCR = 0;
351 hdma2d->Instance->OPFCCR = 0;
352
353 /* Update error code */
354 hdma2d->ErrorCode = HAL_DMA2D_ERROR_NONE;
355
356 /* Initialize the DMA2D state*/
357 hdma2d->State = HAL_DMA2D_STATE_RESET;
358
359 /* Release Lock */
360 __HAL_UNLOCK(hdma2d);
361
362 return HAL_OK;
363 }
364
365 /**
366 * @brief Initializes the DMA2D MSP.
367 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
368 * the configuration information for the DMA2D.
369 * @retval None
370 */
371 __weak void HAL_DMA2D_MspInit(DMA2D_HandleTypeDef* hdma2d)
372 {
373 /* Prevent unused argument(s) compilation warning */
374 UNUSED(hdma2d);
375
376 /* NOTE : This function should not be modified; when the callback is needed,
377 the HAL_DMA2D_MspInit can be implemented in the user file.
378 */
379 }
380
381 /**
382 * @brief DeInitializes the DMA2D MSP.
383 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
384 * the configuration information for the DMA2D.
385 * @retval None
386 */
387 __weak void HAL_DMA2D_MspDeInit(DMA2D_HandleTypeDef* hdma2d)
388 {
389 /* Prevent unused argument(s) compilation warning */
390 UNUSED(hdma2d);
391
392 /* NOTE : This function should not be modified; when the callback is needed,
393 the HAL_DMA2D_MspDeInit can be implemented in the user file.
394 */
395 }
396
397 /**
398 * @}
399 */
400
401
402 /** @defgroup DMA2D_Exported_Functions_Group2 IO operation functions
403 * @brief IO operation functions
404 *
405 @verbatim
406 ===============================================================================
407 ##### IO operation functions #####
408 ===============================================================================
409 [..] This section provides functions allowing to:
410 (+) Configure the pdata, destination address and data size then
411 start the DMA2D transfer.
412 (+) Configure the source for foreground and background, destination address
413 and data size then start a MultiBuffer DMA2D transfer.
414 (+) Configure the pdata, destination address and data size then
415 start the DMA2D transfer with interrupt.
416 (+) Configure the source for foreground and background, destination address
417 and data size then start a MultiBuffer DMA2D transfer with interrupt.
418 (+) Abort DMA2D transfer.
419 (+) Suspend DMA2D transfer.
420 (+) Resume DMA2D transfer.
421 (+) Enable CLUT transfer.
422 (+) Configure CLUT loading then start transfer in polling mode.
423 (+) Configure CLUT loading then start transfer in interrupt mode.
424 (+) Abort DMA2D CLUT loading.
425 (+) Suspend DMA2D CLUT loading.
426 (+) Resume DMA2D CLUT loading.
427 (+) Poll for transfer complete.
428 (+) handle DMA2D interrupt request.
429 (+) Transfer watermark callback.
430 (+) CLUT Transfer Complete callback.
431
432
433 @endverbatim
434 * @{
435 */
436
437 /**
438 * @brief Start the DMA2D Transfer.
439 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
440 * the configuration information for the DMA2D.
441 * @param pdata: Configure the source memory Buffer address if
442 * Memory-to-Memory or Memory-to-Memory with pixel format
443 * conversion mode is selected, or configure
444 * the color value if Register-to-Memory mode is selected.
445 * @param DstAddress: The destination memory Buffer address.
446 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
447 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
448 * @retval HAL status
449 */
450 HAL_StatusTypeDef HAL_DMA2D_Start(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
451 {
452 /* Check the parameters */
453 assert_param(IS_DMA2D_LINE(Height));
454 assert_param(IS_DMA2D_PIXEL(Width));
455
456 /* Process locked */
457 __HAL_LOCK(hdma2d);
458
459 /* Change DMA2D peripheral state */
460 hdma2d->State = HAL_DMA2D_STATE_BUSY;
461
462 /* Configure the source, destination address and the data size */
463 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
464
465 /* Enable the Peripheral */
466 __HAL_DMA2D_ENABLE(hdma2d);
467
468 return HAL_OK;
469 }
470
471 /**
472 * @brief Start the DMA2D Transfer with interrupt enabled.
473 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
474 * the configuration information for the DMA2D.
475 * @param pdata: Configure the source memory Buffer address if
476 * the Memory-to-Memory or Memory-to-Memory with pixel format
477 * conversion mode is selected, or configure
478 * the color value if Register-to-Memory mode is selected.
479 * @param DstAddress: The destination memory Buffer address.
480 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
481 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
482 * @retval HAL status
483 */
484 HAL_StatusTypeDef HAL_DMA2D_Start_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
485 {
486 /* Check the parameters */
487 assert_param(IS_DMA2D_LINE(Height));
488 assert_param(IS_DMA2D_PIXEL(Width));
489
490 /* Process locked */
491 __HAL_LOCK(hdma2d);
492
493 /* Change DMA2D peripheral state */
494 hdma2d->State = HAL_DMA2D_STATE_BUSY;
495
496 /* Configure the source, destination address and the data size */
497 DMA2D_SetConfig(hdma2d, pdata, DstAddress, Width, Height);
498
499 /* Enable the transfer complete, transfer error and configuration error interrupts */
500 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
501
502 /* Enable the Peripheral */
503 __HAL_DMA2D_ENABLE(hdma2d);
504
505 return HAL_OK;
506 }
507
508 /**
509 * @brief Start the multi-source DMA2D Transfer.
510 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
511 * the configuration information for the DMA2D.
512 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
513 * @param SrcAddress2: The source memory Buffer address for the background layer.
514 * @param DstAddress: The destination memory Buffer address.
515 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
516 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
517 * @retval HAL status
518 */
519 HAL_StatusTypeDef HAL_DMA2D_BlendingStart(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
520 {
521 /* Check the parameters */
522 assert_param(IS_DMA2D_LINE(Height));
523 assert_param(IS_DMA2D_PIXEL(Width));
524
525 /* Process locked */
526 __HAL_LOCK(hdma2d);
527
528 /* Change DMA2D peripheral state */
529 hdma2d->State = HAL_DMA2D_STATE_BUSY;
530
531 /* Configure DMA2D Stream source2 address */
532 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
533
534 /* Configure the source, destination address and the data size */
535 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
536
537 /* Enable the Peripheral */
538 __HAL_DMA2D_ENABLE(hdma2d);
539
540 return HAL_OK;
541 }
542
543 /**
544 * @brief Start the multi-source DMA2D Transfer with interrupt enabled.
545 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
546 * the configuration information for the DMA2D.
547 * @param SrcAddress1: The source memory Buffer address for the foreground layer.
548 * @param SrcAddress2: The source memory Buffer address for the background layer.
549 * @param DstAddress: The destination memory Buffer address.
550 * @param Width: The width of data to be transferred from source to destination (expressed in number of pixels per line).
551 * @param Height: The height of data to be transferred from source to destination (expressed in number of lines).
552 * @retval HAL status
553 */
554 HAL_StatusTypeDef HAL_DMA2D_BlendingStart_IT(DMA2D_HandleTypeDef *hdma2d, uint32_t SrcAddress1, uint32_t SrcAddress2, uint32_t DstAddress, uint32_t Width, uint32_t Height)
555 {
556 /* Check the parameters */
557 assert_param(IS_DMA2D_LINE(Height));
558 assert_param(IS_DMA2D_PIXEL(Width));
559
560 /* Process locked */
561 __HAL_LOCK(hdma2d);
562
563 /* Change DMA2D peripheral state */
564 hdma2d->State = HAL_DMA2D_STATE_BUSY;
565
566 /* Configure DMA2D Stream source2 address */
567 WRITE_REG(hdma2d->Instance->BGMAR, SrcAddress2);
568
569 /* Configure the source, destination address and the data size */
570 DMA2D_SetConfig(hdma2d, SrcAddress1, DstAddress, Width, Height);
571
572 /* Enable the transfer complete, transfer error and configuration error interrupts */
573 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
574
575 /* Enable the Peripheral */
576 __HAL_DMA2D_ENABLE(hdma2d);
577
578 return HAL_OK;
579 }
580
581 /**
582 * @brief Abort the DMA2D Transfer.
583 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
584 * the configuration information for the DMA2D.
585 * @retval HAL status
586 */
587 HAL_StatusTypeDef HAL_DMA2D_Abort(DMA2D_HandleTypeDef *hdma2d)
588 {
589 uint32_t tickstart = 0;
590
591 /* Abort the DMA2D transfer */
592 /* START bit is reset to make sure not to set it again, in the event the HW clears it
593 between the register read and the register write by the CPU (writing 0 has no
594 effect on START bitvalue) */
595 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_ABORT|DMA2D_CR_START, DMA2D_CR_ABORT);
596
597 /* Get tick */
598 tickstart = HAL_GetTick();
599
600 /* Check if the DMA2D is effectively disabled */
601 while((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
602 {
603 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
604 {
605 /* Update error code */
606 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
607
608 /* Change the DMA2D state */
609 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
610
611 /* Process Unlocked */
612 __HAL_UNLOCK(hdma2d);
613
614 return HAL_TIMEOUT;
615 }
616 }
617
618 /* Disable the Transfer Complete, Transfer Error and Configuration Error interrupts */
619 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC|DMA2D_IT_TE|DMA2D_IT_CE);
620
621 /* Change the DMA2D state*/
622 hdma2d->State = HAL_DMA2D_STATE_READY;
623
624 /* Process Unlocked */
625 __HAL_UNLOCK(hdma2d);
626
627 return HAL_OK;
628 }
629
630 /**
631 * @brief Suspend the DMA2D Transfer.
632 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
633 * the configuration information for the DMA2D.
634 * @retval HAL status
635 */
636 HAL_StatusTypeDef HAL_DMA2D_Suspend(DMA2D_HandleTypeDef *hdma2d)
637 {
638 uint32_t tickstart = 0;
639
640 /* Suspend the DMA2D transfer */
641 /* START bit is reset to make sure not to set it again, in the event the HW clears it
642 between the register read and the register write by the CPU (writing 0 has no
643 effect on START bitvalue). */
644 MODIFY_REG(hdma2d->Instance->CR, DMA2D_CR_SUSP|DMA2D_CR_START, DMA2D_CR_SUSP);
645
646 /* Get tick */
647 tickstart = HAL_GetTick();
648
649 /* Check if the DMA2D is effectively suspended */
650 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
651 && ((hdma2d->Instance->CR & DMA2D_CR_START) == DMA2D_CR_START))
652 {
653 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
654 {
655 /* Update error code */
656 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
657
658 /* Change the DMA2D state */
659 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
660
661 return HAL_TIMEOUT;
662 }
663 }
664
665 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
666 if ((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
667 {
668 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
669 }
670 else
671 {
672 /* Make sure SUSP bit is cleared since it is meaningless
673 when no tranfer is on-going */
674 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
675 }
676
677 return HAL_OK;
678 }
679
680 /**
681 * @brief Resume the DMA2D Transfer.
682 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
683 * the configuration information for the DMA2D.
684 * @retval HAL status
685 */
686 HAL_StatusTypeDef HAL_DMA2D_Resume(DMA2D_HandleTypeDef *hdma2d)
687 {
688 /* Check the SUSP and START bits */
689 if((hdma2d->Instance->CR & (DMA2D_CR_SUSP | DMA2D_CR_START)) == (DMA2D_CR_SUSP | DMA2D_CR_START))
690 {
691 /* Ongoing transfer is suspended: change the DMA2D state before resuming */
692 hdma2d->State = HAL_DMA2D_STATE_BUSY;
693 }
694
695 /* Resume the DMA2D transfer */
696 /* START bit is reset to make sure not to set it again, in the event the HW clears it
697 between the register read and the register write by the CPU (writing 0 has no
698 effect on START bitvalue). */
699 CLEAR_BIT(hdma2d->Instance->CR, (DMA2D_CR_SUSP|DMA2D_CR_START));
700
701 return HAL_OK;
702 }
703
704
705 /**
706 * @brief Enable the DMA2D CLUT Transfer.
707 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
708 * the configuration information for the DMA2D.
709 * @param LayerIdx: DMA2D Layer index.
710 * This parameter can be one of the following values:
711 * 0(background) / 1(foreground)
712 * @retval HAL status
713 */
714 HAL_StatusTypeDef HAL_DMA2D_EnableCLUT(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
715 {
716 /* Check the parameters */
717 assert_param(IS_DMA2D_LAYER(LayerIdx));
718
719 /* Process locked */
720 __HAL_LOCK(hdma2d);
721
722 /* Change DMA2D peripheral state */
723 hdma2d->State = HAL_DMA2D_STATE_BUSY;
724
725 if(LayerIdx == 0)
726 {
727 /* Enable the background CLUT loading */
728 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
729 }
730 else
731 {
732 /* Enable the foreground CLUT loading */
733 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
734 }
735
736 return HAL_OK;
737 }
738
739
740 /**
741 * @brief Start DMA2D CLUT Loading.
742 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
743 * the configuration information for the DMA2D.
744 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
745 * the configuration information for the color look up table.
746 * @param LayerIdx: DMA2D Layer index.
747 * This parameter can be one of the following values:
748 * 0(background) / 1(foreground)
749 * @note Invoking this API is similar to calling HAL_DMA2D_ConfigCLUT() then HAL_DMA2D_EnableCLUT().
750 * @retval HAL status
751 */
752 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
753 {
754 /* Check the parameters */
755 assert_param(IS_DMA2D_LAYER(LayerIdx));
756 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
757 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
758
759 /* Process locked */
760 __HAL_LOCK(hdma2d);
761
762 /* Change DMA2D peripheral state */
763 hdma2d->State = HAL_DMA2D_STATE_BUSY;
764
765 /* Configure the CLUT of the background DMA2D layer */
766 if(LayerIdx == 0)
767 {
768 /* Write background CLUT memory address */
769 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
770
771 /* Write background CLUT size and CLUT color mode */
772 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
773 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
774
775 /* Enable the CLUT loading for the background */
776 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
777 }
778 /* Configure the CLUT of the foreground DMA2D layer */
779 else
780 {
781 /* Write foreground CLUT memory address */
782 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
783
784 /* Write foreground CLUT size and CLUT color mode */
785 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
786 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
787
788 /* Enable the CLUT loading for the foreground */
789 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
790 }
791
792 return HAL_OK;
793 }
794
795 /**
796 * @brief Start DMA2D CLUT Loading with interrupt enabled.
797 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
798 * the configuration information for the DMA2D.
799 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
800 * the configuration information for the color look up table.
801 * @param LayerIdx: DMA2D Layer index.
802 * This parameter can be one of the following values:
803 * 0(background) / 1(foreground)
804 * @retval HAL status
805 */
806 HAL_StatusTypeDef HAL_DMA2D_CLUTLoad_IT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
807 {
808 /* Check the parameters */
809 assert_param(IS_DMA2D_LAYER(LayerIdx));
810 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
811 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
812
813 /* Process locked */
814 __HAL_LOCK(hdma2d);
815
816 /* Change DMA2D peripheral state */
817 hdma2d->State = HAL_DMA2D_STATE_BUSY;
818
819 /* Configure the CLUT of the background DMA2D layer */
820 if(LayerIdx == 0)
821 {
822 /* Write background CLUT memory address */
823 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
824
825 /* Write background CLUT size and CLUT color mode */
826 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
827 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
828
829 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
830 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
831
832 /* Enable the CLUT loading for the background */
833 SET_BIT(hdma2d->Instance->BGPFCCR, DMA2D_BGPFCCR_START);
834 }
835 /* Configure the CLUT of the foreground DMA2D layer */
836 else
837 {
838 /* Write foreground CLUT memory address */
839 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
840
841 /* Write foreground CLUT size and CLUT color mode */
842 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
843 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
844
845 /* Enable the CLUT Transfer Complete, transfer Error, configuration Error and CLUT Access Error interrupts */
846 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
847
848 /* Enable the CLUT loading for the foreground */
849 SET_BIT(hdma2d->Instance->FGPFCCR, DMA2D_FGPFCCR_START);
850 }
851
852 return HAL_OK;
853 }
854
855 /**
856 * @brief Abort the DMA2D CLUT loading.
857 * @param hdma2d : Pointer to a DMA2D_HandleTypeDef structure that contains
858 * the configuration information for the DMA2D.
859 * @param LayerIdx: DMA2D Layer index.
860 * This parameter can be one of the following values:
861 * 0(background) / 1(foreground)
862 * @retval HAL status
863 */
864 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Abort(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
865 {
866 uint32_t tickstart = 0;
867 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
868
869 /* Abort the CLUT loading */
870 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_ABORT);
871
872 /* If foreground CLUT loading is considered, update local variables */
873 if(LayerIdx == 1)
874 {
875 reg = &(hdma2d->Instance->FGPFCCR);
876 }
877
878
879 /* Get tick */
880 tickstart = HAL_GetTick();
881
882 /* Check if the CLUT loading is aborted */
883 while((*reg & DMA2D_BGPFCCR_START) != RESET)
884 {
885 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_ABORT)
886 {
887 /* Update error code */
888 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
889
890 /* Change the DMA2D state */
891 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
892
893 /* Process Unlocked */
894 __HAL_UNLOCK(hdma2d);
895
896 return HAL_TIMEOUT;
897 }
898 }
899
900 /* Disable the CLUT Transfer Complete, Transfer Error, Configuration Error and CLUT Access Error interrupts */
901 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC | DMA2D_IT_TE | DMA2D_IT_CE |DMA2D_IT_CAE);
902
903 /* Change the DMA2D state*/
904 hdma2d->State = HAL_DMA2D_STATE_READY;
905
906 /* Process Unlocked */
907 __HAL_UNLOCK(hdma2d);
908
909 return HAL_OK;
910 }
911
912 /**
913 * @brief Suspend the DMA2D CLUT loading.
914 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
915 * the configuration information for the DMA2D.
916 * @param LayerIdx: DMA2D Layer index.
917 * This parameter can be one of the following values:
918 * 0(background) / 1(foreground)
919 * @retval HAL status
920 */
921 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Suspend(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
922 {
923 uint32_t tickstart = 0;
924 __IO uint32_t * reg = &(hdma2d->Instance->BGPFCCR); /* by default, point at background register */
925
926 /* Suspend the CLUT loading */
927 SET_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
928
929 /* If foreground CLUT loading is considered, update local variables */
930 if(LayerIdx == 1)
931 {
932 reg = &(hdma2d->Instance->FGPFCCR);
933 }
934
935 /* Get tick */
936 tickstart = HAL_GetTick();
937
938 /* Check if the CLUT loading is suspended */
939 while (((hdma2d->Instance->CR & DMA2D_CR_SUSP) != DMA2D_CR_SUSP) \
940 && ((*reg & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
941 {
942 if((HAL_GetTick() - tickstart ) > DMA2D_TIMEOUT_SUSPEND)
943 {
944 /* Update error code */
945 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
946
947 /* Change the DMA2D state */
948 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
949
950 return HAL_TIMEOUT;
951 }
952 }
953
954 /* Check whether or not a transfer is actually suspended and change the DMA2D state accordingly */
955 if ((*reg & DMA2D_BGPFCCR_START) != RESET)
956 {
957 hdma2d->State = HAL_DMA2D_STATE_SUSPEND;
958 }
959 else
960 {
961 /* Make sure SUSP bit is cleared since it is meaningless
962 when no tranfer is on-going */
963 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
964 }
965
966 return HAL_OK;
967 }
968
969 /**
970 * @brief Resume the DMA2D CLUT loading.
971 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
972 * the configuration information for the DMA2D.
973 * @param LayerIdx: DMA2D Layer index.
974 * This parameter can be one of the following values:
975 * 0(background) / 1(foreground)
976 * @retval HAL status
977 */
978 HAL_StatusTypeDef HAL_DMA2D_CLUTLoading_Resume(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
979 {
980 /* Check the SUSP and START bits for background or foreground CLUT loading */
981 if(LayerIdx == 0)
982 {
983 /* Background CLUT loading suspension check */
984 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
985 && ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) == DMA2D_BGPFCCR_START))
986 {
987 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
988 hdma2d->State = HAL_DMA2D_STATE_BUSY;
989 }
990 }
991 else
992 {
993 /* Foreground CLUT loading suspension check */
994 if (((hdma2d->Instance->CR & DMA2D_CR_SUSP) == DMA2D_CR_SUSP)
995 && ((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) == DMA2D_FGPFCCR_START))
996 {
997 /* Ongoing CLUT loading is suspended: change the DMA2D state before resuming */
998 hdma2d->State = HAL_DMA2D_STATE_BUSY;
999 }
1000 }
1001
1002 /* Resume the CLUT loading */
1003 CLEAR_BIT(hdma2d->Instance->CR, DMA2D_CR_SUSP);
1004
1005 return HAL_OK;
1006 }
1007
1008
1009 /**
1010
1011 * @brief Polling for transfer complete or CLUT loading.
1012 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1013 * the configuration information for the DMA2D.
1014 * @param Timeout: Timeout duration
1015 * @retval HAL status
1016 */
1017 HAL_StatusTypeDef HAL_DMA2D_PollForTransfer(DMA2D_HandleTypeDef *hdma2d, uint32_t Timeout)
1018 {
1019 uint32_t tickstart = 0;
1020 __IO uint32_t isrflags = 0x0;
1021
1022 /* Polling for DMA2D transfer */
1023 if((hdma2d->Instance->CR & DMA2D_CR_START) != RESET)
1024 {
1025 /* Get tick */
1026 tickstart = HAL_GetTick();
1027
1028 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_TC) == RESET)
1029 {
1030 isrflags = READ_REG(hdma2d->Instance->ISR);
1031 if ((isrflags & (DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1032 {
1033 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1034 {
1035 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1036 }
1037 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1038 {
1039 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1040 }
1041 /* Clear the transfer and configuration error flags */
1042 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1043
1044 /* Change DMA2D state */
1045 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1046
1047 /* Process unlocked */
1048 __HAL_UNLOCK(hdma2d);
1049
1050 return HAL_ERROR;
1051 }
1052 /* Check for the Timeout */
1053 if(Timeout != HAL_MAX_DELAY)
1054 {
1055 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1056 {
1057 /* Update error code */
1058 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1059
1060 /* Change the DMA2D state */
1061 hdma2d->State = HAL_DMA2D_STATE_TIMEOUT;
1062
1063 /* Process unlocked */
1064 __HAL_UNLOCK(hdma2d);
1065
1066 return HAL_TIMEOUT;
1067 }
1068 }
1069 }
1070 }
1071 /* Polling for CLUT loading (foreground or background) */
1072 if (((hdma2d->Instance->FGPFCCR & DMA2D_FGPFCCR_START) != RESET) ||
1073 ((hdma2d->Instance->BGPFCCR & DMA2D_BGPFCCR_START) != RESET))
1074 {
1075 /* Get tick */
1076 tickstart = HAL_GetTick();
1077
1078 while(__HAL_DMA2D_GET_FLAG(hdma2d, DMA2D_FLAG_CTC) == RESET)
1079 {
1080 isrflags = READ_REG(hdma2d->Instance->ISR);
1081 if ((isrflags & (DMA2D_FLAG_CAE|DMA2D_FLAG_CE|DMA2D_FLAG_TE)) != RESET)
1082 {
1083 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1084 {
1085 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1086 }
1087 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1088 {
1089 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1090 }
1091 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1092 {
1093 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1094 }
1095 /* Clear the CLUT Access Error, Configuration Error and Transfer Error flags */
1096 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE | DMA2D_FLAG_CE | DMA2D_FLAG_TE);
1097
1098 /* Change DMA2D state */
1099 hdma2d->State= HAL_DMA2D_STATE_ERROR;
1100
1101 /* Process unlocked */
1102 __HAL_UNLOCK(hdma2d);
1103
1104 return HAL_ERROR;
1105 }
1106 /* Check for the Timeout */
1107 if(Timeout != HAL_MAX_DELAY)
1108 {
1109 if((Timeout == 0)||((HAL_GetTick() - tickstart ) > Timeout))
1110 {
1111 /* Update error code */
1112 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TIMEOUT;
1113
1114 /* Change the DMA2D state */
1115 hdma2d->State= HAL_DMA2D_STATE_TIMEOUT;
1116
1117 /* Process unlocked */
1118 __HAL_UNLOCK(hdma2d);
1119
1120 return HAL_TIMEOUT;
1121 }
1122 }
1123 }
1124 }
1125
1126 /* Clear the transfer complete and CLUT loading flags */
1127 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC|DMA2D_FLAG_CTC);
1128
1129 /* Change DMA2D state */
1130 hdma2d->State = HAL_DMA2D_STATE_READY;
1131
1132 /* Process unlocked */
1133 __HAL_UNLOCK(hdma2d);
1134
1135 return HAL_OK;
1136 }
1137 /**
1138 * @brief Handle DMA2D interrupt request.
1139 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1140 * the configuration information for the DMA2D.
1141 * @retval HAL status
1142 */
1143 void HAL_DMA2D_IRQHandler(DMA2D_HandleTypeDef *hdma2d)
1144 {
1145 uint32_t isrflags = READ_REG(hdma2d->Instance->ISR);
1146 uint32_t crflags = READ_REG(hdma2d->Instance->CR);
1147
1148 /* Transfer Error Interrupt management ***************************************/
1149 if ((isrflags & DMA2D_FLAG_TE) != RESET)
1150 {
1151 if ((crflags & DMA2D_IT_TE) != RESET)
1152 {
1153 /* Disable the transfer Error interrupt */
1154 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TE);
1155
1156 /* Update error code */
1157 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_TE;
1158
1159 /* Clear the transfer error flag */
1160 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TE);
1161
1162 /* Change DMA2D state */
1163 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1164
1165 /* Process Unlocked */
1166 __HAL_UNLOCK(hdma2d);
1167
1168 if(hdma2d->XferErrorCallback != NULL)
1169 {
1170 /* Transfer error Callback */
1171 hdma2d->XferErrorCallback(hdma2d);
1172 }
1173 }
1174 }
1175 /* Configuration Error Interrupt management **********************************/
1176 if ((isrflags & DMA2D_FLAG_CE) != RESET)
1177 {
1178 if ((crflags & DMA2D_IT_CE) != RESET)
1179 {
1180 /* Disable the Configuration Error interrupt */
1181 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CE);
1182
1183 /* Clear the Configuration error flag */
1184 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CE);
1185
1186 /* Update error code */
1187 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CE;
1188
1189 /* Change DMA2D state */
1190 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1191
1192 /* Process Unlocked */
1193 __HAL_UNLOCK(hdma2d);
1194
1195 if(hdma2d->XferErrorCallback != NULL)
1196 {
1197 /* Transfer error Callback */
1198 hdma2d->XferErrorCallback(hdma2d);
1199 }
1200 }
1201 }
1202 /* CLUT access Error Interrupt management ***********************************/
1203 if ((isrflags & DMA2D_FLAG_CAE) != RESET)
1204 {
1205 if ((crflags & DMA2D_IT_CAE) != RESET)
1206 {
1207 /* Disable the CLUT access error interrupt */
1208 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CAE);
1209
1210 /* Clear the CLUT access error flag */
1211 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CAE);
1212
1213 /* Update error code */
1214 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_CAE;
1215
1216 /* Change DMA2D state */
1217 hdma2d->State = HAL_DMA2D_STATE_ERROR;
1218
1219 /* Process Unlocked */
1220 __HAL_UNLOCK(hdma2d);
1221
1222 if(hdma2d->XferErrorCallback != NULL)
1223 {
1224 /* Transfer error Callback */
1225 hdma2d->XferErrorCallback(hdma2d);
1226 }
1227 }
1228 }
1229 /* Transfer watermark Interrupt management **********************************/
1230 if ((isrflags & DMA2D_FLAG_TW) != RESET)
1231 {
1232 if ((crflags & DMA2D_IT_TW) != RESET)
1233 {
1234 /* Disable the transfer watermark interrupt */
1235 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TW);
1236
1237 /* Clear the transfer watermark flag */
1238 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TW);
1239
1240 /* Transfer watermark Callback */
1241 HAL_DMA2D_LineEventCallback(hdma2d);
1242 }
1243 }
1244 /* Transfer Complete Interrupt management ************************************/
1245 if ((isrflags & DMA2D_FLAG_TC) != RESET)
1246 {
1247 if ((crflags & DMA2D_IT_TC) != RESET)
1248 {
1249 /* Disable the transfer complete interrupt */
1250 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_TC);
1251
1252 /* Clear the transfer complete flag */
1253 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_TC);
1254
1255 /* Update error code */
1256 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1257
1258 /* Change DMA2D state */
1259 hdma2d->State = HAL_DMA2D_STATE_READY;
1260
1261 /* Process Unlocked */
1262 __HAL_UNLOCK(hdma2d);
1263
1264 if(hdma2d->XferCpltCallback != NULL)
1265 {
1266 /* Transfer complete Callback */
1267 hdma2d->XferCpltCallback(hdma2d);
1268 }
1269 }
1270 }
1271 /* CLUT Transfer Complete Interrupt management ******************************/
1272 if ((isrflags & DMA2D_FLAG_CTC) != RESET)
1273 {
1274 if ((crflags & DMA2D_IT_CTC) != RESET)
1275 {
1276 /* Disable the CLUT transfer complete interrupt */
1277 __HAL_DMA2D_DISABLE_IT(hdma2d, DMA2D_IT_CTC);
1278
1279 /* Clear the CLUT transfer complete flag */
1280 __HAL_DMA2D_CLEAR_FLAG(hdma2d, DMA2D_FLAG_CTC);
1281
1282 /* Update error code */
1283 hdma2d->ErrorCode |= HAL_DMA2D_ERROR_NONE;
1284
1285 /* Change DMA2D state */
1286 hdma2d->State = HAL_DMA2D_STATE_READY;
1287
1288 /* Process Unlocked */
1289 __HAL_UNLOCK(hdma2d);
1290
1291 /* CLUT Transfer complete Callback */
1292 HAL_DMA2D_CLUTLoadingCpltCallback(hdma2d);
1293 }
1294 }
1295
1296 }
1297
1298 /**
1299 * @brief Transfer watermark callback.
1300 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1301 * the configuration information for the DMA2D.
1302 * @retval None
1303 */
1304 __weak void HAL_DMA2D_LineEventCallback(DMA2D_HandleTypeDef *hdma2d)
1305 {
1306 /* Prevent unused argument(s) compilation warning */
1307 UNUSED(hdma2d);
1308
1309 /* NOTE : This function should not be modified; when the callback is needed,
1310 the HAL_DMA2D_LineEventCallback can be implemented in the user file.
1311 */
1312 }
1313
1314 /**
1315 * @brief CLUT Transfer Complete callback.
1316 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1317 * the configuration information for the DMA2D.
1318 * @retval None
1319 */
1320 __weak void HAL_DMA2D_CLUTLoadingCpltCallback(DMA2D_HandleTypeDef *hdma2d)
1321 {
1322 /* Prevent unused argument(s) compilation warning */
1323 UNUSED(hdma2d);
1324
1325 /* NOTE : This function should not be modified; when the callback is needed,
1326 the HAL_DMA2D_CLUTLoadingCpltCallback can be implemented in the user file.
1327 */
1328 }
1329
1330 /**
1331 * @}
1332 */
1333
1334 /** @defgroup DMA2D_Exported_Functions_Group3 Peripheral Control functions
1335 * @brief Peripheral Control functions
1336 *
1337 @verbatim
1338 ===============================================================================
1339 ##### Peripheral Control functions #####
1340 ===============================================================================
1341 [..] This section provides functions allowing to:
1342 (+) Configure the DMA2D foreground or background layer parameters.
1343 (+) Configure the DMA2D CLUT transfer.
1344 (+) Configure the line watermark
1345 (+) Configure the dead time value.
1346 (+) Enable or disable the dead time value functionality.
1347
1348
1349 @endverbatim
1350 * @{
1351 */
1352
1353 /**
1354 * @brief Configure the DMA2D Layer according to the specified
1355 * parameters in the DMA2D_InitTypeDef and create the associated handle.
1356 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1357 * the configuration information for the DMA2D.
1358 * @param LayerIdx: DMA2D Layer index.
1359 * This parameter can be one of the following values:
1360 * 0(background) / 1(foreground)
1361 * @retval HAL status
1362 */
1363 HAL_StatusTypeDef HAL_DMA2D_ConfigLayer(DMA2D_HandleTypeDef *hdma2d, uint32_t LayerIdx)
1364 {
1365 DMA2D_LayerCfgTypeDef *pLayerCfg = &hdma2d->LayerCfg[LayerIdx];
1366
1367 uint32_t regMask = 0, regValue = 0;
1368
1369 /* Check the parameters */
1370 assert_param(IS_DMA2D_LAYER(LayerIdx));
1371 assert_param(IS_DMA2D_OFFSET(pLayerCfg->InputOffset));
1372 if(hdma2d->Init.Mode != DMA2D_R2M)
1373 {
1374 assert_param(IS_DMA2D_INPUT_COLOR_MODE(pLayerCfg->InputColorMode));
1375 if(hdma2d->Init.Mode != DMA2D_M2M)
1376 {
1377 assert_param(IS_DMA2D_ALPHA_MODE(pLayerCfg->AlphaMode));
1378 }
1379 }
1380
1381 /* Process locked */
1382 __HAL_LOCK(hdma2d);
1383
1384 /* Change DMA2D peripheral state */
1385 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1386
1387 /* DMA2D BGPFCR register configuration -----------------------------------*/
1388 /* Prepare the value to be written to the BGPFCCR register */
1389
1390 regValue = pLayerCfg->InputColorMode | (pLayerCfg->AlphaMode << DMA2D_POSITION_BGPFCCR_AM);
1391 regMask = DMA2D_BGPFCCR_CM | DMA2D_BGPFCCR_AM | DMA2D_BGPFCCR_ALPHA;
1392
1393 #if defined (DMA2D_FGPFCCR_AI) && defined (DMA2D_BGPFCCR_AI)
1394 regValue |= (pLayerCfg->AlphaInverted << DMA2D_POSITION_BGPFCCR_AI);
1395 regMask |= DMA2D_BGPFCCR_AI;
1396 #endif /* (DMA2D_FGPFCCR_AI) && (DMA2D_BGPFCCR_AI) */
1397
1398 #if defined (DMA2D_FGPFCCR_RBS) && defined (DMA2D_BGPFCCR_RBS)
1399 regValue |= (pLayerCfg->RedBlueSwap << DMA2D_POSITION_BGPFCCR_RBS);
1400 regMask |= DMA2D_BGPFCCR_RBS;
1401 #endif
1402
1403 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1404 {
1405 regValue |= (pLayerCfg->InputAlpha & DMA2D_BGPFCCR_ALPHA);
1406 }
1407 else
1408 {
1409 regValue |= (pLayerCfg->InputAlpha << DMA2D_POSITION_BGPFCCR_ALPHA);
1410 }
1411
1412 /* Configure the background DMA2D layer */
1413 if(LayerIdx == 0)
1414 {
1415 /* Write DMA2D BGPFCCR register */
1416 MODIFY_REG(hdma2d->Instance->BGPFCCR, regMask, regValue);
1417
1418 /* DMA2D BGOR register configuration -------------------------------------*/
1419 WRITE_REG(hdma2d->Instance->BGOR, pLayerCfg->InputOffset);
1420
1421 /* DMA2D BGCOLR register configuration -------------------------------------*/
1422 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1423 {
1424 WRITE_REG(hdma2d->Instance->BGCOLR, pLayerCfg->InputAlpha & (DMA2D_BGCOLR_BLUE|DMA2D_BGCOLR_GREEN|DMA2D_BGCOLR_RED));
1425 }
1426 }
1427 /* Configure the foreground DMA2D layer */
1428 else
1429 {
1430 /* Write DMA2D FGPFCCR register */
1431 MODIFY_REG(hdma2d->Instance->FGPFCCR, regMask, regValue);
1432
1433 /* DMA2D FGOR register configuration -------------------------------------*/
1434 WRITE_REG(hdma2d->Instance->FGOR, pLayerCfg->InputOffset);
1435
1436 /* DMA2D FGCOLR register configuration -------------------------------------*/
1437 if ((pLayerCfg->InputColorMode == DMA2D_INPUT_A4) || (pLayerCfg->InputColorMode == DMA2D_INPUT_A8))
1438 {
1439 WRITE_REG(hdma2d->Instance->FGCOLR, pLayerCfg->InputAlpha & (DMA2D_FGCOLR_BLUE|DMA2D_FGCOLR_GREEN|DMA2D_FGCOLR_RED));
1440 }
1441 }
1442 /* Initialize the DMA2D state*/
1443 hdma2d->State = HAL_DMA2D_STATE_READY;
1444
1445 /* Process unlocked */
1446 __HAL_UNLOCK(hdma2d);
1447
1448 return HAL_OK;
1449 }
1450
1451 /**
1452 * @brief Configure the DMA2D CLUT Transfer.
1453 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1454 * the configuration information for the DMA2D.
1455 * @param CLUTCfg: Pointer to a DMA2D_CLUTCfgTypeDef structure that contains
1456 * the configuration information for the color look up table.
1457 * @param LayerIdx: DMA2D Layer index.
1458 * This parameter can be one of the following values:
1459 * 0(background) / 1(foreground)
1460 * @retval HAL status
1461 */
1462 HAL_StatusTypeDef HAL_DMA2D_ConfigCLUT(DMA2D_HandleTypeDef *hdma2d, DMA2D_CLUTCfgTypeDef CLUTCfg, uint32_t LayerIdx)
1463 {
1464 /* Check the parameters */
1465 assert_param(IS_DMA2D_LAYER(LayerIdx));
1466 assert_param(IS_DMA2D_CLUT_CM(CLUTCfg.CLUTColorMode));
1467 assert_param(IS_DMA2D_CLUT_SIZE(CLUTCfg.Size));
1468
1469 /* Process locked */
1470 __HAL_LOCK(hdma2d);
1471
1472 /* Change DMA2D peripheral state */
1473 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1474
1475 /* Configure the CLUT of the background DMA2D layer */
1476 if(LayerIdx == 0)
1477 {
1478 /* Write background CLUT memory address */
1479 WRITE_REG(hdma2d->Instance->BGCMAR, (uint32_t)CLUTCfg.pCLUT);
1480
1481 /* Write background CLUT size and CLUT color mode */
1482 MODIFY_REG(hdma2d->Instance->BGPFCCR, (DMA2D_BGPFCCR_CS | DMA2D_BGPFCCR_CCM),
1483 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_BGPFCCR_CCM)));
1484 }
1485 /* Configure the CLUT of the foreground DMA2D layer */
1486 else
1487 {
1488 /* Write foreground CLUT memory address */
1489 WRITE_REG(hdma2d->Instance->FGCMAR, (uint32_t)CLUTCfg.pCLUT);
1490
1491 /* Write foreground CLUT size and CLUT color mode */
1492 MODIFY_REG(hdma2d->Instance->FGPFCCR, (DMA2D_FGPFCCR_CS | DMA2D_FGPFCCR_CCM),
1493 ((CLUTCfg.Size << DMA2D_POSITION_BGPFCCR_CS) | (CLUTCfg.CLUTColorMode << DMA2D_POSITION_FGPFCCR_CCM)));
1494 }
1495
1496 /* Set the DMA2D state to Ready*/
1497 hdma2d->State = HAL_DMA2D_STATE_READY;
1498
1499 /* Process unlocked */
1500 __HAL_UNLOCK(hdma2d);
1501
1502 return HAL_OK;
1503 }
1504
1505
1506 /**
1507 * @brief Configure the line watermark.
1508 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1509 * the configuration information for the DMA2D.
1510 * @param Line: Line Watermark configuration (maximum 16-bit long value expected).
1511 * @note HAL_DMA2D_ProgramLineEvent() API enables the transfer watermark interrupt.
1512 * @note The transfer watermark interrupt is disabled once it has occurred.
1513 * @retval HAL status
1514 */
1515
1516 HAL_StatusTypeDef HAL_DMA2D_ProgramLineEvent(DMA2D_HandleTypeDef *hdma2d, uint32_t Line)
1517 {
1518 /* Check the parameters */
1519 assert_param(IS_DMA2D_LINEWATERMARK(Line));
1520
1521 if (Line > DMA2D_LWR_LW)
1522 {
1523 return HAL_ERROR;
1524 }
1525 else
1526 {
1527 /* Process locked */
1528 __HAL_LOCK(hdma2d);
1529
1530 /* Change DMA2D peripheral state */
1531 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1532
1533 /* Sets the Line watermark configuration */
1534 WRITE_REG(hdma2d->Instance->LWR, Line);
1535
1536 /* Enable the Line interrupt */
1537 __HAL_DMA2D_ENABLE_IT(hdma2d, DMA2D_IT_TW);
1538
1539 /* Initialize the DMA2D state*/
1540 hdma2d->State = HAL_DMA2D_STATE_READY;
1541
1542 /* Process unlocked */
1543 __HAL_UNLOCK(hdma2d);
1544
1545 return HAL_OK;
1546 }
1547 }
1548
1549 /**
1550 * @brief Enable DMA2D dead time feature.
1551 * @param hdma2d: DMA2D handle.
1552 * @retval HAL status
1553 */
1554 HAL_StatusTypeDef HAL_DMA2D_EnableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1555 {
1556 /* Process Locked */
1557 __HAL_LOCK(hdma2d);
1558
1559 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1560
1561 /* Set DMA2D_AMTCR EN bit */
1562 SET_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1563
1564 hdma2d->State = HAL_DMA2D_STATE_READY;
1565
1566 /* Process Unlocked */
1567 __HAL_UNLOCK(hdma2d);
1568
1569 return HAL_OK;
1570 }
1571
1572 /**
1573 * @brief Disable DMA2D dead time feature.
1574 * @param hdma2d: DMA2D handle.
1575 * @retval HAL status
1576 */
1577 HAL_StatusTypeDef HAL_DMA2D_DisableDeadTime(DMA2D_HandleTypeDef *hdma2d)
1578 {
1579 /* Process Locked */
1580 __HAL_LOCK(hdma2d);
1581
1582 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1583
1584 /* Clear DMA2D_AMTCR EN bit */
1585 CLEAR_BIT(hdma2d->Instance->AMTCR, DMA2D_AMTCR_EN);
1586
1587 hdma2d->State = HAL_DMA2D_STATE_READY;
1588
1589 /* Process Unlocked */
1590 __HAL_UNLOCK(hdma2d);
1591
1592 return HAL_OK;
1593 }
1594
1595 /**
1596 * @brief Configure dead time.
1597 * @note The dead time value represents the guaranteed minimum number of cycles between
1598 * two consecutive transactions on the AHB bus.
1599 * @param hdma2d: DMA2D handle.
1600 * @param DeadTime: dead time value.
1601 * @retval HAL status
1602 */
1603 HAL_StatusTypeDef HAL_DMA2D_ConfigDeadTime(DMA2D_HandleTypeDef *hdma2d, uint8_t DeadTime)
1604 {
1605 /* Process Locked */
1606 __HAL_LOCK(hdma2d);
1607
1608 hdma2d->State = HAL_DMA2D_STATE_BUSY;
1609
1610 /* Set DMA2D_AMTCR DT field */
1611 MODIFY_REG(hdma2d->Instance->AMTCR, DMA2D_AMTCR_DT, (((uint32_t) DeadTime) << DMA2D_POSITION_AMTCR_DT));
1612
1613 hdma2d->State = HAL_DMA2D_STATE_READY;
1614
1615 /* Process Unlocked */
1616 __HAL_UNLOCK(hdma2d);
1617
1618 return HAL_OK;
1619 }
1620
1621 /**
1622 * @}
1623 */
1624
1625
1626 /** @defgroup DMA2D_Exported_Functions_Group4 Peripheral State and Error functions
1627 * @brief Peripheral State functions
1628 *
1629 @verbatim
1630 ===============================================================================
1631 ##### Peripheral State and Errors functions #####
1632 ===============================================================================
1633 [..]
1634 This subsection provides functions allowing to :
1635 (+) Get the DMA2D state
1636 (+) Get the DMA2D error code
1637
1638 @endverbatim
1639 * @{
1640 */
1641
1642 /**
1643 * @brief Return the DMA2D state
1644 * @param hdma2d: pointer to a DMA2D_HandleTypeDef structure that contains
1645 * the configuration information for the DMA2D.
1646 * @retval HAL state
1647 */
1648 HAL_DMA2D_StateTypeDef HAL_DMA2D_GetState(DMA2D_HandleTypeDef *hdma2d)
1649 {
1650 return hdma2d->State;
1651 }
1652
1653 /**
1654 * @brief Return the DMA2D error code
1655 * @param hdma2d : pointer to a DMA2D_HandleTypeDef structure that contains
1656 * the configuration information for DMA2D.
1657 * @retval DMA2D Error Code
1658 */
1659 uint32_t HAL_DMA2D_GetError(DMA2D_HandleTypeDef *hdma2d)
1660 {
1661 return hdma2d->ErrorCode;
1662 }
1663
1664 /**
1665 * @}
1666 */
1667
1668 /**
1669 * @}
1670 */
1671
1672
1673 /** @defgroup DMA2D_Private_Functions DMA2D Private Functions
1674 * @{
1675 */
1676
1677 /**
1678 * @brief Set the DMA2D transfer parameters.
1679 * @param hdma2d: Pointer to a DMA2D_HandleTypeDef structure that contains
1680 * the configuration information for the specified DMA2D.
1681 * @param pdata: The source memory Buffer address
1682 * @param DstAddress: The destination memory Buffer address
1683 * @param Width: The width of data to be transferred from source to destination.
1684 * @param Height: The height of data to be transferred from source to destination.
1685 * @retval HAL status
1686 */
1687 static void DMA2D_SetConfig(DMA2D_HandleTypeDef *hdma2d, uint32_t pdata, uint32_t DstAddress, uint32_t Width, uint32_t Height)
1688 {
1689 uint32_t tmp = 0;
1690 uint32_t tmp1 = 0;
1691 uint32_t tmp2 = 0;
1692 uint32_t tmp3 = 0;
1693 uint32_t tmp4 = 0;
1694
1695 /* Configure DMA2D data size */
1696 MODIFY_REG(hdma2d->Instance->NLR, (DMA2D_NLR_NL|DMA2D_NLR_PL), (Height| (Width << DMA2D_POSITION_NLR_PL)));
1697
1698 /* Configure DMA2D destination address */
1699 WRITE_REG(hdma2d->Instance->OMAR, DstAddress);
1700
1701 /* Register to memory DMA2D mode selected */
1702 if (hdma2d->Init.Mode == DMA2D_R2M)
1703 {
1704 tmp1 = pdata & DMA2D_OCOLR_ALPHA_1;
1705 tmp2 = pdata & DMA2D_OCOLR_RED_1;
1706 tmp3 = pdata & DMA2D_OCOLR_GREEN_1;
1707 tmp4 = pdata & DMA2D_OCOLR_BLUE_1;
1708
1709 /* Prepare the value to be written to the OCOLR register according to the color mode */
1710 if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB8888)
1711 {
1712 tmp = (tmp3 | tmp2 | tmp1| tmp4);
1713 }
1714 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB888)
1715 {
1716 tmp = (tmp3 | tmp2 | tmp4);
1717 }
1718 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_RGB565)
1719 {
1720 tmp2 = (tmp2 >> 19);
1721 tmp3 = (tmp3 >> 10);
1722 tmp4 = (tmp4 >> 3 );
1723 tmp = ((tmp3 << 5) | (tmp2 << 11) | tmp4);
1724 }
1725 else if (hdma2d->Init.ColorMode == DMA2D_OUTPUT_ARGB1555)
1726 {
1727 tmp1 = (tmp1 >> 31);
1728 tmp2 = (tmp2 >> 19);
1729 tmp3 = (tmp3 >> 11);
1730 tmp4 = (tmp4 >> 3 );
1731 tmp = ((tmp3 << 5) | (tmp2 << 10) | (tmp1 << 15) | tmp4);
1732 }
1733 else /* Dhdma2d->Init.ColorMode = DMA2D_OUTPUT_ARGB4444 */
1734 {
1735 tmp1 = (tmp1 >> 28);
1736 tmp2 = (tmp2 >> 20);
1737 tmp3 = (tmp3 >> 12);
1738 tmp4 = (tmp4 >> 4 );
1739 tmp = ((tmp3 << 4) | (tmp2 << 8) | (tmp1 << 12) | tmp4);
1740 }
1741 /* Write to DMA2D OCOLR register */
1742 WRITE_REG(hdma2d->Instance->OCOLR, tmp);
1743 }
1744 else /* M2M, M2M_PFC or M2M_Blending DMA2D Mode */
1745 {
1746 /* Configure DMA2D source address */
1747 WRITE_REG(hdma2d->Instance->FGMAR, pdata);
1748 }
1749 }
1750
1751 /**
1752 * @}
1753 */
1754 #endif /* DMA2D */
1755 #endif /* HAL_DMA2D_MODULE_ENABLED */
1756 /**
1757 * @}
1758 */
1759
1760 /**
1761 * @}
1762 */
1763
1764 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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