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Merge pull request #10558 from iNavFlight/MrD_Correct-comments-on-OSD-symbols
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_hal_i2c.c
blob5ba136e1b83a80487416012dcbf149082890d470
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_hal_i2c.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief I2C HAL module driver.
8 * This file provides firmware functions to manage the following
9 * functionalities of the Inter Integrated Circuit (I2C) peripheral:
10 * + Initialization and de-initialization functions
11 * + IO operation functions
12 * + Peripheral State and Errors functions
13 *
14 @verbatim
15 ==============================================================================
16 ##### How to use this driver #####
17 ==============================================================================
18 [..]
19 The I2C HAL driver can be used as follows:
20
21 (#) Declare a I2C_HandleTypeDef handle structure, for example:
22 I2C_HandleTypeDef hi2c;
23
24 (#)Initialize the I2C low level resources by implementing the HAL_I2C_MspInit() API:
25 (##) Enable the I2Cx interface clock
26 (##) I2C pins configuration
27 (+++) Enable the clock for the I2C GPIOs
28 (+++) Configure I2C pins as alternate function open-drain
29 (##) NVIC configuration if you need to use interrupt process
30 (+++) Configure the I2Cx interrupt priority
31 (+++) Enable the NVIC I2C IRQ Channel
32 (##) DMA Configuration if you need to use DMA process
33 (+++) Declare a DMA_HandleTypeDef handle structure for the transmit or receive stream
34 (+++) Enable the DMAx interface clock using
35 (+++) Configure the DMA handle parameters
36 (+++) Configure the DMA Tx or Rx stream
37 (+++) Associate the initialized DMA handle to the hi2c DMA Tx or Rx handle
38 (+++) Configure the priority and enable the NVIC for the transfer complete interrupt on
39 the DMA Tx or Rx stream
40
41 (#) Configure the Communication Clock Timing, Own Address1, Master Addressing mode, Dual Addressing mode,
42 Own Address2, Own Address2 Mask, General call and Nostretch mode in the hi2c Init structure.
43
44 (#) Initialize the I2C registers by calling the HAL_I2C_Init(), configures also the low level Hardware
45 (GPIO, CLOCK, NVIC...etc) by calling the customized HAL_I2C_MspInit(&hi2c) API.
46
47 (#) To check if target device is ready for communication, use the function HAL_I2C_IsDeviceReady()
48
49 (#) For I2C IO and IO MEM operations, three operation modes are available within this driver :
50
51 *** Polling mode IO operation ***
52 =================================
53 [..]
54 (+) Transmit in master mode an amount of data in blocking mode using HAL_I2C_Master_Transmit()
55 (+) Receive in master mode an amount of data in blocking mode using HAL_I2C_Master_Receive()
56 (+) Transmit in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Transmit()
57 (+) Receive in slave mode an amount of data in blocking mode using HAL_I2C_Slave_Receive()
58
59 *** Polling mode IO MEM operation ***
60 =====================================
61 [..]
62 (+) Write an amount of data in blocking mode to a specific memory address using HAL_I2C_Mem_Write()
63 (+) Read an amount of data in blocking mode from a specific memory address using HAL_I2C_Mem_Read()
64
65
66 *** Interrupt mode IO operation ***
67 ===================================
68 [..]
69 (+) Transmit in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Transmit_IT()
70 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
71 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
72 (+) Receive in master mode an amount of data in non-blocking mode using HAL_I2C_Master_Receive_IT()
73 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
74 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
75 (+) Transmit in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Transmit_IT()
76 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
77 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
78 (+) Receive in slave mode an amount of data in non-blocking mode using HAL_I2C_Slave_Receive_IT()
79 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
80 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
81 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
82 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
83 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
84 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
85 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
86 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
87 This action will inform Master to generate a Stop condition to discard the communication.
88
89
90 *** Interrupt mode IO sequential operation ***
91 ==============================================
92 [..]
93 (@) These interfaces allow to manage a sequential transfer with a repeated start condition
94 when a direction change during transfer
95 [..]
96 (+) A specific option field manage the different steps of a sequential transfer
97 (+) Option field values are defined through @ref I2C_XFEROPTIONS and are listed below:
98 (++) I2C_FIRST_AND_LAST_FRAME: No sequential usage, functionnal is same as associated interfaces in no sequential mode
99 (++) I2C_FIRST_FRAME: Sequential usage, this option allow to manage a sequence with start condition, address
100 and data to transfer without a final stop condition
101 (++) I2C_FIRST_AND_NEXT_FRAME: Sequential usage (Master only), this option allow to manage a sequence with start condition, address
102 and data to transfer without a final stop condition, an then permit a call the same master sequential interface
103 several times (like HAL_I2C_Master_Sequential_Transmit_IT() then HAL_I2C_Master_Sequential_Transmit_IT())
104 (++) I2C_NEXT_FRAME: Sequential usage, this option allow to manage a sequence with a restart condition, address
105 and with new data to transfer if the direction change or manage only the new data to transfer
106 if no direction change and without a final stop condition in both cases
107 (++) I2C_LAST_FRAME: Sequential usage, this option allow to manage a sequance with a restart condition, address
108 and with new data to transfer if the direction change or manage only the new data to transfer
109 if no direction change and with a final stop condition in both cases
110
111 (+) Differents sequential I2C interfaces are listed below:
112 (++) Sequential transmit in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Transmit_IT()
113 (+++) At transmission end of current frame transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
114 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
115 (++) Sequential receive in master I2C mode an amount of data in non-blocking mode using HAL_I2C_Master_Sequential_Receive_IT()
116 (+++) At reception end of current frame transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
117 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
118 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
119 (+++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
120 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
121 (++) Enable/disable the Address listen mode in slave I2C mode using HAL_I2C_EnableListen_IT() HAL_I2C_DisableListen_IT()
122 (+++) When address slave I2C match, HAL_I2C_AddrCallback() is executed and user can
123 add his own code to check the Address Match Code and the transmission direction request by master (Write/Read).
124 (+++) At Listen mode end HAL_I2C_ListenCpltCallback() is executed and user can
125 add his own code by customization of function pointer HAL_I2C_ListenCpltCallback()
126 (++) Sequential transmit in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Transmit_IT()
127 (+++) At transmission end of current frame transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
128 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
129 (++) Sequential receive in slave I2C mode an amount of data in non-blocking mode using HAL_I2C_Slave_Sequential_Receive_IT()
130 (+++) At reception end of current frame transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
131 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
132 (++) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
133 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
134 (++) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
135 (++) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
136 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
137 (++) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
138 This action will inform Master to generate a Stop condition to discard the communication.
139
140 *** Interrupt mode IO MEM operation ***
141 =======================================
142 [..]
143 (+) Write an amount of data in non-blocking mode with Interrupt to a specific memory address using
144 HAL_I2C_Mem_Write_IT()
145 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
146 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
147 (+) Read an amount of data in non-blocking mode with Interrupt from a specific memory address using
148 HAL_I2C_Mem_Read_IT()
149 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
150 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
151 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
152 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
153
154 *** DMA mode IO operation ***
155 ==============================
156 [..]
157 (+) Transmit in master mode an amount of data in non-blocking mode (DMA) using
158 HAL_I2C_Master_Transmit_DMA()
159 (+) At transmission end of transfer, HAL_I2C_MasterTxCpltCallback() is executed and user can
160 add his own code by customization of function pointer HAL_I2C_MasterTxCpltCallback()
161 (+) Receive in master mode an amount of data in non-blocking mode (DMA) using
162 HAL_I2C_Master_Receive_DMA()
163 (+) At reception end of transfer, HAL_I2C_MasterRxCpltCallback() is executed and user can
164 add his own code by customization of function pointer HAL_I2C_MasterRxCpltCallback()
165 (+) Transmit in slave mode an amount of data in non-blocking mode (DMA) using
166 HAL_I2C_Slave_Transmit_DMA()
167 (+) At transmission end of transfer, HAL_I2C_SlaveTxCpltCallback() is executed and user can
168 add his own code by customization of function pointer HAL_I2C_SlaveTxCpltCallback()
169 (+) Receive in slave mode an amount of data in non-blocking mode (DMA) using
170 HAL_I2C_Slave_Receive_DMA()
171 (+) At reception end of transfer, HAL_I2C_SlaveRxCpltCallback() is executed and user can
172 add his own code by customization of function pointer HAL_I2C_SlaveRxCpltCallback()
173 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
174 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
175 (+) Abort a master I2C process communication with Interrupt using HAL_I2C_Master_Abort_IT()
176 (+) End of abort process, HAL_I2C_AbortCpltCallback() is executed and user can
177 add his own code by customization of function pointer HAL_I2C_AbortCpltCallback()
178 (+) Discard a slave I2C process communication using __HAL_I2C_GENERATE_NACK() macro.
179 This action will inform Master to generate a Stop condition to discard the communication.
180
181 *** DMA mode IO MEM operation ***
182 =================================
183 [..]
184 (+) Write an amount of data in non-blocking mode with DMA to a specific memory address using
185 HAL_I2C_Mem_Write_DMA()
186 (+) At Memory end of write transfer, HAL_I2C_MemTxCpltCallback() is executed and user can
187 add his own code by customization of function pointer HAL_I2C_MemTxCpltCallback()
188 (+) Read an amount of data in non-blocking mode with DMA from a specific memory address using
189 HAL_I2C_Mem_Read_DMA()
190 (+) At Memory end of read transfer, HAL_I2C_MemRxCpltCallback() is executed and user can
191 add his own code by customization of function pointer HAL_I2C_MemRxCpltCallback()
192 (+) In case of transfer Error, HAL_I2C_ErrorCallback() function is executed and user can
193 add his own code by customization of function pointer HAL_I2C_ErrorCallback()
194
195
196 *** I2C HAL driver macros list ***
197 ==================================
198 [..]
199 Below the list of most used macros in I2C HAL driver.
200
201 (+) __HAL_I2C_ENABLE: Enable the I2C peripheral
202 (+) __HAL_I2C_DISABLE: Disable the I2C peripheral
203 (+) __HAL_I2C_GENERATE_NACK: Generate a Non-Acknowledge I2C peripheral in Slave mode
204 (+) __HAL_I2C_GET_FLAG: Check whether the specified I2C flag is set or not
205 (+) __HAL_I2C_CLEAR_FLAG: Clear the specified I2C pending flag
206 (+) __HAL_I2C_ENABLE_IT: Enable the specified I2C interrupt
207 (+) __HAL_I2C_DISABLE_IT: Disable the specified I2C interrupt
208
209 [..]
210 (@) You can refer to the I2C HAL driver header file for more useful macros
211
212 @endverbatim
213 ******************************************************************************
214 * @attention
215 *
216 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
217 *
218 * Redistribution and use in source and binary forms, with or without modification,
219 * are permitted provided that the following conditions are met:
220 * 1. Redistributions of source code must retain the above copyright notice,
221 * this list of conditions and the following disclaimer.
222 * 2. Redistributions in binary form must reproduce the above copyright notice,
223 * this list of conditions and the following disclaimer in the documentation
224 * and/or other materials provided with the distribution.
225 * 3. Neither the name of STMicroelectronics nor the names of its contributors
226 * may be used to endorse or promote products derived from this software
227 * without specific prior written permission.
228 *
229 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
230 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
231 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
232 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
233 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
234 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
235 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
236 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
237 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
238 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
239 *
240 ******************************************************************************
241 */
242
243 /* Includes ------------------------------------------------------------------*/
244 #include "stm32f7xx_hal.h"
245
246 /** @addtogroup STM32F7xx_HAL_Driver
247 * @{
248 */
249
250 /** @defgroup I2C I2C
251 * @brief I2C HAL module driver
252 * @{
253 */
254
255 #ifdef HAL_I2C_MODULE_ENABLED
256
257 /* Private typedef -----------------------------------------------------------*/
258 /* Private define ------------------------------------------------------------*/
259
260 /** @defgroup I2C_Private_Define I2C Private Define
261 * @{
262 */
263 #define TIMING_CLEAR_MASK (0xF0FFFFFFU) /*!< I2C TIMING clear register Mask */
264 #define I2C_TIMEOUT_ADDR (10000U) /*!< 10 s */
265 #define I2C_TIMEOUT_BUSY (25U) /*!< 25 ms */
266 #define I2C_TIMEOUT_DIR (25U) /*!< 25 ms */
267 #define I2C_TIMEOUT_RXNE (25U) /*!< 25 ms */
268 #define I2C_TIMEOUT_STOPF (25U) /*!< 25 ms */
269 #define I2C_TIMEOUT_TC (25U) /*!< 25 ms */
270 #define I2C_TIMEOUT_TCR (25U) /*!< 25 ms */
271 #define I2C_TIMEOUT_TXIS (25U) /*!< 25 ms */
272 #define I2C_TIMEOUT_FLAG (25U) /*!< 25 ms */
273
274 #define MAX_NBYTE_SIZE 255U
275 #define SlaveAddr_SHIFT 7U
276 #define SlaveAddr_MSK 0x06U
277
278 /* Private define for @ref PreviousState usage */
279 #define I2C_STATE_MSK ((uint32_t)((HAL_I2C_STATE_BUSY_TX | HAL_I2C_STATE_BUSY_RX) & (~((uint32_t)HAL_I2C_STATE_READY)))) /*!< Mask State define, keep only RX and TX bits */
280 #define I2C_STATE_NONE ((uint32_t)(HAL_I2C_MODE_NONE)) /*!< Default Value */
281 #define I2C_STATE_MASTER_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy TX, combinaison of State LSB and Mode enum */
282 #define I2C_STATE_MASTER_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MASTER)) /*!< Master Busy RX, combinaison of State LSB and Mode enum */
283 #define I2C_STATE_SLAVE_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy TX, combinaison of State LSB and Mode enum */
284 #define I2C_STATE_SLAVE_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_SLAVE)) /*!< Slave Busy RX, combinaison of State LSB and Mode enum */
285 #define I2C_STATE_MEM_BUSY_TX ((uint32_t)((HAL_I2C_STATE_BUSY_TX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy TX, combinaison of State LSB and Mode enum */
286 #define I2C_STATE_MEM_BUSY_RX ((uint32_t)((HAL_I2C_STATE_BUSY_RX & I2C_STATE_MSK) | HAL_I2C_MODE_MEM)) /*!< Memory Busy RX, combinaison of State LSB and Mode enum */
287
288
289 /* Private define to centralize the enable/disable of Interrupts */
290 #define I2C_XFER_TX_IT (0x00000001U)
291 #define I2C_XFER_RX_IT (0x00000002U)
292 #define I2C_XFER_LISTEN_IT (0x00000004U)
293
294 #define I2C_XFER_ERROR_IT (0x00000011U)
295 #define I2C_XFER_CPLT_IT (0x00000012U)
296 #define I2C_XFER_RELOAD_IT (0x00000012U)
297
298 /* Private define Sequential Transfer Options default/reset value */
299 #define I2C_NO_OPTION_FRAME (0xFFFF0000U)
300 /**
301 * @}
302 */
303
304 /* Private macro -------------------------------------------------------------*/
305 #define I2C_GET_DMA_REMAIN_DATA(__HANDLE__) ((((__HANDLE__)->State) == HAL_I2C_STATE_BUSY_TX) ? \
306 ((uint32_t)((__HANDLE__)->hdmatx->Instance->NDTR)) : \
307 ((uint32_t)((__HANDLE__)->hdmarx->Instance->NDTR)))
308
309 /* Private variables ---------------------------------------------------------*/
310 /* Private function prototypes -----------------------------------------------*/
311
312 /** @defgroup I2C_Private_Functions I2C Private Functions
313 * @{
314 */
315 /* Private functions to handle DMA transfer */
316 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma);
317 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma);
318 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma);
319 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma);
320 static void I2C_DMAError(DMA_HandleTypeDef *hdma);
321 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma);
322
323 /* Private functions to handle IT transfer */
324 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
325 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c);
326 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c);
327 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
328 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
329 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags);
330 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode);
331
332 /* Private functions to handle IT transfer */
333 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
334 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart);
335
336 /* Private functions for I2C transfer IRQ handler */
337 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
338 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
339 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
340 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources);
341
342 /* Private functions to handle flags during polling transfer */
343 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart);
344 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
345 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
346 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
347 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart);
348
349 /* Private functions to centralize the enable/disable of Interrupts */
350 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
351 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest);
352
353 /* Private functions to flush TXDR register */
354 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c);
355
356 /* Private functions to handle start, restart or stop a transfer */
357 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request);
358 /**
359 * @}
360 */
361
362 /* Exported functions --------------------------------------------------------*/
363
364 /** @defgroup I2C_Exported_Functions I2C Exported Functions
365 * @{
366 */
367
368 /** @defgroup I2C_Exported_Functions_Group1 Initialization and de-initialization functions
369 * @brief Initialization and Configuration functions
370 *
371 @verbatim
372 ===============================================================================
373 ##### Initialization and de-initialization functions #####
374 ===============================================================================
375 [..] This subsection provides a set of functions allowing to initialize and
376 deinitialize the I2Cx peripheral:
377
378 (+) User must Implement HAL_I2C_MspInit() function in which he configures
379 all related peripherals resources (CLOCK, GPIO, DMA, IT and NVIC ).
380
381 (+) Call the function HAL_I2C_Init() to configure the selected device with
382 the selected configuration:
383 (++) Clock Timing
384 (++) Own Address 1
385 (++) Addressing mode (Master, Slave)
386 (++) Dual Addressing mode
387 (++) Own Address 2
388 (++) Own Address 2 Mask
389 (++) General call mode
390 (++) Nostretch mode
391
392 (+) Call the function HAL_I2C_DeInit() to restore the default configuration
393 of the selected I2Cx peripheral.
394
395 @endverbatim
396 * @{
397 */
398
399 /**
400 * @brief Initializes the I2C according to the specified parameters
401 * in the I2C_InitTypeDef and initialize the associated handle.
402 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
403 * the configuration information for the specified I2C.
404 * @retval HAL status
405 */
406 HAL_StatusTypeDef HAL_I2C_Init(I2C_HandleTypeDef *hi2c)
407 {
408 /* Check the I2C handle allocation */
409 if(hi2c == NULL)
410 {
411 return HAL_ERROR;
412 }
413
414 /* Check the parameters */
415 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
416 assert_param(IS_I2C_OWN_ADDRESS1(hi2c->Init.OwnAddress1));
417 assert_param(IS_I2C_ADDRESSING_MODE(hi2c->Init.AddressingMode));
418 assert_param(IS_I2C_DUAL_ADDRESS(hi2c->Init.DualAddressMode));
419 assert_param(IS_I2C_OWN_ADDRESS2(hi2c->Init.OwnAddress2));
420 assert_param(IS_I2C_OWN_ADDRESS2_MASK(hi2c->Init.OwnAddress2Masks));
421 assert_param(IS_I2C_GENERAL_CALL(hi2c->Init.GeneralCallMode));
422 assert_param(IS_I2C_NO_STRETCH(hi2c->Init.NoStretchMode));
423
424 if(hi2c->State == HAL_I2C_STATE_RESET)
425 {
426 /* Allocate lock resource and initialize it */
427 hi2c->Lock = HAL_UNLOCKED;
428
429 /* Init the low level hardware : GPIO, CLOCK, CORTEX...etc */
430 HAL_I2C_MspInit(hi2c);
431 }
432
433 hi2c->State = HAL_I2C_STATE_BUSY;
434
435 /* Disable the selected I2C peripheral */
436 __HAL_I2C_DISABLE(hi2c);
437
438 /*---------------------------- I2Cx TIMINGR Configuration ------------------*/
439 /* Configure I2Cx: Frequency range */
440 hi2c->Instance->TIMINGR = hi2c->Init.Timing & TIMING_CLEAR_MASK;
441
442 /*---------------------------- I2Cx OAR1 Configuration ---------------------*/
443 /* Disable Own Address1 before set the Own Address1 configuration */
444 hi2c->Instance->OAR1 &= ~I2C_OAR1_OA1EN;
445
446 /* Configure I2Cx: Own Address1 and ack own address1 mode */
447 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_7BIT)
448 {
449 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | hi2c->Init.OwnAddress1);
450 }
451 else /* I2C_ADDRESSINGMODE_10BIT */
452 {
453 hi2c->Instance->OAR1 = (I2C_OAR1_OA1EN | I2C_OAR1_OA1MODE | hi2c->Init.OwnAddress1);
454 }
455
456 /*---------------------------- I2Cx CR2 Configuration ----------------------*/
457 /* Configure I2Cx: Addressing Master mode */
458 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
459 {
460 hi2c->Instance->CR2 = (I2C_CR2_ADD10);
461 }
462 /* Enable the AUTOEND by default, and enable NACK (should be disable only during Slave process */
463 hi2c->Instance->CR2 |= (I2C_CR2_AUTOEND | I2C_CR2_NACK);
464
465 /*---------------------------- I2Cx OAR2 Configuration ---------------------*/
466 /* Disable Own Address2 before set the Own Address2 configuration */
467 hi2c->Instance->OAR2 &= ~I2C_DUALADDRESS_ENABLE;
468
469 /* Configure I2Cx: Dual mode and Own Address2 */
470 hi2c->Instance->OAR2 = (hi2c->Init.DualAddressMode | hi2c->Init.OwnAddress2 | (hi2c->Init.OwnAddress2Masks << 8));
471
472 /*---------------------------- I2Cx CR1 Configuration ----------------------*/
473 /* Configure I2Cx: Generalcall and NoStretch mode */
474 hi2c->Instance->CR1 = (hi2c->Init.GeneralCallMode | hi2c->Init.NoStretchMode);
475
476 /* Enable the selected I2C peripheral */
477 __HAL_I2C_ENABLE(hi2c);
478
479 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
480 hi2c->State = HAL_I2C_STATE_READY;
481 hi2c->PreviousState = I2C_STATE_NONE;
482 hi2c->Mode = HAL_I2C_MODE_NONE;
483
484 return HAL_OK;
485 }
486
487 /**
488 * @brief DeInitialize the I2C peripheral.
489 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
490 * the configuration information for the specified I2C.
491 * @retval HAL status
492 */
493 HAL_StatusTypeDef HAL_I2C_DeInit(I2C_HandleTypeDef *hi2c)
494 {
495 /* Check the I2C handle allocation */
496 if(hi2c == NULL)
497 {
498 return HAL_ERROR;
499 }
500
501 /* Check the parameters */
502 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
503
504 hi2c->State = HAL_I2C_STATE_BUSY;
505
506 /* Disable the I2C Peripheral Clock */
507 __HAL_I2C_DISABLE(hi2c);
508
509 /* DeInit the low level hardware: GPIO, CLOCK, NVIC */
510 HAL_I2C_MspDeInit(hi2c);
511
512 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
513 hi2c->State = HAL_I2C_STATE_RESET;
514 hi2c->PreviousState = I2C_STATE_NONE;
515 hi2c->Mode = HAL_I2C_MODE_NONE;
516
517 /* Release Lock */
518 __HAL_UNLOCK(hi2c);
519
520 return HAL_OK;
521 }
522
523 /**
524 * @brief Initialize the I2C MSP.
525 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
526 * the configuration information for the specified I2C.
527 * @retval None
528 */
529 __weak void HAL_I2C_MspInit(I2C_HandleTypeDef *hi2c)
530 {
531 /* Prevent unused argument(s) compilation warning */
532 UNUSED(hi2c);
533
534 /* NOTE : This function should not be modified, when the callback is needed,
535 the HAL_I2C_MspInit could be implemented in the user file
536 */
537 }
538
539 /**
540 * @brief DeInitialize the I2C MSP.
541 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
542 * the configuration information for the specified I2C.
543 * @retval None
544 */
545 __weak void HAL_I2C_MspDeInit(I2C_HandleTypeDef *hi2c)
546 {
547 /* Prevent unused argument(s) compilation warning */
548 UNUSED(hi2c);
549
550 /* NOTE : This function should not be modified, when the callback is needed,
551 the HAL_I2C_MspDeInit could be implemented in the user file
552 */
553 }
554
555 /**
556 * @}
557 */
558
559 /** @defgroup I2C_Exported_Functions_Group2 Input and Output operation functions
560 * @brief Data transfers functions
561 *
562 @verbatim
563 ===============================================================================
564 ##### IO operation functions #####
565 ===============================================================================
566 [..]
567 This subsection provides a set of functions allowing to manage the I2C data
568 transfers.
569
570 (#) There are two modes of transfer:
571 (++) Blocking mode : The communication is performed in the polling mode.
572 The status of all data processing is returned by the same function
573 after finishing transfer.
574 (++) No-Blocking mode : The communication is performed using Interrupts
575 or DMA. These functions return the status of the transfer startup.
576 The end of the data processing will be indicated through the
577 dedicated I2C IRQ when using Interrupt mode or the DMA IRQ when
578 using DMA mode.
579
580 (#) Blocking mode functions are :
581 (++) HAL_I2C_Master_Transmit()
582 (++) HAL_I2C_Master_Receive()
583 (++) HAL_I2C_Slave_Transmit()
584 (++) HAL_I2C_Slave_Receive()
585 (++) HAL_I2C_Mem_Write()
586 (++) HAL_I2C_Mem_Read()
587 (++) HAL_I2C_IsDeviceReady()
588
589 (#) No-Blocking mode functions with Interrupt are :
590 (++) HAL_I2C_Master_Transmit_IT()
591 (++) HAL_I2C_Master_Receive_IT()
592 (++) HAL_I2C_Slave_Transmit_IT()
593 (++) HAL_I2C_Slave_Receive_IT()
594 (++) HAL_I2C_Mem_Write_IT()
595 (++) HAL_I2C_Mem_Read_IT()
596
597 (#) No-Blocking mode functions with DMA are :
598 (++) HAL_I2C_Master_Transmit_DMA()
599 (++) HAL_I2C_Master_Receive_DMA()
600 (++) HAL_I2C_Slave_Transmit_DMA()
601 (++) HAL_I2C_Slave_Receive_DMA()
602 (++) HAL_I2C_Mem_Write_DMA()
603 (++) HAL_I2C_Mem_Read_DMA()
604
605 (#) A set of Transfer Complete Callbacks are provided in non Blocking mode:
606 (++) HAL_I2C_MemTxCpltCallback()
607 (++) HAL_I2C_MemRxCpltCallback()
608 (++) HAL_I2C_MasterTxCpltCallback()
609 (++) HAL_I2C_MasterRxCpltCallback()
610 (++) HAL_I2C_SlaveTxCpltCallback()
611 (++) HAL_I2C_SlaveRxCpltCallback()
612 (++) HAL_I2C_ErrorCallback()
613
614 @endverbatim
615 * @{
616 */
617
618 /**
619 * @brief Transmits in master mode an amount of data in blocking mode.
620 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
621 * the configuration information for the specified I2C.
622 * @param DevAddress Target device address: The device 7 bits address value
623 * in datasheet must be shift at right before call interface
624 * @param pData Pointer to data buffer
625 * @param Size Amount of data to be sent
626 * @param Timeout Timeout duration
627 * @retval HAL status
628 */
629 HAL_StatusTypeDef HAL_I2C_Master_Transmit(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
630 {
631 uint32_t tickstart = 0U;
632
633 if(hi2c->State == HAL_I2C_STATE_READY)
634 {
635 /* Process Locked */
636 __HAL_LOCK(hi2c);
637
638 /* Init tickstart for timeout management*/
639 tickstart = HAL_GetTick();
640
641 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
642 {
643 return HAL_TIMEOUT;
644 }
645
646 hi2c->State = HAL_I2C_STATE_BUSY_TX;
647 hi2c->Mode = HAL_I2C_MODE_MASTER;
648 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
649
650 /* Prepare transfer parameters */
651 hi2c->pBuffPtr = pData;
652 hi2c->XferCount = Size;
653 hi2c->XferISR = NULL;
654
655 /* Send Slave Address */
656 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
657 if(hi2c->XferCount > MAX_NBYTE_SIZE)
658 {
659 hi2c->XferSize = MAX_NBYTE_SIZE;
660 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
661 }
662 else
663 {
664 hi2c->XferSize = hi2c->XferCount;
665 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
666 }
667
668 while(hi2c->XferCount > 0U)
669 {
670 /* Wait until TXIS flag is set */
671 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
672 {
673 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
674 {
675 return HAL_ERROR;
676 }
677 else
678 {
679 return HAL_TIMEOUT;
680 }
681 }
682 /* Write data to TXDR */
683 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
684 hi2c->XferCount--;
685 hi2c->XferSize--;
686
687 if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
688 {
689 /* Wait until TCR flag is set */
690 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
691 {
692 return HAL_TIMEOUT;
693 }
694
695 if(hi2c->XferCount > MAX_NBYTE_SIZE)
696 {
697 hi2c->XferSize = MAX_NBYTE_SIZE;
698 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
699 }
700 else
701 {
702 hi2c->XferSize = hi2c->XferCount;
703 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
704 }
705 }
706 }
707
708 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
709 /* Wait until STOPF flag is set */
710 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
711 {
712 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
713 {
714 return HAL_ERROR;
715 }
716 else
717 {
718 return HAL_TIMEOUT;
719 }
720 }
721
722 /* Clear STOP Flag */
723 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
724
725 /* Clear Configuration Register 2 */
726 I2C_RESET_CR2(hi2c);
727
728 hi2c->State = HAL_I2C_STATE_READY;
729 hi2c->Mode = HAL_I2C_MODE_NONE;
730
731 /* Process Unlocked */
732 __HAL_UNLOCK(hi2c);
733
734 return HAL_OK;
735 }
736 else
737 {
738 return HAL_BUSY;
739 }
740 }
741
742 /**
743 * @brief Receives in master mode an amount of data in blocking mode.
744 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
745 * the configuration information for the specified I2C.
746 * @param DevAddress Target device address: The device 7 bits address value
747 * in datasheet must be shift at right before call interface
748 * @param pData Pointer to data buffer
749 * @param Size Amount of data to be sent
750 * @param Timeout Timeout duration
751 * @retval HAL status
752 */
753 HAL_StatusTypeDef HAL_I2C_Master_Receive(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t Timeout)
754 {
755 uint32_t tickstart = 0U;
756
757 if(hi2c->State == HAL_I2C_STATE_READY)
758 {
759 /* Process Locked */
760 __HAL_LOCK(hi2c);
761
762 /* Init tickstart for timeout management*/
763 tickstart = HAL_GetTick();
764
765 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
766 {
767 return HAL_TIMEOUT;
768 }
769
770 hi2c->State = HAL_I2C_STATE_BUSY_RX;
771 hi2c->Mode = HAL_I2C_MODE_MASTER;
772 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
773
774 /* Prepare transfer parameters */
775 hi2c->pBuffPtr = pData;
776 hi2c->XferCount = Size;
777 hi2c->XferISR = NULL;
778
779 /* Send Slave Address */
780 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
781 if(hi2c->XferCount > MAX_NBYTE_SIZE)
782 {
783 hi2c->XferSize = MAX_NBYTE_SIZE;
784 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
785 }
786 else
787 {
788 hi2c->XferSize = hi2c->XferCount;
789 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
790 }
791
792 while(hi2c->XferCount > 0U)
793 {
794 /* Wait until RXNE flag is set */
795 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
796 {
797 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
798 {
799 return HAL_ERROR;
800 }
801 else
802 {
803 return HAL_TIMEOUT;
804 }
805 }
806
807 /* Read data from RXDR */
808 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
809 hi2c->XferSize--;
810 hi2c->XferCount--;
811
812 if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
813 {
814 /* Wait until TCR flag is set */
815 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
816 {
817 return HAL_TIMEOUT;
818 }
819
820 if(hi2c->XferCount > MAX_NBYTE_SIZE)
821 {
822 hi2c->XferSize = MAX_NBYTE_SIZE;
823 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
824 }
825 else
826 {
827 hi2c->XferSize = hi2c->XferCount;
828 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
829 }
830 }
831 }
832
833 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
834 /* Wait until STOPF flag is set */
835 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
836 {
837 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
838 {
839 return HAL_ERROR;
840 }
841 else
842 {
843 return HAL_TIMEOUT;
844 }
845 }
846
847 /* Clear STOP Flag */
848 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
849
850 /* Clear Configuration Register 2 */
851 I2C_RESET_CR2(hi2c);
852
853 hi2c->State = HAL_I2C_STATE_READY;
854 hi2c->Mode = HAL_I2C_MODE_NONE;
855
856 /* Process Unlocked */
857 __HAL_UNLOCK(hi2c);
858
859 return HAL_OK;
860 }
861 else
862 {
863 return HAL_BUSY;
864 }
865 }
866
867 /**
868 * @brief Transmits in slave mode an amount of data in blocking mode.
869 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
870 * the configuration information for the specified I2C.
871 * @param pData Pointer to data buffer
872 * @param Size Amount of data to be sent
873 * @param Timeout Timeout duration
874 * @retval HAL status
875 */
876 HAL_StatusTypeDef HAL_I2C_Slave_Transmit(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
877 {
878 uint32_t tickstart = 0U;
879
880 if(hi2c->State == HAL_I2C_STATE_READY)
881 {
882 if((pData == NULL) || (Size == 0U))
883 {
884 return HAL_ERROR;
885 }
886 /* Process Locked */
887 __HAL_LOCK(hi2c);
888
889 /* Init tickstart for timeout management*/
890 tickstart = HAL_GetTick();
891
892 hi2c->State = HAL_I2C_STATE_BUSY_TX;
893 hi2c->Mode = HAL_I2C_MODE_SLAVE;
894 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
895
896 /* Prepare transfer parameters */
897 hi2c->pBuffPtr = pData;
898 hi2c->XferCount = Size;
899 hi2c->XferISR = NULL;
900
901 /* Enable Address Acknowledge */
902 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
903
904 /* Wait until ADDR flag is set */
905 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
906 {
907 /* Disable Address Acknowledge */
908 hi2c->Instance->CR2 |= I2C_CR2_NACK;
909 return HAL_TIMEOUT;
910 }
911
912 /* Clear ADDR flag */
913 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
914
915 /* If 10bit addressing mode is selected */
916 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
917 {
918 /* Wait until ADDR flag is set */
919 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
920 {
921 /* Disable Address Acknowledge */
922 hi2c->Instance->CR2 |= I2C_CR2_NACK;
923 return HAL_TIMEOUT;
924 }
925
926 /* Clear ADDR flag */
927 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
928 }
929
930 /* Wait until DIR flag is set Transmitter mode */
931 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, RESET, Timeout, tickstart) != HAL_OK)
932 {
933 /* Disable Address Acknowledge */
934 hi2c->Instance->CR2 |= I2C_CR2_NACK;
935 return HAL_TIMEOUT;
936 }
937
938 while(hi2c->XferCount > 0U)
939 {
940 /* Wait until TXIS flag is set */
941 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
942 {
943 /* Disable Address Acknowledge */
944 hi2c->Instance->CR2 |= I2C_CR2_NACK;
945
946 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
947 {
948 return HAL_ERROR;
949 }
950 else
951 {
952 return HAL_TIMEOUT;
953 }
954 }
955
956 /* Write data to TXDR */
957 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
958 hi2c->XferCount--;
959 }
960
961 /* Wait until STOP flag is set */
962 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
963 {
964 /* Disable Address Acknowledge */
965 hi2c->Instance->CR2 |= I2C_CR2_NACK;
966
967 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
968 {
969 /* Normal use case for Transmitter mode */
970 /* A NACK is generated to confirm the end of transfer */
971 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
972 }
973 else
974 {
975 return HAL_TIMEOUT;
976 }
977 }
978
979 /* Clear STOP flag */
980 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
981
982 /* Wait until BUSY flag is reset */
983 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
984 {
985 /* Disable Address Acknowledge */
986 hi2c->Instance->CR2 |= I2C_CR2_NACK;
987 return HAL_TIMEOUT;
988 }
989
990 /* Disable Address Acknowledge */
991 hi2c->Instance->CR2 |= I2C_CR2_NACK;
992
993 hi2c->State = HAL_I2C_STATE_READY;
994 hi2c->Mode = HAL_I2C_MODE_NONE;
995
996 /* Process Unlocked */
997 __HAL_UNLOCK(hi2c);
998
999 return HAL_OK;
1000 }
1001 else
1002 {
1003 return HAL_BUSY;
1004 }
1005 }
1006
1007 /**
1008 * @brief Receive in slave mode an amount of data in blocking mode
1009 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1010 * the configuration information for the specified I2C.
1011 * @param pData Pointer to data buffer
1012 * @param Size Amount of data to be sent
1013 * @param Timeout Timeout duration
1014 * @retval HAL status
1015 */
1016 HAL_StatusTypeDef HAL_I2C_Slave_Receive(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1017 {
1018 uint32_t tickstart = 0U;
1019
1020 if(hi2c->State == HAL_I2C_STATE_READY)
1021 {
1022 if((pData == NULL) || (Size == 0U))
1023 {
1024 return HAL_ERROR;
1025 }
1026 /* Process Locked */
1027 __HAL_LOCK(hi2c);
1028
1029 /* Init tickstart for timeout management*/
1030 tickstart = HAL_GetTick();
1031
1032 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1033 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1034 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1035
1036 /* Prepare transfer parameters */
1037 hi2c->pBuffPtr = pData;
1038 hi2c->XferCount = Size;
1039 hi2c->XferISR = NULL;
1040
1041 /* Enable Address Acknowledge */
1042 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1043
1044 /* Wait until ADDR flag is set */
1045 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_ADDR, RESET, Timeout, tickstart) != HAL_OK)
1046 {
1047 /* Disable Address Acknowledge */
1048 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1049 return HAL_TIMEOUT;
1050 }
1051
1052 /* Clear ADDR flag */
1053 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
1054
1055 /* Wait until DIR flag is reset Receiver mode */
1056 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_DIR, SET, Timeout, tickstart) != HAL_OK)
1057 {
1058 /* Disable Address Acknowledge */
1059 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1060 return HAL_TIMEOUT;
1061 }
1062
1063 while(hi2c->XferCount > 0U)
1064 {
1065 /* Wait until RXNE flag is set */
1066 if(I2C_WaitOnRXNEFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1067 {
1068 /* Disable Address Acknowledge */
1069 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1070
1071 /* Store Last receive data if any */
1072 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == SET)
1073 {
1074 /* Read data from RXDR */
1075 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1076 hi2c->XferCount--;
1077 }
1078
1079 if(hi2c->ErrorCode == HAL_I2C_ERROR_TIMEOUT)
1080 {
1081 return HAL_TIMEOUT;
1082 }
1083 else
1084 {
1085 return HAL_ERROR;
1086 }
1087 }
1088
1089 /* Read data from RXDR */
1090 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1091 hi2c->XferCount--;
1092 }
1093
1094 /* Wait until STOP flag is set */
1095 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1096 {
1097 /* Disable Address Acknowledge */
1098 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1099
1100 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1101 {
1102 return HAL_ERROR;
1103 }
1104 else
1105 {
1106 return HAL_TIMEOUT;
1107 }
1108 }
1109
1110 /* Clear STOP flag */
1111 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_STOPF);
1112
1113 /* Wait until BUSY flag is reset */
1114 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, Timeout, tickstart) != HAL_OK)
1115 {
1116 /* Disable Address Acknowledge */
1117 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1118 return HAL_TIMEOUT;
1119 }
1120
1121 /* Disable Address Acknowledge */
1122 hi2c->Instance->CR2 |= I2C_CR2_NACK;
1123
1124 hi2c->State = HAL_I2C_STATE_READY;
1125 hi2c->Mode = HAL_I2C_MODE_NONE;
1126
1127 /* Process Unlocked */
1128 __HAL_UNLOCK(hi2c);
1129
1130 return HAL_OK;
1131 }
1132 else
1133 {
1134 return HAL_BUSY;
1135 }
1136 }
1137
1138 /**
1139 * @brief Transmit in master mode an amount of data in non-blocking mode with Interrupt
1140 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1141 * the configuration information for the specified I2C.
1142 * @param DevAddress Target device address: The device 7 bits address value
1143 * in datasheet must be shift at right before call interface
1144 * @param pData Pointer to data buffer
1145 * @param Size Amount of data to be sent
1146 * @retval HAL status
1147 */
1148 HAL_StatusTypeDef HAL_I2C_Master_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1149 {
1150 uint32_t xfermode = 0U;
1151
1152 if(hi2c->State == HAL_I2C_STATE_READY)
1153 {
1154 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1155 {
1156 return HAL_BUSY;
1157 }
1158
1159 /* Process Locked */
1160 __HAL_LOCK(hi2c);
1161
1162 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1163 hi2c->Mode = HAL_I2C_MODE_MASTER;
1164 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1165
1166 /* Prepare transfer parameters */
1167 hi2c->pBuffPtr = pData;
1168 hi2c->XferCount = Size;
1169 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1170 hi2c->XferISR = I2C_Master_ISR_IT;
1171
1172 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1173 {
1174 hi2c->XferSize = MAX_NBYTE_SIZE;
1175 xfermode = I2C_RELOAD_MODE;
1176 }
1177 else
1178 {
1179 hi2c->XferSize = hi2c->XferCount;
1180 xfermode = I2C_AUTOEND_MODE;
1181 }
1182
1183 /* Send Slave Address */
1184 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1185 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1186
1187 /* Process Unlocked */
1188 __HAL_UNLOCK(hi2c);
1189
1190 /* Note : The I2C interrupts must be enabled after unlocking current process
1191 to avoid the risk of I2C interrupt handle execution before current
1192 process unlock */
1193
1194 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1195 /* possible to enable all of these */
1196 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1197 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1198
1199 return HAL_OK;
1200 }
1201 else
1202 {
1203 return HAL_BUSY;
1204 }
1205 }
1206
1207 /**
1208 * @brief Receive in master mode an amount of data in non-blocking mode with Interrupt
1209 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1210 * the configuration information for the specified I2C.
1211 * @param DevAddress Target device address: The device 7 bits address value
1212 * in datasheet must be shift at right before call interface
1213 * @param pData Pointer to data buffer
1214 * @param Size Amount of data to be sent
1215 * @retval HAL status
1216 */
1217 HAL_StatusTypeDef HAL_I2C_Master_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1218 {
1219 uint32_t xfermode = 0U;
1220
1221 if(hi2c->State == HAL_I2C_STATE_READY)
1222 {
1223 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1224 {
1225 return HAL_BUSY;
1226 }
1227
1228 /* Process Locked */
1229 __HAL_LOCK(hi2c);
1230
1231 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1232 hi2c->Mode = HAL_I2C_MODE_MASTER;
1233 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1234
1235 /* Prepare transfer parameters */
1236 hi2c->pBuffPtr = pData;
1237 hi2c->XferCount = Size;
1238 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1239 hi2c->XferISR = I2C_Master_ISR_IT;
1240
1241 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1242 {
1243 hi2c->XferSize = MAX_NBYTE_SIZE;
1244 xfermode = I2C_RELOAD_MODE;
1245 }
1246 else
1247 {
1248 hi2c->XferSize = hi2c->XferCount;
1249 xfermode = I2C_AUTOEND_MODE;
1250 }
1251
1252 /* Send Slave Address */
1253 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1254 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1255
1256 /* Process Unlocked */
1257 __HAL_UNLOCK(hi2c);
1258
1259 /* Note : The I2C interrupts must be enabled after unlocking current process
1260 to avoid the risk of I2C interrupt handle execution before current
1261 process unlock */
1262
1263 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1264 /* possible to enable all of these */
1265 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1266 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
1267
1268 return HAL_OK;
1269 }
1270 else
1271 {
1272 return HAL_BUSY;
1273 }
1274 }
1275
1276 /**
1277 * @brief Transmit in slave mode an amount of data in non-blocking mode with Interrupt
1278 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1279 * the configuration information for the specified I2C.
1280 * @param pData Pointer to data buffer
1281 * @param Size Amount of data to be sent
1282 * @retval HAL status
1283 */
1284 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1285 {
1286 if(hi2c->State == HAL_I2C_STATE_READY)
1287 {
1288 /* Process Locked */
1289 __HAL_LOCK(hi2c);
1290
1291 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1292 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1293 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1294
1295 /* Enable Address Acknowledge */
1296 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1297
1298 /* Prepare transfer parameters */
1299 hi2c->pBuffPtr = pData;
1300 hi2c->XferCount = Size;
1301 hi2c->XferSize = hi2c->XferCount;
1302 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1303 hi2c->XferISR = I2C_Slave_ISR_IT;
1304
1305 /* Process Unlocked */
1306 __HAL_UNLOCK(hi2c);
1307
1308 /* Note : The I2C interrupts must be enabled after unlocking current process
1309 to avoid the risk of I2C interrupt handle execution before current
1310 process unlock */
1311
1312 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1313 /* possible to enable all of these */
1314 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1315 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
1316
1317 return HAL_OK;
1318 }
1319 else
1320 {
1321 return HAL_BUSY;
1322 }
1323 }
1324
1325 /**
1326 * @brief Receive in slave mode an amount of data in non-blocking mode with Interrupt
1327 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1328 * the configuration information for the specified I2C.
1329 * @param pData Pointer to data buffer
1330 * @param Size Amount of data to be sent
1331 * @retval HAL status
1332 */
1333 HAL_StatusTypeDef HAL_I2C_Slave_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1334 {
1335 if(hi2c->State == HAL_I2C_STATE_READY)
1336 {
1337 /* Process Locked */
1338 __HAL_LOCK(hi2c);
1339
1340 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1341 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1342 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1343
1344 /* Enable Address Acknowledge */
1345 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1346
1347 /* Prepare transfer parameters */
1348 hi2c->pBuffPtr = pData;
1349 hi2c->XferCount = Size;
1350 hi2c->XferSize = hi2c->XferCount;
1351 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1352 hi2c->XferISR = I2C_Slave_ISR_IT;
1353
1354 /* Process Unlocked */
1355 __HAL_UNLOCK(hi2c);
1356
1357 /* Note : The I2C interrupts must be enabled after unlocking current process
1358 to avoid the risk of I2C interrupt handle execution before current
1359 process unlock */
1360
1361 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
1362 /* possible to enable all of these */
1363 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1364 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
1365
1366 return HAL_OK;
1367 }
1368 else
1369 {
1370 return HAL_BUSY;
1371 }
1372 }
1373
1374 /**
1375 * @brief Transmit in master mode an amount of data in non-blocking mode with DMA
1376 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1377 * the configuration information for the specified I2C.
1378 * @param DevAddress Target device address: The device 7 bits address value
1379 * in datasheet must be shift at right before call interface
1380 * @param pData Pointer to data buffer
1381 * @param Size Amount of data to be sent
1382 * @retval HAL status
1383 */
1384 HAL_StatusTypeDef HAL_I2C_Master_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1385 {
1386 uint32_t xfermode = 0U;
1387
1388 if(hi2c->State == HAL_I2C_STATE_READY)
1389 {
1390 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1391 {
1392 return HAL_BUSY;
1393 }
1394
1395 /* Process Locked */
1396 __HAL_LOCK(hi2c);
1397
1398 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1399 hi2c->Mode = HAL_I2C_MODE_MASTER;
1400 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1401
1402 /* Prepare transfer parameters */
1403 hi2c->pBuffPtr = pData;
1404 hi2c->XferCount = Size;
1405 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1406 hi2c->XferISR = I2C_Master_ISR_DMA;
1407
1408 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1409 {
1410 hi2c->XferSize = MAX_NBYTE_SIZE;
1411 xfermode = I2C_RELOAD_MODE;
1412 }
1413 else
1414 {
1415 hi2c->XferSize = hi2c->XferCount;
1416 xfermode = I2C_AUTOEND_MODE;
1417 }
1418
1419 if(hi2c->XferSize > 0U)
1420 {
1421 /* Set the I2C DMA transfer complete callback */
1422 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
1423
1424 /* Set the DMA error callback */
1425 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1426
1427 /* Set the unused DMA callbacks to NULL */
1428 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1429 hi2c->hdmatx->XferAbortCallback = NULL;
1430
1431 /* Enable the DMA channel */
1432 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
1433
1434 /* Send Slave Address */
1435 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1436 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_WRITE);
1437
1438 /* Update XferCount value */
1439 hi2c->XferCount -= hi2c->XferSize;
1440
1441 /* Process Unlocked */
1442 __HAL_UNLOCK(hi2c);
1443
1444 /* Note : The I2C interrupts must be enabled after unlocking current process
1445 to avoid the risk of I2C interrupt handle execution before current
1446 process unlock */
1447 /* Enable ERR and NACK interrupts */
1448 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1449
1450 /* Enable DMA Request */
1451 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1452 }
1453 else
1454 {
1455 /* Update Transfer ISR function pointer */
1456 hi2c->XferISR = I2C_Master_ISR_IT;
1457
1458 /* Send Slave Address */
1459 /* Set NBYTES to write and generate START condition */
1460 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_WRITE);
1461
1462 /* Process Unlocked */
1463 __HAL_UNLOCK(hi2c);
1464
1465 /* Note : The I2C interrupts must be enabled after unlocking current process
1466 to avoid the risk of I2C interrupt handle execution before current
1467 process unlock */
1468 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1469 /* possible to enable all of these */
1470 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1471 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1472 }
1473
1474 return HAL_OK;
1475 }
1476 else
1477 {
1478 return HAL_BUSY;
1479 }
1480 }
1481
1482 /**
1483 * @brief Receive in master mode an amount of data in non-blocking mode with DMA
1484 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1485 * the configuration information for the specified I2C.
1486 * @param DevAddress Target device address: The device 7 bits address value
1487 * in datasheet must be shift at right before call interface
1488 * @param pData Pointer to data buffer
1489 * @param Size Amount of data to be sent
1490 * @retval HAL status
1491 */
1492 HAL_StatusTypeDef HAL_I2C_Master_Receive_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size)
1493 {
1494 uint32_t xfermode = 0U;
1495
1496 if(hi2c->State == HAL_I2C_STATE_READY)
1497 {
1498 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
1499 {
1500 return HAL_BUSY;
1501 }
1502
1503 /* Process Locked */
1504 __HAL_LOCK(hi2c);
1505
1506 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1507 hi2c->Mode = HAL_I2C_MODE_MASTER;
1508 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1509
1510 /* Prepare transfer parameters */
1511 hi2c->pBuffPtr = pData;
1512 hi2c->XferCount = Size;
1513 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1514 hi2c->XferISR = I2C_Master_ISR_DMA;
1515
1516 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1517 {
1518 hi2c->XferSize = MAX_NBYTE_SIZE;
1519 xfermode = I2C_RELOAD_MODE;
1520 }
1521 else
1522 {
1523 hi2c->XferSize = hi2c->XferCount;
1524 xfermode = I2C_AUTOEND_MODE;
1525 }
1526
1527 if(hi2c->XferSize > 0U)
1528 {
1529 /* Set the I2C DMA transfer complete callback */
1530 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
1531
1532 /* Set the DMA error callback */
1533 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
1534
1535 /* Set the unused DMA callbacks to NULL */
1536 hi2c->hdmarx->XferHalfCpltCallback = NULL;
1537 hi2c->hdmarx->XferAbortCallback = NULL;
1538
1539 /* Enable the DMA channel */
1540 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
1541
1542 /* Send Slave Address */
1543 /* Set NBYTES to read and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1544 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
1545
1546 /* Update XferCount value */
1547 hi2c->XferCount -= hi2c->XferSize;
1548
1549 /* Process Unlocked */
1550 __HAL_UNLOCK(hi2c);
1551
1552 /* Note : The I2C interrupts must be enabled after unlocking current process
1553 to avoid the risk of I2C interrupt handle execution before current
1554 process unlock */
1555 /* Enable ERR and NACK interrupts */
1556 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
1557
1558 /* Enable DMA Request */
1559 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
1560 }
1561 else
1562 {
1563 /* Update Transfer ISR function pointer */
1564 hi2c->XferISR = I2C_Master_ISR_IT;
1565
1566 /* Send Slave Address */
1567 /* Set NBYTES to read and generate START condition */
1568 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1569
1570 /* Process Unlocked */
1571 __HAL_UNLOCK(hi2c);
1572
1573 /* Note : The I2C interrupts must be enabled after unlocking current process
1574 to avoid the risk of I2C interrupt handle execution before current
1575 process unlock */
1576 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
1577 /* possible to enable all of these */
1578 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
1579 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
1580 }
1581 return HAL_OK;
1582 }
1583 else
1584 {
1585 return HAL_BUSY;
1586 }
1587 }
1588
1589 /**
1590 * @brief Transmit in slave mode an amount of data in non-blocking mode with DMA
1591 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1592 * the configuration information for the specified I2C.
1593 * @param pData Pointer to data buffer
1594 * @param Size Amount of data to be sent
1595 * @retval HAL status
1596 */
1597 HAL_StatusTypeDef HAL_I2C_Slave_Transmit_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1598 {
1599 if(hi2c->State == HAL_I2C_STATE_READY)
1600 {
1601 if((pData == NULL) || (Size == 0U))
1602 {
1603 return HAL_ERROR;
1604 }
1605 /* Process Locked */
1606 __HAL_LOCK(hi2c);
1607
1608 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1609 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1610 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1611
1612 /* Prepare transfer parameters */
1613 hi2c->pBuffPtr = pData;
1614 hi2c->XferCount = Size;
1615 hi2c->XferSize = hi2c->XferCount;
1616 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1617 hi2c->XferISR = I2C_Slave_ISR_DMA;
1618
1619 /* Set the I2C DMA transfer complete callback */
1620 hi2c->hdmatx->XferCpltCallback = I2C_DMASlaveTransmitCplt;
1621
1622 /* Set the DMA error callback */
1623 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
1624
1625 /* Set the unused DMA callbacks to NULL */
1626 hi2c->hdmatx->XferHalfCpltCallback = NULL;
1627 hi2c->hdmatx->XferAbortCallback = NULL;
1628
1629 /* Enable the DMA channel */
1630 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
1631
1632 /* Enable Address Acknowledge */
1633 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1634
1635 /* Process Unlocked */
1636 __HAL_UNLOCK(hi2c);
1637
1638 /* Note : The I2C interrupts must be enabled after unlocking current process
1639 to avoid the risk of I2C interrupt handle execution before current
1640 process unlock */
1641 /* Enable ERR, STOP, NACK, ADDR interrupts */
1642 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
1643
1644 /* Enable DMA Request */
1645 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
1646
1647 return HAL_OK;
1648 }
1649 else
1650 {
1651 return HAL_BUSY;
1652 }
1653 }
1654
1655 /**
1656 * @brief Receive in slave mode an amount of data in non-blocking mode with DMA
1657 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1658 * the configuration information for the specified I2C.
1659 * @param pData Pointer to data buffer
1660 * @param Size Amount of data to be sent
1661 * @retval HAL status
1662 */
1663 HAL_StatusTypeDef HAL_I2C_Slave_Receive_DMA(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size)
1664 {
1665 if(hi2c->State == HAL_I2C_STATE_READY)
1666 {
1667 if((pData == NULL) || (Size == 0U))
1668 {
1669 return HAL_ERROR;
1670 }
1671 /* Process Locked */
1672 __HAL_LOCK(hi2c);
1673
1674 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1675 hi2c->Mode = HAL_I2C_MODE_SLAVE;
1676 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1677
1678 /* Prepare transfer parameters */
1679 hi2c->pBuffPtr = pData;
1680 hi2c->XferCount = Size;
1681 hi2c->XferSize = hi2c->XferCount;
1682 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
1683 hi2c->XferISR = I2C_Slave_ISR_DMA;
1684
1685 /* Set the I2C DMA transfer complete callback */
1686 hi2c->hdmarx->XferCpltCallback = I2C_DMASlaveReceiveCplt;
1687
1688 /* Set the DMA error callback */
1689 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
1690
1691 /* Set the unused DMA callbacks to NULL */
1692 hi2c->hdmarx->XferHalfCpltCallback = NULL;
1693 hi2c->hdmarx->XferAbortCallback = NULL;
1694
1695 /* Enable the DMA channel */
1696 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
1697
1698 /* Enable Address Acknowledge */
1699 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
1700
1701 /* Process Unlocked */
1702 __HAL_UNLOCK(hi2c);
1703
1704 /* Note : The I2C interrupts must be enabled after unlocking current process
1705 to avoid the risk of I2C interrupt handle execution before current
1706 process unlock */
1707 /* Enable ERR, STOP, NACK, ADDR interrupts */
1708 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
1709
1710 /* Enable DMA Request */
1711 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
1712
1713 return HAL_OK;
1714 }
1715 else
1716 {
1717 return HAL_BUSY;
1718 }
1719 }
1720 /**
1721 * @brief Write an amount of data in blocking mode to a specific memory address
1722 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1723 * the configuration information for the specified I2C.
1724 * @param DevAddress Target device address: The device 7 bits address value
1725 * in datasheet must be shift at right before call interface
1726 * @param MemAddress Internal memory address
1727 * @param MemAddSize Size of internal memory address
1728 * @param pData Pointer to data buffer
1729 * @param Size Amount of data to be sent
1730 * @param Timeout Timeout duration
1731 * @retval HAL status
1732 */
1733 HAL_StatusTypeDef HAL_I2C_Mem_Write(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1734 {
1735 uint32_t tickstart = 0U;
1736
1737 /* Check the parameters */
1738 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
1739
1740 if(hi2c->State == HAL_I2C_STATE_READY)
1741 {
1742 if((pData == NULL) || (Size == 0U))
1743 {
1744 return HAL_ERROR;
1745 }
1746
1747 /* Process Locked */
1748 __HAL_LOCK(hi2c);
1749
1750 /* Init tickstart for timeout management*/
1751 tickstart = HAL_GetTick();
1752
1753 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1754 {
1755 return HAL_TIMEOUT;
1756 }
1757
1758 hi2c->State = HAL_I2C_STATE_BUSY_TX;
1759 hi2c->Mode = HAL_I2C_MODE_MEM;
1760 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1761
1762 /* Prepare transfer parameters */
1763 hi2c->pBuffPtr = pData;
1764 hi2c->XferCount = Size;
1765 hi2c->XferISR = NULL;
1766
1767 /* Send Slave Address and Memory Address */
1768 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
1769 {
1770 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1771 {
1772 /* Process Unlocked */
1773 __HAL_UNLOCK(hi2c);
1774 return HAL_ERROR;
1775 }
1776 else
1777 {
1778 /* Process Unlocked */
1779 __HAL_UNLOCK(hi2c);
1780 return HAL_TIMEOUT;
1781 }
1782 }
1783
1784 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE */
1785 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1786 {
1787 hi2c->XferSize = MAX_NBYTE_SIZE;
1788 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1789 }
1790 else
1791 {
1792 hi2c->XferSize = hi2c->XferCount;
1793 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1794 }
1795
1796 do
1797 {
1798 /* Wait until TXIS flag is set */
1799 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1800 {
1801 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1802 {
1803 return HAL_ERROR;
1804 }
1805 else
1806 {
1807 return HAL_TIMEOUT;
1808 }
1809 }
1810
1811 /* Write data to TXDR */
1812 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
1813 hi2c->XferCount--;
1814 hi2c->XferSize--;
1815
1816 if((hi2c->XferSize == 0U) && (hi2c->XferCount!=0U))
1817 {
1818 /* Wait until TCR flag is set */
1819 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1820 {
1821 return HAL_TIMEOUT;
1822 }
1823
1824 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1825 {
1826 hi2c->XferSize = MAX_NBYTE_SIZE;
1827 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1828 }
1829 else
1830 {
1831 hi2c->XferSize = hi2c->XferCount;
1832 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1833 }
1834 }
1835
1836 }while(hi2c->XferCount > 0U);
1837
1838 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1839 /* Wait until STOPF flag is reset */
1840 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1841 {
1842 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1843 {
1844 return HAL_ERROR;
1845 }
1846 else
1847 {
1848 return HAL_TIMEOUT;
1849 }
1850 }
1851
1852 /* Clear STOP Flag */
1853 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1854
1855 /* Clear Configuration Register 2 */
1856 I2C_RESET_CR2(hi2c);
1857
1858 hi2c->State = HAL_I2C_STATE_READY;
1859 hi2c->Mode = HAL_I2C_MODE_NONE;
1860
1861 /* Process Unlocked */
1862 __HAL_UNLOCK(hi2c);
1863
1864 return HAL_OK;
1865 }
1866 else
1867 {
1868 return HAL_BUSY;
1869 }
1870 }
1871
1872 /**
1873 * @brief Read an amount of data in blocking mode from a specific memory address
1874 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
1875 * the configuration information for the specified I2C.
1876 * @param DevAddress Target device address: The device 7 bits address value
1877 * in datasheet must be shift at right before call interface
1878 * @param MemAddress Internal memory address
1879 * @param MemAddSize Size of internal memory address
1880 * @param pData Pointer to data buffer
1881 * @param Size Amount of data to be sent
1882 * @param Timeout Timeout duration
1883 * @retval HAL status
1884 */
1885 HAL_StatusTypeDef HAL_I2C_Mem_Read(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size, uint32_t Timeout)
1886 {
1887 uint32_t tickstart = 0U;
1888
1889 /* Check the parameters */
1890 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
1891
1892 if(hi2c->State == HAL_I2C_STATE_READY)
1893 {
1894 if((pData == NULL) || (Size == 0U))
1895 {
1896 return HAL_ERROR;
1897 }
1898
1899 /* Process Locked */
1900 __HAL_LOCK(hi2c);
1901
1902 /* Init tickstart for timeout management*/
1903 tickstart = HAL_GetTick();
1904
1905 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_BUSY, SET, I2C_TIMEOUT_BUSY, tickstart) != HAL_OK)
1906 {
1907 return HAL_TIMEOUT;
1908 }
1909
1910 hi2c->State = HAL_I2C_STATE_BUSY_RX;
1911 hi2c->Mode = HAL_I2C_MODE_MEM;
1912 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
1913
1914 /* Prepare transfer parameters */
1915 hi2c->pBuffPtr = pData;
1916 hi2c->XferCount = Size;
1917 hi2c->XferISR = NULL;
1918
1919 /* Send Slave Address and Memory Address */
1920 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, Timeout, tickstart) != HAL_OK)
1921 {
1922 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1923 {
1924 /* Process Unlocked */
1925 __HAL_UNLOCK(hi2c);
1926 return HAL_ERROR;
1927 }
1928 else
1929 {
1930 /* Process Unlocked */
1931 __HAL_UNLOCK(hi2c);
1932 return HAL_TIMEOUT;
1933 }
1934 }
1935
1936 /* Send Slave Address */
1937 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
1938 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1939 {
1940 hi2c->XferSize = MAX_NBYTE_SIZE;
1941 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_GENERATE_START_READ);
1942 }
1943 else
1944 {
1945 hi2c->XferSize = hi2c->XferCount;
1946 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_GENERATE_START_READ);
1947 }
1948
1949 do
1950 {
1951 /* Wait until RXNE flag is set */
1952 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_RXNE, RESET, Timeout, tickstart) != HAL_OK)
1953 {
1954 return HAL_TIMEOUT;
1955 }
1956
1957 /* Read data from RXDR */
1958 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
1959 hi2c->XferSize--;
1960 hi2c->XferCount--;
1961
1962 if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
1963 {
1964 /* Wait until TCR flag is set */
1965 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, tickstart) != HAL_OK)
1966 {
1967 return HAL_TIMEOUT;
1968 }
1969
1970 if(hi2c->XferCount > MAX_NBYTE_SIZE)
1971 {
1972 hi2c->XferSize = MAX_NBYTE_SIZE;
1973 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
1974 }
1975 else
1976 {
1977 hi2c->XferSize = hi2c->XferCount;
1978 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
1979 }
1980 }
1981 }while(hi2c->XferCount > 0U);
1982
1983 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
1984 /* Wait until STOPF flag is reset */
1985 if(I2C_WaitOnSTOPFlagUntilTimeout(hi2c, Timeout, tickstart) != HAL_OK)
1986 {
1987 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
1988 {
1989 return HAL_ERROR;
1990 }
1991 else
1992 {
1993 return HAL_TIMEOUT;
1994 }
1995 }
1996
1997 /* Clear STOP Flag */
1998 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
1999
2000 /* Clear Configuration Register 2 */
2001 I2C_RESET_CR2(hi2c);
2002
2003 hi2c->State = HAL_I2C_STATE_READY;
2004 hi2c->Mode = HAL_I2C_MODE_NONE;
2005
2006 /* Process Unlocked */
2007 __HAL_UNLOCK(hi2c);
2008
2009 return HAL_OK;
2010 }
2011 else
2012 {
2013 return HAL_BUSY;
2014 }
2015 }
2016 /**
2017 * @brief Write an amount of data in non-blocking mode with Interrupt to a specific memory address
2018 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2019 * the configuration information for the specified I2C.
2020 * @param DevAddress Target device address: The device 7 bits address value
2021 * in datasheet must be shift at right before call interface
2022 * @param MemAddress Internal memory address
2023 * @param MemAddSize Size of internal memory address
2024 * @param pData Pointer to data buffer
2025 * @param Size Amount of data to be sent
2026 * @retval HAL status
2027 */
2028 HAL_StatusTypeDef HAL_I2C_Mem_Write_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2029 {
2030 uint32_t tickstart = 0U;
2031 uint32_t xfermode = 0U;
2032
2033 /* Check the parameters */
2034 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2035
2036 if(hi2c->State == HAL_I2C_STATE_READY)
2037 {
2038 if((pData == NULL) || (Size == 0U))
2039 {
2040 return HAL_ERROR;
2041 }
2042
2043 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2044 {
2045 return HAL_BUSY;
2046 }
2047
2048 /* Process Locked */
2049 __HAL_LOCK(hi2c);
2050
2051 /* Init tickstart for timeout management*/
2052 tickstart = HAL_GetTick();
2053
2054 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2055 hi2c->Mode = HAL_I2C_MODE_MEM;
2056 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2057
2058 /* Prepare transfer parameters */
2059 hi2c->pBuffPtr = pData;
2060 hi2c->XferCount = Size;
2061 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2062 hi2c->XferISR = I2C_Master_ISR_IT;
2063
2064 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2065 {
2066 hi2c->XferSize = MAX_NBYTE_SIZE;
2067 xfermode = I2C_RELOAD_MODE;
2068 }
2069 else
2070 {
2071 hi2c->XferSize = hi2c->XferCount;
2072 xfermode = I2C_AUTOEND_MODE;
2073 }
2074
2075 /* Send Slave Address and Memory Address */
2076 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2077 {
2078 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2079 {
2080 /* Process Unlocked */
2081 __HAL_UNLOCK(hi2c);
2082 return HAL_ERROR;
2083 }
2084 else
2085 {
2086 /* Process Unlocked */
2087 __HAL_UNLOCK(hi2c);
2088 return HAL_TIMEOUT;
2089 }
2090 }
2091
2092 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2093 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2094
2095 /* Process Unlocked */
2096 __HAL_UNLOCK(hi2c);
2097
2098 /* Note : The I2C interrupts must be enabled after unlocking current process
2099 to avoid the risk of I2C interrupt handle execution before current
2100 process unlock */
2101
2102 /* Enable ERR, TC, STOP, NACK, TXI interrupt */
2103 /* possible to enable all of these */
2104 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2105 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2106
2107 return HAL_OK;
2108 }
2109 else
2110 {
2111 return HAL_BUSY;
2112 }
2113 }
2114
2115 /**
2116 * @brief Read an amount of data in non-blocking mode with Interrupt from a specific memory address
2117 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2118 * the configuration information for the specified I2C.
2119 * @param DevAddress Target device address: The device 7 bits address value
2120 * in datasheet must be shift at right before call interface
2121 * @param MemAddress Internal memory address
2122 * @param MemAddSize Size of internal memory address
2123 * @param pData Pointer to data buffer
2124 * @param Size Amount of data to be sent
2125 * @retval HAL status
2126 */
2127 HAL_StatusTypeDef HAL_I2C_Mem_Read_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2128 {
2129 uint32_t tickstart = 0U;
2130 uint32_t xfermode = 0U;
2131
2132 /* Check the parameters */
2133 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2134
2135 if(hi2c->State == HAL_I2C_STATE_READY)
2136 {
2137 if((pData == NULL) || (Size == 0U))
2138 {
2139 return HAL_ERROR;
2140 }
2141
2142 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2143 {
2144 return HAL_BUSY;
2145 }
2146
2147 /* Process Locked */
2148 __HAL_LOCK(hi2c);
2149
2150 /* Init tickstart for timeout management*/
2151 tickstart = HAL_GetTick();
2152
2153 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2154 hi2c->Mode = HAL_I2C_MODE_MEM;
2155 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2156
2157 /* Prepare transfer parameters */
2158 hi2c->pBuffPtr = pData;
2159 hi2c->XferCount = Size;
2160 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2161 hi2c->XferISR = I2C_Master_ISR_IT;
2162
2163 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2164 {
2165 hi2c->XferSize = MAX_NBYTE_SIZE;
2166 xfermode = I2C_RELOAD_MODE;
2167 }
2168 else
2169 {
2170 hi2c->XferSize = hi2c->XferCount;
2171 xfermode = I2C_AUTOEND_MODE;
2172 }
2173
2174 /* Send Slave Address and Memory Address */
2175 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2176 {
2177 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2178 {
2179 /* Process Unlocked */
2180 __HAL_UNLOCK(hi2c);
2181 return HAL_ERROR;
2182 }
2183 else
2184 {
2185 /* Process Unlocked */
2186 __HAL_UNLOCK(hi2c);
2187 return HAL_TIMEOUT;
2188 }
2189 }
2190
2191 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2192 I2C_TransferConfig(hi2c,DevAddress,hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2193
2194 /* Process Unlocked */
2195 __HAL_UNLOCK(hi2c);
2196
2197 /* Note : The I2C interrupts must be enabled after unlocking current process
2198 to avoid the risk of I2C interrupt handle execution before current
2199 process unlock */
2200
2201 /* Enable ERR, TC, STOP, NACK, RXI interrupt */
2202 /* possible to enable all of these */
2203 /* I2C_IT_ERRI | I2C_IT_TCI| I2C_IT_STOPI| I2C_IT_NACKI | I2C_IT_ADDRI | I2C_IT_RXI | I2C_IT_TXI */
2204 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2205
2206 return HAL_OK;
2207 }
2208 else
2209 {
2210 return HAL_BUSY;
2211 }
2212 }
2213 /**
2214 * @brief Write an amount of data in non-blocking mode with DMA to a specific memory address
2215 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2216 * the configuration information for the specified I2C.
2217 * @param DevAddress Target device address: The device 7 bits address value
2218 * in datasheet must be shift at right before call interface
2219 * @param MemAddress Internal memory address
2220 * @param MemAddSize Size of internal memory address
2221 * @param pData Pointer to data buffer
2222 * @param Size Amount of data to be sent
2223 * @retval HAL status
2224 */
2225 HAL_StatusTypeDef HAL_I2C_Mem_Write_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2226 {
2227 uint32_t tickstart = 0U;
2228 uint32_t xfermode = 0U;
2229
2230 /* Check the parameters */
2231 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2232
2233 if(hi2c->State == HAL_I2C_STATE_READY)
2234 {
2235 if((pData == NULL) || (Size == 0U))
2236 {
2237 return HAL_ERROR;
2238 }
2239
2240 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2241 {
2242 return HAL_BUSY;
2243 }
2244
2245 /* Process Locked */
2246 __HAL_LOCK(hi2c);
2247
2248 /* Init tickstart for timeout management*/
2249 tickstart = HAL_GetTick();
2250
2251 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2252 hi2c->Mode = HAL_I2C_MODE_MEM;
2253 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2254
2255 /* Prepare transfer parameters */
2256 hi2c->pBuffPtr = pData;
2257 hi2c->XferCount = Size;
2258 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2259 hi2c->XferISR = I2C_Master_ISR_DMA;
2260
2261 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2262 {
2263 hi2c->XferSize = MAX_NBYTE_SIZE;
2264 xfermode = I2C_RELOAD_MODE;
2265 }
2266 else
2267 {
2268 hi2c->XferSize = hi2c->XferCount;
2269 xfermode = I2C_AUTOEND_MODE;
2270 }
2271
2272 /* Send Slave Address and Memory Address */
2273 if(I2C_RequestMemoryWrite(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2274 {
2275 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2276 {
2277 /* Process Unlocked */
2278 __HAL_UNLOCK(hi2c);
2279 return HAL_ERROR;
2280 }
2281 else
2282 {
2283 /* Process Unlocked */
2284 __HAL_UNLOCK(hi2c);
2285 return HAL_TIMEOUT;
2286 }
2287 }
2288
2289 /* Set the I2C DMA transfer complete callback */
2290 hi2c->hdmatx->XferCpltCallback = I2C_DMAMasterTransmitCplt;
2291
2292 /* Set the DMA error callback */
2293 hi2c->hdmatx->XferErrorCallback = I2C_DMAError;
2294
2295 /* Set the unused DMA callbacks to NULL */
2296 hi2c->hdmatx->XferHalfCpltCallback = NULL;
2297 hi2c->hdmatx->XferAbortCallback = NULL;
2298
2299 /* Enable the DMA channel */
2300 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)pData, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
2301
2302 /* Send Slave Address */
2303 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2304 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
2305
2306 /* Update XferCount value */
2307 hi2c->XferCount -= hi2c->XferSize;
2308
2309 /* Process Unlocked */
2310 __HAL_UNLOCK(hi2c);
2311
2312 /* Note : The I2C interrupts must be enabled after unlocking current process
2313 to avoid the risk of I2C interrupt handle execution before current
2314 process unlock */
2315 /* Enable ERR and NACK interrupts */
2316 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2317
2318 /* Enable DMA Request */
2319 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
2320
2321 return HAL_OK;
2322 }
2323 else
2324 {
2325 return HAL_BUSY;
2326 }
2327 }
2328
2329 /**
2330 * @brief Reads an amount of data in non-blocking mode with DMA from a specific memory address.
2331 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2332 * the configuration information for the specified I2C.
2333 * @param DevAddress Target device address: The device 7 bits address value
2334 * in datasheet must be shift at right before call interface
2335 * @param MemAddress Internal memory address
2336 * @param MemAddSize Size of internal memory address
2337 * @param pData Pointer to data buffer
2338 * @param Size Amount of data to be read
2339 * @retval HAL status
2340 */
2341 HAL_StatusTypeDef HAL_I2C_Mem_Read_DMA(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint8_t *pData, uint16_t Size)
2342 {
2343 uint32_t tickstart = 0U;
2344 uint32_t xfermode = 0U;
2345
2346 /* Check the parameters */
2347 assert_param(IS_I2C_MEMADD_SIZE(MemAddSize));
2348
2349 if(hi2c->State == HAL_I2C_STATE_READY)
2350 {
2351 if((pData == NULL) || (Size == 0U))
2352 {
2353 return HAL_ERROR;
2354 }
2355
2356 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2357 {
2358 return HAL_BUSY;
2359 }
2360
2361 /* Process Locked */
2362 __HAL_LOCK(hi2c);
2363
2364 /* Init tickstart for timeout management*/
2365 tickstart = HAL_GetTick();
2366
2367 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2368 hi2c->Mode = HAL_I2C_MODE_MEM;
2369 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2370
2371 /* Prepare transfer parameters */
2372 hi2c->pBuffPtr = pData;
2373 hi2c->XferCount = Size;
2374 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
2375 hi2c->XferISR = I2C_Master_ISR_DMA;
2376
2377 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2378 {
2379 hi2c->XferSize = MAX_NBYTE_SIZE;
2380 xfermode = I2C_RELOAD_MODE;
2381 }
2382 else
2383 {
2384 hi2c->XferSize = hi2c->XferCount;
2385 xfermode = I2C_AUTOEND_MODE;
2386 }
2387
2388 /* Send Slave Address and Memory Address */
2389 if(I2C_RequestMemoryRead(hi2c, DevAddress, MemAddress, MemAddSize, I2C_TIMEOUT_FLAG, tickstart) != HAL_OK)
2390 {
2391 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
2392 {
2393 /* Process Unlocked */
2394 __HAL_UNLOCK(hi2c);
2395 return HAL_ERROR;
2396 }
2397 else
2398 {
2399 /* Process Unlocked */
2400 __HAL_UNLOCK(hi2c);
2401 return HAL_TIMEOUT;
2402 }
2403 }
2404
2405 /* Set the I2C DMA transfer complete callback */
2406 hi2c->hdmarx->XferCpltCallback = I2C_DMAMasterReceiveCplt;
2407
2408 /* Set the DMA error callback */
2409 hi2c->hdmarx->XferErrorCallback = I2C_DMAError;
2410
2411 /* Set the unused DMA callbacks to NULL */
2412 hi2c->hdmarx->XferHalfCpltCallback = NULL;
2413 hi2c->hdmarx->XferAbortCallback = NULL;
2414
2415 /* Enable the DMA channel */
2416 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)pData, hi2c->XferSize);
2417
2418 /* Set NBYTES to write and reload if hi2c->XferCount > MAX_NBYTE_SIZE and generate RESTART */
2419 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, I2C_GENERATE_START_READ);
2420
2421 /* Update XferCount value */
2422 hi2c->XferCount -= hi2c->XferSize;
2423
2424 /* Process Unlocked */
2425 __HAL_UNLOCK(hi2c);
2426
2427 /* Enable DMA Request */
2428 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
2429
2430 /* Note : The I2C interrupts must be enabled after unlocking current process
2431 to avoid the risk of I2C interrupt handle execution before current
2432 process unlock */
2433 /* Enable ERR and NACK interrupts */
2434 I2C_Enable_IRQ(hi2c, I2C_XFER_ERROR_IT);
2435
2436 return HAL_OK;
2437 }
2438 else
2439 {
2440 return HAL_BUSY;
2441 }
2442 }
2443
2444 /**
2445 * @brief Checks if target device is ready for communication.
2446 * @note This function is used with Memory devices
2447 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2448 * the configuration information for the specified I2C.
2449 * @param DevAddress Target device address: The device 7 bits address value
2450 * in datasheet must be shift at right before call interface
2451 * @param Trials Number of trials
2452 * @param Timeout Timeout duration
2453 * @retval HAL status
2454 */
2455 HAL_StatusTypeDef HAL_I2C_IsDeviceReady(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint32_t Trials, uint32_t Timeout)
2456 {
2457 uint32_t tickstart = 0U;
2458
2459 __IO uint32_t I2C_Trials = 0U;
2460
2461 if(hi2c->State == HAL_I2C_STATE_READY)
2462 {
2463 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_BUSY) == SET)
2464 {
2465 return HAL_BUSY;
2466 }
2467
2468 /* Process Locked */
2469 __HAL_LOCK(hi2c);
2470
2471 hi2c->State = HAL_I2C_STATE_BUSY;
2472 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2473
2474 do
2475 {
2476 /* Generate Start */
2477 hi2c->Instance->CR2 = I2C_GENERATE_START(hi2c->Init.AddressingMode,DevAddress);
2478
2479 /* No need to Check TC flag, with AUTOEND mode the stop is automatically generated */
2480 /* Wait until STOPF flag is set or a NACK flag is set*/
2481 tickstart = HAL_GetTick();
2482 while((__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET) && (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET) && (hi2c->State != HAL_I2C_STATE_TIMEOUT))
2483 {
2484 if(Timeout != HAL_MAX_DELAY)
2485 {
2486 if((Timeout == 0U) || ((HAL_GetTick() - tickstart) > Timeout))
2487 {
2488 /* Device is ready */
2489 hi2c->State = HAL_I2C_STATE_READY;
2490 /* Process Unlocked */
2491 __HAL_UNLOCK(hi2c);
2492 return HAL_TIMEOUT;
2493 }
2494 }
2495 }
2496
2497 /* Check if the NACKF flag has not been set */
2498 if (__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == RESET)
2499 {
2500 /* Wait until STOPF flag is reset */
2501 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2502 {
2503 return HAL_TIMEOUT;
2504 }
2505
2506 /* Clear STOP Flag */
2507 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2508
2509 /* Device is ready */
2510 hi2c->State = HAL_I2C_STATE_READY;
2511
2512 /* Process Unlocked */
2513 __HAL_UNLOCK(hi2c);
2514
2515 return HAL_OK;
2516 }
2517 else
2518 {
2519 /* Wait until STOPF flag is reset */
2520 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2521 {
2522 return HAL_TIMEOUT;
2523 }
2524
2525 /* Clear NACK Flag */
2526 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
2527
2528 /* Clear STOP Flag, auto generated with autoend*/
2529 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2530 }
2531
2532 /* Check if the maximum allowed number of trials has been reached */
2533 if (I2C_Trials++ == Trials)
2534 {
2535 /* Generate Stop */
2536 hi2c->Instance->CR2 |= I2C_CR2_STOP;
2537
2538 /* Wait until STOPF flag is reset */
2539 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_STOPF, RESET, Timeout, tickstart) != HAL_OK)
2540 {
2541 return HAL_TIMEOUT;
2542 }
2543
2544 /* Clear STOP Flag */
2545 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
2546 }
2547 }while(I2C_Trials < Trials);
2548
2549 hi2c->State = HAL_I2C_STATE_READY;
2550
2551 /* Process Unlocked */
2552 __HAL_UNLOCK(hi2c);
2553
2554 return HAL_TIMEOUT;
2555 }
2556 else
2557 {
2558 return HAL_BUSY;
2559 }
2560 }
2561
2562 /**
2563 * @brief Sequential transmit in master I2C mode an amount of data in non-blocking mode with Interrupt.
2564 * @note This interface allow to manage repeated start condition when a direction change during transfer
2565 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2566 * the configuration information for the specified I2C.
2567 * @param DevAddress Target device address: The device 7 bits address value
2568 * in datasheet must be shift at right before call interface
2569 * @param pData Pointer to data buffer
2570 * @param Size Amount of data to be sent
2571 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
2572 * @retval HAL status
2573 */
2574 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2575 {
2576 uint32_t xfermode = 0U;
2577 uint32_t xferrequest = I2C_GENERATE_START_WRITE;
2578
2579 /* Check the parameters */
2580 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2581
2582 if(hi2c->State == HAL_I2C_STATE_READY)
2583 {
2584 /* Process Locked */
2585 __HAL_LOCK(hi2c);
2586
2587 hi2c->State = HAL_I2C_STATE_BUSY_TX;
2588 hi2c->Mode = HAL_I2C_MODE_MASTER;
2589 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2590
2591 /* Prepare transfer parameters */
2592 hi2c->pBuffPtr = pData;
2593 hi2c->XferCount = Size;
2594 hi2c->XferOptions = XferOptions;
2595 hi2c->XferISR = I2C_Master_ISR_IT;
2596
2597 /* If size > MAX_NBYTE_SIZE, use reload mode */
2598 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2599 {
2600 hi2c->XferSize = MAX_NBYTE_SIZE;
2601 xfermode = I2C_RELOAD_MODE;
2602 }
2603 else
2604 {
2605 hi2c->XferSize = hi2c->XferCount;
2606 xfermode = hi2c->XferOptions;
2607 }
2608
2609 /* If transfer direction not change, do not generate Restart Condition */
2610 /* Mean Previous state is same as current state */
2611 if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_TX)
2612 {
2613 xferrequest = I2C_NO_STARTSTOP;
2614 }
2615
2616 /* Send Slave Address and set NBYTES to write */
2617 I2C_TransferConfig(hi2c, DevAddress, hi2c->XferSize, xfermode, xferrequest);
2618
2619 /* Process Unlocked */
2620 __HAL_UNLOCK(hi2c);
2621
2622 /* Note : The I2C interrupts must be enabled after unlocking current process
2623 to avoid the risk of I2C interrupt handle execution before current
2624 process unlock */
2625 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT);
2626
2627 return HAL_OK;
2628 }
2629 else
2630 {
2631 return HAL_BUSY;
2632 }
2633 }
2634
2635 /**
2636 * @brief Sequential receive in master I2C mode an amount of data in non-blocking mode with Interrupt
2637 * @note This interface allow to manage repeated start condition when a direction change during transfer
2638 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2639 * the configuration information for the specified I2C.
2640 * @param DevAddress Target device address: The device 7 bits address value
2641 * in datasheet must be shift at right before call interface
2642 * @param pData Pointer to data buffer
2643 * @param Size Amount of data to be sent
2644 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
2645 * @retval HAL status
2646 */
2647 HAL_StatusTypeDef HAL_I2C_Master_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2648 {
2649 uint32_t xfermode = 0U;
2650 uint32_t xferrequest = I2C_GENERATE_START_READ;
2651
2652 /* Check the parameters */
2653 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2654
2655 if(hi2c->State == HAL_I2C_STATE_READY)
2656 {
2657 /* Process Locked */
2658 __HAL_LOCK(hi2c);
2659
2660 hi2c->State = HAL_I2C_STATE_BUSY_RX;
2661 hi2c->Mode = HAL_I2C_MODE_MASTER;
2662 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2663
2664 /* Prepare transfer parameters */
2665 hi2c->pBuffPtr = pData;
2666 hi2c->XferCount = Size;
2667 hi2c->XferOptions = XferOptions;
2668 hi2c->XferISR = I2C_Master_ISR_IT;
2669
2670 /* If hi2c->XferCount > MAX_NBYTE_SIZE, use reload mode */
2671 if(hi2c->XferCount > MAX_NBYTE_SIZE)
2672 {
2673 hi2c->XferSize = MAX_NBYTE_SIZE;
2674 xfermode = I2C_RELOAD_MODE;
2675 }
2676 else
2677 {
2678 hi2c->XferSize = hi2c->XferCount;
2679 xfermode = hi2c->XferOptions;
2680 }
2681
2682 /* If transfer direction not change, do not generate Restart Condition */
2683 /* Mean Previous state is same as current state */
2684 if(hi2c->PreviousState == I2C_STATE_MASTER_BUSY_RX)
2685 {
2686 xferrequest = I2C_NO_STARTSTOP;
2687 }
2688
2689 /* Send Slave Address and set NBYTES to read */
2690 I2C_TransferConfig(hi2c,DevAddress, hi2c->XferSize, xfermode, xferrequest);
2691
2692 /* Process Unlocked */
2693 __HAL_UNLOCK(hi2c);
2694
2695 /* Note : The I2C interrupts must be enabled after unlocking current process
2696 to avoid the risk of I2C interrupt handle execution before current
2697 process unlock */
2698 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT);
2699
2700 return HAL_OK;
2701 }
2702 else
2703 {
2704 return HAL_BUSY;
2705 }
2706 }
2707
2708 /**
2709 * @brief Sequential transmit in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
2710 * @note This interface allow to manage repeated start condition when a direction change during transfer
2711 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2712 * the configuration information for the specified I2C.
2713 * @param pData Pointer to data buffer
2714 * @param Size Amount of data to be sent
2715 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
2716 * @retval HAL status
2717 */
2718 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Transmit_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2719 {
2720 /* Check the parameters */
2721 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2722
2723 if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
2724 {
2725 if((pData == NULL) || (Size == 0U))
2726 {
2727 return HAL_ERROR;
2728 }
2729
2730 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
2731 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT);
2732
2733 /* Process Locked */
2734 __HAL_LOCK(hi2c);
2735
2736 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
2737 /* and then toggle the HAL slave RX state to TX state */
2738 if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
2739 {
2740 /* Disable associated Interrupts */
2741 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
2742 }
2743
2744 hi2c->State = HAL_I2C_STATE_BUSY_TX_LISTEN;
2745 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2746 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2747
2748 /* Enable Address Acknowledge */
2749 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2750
2751 /* Prepare transfer parameters */
2752 hi2c->pBuffPtr = pData;
2753 hi2c->XferCount = Size;
2754 hi2c->XferSize = hi2c->XferCount;
2755 hi2c->XferOptions = XferOptions;
2756 hi2c->XferISR = I2C_Slave_ISR_IT;
2757
2758 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_RECEIVE)
2759 {
2760 /* Clear ADDR flag after prepare the transfer parameters */
2761 /* This action will generate an acknowledge to the Master */
2762 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
2763 }
2764
2765 /* Process Unlocked */
2766 __HAL_UNLOCK(hi2c);
2767
2768 /* Note : The I2C interrupts must be enabled after unlocking current process
2769 to avoid the risk of I2C interrupt handle execution before current
2770 process unlock */
2771 /* REnable ADDR interrupt */
2772 I2C_Enable_IRQ(hi2c, I2C_XFER_TX_IT | I2C_XFER_LISTEN_IT);
2773
2774 return HAL_OK;
2775 }
2776 else
2777 {
2778 return HAL_ERROR;
2779 }
2780 }
2781
2782 /**
2783 * @brief Sequential receive in slave/device I2C mode an amount of data in non-blocking mode with Interrupt
2784 * @note This interface allow to manage repeated start condition when a direction change during transfer
2785 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2786 * the configuration information for the specified I2C.
2787 * @param pData Pointer to data buffer
2788 * @param Size Amount of data to be sent
2789 * @param XferOptions Options of Transfer, value of @ref I2C_XFEROPTIONS
2790 * @retval HAL status
2791 */
2792 HAL_StatusTypeDef HAL_I2C_Slave_Sequential_Receive_IT(I2C_HandleTypeDef *hi2c, uint8_t *pData, uint16_t Size, uint32_t XferOptions)
2793 {
2794 /* Check the parameters */
2795 assert_param(IS_I2C_TRANSFER_OPTIONS_REQUEST(XferOptions));
2796
2797 if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
2798 {
2799 if((pData == NULL) || (Size == 0U))
2800 {
2801 return HAL_ERROR;
2802 }
2803
2804 /* Disable Interrupts, to prevent preemption during treatment in case of multicall */
2805 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT);
2806
2807 /* Process Locked */
2808 __HAL_LOCK(hi2c);
2809
2810 /* I2C cannot manage full duplex exchange so disable previous IT enabled if any */
2811 /* and then toggle the HAL slave TX state to RX state */
2812 if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
2813 {
2814 /* Disable associated Interrupts */
2815 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
2816 }
2817
2818 hi2c->State = HAL_I2C_STATE_BUSY_RX_LISTEN;
2819 hi2c->Mode = HAL_I2C_MODE_SLAVE;
2820 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
2821
2822 /* Enable Address Acknowledge */
2823 hi2c->Instance->CR2 &= ~I2C_CR2_NACK;
2824
2825 /* Prepare transfer parameters */
2826 hi2c->pBuffPtr = pData;
2827 hi2c->XferCount = Size;
2828 hi2c->XferSize = hi2c->XferCount;
2829 hi2c->XferOptions = XferOptions;
2830 hi2c->XferISR = I2C_Slave_ISR_IT;
2831
2832 if(I2C_GET_DIR(hi2c) == I2C_DIRECTION_TRANSMIT)
2833 {
2834 /* Clear ADDR flag after prepare the transfer parameters */
2835 /* This action will generate an acknowledge to the Master */
2836 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
2837 }
2838
2839 /* Process Unlocked */
2840 __HAL_UNLOCK(hi2c);
2841
2842 /* Note : The I2C interrupts must be enabled after unlocking current process
2843 to avoid the risk of I2C interrupt handle execution before current
2844 process unlock */
2845 /* REnable ADDR interrupt */
2846 I2C_Enable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_LISTEN_IT);
2847
2848 return HAL_OK;
2849 }
2850 else
2851 {
2852 return HAL_ERROR;
2853 }
2854 }
2855
2856 /**
2857 * @brief Enable the Address listen mode with Interrupt.
2858 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2859 * the configuration information for the specified I2C.
2860 * @retval HAL status
2861 */
2862 HAL_StatusTypeDef HAL_I2C_EnableListen_IT(I2C_HandleTypeDef *hi2c)
2863 {
2864 if(hi2c->State == HAL_I2C_STATE_READY)
2865 {
2866 hi2c->State = HAL_I2C_STATE_LISTEN;
2867 hi2c->XferISR = I2C_Slave_ISR_IT;
2868
2869 /* Enable the Address Match interrupt */
2870 I2C_Enable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2871
2872 return HAL_OK;
2873 }
2874 else
2875 {
2876 return HAL_BUSY;
2877 }
2878 }
2879
2880 /**
2881 * @brief Disable the Address listen mode with Interrupt.
2882 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2883 * the configuration information for the specified I2C
2884 * @retval HAL status
2885 */
2886 HAL_StatusTypeDef HAL_I2C_DisableListen_IT(I2C_HandleTypeDef *hi2c)
2887 {
2888 /* Declaration of tmp to prevent undefined behavior of volatile usage */
2889 uint32_t tmp;
2890
2891 /* Disable Address listen mode only if a transfer is not ongoing */
2892 if(hi2c->State == HAL_I2C_STATE_LISTEN)
2893 {
2894 tmp = (uint32_t)(hi2c->State) & I2C_STATE_MSK;
2895 hi2c->PreviousState = tmp | (uint32_t)(hi2c->Mode);
2896 hi2c->State = HAL_I2C_STATE_READY;
2897 hi2c->Mode = HAL_I2C_MODE_NONE;
2898 hi2c->XferISR = NULL;
2899
2900 /* Disable the Address Match interrupt */
2901 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
2902
2903 return HAL_OK;
2904 }
2905 else
2906 {
2907 return HAL_BUSY;
2908 }
2909 }
2910
2911 /**
2912 * @brief Abort a master I2C IT or DMA process communication with Interrupt.
2913 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2914 * the configuration information for the specified I2C.
2915 * @param DevAddress Target device address: The device 7 bits address value
2916 * in datasheet must be shift at right before call interface
2917 * @retval HAL status
2918 */
2919 HAL_StatusTypeDef HAL_I2C_Master_Abort_IT(I2C_HandleTypeDef *hi2c, uint16_t DevAddress)
2920 {
2921 if(hi2c->Mode == HAL_I2C_MODE_MASTER)
2922 {
2923 /* Process Locked */
2924 __HAL_LOCK(hi2c);
2925
2926 /* Disable Interrupts */
2927 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
2928 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
2929
2930 /* Set State at HAL_I2C_STATE_ABORT */
2931 hi2c->State = HAL_I2C_STATE_ABORT;
2932
2933 /* Set NBYTES to 1 to generate a dummy read on I2C peripheral */
2934 /* Set AUTOEND mode, this will generate a NACK then STOP condition to abort the current transfer */
2935 I2C_TransferConfig(hi2c, DevAddress, 1, I2C_AUTOEND_MODE, I2C_GENERATE_STOP);
2936
2937 /* Process Unlocked */
2938 __HAL_UNLOCK(hi2c);
2939
2940 /* Note : The I2C interrupts must be enabled after unlocking current process
2941 to avoid the risk of I2C interrupt handle execution before current
2942 process unlock */
2943 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
2944
2945 return HAL_OK;
2946 }
2947 else
2948 {
2949 /* Wrong usage of abort function */
2950 /* This function should be used only in case of abort monitored by master device */
2951 return HAL_ERROR;
2952 }
2953 }
2954
2955 /**
2956 * @}
2957 */
2958
2959 /** @defgroup I2C_IRQ_Handler_and_Callbacks IRQ Handler and Callbacks
2960 * @{
2961 */
2962
2963 /**
2964 * @brief This function handles I2C event interrupt request.
2965 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2966 * the configuration information for the specified I2C.
2967 * @retval None
2968 */
2969 void HAL_I2C_EV_IRQHandler(I2C_HandleTypeDef *hi2c)
2970 {
2971 /* Get current IT Flags and IT sources value */
2972 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
2973 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
2974
2975 /* I2C events treatment -------------------------------------*/
2976 if(hi2c->XferISR != NULL)
2977 {
2978 hi2c->XferISR(hi2c, itflags, itsources);
2979 }
2980 }
2981
2982 /**
2983 * @brief This function handles I2C error interrupt request.
2984 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
2985 * the configuration information for the specified I2C.
2986 * @retval None
2987 */
2988 void HAL_I2C_ER_IRQHandler(I2C_HandleTypeDef *hi2c)
2989 {
2990 uint32_t itflags = READ_REG(hi2c->Instance->ISR);
2991 uint32_t itsources = READ_REG(hi2c->Instance->CR1);
2992
2993 /* I2C Bus error interrupt occurred ------------------------------------*/
2994 if(((itflags & I2C_FLAG_BERR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
2995 {
2996 hi2c->ErrorCode |= HAL_I2C_ERROR_BERR;
2997
2998 /* Clear BERR flag */
2999 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_BERR);
3000 }
3001
3002 /* I2C Over-Run/Under-Run interrupt occurred ----------------------------------------*/
3003 if(((itflags & I2C_FLAG_OVR) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
3004 {
3005 hi2c->ErrorCode |= HAL_I2C_ERROR_OVR;
3006
3007 /* Clear OVR flag */
3008 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_OVR);
3009 }
3010
3011 /* I2C Arbitration Loss error interrupt occurred -------------------------------------*/
3012 if(((itflags & I2C_FLAG_ARLO) != RESET) && ((itsources & I2C_IT_ERRI) != RESET))
3013 {
3014 hi2c->ErrorCode |= HAL_I2C_ERROR_ARLO;
3015
3016 /* Clear ARLO flag */
3017 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ARLO);
3018 }
3019
3020 /* Call the Error Callback in case of Error detected */
3021 if((hi2c->ErrorCode & (HAL_I2C_ERROR_BERR | HAL_I2C_ERROR_OVR | HAL_I2C_ERROR_ARLO)) != HAL_I2C_ERROR_NONE)
3022 {
3023 I2C_ITError(hi2c, hi2c->ErrorCode);
3024 }
3025 }
3026
3027 /**
3028 * @brief Master Tx Transfer completed callback.
3029 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3030 * the configuration information for the specified I2C.
3031 * @retval None
3032 */
3033 __weak void HAL_I2C_MasterTxCpltCallback(I2C_HandleTypeDef *hi2c)
3034 {
3035 /* Prevent unused argument(s) compilation warning */
3036 UNUSED(hi2c);
3037
3038 /* NOTE : This function should not be modified, when the callback is needed,
3039 the HAL_I2C_MasterTxCpltCallback could be implemented in the user file
3040 */
3041 }
3042
3043 /**
3044 * @brief Master Rx Transfer completed callback.
3045 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3046 * the configuration information for the specified I2C.
3047 * @retval None
3048 */
3049 __weak void HAL_I2C_MasterRxCpltCallback(I2C_HandleTypeDef *hi2c)
3050 {
3051 /* Prevent unused argument(s) compilation warning */
3052 UNUSED(hi2c);
3053
3054 /* NOTE : This function should not be modified, when the callback is needed,
3055 the HAL_I2C_MasterRxCpltCallback could be implemented in the user file
3056 */
3057 }
3058
3059 /** @brief Slave Tx Transfer completed callback.
3060 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3061 * the configuration information for the specified I2C.
3062 * @retval None
3063 */
3064 __weak void HAL_I2C_SlaveTxCpltCallback(I2C_HandleTypeDef *hi2c)
3065 {
3066 /* Prevent unused argument(s) compilation warning */
3067 UNUSED(hi2c);
3068
3069 /* NOTE : This function should not be modified, when the callback is needed,
3070 the HAL_I2C_SlaveTxCpltCallback could be implemented in the user file
3071 */
3072 }
3073
3074 /**
3075 * @brief Slave Rx Transfer completed callback.
3076 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3077 * the configuration information for the specified I2C.
3078 * @retval None
3079 */
3080 __weak void HAL_I2C_SlaveRxCpltCallback(I2C_HandleTypeDef *hi2c)
3081 {
3082 /* Prevent unused argument(s) compilation warning */
3083 UNUSED(hi2c);
3084
3085 /* NOTE : This function should not be modified, when the callback is needed,
3086 the HAL_I2C_SlaveRxCpltCallback could be implemented in the user file
3087 */
3088 }
3089
3090 /**
3091 * @brief Slave Address Match callback.
3092 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3093 * the configuration information for the specified I2C.
3094 * @param TransferDirection: Master request Transfer Direction (Write/Read), value of @ref I2C_XFERDIRECTION
3095 * @param AddrMatchCode: Address Match Code
3096 * @retval None
3097 */
3098 __weak void HAL_I2C_AddrCallback(I2C_HandleTypeDef *hi2c, uint8_t TransferDirection, uint16_t AddrMatchCode)
3099 {
3100 /* Prevent unused argument(s) compilation warning */
3101 UNUSED(hi2c);
3102 UNUSED(TransferDirection);
3103 UNUSED(AddrMatchCode);
3104
3105 /* NOTE : This function should not be modified, when the callback is needed,
3106 the HAL_I2C_AddrCallback() could be implemented in the user file
3107 */
3108 }
3109
3110 /**
3111 * @brief Listen Complete callback.
3112 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3113 * the configuration information for the specified I2C.
3114 * @retval None
3115 */
3116 __weak void HAL_I2C_ListenCpltCallback(I2C_HandleTypeDef *hi2c)
3117 {
3118 /* Prevent unused argument(s) compilation warning */
3119 UNUSED(hi2c);
3120
3121 /* NOTE : This function should not be modified, when the callback is needed,
3122 the HAL_I2C_ListenCpltCallback() could be implemented in the user file
3123 */
3124 }
3125
3126 /**
3127 * @brief Memory Tx Transfer completed callback.
3128 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3129 * the configuration information for the specified I2C.
3130 * @retval None
3131 */
3132 __weak void HAL_I2C_MemTxCpltCallback(I2C_HandleTypeDef *hi2c)
3133 {
3134 /* Prevent unused argument(s) compilation warning */
3135 UNUSED(hi2c);
3136
3137 /* NOTE : This function should not be modified, when the callback is needed,
3138 the HAL_I2C_MemTxCpltCallback could be implemented in the user file
3139 */
3140 }
3141
3142 /**
3143 * @brief Memory Rx Transfer completed callback.
3144 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3145 * the configuration information for the specified I2C.
3146 * @retval None
3147 */
3148 __weak void HAL_I2C_MemRxCpltCallback(I2C_HandleTypeDef *hi2c)
3149 {
3150 /* Prevent unused argument(s) compilation warning */
3151 UNUSED(hi2c);
3152
3153 /* NOTE : This function should not be modified, when the callback is needed,
3154 the HAL_I2C_MemRxCpltCallback could be implemented in the user file
3155 */
3156 }
3157
3158 /**
3159 * @brief I2C error callback.
3160 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3161 * the configuration information for the specified I2C.
3162 * @retval None
3163 */
3164 __weak void HAL_I2C_ErrorCallback(I2C_HandleTypeDef *hi2c)
3165 {
3166 /* Prevent unused argument(s) compilation warning */
3167 UNUSED(hi2c);
3168
3169 /* NOTE : This function should not be modified, when the callback is needed,
3170 the HAL_I2C_ErrorCallback could be implemented in the user file
3171 */
3172 }
3173
3174 /**
3175 * @brief I2C abort callback.
3176 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3177 * the configuration information for the specified I2C.
3178 * @retval None
3179 */
3180 __weak void HAL_I2C_AbortCpltCallback(I2C_HandleTypeDef *hi2c)
3181 {
3182 /* Prevent unused argument(s) compilation warning */
3183 UNUSED(hi2c);
3184
3185 /* NOTE : This function should not be modified, when the callback is needed,
3186 the HAL_I2C_AbortCpltCallback could be implemented in the user file
3187 */
3188 }
3189
3190 /**
3191 * @}
3192 */
3193
3194 /** @defgroup I2C_Exported_Functions_Group3 Peripheral State, Mode and Error functions
3195 * @brief Peripheral State, Mode and Error functions
3196 *
3197 @verbatim
3198 ===============================================================================
3199 ##### Peripheral State, Mode and Error functions #####
3200 ===============================================================================
3201 [..]
3202 This subsection permit to get in run-time the status of the peripheral
3203 and the data flow.
3204
3205 @endverbatim
3206 * @{
3207 */
3208
3209 /**
3210 * @brief Return the I2C handle state.
3211 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3212 * the configuration information for the specified I2C.
3213 * @retval HAL state
3214 */
3215 HAL_I2C_StateTypeDef HAL_I2C_GetState(I2C_HandleTypeDef *hi2c)
3216 {
3217 /* Return I2C handle state */
3218 return hi2c->State;
3219 }
3220
3221 /**
3222 * @brief Returns the I2C Master, Slave, Memory or no mode.
3223 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3224 * the configuration information for I2C module
3225 * @retval HAL mode
3226 */
3227 HAL_I2C_ModeTypeDef HAL_I2C_GetMode(I2C_HandleTypeDef *hi2c)
3228 {
3229 return hi2c->Mode;
3230 }
3231
3232 /**
3233 * @brief Return the I2C error code.
3234 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3235 * the configuration information for the specified I2C.
3236 * @retval I2C Error Code
3237 */
3238 uint32_t HAL_I2C_GetError(I2C_HandleTypeDef *hi2c)
3239 {
3240 return hi2c->ErrorCode;
3241 }
3242
3243 /**
3244 * @}
3245 */
3246
3247 /**
3248 * @}
3249 */
3250
3251 /** @addtogroup I2C_Private_Functions
3252 * @{
3253 */
3254
3255 /**
3256 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with Interrupt.
3257 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3258 * the configuration information for the specified I2C.
3259 * @param ITFlags Interrupt flags to handle.
3260 * @param ITSources Interrupt sources enabled.
3261 * @retval HAL status
3262 */
3263 static HAL_StatusTypeDef I2C_Master_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3264 {
3265 uint16_t devaddress = 0U;
3266
3267 /* Process Locked */
3268 __HAL_LOCK(hi2c);
3269
3270 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3271 {
3272 /* Clear NACK Flag */
3273 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3274
3275 /* Set corresponding Error Code */
3276 /* No need to generate STOP, it is automatically done */
3277 /* Error callback will be send during stop flag treatment */
3278 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3279
3280 /* Flush TX register */
3281 I2C_Flush_TXDR(hi2c);
3282 }
3283 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
3284 {
3285 /* Read data from RXDR */
3286 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
3287 hi2c->XferSize--;
3288 hi2c->XferCount--;
3289 }
3290 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
3291 {
3292 /* Write data to TXDR */
3293 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
3294 hi2c->XferSize--;
3295 hi2c->XferCount--;
3296 }
3297 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3298 {
3299 if((hi2c->XferSize == 0U) && (hi2c->XferCount != 0U))
3300 {
3301 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
3302
3303 if(hi2c->XferCount > MAX_NBYTE_SIZE)
3304 {
3305 hi2c->XferSize = MAX_NBYTE_SIZE;
3306 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_RELOAD_MODE, I2C_NO_STARTSTOP);
3307 }
3308 else
3309 {
3310 hi2c->XferSize = hi2c->XferCount;
3311 if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
3312 {
3313 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, hi2c->XferOptions, I2C_NO_STARTSTOP);
3314 }
3315 else
3316 {
3317 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, I2C_AUTOEND_MODE, I2C_NO_STARTSTOP);
3318 }
3319 }
3320 }
3321 else
3322 {
3323 /* Call TxCpltCallback() if no stop mode is set */
3324 if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
3325 {
3326 /* Call I2C Master Sequential complete process */
3327 I2C_ITMasterSequentialCplt(hi2c);
3328 }
3329 else
3330 {
3331 /* Wrong size Status regarding TCR flag event */
3332 /* Call the corresponding callback to inform upper layer of End of Transfer */
3333 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3334 }
3335 }
3336 }
3337 else if(((ITFlags & I2C_FLAG_TC) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3338 {
3339 if(hi2c->XferCount == 0U)
3340 {
3341 if(I2C_GET_STOP_MODE(hi2c) != I2C_AUTOEND_MODE)
3342 {
3343 /* Generate a stop condition in case of no transfer option */
3344 if(hi2c->XferOptions == I2C_NO_OPTION_FRAME)
3345 {
3346 /* Generate Stop */
3347 hi2c->Instance->CR2 |= I2C_CR2_STOP;
3348 }
3349 else
3350 {
3351 /* Call I2C Master Sequential complete process */
3352 I2C_ITMasterSequentialCplt(hi2c);
3353 }
3354 }
3355 }
3356 else
3357 {
3358 /* Wrong size Status regarding TC flag event */
3359 /* Call the corresponding callback to inform upper layer of End of Transfer */
3360 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3361 }
3362 }
3363
3364 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3365 {
3366 /* Call I2C Master complete process */
3367 I2C_ITMasterCplt(hi2c, ITFlags);
3368 }
3369
3370 /* Process Unlocked */
3371 __HAL_UNLOCK(hi2c);
3372
3373 return HAL_OK;
3374 }
3375
3376 /**
3377 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with Interrupt.
3378 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3379 * the configuration information for the specified I2C.
3380 * @param ITFlags Interrupt flags to handle.
3381 * @param ITSources Interrupt sources enabled.
3382 * @retval HAL status
3383 */
3384 static HAL_StatusTypeDef I2C_Slave_ISR_IT(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3385 {
3386 /* Process locked */
3387 __HAL_LOCK(hi2c);
3388
3389 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3390 {
3391 /* Check that I2C transfer finished */
3392 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
3393 /* Mean XferCount == 0*/
3394 /* So clear Flag NACKF only */
3395 if(hi2c->XferCount == 0U)
3396 {
3397 if(((hi2c->XferOptions == I2C_FIRST_AND_LAST_FRAME) || (hi2c->XferOptions == I2C_LAST_FRAME)) && \
3398 (hi2c->State == HAL_I2C_STATE_LISTEN))
3399 {
3400 /* Call I2C Listen complete process */
3401 I2C_ITListenCplt(hi2c, ITFlags);
3402 }
3403 else if((hi2c->XferOptions != I2C_NO_OPTION_FRAME) && (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN))
3404 {
3405 /* Clear NACK Flag */
3406 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3407
3408 /* Flush TX register */
3409 I2C_Flush_TXDR(hi2c);
3410
3411 /* Last Byte is Transmitted */
3412 /* Call I2C Slave Sequential complete process */
3413 I2C_ITSlaveSequentialCplt(hi2c);
3414 }
3415 else
3416 {
3417 /* Clear NACK Flag */
3418 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3419 }
3420 }
3421 else
3422 {
3423 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
3424 /* Clear NACK Flag */
3425 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3426
3427 /* Set ErrorCode corresponding to a Non-Acknowledge */
3428 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3429 }
3430 }
3431 else if(((ITFlags & I2C_FLAG_RXNE) != RESET) && ((ITSources & I2C_IT_RXI) != RESET))
3432 {
3433 if(hi2c->XferCount > 0U)
3434 {
3435 /* Read data from RXDR */
3436 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
3437 hi2c->XferSize--;
3438 hi2c->XferCount--;
3439 }
3440
3441 if((hi2c->XferCount == 0U) && \
3442 (hi2c->XferOptions != I2C_NO_OPTION_FRAME))
3443 {
3444 /* Call I2C Slave Sequential complete process */
3445 I2C_ITSlaveSequentialCplt(hi2c);
3446 }
3447 }
3448 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
3449 {
3450 I2C_ITAddrCplt(hi2c, ITFlags);
3451 }
3452 else if(((ITFlags & I2C_FLAG_TXIS) != RESET) && ((ITSources & I2C_IT_TXI) != RESET))
3453 {
3454 /* Write data to TXDR only if XferCount not reach "0" */
3455 /* A TXIS flag can be set, during STOP treatment */
3456 /* Check if all Datas have already been sent */
3457 /* If it is the case, this last write in TXDR is not sent, correspond to a dummy TXIS event */
3458 if(hi2c->XferCount > 0U)
3459 {
3460 /* Write data to TXDR */
3461 hi2c->Instance->TXDR = (*hi2c->pBuffPtr++);
3462 hi2c->XferCount--;
3463 hi2c->XferSize--;
3464 }
3465 else
3466 {
3467 if((hi2c->XferOptions == I2C_NEXT_FRAME) || (hi2c->XferOptions == I2C_FIRST_FRAME))
3468 {
3469 /* Last Byte is Transmitted */
3470 /* Call I2C Slave Sequential complete process */
3471 I2C_ITSlaveSequentialCplt(hi2c);
3472 }
3473 }
3474 }
3475
3476 /* Check if STOPF is set */
3477 if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3478 {
3479 /* Call I2C Slave complete process */
3480 I2C_ITSlaveCplt(hi2c, ITFlags);
3481 }
3482
3483 /* Process Unlocked */
3484 __HAL_UNLOCK(hi2c);
3485
3486 return HAL_OK;
3487 }
3488
3489 /**
3490 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Master Mode with DMA.
3491 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3492 * the configuration information for the specified I2C.
3493 * @param ITFlags Interrupt flags to handle.
3494 * @param ITSources Interrupt sources enabled.
3495 * @retval HAL status
3496 */
3497 static HAL_StatusTypeDef I2C_Master_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3498 {
3499 uint16_t devaddress = 0U;
3500 uint32_t xfermode = 0U;
3501
3502 /* Process Locked */
3503 __HAL_LOCK(hi2c);
3504
3505 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3506 {
3507 /* Clear NACK Flag */
3508 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3509
3510 /* Set corresponding Error Code */
3511 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3512
3513 /* No need to generate STOP, it is automatically done */
3514 /* But enable STOP interrupt, to treat it */
3515 /* Error callback will be send during stop flag treatment */
3516 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
3517
3518 /* Flush TX register */
3519 I2C_Flush_TXDR(hi2c);
3520 }
3521 else if(((ITFlags & I2C_FLAG_TCR) != RESET) && ((ITSources & I2C_IT_TCI) != RESET))
3522 {
3523 /* Disable TC interrupt */
3524 __HAL_I2C_DISABLE_IT(hi2c, I2C_IT_TCI);
3525
3526 if(hi2c->XferCount != 0U)
3527 {
3528 /* Recover Slave address */
3529 devaddress = (hi2c->Instance->CR2 & I2C_CR2_SADD);
3530
3531 /* Prepare the new XferSize to transfer */
3532 if(hi2c->XferCount > MAX_NBYTE_SIZE)
3533 {
3534 hi2c->XferSize = MAX_NBYTE_SIZE;
3535 xfermode = I2C_RELOAD_MODE;
3536 }
3537 else
3538 {
3539 hi2c->XferSize = hi2c->XferCount;
3540 xfermode = I2C_AUTOEND_MODE;
3541 }
3542
3543 /* Set the new XferSize in Nbytes register */
3544 I2C_TransferConfig(hi2c, devaddress, hi2c->XferSize, xfermode, I2C_NO_STARTSTOP);
3545
3546 /* Update XferCount value */
3547 hi2c->XferCount -= hi2c->XferSize;
3548
3549 /* Enable DMA Request */
3550 if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
3551 {
3552 hi2c->Instance->CR1 |= I2C_CR1_RXDMAEN;
3553 }
3554 else
3555 {
3556 hi2c->Instance->CR1 |= I2C_CR1_TXDMAEN;
3557 }
3558 }
3559 else
3560 {
3561 /* Wrong size Status regarding TCR flag event */
3562 /* Call the corresponding callback to inform upper layer of End of Transfer */
3563 I2C_ITError(hi2c, HAL_I2C_ERROR_SIZE);
3564 }
3565 }
3566 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3567 {
3568 /* Call I2C Master complete process */
3569 I2C_ITMasterCplt(hi2c, ITFlags);
3570 }
3571
3572 /* Process Unlocked */
3573 __HAL_UNLOCK(hi2c);
3574
3575 return HAL_OK;
3576 }
3577
3578 /**
3579 * @brief Interrupt Sub-Routine which handle the Interrupt Flags Slave Mode with DMA.
3580 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3581 * the configuration information for the specified I2C.
3582 * @param ITFlags Interrupt flags to handle.
3583 * @param ITSources Interrupt sources enabled.
3584 * @retval HAL status
3585 */
3586 static HAL_StatusTypeDef I2C_Slave_ISR_DMA(struct __I2C_HandleTypeDef *hi2c, uint32_t ITFlags, uint32_t ITSources)
3587 {
3588 /* Process locked */
3589 __HAL_LOCK(hi2c);
3590
3591 if(((ITFlags & I2C_FLAG_AF) != RESET) && ((ITSources & I2C_IT_NACKI) != RESET))
3592 {
3593 /* Check that I2C transfer finished */
3594 /* if yes, normal use case, a NACK is sent by the MASTER when Transfer is finished */
3595 /* Mean XferCount == 0 */
3596 /* So clear Flag NACKF only */
3597 if(I2C_GET_DMA_REMAIN_DATA(hi2c) == 0U)
3598 {
3599 /* Clear NACK Flag */
3600 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3601 }
3602 else
3603 {
3604 /* if no, error use case, a Non-Acknowledge of last Data is generated by the MASTER*/
3605 /* Clear NACK Flag */
3606 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3607
3608 /* Set ErrorCode corresponding to a Non-Acknowledge */
3609 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3610 }
3611 }
3612 else if(((ITFlags & I2C_FLAG_ADDR) != RESET) && ((ITSources & I2C_IT_ADDRI) != RESET))
3613 {
3614 /* Clear ADDR flag */
3615 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3616 }
3617 else if(((ITFlags & I2C_FLAG_STOPF) != RESET) && ((ITSources & I2C_IT_STOPI) != RESET))
3618 {
3619 /* Call I2C Slave complete process */
3620 I2C_ITSlaveCplt(hi2c, ITFlags);
3621 }
3622
3623 /* Process Unlocked */
3624 __HAL_UNLOCK(hi2c);
3625
3626 return HAL_OK;
3627 }
3628
3629 /**
3630 * @brief Master sends target device address followed by internal memory address for write request.
3631 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3632 * the configuration information for the specified I2C.
3633 * @param DevAddress Target device address: The device 7 bits address value
3634 * in datasheet must be shift at right before call interface
3635 * @param MemAddress Internal memory address
3636 * @param MemAddSize Size of internal memory address
3637 * @param Timeout Timeout duration
3638 * @param Tickstart Tick start value
3639 * @retval HAL status
3640 */
3641 static HAL_StatusTypeDef I2C_RequestMemoryWrite(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
3642 {
3643 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_RELOAD_MODE, I2C_GENERATE_START_WRITE);
3644
3645 /* Wait until TXIS flag is set */
3646 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3647 {
3648 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3649 {
3650 return HAL_ERROR;
3651 }
3652 else
3653 {
3654 return HAL_TIMEOUT;
3655 }
3656 }
3657
3658 /* If Memory address size is 8Bit */
3659 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
3660 {
3661 /* Send Memory Address */
3662 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3663 }
3664 /* If Memory address size is 16Bit */
3665 else
3666 {
3667 /* Send MSB of Memory Address */
3668 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3669
3670 /* Wait until TXIS flag is set */
3671 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3672 {
3673 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3674 {
3675 return HAL_ERROR;
3676 }
3677 else
3678 {
3679 return HAL_TIMEOUT;
3680 }
3681 }
3682
3683 /* Send LSB of Memory Address */
3684 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3685 }
3686
3687 /* Wait until TCR flag is set */
3688 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TCR, RESET, Timeout, Tickstart) != HAL_OK)
3689 {
3690 return HAL_TIMEOUT;
3691 }
3692
3693 return HAL_OK;
3694 }
3695
3696 /**
3697 * @brief Master sends target device address followed by internal memory address for read request.
3698 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
3699 * the configuration information for the specified I2C.
3700 * @param DevAddress Target device address: The device 7 bits address value
3701 * in datasheet must be shift at right before call interface
3702 * @param MemAddress Internal memory address
3703 * @param MemAddSize Size of internal memory address
3704 * @param Timeout Timeout duration
3705 * @param Tickstart Tick start value
3706 * @retval HAL status
3707 */
3708 static HAL_StatusTypeDef I2C_RequestMemoryRead(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint16_t MemAddress, uint16_t MemAddSize, uint32_t Timeout, uint32_t Tickstart)
3709 {
3710 I2C_TransferConfig(hi2c,DevAddress,MemAddSize, I2C_SOFTEND_MODE, I2C_GENERATE_START_WRITE);
3711
3712 /* Wait until TXIS flag is set */
3713 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3714 {
3715 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3716 {
3717 return HAL_ERROR;
3718 }
3719 else
3720 {
3721 return HAL_TIMEOUT;
3722 }
3723 }
3724
3725 /* If Memory address size is 8Bit */
3726 if(MemAddSize == I2C_MEMADD_SIZE_8BIT)
3727 {
3728 /* Send Memory Address */
3729 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3730 }
3731 /* If Memory address size is 16Bit */
3732 else
3733 {
3734 /* Send MSB of Memory Address */
3735 hi2c->Instance->TXDR = I2C_MEM_ADD_MSB(MemAddress);
3736
3737 /* Wait until TXIS flag is set */
3738 if(I2C_WaitOnTXISFlagUntilTimeout(hi2c, Timeout, Tickstart) != HAL_OK)
3739 {
3740 if(hi2c->ErrorCode == HAL_I2C_ERROR_AF)
3741 {
3742 return HAL_ERROR;
3743 }
3744 else
3745 {
3746 return HAL_TIMEOUT;
3747 }
3748 }
3749
3750 /* Send LSB of Memory Address */
3751 hi2c->Instance->TXDR = I2C_MEM_ADD_LSB(MemAddress);
3752 }
3753
3754 /* Wait until TC flag is set */
3755 if(I2C_WaitOnFlagUntilTimeout(hi2c, I2C_FLAG_TC, RESET, Timeout, Tickstart) != HAL_OK)
3756 {
3757 return HAL_TIMEOUT;
3758 }
3759
3760 return HAL_OK;
3761 }
3762
3763 /**
3764 * @brief I2C Address complete process callback.
3765 * @param hi2c I2C handle.
3766 * @param ITFlags Interrupt flags to handle.
3767 * @retval None
3768 */
3769 static void I2C_ITAddrCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
3770 {
3771 uint8_t transferdirection = 0U;
3772 uint16_t slaveaddrcode = 0U;
3773 uint16_t ownadd1code = 0U;
3774 uint16_t ownadd2code = 0U;
3775
3776 /* Prevent unused argument(s) compilation warning */
3777 UNUSED(ITFlags);
3778
3779 /* In case of Listen state, need to inform upper layer of address match code event */
3780 if((hi2c->State & HAL_I2C_STATE_LISTEN) == HAL_I2C_STATE_LISTEN)
3781 {
3782 transferdirection = I2C_GET_DIR(hi2c);
3783 slaveaddrcode = I2C_GET_ADDR_MATCH(hi2c);
3784 ownadd1code = I2C_GET_OWN_ADDRESS1(hi2c);
3785 ownadd2code = I2C_GET_OWN_ADDRESS2(hi2c);
3786
3787 /* If 10bits addressing mode is selected */
3788 if(hi2c->Init.AddressingMode == I2C_ADDRESSINGMODE_10BIT)
3789 {
3790 if((slaveaddrcode & SlaveAddr_MSK) == ((ownadd1code >> SlaveAddr_SHIFT) & SlaveAddr_MSK))
3791 {
3792 slaveaddrcode = ownadd1code;
3793 hi2c->AddrEventCount++;
3794 if(hi2c->AddrEventCount == 2U)
3795 {
3796 /* Reset Address Event counter */
3797 hi2c->AddrEventCount = 0U;
3798
3799 /* Clear ADDR flag */
3800 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
3801
3802 /* Process Unlocked */
3803 __HAL_UNLOCK(hi2c);
3804
3805 /* Call Slave Addr callback */
3806 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3807 }
3808 }
3809 else
3810 {
3811 slaveaddrcode = ownadd2code;
3812
3813 /* Disable ADDR Interrupts */
3814 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
3815
3816 /* Process Unlocked */
3817 __HAL_UNLOCK(hi2c);
3818
3819 /* Call Slave Addr callback */
3820 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3821 }
3822 }
3823 /* else 7 bits addressing mode is selected */
3824 else
3825 {
3826 /* Disable ADDR Interrupts */
3827 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT);
3828
3829 /* Process Unlocked */
3830 __HAL_UNLOCK(hi2c);
3831
3832 /* Call Slave Addr callback */
3833 HAL_I2C_AddrCallback(hi2c, transferdirection, slaveaddrcode);
3834 }
3835 }
3836 /* Else clear address flag only */
3837 else
3838 {
3839 /* Clear ADDR flag */
3840 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_ADDR);
3841
3842 /* Process Unlocked */
3843 __HAL_UNLOCK(hi2c);
3844 }
3845 }
3846
3847 /**
3848 * @brief I2C Master sequential complete process.
3849 * @param hi2c I2C handle.
3850 * @retval None
3851 */
3852 static void I2C_ITMasterSequentialCplt(I2C_HandleTypeDef *hi2c)
3853 {
3854 /* Reset I2C handle mode */
3855 hi2c->Mode = HAL_I2C_MODE_NONE;
3856
3857 /* No Generate Stop, to permit restart mode */
3858 /* The stop will be done at the end of transfer, when I2C_AUTOEND_MODE enable */
3859 if (hi2c->State == HAL_I2C_STATE_BUSY_TX)
3860 {
3861 hi2c->State = HAL_I2C_STATE_READY;
3862 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_TX;
3863 hi2c->XferISR = NULL;
3864
3865 /* Disable Interrupts */
3866 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
3867
3868 /* Process Unlocked */
3869 __HAL_UNLOCK(hi2c);
3870
3871 /* Call the corresponding callback to inform upper layer of End of Transfer */
3872 HAL_I2C_MasterTxCpltCallback(hi2c);
3873 }
3874 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
3875 else
3876 {
3877 hi2c->State = HAL_I2C_STATE_READY;
3878 hi2c->PreviousState = I2C_STATE_MASTER_BUSY_RX;
3879 hi2c->XferISR = NULL;
3880
3881 /* Disable Interrupts */
3882 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3883
3884 /* Process Unlocked */
3885 __HAL_UNLOCK(hi2c);
3886
3887 /* Call the corresponding callback to inform upper layer of End of Transfer */
3888 HAL_I2C_MasterRxCpltCallback(hi2c);
3889 }
3890 }
3891
3892 /**
3893 * @brief I2C Slave sequential complete process.
3894 * @param hi2c I2C handle.
3895 * @retval None
3896 */
3897 static void I2C_ITSlaveSequentialCplt(I2C_HandleTypeDef *hi2c)
3898 {
3899 /* Reset I2C handle mode */
3900 hi2c->Mode = HAL_I2C_MODE_NONE;
3901
3902 if(hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN)
3903 {
3904 /* Remove HAL_I2C_STATE_SLAVE_BUSY_TX, keep only HAL_I2C_STATE_LISTEN */
3905 hi2c->State = HAL_I2C_STATE_LISTEN;
3906 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_TX;
3907
3908 /* Disable Interrupts */
3909 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT);
3910
3911 /* Process Unlocked */
3912 __HAL_UNLOCK(hi2c);
3913
3914 /* Call the Tx complete callback to inform upper layer of the end of transmit process */
3915 HAL_I2C_SlaveTxCpltCallback(hi2c);
3916 }
3917
3918 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN)
3919 {
3920 /* Remove HAL_I2C_STATE_SLAVE_BUSY_RX, keep only HAL_I2C_STATE_LISTEN */
3921 hi2c->State = HAL_I2C_STATE_LISTEN;
3922 hi2c->PreviousState = I2C_STATE_SLAVE_BUSY_RX;
3923
3924 /* Disable Interrupts */
3925 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT);
3926
3927 /* Process Unlocked */
3928 __HAL_UNLOCK(hi2c);
3929
3930 /* Call the Rx complete callback to inform upper layer of the end of receive process */
3931 HAL_I2C_SlaveRxCpltCallback(hi2c);
3932 }
3933 }
3934
3935 /**
3936 * @brief I2C Master complete process.
3937 * @param hi2c I2C handle.
3938 * @param ITFlags Interrupt flags to handle.
3939 * @retval None
3940 */
3941 static void I2C_ITMasterCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
3942 {
3943 /* Clear STOP Flag */
3944 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
3945
3946 /* Clear Configuration Register 2 */
3947 I2C_RESET_CR2(hi2c);
3948
3949 /* Reset handle parameters */
3950 hi2c->PreviousState = I2C_STATE_NONE;
3951 hi2c->XferISR = NULL;
3952 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
3953
3954 if((ITFlags & I2C_FLAG_AF) != RESET)
3955 {
3956 /* Clear NACK Flag */
3957 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
3958
3959 /* Set acknowledge error code */
3960 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
3961 }
3962
3963 /* Flush TX register */
3964 I2C_Flush_TXDR(hi2c);
3965
3966 /* Disable Interrupts */
3967 I2C_Disable_IRQ(hi2c, I2C_XFER_TX_IT| I2C_XFER_RX_IT);
3968
3969 /* Call the corresponding callback to inform upper layer of End of Transfer */
3970 if((hi2c->ErrorCode != HAL_I2C_ERROR_NONE) || (hi2c->State == HAL_I2C_STATE_ABORT))
3971 {
3972 /* Call the corresponding callback to inform upper layer of End of Transfer */
3973 I2C_ITError(hi2c, hi2c->ErrorCode);
3974 }
3975 /* hi2c->State == HAL_I2C_STATE_BUSY_TX */
3976 else if(hi2c->State == HAL_I2C_STATE_BUSY_TX)
3977 {
3978 hi2c->State = HAL_I2C_STATE_READY;
3979
3980 if (hi2c->Mode == HAL_I2C_MODE_MEM)
3981 {
3982 hi2c->Mode = HAL_I2C_MODE_NONE;
3983
3984 /* Process Unlocked */
3985 __HAL_UNLOCK(hi2c);
3986
3987 /* Call the corresponding callback to inform upper layer of End of Transfer */
3988 HAL_I2C_MemTxCpltCallback(hi2c);
3989 }
3990 else
3991 {
3992 hi2c->Mode = HAL_I2C_MODE_NONE;
3993
3994 /* Process Unlocked */
3995 __HAL_UNLOCK(hi2c);
3996
3997 /* Call the corresponding callback to inform upper layer of End of Transfer */
3998 HAL_I2C_MasterTxCpltCallback(hi2c);
3999 }
4000 }
4001 /* hi2c->State == HAL_I2C_STATE_BUSY_RX */
4002 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
4003 {
4004 hi2c->State = HAL_I2C_STATE_READY;
4005
4006 if (hi2c->Mode == HAL_I2C_MODE_MEM)
4007 {
4008 hi2c->Mode = HAL_I2C_MODE_NONE;
4009
4010 /* Process Unlocked */
4011 __HAL_UNLOCK(hi2c);
4012
4013 HAL_I2C_MemRxCpltCallback(hi2c);
4014 }
4015 else
4016 {
4017 hi2c->Mode = HAL_I2C_MODE_NONE;
4018
4019 /* Process Unlocked */
4020 __HAL_UNLOCK(hi2c);
4021
4022 HAL_I2C_MasterRxCpltCallback(hi2c);
4023 }
4024 }
4025 }
4026
4027 /**
4028 * @brief I2C Slave complete process.
4029 * @param hi2c I2C handle.
4030 * @param ITFlags Interrupt flags to handle.
4031 * @retval None
4032 */
4033 static void I2C_ITSlaveCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
4034 {
4035 /* Clear STOP Flag */
4036 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
4037
4038 /* Clear ADDR flag */
4039 __HAL_I2C_CLEAR_FLAG(hi2c,I2C_FLAG_ADDR);
4040
4041 /* Disable all interrupts */
4042 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_TX_IT | I2C_XFER_RX_IT);
4043
4044 /* Disable Address Acknowledge */
4045 hi2c->Instance->CR2 |= I2C_CR2_NACK;
4046
4047 /* Clear Configuration Register 2 */
4048 I2C_RESET_CR2(hi2c);
4049
4050 /* Flush TX register */
4051 I2C_Flush_TXDR(hi2c);
4052
4053 /* If a DMA is ongoing, Update handle size context */
4054 if(((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN) ||
4055 ((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN))
4056 {
4057 hi2c->XferCount = I2C_GET_DMA_REMAIN_DATA(hi2c);
4058 }
4059
4060 /* All data are not transferred, so set error code accordingly */
4061 if(hi2c->XferCount != 0U)
4062 {
4063 /* Set ErrorCode corresponding to a Non-Acknowledge */
4064 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4065 }
4066
4067 /* Store Last receive data if any */
4068 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
4069 {
4070 /* Read data from RXDR */
4071 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
4072
4073 if((hi2c->XferSize > 0U))
4074 {
4075 hi2c->XferSize--;
4076 hi2c->XferCount--;
4077
4078 /* Set ErrorCode corresponding to a Non-Acknowledge */
4079 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4080 }
4081 }
4082
4083 hi2c->PreviousState = I2C_STATE_NONE;
4084 hi2c->Mode = HAL_I2C_MODE_NONE;
4085 hi2c->XferISR = NULL;
4086
4087 if(hi2c->ErrorCode != HAL_I2C_ERROR_NONE)
4088 {
4089 /* Call the corresponding callback to inform upper layer of End of Transfer */
4090 I2C_ITError(hi2c, hi2c->ErrorCode);
4091
4092 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4093 if(hi2c->State == HAL_I2C_STATE_LISTEN)
4094 {
4095 /* Call I2C Listen complete process */
4096 I2C_ITListenCplt(hi2c, ITFlags);
4097 }
4098 }
4099 else if(hi2c->XferOptions != I2C_NO_OPTION_FRAME)
4100 {
4101 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4102 hi2c->State = HAL_I2C_STATE_READY;
4103
4104 /* Process Unlocked */
4105 __HAL_UNLOCK(hi2c);
4106
4107 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4108 HAL_I2C_ListenCpltCallback(hi2c);
4109 }
4110 /* Call the corresponding callback to inform upper layer of End of Transfer */
4111 else if(hi2c->State == HAL_I2C_STATE_BUSY_RX)
4112 {
4113 hi2c->State = HAL_I2C_STATE_READY;
4114
4115 /* Process Unlocked */
4116 __HAL_UNLOCK(hi2c);
4117
4118 /* Call the Slave Rx Complete callback */
4119 HAL_I2C_SlaveRxCpltCallback(hi2c);
4120 }
4121 else
4122 {
4123 hi2c->State = HAL_I2C_STATE_READY;
4124
4125 /* Process Unlocked */
4126 __HAL_UNLOCK(hi2c);
4127
4128 /* Call the Slave Tx Complete callback */
4129 HAL_I2C_SlaveTxCpltCallback(hi2c);
4130 }
4131 }
4132
4133 /**
4134 * @brief I2C Listen complete process.
4135 * @param hi2c I2C handle.
4136 * @param ITFlags Interrupt flags to handle.
4137 * @retval None
4138 */
4139 static void I2C_ITListenCplt(I2C_HandleTypeDef *hi2c, uint32_t ITFlags)
4140 {
4141 /* Reset handle parameters */
4142 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4143 hi2c->PreviousState = I2C_STATE_NONE;
4144 hi2c->State = HAL_I2C_STATE_READY;
4145 hi2c->Mode = HAL_I2C_MODE_NONE;
4146 hi2c->XferISR = NULL;
4147
4148 /* Store Last receive data if any */
4149 if(((ITFlags & I2C_FLAG_RXNE) != RESET))
4150 {
4151 /* Read data from RXDR */
4152 (*hi2c->pBuffPtr++) = hi2c->Instance->RXDR;
4153
4154 if((hi2c->XferSize > 0U))
4155 {
4156 hi2c->XferSize--;
4157 hi2c->XferCount--;
4158
4159 /* Set ErrorCode corresponding to a Non-Acknowledge */
4160 hi2c->ErrorCode |= HAL_I2C_ERROR_AF;
4161 }
4162 }
4163
4164 /* Disable all Interrupts*/
4165 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4166
4167 /* Clear NACK Flag */
4168 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4169
4170 /* Process Unlocked */
4171 __HAL_UNLOCK(hi2c);
4172
4173 /* Call the Listen Complete callback, to inform upper layer of the end of Listen usecase */
4174 HAL_I2C_ListenCpltCallback(hi2c);
4175 }
4176
4177 /**
4178 * @brief I2C interrupts error process.
4179 * @param hi2c I2C handle.
4180 * @param ErrorCode Error code to handle.
4181 * @retval None
4182 */
4183 static void I2C_ITError(I2C_HandleTypeDef *hi2c, uint32_t ErrorCode)
4184 {
4185 /* Reset handle parameters */
4186 hi2c->Mode = HAL_I2C_MODE_NONE;
4187 hi2c->XferOptions = I2C_NO_OPTION_FRAME;
4188 hi2c->XferCount = 0U;
4189
4190 /* Set new error code */
4191 hi2c->ErrorCode |= ErrorCode;
4192
4193 /* Disable Interrupts */
4194 if((hi2c->State == HAL_I2C_STATE_LISTEN) ||
4195 (hi2c->State == HAL_I2C_STATE_BUSY_TX_LISTEN) ||
4196 (hi2c->State == HAL_I2C_STATE_BUSY_RX_LISTEN))
4197 {
4198 /* Disable all interrupts, except interrupts related to LISTEN state */
4199 I2C_Disable_IRQ(hi2c, I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4200
4201 /* keep HAL_I2C_STATE_LISTEN if set */
4202 hi2c->State = HAL_I2C_STATE_LISTEN;
4203 hi2c->PreviousState = I2C_STATE_NONE;
4204 hi2c->XferISR = I2C_Slave_ISR_IT;
4205 }
4206 else
4207 {
4208 /* Disable all interrupts */
4209 I2C_Disable_IRQ(hi2c, I2C_XFER_LISTEN_IT | I2C_XFER_RX_IT | I2C_XFER_TX_IT);
4210
4211 /* If state is an abort treatment on goind, don't change state */
4212 /* This change will be do later */
4213 if(hi2c->State != HAL_I2C_STATE_ABORT)
4214 {
4215 /* Set HAL_I2C_STATE_READY */
4216 hi2c->State = HAL_I2C_STATE_READY;
4217 }
4218 hi2c->PreviousState = I2C_STATE_NONE;
4219 hi2c->XferISR = NULL;
4220 }
4221
4222 /* Abort DMA TX transfer if any */
4223 if((hi2c->Instance->CR1 & I2C_CR1_TXDMAEN) == I2C_CR1_TXDMAEN)
4224 {
4225 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4226
4227 /* Set the I2C DMA Abort callback :
4228 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4229 hi2c->hdmatx->XferAbortCallback = I2C_DMAAbort;
4230
4231 /* Process Unlocked */
4232 __HAL_UNLOCK(hi2c);
4233
4234 /* Abort DMA TX */
4235 if(HAL_DMA_Abort_IT(hi2c->hdmatx) != HAL_OK)
4236 {
4237 /* Call Directly XferAbortCallback function in case of error */
4238 hi2c->hdmatx->XferAbortCallback(hi2c->hdmatx);
4239 }
4240 }
4241 /* Abort DMA RX transfer if any */
4242 else if((hi2c->Instance->CR1 & I2C_CR1_RXDMAEN) == I2C_CR1_RXDMAEN)
4243 {
4244 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4245
4246 /* Set the I2C DMA Abort callback :
4247 will lead to call HAL_I2C_ErrorCallback() at end of DMA abort procedure */
4248 hi2c->hdmarx->XferAbortCallback = I2C_DMAAbort;
4249
4250 /* Process Unlocked */
4251 __HAL_UNLOCK(hi2c);
4252
4253 /* Abort DMA RX */
4254 if(HAL_DMA_Abort_IT(hi2c->hdmarx) != HAL_OK)
4255 {
4256 /* Call Directly hi2c->hdmarx->XferAbortCallback function in case of error */
4257 hi2c->hdmarx->XferAbortCallback(hi2c->hdmarx);
4258 }
4259 }
4260 else if(hi2c->State == HAL_I2C_STATE_ABORT)
4261 {
4262 hi2c->State = HAL_I2C_STATE_READY;
4263
4264 /* Process Unlocked */
4265 __HAL_UNLOCK(hi2c);
4266
4267 /* Call the corresponding callback to inform upper layer of End of Transfer */
4268 HAL_I2C_AbortCpltCallback(hi2c);
4269 }
4270 else
4271 {
4272 /* Process Unlocked */
4273 __HAL_UNLOCK(hi2c);
4274
4275 /* Call the corresponding callback to inform upper layer of End of Transfer */
4276 HAL_I2C_ErrorCallback(hi2c);
4277 }
4278 }
4279
4280 /**
4281 * @brief I2C Tx data register flush process.
4282 * @param hi2c I2C handle.
4283 * @retval None
4284 */
4285 static void I2C_Flush_TXDR(I2C_HandleTypeDef *hi2c)
4286 {
4287 /* If a pending TXIS flag is set */
4288 /* Write a dummy data in TXDR to clear it */
4289 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) != RESET)
4290 {
4291 hi2c->Instance->TXDR = 0x00U;
4292 }
4293
4294 /* Flush TX register if not empty */
4295 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXE) == RESET)
4296 {
4297 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_TXE);
4298 }
4299 }
4300
4301 /**
4302 * @brief DMA I2C master transmit process complete callback.
4303 * @param hdma DMA handle
4304 * @retval None
4305 */
4306 static void I2C_DMAMasterTransmitCplt(DMA_HandleTypeDef *hdma)
4307 {
4308 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
4309
4310 /* Disable DMA Request */
4311 hi2c->Instance->CR1 &= ~I2C_CR1_TXDMAEN;
4312
4313 /* If last transfer, enable STOP interrupt */
4314 if(hi2c->XferCount == 0U)
4315 {
4316 /* Enable STOP interrupt */
4317 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4318 }
4319 /* else prepare a new DMA transfer and enable TCReload interrupt */
4320 else
4321 {
4322 /* Update Buffer pointer */
4323 hi2c->pBuffPtr += hi2c->XferSize;
4324
4325 /* Set the XferSize to transfer */
4326 if(hi2c->XferCount > MAX_NBYTE_SIZE)
4327 {
4328 hi2c->XferSize = MAX_NBYTE_SIZE;
4329 }
4330 else
4331 {
4332 hi2c->XferSize = hi2c->XferCount;
4333 }
4334
4335 /* Enable the DMA channel */
4336 HAL_DMA_Start_IT(hi2c->hdmatx, (uint32_t)hi2c->pBuffPtr, (uint32_t)&hi2c->Instance->TXDR, hi2c->XferSize);
4337
4338 /* Enable TC interrupts */
4339 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
4340 }
4341 }
4342
4343 /**
4344 * @brief DMA I2C slave transmit process complete callback.
4345 * @param hdma DMA handle
4346 * @retval None
4347 */
4348 static void I2C_DMASlaveTransmitCplt(DMA_HandleTypeDef *hdma)
4349 {
4350 /* Prevent unused argument(s) compilation warning */
4351 UNUSED(hdma);
4352
4353 /* No specific action, Master fully manage the generation of STOP condition */
4354 /* Mean that this generation can arrive at any time, at the end or during DMA process */
4355 /* So STOP condition should be manage through Interrupt treatment */
4356 }
4357
4358 /**
4359 * @brief DMA I2C master receive process complete callback.
4360 * @param hdma DMA handle
4361 * @retval None
4362 */
4363 static void I2C_DMAMasterReceiveCplt(DMA_HandleTypeDef *hdma)
4364 {
4365 I2C_HandleTypeDef* hi2c = (I2C_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
4366
4367 /* Disable DMA Request */
4368 hi2c->Instance->CR1 &= ~I2C_CR1_RXDMAEN;
4369
4370 /* If last transfer, enable STOP interrupt */
4371 if(hi2c->XferCount == 0U)
4372 {
4373 /* Enable STOP interrupt */
4374 I2C_Enable_IRQ(hi2c, I2C_XFER_CPLT_IT);
4375 }
4376 /* else prepare a new DMA transfer and enable TCReload interrupt */
4377 else
4378 {
4379 /* Update Buffer pointer */
4380 hi2c->pBuffPtr += hi2c->XferSize;
4381
4382 /* Set the XferSize to transfer */
4383 if(hi2c->XferCount > MAX_NBYTE_SIZE)
4384 {
4385 hi2c->XferSize = MAX_NBYTE_SIZE;
4386 }
4387 else
4388 {
4389 hi2c->XferSize = hi2c->XferCount;
4390 }
4391
4392 /* Enable the DMA channel */
4393 HAL_DMA_Start_IT(hi2c->hdmarx, (uint32_t)&hi2c->Instance->RXDR, (uint32_t)hi2c->pBuffPtr, hi2c->XferSize);
4394
4395 /* Enable TC interrupts */
4396 I2C_Enable_IRQ(hi2c, I2C_XFER_RELOAD_IT);
4397 }
4398 }
4399
4400 /**
4401 * @brief DMA I2C slave receive process complete callback.
4402 * @param hdma DMA handle
4403 * @retval None
4404 */
4405 static void I2C_DMASlaveReceiveCplt(DMA_HandleTypeDef *hdma)
4406 {
4407 /* Prevent unused argument(s) compilation warning */
4408 UNUSED(hdma);
4409
4410 /* No specific action, Master fully manage the generation of STOP condition */
4411 /* Mean that this generation can arrive at any time, at the end or during DMA process */
4412 /* So STOP condition should be manage through Interrupt treatment */
4413 }
4414
4415 /**
4416 * @brief DMA I2C communication error callback.
4417 * @param hdma DMA handle
4418 * @retval None
4419 */
4420 static void I2C_DMAError(DMA_HandleTypeDef *hdma)
4421 {
4422 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4423
4424 /* Disable Acknowledge */
4425 hi2c->Instance->CR2 |= I2C_CR2_NACK;
4426
4427 /* Call the corresponding callback to inform upper layer of End of Transfer */
4428 I2C_ITError(hi2c, HAL_I2C_ERROR_DMA);
4429 }
4430
4431 /**
4432 * @brief DMA I2C communication abort callback
4433 * (To be called at end of DMA Abort procedure).
4434 * @param hdma: DMA handle.
4435 * @retval None
4436 */
4437 static void I2C_DMAAbort(DMA_HandleTypeDef *hdma)
4438 {
4439 I2C_HandleTypeDef* hi2c = ( I2C_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
4440
4441 /* Disable Acknowledge */
4442 hi2c->Instance->CR2 |= I2C_CR2_NACK;
4443
4444 /* Reset AbortCpltCallback */
4445 hi2c->hdmatx->XferAbortCallback = NULL;
4446 hi2c->hdmarx->XferAbortCallback = NULL;
4447
4448 /* Check if come from abort from user */
4449 if(hi2c->State == HAL_I2C_STATE_ABORT)
4450 {
4451 hi2c->State = HAL_I2C_STATE_READY;
4452
4453 /* Call the corresponding callback to inform upper layer of End of Transfer */
4454 HAL_I2C_AbortCpltCallback(hi2c);
4455 }
4456 else
4457 {
4458 /* Call the corresponding callback to inform upper layer of End of Transfer */
4459 HAL_I2C_ErrorCallback(hi2c);
4460 }
4461 }
4462
4463 /**
4464 * @brief This function handles I2C Communication Timeout.
4465 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4466 * the configuration information for the specified I2C.
4467 * @param Flag Specifies the I2C flag to check.
4468 * @param Status The new Flag status (SET or RESET).
4469 * @param Timeout Timeout duration
4470 * @param Tickstart Tick start value
4471 * @retval HAL status
4472 */
4473 static HAL_StatusTypeDef I2C_WaitOnFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Flag, FlagStatus Status, uint32_t Timeout, uint32_t Tickstart)
4474 {
4475 while(__HAL_I2C_GET_FLAG(hi2c, Flag) == Status)
4476 {
4477 /* Check for the Timeout */
4478 if(Timeout != HAL_MAX_DELAY)
4479 {
4480 if((Timeout == 0U)||((HAL_GetTick() - Tickstart ) > Timeout))
4481 {
4482 hi2c->State= HAL_I2C_STATE_READY;
4483 hi2c->Mode = HAL_I2C_MODE_NONE;
4484
4485 /* Process Unlocked */
4486 __HAL_UNLOCK(hi2c);
4487 return HAL_TIMEOUT;
4488 }
4489 }
4490 }
4491 return HAL_OK;
4492 }
4493
4494 /**
4495 * @brief This function handles I2C Communication Timeout for specific usage of TXIS flag.
4496 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4497 * the configuration information for the specified I2C.
4498 * @param Timeout Timeout duration
4499 * @param Tickstart Tick start value
4500 * @retval HAL status
4501 */
4502 static HAL_StatusTypeDef I2C_WaitOnTXISFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4503 {
4504 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_TXIS) == RESET)
4505 {
4506 /* Check if a NACK is detected */
4507 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4508 {
4509 return HAL_ERROR;
4510 }
4511
4512 /* Check for the Timeout */
4513 if(Timeout != HAL_MAX_DELAY)
4514 {
4515 if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
4516 {
4517 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4518 hi2c->State= HAL_I2C_STATE_READY;
4519 hi2c->Mode = HAL_I2C_MODE_NONE;
4520
4521 /* Process Unlocked */
4522 __HAL_UNLOCK(hi2c);
4523
4524 return HAL_TIMEOUT;
4525 }
4526 }
4527 }
4528 return HAL_OK;
4529 }
4530
4531 /**
4532 * @brief This function handles I2C Communication Timeout for specific usage of STOP flag.
4533 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4534 * the configuration information for the specified I2C.
4535 * @param Timeout Timeout duration
4536 * @param Tickstart Tick start value
4537 * @retval HAL status
4538 */
4539 static HAL_StatusTypeDef I2C_WaitOnSTOPFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4540 {
4541 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
4542 {
4543 /* Check if a NACK is detected */
4544 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4545 {
4546 return HAL_ERROR;
4547 }
4548
4549 /* Check for the Timeout */
4550 if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
4551 {
4552 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4553 hi2c->State= HAL_I2C_STATE_READY;
4554 hi2c->Mode = HAL_I2C_MODE_NONE;
4555
4556 /* Process Unlocked */
4557 __HAL_UNLOCK(hi2c);
4558
4559 return HAL_TIMEOUT;
4560 }
4561 }
4562 return HAL_OK;
4563 }
4564
4565 /**
4566 * @brief This function handles I2C Communication Timeout for specific usage of RXNE flag.
4567 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4568 * the configuration information for the specified I2C.
4569 * @param Timeout Timeout duration
4570 * @param Tickstart Tick start value
4571 * @retval HAL status
4572 */
4573 static HAL_StatusTypeDef I2C_WaitOnRXNEFlagUntilTimeout(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4574 {
4575 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_RXNE) == RESET)
4576 {
4577 /* Check if a NACK is detected */
4578 if(I2C_IsAcknowledgeFailed(hi2c, Timeout, Tickstart) != HAL_OK)
4579 {
4580 return HAL_ERROR;
4581 }
4582
4583 /* Check if a STOPF is detected */
4584 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == SET)
4585 {
4586 /* Clear STOP Flag */
4587 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
4588
4589 /* Clear Configuration Register 2 */
4590 I2C_RESET_CR2(hi2c);
4591
4592 hi2c->ErrorCode = HAL_I2C_ERROR_NONE;
4593 hi2c->State= HAL_I2C_STATE_READY;
4594 hi2c->Mode = HAL_I2C_MODE_NONE;
4595
4596 /* Process Unlocked */
4597 __HAL_UNLOCK(hi2c);
4598
4599 return HAL_ERROR;
4600 }
4601
4602 /* Check for the Timeout */
4603 if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
4604 {
4605 hi2c->ErrorCode |= HAL_I2C_ERROR_TIMEOUT;
4606 hi2c->State= HAL_I2C_STATE_READY;
4607
4608 /* Process Unlocked */
4609 __HAL_UNLOCK(hi2c);
4610
4611 return HAL_TIMEOUT;
4612 }
4613 }
4614 return HAL_OK;
4615 }
4616
4617 /**
4618 * @brief This function handles Acknowledge failed detection during an I2C Communication.
4619 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4620 * the configuration information for the specified I2C.
4621 * @param Timeout Timeout duration
4622 * @param Tickstart Tick start value
4623 * @retval HAL status
4624 */
4625 static HAL_StatusTypeDef I2C_IsAcknowledgeFailed(I2C_HandleTypeDef *hi2c, uint32_t Timeout, uint32_t Tickstart)
4626 {
4627 if(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_AF) == SET)
4628 {
4629 /* Wait until STOP Flag is reset */
4630 /* AutoEnd should be initiate after AF */
4631 while(__HAL_I2C_GET_FLAG(hi2c, I2C_FLAG_STOPF) == RESET)
4632 {
4633 /* Check for the Timeout */
4634 if(Timeout != HAL_MAX_DELAY)
4635 {
4636 if((Timeout == 0U)||((HAL_GetTick() - Tickstart) > Timeout))
4637 {
4638 hi2c->State= HAL_I2C_STATE_READY;
4639 hi2c->Mode = HAL_I2C_MODE_NONE;
4640
4641 /* Process Unlocked */
4642 __HAL_UNLOCK(hi2c);
4643 return HAL_TIMEOUT;
4644 }
4645 }
4646 }
4647
4648 /* Clear NACKF Flag */
4649 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_AF);
4650
4651 /* Clear STOP Flag */
4652 __HAL_I2C_CLEAR_FLAG(hi2c, I2C_FLAG_STOPF);
4653
4654 /* Flush TX register */
4655 I2C_Flush_TXDR(hi2c);
4656
4657 /* Clear Configuration Register 2 */
4658 I2C_RESET_CR2(hi2c);
4659
4660 hi2c->ErrorCode = HAL_I2C_ERROR_AF;
4661 hi2c->State= HAL_I2C_STATE_READY;
4662 hi2c->Mode = HAL_I2C_MODE_NONE;
4663
4664 /* Process Unlocked */
4665 __HAL_UNLOCK(hi2c);
4666
4667 return HAL_ERROR;
4668 }
4669 return HAL_OK;
4670 }
4671
4672 /**
4673 * @brief Handles I2Cx communication when starting transfer or during transfer (TC or TCR flag are set).
4674 * @param hi2c I2C handle.
4675 * @param DevAddress Specifies the slave address to be programmed.
4676 * @param Size Specifies the number of bytes to be programmed.
4677 * This parameter must be a value between 0 and 255.
4678 * @param Mode New state of the I2C START condition generation.
4679 * This parameter can be one of the following values:
4680 * @arg @ref I2C_RELOAD_MODE Enable Reload mode .
4681 * @arg @ref I2C_AUTOEND_MODE Enable Automatic end mode.
4682 * @arg @ref I2C_SOFTEND_MODE Enable Software end mode.
4683 * @param Request New state of the I2C START condition generation.
4684 * This parameter can be one of the following values:
4685 * @arg @ref I2C_NO_STARTSTOP Don't Generate stop and start condition.
4686 * @arg @ref I2C_GENERATE_STOP Generate stop condition (Size should be set to 0).
4687 * @arg @ref I2C_GENERATE_START_READ Generate Restart for read request.
4688 * @arg @ref I2C_GENERATE_START_WRITE Generate Restart for write request.
4689 * @retval None
4690 */
4691 static void I2C_TransferConfig(I2C_HandleTypeDef *hi2c, uint16_t DevAddress, uint8_t Size, uint32_t Mode, uint32_t Request)
4692 {
4693 uint32_t tmpreg = 0U;
4694
4695 /* Check the parameters */
4696 assert_param(IS_I2C_ALL_INSTANCE(hi2c->Instance));
4697 assert_param(IS_TRANSFER_MODE(Mode));
4698 assert_param(IS_TRANSFER_REQUEST(Request));
4699
4700 /* Get the CR2 register value */
4701 tmpreg = hi2c->Instance->CR2;
4702
4703 /* clear tmpreg specific bits */
4704 tmpreg &= (uint32_t)~((uint32_t)(I2C_CR2_SADD | I2C_CR2_NBYTES | I2C_CR2_RELOAD | I2C_CR2_AUTOEND | I2C_CR2_RD_WRN | I2C_CR2_START | I2C_CR2_STOP));
4705
4706 /* update tmpreg */
4707 tmpreg |= (uint32_t)(((uint32_t)DevAddress & I2C_CR2_SADD) | (((uint32_t)Size << 16 ) & I2C_CR2_NBYTES) | \
4708 (uint32_t)Mode | (uint32_t)Request);
4709
4710 /* update CR2 register */
4711 hi2c->Instance->CR2 = tmpreg;
4712 }
4713
4714 /**
4715 * @brief Manage the enabling of Interrupts.
4716 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4717 * the configuration information for the specified I2C.
4718 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
4719 * @retval HAL status
4720 */
4721 static HAL_StatusTypeDef I2C_Enable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
4722 {
4723 uint32_t tmpisr = 0U;
4724
4725 if((hi2c->XferISR == I2C_Master_ISR_DMA) || \
4726 (hi2c->XferISR == I2C_Slave_ISR_DMA))
4727 {
4728 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4729 {
4730 /* Enable ERR, STOP, NACK and ADDR interrupts */
4731 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4732 }
4733
4734 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
4735 {
4736 /* Enable ERR and NACK interrupts */
4737 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
4738 }
4739
4740 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4741 {
4742 /* Enable STOP interrupts */
4743 tmpisr |= I2C_IT_STOPI;
4744 }
4745
4746 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
4747 {
4748 /* Enable TC interrupts */
4749 tmpisr |= I2C_IT_TCI;
4750 }
4751 }
4752 else
4753 {
4754 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4755 {
4756 /* Enable ERR, STOP, NACK, and ADDR interrupts */
4757 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4758 }
4759
4760 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
4761 {
4762 /* Enable ERR, TC, STOP, NACK and RXI interrupts */
4763 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_TXI;
4764 }
4765
4766 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
4767 {
4768 /* Enable ERR, TC, STOP, NACK and TXI interrupts */
4769 tmpisr |= I2C_IT_ERRI | I2C_IT_TCI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_RXI;
4770 }
4771
4772 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4773 {
4774 /* Enable STOP interrupts */
4775 tmpisr |= I2C_IT_STOPI;
4776 }
4777 }
4778
4779 /* Enable interrupts only at the end */
4780 /* to avoid the risk of I2C interrupt handle execution before */
4781 /* all interrupts requested done */
4782 __HAL_I2C_ENABLE_IT(hi2c, tmpisr);
4783
4784 return HAL_OK;
4785 }
4786
4787 /**
4788 * @brief Manage the disabling of Interrupts.
4789 * @param hi2c Pointer to a I2C_HandleTypeDef structure that contains
4790 * the configuration information for the specified I2C.
4791 * @param InterruptRequest Value of @ref I2C_Interrupt_configuration_definition.
4792 * @retval HAL status
4793 */
4794 static HAL_StatusTypeDef I2C_Disable_IRQ(I2C_HandleTypeDef *hi2c, uint16_t InterruptRequest)
4795 {
4796 uint32_t tmpisr = 0U;
4797
4798 if((InterruptRequest & I2C_XFER_TX_IT) == I2C_XFER_TX_IT)
4799 {
4800 /* Disable TC and TXI interrupts */
4801 tmpisr |= I2C_IT_TCI | I2C_IT_TXI;
4802
4803 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
4804 {
4805 /* Disable NACK and STOP interrupts */
4806 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4807 }
4808 }
4809
4810 if((InterruptRequest & I2C_XFER_RX_IT) == I2C_XFER_RX_IT)
4811 {
4812 /* Disable TC and RXI interrupts */
4813 tmpisr |= I2C_IT_TCI | I2C_IT_RXI;
4814
4815 if((hi2c->State & HAL_I2C_STATE_LISTEN) != HAL_I2C_STATE_LISTEN)
4816 {
4817 /* Disable NACK and STOP interrupts */
4818 tmpisr |= I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4819 }
4820 }
4821
4822 if((InterruptRequest & I2C_XFER_LISTEN_IT) == I2C_XFER_LISTEN_IT)
4823 {
4824 /* Disable ADDR, NACK and STOP interrupts */
4825 tmpisr |= I2C_IT_ADDRI | I2C_IT_STOPI | I2C_IT_NACKI | I2C_IT_ERRI;
4826 }
4827
4828 if((InterruptRequest & I2C_XFER_ERROR_IT) == I2C_XFER_ERROR_IT)
4829 {
4830 /* Enable ERR and NACK interrupts */
4831 tmpisr |= I2C_IT_ERRI | I2C_IT_NACKI;
4832 }
4833
4834 if((InterruptRequest & I2C_XFER_CPLT_IT) == I2C_XFER_CPLT_IT)
4835 {
4836 /* Enable STOP interrupts */
4837 tmpisr |= I2C_IT_STOPI;
4838 }
4839
4840 if((InterruptRequest & I2C_XFER_RELOAD_IT) == I2C_XFER_RELOAD_IT)
4841 {
4842 /* Enable TC interrupts */
4843 tmpisr |= I2C_IT_TCI;
4844 }
4845
4846 /* Disable interrupts only at the end */
4847 /* to avoid a breaking situation like at "t" time */
4848 /* all disable interrupts request are not done */
4849 __HAL_I2C_DISABLE_IT(hi2c, tmpisr);
4850
4851 return HAL_OK;
4852 }
4853
4854 /**
4855 * @}
4856 */
4857
4858 #endif /* HAL_I2C_MODULE_ENABLED */
4859 /**
4860 * @}
4861 */
4862
4863 /**
4864 * @}
4865 */
4866
4867 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software