lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_qspi.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_qspi.c
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   QSPI HAL module driver.
   8   *          This file provides firmware functions to manage the following
   9   *          functionalities of the QuadSPI interface (QSPI).
  10   *           + Initialization and de-initialization functions
  11   *           + Indirect functional mode management
  12   *           + Memory-mapped functional mode management
  13   *           + Auto-polling functional mode management
  14   *           + Interrupts and flags management
  15   *           + DMA channel configuration for indirect functional mode
  16   *           + Errors management and abort functionality
  17   *
  18   *
  19   @verbatim
  20  ===============================================================================
  21                         ##### How to use this driver #####
  22  ===============================================================================
  23   [..]
  24     *** Initialization ***
  25     ======================
  26     [..]
  27       (#) As prerequisite, fill in the HAL_QSPI_MspInit() :
  28         (++) Enable QuadSPI clock interface with __HAL_RCC_QSPI_CLK_ENABLE().
  29         (++) Reset QuadSPI IP with __HAL_RCC_QSPI_FORCE_RESET() and __HAL_RCC_QSPI_RELEASE_RESET().
  30         (++) Enable the clocks for the QuadSPI GPIOS with __HAL_RCC_GPIOx_CLK_ENABLE().
  31         (++) Configure these QuadSPI pins in alternate mode using HAL_GPIO_Init().
  32         (++) If interrupt mode is used, enable and configure QuadSPI global
  33             interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  34         (++) If DMA mode is used, enable the clocks for the QuadSPI DMA channel
  35             with __HAL_RCC_DMAx_CLK_ENABLE(), configure DMA with HAL_DMA_Init(),
  36             link it with QuadSPI handle using __HAL_LINKDMA(), enable and configure
  37             DMA channel global interrupt with HAL_NVIC_SetPriority() and HAL_NVIC_EnableIRQ().
  38       (#) Configure the flash size, the clock prescaler, the fifo threshold, the
  39           clock mode, the sample shifting and the CS high time using the HAL_QSPI_Init() function.
  40
  41     *** Indirect functional mode ***
  42     ================================
  43     [..]
  44       (#) Configure the command sequence using the HAL_QSPI_Command() or HAL_QSPI_Command_IT()
  45           functions :
  46          (++) Instruction phase : the mode used and if present the instruction opcode.
  47          (++) Address phase : the mode used and if present the size and the address value.
  48          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  49              bytes values.
  50          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  51          (++) Data phase : the mode used and if present the number of bytes.
  52          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  53              if activated.
  54          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  55       (#) If no data is required for the command, it is sent directly to the memory :
  56          (++) In polling mode, the output of the function is done when the transfer is complete.
  57          (++) In interrupt mode, HAL_QSPI_CmdCpltCallback() will be called when the transfer is complete.
  58       (#) For the indirect write mode, use HAL_QSPI_Transmit(), HAL_QSPI_Transmit_DMA() or
  59           HAL_QSPI_Transmit_IT() after the command configuration :
  60          (++) In polling mode, the output of the function is done when the transfer is complete.
  61          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  62              is reached and HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  63          (++) In DMA mode, HAL_QSPI_TxHalfCpltCallback() will be called at the half transfer and
  64              HAL_QSPI_TxCpltCallback() will be called when the transfer is complete.
  65       (#) For the indirect read mode, use HAL_QSPI_Receive(), HAL_QSPI_Receive_DMA() or
  66           HAL_QSPI_Receive_IT() after the command configuration :
  67          (++) In polling mode, the output of the function is done when the transfer is complete.
  68          (++) In interrupt mode, HAL_QSPI_FifoThresholdCallback() will be called when the fifo threshold
  69              is reached and HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  70          (++) In DMA mode, HAL_QSPI_RxHalfCpltCallback() will be called at the half transfer and
  71              HAL_QSPI_RxCpltCallback() will be called when the transfer is complete.
  72
  73     *** Auto-polling functional mode ***
  74     ====================================
  75     [..]
  76       (#) Configure the command sequence and the auto-polling functional mode using the
  77           HAL_QSPI_AutoPolling() or HAL_QSPI_AutoPolling_IT() functions :
  78          (++) Instruction phase : the mode used and if present the instruction opcode.
  79          (++) Address phase : the mode used and if present the size and the address value.
  80          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
  81              bytes values.
  82          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
  83          (++) Data phase : the mode used.
  84          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
  85              if activated.
  86          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
  87          (++) The size of the status bytes, the match value, the mask used, the match mode (OR/AND),
  88              the polling interval and the automatic stop activation.
  89       (#) After the configuration :
  90          (++) In polling mode, the output of the function is done when the status match is reached. The
  91              automatic stop is activated to avoid an infinite loop.
  92          (++) In interrupt mode, HAL_QSPI_StatusMatchCallback() will be called each time the status match is reached.
  93
  94     *** Memory-mapped functional mode ***
  95     =====================================
  96     [..]
  97       (#) Configure the command sequence and the memory-mapped functional mode using the
  98           HAL_QSPI_MemoryMapped() functions :
  99          (++) Instruction phase : the mode used and if present the instruction opcode.
 100          (++) Address phase : the mode used and the size.
 101          (++) Alternate-bytes phase : the mode used and if present the size and the alternate
 102              bytes values.
 103          (++) Dummy-cycles phase : the number of dummy cycles (mode used is same as data phase).
 104          (++) Data phase : the mode used.
 105          (++) Double Data Rate (DDR) mode : the activation (or not) of this mode and the delay
 106              if activated.
 107          (++) Sending Instruction Only Once (SIOO) mode : the activation (or not) of this mode.
 108          (++) The timeout activation and the timeout period.
 109       (#) After the configuration, the QuadSPI will be used as soon as an access on the AHB is done on
 110           the address range. HAL_QSPI_TimeOutCallback() will be called when the timeout expires.
 111
 112     *** Errors management and abort functionality ***
 113     ==================================================
 114     [..]
 115       (#) HAL_QSPI_GetError() function gives the error raised during the last operation.
 116       (#) HAL_QSPI_Abort() and HAL_QSPI_AbortIT() functions aborts any on-going operation and
 117           flushes the fifo :
 118          (++) In polling mode, the output of the function is done when the transfer
 119               complete bit is set and the busy bit cleared.
 120          (++) In interrupt mode, HAL_QSPI_AbortCpltCallback() will be called when
 121               the transfer complete bi is set.
 122
 123     *** Control functions ***
 124     =========================
 125     [..]
 126       (#) HAL_QSPI_GetState() function gives the current state of the HAL QuadSPI driver.
 127       (#) HAL_QSPI_SetTimeout() function configures the timeout value used in the driver.
 128       (#) HAL_QSPI_SetFifoThreshold() function configures the threshold on the Fifo of the QSPI IP.
 129       (#) HAL_QSPI_GetFifoThreshold() function gives the current of the Fifo's threshold
 130
 131     *** Workarounds linked to Silicon Limitation ***
 132     ====================================================
 133     [..]
 134       (#) Workarounds Implemented inside HAL Driver
 135          (++) Extra data written in the FIFO at the end of a read transfer
 136
 137   @endverbatim
 138   ******************************************************************************
 139   * @attention
 140   *
 141   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
 142   *
 143   * Redistribution and use in source and binary forms, with or without modification,
 144   * are permitted provided that the following conditions are met:
 145   *   1. Redistributions of source code must retain the above copyright notice,
 146   *      this list of conditions and the following disclaimer.
 147   *   2. Redistributions in binary form must reproduce the above copyright notice,
 148   *      this list of conditions and the following disclaimer in the documentation
 149   *      and/or other materials provided with the distribution.
 150   *   3. Neither the name of STMicroelectronics nor the names of its contributors
 151   *      may be used to endorse or promote products derived from this software
 152   *      without specific prior written permission.
 153   *
 154   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
 155   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
 156   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
 157   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
 158   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
 159   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
 160   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
 161   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
 162   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
 163   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
 164   *
 165   ******************************************************************************
 166   */
 167
 168 /* Includes ------------------------------------------------------------------*/
 169 #include "stm32f7xx_hal.h"
 170
 171 /** @addtogroup STM32F7xx_HAL_Driver
 172   * @{
 173   */
 174
 175 /** @defgroup QSPI QSPI
 176   * @brief HAL QSPI module driver
 177   * @{
 178   */
 179 #ifdef HAL_QSPI_MODULE_ENABLED
 180
 181 /* Private typedef -----------------------------------------------------------*/
 182 /* Private define ------------------------------------------------------------*/
 183 /** @addtogroup QSPI_Private_Constants
 184   * @{
 185   */
 186 #define QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE ((uint32_t)0x00000000U)          /*!<Indirect write mode*/
 187 #define QSPI_FUNCTIONAL_MODE_INDIRECT_READ  ((uint32_t)QUADSPI_CCR_FMODE_0) /*!<Indirect read mode*/
 188 #define QSPI_FUNCTIONAL_MODE_AUTO_POLLING   ((uint32_t)QUADSPI_CCR_FMODE_1) /*!<Automatic polling mode*/
 189 #define QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED  ((uint32_t)QUADSPI_CCR_FMODE)   /*!<Memory-mapped mode*/
 190 /**
 191   * @}
 192   */
 193
 194 /* Private macro -------------------------------------------------------------*/
 195 /** @addtogroup QSPI_Private_Macros QSPI Private Macros
 196   * @{
 197   */
 198 #define IS_QSPI_FUNCTIONAL_MODE(MODE) (((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE) || \
 199                                        ((MODE) == QSPI_FUNCTIONAL_MODE_INDIRECT_READ)  || \
 200                                        ((MODE) == QSPI_FUNCTIONAL_MODE_AUTO_POLLING)   || \
 201                                        ((MODE) == QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
 202 /**
 203   * @}
 204   */
 205
 206 /* Private variables ---------------------------------------------------------*/
 207 /* Private function prototypes -----------------------------------------------*/
 208 /** @addtogroup QSPI_Private_Functions QSPI Private Functions
 209   * @{
 210   */
 211 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma);
 212 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma);
 213 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma);
 214 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma);
 215 static void QSPI_DMAError(DMA_HandleTypeDef *hdma);
 216 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma);
 217 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag, FlagStatus State, uint32_t tickstart, uint32_t Timeout);
 218 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode);
 219 /**
 220   * @}
 221   */
 222
 223 /* Exported functions ---------------------------------------------------------*/
 224
 225 /** @defgroup QSPI_Exported_Functions QSPI Exported Functions
 226   * @{
 227   */
 228
 229 /** @defgroup QSPI_Exported_Functions_Group1 Initialization/de-initialization functions
 230   *  @brief    Initialization and Configuration functions
 231   *
 232 @verbatim
 233 ===============================================================================
 234             ##### Initialization and Configuration functions #####
 235  ===============================================================================
 236     [..]
 237     This subsection provides a set of functions allowing to :
 238       (+) Initialize the QuadSPI.
 239       (+) De-initialize the QuadSPI.
 240
 241 @endverbatim
 242   * @{
 243   */
 244
 245 /**
 246   * @brief Initializes the QSPI mode according to the specified parameters
 247   *        in the QSPI_InitTypeDef and creates the associated handle.
 248   * @param hqspi: qspi handle
 249   * @retval HAL status
 250   */
 251 HAL_StatusTypeDef HAL_QSPI_Init(QSPI_HandleTypeDef *hqspi)
 252 {
 253   HAL_StatusTypeDef status = HAL_ERROR;
 254   uint32_t tickstart = HAL_GetTick();
 255
 256   /* Check the QSPI handle allocation */
 257   if(hqspi == NULL)
 258   {
 259     return HAL_ERROR;
 260   }
 261
 262   /* Check the parameters */
 263   assert_param(IS_QSPI_ALL_INSTANCE(hqspi->Instance));
 264   assert_param(IS_QSPI_CLOCK_PRESCALER(hqspi->Init.ClockPrescaler));
 265   assert_param(IS_QSPI_FIFO_THRESHOLD(hqspi->Init.FifoThreshold));
 266   assert_param(IS_QSPI_SSHIFT(hqspi->Init.SampleShifting));
 267   assert_param(IS_QSPI_FLASH_SIZE(hqspi->Init.FlashSize));
 268   assert_param(IS_QSPI_CS_HIGH_TIME(hqspi->Init.ChipSelectHighTime));
 269   assert_param(IS_QSPI_CLOCK_MODE(hqspi->Init.ClockMode));
 270   assert_param(IS_QSPI_DUAL_FLASH_MODE(hqspi->Init.DualFlash));
 271
 272   if (hqspi->Init.DualFlash != QSPI_DUALFLASH_ENABLE )
 273   {
 274     assert_param(IS_QSPI_FLASH_ID(hqspi->Init.FlashID));
 275   }
 276
 277   /* Process locked */
 278   __HAL_LOCK(hqspi);
 279
 280   if(hqspi->State == HAL_QSPI_STATE_RESET)
 281   {
 282     /* Allocate lock resource and initialize it */
 283     hqspi->Lock = HAL_UNLOCKED;
 284
 285     /* Init the low level hardware : GPIO, CLOCK */
 286     HAL_QSPI_MspInit(hqspi);
 287
 288     /* Configure the default timeout for the QSPI memory access */
 289     HAL_QSPI_SetTimeout(hqspi, HAL_QPSI_TIMEOUT_DEFAULT_VALUE);
 290   }
 291
 292   /* Configure QSPI FIFO Threshold */
 293   MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES, ((hqspi->Init.FifoThreshold - 1) << 8));
 294
 295   /* Wait till BUSY flag reset */
 296   status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
 297
 298   if(status == HAL_OK)
 299   {
 300
 301     /* Configure QSPI Clock Prescaler and Sample Shift */
 302     MODIFY_REG(hqspi->Instance->CR,(QUADSPI_CR_PRESCALER | QUADSPI_CR_SSHIFT | QUADSPI_CR_FSEL | QUADSPI_CR_DFM), ((hqspi->Init.ClockPrescaler << 24)| hqspi->Init.SampleShifting | hqspi->Init.FlashID| hqspi->Init.DualFlash ));
 303
 304     /* Configure QSPI Flash Size, CS High Time and Clock Mode */
 305     MODIFY_REG(hqspi->Instance->DCR, (QUADSPI_DCR_FSIZE | QUADSPI_DCR_CSHT | QUADSPI_DCR_CKMODE),
 306                ((hqspi->Init.FlashSize << 16) | hqspi->Init.ChipSelectHighTime | hqspi->Init.ClockMode));
 307
 308     /* Enable the QSPI peripheral */
 309     __HAL_QSPI_ENABLE(hqspi);
 310
 311     /* Set QSPI error code to none */
 312     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 313
 314     /* Initialize the QSPI state */
 315     hqspi->State = HAL_QSPI_STATE_READY;
 316   }
 317
 318   /* Release Lock */
 319   __HAL_UNLOCK(hqspi);
 320
 321   /* Return function status */
 322   return status;
 323 }
 324
 325 /**
 326   * @brief DeInitializes the QSPI peripheral
 327   * @param hqspi: qspi handle
 328   * @retval HAL status
 329   */
 330 HAL_StatusTypeDef HAL_QSPI_DeInit(QSPI_HandleTypeDef *hqspi)
 331 {
 332   /* Check the QSPI handle allocation */
 333   if(hqspi == NULL)
 334   {
 335     return HAL_ERROR;
 336   }
 337
 338   /* Process locked */
 339   __HAL_LOCK(hqspi);
 340
 341   /* Disable the QSPI Peripheral Clock */
 342   __HAL_QSPI_DISABLE(hqspi);
 343
 344   /* DeInit the low level hardware: GPIO, CLOCK, NVIC... */
 345   HAL_QSPI_MspDeInit(hqspi);
 346
 347   /* Set QSPI error code to none */
 348   hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 349
 350   /* Initialize the QSPI state */
 351   hqspi->State = HAL_QSPI_STATE_RESET;
 352
 353   /* Release Lock */
 354   __HAL_UNLOCK(hqspi);
 355
 356   return HAL_OK;
 357 }
 358
 359 /**
 360   * @brief QSPI MSP Init
 361   * @param hqspi: QSPI handle
 362   * @retval None
 363   */
 364  __weak void HAL_QSPI_MspInit(QSPI_HandleTypeDef *hqspi)
 365 {
 366   /* Prevent unused argument(s) compilation warning */
 367   UNUSED(hqspi);
 368
 369   /* NOTE : This function should not be modified, when the callback is needed,
 370             the HAL_QSPI_MspInit can be implemented in the user file
 371    */
 372 }
 373
 374 /**
 375   * @brief QSPI MSP DeInit
 376   * @param hqspi: QSPI handle
 377   * @retval None
 378   */
 379  __weak void HAL_QSPI_MspDeInit(QSPI_HandleTypeDef *hqspi)
 380 {
 381   /* Prevent unused argument(s) compilation warning */
 382   UNUSED(hqspi);
 383
 384   /* NOTE : This function should not be modified, when the callback is needed,
 385             the HAL_QSPI_MspDeInit can be implemented in the user file
 386    */
 387 }
 388
 389 /**
 390   * @}
 391   */
 392
 393 /** @defgroup QSPI_Exported_Functions_Group2 IO operation functions
 394   *  @brief QSPI Transmit/Receive functions
 395   *
 396 @verbatim
 397  ===============================================================================
 398                       ##### IO operation functions #####
 399  ===============================================================================
 400        [..]
 401     This subsection provides a set of functions allowing to :
 402       (+) Handle the interrupts.
 403       (+) Handle the command sequence.
 404       (+) Transmit data in blocking, interrupt or DMA mode.
 405       (+) Receive data in blocking, interrupt or DMA mode.
 406       (+) Manage the auto-polling functional mode.
 407       (+) Manage the memory-mapped functional mode.
 408
 409 @endverbatim
 410   * @{
 411   */
 412
 413 /**
 414   * @brief This function handles QSPI interrupt request.
 415   * @param hqspi: QSPI handle
 416   * @retval None.
 417   */
 418 void HAL_QSPI_IRQHandler(QSPI_HandleTypeDef *hqspi)
 419 {
 420   __IO uint32_t *data_reg;
 421   uint32_t flag = READ_REG(hqspi->Instance->SR);
 422   uint32_t itsource = READ_REG(hqspi->Instance->CR);
 423
 424   /* QSPI Fifo Threshold interrupt occurred ----------------------------------*/
 425   if(((flag & QSPI_FLAG_FT)!= RESET) && ((itsource & QSPI_IT_FT)!= RESET))
 426   {
 427     data_reg = &hqspi->Instance->DR;
 428
 429     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
 430     {
 431       /* Transmission process */
 432       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
 433       {
 434         if (hqspi->TxXferCount > 0)
 435         {
 436           /* Fill the FIFO until it is full */
 437           *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
 438           hqspi->TxXferCount--;
 439         }
 440         else
 441         {
 442           /* No more data available for the transfer */
 443           /* Disable the QSPI FIFO Threshold Interrupt */
 444           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
 445           break;
 446         }
 447       }
 448     }
 449     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
 450     {
 451       /* Receiving Process */
 452       while(__HAL_QSPI_GET_FLAG(hqspi, QSPI_FLAG_FT) != 0)
 453       {
 454         if (hqspi->RxXferCount > 0)
 455         {
 456           /* Read the FIFO until it is empty */
 457           *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
 458           hqspi->RxXferCount--;
 459         }
 460         else
 461         {
 462           /* All data have been received for the transfer */
 463           /* Disable the QSPI FIFO Threshold Interrupt */
 464           __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_FT);
 465           break;
 466         }
 467       }
 468     }
 469
 470     /* FIFO Threshold callback */
 471     HAL_QSPI_FifoThresholdCallback(hqspi);
 472   }
 473
 474   /* QSPI Transfer Complete interrupt occurred -------------------------------*/
 475   else if(((flag & QSPI_FLAG_TC)!= RESET) && ((itsource & QSPI_IT_TC)!= RESET))
 476   {
 477     /* Clear interrupt */
 478     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TC);
 479
 480     /* Disable the QSPI FIFO Threshold, Transfer Error and Transfer complete Interrupts */
 481     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
 482
 483     /* Transfer complete callback */
 484     if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_TX)
 485     {
 486       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
 487       {
 488         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
 489         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
 490
 491         /* Disable the DMA channel */
 492         __HAL_DMA_DISABLE(hqspi->hdma);
 493       }
 494
 495 #if defined(QSPI1_V1_0)
 496 /* Clear Busy bit */
 497       HAL_QSPI_Abort_IT(hqspi);
 498 #endif
 499
 500       /* Change state of QSPI */
 501       hqspi->State = HAL_QSPI_STATE_READY;
 502
 503       /* TX Complete callback */
 504       HAL_QSPI_TxCpltCallback(hqspi);
 505     }
 506     else if(hqspi->State == HAL_QSPI_STATE_BUSY_INDIRECT_RX)
 507     {
 508       if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
 509       {
 510         /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
 511         CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
 512
 513         /* Disable the DMA channel */
 514         __HAL_DMA_DISABLE(hqspi->hdma);
 515       }
 516       else
 517       {
 518         data_reg = &hqspi->Instance->DR;
 519         while(READ_BIT(hqspi->Instance->SR, QUADSPI_SR_FLEVEL) != 0)
 520         {
 521           if (hqspi->RxXferCount > 0)
 522           {
 523             /* Read the last data received in the FIFO until it is empty */
 524             *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
 525             hqspi->RxXferCount--;
 526           }
 527           else
 528           {
 529             /* All data have been received for the transfer */
 530             break;
 531           }
 532         }
 533       }
 534 #if defined(QSPI1_V1_0)
 535       /* Workaround - Extra data written in the FIFO at the end of a read transfer */
 536       HAL_QSPI_Abort_IT(hqspi);
 537 #endif /* QSPI_V1_0*/
 538
 539       /* Change state of QSPI */
 540       hqspi->State = HAL_QSPI_STATE_READY;
 541
 542       /* RX Complete callback */
 543       HAL_QSPI_RxCpltCallback(hqspi);
 544     }
 545     else if(hqspi->State == HAL_QSPI_STATE_BUSY)
 546     {
 547       /* Change state of QSPI */
 548       hqspi->State = HAL_QSPI_STATE_READY;
 549
 550       /* Command Complete callback */
 551       HAL_QSPI_CmdCpltCallback(hqspi);
 552     }
 553     else if(hqspi->State == HAL_QSPI_STATE_ABORT)
 554     {
 555       /* Change state of QSPI */
 556       hqspi->State = HAL_QSPI_STATE_READY;
 557
 558       if (hqspi->ErrorCode == HAL_QSPI_ERROR_NONE)
 559       {
 560         /* Abort called by the user */
 561
 562         /* Abort Complete callback */
 563         HAL_QSPI_AbortCpltCallback(hqspi);
 564       }
 565       else
 566       {
 567         /* Abort due to an error (eg :  DMA error) */
 568
 569         /* Error callback */
 570         HAL_QSPI_ErrorCallback(hqspi);
 571       }
 572     }
 573   }
 574
 575   /* QSPI Status Match interrupt occurred ------------------------------------*/
 576   else if(((flag & QSPI_FLAG_SM)!= RESET) && ((itsource & QSPI_IT_SM)!= RESET))
 577   {
 578     /* Clear interrupt */
 579     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_SM);
 580
 581     /* Check if the automatic poll mode stop is activated */
 582     if(READ_BIT(hqspi->Instance->CR, QUADSPI_CR_APMS) != 0)
 583     {
 584       /* Disable the QSPI Transfer Error and Status Match Interrupts */
 585       __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
 586
 587       /* Change state of QSPI */
 588       hqspi->State = HAL_QSPI_STATE_READY;
 589     }
 590
 591     /* Status match callback */
 592     HAL_QSPI_StatusMatchCallback(hqspi);
 593   }
 594
 595   /* QSPI Transfer Error interrupt occurred ----------------------------------*/
 596   else if(((flag & QSPI_FLAG_TE)!= RESET) && ((itsource & QSPI_IT_TE)!= RESET))
 597   {
 598     /* Clear interrupt */
 599     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TE);
 600
 601     /* Disable all the QSPI Interrupts */
 602     __HAL_QSPI_DISABLE_IT(hqspi, QSPI_IT_SM | QSPI_IT_TC | QSPI_IT_TE | QSPI_IT_FT);
 603
 604     /* Set error code */
 605     hqspi->ErrorCode |= HAL_QSPI_ERROR_TRANSFER;
 606
 607     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
 608     {
 609       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
 610       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
 611
 612       /* Disable the DMA channel */
 613       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
 614       HAL_DMA_Abort_IT(hqspi->hdma);
 615     }
 616     else
 617     {
 618       /* Change state of QSPI */
 619       hqspi->State = HAL_QSPI_STATE_READY;
 620
 621       /* Error callback */
 622       HAL_QSPI_ErrorCallback(hqspi);
 623     }
 624   }
 625
 626   /* QSPI Timeout interrupt occurred -----------------------------------------*/
 627   else if(((flag & QSPI_FLAG_TO)!= RESET) && ((itsource & QSPI_IT_TO)!= RESET))
 628   {
 629     /* Clear interrupt */
 630     WRITE_REG(hqspi->Instance->FCR, QSPI_FLAG_TO);
 631
 632     /* Time out callback */
 633     HAL_QSPI_TimeOutCallback(hqspi);
 634   }
 635 }
 636
 637 /**
 638   * @brief Sets the command configuration.
 639   * @param hqspi: QSPI handle
 640   * @param cmd : structure that contains the command configuration information
 641   * @param Timeout : Time out duration
 642   * @note   This function is used only in Indirect Read or Write Modes
 643   * @retval HAL status
 644   */
 645 HAL_StatusTypeDef HAL_QSPI_Command(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t Timeout)
 646 {
 647   HAL_StatusTypeDef status = HAL_ERROR;
 648   uint32_t tickstart = HAL_GetTick();
 649
 650   /* Check the parameters */
 651   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
 652   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
 653   {
 654     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
 655   }
 656
 657   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
 658   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
 659   {
 660     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
 661   }
 662
 663   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
 664   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
 665   {
 666     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
 667   }
 668
 669   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
 670   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
 671
 672   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
 673   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
 674   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
 675
 676   /* Process locked */
 677   __HAL_LOCK(hqspi);
 678
 679   if(hqspi->State == HAL_QSPI_STATE_READY)
 680   {
 681     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 682
 683     /* Update QSPI state */
 684     hqspi->State = HAL_QSPI_STATE_BUSY;
 685
 686     /* Wait till BUSY flag reset */
 687     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
 688
 689     if (status == HAL_OK)
 690     {
 691       /* Call the configuration function */
 692       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
 693
 694       if (cmd->DataMode == QSPI_DATA_NONE)
 695       {
 696         /* When there is no data phase, the transfer start as soon as the configuration is done
 697         so wait until TC flag is set to go back in idle state */
 698         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
 699
 700         if (status == HAL_OK)
 701         {
 702           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
 703
 704           /* Update QSPI state */
 705           hqspi->State = HAL_QSPI_STATE_READY;
 706         }
 707
 708       }
 709       else
 710       {
 711         /* Update QSPI state */
 712         hqspi->State = HAL_QSPI_STATE_READY;
 713       }
 714     }
 715   }
 716   else
 717   {
 718     status = HAL_BUSY;
 719   }
 720
 721   /* Process unlocked */
 722   __HAL_UNLOCK(hqspi);
 723
 724   /* Return function status */
 725   return status;
 726 }
 727
 728 /**
 729   * @brief Sets the command configuration in interrupt mode.
 730   * @param hqspi: QSPI handle
 731   * @param cmd : structure that contains the command configuration information
 732   * @note   This function is used only in Indirect Read or Write Modes
 733   * @retval HAL status
 734   */
 735 HAL_StatusTypeDef HAL_QSPI_Command_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd)
 736 {
 737   HAL_StatusTypeDef status = HAL_ERROR;
 738   uint32_t tickstart = HAL_GetTick();
 739
 740   /* Check the parameters */
 741   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
 742   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
 743   {
 744     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
 745   }
 746
 747   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
 748   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
 749   {
 750     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
 751   }
 752
 753   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
 754   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
 755   {
 756     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
 757   }
 758
 759   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
 760   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
 761
 762   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
 763   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
 764   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
 765
 766   /* Process locked */
 767   __HAL_LOCK(hqspi);
 768
 769   if(hqspi->State == HAL_QSPI_STATE_READY)
 770   {
 771     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 772
 773     /* Update QSPI state */
 774     hqspi->State = HAL_QSPI_STATE_BUSY;
 775
 776     /* Wait till BUSY flag reset */
 777     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
 778
 779     if (status == HAL_OK)
 780     {
 781       if (cmd->DataMode == QSPI_DATA_NONE)
 782       {
 783         /* Clear interrupt */
 784         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
 785       }
 786
 787       /* Call the configuration function */
 788       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
 789
 790       if (cmd->DataMode == QSPI_DATA_NONE)
 791       {
 792         /* When there is no data phase, the transfer start as soon as the configuration is done
 793         so activate TC and TE interrupts */
 794         /* Process unlocked */
 795         __HAL_UNLOCK(hqspi);
 796
 797         /* Enable the QSPI Transfer Error Interrupt */
 798         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_TC);
 799       }
 800       else
 801       {
 802         /* Update QSPI state */
 803         hqspi->State = HAL_QSPI_STATE_READY;
 804
 805         /* Process unlocked */
 806         __HAL_UNLOCK(hqspi);
 807       }
 808     }
 809     else
 810     {
 811       /* Process unlocked */
 812       __HAL_UNLOCK(hqspi);
 813     }
 814   }
 815   else
 816   {
 817     status = HAL_BUSY;
 818
 819     /* Process unlocked */
 820     __HAL_UNLOCK(hqspi);
 821   }
 822
 823   /* Return function status */
 824   return status;
 825 }
 826
 827 /**
 828   * @brief Transmit an amount of data in blocking mode.
 829   * @param hqspi: QSPI handle
 830   * @param pData: pointer to data buffer
 831   * @param Timeout : Time out duration
 832   * @note   This function is used only in Indirect Write Mode
 833   * @retval HAL status
 834   */
 835 HAL_StatusTypeDef HAL_QSPI_Transmit(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
 836 {
 837    HAL_StatusTypeDef status = HAL_OK;
 838   uint32_t tickstart = HAL_GetTick();
 839   __IO uint32_t *data_reg = &hqspi->Instance->DR;
 840
 841   /* Process locked */
 842   __HAL_LOCK(hqspi);
 843
 844   if(hqspi->State == HAL_QSPI_STATE_READY)
 845   {
 846     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 847
 848     if(pData != NULL )
 849     {
 850       /* Update state */
 851       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
 852
 853       /* Configure counters and size of the handle */
 854       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
 855       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
 856       hqspi->pTxBuffPtr = pData;
 857
 858       /* Configure QSPI: CCR register with functional as indirect write */
 859       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
 860
 861       while(hqspi->TxXferCount > 0)
 862       {
 863         /* Wait until FT flag is set to send data */
 864         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_FT, SET, tickstart, Timeout);
 865
 866         if (status != HAL_OK)
 867         {
 868           break;
 869         }
 870
 871         *(__IO uint8_t *)data_reg = *hqspi->pTxBuffPtr++;
 872         hqspi->TxXferCount--;
 873       }
 874
 875       if (status == HAL_OK)
 876       {
 877         /* Wait until TC flag is set to go back in idle state */
 878         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
 879
 880         if (status == HAL_OK)
 881         {
 882           /* Clear Transfer Complete bit */
 883           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
 884
 885 #if defined(QSPI1_V1_0)
 886           /* Clear Busy bit */
 887           status = HAL_QSPI_Abort(hqspi);
 888 #endif /* QSPI_V1_0 */
 889         }
 890       }
 891
 892       /* Update QSPI state */
 893       hqspi->State = HAL_QSPI_STATE_READY;
 894     }
 895     else
 896     {
 897       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
 898       status = HAL_ERROR;
 899     }
 900   }
 901   else
 902   {
 903     status = HAL_BUSY;
 904   }
 905
 906   /* Process unlocked */
 907   __HAL_UNLOCK(hqspi);
 908
 909   return status;
 910 }
 911
 912
 913 /**
 914   * @brief Receive an amount of data in blocking mode
 915   * @param hqspi: QSPI handle
 916   * @param pData: pointer to data buffer
 917   * @param Timeout : Time out duration
 918   * @note   This function is used only in Indirect Read Mode
 919   * @retval HAL status
 920   */
 921 HAL_StatusTypeDef HAL_QSPI_Receive(QSPI_HandleTypeDef *hqspi, uint8_t *pData, uint32_t Timeout)
 922 {
 923   HAL_StatusTypeDef status = HAL_OK;
 924   uint32_t tickstart = HAL_GetTick();
 925   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
 926   __IO uint32_t *data_reg = &hqspi->Instance->DR;
 927
 928   /* Process locked */
 929   __HAL_LOCK(hqspi);
 930
 931   if(hqspi->State == HAL_QSPI_STATE_READY)
 932   {
 933     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
 934     if(pData != NULL )
 935     {
 936       /* Update state */
 937       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
 938
 939       /* Configure counters and size of the handle */
 940       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
 941       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
 942       hqspi->pRxBuffPtr = pData;
 943
 944       /* Configure QSPI: CCR register with functional as indirect read */
 945       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
 946
 947       /* Start the transfer by re-writing the address in AR register */
 948       WRITE_REG(hqspi->Instance->AR, addr_reg);
 949
 950       while(hqspi->RxXferCount > 0)
 951       {
 952         /* Wait until FT or TC flag is set to read received data */
 953         status = QSPI_WaitFlagStateUntilTimeout(hqspi, (QSPI_FLAG_FT | QSPI_FLAG_TC), SET, tickstart, Timeout);
 954
 955         if  (status != HAL_OK)
 956         {
 957           break;
 958         }
 959
 960         *hqspi->pRxBuffPtr++ = *(__IO uint8_t *)data_reg;
 961         hqspi->RxXferCount--;
 962       }
 963
 964       if (status == HAL_OK)
 965       {
 966         /* Wait until TC flag is set to go back in idle state */
 967         status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, Timeout);
 968
 969         if  (status == HAL_OK)
 970         {
 971           /* Clear Transfer Complete bit */
 972           __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
 973
 974 #if defined(QSPI1_V1_0)
 975          /* Workaround - Extra data written in the FIFO at the end of a read transfer */
 976          status = HAL_QSPI_Abort(hqspi);
 977 #endif /* QSPI_V1_0 */
 978         }
 979       }
 980
 981       /* Update QSPI state */
 982       hqspi->State = HAL_QSPI_STATE_READY;
 983     }
 984     else
 985     {
 986       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
 987       status = HAL_ERROR;
 988     }
 989   }
 990   else
 991   {
 992     status = HAL_BUSY;
 993   }
 994
 995   /* Process unlocked */
 996   __HAL_UNLOCK(hqspi);
 997
 998   return status;
 999 }
1000
1001 /**
1002   * @brief  Send an amount of data in interrupt mode
1003   * @param  hqspi: QSPI handle
1004   * @param  pData: pointer to data buffer
1005   * @note   This function is used only in Indirect Write Mode
1006   * @retval HAL status
1007   */
1008 HAL_StatusTypeDef HAL_QSPI_Transmit_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1009 {
1010   HAL_StatusTypeDef status = HAL_OK;
1011
1012   /* Process locked */
1013   __HAL_LOCK(hqspi);
1014
1015   if(hqspi->State == HAL_QSPI_STATE_READY)
1016   {
1017     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1018     if(pData != NULL )
1019     {
1020       /* Update state */
1021       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1022
1023       /* Configure counters and size of the handle */
1024       hqspi->TxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
1025       hqspi->TxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
1026       hqspi->pTxBuffPtr = pData;
1027
1028       /* Configure QSPI: CCR register with functional as indirect write */
1029       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1030
1031       /* Clear interrupt */
1032       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1033
1034       /* Process unlocked */
1035       __HAL_UNLOCK(hqspi);
1036
1037       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1038       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1039
1040     }
1041     else
1042     {
1043       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1044       status = HAL_ERROR;
1045
1046       /* Process unlocked */
1047       __HAL_UNLOCK(hqspi);
1048     }
1049   }
1050   else
1051   {
1052     status = HAL_BUSY;
1053
1054     /* Process unlocked */
1055     __HAL_UNLOCK(hqspi);
1056   }
1057
1058   return status;
1059 }
1060
1061 /**
1062   * @brief  Receive an amount of data in no-blocking mode with Interrupt
1063   * @param  hqspi: QSPI handle
1064   * @param  pData: pointer to data buffer
1065   * @note   This function is used only in Indirect Read Mode
1066   * @retval HAL status
1067   */
1068 HAL_StatusTypeDef HAL_QSPI_Receive_IT(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1069 {
1070   HAL_StatusTypeDef status = HAL_OK;
1071   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1072
1073   /* Process locked */
1074   __HAL_LOCK(hqspi);
1075
1076   if(hqspi->State == HAL_QSPI_STATE_READY)
1077   {
1078     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1079
1080     if(pData != NULL )
1081     {
1082       /* Update state */
1083       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1084
1085       /* Configure counters and size of the handle */
1086       hqspi->RxXferCount = READ_REG(hqspi->Instance->DLR) + 1;
1087       hqspi->RxXferSize = READ_REG(hqspi->Instance->DLR) + 1;
1088       hqspi->pRxBuffPtr = pData;
1089
1090       /* Configure QSPI: CCR register with functional as indirect read */
1091       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1092
1093       /* Start the transfer by re-writing the address in AR register */
1094       WRITE_REG(hqspi->Instance->AR, addr_reg);
1095
1096       /* Clear interrupt */
1097       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_TC);
1098
1099       /* Process unlocked */
1100       __HAL_UNLOCK(hqspi);
1101
1102       /* Enable the QSPI transfer error, FIFO threshold and transfer complete Interrupts */
1103       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE | QSPI_IT_FT | QSPI_IT_TC);
1104     }
1105     else
1106     {
1107       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1108       status = HAL_ERROR;
1109
1110       /* Process unlocked */
1111       __HAL_UNLOCK(hqspi);
1112     }
1113   }
1114   else
1115   {
1116     status = HAL_BUSY;
1117
1118     /* Process unlocked */
1119     __HAL_UNLOCK(hqspi);
1120   }
1121
1122   return status;
1123 }
1124
1125 /**
1126   * @brief  Sends an amount of data in non blocking mode with DMA.
1127   * @param  hqspi: QSPI handle
1128   * @param  pData: pointer to data buffer
1129   * @note   This function is used only in Indirect Write Mode
1130   * @note   If DMA peripheral access is configured as halfword, the number
1131   *         of data and the fifo threshold should be aligned on halfword
1132   * @note   If DMA peripheral access is configured as word, the number
1133   *         of data and the fifo threshold should be aligned on word
1134   * @retval HAL status
1135   */
1136 HAL_StatusTypeDef HAL_QSPI_Transmit_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1137 {
1138   HAL_StatusTypeDef status = HAL_OK;
1139   uint32_t *tmp;
1140   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
1141
1142   /* Process locked */
1143   __HAL_LOCK(hqspi);
1144
1145   if(hqspi->State == HAL_QSPI_STATE_READY)
1146   {
1147     /* Clear the error code */
1148     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1149
1150     if(pData != NULL )
1151     {
1152       /* Configure counters of the handle */
1153       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
1154       {
1155         hqspi->TxXferCount = data_size;
1156       }
1157       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
1158       {
1159         if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
1160         {
1161           /* The number of data or the fifo threshold is not aligned on halfword
1162           => no transfer possible with DMA peripheral access configured as halfword */
1163           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1164           status = HAL_ERROR;
1165
1166           /* Process unlocked */
1167           __HAL_UNLOCK(hqspi);
1168         }
1169         else
1170         {
1171           hqspi->TxXferCount = (data_size >> 1);
1172         }
1173       }
1174       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
1175       {
1176         if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
1177         {
1178           /* The number of data or the fifo threshold is not aligned on word
1179           => no transfer possible with DMA peripheral access configured as word */
1180           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1181           status = HAL_ERROR;
1182
1183           /* Process unlocked */
1184           __HAL_UNLOCK(hqspi);
1185         }
1186         else
1187         {
1188           hqspi->TxXferCount = (data_size >> 2);
1189         }
1190       }
1191
1192       if (status == HAL_OK)
1193       {
1194
1195       /* Update state */
1196       hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_TX;
1197
1198       /* Clear interrupt */
1199       __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1200
1201       /* Configure size and pointer of the handle */
1202       hqspi->TxXferSize = hqspi->TxXferCount;
1203       hqspi->pTxBuffPtr = pData;
1204
1205       /* Configure QSPI: CCR register with functional mode as indirect write */
1206       MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE);
1207
1208       /* Set the QSPI DMA transfer complete callback */
1209       hqspi->hdma->XferCpltCallback = QSPI_DMATxCplt;
1210
1211       /* Set the QSPI DMA Half transfer complete callback */
1212       hqspi->hdma->XferHalfCpltCallback = QSPI_DMATxHalfCplt;
1213
1214       /* Set the DMA error callback */
1215       hqspi->hdma->XferErrorCallback = QSPI_DMAError;
1216
1217       /* Clear the DMA abort callback */
1218       hqspi->hdma->XferAbortCallback = NULL;
1219
1220       /* Configure the direction of the DMA */
1221       hqspi->hdma->Init.Direction = DMA_MEMORY_TO_PERIPH;
1222       MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
1223
1224       /* Enable the QSPI transmit DMA Channel */
1225       tmp = (uint32_t*)&pData;
1226       HAL_DMA_Start_IT(hqspi->hdma, *(uint32_t*)tmp, (uint32_t)&hqspi->Instance->DR, hqspi->TxXferSize);
1227
1228       /* Process unlocked */
1229       __HAL_UNLOCK(hqspi);
1230
1231       /* Enable the QSPI transfer error Interrupt */
1232       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1233
1234       /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
1235       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1236     }
1237     }
1238     else
1239     {
1240       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1241
1242       status = HAL_ERROR;
1243
1244       /* Process unlocked */
1245       __HAL_UNLOCK(hqspi);
1246     }
1247   }
1248   else
1249   {
1250     status = HAL_BUSY;
1251
1252     /* Process unlocked */
1253     __HAL_UNLOCK(hqspi);
1254   }
1255
1256   return status;
1257 }
1258
1259 /**
1260   * @brief  Receives an amount of data in non blocking mode with DMA.
1261   * @param  hqspi: QSPI handle
1262   * @param  pData: pointer to data buffer.
1263   * @note   This function is used only in Indirect Read Mode
1264   * @note   If DMA peripheral access is configured as halfword, the number
1265   *         of data and the fifo threshold should be aligned on halfword
1266   * @note   If DMA peripheral access is configured as word, the number
1267   *         of data and the fifo threshold should be aligned on word
1268   * @retval HAL status
1269   */
1270 HAL_StatusTypeDef HAL_QSPI_Receive_DMA(QSPI_HandleTypeDef *hqspi, uint8_t *pData)
1271 {
1272   HAL_StatusTypeDef status = HAL_OK;
1273   uint32_t *tmp;
1274   uint32_t addr_reg = READ_REG(hqspi->Instance->AR);
1275   uint32_t data_size = (READ_REG(hqspi->Instance->DLR) + 1);
1276
1277   /* Process locked */
1278   __HAL_LOCK(hqspi);
1279
1280   if(hqspi->State == HAL_QSPI_STATE_READY)
1281   {
1282     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1283
1284     if(pData != NULL )
1285     {
1286       /* Configure counters of the handle */
1287       if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_BYTE)
1288       {
1289         hqspi->RxXferCount = data_size;
1290       }
1291       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_HALFWORD)
1292       {
1293         if (((data_size % 2) != 0) || ((hqspi->Init.FifoThreshold % 2) != 0))
1294         {
1295           /* The number of data or the fifo threshold is not aligned on halfword
1296           => no transfer possible with DMA peripheral access configured as halfword */
1297           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1298           status = HAL_ERROR;
1299
1300           /* Process unlocked */
1301           __HAL_UNLOCK(hqspi);
1302         }
1303         else
1304         {
1305           hqspi->RxXferCount = (data_size >> 1);
1306         }
1307       }
1308       else if (hqspi->hdma->Init.PeriphDataAlignment == DMA_PDATAALIGN_WORD)
1309       {
1310         if (((data_size % 4) != 0) || ((hqspi->Init.FifoThreshold % 4) != 0))
1311         {
1312           /* The number of data or the fifo threshold is not aligned on word
1313           => no transfer possible with DMA peripheral access configured as word */
1314           hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1315           status = HAL_ERROR;
1316
1317           /* Process unlocked */
1318           __HAL_UNLOCK(hqspi);
1319         }
1320         else
1321         {
1322           hqspi->RxXferCount = (data_size >> 2);
1323         }
1324       }
1325
1326       if (status == HAL_OK)
1327       {
1328
1329         /* Update state */
1330         hqspi->State = HAL_QSPI_STATE_BUSY_INDIRECT_RX;
1331
1332         /* Clear interrupt */
1333         __HAL_QSPI_CLEAR_FLAG(hqspi, (QSPI_FLAG_TE | QSPI_FLAG_TC));
1334
1335         /* Configure size and pointer of the handle */
1336         hqspi->RxXferSize = hqspi->RxXferCount;
1337         hqspi->pRxBuffPtr = pData;
1338
1339         /* Set the QSPI DMA transfer complete callback */
1340         hqspi->hdma->XferCpltCallback = QSPI_DMARxCplt;
1341
1342         /* Set the QSPI DMA Half transfer complete callback */
1343         hqspi->hdma->XferHalfCpltCallback = QSPI_DMARxHalfCplt;
1344
1345         /* Set the DMA error callback */
1346         hqspi->hdma->XferErrorCallback = QSPI_DMAError;
1347
1348         /* Clear the DMA abort callback */
1349         hqspi->hdma->XferAbortCallback = NULL;
1350
1351         /* Configure the direction of the DMA */
1352         hqspi->hdma->Init.Direction = DMA_PERIPH_TO_MEMORY;
1353         MODIFY_REG(hqspi->hdma->Instance->CR, DMA_SxCR_DIR, hqspi->hdma->Init.Direction);
1354
1355         /* Enable the DMA Channel */
1356         tmp = (uint32_t*)&pData;
1357         HAL_DMA_Start_IT(hqspi->hdma, (uint32_t)&hqspi->Instance->DR, *(uint32_t*)tmp, hqspi->RxXferSize);
1358
1359         /* Configure QSPI: CCR register with functional as indirect read */
1360         MODIFY_REG(hqspi->Instance->CCR, QUADSPI_CCR_FMODE, QSPI_FUNCTIONAL_MODE_INDIRECT_READ);
1361
1362         /* Start the transfer by re-writing the address in AR register */
1363         WRITE_REG(hqspi->Instance->AR, addr_reg);
1364
1365         /* Process unlocked */
1366         __HAL_UNLOCK(hqspi);
1367
1368         /* Enable the QSPI transfer error Interrupt */
1369         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TE);
1370
1371         /* Enable the DMA transfer by setting the DMAEN bit in the QSPI CR register */
1372         SET_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1373       }
1374     }
1375     else
1376     {
1377       hqspi->ErrorCode |= HAL_QSPI_ERROR_INVALID_PARAM;
1378       status = HAL_ERROR;
1379
1380       /* Process unlocked */
1381       __HAL_UNLOCK(hqspi);
1382     }
1383   }
1384   else
1385   {
1386     status = HAL_BUSY;
1387
1388     /* Process unlocked */
1389     __HAL_UNLOCK(hqspi);
1390   }
1391
1392   return status;
1393 }
1394
1395 /**
1396   * @brief  Configure the QSPI Automatic Polling Mode in blocking mode.
1397   * @param  hqspi: QSPI handle
1398   * @param  cmd: structure that contains the command configuration information.
1399   * @param  cfg: structure that contains the polling configuration information.
1400   * @param  Timeout : Time out duration
1401   * @note   This function is used only in Automatic Polling Mode
1402   * @retval HAL status
1403   */
1404 HAL_StatusTypeDef HAL_QSPI_AutoPolling(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg, uint32_t Timeout)
1405 {
1406   HAL_StatusTypeDef status = HAL_ERROR;
1407   uint32_t tickstart = HAL_GetTick();
1408
1409   /* Check the parameters */
1410   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1411   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1412   {
1413     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1414   }
1415
1416   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1417   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1418   {
1419     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1420   }
1421
1422   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1423   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1424   {
1425     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1426   }
1427
1428   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1429   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1430
1431   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1432   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1433   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1434
1435   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1436   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1437   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1438
1439   /* Process locked */
1440   __HAL_LOCK(hqspi);
1441
1442   if(hqspi->State == HAL_QSPI_STATE_READY)
1443   {
1444
1445     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1446
1447     /* Update state */
1448     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1449
1450     /* Wait till BUSY flag reset */
1451     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, Timeout);
1452
1453     if (status == HAL_OK)
1454     {
1455       /* Configure QSPI: PSMAR register with the status match value */
1456       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1457
1458       /* Configure QSPI: PSMKR register with the status mask value */
1459       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1460
1461       /* Configure QSPI: PIR register with the interval value */
1462       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1463
1464       /* Configure QSPI: CR register with Match mode and Automatic stop enabled
1465       (otherwise there will be an infinite loop in blocking mode) */
1466       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1467                (cfg->MatchMode | QSPI_AUTOMATIC_STOP_ENABLE));
1468
1469       /* Call the configuration function */
1470       cmd->NbData = cfg->StatusBytesSize;
1471       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1472
1473       /* Wait until SM flag is set to go back in idle state */
1474       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_SM, SET, tickstart, Timeout);
1475
1476       if (status == HAL_OK)
1477       {
1478         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_SM);
1479
1480         /* Update state */
1481         hqspi->State = HAL_QSPI_STATE_READY;
1482       }
1483     }
1484   }
1485   else
1486   {
1487     status = HAL_BUSY;
1488   }
1489   /* Process unlocked */
1490   __HAL_UNLOCK(hqspi);
1491
1492   /* Return function status */
1493   return status;
1494 }
1495
1496 /**
1497   * @brief  Configure the QSPI Automatic Polling Mode in non-blocking mode.
1498   * @param  hqspi: QSPI handle
1499   * @param  cmd: structure that contains the command configuration information.
1500   * @param  cfg: structure that contains the polling configuration information.
1501   * @note   This function is used only in Automatic Polling Mode
1502   * @retval HAL status
1503   */
1504 HAL_StatusTypeDef HAL_QSPI_AutoPolling_IT(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_AutoPollingTypeDef *cfg)
1505 {
1506   HAL_StatusTypeDef status = HAL_ERROR;
1507   uint32_t tickstart = HAL_GetTick();
1508
1509   /* Check the parameters */
1510   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1511   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1512   {
1513     assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1514   }
1515
1516   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1517   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1518   {
1519     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1520   }
1521
1522   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1523   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1524   {
1525     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1526   }
1527
1528   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1529   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1530
1531   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1532   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1533   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1534
1535   assert_param(IS_QSPI_INTERVAL(cfg->Interval));
1536   assert_param(IS_QSPI_STATUS_BYTES_SIZE(cfg->StatusBytesSize));
1537   assert_param(IS_QSPI_MATCH_MODE(cfg->MatchMode));
1538   assert_param(IS_QSPI_AUTOMATIC_STOP(cfg->AutomaticStop));
1539
1540   /* Process locked */
1541   __HAL_LOCK(hqspi);
1542
1543   if(hqspi->State == HAL_QSPI_STATE_READY)
1544   {
1545     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1546
1547     /* Update state */
1548     hqspi->State = HAL_QSPI_STATE_BUSY_AUTO_POLLING;
1549
1550     /* Wait till BUSY flag reset */
1551     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1552
1553     if (status == HAL_OK)
1554     {
1555       /* Configure QSPI: PSMAR register with the status match value */
1556       WRITE_REG(hqspi->Instance->PSMAR, cfg->Match);
1557
1558       /* Configure QSPI: PSMKR register with the status mask value */
1559       WRITE_REG(hqspi->Instance->PSMKR, cfg->Mask);
1560
1561       /* Configure QSPI: PIR register with the interval value */
1562       WRITE_REG(hqspi->Instance->PIR, cfg->Interval);
1563
1564       /* Configure QSPI: CR register with Match mode and Automatic stop mode */
1565       MODIFY_REG(hqspi->Instance->CR, (QUADSPI_CR_PMM | QUADSPI_CR_APMS),
1566                (cfg->MatchMode | cfg->AutomaticStop));
1567
1568       /* Clear interrupt */
1569       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TE | QSPI_FLAG_SM);
1570
1571       /* Call the configuration function */
1572       cmd->NbData = cfg->StatusBytesSize;
1573       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_AUTO_POLLING);
1574
1575       /* Process unlocked */
1576       __HAL_UNLOCK(hqspi);
1577
1578       /* Enable the QSPI Transfer Error and status match Interrupt */
1579       __HAL_QSPI_ENABLE_IT(hqspi, (QSPI_IT_SM | QSPI_IT_TE));
1580
1581     }
1582     else
1583     {
1584       /* Process unlocked */
1585       __HAL_UNLOCK(hqspi);
1586     }
1587   }
1588   else
1589   {
1590     status = HAL_BUSY;
1591
1592     /* Process unlocked */
1593     __HAL_UNLOCK(hqspi);
1594   }
1595
1596   /* Return function status */
1597   return status;
1598 }
1599
1600 /**
1601   * @brief  Configure the Memory Mapped mode.
1602   * @param  hqspi: QSPI handle
1603   * @param  cmd: structure that contains the command configuration information.
1604   * @param  cfg: structure that contains the memory mapped configuration information.
1605   * @note   This function is used only in Memory mapped Mode
1606   * @retval HAL status
1607   */
1608 HAL_StatusTypeDef HAL_QSPI_MemoryMapped(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, QSPI_MemoryMappedTypeDef *cfg)
1609 {
1610   HAL_StatusTypeDef status = HAL_ERROR;
1611   uint32_t tickstart = HAL_GetTick();
1612
1613   /* Check the parameters */
1614   assert_param(IS_QSPI_INSTRUCTION_MODE(cmd->InstructionMode));
1615   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
1616   {
1617   assert_param(IS_QSPI_INSTRUCTION(cmd->Instruction));
1618   }
1619
1620   assert_param(IS_QSPI_ADDRESS_MODE(cmd->AddressMode));
1621   if (cmd->AddressMode != QSPI_ADDRESS_NONE)
1622   {
1623     assert_param(IS_QSPI_ADDRESS_SIZE(cmd->AddressSize));
1624   }
1625
1626   assert_param(IS_QSPI_ALTERNATE_BYTES_MODE(cmd->AlternateByteMode));
1627   if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
1628   {
1629     assert_param(IS_QSPI_ALTERNATE_BYTES_SIZE(cmd->AlternateBytesSize));
1630   }
1631
1632   assert_param(IS_QSPI_DUMMY_CYCLES(cmd->DummyCycles));
1633   assert_param(IS_QSPI_DATA_MODE(cmd->DataMode));
1634
1635   assert_param(IS_QSPI_DDR_MODE(cmd->DdrMode));
1636   assert_param(IS_QSPI_DDR_HHC(cmd->DdrHoldHalfCycle));
1637   assert_param(IS_QSPI_SIOO_MODE(cmd->SIOOMode));
1638
1639   assert_param(IS_QSPI_TIMEOUT_ACTIVATION(cfg->TimeOutActivation));
1640
1641   /* Process locked */
1642   __HAL_LOCK(hqspi);
1643
1644   if(hqspi->State == HAL_QSPI_STATE_READY)
1645   {
1646     hqspi->ErrorCode = HAL_QSPI_ERROR_NONE;
1647
1648     /* Update state */
1649     hqspi->State = HAL_QSPI_STATE_BUSY_MEM_MAPPED;
1650
1651     /* Wait till BUSY flag reset */
1652     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1653
1654     if (status == HAL_OK)
1655     {
1656       /* Configure QSPI: CR register with timeout counter enable */
1657     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_TCEN, cfg->TimeOutActivation);
1658
1659     if (cfg->TimeOutActivation == QSPI_TIMEOUT_COUNTER_ENABLE)
1660       {
1661         assert_param(IS_QSPI_TIMEOUT_PERIOD(cfg->TimeOutPeriod));
1662
1663         /* Configure QSPI: LPTR register with the low-power timeout value */
1664         WRITE_REG(hqspi->Instance->LPTR, cfg->TimeOutPeriod);
1665
1666         /* Clear interrupt */
1667         __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TO);
1668
1669         /* Enable the QSPI TimeOut Interrupt */
1670         __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TO);
1671       }
1672
1673       /* Call the configuration function */
1674       QSPI_Config(hqspi, cmd, QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED);
1675     }
1676   }
1677   else
1678   {
1679     status = HAL_BUSY;
1680   }
1681
1682   /* Process unlocked */
1683   __HAL_UNLOCK(hqspi);
1684
1685   /* Return function status */
1686   return status;
1687 }
1688
1689 /**
1690   * @brief  Transfer Error callbacks
1691   * @param  hqspi: QSPI handle
1692   * @retval None
1693   */
1694 __weak void HAL_QSPI_ErrorCallback(QSPI_HandleTypeDef *hqspi)
1695 {
1696   /* Prevent unused argument(s) compilation warning */
1697   UNUSED(hqspi);
1698
1699   /* NOTE : This function Should not be modified, when the callback is needed,
1700             the HAL_QSPI_ErrorCallback could be implemented in the user file
1701    */
1702 }
1703
1704 /**
1705   * @brief  Abort completed callback.
1706   * @param  hqspi: QSPI handle
1707   * @retval None
1708   */
1709 __weak void HAL_QSPI_AbortCpltCallback(QSPI_HandleTypeDef *hqspi)
1710 {
1711   /* Prevent unused argument(s) compilation warning */
1712   UNUSED(hqspi);
1713
1714   /* NOTE: This function should not be modified, when the callback is needed,
1715            the HAL_QSPI_AbortCpltCallback could be implemented in the user file
1716    */
1717 }
1718
1719 /**
1720   * @brief  Command completed callback.
1721   * @param  hqspi: QSPI handle
1722   * @retval None
1723   */
1724 __weak void HAL_QSPI_CmdCpltCallback(QSPI_HandleTypeDef *hqspi)
1725 {
1726   /* Prevent unused argument(s) compilation warning */
1727   UNUSED(hqspi);
1728
1729   /* NOTE: This function Should not be modified, when the callback is needed,
1730            the HAL_QSPI_CmdCpltCallback could be implemented in the user file
1731    */
1732 }
1733
1734 /**
1735   * @brief  Rx Transfer completed callbacks.
1736   * @param  hqspi: QSPI handle
1737   * @retval None
1738   */
1739 __weak void HAL_QSPI_RxCpltCallback(QSPI_HandleTypeDef *hqspi)
1740 {
1741   /* Prevent unused argument(s) compilation warning */
1742   UNUSED(hqspi);
1743
1744   /* NOTE: This function Should not be modified, when the callback is needed,
1745            the HAL_QSPI_RxCpltCallback could be implemented in the user file
1746    */
1747 }
1748
1749 /**
1750   * @brief  Tx Transfer completed callbacks.
1751   * @param  hqspi: QSPI handle
1752   * @retval None
1753   */
1754  __weak void HAL_QSPI_TxCpltCallback(QSPI_HandleTypeDef *hqspi)
1755 {
1756   /* Prevent unused argument(s) compilation warning */
1757   UNUSED(hqspi);
1758
1759   /* NOTE: This function Should not be modified, when the callback is needed,
1760            the HAL_QSPI_TxCpltCallback could be implemented in the user file
1761    */
1762 }
1763
1764 /**
1765   * @brief  Rx Half Transfer completed callbacks.
1766   * @param  hqspi: QSPI handle
1767   * @retval None
1768   */
1769 __weak void HAL_QSPI_RxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
1770 {
1771   /* Prevent unused argument(s) compilation warning */
1772   UNUSED(hqspi);
1773
1774   /* NOTE: This function Should not be modified, when the callback is needed,
1775            the HAL_QSPI_RxHalfCpltCallback could be implemented in the user file
1776    */
1777 }
1778
1779 /**
1780   * @brief  Tx Half Transfer completed callbacks.
1781   * @param  hqspi: QSPI handle
1782   * @retval None
1783   */
1784  __weak void HAL_QSPI_TxHalfCpltCallback(QSPI_HandleTypeDef *hqspi)
1785 {
1786   /* Prevent unused argument(s) compilation warning */
1787   UNUSED(hqspi);
1788
1789   /* NOTE: This function Should not be modified, when the callback is needed,
1790            the HAL_QSPI_TxHalfCpltCallback could be implemented in the user file
1791    */
1792 }
1793
1794 /**
1795   * @brief  FIFO Threshold callbacks
1796   * @param  hqspi: QSPI handle
1797   * @retval None
1798   */
1799 __weak void HAL_QSPI_FifoThresholdCallback(QSPI_HandleTypeDef *hqspi)
1800 {
1801   /* Prevent unused argument(s) compilation warning */
1802   UNUSED(hqspi);
1803
1804   /* NOTE : This function Should not be modified, when the callback is needed,
1805             the HAL_QSPI_FIFOThresholdCallback could be implemented in the user file
1806    */
1807 }
1808
1809 /**
1810   * @brief  Status Match callbacks
1811   * @param  hqspi: QSPI handle
1812   * @retval None
1813   */
1814 __weak void HAL_QSPI_StatusMatchCallback(QSPI_HandleTypeDef *hqspi)
1815 {
1816   /* Prevent unused argument(s) compilation warning */
1817   UNUSED(hqspi);
1818
1819   /* NOTE : This function Should not be modified, when the callback is needed,
1820             the HAL_QSPI_StatusMatchCallback could be implemented in the user file
1821    */
1822 }
1823
1824 /**
1825   * @brief  Timeout callbacks
1826   * @param  hqspi: QSPI handle
1827   * @retval None
1828   */
1829 __weak void HAL_QSPI_TimeOutCallback(QSPI_HandleTypeDef *hqspi)
1830 {
1831   /* Prevent unused argument(s) compilation warning */
1832   UNUSED(hqspi);
1833
1834   /* NOTE : This function Should not be modified, when the callback is needed,
1835             the HAL_QSPI_TimeOutCallback could be implemented in the user file
1836    */
1837 }
1838
1839 /**
1840   * @}
1841   */
1842
1843 /** @defgroup QSPI_Exported_Functions_Group3 Peripheral Control and State functions
1844   *  @brief   QSPI control and State functions
1845   *
1846 @verbatim
1847  ===============================================================================
1848                   ##### Peripheral Control and State functions #####
1849  ===============================================================================
1850     [..]
1851     This subsection provides a set of functions allowing to :
1852       (+) Check in run-time the state of the driver.
1853       (+) Check the error code set during last operation.
1854       (+) Abort any operation.
1855 .....
1856 @endverbatim
1857   * @{
1858   */
1859
1860 /**
1861   * @brief  Return the QSPI handle state.
1862   * @param  hqspi: QSPI handle
1863   * @retval HAL state
1864   */
1865 HAL_QSPI_StateTypeDef HAL_QSPI_GetState(QSPI_HandleTypeDef *hqspi)
1866 {
1867   /* Return QSPI handle state */
1868   return hqspi->State;
1869 }
1870
1871 /**
1872 * @brief  Return the QSPI error code
1873 * @param  hqspi: QSPI handle
1874 * @retval QSPI Error Code
1875 */
1876 uint32_t HAL_QSPI_GetError(QSPI_HandleTypeDef *hqspi)
1877 {
1878   return hqspi->ErrorCode;
1879 }
1880
1881 /**
1882 * @brief  Abort the current transmission
1883 * @param  hqspi: QSPI handle
1884 * @retval HAL status
1885 */
1886 HAL_StatusTypeDef HAL_QSPI_Abort(QSPI_HandleTypeDef *hqspi)
1887 {
1888   HAL_StatusTypeDef status = HAL_OK;
1889   uint32_t tickstart = HAL_GetTick();
1890
1891   /* Check if the state is in one of the busy states */
1892   if ((hqspi->State & 0x2) != 0)
1893   {
1894     /* Process unlocked */
1895     __HAL_UNLOCK(hqspi);
1896
1897     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
1898     {
1899       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
1900       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1901
1902       /* Abort DMA channel */
1903       status = HAL_DMA_Abort(hqspi->hdma);
1904       if(status != HAL_OK)
1905       {
1906         hqspi->ErrorCode |= HAL_QSPI_ERROR_DMA;
1907       }
1908     }
1909
1910     /* Configure QSPI: CR register with Abort request */
1911     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
1912
1913     /* Wait until TC flag is set to go back in idle state */
1914     status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_TC, SET, tickstart, hqspi->Timeout);
1915
1916     if(status == HAL_OK)
1917     {
1918       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
1919
1920       /* Wait until BUSY flag is reset */
1921       status = QSPI_WaitFlagStateUntilTimeout(hqspi, QSPI_FLAG_BUSY, RESET, tickstart, hqspi->Timeout);
1922     }
1923
1924     if (status == HAL_OK)
1925     {
1926       /* Update state */
1927       hqspi->State = HAL_QSPI_STATE_READY;
1928     }
1929   }
1930
1931   return status;
1932 }
1933
1934 /**
1935 * @brief  Abort the current transmission (non-blocking function)
1936 * @param  hqspi: QSPI handle
1937 * @retval HAL status
1938 */
1939 HAL_StatusTypeDef HAL_QSPI_Abort_IT(QSPI_HandleTypeDef *hqspi)
1940 {
1941   HAL_StatusTypeDef status = HAL_OK;
1942
1943   /* Check if the state is in one of the busy states */
1944   if ((hqspi->State & 0x2) != 0)
1945   {
1946     /* Process unlocked */
1947     __HAL_UNLOCK(hqspi);
1948
1949     /* Update QSPI state */
1950     hqspi->State = HAL_QSPI_STATE_ABORT;
1951
1952     /* Disable all interrupts */
1953     __HAL_QSPI_DISABLE_IT(hqspi, (QSPI_IT_TO | QSPI_IT_SM | QSPI_IT_FT | QSPI_IT_TC | QSPI_IT_TE));
1954
1955     if ((hqspi->Instance->CR & QUADSPI_CR_DMAEN)!= RESET)
1956     {
1957       /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
1958       CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
1959
1960       /* Abort DMA channel */
1961       hqspi->hdma->XferAbortCallback = QSPI_DMAAbortCplt;
1962       HAL_DMA_Abort_IT(hqspi->hdma);
1963     }
1964     else
1965     {
1966       /* Clear interrupt */
1967       __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
1968
1969       /* Enable the QSPI Transfer Complete Interrupt */
1970       __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
1971
1972       /* Configure QSPI: CR register with Abort request */
1973       SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
1974     }
1975   }
1976
1977   return status;
1978 }
1979
1980 /** @brief Set QSPI timeout
1981   * @param  hqspi: QSPI handle.
1982   * @param  Timeout: Timeout for the QSPI memory access.
1983   * @retval None
1984   */
1985 void HAL_QSPI_SetTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Timeout)
1986 {
1987   hqspi->Timeout = Timeout;
1988 }
1989
1990 /** @brief Set QSPI Fifo threshold.
1991   * @param  hqspi: QSPI handle.
1992   * @param  Threshold: Threshold of the Fifo (value between 1 and 16).
1993   * @retval HAL status
1994   */
1995 HAL_StatusTypeDef HAL_QSPI_SetFifoThreshold(QSPI_HandleTypeDef *hqspi, uint32_t Threshold)
1996 {
1997   HAL_StatusTypeDef status = HAL_OK;
1998
1999   /* Process locked */
2000   __HAL_LOCK(hqspi);
2001
2002   if(hqspi->State == HAL_QSPI_STATE_READY)
2003   {
2004     /* Synchronize init structure with new FIFO threshold value */
2005     hqspi->Init.FifoThreshold = Threshold;
2006
2007     /* Configure QSPI FIFO Threshold */
2008     MODIFY_REG(hqspi->Instance->CR, QUADSPI_CR_FTHRES,
2009                ((hqspi->Init.FifoThreshold - 1) << POSITION_VAL(QUADSPI_CR_FTHRES)));
2010   }
2011   else
2012   {
2013     status = HAL_BUSY;
2014   }
2015
2016   /* Process unlocked */
2017   __HAL_UNLOCK(hqspi);
2018
2019   /* Return function status */
2020   return status;
2021 }
2022
2023 /** @brief Get QSPI Fifo threshold.
2024   * @param  hqspi: QSPI handle.
2025   * @retval Fifo threshold (value between 1 and 16)
2026   */
2027 uint32_t HAL_QSPI_GetFifoThreshold(QSPI_HandleTypeDef *hqspi)
2028 {
2029   return ((READ_BIT(hqspi->Instance->CR, QUADSPI_CR_FTHRES) >> POSITION_VAL(QUADSPI_CR_FTHRES)) + 1);
2030 }
2031
2032 /**
2033   * @}
2034   */
2035
2036 /* Private functions ---------------------------------------------------------*/
2037
2038 /**
2039   * @brief  DMA QSPI receive process complete callback.
2040   * @param  hdma: DMA handle
2041   * @retval None
2042   */
2043 static void QSPI_DMARxCplt(DMA_HandleTypeDef *hdma)
2044 {
2045   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2046   hqspi->RxXferCount = 0;
2047
2048   /* Enable the QSPI transfer complete Interrupt */
2049   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2050 }
2051
2052 /**
2053   * @brief  DMA QSPI transmit process complete callback.
2054   * @param  hdma: DMA handle
2055   * @retval None
2056   */
2057 static void QSPI_DMATxCplt(DMA_HandleTypeDef *hdma)
2058 {
2059   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2060   hqspi->TxXferCount = 0;
2061
2062   /* Enable the QSPI transfer complete Interrupt */
2063   __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2064 }
2065
2066 /**
2067   * @brief  DMA QSPI receive process half complete callback
2068   * @param  hdma : DMA handle
2069   * @retval None
2070   */
2071 static void QSPI_DMARxHalfCplt(DMA_HandleTypeDef *hdma)
2072 {
2073   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2074
2075   HAL_QSPI_RxHalfCpltCallback(hqspi);
2076 }
2077
2078 /**
2079   * @brief  DMA QSPI transmit process half complete callback
2080   * @param  hdma : DMA handle
2081   * @retval None
2082   */
2083 static void QSPI_DMATxHalfCplt(DMA_HandleTypeDef *hdma)
2084 {
2085   QSPI_HandleTypeDef* hqspi = (QSPI_HandleTypeDef*)((DMA_HandleTypeDef*)hdma)->Parent;
2086
2087   HAL_QSPI_TxHalfCpltCallback(hqspi);
2088 }
2089
2090 /**
2091   * @brief  DMA QSPI communication error callback.
2092   * @param  hdma: DMA handle
2093   * @retval None
2094   */
2095 static void QSPI_DMAError(DMA_HandleTypeDef *hdma)
2096 {
2097   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2098
2099   /* if DMA error is FIFO error ignore it */
2100   if(HAL_DMA_GetError(hdma) != HAL_DMA_ERROR_FE)
2101   {
2102     hqspi->RxXferCount = 0;
2103     hqspi->TxXferCount = 0;
2104     hqspi->ErrorCode   |= HAL_QSPI_ERROR_DMA;
2105
2106     /* Disable the DMA transfer by clearing the DMAEN bit in the QSPI CR register */
2107     CLEAR_BIT(hqspi->Instance->CR, QUADSPI_CR_DMAEN);
2108
2109     /* Abort the QSPI */
2110     HAL_QSPI_Abort_IT(hqspi);
2111   }
2112 }
2113
2114 /**
2115   * @brief  DMA QSPI abort complete callback.
2116   * @param  hdma: DMA handle
2117   * @retval None
2118   */
2119 static void QSPI_DMAAbortCplt(DMA_HandleTypeDef *hdma)
2120 {
2121   QSPI_HandleTypeDef* hqspi = ( QSPI_HandleTypeDef* )((DMA_HandleTypeDef* )hdma)->Parent;
2122
2123   hqspi->RxXferCount = 0;
2124   hqspi->TxXferCount = 0;
2125
2126   if(hqspi->State == HAL_QSPI_STATE_ABORT)
2127   {
2128     /* DMA Abort called by QSPI abort */
2129     /* Clear interrupt */
2130     __HAL_QSPI_CLEAR_FLAG(hqspi, QSPI_FLAG_TC);
2131
2132     /* Enable the QSPI Transfer Complete Interrupt */
2133     __HAL_QSPI_ENABLE_IT(hqspi, QSPI_IT_TC);
2134
2135     /* Configure QSPI: CR register with Abort request */
2136     SET_BIT(hqspi->Instance->CR, QUADSPI_CR_ABORT);
2137   }
2138   else
2139   {
2140     /* DMA Abort called due to a transfer error interrupt */
2141     /* Change state of QSPI */
2142     hqspi->State = HAL_QSPI_STATE_READY;
2143
2144     /* Error callback */
2145     HAL_QSPI_ErrorCallback(hqspi);
2146   }
2147 }
2148
2149 /**
2150   * @brief  Wait for a flag state until timeout.
2151   * @param  hqspi: QSPI handle
2152   * @param  Flag: Flag checked
2153   * @param  State: Value of the flag expected
2154   * @param  tickstart: Start tick value
2155   * @param  Timeout: Duration of the time out
2156   * @retval HAL status
2157   */
2158 static HAL_StatusTypeDef QSPI_WaitFlagStateUntilTimeout(QSPI_HandleTypeDef *hqspi, uint32_t Flag,
2159                                                         FlagStatus State, uint32_t tickstart, uint32_t Timeout)
2160 {
2161   /* Wait until flag is in expected state */
2162   while((FlagStatus)(__HAL_QSPI_GET_FLAG(hqspi, Flag)) != State)
2163   {
2164     /* Check for the Timeout */
2165     if (Timeout != HAL_MAX_DELAY)
2166     {
2167       if((Timeout == 0) || ((HAL_GetTick() - tickstart) > Timeout))
2168       {
2169         hqspi->State     = HAL_QSPI_STATE_ERROR;
2170         hqspi->ErrorCode |= HAL_QSPI_ERROR_TIMEOUT;
2171
2172         return HAL_ERROR;
2173       }
2174     }
2175   }
2176   return HAL_OK;
2177 }
2178
2179 /**
2180   * @brief  Configure the communication registers.
2181   * @param  hqspi: QSPI handle
2182   * @param  cmd: structure that contains the command configuration information
2183   * @param  FunctionalMode: functional mode to configured
2184   *           This parameter can be one of the following values:
2185   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_WRITE: Indirect write mode
2186   *            @arg QSPI_FUNCTIONAL_MODE_INDIRECT_READ: Indirect read mode
2187   *            @arg QSPI_FUNCTIONAL_MODE_AUTO_POLLING: Automatic polling mode
2188   *            @arg QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED: Memory-mapped mode
2189   * @retval None
2190   */
2191 static void QSPI_Config(QSPI_HandleTypeDef *hqspi, QSPI_CommandTypeDef *cmd, uint32_t FunctionalMode)
2192 {
2193   assert_param(IS_QSPI_FUNCTIONAL_MODE(FunctionalMode));
2194
2195   if ((cmd->DataMode != QSPI_DATA_NONE) && (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED))
2196   {
2197     /* Configure QSPI: DLR register with the number of data to read or write */
2198     WRITE_REG(hqspi->Instance->DLR, (cmd->NbData - 1));
2199   }
2200
2201   if (cmd->InstructionMode != QSPI_INSTRUCTION_NONE)
2202   {
2203     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2204     {
2205       /* Configure QSPI: ABR register with alternate bytes value */
2206       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2207
2208       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2209       {
2210         /*---- Command with instruction, address and alternate bytes ----*/
2211         /* Configure QSPI: CCR register with all communications parameters */
2212         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2213                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
2214                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
2215                                          cmd->InstructionMode | cmd->Instruction | FunctionalMode));
2216
2217         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2218         {
2219           /* Configure QSPI: AR register with address value */
2220           WRITE_REG(hqspi->Instance->AR, cmd->Address);
2221         }
2222       }
2223       else
2224       {
2225         /*---- Command with instruction and alternate bytes ----*/
2226         /* Configure QSPI: CCR register with all communications parameters */
2227         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2228                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
2229                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
2230                                          cmd->Instruction | FunctionalMode));
2231       }
2232     }
2233     else
2234     {
2235       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2236       {
2237         /*---- Command with instruction and address ----*/
2238         /* Configure QSPI: CCR register with all communications parameters */
2239         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2240                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
2241                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
2242                                          cmd->Instruction | FunctionalMode));
2243
2244         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2245         {
2246           /* Configure QSPI: AR register with address value */
2247           WRITE_REG(hqspi->Instance->AR, cmd->Address);
2248         }
2249       }
2250       else
2251       {
2252         /*---- Command with only instruction ----*/
2253         /* Configure QSPI: CCR register with all communications parameters */
2254         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2255                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
2256                                          cmd->AddressMode | cmd->InstructionMode | cmd->Instruction  |
2257                                          FunctionalMode));
2258       }
2259     }
2260   }
2261   else
2262   {
2263     if (cmd->AlternateByteMode != QSPI_ALTERNATE_BYTES_NONE)
2264     {
2265       /* Configure QSPI: ABR register with alternate bytes value */
2266       WRITE_REG(hqspi->Instance->ABR, cmd->AlternateBytes);
2267
2268       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2269       {
2270         /*---- Command with address and alternate bytes ----*/
2271         /* Configure QSPI: CCR register with all communications parameters */
2272         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2273                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
2274                                          cmd->AlternateByteMode | cmd->AddressSize | cmd->AddressMode |
2275                                          cmd->InstructionMode | FunctionalMode));
2276
2277         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2278         {
2279           /* Configure QSPI: AR register with address value */
2280           WRITE_REG(hqspi->Instance->AR, cmd->Address);
2281         }
2282       }
2283       else
2284       {
2285         /*---- Command with only alternate bytes ----*/
2286         /* Configure QSPI: CCR register with all communications parameters */
2287         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2288                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateBytesSize |
2289                                          cmd->AlternateByteMode | cmd->AddressMode | cmd->InstructionMode |
2290                                          FunctionalMode));
2291       }
2292     }
2293     else
2294     {
2295       if (cmd->AddressMode != QSPI_ADDRESS_NONE)
2296       {
2297         /*---- Command with only address ----*/
2298         /* Configure QSPI: CCR register with all communications parameters */
2299         WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2300                                          cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
2301                                          cmd->AddressSize | cmd->AddressMode | cmd->InstructionMode |
2302                                          FunctionalMode));
2303
2304         if (FunctionalMode != QSPI_FUNCTIONAL_MODE_MEMORY_MAPPED)
2305         {
2306           /* Configure QSPI: AR register with address value */
2307           WRITE_REG(hqspi->Instance->AR, cmd->Address);
2308         }
2309       }
2310       else
2311       {
2312         /*---- Command with only data phase ----*/
2313         if (cmd->DataMode != QSPI_DATA_NONE)
2314         {
2315           /* Configure QSPI: CCR register with all communications parameters */
2316           WRITE_REG(hqspi->Instance->CCR, (cmd->DdrMode | cmd->DdrHoldHalfCycle | cmd->SIOOMode |
2317                                            cmd->DataMode | (cmd->DummyCycles << 18) | cmd->AlternateByteMode |
2318                                            cmd->AddressMode | cmd->InstructionMode | FunctionalMode));
2319         }
2320       }
2321     }
2322   }
2323 }
2324 /**
2325   * @}
2326   */
2327
2328 #endif /* HAL_QSPI_MODULE_ENABLED */
2329 /**
2330   * @}
2331   */
2332
2333 /**
2334   * @}
2335   */
2336
2337 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/