lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_hal_sram.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_hal_sram.c
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   SRAM HAL module driver.
   8   *          This file provides a generic firmware to drive SRAM memories
   9   *          mounted as external device.
  10   *
  11   @verbatim
  12   ==============================================================================
  13                           ##### How to use this driver #####
  14   ==============================================================================
  15   [..]
  16     This driver is a generic layered driver which contains a set of APIs used to
  17     control SRAM memories. It uses the FMC layer functions to interface
  18     with SRAM devices.
  19     The following sequence should be followed to configure the FMC to interface
  20     with SRAM/PSRAM memories:
  21
  22    (#) Declare a SRAM_HandleTypeDef handle structure, for example:
  23           SRAM_HandleTypeDef  hsram; and:
  24
  25        (++) Fill the SRAM_HandleTypeDef handle "Init" field with the allowed
  26             values of the structure member.
  27
  28        (++) Fill the SRAM_HandleTypeDef handle "Instance" field with a predefined
  29             base register instance for NOR or SRAM device
  30
  31        (++) Fill the SRAM_HandleTypeDef handle "Extended" field with a predefined
  32             base register instance for NOR or SRAM extended mode
  33
  34    (#) Declare two FMC_NORSRAM_TimingTypeDef structures, for both normal and extended
  35        mode timings; for example:
  36           FMC_NORSRAM_TimingTypeDef  Timing and FMC_NORSRAM_TimingTypeDef  ExTiming;
  37       and fill its fields with the allowed values of the structure member.
  38
  39    (#) Initialize the SRAM Controller by calling the function HAL_SRAM_Init(). This function
  40        performs the following sequence:
  41
  42        (##) MSP hardware layer configuration using the function HAL_SRAM_MspInit()
  43        (##) Control register configuration using the FMC NORSRAM interface function
  44             FMC_NORSRAM_Init()
  45        (##) Timing register configuration using the FMC NORSRAM interface function
  46             FMC_NORSRAM_Timing_Init()
  47        (##) Extended mode Timing register configuration using the FMC NORSRAM interface function
  48             FMC_NORSRAM_Extended_Timing_Init()
  49        (##) Enable the SRAM device using the macro __FMC_NORSRAM_ENABLE()
  50
  51    (#) At this stage you can perform read/write accesses from/to the memory connected
  52        to the NOR/SRAM Bank. You can perform either polling or DMA transfer using the
  53        following APIs:
  54        (++) HAL_SRAM_Read()/HAL_SRAM_Write() for polling read/write access
  55        (++) HAL_SRAM_Read_DMA()/HAL_SRAM_Write_DMA() for DMA read/write transfer
  56
  57    (#) You can also control the SRAM device by calling the control APIs HAL_SRAM_WriteOperation_Enable()/
  58        HAL_SRAM_WriteOperation_Disable() to respectively enable/disable the SRAM write operation
  59
  60    (#) You can continuously monitor the SRAM device HAL state by calling the function
  61        HAL_SRAM_GetState()
  62
  63   @endverbatim
  64   ******************************************************************************
  65   * @attention
  66   *
  67   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  68   *
  69   * Redistribution and use in source and binary forms, with or without modification,
  70   * are permitted provided that the following conditions are met:
  71   *   1. Redistributions of source code must retain the above copyright notice,
  72   *      this list of conditions and the following disclaimer.
  73   *   2. Redistributions in binary form must reproduce the above copyright notice,
  74   *      this list of conditions and the following disclaimer in the documentation
  75   *      and/or other materials provided with the distribution.
  76   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  77   *      may be used to endorse or promote products derived from this software
  78   *      without specific prior written permission.
  79   *
  80   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  81   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  82   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  83   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  84   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  85   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  86   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  87   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  88   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  89   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  90   *
  91   ******************************************************************************
  92   */
  93
  94 /* Includes ------------------------------------------------------------------*/
  95 #include "stm32f7xx_hal.h"
  96
  97 /** @addtogroup STM32F7xx_HAL_Driver
  98   * @{
  99   */
 100
 101 /** @defgroup SRAM SRAM
 102   * @brief SRAM driver modules
 103   * @{
 104   */
 105 #ifdef HAL_SRAM_MODULE_ENABLED
 106 /* Private typedef -----------------------------------------------------------*/
 107 /* Private define ------------------------------------------------------------*/
 108 /* Private macro -------------------------------------------------------------*/
 109 /* Private variables ---------------------------------------------------------*/
 110 /* Private function prototypes -----------------------------------------------*/
 111 /* Exported functions --------------------------------------------------------*/
 112
 113 /** @defgroup SRAM_Exported_Functions SRAM Exported Functions
 114   * @{
 115   */
 116
 117 /** @defgroup SRAM_Exported_Functions_Group1 Initialization and de-initialization functions
 118   * @brief    Initialization and Configuration functions.
 119   *
 120   @verbatim
 121   ==============================================================================
 122            ##### SRAM Initialization and de_initialization functions #####
 123   ==============================================================================
 124     [..]  This section provides functions allowing to initialize/de-initialize
 125           the SRAM memory
 126
 127 @endverbatim
 128   * @{
 129   */
 130
 131 /**
 132   * @brief  Performs the SRAM device initialization sequence
 133   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 134   *                the configuration information for SRAM module.
 135   * @param  Timing: Pointer to SRAM control timing structure
 136   * @param  ExtTiming: Pointer to SRAM extended mode timing structure
 137   * @retval HAL status
 138   */
 139 HAL_StatusTypeDef HAL_SRAM_Init(SRAM_HandleTypeDef *hsram, FMC_NORSRAM_TimingTypeDef *Timing, FMC_NORSRAM_TimingTypeDef *ExtTiming)
 140 {
 141   /* Check the SRAM handle parameter */
 142   if(hsram == NULL)
 143   {
 144      return HAL_ERROR;
 145   }
 146
 147   if(hsram->State == HAL_SRAM_STATE_RESET)
 148   {
 149     /* Allocate lock resource and initialize it */
 150     hsram->Lock = HAL_UNLOCKED;
 151     /* Initialize the low level hardware (MSP) */
 152     HAL_SRAM_MspInit(hsram);
 153   }
 154
 155   /* Initialize SRAM control Interface */
 156   FMC_NORSRAM_Init(hsram->Instance, &(hsram->Init));
 157
 158   /* Initialize SRAM timing Interface */
 159   FMC_NORSRAM_Timing_Init(hsram->Instance, Timing, hsram->Init.NSBank);
 160
 161   /* Initialize SRAM extended mode timing Interface */
 162   FMC_NORSRAM_Extended_Timing_Init(hsram->Extended, ExtTiming, hsram->Init.NSBank,  hsram->Init.ExtendedMode);
 163
 164   /* Enable the NORSRAM device */
 165   __FMC_NORSRAM_ENABLE(hsram->Instance, hsram->Init.NSBank);
 166
 167   return HAL_OK;
 168 }
 169
 170 /**
 171   * @brief  Performs the SRAM device De-initialization sequence.
 172   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 173   *                the configuration information for SRAM module.
 174   * @retval HAL status
 175   */
 176 HAL_StatusTypeDef  HAL_SRAM_DeInit(SRAM_HandleTypeDef *hsram)
 177 {
 178   /* De-Initialize the low level hardware (MSP) */
 179   HAL_SRAM_MspDeInit(hsram);
 180
 181   /* Configure the SRAM registers with their reset values */
 182   FMC_NORSRAM_DeInit(hsram->Instance, hsram->Extended, hsram->Init.NSBank);
 183
 184   hsram->State = HAL_SRAM_STATE_RESET;
 185
 186   /* Release Lock */
 187   __HAL_UNLOCK(hsram);
 188
 189   return HAL_OK;
 190 }
 191
 192 /**
 193   * @brief  SRAM MSP Init.
 194   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 195   *                the configuration information for SRAM module.
 196   * @retval None
 197   */
 198 __weak void HAL_SRAM_MspInit(SRAM_HandleTypeDef *hsram)
 199 {
 200   /* Prevent unused argument(s) compilation warning */
 201   UNUSED(hsram);
 202
 203   /* NOTE : This function Should not be modified, when the callback is needed,
 204             the HAL_SRAM_MspInit could be implemented in the user file
 205    */
 206 }
 207
 208 /**
 209   * @brief  SRAM MSP DeInit.
 210   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 211   *                the configuration information for SRAM module.
 212   * @retval None
 213   */
 214 __weak void HAL_SRAM_MspDeInit(SRAM_HandleTypeDef *hsram)
 215 {
 216   /* Prevent unused argument(s) compilation warning */
 217   UNUSED(hsram);
 218
 219   /* NOTE : This function Should not be modified, when the callback is needed,
 220             the HAL_SRAM_MspDeInit could be implemented in the user file
 221    */
 222 }
 223
 224 /**
 225   * @brief  DMA transfer complete callback.
 226   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
 227   *                the configuration information for SRAM module.
 228   * @retval None
 229   */
 230 __weak void HAL_SRAM_DMA_XferCpltCallback(DMA_HandleTypeDef *hdma)
 231 {
 232   /* Prevent unused argument(s) compilation warning */
 233   UNUSED(hdma);
 234
 235   /* NOTE : This function Should not be modified, when the callback is needed,
 236             the HAL_SRAM_DMA_XferCpltCallback could be implemented in the user file
 237    */
 238 }
 239
 240 /**
 241   * @brief  DMA transfer complete error callback.
 242   * @param  hdma: pointer to a SRAM_HandleTypeDef structure that contains
 243   *                the configuration information for SRAM module.
 244   * @retval None
 245   */
 246 __weak void HAL_SRAM_DMA_XferErrorCallback(DMA_HandleTypeDef *hdma)
 247 {
 248   /* Prevent unused argument(s) compilation warning */
 249   UNUSED(hdma);
 250
 251   /* NOTE : This function Should not be modified, when the callback is needed,
 252             the HAL_SRAM_DMA_XferErrorCallback could be implemented in the user file
 253    */
 254 }
 255
 256 /**
 257   * @}
 258   */
 259
 260 /** @defgroup SRAM_Exported_Functions_Group2 Input Output and memory control functions
 261   * @brief    Input Output and memory control functions
 262   *
 263   @verbatim
 264   ==============================================================================
 265                   ##### SRAM Input and Output functions #####
 266   ==============================================================================
 267   [..]
 268     This section provides functions allowing to use and control the SRAM memory
 269
 270 @endverbatim
 271   * @{
 272   */
 273
 274 /**
 275   * @brief  Reads 8-bit buffer from SRAM memory.
 276   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 277   *                the configuration information for SRAM module.
 278   * @param  pAddress: Pointer to read start address
 279   * @param  pDstBuffer: Pointer to destination buffer
 280   * @param  BufferSize: Size of the buffer to read from memory
 281   * @retval HAL status
 282   */
 283 HAL_StatusTypeDef HAL_SRAM_Read_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pDstBuffer, uint32_t BufferSize)
 284 {
 285   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
 286
 287   /* Process Locked */
 288   __HAL_LOCK(hsram);
 289
 290   /* Update the SRAM controller state */
 291   hsram->State = HAL_SRAM_STATE_BUSY;
 292
 293   /* Read data from memory */
 294   for(; BufferSize != 0; BufferSize--)
 295   {
 296     *pDstBuffer = *(__IO uint8_t *)psramaddress;
 297     pDstBuffer++;
 298     psramaddress++;
 299   }
 300
 301   /* Update the SRAM controller state */
 302   hsram->State = HAL_SRAM_STATE_READY;
 303
 304   /* Process unlocked */
 305   __HAL_UNLOCK(hsram);
 306
 307   return HAL_OK;
 308 }
 309
 310 /**
 311   * @brief  Writes 8-bit buffer to SRAM memory.
 312   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 313   *                the configuration information for SRAM module.
 314   * @param  pAddress: Pointer to write start address
 315   * @param  pSrcBuffer: Pointer to source buffer to write
 316   * @param  BufferSize: Size of the buffer to write to memory
 317   * @retval HAL status
 318   */
 319 HAL_StatusTypeDef HAL_SRAM_Write_8b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint8_t *pSrcBuffer, uint32_t BufferSize)
 320 {
 321   __IO uint8_t * psramaddress = (uint8_t *)pAddress;
 322
 323   /* Check the SRAM controller state */
 324   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
 325   {
 326     return  HAL_ERROR;
 327   }
 328
 329   /* Process Locked */
 330   __HAL_LOCK(hsram);
 331
 332   /* Update the SRAM controller state */
 333   hsram->State = HAL_SRAM_STATE_BUSY;
 334
 335   /* Write data to memory */
 336   for(; BufferSize != 0; BufferSize--)
 337   {
 338     *(__IO uint8_t *)psramaddress = *pSrcBuffer;
 339     pSrcBuffer++;
 340     psramaddress++;
 341   }
 342
 343   /* Update the SRAM controller state */
 344   hsram->State = HAL_SRAM_STATE_READY;
 345
 346   /* Process unlocked */
 347   __HAL_UNLOCK(hsram);
 348
 349   return HAL_OK;
 350 }
 351
 352 /**
 353   * @brief  Reads 16-bit buffer from SRAM memory.
 354   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 355   *                the configuration information for SRAM module.
 356   * @param  pAddress: Pointer to read start address
 357   * @param  pDstBuffer: Pointer to destination buffer
 358   * @param  BufferSize: Size of the buffer to read from memory
 359   * @retval HAL status
 360   */
 361 HAL_StatusTypeDef HAL_SRAM_Read_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pDstBuffer, uint32_t BufferSize)
 362 {
 363   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
 364
 365   /* Process Locked */
 366   __HAL_LOCK(hsram);
 367
 368   /* Update the SRAM controller state */
 369   hsram->State = HAL_SRAM_STATE_BUSY;
 370
 371   /* Read data from memory */
 372   for(; BufferSize != 0; BufferSize--)
 373   {
 374     *pDstBuffer = *(__IO uint16_t *)psramaddress;
 375     pDstBuffer++;
 376     psramaddress++;
 377   }
 378
 379   /* Update the SRAM controller state */
 380   hsram->State = HAL_SRAM_STATE_READY;
 381
 382   /* Process unlocked */
 383   __HAL_UNLOCK(hsram);
 384
 385   return HAL_OK;
 386 }
 387
 388 /**
 389   * @brief  Writes 16-bit buffer to SRAM memory.
 390   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 391   *                the configuration information for SRAM module.
 392   * @param  pAddress: Pointer to write start address
 393   * @param  pSrcBuffer: Pointer to source buffer to write
 394   * @param  BufferSize: Size of the buffer to write to memory
 395   * @retval HAL status
 396   */
 397 HAL_StatusTypeDef HAL_SRAM_Write_16b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint16_t *pSrcBuffer, uint32_t BufferSize)
 398 {
 399   __IO uint16_t * psramaddress = (uint16_t *)pAddress;
 400
 401   /* Check the SRAM controller state */
 402   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
 403   {
 404     return  HAL_ERROR;
 405   }
 406
 407   /* Process Locked */
 408   __HAL_LOCK(hsram);
 409
 410   /* Update the SRAM controller state */
 411   hsram->State = HAL_SRAM_STATE_BUSY;
 412
 413   /* Write data to memory */
 414   for(; BufferSize != 0; BufferSize--)
 415   {
 416     *(__IO uint16_t *)psramaddress = *pSrcBuffer;
 417     pSrcBuffer++;
 418     psramaddress++;
 419   }
 420
 421   /* Update the SRAM controller state */
 422   hsram->State = HAL_SRAM_STATE_READY;
 423
 424   /* Process unlocked */
 425   __HAL_UNLOCK(hsram);
 426
 427   return HAL_OK;
 428 }
 429
 430 /**
 431   * @brief  Reads 32-bit buffer from SRAM memory.
 432   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 433   *                the configuration information for SRAM module.
 434   * @param  pAddress: Pointer to read start address
 435   * @param  pDstBuffer: Pointer to destination buffer
 436   * @param  BufferSize: Size of the buffer to read from memory
 437   * @retval HAL status
 438   */
 439 HAL_StatusTypeDef HAL_SRAM_Read_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 440 {
 441   /* Process Locked */
 442   __HAL_LOCK(hsram);
 443
 444   /* Update the SRAM controller state */
 445   hsram->State = HAL_SRAM_STATE_BUSY;
 446
 447   /* Read data from memory */
 448   for(; BufferSize != 0; BufferSize--)
 449   {
 450     *pDstBuffer = *(__IO uint32_t *)pAddress;
 451     pDstBuffer++;
 452     pAddress++;
 453   }
 454
 455   /* Update the SRAM controller state */
 456   hsram->State = HAL_SRAM_STATE_READY;
 457
 458   /* Process unlocked */
 459   __HAL_UNLOCK(hsram);
 460
 461   return HAL_OK;
 462 }
 463
 464 /**
 465   * @brief  Writes 32-bit buffer to SRAM memory.
 466   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 467   *                the configuration information for SRAM module.
 468   * @param  pAddress: Pointer to write start address
 469   * @param  pSrcBuffer: Pointer to source buffer to write
 470   * @param  BufferSize: Size of the buffer to write to memory
 471   * @retval HAL status
 472   */
 473 HAL_StatusTypeDef HAL_SRAM_Write_32b(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 474 {
 475   /* Check the SRAM controller state */
 476   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
 477   {
 478     return  HAL_ERROR;
 479   }
 480
 481   /* Process Locked */
 482   __HAL_LOCK(hsram);
 483
 484   /* Update the SRAM controller state */
 485   hsram->State = HAL_SRAM_STATE_BUSY;
 486
 487   /* Write data to memory */
 488   for(; BufferSize != 0; BufferSize--)
 489   {
 490     *(__IO uint32_t *)pAddress = *pSrcBuffer;
 491     pSrcBuffer++;
 492     pAddress++;
 493   }
 494
 495   /* Update the SRAM controller state */
 496   hsram->State = HAL_SRAM_STATE_READY;
 497
 498   /* Process unlocked */
 499   __HAL_UNLOCK(hsram);
 500
 501   return HAL_OK;
 502 }
 503
 504 /**
 505   * @brief  Reads a Words data from the SRAM memory using DMA transfer.
 506   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 507   *                the configuration information for SRAM module.
 508   * @param  pAddress: Pointer to read start address
 509   * @param  pDstBuffer: Pointer to destination buffer
 510   * @param  BufferSize: Size of the buffer to read from memory
 511   * @retval HAL status
 512   */
 513 HAL_StatusTypeDef HAL_SRAM_Read_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pDstBuffer, uint32_t BufferSize)
 514 {
 515   /* Process Locked */
 516   __HAL_LOCK(hsram);
 517
 518   /* Update the SRAM controller state */
 519   hsram->State = HAL_SRAM_STATE_BUSY;
 520
 521   /* Configure DMA user callbacks */
 522   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
 523   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
 524
 525   /* Enable the DMA Stream */
 526   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pAddress, (uint32_t)pDstBuffer, (uint32_t)BufferSize);
 527
 528   /* Update the SRAM controller state */
 529   hsram->State = HAL_SRAM_STATE_READY;
 530
 531   /* Process unlocked */
 532   __HAL_UNLOCK(hsram);
 533
 534   return HAL_OK;
 535 }
 536
 537 /**
 538   * @brief  Writes a Words data buffer to SRAM memory using DMA transfer.
 539   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 540   *                the configuration information for SRAM module.
 541   * @param  pAddress: Pointer to write start address
 542   * @param  pSrcBuffer: Pointer to source buffer to write
 543   * @param  BufferSize: Size of the buffer to write to memory
 544   * @retval HAL status
 545   */
 546 HAL_StatusTypeDef HAL_SRAM_Write_DMA(SRAM_HandleTypeDef *hsram, uint32_t *pAddress, uint32_t *pSrcBuffer, uint32_t BufferSize)
 547 {
 548   /* Check the SRAM controller state */
 549   if(hsram->State == HAL_SRAM_STATE_PROTECTED)
 550   {
 551     return  HAL_ERROR;
 552   }
 553
 554   /* Process Locked */
 555   __HAL_LOCK(hsram);
 556
 557   /* Update the SRAM controller state */
 558   hsram->State = HAL_SRAM_STATE_BUSY;
 559
 560   /* Configure DMA user callbacks */
 561   hsram->hdma->XferCpltCallback  = HAL_SRAM_DMA_XferCpltCallback;
 562   hsram->hdma->XferErrorCallback = HAL_SRAM_DMA_XferErrorCallback;
 563
 564   /* Enable the DMA Stream */
 565   HAL_DMA_Start_IT(hsram->hdma, (uint32_t)pSrcBuffer, (uint32_t)pAddress, (uint32_t)BufferSize);
 566
 567   /* Update the SRAM controller state */
 568   hsram->State = HAL_SRAM_STATE_READY;
 569
 570   /* Process unlocked */
 571   __HAL_UNLOCK(hsram);
 572
 573   return HAL_OK;
 574 }
 575
 576 /**
 577   * @}
 578   */
 579
 580 /** @defgroup SRAM_Exported_Functions_Group3 Control functions
 581  *  @brief   Control functions
 582  *
 583 @verbatim
 584   ==============================================================================
 585                         ##### SRAM Control functions #####
 586   ==============================================================================
 587   [..]
 588     This subsection provides a set of functions allowing to control dynamically
 589     the SRAM interface.
 590
 591 @endverbatim
 592   * @{
 593   */
 594
 595 /**
 596   * @brief  Enables dynamically SRAM write operation.
 597   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 598   *                the configuration information for SRAM module.
 599   * @retval HAL status
 600   */
 601 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Enable(SRAM_HandleTypeDef *hsram)
 602 {
 603   /* Process Locked */
 604   __HAL_LOCK(hsram);
 605
 606   /* Enable write operation */
 607   FMC_NORSRAM_WriteOperation_Enable(hsram->Instance, hsram->Init.NSBank);
 608
 609   /* Update the SRAM controller state */
 610   hsram->State = HAL_SRAM_STATE_READY;
 611
 612   /* Process unlocked */
 613   __HAL_UNLOCK(hsram);
 614
 615   return HAL_OK;
 616 }
 617
 618 /**
 619   * @brief  Disables dynamically SRAM write operation.
 620   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 621   *                the configuration information for SRAM module.
 622   * @retval HAL status
 623   */
 624 HAL_StatusTypeDef HAL_SRAM_WriteOperation_Disable(SRAM_HandleTypeDef *hsram)
 625 {
 626   /* Process Locked */
 627   __HAL_LOCK(hsram);
 628
 629   /* Update the SRAM controller state */
 630   hsram->State = HAL_SRAM_STATE_BUSY;
 631
 632   /* Disable write operation */
 633   FMC_NORSRAM_WriteOperation_Disable(hsram->Instance, hsram->Init.NSBank);
 634
 635   /* Update the SRAM controller state */
 636   hsram->State = HAL_SRAM_STATE_PROTECTED;
 637
 638   /* Process unlocked */
 639   __HAL_UNLOCK(hsram);
 640
 641   return HAL_OK;
 642 }
 643
 644 /**
 645   * @}
 646   */
 647
 648 /** @defgroup SRAM_Exported_Functions_Group4 Peripheral State functions
 649  *  @brief   Peripheral State functions
 650  *
 651 @verbatim
 652   ==============================================================================
 653                       ##### SRAM State functions #####
 654   ==============================================================================
 655   [..]
 656     This subsection permits to get in run-time the status of the SRAM controller
 657     and the data flow.
 658
 659 @endverbatim
 660   * @{
 661   */
 662
 663 /**
 664   * @brief  Returns the SRAM controller state
 665   * @param  hsram: pointer to a SRAM_HandleTypeDef structure that contains
 666   *                the configuration information for SRAM module.
 667   * @retval HAL state
 668   */
 669 HAL_SRAM_StateTypeDef HAL_SRAM_GetState(SRAM_HandleTypeDef *hsram)
 670 {
 671   return hsram->State;
 672 }
 673
 674 /**
 675   * @}
 676   */
 677
 678 /**
 679   * @}
 680   */
 681 #endif /* HAL_SRAM_MODULE_ENABLED */
 682 /**
 683   * @}
 684   */
 685
 686 /**
 687   * @}
 688   */
 689
 690 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/