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Merge pull request #10558 from iNavFlight/MrD_Correct-comments-on-OSD-symbols
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_adc.c
blob653691abac8f3800cb58a2cfe5f7179f2d80c052
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_adc.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief ADC LL module driver
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f7xx_ll_adc.h"
41 #include "stm32f7xx_ll_bus.h"
42
43 #ifdef USE_FULL_ASSERT
44 #include "stm32_assert.h"
45 #else
46 #define assert_param(expr) ((void)0U)
47 #endif
48
49 /** @addtogroup STM32F7xx_LL_Driver
50 * @{
51 */
52
53 #if defined (ADC1) || defined (ADC2) || defined (ADC3)
54
55 /** @addtogroup ADC_LL ADC
56 * @{
57 */
58
59 /* Private types -------------------------------------------------------------*/
60 /* Private variables ---------------------------------------------------------*/
61 /* Private constants ---------------------------------------------------------*/
62 /* Private macros ------------------------------------------------------------*/
63
64 /** @addtogroup ADC_LL_Private_Macros
65 * @{
66 */
67
68 /* Check of parameters for configuration of ADC hierarchical scope: */
69 /* common to several ADC instances. */
70 #define IS_LL_ADC_COMMON_CLOCK(__CLOCK__) \
71 ( ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV2) \
72 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV4) \
73 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV6) \
74 || ((__CLOCK__) == LL_ADC_CLOCK_SYNC_PCLK_DIV8) \
75 )
76
77 /* Check of parameters for configuration of ADC hierarchical scope: */
78 /* ADC instance. */
79 #define IS_LL_ADC_RESOLUTION(__RESOLUTION__) \
80 ( ((__RESOLUTION__) == LL_ADC_RESOLUTION_12B) \
81 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_10B) \
82 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_8B) \
83 || ((__RESOLUTION__) == LL_ADC_RESOLUTION_6B) \
84 )
85
86 #define IS_LL_ADC_DATA_ALIGN(__DATA_ALIGN__) \
87 ( ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_RIGHT) \
88 || ((__DATA_ALIGN__) == LL_ADC_DATA_ALIGN_LEFT) \
89 )
90
91 #define IS_LL_ADC_SCAN_SELECTION(__SCAN_SELECTION__) \
92 ( ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_DISABLE) \
93 || ((__SCAN_SELECTION__) == LL_ADC_SEQ_SCAN_ENABLE) \
94 )
95
96 #define IS_LL_ADC_SEQ_SCAN_MODE(__SEQ_SCAN_MODE__) \
97 ( ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_DISABLE) \
98 || ((__SCAN_MODE__) == LL_ADC_SEQ_SCAN_ENABLE) \
99 )
100
101 /* Check of parameters for configuration of ADC hierarchical scope: */
102 /* ADC group regular */
103 #define IS_LL_ADC_REG_TRIG_SOURCE(__REG_TRIG_SOURCE__) \
104 ( ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_SOFTWARE) \
105 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH1) \
106 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH2) \
107 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_CH3) \
108 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_CH2) \
109 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM5_TRGO) \
110 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_CH4) \
111 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM3_CH4) \
112 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM8_TRGO) \
113 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO) \
114 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM1_TRGO2) \
115 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM2_TRGO) \
116 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM4_TRGO) \
117 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_TIM6_TRGO) \
118 || ((__REG_TRIG_SOURCE__) == LL_ADC_REG_TRIG_EXT_EXTI_LINE11) \
119 )
120
121 #define IS_LL_ADC_REG_CONTINUOUS_MODE(__REG_CONTINUOUS_MODE__) \
122 ( ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_SINGLE) \
123 || ((__REG_CONTINUOUS_MODE__) == LL_ADC_REG_CONV_CONTINUOUS) \
124 )
125
126 #define IS_LL_ADC_REG_DMA_TRANSFER(__REG_DMA_TRANSFER__) \
127 ( ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_NONE) \
128 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_LIMITED) \
129 || ((__REG_DMA_TRANSFER__) == LL_ADC_REG_DMA_TRANSFER_UNLIMITED) \
130 )
131
132 #define IS_LL_ADC_REG_FLAG_EOC_SELECTION(__REG_FLAG_EOC_SELECTION__) \
133 ( ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_SEQUENCE_CONV) \
134 || ((__REG_FLAG_EOC_SELECTION__) == LL_ADC_REG_FLAG_EOC_UNITARY_CONV) \
135 )
136
137 #define IS_LL_ADC_REG_SEQ_SCAN_LENGTH(__REG_SEQ_SCAN_LENGTH__) \
138 ( ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_DISABLE) \
139 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_2RANKS) \
140 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_3RANKS) \
141 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_4RANKS) \
142 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_5RANKS) \
143 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_6RANKS) \
144 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_7RANKS) \
145 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_8RANKS) \
146 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_9RANKS) \
147 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_10RANKS) \
148 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_11RANKS) \
149 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_12RANKS) \
150 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_13RANKS) \
151 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_14RANKS) \
152 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_15RANKS) \
153 || ((__REG_SEQ_SCAN_LENGTH__) == LL_ADC_REG_SEQ_SCAN_ENABLE_16RANKS) \
154 )
155
156 #define IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(__REG_SEQ_DISCONT_MODE__) \
157 ( ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_DISABLE) \
158 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_1RANK) \
159 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_2RANKS) \
160 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_3RANKS) \
161 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_4RANKS) \
162 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_5RANKS) \
163 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_6RANKS) \
164 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_7RANKS) \
165 || ((__REG_SEQ_DISCONT_MODE__) == LL_ADC_REG_SEQ_DISCONT_8RANKS) \
166 )
167
168 /* Check of parameters for configuration of ADC hierarchical scope: */
169 /* ADC group injected */
170 #define IS_LL_ADC_INJ_TRIG_SOURCE(__INJ_TRIG_SOURCE__) \
171 ( ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_SOFTWARE) \
172 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO) \
173 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_CH4) \
174 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_TRGO) \
175 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM2_CH1) \
176 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH4) \
177 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM4_TRGO) \
178 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_CH4) \
179 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM1_TRGO2) \
180 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO) \
181 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM8_TRGO2) \
182 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH3) \
183 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM5_TRGO) \
184 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM3_CH1) \
185 || ((__INJ_TRIG_SOURCE__) == LL_ADC_INJ_TRIG_EXT_TIM6_TRGO) \
186 )
187 #define IS_LL_ADC_INJ_TRIG_EXT_EDGE(__INJ_TRIG_EXT_EDGE__) \
188 ( ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISING) \
189 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_FALLING) \
190 || ((__INJ_TRIG_EXT_EDGE__) == LL_ADC_INJ_TRIG_EXT_RISINGFALLING) \
191 )
192
193 #define IS_LL_ADC_INJ_TRIG_AUTO(__INJ_TRIG_AUTO__) \
194 ( ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_INDEPENDENT) \
195 || ((__INJ_TRIG_AUTO__) == LL_ADC_INJ_TRIG_FROM_GRP_REGULAR) \
196 )
197
198 #define IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(__INJ_SEQ_SCAN_LENGTH__) \
199 ( ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_DISABLE) \
200 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_2RANKS) \
201 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_3RANKS) \
202 || ((__INJ_SEQ_SCAN_LENGTH__) == LL_ADC_INJ_SEQ_SCAN_ENABLE_4RANKS) \
203 )
204
205 #define IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(__INJ_SEQ_DISCONT_MODE__) \
206 ( ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_DISABLE) \
207 || ((__INJ_SEQ_DISCONT_MODE__) == LL_ADC_INJ_SEQ_DISCONT_1RANK) \
208 )
209
210 /* Check of parameters for configuration of ADC hierarchical scope: */
211 /* multimode. */
212 #if defined(ADC3)
213 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
214 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
215 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
216 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
217 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
218 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
219 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
220 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
221 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
222 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_SIM) \
223 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIM_INJ_ALT) \
224 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_SIMULT) \
225 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_SIMULT) \
226 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_REG_INTERL) \
227 || ((__MULTI_MODE__) == LL_ADC_MULTI_TRIPLE_INJ_ALTERN) \
228 )
229 #else
230 #define IS_LL_ADC_MULTI_MODE(__MULTI_MODE__) \
231 ( ((__MULTI_MODE__) == LL_ADC_MULTI_INDEPENDENT) \
232 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIMULT) \
233 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INTERL) \
234 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_SIMULT) \
235 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_INJ_ALTERN) \
236 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_SIM) \
237 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_SIM_INJ_ALT) \
238 || ((__MULTI_MODE__) == LL_ADC_MULTI_DUAL_REG_INT_INJ_SIM) \
239 )
240 #endif
241
242 #define IS_LL_ADC_MULTI_DMA_TRANSFER(__MULTI_DMA_TRANSFER__) \
243 ( ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_EACH_ADC) \
244 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_1) \
245 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_2) \
246 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_LIMIT_3) \
247 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_1) \
248 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_2) \
249 || ((__MULTI_DMA_TRANSFER__) == LL_ADC_MULTI_REG_DMA_UNLMT_3) \
250 )
251
252 #define IS_LL_ADC_MULTI_TWOSMP_DELAY(__MULTI_TWOSMP_DELAY__) \
253 ( ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES) \
254 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_6CYCLES) \
255 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_7CYCLES) \
256 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_8CYCLES) \
257 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_9CYCLES) \
258 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_10CYCLES) \
259 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_11CYCLES) \
260 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_12CYCLES) \
261 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_13CYCLES) \
262 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_14CYCLES) \
263 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_15CYCLES) \
264 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_16CYCLES) \
265 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_17CYCLES) \
266 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_18CYCLES) \
267 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_19CYCLES) \
268 || ((__MULTI_TWOSMP_DELAY__) == LL_ADC_MULTI_TWOSMP_DELAY_20CYCLES) \
269 )
270
271 #define IS_LL_ADC_MULTI_MASTER_SLAVE(__MULTI_MASTER_SLAVE__) \
272 ( ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER) \
273 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_SLAVE) \
274 || ((__MULTI_MASTER_SLAVE__) == LL_ADC_MULTI_MASTER_SLAVE) \
275 )
276
277 /**
278 * @}
279 */
280
281
282 /* Private function prototypes -----------------------------------------------*/
283
284 /* Exported functions --------------------------------------------------------*/
285 /** @addtogroup ADC_LL_Exported_Functions
286 * @{
287 */
288
289 /** @addtogroup ADC_LL_EF_Init
290 * @{
291 */
292
293 /**
294 * @brief De-initialize registers of all ADC instances belonging to
295 * the same ADC common instance to their default reset values.
296 * @param ADCxy_COMMON ADC common instance
297 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
298 * @retval An ErrorStatus enumeration value:
299 * - SUCCESS: ADC common registers are de-initialized
300 * - ERROR: not applicable
301 */
302 ErrorStatus LL_ADC_CommonDeInit(ADC_Common_TypeDef *ADCxy_COMMON)
303 {
304 /* Check the parameters */
305 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
306
307
308 /* Force reset of ADC clock (core clock) */
309 LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_ADC);
310
311 /* Release reset of ADC clock (core clock) */
312 LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_ADC);
313
314 return SUCCESS;
315 }
316
317 /**
318 * @brief Initialize some features of ADC common parameters
319 * (all ADC instances belonging to the same ADC common instance)
320 * and multimode (for devices with several ADC instances available).
321 * @note The setting of ADC common parameters is conditioned to
322 * ADC instances state:
323 * All ADC instances belonging to the same ADC common instance
324 * must be disabled.
325 * @param ADCxy_COMMON ADC common instance
326 * (can be set directly from CMSIS definition or by using helper macro @ref __LL_ADC_COMMON_INSTANCE() )
327 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
328 * @retval An ErrorStatus enumeration value:
329 * - SUCCESS: ADC common registers are initialized
330 * - ERROR: ADC common registers are not initialized
331 */
332 ErrorStatus LL_ADC_CommonInit(ADC_Common_TypeDef *ADCxy_COMMON, LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
333 {
334 ErrorStatus status = SUCCESS;
335
336 /* Check the parameters */
337 assert_param(IS_ADC_COMMON_INSTANCE(ADCxy_COMMON));
338 assert_param(IS_LL_ADC_COMMON_CLOCK(ADC_CommonInitStruct->CommonClock));
339
340 assert_param(IS_LL_ADC_MULTI_MODE(ADC_CommonInitStruct->Multimode));
341 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
342 {
343 assert_param(IS_LL_ADC_MULTI_DMA_TRANSFER(ADC_CommonInitStruct->MultiDMATransfer));
344 assert_param(IS_LL_ADC_MULTI_TWOSMP_DELAY(ADC_CommonInitStruct->MultiTwoSamplingDelay));
345 }
346
347 /* Note: Hardware constraint (refer to description of functions */
348 /* "LL_ADC_SetCommonXXX()" and "LL_ADC_SetMultiXXX()"): */
349 /* On this STM32 serie, setting of these features is conditioned to */
350 /* ADC state: */
351 /* All ADC instances of the ADC common group must be disabled. */
352 if(__LL_ADC_IS_ENABLED_ALL_COMMON_INSTANCE(ADCxy_COMMON) == 0U)
353 {
354 /* Configuration of ADC hierarchical scope: */
355 /* - common to several ADC */
356 /* (all ADC instances belonging to the same ADC common instance) */
357 /* - Set ADC clock (conversion clock) */
358 /* - multimode (if several ADC instances available on the */
359 /* selected device) */
360 /* - Set ADC multimode configuration */
361 /* - Set ADC multimode DMA transfer */
362 /* - Set ADC multimode: delay between 2 sampling phases */
363 if(ADC_CommonInitStruct->Multimode != LL_ADC_MULTI_INDEPENDENT)
364 {
365 MODIFY_REG(ADCxy_COMMON->CCR,
366 ADC_CCR_ADCPRE
367 | ADC_CCR_MULTI
368 | ADC_CCR_DMA
369 | ADC_CCR_DDS
370 | ADC_CCR_DELAY
371 ,
372 ADC_CommonInitStruct->CommonClock
373 | ADC_CommonInitStruct->Multimode
374 | ADC_CommonInitStruct->MultiDMATransfer
375 | ADC_CommonInitStruct->MultiTwoSamplingDelay
376 );
377 }
378 else
379 {
380 MODIFY_REG(ADCxy_COMMON->CCR,
381 ADC_CCR_ADCPRE
382 | ADC_CCR_MULTI
383 | ADC_CCR_DMA
384 | ADC_CCR_DDS
385 | ADC_CCR_DELAY
386 ,
387 ADC_CommonInitStruct->CommonClock
388 | LL_ADC_MULTI_INDEPENDENT
389 );
390 }
391 }
392 else
393 {
394 /* Initialization error: One or several ADC instances belonging to */
395 /* the same ADC common instance are not disabled. */
396 status = ERROR;
397 }
398
399 return status;
400 }
401
402 /**
403 * @brief Set each @ref LL_ADC_CommonInitTypeDef field to default value.
404 * @param ADC_CommonInitStruct Pointer to a @ref LL_ADC_CommonInitTypeDef structure
405 * whose fields will be set to default values.
406 * @retval None
407 */
408 void LL_ADC_CommonStructInit(LL_ADC_CommonInitTypeDef *ADC_CommonInitStruct)
409 {
410 /* Set ADC_CommonInitStruct fields to default values */
411 /* Set fields of ADC common */
412 /* (all ADC instances belonging to the same ADC common instance) */
413 ADC_CommonInitStruct->CommonClock = LL_ADC_CLOCK_SYNC_PCLK_DIV2;
414
415 /* Set fields of ADC multimode */
416 ADC_CommonInitStruct->Multimode = LL_ADC_MULTI_INDEPENDENT;
417 ADC_CommonInitStruct->MultiDMATransfer = LL_ADC_MULTI_REG_DMA_EACH_ADC;
418 ADC_CommonInitStruct->MultiTwoSamplingDelay = LL_ADC_MULTI_TWOSMP_DELAY_5CYCLES;
419 }
420
421 /**
422 * @brief De-initialize registers of the selected ADC instance
423 * to their default reset values.
424 * @note To reset all ADC instances quickly (perform a hard reset),
425 * use function @ref LL_ADC_CommonDeInit().
426 * @param ADCx ADC instance
427 * @retval An ErrorStatus enumeration value:
428 * - SUCCESS: ADC registers are de-initialized
429 * - ERROR: ADC registers are not de-initialized
430 */
431 ErrorStatus LL_ADC_DeInit(ADC_TypeDef *ADCx)
432 {
433 ErrorStatus status = SUCCESS;
434
435 /* Check the parameters */
436 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
437
438 /* Disable ADC instance if not already disabled. */
439 if(LL_ADC_IsEnabled(ADCx) == 1U)
440 {
441 /* Set ADC group regular trigger source to SW start to ensure to not */
442 /* have an external trigger event occurring during the conversion stop */
443 /* ADC disable process. */
444 LL_ADC_REG_SetTriggerSource(ADCx, LL_ADC_REG_TRIG_SOFTWARE);
445
446 /* Set ADC group injected trigger source to SW start to ensure to not */
447 /* have an external trigger event occurring during the conversion stop */
448 /* ADC disable process. */
449 LL_ADC_INJ_SetTriggerSource(ADCx, LL_ADC_INJ_TRIG_SOFTWARE);
450
451 /* Disable the ADC instance */
452 LL_ADC_Disable(ADCx);
453 }
454
455 /* Check whether ADC state is compliant with expected state */
456 /* (hardware requirements of bits state to reset registers below) */
457 if(READ_BIT(ADCx->CR2, ADC_CR2_ADON) == 0U)
458 {
459 /* ========== Reset ADC registers ========== */
460 /* Reset register SR */
461 CLEAR_BIT(ADCx->SR,
462 ( LL_ADC_FLAG_STRT
463 | LL_ADC_FLAG_JSTRT
464 | LL_ADC_FLAG_EOCS
465 | LL_ADC_FLAG_OVR
466 | LL_ADC_FLAG_JEOS
467 | LL_ADC_FLAG_AWD1 )
468 );
469
470 /* Reset register CR1 */
471 CLEAR_BIT(ADCx->CR1,
472 ( ADC_CR1_OVRIE | ADC_CR1_RES | ADC_CR1_AWDEN
473 | ADC_CR1_JAWDEN
474 | ADC_CR1_DISCNUM | ADC_CR1_JDISCEN | ADC_CR1_DISCEN
475 | ADC_CR1_JAUTO | ADC_CR1_AWDSGL | ADC_CR1_SCAN
476 | ADC_CR1_JEOCIE | ADC_CR1_AWDIE | ADC_CR1_EOCIE
477 | ADC_CR1_AWDCH )
478 );
479
480 /* Reset register CR2 */
481 CLEAR_BIT(ADCx->CR2,
482 ( ADC_CR2_SWSTART | ADC_CR2_EXTEN | ADC_CR2_EXTSEL
483 | ADC_CR2_JSWSTART | ADC_CR2_JEXTEN | ADC_CR2_JEXTSEL
484 | ADC_CR2_ALIGN | ADC_CR2_EOCS
485 | ADC_CR2_DDS | ADC_CR2_DMA
486 | ADC_CR2_CONT | ADC_CR2_ADON )
487 );
488
489 /* Reset register SMPR1 */
490 CLEAR_BIT(ADCx->SMPR1,
491 ( ADC_SMPR1_SMP18 | ADC_SMPR1_SMP17 | ADC_SMPR1_SMP16
492 | ADC_SMPR1_SMP15 | ADC_SMPR1_SMP14 | ADC_SMPR1_SMP13
493 | ADC_SMPR1_SMP12 | ADC_SMPR1_SMP11 | ADC_SMPR1_SMP10)
494 );
495
496 /* Reset register SMPR2 */
497 CLEAR_BIT(ADCx->SMPR2,
498 ( ADC_SMPR2_SMP9
499 | ADC_SMPR2_SMP8 | ADC_SMPR2_SMP7 | ADC_SMPR2_SMP6
500 | ADC_SMPR2_SMP5 | ADC_SMPR2_SMP4 | ADC_SMPR2_SMP3
501 | ADC_SMPR2_SMP2 | ADC_SMPR2_SMP1 | ADC_SMPR2_SMP0)
502 );
503
504 /* Reset register JOFR1 */
505 CLEAR_BIT(ADCx->JOFR1, ADC_JOFR1_JOFFSET1);
506 /* Reset register JOFR2 */
507 CLEAR_BIT(ADCx->JOFR2, ADC_JOFR2_JOFFSET2);
508 /* Reset register JOFR3 */
509 CLEAR_BIT(ADCx->JOFR3, ADC_JOFR3_JOFFSET3);
510 /* Reset register JOFR4 */
511 CLEAR_BIT(ADCx->JOFR4, ADC_JOFR4_JOFFSET4);
512
513 /* Reset register HTR */
514 SET_BIT(ADCx->HTR, ADC_HTR_HT);
515 /* Reset register LTR */
516 CLEAR_BIT(ADCx->LTR, ADC_LTR_LT);
517
518 /* Reset register SQR1 */
519 CLEAR_BIT(ADCx->SQR1,
520 ( ADC_SQR1_L
521 | ADC_SQR1_SQ16
522 | ADC_SQR1_SQ15 | ADC_SQR1_SQ14 | ADC_SQR1_SQ13)
523 );
524
525 /* Reset register SQR2 */
526 CLEAR_BIT(ADCx->SQR2,
527 ( ADC_SQR2_SQ12 | ADC_SQR2_SQ11 | ADC_SQR2_SQ10
528 | ADC_SQR2_SQ9 | ADC_SQR2_SQ8 | ADC_SQR2_SQ7)
529 );
530
531
532 /* Reset register JSQR */
533 CLEAR_BIT(ADCx->JSQR,
534 ( ADC_JSQR_JL
535 | ADC_JSQR_JSQ4 | ADC_JSQR_JSQ3
536 | ADC_JSQR_JSQ2 | ADC_JSQR_JSQ1 )
537 );
538
539 /* Reset register DR */
540 /* bits in access mode read only, no direct reset applicable */
541
542 /* Reset registers JDR1, JDR2, JDR3, JDR4 */
543 /* bits in access mode read only, no direct reset applicable */
544
545 /* Reset register CCR */
546 CLEAR_BIT(ADC->CCR, ADC_CCR_TSVREFE | ADC_CCR_ADCPRE);
547 }
548
549 return status;
550 }
551
552 /**
553 * @brief Initialize some features of ADC instance.
554 * @note These parameters have an impact on ADC scope: ADC instance.
555 * Affects both group regular and group injected (availability
556 * of ADC group injected depends on STM32 families).
557 * Refer to corresponding unitary functions into
558 * @ref ADC_LL_EF_Configuration_ADC_Instance .
559 * @note The setting of these parameters by function @ref LL_ADC_Init()
560 * is conditioned to ADC state:
561 * ADC instance must be disabled.
562 * This condition is applied to all ADC features, for efficiency
563 * and compatibility over all STM32 families. However, the different
564 * features can be set under different ADC state conditions
565 * (setting possible with ADC enabled without conversion on going,
566 * ADC enabled with conversion on going, ...)
567 * Each feature can be updated afterwards with a unitary function
568 * and potentially with ADC in a different state than disabled,
569 * refer to description of each function for setting
570 * conditioned to ADC state.
571 * @note After using this function, some other features must be configured
572 * using LL unitary functions.
573 * The minimum configuration remaining to be done is:
574 * - Set ADC group regular or group injected sequencer:
575 * map channel on the selected sequencer rank.
576 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
577 * - Set ADC channel sampling time
578 * Refer to function LL_ADC_SetChannelSamplingTime();
579 * @param ADCx ADC instance
580 * @param ADC_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
581 * @retval An ErrorStatus enumeration value:
582 * - SUCCESS: ADC registers are initialized
583 * - ERROR: ADC registers are not initialized
584 */
585 ErrorStatus LL_ADC_Init(ADC_TypeDef *ADCx, LL_ADC_InitTypeDef *ADC_InitStruct)
586 {
587 ErrorStatus status = SUCCESS;
588
589 /* Check the parameters */
590 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
591
592 assert_param(IS_LL_ADC_RESOLUTION(ADC_InitStruct->Resolution));
593 assert_param(IS_LL_ADC_DATA_ALIGN(ADC_InitStruct->DataAlignment));
594 assert_param(IS_LL_ADC_SCAN_SELECTION(ADC_InitStruct->SequencersScanMode));
595
596 /* Note: Hardware constraint (refer to description of this function): */
597 /* ADC instance must be disabled. */
598 if(LL_ADC_IsEnabled(ADCx) == 0U)
599 {
600 /* Configuration of ADC hierarchical scope: */
601 /* - ADC instance */
602 /* - Set ADC data resolution */
603 /* - Set ADC conversion data alignment */
604 MODIFY_REG(ADCx->CR1,
605 ADC_CR1_RES
606 | ADC_CR1_SCAN
607 ,
608 ADC_InitStruct->Resolution
609 | ADC_InitStruct->SequencersScanMode
610 );
611
612 MODIFY_REG(ADCx->CR2,
613 ADC_CR2_ALIGN
614 ,
615 ADC_InitStruct->DataAlignment
616 );
617
618 }
619 else
620 {
621 /* Initialization error: ADC instance is not disabled. */
622 status = ERROR;
623 }
624 return status;
625 }
626
627 /**
628 * @brief Set each @ref LL_ADC_InitTypeDef field to default value.
629 * @param ADC_InitStruct Pointer to a @ref LL_ADC_InitTypeDef structure
630 * whose fields will be set to default values.
631 * @retval None
632 */
633 void LL_ADC_StructInit(LL_ADC_InitTypeDef *ADC_InitStruct)
634 {
635 /* Set ADC_InitStruct fields to default values */
636 /* Set fields of ADC instance */
637 ADC_InitStruct->Resolution = LL_ADC_RESOLUTION_12B;
638 ADC_InitStruct->DataAlignment = LL_ADC_DATA_ALIGN_RIGHT;
639
640 /* Enable scan mode to have a generic behavior with ADC of other */
641 /* STM32 families, without this setting available: */
642 /* ADC group regular sequencer and ADC group injected sequencer depend */
643 /* only of their own configuration. */
644 ADC_InitStruct->SequencersScanMode = LL_ADC_SEQ_SCAN_ENABLE;
645
646 }
647
648 /**
649 * @brief Initialize some features of ADC group regular.
650 * @note These parameters have an impact on ADC scope: ADC group regular.
651 * Refer to corresponding unitary functions into
652 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
653 * (functions with prefix "REG").
654 * @note The setting of these parameters by function @ref LL_ADC_Init()
655 * is conditioned to ADC state:
656 * ADC instance must be disabled.
657 * This condition is applied to all ADC features, for efficiency
658 * and compatibility over all STM32 families. However, the different
659 * features can be set under different ADC state conditions
660 * (setting possible with ADC enabled without conversion on going,
661 * ADC enabled with conversion on going, ...)
662 * Each feature can be updated afterwards with a unitary function
663 * and potentially with ADC in a different state than disabled,
664 * refer to description of each function for setting
665 * conditioned to ADC state.
666 * @note After using this function, other features must be configured
667 * using LL unitary functions.
668 * The minimum configuration remaining to be done is:
669 * - Set ADC group regular or group injected sequencer:
670 * map channel on the selected sequencer rank.
671 * Refer to function @ref LL_ADC_REG_SetSequencerRanks().
672 * - Set ADC channel sampling time
673 * Refer to function LL_ADC_SetChannelSamplingTime();
674 * @param ADCx ADC instance
675 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
676 * @retval An ErrorStatus enumeration value:
677 * - SUCCESS: ADC registers are initialized
678 * - ERROR: ADC registers are not initialized
679 */
680 ErrorStatus LL_ADC_REG_Init(ADC_TypeDef *ADCx, LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
681 {
682 ErrorStatus status = SUCCESS;
683
684 /* Check the parameters */
685 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
686 assert_param(IS_LL_ADC_REG_TRIG_SOURCE(ADC_REG_InitStruct->TriggerSource));
687 assert_param(IS_LL_ADC_REG_SEQ_SCAN_LENGTH(ADC_REG_InitStruct->SequencerLength));
688 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
689 {
690 assert_param(IS_LL_ADC_REG_SEQ_SCAN_DISCONT_MODE(ADC_REG_InitStruct->SequencerDiscont));
691 }
692 assert_param(IS_LL_ADC_REG_CONTINUOUS_MODE(ADC_REG_InitStruct->ContinuousMode));
693 assert_param(IS_LL_ADC_REG_DMA_TRANSFER(ADC_REG_InitStruct->DMATransfer));
694
695 /* Note: Hardware constraint (refer to description of this function): */
696 /* ADC instance must be disabled. */
697 if(LL_ADC_IsEnabled(ADCx) == 0U)
698 {
699 /* Configuration of ADC hierarchical scope: */
700 /* - ADC group regular */
701 /* - Set ADC group regular trigger source */
702 /* - Set ADC group regular sequencer length */
703 /* - Set ADC group regular sequencer discontinuous mode */
704 /* - Set ADC group regular continuous mode */
705 /* - Set ADC group regular conversion data transfer: no transfer or */
706 /* transfer by DMA, and DMA requests mode */
707 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
708 /* ADC conversion. */
709 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
710 if(ADC_REG_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
711 {
712 MODIFY_REG(ADCx->CR1,
713 ADC_CR1_DISCEN
714 | ADC_CR1_DISCNUM
715 ,
716 ADC_REG_InitStruct->SequencerLength
717 | ADC_REG_InitStruct->SequencerDiscont
718 );
719 }
720 else
721 {
722 MODIFY_REG(ADCx->CR1,
723 ADC_CR1_DISCEN
724 | ADC_CR1_DISCNUM
725 ,
726 ADC_REG_InitStruct->SequencerLength
727 | LL_ADC_REG_SEQ_DISCONT_DISABLE
728 );
729 }
730
731 MODIFY_REG(ADCx->CR2,
732 ADC_CR2_EXTSEL
733 | ADC_CR2_EXTEN
734 | ADC_CR2_CONT
735 | ADC_CR2_DMA
736 | ADC_CR2_DDS
737 ,
738 (ADC_REG_InitStruct->TriggerSource & ADC_CR2_EXTSEL)
739 | ADC_REG_InitStruct->ContinuousMode
740 | ADC_REG_InitStruct->DMATransfer
741 );
742
743 /* Set ADC group regular sequencer length and scan direction */
744 /* Note: Hardware constraint (refer to description of this function): */
745 /* Note: If ADC instance feature scan mode is disabled */
746 /* (refer to ADC instance initialization structure */
747 /* parameter @ref SequencersScanMode */
748 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
749 /* this parameter is discarded. */
750 LL_ADC_REG_SetSequencerLength(ADCx, ADC_REG_InitStruct->SequencerLength);
751 }
752 else
753 {
754 /* Initialization error: ADC instance is not disabled. */
755 status = ERROR;
756 }
757 return status;
758 }
759
760 /**
761 * @brief Set each @ref LL_ADC_REG_InitTypeDef field to default value.
762 * @param ADC_REG_InitStruct Pointer to a @ref LL_ADC_REG_InitTypeDef structure
763 * whose fields will be set to default values.
764 * @retval None
765 */
766 void LL_ADC_REG_StructInit(LL_ADC_REG_InitTypeDef *ADC_REG_InitStruct)
767 {
768 /* Set ADC_REG_InitStruct fields to default values */
769 /* Set fields of ADC group regular */
770 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
771 /* ADC conversion. */
772 /* Refer to function @ref LL_ADC_REG_StartConversionExtTrig(). */
773 ADC_REG_InitStruct->TriggerSource = LL_ADC_REG_TRIG_SOFTWARE;
774 ADC_REG_InitStruct->SequencerLength = LL_ADC_REG_SEQ_SCAN_DISABLE;
775 ADC_REG_InitStruct->SequencerDiscont = LL_ADC_REG_SEQ_DISCONT_DISABLE;
776 ADC_REG_InitStruct->ContinuousMode = LL_ADC_REG_CONV_SINGLE;
777 ADC_REG_InitStruct->DMATransfer = LL_ADC_REG_DMA_TRANSFER_NONE;
778 }
779
780 /**
781 * @brief Initialize some features of ADC group injected.
782 * @note These parameters have an impact on ADC scope: ADC group injected.
783 * Refer to corresponding unitary functions into
784 * @ref ADC_LL_EF_Configuration_ADC_Group_Regular
785 * (functions with prefix "INJ").
786 * @note The setting of these parameters by function @ref LL_ADC_Init()
787 * is conditioned to ADC state:
788 * ADC instance must be disabled.
789 * This condition is applied to all ADC features, for efficiency
790 * and compatibility over all STM32 families. However, the different
791 * features can be set under different ADC state conditions
792 * (setting possible with ADC enabled without conversion on going,
793 * ADC enabled with conversion on going, ...)
794 * Each feature can be updated afterwards with a unitary function
795 * and potentially with ADC in a different state than disabled,
796 * refer to description of each function for setting
797 * conditioned to ADC state.
798 * @note After using this function, other features must be configured
799 * using LL unitary functions.
800 * The minimum configuration remaining to be done is:
801 * - Set ADC group injected sequencer:
802 * map channel on the selected sequencer rank.
803 * Refer to function @ref LL_ADC_INJ_SetSequencerRanks().
804 * - Set ADC channel sampling time
805 * Refer to function LL_ADC_SetChannelSamplingTime();
806 * @param ADCx ADC instance
807 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
808 * @retval An ErrorStatus enumeration value:
809 * - SUCCESS: ADC registers are initialized
810 * - ERROR: ADC registers are not initialized
811 */
812 ErrorStatus LL_ADC_INJ_Init(ADC_TypeDef *ADCx, LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
813 {
814 ErrorStatus status = SUCCESS;
815
816 /* Check the parameters */
817 assert_param(IS_ADC_ALL_INSTANCE(ADCx));
818 assert_param(IS_LL_ADC_INJ_TRIG_SOURCE(ADC_INJ_InitStruct->TriggerSource));
819 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_LENGTH(ADC_INJ_InitStruct->SequencerLength));
820 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_INJ_SEQ_SCAN_DISABLE)
821 {
822 assert_param(IS_LL_ADC_INJ_SEQ_SCAN_DISCONT_MODE(ADC_INJ_InitStruct->SequencerDiscont));
823 }
824 assert_param(IS_LL_ADC_INJ_TRIG_AUTO(ADC_INJ_InitStruct->TrigAuto));
825
826 /* Note: Hardware constraint (refer to description of this function): */
827 /* ADC instance must be disabled. */
828 if(LL_ADC_IsEnabled(ADCx) == 0U)
829 {
830 /* Configuration of ADC hierarchical scope: */
831 /* - ADC group injected */
832 /* - Set ADC group injected trigger source */
833 /* - Set ADC group injected sequencer length */
834 /* - Set ADC group injected sequencer discontinuous mode */
835 /* - Set ADC group injected conversion trigger: independent or */
836 /* from ADC group regular */
837 /* Note: On this STM32 serie, ADC trigger edge is set when starting */
838 /* ADC conversion. */
839 /* Refer to function @ref LL_ADC_INJ_StartConversionExtTrig(). */
840 if(ADC_INJ_InitStruct->SequencerLength != LL_ADC_REG_SEQ_SCAN_DISABLE)
841 {
842 MODIFY_REG(ADCx->CR1,
843 ADC_CR1_JDISCEN
844 | ADC_CR1_JAUTO
845 ,
846 ADC_INJ_InitStruct->SequencerDiscont
847 | ADC_INJ_InitStruct->TrigAuto
848 );
849 }
850 else
851 {
852 MODIFY_REG(ADCx->CR1,
853 ADC_CR1_JDISCEN
854 | ADC_CR1_JAUTO
855 ,
856 LL_ADC_REG_SEQ_DISCONT_DISABLE
857 | ADC_INJ_InitStruct->TrigAuto
858 );
859 }
860
861 MODIFY_REG(ADCx->CR2,
862 ADC_CR2_JEXTSEL
863 | ADC_CR2_JEXTEN
864 ,
865 (ADC_INJ_InitStruct->TriggerSource & ADC_CR2_JEXTSEL)
866 );
867
868 /* Note: Hardware constraint (refer to description of this function): */
869 /* Note: If ADC instance feature scan mode is disabled */
870 /* (refer to ADC instance initialization structure */
871 /* parameter @ref SequencersScanMode */
872 /* or function @ref LL_ADC_SetSequencersScanMode() ), */
873 /* this parameter is discarded. */
874 LL_ADC_INJ_SetSequencerLength(ADCx, ADC_INJ_InitStruct->SequencerLength);
875 }
876 else
877 {
878 /* Initialization error: ADC instance is not disabled. */
879 status = ERROR;
880 }
881 return status;
882 }
883
884 /**
885 * @brief Set each @ref LL_ADC_INJ_InitTypeDef field to default value.
886 * @param ADC_INJ_InitStruct Pointer to a @ref LL_ADC_INJ_InitTypeDef structure
887 * whose fields will be set to default values.
888 * @retval None
889 */
890 void LL_ADC_INJ_StructInit(LL_ADC_INJ_InitTypeDef *ADC_INJ_InitStruct)
891 {
892 /* Set ADC_INJ_InitStruct fields to default values */
893 /* Set fields of ADC group injected */
894 ADC_INJ_InitStruct->TriggerSource = LL_ADC_INJ_TRIG_SOFTWARE;
895 ADC_INJ_InitStruct->SequencerLength = LL_ADC_INJ_SEQ_SCAN_DISABLE;
896 ADC_INJ_InitStruct->SequencerDiscont = LL_ADC_INJ_SEQ_DISCONT_DISABLE;
897 ADC_INJ_InitStruct->TrigAuto = LL_ADC_INJ_TRIG_INDEPENDENT;
898 }
899
900 /**
901 * @}
902 */
903
904 /**
905 * @}
906 */
907
908 /**
909 * @}
910 */
911
912 #endif /* ADC1 || ADC2 || ADC3 */
913
914 /**
915 * @}
916 */
917
918 #endif /* USE_FULL_LL_DRIVER */
919
920 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software