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Merge pull request #10558 from iNavFlight/MrD_Correct-comments-on-OSD-symbols
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_dma.c
blobc0b1d24037d09657e4ab5902b356d903e2d7bf82
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_dma.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief DMA LL module driver.
8 ******************************************************************************
9 * @attention
10 *
11 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
12 *
13 * Redistribution and use in source and binary forms, with or without modification,
14 * are permitted provided that the following conditions are met:
15 * 1. Redistributions of source code must retain the above copyright notice,
16 * this list of conditions and the following disclaimer.
17 * 2. Redistributions in binary form must reproduce the above copyright notice,
18 * this list of conditions and the following disclaimer in the documentation
19 * and/or other materials provided with the distribution.
20 * 3. Neither the name of STMicroelectronics nor the names of its contributors
21 * may be used to endorse or promote products derived from this software
22 * without specific prior written permission.
23 *
24 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
25 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
26 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
27 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
28 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
29 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
30 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
31 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
32 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
33 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
34 *
35 ******************************************************************************
36 */
37 #if defined(USE_FULL_LL_DRIVER)
38
39 /* Includes ------------------------------------------------------------------*/
40 #include "stm32f7xx_ll_dma.h"
41 #include "stm32f7xx_ll_bus.h"
42 #ifdef USE_FULL_ASSERT
43 #include "stm32_assert.h"
44 #else
45 #define assert_param(expr) ((void)0U)
46 #endif
47
48 /** @addtogroup STM32F7xx_LL_Driver
49 * @{
50 */
51
52 #if defined (DMA1) || defined (DMA2)
53
54 /** @defgroup DMA_LL DMA
55 * @{
56 */
57
58 /* Private types -------------------------------------------------------------*/
59 /* Private variables ---------------------------------------------------------*/
60 /* Private constants ---------------------------------------------------------*/
61 /* Private macros ------------------------------------------------------------*/
62 /** @addtogroup DMA_LL_Private_Macros
63 * @{
64 */
65 #define IS_LL_DMA_DIRECTION(__VALUE__) (((__VALUE__) == LL_DMA_DIRECTION_PERIPH_TO_MEMORY) || \
66 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_PERIPH) || \
67 ((__VALUE__) == LL_DMA_DIRECTION_MEMORY_TO_MEMORY))
68
69 #define IS_LL_DMA_MODE(__VALUE__) (((__VALUE__) == LL_DMA_MODE_NORMAL) || \
70 ((__VALUE__) == LL_DMA_MODE_CIRCULAR) || \
71 ((__VALUE__) == LL_DMA_MODE_PFCTRL))
72
73 #define IS_LL_DMA_PERIPHINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_PERIPH_INCREMENT) || \
74 ((__VALUE__) == LL_DMA_PERIPH_NOINCREMENT))
75
76 #define IS_LL_DMA_MEMORYINCMODE(__VALUE__) (((__VALUE__) == LL_DMA_MEMORY_INCREMENT) || \
77 ((__VALUE__) == LL_DMA_MEMORY_NOINCREMENT))
78
79 #define IS_LL_DMA_PERIPHDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_PDATAALIGN_BYTE) || \
80 ((__VALUE__) == LL_DMA_PDATAALIGN_HALFWORD) || \
81 ((__VALUE__) == LL_DMA_PDATAALIGN_WORD))
82
83 #define IS_LL_DMA_MEMORYDATASIZE(__VALUE__) (((__VALUE__) == LL_DMA_MDATAALIGN_BYTE) || \
84 ((__VALUE__) == LL_DMA_MDATAALIGN_HALFWORD) || \
85 ((__VALUE__) == LL_DMA_MDATAALIGN_WORD))
86
87 #define IS_LL_DMA_NBDATA(__VALUE__) ((__VALUE__) <= 0x0000FFFFU)
88
89 #if defined(DMA_CHANNEL_SELECTION_8_15)
90 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
91 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
92 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
93 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
94 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
95 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
96 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
97 ((__VALUE__) == LL_DMA_CHANNEL_7) || \
98 ((__VALUE__) == LL_DMA_CHANNEL_8) || \
99 ((__VALUE__) == LL_DMA_CHANNEL_9) || \
100 ((__VALUE__) == LL_DMA_CHANNEL_10) || \
101 ((__VALUE__) == LL_DMA_CHANNEL_11) || \
102 ((__VALUE__) == LL_DMA_CHANNEL_12) || \
103 ((__VALUE__) == LL_DMA_CHANNEL_13) || \
104 ((__VALUE__) == LL_DMA_CHANNEL_14) || \
105 ((__VALUE__) == LL_DMA_CHANNEL_15))
106
107 #else
108 #define IS_LL_DMA_CHANNEL(__VALUE__) (((__VALUE__) == LL_DMA_CHANNEL_0) || \
109 ((__VALUE__) == LL_DMA_CHANNEL_1) || \
110 ((__VALUE__) == LL_DMA_CHANNEL_2) || \
111 ((__VALUE__) == LL_DMA_CHANNEL_3) || \
112 ((__VALUE__) == LL_DMA_CHANNEL_4) || \
113 ((__VALUE__) == LL_DMA_CHANNEL_5) || \
114 ((__VALUE__) == LL_DMA_CHANNEL_6) || \
115 ((__VALUE__) == LL_DMA_CHANNEL_7))
116
117 #endif /* DMA_CHANNEL_SELECTION_8_15 */
118
119 #define IS_LL_DMA_PRIORITY(__VALUE__) (((__VALUE__) == LL_DMA_PRIORITY_LOW) || \
120 ((__VALUE__) == LL_DMA_PRIORITY_MEDIUM) || \
121 ((__VALUE__) == LL_DMA_PRIORITY_HIGH) || \
122 ((__VALUE__) == LL_DMA_PRIORITY_VERYHIGH))
123
124 #define IS_LL_DMA_ALL_STREAM_INSTANCE(INSTANCE, STREAM) ((((INSTANCE) == DMA1) && \
125 (((STREAM) == LL_DMA_STREAM_0) || \
126 ((STREAM) == LL_DMA_STREAM_1) || \
127 ((STREAM) == LL_DMA_STREAM_2) || \
128 ((STREAM) == LL_DMA_STREAM_3) || \
129 ((STREAM) == LL_DMA_STREAM_4) || \
130 ((STREAM) == LL_DMA_STREAM_5) || \
131 ((STREAM) == LL_DMA_STREAM_6) || \
132 ((STREAM) == LL_DMA_STREAM_7) || \
133 ((STREAM) == LL_DMA_STREAM_ALL))) ||\
134 (((INSTANCE) == DMA2) && \
135 (((STREAM) == LL_DMA_STREAM_0) || \
136 ((STREAM) == LL_DMA_STREAM_1) || \
137 ((STREAM) == LL_DMA_STREAM_2) || \
138 ((STREAM) == LL_DMA_STREAM_3) || \
139 ((STREAM) == LL_DMA_STREAM_4) || \
140 ((STREAM) == LL_DMA_STREAM_5) || \
141 ((STREAM) == LL_DMA_STREAM_6) || \
142 ((STREAM) == LL_DMA_STREAM_7) || \
143 ((STREAM) == LL_DMA_STREAM_ALL))))
144
145 #define IS_LL_DMA_FIFO_MODE_STATE(STATE) (((STATE) == LL_DMA_FIFOMODE_DISABLE ) || \
146 ((STATE) == LL_DMA_FIFOMODE_ENABLE))
147
148 #define IS_LL_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_4) || \
149 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_1_2) || \
150 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_3_4) || \
151 ((THRESHOLD) == LL_DMA_FIFOTHRESHOLD_FULL))
152
153 #define IS_LL_DMA_MEMORY_BURST(BURST) (((BURST) == LL_DMA_MBURST_SINGLE) || \
154 ((BURST) == LL_DMA_MBURST_INC4) || \
155 ((BURST) == LL_DMA_MBURST_INC8) || \
156 ((BURST) == LL_DMA_MBURST_INC16))
157
158 #define IS_LL_DMA_PERIPHERAL_BURST(BURST) (((BURST) == LL_DMA_PBURST_SINGLE) || \
159 ((BURST) == LL_DMA_PBURST_INC4) || \
160 ((BURST) == LL_DMA_PBURST_INC8) || \
161 ((BURST) == LL_DMA_PBURST_INC16))
162
163 /**
164 * @}
165 */
166
167 /* Private function prototypes -----------------------------------------------*/
168
169 /* Exported functions --------------------------------------------------------*/
170 /** @addtogroup DMA_LL_Exported_Functions
171 * @{
172 */
173
174 /** @addtogroup DMA_LL_EF_Init
175 * @{
176 */
177
178 /**
179 * @brief De-initialize the DMA registers to their default reset values.
180 * @param DMAx DMAx Instance
181 * @param Stream This parameter can be one of the following values:
182 * @arg @ref LL_DMA_STREAM_0
183 * @arg @ref LL_DMA_STREAM_1
184 * @arg @ref LL_DMA_STREAM_2
185 * @arg @ref LL_DMA_STREAM_3
186 * @arg @ref LL_DMA_STREAM_4
187 * @arg @ref LL_DMA_STREAM_5
188 * @arg @ref LL_DMA_STREAM_6
189 * @arg @ref LL_DMA_STREAM_7
190 * @arg @ref LL_DMA_STREAM_ALL
191 * @retval An ErrorStatus enumeration value:
192 * - SUCCESS: DMA registers are de-initialized
193 * - ERROR: DMA registers are not de-initialized
194 */
195 uint32_t LL_DMA_DeInit(DMA_TypeDef *DMAx, uint32_t Stream)
196 {
197 DMA_Stream_TypeDef *tmp = (DMA_Stream_TypeDef *)DMA1_Stream0;
198 ErrorStatus status = SUCCESS;
199
200 /* Check the DMA Instance DMAx and Stream parameters*/
201 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
202
203 if (Stream == LL_DMA_STREAM_ALL)
204 {
205 if (DMAx == DMA1)
206 {
207 /* Force reset of DMA clock */
208 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA1);
209
210 /* Release reset of DMA clock */
211 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA1);
212 }
213 else if (DMAx == DMA2)
214 {
215 /* Force reset of DMA clock */
216 LL_AHB1_GRP1_ForceReset(LL_AHB1_GRP1_PERIPH_DMA2);
217
218 /* Release reset of DMA clock */
219 LL_AHB1_GRP1_ReleaseReset(LL_AHB1_GRP1_PERIPH_DMA2);
220 }
221 else
222 {
223 status = ERROR;
224 }
225 }
226 else
227 {
228 /* Disable the selected Stream */
229 LL_DMA_DisableStream(DMAx,Stream);
230
231 /* Get the DMA Stream Instance */
232 tmp = (DMA_Stream_TypeDef *)(__LL_DMA_GET_STREAM_INSTANCE(DMAx, Stream));
233
234 /* Reset DMAx_Streamy configuration register */
235 LL_DMA_WriteReg(tmp, CR, 0U);
236
237 /* Reset DMAx_Streamy remaining bytes register */
238 LL_DMA_WriteReg(tmp, NDTR, 0U);
239
240 /* Reset DMAx_Streamy peripheral address register */
241 LL_DMA_WriteReg(tmp, PAR, 0U);
242
243 /* Reset DMAx_Streamy memory address register */
244 LL_DMA_WriteReg(tmp, M0AR, 0U);
245
246 /* Reset DMAx_Streamy memory address register */
247 LL_DMA_WriteReg(tmp, M1AR, 0U);
248
249 /* Reset DMAx_Streamy FIFO control register */
250 LL_DMA_WriteReg(tmp, FCR, 0x00000021U);
251
252 /* Reset Channel register field for DMAx Stream*/
253 LL_DMA_SetChannelSelection(DMAx, Stream, LL_DMA_CHANNEL_0);
254
255 if(Stream == LL_DMA_STREAM_0)
256 {
257 /* Reset the Stream0 pending flags */
258 DMAx->LIFCR = 0x0000003FU;
259 }
260 else if(Stream == LL_DMA_STREAM_1)
261 {
262 /* Reset the Stream1 pending flags */
263 DMAx->LIFCR = 0x00000F40U;
264 }
265 else if(Stream == LL_DMA_STREAM_2)
266 {
267 /* Reset the Stream2 pending flags */
268 DMAx->LIFCR = 0x003F0000U;
269 }
270 else if(Stream == LL_DMA_STREAM_3)
271 {
272 /* Reset the Stream3 pending flags */
273 DMAx->LIFCR = 0x0F400000U;
274 }
275 else if(Stream == LL_DMA_STREAM_4)
276 {
277 /* Reset the Stream4 pending flags */
278 DMAx->HIFCR = 0x0000003FU;
279 }
280 else if(Stream == LL_DMA_STREAM_5)
281 {
282 /* Reset the Stream5 pending flags */
283 DMAx->HIFCR = 0x00000F40U;
284 }
285 else if(Stream == LL_DMA_STREAM_6)
286 {
287 /* Reset the Stream6 pending flags */
288 DMAx->HIFCR = 0x003F0000U;
289 }
290 else if(Stream == LL_DMA_STREAM_7)
291 {
292 /* Reset the Stream7 pending flags */
293 DMAx->HIFCR = 0x0F400000U;
294 }
295 else
296 {
297 status = ERROR;
298 }
299 }
300
301 return status;
302 }
303
304 /**
305 * @brief Initialize the DMA registers according to the specified parameters in DMA_InitStruct.
306 * @note To convert DMAx_Streamy Instance to DMAx Instance and Streamy, use helper macros :
307 * @arg @ref __LL_DMA_GET_INSTANCE
308 * @arg @ref __LL_DMA_GET_STREAM
309 * @param DMAx DMAx Instance
310 * @param Stream This parameter can be one of the following values:
311 * @arg @ref LL_DMA_STREAM_0
312 * @arg @ref LL_DMA_STREAM_1
313 * @arg @ref LL_DMA_STREAM_2
314 * @arg @ref LL_DMA_STREAM_3
315 * @arg @ref LL_DMA_STREAM_4
316 * @arg @ref LL_DMA_STREAM_5
317 * @arg @ref LL_DMA_STREAM_6
318 * @arg @ref LL_DMA_STREAM_7
319 * @param DMA_InitStruct pointer to a @ref LL_DMA_InitTypeDef structure.
320 * @retval An ErrorStatus enumeration value:
321 * - SUCCESS: DMA registers are initialized
322 * - ERROR: Not applicable
323 */
324 uint32_t LL_DMA_Init(DMA_TypeDef *DMAx, uint32_t Stream, LL_DMA_InitTypeDef *DMA_InitStruct)
325 {
326 /* Check the DMA Instance DMAx and Stream parameters*/
327 assert_param(IS_LL_DMA_ALL_STREAM_INSTANCE(DMAx, Stream));
328
329 /* Check the DMA parameters from DMA_InitStruct */
330 assert_param(IS_LL_DMA_DIRECTION(DMA_InitStruct->Direction));
331 assert_param(IS_LL_DMA_MODE(DMA_InitStruct->Mode));
332 assert_param(IS_LL_DMA_PERIPHINCMODE(DMA_InitStruct->PeriphOrM2MSrcIncMode));
333 assert_param(IS_LL_DMA_MEMORYINCMODE(DMA_InitStruct->MemoryOrM2MDstIncMode));
334 assert_param(IS_LL_DMA_PERIPHDATASIZE(DMA_InitStruct->PeriphOrM2MSrcDataSize));
335 assert_param(IS_LL_DMA_MEMORYDATASIZE(DMA_InitStruct->MemoryOrM2MDstDataSize));
336 assert_param(IS_LL_DMA_NBDATA(DMA_InitStruct->NbData));
337 assert_param(IS_LL_DMA_CHANNEL(DMA_InitStruct->Channel));
338 assert_param(IS_LL_DMA_PRIORITY(DMA_InitStruct->Priority));
339 assert_param(IS_LL_DMA_FIFO_MODE_STATE(DMA_InitStruct->FIFOMode));
340 /* Check the memory burst, peripheral burst and FIFO threshold parameters only
341 when FIFO mode is enabled */
342 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
343 {
344 assert_param(IS_LL_DMA_FIFO_THRESHOLD(DMA_InitStruct->FIFOThreshold));
345 assert_param(IS_LL_DMA_MEMORY_BURST(DMA_InitStruct->MemBurst));
346 assert_param(IS_LL_DMA_PERIPHERAL_BURST(DMA_InitStruct->PeriphBurst));
347 }
348
349 /*---------------------------- DMAx SxCR Configuration ------------------------
350 * Configure DMAx_Streamy: data transfer direction, data transfer mode,
351 * peripheral and memory increment mode,
352 * data size alignment and priority level with parameters :
353 * - Direction: DMA_SxCR_DIR[1:0] bits
354 * - Mode: DMA_SxCR_CIRC bit
355 * - PeriphOrM2MSrcIncMode: DMA_SxCR_PINC bit
356 * - MemoryOrM2MDstIncMode: DMA_SxCR_MINC bit
357 * - PeriphOrM2MSrcDataSize: DMA_SxCR_PSIZE[1:0] bits
358 * - MemoryOrM2MDstDataSize: DMA_SxCR_MSIZE[1:0] bits
359 * - Priority: DMA_SxCR_PL[1:0] bits
360 */
361 LL_DMA_ConfigTransfer(DMAx, Stream, DMA_InitStruct->Direction | \
362 DMA_InitStruct->Mode | \
363 DMA_InitStruct->PeriphOrM2MSrcIncMode | \
364 DMA_InitStruct->MemoryOrM2MDstIncMode | \
365 DMA_InitStruct->PeriphOrM2MSrcDataSize | \
366 DMA_InitStruct->MemoryOrM2MDstDataSize | \
367 DMA_InitStruct->Priority
368 );
369
370 if(DMA_InitStruct->FIFOMode != LL_DMA_FIFOMODE_DISABLE)
371 {
372 /*---------------------------- DMAx SxFCR Configuration ------------------------
373 * Configure DMAx_Streamy: fifo mode and fifo threshold with parameters :
374 * - FIFOMode: DMA_SxFCR_DMDIS bit
375 * - FIFOThreshold: DMA_SxFCR_FTH[1:0] bits
376 */
377 LL_DMA_ConfigFifo(DMAx, Stream, DMA_InitStruct->FIFOMode, DMA_InitStruct->FIFOThreshold);
378
379 /*---------------------------- DMAx SxCR Configuration --------------------------
380 * Configure DMAx_Streamy: memory burst transfer with parameters :
381 * - MemBurst: DMA_SxCR_MBURST[1:0] bits
382 */
383 LL_DMA_SetMemoryBurstxfer(DMAx,Stream,DMA_InitStruct->MemBurst);
384
385 /*---------------------------- DMAx SxCR Configuration --------------------------
386 * Configure DMAx_Streamy: peripheral burst transfer with parameters :
387 * - PeriphBurst: DMA_SxCR_PBURST[1:0] bits
388 */
389 LL_DMA_SetPeriphBurstxfer(DMAx,Stream,DMA_InitStruct->PeriphBurst);
390 }
391
392 /*-------------------------- DMAx SxM0AR Configuration --------------------------
393 * Configure the memory or destination base address with parameter :
394 * - MemoryOrM2MDstAddress: DMA_SxM0AR_M0A[31:0] bits
395 */
396 LL_DMA_SetMemoryAddress(DMAx, Stream, DMA_InitStruct->MemoryOrM2MDstAddress);
397
398 /*-------------------------- DMAx SxPAR Configuration ---------------------------
399 * Configure the peripheral or source base address with parameter :
400 * - PeriphOrM2MSrcAddress: DMA_SxPAR_PA[31:0] bits
401 */
402 LL_DMA_SetPeriphAddress(DMAx, Stream, DMA_InitStruct->PeriphOrM2MSrcAddress);
403
404 /*--------------------------- DMAx SxNDTR Configuration -------------------------
405 * Configure the peripheral base address with parameter :
406 * - NbData: DMA_SxNDT[15:0] bits
407 */
408 LL_DMA_SetDataLength(DMAx, Stream, DMA_InitStruct->NbData);
409
410 /*--------------------------- DMA SxCR_CHSEL Configuration ----------------------
411 * Configure the peripheral base address with parameter :
412 * - PeriphRequest: DMA_SxCR_CHSEL[3:0] bits
413 */
414 LL_DMA_SetChannelSelection(DMAx, Stream, DMA_InitStruct->Channel);
415
416 return SUCCESS;
417 }
418
419 /**
420 * @brief Set each @ref LL_DMA_InitTypeDef field to default value.
421 * @param DMA_InitStruct Pointer to a @ref LL_DMA_InitTypeDef structure.
422 * @retval None
423 */
424 void LL_DMA_StructInit(LL_DMA_InitTypeDef *DMA_InitStruct)
425 {
426 /* Set DMA_InitStruct fields to default values */
427 DMA_InitStruct->PeriphOrM2MSrcAddress = 0x00000000U;
428 DMA_InitStruct->MemoryOrM2MDstAddress = 0x00000000U;
429 DMA_InitStruct->Direction = LL_DMA_DIRECTION_PERIPH_TO_MEMORY;
430 DMA_InitStruct->Mode = LL_DMA_MODE_NORMAL;
431 DMA_InitStruct->PeriphOrM2MSrcIncMode = LL_DMA_PERIPH_NOINCREMENT;
432 DMA_InitStruct->MemoryOrM2MDstIncMode = LL_DMA_MEMORY_NOINCREMENT;
433 DMA_InitStruct->PeriphOrM2MSrcDataSize = LL_DMA_PDATAALIGN_BYTE;
434 DMA_InitStruct->MemoryOrM2MDstDataSize = LL_DMA_MDATAALIGN_BYTE;
435 DMA_InitStruct->NbData = 0x00000000U;
436 DMA_InitStruct->Channel = LL_DMA_CHANNEL_0;
437 DMA_InitStruct->Priority = LL_DMA_PRIORITY_LOW;
438 DMA_InitStruct->FIFOMode = LL_DMA_FIFOMODE_DISABLE;
439 DMA_InitStruct->FIFOThreshold = LL_DMA_FIFOTHRESHOLD_1_4;
440 DMA_InitStruct->MemBurst = LL_DMA_MBURST_SINGLE;
441 DMA_InitStruct->PeriphBurst = LL_DMA_PBURST_SINGLE;
442 }
443
444 /**
445 * @}
446 */
447
448 /**
449 * @}
450 */
451
452 /**
453 * @}
454 */
455
456 #endif /* DMA1 || DMA2 */
457
458 /**
459 * @}
460 */
461
462 #endif /* USE_FULL_LL_DRIVER */
463
464 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
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