lib/main/STM32F7/Drivers/STM32F7xx_HAL_Driver/Src/stm32f7xx_ll_tim.c

   1 /**
   2   ******************************************************************************
   3   * @file    stm32f7xx_ll_tim.c
   4   * @author  MCD Application Team
   5   * @version V1.2.2
   6   * @date    14-April-2017
   7   * @brief   TIM LL module driver.
   8   ******************************************************************************
   9   * @attention
  10   *
  11   * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
  12   *
  13   * Redistribution and use in source and binary forms, with or without modification,
  14   * are permitted provided that the following conditions are met:
  15   *   1. Redistributions of source code must retain the above copyright notice,
  16   *      this list of conditions and the following disclaimer.
  17   *   2. Redistributions in binary form must reproduce the above copyright notice,
  18   *      this list of conditions and the following disclaimer in the documentation
  19   *      and/or other materials provided with the distribution.
  20   *   3. Neither the name of STMicroelectronics nor the names of its contributors
  21   *      may be used to endorse or promote products derived from this software
  22   *      without specific prior written permission.
  23   *
  24   * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
  25   * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
  26   * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
  27   * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
  28   * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
  29   * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
  30   * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
  31   * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
  32   * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  33   * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  34   *
  35   ******************************************************************************
  36   */
  37 #if defined(USE_FULL_LL_DRIVER)
  38
  39 /* Includes ------------------------------------------------------------------*/
  40 #include "stm32f7xx_ll_tim.h"
  41 #include "stm32f7xx_ll_bus.h"
  42
  43 #ifdef  USE_FULL_ASSERT
  44 #include "stm32_assert.h"
  45 #else
  46 #define assert_param(expr) ((void)0U)
  47 #endif
  48
  49 /** @addtogroup STM32F7xx_LL_Driver
  50   * @{
  51   */
  52
  53 #if defined (TIM1) || defined (TIM8) || defined (TIM2) || defined (TIM3) ||  defined (TIM4) || defined (TIM5) || defined (TIM9) || defined (TIM10) || defined (TIM11) || defined (TIM12) || defined (TIM13) || defined (TIM14) || defined (TIM6) || defined (TIM7)
  54
  55 /** @addtogroup TIM_LL
  56   * @{
  57   */
  58
  59 /* Private types -------------------------------------------------------------*/
  60 /* Private variables ---------------------------------------------------------*/
  61 /* Private constants ---------------------------------------------------------*/
  62 /* Private macros ------------------------------------------------------------*/
  63 /** @addtogroup TIM_LL_Private_Macros
  64   * @{
  65   */
  66 #define IS_LL_TIM_COUNTERMODE(__VALUE__) (((__VALUE__) == LL_TIM_COUNTERMODE_UP) \
  67                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_DOWN) \
  68                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP) \
  69                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_DOWN) \
  70                                        || ((__VALUE__) == LL_TIM_COUNTERMODE_CENTER_UP_DOWN))
  71
  72 #define IS_LL_TIM_CLOCKDIVISION(__VALUE__) (((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV1) \
  73                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV2) \
  74                                          || ((__VALUE__) == LL_TIM_CLOCKDIVISION_DIV4))
  75
  76 #define IS_LL_TIM_OCMODE(__VALUE__) (((__VALUE__) == LL_TIM_OCMODE_FROZEN) \
  77                                   || ((__VALUE__) == LL_TIM_OCMODE_ACTIVE) \
  78                                   || ((__VALUE__) == LL_TIM_OCMODE_INACTIVE) \
  79                                   || ((__VALUE__) == LL_TIM_OCMODE_TOGGLE) \
  80                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_INACTIVE) \
  81                                   || ((__VALUE__) == LL_TIM_OCMODE_FORCED_ACTIVE) \
  82                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM1) \
  83                                   || ((__VALUE__) == LL_TIM_OCMODE_PWM2) \
  84                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM1) \
  85                                   || ((__VALUE__) == LL_TIM_OCMODE_RETRIG_OPM2) \
  86                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM1) \
  87                                   || ((__VALUE__) == LL_TIM_OCMODE_COMBINED_PWM2) \
  88                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM1) \
  89                                   || ((__VALUE__) == LL_TIM_OCMODE_ASSYMETRIC_PWM2))
  90
  91 #define IS_LL_TIM_OCSTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCSTATE_DISABLE) \
  92                                    || ((__VALUE__) == LL_TIM_OCSTATE_ENABLE))
  93
  94 #define IS_LL_TIM_OCPOLARITY(__VALUE__) (((__VALUE__) == LL_TIM_OCPOLARITY_HIGH) \
  95                                       || ((__VALUE__) == LL_TIM_OCPOLARITY_LOW))
  96
  97 #define IS_LL_TIM_OCIDLESTATE(__VALUE__) (((__VALUE__) == LL_TIM_OCIDLESTATE_LOW) \
  98                                        || ((__VALUE__) == LL_TIM_OCIDLESTATE_HIGH))
  99
 100 #define IS_LL_TIM_ACTIVEINPUT(__VALUE__) (((__VALUE__) == LL_TIM_ACTIVEINPUT_DIRECTTI) \
 101                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_INDIRECTTI) \
 102                                        || ((__VALUE__) == LL_TIM_ACTIVEINPUT_TRC))
 103
 104 #define IS_LL_TIM_ICPSC(__VALUE__) (((__VALUE__) == LL_TIM_ICPSC_DIV1) \
 105                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV2) \
 106                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV4) \
 107                                  || ((__VALUE__) == LL_TIM_ICPSC_DIV8))
 108
 109 #define IS_LL_TIM_IC_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_IC_FILTER_FDIV1) \
 110                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N2) \
 111                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N4) \
 112                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV1_N8) \
 113                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N6) \
 114                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV2_N8) \
 115                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N6) \
 116                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV4_N8) \
 117                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N6) \
 118                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV8_N8) \
 119                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N5) \
 120                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N6) \
 121                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV16_N8) \
 122                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N5) \
 123                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N6) \
 124                                      || ((__VALUE__) == LL_TIM_IC_FILTER_FDIV32_N8))
 125
 126 #define IS_LL_TIM_IC_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 127                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING) \
 128                                        || ((__VALUE__) == LL_TIM_IC_POLARITY_BOTHEDGE))
 129
 130 #define IS_LL_TIM_ENCODERMODE(__VALUE__) (((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI1) \
 131                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X2_TI2) \
 132                                        || ((__VALUE__) == LL_TIM_ENCODERMODE_X4_TI12))
 133
 134 #define IS_LL_TIM_IC_POLARITY_ENCODER(__VALUE__) (((__VALUE__) == LL_TIM_IC_POLARITY_RISING) \
 135                                                || ((__VALUE__) == LL_TIM_IC_POLARITY_FALLING))
 136
 137 #define IS_LL_TIM_OSSR_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSR_DISABLE) \
 138                                      || ((__VALUE__) == LL_TIM_OSSR_ENABLE))
 139
 140 #define IS_LL_TIM_OSSI_STATE(__VALUE__) (((__VALUE__) == LL_TIM_OSSI_DISABLE) \
 141                                       || ((__VALUE__) == LL_TIM_OSSI_ENABLE))
 142
 143 #define IS_LL_TIM_LOCK_LEVEL(__VALUE__) (((__VALUE__) == LL_TIM_LOCKLEVEL_OFF) \
 144                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_1)   \
 145                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_2)   \
 146                                       || ((__VALUE__) == LL_TIM_LOCKLEVEL_3))
 147
 148 #define IS_LL_TIM_BREAK_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_DISABLE) \
 149                                        || ((__VALUE__) == LL_TIM_BREAK_ENABLE))
 150
 151 #define IS_LL_TIM_BREAK_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_POLARITY_LOW) \
 152                                           || ((__VALUE__) == LL_TIM_BREAK_POLARITY_HIGH))
 153
 154 #define IS_LL_TIM_BREAK_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1)     \
 155                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N2)  \
 156                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N4)  \
 157                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV1_N8)  \
 158                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N6)  \
 159                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV2_N8)  \
 160                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N6)  \
 161                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV4_N8)  \
 162                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N6)  \
 163                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV8_N8)  \
 164                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N5) \
 165                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N6) \
 166                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV16_N8) \
 167                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N5) \
 168                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N6) \
 169                                         || ((__VALUE__) == LL_TIM_BREAK_FILTER_FDIV32_N8))
 170
 171 #define IS_LL_TIM_BREAK2_STATE(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_DISABLE) \
 172                                         || ((__VALUE__) == LL_TIM_BREAK2_ENABLE))
 173
 174 #define IS_LL_TIM_BREAK2_POLARITY(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_POLARITY_LOW) \
 175                                           || ((__VALUE__) == LL_TIM_BREAK2_POLARITY_HIGH))
 176
 177 #define IS_LL_TIM_BREAK2_FILTER(__VALUE__) (((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1)    \
 178                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N2)  \
 179                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N4)  \
 180                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV1_N8)  \
 181                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N6)  \
 182                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV2_N8)  \
 183                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N6)  \
 184                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV4_N8)  \
 185                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N6)  \
 186                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV8_N8)  \
 187                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N5) \
 188                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N6) \
 189                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV16_N8) \
 190                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N5) \
 191                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N6) \
 192                                         || ((__VALUE__) == LL_TIM_BREAK2_FILTER_FDIV32_N8))
 193
 194 #define IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(__VALUE__) (((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_DISABLE) \
 195                                                   || ((__VALUE__) == LL_TIM_AUTOMATICOUTPUT_ENABLE))
 196 /**
 197   * @}
 198   */
 199
 200
 201 /* Private function prototypes -----------------------------------------------*/
 202 /** @defgroup TIM_LL_Private_Functions TIM Private Functions
 203   * @{
 204   */
 205 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 206 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 207 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 208 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 209 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 210 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct);
 211 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 212 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 213 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 214 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct);
 215 /**
 216   * @}
 217   */
 218
 219 /* Exported functions --------------------------------------------------------*/
 220 /** @addtogroup TIM_LL_Exported_Functions
 221   * @{
 222   */
 223
 224 /** @addtogroup TIM_LL_EF_Init
 225   * @{
 226   */
 227
 228 /**
 229   * @brief  Set TIMx registers to their reset values.
 230   * @param  TIMx Timer instance
 231   * @retval An ErrorStatus enumeration value:
 232   *          - SUCCESS: TIMx registers are de-initialized
 233   *          - ERROR: invalid TIMx instance
 234   */
 235 ErrorStatus LL_TIM_DeInit(TIM_TypeDef *TIMx)
 236 {
 237   ErrorStatus result = SUCCESS;
 238
 239   /* Check the parameters */
 240   assert_param(IS_TIM_INSTANCE(TIMx));
 241
 242   if (TIMx == TIM1)
 243   {
 244     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM1);
 245     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM1);
 246   }
 247   else if (TIMx == TIM2)
 248   {
 249     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM2);
 250     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM2);
 251   }
 252 #if defined(TIM3)
 253   else if (TIMx == TIM3)
 254   {
 255     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM3);
 256     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM3);
 257   }
 258 #endif
 259 #if defined(TIM4)
 260   else if (TIMx == TIM4)
 261   {
 262     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM4);
 263     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM4);
 264   }
 265 #endif
 266 #if defined(TIM5)
 267   else if (TIMx == TIM5)
 268   {
 269     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM5);
 270     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM5);
 271   }
 272 #endif
 273 #if defined(TIM6)
 274   else if (TIMx == TIM6)
 275   {
 276     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM6);
 277     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM6);
 278   }
 279 #endif
 280 #if defined (TIM7)
 281   else if (TIMx == TIM7)
 282   {
 283     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM7);
 284     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM7);
 285   }
 286 #endif
 287 #if defined(TIM8)
 288   else if (TIMx == TIM8)
 289   {
 290     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM8);
 291     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM8);
 292   }
 293 #endif
 294 #if defined(TIM9)
 295   else if (TIMx == TIM9)
 296   {
 297     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM9);
 298     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM9);
 299   }
 300 #endif
 301 #if defined(TIM10)
 302   else if (TIMx == TIM10)
 303   {
 304     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM10);
 305     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM10);
 306   }
 307 #endif
 308 #if defined(TIM11)
 309   else if (TIMx == TIM11)
 310   {
 311     LL_APB2_GRP1_ForceReset(LL_APB2_GRP1_PERIPH_TIM11);
 312     LL_APB2_GRP1_ReleaseReset(LL_APB2_GRP1_PERIPH_TIM11);
 313   }
 314 #endif
 315 #if defined(TIM12)
 316   else if (TIMx == TIM12)
 317   {
 318     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM12);
 319     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM12);
 320   }
 321 #endif
 322 #if defined(TIM13)
 323   else if (TIMx == TIM13)
 324   {
 325     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM13);
 326     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM13);
 327   }
 328 #endif
 329 #if defined(TIM14)
 330   else if (TIMx == TIM14)
 331   {
 332     LL_APB1_GRP1_ForceReset(LL_APB1_GRP1_PERIPH_TIM14);
 333     LL_APB1_GRP1_ReleaseReset(LL_APB1_GRP1_PERIPH_TIM14);
 334   }
 335 #endif
 336   else
 337   {
 338     result = ERROR;
 339   }
 340
 341   return result;
 342 }
 343
 344 /**
 345   * @brief  Set the fields of the time base unit configuration data structure
 346   *         to their default values.
 347   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (time base unit configuration data structure)
 348   * @retval None
 349   */
 350 void LL_TIM_StructInit(LL_TIM_InitTypeDef *TIM_InitStruct)
 351 {
 352   /* Set the default configuration */
 353   TIM_InitStruct->Prescaler         = (uint16_t)0x0000U;
 354   TIM_InitStruct->CounterMode       = LL_TIM_COUNTERMODE_UP;
 355   TIM_InitStruct->Autoreload        = 0xFFFFFFFFU;
 356   TIM_InitStruct->ClockDivision     = LL_TIM_CLOCKDIVISION_DIV1;
 357   TIM_InitStruct->RepetitionCounter = (uint8_t)0x00U;
 358 }
 359
 360 /**
 361   * @brief  Configure the TIMx time base unit.
 362   * @param  TIMx Timer Instance
 363   * @param  TIM_InitStruct pointer to a @ref LL_TIM_InitTypeDef structure (TIMx time base unit configuration data structure)
 364   * @retval An ErrorStatus enumeration value:
 365   *          - SUCCESS: TIMx registers are de-initialized
 366   *          - ERROR: not applicable
 367   */
 368 ErrorStatus LL_TIM_Init(TIM_TypeDef *TIMx, LL_TIM_InitTypeDef *TIM_InitStruct)
 369 {
 370   uint32_t tmpcr1 = 0U;
 371
 372   /* Check the parameters */
 373   assert_param(IS_TIM_INSTANCE(TIMx));
 374   assert_param(IS_LL_TIM_COUNTERMODE(TIM_InitStruct->CounterMode));
 375   assert_param(IS_LL_TIM_CLOCKDIVISION(TIM_InitStruct->ClockDivision));
 376
 377   tmpcr1 = LL_TIM_ReadReg(TIMx, CR1);
 378
 379   if (IS_TIM_COUNTER_MODE_SELECT_INSTANCE(TIMx))
 380   {
 381     /* Select the Counter Mode */
 382     MODIFY_REG(tmpcr1, (TIM_CR1_DIR | TIM_CR1_CMS), TIM_InitStruct->CounterMode);
 383   }
 384
 385   if (IS_TIM_CLOCK_DIVISION_INSTANCE(TIMx))
 386   {
 387     /* Set the clock division */
 388     MODIFY_REG(tmpcr1, TIM_CR1_CKD, TIM_InitStruct->ClockDivision);
 389   }
 390
 391   /* Write to TIMx CR1 */
 392   LL_TIM_WriteReg(TIMx, CR1, tmpcr1);
 393
 394   /* Set the Autoreload value */
 395   LL_TIM_SetAutoReload(TIMx, TIM_InitStruct->Autoreload);
 396
 397   /* Set the Prescaler value */
 398   LL_TIM_SetPrescaler(TIMx, TIM_InitStruct->Prescaler);
 399
 400   if (IS_TIM_REPETITION_COUNTER_INSTANCE(TIMx))
 401   {
 402     /* Set the Repetition Counter value */
 403     LL_TIM_SetRepetitionCounter(TIMx, TIM_InitStruct->RepetitionCounter);
 404   }
 405
 406   /* Generate an update event to reload the Prescaler
 407      and the repetition counter value (if applicable) immediately */
 408   LL_TIM_GenerateEvent_UPDATE(TIMx);
 409
 410   return SUCCESS;
 411 }
 412
 413 /**
 414   * @brief  Set the fields of the TIMx output channel configuration data
 415   *         structure to their default values.
 416   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (the output channel configuration data structure)
 417   * @retval None
 418   */
 419 void LL_TIM_OC_StructInit(LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 420 {
 421   /* Set the default configuration */
 422   TIM_OC_InitStruct->OCMode       = LL_TIM_OCMODE_FROZEN;
 423   TIM_OC_InitStruct->OCState      = LL_TIM_OCSTATE_DISABLE;
 424   TIM_OC_InitStruct->OCNState     = LL_TIM_OCSTATE_DISABLE;
 425   TIM_OC_InitStruct->CompareValue = 0x00000000U;
 426   TIM_OC_InitStruct->OCPolarity   = LL_TIM_OCPOLARITY_HIGH;
 427   TIM_OC_InitStruct->OCNPolarity  = LL_TIM_OCPOLARITY_HIGH;
 428   TIM_OC_InitStruct->OCIdleState  = LL_TIM_OCIDLESTATE_LOW;
 429   TIM_OC_InitStruct->OCNIdleState = LL_TIM_OCIDLESTATE_LOW;
 430 }
 431
 432 /**
 433   * @brief  Configure the TIMx output channel.
 434   * @param  TIMx Timer Instance
 435   * @param  Channel This parameter can be one of the following values:
 436   *         @arg @ref LL_TIM_CHANNEL_CH1
 437   *         @arg @ref LL_TIM_CHANNEL_CH2
 438   *         @arg @ref LL_TIM_CHANNEL_CH3
 439   *         @arg @ref LL_TIM_CHANNEL_CH4
 440   *         @arg @ref LL_TIM_CHANNEL_CH5
 441   *         @arg @ref LL_TIM_CHANNEL_CH6
 442   * @param  TIM_OC_InitStruct pointer to a @ref LL_TIM_OC_InitTypeDef structure (TIMx output channel configuration data structure)
 443   * @retval An ErrorStatus enumeration value:
 444   *          - SUCCESS: TIMx output channel is initialized
 445   *          - ERROR: TIMx output channel is not initialized
 446   */
 447 ErrorStatus LL_TIM_OC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_OC_InitTypeDef *TIM_OC_InitStruct)
 448 {
 449   ErrorStatus result = ERROR;
 450
 451   switch (Channel)
 452   {
 453     case LL_TIM_CHANNEL_CH1:
 454       result = OC1Config(TIMx, TIM_OC_InitStruct);
 455       break;
 456     case LL_TIM_CHANNEL_CH2:
 457       result = OC2Config(TIMx, TIM_OC_InitStruct);
 458       break;
 459     case LL_TIM_CHANNEL_CH3:
 460       result = OC3Config(TIMx, TIM_OC_InitStruct);
 461       break;
 462     case LL_TIM_CHANNEL_CH4:
 463       result = OC4Config(TIMx, TIM_OC_InitStruct);
 464       break;
 465     case LL_TIM_CHANNEL_CH5:
 466       result = OC5Config(TIMx, TIM_OC_InitStruct);
 467       break;
 468     case LL_TIM_CHANNEL_CH6:
 469       result = OC6Config(TIMx, TIM_OC_InitStruct);
 470       break;
 471     default:
 472       break;
 473   }
 474
 475   return result;
 476 }
 477
 478 /**
 479   * @brief  Set the fields of the TIMx input channel configuration data
 480   *         structure to their default values.
 481   * @param  TIM_ICInitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (the input channel configuration data structure)
 482   * @retval None
 483   */
 484 void LL_TIM_IC_StructInit(LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
 485 {
 486   /* Set the default configuration */
 487   TIM_ICInitStruct->ICPolarity    = LL_TIM_IC_POLARITY_RISING;
 488   TIM_ICInitStruct->ICActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 489   TIM_ICInitStruct->ICPrescaler   = LL_TIM_ICPSC_DIV1;
 490   TIM_ICInitStruct->ICFilter      = LL_TIM_IC_FILTER_FDIV1;
 491 }
 492
 493 /**
 494   * @brief  Configure the TIMx input channel.
 495   * @param  TIMx Timer Instance
 496   * @param  Channel This parameter can be one of the following values:
 497   *         @arg @ref LL_TIM_CHANNEL_CH1
 498   *         @arg @ref LL_TIM_CHANNEL_CH2
 499   *         @arg @ref LL_TIM_CHANNEL_CH3
 500   *         @arg @ref LL_TIM_CHANNEL_CH4
 501   * @param  TIM_IC_InitStruct pointer to a @ref LL_TIM_IC_InitTypeDef structure (TIMx input channel configuration data structure)
 502   * @retval An ErrorStatus enumeration value:
 503   *          - SUCCESS: TIMx output channel is initialized
 504   *          - ERROR: TIMx output channel is not initialized
 505   */
 506 ErrorStatus LL_TIM_IC_Init(TIM_TypeDef *TIMx, uint32_t Channel, LL_TIM_IC_InitTypeDef *TIM_IC_InitStruct)
 507 {
 508   ErrorStatus result = ERROR;
 509
 510   switch (Channel)
 511   {
 512     case LL_TIM_CHANNEL_CH1:
 513       result = IC1Config(TIMx, TIM_IC_InitStruct);
 514       break;
 515     case LL_TIM_CHANNEL_CH2:
 516       result = IC2Config(TIMx, TIM_IC_InitStruct);
 517       break;
 518     case LL_TIM_CHANNEL_CH3:
 519       result = IC3Config(TIMx, TIM_IC_InitStruct);
 520       break;
 521     case LL_TIM_CHANNEL_CH4:
 522       result = IC4Config(TIMx, TIM_IC_InitStruct);
 523       break;
 524     default:
 525       break;
 526   }
 527
 528   return result;
 529 }
 530
 531 /**
 532   * @brief  Fills each TIM_EncoderInitStruct field with its default value
 533   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (encoder interface configuration data structure)
 534   * @retval None
 535   */
 536 void LL_TIM_ENCODER_StructInit(LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 537 {
 538   /* Set the default configuration */
 539   TIM_EncoderInitStruct->EncoderMode    = LL_TIM_ENCODERMODE_X2_TI1;
 540   TIM_EncoderInitStruct->IC1Polarity    = LL_TIM_IC_POLARITY_RISING;
 541   TIM_EncoderInitStruct->IC1ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 542   TIM_EncoderInitStruct->IC1Prescaler   = LL_TIM_ICPSC_DIV1;
 543   TIM_EncoderInitStruct->IC1Filter      = LL_TIM_IC_FILTER_FDIV1;
 544   TIM_EncoderInitStruct->IC2Polarity    = LL_TIM_IC_POLARITY_RISING;
 545   TIM_EncoderInitStruct->IC2ActiveInput = LL_TIM_ACTIVEINPUT_DIRECTTI;
 546   TIM_EncoderInitStruct->IC2Prescaler   = LL_TIM_ICPSC_DIV1;
 547   TIM_EncoderInitStruct->IC2Filter      = LL_TIM_IC_FILTER_FDIV1;
 548 }
 549
 550 /**
 551   * @brief  Configure the encoder interface of the timer instance.
 552   * @param  TIMx Timer Instance
 553   * @param  TIM_EncoderInitStruct pointer to a @ref LL_TIM_ENCODER_InitTypeDef structure (TIMx encoder interface configuration data structure)
 554   * @retval An ErrorStatus enumeration value:
 555   *          - SUCCESS: TIMx registers are de-initialized
 556   *          - ERROR: not applicable
 557   */
 558 ErrorStatus LL_TIM_ENCODER_Init(TIM_TypeDef *TIMx, LL_TIM_ENCODER_InitTypeDef *TIM_EncoderInitStruct)
 559 {
 560   uint32_t tmpccmr1 = 0U;
 561   uint32_t tmpccer = 0U;
 562
 563   /* Check the parameters */
 564   assert_param(IS_TIM_ENCODER_INTERFACE_INSTANCE(TIMx));
 565   assert_param(IS_LL_TIM_ENCODERMODE(TIM_EncoderInitStruct->EncoderMode));
 566   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC1Polarity));
 567   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC1ActiveInput));
 568   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC1Prescaler));
 569   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC1Filter));
 570   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_EncoderInitStruct->IC2Polarity));
 571   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_EncoderInitStruct->IC2ActiveInput));
 572   assert_param(IS_LL_TIM_ICPSC(TIM_EncoderInitStruct->IC2Prescaler));
 573   assert_param(IS_LL_TIM_IC_FILTER(TIM_EncoderInitStruct->IC2Filter));
 574
 575   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 576   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 577
 578   /* Get the TIMx CCMR1 register value */
 579   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 580
 581   /* Get the TIMx CCER register value */
 582   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 583
 584   /* Configure TI1 */
 585   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 586   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1ActiveInput >> 16U);
 587   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Filter >> 16U);
 588   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC1Prescaler >> 16U);
 589
 590   /* Configure TI2 */
 591   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC2S | TIM_CCMR1_IC2F  | TIM_CCMR1_IC2PSC);
 592   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2ActiveInput >> 8U);
 593   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Filter >> 8U);
 594   tmpccmr1 |= (uint32_t)(TIM_EncoderInitStruct->IC2Prescaler >> 8U);
 595
 596   /* Set TI1 and TI2 polarity and enable TI1 and TI2 */
 597   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 598   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC1Polarity);
 599   tmpccer |= (uint32_t)(TIM_EncoderInitStruct->IC2Polarity << 4U);
 600   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 601
 602   /* Set encoder mode */
 603   LL_TIM_SetEncoderMode(TIMx, TIM_EncoderInitStruct->EncoderMode);
 604
 605   /* Write to TIMx CCMR1 */
 606   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 607
 608   /* Write to TIMx CCER */
 609   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 610
 611   return SUCCESS;
 612 }
 613
 614 /**
 615   * @brief  Set the fields of the TIMx Hall sensor interface configuration data
 616   *         structure to their default values.
 617   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (HALL sensor interface configuration data structure)
 618   * @retval None
 619   */
 620 void LL_TIM_HALLSENSOR_StructInit(LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 621 {
 622   /* Set the default configuration */
 623   TIM_HallSensorInitStruct->IC1Polarity       = LL_TIM_IC_POLARITY_RISING;
 624   TIM_HallSensorInitStruct->IC1Prescaler      = LL_TIM_ICPSC_DIV1;
 625   TIM_HallSensorInitStruct->IC1Filter         = LL_TIM_IC_FILTER_FDIV1;
 626   TIM_HallSensorInitStruct->CommutationDelay  = 0U;
 627 }
 628
 629 /**
 630   * @brief  Configure the Hall sensor interface of the timer instance.
 631   * @note TIMx CH1, CH2 and CH3 inputs connected through a XOR
 632   *       to the TI1 input channel
 633   * @note TIMx slave mode controller is configured in reset mode.
 634           Selected internal trigger is TI1F_ED.
 635   * @note Channel 1 is configured as input, IC1 is mapped on TRC.
 636   * @note Captured value stored in TIMx_CCR1 correspond to the time elapsed
 637   *       between 2 changes on the inputs. It gives information about motor speed.
 638   * @note Channel 2 is configured in output PWM 2 mode.
 639   * @note Compare value stored in TIMx_CCR2 corresponds to the commutation delay.
 640   * @note OC2REF is selected as trigger output on TRGO.
 641   * @note LL_TIM_IC_POLARITY_BOTHEDGE must not be used for TI1 when it is used
 642   *       when TIMx operates in Hall sensor interface mode.
 643   * @param  TIMx Timer Instance
 644   * @param  TIM_HallSensorInitStruct pointer to a @ref LL_TIM_HALLSENSOR_InitTypeDef structure (TIMx HALL sensor interface configuration data structure)
 645   * @retval An ErrorStatus enumeration value:
 646   *          - SUCCESS: TIMx registers are de-initialized
 647   *          - ERROR: not applicable
 648   */
 649 ErrorStatus LL_TIM_HALLSENSOR_Init(TIM_TypeDef *TIMx, LL_TIM_HALLSENSOR_InitTypeDef *TIM_HallSensorInitStruct)
 650 {
 651   uint32_t tmpcr2 = 0U;
 652   uint32_t tmpccmr1 = 0U;
 653   uint32_t tmpccer = 0U;
 654   uint32_t tmpsmcr = 0U;
 655
 656   /* Check the parameters */
 657   assert_param(IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(TIMx));
 658   assert_param(IS_LL_TIM_IC_POLARITY_ENCODER(TIM_HallSensorInitStruct->IC1Polarity));
 659   assert_param(IS_LL_TIM_ICPSC(TIM_HallSensorInitStruct->IC1Prescaler));
 660   assert_param(IS_LL_TIM_IC_FILTER(TIM_HallSensorInitStruct->IC1Filter));
 661
 662   /* Disable the CC1 and CC2: Reset the CC1E and CC2E Bits */
 663   TIMx->CCER &= (uint32_t)~(TIM_CCER_CC1E | TIM_CCER_CC2E);
 664
 665   /* Get the TIMx CR2 register value */
 666   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 667
 668   /* Get the TIMx CCMR1 register value */
 669   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 670
 671   /* Get the TIMx CCER register value */
 672   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 673
 674   /* Get the TIMx SMCR register value */
 675   tmpsmcr = LL_TIM_ReadReg(TIMx, SMCR);
 676
 677   /* Connect TIMx_CH1, CH2 and CH3 pins to the TI1 input */
 678   tmpcr2 |= TIM_CR2_TI1S;
 679
 680   /* OC2REF signal is used as trigger output (TRGO) */
 681   tmpcr2 |= LL_TIM_TRGO_OC2REF;
 682
 683   /* Configure the slave mode controller */
 684   tmpsmcr &= (uint32_t)~(TIM_SMCR_TS | TIM_SMCR_SMS);
 685   tmpsmcr |= LL_TIM_TS_TI1F_ED;
 686   tmpsmcr |= LL_TIM_SLAVEMODE_RESET;
 687
 688   /* Configure input channel 1 */
 689   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_CC1S | TIM_CCMR1_IC1F  | TIM_CCMR1_IC1PSC);
 690   tmpccmr1 |= (uint32_t)(LL_TIM_ACTIVEINPUT_TRC >> 16U);
 691   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Filter >> 16U);
 692   tmpccmr1 |= (uint32_t)(TIM_HallSensorInitStruct->IC1Prescaler >> 16U);
 693
 694   /* Configure input channel 2 */
 695   tmpccmr1 &= (uint32_t)~(TIM_CCMR1_OC2M | TIM_CCMR1_OC2FE  | TIM_CCMR1_OC2PE  | TIM_CCMR1_OC2CE);
 696   tmpccmr1 |= (uint32_t)(LL_TIM_OCMODE_PWM2 << 8U);
 697
 698   /* Set Channel 1 polarity and enable Channel 1 and Channel2 */
 699   tmpccer &= (uint32_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP | TIM_CCER_CC2P | TIM_CCER_CC2NP);
 700   tmpccer |= (uint32_t)(TIM_HallSensorInitStruct->IC1Polarity);
 701   tmpccer |= (uint32_t)(TIM_CCER_CC1E | TIM_CCER_CC2E);
 702
 703   /* Write to TIMx CR2 */
 704   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 705
 706   /* Write to TIMx SMCR */
 707   LL_TIM_WriteReg(TIMx, SMCR, tmpsmcr);
 708
 709   /* Write to TIMx CCMR1 */
 710   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 711
 712   /* Write to TIMx CCER */
 713   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 714
 715   /* Write to TIMx CCR2 */
 716   LL_TIM_OC_SetCompareCH2(TIMx, TIM_HallSensorInitStruct->CommutationDelay);
 717
 718   return SUCCESS;
 719 }
 720
 721 /**
 722   * @brief  Set the fields of the Break and Dead Time configuration data structure
 723   *         to their default values.
 724   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 725   * @retval None
 726   */
 727 void LL_TIM_BDTR_StructInit(LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 728 {
 729   /* Set the default configuration */
 730   TIM_BDTRInitStruct->OSSRState       = LL_TIM_OSSR_DISABLE;
 731   TIM_BDTRInitStruct->OSSIState       = LL_TIM_OSSI_DISABLE;
 732   TIM_BDTRInitStruct->LockLevel       = LL_TIM_LOCKLEVEL_OFF;
 733   TIM_BDTRInitStruct->DeadTime        = (uint8_t)0x00U;
 734   TIM_BDTRInitStruct->BreakState      = LL_TIM_BREAK_DISABLE;
 735   TIM_BDTRInitStruct->BreakPolarity   = LL_TIM_BREAK_POLARITY_LOW;
 736   TIM_BDTRInitStruct->BreakFilter     = LL_TIM_BREAK_FILTER_FDIV1;
 737   TIM_BDTRInitStruct->Break2State     = LL_TIM_BREAK2_DISABLE;
 738   TIM_BDTRInitStruct->Break2Polarity  = LL_TIM_BREAK2_POLARITY_LOW;
 739   TIM_BDTRInitStruct->Break2Filter    = LL_TIM_BREAK2_FILTER_FDIV1;
 740   TIM_BDTRInitStruct->AutomaticOutput = LL_TIM_AUTOMATICOUTPUT_DISABLE;
 741 }
 742
 743 /**
 744   * @brief  Configure the Break and Dead Time feature of the timer instance.
 745   * @note As the bits BK2P, BK2E, BK2F[3:0], BKF[3:0], AOE, BKP, BKE, OSSI, OSSR
 746   *  and DTG[7:0] can be write-locked depending on the LOCK configuration, it
 747   *  can be necessary to configure all of them during the first write access to
 748   *  the TIMx_BDTR register.
 749   * @note Macro @ref IS_TIM_BREAK_INSTANCE(TIMx) can be used to check whether or not
 750   *       a timer instance provides a break input.
 751   * @note Macro @ref IS_TIM_BKIN2_INSTANCE(TIMx) can be used to check whether or not
 752   *       a timer instance provides a second break input.
 753   * @param  TIMx Timer Instance
 754   * @param  TIM_BDTRInitStruct pointer to a @ref LL_TIM_BDTR_InitTypeDef structure (Break and Dead Time configuration data structure)
 755   * @retval An ErrorStatus enumeration value:
 756   *          - SUCCESS: Break and Dead Time is initialized
 757   *          - ERROR: not applicable
 758   */
 759 ErrorStatus LL_TIM_BDTR_Init(TIM_TypeDef *TIMx, LL_TIM_BDTR_InitTypeDef *TIM_BDTRInitStruct)
 760 {
 761   uint32_t tmpbdtr = 0;
 762
 763   /* Check the parameters */
 764   assert_param(IS_TIM_BREAK_INSTANCE(TIMx));
 765   assert_param(IS_LL_TIM_OSSR_STATE(TIM_BDTRInitStruct->OSSRState));
 766   assert_param(IS_LL_TIM_OSSI_STATE(TIM_BDTRInitStruct->OSSIState));
 767   assert_param(IS_LL_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->LockLevel));
 768   assert_param(IS_LL_TIM_BREAK_STATE(TIM_BDTRInitStruct->BreakState));
 769   assert_param(IS_LL_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->BreakPolarity));
 770   assert_param(IS_LL_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->AutomaticOutput));
 771
 772   /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
 773   the OSSI State, the dead time value and the Automatic Output Enable Bit */
 774
 775   /* Set the BDTR bits */
 776   MODIFY_REG(tmpbdtr, TIM_BDTR_DTG, TIM_BDTRInitStruct->DeadTime);
 777   MODIFY_REG(tmpbdtr, TIM_BDTR_LOCK, TIM_BDTRInitStruct->LockLevel);
 778   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSI, TIM_BDTRInitStruct->OSSIState);
 779   MODIFY_REG(tmpbdtr, TIM_BDTR_OSSR, TIM_BDTRInitStruct->OSSRState);
 780   MODIFY_REG(tmpbdtr, TIM_BDTR_BKE, TIM_BDTRInitStruct->BreakState);
 781   MODIFY_REG(tmpbdtr, TIM_BDTR_BKP, TIM_BDTRInitStruct->BreakPolarity);
 782   MODIFY_REG(tmpbdtr, TIM_BDTR_AOE, TIM_BDTRInitStruct->AutomaticOutput);
 783   MODIFY_REG(tmpbdtr, TIM_BDTR_MOE, TIM_BDTRInitStruct->AutomaticOutput);
 784   if (IS_TIM_ADVANCED_INSTANCE(TIMx))
 785   {
 786     assert_param(IS_LL_TIM_BREAK_FILTER(TIM_BDTRInitStruct->BreakFilter));
 787     MODIFY_REG(tmpbdtr, TIM_BDTR_BKF, TIM_BDTRInitStruct->BreakFilter);
 788   }
 789
 790   if (IS_TIM_BKIN2_INSTANCE(TIMx))
 791   {
 792     assert_param(IS_LL_TIM_BREAK2_STATE(TIM_BDTRInitStruct->Break2State));
 793     assert_param(IS_LL_TIM_BREAK2_POLARITY(TIM_BDTRInitStruct->Break2Polarity));
 794     assert_param(IS_LL_TIM_BREAK2_FILTER(TIM_BDTRInitStruct->Break2Filter));
 795
 796     /* Set the BREAK2 input related BDTR bit-fields */
 797     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2F, (TIM_BDTRInitStruct->Break2Filter));
 798     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2E, TIM_BDTRInitStruct->Break2State);
 799     MODIFY_REG(tmpbdtr, TIM_BDTR_BK2P, TIM_BDTRInitStruct->Break2Polarity);
 800   }
 801
 802   /* Set TIMx_BDTR */
 803   LL_TIM_WriteReg(TIMx, BDTR, tmpbdtr);
 804
 805   return SUCCESS;
 806 }
 807 /**
 808   * @}
 809   */
 810
 811 /**
 812   * @}
 813   */
 814
 815 /** @addtogroup TIM_LL_Private_Functions TIM Private Functions
 816  *  @brief   Private functions
 817   * @{
 818   */
 819 /**
 820   * @brief  Configure the TIMx output channel 1.
 821   * @param  TIMx Timer Instance
 822   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 1 configuration data structure
 823   * @retval An ErrorStatus enumeration value:
 824   *          - SUCCESS: TIMx registers are de-initialized
 825   *          - ERROR: not applicable
 826   */
 827 static ErrorStatus OC1Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 828 {
 829   uint32_t tmpccmr1 = 0U;
 830   uint32_t tmpccer = 0U;
 831   uint32_t tmpcr2 = 0U;
 832
 833   /* Check the parameters */
 834   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
 835   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 836   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 837   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 838   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 839   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 840
 841   /* Disable the Channel 1: Reset the CC1E Bit */
 842   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC1E);
 843
 844   /* Get the TIMx CCER register value */
 845   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
 846
 847   /* Get the TIMx CR2 register value */
 848   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 849
 850   /* Get the TIMx CCMR1 register value */
 851   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 852
 853   /* Reset Capture/Compare selection Bits */
 854   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC1S);
 855
 856   /* Set the Output Compare Mode */
 857   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC1M, TIM_OCInitStruct->OCMode);
 858
 859   /* Set the Output Compare Polarity */
 860   MODIFY_REG(tmpccer, TIM_CCER_CC1P, TIM_OCInitStruct->OCPolarity);
 861
 862   /* Set the Output State */
 863   MODIFY_REG(tmpccer, TIM_CCER_CC1E, TIM_OCInitStruct->OCState);
 864
 865   if (IS_TIM_BREAK_INSTANCE(TIMx))
 866   {
 867     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 868     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 869
 870     /* Set the complementary output Polarity */
 871     MODIFY_REG(tmpccer, TIM_CCER_CC1NP, TIM_OCInitStruct->OCNPolarity << 2U);
 872
 873     /* Set the complementary output State */
 874     MODIFY_REG(tmpccer, TIM_CCER_CC1NE, TIM_OCInitStruct->OCNState << 2U);
 875
 876     /* Set the Output Idle state */
 877     MODIFY_REG(tmpcr2, TIM_CR2_OIS1, TIM_OCInitStruct->OCIdleState);
 878
 879     /* Set the complementary output Idle state */
 880     MODIFY_REG(tmpcr2, TIM_CR2_OIS1N, TIM_OCInitStruct->OCNIdleState << 1U);
 881   }
 882
 883   /* Write to TIMx CR2 */
 884   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 885
 886   /* Write to TIMx CCMR1 */
 887   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 888
 889   /* Set the Capture Compare Register value */
 890   LL_TIM_OC_SetCompareCH1(TIMx, TIM_OCInitStruct->CompareValue);
 891
 892   /* Write to TIMx CCER */
 893   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 894
 895   return SUCCESS;
 896 }
 897
 898 /**
 899   * @brief  Configure the TIMx output channel 2.
 900   * @param  TIMx Timer Instance
 901   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 2 configuration data structure
 902   * @retval An ErrorStatus enumeration value:
 903   *          - SUCCESS: TIMx registers are de-initialized
 904   *          - ERROR: not applicable
 905   */
 906 static ErrorStatus OC2Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 907 {
 908   uint32_t tmpccmr1 = 0U;
 909   uint32_t tmpccer = 0U;
 910   uint32_t tmpcr2 = 0U;
 911
 912   /* Check the parameters */
 913   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
 914   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 915   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 916   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 917   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 918   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 919
 920   /* Disable the Channel 2: Reset the CC2E Bit */
 921   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC2E);
 922
 923   /* Get the TIMx CCER register value */
 924   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
 925
 926   /* Get the TIMx CR2 register value */
 927   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
 928
 929   /* Get the TIMx CCMR1 register value */
 930   tmpccmr1 = LL_TIM_ReadReg(TIMx, CCMR1);
 931
 932   /* Reset Capture/Compare selection Bits */
 933   CLEAR_BIT(tmpccmr1, TIM_CCMR1_CC2S);
 934
 935   /* Select the Output Compare Mode */
 936   MODIFY_REG(tmpccmr1, TIM_CCMR1_OC2M, TIM_OCInitStruct->OCMode << 8U);
 937
 938   /* Set the Output Compare Polarity */
 939   MODIFY_REG(tmpccer, TIM_CCER_CC2P, TIM_OCInitStruct->OCPolarity << 4U);
 940
 941   /* Set the Output State */
 942   MODIFY_REG(tmpccer, TIM_CCER_CC2E, TIM_OCInitStruct->OCState << 4U);
 943
 944   if (IS_TIM_BREAK_INSTANCE(TIMx))
 945   {
 946     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
 947     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
 948
 949     /* Set the complementary output Polarity */
 950     MODIFY_REG(tmpccer, TIM_CCER_CC2NP, TIM_OCInitStruct->OCNPolarity << 6U);
 951
 952     /* Set the complementary output State */
 953     MODIFY_REG(tmpccer, TIM_CCER_CC2NE, TIM_OCInitStruct->OCNState << 6U);
 954
 955     /* Set the Output Idle state */
 956     MODIFY_REG(tmpcr2, TIM_CR2_OIS2, TIM_OCInitStruct->OCIdleState << 2U);
 957
 958     /* Set the complementary output Idle state */
 959     MODIFY_REG(tmpcr2, TIM_CR2_OIS2N, TIM_OCInitStruct->OCNIdleState << 3U);
 960   }
 961
 962   /* Write to TIMx CR2 */
 963   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
 964
 965   /* Write to TIMx CCMR1 */
 966   LL_TIM_WriteReg(TIMx, CCMR1, tmpccmr1);
 967
 968   /* Set the Capture Compare Register value */
 969   LL_TIM_OC_SetCompareCH2(TIMx, TIM_OCInitStruct->CompareValue);
 970
 971   /* Write to TIMx CCER */
 972   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
 973
 974   return SUCCESS;
 975 }
 976
 977 /**
 978   * @brief  Configure the TIMx output channel 3.
 979   * @param  TIMx Timer Instance
 980   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 3 configuration data structure
 981   * @retval An ErrorStatus enumeration value:
 982   *          - SUCCESS: TIMx registers are de-initialized
 983   *          - ERROR: not applicable
 984   */
 985 static ErrorStatus OC3Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
 986 {
 987   uint32_t tmpccmr2 = 0U;
 988   uint32_t tmpccer = 0U;
 989   uint32_t tmpcr2 = 0U;
 990
 991   /* Check the parameters */
 992   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
 993   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
 994   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
 995   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
 996   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
 997   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
 998
 999   /* Disable the Channel 3: Reset the CC3E Bit */
1000   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC3E);
1001
1002   /* Get the TIMx CCER register value */
1003   tmpccer =  LL_TIM_ReadReg(TIMx, CCER);
1004
1005   /* Get the TIMx CR2 register value */
1006   tmpcr2 = LL_TIM_ReadReg(TIMx, CR2);
1007
1008   /* Get the TIMx CCMR2 register value */
1009   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1010
1011   /* Reset Capture/Compare selection Bits */
1012   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC3S);
1013
1014   /* Select the Output Compare Mode */
1015   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC3M, TIM_OCInitStruct->OCMode);
1016
1017   /* Set the Output Compare Polarity */
1018   MODIFY_REG(tmpccer, TIM_CCER_CC3P, TIM_OCInitStruct->OCPolarity << 8U);
1019
1020   /* Set the Output State */
1021   MODIFY_REG(tmpccer, TIM_CCER_CC3E, TIM_OCInitStruct->OCState << 8U);
1022
1023   if (IS_TIM_BREAK_INSTANCE(TIMx))
1024   {
1025     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1026     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1027
1028     /* Set the complementary output Polarity */
1029     MODIFY_REG(tmpccer, TIM_CCER_CC3NP, TIM_OCInitStruct->OCNPolarity << 10U);
1030
1031     /* Set the complementary output State */
1032     MODIFY_REG(tmpccer, TIM_CCER_CC3NE, TIM_OCInitStruct->OCNState << 10U);
1033
1034     /* Set the Output Idle state */
1035     MODIFY_REG(tmpcr2, TIM_CR2_OIS3, TIM_OCInitStruct->OCIdleState << 4U);
1036
1037     /* Set the complementary output Idle state */
1038     MODIFY_REG(tmpcr2, TIM_CR2_OIS3N, TIM_OCInitStruct->OCNIdleState << 5U);
1039   }
1040
1041   /* Write to TIMx CR2 */
1042   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1043
1044   /* Write to TIMx CCMR2 */
1045   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1046
1047   /* Set the Capture Compare Register value */
1048   LL_TIM_OC_SetCompareCH3(TIMx, TIM_OCInitStruct->CompareValue);
1049
1050   /* Write to TIMx CCER */
1051   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1052
1053   return SUCCESS;
1054 }
1055
1056 /**
1057   * @brief  Configure the TIMx output channel 4.
1058   * @param  TIMx Timer Instance
1059   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 4 configuration data structure
1060   * @retval An ErrorStatus enumeration value:
1061   *          - SUCCESS: TIMx registers are de-initialized
1062   *          - ERROR: not applicable
1063   */
1064 static ErrorStatus OC4Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1065 {
1066   uint32_t tmpccmr2 = 0U;
1067   uint32_t tmpccer = 0U;
1068   uint32_t tmpcr2 = 0U;
1069
1070   /* Check the parameters */
1071   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1072   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1073   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1074   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1075   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1076   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1077
1078   /* Disable the Channel 4: Reset the CC4E Bit */
1079   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC4E);
1080
1081   /* Get the TIMx CCER register value */
1082   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1083
1084   /* Get the TIMx CR2 register value */
1085   tmpcr2 =  LL_TIM_ReadReg(TIMx, CR2);
1086
1087   /* Get the TIMx CCMR2 register value */
1088   tmpccmr2 = LL_TIM_ReadReg(TIMx, CCMR2);
1089
1090   /* Reset Capture/Compare selection Bits */
1091   CLEAR_BIT(tmpccmr2, TIM_CCMR2_CC4S);
1092
1093   /* Select the Output Compare Mode */
1094   MODIFY_REG(tmpccmr2, TIM_CCMR2_OC4M, TIM_OCInitStruct->OCMode << 8U);
1095
1096   /* Set the Output Compare Polarity */
1097   MODIFY_REG(tmpccer, TIM_CCER_CC4P, TIM_OCInitStruct->OCPolarity << 12U);
1098
1099   /* Set the Output State */
1100   MODIFY_REG(tmpccer, TIM_CCER_CC4E, TIM_OCInitStruct->OCState << 12U);
1101
1102   if (IS_TIM_BREAK_INSTANCE(TIMx))
1103   {
1104     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1105     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1106
1107     /* Set the Output Idle state */
1108     MODIFY_REG(tmpcr2, TIM_CR2_OIS4, TIM_OCInitStruct->OCIdleState << 6U);
1109   }
1110
1111   /* Write to TIMx CR2 */
1112   LL_TIM_WriteReg(TIMx, CR2, tmpcr2);
1113
1114   /* Write to TIMx CCMR2 */
1115   LL_TIM_WriteReg(TIMx, CCMR2, tmpccmr2);
1116
1117   /* Set the Capture Compare Register value */
1118   LL_TIM_OC_SetCompareCH4(TIMx, TIM_OCInitStruct->CompareValue);
1119
1120   /* Write to TIMx CCER */
1121   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1122
1123   return SUCCESS;
1124 }
1125
1126 /**
1127   * @brief  Configure the TIMx output channel 5.
1128   * @param  TIMx Timer Instance
1129   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 5 configuration data structure
1130   * @retval An ErrorStatus enumeration value:
1131   *          - SUCCESS: TIMx registers are de-initialized
1132   *          - ERROR: not applicable
1133   */
1134 static ErrorStatus OC5Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1135 {
1136   uint32_t tmpccmr3 = 0U;
1137   uint32_t tmpccer = 0U;
1138
1139   /* Check the parameters */
1140   assert_param(IS_TIM_CC5_INSTANCE(TIMx));
1141   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1142   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1143   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1144   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1145   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1146
1147   /* Disable the Channel 5: Reset the CC5E Bit */
1148   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC5E);
1149
1150   /* Get the TIMx CCER register value */
1151   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1152
1153   /* Get the TIMx CCMR3 register value */
1154   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1155
1156   /* Select the Output Compare Mode */
1157   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC5M, TIM_OCInitStruct->OCMode);
1158
1159   /* Set the Output Compare Polarity */
1160   MODIFY_REG(tmpccer, TIM_CCER_CC5P, TIM_OCInitStruct->OCPolarity << 16U);
1161
1162   /* Set the Output State */
1163   MODIFY_REG(tmpccer, TIM_CCER_CC5E, TIM_OCInitStruct->OCState << 16U);
1164
1165   if (IS_TIM_BREAK_INSTANCE(TIMx))
1166   {
1167     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1168     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1169
1170     /* Set the Output Idle state */
1171     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS5, TIM_OCInitStruct->OCIdleState << 8U);
1172
1173   }
1174
1175   /* Write to TIMx CCMR3 */
1176   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1177
1178   /* Set the Capture Compare Register value */
1179   LL_TIM_OC_SetCompareCH5(TIMx, TIM_OCInitStruct->CompareValue);
1180
1181   /* Write to TIMx CCER */
1182   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1183
1184   return SUCCESS;
1185 }
1186
1187 /**
1188   * @brief  Configure the TIMx output channel 6.
1189   * @param  TIMx Timer Instance
1190   * @param  TIM_OCInitStruct pointer to the the TIMx output channel 6 configuration data structure
1191   * @retval An ErrorStatus enumeration value:
1192   *          - SUCCESS: TIMx registers are de-initialized
1193   *          - ERROR: not applicable
1194   */
1195 static ErrorStatus OC6Config(TIM_TypeDef *TIMx, LL_TIM_OC_InitTypeDef *TIM_OCInitStruct)
1196 {
1197   uint32_t tmpccmr3 = 0U;
1198   uint32_t tmpccer = 0U;
1199
1200   /* Check the parameters */
1201   assert_param(IS_TIM_CC6_INSTANCE(TIMx));
1202   assert_param(IS_LL_TIM_OCMODE(TIM_OCInitStruct->OCMode));
1203   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCState));
1204   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCPolarity));
1205   assert_param(IS_LL_TIM_OCPOLARITY(TIM_OCInitStruct->OCNPolarity));
1206   assert_param(IS_LL_TIM_OCSTATE(TIM_OCInitStruct->OCNState));
1207
1208   /* Disable the Channel 5: Reset the CC6E Bit */
1209   CLEAR_BIT(TIMx->CCER, TIM_CCER_CC6E);
1210
1211   /* Get the TIMx CCER register value */
1212   tmpccer = LL_TIM_ReadReg(TIMx, CCER);
1213
1214   /* Get the TIMx CCMR3 register value */
1215   tmpccmr3 = LL_TIM_ReadReg(TIMx, CCMR3);
1216
1217   /* Select the Output Compare Mode */
1218   MODIFY_REG(tmpccmr3, TIM_CCMR3_OC6M, TIM_OCInitStruct->OCMode << 8U);
1219
1220   /* Set the Output Compare Polarity */
1221   MODIFY_REG(tmpccer, TIM_CCER_CC6P, TIM_OCInitStruct->OCPolarity << 20U);
1222
1223   /* Set the Output State */
1224   MODIFY_REG(tmpccer, TIM_CCER_CC6E, TIM_OCInitStruct->OCState << 20U);
1225
1226   if (IS_TIM_BREAK_INSTANCE(TIMx))
1227   {
1228     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCNIdleState));
1229     assert_param(IS_LL_TIM_OCIDLESTATE(TIM_OCInitStruct->OCIdleState));
1230
1231     /* Set the Output Idle state */
1232     MODIFY_REG(TIMx->CR2, TIM_CR2_OIS6, TIM_OCInitStruct->OCIdleState << 10U);
1233   }
1234
1235   /* Write to TIMx CCMR3 */
1236   LL_TIM_WriteReg(TIMx, CCMR3, tmpccmr3);
1237
1238   /* Set the Capture Compare Register value */
1239   LL_TIM_OC_SetCompareCH6(TIMx, TIM_OCInitStruct->CompareValue);
1240
1241   /* Write to TIMx CCER */
1242   LL_TIM_WriteReg(TIMx, CCER, tmpccer);
1243
1244   return SUCCESS;
1245 }
1246
1247 /**
1248   * @brief  Configure the TIMx input channel 1.
1249   * @param  TIMx Timer Instance
1250   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 1 configuration data structure
1251   * @retval An ErrorStatus enumeration value:
1252   *          - SUCCESS: TIMx registers are de-initialized
1253   *          - ERROR: not applicable
1254   */
1255 static ErrorStatus IC1Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1256 {
1257   /* Check the parameters */
1258   assert_param(IS_TIM_CC1_INSTANCE(TIMx));
1259   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1260   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1261   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1262   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1263
1264   /* Disable the Channel 1: Reset the CC1E Bit */
1265   TIMx->CCER &= (uint32_t)~TIM_CCER_CC1E;
1266
1267   /* Select the Input and set the filter and the prescaler value */
1268   MODIFY_REG(TIMx->CCMR1,
1269              (TIM_CCMR1_CC1S | TIM_CCMR1_IC1F | TIM_CCMR1_IC1PSC),
1270              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1271
1272   /* Select the Polarity and set the CC1E Bit */
1273   MODIFY_REG(TIMx->CCER,
1274              (TIM_CCER_CC1P | TIM_CCER_CC1NP),
1275              (TIM_ICInitStruct->ICPolarity | TIM_CCER_CC1E));
1276
1277   return SUCCESS;
1278 }
1279
1280 /**
1281   * @brief  Configure the TIMx input channel 2.
1282   * @param  TIMx Timer Instance
1283   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 2 configuration data structure
1284   * @retval An ErrorStatus enumeration value:
1285   *          - SUCCESS: TIMx registers are de-initialized
1286   *          - ERROR: not applicable
1287   */
1288 static ErrorStatus IC2Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1289 {
1290   /* Check the parameters */
1291   assert_param(IS_TIM_CC2_INSTANCE(TIMx));
1292   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1293   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1294   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1295   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1296
1297   /* Disable the Channel 2: Reset the CC2E Bit */
1298   TIMx->CCER &= (uint32_t)~TIM_CCER_CC2E;
1299
1300   /* Select the Input and set the filter and the prescaler value */
1301   MODIFY_REG(TIMx->CCMR1,
1302              (TIM_CCMR1_CC2S | TIM_CCMR1_IC2F | TIM_CCMR1_IC2PSC),
1303              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1304
1305   /* Select the Polarity and set the CC2E Bit */
1306   MODIFY_REG(TIMx->CCER,
1307              (TIM_CCER_CC2P | TIM_CCER_CC2NP),
1308              ((TIM_ICInitStruct->ICPolarity << 4U) | TIM_CCER_CC2E));
1309
1310   return SUCCESS;
1311 }
1312
1313 /**
1314   * @brief  Configure the TIMx input channel 3.
1315   * @param  TIMx Timer Instance
1316   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 3 configuration data structure
1317   * @retval An ErrorStatus enumeration value:
1318   *          - SUCCESS: TIMx registers are de-initialized
1319   *          - ERROR: not applicable
1320   */
1321 static ErrorStatus IC3Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1322 {
1323   /* Check the parameters */
1324   assert_param(IS_TIM_CC3_INSTANCE(TIMx));
1325   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1326   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1327   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1328   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1329
1330   /* Disable the Channel 3: Reset the CC3E Bit */
1331   TIMx->CCER &= (uint32_t)~TIM_CCER_CC3E;
1332
1333   /* Select the Input and set the filter and the prescaler value */
1334   MODIFY_REG(TIMx->CCMR2,
1335              (TIM_CCMR2_CC3S | TIM_CCMR2_IC3F | TIM_CCMR2_IC3PSC),
1336              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 16U);
1337
1338   /* Select the Polarity and set the CC3E Bit */
1339   MODIFY_REG(TIMx->CCER,
1340              (TIM_CCER_CC3P | TIM_CCER_CC3NP),
1341              ((TIM_ICInitStruct->ICPolarity << 8U) | TIM_CCER_CC3E));
1342
1343   return SUCCESS;
1344 }
1345
1346 /**
1347   * @brief  Configure the TIMx input channel 4.
1348   * @param  TIMx Timer Instance
1349   * @param  TIM_ICInitStruct pointer to the the TIMx input channel 4 configuration data structure
1350   * @retval An ErrorStatus enumeration value:
1351   *          - SUCCESS: TIMx registers are de-initialized
1352   *          - ERROR: not applicable
1353   */
1354 static ErrorStatus IC4Config(TIM_TypeDef *TIMx, LL_TIM_IC_InitTypeDef *TIM_ICInitStruct)
1355 {
1356   /* Check the parameters */
1357   assert_param(IS_TIM_CC4_INSTANCE(TIMx));
1358   assert_param(IS_LL_TIM_IC_POLARITY(TIM_ICInitStruct->ICPolarity));
1359   assert_param(IS_LL_TIM_ACTIVEINPUT(TIM_ICInitStruct->ICActiveInput));
1360   assert_param(IS_LL_TIM_ICPSC(TIM_ICInitStruct->ICPrescaler));
1361   assert_param(IS_LL_TIM_IC_FILTER(TIM_ICInitStruct->ICFilter));
1362
1363   /* Disable the Channel 4: Reset the CC4E Bit */
1364   TIMx->CCER &= (uint32_t)~TIM_CCER_CC4E;
1365
1366   /* Select the Input and set the filter and the prescaler value */
1367   MODIFY_REG(TIMx->CCMR2,
1368              (TIM_CCMR2_CC4S | TIM_CCMR2_IC4F | TIM_CCMR2_IC4PSC),
1369              (TIM_ICInitStruct->ICActiveInput | TIM_ICInitStruct->ICFilter | TIM_ICInitStruct->ICPrescaler) >> 8U);
1370
1371   /* Select the Polarity and set the CC2E Bit */
1372   MODIFY_REG(TIMx->CCER,
1373              (TIM_CCER_CC4P | TIM_CCER_CC4NP),
1374              ((TIM_ICInitStruct->ICPolarity << 12U) | TIM_CCER_CC4E));
1375
1376   return SUCCESS;
1377 }
1378
1379
1380 /**
1381   * @}
1382   */
1383
1384 /**
1385   * @}
1386   */
1387
1388 #endif /* TIM1 || TIM8 || TIM2 || TIM3 ||  TIM4 || TIM5 ||TIM9 || TIM10 || TIM11 || TIM12 || TIM13 || TIM14 || TIM6 || TIM7 */
1389
1390 /**
1391   * @}
1392   */
1393
1394 #endif /* USE_FULL_LL_DRIVER */
1395
1396 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/