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Merge pull request #10558 from iNavFlight/MrD_Correct-comments-on-OSD-symbols
[inav.git] / lib / main / STM32F7 / Drivers / STM32F7xx_HAL_Driver / Src / stm32f7xx_ll_usb.c
blobffc4f247fe7fea652d7a0efc303428df958cefc9
1 /**
2 ******************************************************************************
3 * @file stm32f7xx_ll_usb.c
4 * @author MCD Application Team
5 * @version V1.2.2
6 * @date 14-April-2017
7 * @brief USB Low Layer HAL module driver.
8 *
9 * This file provides firmware functions to manage the following
10 * functionalities of the USB Peripheral Controller:
11 * + Initialization/de-initialization functions
12 * + I/O operation functions
13 * + Peripheral Control functions
14 * + Peripheral State functions
15 *
16 @verbatim
17 ==============================================================================
18 ##### How to use this driver #####
19 ==============================================================================
20 [..]
21 (#) Fill parameters of Init structure in USB_OTG_CfgTypeDef structure.
22
23 (#) Call USB_CoreInit() API to initialize the USB Core peripheral.
24
25 (#) The upper HAL HCD/PCD driver will call the right routines for its internal processes.
26
27 @endverbatim
28 ******************************************************************************
29 * @attention
30 *
31 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics</center></h2>
32 *
33 * Redistribution and use in source and binary forms, with or without modification,
34 * are permitted provided that the following conditions are met:
35 * 1. Redistributions of source code must retain the above copyright notice,
36 * this list of conditions and the following disclaimer.
37 * 2. Redistributions in binary form must reproduce the above copyright notice,
38 * this list of conditions and the following disclaimer in the documentation
39 * and/or other materials provided with the distribution.
40 * 3. Neither the name of STMicroelectronics nor the names of its contributors
41 * may be used to endorse or promote products derived from this software
42 * without specific prior written permission.
43 *
44 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
45 * AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
46 * IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE
47 * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE
48 * FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
49 * DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
50 * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
51 * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
52 * OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
53 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
54 *
55 ******************************************************************************
56 */
57
58 /* Includes ------------------------------------------------------------------*/
59 #include "stm32f7xx_hal.h"
60
61 /** @addtogroup STM32F7xx_LL_USB_DRIVER
62 * @{
63 */
64
65 #if defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED)
66
67 /* Private typedef -----------------------------------------------------------*/
68 /* Private define ------------------------------------------------------------*/
69 /* Private macro -------------------------------------------------------------*/
70 /* Private variables ---------------------------------------------------------*/
71 /* Private function prototypes -----------------------------------------------*/
72 /* Private functions ---------------------------------------------------------*/
73 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx);
74
75 #ifdef USB_HS_PHYC
76 static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx);
77 #endif
78
79 /* Exported functions --------------------------------------------------------*/
80 /** @defgroup LL_USB_Exported_Functions USB Low Layer Exported Functions
81 * @{
82 */
83
84 /** @defgroup LL_USB_Group1 Initialization/de-initialization functions
85 * @brief Initialization and Configuration functions
86 *
87 @verbatim
88 ===============================================================================
89 ##### Initialization/de-initialization functions #####
90 ===============================================================================
91 [..] This section provides functions allowing to:
92
93 @endverbatim
94 * @{
95 */
96
97 /**
98 * @brief Initializes the USB Core
99 * @param USBx: USB Instance
100 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
101 * the configuration information for the specified USBx peripheral.
102 * @retval HAL status
103 */
104 HAL_StatusTypeDef USB_CoreInit(USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
105 {
106 if (cfg.phy_itface == USB_OTG_ULPI_PHY)
107 {
108
109 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
110
111 /* Init The ULPI Interface */
112 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
113
114 /* Select vbus source */
115 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
116 if(cfg.use_external_vbus == 1)
117 {
118 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
119 }
120 /* Reset after a PHY select */
121 USB_CoreReset(USBx);
122 }
123 #ifdef USB_HS_PHYC
124
125 else if (cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
126 {
127 USBx->GCCFG &= ~(USB_OTG_GCCFG_PWRDWN);
128
129 /* Init The UTMI Interface */
130 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_TSDPS | USB_OTG_GUSBCFG_ULPIFSLS | USB_OTG_GUSBCFG_PHYSEL);
131
132 /* Select vbus source */
133 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_ULPIEVBUSD | USB_OTG_GUSBCFG_ULPIEVBUSI);
134
135 /* Select UTMI Interace */
136 USBx->GUSBCFG &= ~ USB_OTG_GUSBCFG_ULPI_UTMI_SEL;
137 USBx->GCCFG |= USB_OTG_GCCFG_PHYHSEN;
138
139 /* Enables control of a High Speed USB PHY */
140 USB_HS_PHYCInit(USBx);
141
142 if(cfg.use_external_vbus == 1)
143 {
144 USBx->GUSBCFG |= USB_OTG_GUSBCFG_ULPIEVBUSD;
145 }
146 /* Reset after a PHY select */
147 USB_CoreReset(USBx);
148
149 }
150 #endif
151 else /* FS interface (embedded Phy) */
152 {
153 /* Select FS Embedded PHY */
154 USBx->GUSBCFG |= USB_OTG_GUSBCFG_PHYSEL;
155
156 /* Reset after a PHY select and set Host mode */
157 USB_CoreReset(USBx);
158
159 /* Deactivate the power down*/
160 USBx->GCCFG = USB_OTG_GCCFG_PWRDWN;
161 }
162
163 if(cfg.dma_enable == ENABLE)
164 {
165 USBx->GAHBCFG |= USB_OTG_GAHBCFG_HBSTLEN_2;
166 USBx->GAHBCFG |= USB_OTG_GAHBCFG_DMAEN;
167 }
168
169 return HAL_OK;
170 }
171
172 /**
173 * @brief USB_EnableGlobalInt
174 * Enables the controller's Global Int in the AHB Config reg
175 * @param USBx : Selected device
176 * @retval HAL status
177 */
178 HAL_StatusTypeDef USB_EnableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
179 {
180 USBx->GAHBCFG |= USB_OTG_GAHBCFG_GINT;
181 return HAL_OK;
182 }
183
184
185 /**
186 * @brief USB_DisableGlobalInt
187 * Disable the controller's Global Int in the AHB Config reg
188 * @param USBx : Selected device
189 * @retval HAL status
190 */
191 HAL_StatusTypeDef USB_DisableGlobalInt(USB_OTG_GlobalTypeDef *USBx)
192 {
193 USBx->GAHBCFG &= ~USB_OTG_GAHBCFG_GINT;
194 return HAL_OK;
195 }
196
197 /**
198 * @brief USB_SetCurrentMode : Set functional mode
199 * @param USBx : Selected device
200 * @param mode : current core mode
201 * This parameter can be one of these values:
202 * @arg USB_OTG_DEVICE_MODE: Peripheral mode
203 * @arg USB_OTG_HOST_MODE: Host mode
204 * @arg USB_OTG_DRD_MODE: Dual Role Device mode
205 * @retval HAL status
206 */
207 HAL_StatusTypeDef USB_SetCurrentMode(USB_OTG_GlobalTypeDef *USBx , USB_OTG_ModeTypeDef mode)
208 {
209 USBx->GUSBCFG &= ~(USB_OTG_GUSBCFG_FHMOD | USB_OTG_GUSBCFG_FDMOD);
210
211 if ( mode == USB_OTG_HOST_MODE)
212 {
213 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FHMOD;
214 }
215 else if ( mode == USB_OTG_DEVICE_MODE)
216 {
217 USBx->GUSBCFG |= USB_OTG_GUSBCFG_FDMOD;
218 }
219 HAL_Delay(50);
220
221 return HAL_OK;
222 }
223
224 /**
225 * @brief USB_DevInit : Initializes the USB_OTG controller registers
226 * for device mode
227 * @param USBx : Selected device
228 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
229 * the configuration information for the specified USBx peripheral.
230 * @retval HAL status
231 */
232 HAL_StatusTypeDef USB_DevInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
233 {
234 uint32_t i = 0;
235
236 /*Activate VBUS Sensing B */
237 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
238
239 if (cfg.vbus_sensing_enable == 0)
240 {
241 /* Deactivate VBUS Sensing B */
242 USBx->GCCFG &= ~ USB_OTG_GCCFG_VBDEN;
243
244 /* B-peripheral session valid override enable*/
245 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOEN;
246 USBx->GOTGCTL |= USB_OTG_GOTGCTL_BVALOVAL;
247 }
248
249 /* Restart the Phy Clock */
250 USBx_PCGCCTL = 0;
251
252 /* Device mode configuration */
253 USBx_DEVICE->DCFG |= DCFG_FRAME_INTERVAL_80;
254
255 if(cfg.phy_itface == USB_OTG_ULPI_PHY)
256 {
257 if(cfg.speed == USB_OTG_SPEED_HIGH)
258 {
259 /* Set High speed phy */
260 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
261 }
262 else
263 {
264 /* set High speed phy in Full speed mode */
265 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
266 }
267 }
268
269 else if(cfg.phy_itface == USB_OTG_HS_EMBEDDED_PHY)
270 {
271 if(cfg.speed == USB_OTG_SPEED_HIGH)
272 {
273 /* Set High speed phy */
274 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH);
275 }
276 else
277 {
278 /* set High speed phy in Full speed mode */
279 USB_SetDevSpeed (USBx , USB_OTG_SPEED_HIGH_IN_FULL);
280 }
281 }
282
283 else
284 {
285 /* Set Full speed phy */
286 USB_SetDevSpeed (USBx , USB_OTG_SPEED_FULL);
287 }
288
289 /* Flush the FIFOs */
290 USB_FlushTxFifo(USBx , 0x10); /* all Tx FIFOs */
291 USB_FlushRxFifo(USBx);
292
293 /* Clear all pending Device Interrupts */
294 USBx_DEVICE->DIEPMSK = 0;
295 USBx_DEVICE->DOEPMSK = 0;
296 USBx_DEVICE->DAINT = 0xFFFFFFFF;
297 USBx_DEVICE->DAINTMSK = 0;
298
299 for (i = 0; i < cfg.dev_endpoints; i++)
300 {
301 if ((USBx_INEP(i)->DIEPCTL & USB_OTG_DIEPCTL_EPENA) == USB_OTG_DIEPCTL_EPENA)
302 {
303 USBx_INEP(i)->DIEPCTL = (USB_OTG_DIEPCTL_EPDIS | USB_OTG_DIEPCTL_SNAK);
304 }
305 else
306 {
307 USBx_INEP(i)->DIEPCTL = 0;
308 }
309
310 USBx_INEP(i)->DIEPTSIZ = 0;
311 USBx_INEP(i)->DIEPINT = 0xFF;
312 }
313
314 for (i = 0; i < cfg.dev_endpoints; i++)
315 {
316 if ((USBx_OUTEP(i)->DOEPCTL & USB_OTG_DOEPCTL_EPENA) == USB_OTG_DOEPCTL_EPENA)
317 {
318 USBx_OUTEP(i)->DOEPCTL = (USB_OTG_DOEPCTL_EPDIS | USB_OTG_DOEPCTL_SNAK);
319 }
320 else
321 {
322 USBx_OUTEP(i)->DOEPCTL = 0;
323 }
324
325 USBx_OUTEP(i)->DOEPTSIZ = 0;
326 USBx_OUTEP(i)->DOEPINT = 0xFF;
327 }
328
329 USBx_DEVICE->DIEPMSK &= ~(USB_OTG_DIEPMSK_TXFURM);
330
331 if (cfg.dma_enable == 1)
332 {
333 /*Set threshold parameters */
334 USBx_DEVICE->DTHRCTL = (USB_OTG_DTHRCTL_TXTHRLEN_6 | USB_OTG_DTHRCTL_RXTHRLEN_6);
335 USBx_DEVICE->DTHRCTL |= (USB_OTG_DTHRCTL_RXTHREN | USB_OTG_DTHRCTL_ISOTHREN | USB_OTG_DTHRCTL_NONISOTHREN);
336
337 i= USBx_DEVICE->DTHRCTL;
338 }
339
340 /* Disable all interrupts. */
341 USBx->GINTMSK = 0;
342
343 /* Clear any pending interrupts */
344 USBx->GINTSTS = 0xBFFFFFFF;
345
346 /* Enable the common interrupts */
347 if (cfg.dma_enable == DISABLE)
348 {
349 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
350 }
351
352 /* Enable interrupts matching to the Device mode ONLY */
353 USBx->GINTMSK |= (USB_OTG_GINTMSK_USBSUSPM | USB_OTG_GINTMSK_USBRST |\
354 USB_OTG_GINTMSK_ENUMDNEM | USB_OTG_GINTMSK_IEPINT |\
355 USB_OTG_GINTMSK_OEPINT | USB_OTG_GINTMSK_IISOIXFRM|\
356 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
357
358 if(cfg.Sof_enable)
359 {
360 USBx->GINTMSK |= USB_OTG_GINTMSK_SOFM;
361 }
362
363 if (cfg.vbus_sensing_enable == ENABLE)
364 {
365 USBx->GINTMSK |= (USB_OTG_GINTMSK_SRQIM | USB_OTG_GINTMSK_OTGINT);
366 }
367
368 return HAL_OK;
369 }
370
371
372 /**
373 * @brief USB_OTG_FlushTxFifo : Flush a Tx FIFO
374 * @param USBx : Selected device
375 * @param num : FIFO number
376 * This parameter can be a value from 1 to 15
377 15 means Flush all Tx FIFOs
378 * @retval HAL status
379 */
380 HAL_StatusTypeDef USB_FlushTxFifo (USB_OTG_GlobalTypeDef *USBx, uint32_t num )
381 {
382 uint32_t count = 0;
383
384 USBx->GRSTCTL = ( USB_OTG_GRSTCTL_TXFFLSH |(uint32_t)( num << 6));
385
386 do
387 {
388 if (++count > 200000)
389 {
390 return HAL_TIMEOUT;
391 }
392 }
393 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_TXFFLSH) == USB_OTG_GRSTCTL_TXFFLSH);
394
395 return HAL_OK;
396 }
397
398
399 /**
400 * @brief USB_FlushRxFifo : Flush Rx FIFO
401 * @param USBx : Selected device
402 * @retval HAL status
403 */
404 HAL_StatusTypeDef USB_FlushRxFifo(USB_OTG_GlobalTypeDef *USBx)
405 {
406 uint32_t count = 0;
407
408 USBx->GRSTCTL = USB_OTG_GRSTCTL_RXFFLSH;
409
410 do
411 {
412 if (++count > 200000)
413 {
414 return HAL_TIMEOUT;
415 }
416 }
417 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_RXFFLSH) == USB_OTG_GRSTCTL_RXFFLSH);
418
419 return HAL_OK;
420 }
421
422 /**
423 * @brief USB_SetDevSpeed :Initializes the DevSpd field of DCFG register
424 * depending the PHY type and the enumeration speed of the device.
425 * @param USBx : Selected device
426 * @param speed : device speed
427 * This parameter can be one of these values:
428 * @arg USB_OTG_SPEED_HIGH: High speed mode
429 * @arg USB_OTG_SPEED_HIGH_IN_FULL: High speed core in Full Speed mode
430 * @arg USB_OTG_SPEED_FULL: Full speed mode
431 * @arg USB_OTG_SPEED_LOW: Low speed mode
432 * @retval Hal status
433 */
434 HAL_StatusTypeDef USB_SetDevSpeed(USB_OTG_GlobalTypeDef *USBx , uint8_t speed)
435 {
436 USBx_DEVICE->DCFG |= speed;
437 return HAL_OK;
438 }
439
440 /**
441 * @brief USB_GetDevSpeed :Return the Dev Speed
442 * @param USBx : Selected device
443 * @retval speed : device speed
444 * This parameter can be one of these values:
445 * @arg USB_OTG_SPEED_HIGH: High speed mode
446 * @arg USB_OTG_SPEED_FULL: Full speed mode
447 * @arg USB_OTG_SPEED_LOW: Low speed mode
448 */
449 uint8_t USB_GetDevSpeed(USB_OTG_GlobalTypeDef *USBx)
450 {
451 uint8_t speed = 0;
452
453 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_HS_PHY_30MHZ_OR_60MHZ)
454 {
455 speed = USB_OTG_SPEED_HIGH;
456 }
457 else if (((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_30MHZ_OR_60MHZ)||
458 ((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_FS_PHY_48MHZ))
459 {
460 speed = USB_OTG_SPEED_FULL;
461 }
462 else if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
463 {
464 speed = USB_OTG_SPEED_LOW;
465 }
466
467 return speed;
468 }
469
470 /**
471 * @brief Activate and configure an endpoint
472 * @param USBx : Selected device
473 * @param ep: pointer to endpoint structure
474 * @retval HAL status
475 */
476 HAL_StatusTypeDef USB_ActivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
477 {
478 if (ep->is_in == 1)
479 {
480 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
481
482 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
483 {
484 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
485 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
486 }
487
488 }
489 else
490 {
491 USBx_DEVICE->DAINTMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
492
493 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
494 {
495 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
496 (USB_OTG_DIEPCTL_SD0PID_SEVNFRM)| (USB_OTG_DOEPCTL_USBAEP));
497 }
498 }
499 return HAL_OK;
500 }
501 /**
502 * @brief Activate and configure a dedicated endpoint
503 * @param USBx : Selected device
504 * @param ep: pointer to endpoint structure
505 * @retval HAL status
506 */
507 HAL_StatusTypeDef USB_ActivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
508 {
509 static __IO uint32_t debug = 0;
510
511 /* Read DEPCTLn register */
512 if (ep->is_in == 1)
513 {
514 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_USBAEP) == 0)
515 {
516 USBx_INEP(ep->num)->DIEPCTL |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
517 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
518 }
519
520
521 debug |= ((ep->maxpacket & USB_OTG_DIEPCTL_MPSIZ ) | (ep->type << 18 ) |\
522 ((ep->num) << 22 ) | (USB_OTG_DIEPCTL_SD0PID_SEVNFRM) | (USB_OTG_DIEPCTL_USBAEP));
523
524 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num)));
525 }
526 else
527 {
528 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_USBAEP) == 0)
529 {
530 USBx_OUTEP(ep->num)->DOEPCTL |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
531 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
532
533 debug = (uint32_t)(((uint32_t )USBx) + USB_OTG_OUT_ENDPOINT_BASE + (0)*USB_OTG_EP_REG_SIZE);
534 debug = (uint32_t )&USBx_OUTEP(ep->num)->DOEPCTL;
535 debug |= ((ep->maxpacket & USB_OTG_DOEPCTL_MPSIZ ) | (ep->type << 18 ) |\
536 ((ep->num) << 22 ) | (USB_OTG_DOEPCTL_USBAEP));
537 }
538
539 USBx_DEVICE->DEACHMSK |= USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16);
540 }
541
542 return HAL_OK;
543 }
544 /**
545 * @brief De-activate and de-initialize an endpoint
546 * @param USBx : Selected device
547 * @param ep: pointer to endpoint structure
548 * @retval HAL status
549 */
550 HAL_StatusTypeDef USB_DeactivateEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
551 {
552 /* Read DEPCTLn register */
553 if (ep->is_in == 1)
554 {
555 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
556 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
557 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
558 }
559 else
560 {
561 USBx_DEVICE->DEACHMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
562 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
563 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
564 }
565 return HAL_OK;
566 }
567
568 /**
569 * @brief De-activate and de-initialize a dedicated endpoint
570 * @param USBx : Selected device
571 * @param ep: pointer to endpoint structure
572 * @retval HAL status
573 */
574 HAL_StatusTypeDef USB_DeactivateDedicatedEndpoint(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
575 {
576 /* Read DEPCTLn register */
577 if (ep->is_in == 1)
578 {
579 USBx_INEP(ep->num)->DIEPCTL &= ~ USB_OTG_DIEPCTL_USBAEP;
580 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_IEPM & ((1 << (ep->num))));
581 }
582 else
583 {
584 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_USBAEP;
585 USBx_DEVICE->DAINTMSK &= ~(USB_OTG_DAINTMSK_OEPM & ((1 << (ep->num)) << 16));
586 }
587 return HAL_OK;
588 }
589
590 /**
591 * @brief USB_EPStartXfer : setup and starts a transfer over an EP
592 * @param USBx : Selected device
593 * @param ep: pointer to endpoint structure
594 * @param dma: USB dma enabled or disabled
595 * This parameter can be one of these values:
596 * 0 : DMA feature not used
597 * 1 : DMA feature used
598 * @retval HAL status
599 */
600 HAL_StatusTypeDef USB_EPStartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
601 {
602 uint16_t pktcnt = 0;
603
604 /* IN endpoint */
605 if (ep->is_in == 1)
606 {
607 /* Zero Length Packet? */
608 if (ep->xfer_len == 0)
609 {
610 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
611 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
612 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
613 }
614 else
615 {
616 /* Program the transfer size and packet count
617 * as follows: xfersize = N * maxpacket +
618 * short_packet pktcnt = N + (short_packet
619 * exist ? 1 : 0)
620 */
621 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
622 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
623 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (((ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket) << 19)) ;
624 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
625
626 if (ep->type == EP_TYPE_ISOC)
627 {
628 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_MULCNT);
629 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_MULCNT & (1 << 29));
630 }
631 }
632
633 if (dma == 1)
634 {
635 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
636 }
637 else
638 {
639 if (ep->type != EP_TYPE_ISOC)
640 {
641 /* Enable the Tx FIFO Empty Interrupt for this EP */
642 if (ep->xfer_len > 0)
643 {
644 USBx_DEVICE->DIEPEMPMSK |= 1 << ep->num;
645 }
646 }
647 }
648
649 if (ep->type == EP_TYPE_ISOC)
650 {
651 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
652 {
653 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SODDFRM;
654 }
655 else
656 {
657 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM;
658 }
659 }
660
661 /* EP enable, IN data in FIFO */
662 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
663
664 if (ep->type == EP_TYPE_ISOC)
665 {
666 USB_WritePacket(USBx, ep->xfer_buff, ep->num, ep->xfer_len, dma);
667 }
668 }
669 else /* OUT endpoint */
670 {
671 /* Program the transfer size and packet count as follows:
672 * pktcnt = N
673 * xfersize = N * maxpacket
674 */
675 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
676 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
677
678 if (ep->xfer_len == 0)
679 {
680 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & ep->maxpacket);
681 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
682 }
683 else
684 {
685 pktcnt = (ep->xfer_len + ep->maxpacket -1)/ ep->maxpacket;
686 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (pktcnt << 19));
687 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket * pktcnt));
688 }
689
690 if (dma == 1)
691 {
692 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)ep->xfer_buff;
693 }
694
695 if (ep->type == EP_TYPE_ISOC)
696 {
697 if ((USBx_DEVICE->DSTS & ( 1 << 8 )) == 0)
698 {
699 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SODDFRM;
700 }
701 else
702 {
703 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM;
704 }
705 }
706 /* EP enable */
707 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
708 }
709 return HAL_OK;
710 }
711
712 /**
713 * @brief USB_EP0StartXfer : setup and starts a transfer over the EP 0
714 * @param USBx : Selected device
715 * @param ep: pointer to endpoint structure
716 * @param dma: USB dma enabled or disabled
717 * This parameter can be one of these values:
718 * 0 : DMA feature not used
719 * 1 : DMA feature used
720 * @retval HAL status
721 */
722 HAL_StatusTypeDef USB_EP0StartXfer(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep, uint8_t dma)
723 {
724 /* IN endpoint */
725 if (ep->is_in == 1)
726 {
727 /* Zero Length Packet? */
728 if (ep->xfer_len == 0)
729 {
730 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
731 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
732 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
733 }
734 else
735 {
736 /* Program the transfer size and packet count
737 * as follows: xfersize = N * maxpacket +
738 * short_packet pktcnt = N + (short_packet
739 * exist ? 1 : 0)
740 */
741 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_XFRSIZ);
742 USBx_INEP(ep->num)->DIEPTSIZ &= ~(USB_OTG_DIEPTSIZ_PKTCNT);
743
744 if(ep->xfer_len > ep->maxpacket)
745 {
746 ep->xfer_len = ep->maxpacket;
747 }
748 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_PKTCNT & (1 << 19)) ;
749 USBx_INEP(ep->num)->DIEPTSIZ |= (USB_OTG_DIEPTSIZ_XFRSIZ & ep->xfer_len);
750
751 }
752
753 /* EP enable, IN data in FIFO */
754 USBx_INEP(ep->num)->DIEPCTL |= (USB_OTG_DIEPCTL_CNAK | USB_OTG_DIEPCTL_EPENA);
755
756 if (dma == 1)
757 {
758 USBx_INEP(ep->num)->DIEPDMA = (uint32_t)(ep->dma_addr);
759 }
760 else
761 {
762 /* Enable the Tx FIFO Empty Interrupt for this EP */
763 if (ep->xfer_len > 0U)
764 {
765 USBx_DEVICE->DIEPEMPMSK |= 1U << (ep->num);
766 }
767 }
768 }
769 else /* OUT endpoint */
770 {
771 /* Program the transfer size and packet count as follows:
772 * pktcnt = N
773 * xfersize = N * maxpacket
774 */
775 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_XFRSIZ);
776 USBx_OUTEP(ep->num)->DOEPTSIZ &= ~(USB_OTG_DOEPTSIZ_PKTCNT);
777
778 if (ep->xfer_len > 0)
779 {
780 ep->xfer_len = ep->maxpacket;
781 }
782
783 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19));
784 USBx_OUTEP(ep->num)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_XFRSIZ & (ep->maxpacket));
785
786
787 if (dma == 1)
788 {
789 USBx_OUTEP(ep->num)->DOEPDMA = (uint32_t)(ep->xfer_buff);
790 }
791
792 /* EP enable */
793 USBx_OUTEP(ep->num)->DOEPCTL |= (USB_OTG_DOEPCTL_CNAK | USB_OTG_DOEPCTL_EPENA);
794 }
795 return HAL_OK;
796 }
797
798 /**
799 * @brief USB_WritePacket : Writes a packet into the Tx FIFO associated
800 * with the EP/channel
801 * @param USBx : Selected device
802 * @param src : pointer to source buffer
803 * @param ch_ep_num : endpoint or host channel number
804 * @param len : Number of bytes to write
805 * @param dma: USB dma enabled or disabled
806 * This parameter can be one of these values:
807 * 0 : DMA feature not used
808 * 1 : DMA feature used
809 * @retval HAL status
810 */
811 HAL_StatusTypeDef USB_WritePacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *src, uint8_t ch_ep_num, uint16_t len, uint8_t dma)
812 {
813 uint32_t count32b= 0 , i= 0;
814
815 if (dma == 0)
816 {
817 count32b = (len + 3) / 4;
818 for (i = 0; i < count32b; i++, src += 4)
819 {
820 USBx_DFIFO(ch_ep_num) = *((uint32_t *)src);
821 }
822 }
823 return HAL_OK;
824 }
825
826 /**
827 * @brief USB_ReadPacket : read a packet from the Tx FIFO associated
828 * with the EP/channel
829 * @param USBx : Selected device
830 * @param src : source pointer
831 * @param ch_ep_num : endpoint or host channel number
832 * @param len : Number of bytes to read
833 * @param dma: USB dma enabled or disabled
834 * This parameter can be one of these values:
835 * 0 : DMA feature not used
836 * 1 : DMA feature used
837 * @retval pointer to destination buffer
838 */
839 void *USB_ReadPacket(USB_OTG_GlobalTypeDef *USBx, uint8_t *dest, uint16_t len)
840 {
841 uint32_t i=0;
842 uint32_t count32b = (len + 3) / 4;
843
844 for ( i = 0; i < count32b; i++, dest += 4 )
845 {
846 *(uint32_t *)dest = USBx_DFIFO(0);
847
848 }
849 return ((void *)dest);
850 }
851
852 /**
853 * @brief USB_EPSetStall : set a stall condition over an EP
854 * @param USBx : Selected device
855 * @param ep: pointer to endpoint structure
856 * @retval HAL status
857 */
858 HAL_StatusTypeDef USB_EPSetStall(USB_OTG_GlobalTypeDef *USBx , USB_OTG_EPTypeDef *ep)
859 {
860 if (ep->is_in == 1)
861 {
862 if (((USBx_INEP(ep->num)->DIEPCTL) & USB_OTG_DIEPCTL_EPENA) == 0)
863 {
864 USBx_INEP(ep->num)->DIEPCTL &= ~(USB_OTG_DIEPCTL_EPDIS);
865 }
866 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_STALL;
867 }
868 else
869 {
870 if (((USBx_OUTEP(ep->num)->DOEPCTL) & USB_OTG_DOEPCTL_EPENA) == 0)
871 {
872 USBx_OUTEP(ep->num)->DOEPCTL &= ~(USB_OTG_DOEPCTL_EPDIS);
873 }
874 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_STALL;
875 }
876 return HAL_OK;
877 }
878
879
880 /**
881 * @brief USB_EPClearStall : Clear a stall condition over an EP
882 * @param USBx : Selected device
883 * @param ep: pointer to endpoint structure
884 * @retval HAL status
885 */
886 HAL_StatusTypeDef USB_EPClearStall(USB_OTG_GlobalTypeDef *USBx, USB_OTG_EPTypeDef *ep)
887 {
888 if (ep->is_in == 1)
889 {
890 USBx_INEP(ep->num)->DIEPCTL &= ~USB_OTG_DIEPCTL_STALL;
891 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
892 {
893 USBx_INEP(ep->num)->DIEPCTL |= USB_OTG_DIEPCTL_SD0PID_SEVNFRM; /* DATA0 */
894 }
895 }
896 else
897 {
898 USBx_OUTEP(ep->num)->DOEPCTL &= ~USB_OTG_DOEPCTL_STALL;
899 if (ep->type == EP_TYPE_INTR || ep->type == EP_TYPE_BULK)
900 {
901 USBx_OUTEP(ep->num)->DOEPCTL |= USB_OTG_DOEPCTL_SD0PID_SEVNFRM; /* DATA0 */
902 }
903 }
904 return HAL_OK;
905 }
906
907 /**
908 * @brief USB_StopDevice : Stop the usb device mode
909 * @param USBx : Selected device
910 * @retval HAL status
911 */
912 HAL_StatusTypeDef USB_StopDevice(USB_OTG_GlobalTypeDef *USBx)
913 {
914 uint32_t i;
915
916 /* Clear Pending interrupt */
917 for (i = 0; i < 15 ; i++)
918 {
919 USBx_INEP(i)->DIEPINT = 0xFF;
920 USBx_OUTEP(i)->DOEPINT = 0xFF;
921 }
922 USBx_DEVICE->DAINT = 0xFFFFFFFF;
923
924 /* Clear interrupt masks */
925 USBx_DEVICE->DIEPMSK = 0;
926 USBx_DEVICE->DOEPMSK = 0;
927 USBx_DEVICE->DAINTMSK = 0;
928
929 /* Flush the FIFO */
930 USB_FlushRxFifo(USBx);
931 USB_FlushTxFifo(USBx , 0x10 );
932
933 return HAL_OK;
934 }
935
936 /**
937 * @brief USB_SetDevAddress : Stop the usb device mode
938 * @param USBx : Selected device
939 * @param address : new device address to be assigned
940 * This parameter can be a value from 0 to 255
941 * @retval HAL status
942 */
943 HAL_StatusTypeDef USB_SetDevAddress (USB_OTG_GlobalTypeDef *USBx, uint8_t address)
944 {
945 USBx_DEVICE->DCFG &= ~ (USB_OTG_DCFG_DAD);
946 USBx_DEVICE->DCFG |= (address << 4) & USB_OTG_DCFG_DAD ;
947
948 return HAL_OK;
949 }
950
951 /**
952 * @brief USB_DevConnect : Connect the USB device by enabling the pull-up/pull-down
953 * @param USBx : Selected device
954 * @retval HAL status
955 */
956 HAL_StatusTypeDef USB_DevConnect (USB_OTG_GlobalTypeDef *USBx)
957 {
958 USBx_DEVICE->DCTL &= ~USB_OTG_DCTL_SDIS ;
959 HAL_Delay(3);
960
961 return HAL_OK;
962 }
963
964 /**
965 * @brief USB_DevDisconnect : Disconnect the USB device by disabling the pull-up/pull-down
966 * @param USBx : Selected device
967 * @retval HAL status
968 */
969 HAL_StatusTypeDef USB_DevDisconnect (USB_OTG_GlobalTypeDef *USBx)
970 {
971 USBx_DEVICE->DCTL |= USB_OTG_DCTL_SDIS ;
972 HAL_Delay(3);
973
974 return HAL_OK;
975 }
976
977 /**
978 * @brief USB_ReadInterrupts: return the global USB interrupt status
979 * @param USBx : Selected device
980 * @retval HAL status
981 */
982 uint32_t USB_ReadInterrupts (USB_OTG_GlobalTypeDef *USBx)
983 {
984 uint32_t v = 0;
985
986 v = USBx->GINTSTS;
987 v &= USBx->GINTMSK;
988 return v;
989 }
990
991 /**
992 * @brief USB_ReadDevAllOutEpInterrupt: return the USB device OUT endpoints interrupt status
993 * @param USBx : Selected device
994 * @retval HAL status
995 */
996 uint32_t USB_ReadDevAllOutEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
997 {
998 uint32_t v;
999 v = USBx_DEVICE->DAINT;
1000 v &= USBx_DEVICE->DAINTMSK;
1001 return ((v & 0xffff0000) >> 16);
1002 }
1003
1004 /**
1005 * @brief USB_ReadDevAllInEpInterrupt: return the USB device IN endpoints interrupt status
1006 * @param USBx : Selected device
1007 * @retval HAL status
1008 */
1009 uint32_t USB_ReadDevAllInEpInterrupt (USB_OTG_GlobalTypeDef *USBx)
1010 {
1011 uint32_t v;
1012 v = USBx_DEVICE->DAINT;
1013 v &= USBx_DEVICE->DAINTMSK;
1014 return ((v & 0xFFFF));
1015 }
1016
1017 /**
1018 * @brief Returns Device OUT EP Interrupt register
1019 * @param USBx : Selected device
1020 * @param epnum : endpoint number
1021 * This parameter can be a value from 0 to 15
1022 * @retval Device OUT EP Interrupt register
1023 */
1024 uint32_t USB_ReadDevOutEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
1025 {
1026 uint32_t v;
1027 v = USBx_OUTEP(epnum)->DOEPINT;
1028 v &= USBx_DEVICE->DOEPMSK;
1029 return v;
1030 }
1031
1032 /**
1033 * @brief Returns Device IN EP Interrupt register
1034 * @param USBx : Selected device
1035 * @param epnum : endpoint number
1036 * This parameter can be a value from 0 to 15
1037 * @retval Device IN EP Interrupt register
1038 */
1039 uint32_t USB_ReadDevInEPInterrupt (USB_OTG_GlobalTypeDef *USBx , uint8_t epnum)
1040 {
1041 uint32_t v, msk, emp;
1042
1043 msk = USBx_DEVICE->DIEPMSK;
1044 emp = USBx_DEVICE->DIEPEMPMSK;
1045 msk |= ((emp >> epnum) & 0x1) << 7;
1046 v = USBx_INEP(epnum)->DIEPINT & msk;
1047 return v;
1048 }
1049
1050 /**
1051 * @brief USB_ClearInterrupts: clear a USB interrupt
1052 * @param USBx : Selected device
1053 * @param interrupt : interrupt flag
1054 * @retval None
1055 */
1056 void USB_ClearInterrupts (USB_OTG_GlobalTypeDef *USBx, uint32_t interrupt)
1057 {
1058 USBx->GINTSTS |= interrupt;
1059 }
1060
1061 /**
1062 * @brief Returns USB core mode
1063 * @param USBx : Selected device
1064 * @retval return core mode : Host or Device
1065 * This parameter can be one of these values:
1066 * 0 : Host
1067 * 1 : Device
1068 */
1069 uint32_t USB_GetMode(USB_OTG_GlobalTypeDef *USBx)
1070 {
1071 return ((USBx->GINTSTS ) & 0x1);
1072 }
1073
1074
1075 /**
1076 * @brief Activate EP0 for Setup transactions
1077 * @param USBx : Selected device
1078 * @retval HAL status
1079 */
1080 HAL_StatusTypeDef USB_ActivateSetup (USB_OTG_GlobalTypeDef *USBx)
1081 {
1082 /* Set the MPS of the IN EP based on the enumeration speed */
1083 USBx_INEP(0)->DIEPCTL &= ~USB_OTG_DIEPCTL_MPSIZ;
1084
1085 if((USBx_DEVICE->DSTS & USB_OTG_DSTS_ENUMSPD) == DSTS_ENUMSPD_LS_PHY_6MHZ)
1086 {
1087 USBx_INEP(0)->DIEPCTL |= 3;
1088 }
1089 USBx_DEVICE->DCTL |= USB_OTG_DCTL_CGINAK;
1090
1091 return HAL_OK;
1092 }
1093
1094
1095 /**
1096 * @brief Prepare the EP0 to start the first control setup
1097 * @param USBx : Selected device
1098 * @param dma: USB dma enabled or disabled
1099 * This parameter can be one of these values:
1100 * 0 : DMA feature not used
1101 * 1 : DMA feature used
1102 * @param psetup : pointer to setup packet
1103 * @retval HAL status
1104 */
1105 HAL_StatusTypeDef USB_EP0_OutStart(USB_OTG_GlobalTypeDef *USBx, uint8_t dma, uint8_t *psetup)
1106 {
1107 USBx_OUTEP(0)->DOEPTSIZ = 0;
1108 USBx_OUTEP(0)->DOEPTSIZ |= (USB_OTG_DOEPTSIZ_PKTCNT & (1 << 19)) ;
1109 USBx_OUTEP(0)->DOEPTSIZ |= (3 * 8);
1110 USBx_OUTEP(0)->DOEPTSIZ |= USB_OTG_DOEPTSIZ_STUPCNT;
1111
1112 if (dma == 1)
1113 {
1114 USBx_OUTEP(0)->DOEPDMA = (uint32_t)psetup;
1115 /* EP enable */
1116 USBx_OUTEP(0)->DOEPCTL = 0x80008000;
1117 }
1118
1119 return HAL_OK;
1120 }
1121
1122
1123 /**
1124 * @brief Reset the USB Core (needed after USB clock settings change)
1125 * @param USBx : Selected device
1126 * @retval HAL status
1127 */
1128 static HAL_StatusTypeDef USB_CoreReset(USB_OTG_GlobalTypeDef *USBx)
1129 {
1130 uint32_t count = 0;
1131
1132 /* Wait for AHB master IDLE state. */
1133 do
1134 {
1135 if (++count > 200000)
1136 {
1137 return HAL_TIMEOUT;
1138 }
1139 }
1140 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_AHBIDL) == 0);
1141
1142 /* Core Soft Reset */
1143 count = 0;
1144 USBx->GRSTCTL |= USB_OTG_GRSTCTL_CSRST;
1145
1146 do
1147 {
1148 if (++count > 200000)
1149 {
1150 return HAL_TIMEOUT;
1151 }
1152 }
1153 while ((USBx->GRSTCTL & USB_OTG_GRSTCTL_CSRST) == USB_OTG_GRSTCTL_CSRST);
1154
1155 return HAL_OK;
1156 }
1157
1158 #ifdef USB_HS_PHYC
1159 /**
1160 * @brief Enables control of a High Speed USB PHY’s
1161 * Init the low level hardware : GPIO, CLOCK, NVIC...
1162 * @param USBx : Selected device
1163 * @retval HAL status
1164 */
1165 static HAL_StatusTypeDef USB_HS_PHYCInit(USB_OTG_GlobalTypeDef *USBx)
1166 {
1167 uint32_t count = 0;
1168
1169 /* Enable LDO */
1170 USB_HS_PHYC->USB_HS_PHYC_LDO |= USB_HS_PHYC_LDO_ENABLE;
1171
1172 /* wait for LDO Ready */
1173 while((USB_HS_PHYC->USB_HS_PHYC_LDO & USB_HS_PHYC_LDO_STATUS) == RESET)
1174 {
1175 if (++count > 200000)
1176 {
1177 return HAL_TIMEOUT;
1178 }
1179 }
1180
1181 /* Controls PHY frequency operation selection */
1182 if (HSE_VALUE == 12000000) /* HSE = 12MHz */
1183 {
1184 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x0 << 1);
1185 }
1186 else if (HSE_VALUE == 12500000) /* HSE = 12.5MHz */
1187 {
1188 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x2 << 1);
1189 }
1190 else if (HSE_VALUE == 16000000) /* HSE = 16MHz */
1191 {
1192 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x3 << 1);
1193 }
1194
1195 else if (HSE_VALUE == 24000000) /* HSE = 24MHz */
1196 {
1197 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x4 << 1);
1198 }
1199 else if (HSE_VALUE == 25000000) /* HSE = 25MHz */
1200 {
1201 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x5 << 1);
1202 }
1203 else if (HSE_VALUE == 32000000) /* HSE = 32MHz */
1204 {
1205 USB_HS_PHYC->USB_HS_PHYC_PLL = (uint32_t)(0x7 << 1);
1206 }
1207
1208 /* Control the tuning interface of the High Speed PHY */
1209 USB_HS_PHYC->USB_HS_PHYC_TUNE |= USB_HS_PHYC_TUNE_VALUE;
1210
1211 /* Enable PLL internal PHY */
1212 USB_HS_PHYC->USB_HS_PHYC_PLL |= USB_HS_PHYC_PLL_PLLEN;
1213
1214 /* 2ms Delay required to get internal phy clock stable */
1215 HAL_Delay(2);
1216
1217 return HAL_OK;
1218 }
1219
1220 #endif /* USB_HS_PHYC */
1221 /**
1222 * @brief USB_HostInit : Initializes the USB OTG controller registers
1223 * for Host mode
1224 * @param USBx : Selected device
1225 * @param cfg : pointer to a USB_OTG_CfgTypeDef structure that contains
1226 * the configuration information for the specified USBx peripheral.
1227 * @retval HAL status
1228 */
1229 HAL_StatusTypeDef USB_HostInit (USB_OTG_GlobalTypeDef *USBx, USB_OTG_CfgTypeDef cfg)
1230 {
1231 uint32_t i;
1232
1233 /* Restart the Phy Clock */
1234 USBx_PCGCCTL = 0;
1235
1236 /*Activate VBUS Sensing B */
1237 USBx->GCCFG |= USB_OTG_GCCFG_VBDEN;
1238
1239 /* Disable the FS/LS support mode only */
1240 if((cfg.speed == USB_OTG_SPEED_FULL)&&
1241 (USBx != USB_OTG_FS))
1242 {
1243 USBx_HOST->HCFG |= USB_OTG_HCFG_FSLSS;
1244 }
1245 else
1246 {
1247 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSS);
1248 }
1249
1250 /* Make sure the FIFOs are flushed. */
1251 USB_FlushTxFifo(USBx, 0x10 ); /* all Tx FIFOs */
1252 USB_FlushRxFifo(USBx);
1253
1254 /* Clear all pending HC Interrupts */
1255 for (i = 0; i < cfg.Host_channels; i++)
1256 {
1257 USBx_HC(i)->HCINT = 0xFFFFFFFF;
1258 USBx_HC(i)->HCINTMSK = 0;
1259 }
1260
1261 /* Enable VBUS driving */
1262 USB_DriveVbus(USBx, 1);
1263
1264 HAL_Delay(200);
1265
1266 /* Disable all interrupts. */
1267 USBx->GINTMSK = 0;
1268
1269 /* Clear any pending interrupts */
1270 USBx->GINTSTS = 0xFFFFFFFF;
1271
1272 if(USBx == USB_OTG_FS)
1273 {
1274 /* set Rx FIFO size */
1275 USBx->GRXFSIZ = (uint32_t )0x80;
1276 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x60 << 16)& USB_OTG_NPTXFD) | 0x80);
1277 USBx->HPTXFSIZ = (uint32_t )(((0x40 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0xE0);
1278 }
1279 else
1280 {
1281 /* set Rx FIFO size */
1282 USBx->GRXFSIZ = (uint32_t )0x200;
1283 USBx->DIEPTXF0_HNPTXFSIZ = (uint32_t )(((0x100 << 16)& USB_OTG_NPTXFD) | 0x200);
1284 USBx->HPTXFSIZ = (uint32_t )(((0xE0 << 16)& USB_OTG_HPTXFSIZ_PTXFD) | 0x300);
1285 }
1286
1287 /* Enable the common interrupts */
1288 if (cfg.dma_enable == DISABLE)
1289 {
1290 USBx->GINTMSK |= USB_OTG_GINTMSK_RXFLVLM;
1291 }
1292
1293 /* Enable interrupts matching to the Host mode ONLY */
1294 USBx->GINTMSK |= (USB_OTG_GINTMSK_PRTIM | USB_OTG_GINTMSK_HCIM |\
1295 USB_OTG_GINTMSK_SOFM |USB_OTG_GINTSTS_DISCINT|\
1296 USB_OTG_GINTMSK_PXFRM_IISOOXFRM | USB_OTG_GINTMSK_WUIM);
1297
1298 return HAL_OK;
1299 }
1300
1301 /**
1302 * @brief USB_InitFSLSPClkSel : Initializes the FSLSPClkSel field of the
1303 * HCFG register on the PHY type and set the right frame interval
1304 * @param USBx : Selected device
1305 * @param freq : clock frequency
1306 * This parameter can be one of these values:
1307 * HCFG_48_MHZ : Full Speed 48 MHz Clock
1308 * HCFG_6_MHZ : Low Speed 6 MHz Clock
1309 * @retval HAL status
1310 */
1311 HAL_StatusTypeDef USB_InitFSLSPClkSel(USB_OTG_GlobalTypeDef *USBx , uint8_t freq)
1312 {
1313 USBx_HOST->HCFG &= ~(USB_OTG_HCFG_FSLSPCS);
1314 USBx_HOST->HCFG |= (freq & USB_OTG_HCFG_FSLSPCS);
1315
1316 if (freq == HCFG_48_MHZ)
1317 {
1318 USBx_HOST->HFIR = (uint32_t)48000;
1319 }
1320 else if (freq == HCFG_6_MHZ)
1321 {
1322 USBx_HOST->HFIR = (uint32_t)6000;
1323 }
1324 return HAL_OK;
1325 }
1326
1327 /**
1328 * @brief USB_OTG_ResetPort : Reset Host Port
1329 * @param USBx : Selected device
1330 * @retval HAL status
1331 * @note : (1)The application must wait at least 10 ms
1332 * before clearing the reset bit.
1333 */
1334 HAL_StatusTypeDef USB_ResetPort(USB_OTG_GlobalTypeDef *USBx)
1335 {
1336 __IO uint32_t hprt0;
1337
1338 hprt0 = USBx_HPRT0;
1339
1340 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1341 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1342
1343 USBx_HPRT0 = (USB_OTG_HPRT_PRST | hprt0);
1344 HAL_Delay (100); /* See Note #1 */
1345 USBx_HPRT0 = ((~USB_OTG_HPRT_PRST) & hprt0);
1346 HAL_Delay (10);
1347
1348 return HAL_OK;
1349 }
1350
1351 /**
1352 * @brief USB_DriveVbus : activate or de-activate vbus
1353 * @param state : VBUS state
1354 * This parameter can be one of these values:
1355 * 0 : VBUS Active
1356 * 1 : VBUS Inactive
1357 * @retval HAL status
1358 */
1359 HAL_StatusTypeDef USB_DriveVbus (USB_OTG_GlobalTypeDef *USBx, uint8_t state)
1360 {
1361 __IO uint32_t hprt0;
1362
1363 hprt0 = USBx_HPRT0;
1364
1365 hprt0 &= ~(USB_OTG_HPRT_PENA | USB_OTG_HPRT_PCDET |
1366 USB_OTG_HPRT_PENCHNG | USB_OTG_HPRT_POCCHNG);
1367
1368 if (((hprt0 & USB_OTG_HPRT_PPWR) == 0 ) && (state == 1 ))
1369 {
1370 USBx_HPRT0 = (USB_OTG_HPRT_PPWR | hprt0);
1371 }
1372 if (((hprt0 & USB_OTG_HPRT_PPWR) == USB_OTG_HPRT_PPWR) && (state == 0 ))
1373 {
1374 USBx_HPRT0 = ((~USB_OTG_HPRT_PPWR) & hprt0);
1375 }
1376 return HAL_OK;
1377 }
1378
1379 /**
1380 * @brief Return Host Core speed
1381 * @param USBx : Selected device
1382 * @retval speed : Host speed
1383 * This parameter can be one of these values:
1384 * @arg USB_OTG_SPEED_HIGH: High speed mode
1385 * @arg USB_OTG_SPEED_FULL: Full speed mode
1386 * @arg USB_OTG_SPEED_LOW: Low speed mode
1387 */
1388 uint32_t USB_GetHostSpeed (USB_OTG_GlobalTypeDef *USBx)
1389 {
1390 __IO uint32_t hprt0;
1391
1392 hprt0 = USBx_HPRT0;
1393 return ((hprt0 & USB_OTG_HPRT_PSPD) >> 17);
1394 }
1395
1396 /**
1397 * @brief Return Host Current Frame number
1398 * @param USBx : Selected device
1399 * @retval current frame number
1400 */
1401 uint32_t USB_GetCurrentFrame (USB_OTG_GlobalTypeDef *USBx)
1402 {
1403 return (USBx_HOST->HFNUM & USB_OTG_HFNUM_FRNUM);
1404 }
1405
1406 /**
1407 * @brief Initialize a host channel
1408 * @param USBx : Selected device
1409 * @param ch_num : Channel number
1410 * This parameter can be a value from 1 to 15
1411 * @param epnum : Endpoint number
1412 * This parameter can be a value from 1 to 15
1413 * @param dev_address : Current device address
1414 * This parameter can be a value from 0 to 255
1415 * @param speed : Current device speed
1416 * This parameter can be one of these values:
1417 * @arg USB_OTG_SPEED_HIGH: High speed mode
1418 * @arg USB_OTG_SPEED_FULL: Full speed mode
1419 * @arg USB_OTG_SPEED_LOW: Low speed mode
1420 * @param ep_type : Endpoint Type
1421 * This parameter can be one of these values:
1422 * @arg EP_TYPE_CTRL: Control type
1423 * @arg EP_TYPE_ISOC: Isochronous type
1424 * @arg EP_TYPE_BULK: Bulk type
1425 * @arg EP_TYPE_INTR: Interrupt type
1426 * @param mps : Max Packet Size
1427 * This parameter can be a value from 0 to32K
1428 * @retval HAL state
1429 */
1430 HAL_StatusTypeDef USB_HC_Init(USB_OTG_GlobalTypeDef *USBx,
1431 uint8_t ch_num,
1432 uint8_t epnum,
1433 uint8_t dev_address,
1434 uint8_t speed,
1435 uint8_t ep_type,
1436 uint16_t mps)
1437 {
1438
1439 /* Clear old interrupt conditions for this host channel. */
1440 USBx_HC(ch_num)->HCINT = 0xFFFFFFFF;
1441
1442 /* Enable channel interrupts required for this transfer. */
1443 switch (ep_type)
1444 {
1445 case EP_TYPE_CTRL:
1446 case EP_TYPE_BULK:
1447
1448 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
1449 USB_OTG_HCINTMSK_STALLM |\
1450 USB_OTG_HCINTMSK_TXERRM |\
1451 USB_OTG_HCINTMSK_DTERRM |\
1452 USB_OTG_HCINTMSK_AHBERR |\
1453 USB_OTG_HCINTMSK_NAKM ;
1454
1455 if (epnum & 0x80)
1456 {
1457 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1458 }
1459 else
1460 {
1461 if(USBx != USB_OTG_FS)
1462 {
1463 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1464 }
1465 }
1466 break;
1467
1468 case EP_TYPE_INTR:
1469
1470 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
1471 USB_OTG_HCINTMSK_STALLM |\
1472 USB_OTG_HCINTMSK_TXERRM |\
1473 USB_OTG_HCINTMSK_DTERRM |\
1474 USB_OTG_HCINTMSK_NAKM |\
1475 USB_OTG_HCINTMSK_AHBERR |\
1476 USB_OTG_HCINTMSK_FRMORM ;
1477
1478 if (epnum & 0x80)
1479 {
1480 USBx_HC(ch_num)->HCINTMSK |= USB_OTG_HCINTMSK_BBERRM;
1481 }
1482
1483 break;
1484 case EP_TYPE_ISOC:
1485
1486 USBx_HC(ch_num)->HCINTMSK = USB_OTG_HCINTMSK_XFRCM |\
1487 USB_OTG_HCINTMSK_ACKM |\
1488 USB_OTG_HCINTMSK_AHBERR |\
1489 USB_OTG_HCINTMSK_FRMORM ;
1490
1491 if (epnum & 0x80)
1492 {
1493 USBx_HC(ch_num)->HCINTMSK |= (USB_OTG_HCINTMSK_TXERRM | USB_OTG_HCINTMSK_BBERRM);
1494 }
1495 break;
1496 }
1497
1498 /* Enable the top level host channel interrupt. */
1499 USBx_HOST->HAINTMSK |= (1 << ch_num);
1500
1501 /* Make sure host channel interrupts are enabled. */
1502 USBx->GINTMSK |= USB_OTG_GINTMSK_HCIM;
1503
1504 /* Program the HCCHAR register */
1505 USBx_HC(ch_num)->HCCHAR = (((dev_address << 22) & USB_OTG_HCCHAR_DAD) |\
1506 (((epnum & 0x7F)<< 11) & USB_OTG_HCCHAR_EPNUM)|\
1507 ((((epnum & 0x80) == 0x80)<< 15) & USB_OTG_HCCHAR_EPDIR)|\
1508 (((speed == HPRT0_PRTSPD_LOW_SPEED)<< 17) & USB_OTG_HCCHAR_LSDEV)|\
1509 ((ep_type << 18) & USB_OTG_HCCHAR_EPTYP)|\
1510 (mps & USB_OTG_HCCHAR_MPSIZ));
1511
1512 if (ep_type == EP_TYPE_INTR)
1513 {
1514 USBx_HC(ch_num)->HCCHAR |= USB_OTG_HCCHAR_ODDFRM ;
1515 }
1516
1517 return HAL_OK;
1518 }
1519
1520 /**
1521 * @brief Start a transfer over a host channel
1522 * @param USBx : Selected device
1523 * @param hc : pointer to host channel structure
1524 * @param dma: USB dma enabled or disabled
1525 * This parameter can be one of these values:
1526 * 0 : DMA feature not used
1527 * 1 : DMA feature used
1528 * @retval HAL state
1529 */
1530 HAL_StatusTypeDef USB_HC_StartXfer(USB_OTG_GlobalTypeDef *USBx, USB_OTG_HCTypeDef *hc, uint8_t dma)
1531 {
1532 static __IO uint32_t tmpreg = 0;
1533 uint8_t is_oddframe = 0;
1534 uint16_t len_words = 0;
1535 uint16_t num_packets = 0;
1536 uint16_t max_hc_pkt_count = 256;
1537
1538 if((USBx != USB_OTG_FS) && (hc->speed == USB_OTG_SPEED_HIGH))
1539 {
1540 if((dma == 0) && (hc->do_ping == 1))
1541 {
1542 USB_DoPing(USBx, hc->ch_num);
1543 return HAL_OK;
1544 }
1545 else if(dma == 1)
1546 {
1547 USBx_HC(hc->ch_num)->HCINTMSK &= ~(USB_OTG_HCINTMSK_NYET | USB_OTG_HCINTMSK_ACKM);
1548 hc->do_ping = 0;
1549 }
1550 }
1551
1552 /* Compute the expected number of packets associated to the transfer */
1553 if (hc->xfer_len > 0)
1554 {
1555 num_packets = (hc->xfer_len + hc->max_packet - 1) / hc->max_packet;
1556
1557 if (num_packets > max_hc_pkt_count)
1558 {
1559 num_packets = max_hc_pkt_count;
1560 hc->xfer_len = num_packets * hc->max_packet;
1561 }
1562 }
1563 else
1564 {
1565 num_packets = 1;
1566 }
1567 if (hc->ep_is_in)
1568 {
1569 hc->xfer_len = num_packets * hc->max_packet;
1570 }
1571
1572 /* Initialize the HCTSIZn register */
1573 USBx_HC(hc->ch_num)->HCTSIZ = (((hc->xfer_len) & USB_OTG_HCTSIZ_XFRSIZ)) |\
1574 ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
1575 (((hc->data_pid) << 29) & USB_OTG_HCTSIZ_DPID);
1576
1577 if (dma)
1578 {
1579 /* xfer_buff MUST be 32-bits aligned */
1580 USBx_HC(hc->ch_num)->HCDMA = (uint32_t)hc->xfer_buff;
1581 }
1582
1583 is_oddframe = (USBx_HOST->HFNUM & 0x01) ? 0 : 1;
1584 USBx_HC(hc->ch_num)->HCCHAR &= ~USB_OTG_HCCHAR_ODDFRM;
1585 USBx_HC(hc->ch_num)->HCCHAR |= (is_oddframe << 29);
1586
1587 /* Set host channel enable */
1588 tmpreg = USBx_HC(hc->ch_num)->HCCHAR;
1589 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1590 tmpreg |= USB_OTG_HCCHAR_CHENA;
1591 USBx_HC(hc->ch_num)->HCCHAR = tmpreg;
1592
1593 if (dma == 0) /* Slave mode */
1594 {
1595 if((hc->ep_is_in == 0) && (hc->xfer_len > 0))
1596 {
1597 switch(hc->ep_type)
1598 {
1599 /* Non periodic transfer */
1600 case EP_TYPE_CTRL:
1601 case EP_TYPE_BULK:
1602
1603 len_words = (hc->xfer_len + 3) / 4;
1604
1605 /* check if there is enough space in FIFO space */
1606 if(len_words > (USBx->HNPTXSTS & 0xFFFF))
1607 {
1608 /* need to process data in nptxfempty interrupt */
1609 USBx->GINTMSK |= USB_OTG_GINTMSK_NPTXFEM;
1610 }
1611 break;
1612 /* Periodic transfer */
1613 case EP_TYPE_INTR:
1614 case EP_TYPE_ISOC:
1615 len_words = (hc->xfer_len + 3) / 4;
1616 /* check if there is enough space in FIFO space */
1617 if(len_words > (USBx_HOST->HPTXSTS & 0xFFFF)) /* split the transfer */
1618 {
1619 /* need to process data in ptxfempty interrupt */
1620 USBx->GINTMSK |= USB_OTG_GINTMSK_PTXFEM;
1621 }
1622 break;
1623
1624 default:
1625 break;
1626 }
1627
1628 /* Write packet into the Tx FIFO. */
1629 USB_WritePacket(USBx, hc->xfer_buff, hc->ch_num, hc->xfer_len, 0);
1630 }
1631 }
1632
1633 return HAL_OK;
1634 }
1635
1636 /**
1637 * @brief Read all host channel interrupts status
1638 * @param USBx : Selected device
1639 * @retval HAL state
1640 */
1641 uint32_t USB_HC_ReadInterrupt (USB_OTG_GlobalTypeDef *USBx)
1642 {
1643 return ((USBx_HOST->HAINT) & 0xFFFF);
1644 }
1645
1646 /**
1647 * @brief Halt a host channel
1648 * @param USBx : Selected device
1649 * @param hc_num : Host Channel number
1650 * This parameter can be a value from 1 to 15
1651 * @retval HAL state
1652 */
1653 HAL_StatusTypeDef USB_HC_Halt(USB_OTG_GlobalTypeDef *USBx , uint8_t hc_num)
1654 {
1655 uint32_t count = 0;
1656
1657 /* Check for space in the request queue to issue the halt. */
1658 if (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_CTRL) ||
1659 (((((USBx_HC(hc_num)->HCCHAR) & USB_OTG_HCCHAR_EPTYP) >> 18) == HCCHAR_BULK)))
1660 {
1661 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1662
1663 if ((USBx->HNPTXSTS & 0xFFFF) == 0)
1664 {
1665 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1666 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1667 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1668 do
1669 {
1670 if (++count > 1000)
1671 {
1672 break;
1673 }
1674 }
1675 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1676 }
1677 else
1678 {
1679 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1680 }
1681 }
1682 else
1683 {
1684 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHDIS;
1685
1686 if ((USBx_HOST->HPTXSTS & 0xFFFF) == 0)
1687 {
1688 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_CHENA;
1689 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1690 USBx_HC(hc_num)->HCCHAR &= ~USB_OTG_HCCHAR_EPDIR;
1691 do
1692 {
1693 if (++count > 1000)
1694 {
1695 break;
1696 }
1697 }
1698 while ((USBx_HC(hc_num)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1699 }
1700 else
1701 {
1702 USBx_HC(hc_num)->HCCHAR |= USB_OTG_HCCHAR_CHENA;
1703 }
1704 }
1705
1706 return HAL_OK;
1707 }
1708
1709 /**
1710 * @brief Initiate Do Ping protocol
1711 * @param USBx : Selected device
1712 * @param hc_num : Host Channel number
1713 * This parameter can be a value from 1 to 15
1714 * @retval HAL state
1715 */
1716 HAL_StatusTypeDef USB_DoPing(USB_OTG_GlobalTypeDef *USBx , uint8_t ch_num)
1717 {
1718 uint8_t num_packets = 1;
1719 uint32_t tmpreg = 0;
1720
1721 USBx_HC(ch_num)->HCTSIZ = ((num_packets << 19) & USB_OTG_HCTSIZ_PKTCNT) |\
1722 USB_OTG_HCTSIZ_DOPING;
1723
1724 /* Set host channel enable */
1725 tmpreg = USBx_HC(ch_num)->HCCHAR;
1726 tmpreg &= ~USB_OTG_HCCHAR_CHDIS;
1727 tmpreg |= USB_OTG_HCCHAR_CHENA;
1728 USBx_HC(ch_num)->HCCHAR = tmpreg;
1729
1730 return HAL_OK;
1731 }
1732
1733 /**
1734 * @brief Stop Host Core
1735 * @param USBx : Selected device
1736 * @retval HAL state
1737 */
1738 HAL_StatusTypeDef USB_StopHost(USB_OTG_GlobalTypeDef *USBx)
1739 {
1740 uint8_t i;
1741 uint32_t count = 0;
1742 uint32_t value;
1743
1744 USB_DisableGlobalInt(USBx);
1745
1746 /* Flush FIFO */
1747 USB_FlushTxFifo(USBx, 0x10);
1748 USB_FlushRxFifo(USBx);
1749
1750 /* Flush out any leftover queued requests. */
1751 for (i = 0; i <= 15; i++)
1752 {
1753
1754 value = USBx_HC(i)->HCCHAR ;
1755 value |= USB_OTG_HCCHAR_CHDIS;
1756 value &= ~USB_OTG_HCCHAR_CHENA;
1757 value &= ~USB_OTG_HCCHAR_EPDIR;
1758 USBx_HC(i)->HCCHAR = value;
1759 }
1760
1761 /* Halt all channels to put them into a known state. */
1762 for (i = 0; i <= 15; i++)
1763 {
1764 value = USBx_HC(i)->HCCHAR ;
1765
1766 value |= USB_OTG_HCCHAR_CHDIS;
1767 value |= USB_OTG_HCCHAR_CHENA;
1768 value &= ~USB_OTG_HCCHAR_EPDIR;
1769
1770 USBx_HC(i)->HCCHAR = value;
1771 do
1772 {
1773 if (++count > 1000)
1774 {
1775 break;
1776 }
1777 }
1778 while ((USBx_HC(i)->HCCHAR & USB_OTG_HCCHAR_CHENA) == USB_OTG_HCCHAR_CHENA);
1779 }
1780
1781 /* Clear any pending Host interrupts */
1782 USBx_HOST->HAINT = 0xFFFFFFFF;
1783 USBx->GINTSTS = 0xFFFFFFFF;
1784 USB_EnableGlobalInt(USBx);
1785 return HAL_OK;
1786 }
1787 /**
1788 * @}
1789 */
1790
1791 #endif /* defined (HAL_PCD_MODULE_ENABLED) || defined (HAL_HCD_MODULE_ENABLED) */
1792
1793 /**
1794 * @}
1795 */
1796
1797 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software