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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / CMSIS / Device / ST / STM32H7xx / Include / stm32h742xx.h
blob309aebbe23406044262bcb91cd3c30c527733970
1 /**
2 ******************************************************************************
3 * @file stm32h742xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H742xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32h742xx
31 * @{
32 */
33
34 #ifndef STM32H742xx_H
35 #define STM32H742xx_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45 /**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49 typedef enum
50 {
51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
126 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
127 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
128 USART6_IRQn = 71, /*!< USART6 global interrupt */
129 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
130 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
131 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
132 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
133 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
134 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
135 DCMI_IRQn = 78, /*!< DCMI global interrupt */
136 RNG_IRQn = 80, /*!< RNG global interrupt */
137 FPU_IRQn = 81, /*!< FPU global interrupt */
138 UART7_IRQn = 82, /*!< UART7 global interrupt */
139 UART8_IRQn = 83, /*!< UART8 global interrupt */
140 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
141 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
142 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
143 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
144 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
145 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
146 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
147 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
148 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
149 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
150 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
151 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
152 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
153 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
154 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
155 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
156 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
157 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
158 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
159 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
160 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
161 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
162 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
163 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
164 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
165 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
166 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
167 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
168 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
169 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
170 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
171 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
172 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
173 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
174 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
175 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
176 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
177 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
178 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
179 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
180 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
181 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
182 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
183 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
184 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
185 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
186 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
187 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
188 COMP_IRQn = 137 , /*!< COMP global Interrupt */
189 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
190 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
191 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
192 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
193 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
194 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
195 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
196 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
197 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
198 } IRQn_Type;
199
200 /**
201 * @}
202 */
203
204 /** @addtogroup Configuration_section_for_CMSIS
205 * @{
206 */
207
208
209
210
211 /**
212 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
213 */
214 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
215 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
216 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
217 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
218 #define __FPU_PRESENT 1 /*!< FPU present */
219 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
220 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
221 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
222
223 /**
224 * @}
225 */
226
227
228
229
230 #include "system_stm32h7xx.h"
231 #include <stdint.h>
232
233 /** @addtogroup Peripheral_registers_structures
234 * @{
235 */
236
237 /**
238 * @brief Analog to Digital Converter
239 */
240
241 typedef struct
242 {
243 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
244 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
245 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
246 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
247 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
248 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
249 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
250 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
251 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
252 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
253 uint32_t RESERVED1; /*!< Reserved, 0x028 */
254 uint32_t RESERVED2; /*!< Reserved, 0x02C */
255 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
256 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
257 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
258 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
259 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
260 uint32_t RESERVED3; /*!< Reserved, 0x044 */
261 uint32_t RESERVED4; /*!< Reserved, 0x048 */
262 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
263 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
264 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
265 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
266 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
267 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
268 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
269 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
270 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
271 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
272 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
273 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
274 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
275 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
276 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
277 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
278 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
279 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
280 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
281 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
282 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
283 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
284 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
285 } ADC_TypeDef;
286
287
288 typedef struct
289 {
290 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
291 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
292 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
293 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
294 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
295
296 } ADC_Common_TypeDef;
297
298
299 /**
300 * @brief VREFBUF
301 */
302
303 typedef struct
304 {
305 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
306 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
307 } VREFBUF_TypeDef;
308
309
310 /**
311 * @brief FD Controller Area Network
312 */
313
314 typedef struct
315 {
316 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
317 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
318 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
319 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
320 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
321 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
322 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
323 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
324 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
325 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
326 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
327 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
328 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
329 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
330 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
331 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
332 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
333 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
334 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
335 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
336 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
337 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
338 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
339 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
340 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
341 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
342 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
343 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
344 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
345 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
346 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
347 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
348 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
349 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
350 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
351 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
352 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
353 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
354 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
355 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
356 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
357 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
358 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
359 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
360 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
361 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
362 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
363 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
364 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
365 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
366 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
367 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
368 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
369 } FDCAN_GlobalTypeDef;
370
371 /**
372 * @brief TTFD Controller Area Network
373 */
374
375 typedef struct
376 {
377 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
378 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
379 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
380 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
381 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
382 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
383 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
384 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
385 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
386 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
387 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
388 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
389 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
390 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
391 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
392 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
393 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
394 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
395 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
396 } TTCAN_TypeDef;
397
398 /**
399 * @brief FD Controller Area Network
400 */
401
402 typedef struct
403 {
404 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
405 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
406 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
407 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
408 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
409 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
410 } FDCAN_ClockCalibrationUnit_TypeDef;
411
412
413 /**
414 * @brief Consumer Electronics Control
415 */
416
417 typedef struct
418 {
419 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
420 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
421 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
422 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
423 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
424 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
425 }CEC_TypeDef;
426
427 /**
428 * @brief CRC calculation unit
429 */
430
431 typedef struct
432 {
433 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
434 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
435 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
436 uint32_t RESERVED2; /*!< Reserved, 0x0C */
437 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
438 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
439 } CRC_TypeDef;
440
441
442 /**
443 * @brief Clock Recovery System
444 */
445 typedef struct
446 {
447 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
448 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
449 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
450 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
451 } CRS_TypeDef;
452
453
454 /**
455 * @brief Digital to Analog Converter
456 */
457
458 typedef struct
459 {
460 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
461 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
462 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
463 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
464 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
465 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
466 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
467 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
468 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
469 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
470 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
471 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
472 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
473 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
474 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
475 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
476 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
477 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
478 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
479 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
480 } DAC_TypeDef;
481
482 /**
483 * @brief DFSDM module registers
484 */
485 typedef struct
486 {
487 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
488 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
489 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
490 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
491 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
492 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
493 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
494 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
495 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
496 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
497 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
498 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
499 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
500 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
501 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
502 } DFSDM_Filter_TypeDef;
503
504 /**
505 * @brief DFSDM channel configuration registers
506 */
507 typedef struct
508 {
509 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
510 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
511 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
512 short circuit detector register, Address offset: 0x08 */
513 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
514 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
515 } DFSDM_Channel_TypeDef;
516
517 /**
518 * @brief Debug MCU
519 */
520 typedef struct
521 {
522 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
523 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
524 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
525 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
526 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
527 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
528 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
529 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
530 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
531 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
532 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
533 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
534 }DBGMCU_TypeDef;
535 /**
536 * @brief DCMI
537 */
538
539 typedef struct
540 {
541 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
542 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
543 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
544 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
545 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
546 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
547 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
548 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
549 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
550 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
551 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
552 } DCMI_TypeDef;
553
554 /**
555 * @brief DMA Controller
556 */
557
558 typedef struct
559 {
560 __IO uint32_t CR; /*!< DMA stream x configuration register */
561 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
562 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
563 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
564 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
565 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
566 } DMA_Stream_TypeDef;
567
568 typedef struct
569 {
570 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
571 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
572 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
573 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
574 } DMA_TypeDef;
575
576 typedef struct
577 {
578 __IO uint32_t CCR; /*!< DMA channel x configuration register */
579 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
580 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
581 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
582 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
583 } BDMA_Channel_TypeDef;
584
585 typedef struct
586 {
587 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
588 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
589 } BDMA_TypeDef;
590
591 typedef struct
592 {
593 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
594 }DMAMUX_Channel_TypeDef;
595
596 typedef struct
597 {
598 __IO uint32_t CSR; /*!< DMA Channel Status Register */
599 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
600 }DMAMUX_ChannelStatus_TypeDef;
601
602 typedef struct
603 {
604 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
605 }DMAMUX_RequestGen_TypeDef;
606
607 typedef struct
608 {
609 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
610 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
611 }DMAMUX_RequestGenStatus_TypeDef;
612
613 /**
614 * @brief MDMA Controller
615 */
616 typedef struct
617 {
618 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
619 }MDMA_TypeDef;
620
621 typedef struct
622 {
623 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
624 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
625 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
626 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
627 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
628 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
629 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
630 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
631 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
632 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
633 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
634 uint32_t RESERVED0; /*!< Reserved, 0x68 */
635 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
636 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
637 }MDMA_Channel_TypeDef;
638
639 /**
640 * @brief DMA2D Controller
641 */
642
643 typedef struct
644 {
645 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
646 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
647 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
648 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
649 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
650 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
651 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
652 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
653 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
654 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
655 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
656 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
657 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
658 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
659 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
660 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
661 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
662 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
663 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
664 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
665 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
666 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
667 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
668 } DMA2D_TypeDef;
669
670
671 /**
672 * @brief Ethernet MAC
673 */
674 typedef struct
675 {
676 __IO uint32_t MACCR;
677 __IO uint32_t MACECR;
678 __IO uint32_t MACPFR;
679 __IO uint32_t MACWTR;
680 __IO uint32_t MACHT0R;
681 __IO uint32_t MACHT1R;
682 uint32_t RESERVED1[14];
683 __IO uint32_t MACVTR;
684 uint32_t RESERVED2;
685 __IO uint32_t MACVHTR;
686 uint32_t RESERVED3;
687 __IO uint32_t MACVIR;
688 __IO uint32_t MACIVIR;
689 uint32_t RESERVED4[2];
690 __IO uint32_t MACTFCR;
691 uint32_t RESERVED5[7];
692 __IO uint32_t MACRFCR;
693 uint32_t RESERVED6[7];
694 __IO uint32_t MACISR;
695 __IO uint32_t MACIER;
696 __IO uint32_t MACRXTXSR;
697 uint32_t RESERVED7;
698 __IO uint32_t MACPCSR;
699 __IO uint32_t MACRWKPFR;
700 uint32_t RESERVED8[2];
701 __IO uint32_t MACLCSR;
702 __IO uint32_t MACLTCR;
703 __IO uint32_t MACLETR;
704 __IO uint32_t MAC1USTCR;
705 uint32_t RESERVED9[12];
706 __IO uint32_t MACVR;
707 __IO uint32_t MACDR;
708 uint32_t RESERVED10;
709 __IO uint32_t MACHWF0R;
710 __IO uint32_t MACHWF1R;
711 __IO uint32_t MACHWF2R;
712 uint32_t RESERVED11[54];
713 __IO uint32_t MACMDIOAR;
714 __IO uint32_t MACMDIODR;
715 uint32_t RESERVED12[2];
716 __IO uint32_t MACARPAR;
717 uint32_t RESERVED13[59];
718 __IO uint32_t MACA0HR;
719 __IO uint32_t MACA0LR;
720 __IO uint32_t MACA1HR;
721 __IO uint32_t MACA1LR;
722 __IO uint32_t MACA2HR;
723 __IO uint32_t MACA2LR;
724 __IO uint32_t MACA3HR;
725 __IO uint32_t MACA3LR;
726 uint32_t RESERVED14[248];
727 __IO uint32_t MMCCR;
728 __IO uint32_t MMCRIR;
729 __IO uint32_t MMCTIR;
730 __IO uint32_t MMCRIMR;
731 __IO uint32_t MMCTIMR;
732 uint32_t RESERVED15[14];
733 __IO uint32_t MMCTSCGPR;
734 __IO uint32_t MMCTMCGPR;
735 uint32_t RESERVED16[5];
736 __IO uint32_t MMCTPCGR;
737 uint32_t RESERVED17[10];
738 __IO uint32_t MMCRCRCEPR;
739 __IO uint32_t MMCRAEPR;
740 uint32_t RESERVED18[10];
741 __IO uint32_t MMCRUPGR;
742 uint32_t RESERVED19[9];
743 __IO uint32_t MMCTLPIMSTR;
744 __IO uint32_t MMCTLPITCR;
745 __IO uint32_t MMCRLPIMSTR;
746 __IO uint32_t MMCRLPITCR;
747 uint32_t RESERVED20[65];
748 __IO uint32_t MACL3L4C0R;
749 __IO uint32_t MACL4A0R;
750 uint32_t RESERVED21[2];
751 __IO uint32_t MACL3A0R0R;
752 __IO uint32_t MACL3A1R0R;
753 __IO uint32_t MACL3A2R0R;
754 __IO uint32_t MACL3A3R0R;
755 uint32_t RESERVED22[4];
756 __IO uint32_t MACL3L4C1R;
757 __IO uint32_t MACL4A1R;
758 uint32_t RESERVED23[2];
759 __IO uint32_t MACL3A0R1R;
760 __IO uint32_t MACL3A1R1R;
761 __IO uint32_t MACL3A2R1R;
762 __IO uint32_t MACL3A3R1R;
763 uint32_t RESERVED24[108];
764 __IO uint32_t MACTSCR;
765 __IO uint32_t MACSSIR;
766 __IO uint32_t MACSTSR;
767 __IO uint32_t MACSTNR;
768 __IO uint32_t MACSTSUR;
769 __IO uint32_t MACSTNUR;
770 __IO uint32_t MACTSAR;
771 uint32_t RESERVED25;
772 __IO uint32_t MACTSSR;
773 uint32_t RESERVED26[3];
774 __IO uint32_t MACTTSSNR;
775 __IO uint32_t MACTTSSSR;
776 uint32_t RESERVED27[2];
777 __IO uint32_t MACACR;
778 uint32_t RESERVED28;
779 __IO uint32_t MACATSNR;
780 __IO uint32_t MACATSSR;
781 __IO uint32_t MACTSIACR;
782 __IO uint32_t MACTSEACR;
783 __IO uint32_t MACTSICNR;
784 __IO uint32_t MACTSECNR;
785 uint32_t RESERVED29[4];
786 __IO uint32_t MACPPSCR;
787 uint32_t RESERVED30[3];
788 __IO uint32_t MACPPSTTSR;
789 __IO uint32_t MACPPSTTNR;
790 __IO uint32_t MACPPSIR;
791 __IO uint32_t MACPPSWR;
792 uint32_t RESERVED31[12];
793 __IO uint32_t MACPOCR;
794 __IO uint32_t MACSPI0R;
795 __IO uint32_t MACSPI1R;
796 __IO uint32_t MACSPI2R;
797 __IO uint32_t MACLMIR;
798 uint32_t RESERVED32[11];
799 __IO uint32_t MTLOMR;
800 uint32_t RESERVED33[7];
801 __IO uint32_t MTLISR;
802 uint32_t RESERVED34[55];
803 __IO uint32_t MTLTQOMR;
804 __IO uint32_t MTLTQUR;
805 __IO uint32_t MTLTQDR;
806 uint32_t RESERVED35[8];
807 __IO uint32_t MTLQICSR;
808 __IO uint32_t MTLRQOMR;
809 __IO uint32_t MTLRQMPOCR;
810 __IO uint32_t MTLRQDR;
811 uint32_t RESERVED36[177];
812 __IO uint32_t DMAMR;
813 __IO uint32_t DMASBMR;
814 __IO uint32_t DMAISR;
815 __IO uint32_t DMADSR;
816 uint32_t RESERVED37[60];
817 __IO uint32_t DMACCR;
818 __IO uint32_t DMACTCR;
819 __IO uint32_t DMACRCR;
820 uint32_t RESERVED38[2];
821 __IO uint32_t DMACTDLAR;
822 uint32_t RESERVED39;
823 __IO uint32_t DMACRDLAR;
824 __IO uint32_t DMACTDTPR;
825 uint32_t RESERVED40;
826 __IO uint32_t DMACRDTPR;
827 __IO uint32_t DMACTDRLR;
828 __IO uint32_t DMACRDRLR;
829 __IO uint32_t DMACIER;
830 __IO uint32_t DMACRIWTR;
831 __IO uint32_t DMACSFCSR;
832 uint32_t RESERVED41;
833 __IO uint32_t DMACCATDR;
834 uint32_t RESERVED42;
835 __IO uint32_t DMACCARDR;
836 uint32_t RESERVED43;
837 __IO uint32_t DMACCATBR;
838 uint32_t RESERVED44;
839 __IO uint32_t DMACCARBR;
840 __IO uint32_t DMACSR;
841 uint32_t RESERVED45[2];
842 __IO uint32_t DMACMFCR;
843 }ETH_TypeDef;
844 /**
845 * @brief External Interrupt/Event Controller
846 */
847
848 typedef struct
849 {
850 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
851 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
852 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
853 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
854 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
855 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
856 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
857 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
858 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
859 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
860 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
861 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
862 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
863 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
864 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
865 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
866 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
867 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
868 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
869 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
870 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
871 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
872 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
873 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
874 uint32_t RESERVED4; /*!< Reserved, 0x8C */
875 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
876 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
877 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
878 uint32_t RESERVED5; /*!< Reserved, 0x9C */
879 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
880 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
881 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
882 }EXTI_TypeDef;
883
884 typedef struct
885 {
886 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
887 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
888 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
889 uint32_t RESERVED1; /*!< Reserved, 0x0C */
890 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
891 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
892 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
893 uint32_t RESERVED2; /*!< Reserved, 0x1C */
894 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
895 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
896 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
897 }EXTI_Core_TypeDef;
898
899
900 /**
901 * @brief FLASH Registers
902 */
903
904 typedef struct
905 {
906 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
907 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
908 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
909 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
910 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
911 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
912 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
913 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
914 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
915 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
916 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
917 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
918 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
919 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
920 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
921 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
922 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
923 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
924 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
925 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
926 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
927 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
928 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
929 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
930 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
931 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
932 uint32_t RESERVED2; /*!< Reserved, 0x108 */
933 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
934 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
935 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
936 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
937 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
938 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
939 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
940 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
941 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
942 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
943 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
944 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
945 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
946 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
947 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
948 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
949 } FLASH_TypeDef;
950
951 /**
952 * @brief Flexible Memory Controller
953 */
954
955 typedef struct
956 {
957 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
958 } FMC_Bank1_TypeDef;
959
960 /**
961 * @brief Flexible Memory Controller Bank1E
962 */
963
964 typedef struct
965 {
966 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
967 } FMC_Bank1E_TypeDef;
968
969 /**
970 * @brief Flexible Memory Controller Bank2
971 */
972
973 typedef struct
974 {
975 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
976 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
977 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
978 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
979 uint32_t RESERVED0; /*!< Reserved, 0x70 */
980 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
981 } FMC_Bank2_TypeDef;
982
983 /**
984 * @brief Flexible Memory Controller Bank3
985 */
986
987 typedef struct
988 {
989 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
990 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
991 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
992 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
993 uint32_t RESERVED; /*!< Reserved, 0x90 */
994 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
995 } FMC_Bank3_TypeDef;
996
997 /**
998 * @brief Flexible Memory Controller Bank5 and 6
999 */
1000
1001
1002 typedef struct
1003 {
1004 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1005 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1006 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1007 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1008 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1009 } FMC_Bank5_6_TypeDef;
1010
1011 /**
1012 * @brief General Purpose I/O
1013 */
1014
1015 typedef struct
1016 {
1017 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1018 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1019 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1020 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1021 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1022 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1023 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1024 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1025 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1026 } GPIO_TypeDef;
1027
1028 /**
1029 * @brief Operational Amplifier (OPAMP)
1030 */
1031
1032 typedef struct
1033 {
1034 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1035 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1036 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1037 } OPAMP_TypeDef;
1038
1039 /**
1040 * @brief System configuration controller
1041 */
1042
1043 typedef struct
1044 {
1045 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1046 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1047 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1048 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1049 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1050 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1051 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1052 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1053 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1054 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1055 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1056 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1057 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1058 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1059 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1060 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1061 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1062 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1063 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1064 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1065 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1066 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1067 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1068 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1069 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1070 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1071 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1072 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1073 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1074 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1075
1076 } SYSCFG_TypeDef;
1077
1078 /**
1079 * @brief Inter-integrated Circuit Interface
1080 */
1081
1082 typedef struct
1083 {
1084 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1085 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1086 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1087 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1088 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1089 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1090 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1091 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1092 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1093 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1094 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1095 } I2C_TypeDef;
1096
1097 /**
1098 * @brief Independent WATCHDOG
1099 */
1100
1101 typedef struct
1102 {
1103 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1104 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1105 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1106 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1107 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1108 } IWDG_TypeDef;
1109
1110
1111
1112 /**
1113 * @brief Power Control
1114 */
1115
1116 typedef struct
1117 {
1118 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1119 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1120 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1121 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1122 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1123 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1124 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1125 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1126 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1127 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1128 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1129 } PWR_TypeDef;
1130
1131 /**
1132 * @brief Reset and Clock Control
1133 */
1134
1135 typedef struct
1136 {
1137 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1138 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1139 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1140 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1141 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1142 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1143 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1144 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1145 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1146 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1147 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1148 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1149 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1150 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1151 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1152 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1153 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1154 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1155 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1156 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1157 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1158 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1159 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1160 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1161 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1162 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1163 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1164 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1165 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1166 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1167 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1168 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1169 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1170 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1171 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1172 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1173 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1174 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1175 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1176 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1177 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1178 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1179 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1180 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1181 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1182 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1183 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1184 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1185 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1186 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1187 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1188 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1189 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1190 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1191 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1192 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1193 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1194 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1195 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1196 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1197 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1198 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1199 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1200 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1201 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1202
1203 } RCC_TypeDef;
1204
1205
1206 /**
1207 * @brief Real-Time Clock
1208 */
1209 typedef struct
1210 {
1211 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1212 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1213 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1214 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1215 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1216 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1217 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1218 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1219 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1220 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1221 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1222 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1223 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1224 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1225 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1226 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1227 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1228 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1229 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1230 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1231 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1232 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1233 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1234 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1235 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1236 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1237 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1238 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1239 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1240 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1241 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1242 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1243 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1244 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1245 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1246 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1247 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1248 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1249 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1250 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1251 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1252 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1253 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1254 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1255 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1256 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1257 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1258 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1259 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1260 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1261 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1262 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1263 } RTC_TypeDef;
1264
1265 /**
1266 * @brief Serial Audio Interface
1267 */
1268
1269 typedef struct
1270 {
1271 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1272 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1273 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1274 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1275 } SAI_TypeDef;
1276
1277 typedef struct
1278 {
1279 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1280 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1281 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1282 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1283 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1284 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1285 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1286 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1287 } SAI_Block_TypeDef;
1288
1289 /**
1290 * @brief SPDIF-RX Interface
1291 */
1292
1293 typedef struct
1294 {
1295 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1296 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1297 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1298 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1299 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1300 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1301 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1302 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1303 } SPDIFRX_TypeDef;
1304
1305
1306 /**
1307 * @brief Secure digital input/output Interface
1308 */
1309
1310 typedef struct
1311 {
1312 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1313 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1314 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1315 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1316 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1317 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1318 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1319 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1320 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1321 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1322 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1323 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1324 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1325 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1326 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1327 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1328 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1329 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1330 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1331 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1332 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1333 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1334 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1335 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1336 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1337 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1338 } SDMMC_TypeDef;
1339
1340
1341 /**
1342 * @brief Delay Block DLYB
1343 */
1344
1345 typedef struct
1346 {
1347 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1348 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1349 } DLYB_TypeDef;
1350
1351 /**
1352 * @brief HW Semaphore HSEM
1353 */
1354
1355 typedef struct
1356 {
1357 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1358 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1359 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1360 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1361 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1362 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1363 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1364 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1365 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1366
1367 } HSEM_TypeDef;
1368
1369 typedef struct
1370 {
1371 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1372 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1373 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1374 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1375 } HSEM_Common_TypeDef;
1376
1377 /**
1378 * @brief Serial Peripheral Interface
1379 */
1380
1381 typedef struct
1382 {
1383 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1384 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1385 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1386 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1387 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1388 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1389 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1390 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1391 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1392 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1393 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1394 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1395 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1396 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1397 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1398 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1399 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1400
1401 } SPI_TypeDef;
1402 /**
1403 * @brief QUAD Serial Peripheral Interface
1404 */
1405
1406 typedef struct
1407 {
1408 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1409 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1410 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1411 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1412 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1413 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1414 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1415 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1416 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1417 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1418 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1419 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1420 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1421 } QUADSPI_TypeDef;
1422
1423 /**
1424 * @brief TIM
1425 */
1426
1427 typedef struct
1428 {
1429 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1430 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1431 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1432 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1433 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1434 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1435 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1436 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1437 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1438 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1439 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1440 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1441 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1442 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1443 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1444 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1445 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1446 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1447 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1448 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1449 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1450 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1451 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1452 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1453 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1454 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1455 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1456 } TIM_TypeDef;
1457
1458 /**
1459 * @brief LPTIMIMER
1460 */
1461 typedef struct
1462 {
1463 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1464 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1465 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1466 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1467 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1468 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1469 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1470 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1471 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1472 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1473 } LPTIM_TypeDef;
1474
1475 /**
1476 * @brief Comparator
1477 */
1478 typedef struct
1479 {
1480 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1481 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1482 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1483 } COMPOPT_TypeDef;
1484
1485 typedef struct
1486 {
1487 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1488 } COMP_TypeDef;
1489
1490 typedef struct
1491 {
1492 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1493 } COMP_Common_TypeDef;
1494 /**
1495 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1496 */
1497
1498 typedef struct
1499 {
1500 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1501 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1502 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1503 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1504 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1505 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1506 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1507 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1508 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1509 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1510 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1511 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1512 } USART_TypeDef;
1513
1514 /**
1515 * @brief Single Wire Protocol Master Interface SPWMI
1516 */
1517 typedef struct
1518 {
1519 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1520 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1521 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1522 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1523 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1524 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1525 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1526 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1527 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1528 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1529 } SWPMI_TypeDef;
1530
1531 /**
1532 * @brief Window WATCHDOG
1533 */
1534
1535 typedef struct
1536 {
1537 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1538 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1539 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1540 } WWDG_TypeDef;
1541
1542
1543 /**
1544 * @brief RAM_ECC_Specific_Registers
1545 */
1546 typedef struct
1547 {
1548 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1549 __IO uint32_t SR; /*!< RAMECC monitor status register */
1550 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1551 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1552 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1553 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1554 } RAMECC_MonitorTypeDef;
1555
1556 typedef struct
1557 {
1558 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1559 } RAMECC_TypeDef;
1560 /**
1561 * @}
1562 */
1563
1564
1565
1566 /**
1567 * @brief High resolution Timer (HRTIM)
1568 */
1569 /* HRTIM master registers definition */
1570 typedef struct
1571 {
1572 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1573 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1574 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1575 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1576 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1577 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1578 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1579 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1580 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1581 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1582 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1583 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1584 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1585 }HRTIM_Master_TypeDef;
1586
1587 /* HRTIM Timer A to E registers definition */
1588 typedef struct
1589 {
1590 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1591 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1592 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1593 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1594 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1595 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1596 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1597 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1598 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1599 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1600 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1601 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1602 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1603 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1604 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1605 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1606 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1607 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1608 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1609 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1610 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1611 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1612 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1613 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1614 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1615 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1616 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1617 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1618 }HRTIM_Timerx_TypeDef;
1619
1620 /* HRTIM common register definition */
1621 typedef struct
1622 {
1623 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1624 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1625 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1626 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1627 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1628 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1629 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1630 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1631 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1632 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1633 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1634 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1635 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1636 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1637 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1638 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1639 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1640 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1641 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1642 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1643 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1644 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1645 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1646 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1647 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1648 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1649 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1650 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1651 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1652 }HRTIM_Common_TypeDef;
1653
1654 /* HRTIM register definition */
1655 typedef struct {
1656 HRTIM_Master_TypeDef sMasterRegs;
1657 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1658 uint32_t RESERVED0[32];
1659 HRTIM_Common_TypeDef sCommonRegs;
1660 }HRTIM_TypeDef;
1661 /**
1662 * @brief RNG
1663 */
1664
1665 typedef struct
1666 {
1667 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1668 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1669 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1670 } RNG_TypeDef;
1671
1672 /**
1673 * @brief MDIOS
1674 */
1675
1676 typedef struct
1677 {
1678 __IO uint32_t CR;
1679 __IO uint32_t WRFR;
1680 __IO uint32_t CWRFR;
1681 __IO uint32_t RDFR;
1682 __IO uint32_t CRDFR;
1683 __IO uint32_t SR;
1684 __IO uint32_t CLRFR;
1685 uint32_t RESERVED[57];
1686 __IO uint32_t DINR0;
1687 __IO uint32_t DINR1;
1688 __IO uint32_t DINR2;
1689 __IO uint32_t DINR3;
1690 __IO uint32_t DINR4;
1691 __IO uint32_t DINR5;
1692 __IO uint32_t DINR6;
1693 __IO uint32_t DINR7;
1694 __IO uint32_t DINR8;
1695 __IO uint32_t DINR9;
1696 __IO uint32_t DINR10;
1697 __IO uint32_t DINR11;
1698 __IO uint32_t DINR12;
1699 __IO uint32_t DINR13;
1700 __IO uint32_t DINR14;
1701 __IO uint32_t DINR15;
1702 __IO uint32_t DINR16;
1703 __IO uint32_t DINR17;
1704 __IO uint32_t DINR18;
1705 __IO uint32_t DINR19;
1706 __IO uint32_t DINR20;
1707 __IO uint32_t DINR21;
1708 __IO uint32_t DINR22;
1709 __IO uint32_t DINR23;
1710 __IO uint32_t DINR24;
1711 __IO uint32_t DINR25;
1712 __IO uint32_t DINR26;
1713 __IO uint32_t DINR27;
1714 __IO uint32_t DINR28;
1715 __IO uint32_t DINR29;
1716 __IO uint32_t DINR30;
1717 __IO uint32_t DINR31;
1718 __IO uint32_t DOUTR0;
1719 __IO uint32_t DOUTR1;
1720 __IO uint32_t DOUTR2;
1721 __IO uint32_t DOUTR3;
1722 __IO uint32_t DOUTR4;
1723 __IO uint32_t DOUTR5;
1724 __IO uint32_t DOUTR6;
1725 __IO uint32_t DOUTR7;
1726 __IO uint32_t DOUTR8;
1727 __IO uint32_t DOUTR9;
1728 __IO uint32_t DOUTR10;
1729 __IO uint32_t DOUTR11;
1730 __IO uint32_t DOUTR12;
1731 __IO uint32_t DOUTR13;
1732 __IO uint32_t DOUTR14;
1733 __IO uint32_t DOUTR15;
1734 __IO uint32_t DOUTR16;
1735 __IO uint32_t DOUTR17;
1736 __IO uint32_t DOUTR18;
1737 __IO uint32_t DOUTR19;
1738 __IO uint32_t DOUTR20;
1739 __IO uint32_t DOUTR21;
1740 __IO uint32_t DOUTR22;
1741 __IO uint32_t DOUTR23;
1742 __IO uint32_t DOUTR24;
1743 __IO uint32_t DOUTR25;
1744 __IO uint32_t DOUTR26;
1745 __IO uint32_t DOUTR27;
1746 __IO uint32_t DOUTR28;
1747 __IO uint32_t DOUTR29;
1748 __IO uint32_t DOUTR30;
1749 __IO uint32_t DOUTR31;
1750 } MDIOS_TypeDef;
1751
1752
1753 /**
1754 * @brief USB_OTG_Core_Registers
1755 */
1756 typedef struct
1757 {
1758 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1759 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1760 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1761 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1762 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1763 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1764 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1765 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1766 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1767 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1768 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1769 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1770 uint32_t Reserved30[2]; /*!< Reserved 030h */
1771 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1772 __IO uint32_t CID; /*!< User ID Register 03Ch */
1773 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1774 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1775 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1776 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1777 uint32_t Reserved6; /*!< Reserved 050h */
1778 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1779 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1780 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1781 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1782 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1783 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1784 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1785 } USB_OTG_GlobalTypeDef;
1786
1787
1788 /**
1789 * @brief USB_OTG_device_Registers
1790 */
1791 typedef struct
1792 {
1793 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1794 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1795 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1796 uint32_t Reserved0C; /*!< Reserved 80Ch */
1797 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1798 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1799 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1800 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1801 uint32_t Reserved20; /*!< Reserved 820h */
1802 uint32_t Reserved9; /*!< Reserved 824h */
1803 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1804 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1805 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1806 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1807 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1808 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1809 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1810 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1811 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1812 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1813 } USB_OTG_DeviceTypeDef;
1814
1815
1816 /**
1817 * @brief USB_OTG_IN_Endpoint-Specific_Register
1818 */
1819 typedef struct
1820 {
1821 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1822 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1823 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1824 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1825 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1826 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1827 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1828 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1829 } USB_OTG_INEndpointTypeDef;
1830
1831
1832 /**
1833 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1834 */
1835 typedef struct
1836 {
1837 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1838 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1839 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1840 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1841 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1842 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1843 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1844 } USB_OTG_OUTEndpointTypeDef;
1845
1846
1847 /**
1848 * @brief USB_OTG_Host_Mode_Register_Structures
1849 */
1850 typedef struct
1851 {
1852 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1853 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1854 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1855 uint32_t Reserved40C; /*!< Reserved 40Ch */
1856 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1857 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1858 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1859 } USB_OTG_HostTypeDef;
1860
1861 /**
1862 * @brief USB_OTG_Host_Channel_Specific_Registers
1863 */
1864 typedef struct
1865 {
1866 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1867 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1868 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1869 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1870 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1871 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1872 uint32_t Reserved[2]; /*!< Reserved */
1873 } USB_OTG_HostChannelTypeDef;
1874 /**
1875 * @}
1876 */
1877
1878
1879 /** @addtogroup Peripheral_memory_map
1880 * @{
1881 */
1882 #define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1883 #define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
1884 #define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
1885 #define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1886 #define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
1887 #define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 384KB) system data RAM accessible over over AXI */
1888
1889 #define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 48KB) system data RAM accessible over over AXI */
1890 #define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 48KB) system data RAM accessible over over AXI->AHB Bridge */
1891
1892 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1893 #define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
1894
1895 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
1896 #define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
1897
1898 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
1899 #define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
1900 #define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
1901
1902 /* Legacy define */
1903 #define FLASH_BASE FLASH_BANK1_BASE
1904
1905 /*!< Device electronic signature memory map */
1906 #define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
1907 #define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
1908
1909
1910 /*!< Peripheral memory map */
1911 #define D2_APB1PERIPH_BASE PERIPH_BASE
1912 #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1913 #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1914 #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
1915
1916 #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
1917 #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
1918
1919 #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
1920 #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
1921
1922 /*!< Legacy Peripheral memory map */
1923 #define APB1PERIPH_BASE PERIPH_BASE
1924 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1925 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1926 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
1927
1928
1929 /*!< D1_AHB1PERIPH peripherals */
1930
1931 #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
1932 #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
1933 #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
1934 #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
1935 #define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
1936 #define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
1937 #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
1938 #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
1939 #define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
1940
1941 /*!< D2_AHB1PERIPH peripherals */
1942
1943 #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
1944 #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
1945 #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
1946 #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
1947 #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
1948 #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
1949 #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
1950 #define ETH_MAC_BASE (ETH_BASE)
1951
1952 /*!< USB registers base address */
1953 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
1954 #define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
1955 #define USB_OTG_GLOBAL_BASE (0x000UL)
1956 #define USB_OTG_DEVICE_BASE (0x800UL)
1957 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
1958 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
1959 #define USB_OTG_EP_REG_SIZE (0x20UL)
1960 #define USB_OTG_HOST_BASE (0x400UL)
1961 #define USB_OTG_HOST_PORT_BASE (0x440UL)
1962 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
1963 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
1964 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
1965 #define USB_OTG_FIFO_BASE (0x1000UL)
1966 #define USB_OTG_FIFO_SIZE (0x1000UL)
1967
1968 /*!< D2_AHB2PERIPH peripherals */
1969
1970 #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
1971 #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
1972 #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
1973 #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
1974 #define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
1975
1976 /*!< D3_AHB1PERIPH peripherals */
1977 #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
1978 #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
1979 #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
1980 #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
1981 #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
1982 #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
1983 #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
1984 #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
1985 #define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
1986 #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
1987 #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
1988 #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
1989 #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
1990 #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
1991 #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
1992 #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
1993 #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
1994 #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
1995 #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
1996 #define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
1997
1998 /*!< D1_APB1PERIPH peripherals */
1999 #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2000
2001 /*!< D2_APB1PERIPH peripherals */
2002 #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2003 #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2004 #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2005 #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2006 #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2007 #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2008 #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2009 #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2010 #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2011 #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2012
2013
2014 #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2015 #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2016 #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2017 #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2018 #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2019 #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2020 #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2021 #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2022 #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2023 #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2024 #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2025 #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2026 #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2027 #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2028 #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2029 #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2030 #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2031 #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2032 #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2033 #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2034 #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2035 #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2036 #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2037 #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2038
2039 /*!< D2_APB2PERIPH peripherals */
2040
2041 #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2042 #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2043 #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2044 #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2045 #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2046 #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2047 #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2048 #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2049 #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2050 #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2051 #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2052 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2053 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2054 #define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2055 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2056 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2057 #define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2058 #define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2059 #define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2060 #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2061 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2062 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2063 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2064 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2065 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2066 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2067 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2068 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2069 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2070 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2071 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2072 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2073 #define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2074 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2075 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2076 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2077 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2078 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2079 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2080
2081
2082 /*!< D3_APB1PERIPH peripherals */
2083 #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2084 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2085 #define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2086 #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2087 #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2088 #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2089 #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2090 #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2091 #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2092 #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2093 #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2094 #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2095 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
2096 #define COMP2_BASE (COMP12_BASE + 0x10UL)
2097 #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2098 #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2099 #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2100
2101
2102 #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2103 #define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2104 #define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2105
2106
2107
2108
2109 #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2110 #define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2111 #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2112 #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2113 #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2114 #define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2115 #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2116 #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2117
2118 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2119 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2120 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2121 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2122 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2123 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2124 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2125 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2126
2127 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2128 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2129 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2130 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2131 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2132 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2133 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2134 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2135
2136 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2137 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2138
2139 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2140 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2141 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2142 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2143 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2144 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2145 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2146 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2147
2148 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2149 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2150 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2151 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2152 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2153 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2154 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2155 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2156
2157 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2158 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2159 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2160 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2161 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2162 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2163 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2164 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2165 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2166 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2167 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2168 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2169 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2170 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2171 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2172 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2173
2174 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2175 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2176 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2177 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2178 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2179 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2180 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2181 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2182
2183 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2184 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2185
2186 /*!< FMC Banks registers base address */
2187 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2188 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2189 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2190 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2191 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2192
2193 /* Debug MCU registers base address */
2194 #define DBGMCU_BASE (0x5C001000UL)
2195
2196 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2197 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2198 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2199 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2200 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2201 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2202 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2203 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2204 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2205 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2206 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2207 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2208 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2209 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2210 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2211 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2212
2213 #define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2214 #define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2215 #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2216 #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2217 #define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2218
2219 #define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2220 #define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2221 #define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2222 #define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2223 #define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2224
2225 #define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2226 #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2227
2228
2229 /**
2230 * @}
2231 */
2232
2233 /** @addtogroup Peripheral_declaration
2234 * @{
2235 */
2236 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2237 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2238 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2239 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2240 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2241 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2242 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2243 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2244 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2245 #define RTC ((RTC_TypeDef *) RTC_BASE)
2246 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2247
2248
2249 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2250 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2251 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2252 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2253 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2254 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2255 #define USART2 ((USART_TypeDef *) USART2_BASE)
2256 #define USART3 ((USART_TypeDef *) USART3_BASE)
2257 #define USART6 ((USART_TypeDef *) USART6_BASE)
2258 #define UART7 ((USART_TypeDef *) UART7_BASE)
2259 #define UART8 ((USART_TypeDef *) UART8_BASE)
2260 #define CRS ((CRS_TypeDef *) CRS_BASE)
2261 #define UART4 ((USART_TypeDef *) UART4_BASE)
2262 #define UART5 ((USART_TypeDef *) UART5_BASE)
2263 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2264 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2265 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2266 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2267 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2268 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2269 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2270 #define CEC ((CEC_TypeDef *) CEC_BASE)
2271 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2272 #define PWR ((PWR_TypeDef *) PWR_BASE)
2273 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2274 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2275 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2276 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2277 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2278 #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2279 #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2280
2281 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2282 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2283 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2284 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2285 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2286 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2287 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2288 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2289
2290
2291 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2292 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2293 #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2294 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2295 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2296 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2297 #define USART1 ((USART_TypeDef *) USART1_BASE)
2298 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2299 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2300 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2301 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2302 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2303 #define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2304 #define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2305 #define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2306 #define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2307 #define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2308 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2309 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2310 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2311 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2312 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2313 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2314 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2315 #define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2316 #define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2317 #define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2318 #define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2319 #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2320 #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2321
2322 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2323 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2324 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2325 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2326 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2327 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2328 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2329 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2330 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2331 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2332 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2333 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2334 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2335 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2336 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2337 #define RCC ((RCC_TypeDef *) RCC_BASE)
2338 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2339 #define CRC ((CRC_TypeDef *) CRC_BASE)
2340
2341 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2342 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2343 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2344 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2345 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2346 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2347 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2348 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2349 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2350 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2351 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2352
2353 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2354 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2355 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2356 #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2357 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2358
2359 #define RNG ((RNG_TypeDef *) RNG_BASE)
2360 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2361 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2362
2363 #define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2364 #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2365 #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2366 #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2367 #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2368 #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2369 #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2370 #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2371 #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2372
2373 #define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2374 #define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2375 #define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2376 #define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2377 #define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2378 #define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2379
2380 #define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2381 #define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2382 #define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2383 #define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2384 #define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2385 #define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2386
2387 #define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2388 #define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2389 #define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2390
2391 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2392 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2393 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2394 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2395 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2396 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2397 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2398 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2399 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2400
2401
2402 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2403 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2404 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2405 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2406 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2407 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2408 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2409 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2410
2411 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2412 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2413
2414 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2415 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2416 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2417 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2418 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2419 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2420 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2421 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2422 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2423
2424 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2425 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2426 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2427 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2428 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2429 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2430 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2431 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2432 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2433
2434
2435 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2436 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2437 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2438 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2439 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2440 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2441 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2442 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2443 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2444 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2445 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2446 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2447 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2448 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2449 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2450 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2451 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2452
2453 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2454 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2455 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2456 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2457 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2458 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2459 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2460 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2461
2462 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2463 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2464
2465
2466 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2467 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2468 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2469 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2470 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2471
2472
2473 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2474 #define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2475 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2476 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2477
2478 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2479
2480 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2481 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2482
2483
2484 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2485
2486 #define ETH ((ETH_TypeDef *)ETH_BASE)
2487 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2488 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2489 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2490 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2491 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2492 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2493 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2494 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2495 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2496 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2497 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2498 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2499 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2500 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2501 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2502 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2503 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2504
2505
2506 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2507 #define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2508
2509 /* Legacy defines */
2510 #define USB_OTG_HS USB1_OTG_HS
2511 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2512 #define USB_OTG_FS USB2_OTG_FS
2513 #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2514
2515 /**
2516 * @}
2517 */
2518
2519 /** @addtogroup Exported_constants
2520 * @{
2521 */
2522
2523 /** @addtogroup Peripheral_Registers_Bits_Definition
2524 * @{
2525 */
2526
2527 /******************************************************************************/
2528 /* Peripheral Registers_Bits_Definition */
2529 /******************************************************************************/
2530
2531 /******************************************************************************/
2532 /* */
2533 /* Analog to Digital Converter */
2534 /* */
2535 /******************************************************************************/
2536 /******************************* ADC VERSION ********************************/
2537 #define ADC_VER_V5_X
2538 /******************** Bit definition for ADC_ISR register ********************/
2539 #define ADC_ISR_ADRDY_Pos (0U)
2540 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2541 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2542 #define ADC_ISR_EOSMP_Pos (1U)
2543 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2544 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2545 #define ADC_ISR_EOC_Pos (2U)
2546 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2547 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2548 #define ADC_ISR_EOS_Pos (3U)
2549 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2550 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2551 #define ADC_ISR_OVR_Pos (4U)
2552 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2553 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2554 #define ADC_ISR_JEOC_Pos (5U)
2555 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2556 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2557 #define ADC_ISR_JEOS_Pos (6U)
2558 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2559 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2560 #define ADC_ISR_AWD1_Pos (7U)
2561 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2562 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2563 #define ADC_ISR_AWD2_Pos (8U)
2564 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2565 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2566 #define ADC_ISR_AWD3_Pos (9U)
2567 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2568 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2569 #define ADC_ISR_JQOVF_Pos (10U)
2570 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2571 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2572
2573 /******************** Bit definition for ADC_IER register ********************/
2574 #define ADC_IER_ADRDYIE_Pos (0U)
2575 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2576 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2577 #define ADC_IER_EOSMPIE_Pos (1U)
2578 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2579 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2580 #define ADC_IER_EOCIE_Pos (2U)
2581 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2582 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2583 #define ADC_IER_EOSIE_Pos (3U)
2584 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2585 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2586 #define ADC_IER_OVRIE_Pos (4U)
2587 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2588 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2589 #define ADC_IER_JEOCIE_Pos (5U)
2590 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2591 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2592 #define ADC_IER_JEOSIE_Pos (6U)
2593 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2594 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2595 #define ADC_IER_AWD1IE_Pos (7U)
2596 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2597 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2598 #define ADC_IER_AWD2IE_Pos (8U)
2599 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2600 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2601 #define ADC_IER_AWD3IE_Pos (9U)
2602 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2603 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2604 #define ADC_IER_JQOVFIE_Pos (10U)
2605 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2606 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2607
2608 /******************** Bit definition for ADC_CR register ********************/
2609 #define ADC_CR_ADEN_Pos (0U)
2610 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2611 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2612 #define ADC_CR_ADDIS_Pos (1U)
2613 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2614 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2615 #define ADC_CR_ADSTART_Pos (2U)
2616 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2617 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2618 #define ADC_CR_JADSTART_Pos (3U)
2619 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2620 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2621 #define ADC_CR_ADSTP_Pos (4U)
2622 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2623 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2624 #define ADC_CR_JADSTP_Pos (5U)
2625 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2626 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2627 #define ADC_CR_BOOST_Pos (8U)
2628 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2629 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2630 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2631 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2632 #define ADC_CR_ADCALLIN_Pos (16U)
2633 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2634 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2635 #define ADC_CR_LINCALRDYW1_Pos (22U)
2636 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2637 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2638 #define ADC_CR_LINCALRDYW2_Pos (23U)
2639 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2640 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2641 #define ADC_CR_LINCALRDYW3_Pos (24U)
2642 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2643 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2644 #define ADC_CR_LINCALRDYW4_Pos (25U)
2645 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2646 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2647 #define ADC_CR_LINCALRDYW5_Pos (26U)
2648 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2649 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2650 #define ADC_CR_LINCALRDYW6_Pos (27U)
2651 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2652 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2653 #define ADC_CR_ADVREGEN_Pos (28U)
2654 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2655 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2656 #define ADC_CR_DEEPPWD_Pos (29U)
2657 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2658 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2659 #define ADC_CR_ADCALDIF_Pos (30U)
2660 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2661 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2662 #define ADC_CR_ADCAL_Pos (31U)
2663 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2664 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2665
2666 /******************** Bit definition for ADC_CFGR register ********************/
2667 #define ADC_CFGR_DMNGT_Pos (0U)
2668 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2669 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2670 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2671 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2672
2673 #define ADC_CFGR_RES_Pos (2U)
2674 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2675 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2676 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2677 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2678 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2679
2680 #define ADC_CFGR_EXTSEL_Pos (5U)
2681 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2682 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2683 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2684 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2685 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2686 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2687 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2688
2689 #define ADC_CFGR_EXTEN_Pos (10U)
2690 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2691 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2692 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2693 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2694
2695 #define ADC_CFGR_OVRMOD_Pos (12U)
2696 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2697 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2698 #define ADC_CFGR_CONT_Pos (13U)
2699 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2700 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2701 #define ADC_CFGR_AUTDLY_Pos (14U)
2702 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2703 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2704
2705 #define ADC_CFGR_DISCEN_Pos (16U)
2706 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2707 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2708
2709 #define ADC_CFGR_DISCNUM_Pos (17U)
2710 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2711 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2712 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2713 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2714 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2715
2716 #define ADC_CFGR_JDISCEN_Pos (20U)
2717 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2718 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2719 #define ADC_CFGR_JQM_Pos (21U)
2720 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2721 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2722 #define ADC_CFGR_AWD1SGL_Pos (22U)
2723 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2724 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2725 #define ADC_CFGR_AWD1EN_Pos (23U)
2726 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2727 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2728 #define ADC_CFGR_JAWD1EN_Pos (24U)
2729 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2730 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2731 #define ADC_CFGR_JAUTO_Pos (25U)
2732 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2733 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2734
2735 #define ADC_CFGR_AWD1CH_Pos (26U)
2736 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2737 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2738 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2739 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2740 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2741 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2742 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2743
2744 #define ADC_CFGR_JQDIS_Pos (31U)
2745 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2746 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2747
2748 /******************** Bit definition for ADC_CFGR2 register ********************/
2749 #define ADC_CFGR2_ROVSE_Pos (0U)
2750 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2751 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2752 #define ADC_CFGR2_JOVSE_Pos (1U)
2753 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2754 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2755
2756 #define ADC_CFGR2_OVSS_Pos (5U)
2757 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2758 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2759 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2760 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2761 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2762 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2763
2764 #define ADC_CFGR2_TROVS_Pos (9U)
2765 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2766 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2767 #define ADC_CFGR2_ROVSM_Pos (10U)
2768 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2769 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2770
2771 #define ADC_CFGR2_RSHIFT1_Pos (11U)
2772 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2773 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2774 #define ADC_CFGR2_RSHIFT2_Pos (12U)
2775 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2776 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2777 #define ADC_CFGR2_RSHIFT3_Pos (13U)
2778 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2779 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2780 #define ADC_CFGR2_RSHIFT4_Pos (14U)
2781 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2782 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2783
2784 #define ADC_CFGR2_OVSR_Pos (16U)
2785 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2786 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2787 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2788 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2789 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2790 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2791 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2792 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2793 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2794 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2795 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2796 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2797
2798 #define ADC_CFGR2_LSHIFT_Pos (28U)
2799 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2800 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2801 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2802 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2803 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2804 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2805
2806 /******************** Bit definition for ADC_SMPR1 register ********************/
2807 #define ADC_SMPR1_SMP0_Pos (0U)
2808 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2809 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2810 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2811 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2812 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2813
2814 #define ADC_SMPR1_SMP1_Pos (3U)
2815 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2816 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2817 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2818 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2819 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2820
2821 #define ADC_SMPR1_SMP2_Pos (6U)
2822 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2823 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2824 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2825 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2826 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2827
2828 #define ADC_SMPR1_SMP3_Pos (9U)
2829 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2830 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2831 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2832 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2833 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2834
2835 #define ADC_SMPR1_SMP4_Pos (12U)
2836 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2837 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2838 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2839 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2840 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2841
2842 #define ADC_SMPR1_SMP5_Pos (15U)
2843 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2844 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2845 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2846 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2847 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2848
2849 #define ADC_SMPR1_SMP6_Pos (18U)
2850 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2851 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2852 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2853 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2854 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2855
2856 #define ADC_SMPR1_SMP7_Pos (21U)
2857 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2858 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2859 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2860 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2861 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2862
2863 #define ADC_SMPR1_SMP8_Pos (24U)
2864 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2865 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2866 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2867 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2868 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2869
2870 #define ADC_SMPR1_SMP9_Pos (27U)
2871 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2872 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2873 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2874 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2875 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2876
2877 /******************** Bit definition for ADC_SMPR2 register ********************/
2878 #define ADC_SMPR2_SMP10_Pos (0U)
2879 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2880 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2881 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2882 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2883 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2884
2885 #define ADC_SMPR2_SMP11_Pos (3U)
2886 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2887 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2888 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2889 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2890 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2891
2892 #define ADC_SMPR2_SMP12_Pos (6U)
2893 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2894 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2895 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2896 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2897 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2898
2899 #define ADC_SMPR2_SMP13_Pos (9U)
2900 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2901 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2902 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2903 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2904 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2905
2906 #define ADC_SMPR2_SMP14_Pos (12U)
2907 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2908 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
2909 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
2910 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
2911 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
2912
2913 #define ADC_SMPR2_SMP15_Pos (15U)
2914 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
2915 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
2916 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
2917 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
2918 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
2919
2920 #define ADC_SMPR2_SMP16_Pos (18U)
2921 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
2922 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
2923 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
2924 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
2925 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
2926
2927 #define ADC_SMPR2_SMP17_Pos (21U)
2928 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
2929 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
2930 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
2931 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
2932 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
2933
2934 #define ADC_SMPR2_SMP18_Pos (24U)
2935 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
2936 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
2937 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
2938 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
2939 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
2940
2941 #define ADC_SMPR2_SMP19_Pos (27U)
2942 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
2943 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
2944 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
2945 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
2946 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
2947
2948 /******************** Bit definition for ADC_PCSEL register ********************/
2949 #define ADC_PCSEL_PCSEL_Pos (0U)
2950 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
2951 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
2952 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
2953 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
2954 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
2955 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
2956 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
2957 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
2958 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
2959 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
2960 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
2961 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
2962 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
2963 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
2964 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
2965 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
2966 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
2967 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
2968 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
2969 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
2970 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
2971 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
2972
2973 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
2974 #define ADC_LTR_LT_Pos (0U)
2975 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
2976 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
2977
2978 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
2979 #define ADC_HTR_HT_Pos (0U)
2980 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
2981 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
2982
2983
2984 /******************** Bit definition for ADC_SQR1 register ********************/
2985 #define ADC_SQR1_L_Pos (0U)
2986 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
2987 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
2988 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
2989 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
2990 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
2991 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
2992
2993 #define ADC_SQR1_SQ1_Pos (6U)
2994 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
2995 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
2996 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
2997 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
2998 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
2999 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3000 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3001
3002 #define ADC_SQR1_SQ2_Pos (12U)
3003 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3004 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3005 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3006 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3007 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3008 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3009 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3010
3011 #define ADC_SQR1_SQ3_Pos (18U)
3012 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3013 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3014 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3015 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3016 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3017 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3018 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3019
3020 #define ADC_SQR1_SQ4_Pos (24U)
3021 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3022 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3023 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3024 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3025 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3026 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3027 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3028
3029 /******************** Bit definition for ADC_SQR2 register ********************/
3030 #define ADC_SQR2_SQ5_Pos (0U)
3031 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3032 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3033 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3034 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3035 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3036 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3037 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3038
3039 #define ADC_SQR2_SQ6_Pos (6U)
3040 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3041 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3042 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3043 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3044 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3045 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3046 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3047
3048 #define ADC_SQR2_SQ7_Pos (12U)
3049 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3050 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3051 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3052 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3053 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3054 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3055 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3056
3057 #define ADC_SQR2_SQ8_Pos (18U)
3058 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3059 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3060 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3061 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3062 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3063 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3064 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3065
3066 #define ADC_SQR2_SQ9_Pos (24U)
3067 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3068 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3069 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3070 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3071 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3072 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3073 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3074
3075 /******************** Bit definition for ADC_SQR3 register ********************/
3076 #define ADC_SQR3_SQ10_Pos (0U)
3077 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3078 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3079 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3080 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3081 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3082 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3083 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3084
3085 #define ADC_SQR3_SQ11_Pos (6U)
3086 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3087 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3088 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3089 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3090 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3091 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3092 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3093
3094 #define ADC_SQR3_SQ12_Pos (12U)
3095 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3096 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3097 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3098 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3099 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3100 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3101 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3102
3103 #define ADC_SQR3_SQ13_Pos (18U)
3104 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3105 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3106 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3107 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3108 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3109 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3110 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3111
3112 #define ADC_SQR3_SQ14_Pos (24U)
3113 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3114 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3115 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3116 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3117 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3118 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3119 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3120
3121 /******************** Bit definition for ADC_SQR4 register ********************/
3122 #define ADC_SQR4_SQ15_Pos (0U)
3123 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3124 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3125 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3126 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3127 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3128 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3129 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3130
3131 #define ADC_SQR4_SQ16_Pos (6U)
3132 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3133 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3134 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3135 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3136 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3137 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3138 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3139 /******************** Bit definition for ADC_DR register ********************/
3140 #define ADC_DR_RDATA_Pos (0U)
3141 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3142 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3143
3144 /******************** Bit definition for ADC_JSQR register ********************/
3145 #define ADC_JSQR_JL_Pos (0U)
3146 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3147 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3148 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3149 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3150
3151 #define ADC_JSQR_JEXTSEL_Pos (2U)
3152 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3153 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3154 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3155 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3156 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3157 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3158 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3159
3160 #define ADC_JSQR_JEXTEN_Pos (7U)
3161 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3162 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3163 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3164 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3165
3166 #define ADC_JSQR_JSQ1_Pos (9U)
3167 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3168 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3169 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3170 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3171 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3172 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3173 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3174
3175 #define ADC_JSQR_JSQ2_Pos (15U)
3176 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3177 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3178 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3179 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3180 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3181 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3182 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3183
3184 #define ADC_JSQR_JSQ3_Pos (21U)
3185 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3186 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3187 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3188 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3189 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3190 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3191 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3192
3193 #define ADC_JSQR_JSQ4_Pos (27U)
3194 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3195 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3196 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3197 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3198 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3199 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3200 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3201
3202 /******************** Bit definition for ADC_OFR1 register ********************/
3203 #define ADC_OFR1_OFFSET1_Pos (0U)
3204 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3205 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3206 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3207 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3208 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3209 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3210 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3211 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3212 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3213 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3214 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3215 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3216 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3217 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3218 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3219 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3220 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3221 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3222 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3223 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3224 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3225 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3226 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3227 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3228 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3229 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3230 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3231 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3232
3233 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
3234 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3235 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3236 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3237 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3238 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3239 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3240 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3241
3242 #define ADC_OFR1_SSATE_Pos (31U)
3243 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3244 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3245
3246
3247 /******************** Bit definition for ADC_OFR2 register ********************/
3248 #define ADC_OFR2_OFFSET2_Pos (0U)
3249 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3250 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3251 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3252 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3253 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3254 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3255 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3256 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3257 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3258 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3259 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3260 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3261 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3262 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3263 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3264 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3265 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3266 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3267 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3268 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3269 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3270 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3271 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3272 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3273 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3274 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3275 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3276 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3277
3278 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
3279 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3280 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3281 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3282 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3283 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3284 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3285 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3286
3287 #define ADC_OFR2_SSATE_Pos (31U)
3288 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3289 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3290
3291
3292 /******************** Bit definition for ADC_OFR3 register ********************/
3293 #define ADC_OFR3_OFFSET3_Pos (0U)
3294 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3295 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3296 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3297 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3298 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3299 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3300 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3301 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3302 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3303 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3304 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3305 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3306 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3307 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3308 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3309 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3310 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3311 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3312 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3313 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3314 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3315 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3316 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3317 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3318 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3319 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3320 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3321 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3322
3323 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
3324 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3325 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3326 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3327 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3328 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3329 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3330 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3331
3332 #define ADC_OFR3_SSATE_Pos (31U)
3333 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3334 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3335
3336
3337 /******************** Bit definition for ADC_OFR4 register ********************/
3338 #define ADC_OFR4_OFFSET4_Pos (0U)
3339 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3340 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3341 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3342 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3343 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3344 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3345 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3346 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3347 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3348 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3349 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3350 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3351 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3352 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3353 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3354 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3355 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3356 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3357 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3358 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3359 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3360 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3361 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3362 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3363 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3364 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3365 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3366 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3367
3368 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
3369 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3370 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3371 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3372 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3373 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3374 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3375 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3376
3377 #define ADC_OFR4_SSATE_Pos (31U)
3378 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3379 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3380
3381
3382 /******************** Bit definition for ADC_JDR1 register ********************/
3383 #define ADC_JDR1_JDATA_Pos (0U)
3384 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3385 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3386 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3387 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3388 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3389 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3390 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3391 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3392 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3393 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3394 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3395 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3396 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3397 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3398 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3399 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3400 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3401 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3402 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3403 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3404 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3405 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3406 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3407 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3408 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3409 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3410 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3411 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3412 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3413 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3414 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3415 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3416 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3417 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3418
3419 /******************** Bit definition for ADC_JDR2 register ********************/
3420 #define ADC_JDR2_JDATA_Pos (0U)
3421 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3422 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3423 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3424 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3425 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3426 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3427 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3428 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3429 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3430 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3431 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3432 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3433 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3434 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3435 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3436 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3437 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3438 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3439 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3440 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3441 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3442 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3443 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3444 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3445 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3446 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3447 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3448 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3449 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3450 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3451 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3452 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3453 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3454 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3455
3456 /******************** Bit definition for ADC_JDR3 register ********************/
3457 #define ADC_JDR3_JDATA_Pos (0U)
3458 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3459 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3460 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3461 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3462 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3463 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3464 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3465 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3466 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3467 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3468 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3469 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3470 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3471 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3472 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3473 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3474 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3475 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3476 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3477 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3478 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3479 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3480 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3481 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3482 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3483 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3484 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3485 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3486 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3487 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3488 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3489 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3490 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3491 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3492
3493 /******************** Bit definition for ADC_JDR4 register ********************/
3494 #define ADC_JDR4_JDATA_Pos (0U)
3495 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3496 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3497 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3498 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3499 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3500 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3501 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3502 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3503 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3504 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3505 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3506 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3507 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3508 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3509 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3510 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3511 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3512 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3513 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3514 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3515 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3516 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3517 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3518 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3519 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3520 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3521 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3522 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3523 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3524 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3525 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3526 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3527 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3528 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3529
3530 /******************** Bit definition for ADC_AWD2CR register ********************/
3531 #define ADC_AWD2CR_AWD2CH_Pos (0U)
3532 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3533 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3534 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3535 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3536 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3537 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3538 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3539 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3540 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3541 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3542 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3543 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3544 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3545 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3546 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3547 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3548 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3549 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3550 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3551 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3552 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3553 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3554
3555 /******************** Bit definition for ADC_AWD3CR register ********************/
3556 #define ADC_AWD3CR_AWD3CH_Pos (0U)
3557 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3558 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3559 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3560 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3561 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3562 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3563 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3564 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3565 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3566 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3567 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3568 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3569 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3570 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3571 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3572 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3573 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3574 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3575 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3576 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3577 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3578 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3579
3580 /******************** Bit definition for ADC_DIFSEL register ********************/
3581 #define ADC_DIFSEL_DIFSEL_Pos (0U)
3582 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3583 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3584 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3585 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3586 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3587 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3588 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3589 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3590 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3591 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3592 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3593 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3594 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3595 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3596 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3597 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3598 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3599 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3600 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3601 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3602 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3603 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3604
3605 /******************** Bit definition for ADC_CALFACT register ********************/
3606 #define ADC_CALFACT_CALFACT_S_Pos (0U)
3607 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3608 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3609 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3610 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3611 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3612 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3613 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3614 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3615 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3616 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3617 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3618 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3619 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3620 #define ADC_CALFACT_CALFACT_D_Pos (16U)
3621 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3622 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3623 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3624 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3625 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3626 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3627 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3628 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3629 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3630 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3631 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3632 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3633 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3634
3635 /******************** Bit definition for ADC_CALFACT2 register ********************/
3636 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
3637 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3638 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3639 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3640 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3641 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3642 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3643 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3644 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3645 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3646 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3647 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3648 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3649 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3650 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3651 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3652 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3653 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3654 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3655 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3656 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3657 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3658 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3659 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3660 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3661 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3662 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3663 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3664 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3665 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3666 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3667 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3668 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3669
3670 /************************* ADC Common registers *****************************/
3671 /******************** Bit definition for ADC_CSR register ********************/
3672 #define ADC_CSR_ADRDY_MST_Pos (0U)
3673 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3674 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3675 #define ADC_CSR_EOSMP_MST_Pos (1U)
3676 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3677 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3678 #define ADC_CSR_EOC_MST_Pos (2U)
3679 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3680 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3681 #define ADC_CSR_EOS_MST_Pos (3U)
3682 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3683 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3684 #define ADC_CSR_OVR_MST_Pos (4U)
3685 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3686 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3687 #define ADC_CSR_JEOC_MST_Pos (5U)
3688 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3689 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3690 #define ADC_CSR_JEOS_MST_Pos (6U)
3691 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3692 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3693 #define ADC_CSR_AWD1_MST_Pos (7U)
3694 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3695 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3696 #define ADC_CSR_AWD2_MST_Pos (8U)
3697 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3698 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3699 #define ADC_CSR_AWD3_MST_Pos (9U)
3700 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3701 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3702 #define ADC_CSR_JQOVF_MST_Pos (10U)
3703 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3704 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3705 #define ADC_CSR_ADRDY_SLV_Pos (16U)
3706 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3707 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3708 #define ADC_CSR_EOSMP_SLV_Pos (17U)
3709 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3710 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3711 #define ADC_CSR_EOC_SLV_Pos (18U)
3712 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3713 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3714 #define ADC_CSR_EOS_SLV_Pos (19U)
3715 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3716 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3717 #define ADC_CSR_OVR_SLV_Pos (20U)
3718 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3719 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3720 #define ADC_CSR_JEOC_SLV_Pos (21U)
3721 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3722 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3723 #define ADC_CSR_JEOS_SLV_Pos (22U)
3724 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3725 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3726 #define ADC_CSR_AWD1_SLV_Pos (23U)
3727 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3728 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3729 #define ADC_CSR_AWD2_SLV_Pos (24U)
3730 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3731 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3732 #define ADC_CSR_AWD3_SLV_Pos (25U)
3733 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3734 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3735 #define ADC_CSR_JQOVF_SLV_Pos (26U)
3736 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3737 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3738
3739 /******************** Bit definition for ADC_CCR register ********************/
3740 #define ADC_CCR_DUAL_Pos (0U)
3741 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3742 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3743 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3744 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3745 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3746 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3747 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3748
3749 #define ADC_CCR_DELAY_Pos (8U)
3750 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3751 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3752 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3753 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3754 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3755 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3756
3757
3758 #define ADC_CCR_DAMDF_Pos (14U)
3759 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3760 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3761 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3762 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3763
3764 #define ADC_CCR_CKMODE_Pos (16U)
3765 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3766 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3767 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3768 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3769
3770 #define ADC_CCR_PRESC_Pos (18U)
3771 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3772 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3773 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3774 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3775 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3776 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3777
3778 #define ADC_CCR_VREFEN_Pos (22U)
3779 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3780 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3781 #define ADC_CCR_TSEN_Pos (23U)
3782 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3783 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3784 #define ADC_CCR_VBATEN_Pos (24U)
3785 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3786 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3787
3788 /******************** Bit definition for ADC_CDR register *******************/
3789 #define ADC_CDR_RDATA_MST_Pos (0U)
3790 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3791 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3792
3793 #define ADC_CDR_RDATA_SLV_Pos (16U)
3794 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3795 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3796
3797 /******************** Bit definition for ADC_CDR2 register ******************/
3798 #define ADC_CDR2_RDATA_ALT_Pos (0U)
3799 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3800 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3801
3802
3803 /******************************************************************************/
3804 /* */
3805 /* VREFBUF */
3806 /* */
3807 /******************************************************************************/
3808 /******************* Bit definition for VREFBUF_CSR register ****************/
3809 #define VREFBUF_CSR_ENVR_Pos (0U)
3810 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3811 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3812 #define VREFBUF_CSR_HIZ_Pos (1U)
3813 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3814 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3815 #define VREFBUF_CSR_VRR_Pos (3U)
3816 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3817 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3818 #define VREFBUF_CSR_VRS_Pos (4U)
3819 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3820 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3821
3822 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3823 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3824 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3825 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3826 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3827 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3828 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
3829 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3830 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
3831 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
3832
3833 /******************* Bit definition for VREFBUF_CCR register ****************/
3834 #define VREFBUF_CCR_TRIM_Pos (0U)
3835 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
3836 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
3837
3838 /******************************************************************************/
3839 /* */
3840 /* Flexible Datarate Controller Area Network */
3841 /* */
3842 /******************************************************************************/
3843 /*!<FDCAN control and status registers */
3844 /***************** Bit definition for FDCAN_CREL register *******************/
3845 #define FDCAN_CREL_DAY_Pos (0U)
3846 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
3847 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
3848 #define FDCAN_CREL_MON_Pos (8U)
3849 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
3850 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
3851 #define FDCAN_CREL_YEAR_Pos (16U)
3852 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
3853 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
3854 #define FDCAN_CREL_SUBSTEP_Pos (20U)
3855 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
3856 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
3857 #define FDCAN_CREL_STEP_Pos (24U)
3858 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
3859 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
3860 #define FDCAN_CREL_REL_Pos (28U)
3861 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
3862 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
3863
3864 /***************** Bit definition for FDCAN_ENDN register *******************/
3865 #define FDCAN_ENDN_ETV_Pos (0U)
3866 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
3867 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
3868
3869 /***************** Bit definition for FDCAN_DBTP register *******************/
3870 #define FDCAN_DBTP_DSJW_Pos (0U)
3871 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
3872 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
3873 #define FDCAN_DBTP_DTSEG2_Pos (4U)
3874 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
3875 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
3876 #define FDCAN_DBTP_DTSEG1_Pos (8U)
3877 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
3878 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
3879 #define FDCAN_DBTP_DBRP_Pos (16U)
3880 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
3881 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
3882 #define FDCAN_DBTP_TDC_Pos (23U)
3883 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
3884 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
3885
3886 /***************** Bit definition for FDCAN_TEST register *******************/
3887 #define FDCAN_TEST_LBCK_Pos (4U)
3888 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
3889 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
3890 #define FDCAN_TEST_TX_Pos (5U)
3891 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
3892 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
3893 #define FDCAN_TEST_RX_Pos (7U)
3894 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
3895 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
3896
3897 /***************** Bit definition for FDCAN_RWD register ********************/
3898 #define FDCAN_RWD_WDC_Pos (0U)
3899 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
3900 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
3901 #define FDCAN_RWD_WDV_Pos (8U)
3902 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
3903 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
3904
3905 /***************** Bit definition for FDCAN_CCCR register ********************/
3906 #define FDCAN_CCCR_INIT_Pos (0U)
3907 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
3908 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
3909 #define FDCAN_CCCR_CCE_Pos (1U)
3910 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
3911 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
3912 #define FDCAN_CCCR_ASM_Pos (2U)
3913 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
3914 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
3915 #define FDCAN_CCCR_CSA_Pos (3U)
3916 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
3917 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
3918 #define FDCAN_CCCR_CSR_Pos (4U)
3919 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
3920 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
3921 #define FDCAN_CCCR_MON_Pos (5U)
3922 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
3923 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
3924 #define FDCAN_CCCR_DAR_Pos (6U)
3925 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
3926 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
3927 #define FDCAN_CCCR_TEST_Pos (7U)
3928 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
3929 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
3930 #define FDCAN_CCCR_FDOE_Pos (8U)
3931 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
3932 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
3933 #define FDCAN_CCCR_BRSE_Pos (9U)
3934 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
3935 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
3936 #define FDCAN_CCCR_PXHD_Pos (12U)
3937 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
3938 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
3939 #define FDCAN_CCCR_EFBI_Pos (13U)
3940 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
3941 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
3942 #define FDCAN_CCCR_TXP_Pos (14U)
3943 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
3944 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
3945 #define FDCAN_CCCR_NISO_Pos (15U)
3946 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
3947 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
3948
3949 /***************** Bit definition for FDCAN_NBTP register ********************/
3950 #define FDCAN_NBTP_NTSEG2_Pos (0U)
3951 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
3952 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
3953 #define FDCAN_NBTP_NTSEG1_Pos (8U)
3954 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
3955 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
3956 #define FDCAN_NBTP_NBRP_Pos (16U)
3957 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
3958 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
3959 #define FDCAN_NBTP_NSJW_Pos (25U)
3960 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
3961 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
3962
3963 /***************** Bit definition for FDCAN_TSCC register ********************/
3964 #define FDCAN_TSCC_TSS_Pos (0U)
3965 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
3966 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
3967 #define FDCAN_TSCC_TCP_Pos (16U)
3968 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
3969 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
3970
3971 /***************** Bit definition for FDCAN_TSCV register ********************/
3972 #define FDCAN_TSCV_TSC_Pos (0U)
3973 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
3974 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
3975
3976 /***************** Bit definition for FDCAN_TOCC register ********************/
3977 #define FDCAN_TOCC_ETOC_Pos (0U)
3978 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
3979 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
3980 #define FDCAN_TOCC_TOS_Pos (1U)
3981 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
3982 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
3983 #define FDCAN_TOCC_TOP_Pos (16U)
3984 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
3985 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
3986
3987 /***************** Bit definition for FDCAN_TOCV register ********************/
3988 #define FDCAN_TOCV_TOC_Pos (0U)
3989 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
3990 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
3991
3992 /***************** Bit definition for FDCAN_ECR register *********************/
3993 #define FDCAN_ECR_TEC_Pos (0U)
3994 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
3995 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
3996 #define FDCAN_ECR_REC_Pos (8U)
3997 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
3998 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
3999 #define FDCAN_ECR_RP_Pos (15U)
4000 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4001 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4002 #define FDCAN_ECR_CEL_Pos (16U)
4003 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4004 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4005
4006 /***************** Bit definition for FDCAN_PSR register *********************/
4007 #define FDCAN_PSR_LEC_Pos (0U)
4008 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4009 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4010 #define FDCAN_PSR_ACT_Pos (3U)
4011 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4012 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4013 #define FDCAN_PSR_EP_Pos (5U)
4014 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4015 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4016 #define FDCAN_PSR_EW_Pos (6U)
4017 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4018 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4019 #define FDCAN_PSR_BO_Pos (7U)
4020 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4021 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4022 #define FDCAN_PSR_DLEC_Pos (8U)
4023 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4024 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4025 #define FDCAN_PSR_RESI_Pos (11U)
4026 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4027 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4028 #define FDCAN_PSR_RBRS_Pos (12U)
4029 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4030 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4031 #define FDCAN_PSR_REDL_Pos (13U)
4032 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4033 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4034 #define FDCAN_PSR_PXE_Pos (14U)
4035 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4036 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4037 #define FDCAN_PSR_TDCV_Pos (16U)
4038 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4039 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4040
4041 /***************** Bit definition for FDCAN_TDCR register ********************/
4042 #define FDCAN_TDCR_TDCF_Pos (0U)
4043 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4044 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4045 #define FDCAN_TDCR_TDCO_Pos (8U)
4046 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4047 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4048
4049 /***************** Bit definition for FDCAN_IR register **********************/
4050 #define FDCAN_IR_RF0N_Pos (0U)
4051 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4052 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4053 #define FDCAN_IR_RF0W_Pos (1U)
4054 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4055 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4056 #define FDCAN_IR_RF0F_Pos (2U)
4057 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4058 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4059 #define FDCAN_IR_RF0L_Pos (3U)
4060 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4061 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4062 #define FDCAN_IR_RF1N_Pos (4U)
4063 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4064 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4065 #define FDCAN_IR_RF1W_Pos (5U)
4066 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4067 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4068 #define FDCAN_IR_RF1F_Pos (6U)
4069 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4070 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4071 #define FDCAN_IR_RF1L_Pos (7U)
4072 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4073 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4074 #define FDCAN_IR_HPM_Pos (8U)
4075 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4076 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4077 #define FDCAN_IR_TC_Pos (9U)
4078 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4079 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4080 #define FDCAN_IR_TCF_Pos (10U)
4081 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4082 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4083 #define FDCAN_IR_TFE_Pos (11U)
4084 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4085 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4086 #define FDCAN_IR_TEFN_Pos (12U)
4087 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4088 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4089 #define FDCAN_IR_TEFW_Pos (13U)
4090 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4091 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4092 #define FDCAN_IR_TEFF_Pos (14U)
4093 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4094 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4095 #define FDCAN_IR_TEFL_Pos (15U)
4096 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4097 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4098 #define FDCAN_IR_TSW_Pos (16U)
4099 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4100 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4101 #define FDCAN_IR_MRAF_Pos (17U)
4102 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4103 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4104 #define FDCAN_IR_TOO_Pos (18U)
4105 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4106 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4107 #define FDCAN_IR_DRX_Pos (19U)
4108 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4109 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4110 #define FDCAN_IR_ELO_Pos (22U)
4111 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4112 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4113 #define FDCAN_IR_EP_Pos (23U)
4114 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4115 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4116 #define FDCAN_IR_EW_Pos (24U)
4117 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4118 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4119 #define FDCAN_IR_BO_Pos (25U)
4120 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4121 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4122 #define FDCAN_IR_WDI_Pos (26U)
4123 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4124 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4125 #define FDCAN_IR_PEA_Pos (27U)
4126 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4127 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4128 #define FDCAN_IR_PED_Pos (28U)
4129 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4130 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4131 #define FDCAN_IR_ARA_Pos (29U)
4132 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4133 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4134
4135 /***************** Bit definition for FDCAN_IE register **********************/
4136 #define FDCAN_IE_RF0NE_Pos (0U)
4137 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4138 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4139 #define FDCAN_IE_RF0WE_Pos (1U)
4140 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4141 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4142 #define FDCAN_IE_RF0FE_Pos (2U)
4143 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4144 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4145 #define FDCAN_IE_RF0LE_Pos (3U)
4146 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4147 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4148 #define FDCAN_IE_RF1NE_Pos (4U)
4149 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4150 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4151 #define FDCAN_IE_RF1WE_Pos (5U)
4152 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4153 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4154 #define FDCAN_IE_RF1FE_Pos (6U)
4155 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4156 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4157 #define FDCAN_IE_RF1LE_Pos (7U)
4158 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4159 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4160 #define FDCAN_IE_HPME_Pos (8U)
4161 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4162 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4163 #define FDCAN_IE_TCE_Pos (9U)
4164 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4165 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4166 #define FDCAN_IE_TCFE_Pos (10U)
4167 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4168 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4169 #define FDCAN_IE_TFEE_Pos (11U)
4170 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4171 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4172 #define FDCAN_IE_TEFNE_Pos (12U)
4173 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4174 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4175 #define FDCAN_IE_TEFWE_Pos (13U)
4176 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4177 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4178 #define FDCAN_IE_TEFFE_Pos (14U)
4179 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4180 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4181 #define FDCAN_IE_TEFLE_Pos (15U)
4182 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4183 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4184 #define FDCAN_IE_TSWE_Pos (16U)
4185 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4186 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4187 #define FDCAN_IE_MRAFE_Pos (17U)
4188 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4189 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4190 #define FDCAN_IE_TOOE_Pos (18U)
4191 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4192 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4193 #define FDCAN_IE_DRXE_Pos (19U)
4194 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4195 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4196 #define FDCAN_IE_BECE_Pos (20U)
4197 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4198 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4199 #define FDCAN_IE_BEUE_Pos (21U)
4200 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4201 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4202 #define FDCAN_IE_ELOE_Pos (22U)
4203 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4204 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4205 #define FDCAN_IE_EPE_Pos (23U)
4206 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4207 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4208 #define FDCAN_IE_EWE_Pos (24U)
4209 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4210 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4211 #define FDCAN_IE_BOE_Pos (25U)
4212 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4213 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4214 #define FDCAN_IE_WDIE_Pos (26U)
4215 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4216 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4217 #define FDCAN_IE_PEAE_Pos (27U)
4218 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4219 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4220 #define FDCAN_IE_PEDE_Pos (28U)
4221 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4222 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4223 #define FDCAN_IE_ARAE_Pos (29U)
4224 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4225 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4226
4227 /***************** Bit definition for FDCAN_ILS register **********************/
4228 #define FDCAN_ILS_RF0NL_Pos (0U)
4229 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4230 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4231 #define FDCAN_ILS_RF0WL_Pos (1U)
4232 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4233 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4234 #define FDCAN_ILS_RF0FL_Pos (2U)
4235 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4236 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4237 #define FDCAN_ILS_RF0LL_Pos (3U)
4238 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4239 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4240 #define FDCAN_ILS_RF1NL_Pos (4U)
4241 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4242 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4243 #define FDCAN_ILS_RF1WL_Pos (5U)
4244 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4245 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4246 #define FDCAN_ILS_RF1FL_Pos (6U)
4247 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4248 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4249 #define FDCAN_ILS_RF1LL_Pos (7U)
4250 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4251 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4252 #define FDCAN_ILS_HPML_Pos (8U)
4253 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4254 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4255 #define FDCAN_ILS_TCL_Pos (9U)
4256 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4257 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4258 #define FDCAN_ILS_TCFL_Pos (10U)
4259 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4260 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4261 #define FDCAN_ILS_TFEL_Pos (11U)
4262 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4263 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4264 #define FDCAN_ILS_TEFNL_Pos (12U)
4265 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4266 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4267 #define FDCAN_ILS_TEFWL_Pos (13U)
4268 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4269 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4270 #define FDCAN_ILS_TEFFL_Pos (14U)
4271 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4272 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4273 #define FDCAN_ILS_TEFLL_Pos (15U)
4274 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4275 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4276 #define FDCAN_ILS_TSWL_Pos (16U)
4277 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4278 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4279 #define FDCAN_ILS_MRAFE_Pos (17U)
4280 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4281 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4282 #define FDCAN_ILS_TOOE_Pos (18U)
4283 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4284 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4285 #define FDCAN_ILS_DRXE_Pos (19U)
4286 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4287 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4288 #define FDCAN_ILS_BECE_Pos (20U)
4289 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4290 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4291 #define FDCAN_ILS_BEUE_Pos (21U)
4292 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4293 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4294 #define FDCAN_ILS_ELOE_Pos (22U)
4295 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4296 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4297 #define FDCAN_ILS_EPE_Pos (23U)
4298 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4299 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4300 #define FDCAN_ILS_EWE_Pos (24U)
4301 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4302 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4303 #define FDCAN_ILS_BOE_Pos (25U)
4304 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4305 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4306 #define FDCAN_ILS_WDIE_Pos (26U)
4307 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4308 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4309 #define FDCAN_ILS_PEAE_Pos (27U)
4310 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4311 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4312 #define FDCAN_ILS_PEDE_Pos (28U)
4313 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4314 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4315 #define FDCAN_ILS_ARAE_Pos (29U)
4316 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4317 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4318
4319 /***************** Bit definition for FDCAN_ILE register **********************/
4320 #define FDCAN_ILE_EINT0_Pos (0U)
4321 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4322 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4323 #define FDCAN_ILE_EINT1_Pos (1U)
4324 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4325 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4326
4327 /***************** Bit definition for FDCAN_GFC register **********************/
4328 #define FDCAN_GFC_RRFE_Pos (0U)
4329 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4330 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4331 #define FDCAN_GFC_RRFS_Pos (1U)
4332 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4333 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4334 #define FDCAN_GFC_ANFE_Pos (2U)
4335 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4336 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4337 #define FDCAN_GFC_ANFS_Pos (4U)
4338 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4339 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4340
4341 /***************** Bit definition for FDCAN_SIDFC register ********************/
4342 #define FDCAN_SIDFC_FLSSA_Pos (2U)
4343 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4344 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4345 #define FDCAN_SIDFC_LSS_Pos (16U)
4346 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4347 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4348
4349 /***************** Bit definition for FDCAN_XIDFC register ********************/
4350 #define FDCAN_XIDFC_FLESA_Pos (2U)
4351 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4352 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4353 #define FDCAN_XIDFC_LSE_Pos (16U)
4354 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4355 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4356
4357 /***************** Bit definition for FDCAN_XIDAM register ********************/
4358 #define FDCAN_XIDAM_EIDM_Pos (0U)
4359 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4360 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4361
4362 /***************** Bit definition for FDCAN_HPMS register *********************/
4363 #define FDCAN_HPMS_BIDX_Pos (0U)
4364 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4365 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4366 #define FDCAN_HPMS_MSI_Pos (6U)
4367 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4368 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4369 #define FDCAN_HPMS_FIDX_Pos (8U)
4370 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4371 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4372 #define FDCAN_HPMS_FLST_Pos (15U)
4373 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4374 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4375
4376 /***************** Bit definition for FDCAN_NDAT1 register ********************/
4377 #define FDCAN_NDAT1_ND0_Pos (0U)
4378 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4379 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4380 #define FDCAN_NDAT1_ND1_Pos (1U)
4381 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4382 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4383 #define FDCAN_NDAT1_ND2_Pos (2U)
4384 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4385 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4386 #define FDCAN_NDAT1_ND3_Pos (3U)
4387 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4388 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4389 #define FDCAN_NDAT1_ND4_Pos (4U)
4390 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4391 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4392 #define FDCAN_NDAT1_ND5_Pos (5U)
4393 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4394 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4395 #define FDCAN_NDAT1_ND6_Pos (6U)
4396 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4397 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4398 #define FDCAN_NDAT1_ND7_Pos (7U)
4399 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4400 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4401 #define FDCAN_NDAT1_ND8_Pos (8U)
4402 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4403 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4404 #define FDCAN_NDAT1_ND9_Pos (9U)
4405 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4406 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4407 #define FDCAN_NDAT1_ND10_Pos (10U)
4408 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4409 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4410 #define FDCAN_NDAT1_ND11_Pos (11U)
4411 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4412 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4413 #define FDCAN_NDAT1_ND12_Pos (12U)
4414 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4415 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4416 #define FDCAN_NDAT1_ND13_Pos (13U)
4417 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4418 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4419 #define FDCAN_NDAT1_ND14_Pos (14U)
4420 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4421 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4422 #define FDCAN_NDAT1_ND15_Pos (15U)
4423 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4424 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4425 #define FDCAN_NDAT1_ND16_Pos (16U)
4426 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4427 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4428 #define FDCAN_NDAT1_ND17_Pos (17U)
4429 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4430 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4431 #define FDCAN_NDAT1_ND18_Pos (18U)
4432 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4433 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4434 #define FDCAN_NDAT1_ND19_Pos (19U)
4435 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4436 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4437 #define FDCAN_NDAT1_ND20_Pos (20U)
4438 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4439 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4440 #define FDCAN_NDAT1_ND21_Pos (21U)
4441 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4442 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4443 #define FDCAN_NDAT1_ND22_Pos (22U)
4444 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4445 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4446 #define FDCAN_NDAT1_ND23_Pos (23U)
4447 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4448 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4449 #define FDCAN_NDAT1_ND24_Pos (24U)
4450 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4451 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4452 #define FDCAN_NDAT1_ND25_Pos (25U)
4453 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4454 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4455 #define FDCAN_NDAT1_ND26_Pos (26U)
4456 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4457 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4458 #define FDCAN_NDAT1_ND27_Pos (27U)
4459 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4460 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4461 #define FDCAN_NDAT1_ND28_Pos (28U)
4462 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4463 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4464 #define FDCAN_NDAT1_ND29_Pos (29U)
4465 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4466 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4467 #define FDCAN_NDAT1_ND30_Pos (30U)
4468 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4469 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4470 #define FDCAN_NDAT1_ND31_Pos (31U)
4471 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4472 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4473
4474 /***************** Bit definition for FDCAN_NDAT2 register ********************/
4475 #define FDCAN_NDAT2_ND32_Pos (0U)
4476 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4477 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4478 #define FDCAN_NDAT2_ND33_Pos (1U)
4479 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4480 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4481 #define FDCAN_NDAT2_ND34_Pos (2U)
4482 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4483 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4484 #define FDCAN_NDAT2_ND35_Pos (3U)
4485 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4486 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4487 #define FDCAN_NDAT2_ND36_Pos (4U)
4488 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4489 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4490 #define FDCAN_NDAT2_ND37_Pos (5U)
4491 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4492 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4493 #define FDCAN_NDAT2_ND38_Pos (6U)
4494 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4495 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4496 #define FDCAN_NDAT2_ND39_Pos (7U)
4497 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4498 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4499 #define FDCAN_NDAT2_ND40_Pos (8U)
4500 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4501 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4502 #define FDCAN_NDAT2_ND41_Pos (9U)
4503 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4504 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4505 #define FDCAN_NDAT2_ND42_Pos (10U)
4506 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4507 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4508 #define FDCAN_NDAT2_ND43_Pos (11U)
4509 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4510 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4511 #define FDCAN_NDAT2_ND44_Pos (12U)
4512 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4513 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4514 #define FDCAN_NDAT2_ND45_Pos (13U)
4515 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4516 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4517 #define FDCAN_NDAT2_ND46_Pos (14U)
4518 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4519 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4520 #define FDCAN_NDAT2_ND47_Pos (15U)
4521 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4522 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4523 #define FDCAN_NDAT2_ND48_Pos (16U)
4524 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4525 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4526 #define FDCAN_NDAT2_ND49_Pos (17U)
4527 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4528 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4529 #define FDCAN_NDAT2_ND50_Pos (18U)
4530 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4531 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4532 #define FDCAN_NDAT2_ND51_Pos (19U)
4533 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4534 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4535 #define FDCAN_NDAT2_ND52_Pos (20U)
4536 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4537 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4538 #define FDCAN_NDAT2_ND53_Pos (21U)
4539 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4540 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4541 #define FDCAN_NDAT2_ND54_Pos (22U)
4542 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4543 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4544 #define FDCAN_NDAT2_ND55_Pos (23U)
4545 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4546 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4547 #define FDCAN_NDAT2_ND56_Pos (24U)
4548 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4549 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4550 #define FDCAN_NDAT2_ND57_Pos (25U)
4551 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4552 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4553 #define FDCAN_NDAT2_ND58_Pos (26U)
4554 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4555 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4556 #define FDCAN_NDAT2_ND59_Pos (27U)
4557 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4558 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4559 #define FDCAN_NDAT2_ND60_Pos (28U)
4560 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4561 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4562 #define FDCAN_NDAT2_ND61_Pos (29U)
4563 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4564 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4565 #define FDCAN_NDAT2_ND62_Pos (30U)
4566 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4567 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4568 #define FDCAN_NDAT2_ND63_Pos (31U)
4569 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4570 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4571
4572 /***************** Bit definition for FDCAN_RXF0C register ********************/
4573 #define FDCAN_RXF0C_F0SA_Pos (2U)
4574 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4575 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4576 #define FDCAN_RXF0C_F0S_Pos (16U)
4577 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4578 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4579 #define FDCAN_RXF0C_F0WM_Pos (24U)
4580 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4581 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4582 #define FDCAN_RXF0C_F0OM_Pos (31U)
4583 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4584 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4585
4586 /***************** Bit definition for FDCAN_RXF0S register ********************/
4587 #define FDCAN_RXF0S_F0FL_Pos (0U)
4588 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4589 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4590 #define FDCAN_RXF0S_F0GI_Pos (8U)
4591 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4592 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4593 #define FDCAN_RXF0S_F0PI_Pos (16U)
4594 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4595 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4596 #define FDCAN_RXF0S_F0F_Pos (24U)
4597 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4598 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4599 #define FDCAN_RXF0S_RF0L_Pos (25U)
4600 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4601 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4602
4603 /***************** Bit definition for FDCAN_RXF0A register ********************/
4604 #define FDCAN_RXF0A_F0AI_Pos (0U)
4605 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4606 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4607
4608 /***************** Bit definition for FDCAN_RXBC register ********************/
4609 #define FDCAN_RXBC_RBSA_Pos (2U)
4610 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4611 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4612
4613 /***************** Bit definition for FDCAN_RXF1C register ********************/
4614 #define FDCAN_RXF1C_F1SA_Pos (2U)
4615 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4616 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4617 #define FDCAN_RXF1C_F1S_Pos (16U)
4618 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4619 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4620 #define FDCAN_RXF1C_F1WM_Pos (24U)
4621 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4622 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4623 #define FDCAN_RXF1C_F1OM_Pos (31U)
4624 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4625 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4626
4627 /***************** Bit definition for FDCAN_RXF1S register ********************/
4628 #define FDCAN_RXF1S_F1FL_Pos (0U)
4629 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4630 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4631 #define FDCAN_RXF1S_F1GI_Pos (8U)
4632 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4633 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4634 #define FDCAN_RXF1S_F1PI_Pos (16U)
4635 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4636 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4637 #define FDCAN_RXF1S_F1F_Pos (24U)
4638 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4639 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4640 #define FDCAN_RXF1S_RF1L_Pos (25U)
4641 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4642 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4643
4644 /***************** Bit definition for FDCAN_RXF1A register ********************/
4645 #define FDCAN_RXF1A_F1AI_Pos (0U)
4646 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4647 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4648
4649 /***************** Bit definition for FDCAN_RXESC register ********************/
4650 #define FDCAN_RXESC_F0DS_Pos (0U)
4651 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4652 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4653 #define FDCAN_RXESC_F1DS_Pos (4U)
4654 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4655 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4656 #define FDCAN_RXESC_RBDS_Pos (8U)
4657 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4658 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4659
4660 /***************** Bit definition for FDCAN_TXBC register *********************/
4661 #define FDCAN_TXBC_TBSA_Pos (2U)
4662 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4663 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4664 #define FDCAN_TXBC_NDTB_Pos (16U)
4665 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4666 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4667 #define FDCAN_TXBC_TFQS_Pos (24U)
4668 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4669 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4670 #define FDCAN_TXBC_TFQM_Pos (30U)
4671 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4672 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4673
4674 /***************** Bit definition for FDCAN_TXFQS register *********************/
4675 #define FDCAN_TXFQS_TFFL_Pos (0U)
4676 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4677 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4678 #define FDCAN_TXFQS_TFGI_Pos (8U)
4679 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4680 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4681 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4682 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4683 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4684 #define FDCAN_TXFQS_TFQF_Pos (21U)
4685 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4686 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4687
4688 /***************** Bit definition for FDCAN_TXESC register *********************/
4689 #define FDCAN_TXESC_TBDS_Pos (0U)
4690 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4691 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4692
4693 /***************** Bit definition for FDCAN_TXBRP register *********************/
4694 #define FDCAN_TXBRP_TRP_Pos (0U)
4695 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4696 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4697
4698 /***************** Bit definition for FDCAN_TXBAR register *********************/
4699 #define FDCAN_TXBAR_AR_Pos (0U)
4700 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4701 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4702
4703 /***************** Bit definition for FDCAN_TXBCR register *********************/
4704 #define FDCAN_TXBCR_CR_Pos (0U)
4705 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4706 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4707
4708 /***************** Bit definition for FDCAN_TXBTO register *********************/
4709 #define FDCAN_TXBTO_TO_Pos (0U)
4710 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4711 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4712
4713 /***************** Bit definition for FDCAN_TXBCF register *********************/
4714 #define FDCAN_TXBCF_CF_Pos (0U)
4715 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4716 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4717
4718 /***************** Bit definition for FDCAN_TXBTIE register ********************/
4719 #define FDCAN_TXBTIE_TIE_Pos (0U)
4720 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4721 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4722
4723 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
4724 #define FDCAN_TXBCIE_CFIE_Pos (0U)
4725 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4726 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4727
4728 /***************** Bit definition for FDCAN_TXEFC register *********************/
4729 #define FDCAN_TXEFC_EFSA_Pos (2U)
4730 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4731 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4732 #define FDCAN_TXEFC_EFS_Pos (16U)
4733 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4734 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4735 #define FDCAN_TXEFC_EFWM_Pos (24U)
4736 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4737 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4738
4739 /***************** Bit definition for FDCAN_TXEFS register *********************/
4740 #define FDCAN_TXEFS_EFFL_Pos (0U)
4741 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4742 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4743 #define FDCAN_TXEFS_EFGI_Pos (8U)
4744 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4745 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4746 #define FDCAN_TXEFS_EFPI_Pos (16U)
4747 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4748 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4749 #define FDCAN_TXEFS_EFF_Pos (24U)
4750 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4751 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4752 #define FDCAN_TXEFS_TEFL_Pos (25U)
4753 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4754 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4755
4756 /***************** Bit definition for FDCAN_TXEFA register *********************/
4757 #define FDCAN_TXEFA_EFAI_Pos (0U)
4758 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4759 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4760
4761 /***************** Bit definition for FDCAN_TTTMC register *********************/
4762 #define FDCAN_TTTMC_TMSA_Pos (2U)
4763 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4764 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4765 #define FDCAN_TTTMC_TME_Pos (16U)
4766 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4767 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4768
4769 /***************** Bit definition for FDCAN_TTRMC register *********************/
4770 #define FDCAN_TTRMC_RID_Pos (0U)
4771 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4772 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4773 #define FDCAN_TTRMC_XTD_Pos (30U)
4774 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4775 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4776 #define FDCAN_TTRMC_RMPS_Pos (31U)
4777 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4778 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4779
4780 /***************** Bit definition for FDCAN_TTOCF register *********************/
4781 #define FDCAN_TTOCF_OM_Pos (0U)
4782 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4783 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4784 #define FDCAN_TTOCF_GEN_Pos (3U)
4785 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4786 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4787 #define FDCAN_TTOCF_TM_Pos (4U)
4788 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4789 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4790 #define FDCAN_TTOCF_LDSDL_Pos (5U)
4791 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4792 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4793 #define FDCAN_TTOCF_IRTO_Pos (8U)
4794 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4795 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4796 #define FDCAN_TTOCF_EECS_Pos (15U)
4797 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4798 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4799 #define FDCAN_TTOCF_AWL_Pos (16U)
4800 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4801 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4802 #define FDCAN_TTOCF_EGTF_Pos (24U)
4803 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4804 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4805 #define FDCAN_TTOCF_ECC_Pos (25U)
4806 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4807 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4808 #define FDCAN_TTOCF_EVTP_Pos (26U)
4809 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4810 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4811
4812 /***************** Bit definition for FDCAN_TTMLM register *********************/
4813 #define FDCAN_TTMLM_CCM_Pos (0U)
4814 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4815 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4816 #define FDCAN_TTMLM_CSS_Pos (6U)
4817 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4818 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4819 #define FDCAN_TTMLM_TXEW_Pos (8U)
4820 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4821 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4822 #define FDCAN_TTMLM_ENTT_Pos (16U)
4823 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4824 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4825
4826 /***************** Bit definition for FDCAN_TURCF register *********************/
4827 #define FDCAN_TURCF_NCL_Pos (0U)
4828 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
4829 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
4830 #define FDCAN_TURCF_DC_Pos (16U)
4831 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
4832 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
4833 #define FDCAN_TURCF_ELT_Pos (31U)
4834 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
4835 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
4836
4837 /***************** Bit definition for FDCAN_TTOCN register ********************/
4838 #define FDCAN_TTOCN_SGT_Pos (0U)
4839 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
4840 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
4841 #define FDCAN_TTOCN_ECS_Pos (1U)
4842 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
4843 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
4844 #define FDCAN_TTOCN_SWP_Pos (2U)
4845 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
4846 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
4847 #define FDCAN_TTOCN_SWS_Pos (3U)
4848 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
4849 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
4850 #define FDCAN_TTOCN_RTIE_Pos (5U)
4851 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
4852 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
4853 #define FDCAN_TTOCN_TMC_Pos (6U)
4854 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
4855 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
4856 #define FDCAN_TTOCN_TTIE_Pos (8U)
4857 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
4858 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
4859 #define FDCAN_TTOCN_GCS_Pos (9U)
4860 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
4861 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
4862 #define FDCAN_TTOCN_FGP_Pos (10U)
4863 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
4864 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
4865 #define FDCAN_TTOCN_TMG_Pos (11U)
4866 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
4867 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
4868 #define FDCAN_TTOCN_NIG_Pos (12U)
4869 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
4870 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
4871 #define FDCAN_TTOCN_ESCN_Pos (13U)
4872 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
4873 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
4874 #define FDCAN_TTOCN_LCKC_Pos (15U)
4875 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
4876 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
4877
4878 /***************** Bit definition for FDCAN_TTGTP register ********************/
4879 #define FDCAN_TTGTP_TP_Pos (0U)
4880 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
4881 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
4882 #define FDCAN_TTGTP_CTP_Pos (16U)
4883 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
4884 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
4885
4886 /***************** Bit definition for FDCAN_TTTMK register ********************/
4887 #define FDCAN_TTTMK_TM_Pos (0U)
4888 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
4889 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
4890 #define FDCAN_TTTMK_TICC_Pos (16U)
4891 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
4892 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
4893 #define FDCAN_TTTMK_LCKM_Pos (31U)
4894 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
4895 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
4896
4897 /***************** Bit definition for FDCAN_TTIR register ********************/
4898 #define FDCAN_TTIR_SBC_Pos (0U)
4899 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
4900 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
4901 #define FDCAN_TTIR_SMC_Pos (1U)
4902 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
4903 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
4904 #define FDCAN_TTIR_CSM_Pos (2U)
4905 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
4906 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
4907 #define FDCAN_TTIR_SOG_Pos (3U)
4908 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
4909 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
4910 #define FDCAN_TTIR_RTMI_Pos (4U)
4911 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
4912 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
4913 #define FDCAN_TTIR_TTMI_Pos (5U)
4914 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
4915 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
4916 #define FDCAN_TTIR_SWE_Pos (6U)
4917 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
4918 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
4919 #define FDCAN_TTIR_GTW_Pos (7U)
4920 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
4921 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
4922 #define FDCAN_TTIR_GTD_Pos (8U)
4923 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
4924 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
4925 #define FDCAN_TTIR_GTE_Pos (9U)
4926 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
4927 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
4928 #define FDCAN_TTIR_TXU_Pos (10U)
4929 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
4930 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
4931 #define FDCAN_TTIR_TXO_Pos (11U)
4932 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
4933 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
4934 #define FDCAN_TTIR_SE1_Pos (12U)
4935 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
4936 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
4937 #define FDCAN_TTIR_SE2_Pos (13U)
4938 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
4939 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
4940 #define FDCAN_TTIR_ELC_Pos (14U)
4941 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
4942 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
4943 #define FDCAN_TTIR_IWT_Pos (15U)
4944 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
4945 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
4946 #define FDCAN_TTIR_WT_Pos (16U)
4947 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
4948 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
4949 #define FDCAN_TTIR_AW_Pos (17U)
4950 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
4951 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
4952 #define FDCAN_TTIR_CER_Pos (18U)
4953 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
4954 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
4955
4956 /***************** Bit definition for FDCAN_TTIE register ********************/
4957 #define FDCAN_TTIE_SBCE_Pos (0U)
4958 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
4959 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
4960 #define FDCAN_TTIE_SMCE_Pos (1U)
4961 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
4962 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
4963 #define FDCAN_TTIE_CSME_Pos (2U)
4964 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
4965 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
4966 #define FDCAN_TTIE_SOGE_Pos (3U)
4967 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
4968 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
4969 #define FDCAN_TTIE_RTMIE_Pos (4U)
4970 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
4971 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
4972 #define FDCAN_TTIE_TTMIE_Pos (5U)
4973 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
4974 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
4975 #define FDCAN_TTIE_SWEE_Pos (6U)
4976 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
4977 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
4978 #define FDCAN_TTIE_GTWE_Pos (7U)
4979 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
4980 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
4981 #define FDCAN_TTIE_GTDE_Pos (8U)
4982 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
4983 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
4984 #define FDCAN_TTIE_GTEE_Pos (9U)
4985 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
4986 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
4987 #define FDCAN_TTIE_TXUE_Pos (10U)
4988 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
4989 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
4990 #define FDCAN_TTIE_TXOE_Pos (11U)
4991 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
4992 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
4993 #define FDCAN_TTIE_SE1E_Pos (12U)
4994 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
4995 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
4996 #define FDCAN_TTIE_SE2E_Pos (13U)
4997 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
4998 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
4999 #define FDCAN_TTIE_ELCE_Pos (14U)
5000 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5001 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5002 #define FDCAN_TTIE_IWTE_Pos (15U)
5003 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5004 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5005 #define FDCAN_TTIE_WTE_Pos (16U)
5006 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5007 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5008 #define FDCAN_TTIE_AWE_Pos (17U)
5009 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5010 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5011 #define FDCAN_TTIE_CERE_Pos (18U)
5012 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5013 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5014
5015 /***************** Bit definition for FDCAN_TTILS register ********************/
5016 #define FDCAN_TTILS_SBCS_Pos (0U)
5017 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5018 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5019 #define FDCAN_TTILS_SMCS_Pos (1U)
5020 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5021 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5022 #define FDCAN_TTILS_CSMS_Pos (2U)
5023 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5024 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5025 #define FDCAN_TTILS_SOGS_Pos (3U)
5026 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5027 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5028 #define FDCAN_TTILS_RTMIS_Pos (4U)
5029 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5030 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5031 #define FDCAN_TTILS_TTMIS_Pos (5U)
5032 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5033 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5034 #define FDCAN_TTILS_SWES_Pos (6U)
5035 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5036 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5037 #define FDCAN_TTILS_GTWS_Pos (7U)
5038 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5039 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5040 #define FDCAN_TTILS_GTDS_Pos (8U)
5041 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5042 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5043 #define FDCAN_TTILS_GTES_Pos (9U)
5044 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5045 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5046 #define FDCAN_TTILS_TXUS_Pos (10U)
5047 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5048 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5049 #define FDCAN_TTILS_TXOS_Pos (11U)
5050 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5051 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5052 #define FDCAN_TTILS_SE1S_Pos (12U)
5053 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5054 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5055 #define FDCAN_TTILS_SE2S_Pos (13U)
5056 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5057 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5058 #define FDCAN_TTILS_ELCS_Pos (14U)
5059 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5060 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5061 #define FDCAN_TTILS_IWTS_Pos (15U)
5062 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5063 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5064 #define FDCAN_TTILS_WTS_Pos (16U)
5065 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5066 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5067 #define FDCAN_TTILS_AWS_Pos (17U)
5068 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5069 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5070 #define FDCAN_TTILS_CERS_Pos (18U)
5071 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5072 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5073
5074 /***************** Bit definition for FDCAN_TTOST register ********************/
5075 #define FDCAN_TTOST_EL_Pos (0U)
5076 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5077 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5078 #define FDCAN_TTOST_MS_Pos (2U)
5079 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5080 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5081 #define FDCAN_TTOST_SYS_Pos (4U)
5082 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5083 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5084 #define FDCAN_TTOST_QGTP_Pos (6U)
5085 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5086 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5087 #define FDCAN_TTOST_QCS_Pos (7U)
5088 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5089 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5090 #define FDCAN_TTOST_RTO_Pos (8U)
5091 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5092 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5093 #define FDCAN_TTOST_WGTD_Pos (22U)
5094 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5095 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5096 #define FDCAN_TTOST_GFI_Pos (23U)
5097 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5098 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5099 #define FDCAN_TTOST_TMP_Pos (24U)
5100 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5101 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5102 #define FDCAN_TTOST_GSI_Pos (27U)
5103 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5104 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5105 #define FDCAN_TTOST_WFE_Pos (28U)
5106 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5107 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5108 #define FDCAN_TTOST_AWE_Pos (29U)
5109 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5110 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5111 #define FDCAN_TTOST_WECS_Pos (30U)
5112 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5113 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5114 #define FDCAN_TTOST_SPL_Pos (31U)
5115 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5116 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5117
5118 /***************** Bit definition for FDCAN_TURNA register ********************/
5119 #define FDCAN_TURNA_NAV_Pos (0U)
5120 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5121 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5122
5123 /***************** Bit definition for FDCAN_TTLGT register ********************/
5124 #define FDCAN_TTLGT_LT_Pos (0U)
5125 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5126 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5127 #define FDCAN_TTLGT_GT_Pos (16U)
5128 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5129 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5130
5131 /***************** Bit definition for FDCAN_TTCTC register ********************/
5132 #define FDCAN_TTCTC_CT_Pos (0U)
5133 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5134 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5135 #define FDCAN_TTCTC_CC_Pos (16U)
5136 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5137 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5138
5139 /***************** Bit definition for FDCAN_TTCPT register ********************/
5140 #define FDCAN_TTCPT_CCV_Pos (0U)
5141 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5142 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5143 #define FDCAN_TTCPT_SWV_Pos (16U)
5144 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5145 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5146
5147 /***************** Bit definition for FDCAN_TTCSM register ********************/
5148 #define FDCAN_TTCSM_CSM_Pos (0U)
5149 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5150 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5151
5152 /***************** Bit definition for FDCAN_TTTS register *********************/
5153 #define FDCAN_TTTS_SWTSEL_Pos (0U)
5154 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5155 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5156 #define FDCAN_TTTS_EVTSEL_Pos (4U)
5157 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5158 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5159
5160 /********************************************************************************/
5161 /* */
5162 /* FDCANCCU (Clock Calibration unit) */
5163 /* */
5164 /********************************************************************************/
5165
5166 /***************** Bit definition for FDCANCCU_CREL register ******************/
5167 #define FDCANCCU_CREL_DAY_Pos (0U)
5168 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5169 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5170 #define FDCANCCU_CREL_MON_Pos (8U)
5171 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5172 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5173 #define FDCANCCU_CREL_YEAR_Pos (16U)
5174 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5175 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5176 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5177 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5178 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5179 #define FDCANCCU_CREL_STEP_Pos (24U)
5180 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5181 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5182 #define FDCANCCU_CREL_REL_Pos (28U)
5183 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5184 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5185
5186 /***************** Bit definition for FDCANCCU_CCFG register ******************/
5187 #define FDCANCCU_CCFG_TQBT_Pos (0U)
5188 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5189 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5190 #define FDCANCCU_CCFG_BCC_Pos (6U)
5191 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5192 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5193 #define FDCANCCU_CCFG_CFL_Pos (7U)
5194 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5195 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5196 #define FDCANCCU_CCFG_OCPM_Pos (8U)
5197 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5198 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5199 #define FDCANCCU_CCFG_CDIV_Pos (16U)
5200 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5201 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5202 #define FDCANCCU_CCFG_SWR_Pos (31U)
5203 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5204 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5205
5206 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
5207 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
5208 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5209 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5210 #define FDCANCCU_CSTAT_TQC_Pos (18U)
5211 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5212 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5213 #define FDCANCCU_CSTAT_CALS_Pos (30U)
5214 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5215 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5216
5217 /****************** Bit definition for FDCANCCU_CWD register ******************/
5218 #define FDCANCCU_CWD_WDC_Pos (0U)
5219 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5220 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5221 #define FDCANCCU_CWD_WDV_Pos (16U)
5222 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5223 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5224
5225 /****************** Bit definition for FDCANCCU_IR register *******************/
5226 #define FDCANCCU_IR_CWE_Pos (0U)
5227 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5228 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5229 #define FDCANCCU_IR_CSC_Pos (1U)
5230 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5231 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5232
5233 /****************** Bit definition for FDCANCCU_IE register *******************/
5234 #define FDCANCCU_IE_CWEE_Pos (0U)
5235 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5236 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5237 #define FDCANCCU_IE_CSCE_Pos (1U)
5238 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5239 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5240
5241 /******************************************************************************/
5242 /* */
5243 /* HDMI-CEC (CEC) */
5244 /* */
5245 /******************************************************************************/
5246
5247 /******************* Bit definition for CEC_CR register *********************/
5248 #define CEC_CR_CECEN_Pos (0U)
5249 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5250 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5251 #define CEC_CR_TXSOM_Pos (1U)
5252 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5253 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5254 #define CEC_CR_TXEOM_Pos (2U)
5255 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5256 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5257
5258 /******************* Bit definition for CEC_CFGR register *******************/
5259 #define CEC_CFGR_SFT_Pos (0U)
5260 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5261 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5262 #define CEC_CFGR_RXTOL_Pos (3U)
5263 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5264 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5265 #define CEC_CFGR_BRESTP_Pos (4U)
5266 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5267 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5268 #define CEC_CFGR_BREGEN_Pos (5U)
5269 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5270 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5271 #define CEC_CFGR_LBPEGEN_Pos (6U)
5272 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5273 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5274 #define CEC_CFGR_SFTOPT_Pos (8U)
5275 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5276 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5277 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5278 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5279 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5280 #define CEC_CFGR_OAR_Pos (16U)
5281 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5282 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5283 #define CEC_CFGR_LSTN_Pos (31U)
5284 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5285 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5286
5287 /******************* Bit definition for CEC_TXDR register *******************/
5288 #define CEC_TXDR_TXD_Pos (0U)
5289 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5290 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5291
5292 /******************* Bit definition for CEC_RXDR register *******************/
5293 #define CEC_RXDR_RXD_Pos (0U)
5294 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5295 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5296
5297 /******************* Bit definition for CEC_ISR register ********************/
5298 #define CEC_ISR_RXBR_Pos (0U)
5299 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5300 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5301 #define CEC_ISR_RXEND_Pos (1U)
5302 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5303 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5304 #define CEC_ISR_RXOVR_Pos (2U)
5305 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5306 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5307 #define CEC_ISR_BRE_Pos (3U)
5308 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5309 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5310 #define CEC_ISR_SBPE_Pos (4U)
5311 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5312 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5313 #define CEC_ISR_LBPE_Pos (5U)
5314 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5315 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5316 #define CEC_ISR_RXACKE_Pos (6U)
5317 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5318 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5319 #define CEC_ISR_ARBLST_Pos (7U)
5320 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5321 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5322 #define CEC_ISR_TXBR_Pos (8U)
5323 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5324 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5325 #define CEC_ISR_TXEND_Pos (9U)
5326 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5327 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5328 #define CEC_ISR_TXUDR_Pos (10U)
5329 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5330 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5331 #define CEC_ISR_TXERR_Pos (11U)
5332 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5333 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5334 #define CEC_ISR_TXACKE_Pos (12U)
5335 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5336 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5337
5338 /******************* Bit definition for CEC_IER register ********************/
5339 #define CEC_IER_RXBRIE_Pos (0U)
5340 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5341 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5342 #define CEC_IER_RXENDIE_Pos (1U)
5343 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5344 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5345 #define CEC_IER_RXOVRIE_Pos (2U)
5346 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5347 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5348 #define CEC_IER_BREIE_Pos (3U)
5349 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5350 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5351 #define CEC_IER_SBPEIE_Pos (4U)
5352 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5353 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5354 #define CEC_IER_LBPEIE_Pos (5U)
5355 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5356 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5357 #define CEC_IER_RXACKEIE_Pos (6U)
5358 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5359 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5360 #define CEC_IER_ARBLSTIE_Pos (7U)
5361 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5362 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5363 #define CEC_IER_TXBRIE_Pos (8U)
5364 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5365 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5366 #define CEC_IER_TXENDIE_Pos (9U)
5367 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5368 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5369 #define CEC_IER_TXUDRIE_Pos (10U)
5370 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5371 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5372 #define CEC_IER_TXERRIE_Pos (11U)
5373 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5374 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5375 #define CEC_IER_TXACKEIE_Pos (12U)
5376 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5377 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5378
5379 /******************************************************************************/
5380 /* */
5381 /* CRC calculation unit */
5382 /* */
5383 /******************************************************************************/
5384 /******************* Bit definition for CRC_DR register *********************/
5385 #define CRC_DR_DR_Pos (0U)
5386 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5387 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5388
5389 /******************* Bit definition for CRC_IDR register ********************/
5390 #define CRC_IDR_IDR_Pos (0U)
5391 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5392 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5393
5394 /******************** Bit definition for CRC_CR register ********************/
5395 #define CRC_CR_RESET_Pos (0U)
5396 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5397 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5398 #define CRC_CR_POLYSIZE_Pos (3U)
5399 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5400 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5401 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5402 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5403 #define CRC_CR_REV_IN_Pos (5U)
5404 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5405 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5406 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5407 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5408 #define CRC_CR_REV_OUT_Pos (7U)
5409 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5410 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5411
5412 /******************* Bit definition for CRC_INIT register *******************/
5413 #define CRC_INIT_INIT_Pos (0U)
5414 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5415 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5416
5417 /******************* Bit definition for CRC_POL register ********************/
5418 #define CRC_POL_POL_Pos (0U)
5419 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5420 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5421
5422 /******************************************************************************/
5423 /* */
5424 /* CRS Clock Recovery System */
5425 /******************************************************************************/
5426
5427 /******************* Bit definition for CRS_CR register *********************/
5428 #define CRS_CR_SYNCOKIE_Pos (0U)
5429 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5430 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5431 #define CRS_CR_SYNCWARNIE_Pos (1U)
5432 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5433 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5434 #define CRS_CR_ERRIE_Pos (2U)
5435 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5436 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5437 #define CRS_CR_ESYNCIE_Pos (3U)
5438 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5439 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5440 #define CRS_CR_CEN_Pos (5U)
5441 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5442 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5443 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5444 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5445 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5446 #define CRS_CR_SWSYNC_Pos (7U)
5447 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5448 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5449 #define CRS_CR_TRIM_Pos (8U)
5450 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5451 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5452
5453 /******************* Bit definition for CRS_CFGR register *********************/
5454 #define CRS_CFGR_RELOAD_Pos (0U)
5455 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5456 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5457 #define CRS_CFGR_FELIM_Pos (16U)
5458 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5459 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5460
5461 #define CRS_CFGR_SYNCDIV_Pos (24U)
5462 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5463 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5464 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5465 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5466 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5467
5468 #define CRS_CFGR_SYNCSRC_Pos (28U)
5469 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5470 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5471 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5472 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5473
5474 #define CRS_CFGR_SYNCPOL_Pos (31U)
5475 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5476 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5477
5478 /******************* Bit definition for CRS_ISR register *********************/
5479 #define CRS_ISR_SYNCOKF_Pos (0U)
5480 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5481 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5482 #define CRS_ISR_SYNCWARNF_Pos (1U)
5483 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5484 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5485 #define CRS_ISR_ERRF_Pos (2U)
5486 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5487 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5488 #define CRS_ISR_ESYNCF_Pos (3U)
5489 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5490 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5491 #define CRS_ISR_SYNCERR_Pos (8U)
5492 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5493 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5494 #define CRS_ISR_SYNCMISS_Pos (9U)
5495 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5496 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5497 #define CRS_ISR_TRIMOVF_Pos (10U)
5498 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5499 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5500 #define CRS_ISR_FEDIR_Pos (15U)
5501 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5502 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5503 #define CRS_ISR_FECAP_Pos (16U)
5504 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5505 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5506
5507 /******************* Bit definition for CRS_ICR register *********************/
5508 #define CRS_ICR_SYNCOKC_Pos (0U)
5509 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5510 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5511 #define CRS_ICR_SYNCWARNC_Pos (1U)
5512 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5513 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5514 #define CRS_ICR_ERRC_Pos (2U)
5515 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5516 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5517 #define CRS_ICR_ESYNCC_Pos (3U)
5518 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5519 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5520
5521 /******************************************************************************/
5522 /* */
5523 /* Digital to Analog Converter */
5524 /* */
5525 /******************************************************************************/
5526 /******************** Bit definition for DAC_CR register ********************/
5527 #define DAC_CR_EN1_Pos (0U)
5528 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5529 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5530 #define DAC_CR_TEN1_Pos (1U)
5531 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5532 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5533
5534 #define DAC_CR_TSEL1_Pos (2U)
5535 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5536 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5537 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5538 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5539 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5540 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5541
5542
5543 #define DAC_CR_WAVE1_Pos (6U)
5544 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5545 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5546 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5547 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5548
5549 #define DAC_CR_MAMP1_Pos (8U)
5550 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5551 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5552 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5553 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5554 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5555 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5556
5557 #define DAC_CR_DMAEN1_Pos (12U)
5558 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5559 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5560 #define DAC_CR_DMAUDRIE1_Pos (13U)
5561 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5562 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5563 #define DAC_CR_CEN1_Pos (14U)
5564 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5565 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5566
5567 #define DAC_CR_EN2_Pos (16U)
5568 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5569 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5570 #define DAC_CR_TEN2_Pos (17U)
5571 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5572 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5573
5574 #define DAC_CR_TSEL2_Pos (18U)
5575 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5576 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5577 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5578 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5579 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5580 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5581
5582
5583 #define DAC_CR_WAVE2_Pos (22U)
5584 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5585 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5586 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5587 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5588
5589 #define DAC_CR_MAMP2_Pos (24U)
5590 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5591 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5592 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5593 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5594 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5595 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5596
5597 #define DAC_CR_DMAEN2_Pos (28U)
5598 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5599 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5600 #define DAC_CR_DMAUDRIE2_Pos (29U)
5601 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5602 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5603 #define DAC_CR_CEN2_Pos (30U)
5604 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5605 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5606
5607 /***************** Bit definition for DAC_SWTRIGR register ******************/
5608 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5609 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5610 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5611 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5612 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5613 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5614
5615 /***************** Bit definition for DAC_DHR12R1 register ******************/
5616 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5617 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5618 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5619
5620 /***************** Bit definition for DAC_DHR12L1 register ******************/
5621 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5622 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5623 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5624
5625 /****************** Bit definition for DAC_DHR8R1 register ******************/
5626 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5627 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5628 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5629
5630 /***************** Bit definition for DAC_DHR12R2 register ******************/
5631 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5632 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5633 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5634
5635 /***************** Bit definition for DAC_DHR12L2 register ******************/
5636 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5637 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5638 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5639
5640 /****************** Bit definition for DAC_DHR8R2 register ******************/
5641 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5642 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5643 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5644
5645 /***************** Bit definition for DAC_DHR12RD register ******************/
5646 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5647 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5648 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5649 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5650 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5651 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5652
5653 /***************** Bit definition for DAC_DHR12LD register ******************/
5654 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5655 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5656 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5657 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5658 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5659 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5660
5661 /****************** Bit definition for DAC_DHR8RD register ******************/
5662 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5663 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5664 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5665 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5666 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5667 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5668
5669 /******************* Bit definition for DAC_DOR1 register *******************/
5670 #define DAC_DOR1_DACC1DOR_Pos (0U)
5671 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5672 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5673
5674 /******************* Bit definition for DAC_DOR2 register *******************/
5675 #define DAC_DOR2_DACC2DOR_Pos (0U)
5676 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5677 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5678
5679 /******************** Bit definition for DAC_SR register ********************/
5680 #define DAC_SR_DMAUDR1_Pos (13U)
5681 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5682 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5683 #define DAC_SR_CAL_FLAG1_Pos (14U)
5684 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5685 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5686 #define DAC_SR_BWST1_Pos (15U)
5687 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5688 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5689
5690 #define DAC_SR_DMAUDR2_Pos (29U)
5691 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5692 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5693 #define DAC_SR_CAL_FLAG2_Pos (30U)
5694 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5695 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5696 #define DAC_SR_BWST2_Pos (31U)
5697 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5698 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5699
5700 /******************* Bit definition for DAC_CCR register ********************/
5701 #define DAC_CCR_OTRIM1_Pos (0U)
5702 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5703 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5704 #define DAC_CCR_OTRIM2_Pos (16U)
5705 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5706 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5707
5708 /******************* Bit definition for DAC_MCR register *******************/
5709 #define DAC_MCR_MODE1_Pos (0U)
5710 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5711 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5712 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5713 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5714 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5715
5716 #define DAC_MCR_MODE2_Pos (16U)
5717 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5718 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5719 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5720 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5721 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5722
5723 /****************** Bit definition for DAC_SHSR1 register ******************/
5724 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
5725 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5726 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5727
5728 /****************** Bit definition for DAC_SHSR2 register ******************/
5729 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
5730 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
5731 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
5732
5733 /****************** Bit definition for DAC_SHHR register ******************/
5734 #define DAC_SHHR_THOLD1_Pos (0U)
5735 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
5736 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
5737 #define DAC_SHHR_THOLD2_Pos (16U)
5738 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
5739 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
5740
5741 /****************** Bit definition for DAC_SHRR register ******************/
5742 #define DAC_SHRR_TREFRESH1_Pos (0U)
5743 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
5744 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
5745 #define DAC_SHRR_TREFRESH2_Pos (16U)
5746 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
5747 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
5748
5749 /******************************************************************************/
5750 /* */
5751 /* DCMI */
5752 /* */
5753 /******************************************************************************/
5754 /******************** Bits definition for DCMI_CR register ******************/
5755 #define DCMI_CR_CAPTURE_Pos (0U)
5756 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5757 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5758 #define DCMI_CR_CM_Pos (1U)
5759 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5760 #define DCMI_CR_CM DCMI_CR_CM_Msk
5761 #define DCMI_CR_CROP_Pos (2U)
5762 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5763 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5764 #define DCMI_CR_JPEG_Pos (3U)
5765 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5766 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5767 #define DCMI_CR_ESS_Pos (4U)
5768 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5769 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5770 #define DCMI_CR_PCKPOL_Pos (5U)
5771 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5772 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5773 #define DCMI_CR_HSPOL_Pos (6U)
5774 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5775 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5776 #define DCMI_CR_VSPOL_Pos (7U)
5777 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5778 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5779 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
5780 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
5781 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
5782 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
5783 #define DCMI_CR_CRE_Pos (12U)
5784 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5785 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5786 #define DCMI_CR_ENABLE_Pos (14U)
5787 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5788 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5789 #define DCMI_CR_BSM_Pos (16U)
5790 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
5791 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
5792 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
5793 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
5794 #define DCMI_CR_OEBS_Pos (18U)
5795 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
5796 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5797 #define DCMI_CR_LSM_Pos (19U)
5798 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
5799 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
5800 #define DCMI_CR_OELS_Pos (20U)
5801 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
5802 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
5803
5804 /******************** Bits definition for DCMI_SR register ******************/
5805 #define DCMI_SR_HSYNC_Pos (0U)
5806 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5807 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5808 #define DCMI_SR_VSYNC_Pos (1U)
5809 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5810 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5811 #define DCMI_SR_FNE_Pos (2U)
5812 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5813 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5814
5815 /******************** Bits definition for DCMI_RIS register ****************/
5816 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5817 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5818 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5819 #define DCMI_RIS_OVR_RIS_Pos (1U)
5820 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5821 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5822 #define DCMI_RIS_ERR_RIS_Pos (2U)
5823 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5824 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5825 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5826 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5827 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5828 #define DCMI_RIS_LINE_RIS_Pos (4U)
5829 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5830 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5831
5832 /******************** Bits definition for DCMI_IER register *****************/
5833 #define DCMI_IER_FRAME_IE_Pos (0U)
5834 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5835 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5836 #define DCMI_IER_OVR_IE_Pos (1U)
5837 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5838 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5839 #define DCMI_IER_ERR_IE_Pos (2U)
5840 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5841 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5842 #define DCMI_IER_VSYNC_IE_Pos (3U)
5843 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5844 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5845 #define DCMI_IER_LINE_IE_Pos (4U)
5846 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5847 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5848
5849
5850 /******************** Bits definition for DCMI_MIS register *****************/
5851 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5852 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5853 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5854 #define DCMI_MIS_OVR_MIS_Pos (1U)
5855 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5856 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5857 #define DCMI_MIS_ERR_MIS_Pos (2U)
5858 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5859 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5860 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5861 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5862 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5863 #define DCMI_MIS_LINE_MIS_Pos (4U)
5864 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5865 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5866
5867
5868 /******************** Bits definition for DCMI_ICR register *****************/
5869 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5870 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5871 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5872 #define DCMI_ICR_OVR_ISC_Pos (1U)
5873 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5874 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5875 #define DCMI_ICR_ERR_ISC_Pos (2U)
5876 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5877 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5878 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5879 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5880 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5881 #define DCMI_ICR_LINE_ISC_Pos (4U)
5882 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5883 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5884
5885
5886 /******************** Bits definition for DCMI_ESCR register ******************/
5887 #define DCMI_ESCR_FSC_Pos (0U)
5888 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5889 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5890 #define DCMI_ESCR_LSC_Pos (8U)
5891 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5892 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5893 #define DCMI_ESCR_LEC_Pos (16U)
5894 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5895 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5896 #define DCMI_ESCR_FEC_Pos (24U)
5897 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5898 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5899
5900 /******************** Bits definition for DCMI_ESUR register ******************/
5901 #define DCMI_ESUR_FSU_Pos (0U)
5902 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5903 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5904 #define DCMI_ESUR_LSU_Pos (8U)
5905 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5906 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5907 #define DCMI_ESUR_LEU_Pos (16U)
5908 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5909 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5910 #define DCMI_ESUR_FEU_Pos (24U)
5911 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5912 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5913
5914 /******************** Bits definition for DCMI_CWSTRT register ******************/
5915 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5916 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5917 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5918 #define DCMI_CWSTRT_VST_Pos (16U)
5919 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5920 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5921
5922 /******************** Bits definition for DCMI_CWSIZE register ******************/
5923 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5924 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5925 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5926 #define DCMI_CWSIZE_VLINE_Pos (16U)
5927 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5928 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5929
5930 /******************** Bits definition for DCMI_DR register ******************/
5931 #define DCMI_DR_BYTE0_Pos (0U)
5932 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5933 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5934 #define DCMI_DR_BYTE1_Pos (8U)
5935 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5936 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5937 #define DCMI_DR_BYTE2_Pos (16U)
5938 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5939 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5940 #define DCMI_DR_BYTE3_Pos (24U)
5941 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5942 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5943
5944 /******************************************************************************/
5945 /* */
5946 /* Digital Filter for Sigma Delta Modulators */
5947 /* */
5948 /******************************************************************************/
5949
5950 /**************** DFSDM channel configuration registers ********************/
5951
5952 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5953 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5954 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
5955 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
5956 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5957 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
5958 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
5959 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5960 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
5961 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
5962 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5963 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
5964 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
5965 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
5966 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
5967 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5968 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
5969 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
5970 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
5971 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
5972 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5973 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
5974 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
5975 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
5976 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
5977 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
5978 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5979 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
5980 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
5981 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5982 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
5983 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
5984 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5985 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
5986 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
5987 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
5988 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
5989 #define DFSDM_CHCFGR1_SITP_Pos (0U)
5990 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
5991 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
5992 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
5993 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
5994
5995 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5996 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5997 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
5998 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
5999 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6000 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6001 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6002
6003 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6004 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6005 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6006 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6007 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6008 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6009 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6010 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6011 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6012 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6013 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6014 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6015 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6016 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6017 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6018
6019 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6020 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6021 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6022 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6023
6024 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6025 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6026 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6027 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6028 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6029 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6030 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6031
6032 /************************ DFSDM module registers ****************************/
6033
6034 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
6035 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6036 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6037 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6038 #define DFSDM_FLTCR1_FAST_Pos (29U)
6039 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6040 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6041 #define DFSDM_FLTCR1_RCH_Pos (24U)
6042 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6043 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6044 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6045 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6046 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6047 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6048 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6049 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6050 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6051 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6052 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6053 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6054 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6055 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6056 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6057 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6058 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6059 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6060 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6061 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6062 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6063 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6064 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6065 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6066 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6067 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6068 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6069
6070 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6071 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6072 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6073 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6074 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6075 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6076 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6077 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6078 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6079 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6080 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6081 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6082 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6083 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6084 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6085
6086 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6087 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6088 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6089 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6090 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6091 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6092 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6093 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6094 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6095 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6096 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6097 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6098 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6099 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6100 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6101 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6102 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6103 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6104 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6105 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6106 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6107 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6108 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6109 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6110 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6111 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6112 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6113 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6114
6115 /******************** Bit definition for DFSDM_FLTISR register *******************/
6116 #define DFSDM_FLTISR_SCDF_Pos (24U)
6117 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6118 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6119 #define DFSDM_FLTISR_CKABF_Pos (16U)
6120 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6121 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6122 #define DFSDM_FLTISR_RCIP_Pos (14U)
6123 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6124 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6125 #define DFSDM_FLTISR_JCIP_Pos (13U)
6126 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6127 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6128 #define DFSDM_FLTISR_AWDF_Pos (4U)
6129 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6130 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6131 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6132 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6133 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6134 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6135 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6136 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6137 #define DFSDM_FLTISR_REOCF_Pos (1U)
6138 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6139 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6140 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6141 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6142 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6143
6144 /******************** Bit definition for DFSDM_FLTICR register *******************/
6145 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6146 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6147 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6148 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6149 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6150 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6151 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6152 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6153 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6154 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6155 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6156 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6157
6158 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6159 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6160 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6161 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6162
6163 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6164 #define DFSDM_FLTFCR_FORD_Pos (29U)
6165 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6166 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6167 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6168 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6169 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6170 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6171 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6172 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6173 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6174 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6175 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6176
6177 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6178 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6179 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6180 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6181 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6182 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6183 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6184
6185 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6186 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6187 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6188 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6189 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6190 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6191 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6192 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6193 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6194 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6195
6196 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6197 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6198 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6199 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6200 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6201 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6202 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6203
6204 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6205 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6206 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6207 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6208 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6209 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6210 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6211
6212 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6213 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6214 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6215 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6216 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6217 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6218 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6219
6220 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6221 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6222 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6223 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6224 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6225 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6226 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6227
6228 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6229 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6230 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6231 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6232 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6233 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6234 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6235
6236 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6237 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6238 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6239 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6240 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6241 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6242 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6243
6244 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6245 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6246 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6247 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6248
6249 /******************************************************************************/
6250 /* */
6251 /* BDMA Controller */
6252 /* */
6253 /******************************************************************************/
6254
6255 /******************* Bit definition for BDMA_ISR register ********************/
6256 #define BDMA_ISR_GIF0_Pos (0U)
6257 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6258 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6259 #define BDMA_ISR_TCIF0_Pos (1U)
6260 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6261 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6262 #define BDMA_ISR_HTIF0_Pos (2U)
6263 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6264 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6265 #define BDMA_ISR_TEIF0_Pos (3U)
6266 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6267 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6268 #define BDMA_ISR_GIF1_Pos (4U)
6269 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6270 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6271 #define BDMA_ISR_TCIF1_Pos (5U)
6272 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6273 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6274 #define BDMA_ISR_HTIF1_Pos (6U)
6275 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6276 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6277 #define BDMA_ISR_TEIF1_Pos (7U)
6278 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6279 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6280 #define BDMA_ISR_GIF2_Pos (8U)
6281 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6282 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6283 #define BDMA_ISR_TCIF2_Pos (9U)
6284 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6285 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6286 #define BDMA_ISR_HTIF2_Pos (10U)
6287 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6288 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6289 #define BDMA_ISR_TEIF2_Pos (11U)
6290 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6291 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6292 #define BDMA_ISR_GIF3_Pos (12U)
6293 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6294 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6295 #define BDMA_ISR_TCIF3_Pos (13U)
6296 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6297 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6298 #define BDMA_ISR_HTIF3_Pos (14U)
6299 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6300 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6301 #define BDMA_ISR_TEIF3_Pos (15U)
6302 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6303 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6304 #define BDMA_ISR_GIF4_Pos (16U)
6305 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6306 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6307 #define BDMA_ISR_TCIF4_Pos (17U)
6308 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6309 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6310 #define BDMA_ISR_HTIF4_Pos (18U)
6311 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6312 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6313 #define BDMA_ISR_TEIF4_Pos (19U)
6314 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6315 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6316 #define BDMA_ISR_GIF5_Pos (20U)
6317 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6318 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6319 #define BDMA_ISR_TCIF5_Pos (21U)
6320 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6321 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6322 #define BDMA_ISR_HTIF5_Pos (22U)
6323 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6324 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6325 #define BDMA_ISR_TEIF5_Pos (23U)
6326 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6327 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6328 #define BDMA_ISR_GIF6_Pos (24U)
6329 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6330 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6331 #define BDMA_ISR_TCIF6_Pos (25U)
6332 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6333 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6334 #define BDMA_ISR_HTIF6_Pos (26U)
6335 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6336 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6337 #define BDMA_ISR_TEIF6_Pos (27U)
6338 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6339 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6340 #define BDMA_ISR_GIF7_Pos (28U)
6341 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6342 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6343 #define BDMA_ISR_TCIF7_Pos (29U)
6344 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6345 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6346 #define BDMA_ISR_HTIF7_Pos (30U)
6347 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6348 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6349 #define BDMA_ISR_TEIF7_Pos (31U)
6350 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6351 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6352
6353 /******************* Bit definition for BDMA_IFCR register *******************/
6354 #define BDMA_IFCR_CGIF0_Pos (0U)
6355 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6356 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6357 #define BDMA_IFCR_CTCIF0_Pos (1U)
6358 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6359 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6360 #define BDMA_IFCR_CHTIF0_Pos (2U)
6361 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6362 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6363 #define BDMA_IFCR_CTEIF0_Pos (3U)
6364 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6365 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6366 #define BDMA_IFCR_CGIF1_Pos (4U)
6367 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6368 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6369 #define BDMA_IFCR_CTCIF1_Pos (5U)
6370 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6371 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6372 #define BDMA_IFCR_CHTIF1_Pos (6U)
6373 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6374 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6375 #define BDMA_IFCR_CTEIF1_Pos (7U)
6376 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6377 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6378 #define BDMA_IFCR_CGIF2_Pos (8U)
6379 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6380 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6381 #define BDMA_IFCR_CTCIF2_Pos (9U)
6382 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6383 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6384 #define BDMA_IFCR_CHTIF2_Pos (10U)
6385 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6386 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6387 #define BDMA_IFCR_CTEIF2_Pos (11U)
6388 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6389 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6390 #define BDMA_IFCR_CGIF3_Pos (12U)
6391 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6392 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6393 #define BDMA_IFCR_CTCIF3_Pos (13U)
6394 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6395 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6396 #define BDMA_IFCR_CHTIF3_Pos (14U)
6397 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6398 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6399 #define BDMA_IFCR_CTEIF3_Pos (15U)
6400 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6401 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6402 #define BDMA_IFCR_CGIF4_Pos (16U)
6403 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6404 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6405 #define BDMA_IFCR_CTCIF4_Pos (17U)
6406 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6407 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6408 #define BDMA_IFCR_CHTIF4_Pos (18U)
6409 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6410 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6411 #define BDMA_IFCR_CTEIF4_Pos (19U)
6412 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6413 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6414 #define BDMA_IFCR_CGIF5_Pos (20U)
6415 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6416 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6417 #define BDMA_IFCR_CTCIF5_Pos (21U)
6418 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6419 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6420 #define BDMA_IFCR_CHTIF5_Pos (22U)
6421 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6422 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6423 #define BDMA_IFCR_CTEIF5_Pos (23U)
6424 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6425 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6426 #define BDMA_IFCR_CGIF6_Pos (24U)
6427 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6428 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6429 #define BDMA_IFCR_CTCIF6_Pos (25U)
6430 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6431 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6432 #define BDMA_IFCR_CHTIF6_Pos (26U)
6433 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6434 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6435 #define BDMA_IFCR_CTEIF6_Pos (27U)
6436 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6437 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6438 #define BDMA_IFCR_CGIF7_Pos (28U)
6439 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6440 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6441 #define BDMA_IFCR_CTCIF7_Pos (29U)
6442 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6443 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6444 #define BDMA_IFCR_CHTIF7_Pos (30U)
6445 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6446 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6447 #define BDMA_IFCR_CTEIF7_Pos (31U)
6448 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6449 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6450
6451 /******************* Bit definition for BDMA_CCR register ********************/
6452 #define BDMA_CCR_EN_Pos (0U)
6453 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6454 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6455 #define BDMA_CCR_TCIE_Pos (1U)
6456 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6457 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6458 #define BDMA_CCR_HTIE_Pos (2U)
6459 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6460 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6461 #define BDMA_CCR_TEIE_Pos (3U)
6462 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6463 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6464 #define BDMA_CCR_DIR_Pos (4U)
6465 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6466 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6467 #define BDMA_CCR_CIRC_Pos (5U)
6468 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6469 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6470 #define BDMA_CCR_PINC_Pos (6U)
6471 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6472 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6473 #define BDMA_CCR_MINC_Pos (7U)
6474 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6475 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6476
6477 #define BDMA_CCR_PSIZE_Pos (8U)
6478 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6479 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6480 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6481 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6482
6483 #define BDMA_CCR_MSIZE_Pos (10U)
6484 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6485 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6486 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6487 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6488
6489 #define BDMA_CCR_PL_Pos (12U)
6490 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6491 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6492 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6493 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6494
6495 #define BDMA_CCR_MEM2MEM_Pos (14U)
6496 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6497 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6498 #define BDMA_CCR_DBM_Pos (15U)
6499 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6500 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6501 #define BDMA_CCR_CT_Pos (16U)
6502 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6503 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6504
6505 /****************** Bit definition for BDMA_CNDTR register *******************/
6506 #define BDMA_CNDTR_NDT_Pos (0U)
6507 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6508 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6509
6510 /****************** Bit definition for BDMA_CPAR register ********************/
6511 #define BDMA_CPAR_PA_Pos (0U)
6512 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6513 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6514
6515 /****************** Bit definition for BDMA_CM0AR register ********************/
6516 #define BDMA_CM0AR_MA_Pos (0U)
6517 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6518 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6519
6520 /****************** Bit definition for BDMA_CM1AR register ********************/
6521 #define BDMA_CM1AR_MA_Pos (0U)
6522 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6523 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6524
6525 /******************************************************************************/
6526 /* */
6527 /* Ethernet MAC Registers bits definitions */
6528 /* */
6529 /******************************************************************************/
6530 /* Bit definition for Ethernet MAC Configuration Register register */
6531 #define ETH_MACCR_ARP_Pos (31U)
6532 #define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
6533 #define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6534 #define ETH_MACCR_SARC_Pos (28U)
6535 #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
6536 #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6537 #define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6538 #define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6539 #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
6540 #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6541 #define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6542 #define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
6543 #define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6544 #define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6545 #define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
6546 #define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6547 #define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6548 #define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
6549 #define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6550 #define ETH_MACCR_IPC_Pos (27U)
6551 #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
6552 #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6553 #define ETH_MACCR_IPG_Pos (24U)
6554 #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
6555 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6556 #define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
6557 #define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
6558 #define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
6559 #define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
6560 #define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
6561 #define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
6562 #define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
6563 #define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
6564 #define ETH_MACCR_GPSLCE_Pos (23U)
6565 #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
6566 #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6567 #define ETH_MACCR_S2KP_Pos (22U)
6568 #define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
6569 #define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6570 #define ETH_MACCR_CST_Pos (21U)
6571 #define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
6572 #define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6573 #define ETH_MACCR_ACS_Pos (20U)
6574 #define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
6575 #define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6576 #define ETH_MACCR_WD_Pos (19U)
6577 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
6578 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6579 #define ETH_MACCR_JD_Pos (17U)
6580 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
6581 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6582 #define ETH_MACCR_JE_Pos (16U)
6583 #define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
6584 #define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6585 #define ETH_MACCR_FES_Pos (14U)
6586 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
6587 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6588 #define ETH_MACCR_DM_Pos (13U)
6589 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
6590 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6591 #define ETH_MACCR_LM_Pos (12U)
6592 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
6593 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6594 #define ETH_MACCR_ECRSFD_Pos (11U)
6595 #define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
6596 #define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6597 #define ETH_MACCR_DO_Pos (10U)
6598 #define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
6599 #define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6600 #define ETH_MACCR_DCRS_Pos (9U)
6601 #define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
6602 #define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6603 #define ETH_MACCR_DR_Pos (8U)
6604 #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
6605 #define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6606 #define ETH_MACCR_BL_Pos (5U)
6607 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6608 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6609 #define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
6610 #define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
6611 #define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
6612 #define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6613 #define ETH_MACCR_DC_Pos (4U)
6614 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
6615 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6616 #define ETH_MACCR_PRELEN_Pos (2U)
6617 #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
6618 #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6619 #define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
6620 #define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
6621 #define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
6622 #define ETH_MACCR_TE_Pos (1U)
6623 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
6624 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6625 #define ETH_MACCR_RE_Pos (0U)
6626 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
6627 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6628
6629 /* Bit definition for Ethernet MAC Extended Configuration Register register */
6630 #define ETH_MACECR_EIPG_Pos (25U)
6631 #define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
6632 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6633 #define ETH_MACECR_EIPGEN_Pos (24U)
6634 #define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
6635 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6636 #define ETH_MACECR_USP_Pos (18U)
6637 #define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
6638 #define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6639 #define ETH_MACECR_SPEN_Pos (17U)
6640 #define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
6641 #define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6642 #define ETH_MACECR_DCRCC_Pos (16U)
6643 #define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
6644 #define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6645 #define ETH_MACECR_GPSL_Pos (0U)
6646 #define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
6647 #define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6648
6649 /* Bit definition for Ethernet MAC Packet Filter Register */
6650 #define ETH_MACPFR_RA_Pos (31U)
6651 #define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
6652 #define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6653 #define ETH_MACPFR_DNTU_Pos (21U)
6654 #define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
6655 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6656 #define ETH_MACPFR_IPFE_Pos (20U)
6657 #define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
6658 #define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6659 #define ETH_MACPFR_VTFE_Pos (16U)
6660 #define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
6661 #define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6662 #define ETH_MACPFR_HPF_Pos (10U)
6663 #define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
6664 #define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6665 #define ETH_MACPFR_SAF_Pos (9U)
6666 #define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
6667 #define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6668 #define ETH_MACPFR_SAIF_Pos (8U)
6669 #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
6670 #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6671 #define ETH_MACPFR_PCF_Pos (6U)
6672 #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
6673 #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6674 #define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
6675 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6676 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
6677 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6678 #define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6679 #define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
6680 #define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6681 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6682 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
6683 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6684 #define ETH_MACPFR_DBF_Pos (5U)
6685 #define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
6686 #define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6687 #define ETH_MACPFR_PM_Pos (4U)
6688 #define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
6689 #define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
6690 #define ETH_MACPFR_DAIF_Pos (3U)
6691 #define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
6692 #define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
6693 #define ETH_MACPFR_HMC_Pos (2U)
6694 #define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
6695 #define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
6696 #define ETH_MACPFR_HUC_Pos (1U)
6697 #define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
6698 #define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
6699 #define ETH_MACPFR_PR_Pos (0U)
6700 #define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
6701 #define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
6702
6703 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
6704 #define ETH_MACWTR_PWE_Pos (8U)
6705 #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
6706 #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
6707 #define ETH_MACWTR_WTO_Pos (0U)
6708 #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
6709 #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
6710 #define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
6711 #define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
6712 #define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
6713 #define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
6714 #define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
6715 #define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
6716 #define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
6717 #define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
6718 #define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
6719 #define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
6720 #define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
6721 #define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
6722 #define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
6723 #define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
6724 #define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
6725
6726 /* Bit definition for Ethernet MAC Hash Table High Register */
6727 #define ETH_MACHTHR_HTH_Pos (0U)
6728 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
6729 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
6730
6731 /* Bit definition for Ethernet MAC Hash Table Low Register */
6732 #define ETH_MACHTLR_HTL_Pos (0U)
6733 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
6734 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
6735
6736 /* Bit definition for Ethernet MAC VLAN Tag Register */
6737 #define ETH_MACVTR_EIVLRXS_Pos (31U)
6738 #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
6739 #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
6740 #define ETH_MACVTR_EIVLS_Pos (28U)
6741 #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
6742 #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
6743 #define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
6744 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
6745 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
6746 #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6747 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
6748 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
6749 #define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6750 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
6751 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
6752 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
6753 #define ETH_MACVTR_ERIVLT_Pos (27U)
6754 #define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
6755 #define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
6756 #define ETH_MACVTR_EDVLP_Pos (26U)
6757 #define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
6758 #define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
6759 #define ETH_MACVTR_VTHM_Pos (25U)
6760 #define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
6761 #define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
6762 #define ETH_MACVTR_EVLRXS_Pos (24U)
6763 #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
6764 #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
6765 #define ETH_MACVTR_EVLS_Pos (21U)
6766 #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
6767 #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
6768 #define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
6769 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
6770 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
6771 #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
6772 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
6773 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
6774 #define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
6775 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
6776 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
6777 #define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
6778 #define ETH_MACVTR_DOVLTC_Pos (20U)
6779 #define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
6780 #define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
6781 #define ETH_MACVTR_ERSVLM_Pos (19U)
6782 #define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
6783 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
6784 #define ETH_MACVTR_ESVL_Pos (18U)
6785 #define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
6786 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
6787 #define ETH_MACVTR_VTIM_Pos (17U)
6788 #define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
6789 #define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
6790 #define ETH_MACVTR_ETV_Pos (16U)
6791 #define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
6792 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
6793 #define ETH_MACVTR_VL_Pos (0U)
6794 #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
6795 #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
6796 #define ETH_MACVTR_VL_UP_Pos (13U)
6797 #define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
6798 #define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
6799 #define ETH_MACVTR_VL_CFIDEI_Pos (12U)
6800 #define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
6801 #define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6802 #define ETH_MACVTR_VL_VID_Pos (0U)
6803 #define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
6804 #define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
6805
6806 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
6807 #define ETH_MACVHTR_VLHT_Pos (0U)
6808 #define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
6809 #define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
6810
6811 /* Bit definition for Ethernet MAC VLAN Incl Register */
6812 #define ETH_MACVIR_VLTI_Pos (20U)
6813 #define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
6814 #define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
6815 #define ETH_MACVIR_CSVL_Pos (19U)
6816 #define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
6817 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6818 #define ETH_MACVIR_VLP_Pos (18U)
6819 #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
6820 #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
6821 #define ETH_MACVIR_VLC_Pos (16U)
6822 #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
6823 #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6824 #define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
6825 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
6826 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6827 #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6828 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
6829 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6830 #define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6831 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
6832 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6833 #define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6834 #define ETH_MACVIR_VLT_Pos (0U)
6835 #define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
6836 #define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6837 #define ETH_MACVIR_VLT_UP_Pos (13U)
6838 #define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6839 #define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
6840 #define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
6841 #define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6842 #define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6843 #define ETH_MACVIR_VLT_VID_Pos (0U)
6844 #define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6845 #define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6846
6847 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
6848 #define ETH_MACIVIR_VLTI_Pos (20U)
6849 #define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
6850 #define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
6851 #define ETH_MACIVIR_CSVL_Pos (19U)
6852 #define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
6853 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
6854 #define ETH_MACIVIR_VLP_Pos (18U)
6855 #define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
6856 #define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
6857 #define ETH_MACIVIR_VLC_Pos (16U)
6858 #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
6859 #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
6860 #define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
6861 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
6862 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
6863 #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
6864 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
6865 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
6866 #define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
6867 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
6868 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
6869 #define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
6870 #define ETH_MACIVIR_VLT_Pos (0U)
6871 #define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
6872 #define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
6873 #define ETH_MACIVIR_VLT_UP_Pos (13U)
6874 #define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
6875 #define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
6876 #define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
6877 #define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
6878 #define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
6879 #define ETH_MACIVIR_VLT_VID_Pos (0U)
6880 #define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
6881 #define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
6882
6883 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
6884 #define ETH_MACTFCR_PT_Pos (16U)
6885 #define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
6886 #define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
6887 #define ETH_MACTFCR_DZPQ_Pos (7U)
6888 #define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
6889 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
6890 #define ETH_MACTFCR_PLT_Pos (4U)
6891 #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
6892 #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
6893 #define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
6894 #define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
6895 #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
6896 #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
6897 #define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
6898 #define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
6899 #define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
6900 #define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
6901 #define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
6902 #define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
6903 #define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
6904 #define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
6905 #define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
6906 #define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
6907 #define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
6908 #define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
6909 #define ETH_MACTFCR_TFE_Pos (1U)
6910 #define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
6911 #define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
6912 #define ETH_MACTFCR_FCB_Pos (0U)
6913 #define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
6914 #define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
6915
6916 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
6917 #define ETH_MACRFCR_UP_Pos (1U)
6918 #define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
6919 #define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
6920 #define ETH_MACRFCR_RFE_Pos (0U)
6921 #define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
6922 #define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
6923
6924 /* Bit definition for Ethernet MAC Interrupt Status Register */
6925 #define ETH_MACISR_RXSTSIS_Pos (14U)
6926 #define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
6927 #define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
6928 #define ETH_MACISR_TXSTSIS_Pos (13U)
6929 #define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
6930 #define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
6931 #define ETH_MACISR_TSIS_Pos (12U)
6932 #define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
6933 #define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
6934 #define ETH_MACISR_MMCTXIS_Pos (10U)
6935 #define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
6936 #define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
6937 #define ETH_MACISR_MMCRXIS_Pos (9U)
6938 #define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
6939 #define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
6940 #define ETH_MACISR_MMCIS_Pos (8U)
6941 #define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
6942 #define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
6943 #define ETH_MACISR_LPIIS_Pos (5U)
6944 #define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
6945 #define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
6946 #define ETH_MACISR_PMTIS_Pos (4U)
6947 #define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
6948 #define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
6949 #define ETH_MACISR_PHYIS_Pos (3U)
6950 #define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
6951 #define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
6952
6953 /* Bit definition for Ethernet MAC Interrupt Enable Register */
6954 #define ETH_MACIER_RXSTSIE_Pos (14U)
6955 #define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
6956 #define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
6957 #define ETH_MACIER_TXSTSIE_Pos (13U)
6958 #define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
6959 #define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
6960 #define ETH_MACIER_TSIE_Pos (12U)
6961 #define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
6962 #define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
6963 #define ETH_MACIER_LPIIE_Pos (5U)
6964 #define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
6965 #define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
6966 #define ETH_MACIER_PMTIE_Pos (4U)
6967 #define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
6968 #define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
6969 #define ETH_MACIER_PHYIE_Pos (3U)
6970 #define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
6971 #define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
6972
6973 /* Bit definition for Ethernet MAC Rx Tx Status Register */
6974 #define ETH_MACRXTXSR_RWT_Pos (8U)
6975 #define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
6976 #define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
6977 #define ETH_MACRXTXSR_EXCOL_Pos (5U)
6978 #define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
6979 #define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
6980 #define ETH_MACRXTXSR_LCOL_Pos (4U)
6981 #define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
6982 #define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
6983 #define ETH_MACRXTXSR_EXDEF_Pos (3U)
6984 #define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
6985 #define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
6986 #define ETH_MACRXTXSR_LCARR_Pos (2U)
6987 #define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
6988 #define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
6989 #define ETH_MACRXTXSR_NCARR_Pos (1U)
6990 #define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
6991 #define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
6992 #define ETH_MACRXTXSR_TJT_Pos (0U)
6993 #define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
6994 #define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
6995
6996 /* Bit definition for Ethernet MAC PMT Control Status Register */
6997 #define ETH_MACPCSR_RWKFILTRST_Pos (31U)
6998 #define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
6999 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7000 #define ETH_MACPCSR_RWKPTR_Pos (24U)
7001 #define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
7002 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7003 #define ETH_MACPCSR_RWKPFE_Pos (10U)
7004 #define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
7005 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7006 #define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7007 #define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
7008 #define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7009 #define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7010 #define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
7011 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7012 #define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7013 #define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
7014 #define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7015 #define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7016 #define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
7017 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7018 #define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7019 #define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
7020 #define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7021 #define ETH_MACPCSR_PWRDWN_Pos (0U)
7022 #define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
7023 #define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7024
7025 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7026 #define ETH_MACRWUPFR_D_Pos (0U)
7027 #define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
7028 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7029
7030 /* Bit definition for Ethernet MAC LPI Control Status Register */
7031 #define ETH_MACLCSR_LPITCSE_Pos (21U)
7032 #define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
7033 #define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7034 #define ETH_MACLCSR_LPITE_Pos (20U)
7035 #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
7036 #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7037 #define ETH_MACLCSR_LPITXA_Pos (19U)
7038 #define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
7039 #define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7040 #define ETH_MACLCSR_PLS_Pos (17U)
7041 #define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
7042 #define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7043 #define ETH_MACLCSR_LPIEN_Pos (16U)
7044 #define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
7045 #define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7046 #define ETH_MACLCSR_RLPIST_Pos (9U)
7047 #define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
7048 #define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7049 #define ETH_MACLCSR_TLPIST_Pos (8U)
7050 #define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
7051 #define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7052 #define ETH_MACLCSR_RLPIEX_Pos (3U)
7053 #define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
7054 #define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7055 #define ETH_MACLCSR_RLPIEN_Pos (2U)
7056 #define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
7057 #define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7058 #define ETH_MACLCSR_TLPIEX_Pos (1U)
7059 #define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
7060 #define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7061 #define ETH_MACLCSR_TLPIEN_Pos (0U)
7062 #define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
7063 #define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7064
7065 /* Bit definition for Ethernet MAC LPI Timers Control Register */
7066 #define ETH_MACLTCR_LST_Pos (16U)
7067 #define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
7068 #define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7069 #define ETH_MACLTCR_TWT_Pos (0U)
7070 #define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
7071 #define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7072
7073 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
7074 #define ETH_MACLETR_LPIET_Pos (0U)
7075 #define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
7076 #define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7077
7078 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
7079 #define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7080 #define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
7081 #define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7082
7083 /* Bit definition for Ethernet MAC Version Register */
7084 #define ETH_MACVR_USERVER_Pos (8U)
7085 #define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
7086 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7087 #define ETH_MACVR_SNPSVER_Pos (0U)
7088 #define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
7089 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7090
7091 /* Bit definition for Ethernet MAC Debug Register */
7092 #define ETH_MACDR_TFCSTS_Pos (17U)
7093 #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
7094 #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7095 #define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7096 #define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7097 #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
7098 #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7099 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7100 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
7101 #define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7102 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7103 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
7104 #define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7105 #define ETH_MACDR_TPESTS_Pos (16U)
7106 #define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
7107 #define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7108 #define ETH_MACDR_RFCFCSTS_Pos (1U)
7109 #define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
7110 #define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7111 #define ETH_MACDR_RPESTS_Pos (0U)
7112 #define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
7113 #define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7114
7115 /* Bit definition for Ethernet MAC HW Feature0 Register */
7116 #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7117 #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
7118 #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7119 #define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
7120 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7121 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
7122 #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7123 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7124 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
7125 #define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7126 #define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7127 #define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
7128 #define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7129 #define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7130 #define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
7131 #define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7132 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7133 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
7134 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7135 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7136 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
7137 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7138 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7139 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
7140 #define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7141 #define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7142 #define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
7143 #define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7144 #define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7145 #define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
7146 #define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7147 #define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7148 #define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
7149 #define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7150 #define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7151 #define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
7152 #define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7153 #define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7154 #define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
7155 #define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7156 #define ETH_MACHWF0R_EEESEL_Pos (13U)
7157 #define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
7158 #define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7159 #define ETH_MACHWF0R_TSSEL_Pos (12U)
7160 #define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
7161 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7162 #define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7163 #define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
7164 #define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7165 #define ETH_MACHWF0R_MMCSEL_Pos (8U)
7166 #define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
7167 #define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7168 #define ETH_MACHWF0R_MGKSEL_Pos (7U)
7169 #define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
7170 #define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7171 #define ETH_MACHWF0R_RWKSEL_Pos (6U)
7172 #define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
7173 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7174 #define ETH_MACHWF0R_SMASEL_Pos (5U)
7175 #define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
7176 #define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7177 #define ETH_MACHWF0R_VLHASH_Pos (4U)
7178 #define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
7179 #define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7180 #define ETH_MACHWF0R_PCSSEL_Pos (3U)
7181 #define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
7182 #define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7183 #define ETH_MACHWF0R_HDSEL_Pos (2U)
7184 #define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
7185 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7186 #define ETH_MACHWF0R_GMIISEL_Pos (1U)
7187 #define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
7188 #define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7189 #define ETH_MACHWF0R_MIISEL_Pos (0U)
7190 #define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
7191 #define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7192
7193 /* Bit definition for Ethernet MAC HW Feature1 Register */
7194 #define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7195 #define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
7196 #define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7197 #define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7198 #define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
7199 #define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7200 #define ETH_MACHWF1R_AVSEL_Pos (20U)
7201 #define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
7202 #define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7203 #define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7204 #define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
7205 #define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7206 #define ETH_MACHWF1R_TSOEN_Pos (18U)
7207 #define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
7208 #define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7209 #define ETH_MACHWF1R_SPHEN_Pos (17U)
7210 #define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
7211 #define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7212 #define ETH_MACHWF1R_DCBEN_Pos (16U)
7213 #define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
7214 #define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7215 #define ETH_MACHWF1R_ADDR64_Pos (14U)
7216 #define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
7217 #define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7218 #define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
7219 #define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
7220 #define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
7221 #define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7222 #define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
7223 #define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7224 #define ETH_MACHWF1R_PTOEN_Pos (12U)
7225 #define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
7226 #define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7227 #define ETH_MACHWF1R_OSTEN_Pos (11U)
7228 #define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
7229 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7230 #define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7231 #define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
7232 #define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7233 #define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7234 #define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
7235 #define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7236
7237 /* Bit definition for Ethernet MAC HW Feature2 Register */
7238 #define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7239 #define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
7240 #define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7241 #define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7242 #define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
7243 #define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7244 #define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7245 #define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
7246 #define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7247 #define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7248 #define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
7249 #define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7250 #define ETH_MACHWF2R_TXQCNT_Pos (6U)
7251 #define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
7252 #define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7253 #define ETH_MACHWF2R_RXQCNT_Pos (0U)
7254 #define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
7255 #define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7256
7257 /* Bit definition for Ethernet MAC MDIO Address Register */
7258 #define ETH_MACMDIOAR_PSE_Pos (27U)
7259 #define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
7260 #define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7261 #define ETH_MACMDIOAR_BTB_Pos (26U)
7262 #define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
7263 #define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7264 #define ETH_MACMDIOAR_PA_Pos (21U)
7265 #define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
7266 #define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7267 #define ETH_MACMDIOAR_RDA_Pos (16U)
7268 #define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
7269 #define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7270 #define ETH_MACMDIOAR_NTC_Pos (12U)
7271 #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
7272 #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7273 #define ETH_MACMDIOAR_CR_Pos (8U)
7274 #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
7275 #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7276 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
7277 #define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7278 #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
7279 #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7280 #define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7281 #define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
7282 #define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7283 #define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7284 #define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
7285 #define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7286 #define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7287 #define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
7288 #define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7289 #define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7290 #define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
7291 #define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7292 #define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7293 #define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
7294 #define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7295 #define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7296 #define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
7297 #define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7298 #define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7299 #define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
7300 #define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7301 #define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7302 #define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
7303 #define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7304 #define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7305 #define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
7306 #define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7307 #define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7308 #define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
7309 #define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7310 #define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7311 #define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
7312 #define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7313 #define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7314 #define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
7315 #define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7316 #define ETH_MACMDIOAR_SKAP_Pos (4U)
7317 #define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
7318 #define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7319 #define ETH_MACMDIOAR_MOC_Pos (2U)
7320 #define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
7321 #define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7322 #define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7323 #define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
7324 #define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7325 #define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7326 #define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
7327 #define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7328 #define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7329 #define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
7330 #define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7331 #define ETH_MACMDIOAR_C45E_Pos (1U)
7332 #define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
7333 #define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7334 #define ETH_MACMDIOAR_MB_Pos (0U)
7335 #define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
7336 #define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7337
7338 /* Bit definition for Ethernet MAC MDIO Data Register */
7339 #define ETH_MACMDIODR_RA_Pos (16U)
7340 #define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
7341 #define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7342 #define ETH_MACMDIODR_MD_Pos (0U)
7343 #define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
7344 #define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7345
7346 /* Bit definition for Ethernet ARP Address Register */
7347 #define ETH_MACARPAR_ARPPA_Pos (0U)
7348 #define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
7349 #define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7350
7351 /* Bit definition for Ethernet MAC Address 0 High Register */
7352 #define ETH_MACA0HR_AE_Pos (31U)
7353 #define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
7354 #define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7355 #define ETH_MACA0HR_ADDRHI_Pos (0U)
7356 #define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7357 #define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7358
7359 /* Bit definition for Ethernet MAC Address 0 Low Register */
7360 #define ETH_MACA0LR_ADDRLO_Pos (0U)
7361 #define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7362 #define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7363
7364 /* Bit definition for Ethernet MAC Address 1 High Register */
7365 #define ETH_MACA1HR_AE_Pos (31U)
7366 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
7367 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7368 #define ETH_MACA1HR_SA_Pos (30U)
7369 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
7370 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7371 #define ETH_MACA1HR_MBC_Pos (24U)
7372 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
7373 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7374 #define ETH_MACA1HR_ADDRHI_Pos (0U)
7375 #define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7376 #define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7377
7378 /* Bit definition for Ethernet MAC Address 1 Low Register */
7379 #define ETH_MACA1LR_ADDRLO_Pos (0U)
7380 #define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7381 #define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7382
7383 /* Bit definition for Ethernet MAC Address 2 High Register */
7384 #define ETH_MACA2HR_AE_Pos (31U)
7385 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
7386 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7387 #define ETH_MACA2HR_SA_Pos (30U)
7388 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
7389 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7390 #define ETH_MACA2HR_MBC_Pos (24U)
7391 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
7392 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7393 #define ETH_MACA2HR_ADDRHI_Pos (0U)
7394 #define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7395 #define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7396
7397 /* Bit definition for Ethernet MAC Address 2 Low Register */
7398 #define ETH_MACA2LR_ADDRLO_Pos (0U)
7399 #define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7400 #define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7401
7402 /* Bit definition for Ethernet MAC Address 3 High Register */
7403 #define ETH_MACA3HR_AE_Pos (31U)
7404 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
7405 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7406 #define ETH_MACA3HR_SA_Pos (30U)
7407 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
7408 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7409 #define ETH_MACA3HR_MBC_Pos (24U)
7410 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
7411 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7412 #define ETH_MACA3HR_ADDRHI_Pos (0U)
7413 #define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7414 #define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7415
7416 /* Bit definition for Ethernet MAC Address 3 Low Register */
7417 #define ETH_MACA3LR_ADDRLO_Pos (0U)
7418 #define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7419 #define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7420
7421 /* Bit definition for Ethernet MAC Address High Register */
7422 #define ETH_MACAHR_AE_Pos (31U)
7423 #define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
7424 #define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7425 #define ETH_MACAHR_SA_Pos (30U)
7426 #define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
7427 #define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7428 #define ETH_MACAHR_MBC_Pos (24U)
7429 #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
7430 #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7431 #define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7432 #define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7433 #define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7434 #define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7435 #define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7436 #define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7437 #define ETH_MACAHR_MACAH_Pos (0U)
7438 #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
7439 #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7440
7441 /* Bit definition for Ethernet MAC Address Low Register */
7442 #define ETH_MACALR_MACAL_Pos (0U)
7443 #define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
7444 #define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7445
7446 /* Bit definition for Ethernet MMC Control Register */
7447 #define ETH_MMCCR_UCDBC_Pos (8U)
7448 #define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
7449 #define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7450 #define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7451 #define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
7452 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7453 #define ETH_MMCCR_CNTPRST_Pos (4U)
7454 #define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
7455 #define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7456 #define ETH_MMCCR_CNTFREEZ_Pos (3U)
7457 #define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
7458 #define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7459 #define ETH_MMCCR_RSTONRD_Pos (2U)
7460 #define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
7461 #define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7462 #define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7463 #define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
7464 #define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7465 #define ETH_MMCCR_CNTRST_Pos (0U)
7466 #define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
7467 #define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7468
7469 /* Bit definition for Ethernet MMC Rx Interrupt Register */
7470 #define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7471 #define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
7472 #define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7473 #define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7474 #define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
7475 #define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7476 #define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7477 #define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
7478 #define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7479 #define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7480 #define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
7481 #define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7482 #define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7483 #define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
7484 #define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7485
7486 /* Bit definition for Ethernet MMC Tx Interrupt Register */
7487 #define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7488 #define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
7489 #define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7490 #define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7491 #define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
7492 #define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7493 #define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7494 #define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
7495 #define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7496 #define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7497 #define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
7498 #define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7499 #define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7500 #define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
7501 #define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7502
7503 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
7504 #define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7505 #define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
7506 #define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7507 #define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7508 #define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
7509 #define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7510 #define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7511 #define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
7512 #define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7513 #define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7514 #define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
7515 #define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7516 #define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7517 #define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
7518 #define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7519
7520 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7521 #define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7522 #define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
7523 #define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7524 #define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7525 #define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
7526 #define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7527 #define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7528 #define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
7529 #define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7530 #define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7531 #define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
7532 #define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7533 #define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7534 #define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
7535 #define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7536
7537 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7538 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7539 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
7540 #define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7541
7542 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7543 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7544 #define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
7545 #define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7546
7547 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7548 #define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7549 #define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
7550 #define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7551
7552 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7553 #define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7554 #define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
7555 #define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7556
7557 /* Bit definition for Ethernet MMC Rx alignment error packets register */
7558 #define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7559 #define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
7560 #define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7561
7562 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7563 #define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7564 #define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
7565 #define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7566
7567 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7568 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7569 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7570 #define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7571
7572 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7573 #define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7574 #define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
7575 #define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7576
7577 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7578 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7579 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7580 #define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7581
7582 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7583 #define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7584 #define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
7585 #define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7586
7587 /* Bit definition for Ethernet MAC L3 L4 Control Register */
7588 #define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7589 #define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
7590 #define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7591 #define ETH_MACL3L4CR_L4DPM_Pos (20U)
7592 #define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
7593 #define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7594 #define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7595 #define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
7596 #define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7597 #define ETH_MACL3L4CR_L4SPM_Pos (18U)
7598 #define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
7599 #define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7600 #define ETH_MACL3L4CR_L4PEN_Pos (16U)
7601 #define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
7602 #define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7603 #define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7604 #define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
7605 #define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7606 #define ETH_MACL3L4CR_L3HSBM_Pos (6U)
7607 #define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
7608 #define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7609 #define ETH_MACL3L4CR_L3DAIM_Pos (5U)
7610 #define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
7611 #define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7612 #define ETH_MACL3L4CR_L3DAM_Pos (4U)
7613 #define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
7614 #define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
7615 #define ETH_MACL3L4CR_L3SAIM_Pos (3U)
7616 #define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
7617 #define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7618 #define ETH_MACL3L4CR_L3SAM_Pos (2U)
7619 #define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
7620 #define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
7621 #define ETH_MACL3L4CR_L3PEN_Pos (0U)
7622 #define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
7623 #define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
7624
7625 /* Bit definition for Ethernet MAC L4 Address Register */
7626 #define ETH_MACL4AR_L4DP_Pos (16U)
7627 #define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
7628 #define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
7629 #define ETH_MACL4AR_L4SP_Pos (0U)
7630 #define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
7631 #define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
7632
7633 /* Bit definition for Ethernet MAC L3 Address0 Register */
7634 #define ETH_MACL3A0R_L3A0_Pos (0U)
7635 #define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
7636 #define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
7637
7638 /* Bit definition for Ethernet MAC L4 Address1 Register */
7639 #define ETH_MACL3A1R_L3A1_Pos (0U)
7640 #define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
7641 #define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
7642
7643 /* Bit definition for Ethernet MAC L4 Address2 Register */
7644 #define ETH_MACL3A2R_L3A2_Pos (0U)
7645 #define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
7646 #define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
7647
7648 /* Bit definition for Ethernet MAC L4 Address3 Register */
7649 #define ETH_MACL3A3R_L3A3_Pos (0U)
7650 #define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
7651 #define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
7652
7653 /* Bit definition for Ethernet MAC Timestamp Control Register */
7654 #define ETH_MACTSCR_TXTSSTSM_Pos (24U)
7655 #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
7656 #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
7657 #define ETH_MACTSCR_CSC_Pos (19U)
7658 #define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
7659 #define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7660 #define ETH_MACTSCR_TSENMACADDR_Pos (18U)
7661 #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
7662 #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
7663 #define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
7664 #define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
7665 #define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
7666 #define ETH_MACTSCR_TSMSTRENA_Pos (15U)
7667 #define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
7668 #define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
7669 #define ETH_MACTSCR_TSEVNTENA_Pos (14U)
7670 #define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
7671 #define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
7672 #define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
7673 #define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
7674 #define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7675 #define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
7676 #define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
7677 #define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7678 #define ETH_MACTSCR_TSIPENA_Pos (11U)
7679 #define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
7680 #define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
7681 #define ETH_MACTSCR_TSVER2ENA_Pos (10U)
7682 #define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
7683 #define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
7684 #define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
7685 #define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
7686 #define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
7687 #define ETH_MACTSCR_TSENALL_Pos (8U)
7688 #define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
7689 #define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
7690 #define ETH_MACTSCR_TSADDREG_Pos (5U)
7691 #define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
7692 #define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
7693 #define ETH_MACTSCR_TSUPDT_Pos (3U)
7694 #define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
7695 #define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
7696 #define ETH_MACTSCR_TSINIT_Pos (2U)
7697 #define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
7698 #define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
7699 #define ETH_MACTSCR_TSCFUPDT_Pos (1U)
7700 #define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
7701 #define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
7702 #define ETH_MACTSCR_TSENA_Pos (0U)
7703 #define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
7704 #define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
7705
7706 /* Bit definition for Ethernet MAC Sub-second Increment Register */
7707 #define ETH_MACMACSSIR_SSINC_Pos (16U)
7708 #define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
7709 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
7710 #define ETH_MACMACSSIR_SNSINC_Pos (8U)
7711 #define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
7712 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
7713
7714 /* Bit definition for Ethernet MAC System Time Seconds Register */
7715 #define ETH_MACSTSR_TSS_Pos (0U)
7716 #define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
7717 #define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
7718
7719 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
7720 #define ETH_MACSTNR_TSSS_Pos (0U)
7721 #define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
7722 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
7723
7724 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
7725 #define ETH_MACSTSUR_TSS_Pos (0U)
7726 #define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
7727 #define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
7728
7729 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
7730 #define ETH_MACSTNUR_ADDSUB_Pos (31U)
7731 #define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
7732 #define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
7733 #define ETH_MACSTNUR_TSSS_Pos (0U)
7734 #define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
7735 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
7736
7737 /* Bit definition for Ethernet MAC Timestamp Addend Register */
7738 #define ETH_MACTSAR_TSAR_Pos (0U)
7739 #define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
7740 #define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
7741
7742 /* Bit definition for Ethernet MAC Timestamp Status Register */
7743 #define ETH_MACTSSR_ATSNS_Pos (25U)
7744 #define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
7745 #define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
7746 #define ETH_MACTSSR_ATSSTM_Pos (24U)
7747 #define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
7748 #define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
7749 #define ETH_MACTSSR_ATSSTN_Pos (16U)
7750 #define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
7751 #define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
7752 #define ETH_MACTSSR_TXTSSIS_Pos (15U)
7753 #define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
7754 #define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
7755 #define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
7756 #define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
7757 #define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
7758 #define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
7759 #define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
7760 #define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
7761 #define ETH_MACTSSR_TSTARGT0_Pos (1U)
7762 #define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
7763 #define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
7764 #define ETH_MACTSSR_TSSOVF_Pos (0U)
7765 #define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
7766 #define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
7767
7768 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
7769 #define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
7770 #define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
7771 #define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
7772 #define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
7773 #define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
7774 #define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
7775
7776 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
7777 #define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
7778 #define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
7779 #define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
7780
7781 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
7782 #define ETH_MACACR_ATSEN3_Pos (7U)
7783 #define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
7784 #define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
7785 #define ETH_MACACR_ATSEN2_Pos (6U)
7786 #define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
7787 #define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
7788 #define ETH_MACACR_ATSEN1_Pos (5U)
7789 #define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
7790 #define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
7791 #define ETH_MACACR_ATSEN0_Pos (4U)
7792 #define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
7793 #define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
7794 #define ETH_MACACR_ATSFC_Pos (0U)
7795 #define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
7796 #define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
7797
7798 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
7799 #define ETH_MACATSNR_AUXTSLO_Pos (0U)
7800 #define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
7801 #define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
7802
7803 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
7804 #define ETH_MACATSSR_AUXTSHI_Pos (0U)
7805 #define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
7806 #define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
7807
7808 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
7809 #define ETH_MACTSIACR_OSTIAC_Pos (0U)
7810 #define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
7811 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
7812
7813 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
7814 #define ETH_MACTSEACR_OSTEAC_Pos (0U)
7815 #define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
7816 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
7817
7818 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
7819 #define ETH_MACTSICNR_TSIC_Pos (0U)
7820 #define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
7821 #define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
7822
7823 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
7824 #define ETH_MACTSECNR_TSEC_Pos (0U)
7825 #define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
7826 #define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
7827
7828 /* Bit definition for Ethernet MAC PPS Control Register */
7829 #define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
7830 #define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
7831 #define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
7832 #define ETH_MACPPSCR_PPSEN0_Pos (4U)
7833 #define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
7834 #define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
7835 #define ETH_MACPPSCR_PPSCTRL_Pos (0U)
7836 #define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
7837 #define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
7838
7839 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
7840 #define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
7841 #define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
7842 #define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
7843
7844 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
7845 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
7846 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
7847 #define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
7848 #define ETH_MACPPSTTNR_TTSL0_Pos (0U)
7849 #define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
7850 #define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
7851
7852 /* Bit definition for Ethernet MAC PPS Interval Register */
7853 #define ETH_MACPPSIR_PPSINT0_Pos (0U)
7854 #define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
7855 #define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
7856
7857 /* Bit definition for Ethernet MAC PPS Width Register */
7858 #define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
7859 #define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
7860 #define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
7861
7862 /* Bit definition for Ethernet MAC PTP Offload Control Register */
7863 #define ETH_MACPOCR_DN_Pos (8U)
7864 #define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
7865 #define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
7866 #define ETH_MACPOCR_DRRDIS_Pos (6U)
7867 #define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
7868 #define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
7869 #define ETH_MACPOCR_APDREQTRIG_Pos (5U)
7870 #define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
7871 #define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
7872 #define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
7873 #define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
7874 #define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
7875 #define ETH_MACPOCR_APDREQEN_Pos (2U)
7876 #define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
7877 #define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
7878 #define ETH_MACPOCR_ASYNCEN_Pos (1U)
7879 #define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
7880 #define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
7881 #define ETH_MACPOCR_PTOEN_Pos (0U)
7882 #define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
7883 #define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
7884
7885 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
7886 #define ETH_MACSPI0R_SPI0_Pos (0U)
7887 #define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
7888 #define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
7889
7890 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
7891 #define ETH_MACSPI1R_SPI1_Pos (0U)
7892 #define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
7893 #define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
7894
7895 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
7896 #define ETH_MACSPI2R_SPI2_Pos (0U)
7897 #define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
7898 #define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
7899
7900 /* Bit definition for Ethernet MAC Log Message Interval Register */
7901 #define ETH_MACLMIR_LMPDRI_Pos (24U)
7902 #define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
7903 #define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
7904 #define ETH_MACLMIR_DRSYNCR_Pos (8U)
7905 #define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
7906 #define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
7907 #define ETH_MACLMIR_LSI_Pos (0U)
7908 #define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
7909 #define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
7910
7911 /* Bit definition for Ethernet MTL Operation Mode Register */
7912 #define ETH_MTLOMR_CNTCLR_Pos (9U)
7913 #define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
7914 #define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
7915 #define ETH_MTLOMR_CNTPRST_Pos (8U)
7916 #define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
7917 #define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
7918 #define ETH_MTLOMR_DTXSTS_Pos (1U)
7919 #define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
7920 #define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
7921
7922 /* Bit definition for Ethernet MTL Interrupt Status Register */
7923 #define ETH_MTLISR_MACIS_Pos (16U)
7924 #define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
7925 #define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
7926 #define ETH_MTLISR_QIS_Pos (0U)
7927 #define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
7928 #define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
7929
7930 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
7931 #define ETH_MTLTQOMR_TTC_Pos (4U)
7932 #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
7933 #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
7934 #define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
7935 #define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
7936 #define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
7937 #define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
7938 #define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
7939 #define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
7940 #define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
7941 #define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
7942 #define ETH_MTLTQOMR_TSF_Pos (1U)
7943 #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
7944 #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
7945 #define ETH_MTLTQOMR_FTQ_Pos (0U)
7946 #define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
7947 #define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
7948
7949 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
7950 #define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
7951 #define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
7952 #define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
7953 #define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
7954 #define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
7955 #define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
7956
7957 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
7958 #define ETH_MTLTQDR_STXSTSF_Pos (20U)
7959 #define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
7960 #define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
7961 #define ETH_MTLTQDR_PTXQ_Pos (16U)
7962 #define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
7963 #define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
7964 #define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
7965 #define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
7966 #define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
7967 #define ETH_MTLTQDR_TXQSTS_Pos (4U)
7968 #define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
7969 #define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
7970 #define ETH_MTLTQDR_TWCSTS_Pos (3U)
7971 #define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
7972 #define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
7973 #define ETH_MTLTQDR_TRCSTS_Pos (1U)
7974 #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
7975 #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
7976 #define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7977 #define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
7978 #define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
7979 #define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
7980 #define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
7981 #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
7982 #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
7983
7984 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
7985 #define ETH_MTLQICSR_RXOIE_Pos (24U)
7986 #define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
7987 #define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
7988 #define ETH_MTLQICSR_RXOVFIS_Pos (16U)
7989 #define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
7990 #define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
7991 #define ETH_MTLQICSR_TXUIE_Pos (8U)
7992 #define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
7993 #define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
7994 #define ETH_MTLQICSR_TXUNFIS_Pos (0U)
7995 #define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
7996 #define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
7997
7998 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
7999 #define ETH_MTLRQOMR_RQS_Pos (20U)
8000 #define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
8001 #define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8002 #define ETH_MTLRQOMR_RFD_Pos (14U)
8003 #define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
8004 #define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8005 #define ETH_MTLRQOMR_RFA_Pos (8U)
8006 #define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
8007 #define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8008 #define ETH_MTLRQOMR_EHFC_Pos (7U)
8009 #define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
8010 #define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8011 #define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8012 #define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
8013 #define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8014 #define ETH_MTLRQOMR_RSF_Pos (5U)
8015 #define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
8016 #define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8017 #define ETH_MTLRQOMR_FEP_Pos (4U)
8018 #define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
8019 #define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8020 #define ETH_MTLRQOMR_FUP_Pos (3U)
8021 #define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
8022 #define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8023 #define ETH_MTLRQOMR_RTC_Pos (0U)
8024 #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
8025 #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8026 #define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
8027 #define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
8028 #define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
8029 #define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
8030
8031 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8032 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8033 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
8034 #define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8035 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8036 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
8037 #define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8038 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8039 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
8040 #define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8041 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8042 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
8043 #define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8044
8045 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
8046 #define ETH_MTLRQDR_PRXQ_Pos (16U)
8047 #define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
8048 #define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8049 #define ETH_MTLRQDR_RXQSTS_Pos (4U)
8050 #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
8051 #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8052 #define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
8053 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8054 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
8055 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8056 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8057 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
8058 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8059 #define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8060 #define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
8061 #define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8062 #define ETH_MTLRQDR_RRCSTS_Pos (1U)
8063 #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
8064 #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8065 #define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8066 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8067 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
8068 #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8069 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8070 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
8071 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8072 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8073 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
8074 #define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8075 #define ETH_MTLRQDR_RWCSTS_Pos (0U)
8076 #define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
8077 #define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8078
8079 /* Bit definition for Ethernet MTL Rx Queue Control Register */
8080 #define ETH_MTLRQCR_RQPA_Pos (3U)
8081 #define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
8082 #define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8083 #define ETH_MTLRQCR_RQW_Pos (0U)
8084 #define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
8085 #define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8086
8087 /* Bit definition for Ethernet DMA Mode Register */
8088 #define ETH_DMAMR_INTM_Pos (16U)
8089 #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
8090 #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8091 #define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
8092 #define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
8093 #define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
8094 #define ETH_DMAMR_PR_Pos (12U)
8095 #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
8096 #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8097 #define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
8098 #define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
8099 #define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
8100 #define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
8101 #define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
8102 #define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
8103 #define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
8104 #define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
8105 #define ETH_DMAMR_TXPR_Pos (11U)
8106 #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
8107 #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8108 #define ETH_DMAMR_DA_Pos (1U)
8109 #define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
8110 #define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8111 #define ETH_DMAMR_SWR_Pos (0U)
8112 #define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
8113 #define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8114
8115 /* Bit definition for Ethernet DMA SysBus Mode Register */
8116 #define ETH_DMASBMR_RB_Pos (15U)
8117 #define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
8118 #define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8119 #define ETH_DMASBMR_MB_Pos (14U)
8120 #define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
8121 #define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8122 #define ETH_DMASBMR_AAL_Pos (12U)
8123 #define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
8124 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8125 #define ETH_DMASBMR_FB_Pos (0U)
8126 #define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
8127 #define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8128
8129 /* Bit definition for Ethernet DMA Interrupt Status Register */
8130 #define ETH_DMAISR_MACIS_Pos (17U)
8131 #define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
8132 #define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8133 #define ETH_DMAISR_MTLIS_Pos (16U)
8134 #define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
8135 #define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8136 #define ETH_DMAISR_DMACIS_Pos (0U)
8137 #define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
8138 #define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8139
8140 /* Bit definition for Ethernet DMA Debug Status Register */
8141 #define ETH_DMADSR_TPS_Pos (12U)
8142 #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
8143 #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8144 #define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
8145 #define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8146 #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
8147 #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8148 #define ETH_DMADSR_TPS_WAITING_Pos (13U)
8149 #define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
8150 #define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8151 #define ETH_DMADSR_TPS_READING_Pos (12U)
8152 #define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
8153 #define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8154 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8155 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
8156 #define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8157 #define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8158 #define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
8159 #define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8160 #define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8161 #define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
8162 #define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8163 #define ETH_DMADSR_RPS_Pos (8U)
8164 #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
8165 #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8166 #define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
8167 #define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8168 #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
8169 #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8170 #define ETH_DMADSR_RPS_WAITING_Pos (12U)
8171 #define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
8172 #define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8173 #define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8174 #define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
8175 #define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8176 #define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8177 #define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
8178 #define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8179 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8180 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
8181 #define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8182 #define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8183 #define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
8184 #define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8185
8186 /* Bit definition for Ethernet DMA Channel Control Register */
8187 #define ETH_DMACCR_DSL_Pos (18U)
8188 #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
8189 #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8190 #define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
8191 #define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
8192 #define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
8193 #define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
8194 #define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
8195 #define ETH_DMACCR_MSS_Pos (0U)
8196 #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
8197 #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8198
8199 /* Bit definition for Ethernet DMA Channel Tx Control Register */
8200 #define ETH_DMACTCR_TPBL_Pos (16U)
8201 #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
8202 #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8203 #define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
8204 #define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
8205 #define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
8206 #define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
8207 #define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
8208 #define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
8209 #define ETH_DMACTCR_TSE_Pos (12U)
8210 #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
8211 #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8212 #define ETH_DMACTCR_OSP_Pos (4U)
8213 #define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
8214 #define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8215 #define ETH_DMACTCR_ST_Pos (0U)
8216 #define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
8217 #define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8218
8219 /* Bit definition for Ethernet DMA Channel Rx Control Register */
8220 #define ETH_DMACRCR_RPF_Pos (31U)
8221 #define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
8222 #define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8223 #define ETH_DMACRCR_RPBL_Pos (16U)
8224 #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
8225 #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8226 #define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
8227 #define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
8228 #define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
8229 #define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
8230 #define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
8231 #define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
8232 #define ETH_DMACRCR_RBSZ_Pos (1U)
8233 #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
8234 #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8235 #define ETH_DMACRCR_SR_Pos (0U)
8236 #define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
8237 #define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8238
8239 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8240 #define ETH_DMACTDLAR_TDESLA_Pos (2U)
8241 #define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
8242 #define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8243
8244 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8245 #define ETH_DMACRDLAR_RDESLA_Pos (2U)
8246 #define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
8247 #define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8248
8249 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8250 #define ETH_DMACTDTPR_TDT_Pos (2U)
8251 #define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
8252 #define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8253
8254 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8255 #define ETH_DMACRDTPR_RDT_Pos (2U)
8256 #define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
8257 #define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8258
8259 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8260 #define ETH_DMACTDRLR_TDRL_Pos (0U)
8261 #define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
8262 #define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8263
8264 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8265 #define ETH_DMACRDRLR_RDRL_Pos (0U)
8266 #define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
8267 #define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8268
8269 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8270 #define ETH_DMACIER_NIE_Pos (15U)
8271 #define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
8272 #define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8273 #define ETH_DMACIER_AIE_Pos (14U)
8274 #define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
8275 #define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8276 #define ETH_DMACIER_CDEE_Pos (13U)
8277 #define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
8278 #define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8279 #define ETH_DMACIER_FBEE_Pos (12U)
8280 #define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
8281 #define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8282 #define ETH_DMACIER_ERIE_Pos (11U)
8283 #define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
8284 #define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8285 #define ETH_DMACIER_ETIE_Pos (10U)
8286 #define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
8287 #define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8288 #define ETH_DMACIER_RWTE_Pos (9U)
8289 #define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
8290 #define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8291 #define ETH_DMACIER_RSE_Pos (8U)
8292 #define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
8293 #define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8294 #define ETH_DMACIER_RBUE_Pos (7U)
8295 #define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
8296 #define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8297 #define ETH_DMACIER_RIE_Pos (6U)
8298 #define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
8299 #define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8300 #define ETH_DMACIER_TBUE_Pos (2U)
8301 #define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
8302 #define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8303 #define ETH_DMACIER_TXSE_Pos (1U)
8304 #define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
8305 #define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8306 #define ETH_DMACIER_TIE_Pos (0U)
8307 #define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
8308 #define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8309
8310 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8311 #define ETH_DMACRIWTR_RWT_Pos (0U)
8312 #define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
8313 #define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8314
8315 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8316 #define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8317 #define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
8318 #define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8319
8320 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8321 #define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8322 #define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
8323 #define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8324
8325 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8326 #define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8327 #define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8328 #define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8329
8330 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8331 #define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8332 #define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8333 #define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8334
8335 /* Bit definition for Ethernet DMA Channel Status Register */
8336 #define ETH_DMACSR_REB_Pos (19U)
8337 #define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
8338 #define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8339 #define ETH_DMACSR_TEB_Pos (16U)
8340 #define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
8341 #define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8342 #define ETH_DMACSR_NIS_Pos (15U)
8343 #define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
8344 #define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8345 #define ETH_DMACSR_AIS_Pos (14U)
8346 #define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
8347 #define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8348 #define ETH_DMACSR_CDE_Pos (13U)
8349 #define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
8350 #define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8351 #define ETH_DMACSR_FBE_Pos (12U)
8352 #define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
8353 #define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8354 #define ETH_DMACSR_ERI_Pos (11U)
8355 #define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
8356 #define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8357 #define ETH_DMACSR_ETI_Pos (10U)
8358 #define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
8359 #define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8360 #define ETH_DMACSR_RWT_Pos (9U)
8361 #define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
8362 #define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8363 #define ETH_DMACSR_RPS_Pos (8U)
8364 #define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
8365 #define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8366 #define ETH_DMACSR_RBU_Pos (7U)
8367 #define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
8368 #define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8369 #define ETH_DMACSR_RI_Pos (6U)
8370 #define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
8371 #define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8372 #define ETH_DMACSR_TBU_Pos (2U)
8373 #define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
8374 #define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8375 #define ETH_DMACSR_TPS_Pos (1U)
8376 #define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
8377 #define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8378 #define ETH_DMACSR_TI_Pos (0U)
8379 #define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
8380 #define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8381
8382 /* Bit definition for Ethernet DMA Channel missed frame count register */
8383 #define ETH_DMACMFCR_MFCO_Pos (15U)
8384 #define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
8385 #define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8386 #define ETH_DMACMFCR_MFC_Pos (0U)
8387 #define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
8388 #define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8389
8390 /******************************************************************************/
8391 /* */
8392 /* DMA Controller */
8393 /* */
8394 /******************************************************************************/
8395 /******************** Bits definition for DMA_SxCR register *****************/
8396 #define DMA_SxCR_MBURST_Pos (23U)
8397 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
8398 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
8399 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
8400 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
8401 #define DMA_SxCR_PBURST_Pos (21U)
8402 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
8403 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
8404 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
8405 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8406 #define DMA_SxCR_CT_Pos (19U)
8407 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
8408 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
8409 #define DMA_SxCR_DBM_Pos (18U)
8410 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
8411 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
8412 #define DMA_SxCR_PL_Pos (16U)
8413 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
8414 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
8415 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
8416 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
8417 #define DMA_SxCR_PINCOS_Pos (15U)
8418 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
8419 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
8420 #define DMA_SxCR_MSIZE_Pos (13U)
8421 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
8422 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
8423 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
8424 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
8425 #define DMA_SxCR_PSIZE_Pos (11U)
8426 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
8427 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8428 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
8429 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
8430 #define DMA_SxCR_MINC_Pos (10U)
8431 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
8432 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
8433 #define DMA_SxCR_PINC_Pos (9U)
8434 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
8435 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
8436 #define DMA_SxCR_CIRC_Pos (8U)
8437 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
8438 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
8439 #define DMA_SxCR_DIR_Pos (6U)
8440 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
8441 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
8442 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
8443 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
8444 #define DMA_SxCR_PFCTRL_Pos (5U)
8445 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
8446 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
8447 #define DMA_SxCR_TCIE_Pos (4U)
8448 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
8449 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
8450 #define DMA_SxCR_HTIE_Pos (3U)
8451 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
8452 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
8453 #define DMA_SxCR_TEIE_Pos (2U)
8454 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
8455 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
8456 #define DMA_SxCR_DMEIE_Pos (1U)
8457 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
8458 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
8459 #define DMA_SxCR_EN_Pos (0U)
8460 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
8461 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
8462
8463 /******************** Bits definition for DMA_SxCNDTR register **************/
8464 #define DMA_SxNDT_Pos (0U)
8465 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
8466 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
8467 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
8468 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
8469 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
8470 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
8471 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
8472 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
8473 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
8474 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
8475 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
8476 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
8477 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
8478 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
8479 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
8480 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
8481 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
8482 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
8483
8484 /******************** Bits definition for DMA_SxFCR register ****************/
8485 #define DMA_SxFCR_FEIE_Pos (7U)
8486 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
8487 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
8488 #define DMA_SxFCR_FS_Pos (3U)
8489 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
8490 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
8491 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
8492 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
8493 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
8494 #define DMA_SxFCR_DMDIS_Pos (2U)
8495 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
8496 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
8497 #define DMA_SxFCR_FTH_Pos (0U)
8498 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
8499 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
8500 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
8501 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
8502
8503 /******************** Bits definition for DMA_LISR register *****************/
8504 #define DMA_LISR_TCIF3_Pos (27U)
8505 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
8506 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
8507 #define DMA_LISR_HTIF3_Pos (26U)
8508 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
8509 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
8510 #define DMA_LISR_TEIF3_Pos (25U)
8511 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
8512 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
8513 #define DMA_LISR_DMEIF3_Pos (24U)
8514 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
8515 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
8516 #define DMA_LISR_FEIF3_Pos (22U)
8517 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
8518 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
8519 #define DMA_LISR_TCIF2_Pos (21U)
8520 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
8521 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
8522 #define DMA_LISR_HTIF2_Pos (20U)
8523 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
8524 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
8525 #define DMA_LISR_TEIF2_Pos (19U)
8526 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
8527 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
8528 #define DMA_LISR_DMEIF2_Pos (18U)
8529 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
8530 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
8531 #define DMA_LISR_FEIF2_Pos (16U)
8532 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
8533 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
8534 #define DMA_LISR_TCIF1_Pos (11U)
8535 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
8536 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
8537 #define DMA_LISR_HTIF1_Pos (10U)
8538 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
8539 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
8540 #define DMA_LISR_TEIF1_Pos (9U)
8541 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
8542 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
8543 #define DMA_LISR_DMEIF1_Pos (8U)
8544 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
8545 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
8546 #define DMA_LISR_FEIF1_Pos (6U)
8547 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
8548 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
8549 #define DMA_LISR_TCIF0_Pos (5U)
8550 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
8551 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
8552 #define DMA_LISR_HTIF0_Pos (4U)
8553 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
8554 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
8555 #define DMA_LISR_TEIF0_Pos (3U)
8556 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
8557 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
8558 #define DMA_LISR_DMEIF0_Pos (2U)
8559 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
8560 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
8561 #define DMA_LISR_FEIF0_Pos (0U)
8562 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
8563 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
8564
8565 /******************** Bits definition for DMA_HISR register *****************/
8566 #define DMA_HISR_TCIF7_Pos (27U)
8567 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
8568 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
8569 #define DMA_HISR_HTIF7_Pos (26U)
8570 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
8571 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
8572 #define DMA_HISR_TEIF7_Pos (25U)
8573 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
8574 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
8575 #define DMA_HISR_DMEIF7_Pos (24U)
8576 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
8577 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
8578 #define DMA_HISR_FEIF7_Pos (22U)
8579 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
8580 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
8581 #define DMA_HISR_TCIF6_Pos (21U)
8582 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
8583 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
8584 #define DMA_HISR_HTIF6_Pos (20U)
8585 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
8586 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
8587 #define DMA_HISR_TEIF6_Pos (19U)
8588 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
8589 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
8590 #define DMA_HISR_DMEIF6_Pos (18U)
8591 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
8592 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
8593 #define DMA_HISR_FEIF6_Pos (16U)
8594 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
8595 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
8596 #define DMA_HISR_TCIF5_Pos (11U)
8597 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
8598 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
8599 #define DMA_HISR_HTIF5_Pos (10U)
8600 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
8601 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
8602 #define DMA_HISR_TEIF5_Pos (9U)
8603 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
8604 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
8605 #define DMA_HISR_DMEIF5_Pos (8U)
8606 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
8607 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
8608 #define DMA_HISR_FEIF5_Pos (6U)
8609 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
8610 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
8611 #define DMA_HISR_TCIF4_Pos (5U)
8612 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
8613 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
8614 #define DMA_HISR_HTIF4_Pos (4U)
8615 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
8616 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
8617 #define DMA_HISR_TEIF4_Pos (3U)
8618 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
8619 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
8620 #define DMA_HISR_DMEIF4_Pos (2U)
8621 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
8622 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
8623 #define DMA_HISR_FEIF4_Pos (0U)
8624 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
8625 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
8626
8627 /******************** Bits definition for DMA_LIFCR register ****************/
8628 #define DMA_LIFCR_CTCIF3_Pos (27U)
8629 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
8630 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
8631 #define DMA_LIFCR_CHTIF3_Pos (26U)
8632 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
8633 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
8634 #define DMA_LIFCR_CTEIF3_Pos (25U)
8635 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
8636 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
8637 #define DMA_LIFCR_CDMEIF3_Pos (24U)
8638 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
8639 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
8640 #define DMA_LIFCR_CFEIF3_Pos (22U)
8641 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
8642 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
8643 #define DMA_LIFCR_CTCIF2_Pos (21U)
8644 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
8645 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
8646 #define DMA_LIFCR_CHTIF2_Pos (20U)
8647 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
8648 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
8649 #define DMA_LIFCR_CTEIF2_Pos (19U)
8650 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
8651 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
8652 #define DMA_LIFCR_CDMEIF2_Pos (18U)
8653 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
8654 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
8655 #define DMA_LIFCR_CFEIF2_Pos (16U)
8656 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
8657 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
8658 #define DMA_LIFCR_CTCIF1_Pos (11U)
8659 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
8660 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
8661 #define DMA_LIFCR_CHTIF1_Pos (10U)
8662 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
8663 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
8664 #define DMA_LIFCR_CTEIF1_Pos (9U)
8665 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
8666 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
8667 #define DMA_LIFCR_CDMEIF1_Pos (8U)
8668 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
8669 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
8670 #define DMA_LIFCR_CFEIF1_Pos (6U)
8671 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
8672 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
8673 #define DMA_LIFCR_CTCIF0_Pos (5U)
8674 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
8675 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
8676 #define DMA_LIFCR_CHTIF0_Pos (4U)
8677 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
8678 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
8679 #define DMA_LIFCR_CTEIF0_Pos (3U)
8680 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
8681 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
8682 #define DMA_LIFCR_CDMEIF0_Pos (2U)
8683 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
8684 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
8685 #define DMA_LIFCR_CFEIF0_Pos (0U)
8686 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
8687 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
8688
8689 /******************** Bits definition for DMA_HIFCR register ****************/
8690 #define DMA_HIFCR_CTCIF7_Pos (27U)
8691 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
8692 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
8693 #define DMA_HIFCR_CHTIF7_Pos (26U)
8694 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
8695 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
8696 #define DMA_HIFCR_CTEIF7_Pos (25U)
8697 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
8698 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
8699 #define DMA_HIFCR_CDMEIF7_Pos (24U)
8700 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
8701 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
8702 #define DMA_HIFCR_CFEIF7_Pos (22U)
8703 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
8704 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
8705 #define DMA_HIFCR_CTCIF6_Pos (21U)
8706 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
8707 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
8708 #define DMA_HIFCR_CHTIF6_Pos (20U)
8709 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
8710 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
8711 #define DMA_HIFCR_CTEIF6_Pos (19U)
8712 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
8713 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
8714 #define DMA_HIFCR_CDMEIF6_Pos (18U)
8715 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
8716 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
8717 #define DMA_HIFCR_CFEIF6_Pos (16U)
8718 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
8719 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
8720 #define DMA_HIFCR_CTCIF5_Pos (11U)
8721 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
8722 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
8723 #define DMA_HIFCR_CHTIF5_Pos (10U)
8724 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
8725 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
8726 #define DMA_HIFCR_CTEIF5_Pos (9U)
8727 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
8728 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
8729 #define DMA_HIFCR_CDMEIF5_Pos (8U)
8730 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
8731 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
8732 #define DMA_HIFCR_CFEIF5_Pos (6U)
8733 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
8734 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
8735 #define DMA_HIFCR_CTCIF4_Pos (5U)
8736 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
8737 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
8738 #define DMA_HIFCR_CHTIF4_Pos (4U)
8739 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
8740 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
8741 #define DMA_HIFCR_CTEIF4_Pos (3U)
8742 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
8743 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
8744 #define DMA_HIFCR_CDMEIF4_Pos (2U)
8745 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
8746 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
8747 #define DMA_HIFCR_CFEIF4_Pos (0U)
8748 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
8749 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
8750
8751 /****************** Bit definition for DMA_SxPAR register ********************/
8752 #define DMA_SxPAR_PA_Pos (0U)
8753 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
8754 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
8755
8756 /****************** Bit definition for DMA_SxM0AR register ********************/
8757 #define DMA_SxM0AR_M0A_Pos (0U)
8758 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
8759 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
8760
8761 /****************** Bit definition for DMA_SxM1AR register ********************/
8762 #define DMA_SxM1AR_M1A_Pos (0U)
8763 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
8764 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
8765
8766 /******************************************************************************/
8767 /* */
8768 /* DMAMUX Controller */
8769 /* */
8770 /******************************************************************************/
8771 /******************** Bits definition for DMAMUX_CxCR register **************/
8772 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
8773 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
8774 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
8775 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
8776 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
8777 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
8778 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
8779 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
8780 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
8781 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
8782 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
8783 #define DMAMUX_CxCR_SOIE_Pos (8U)
8784 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
8785 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
8786 #define DMAMUX_CxCR_EGE_Pos (9U)
8787 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
8788 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
8789 #define DMAMUX_CxCR_SE_Pos (16U)
8790 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
8791 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
8792 #define DMAMUX_CxCR_SPOL_Pos (17U)
8793 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
8794 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
8795 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
8796 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
8797 #define DMAMUX_CxCR_NBREQ_Pos (19U)
8798 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
8799 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
8800 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
8801 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
8802 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
8803 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
8804 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
8805 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
8806 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
8807 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
8808 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
8809 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
8810 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
8811 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
8812 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
8813
8814 /******************** Bits definition for DMAMUX_CSR register **************/
8815 #define DMAMUX_CSR_SOF0_Pos (0U)
8816 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
8817 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
8818 #define DMAMUX_CSR_SOF1_Pos (1U)
8819 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
8820 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
8821 #define DMAMUX_CSR_SOF2_Pos (2U)
8822 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
8823 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
8824 #define DMAMUX_CSR_SOF3_Pos (3U)
8825 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
8826 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
8827 #define DMAMUX_CSR_SOF4_Pos (4U)
8828 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
8829 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
8830 #define DMAMUX_CSR_SOF5_Pos (5U)
8831 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
8832 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
8833 #define DMAMUX_CSR_SOF6_Pos (6U)
8834 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
8835 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
8836 #define DMAMUX_CSR_SOF7_Pos (7U)
8837 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
8838 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
8839 #define DMAMUX_CSR_SOF8_Pos (8U)
8840 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
8841 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
8842 #define DMAMUX_CSR_SOF9_Pos (9U)
8843 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
8844 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
8845 #define DMAMUX_CSR_SOF10_Pos (10U)
8846 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
8847 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
8848 #define DMAMUX_CSR_SOF11_Pos (11U)
8849 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
8850 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
8851 #define DMAMUX_CSR_SOF12_Pos (12U)
8852 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
8853 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
8854 #define DMAMUX_CSR_SOF13_Pos (13U)
8855 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
8856 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
8857 #define DMAMUX_CSR_SOF14_Pos (14U)
8858 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
8859 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
8860 #define DMAMUX_CSR_SOF15_Pos (15U)
8861 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
8862 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
8863
8864 /******************** Bits definition for DMAMUX_CFR register **************/
8865 #define DMAMUX_CFR_CSOF0_Pos (0U)
8866 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
8867 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
8868 #define DMAMUX_CFR_CSOF1_Pos (1U)
8869 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
8870 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
8871 #define DMAMUX_CFR_CSOF2_Pos (2U)
8872 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
8873 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
8874 #define DMAMUX_CFR_CSOF3_Pos (3U)
8875 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
8876 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
8877 #define DMAMUX_CFR_CSOF4_Pos (4U)
8878 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
8879 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
8880 #define DMAMUX_CFR_CSOF5_Pos (5U)
8881 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
8882 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
8883 #define DMAMUX_CFR_CSOF6_Pos (6U)
8884 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
8885 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
8886 #define DMAMUX_CFR_CSOF7_Pos (7U)
8887 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
8888 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
8889 #define DMAMUX_CFR_CSOF8_Pos (8U)
8890 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
8891 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
8892 #define DMAMUX_CFR_CSOF9_Pos (9U)
8893 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
8894 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
8895 #define DMAMUX_CFR_CSOF10_Pos (10U)
8896 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
8897 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
8898 #define DMAMUX_CFR_CSOF11_Pos (11U)
8899 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
8900 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
8901 #define DMAMUX_CFR_CSOF12_Pos (12U)
8902 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
8903 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
8904 #define DMAMUX_CFR_CSOF13_Pos (13U)
8905 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
8906 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
8907 #define DMAMUX_CFR_CSOF14_Pos (14U)
8908 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
8909 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
8910 #define DMAMUX_CFR_CSOF15_Pos (15U)
8911 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
8912 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
8913
8914 /******************** Bits definition for DMAMUX_RGxCR register ************/
8915 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
8916 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
8917 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
8918 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
8919 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
8920 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
8921 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
8922 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
8923 #define DMAMUX_RGxCR_OIE_Pos (8U)
8924 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
8925 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
8926 #define DMAMUX_RGxCR_GE_Pos (16U)
8927 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
8928 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
8929 #define DMAMUX_RGxCR_GPOL_Pos (17U)
8930 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
8931 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
8932 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
8933 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
8934 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
8935 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
8936 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
8937 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
8938 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
8939 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
8940 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
8941 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
8942
8943 /******************** Bits definition for DMAMUX_RGSR register **************/
8944 #define DMAMUX_RGSR_OF0_Pos (0U)
8945 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
8946 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
8947 #define DMAMUX_RGSR_OF1_Pos (1U)
8948 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
8949 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
8950 #define DMAMUX_RGSR_OF2_Pos (2U)
8951 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
8952 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
8953 #define DMAMUX_RGSR_OF3_Pos (3U)
8954 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
8955 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
8956 #define DMAMUX_RGSR_OF4_Pos (4U)
8957 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
8958 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
8959 #define DMAMUX_RGSR_OF5_Pos (5U)
8960 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
8961 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
8962 #define DMAMUX_RGSR_OF6_Pos (6U)
8963 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
8964 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
8965 #define DMAMUX_RGSR_OF7_Pos (7U)
8966 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
8967 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
8968
8969 /******************** Bits definition for DMAMUX_RGCFR register **************/
8970 #define DMAMUX_RGCFR_COF0_Pos (0U)
8971 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
8972 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
8973 #define DMAMUX_RGCFR_COF1_Pos (1U)
8974 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
8975 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
8976 #define DMAMUX_RGCFR_COF2_Pos (2U)
8977 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
8978 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
8979 #define DMAMUX_RGCFR_COF3_Pos (3U)
8980 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
8981 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
8982 #define DMAMUX_RGCFR_COF4_Pos (4U)
8983 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
8984 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
8985 #define DMAMUX_RGCFR_COF5_Pos (5U)
8986 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
8987 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
8988 #define DMAMUX_RGCFR_COF6_Pos (6U)
8989 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
8990 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
8991 #define DMAMUX_RGCFR_COF7_Pos (7U)
8992 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
8993 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
8994
8995 /******************************************************************************/
8996 /* */
8997 /* AHB Master DMA2D Controller (DMA2D) */
8998 /* */
8999 /******************************************************************************/
9000
9001 /******************** Bit definition for DMA2D_CR register ******************/
9002
9003 #define DMA2D_CR_START_Pos (0U)
9004 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
9005 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
9006 #define DMA2D_CR_SUSP_Pos (1U)
9007 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
9008 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
9009 #define DMA2D_CR_ABORT_Pos (2U)
9010 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
9011 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
9012 #define DMA2D_CR_LOM_Pos (6U)
9013 #define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
9014 #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
9015 #define DMA2D_CR_TEIE_Pos (8U)
9016 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
9017 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
9018 #define DMA2D_CR_TCIE_Pos (9U)
9019 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
9020 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
9021 #define DMA2D_CR_TWIE_Pos (10U)
9022 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
9023 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
9024 #define DMA2D_CR_CAEIE_Pos (11U)
9025 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
9026 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
9027 #define DMA2D_CR_CTCIE_Pos (12U)
9028 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
9029 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
9030 #define DMA2D_CR_CEIE_Pos (13U)
9031 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
9032 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
9033 #define DMA2D_CR_MODE_Pos (16U)
9034 #define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
9035 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
9036 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
9037 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
9038 #define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
9039
9040 /******************** Bit definition for DMA2D_ISR register *****************/
9041
9042 #define DMA2D_ISR_TEIF_Pos (0U)
9043 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
9044 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
9045 #define DMA2D_ISR_TCIF_Pos (1U)
9046 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
9047 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
9048 #define DMA2D_ISR_TWIF_Pos (2U)
9049 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
9050 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
9051 #define DMA2D_ISR_CAEIF_Pos (3U)
9052 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
9053 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
9054 #define DMA2D_ISR_CTCIF_Pos (4U)
9055 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
9056 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
9057 #define DMA2D_ISR_CEIF_Pos (5U)
9058 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
9059 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
9060
9061 /******************** Bit definition for DMA2D_IFCR register ****************/
9062
9063 #define DMA2D_IFCR_CTEIF_Pos (0U)
9064 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
9065 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
9066 #define DMA2D_IFCR_CTCIF_Pos (1U)
9067 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
9068 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
9069 #define DMA2D_IFCR_CTWIF_Pos (2U)
9070 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
9071 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
9072 #define DMA2D_IFCR_CAECIF_Pos (3U)
9073 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
9074 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
9075 #define DMA2D_IFCR_CCTCIF_Pos (4U)
9076 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
9077 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
9078 #define DMA2D_IFCR_CCEIF_Pos (5U)
9079 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
9080 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
9081
9082 /******************** Bit definition for DMA2D_FGMAR register ***************/
9083
9084 #define DMA2D_FGMAR_MA_Pos (0U)
9085 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9086 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
9087
9088 /******************** Bit definition for DMA2D_FGOR register ****************/
9089
9090 #define DMA2D_FGOR_LO_Pos (0U)
9091 #define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
9092 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
9093
9094 /******************** Bit definition for DMA2D_BGMAR register ***************/
9095
9096 #define DMA2D_BGMAR_MA_Pos (0U)
9097 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9098 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
9099
9100 /******************** Bit definition for DMA2D_BGOR register ****************/
9101
9102 #define DMA2D_BGOR_LO_Pos (0U)
9103 #define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
9104 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
9105
9106 /******************** Bit definition for DMA2D_FGPFCCR register *************/
9107
9108 #define DMA2D_FGPFCCR_CM_Pos (0U)
9109 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
9110 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9111 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
9112 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
9113 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
9114 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
9115 #define DMA2D_FGPFCCR_CCM_Pos (4U)
9116 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
9117 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
9118 #define DMA2D_FGPFCCR_START_Pos (5U)
9119 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
9120 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
9121 #define DMA2D_FGPFCCR_CS_Pos (8U)
9122 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9123 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
9124 #define DMA2D_FGPFCCR_AM_Pos (16U)
9125 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
9126 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9127 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
9128 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
9129 #define DMA2D_FGPFCCR_CSS_Pos (18U)
9130 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
9131 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9132 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
9133 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
9134 #define DMA2D_FGPFCCR_AI_Pos (20U)
9135 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
9136 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
9137 #define DMA2D_FGPFCCR_RBS_Pos (21U)
9138 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
9139 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
9140 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9141 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9142 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
9143
9144 /******************** Bit definition for DMA2D_FGCOLR register **************/
9145
9146 #define DMA2D_FGCOLR_BLUE_Pos (0U)
9147 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
9148 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
9149 #define DMA2D_FGCOLR_GREEN_Pos (8U)
9150 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9151 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
9152 #define DMA2D_FGCOLR_RED_Pos (16U)
9153 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
9154 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
9155
9156 /******************** Bit definition for DMA2D_BGPFCCR register *************/
9157
9158 #define DMA2D_BGPFCCR_CM_Pos (0U)
9159 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
9160 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9161 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
9162 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
9163 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
9164 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
9165 #define DMA2D_BGPFCCR_CCM_Pos (4U)
9166 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
9167 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
9168 #define DMA2D_BGPFCCR_START_Pos (5U)
9169 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
9170 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
9171 #define DMA2D_BGPFCCR_CS_Pos (8U)
9172 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9173 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
9174 #define DMA2D_BGPFCCR_AM_Pos (16U)
9175 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
9176 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9177 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
9178 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
9179 #define DMA2D_BGPFCCR_AI_Pos (20U)
9180 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
9181 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
9182 #define DMA2D_BGPFCCR_RBS_Pos (21U)
9183 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
9184 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
9185 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9186 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9187 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
9188
9189 /******************** Bit definition for DMA2D_BGCOLR register **************/
9190
9191 #define DMA2D_BGCOLR_BLUE_Pos (0U)
9192 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
9193 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
9194 #define DMA2D_BGCOLR_GREEN_Pos (8U)
9195 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9196 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
9197 #define DMA2D_BGCOLR_RED_Pos (16U)
9198 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
9199 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
9200
9201 /******************** Bit definition for DMA2D_FGCMAR register **************/
9202
9203 #define DMA2D_FGCMAR_MA_Pos (0U)
9204 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9205 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
9206
9207 /******************** Bit definition for DMA2D_BGCMAR register **************/
9208
9209 #define DMA2D_BGCMAR_MA_Pos (0U)
9210 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9211 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
9212
9213 /******************** Bit definition for DMA2D_OPFCCR register **************/
9214
9215 #define DMA2D_OPFCCR_CM_Pos (0U)
9216 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
9217 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
9218 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
9219 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
9220 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
9221 #define DMA2D_OPFCCR_SB_Pos (8U)
9222 #define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
9223 #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
9224 #define DMA2D_OPFCCR_AI_Pos (20U)
9225 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
9226 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
9227 #define DMA2D_OPFCCR_RBS_Pos (21U)
9228 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
9229 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
9230
9231 /******************** Bit definition for DMA2D_OCOLR register ***************/
9232
9233 /*!<Mode_ARGB8888/RGB888 */
9234
9235 #define DMA2D_OCOLR_BLUE_1_Pos (0U)
9236 #define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9237 #define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
9238 #define DMA2D_OCOLR_GREEN_1_Pos (8U)
9239 #define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9240 #define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
9241 #define DMA2D_OCOLR_RED_1_Pos (16U)
9242 #define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9243 #define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
9244 #define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9245 #define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9246 #define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
9247
9248 /*!<Mode_RGB565 */
9249 #define DMA2D_OCOLR_BLUE_2_Pos (0U)
9250 #define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9251 #define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
9252 #define DMA2D_OCOLR_GREEN_2_Pos (5U)
9253 #define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9254 #define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
9255 #define DMA2D_OCOLR_RED_2_Pos (11U)
9256 #define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9257 #define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
9258
9259 /*!<Mode_ARGB1555 */
9260 #define DMA2D_OCOLR_BLUE_3_Pos (0U)
9261 #define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9262 #define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
9263 #define DMA2D_OCOLR_GREEN_3_Pos (5U)
9264 #define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9265 #define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
9266 #define DMA2D_OCOLR_RED_3_Pos (10U)
9267 #define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9268 #define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
9269 #define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9270 #define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9271 #define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
9272
9273 /*!<Mode_ARGB4444 */
9274 #define DMA2D_OCOLR_BLUE_4_Pos (0U)
9275 #define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9276 #define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
9277 #define DMA2D_OCOLR_GREEN_4_Pos (4U)
9278 #define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9279 #define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
9280 #define DMA2D_OCOLR_RED_4_Pos (8U)
9281 #define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9282 #define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
9283 #define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9284 #define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9285 #define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
9286
9287 /******************** Bit definition for DMA2D_OMAR register ****************/
9288
9289 #define DMA2D_OMAR_MA_Pos (0U)
9290 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
9291 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
9292
9293 /******************** Bit definition for DMA2D_OOR register *****************/
9294
9295 #define DMA2D_OOR_LO_Pos (0U)
9296 #define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
9297 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
9298
9299 /******************** Bit definition for DMA2D_NLR register *****************/
9300
9301 #define DMA2D_NLR_NL_Pos (0U)
9302 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
9303 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
9304 #define DMA2D_NLR_PL_Pos (16U)
9305 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
9306 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
9307
9308 /******************** Bit definition for DMA2D_LWR register *****************/
9309
9310 #define DMA2D_LWR_LW_Pos (0U)
9311 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
9312 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
9313
9314 /******************** Bit definition for DMA2D_AMTCR register ***************/
9315
9316 #define DMA2D_AMTCR_EN_Pos (0U)
9317 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
9318 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
9319 #define DMA2D_AMTCR_DT_Pos (8U)
9320 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
9321 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
9322
9323
9324 /******************** Bit definition for DMA2D_FGCLUT register **************/
9325
9326 /******************** Bit definition for DMA2D_BGCLUT register **************/
9327
9328
9329 /******************************************************************************/
9330 /* */
9331 /* External Interrupt/Event Controller */
9332 /* */
9333 /******************************************************************************/
9334 /****************** Bit definition for EXTI_RTSR1 register *******************/
9335 #define EXTI_RTSR1_TR_Pos (0U)
9336 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
9337 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
9338 #define EXTI_RTSR1_TR0_Pos (0U)
9339 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
9340 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
9341 #define EXTI_RTSR1_TR1_Pos (1U)
9342 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
9343 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
9344 #define EXTI_RTSR1_TR2_Pos (2U)
9345 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
9346 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
9347 #define EXTI_RTSR1_TR3_Pos (3U)
9348 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
9349 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
9350 #define EXTI_RTSR1_TR4_Pos (4U)
9351 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
9352 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
9353 #define EXTI_RTSR1_TR5_Pos (5U)
9354 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
9355 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
9356 #define EXTI_RTSR1_TR6_Pos (6U)
9357 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
9358 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
9359 #define EXTI_RTSR1_TR7_Pos (7U)
9360 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
9361 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
9362 #define EXTI_RTSR1_TR8_Pos (8U)
9363 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
9364 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
9365 #define EXTI_RTSR1_TR9_Pos (9U)
9366 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
9367 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
9368 #define EXTI_RTSR1_TR10_Pos (10U)
9369 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
9370 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
9371 #define EXTI_RTSR1_TR11_Pos (11U)
9372 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
9373 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
9374 #define EXTI_RTSR1_TR12_Pos (12U)
9375 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
9376 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
9377 #define EXTI_RTSR1_TR13_Pos (13U)
9378 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
9379 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
9380 #define EXTI_RTSR1_TR14_Pos (14U)
9381 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
9382 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
9383 #define EXTI_RTSR1_TR15_Pos (15U)
9384 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
9385 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
9386 #define EXTI_RTSR1_TR16_Pos (16U)
9387 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
9388 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
9389 #define EXTI_RTSR1_TR17_Pos (17U)
9390 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
9391 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
9392 #define EXTI_RTSR1_TR18_Pos (18U)
9393 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
9394 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
9395 #define EXTI_RTSR1_TR19_Pos (19U)
9396 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
9397 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
9398 #define EXTI_RTSR1_TR20_Pos (20U)
9399 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
9400 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
9401 #define EXTI_RTSR1_TR21_Pos (21U)
9402 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
9403 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
9404
9405 /****************** Bit definition for EXTI_FTSR1 register *******************/
9406 #define EXTI_FTSR1_TR_Pos (0U)
9407 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
9408 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
9409 #define EXTI_FTSR1_TR0_Pos (0U)
9410 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
9411 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
9412 #define EXTI_FTSR1_TR1_Pos (1U)
9413 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
9414 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
9415 #define EXTI_FTSR1_TR2_Pos (2U)
9416 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
9417 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
9418 #define EXTI_FTSR1_TR3_Pos (3U)
9419 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
9420 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
9421 #define EXTI_FTSR1_TR4_Pos (4U)
9422 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
9423 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
9424 #define EXTI_FTSR1_TR5_Pos (5U)
9425 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
9426 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
9427 #define EXTI_FTSR1_TR6_Pos (6U)
9428 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
9429 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
9430 #define EXTI_FTSR1_TR7_Pos (7U)
9431 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
9432 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
9433 #define EXTI_FTSR1_TR8_Pos (8U)
9434 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
9435 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
9436 #define EXTI_FTSR1_TR9_Pos (9U)
9437 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
9438 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
9439 #define EXTI_FTSR1_TR10_Pos (10U)
9440 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
9441 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
9442 #define EXTI_FTSR1_TR11_Pos (11U)
9443 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
9444 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
9445 #define EXTI_FTSR1_TR12_Pos (12U)
9446 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
9447 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
9448 #define EXTI_FTSR1_TR13_Pos (13U)
9449 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
9450 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
9451 #define EXTI_FTSR1_TR14_Pos (14U)
9452 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
9453 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
9454 #define EXTI_FTSR1_TR15_Pos (15U)
9455 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
9456 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
9457 #define EXTI_FTSR1_TR16_Pos (16U)
9458 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
9459 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
9460 #define EXTI_FTSR1_TR17_Pos (17U)
9461 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
9462 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
9463 #define EXTI_FTSR1_TR18_Pos (18U)
9464 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
9465 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
9466 #define EXTI_FTSR1_TR19_Pos (19U)
9467 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
9468 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
9469 #define EXTI_FTSR1_TR20_Pos (20U)
9470 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
9471 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
9472 #define EXTI_FTSR1_TR21_Pos (21U)
9473 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
9474 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
9475
9476 /****************** Bit definition for EXTI_SWIER1 register ******************/
9477 #define EXTI_SWIER1_SWIER0_Pos (0U)
9478 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
9479 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
9480 #define EXTI_SWIER1_SWIER1_Pos (1U)
9481 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
9482 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
9483 #define EXTI_SWIER1_SWIER2_Pos (2U)
9484 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
9485 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
9486 #define EXTI_SWIER1_SWIER3_Pos (3U)
9487 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
9488 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
9489 #define EXTI_SWIER1_SWIER4_Pos (4U)
9490 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
9491 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
9492 #define EXTI_SWIER1_SWIER5_Pos (5U)
9493 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
9494 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
9495 #define EXTI_SWIER1_SWIER6_Pos (6U)
9496 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
9497 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
9498 #define EXTI_SWIER1_SWIER7_Pos (7U)
9499 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
9500 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
9501 #define EXTI_SWIER1_SWIER8_Pos (8U)
9502 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
9503 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
9504 #define EXTI_SWIER1_SWIER9_Pos (9U)
9505 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
9506 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
9507 #define EXTI_SWIER1_SWIER10_Pos (10U)
9508 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
9509 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
9510 #define EXTI_SWIER1_SWIER11_Pos (11U)
9511 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
9512 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
9513 #define EXTI_SWIER1_SWIER12_Pos (12U)
9514 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
9515 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
9516 #define EXTI_SWIER1_SWIER13_Pos (13U)
9517 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
9518 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
9519 #define EXTI_SWIER1_SWIER14_Pos (14U)
9520 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
9521 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
9522 #define EXTI_SWIER1_SWIER15_Pos (15U)
9523 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
9524 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
9525 #define EXTI_SWIER1_SWIER16_Pos (16U)
9526 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
9527 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
9528 #define EXTI_SWIER1_SWIER17_Pos (17U)
9529 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
9530 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
9531 #define EXTI_SWIER1_SWIER18_Pos (18U)
9532 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
9533 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
9534 #define EXTI_SWIER1_SWIER19_Pos (19U)
9535 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
9536 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
9537 #define EXTI_SWIER1_SWIER20_Pos (20U)
9538 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
9539 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
9540 #define EXTI_SWIER1_SWIER21_Pos (21U)
9541 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
9542 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
9543
9544 /****************** Bit definition for EXTI_D3PMR1 register ******************/
9545 #define EXTI_D3PMR1_MR0_Pos (0U)
9546 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
9547 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
9548 #define EXTI_D3PMR1_MR1_Pos (1U)
9549 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
9550 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
9551 #define EXTI_D3PMR1_MR2_Pos (2U)
9552 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
9553 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
9554 #define EXTI_D3PMR1_MR3_Pos (3U)
9555 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
9556 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
9557 #define EXTI_D3PMR1_MR4_Pos (4U)
9558 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
9559 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
9560 #define EXTI_D3PMR1_MR5_Pos (5U)
9561 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
9562 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
9563 #define EXTI_D3PMR1_MR6_Pos (6U)
9564 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
9565 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
9566 #define EXTI_D3PMR1_MR7_Pos (7U)
9567 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
9568 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
9569 #define EXTI_D3PMR1_MR8_Pos (8U)
9570 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
9571 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
9572 #define EXTI_D3PMR1_MR9_Pos (9U)
9573 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
9574 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
9575 #define EXTI_D3PMR1_MR10_Pos (10U)
9576 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
9577 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
9578 #define EXTI_D3PMR1_MR11_Pos (11U)
9579 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
9580 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
9581 #define EXTI_D3PMR1_MR12_Pos (12U)
9582 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
9583 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
9584 #define EXTI_D3PMR1_MR13_Pos (13U)
9585 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
9586 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
9587 #define EXTI_D3PMR1_MR14_Pos (14U)
9588 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
9589 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
9590 #define EXTI_D3PMR1_MR15_Pos (15U)
9591 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
9592 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
9593 #define EXTI_D3PMR1_MR19_Pos (19U)
9594 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
9595 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
9596 #define EXTI_D3PMR1_MR20_Pos (20U)
9597 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
9598 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
9599 #define EXTI_D3PMR1_MR21_Pos (21U)
9600 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
9601 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
9602 #define EXTI_D3PMR1_MR25_Pos (24U)
9603 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
9604 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
9605
9606 /******************* Bit definition for EXTI_D3PCR1L register ****************/
9607 #define EXTI_D3PCR1L_PCS0_Pos (0U)
9608 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
9609 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
9610 #define EXTI_D3PCR1L_PCS1_Pos (2U)
9611 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
9612 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
9613 #define EXTI_D3PCR1L_PCS2_Pos (4U)
9614 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
9615 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
9616 #define EXTI_D3PCR1L_PCS3_Pos (6U)
9617 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
9618 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
9619 #define EXTI_D3PCR1L_PCS4_Pos (8U)
9620 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
9621 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
9622 #define EXTI_D3PCR1L_PCS5_Pos (10U)
9623 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
9624 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
9625 #define EXTI_D3PCR1L_PCS6_Pos (12U)
9626 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
9627 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
9628 #define EXTI_D3PCR1L_PCS7_Pos (14U)
9629 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
9630 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
9631 #define EXTI_D3PCR1L_PCS8_Pos (16U)
9632 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
9633 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
9634 #define EXTI_D3PCR1L_PCS9_Pos (18U)
9635 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
9636 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
9637 #define EXTI_D3PCR1L_PCS10_Pos (20U)
9638 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
9639 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
9640 #define EXTI_D3PCR1L_PCS11_Pos (22U)
9641 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
9642 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
9643 #define EXTI_D3PCR1L_PCS12_Pos (24U)
9644 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
9645 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
9646 #define EXTI_D3PCR1L_PCS13_Pos (26U)
9647 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
9648 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
9649 #define EXTI_D3PCR1L_PCS14_Pos (28U)
9650 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
9651 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
9652 #define EXTI_D3PCR1L_PCS15_Pos (30U)
9653 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
9654 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
9655
9656 /******************* Bit definition for EXTI_D3PCR1H register ****************/
9657 #define EXTI_D3PCR1H_PCS19_Pos (6U)
9658 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
9659 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
9660 #define EXTI_D3PCR1H_PCS20_Pos (8U)
9661 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
9662 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
9663 #define EXTI_D3PCR1H_PCS21_Pos (10U)
9664 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
9665 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
9666 #define EXTI_D3PCR1H_PCS25_Pos (18U)
9667 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
9668 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
9669
9670 /****************** Bit definition for EXTI_RTSR2 register *******************/
9671 #define EXTI_RTSR2_TR_Pos (17U)
9672 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
9673 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
9674 #define EXTI_RTSR2_TR49_Pos (17U)
9675 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
9676 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
9677 #define EXTI_RTSR2_TR51_Pos (19U)
9678 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
9679 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
9680
9681 /****************** Bit definition for EXTI_FTSR2 register *******************/
9682 #define EXTI_FTSR2_TR_Pos (17U)
9683 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
9684 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
9685 #define EXTI_FTSR2_TR49_Pos (17U)
9686 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
9687 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
9688 #define EXTI_FTSR2_TR51_Pos (19U)
9689 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
9690 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
9691
9692 /****************** Bit definition for EXTI_SWIER2 register ******************/
9693 #define EXTI_SWIER2_SWIER49_Pos (17U)
9694 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
9695 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
9696 #define EXTI_SWIER2_SWIER51_Pos (19U)
9697 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
9698 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
9699
9700 /****************** Bit definition for EXTI_D3PMR2 register ******************/
9701 #define EXTI_D3PMR2_MR34_Pos (2U)
9702 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
9703 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
9704 #define EXTI_D3PMR2_MR35_Pos (3U)
9705 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
9706 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
9707 #define EXTI_D3PMR2_MR41_Pos (9U)
9708 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
9709 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
9710 #define EXTI_D3PMR2_MR48_Pos (16U)
9711 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
9712 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
9713 #define EXTI_D3PMR2_MR49_Pos (17U)
9714 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
9715 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
9716 #define EXTI_D3PMR2_MR50_Pos (18U)
9717 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
9718 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
9719 #define EXTI_D3PMR2_MR51_Pos (19U)
9720 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
9721 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
9722 #define EXTI_D3PMR2_MR52_Pos (20U)
9723 #define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
9724 #define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
9725 #define EXTI_D3PMR2_MR53_Pos (21U)
9726 #define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
9727 #define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
9728 /******************* Bit definition for EXTI_D3PCR2L register ****************/
9729 #define EXTI_D3PCR2L_PCS34_Pos (4U)
9730 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
9731 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
9732 #define EXTI_D3PCR2L_PCS35_Pos (6U)
9733 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
9734 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
9735 #define EXTI_D3PCR2L_PCS41_Pos (18U)
9736 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
9737 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
9738
9739
9740 /******************* Bit definition for EXTI_D3PCR2H register ****************/
9741 #define EXTI_D3PCR2H_PCS48_Pos (0U)
9742 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
9743 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
9744 #define EXTI_D3PCR2H_PCS49_Pos (2U)
9745 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
9746 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
9747 #define EXTI_D3PCR2H_PCS50_Pos (4U)
9748 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
9749 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
9750 #define EXTI_D3PCR2H_PCS51_Pos (6U)
9751 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
9752 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
9753 #define EXTI_D3PCR2H_PCS52_Pos (8U)
9754 #define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */
9755 #define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */
9756 #define EXTI_D3PCR2H_PCS53_Pos (10U)
9757 #define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */
9758 #define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */
9759 /****************** Bit definition for EXTI_RTSR3 register *******************/
9760 #define EXTI_RTSR3_TR_Pos (18U)
9761 #define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */
9762 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
9763 #define EXTI_RTSR3_TR82_Pos (18U)
9764 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
9765 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
9766 #define EXTI_RTSR3_TR84_Pos (20U)
9767 #define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
9768 #define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
9769 #define EXTI_RTSR3_TR85_Pos (21U)
9770 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
9771 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
9772 #define EXTI_RTSR3_TR86_Pos (22U)
9773 #define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
9774 #define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
9775
9776 /****************** Bit definition for EXTI_FTSR3 register *******************/
9777 #define EXTI_FTSR3_TR_Pos (18U)
9778 #define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */
9779 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
9780 #define EXTI_FTSR3_TR82_Pos (18U)
9781 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
9782 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
9783 #define EXTI_FTSR3_TR84_Pos (20U)
9784 #define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
9785 #define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
9786 #define EXTI_FTSR3_TR85_Pos (21U)
9787 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
9788 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
9789 #define EXTI_FTSR3_TR86_Pos (22U)
9790 #define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
9791 #define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
9792
9793 /****************** Bit definition for EXTI_SWIER3 register ******************/
9794 #define EXTI_SWIER3_SWI_Pos (18U)
9795 #define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */
9796 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
9797 #define EXTI_SWIER3_SWIER82_Pos (18U)
9798 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
9799 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
9800 #define EXTI_SWIER3_SWIER84_Pos (20U)
9801 #define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
9802 #define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
9803 #define EXTI_SWIER3_SWIER85_Pos (21U)
9804 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
9805 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
9806 #define EXTI_SWIER3_SWIER86_Pos (22U)
9807 #define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
9808 #define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
9809
9810 /******************* Bit definition for EXTI_IMR1 register *******************/
9811 #define EXTI_IMR1_IM_Pos (0U)
9812 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
9813 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
9814 #define EXTI_IMR1_IM0_Pos (0U)
9815 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
9816 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
9817 #define EXTI_IMR1_IM1_Pos (1U)
9818 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
9819 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
9820 #define EXTI_IMR1_IM2_Pos (2U)
9821 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
9822 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
9823 #define EXTI_IMR1_IM3_Pos (3U)
9824 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
9825 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
9826 #define EXTI_IMR1_IM4_Pos (4U)
9827 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
9828 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
9829 #define EXTI_IMR1_IM5_Pos (5U)
9830 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
9831 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
9832 #define EXTI_IMR1_IM6_Pos (6U)
9833 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
9834 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
9835 #define EXTI_IMR1_IM7_Pos (7U)
9836 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
9837 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
9838 #define EXTI_IMR1_IM8_Pos (8U)
9839 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
9840 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
9841 #define EXTI_IMR1_IM9_Pos (9U)
9842 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
9843 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
9844 #define EXTI_IMR1_IM10_Pos (10U)
9845 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
9846 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
9847 #define EXTI_IMR1_IM11_Pos (11U)
9848 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
9849 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
9850 #define EXTI_IMR1_IM12_Pos (12U)
9851 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
9852 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
9853 #define EXTI_IMR1_IM13_Pos (13U)
9854 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
9855 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
9856 #define EXTI_IMR1_IM14_Pos (14U)
9857 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
9858 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
9859 #define EXTI_IMR1_IM15_Pos (15U)
9860 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
9861 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
9862 #define EXTI_IMR1_IM16_Pos (16U)
9863 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
9864 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
9865 #define EXTI_IMR1_IM17_Pos (17U)
9866 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
9867 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
9868 #define EXTI_IMR1_IM18_Pos (18U)
9869 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
9870 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
9871 #define EXTI_IMR1_IM19_Pos (19U)
9872 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
9873 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
9874 #define EXTI_IMR1_IM20_Pos (20U)
9875 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
9876 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
9877 #define EXTI_IMR1_IM21_Pos (21U)
9878 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
9879 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
9880 #define EXTI_IMR1_IM22_Pos (22U)
9881 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
9882 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
9883 #define EXTI_IMR1_IM23_Pos (23U)
9884 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
9885 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
9886 #define EXTI_IMR1_IM24_Pos (24U)
9887 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
9888 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
9889 #define EXTI_IMR1_IM25_Pos (25U)
9890 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
9891 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
9892 #define EXTI_IMR1_IM26_Pos (26U)
9893 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
9894 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
9895 #define EXTI_IMR1_IM27_Pos (27U)
9896 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
9897 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
9898 #define EXTI_IMR1_IM28_Pos (28U)
9899 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
9900 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
9901 #define EXTI_IMR1_IM29_Pos (29U)
9902 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
9903 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
9904 #define EXTI_IMR1_IM30_Pos (30U)
9905 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
9906 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
9907 #define EXTI_IMR1_IM31_Pos (31U)
9908 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
9909 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
9910
9911 /******************* Bit definition for EXTI_EMR1 register *******************/
9912 #define EXTI_EMR1_EM_Pos (0U)
9913 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
9914 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
9915 #define EXTI_EMR1_EM0_Pos (0U)
9916 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
9917 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
9918 #define EXTI_EMR1_EM1_Pos (1U)
9919 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
9920 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
9921 #define EXTI_EMR1_EM2_Pos (2U)
9922 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
9923 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
9924 #define EXTI_EMR1_EM3_Pos (3U)
9925 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
9926 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
9927 #define EXTI_EMR1_EM4_Pos (4U)
9928 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
9929 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
9930 #define EXTI_EMR1_EM5_Pos (5U)
9931 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
9932 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
9933 #define EXTI_EMR1_EM6_Pos (6U)
9934 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
9935 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
9936 #define EXTI_EMR1_EM7_Pos (7U)
9937 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
9938 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
9939 #define EXTI_EMR1_EM8_Pos (8U)
9940 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
9941 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
9942 #define EXTI_EMR1_EM9_Pos (9U)
9943 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
9944 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
9945 #define EXTI_EMR1_EM10_Pos (10U)
9946 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
9947 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
9948 #define EXTI_EMR1_EM11_Pos (11U)
9949 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
9950 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
9951 #define EXTI_EMR1_EM12_Pos (12U)
9952 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
9953 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
9954 #define EXTI_EMR1_EM13_Pos (13U)
9955 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
9956 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
9957 #define EXTI_EMR1_EM14_Pos (14U)
9958 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
9959 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
9960 #define EXTI_EMR1_EM15_Pos (15U)
9961 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
9962 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
9963 #define EXTI_EMR1_EM16_Pos (16U)
9964 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
9965 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
9966 #define EXTI_EMR1_EM17_Pos (17U)
9967 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
9968 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
9969 #define EXTI_EMR1_EM18_Pos (18U)
9970 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
9971 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
9972 #define EXTI_EMR1_EM20_Pos (20U)
9973 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
9974 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
9975 #define EXTI_EMR1_EM21_Pos (21U)
9976 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
9977 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
9978 #define EXTI_EMR1_EM22_Pos (22U)
9979 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
9980 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
9981 #define EXTI_EMR1_EM23_Pos (23U)
9982 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
9983 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
9984 #define EXTI_EMR1_EM24_Pos (24U)
9985 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
9986 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
9987 #define EXTI_EMR1_EM25_Pos (25U)
9988 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
9989 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
9990 #define EXTI_EMR1_EM26_Pos (26U)
9991 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
9992 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
9993 #define EXTI_EMR1_EM27_Pos (27U)
9994 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
9995 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
9996 #define EXTI_EMR1_EM28_Pos (28U)
9997 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
9998 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
9999 #define EXTI_EMR1_EM29_Pos (29U)
10000 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
10001 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
10002 #define EXTI_EMR1_EM30_Pos (30U)
10003 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
10004 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
10005 #define EXTI_EMR1_EM31_Pos (31U)
10006 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
10007 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
10008
10009 /******************* Bit definition for EXTI_PR1 register ********************/
10010 #define EXTI_PR1_PR_Pos (0U)
10011 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
10012 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
10013 #define EXTI_PR1_PR0_Pos (0U)
10014 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
10015 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
10016 #define EXTI_PR1_PR1_Pos (1U)
10017 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
10018 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
10019 #define EXTI_PR1_PR2_Pos (2U)
10020 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
10021 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
10022 #define EXTI_PR1_PR3_Pos (3U)
10023 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
10024 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
10025 #define EXTI_PR1_PR4_Pos (4U)
10026 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
10027 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
10028 #define EXTI_PR1_PR5_Pos (5U)
10029 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
10030 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
10031 #define EXTI_PR1_PR6_Pos (6U)
10032 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
10033 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
10034 #define EXTI_PR1_PR7_Pos (7U)
10035 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
10036 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
10037 #define EXTI_PR1_PR8_Pos (8U)
10038 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
10039 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
10040 #define EXTI_PR1_PR9_Pos (9U)
10041 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
10042 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
10043 #define EXTI_PR1_PR10_Pos (10U)
10044 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
10045 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
10046 #define EXTI_PR1_PR11_Pos (11U)
10047 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
10048 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
10049 #define EXTI_PR1_PR12_Pos (12U)
10050 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
10051 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
10052 #define EXTI_PR1_PR13_Pos (13U)
10053 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
10054 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
10055 #define EXTI_PR1_PR14_Pos (14U)
10056 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
10057 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
10058 #define EXTI_PR1_PR15_Pos (15U)
10059 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
10060 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
10061 #define EXTI_PR1_PR16_Pos (16U)
10062 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
10063 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
10064 #define EXTI_PR1_PR17_Pos (17U)
10065 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
10066 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
10067 #define EXTI_PR1_PR18_Pos (18U)
10068 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
10069 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
10070 #define EXTI_PR1_PR19_Pos (19U)
10071 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
10072 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
10073 #define EXTI_PR1_PR20_Pos (20U)
10074 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
10075 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
10076 #define EXTI_PR1_PR21_Pos (21U)
10077 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
10078 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
10079
10080 /******************* Bit definition for EXTI_IMR2 register *******************/
10081 #define EXTI_IMR2_IM_Pos (0U)
10082 #define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */
10083 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
10084 #define EXTI_IMR2_IM32_Pos (0U)
10085 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
10086 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
10087 #define EXTI_IMR2_IM33_Pos (1U)
10088 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
10089 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
10090 #define EXTI_IMR2_IM34_Pos (2U)
10091 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
10092 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
10093 #define EXTI_IMR2_IM35_Pos (3U)
10094 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
10095 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
10096 #define EXTI_IMR2_IM36_Pos (4U)
10097 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
10098 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
10099 #define EXTI_IMR2_IM37_Pos (5U)
10100 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
10101 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
10102 #define EXTI_IMR2_IM38_Pos (6U)
10103 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
10104 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
10105 #define EXTI_IMR2_IM39_Pos (7U)
10106 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
10107 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
10108 #define EXTI_IMR2_IM40_Pos (8U)
10109 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
10110 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
10111 #define EXTI_IMR2_IM41_Pos (9U)
10112 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
10113 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
10114 #define EXTI_IMR2_IM42_Pos (10U)
10115 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
10116 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
10117 #define EXTI_IMR2_IM43_Pos (11U)
10118 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
10119 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
10120 #define EXTI_IMR2_IM44_Pos (12U)
10121 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
10122 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
10123 #define EXTI_IMR2_IM46_Pos (14U)
10124 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
10125 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
10126 #define EXTI_IMR2_IM47_Pos (15U)
10127 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
10128 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
10129 #define EXTI_IMR2_IM48_Pos (16U)
10130 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
10131 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
10132 #define EXTI_IMR2_IM49_Pos (17U)
10133 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
10134 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
10135 #define EXTI_IMR2_IM50_Pos (18U)
10136 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
10137 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
10138 #define EXTI_IMR2_IM51_Pos (19U)
10139 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
10140 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
10141 #define EXTI_IMR2_IM52_Pos (20U)
10142 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
10143 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
10144 #define EXTI_IMR2_IM53_Pos (21U)
10145 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
10146 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
10147 #define EXTI_IMR2_IM54_Pos (22U)
10148 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
10149 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
10150 #define EXTI_IMR2_IM55_Pos (23U)
10151 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
10152 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
10153 #define EXTI_IMR2_IM56_Pos (24U)
10154 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
10155 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
10156 #define EXTI_IMR2_IM57_Pos (25U)
10157 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
10158 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
10159 #define EXTI_IMR2_IM58_Pos (26U)
10160 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
10161 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
10162 #define EXTI_IMR2_IM59_Pos (27U)
10163 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
10164 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
10165 #define EXTI_IMR2_IM60_Pos (28U)
10166 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
10167 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
10168 #define EXTI_IMR2_IM61_Pos (29U)
10169 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
10170 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
10171 #define EXTI_IMR2_IM62_Pos (30U)
10172 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
10173 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
10174 #define EXTI_IMR2_IM63_Pos (31U)
10175 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
10176 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
10177
10178 /******************* Bit definition for EXTI_EMR2 register *******************/
10179 #define EXTI_EMR2_EM_Pos (0U)
10180 #define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */
10181 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
10182 #define EXTI_EMR2_EM32_Pos (0U)
10183 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
10184 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
10185 #define EXTI_EMR2_EM33_Pos (1U)
10186 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
10187 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
10188 #define EXTI_EMR2_EM34_Pos (2U)
10189 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
10190 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
10191 #define EXTI_EMR2_EM35_Pos (3U)
10192 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
10193 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
10194 #define EXTI_EMR2_EM36_Pos (4U)
10195 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
10196 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
10197 #define EXTI_EMR2_EM37_Pos (5U)
10198 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
10199 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
10200 #define EXTI_EMR2_EM38_Pos (6U)
10201 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
10202 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
10203 #define EXTI_EMR2_EM39_Pos (7U)
10204 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
10205 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
10206 #define EXTI_EMR2_EM40_Pos (8U)
10207 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
10208 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
10209 #define EXTI_EMR2_EM41_Pos (9U)
10210 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
10211 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
10212 #define EXTI_EMR2_EM42_Pos (10U)
10213 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
10214 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
10215 #define EXTI_EMR2_EM43_Pos (11U)
10216 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
10217 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
10218 #define EXTI_EMR2_EM44_Pos (12U)
10219 #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
10220 #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
10221 #define EXTI_EMR2_EM46_Pos (14U)
10222 #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
10223 #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
10224 #define EXTI_EMR2_EM47_Pos (15U)
10225 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
10226 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
10227 #define EXTI_EMR2_EM48_Pos (16U)
10228 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
10229 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
10230 #define EXTI_EMR2_EM49_Pos (17U)
10231 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
10232 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
10233 #define EXTI_EMR2_EM50_Pos (18U)
10234 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
10235 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
10236 #define EXTI_EMR2_EM51_Pos (19U)
10237 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
10238 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
10239 #define EXTI_EMR2_EM52_Pos (20U)
10240 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
10241 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
10242 #define EXTI_EMR2_EM53_Pos (21U)
10243 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
10244 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
10245 #define EXTI_EMR2_EM54_Pos (22U)
10246 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
10247 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
10248 #define EXTI_EMR2_EM55_Pos (23U)
10249 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
10250 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
10251 #define EXTI_EMR2_EM56_Pos (24U)
10252 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
10253 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
10254 #define EXTI_EMR2_EM57_Pos (25U)
10255 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
10256 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
10257 #define EXTI_EMR2_EM58_Pos (26U)
10258 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
10259 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
10260 #define EXTI_EMR2_EM59_Pos (27U)
10261 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
10262 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
10263 #define EXTI_EMR2_EM60_Pos (28U)
10264 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
10265 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
10266 #define EXTI_EMR2_EM61_Pos (29U)
10267 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
10268 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
10269 #define EXTI_EMR2_EM62_Pos (30U)
10270 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
10271 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
10272 #define EXTI_EMR2_EM63_Pos (31U)
10273 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
10274 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
10275
10276 /******************* Bit definition for EXTI_PR2 register ********************/
10277 #define EXTI_PR2_PR_Pos (17U)
10278 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
10279 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
10280 #define EXTI_PR2_PR49_Pos (17U)
10281 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
10282 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
10283 #define EXTI_PR2_PR51_Pos (19U)
10284 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
10285 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
10286
10287 /******************* Bit definition for EXTI_IMR3 register *******************/
10288 #define EXTI_IMR3_IM_Pos (0U)
10289 #define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */
10290 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
10291 #define EXTI_IMR3_IM64_Pos (0U)
10292 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
10293 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
10294 #define EXTI_IMR3_IM65_Pos (1U)
10295 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
10296 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
10297 #define EXTI_IMR3_IM66_Pos (2U)
10298 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
10299 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
10300 #define EXTI_IMR3_IM67_Pos (3U)
10301 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
10302 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
10303 #define EXTI_IMR3_IM68_Pos (4U)
10304 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
10305 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
10306 #define EXTI_IMR3_IM69_Pos (5U)
10307 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
10308 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
10309 #define EXTI_IMR3_IM70_Pos (6U)
10310 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
10311 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
10312 #define EXTI_IMR3_IM71_Pos (7U)
10313 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
10314 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
10315 #define EXTI_IMR3_IM72_Pos (8U)
10316 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
10317 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
10318 #define EXTI_IMR3_IM73_Pos (9U)
10319 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
10320 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
10321 #define EXTI_IMR3_IM74_Pos (10U)
10322 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
10323 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
10324 #define EXTI_IMR3_IM75_Pos (11U)
10325 #define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
10326 #define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
10327 #define EXTI_IMR3_IM76_Pos (12U)
10328 #define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
10329 #define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
10330 #define EXTI_IMR3_IM77_Pos (13U)
10331 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
10332 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
10333 #define EXTI_IMR3_IM78_Pos (14U)
10334 #define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
10335 #define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
10336 #define EXTI_IMR3_IM79_Pos (15U)
10337 #define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
10338 #define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
10339 #define EXTI_IMR3_IM80_Pos (16U)
10340 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
10341 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
10342 #define EXTI_IMR3_IM82_Pos (18U)
10343 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
10344 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
10345 #define EXTI_IMR3_IM84_Pos (20U)
10346 #define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
10347 #define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
10348 #define EXTI_IMR3_IM85_Pos (21U)
10349 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
10350 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
10351 #define EXTI_IMR3_IM86_Pos (22U)
10352 #define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
10353 #define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
10354 #define EXTI_IMR3_IM87_Pos (23U)
10355 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
10356 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
10357
10358
10359 /******************* Bit definition for EXTI_EMR3 register *******************/
10360 #define EXTI_EMR3_EM_Pos (0U)
10361 #define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */
10362 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
10363 #define EXTI_EMR3_EM64_Pos (0U)
10364 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
10365 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
10366 #define EXTI_EMR3_EM65_Pos (1U)
10367 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
10368 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
10369 #define EXTI_EMR3_EM66_Pos (2U)
10370 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
10371 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
10372 #define EXTI_EMR3_EM67_Pos (3U)
10373 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
10374 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
10375 #define EXTI_EMR3_EM68_Pos (4U)
10376 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
10377 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
10378 #define EXTI_EMR3_EM69_Pos (5U)
10379 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
10380 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
10381 #define EXTI_EMR3_EM70_Pos (6U)
10382 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
10383 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
10384 #define EXTI_EMR3_EM71_Pos (7U)
10385 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
10386 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
10387 #define EXTI_EMR3_EM72_Pos (8U)
10388 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
10389 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
10390 #define EXTI_EMR3_EM73_Pos (9U)
10391 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
10392 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
10393 #define EXTI_EMR3_EM74_Pos (10U)
10394 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
10395 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
10396 #define EXTI_EMR3_EM75_Pos (11U)
10397 #define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
10398 #define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
10399 #define EXTI_EMR3_EM76_Pos (12U)
10400 #define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
10401 #define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
10402 #define EXTI_EMR3_EM77_Pos (13U)
10403 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
10404 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
10405 #define EXTI_EMR3_EM78_Pos (14U)
10406 #define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
10407 #define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
10408 #define EXTI_EMR3_EM79_Pos (15U)
10409 #define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
10410 #define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
10411 #define EXTI_EMR3_EM80_Pos (16U)
10412 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
10413 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
10414 #define EXTI_EMR3_EM81_Pos (17U)
10415 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
10416 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
10417 #define EXTI_EMR3_EM82_Pos (18U)
10418 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
10419 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
10420 #define EXTI_EMR3_EM84_Pos (20U)
10421 #define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
10422 #define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
10423 #define EXTI_EMR3_EM85_Pos (21U)
10424 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
10425 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
10426 #define EXTI_EMR3_EM86_Pos (22U)
10427 #define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
10428 #define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
10429 #define EXTI_EMR3_EM87_Pos (23U)
10430 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
10431 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
10432
10433 /******************* Bit definition for EXTI_PR3 register ********************/
10434 #define EXTI_PR3_PR_Pos (18U)
10435 #define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */
10436 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
10437 #define EXTI_PR3_PR82_Pos (18U)
10438 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
10439 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
10440 #define EXTI_PR3_PR84_Pos (20U)
10441 #define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
10442 #define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
10443 #define EXTI_PR3_PR85_Pos (21U)
10444 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
10445 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
10446 #define EXTI_PR3_PR86_Pos (22U)
10447 #define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
10448 #define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
10449 /******************************************************************************/
10450 /* */
10451 /* FLASH */
10452 /* */
10453 /******************************************************************************/
10454 /*
10455 * @brief FLASH Global Defines
10456 */
10457 #define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
10458 #define FLASH_SIZE 0x200000UL /* 2 MB */
10459 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
10460 #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
10461 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
10462 #define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
10463 #define DUAL_BANK /* Dual-bank Flash */
10464
10465 /******************* Bits definition for FLASH_ACR register **********************/
10466 #define FLASH_ACR_LATENCY_Pos (0U)
10467 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
10468 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
10469 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
10470 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
10471 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
10472 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
10473 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
10474 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
10475 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
10476 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
10477 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
10478 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
10479 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
10480 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
10481 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
10482 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
10483 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
10484 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
10485 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
10486 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
10487 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
10488 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
10489 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
10490
10491 /******************* Bits definition for FLASH_CR register ***********************/
10492 #define FLASH_CR_LOCK_Pos (0U)
10493 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
10494 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
10495 #define FLASH_CR_PG_Pos (1U)
10496 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
10497 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
10498 #define FLASH_CR_SER_Pos (2U)
10499 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
10500 #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
10501 #define FLASH_CR_BER_Pos (3U)
10502 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
10503 #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
10504 #define FLASH_CR_PSIZE_Pos (4U)
10505 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
10506 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
10507 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
10508 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
10509 #define FLASH_CR_FW_Pos (6U)
10510 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
10511 #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
10512 #define FLASH_CR_START_Pos (7U)
10513 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
10514 #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
10515 #define FLASH_CR_SNB_Pos (8U)
10516 #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
10517 #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
10518 #define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
10519 #define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
10520 #define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
10521 #define FLASH_CR_CRC_EN_Pos (15U)
10522 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
10523 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
10524 #define FLASH_CR_EOPIE_Pos (16U)
10525 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
10526 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
10527 #define FLASH_CR_WRPERRIE_Pos (17U)
10528 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
10529 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
10530 #define FLASH_CR_PGSERRIE_Pos (18U)
10531 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
10532 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
10533 #define FLASH_CR_STRBERRIE_Pos (19U)
10534 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
10535 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
10536 #define FLASH_CR_INCERRIE_Pos (21U)
10537 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
10538 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
10539 #define FLASH_CR_OPERRIE_Pos (22U)
10540 #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
10541 #define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
10542 #define FLASH_CR_RDPERRIE_Pos (23U)
10543 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
10544 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
10545 #define FLASH_CR_RDSERRIE_Pos (24U)
10546 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
10547 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
10548 #define FLASH_CR_SNECCERRIE_Pos (25U)
10549 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
10550 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
10551 #define FLASH_CR_DBECCERRIE_Pos (26U)
10552 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
10553 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
10554 #define FLASH_CR_CRCENDIE_Pos (27U)
10555 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
10556 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
10557 #define FLASH_CR_CRCRDERRIE_Pos (28U)
10558 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
10559 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
10560
10561 /******************* Bits definition for FLASH_SR register ***********************/
10562 #define FLASH_SR_BSY_Pos (0U)
10563 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
10564 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
10565 #define FLASH_SR_WBNE_Pos (1U)
10566 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
10567 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
10568 #define FLASH_SR_QW_Pos (2U)
10569 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
10570 #define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
10571 #define FLASH_SR_CRC_BUSY_Pos (3U)
10572 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
10573 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
10574 #define FLASH_SR_EOP_Pos (16U)
10575 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
10576 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
10577 #define FLASH_SR_WRPERR_Pos (17U)
10578 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
10579 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
10580 #define FLASH_SR_PGSERR_Pos (18U)
10581 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
10582 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
10583 #define FLASH_SR_STRBERR_Pos (19U)
10584 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
10585 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
10586 #define FLASH_SR_INCERR_Pos (21U)
10587 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
10588 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
10589 #define FLASH_SR_OPERR_Pos (22U)
10590 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
10591 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
10592 #define FLASH_SR_RDPERR_Pos (23U)
10593 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
10594 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
10595 #define FLASH_SR_RDSERR_Pos (24U)
10596 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
10597 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
10598 #define FLASH_SR_SNECCERR_Pos (25U)
10599 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
10600 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
10601 #define FLASH_SR_DBECCERR_Pos (26U)
10602 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
10603 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
10604 #define FLASH_SR_CRCEND_Pos (27U)
10605 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
10606 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
10607 #define FLASH_SR_CRCRDERR_Pos (28U)
10608 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
10609 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
10610
10611 /******************* Bits definition for FLASH_CCR register *******************/
10612 #define FLASH_CCR_CLR_EOP_Pos (16U)
10613 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
10614 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
10615 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
10616 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
10617 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
10618 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
10619 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
10620 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
10621 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
10622 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
10623 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
10624 #define FLASH_CCR_CLR_INCERR_Pos (21U)
10625 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
10626 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
10627 #define FLASH_CCR_CLR_OPERR_Pos (22U)
10628 #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
10629 #define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
10630 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
10631 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
10632 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
10633 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
10634 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
10635 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
10636 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
10637 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
10638 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
10639 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
10640 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
10641 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
10642 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
10643 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
10644 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
10645 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
10646 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
10647 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
10648
10649 /******************* Bits definition for FLASH_OPTCR register *******************/
10650 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
10651 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
10652 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
10653 #define FLASH_OPTCR_OPTSTART_Pos (1U)
10654 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
10655 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
10656 #define FLASH_OPTCR_MER_Pos (4U)
10657 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
10658 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
10659 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
10660 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
10661 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
10662 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
10663 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
10664 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
10665
10666 /******************* Bits definition for FLASH_OPTSR register ***************/
10667 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
10668 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
10669 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
10670 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
10671 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
10672 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
10673 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
10674 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
10675 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
10676 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
10677 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
10678 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
10679 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
10680 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
10681 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
10682 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
10683 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
10684 #define FLASH_OPTSR_RDP_Pos (8U)
10685 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
10686 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
10687 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
10688 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
10689 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
10690 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
10691 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
10692 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
10693 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
10694 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
10695 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
10696 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
10697 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
10698 #define FLASH_OPTSR_SECURITY_Pos (21U)
10699 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
10700 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
10701 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
10702 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
10703 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
10704 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
10705 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
10706 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
10707 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
10708 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
10709 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
10710
10711 /******************* Bits definition for FLASH_OPTCCR register *******************/
10712 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
10713 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
10714 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
10715
10716 /******************* Bits definition for FLASH_PRAR register *********************/
10717 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
10718 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
10719 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
10720 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
10721 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
10722 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
10723 #define FLASH_PRAR_DMEP_Pos (31U)
10724 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
10725 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
10726
10727 /******************* Bits definition for FLASH_SCAR register *********************/
10728 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
10729 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
10730 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
10731 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
10732 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
10733 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
10734 #define FLASH_SCAR_DMES_Pos (31U)
10735 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
10736 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
10737
10738 /******************* Bits definition for FLASH_WPSN register *********************/
10739 #define FLASH_WPSN_WRPSN_Pos (0U)
10740 #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
10741 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
10742
10743 /******************* Bits definition for FLASH_BOOT_CUR register ****************/
10744 #define FLASH_BOOT_ADD0_Pos (0U)
10745 #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
10746 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
10747 #define FLASH_BOOT_ADD1_Pos (16U)
10748 #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
10749 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
10750
10751
10752 /******************* Bits definition for FLASH_CRCCR register ********************/
10753 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
10754 #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
10755 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
10756 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
10757 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
10758 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
10759 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
10760 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
10761 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
10762 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
10763 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
10764 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
10765 #define FLASH_CRCCR_START_CRC_Pos (16U)
10766 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
10767 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
10768 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
10769 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
10770 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
10771 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
10772 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
10773 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
10774 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
10775 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
10776 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
10777 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
10778 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
10779
10780 /******************* Bits definition for FLASH_CRCSADD register ****************/
10781 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
10782 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
10783 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
10784
10785 /******************* Bits definition for FLASH_CRCEADD register ****************/
10786 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
10787 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
10788 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
10789
10790 /******************* Bits definition for FLASH_CRCDATA register ***************/
10791 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
10792 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
10793 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
10794
10795 /******************* Bits definition for FLASH_ECC_FA register *******************/
10796 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
10797 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
10798 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
10799
10800 /******************************************************************************/
10801 /* */
10802 /* Flexible Memory Controller */
10803 /* */
10804 /******************************************************************************/
10805 /****************** Bit definition for FMC_BCR1 register *******************/
10806 #define FMC_BCR1_CCLKEN_Pos (20U)
10807 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
10808 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
10809 #define FMC_BCR1_WFDIS_Pos (21U)
10810 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
10811 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
10812
10813 #define FMC_BCR1_BMAP_Pos (24U)
10814 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
10815 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
10816 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
10817 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
10818
10819 #define FMC_BCR1_FMCEN_Pos (31U)
10820 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
10821 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
10822 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
10823 #define FMC_BCRx_MBKEN_Pos (0U)
10824 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
10825 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
10826 #define FMC_BCRx_MUXEN_Pos (1U)
10827 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
10828 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
10829
10830 #define FMC_BCRx_MTYP_Pos (2U)
10831 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
10832 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
10833 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
10834 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
10835
10836 #define FMC_BCRx_MWID_Pos (4U)
10837 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
10838 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
10839 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
10840 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
10841
10842 #define FMC_BCRx_FACCEN_Pos (6U)
10843 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
10844 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
10845 #define FMC_BCRx_BURSTEN_Pos (8U)
10846 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
10847 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
10848 #define FMC_BCRx_WAITPOL_Pos (9U)
10849 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
10850 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
10851 #define FMC_BCRx_WAITCFG_Pos (11U)
10852 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
10853 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
10854 #define FMC_BCRx_WREN_Pos (12U)
10855 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
10856 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
10857 #define FMC_BCRx_WAITEN_Pos (13U)
10858 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
10859 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
10860 #define FMC_BCRx_EXTMOD_Pos (14U)
10861 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
10862 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
10863 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
10864 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
10865 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
10866
10867 #define FMC_BCRx_CPSIZE_Pos (16U)
10868 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
10869 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
10870 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
10871 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
10872 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
10873
10874 #define FMC_BCRx_CBURSTRW_Pos (19U)
10875 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
10876 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
10877
10878 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
10879 #define FMC_BTRx_ADDSET_Pos (0U)
10880 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
10881 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10882 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
10883 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
10884 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
10885 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
10886
10887 #define FMC_BTRx_ADDHLD_Pos (4U)
10888 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
10889 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10890 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
10891 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
10892 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
10893 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
10894
10895 #define FMC_BTRx_DATAST_Pos (8U)
10896 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
10897 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10898 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
10899 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
10900 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
10901 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
10902 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
10903 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
10904 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
10905 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
10906
10907 #define FMC_BTRx_BUSTURN_Pos (16U)
10908 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
10909 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10910 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
10911 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
10912 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
10913 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
10914
10915 #define FMC_BTRx_CLKDIV_Pos (20U)
10916 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
10917 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
10918 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
10919 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
10920 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
10921 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
10922
10923 #define FMC_BTRx_DATLAT_Pos (24U)
10924 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
10925 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
10926 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
10927 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
10928 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
10929 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
10930
10931 #define FMC_BTRx_ACCMOD_Pos (28U)
10932 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
10933 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10934 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
10935 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
10936
10937 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
10938 #define FMC_BWTRx_ADDSET_Pos (0U)
10939 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
10940 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
10941 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
10942 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
10943 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
10944 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
10945
10946 #define FMC_BWTRx_ADDHLD_Pos (4U)
10947 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
10948 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
10949 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
10950 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
10951 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
10952 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
10953
10954 #define FMC_BWTRx_DATAST_Pos (8U)
10955 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
10956 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
10957 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
10958 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
10959 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
10960 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
10961 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
10962 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
10963 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
10964 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
10965
10966 #define FMC_BWTRx_BUSTURN_Pos (16U)
10967 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
10968 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
10969 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
10970 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
10971 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
10972 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
10973
10974 #define FMC_BWTRx_ACCMOD_Pos (28U)
10975 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
10976 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
10977 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
10978 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
10979
10980 /****************** Bit definition for FMC_PCR register *******************/
10981 #define FMC_PCR_PWAITEN_Pos (1U)
10982 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
10983 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
10984 #define FMC_PCR_PBKEN_Pos (2U)
10985 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
10986 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
10987
10988 #define FMC_PCR_PWID_Pos (4U)
10989 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
10990 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
10991 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
10992 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
10993
10994 #define FMC_PCR_ECCEN_Pos (6U)
10995 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
10996 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
10997
10998 #define FMC_PCR_TCLR_Pos (9U)
10999 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
11000 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
11001 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
11002 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
11003 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
11004 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
11005
11006 #define FMC_PCR_TAR_Pos (13U)
11007 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
11008 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
11009 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
11010 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
11011 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
11012 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
11013
11014 #define FMC_PCR_ECCPS_Pos (17U)
11015 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
11016 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
11017 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
11018 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
11019 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
11020
11021 /******************* Bit definition for FMC_SR register *******************/
11022 #define FMC_SR_IRS_Pos (0U)
11023 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
11024 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
11025 #define FMC_SR_ILS_Pos (1U)
11026 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
11027 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
11028 #define FMC_SR_IFS_Pos (2U)
11029 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
11030 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
11031 #define FMC_SR_IREN_Pos (3U)
11032 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
11033 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
11034 #define FMC_SR_ILEN_Pos (4U)
11035 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
11036 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
11037 #define FMC_SR_IFEN_Pos (5U)
11038 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
11039 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
11040 #define FMC_SR_FEMPT_Pos (6U)
11041 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
11042 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
11043
11044 /****************** Bit definition for FMC_PMEM register ******************/
11045 #define FMC_PMEM_MEMSET_Pos (0U)
11046 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
11047 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
11048 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
11049 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
11050 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
11051 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
11052 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
11053 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
11054 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
11055 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
11056
11057 #define FMC_PMEM_MEMWAIT_Pos (8U)
11058 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
11059 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
11060 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
11061 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
11062 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
11063 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
11064 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
11065 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
11066 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
11067 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
11068
11069 #define FMC_PMEM_MEMHOLD_Pos (16U)
11070 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
11071 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
11072 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
11073 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
11074 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
11075 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
11076 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
11077 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
11078 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
11079 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
11080
11081 #define FMC_PMEM_MEMHIZ_Pos (24U)
11082 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
11083 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
11084 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
11085 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
11086 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
11087 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
11088 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
11089 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
11090 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
11091 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
11092
11093 /****************** Bit definition for FMC_PATT register ******************/
11094 #define FMC_PATT_ATTSET_Pos (0U)
11095 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
11096 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
11097 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
11098 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
11099 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
11100 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
11101 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
11102 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
11103 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
11104 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
11105
11106 #define FMC_PATT_ATTWAIT_Pos (8U)
11107 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
11108 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
11109 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
11110 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
11111 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
11112 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
11113 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
11114 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
11115 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
11116 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
11117
11118 #define FMC_PATT_ATTHOLD_Pos (16U)
11119 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
11120 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
11121 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
11122 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
11123 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
11124 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
11125 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
11126 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
11127 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
11128 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
11129
11130 #define FMC_PATT_ATTHIZ_Pos (24U)
11131 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
11132 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
11133 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
11134 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
11135 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
11136 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
11137 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
11138 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
11139 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
11140 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
11141
11142 /****************** Bit definition for FMC_ECCR3 register ******************/
11143 #define FMC_ECCR3_ECC3_Pos (0U)
11144 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
11145 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
11146
11147 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
11148 #define FMC_SDCRx_NC_Pos (0U)
11149 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
11150 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
11151 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
11152 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
11153
11154 #define FMC_SDCRx_NR_Pos (2U)
11155 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
11156 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
11157 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
11158 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
11159
11160 #define FMC_SDCRx_MWID_Pos (4U)
11161 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
11162 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
11163 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
11164 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
11165
11166 #define FMC_SDCRx_NB_Pos (6U)
11167 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
11168 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
11169
11170 #define FMC_SDCRx_CAS_Pos (7U)
11171 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
11172 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
11173 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
11174 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
11175
11176 #define FMC_SDCRx_WP_Pos (9U)
11177 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
11178 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
11179
11180 #define FMC_SDCRx_SDCLK_Pos (10U)
11181 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
11182 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
11183 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
11184 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
11185
11186 #define FMC_SDCRx_RBURST_Pos (12U)
11187 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
11188 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
11189
11190 #define FMC_SDCRx_RPIPE_Pos (13U)
11191 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
11192 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
11193 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
11194 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
11195
11196 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
11197 #define FMC_SDTRx_TMRD_Pos (0U)
11198 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
11199 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
11200 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
11201 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
11202 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
11203 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
11204
11205 #define FMC_SDTRx_TXSR_Pos (4U)
11206 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
11207 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
11208 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
11209 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
11210 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
11211 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
11212
11213 #define FMC_SDTRx_TRAS_Pos (8U)
11214 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
11215 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
11216 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
11217 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
11218 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
11219 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
11220
11221 #define FMC_SDTRx_TRC_Pos (12U)
11222 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
11223 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
11224 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
11225 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
11226 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
11227
11228 #define FMC_SDTRx_TWR_Pos (16U)
11229 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
11230 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
11231 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
11232 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
11233 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
11234
11235 #define FMC_SDTRx_TRP_Pos (20U)
11236 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
11237 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
11238 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
11239 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
11240 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
11241
11242 #define FMC_SDTRx_TRCD_Pos (24U)
11243 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
11244 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
11245 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
11246 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
11247 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
11248
11249 /****************** Bit definition for FMC_SDCMR register ******************/
11250 #define FMC_SDCMR_MODE_Pos (0U)
11251 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
11252 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
11253 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
11254 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
11255 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
11256
11257 #define FMC_SDCMR_CTB2_Pos (3U)
11258 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
11259 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
11260
11261 #define FMC_SDCMR_CTB1_Pos (4U)
11262 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
11263 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
11264
11265 #define FMC_SDCMR_NRFS_Pos (5U)
11266 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
11267 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
11268 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
11269 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
11270 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
11271 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
11272
11273 #define FMC_SDCMR_MRD_Pos (9U)
11274 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
11275 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
11276
11277 /****************** Bit definition for FMC_SDRTR register ******************/
11278 #define FMC_SDRTR_CRE_Pos (0U)
11279 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
11280 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
11281
11282 #define FMC_SDRTR_COUNT_Pos (1U)
11283 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
11284 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
11285
11286 #define FMC_SDRTR_REIE_Pos (14U)
11287 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
11288 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
11289
11290 /****************** Bit definition for FMC_SDSR register ******************/
11291 #define FMC_SDSR_RE_Pos (0U)
11292 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
11293 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
11294
11295 #define FMC_SDSR_MODES1_Pos (1U)
11296 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
11297 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
11298 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
11299 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
11300
11301 #define FMC_SDSR_MODES2_Pos (3U)
11302 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
11303 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
11304 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
11305 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
11306
11307 /******************************************************************************/
11308 /* */
11309 /* General Purpose I/O */
11310 /* */
11311 /******************************************************************************/
11312 /****************** Bits definition for GPIO_MODER register *****************/
11313 #define GPIO_MODER_MODE0_Pos (0U)
11314 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
11315 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
11316 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
11317 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
11318
11319 #define GPIO_MODER_MODE1_Pos (2U)
11320 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
11321 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
11322 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
11323 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
11324
11325 #define GPIO_MODER_MODE2_Pos (4U)
11326 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
11327 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
11328 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
11329 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
11330
11331 #define GPIO_MODER_MODE3_Pos (6U)
11332 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
11333 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
11334 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
11335 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
11336
11337 #define GPIO_MODER_MODE4_Pos (8U)
11338 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
11339 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
11340 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
11341 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
11342
11343 #define GPIO_MODER_MODE5_Pos (10U)
11344 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
11345 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
11346 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
11347 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
11348
11349 #define GPIO_MODER_MODE6_Pos (12U)
11350 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
11351 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
11352 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
11353 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
11354
11355 #define GPIO_MODER_MODE7_Pos (14U)
11356 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
11357 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
11358 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
11359 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
11360
11361 #define GPIO_MODER_MODE8_Pos (16U)
11362 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
11363 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
11364 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
11365 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
11366
11367 #define GPIO_MODER_MODE9_Pos (18U)
11368 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
11369 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
11370 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
11371 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
11372
11373 #define GPIO_MODER_MODE10_Pos (20U)
11374 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
11375 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
11376 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
11377 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
11378
11379 #define GPIO_MODER_MODE11_Pos (22U)
11380 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
11381 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
11382 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
11383 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
11384
11385 #define GPIO_MODER_MODE12_Pos (24U)
11386 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
11387 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
11388 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
11389 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
11390
11391 #define GPIO_MODER_MODE13_Pos (26U)
11392 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
11393 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
11394 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
11395 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
11396
11397 #define GPIO_MODER_MODE14_Pos (28U)
11398 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
11399 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
11400 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
11401 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
11402
11403 #define GPIO_MODER_MODE15_Pos (30U)
11404 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
11405 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
11406 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
11407 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
11408
11409 /****************** Bits definition for GPIO_OTYPER register ****************/
11410 #define GPIO_OTYPER_OT0_Pos (0U)
11411 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
11412 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
11413 #define GPIO_OTYPER_OT1_Pos (1U)
11414 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
11415 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
11416 #define GPIO_OTYPER_OT2_Pos (2U)
11417 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
11418 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
11419 #define GPIO_OTYPER_OT3_Pos (3U)
11420 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
11421 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
11422 #define GPIO_OTYPER_OT4_Pos (4U)
11423 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
11424 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
11425 #define GPIO_OTYPER_OT5_Pos (5U)
11426 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
11427 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
11428 #define GPIO_OTYPER_OT6_Pos (6U)
11429 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
11430 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
11431 #define GPIO_OTYPER_OT7_Pos (7U)
11432 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
11433 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
11434 #define GPIO_OTYPER_OT8_Pos (8U)
11435 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
11436 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
11437 #define GPIO_OTYPER_OT9_Pos (9U)
11438 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
11439 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
11440 #define GPIO_OTYPER_OT10_Pos (10U)
11441 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
11442 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
11443 #define GPIO_OTYPER_OT11_Pos (11U)
11444 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
11445 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
11446 #define GPIO_OTYPER_OT12_Pos (12U)
11447 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
11448 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
11449 #define GPIO_OTYPER_OT13_Pos (13U)
11450 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
11451 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
11452 #define GPIO_OTYPER_OT14_Pos (14U)
11453 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
11454 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
11455 #define GPIO_OTYPER_OT15_Pos (15U)
11456 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
11457 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
11458
11459 /****************** Bits definition for GPIO_OSPEEDR register ***************/
11460 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
11461 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
11462 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
11463 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
11464 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
11465
11466 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
11467 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
11468 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
11469 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
11470 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
11471
11472 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
11473 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
11474 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
11475 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
11476 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
11477
11478 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
11479 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
11480 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
11481 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
11482 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
11483
11484 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
11485 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
11486 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
11487 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
11488 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
11489
11490 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
11491 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
11492 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
11493 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
11494 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
11495
11496 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
11497 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
11498 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
11499 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
11500 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
11501
11502 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
11503 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
11504 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
11505 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
11506 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
11507
11508 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
11509 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
11510 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
11511 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
11512 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
11513
11514 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
11515 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
11516 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
11517 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
11518 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
11519
11520 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
11521 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
11522 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
11523 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
11524 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
11525
11526 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
11527 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
11528 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
11529 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
11530 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
11531
11532 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
11533 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
11534 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
11535 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
11536 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
11537
11538 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
11539 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
11540 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
11541 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
11542 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
11543
11544 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
11545 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
11546 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
11547 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
11548 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
11549
11550 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
11551 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
11552 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
11553 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
11554 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
11555
11556 /****************** Bits definition for GPIO_PUPDR register *****************/
11557 #define GPIO_PUPDR_PUPD0_Pos (0U)
11558 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
11559 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
11560 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
11561 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
11562
11563 #define GPIO_PUPDR_PUPD1_Pos (2U)
11564 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
11565 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
11566 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
11567 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
11568
11569 #define GPIO_PUPDR_PUPD2_Pos (4U)
11570 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
11571 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
11572 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
11573 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
11574
11575 #define GPIO_PUPDR_PUPD3_Pos (6U)
11576 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
11577 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
11578 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
11579 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
11580
11581 #define GPIO_PUPDR_PUPD4_Pos (8U)
11582 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
11583 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
11584 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
11585 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
11586
11587 #define GPIO_PUPDR_PUPD5_Pos (10U)
11588 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
11589 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
11590 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
11591 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
11592
11593 #define GPIO_PUPDR_PUPD6_Pos (12U)
11594 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
11595 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
11596 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
11597 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
11598
11599 #define GPIO_PUPDR_PUPD7_Pos (14U)
11600 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
11601 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
11602 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
11603 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
11604
11605 #define GPIO_PUPDR_PUPD8_Pos (16U)
11606 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
11607 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
11608 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
11609 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
11610
11611 #define GPIO_PUPDR_PUPD9_Pos (18U)
11612 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
11613 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
11614 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
11615 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
11616
11617 #define GPIO_PUPDR_PUPD10_Pos (20U)
11618 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
11619 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
11620 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
11621 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
11622
11623 #define GPIO_PUPDR_PUPD11_Pos (22U)
11624 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
11625 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
11626 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
11627 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
11628
11629 #define GPIO_PUPDR_PUPD12_Pos (24U)
11630 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
11631 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
11632 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
11633 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
11634
11635 #define GPIO_PUPDR_PUPD13_Pos (26U)
11636 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
11637 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
11638 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
11639 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
11640
11641 #define GPIO_PUPDR_PUPD14_Pos (28U)
11642 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
11643 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
11644 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
11645 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
11646
11647 #define GPIO_PUPDR_PUPD15_Pos (30U)
11648 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
11649 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
11650 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
11651 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
11652
11653 /****************** Bits definition for GPIO_IDR register *******************/
11654 #define GPIO_IDR_ID0_Pos (0U)
11655 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
11656 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
11657 #define GPIO_IDR_ID1_Pos (1U)
11658 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
11659 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
11660 #define GPIO_IDR_ID2_Pos (2U)
11661 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
11662 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
11663 #define GPIO_IDR_ID3_Pos (3U)
11664 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
11665 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
11666 #define GPIO_IDR_ID4_Pos (4U)
11667 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
11668 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
11669 #define GPIO_IDR_ID5_Pos (5U)
11670 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
11671 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
11672 #define GPIO_IDR_ID6_Pos (6U)
11673 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
11674 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
11675 #define GPIO_IDR_ID7_Pos (7U)
11676 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
11677 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
11678 #define GPIO_IDR_ID8_Pos (8U)
11679 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
11680 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
11681 #define GPIO_IDR_ID9_Pos (9U)
11682 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
11683 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
11684 #define GPIO_IDR_ID10_Pos (10U)
11685 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
11686 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
11687 #define GPIO_IDR_ID11_Pos (11U)
11688 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
11689 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
11690 #define GPIO_IDR_ID12_Pos (12U)
11691 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
11692 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
11693 #define GPIO_IDR_ID13_Pos (13U)
11694 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
11695 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
11696 #define GPIO_IDR_ID14_Pos (14U)
11697 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
11698 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
11699 #define GPIO_IDR_ID15_Pos (15U)
11700 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
11701 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
11702
11703 /****************** Bits definition for GPIO_ODR register *******************/
11704 #define GPIO_ODR_OD0_Pos (0U)
11705 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
11706 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
11707 #define GPIO_ODR_OD1_Pos (1U)
11708 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
11709 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
11710 #define GPIO_ODR_OD2_Pos (2U)
11711 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
11712 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
11713 #define GPIO_ODR_OD3_Pos (3U)
11714 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
11715 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
11716 #define GPIO_ODR_OD4_Pos (4U)
11717 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
11718 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
11719 #define GPIO_ODR_OD5_Pos (5U)
11720 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
11721 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
11722 #define GPIO_ODR_OD6_Pos (6U)
11723 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
11724 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
11725 #define GPIO_ODR_OD7_Pos (7U)
11726 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
11727 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
11728 #define GPIO_ODR_OD8_Pos (8U)
11729 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
11730 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
11731 #define GPIO_ODR_OD9_Pos (9U)
11732 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
11733 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
11734 #define GPIO_ODR_OD10_Pos (10U)
11735 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
11736 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
11737 #define GPIO_ODR_OD11_Pos (11U)
11738 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
11739 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
11740 #define GPIO_ODR_OD12_Pos (12U)
11741 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
11742 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
11743 #define GPIO_ODR_OD13_Pos (13U)
11744 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
11745 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
11746 #define GPIO_ODR_OD14_Pos (14U)
11747 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
11748 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
11749 #define GPIO_ODR_OD15_Pos (15U)
11750 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
11751 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
11752
11753 /****************** Bits definition for GPIO_BSRR register ******************/
11754 #define GPIO_BSRR_BS0_Pos (0U)
11755 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
11756 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
11757 #define GPIO_BSRR_BS1_Pos (1U)
11758 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
11759 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
11760 #define GPIO_BSRR_BS2_Pos (2U)
11761 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
11762 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
11763 #define GPIO_BSRR_BS3_Pos (3U)
11764 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
11765 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
11766 #define GPIO_BSRR_BS4_Pos (4U)
11767 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
11768 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
11769 #define GPIO_BSRR_BS5_Pos (5U)
11770 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
11771 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
11772 #define GPIO_BSRR_BS6_Pos (6U)
11773 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
11774 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
11775 #define GPIO_BSRR_BS7_Pos (7U)
11776 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
11777 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
11778 #define GPIO_BSRR_BS8_Pos (8U)
11779 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
11780 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
11781 #define GPIO_BSRR_BS9_Pos (9U)
11782 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
11783 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
11784 #define GPIO_BSRR_BS10_Pos (10U)
11785 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
11786 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
11787 #define GPIO_BSRR_BS11_Pos (11U)
11788 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
11789 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
11790 #define GPIO_BSRR_BS12_Pos (12U)
11791 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
11792 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
11793 #define GPIO_BSRR_BS13_Pos (13U)
11794 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
11795 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
11796 #define GPIO_BSRR_BS14_Pos (14U)
11797 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
11798 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
11799 #define GPIO_BSRR_BS15_Pos (15U)
11800 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
11801 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
11802 #define GPIO_BSRR_BR0_Pos (16U)
11803 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
11804 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
11805 #define GPIO_BSRR_BR1_Pos (17U)
11806 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
11807 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
11808 #define GPIO_BSRR_BR2_Pos (18U)
11809 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
11810 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
11811 #define GPIO_BSRR_BR3_Pos (19U)
11812 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
11813 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
11814 #define GPIO_BSRR_BR4_Pos (20U)
11815 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
11816 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
11817 #define GPIO_BSRR_BR5_Pos (21U)
11818 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
11819 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
11820 #define GPIO_BSRR_BR6_Pos (22U)
11821 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
11822 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
11823 #define GPIO_BSRR_BR7_Pos (23U)
11824 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
11825 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
11826 #define GPIO_BSRR_BR8_Pos (24U)
11827 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
11828 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
11829 #define GPIO_BSRR_BR9_Pos (25U)
11830 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
11831 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
11832 #define GPIO_BSRR_BR10_Pos (26U)
11833 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
11834 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
11835 #define GPIO_BSRR_BR11_Pos (27U)
11836 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
11837 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
11838 #define GPIO_BSRR_BR12_Pos (28U)
11839 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
11840 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
11841 #define GPIO_BSRR_BR13_Pos (29U)
11842 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
11843 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
11844 #define GPIO_BSRR_BR14_Pos (30U)
11845 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
11846 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
11847 #define GPIO_BSRR_BR15_Pos (31U)
11848 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
11849 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
11850
11851 /****************** Bit definition for GPIO_LCKR register *********************/
11852 #define GPIO_LCKR_LCK0_Pos (0U)
11853 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
11854 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
11855 #define GPIO_LCKR_LCK1_Pos (1U)
11856 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
11857 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
11858 #define GPIO_LCKR_LCK2_Pos (2U)
11859 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
11860 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
11861 #define GPIO_LCKR_LCK3_Pos (3U)
11862 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
11863 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
11864 #define GPIO_LCKR_LCK4_Pos (4U)
11865 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
11866 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
11867 #define GPIO_LCKR_LCK5_Pos (5U)
11868 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
11869 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
11870 #define GPIO_LCKR_LCK6_Pos (6U)
11871 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
11872 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
11873 #define GPIO_LCKR_LCK7_Pos (7U)
11874 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
11875 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
11876 #define GPIO_LCKR_LCK8_Pos (8U)
11877 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
11878 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
11879 #define GPIO_LCKR_LCK9_Pos (9U)
11880 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
11881 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
11882 #define GPIO_LCKR_LCK10_Pos (10U)
11883 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
11884 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
11885 #define GPIO_LCKR_LCK11_Pos (11U)
11886 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
11887 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
11888 #define GPIO_LCKR_LCK12_Pos (12U)
11889 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
11890 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
11891 #define GPIO_LCKR_LCK13_Pos (13U)
11892 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
11893 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
11894 #define GPIO_LCKR_LCK14_Pos (14U)
11895 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
11896 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
11897 #define GPIO_LCKR_LCK15_Pos (15U)
11898 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
11899 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
11900 #define GPIO_LCKR_LCKK_Pos (16U)
11901 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
11902 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
11903
11904 /****************** Bit definition for GPIO_AFRL register ********************/
11905 #define GPIO_AFRL_AFSEL0_Pos (0U)
11906 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
11907 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
11908 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
11909 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
11910 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
11911 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
11912 #define GPIO_AFRL_AFSEL1_Pos (4U)
11913 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
11914 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
11915 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
11916 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
11917 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
11918 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
11919 #define GPIO_AFRL_AFSEL2_Pos (8U)
11920 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
11921 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
11922 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
11923 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
11924 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
11925 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
11926 #define GPIO_AFRL_AFSEL3_Pos (12U)
11927 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
11928 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
11929 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
11930 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
11931 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
11932 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
11933 #define GPIO_AFRL_AFSEL4_Pos (16U)
11934 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
11935 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
11936 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
11937 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
11938 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
11939 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
11940 #define GPIO_AFRL_AFSEL5_Pos (20U)
11941 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
11942 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
11943 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
11944 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
11945 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
11946 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
11947 #define GPIO_AFRL_AFSEL6_Pos (24U)
11948 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
11949 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
11950 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
11951 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
11952 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
11953 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
11954 #define GPIO_AFRL_AFSEL7_Pos (28U)
11955 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
11956 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
11957 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
11958 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
11959 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
11960 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
11961
11962 /* Legacy defines */
11963 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
11964 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
11965 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
11966 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
11967 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
11968 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
11969 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
11970 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
11971
11972 /****************** Bit definition for GPIO_AFRH register ********************/
11973 #define GPIO_AFRH_AFSEL8_Pos (0U)
11974 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
11975 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
11976 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
11977 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
11978 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
11979 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
11980 #define GPIO_AFRH_AFSEL9_Pos (4U)
11981 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
11982 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
11983 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
11984 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
11985 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
11986 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
11987 #define GPIO_AFRH_AFSEL10_Pos (8U)
11988 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
11989 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
11990 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
11991 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
11992 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
11993 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
11994 #define GPIO_AFRH_AFSEL11_Pos (12U)
11995 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
11996 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
11997 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
11998 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
11999 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
12000 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
12001 #define GPIO_AFRH_AFSEL12_Pos (16U)
12002 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
12003 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
12004 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
12005 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
12006 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
12007 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
12008 #define GPIO_AFRH_AFSEL13_Pos (20U)
12009 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
12010 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
12011 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
12012 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
12013 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
12014 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
12015 #define GPIO_AFRH_AFSEL14_Pos (24U)
12016 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
12017 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
12018 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
12019 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
12020 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
12021 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
12022 #define GPIO_AFRH_AFSEL15_Pos (28U)
12023 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
12024 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
12025 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
12026 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
12027 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
12028 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
12029
12030 /* Legacy defines */
12031 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
12032 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
12033 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
12034 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
12035 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
12036 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
12037 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
12038 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
12039
12040 /******************************************************************************/
12041 /* */
12042 /* HSEM HW Semaphore */
12043 /* */
12044 /******************************************************************************/
12045 /******************** Bit definition for HSEM_R register ********************/
12046 #define HSEM_R_PROCID_Pos (0U)
12047 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
12048 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
12049 #define HSEM_R_COREID_Pos (8U)
12050 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
12051 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
12052 #define HSEM_R_LOCK_Pos (31U)
12053 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
12054 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
12055
12056 /******************** Bit definition for HSEM_RLR register ******************/
12057 #define HSEM_RLR_PROCID_Pos (0U)
12058 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
12059 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
12060 #define HSEM_RLR_COREID_Pos (8U)
12061 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
12062 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
12063 #define HSEM_RLR_LOCK_Pos (31U)
12064 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
12065 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
12066
12067 /******************** Bit definition for HSEM_C1IER register *****************/
12068 #define HSEM_C1IER_ISE0_Pos (0U)
12069 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
12070 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
12071 #define HSEM_C1IER_ISE1_Pos (1U)
12072 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
12073 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
12074 #define HSEM_C1IER_ISE2_Pos (2U)
12075 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
12076 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
12077 #define HSEM_C1IER_ISE3_Pos (3U)
12078 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
12079 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
12080 #define HSEM_C1IER_ISE4_Pos (4U)
12081 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
12082 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
12083 #define HSEM_C1IER_ISE5_Pos (5U)
12084 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
12085 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
12086 #define HSEM_C1IER_ISE6_Pos (6U)
12087 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
12088 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
12089 #define HSEM_C1IER_ISE7_Pos (7U)
12090 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
12091 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
12092 #define HSEM_C1IER_ISE8_Pos (8U)
12093 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
12094 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
12095 #define HSEM_C1IER_ISE9_Pos (9U)
12096 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
12097 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
12098 #define HSEM_C1IER_ISE10_Pos (10U)
12099 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
12100 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
12101 #define HSEM_C1IER_ISE11_Pos (11U)
12102 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
12103 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
12104 #define HSEM_C1IER_ISE12_Pos (12U)
12105 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
12106 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
12107 #define HSEM_C1IER_ISE13_Pos (13U)
12108 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
12109 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
12110 #define HSEM_C1IER_ISE14_Pos (14U)
12111 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
12112 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
12113 #define HSEM_C1IER_ISE15_Pos (15U)
12114 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
12115 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
12116 #define HSEM_C1IER_ISE16_Pos (16U)
12117 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
12118 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
12119 #define HSEM_C1IER_ISE17_Pos (17U)
12120 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
12121 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
12122 #define HSEM_C1IER_ISE18_Pos (18U)
12123 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
12124 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
12125 #define HSEM_C1IER_ISE19_Pos (19U)
12126 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
12127 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
12128 #define HSEM_C1IER_ISE20_Pos (20U)
12129 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
12130 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
12131 #define HSEM_C1IER_ISE21_Pos (21U)
12132 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
12133 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
12134 #define HSEM_C1IER_ISE22_Pos (22U)
12135 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
12136 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
12137 #define HSEM_C1IER_ISE23_Pos (23U)
12138 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
12139 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
12140 #define HSEM_C1IER_ISE24_Pos (24U)
12141 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
12142 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
12143 #define HSEM_C1IER_ISE25_Pos (25U)
12144 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
12145 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
12146 #define HSEM_C1IER_ISE26_Pos (26U)
12147 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
12148 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
12149 #define HSEM_C1IER_ISE27_Pos (27U)
12150 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
12151 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
12152 #define HSEM_C1IER_ISE28_Pos (28U)
12153 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
12154 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
12155 #define HSEM_C1IER_ISE29_Pos (29U)
12156 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
12157 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
12158 #define HSEM_C1IER_ISE30_Pos (30U)
12159 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
12160 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
12161 #define HSEM_C1IER_ISE31_Pos (31U)
12162 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
12163 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
12164
12165 /******************** Bit definition for HSEM_C1ICR register *****************/
12166 #define HSEM_C1ICR_ISC0_Pos (0U)
12167 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
12168 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
12169 #define HSEM_C1ICR_ISC1_Pos (1U)
12170 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
12171 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
12172 #define HSEM_C1ICR_ISC2_Pos (2U)
12173 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
12174 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
12175 #define HSEM_C1ICR_ISC3_Pos (3U)
12176 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
12177 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
12178 #define HSEM_C1ICR_ISC4_Pos (4U)
12179 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
12180 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
12181 #define HSEM_C1ICR_ISC5_Pos (5U)
12182 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
12183 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
12184 #define HSEM_C1ICR_ISC6_Pos (6U)
12185 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
12186 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
12187 #define HSEM_C1ICR_ISC7_Pos (7U)
12188 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
12189 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
12190 #define HSEM_C1ICR_ISC8_Pos (8U)
12191 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
12192 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
12193 #define HSEM_C1ICR_ISC9_Pos (9U)
12194 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
12195 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
12196 #define HSEM_C1ICR_ISC10_Pos (10U)
12197 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
12198 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
12199 #define HSEM_C1ICR_ISC11_Pos (11U)
12200 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
12201 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
12202 #define HSEM_C1ICR_ISC12_Pos (12U)
12203 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
12204 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
12205 #define HSEM_C1ICR_ISC13_Pos (13U)
12206 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
12207 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
12208 #define HSEM_C1ICR_ISC14_Pos (14U)
12209 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
12210 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
12211 #define HSEM_C1ICR_ISC15_Pos (15U)
12212 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
12213 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
12214 #define HSEM_C1ICR_ISC16_Pos (16U)
12215 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
12216 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
12217 #define HSEM_C1ICR_ISC17_Pos (17U)
12218 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
12219 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
12220 #define HSEM_C1ICR_ISC18_Pos (18U)
12221 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
12222 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
12223 #define HSEM_C1ICR_ISC19_Pos (19U)
12224 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
12225 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
12226 #define HSEM_C1ICR_ISC20_Pos (20U)
12227 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
12228 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
12229 #define HSEM_C1ICR_ISC21_Pos (21U)
12230 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
12231 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
12232 #define HSEM_C1ICR_ISC22_Pos (22U)
12233 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
12234 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
12235 #define HSEM_C1ICR_ISC23_Pos (23U)
12236 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
12237 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
12238 #define HSEM_C1ICR_ISC24_Pos (24U)
12239 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
12240 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
12241 #define HSEM_C1ICR_ISC25_Pos (25U)
12242 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
12243 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
12244 #define HSEM_C1ICR_ISC26_Pos (26U)
12245 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
12246 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
12247 #define HSEM_C1ICR_ISC27_Pos (27U)
12248 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
12249 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
12250 #define HSEM_C1ICR_ISC28_Pos (28U)
12251 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
12252 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
12253 #define HSEM_C1ICR_ISC29_Pos (29U)
12254 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
12255 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
12256 #define HSEM_C1ICR_ISC30_Pos (30U)
12257 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
12258 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
12259 #define HSEM_C1ICR_ISC31_Pos (31U)
12260 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
12261 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
12262
12263 /******************** Bit definition for HSEM_C1ISR register *****************/
12264 #define HSEM_C1ISR_ISF0_Pos (0U)
12265 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
12266 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
12267 #define HSEM_C1ISR_ISF1_Pos (1U)
12268 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
12269 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
12270 #define HSEM_C1ISR_ISF2_Pos (2U)
12271 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
12272 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
12273 #define HSEM_C1ISR_ISF3_Pos (3U)
12274 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
12275 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
12276 #define HSEM_C1ISR_ISF4_Pos (4U)
12277 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
12278 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
12279 #define HSEM_C1ISR_ISF5_Pos (5U)
12280 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
12281 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
12282 #define HSEM_C1ISR_ISF6_Pos (6U)
12283 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
12284 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
12285 #define HSEM_C1ISR_ISF7_Pos (7U)
12286 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
12287 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
12288 #define HSEM_C1ISR_ISF8_Pos (8U)
12289 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
12290 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
12291 #define HSEM_C1ISR_ISF9_Pos (9U)
12292 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
12293 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
12294 #define HSEM_C1ISR_ISF10_Pos (10U)
12295 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
12296 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
12297 #define HSEM_C1ISR_ISF11_Pos (11U)
12298 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
12299 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
12300 #define HSEM_C1ISR_ISF12_Pos (12U)
12301 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
12302 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
12303 #define HSEM_C1ISR_ISF13_Pos (13U)
12304 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
12305 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
12306 #define HSEM_C1ISR_ISF14_Pos (14U)
12307 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
12308 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
12309 #define HSEM_C1ISR_ISF15_Pos (15U)
12310 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
12311 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
12312 #define HSEM_C1ISR_ISF16_Pos (16U)
12313 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
12314 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
12315 #define HSEM_C1ISR_ISF17_Pos (17U)
12316 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
12317 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
12318 #define HSEM_C1ISR_ISF18_Pos (18U)
12319 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
12320 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
12321 #define HSEM_C1ISR_ISF19_Pos (19U)
12322 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
12323 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
12324 #define HSEM_C1ISR_ISF20_Pos (20U)
12325 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
12326 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
12327 #define HSEM_C1ISR_ISF21_Pos (21U)
12328 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
12329 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
12330 #define HSEM_C1ISR_ISF22_Pos (22U)
12331 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
12332 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
12333 #define HSEM_C1ISR_ISF23_Pos (23U)
12334 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
12335 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
12336 #define HSEM_C1ISR_ISF24_Pos (24U)
12337 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
12338 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
12339 #define HSEM_C1ISR_ISF25_Pos (25U)
12340 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
12341 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
12342 #define HSEM_C1ISR_ISF26_Pos (26U)
12343 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
12344 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
12345 #define HSEM_C1ISR_ISF27_Pos (27U)
12346 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
12347 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
12348 #define HSEM_C1ISR_ISF28_Pos (28U)
12349 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
12350 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
12351 #define HSEM_C1ISR_ISF29_Pos (29U)
12352 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
12353 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
12354 #define HSEM_C1ISR_ISF30_Pos (30U)
12355 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
12356 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
12357 #define HSEM_C1ISR_ISF31_Pos (31U)
12358 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
12359 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
12360
12361 /******************** Bit definition for HSEM_C1MISR register *****************/
12362 #define HSEM_C1MISR_MISF0_Pos (0U)
12363 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
12364 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
12365 #define HSEM_C1MISR_MISF1_Pos (1U)
12366 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
12367 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
12368 #define HSEM_C1MISR_MISF2_Pos (2U)
12369 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
12370 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
12371 #define HSEM_C1MISR_MISF3_Pos (3U)
12372 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
12373 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
12374 #define HSEM_C1MISR_MISF4_Pos (4U)
12375 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
12376 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
12377 #define HSEM_C1MISR_MISF5_Pos (5U)
12378 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
12379 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
12380 #define HSEM_C1MISR_MISF6_Pos (6U)
12381 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
12382 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
12383 #define HSEM_C1MISR_MISF7_Pos (7U)
12384 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
12385 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
12386 #define HSEM_C1MISR_MISF8_Pos (8U)
12387 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
12388 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
12389 #define HSEM_C1MISR_MISF9_Pos (9U)
12390 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
12391 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
12392 #define HSEM_C1MISR_MISF10_Pos (10U)
12393 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
12394 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
12395 #define HSEM_C1MISR_MISF11_Pos (11U)
12396 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
12397 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
12398 #define HSEM_C1MISR_MISF12_Pos (12U)
12399 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
12400 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
12401 #define HSEM_C1MISR_MISF13_Pos (13U)
12402 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
12403 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
12404 #define HSEM_C1MISR_MISF14_Pos (14U)
12405 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
12406 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
12407 #define HSEM_C1MISR_MISF15_Pos (15U)
12408 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
12409 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
12410 #define HSEM_C1MISR_MISF16_Pos (16U)
12411 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
12412 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
12413 #define HSEM_C1MISR_MISF17_Pos (17U)
12414 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
12415 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
12416 #define HSEM_C1MISR_MISF18_Pos (18U)
12417 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
12418 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
12419 #define HSEM_C1MISR_MISF19_Pos (19U)
12420 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
12421 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
12422 #define HSEM_C1MISR_MISF20_Pos (20U)
12423 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
12424 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
12425 #define HSEM_C1MISR_MISF21_Pos (21U)
12426 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
12427 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
12428 #define HSEM_C1MISR_MISF22_Pos (22U)
12429 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
12430 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
12431 #define HSEM_C1MISR_MISF23_Pos (23U)
12432 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
12433 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
12434 #define HSEM_C1MISR_MISF24_Pos (24U)
12435 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
12436 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
12437 #define HSEM_C1MISR_MISF25_Pos (25U)
12438 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
12439 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
12440 #define HSEM_C1MISR_MISF26_Pos (26U)
12441 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
12442 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
12443 #define HSEM_C1MISR_MISF27_Pos (27U)
12444 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
12445 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
12446 #define HSEM_C1MISR_MISF28_Pos (28U)
12447 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
12448 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
12449 #define HSEM_C1MISR_MISF29_Pos (29U)
12450 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
12451 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
12452 #define HSEM_C1MISR_MISF30_Pos (30U)
12453 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
12454 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
12455 #define HSEM_C1MISR_MISF31_Pos (31U)
12456 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
12457 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
12458
12459 /******************** Bit definition for HSEM_CR register *****************/
12460 #define HSEM_CR_COREID_Pos (8U)
12461 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
12462 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
12463 #define HSEM_CR_KEY_Pos (16U)
12464 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
12465 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
12466
12467 /******************** Bit definition for HSEM_KEYR register *****************/
12468 #define HSEM_KEYR_KEY_Pos (16U)
12469 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
12470 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
12471
12472 /******************************************************************************/
12473 /* */
12474 /* Inter-integrated Circuit Interface (I2C) */
12475 /* */
12476 /******************************************************************************/
12477 /******************* Bit definition for I2C_CR1 register *******************/
12478 #define I2C_CR1_PE_Pos (0U)
12479 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
12480 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
12481 #define I2C_CR1_TXIE_Pos (1U)
12482 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
12483 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
12484 #define I2C_CR1_RXIE_Pos (2U)
12485 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
12486 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
12487 #define I2C_CR1_ADDRIE_Pos (3U)
12488 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
12489 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
12490 #define I2C_CR1_NACKIE_Pos (4U)
12491 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
12492 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
12493 #define I2C_CR1_STOPIE_Pos (5U)
12494 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
12495 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
12496 #define I2C_CR1_TCIE_Pos (6U)
12497 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
12498 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
12499 #define I2C_CR1_ERRIE_Pos (7U)
12500 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
12501 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
12502 #define I2C_CR1_DNF_Pos (8U)
12503 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
12504 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
12505 #define I2C_CR1_ANFOFF_Pos (12U)
12506 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
12507 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
12508 #define I2C_CR1_TXDMAEN_Pos (14U)
12509 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
12510 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
12511 #define I2C_CR1_RXDMAEN_Pos (15U)
12512 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
12513 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
12514 #define I2C_CR1_SBC_Pos (16U)
12515 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
12516 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
12517 #define I2C_CR1_NOSTRETCH_Pos (17U)
12518 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
12519 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
12520 #define I2C_CR1_WUPEN_Pos (18U)
12521 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
12522 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
12523 #define I2C_CR1_GCEN_Pos (19U)
12524 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
12525 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
12526 #define I2C_CR1_SMBHEN_Pos (20U)
12527 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
12528 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
12529 #define I2C_CR1_SMBDEN_Pos (21U)
12530 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
12531 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
12532 #define I2C_CR1_ALERTEN_Pos (22U)
12533 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
12534 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
12535 #define I2C_CR1_PECEN_Pos (23U)
12536 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
12537 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
12538
12539 /****************** Bit definition for I2C_CR2 register ********************/
12540 #define I2C_CR2_SADD_Pos (0U)
12541 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
12542 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
12543 #define I2C_CR2_RD_WRN_Pos (10U)
12544 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
12545 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
12546 #define I2C_CR2_ADD10_Pos (11U)
12547 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
12548 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
12549 #define I2C_CR2_HEAD10R_Pos (12U)
12550 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
12551 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
12552 #define I2C_CR2_START_Pos (13U)
12553 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
12554 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
12555 #define I2C_CR2_STOP_Pos (14U)
12556 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
12557 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
12558 #define I2C_CR2_NACK_Pos (15U)
12559 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
12560 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
12561 #define I2C_CR2_NBYTES_Pos (16U)
12562 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
12563 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
12564 #define I2C_CR2_RELOAD_Pos (24U)
12565 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
12566 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
12567 #define I2C_CR2_AUTOEND_Pos (25U)
12568 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
12569 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
12570 #define I2C_CR2_PECBYTE_Pos (26U)
12571 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
12572 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
12573
12574 /******************* Bit definition for I2C_OAR1 register ******************/
12575 #define I2C_OAR1_OA1_Pos (0U)
12576 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
12577 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
12578 #define I2C_OAR1_OA1MODE_Pos (10U)
12579 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
12580 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
12581 #define I2C_OAR1_OA1EN_Pos (15U)
12582 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
12583 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
12584
12585 /******************* Bit definition for I2C_OAR2 register ******************/
12586 #define I2C_OAR2_OA2_Pos (1U)
12587 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
12588 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
12589 #define I2C_OAR2_OA2MSK_Pos (8U)
12590 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
12591 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
12592 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
12593 #define I2C_OAR2_OA2MASK01_Pos (8U)
12594 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
12595 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
12596 #define I2C_OAR2_OA2MASK02_Pos (9U)
12597 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
12598 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
12599 #define I2C_OAR2_OA2MASK03_Pos (8U)
12600 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
12601 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
12602 #define I2C_OAR2_OA2MASK04_Pos (10U)
12603 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
12604 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
12605 #define I2C_OAR2_OA2MASK05_Pos (8U)
12606 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
12607 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
12608 #define I2C_OAR2_OA2MASK06_Pos (9U)
12609 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
12610 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
12611 #define I2C_OAR2_OA2MASK07_Pos (8U)
12612 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
12613 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
12614 #define I2C_OAR2_OA2EN_Pos (15U)
12615 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
12616 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
12617
12618 /******************* Bit definition for I2C_TIMINGR register *******************/
12619 #define I2C_TIMINGR_SCLL_Pos (0U)
12620 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
12621 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
12622 #define I2C_TIMINGR_SCLH_Pos (8U)
12623 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
12624 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
12625 #define I2C_TIMINGR_SDADEL_Pos (16U)
12626 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
12627 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
12628 #define I2C_TIMINGR_SCLDEL_Pos (20U)
12629 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
12630 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
12631 #define I2C_TIMINGR_PRESC_Pos (28U)
12632 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
12633 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
12634
12635 /******************* Bit definition for I2C_TIMEOUTR register *******************/
12636 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
12637 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
12638 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
12639 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
12640 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
12641 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
12642 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
12643 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
12644 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
12645 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
12646 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
12647 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
12648 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
12649 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
12650 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
12651
12652 /****************** Bit definition for I2C_ISR register *********************/
12653 #define I2C_ISR_TXE_Pos (0U)
12654 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
12655 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
12656 #define I2C_ISR_TXIS_Pos (1U)
12657 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
12658 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
12659 #define I2C_ISR_RXNE_Pos (2U)
12660 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
12661 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
12662 #define I2C_ISR_ADDR_Pos (3U)
12663 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
12664 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
12665 #define I2C_ISR_NACKF_Pos (4U)
12666 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
12667 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
12668 #define I2C_ISR_STOPF_Pos (5U)
12669 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
12670 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
12671 #define I2C_ISR_TC_Pos (6U)
12672 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
12673 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
12674 #define I2C_ISR_TCR_Pos (7U)
12675 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
12676 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
12677 #define I2C_ISR_BERR_Pos (8U)
12678 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
12679 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
12680 #define I2C_ISR_ARLO_Pos (9U)
12681 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
12682 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
12683 #define I2C_ISR_OVR_Pos (10U)
12684 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
12685 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
12686 #define I2C_ISR_PECERR_Pos (11U)
12687 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
12688 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
12689 #define I2C_ISR_TIMEOUT_Pos (12U)
12690 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
12691 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
12692 #define I2C_ISR_ALERT_Pos (13U)
12693 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
12694 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
12695 #define I2C_ISR_BUSY_Pos (15U)
12696 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
12697 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
12698 #define I2C_ISR_DIR_Pos (16U)
12699 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
12700 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
12701 #define I2C_ISR_ADDCODE_Pos (17U)
12702 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
12703 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
12704
12705 /****************** Bit definition for I2C_ICR register *********************/
12706 #define I2C_ICR_ADDRCF_Pos (3U)
12707 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
12708 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
12709 #define I2C_ICR_NACKCF_Pos (4U)
12710 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
12711 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
12712 #define I2C_ICR_STOPCF_Pos (5U)
12713 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
12714 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
12715 #define I2C_ICR_BERRCF_Pos (8U)
12716 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
12717 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
12718 #define I2C_ICR_ARLOCF_Pos (9U)
12719 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
12720 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
12721 #define I2C_ICR_OVRCF_Pos (10U)
12722 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
12723 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
12724 #define I2C_ICR_PECCF_Pos (11U)
12725 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
12726 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
12727 #define I2C_ICR_TIMOUTCF_Pos (12U)
12728 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
12729 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
12730 #define I2C_ICR_ALERTCF_Pos (13U)
12731 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
12732 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
12733
12734 /****************** Bit definition for I2C_PECR register *********************/
12735 #define I2C_PECR_PEC_Pos (0U)
12736 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
12737 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
12738
12739 /****************** Bit definition for I2C_RXDR register *********************/
12740 #define I2C_RXDR_RXDATA_Pos (0U)
12741 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
12742 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
12743
12744 /****************** Bit definition for I2C_TXDR register *********************/
12745 #define I2C_TXDR_TXDATA_Pos (0U)
12746 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
12747 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
12748
12749 /******************************************************************************/
12750 /* */
12751 /* Independent WATCHDOG */
12752 /* */
12753 /******************************************************************************/
12754 /******************* Bit definition for IWDG_KR register ********************/
12755 #define IWDG_KR_KEY_Pos (0U)
12756 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
12757 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
12758
12759 /******************* Bit definition for IWDG_PR register ********************/
12760 #define IWDG_PR_PR_Pos (0U)
12761 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
12762 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
12763 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
12764 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
12765 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
12766
12767 /******************* Bit definition for IWDG_RLR register *******************/
12768 #define IWDG_RLR_RL_Pos (0U)
12769 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
12770 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
12771
12772 /******************* Bit definition for IWDG_SR register ********************/
12773 #define IWDG_SR_PVU_Pos (0U)
12774 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
12775 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
12776 #define IWDG_SR_RVU_Pos (1U)
12777 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
12778 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
12779 #define IWDG_SR_WVU_Pos (2U)
12780 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
12781 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
12782
12783 /******************* Bit definition for IWDG_KR register ********************/
12784 #define IWDG_WINR_WIN_Pos (0U)
12785 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
12786 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
12787
12788 /******************************************************************************/
12789 /* */
12790 /* MDMA */
12791 /* */
12792 /******************************************************************************/
12793 /******************** Bit definition for MDMA_GISR0 register ****************/
12794 #define MDMA_GISR0_GIF0_Pos (0U)
12795 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
12796 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
12797 #define MDMA_GISR0_GIF1_Pos (1U)
12798 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
12799 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
12800 #define MDMA_GISR0_GIF2_Pos (2U)
12801 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
12802 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
12803 #define MDMA_GISR0_GIF3_Pos (3U)
12804 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
12805 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
12806 #define MDMA_GISR0_GIF4_Pos (4U)
12807 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
12808 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
12809 #define MDMA_GISR0_GIF5_Pos (5U)
12810 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
12811 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
12812 #define MDMA_GISR0_GIF6_Pos (6U)
12813 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
12814 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
12815 #define MDMA_GISR0_GIF7_Pos (7U)
12816 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
12817 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
12818 #define MDMA_GISR0_GIF8_Pos (8U)
12819 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
12820 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
12821 #define MDMA_GISR0_GIF9_Pos (9U)
12822 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
12823 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
12824 #define MDMA_GISR0_GIF10_Pos (10U)
12825 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
12826 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
12827 #define MDMA_GISR0_GIF11_Pos (11U)
12828 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
12829 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
12830 #define MDMA_GISR0_GIF12_Pos (12U)
12831 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
12832 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
12833 #define MDMA_GISR0_GIF13_Pos (13U)
12834 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
12835 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
12836 #define MDMA_GISR0_GIF14_Pos (14U)
12837 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
12838 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
12839 #define MDMA_GISR0_GIF15_Pos (15U)
12840 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
12841 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
12842
12843 /******************** Bit definition for MDMA_CxISR register ****************/
12844 #define MDMA_CISR_TEIF_Pos (0U)
12845 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
12846 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
12847 #define MDMA_CISR_CTCIF_Pos (1U)
12848 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
12849 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
12850 #define MDMA_CISR_BRTIF_Pos (2U)
12851 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
12852 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
12853 #define MDMA_CISR_BTIF_Pos (3U)
12854 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
12855 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
12856 #define MDMA_CISR_TCIF_Pos (4U)
12857 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
12858 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
12859 #define MDMA_CISR_CRQA_Pos (16U)
12860 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
12861 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
12862
12863 /******************** Bit definition for MDMA_CxIFCR register ****************/
12864 #define MDMA_CIFCR_CTEIF_Pos (0U)
12865 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
12866 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
12867 #define MDMA_CIFCR_CCTCIF_Pos (1U)
12868 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
12869 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
12870 #define MDMA_CIFCR_CBRTIF_Pos (2U)
12871 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
12872 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
12873 #define MDMA_CIFCR_CBTIF_Pos (3U)
12874 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
12875 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
12876 #define MDMA_CIFCR_CLTCIF_Pos (4U)
12877 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
12878 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
12879
12880 /******************** Bit definition for MDMA_CxESR register ****************/
12881 #define MDMA_CESR_TEA_Pos (0U)
12882 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
12883 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
12884 #define MDMA_CESR_TED_Pos (7U)
12885 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
12886 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
12887 #define MDMA_CESR_TELD_Pos (8U)
12888 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
12889 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
12890 #define MDMA_CESR_TEMD_Pos (9U)
12891 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
12892 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
12893 #define MDMA_CESR_ASE_Pos (10U)
12894 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
12895 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
12896 #define MDMA_CESR_BSE_Pos (11U)
12897 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
12898 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
12899
12900 /******************** Bit definition for MDMA_CxCR register ****************/
12901 #define MDMA_CCR_EN_Pos (0U)
12902 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
12903 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
12904 #define MDMA_CCR_TEIE_Pos (1U)
12905 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
12906 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
12907 #define MDMA_CCR_CTCIE_Pos (2U)
12908 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
12909 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
12910 #define MDMA_CCR_BRTIE_Pos (3U)
12911 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
12912 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
12913 #define MDMA_CCR_BTIE_Pos (4U)
12914 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
12915 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
12916 #define MDMA_CCR_TCIE_Pos (5U)
12917 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
12918 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
12919 #define MDMA_CCR_PL_Pos (6U)
12920 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
12921 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
12922 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
12923 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
12924 #define MDMA_CCR_BEX_Pos (12U)
12925 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
12926 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
12927 #define MDMA_CCR_HEX_Pos (13U)
12928 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
12929 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
12930 #define MDMA_CCR_WEX_Pos (14U)
12931 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
12932 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
12933 #define MDMA_CCR_SWRQ_Pos (16U)
12934 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
12935 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
12936
12937 /******************** Bit definition for MDMA_CxTCR register ****************/
12938 #define MDMA_CTCR_SINC_Pos (0U)
12939 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
12940 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
12941 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
12942 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
12943 #define MDMA_CTCR_DINC_Pos (2U)
12944 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
12945 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
12946 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
12947 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
12948 #define MDMA_CTCR_SSIZE_Pos (4U)
12949 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
12950 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
12951 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
12952 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
12953 #define MDMA_CTCR_DSIZE_Pos (6U)
12954 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
12955 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
12956 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
12957 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
12958 #define MDMA_CTCR_SINCOS_Pos (8U)
12959 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
12960 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
12961 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
12962 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
12963 #define MDMA_CTCR_DINCOS_Pos (10U)
12964 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
12965 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
12966 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
12967 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
12968 #define MDMA_CTCR_SBURST_Pos (12U)
12969 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
12970 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
12971 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
12972 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
12973 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
12974 #define MDMA_CTCR_DBURST_Pos (15U)
12975 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
12976 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
12977 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
12978 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
12979 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
12980 #define MDMA_CTCR_TLEN_Pos (18U)
12981 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
12982 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
12983 #define MDMA_CTCR_PKE_Pos (25U)
12984 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
12985 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
12986 #define MDMA_CTCR_PAM_Pos (26U)
12987 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
12988 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
12989 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
12990 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
12991 #define MDMA_CTCR_TRGM_Pos (28U)
12992 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
12993 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
12994 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
12995 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
12996 #define MDMA_CTCR_SWRM_Pos (30U)
12997 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
12998 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
12999 #define MDMA_CTCR_BWM_Pos (31U)
13000 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
13001 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
13002
13003 /******************** Bit definition for MDMA_CxBNDTR register ****************/
13004 #define MDMA_CBNDTR_BNDT_Pos (0U)
13005 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
13006 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
13007 #define MDMA_CBNDTR_BRSUM_Pos (18U)
13008 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
13009 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
13010 #define MDMA_CBNDTR_BRDUM_Pos (19U)
13011 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
13012 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
13013 #define MDMA_CBNDTR_BRC_Pos (20U)
13014 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
13015 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
13016
13017 /******************** Bit definition for MDMA_CxSAR register ****************/
13018 #define MDMA_CSAR_SAR_Pos (0U)
13019 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
13020 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
13021
13022 /******************** Bit definition for MDMA_CxDAR register ****************/
13023 #define MDMA_CDAR_DAR_Pos (0U)
13024 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
13025 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
13026
13027 /******************** Bit definition for MDMA_CxBRUR ************************/
13028 #define MDMA_CBRUR_SUV_Pos (0U)
13029 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
13030 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
13031 #define MDMA_CBRUR_DUV_Pos (16U)
13032 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
13033 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
13034
13035 /******************** Bit definition for MDMA_CxLAR *************************/
13036 #define MDMA_CLAR_LAR_Pos (0U)
13037 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
13038 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
13039
13040 /******************** Bit definition for MDMA_CxTBR) ************************/
13041 #define MDMA_CTBR_TSEL_Pos (0U)
13042 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
13043 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
13044 #define MDMA_CTBR_SBUS_Pos (16U)
13045 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
13046 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
13047 #define MDMA_CTBR_DBUS_Pos (17U)
13048 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
13049 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
13050
13051 /******************** Bit definition for MDMA_CxMAR) ************************/
13052 #define MDMA_CMAR_MAR_Pos (0U)
13053 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
13054 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
13055
13056 /******************** Bit definition for MDMA_CxMDR) ************************/
13057 #define MDMA_CMDR_MDR_Pos (0U)
13058 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
13059 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
13060
13061 /******************************************************************************/
13062 /* */
13063 /* Operational Amplifier (OPAMP) */
13064 /* */
13065 /******************************************************************************/
13066 /********************* Bit definition for OPAMPx_CSR register ***************/
13067 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
13068 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
13069 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
13070 #define OPAMP_CSR_FORCEVP_Pos (1U)
13071 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13072 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13073
13074 #define OPAMP_CSR_VPSEL_Pos (2U)
13075 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
13076 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
13077 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
13078 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
13079
13080 #define OPAMP_CSR_VMSEL_Pos (5U)
13081 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
13082 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
13083 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
13084 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
13085
13086 #define OPAMP_CSR_OPAHSM_Pos (8U)
13087 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13088 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
13089 #define OPAMP_CSR_CALON_Pos (11U)
13090 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
13091 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
13092
13093 #define OPAMP_CSR_CALSEL_Pos (12U)
13094 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
13095 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
13096 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
13097 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
13098
13099 #define OPAMP_CSR_PGGAIN_Pos (14U)
13100 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13101 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
13102 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13103 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13104 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13105 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13106
13107 #define OPAMP_CSR_USERTRIM_Pos (18U)
13108 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13109 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
13110 #define OPAMP_CSR_TSTREF_Pos (29U)
13111 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
13112 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13113 #define OPAMP_CSR_CALOUT_Pos (30U)
13114 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
13115 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
13116
13117 /********************* Bit definition for OPAMP1_CSR register ***************/
13118 #define OPAMP1_CSR_OPAEN_Pos (0U)
13119 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
13120 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
13121 #define OPAMP1_CSR_FORCEVP_Pos (1U)
13122 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13123 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13124
13125 #define OPAMP1_CSR_VPSEL_Pos (2U)
13126 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
13127 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
13128 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
13129 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
13130
13131 #define OPAMP1_CSR_VMSEL_Pos (5U)
13132 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
13133 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
13134 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
13135 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
13136
13137 #define OPAMP1_CSR_OPAHSM_Pos (8U)
13138 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13139 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
13140 #define OPAMP1_CSR_CALON_Pos (11U)
13141 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
13142 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
13143
13144 #define OPAMP1_CSR_CALSEL_Pos (12U)
13145 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
13146 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
13147 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
13148 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
13149
13150 #define OPAMP1_CSR_PGGAIN_Pos (14U)
13151 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13152 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
13153 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13154 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13155 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13156 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13157
13158 #define OPAMP1_CSR_USERTRIM_Pos (18U)
13159 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13160 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
13161 #define OPAMP1_CSR_TSTREF_Pos (29U)
13162 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
13163 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13164 #define OPAMP1_CSR_CALOUT_Pos (30U)
13165 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
13166 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
13167
13168 /********************* Bit definition for OPAMP2_CSR register ***************/
13169 #define OPAMP2_CSR_OPAEN_Pos (0U)
13170 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
13171 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
13172 #define OPAMP2_CSR_FORCEVP_Pos (1U)
13173 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
13174 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
13175
13176 #define OPAMP2_CSR_VPSEL_Pos (2U)
13177 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
13178 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
13179 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
13180 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
13181
13182 #define OPAMP2_CSR_VMSEL_Pos (5U)
13183 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
13184 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
13185 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
13186 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
13187
13188 #define OPAMP2_CSR_OPAHSM_Pos (8U)
13189 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
13190 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
13191 #define OPAMP2_CSR_CALON_Pos (11U)
13192 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
13193 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
13194
13195 #define OPAMP2_CSR_CALSEL_Pos (12U)
13196 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
13197 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
13198 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
13199 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
13200
13201 #define OPAMP2_CSR_PGGAIN_Pos (14U)
13202 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
13203 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
13204 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
13205 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
13206 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
13207 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
13208
13209 #define OPAMP2_CSR_USERTRIM_Pos (18U)
13210 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
13211 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
13212 #define OPAMP2_CSR_TSTREF_Pos (29U)
13213 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
13214 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
13215 #define OPAMP2_CSR_CALOUT_Pos (30U)
13216 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
13217 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
13218
13219 /******************* Bit definition for OPAMP_OTR register ******************/
13220 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
13221 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13222 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13223 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
13224 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13225 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13226
13227 /******************* Bit definition for OPAMP1_OTR register ******************/
13228 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
13229 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13230 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13231 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
13232 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13233 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13234
13235 /******************* Bit definition for OPAMP2_OTR register ******************/
13236 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
13237 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
13238 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13239 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
13240 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
13241 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13242
13243 /******************* Bit definition for OPAMP_HSOTR register ****************/
13244 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
13245 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13246 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13247 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
13248 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13249 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13250
13251 /******************* Bit definition for OPAMP1_HSOTR register ****************/
13252 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
13253 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13254 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13255 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
13256 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13257 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13258
13259 /******************* Bit definition for OPAMP2_HSOTR register ****************/
13260 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
13261 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
13262 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
13263 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
13264 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
13265 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
13266
13267 /******************************************************************************/
13268 /* */
13269 /* Power Control */
13270 /* */
13271 /******************************************************************************/
13272 /************************* NUMBER OF POWER DOMAINS **************************/
13273 #define POWER_DOMAINS_NUMBER 3U /*!< 3 Domains */
13274
13275 /******************** Bit definition for PWR_CR1 register *******************/
13276 #define PWR_CR1_ALS_Pos (17U)
13277 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
13278 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
13279 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
13280 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
13281 #define PWR_CR1_AVDEN_Pos (16U)
13282 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
13283 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
13284 #define PWR_CR1_SVOS_Pos (14U)
13285 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
13286 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
13287 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
13288 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
13289 #define PWR_CR1_FLPS_Pos (9U)
13290 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
13291 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
13292 #define PWR_CR1_DBP_Pos (8U)
13293 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
13294 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
13295 #define PWR_CR1_PLS_Pos (5U)
13296 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
13297 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
13298 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
13299 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
13300 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
13301 #define PWR_CR1_PVDEN_Pos (4U)
13302 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
13303 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
13304 #define PWR_CR1_LPDS_Pos (0U)
13305 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
13306 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
13307
13308 /*!< PVD level configuration */
13309 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
13310 #define PWR_CR1_PLS_LEV1_Pos (5U)
13311 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
13312 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
13313 #define PWR_CR1_PLS_LEV2_Pos (6U)
13314 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
13315 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
13316 #define PWR_CR1_PLS_LEV3_Pos (5U)
13317 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
13318 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
13319 #define PWR_CR1_PLS_LEV4_Pos (7U)
13320 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
13321 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
13322 #define PWR_CR1_PLS_LEV5_Pos (5U)
13323 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
13324 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
13325 #define PWR_CR1_PLS_LEV6_Pos (6U)
13326 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
13327 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
13328 #define PWR_CR1_PLS_LEV7_Pos (5U)
13329 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
13330 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
13331
13332 /*!< AVD level configuration */
13333 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
13334 #define PWR_CR1_ALS_LEV1_Pos (17U)
13335 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
13336 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
13337 #define PWR_CR1_ALS_LEV2_Pos (18U)
13338 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
13339 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
13340 #define PWR_CR1_ALS_LEV3_Pos (17U)
13341 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
13342 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
13343
13344 /******************** Bit definition for PWR_CSR1 register ******************/
13345 #define PWR_CSR1_AVDO_Pos (16U)
13346 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
13347 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
13348 #define PWR_CSR1_ACTVOS_Pos (14U)
13349 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
13350 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
13351 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
13352 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
13353 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
13354 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
13355 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
13356 #define PWR_CSR1_PVDO_Pos (4U)
13357 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
13358 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
13359
13360 /******************** Bit definition for PWR_CR2 register *******************/
13361 #define PWR_CR2_TEMPH_Pos (23U)
13362 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
13363 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
13364 #define PWR_CR2_TEMPL_Pos (22U)
13365 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
13366 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
13367 #define PWR_CR2_VBATH_Pos (21U)
13368 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
13369 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
13370 #define PWR_CR2_VBATL_Pos (20U)
13371 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
13372 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
13373 #define PWR_CR2_BRRDY_Pos (16U)
13374 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
13375 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
13376 #define PWR_CR2_MONEN_Pos (4U)
13377 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
13378 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
13379 #define PWR_CR2_BREN_Pos (0U)
13380 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
13381 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
13382
13383 /******************** Bit definition for PWR_CR3 register *******************/
13384 #define PWR_CR3_USB33RDY_Pos (26U)
13385 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
13386 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
13387 #define PWR_CR3_USBREGEN_Pos (25U)
13388 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
13389 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
13390 #define PWR_CR3_USB33DEN_Pos (24U)
13391 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
13392 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
13393 #define PWR_CR3_VBRS_Pos (9U)
13394 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
13395 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
13396 #define PWR_CR3_VBE_Pos (8U)
13397 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
13398 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
13399 #define PWR_CR3_SCUEN_Pos (2U)
13400 #define PWR_CR3_SCUEN_Msk (0x1UL << PWR_CR3_SCUEN_Pos) /*!< 0x00000004 */
13401 #define PWR_CR3_SCUEN PWR_CR3_SCUEN_Msk /*!< Supply configuration update enable */
13402 #define PWR_CR3_LDOEN_Pos (1U)
13403 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
13404 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
13405 #define PWR_CR3_BYPASS_Pos (0U)
13406 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
13407 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
13408
13409 /******************** Bit definition for PWR_CPUCR register *****************/
13410 #define PWR_CPUCR_RUN_D3_Pos (11U)
13411 #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
13412 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
13413 #define PWR_CPUCR_CSSF_Pos (9U)
13414 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
13415 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
13416 #define PWR_CPUCR_SBF_D2_Pos (8U)
13417 #define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
13418 #define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
13419 #define PWR_CPUCR_SBF_D1_Pos (7U)
13420 #define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
13421 #define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
13422 #define PWR_CPUCR_SBF_Pos (6U)
13423 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
13424 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
13425 #define PWR_CPUCR_STOPF_Pos (5U)
13426 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
13427 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
13428 #define PWR_CPUCR_PDDS_D3_Pos (2U)
13429 #define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
13430 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
13431 #define PWR_CPUCR_PDDS_D2_Pos (1U)
13432 #define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
13433 #define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
13434 #define PWR_CPUCR_PDDS_D1_Pos (0U)
13435 #define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
13436 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
13437
13438
13439 /******************** Bit definition for PWR_D3CR register ******************/
13440 #define PWR_D3CR_VOS_Pos (14U)
13441 #define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
13442 #define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
13443 #define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
13444 #define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
13445 #define PWR_D3CR_VOSRDY_Pos (13U)
13446 #define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
13447 #define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
13448
13449 /****************** Bit definition for PWR_WKUPCR register ******************/
13450 #define PWR_WKUPCR_WKUPC6_Pos (5U)
13451 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
13452 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
13453 #define PWR_WKUPCR_WKUPC5_Pos (4U)
13454 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
13455 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
13456 #define PWR_WKUPCR_WKUPC4_Pos (3U)
13457 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
13458 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
13459 #define PWR_WKUPCR_WKUPC3_Pos (2U)
13460 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
13461 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
13462 #define PWR_WKUPCR_WKUPC2_Pos (1U)
13463 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
13464 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
13465 #define PWR_WKUPCR_WKUPC1_Pos (0U)
13466 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
13467 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
13468
13469 /******************** Bit definition for PWR_WKUPFR register ****************/
13470 #define PWR_WKUPFR_WKUPF6_Pos (5U)
13471 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
13472 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
13473 #define PWR_WKUPFR_WKUPF5_Pos (4U)
13474 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
13475 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
13476 #define PWR_WKUPFR_WKUPF4_Pos (3U)
13477 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
13478 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
13479 #define PWR_WKUPFR_WKUPF3_Pos (2U)
13480 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
13481 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
13482 #define PWR_WKUPFR_WKUPF2_Pos (1U)
13483 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
13484 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
13485 #define PWR_WKUPFR_WKUPF1_Pos (0U)
13486 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
13487 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
13488
13489 /****************** Bit definition for PWR_WKUPEPR register *****************/
13490 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
13491 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
13492 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
13493 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
13494 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
13495 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
13496 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
13497 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
13498 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
13499 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
13500 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
13501 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
13502 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
13503 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
13504 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
13505 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
13506 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
13507 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
13508 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
13509 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
13510 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
13511 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
13512 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
13513 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
13514 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
13515 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
13516 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
13517 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
13518 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
13519 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
13520 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
13521 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
13522 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
13523 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
13524 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
13525 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
13526 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
13527 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
13528 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
13529 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
13530 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
13531 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
13532 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
13533 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
13534 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
13535 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
13536 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
13537 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
13538 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
13539 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
13540 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
13541 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
13542 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
13543 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
13544 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
13545 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
13546 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
13547 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
13548 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
13549 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
13550 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
13551 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
13552 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
13553 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
13554 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
13555 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
13556 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
13557 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
13558 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
13559
13560 /******************************************************************************/
13561 /* */
13562 /* Reset and Clock Control */
13563 /* */
13564 /******************************************************************************/
13565 /******************************* RCC VERSION ********************************/
13566 #define RCC_VER_X
13567
13568 /******************** Bit definition for RCC_CR register ********************/
13569 #define RCC_CR_HSION_Pos (0U)
13570 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
13571 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
13572 #define RCC_CR_HSIKERON_Pos (1U)
13573 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
13574 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
13575 #define RCC_CR_HSIRDY_Pos (2U)
13576 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
13577 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
13578 #define RCC_CR_HSIDIV_Pos (3U)
13579 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
13580 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
13581 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
13582 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
13583 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
13584 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
13585
13586 #define RCC_CR_HSIDIVF_Pos (5U)
13587 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
13588 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
13589 #define RCC_CR_CSION_Pos (7U)
13590 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
13591 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
13592 #define RCC_CR_CSIRDY_Pos (8U)
13593 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
13594 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
13595 #define RCC_CR_CSIKERON_Pos (9U)
13596 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
13597 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
13598 #define RCC_CR_HSI48ON_Pos (12U)
13599 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
13600 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
13601 #define RCC_CR_HSI48RDY_Pos (13U)
13602 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
13603 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
13604
13605 #define RCC_CR_D1CKRDY_Pos (14U)
13606 #define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
13607 #define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
13608 #define RCC_CR_D2CKRDY_Pos (15U)
13609 #define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
13610 #define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
13611
13612 #define RCC_CR_HSEON_Pos (16U)
13613 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
13614 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
13615 #define RCC_CR_HSERDY_Pos (17U)
13616 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
13617 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
13618 #define RCC_CR_HSEBYP_Pos (18U)
13619 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
13620 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
13621 #define RCC_CR_CSSHSEON_Pos (19U)
13622 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
13623 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
13624
13625
13626 #define RCC_CR_PLL1ON_Pos (24U)
13627 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
13628 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
13629 #define RCC_CR_PLL1RDY_Pos (25U)
13630 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
13631 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
13632 #define RCC_CR_PLL2ON_Pos (26U)
13633 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
13634 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
13635 #define RCC_CR_PLL2RDY_Pos (27U)
13636 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
13637 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
13638 #define RCC_CR_PLL3ON_Pos (28U)
13639 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
13640 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
13641 #define RCC_CR_PLL3RDY_Pos (29U)
13642 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
13643 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
13644
13645 /*Legacy */
13646 #define RCC_CR_PLLON_Pos (24U)
13647 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
13648 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
13649 #define RCC_CR_PLLRDY_Pos (25U)
13650 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
13651 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
13652
13653 /******************** Bit definition for RCC_HSICFGR register ***************/
13654 /*!< HSICAL configuration */
13655 #define RCC_HSICFGR_HSICAL_Pos (0U)
13656 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
13657 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
13658 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
13659 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
13660 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
13661 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
13662 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
13663 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
13664 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
13665 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
13666 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
13667 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
13668 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
13669 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
13670
13671 /*!< HSITRIM configuration */
13672 #define RCC_HSICFGR_HSITRIM_Pos (24U)
13673 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
13674 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
13675 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
13676 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
13677 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
13678 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
13679 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
13680 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
13681 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
13682
13683
13684 /******************** Bit definition for RCC_CRRCR register *****************/
13685
13686 /*!< HSI48CAL configuration */
13687 #define RCC_CRRCR_HSI48CAL_Pos (0U)
13688 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
13689 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
13690 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
13691 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
13692 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
13693 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
13694 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
13695 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
13696 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
13697 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
13698 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
13699 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
13700
13701
13702 /******************** Bit definition for RCC_CSICFGR register *****************/
13703 /*!< CSICAL configuration */
13704 #define RCC_CSICFGR_CSICAL_Pos (0U)
13705 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
13706 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
13707 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
13708 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
13709 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
13710 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
13711 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
13712 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
13713 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
13714 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
13715
13716 /*!< CSITRIM configuration */
13717 #define RCC_CSICFGR_CSITRIM_Pos (24U)
13718 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
13719 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
13720 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
13721 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
13722 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
13723 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
13724 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
13725 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
13726
13727 /******************** Bit definition for RCC_CFGR register ******************/
13728 /*!< SW configuration */
13729 #define RCC_CFGR_SW_Pos (0U)
13730 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
13731 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
13732 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
13733 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
13734 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
13735
13736 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
13737 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
13738 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
13739 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
13740
13741 /*!< SWS configuration */
13742 #define RCC_CFGR_SWS_Pos (3U)
13743 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
13744 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
13745 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
13746 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
13747 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
13748
13749 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
13750 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
13751 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
13752 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
13753
13754 #define RCC_CFGR_STOPWUCK_Pos (6U)
13755 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
13756 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
13757
13758 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
13759 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
13760 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
13761
13762 /*!< RTCPRE configuration */
13763 #define RCC_CFGR_RTCPRE_Pos (8U)
13764 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
13765 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
13766 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
13767 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
13768 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
13769 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
13770 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
13771 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
13772
13773 /*!< HRTIMSEL configuration */
13774 #define RCC_CFGR_HRTIMSEL_Pos (14U)
13775 #define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
13776 #define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */
13777
13778 /*!< TIMPRE configuration */
13779 #define RCC_CFGR_TIMPRE_Pos (15U)
13780 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
13781 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
13782
13783 /*!< MCO1 configuration */
13784 #define RCC_CFGR_MCO1_Pos (22U)
13785 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
13786 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
13787 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
13788 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
13789 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
13790
13791 #define RCC_CFGR_MCO1PRE_Pos (18U)
13792 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
13793 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
13794 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
13795 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
13796 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
13797 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
13798
13799 #define RCC_CFGR_MCO2PRE_Pos (25U)
13800 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
13801 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
13802 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
13803 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
13804 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
13805 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
13806
13807 #define RCC_CFGR_MCO2_Pos (29U)
13808 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
13809 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
13810 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
13811 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
13812 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
13813
13814 /******************** Bit definition for RCC_D1CFGR register ******************/
13815 /*!< D1HPRE configuration */
13816 #define RCC_D1CFGR_HPRE_Pos (0U)
13817 #define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
13818 #define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
13819 #define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
13820 #define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
13821 #define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
13822 #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
13823
13824
13825 #define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
13826 #define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
13827 #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
13828 #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
13829 #define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
13830 #define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
13831 #define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
13832 #define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
13833 #define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
13834 #define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
13835 #define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
13836 #define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
13837 #define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
13838 #define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
13839 #define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
13840 #define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
13841 #define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
13842 #define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
13843 #define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
13844 #define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
13845 #define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
13846 #define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
13847 #define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
13848 #define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
13849 #define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
13850
13851 /*!< D1PPRE configuration */
13852 #define RCC_D1CFGR_D1PPRE_Pos (4U)
13853 #define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
13854 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
13855 #define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
13856 #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
13857 #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
13858
13859 #define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
13860 #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
13861 #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
13862 #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
13863 #define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
13864 #define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
13865 #define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
13866 #define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
13867 #define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
13868 #define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
13869 #define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
13870 #define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
13871 #define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
13872
13873 #define RCC_D1CFGR_D1CPRE_Pos (8U)
13874 #define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
13875 #define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
13876 #define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
13877 #define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
13878 #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
13879 #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
13880
13881 #define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
13882 #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
13883 #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
13884 #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
13885 #define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
13886 #define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
13887 #define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
13888 #define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
13889 #define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
13890 #define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
13891 #define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
13892 #define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
13893 #define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
13894 #define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
13895 #define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
13896 #define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
13897 #define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
13898 #define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
13899 #define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
13900 #define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
13901 #define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
13902 #define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
13903 #define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
13904 #define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
13905 #define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
13906
13907 /******************** Bit definition for RCC_D2CFGR register ******************/
13908 /*!< D2PPRE1 configuration */
13909 #define RCC_D2CFGR_D2PPRE1_Pos (4U)
13910 #define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
13911 #define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
13912 #define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
13913 #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
13914 #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
13915
13916 #define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
13917 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
13918 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
13919 #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
13920 #define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
13921 #define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
13922 #define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
13923 #define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
13924 #define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
13925 #define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
13926 #define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
13927 #define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
13928 #define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
13929
13930 /*!< D2PPRE2 configuration */
13931 #define RCC_D2CFGR_D2PPRE2_Pos (8U)
13932 #define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
13933 #define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
13934 #define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
13935 #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
13936 #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
13937
13938 #define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
13939 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
13940 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
13941 #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
13942 #define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
13943 #define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
13944 #define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
13945 #define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
13946 #define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
13947 #define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
13948 #define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
13949 #define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
13950 #define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
13951
13952 /******************** Bit definition for RCC_D3CFGR register ******************/
13953 /*!< D3PPRE configuration */
13954 #define RCC_D3CFGR_D3PPRE_Pos (4U)
13955 #define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
13956 #define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
13957 #define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
13958 #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
13959 #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
13960
13961 #define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
13962 #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
13963 #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
13964 #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
13965 #define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
13966 #define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
13967 #define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
13968 #define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
13969 #define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
13970 #define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
13971 #define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
13972 #define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
13973 #define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
13974
13975 /******************** Bit definition for RCC_PLLCKSELR register *************/
13976
13977 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
13978 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
13979 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
13980
13981 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
13982 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
13983 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
13984 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
13985 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
13986 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
13987 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
13988 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
13989 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
13990 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
13991
13992 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
13993 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
13994 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
13995 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
13996 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
13997 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
13998 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
13999 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
14000 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
14001
14002 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
14003 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
14004 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
14005 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
14006 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
14007 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
14008 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
14009 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
14010 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
14011
14012 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
14013 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
14014 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
14015 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
14016 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
14017 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
14018 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
14019 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
14020 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
14021
14022 /******************** Bit definition for RCC_PLLCFGR register ***************/
14023
14024 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
14025 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
14026 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
14027 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
14028 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
14029 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
14030 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
14031 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14032 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
14033 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
14034 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
14035 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
14036 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
14037
14038 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
14039 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
14040 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
14041 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
14042 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
14043 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
14044 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
14045 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
14046 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
14047 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
14048 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
14049 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
14050 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
14051
14052 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
14053 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
14054 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
14055 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
14056 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
14057 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
14058 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
14059 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
14060 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
14061 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
14062 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
14063 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
14064 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
14065
14066 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
14067 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
14068 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
14069 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
14070 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
14071 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
14072 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
14073 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
14074 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
14075
14076 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
14077 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
14078 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
14079 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
14080 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
14081 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
14082 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
14083 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
14084 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
14085
14086 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
14087 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
14088 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
14089 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
14090 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
14091 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
14092 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
14093 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
14094 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
14095
14096
14097 /******************** Bit definition for RCC_PLL1DIVR register ***************/
14098 #define RCC_PLL1DIVR_N1_Pos (0U)
14099 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
14100 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
14101 #define RCC_PLL1DIVR_P1_Pos (9U)
14102 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
14103 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
14104 #define RCC_PLL1DIVR_Q1_Pos (16U)
14105 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
14106 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
14107 #define RCC_PLL1DIVR_R1_Pos (24U)
14108 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
14109 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
14110
14111 /******************** Bit definition for RCC_PLL1FRACR register ***************/
14112 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
14113 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
14114 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
14115
14116 /******************** Bit definition for RCC_PLL2DIVR register ***************/
14117 #define RCC_PLL2DIVR_N2_Pos (0U)
14118 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
14119 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
14120 #define RCC_PLL2DIVR_P2_Pos (9U)
14121 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
14122 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
14123 #define RCC_PLL2DIVR_Q2_Pos (16U)
14124 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
14125 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
14126 #define RCC_PLL2DIVR_R2_Pos (24U)
14127 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
14128 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
14129
14130 /******************** Bit definition for RCC_PLL2FRACR register ***************/
14131 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
14132 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
14133 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
14134
14135 /******************** Bit definition for RCC_PLL3DIVR register ***************/
14136 #define RCC_PLL3DIVR_N3_Pos (0U)
14137 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
14138 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
14139 #define RCC_PLL3DIVR_P3_Pos (9U)
14140 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
14141 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
14142 #define RCC_PLL3DIVR_Q3_Pos (16U)
14143 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
14144 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
14145 #define RCC_PLL3DIVR_R3_Pos (24U)
14146 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
14147 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
14148
14149 /******************** Bit definition for RCC_PLL3FRACR register ***************/
14150 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
14151 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
14152 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
14153
14154 /******************** Bit definition for RCC_D1CCIPR register ***************/
14155 #define RCC_D1CCIPR_FMCSEL_Pos (0U)
14156 #define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
14157 #define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
14158 #define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
14159 #define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
14160 #define RCC_D1CCIPR_QSPISEL_Pos (4U)
14161 #define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
14162 #define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
14163 #define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
14164 #define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
14165 #define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
14166 #define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
14167 #define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
14168 #define RCC_D1CCIPR_CKPERSEL_Pos (28U)
14169 #define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
14170 #define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
14171 #define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
14172 #define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
14173
14174 /******************** Bit definition for RCC_D2CCIP1R register ***************/
14175 #define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
14176 #define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
14177 #define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
14178 #define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
14179 #define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
14180 #define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
14181
14182 #define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
14183 #define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
14184 #define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
14185 #define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
14186 #define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
14187 #define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
14188
14189 #define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
14190 #define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
14191 #define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
14192 #define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
14193 #define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
14194 #define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
14195
14196 #define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
14197 #define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
14198 #define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
14199 #define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
14200 #define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
14201 #define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
14202
14203 #define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
14204 #define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
14205 #define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
14206 #define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
14207 #define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
14208
14209 #define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
14210 #define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
14211 #define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
14212
14213 #define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
14214 #define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
14215 #define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
14216 #define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
14217 #define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
14218
14219 #define RCC_D2CCIP1R_SWPSEL_Pos (31U)
14220 #define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
14221 #define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
14222
14223 /******************** Bit definition for RCC_D2CCIP2R register ***************/
14224 #define RCC_D2CCIP2R_USART16SEL_Pos (3U)
14225 #define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
14226 #define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
14227 #define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
14228 #define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
14229 #define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
14230
14231 #define RCC_D2CCIP2R_USART28SEL_Pos (0U)
14232 #define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
14233 #define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
14234 #define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
14235 #define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
14236 #define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
14237
14238 #define RCC_D2CCIP2R_RNGSEL_Pos (8U)
14239 #define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
14240 #define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
14241 #define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
14242 #define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
14243
14244 #define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
14245 #define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
14246 #define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
14247 #define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
14248 #define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
14249
14250 #define RCC_D2CCIP2R_USBSEL_Pos (20U)
14251 #define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
14252 #define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
14253 #define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
14254 #define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
14255
14256 #define RCC_D2CCIP2R_CECSEL_Pos (22U)
14257 #define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
14258 #define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
14259 #define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
14260 #define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
14261
14262 #define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
14263 #define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
14264 #define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
14265 #define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
14266 #define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
14267 #define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
14268
14269 /******************** Bit definition for RCC_D3CCIPR register ***************/
14270 #define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
14271 #define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
14272 #define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
14273 #define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
14274 #define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
14275 #define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
14276
14277 #define RCC_D3CCIPR_I2C4SEL_Pos (8U)
14278 #define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
14279 #define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
14280 #define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
14281 #define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
14282
14283 #define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
14284 #define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
14285 #define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
14286 #define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
14287 #define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
14288 #define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
14289
14290 #define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
14291 #define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
14292 #define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
14293 #define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
14294 #define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
14295 #define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
14296
14297 #define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
14298 #define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
14299 #define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
14300 #define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
14301 #define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
14302 #define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
14303
14304 #define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
14305 #define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
14306 #define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
14307 #define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
14308 #define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
14309 #define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
14310
14311 #define RCC_D3CCIPR_ADCSEL_Pos (16U)
14312 #define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
14313 #define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
14314 #define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
14315 #define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
14316
14317 #define RCC_D3CCIPR_SPI6SEL_Pos (28U)
14318 #define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
14319 #define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
14320 #define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
14321 #define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
14322 #define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
14323 /******************** Bit definition for RCC_CIER register ******************/
14324 #define RCC_CIER_LSIRDYIE_Pos (0U)
14325 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
14326 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
14327 #define RCC_CIER_LSERDYIE_Pos (1U)
14328 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
14329 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
14330 #define RCC_CIER_HSIRDYIE_Pos (2U)
14331 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
14332 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
14333 #define RCC_CIER_HSERDYIE_Pos (3U)
14334 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
14335 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
14336 #define RCC_CIER_CSIRDYIE_Pos (4U)
14337 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
14338 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
14339 #define RCC_CIER_HSI48RDYIE_Pos (5U)
14340 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
14341 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
14342 #define RCC_CIER_PLL1RDYIE_Pos (6U)
14343 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
14344 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
14345 #define RCC_CIER_PLL2RDYIE_Pos (7U)
14346 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
14347 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
14348 #define RCC_CIER_PLL3RDYIE_Pos (8U)
14349 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
14350 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
14351 #define RCC_CIER_LSECSSIE_Pos (9U)
14352 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
14353 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
14354
14355 /******************** Bit definition for RCC_CIFR register ******************/
14356 #define RCC_CIFR_LSIRDYF_Pos (0U)
14357 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
14358 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
14359 #define RCC_CIFR_LSERDYF_Pos (1U)
14360 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
14361 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
14362 #define RCC_CIFR_HSIRDYF_Pos (2U)
14363 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
14364 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
14365 #define RCC_CIFR_HSERDYF_Pos (3U)
14366 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
14367 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
14368 #define RCC_CIFR_CSIRDYF_Pos (4U)
14369 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
14370 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
14371 #define RCC_CIFR_HSI48RDYF_Pos (5U)
14372 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
14373 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
14374 #define RCC_CIFR_PLLRDYF_Pos (6U)
14375 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
14376 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
14377 #define RCC_CIFR_PLL2RDYF_Pos (7U)
14378 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
14379 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
14380 #define RCC_CIFR_PLL3RDYF_Pos (8U)
14381 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
14382 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
14383 #define RCC_CIFR_LSECSSF_Pos (9U)
14384 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
14385 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
14386 #define RCC_CIFR_HSECSSF_Pos (10U)
14387 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
14388 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
14389
14390 /******************** Bit definition for RCC_CICR register ******************/
14391 #define RCC_CICR_LSIRDYC_Pos (0U)
14392 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
14393 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
14394 #define RCC_CICR_LSERDYC_Pos (1U)
14395 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
14396 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
14397 #define RCC_CICR_HSIRDYC_Pos (2U)
14398 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
14399 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
14400 #define RCC_CICR_HSERDYC_Pos (3U)
14401 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
14402 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
14403 #define RCC_CICR_CSIRDYC_Pos (4U)
14404 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
14405 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
14406 #define RCC_CICR_HSI48RDYC_Pos (5U)
14407 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
14408 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
14409 #define RCC_CICR_PLLRDYC_Pos (6U)
14410 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
14411 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
14412 #define RCC_CICR_PLL2RDYC_Pos (7U)
14413 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
14414 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
14415 #define RCC_CICR_PLL3RDYC_Pos (8U)
14416 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
14417 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
14418 #define RCC_CICR_LSECSSC_Pos (9U)
14419 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
14420 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
14421 #define RCC_CICR_HSECSSC_Pos (10U)
14422 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
14423 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
14424
14425 /******************** Bit definition for RCC_BDCR register ******************/
14426 #define RCC_BDCR_LSEON_Pos (0U)
14427 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
14428 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
14429 #define RCC_BDCR_LSERDY_Pos (1U)
14430 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
14431 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
14432 #define RCC_BDCR_LSEBYP_Pos (2U)
14433 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
14434 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
14435
14436 #define RCC_BDCR_LSEDRV_Pos (3U)
14437 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
14438 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
14439 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
14440 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
14441
14442 #define RCC_BDCR_LSECSSON_Pos (5U)
14443 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
14444 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
14445 #define RCC_BDCR_LSECSSD_Pos (6U)
14446 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
14447 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
14448
14449 #define RCC_BDCR_RTCSEL_Pos (8U)
14450 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
14451 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
14452 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
14453 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
14454
14455 #define RCC_BDCR_RTCEN_Pos (15U)
14456 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
14457 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
14458 #define RCC_BDCR_BDRST_Pos (16U)
14459 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
14460 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
14461 /******************** Bit definition for RCC_CSR register *******************/
14462 #define RCC_CSR_LSION_Pos (0U)
14463 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
14464 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
14465 #define RCC_CSR_LSIRDY_Pos (1U)
14466 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
14467 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
14468
14469
14470 /******************** Bit definition for RCC_AHB3ENR register **************/
14471 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
14472 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
14473 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
14474 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
14475 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
14476 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
14477 #define RCC_AHB3ENR_FMCEN_Pos (12U)
14478 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
14479 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
14480 #define RCC_AHB3ENR_QSPIEN_Pos (14U)
14481 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
14482 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
14483 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
14484 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
14485 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
14486
14487 /******************** Bit definition for RCC_AHB1ENR register ***************/
14488 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
14489 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
14490 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
14491 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
14492 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
14493 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
14494 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
14495 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
14496 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
14497 #define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
14498 #define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
14499 #define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
14500 #define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
14501 #define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
14502 #define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
14503 #define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
14504 #define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
14505 #define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
14506 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
14507 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
14508 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
14509 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
14510 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
14511 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
14512 #define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
14513 #define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
14514 #define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
14515 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
14516 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
14517 #define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
14518
14519 /* Legacy define */
14520 #define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
14521 #define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
14522 #define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
14523 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
14524 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
14525 #define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
14526
14527
14528 /******************** Bit definition for RCC_AHB2ENR register ***************/
14529 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
14530 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
14531 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
14532 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
14533 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
14534 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
14535 #define RCC_AHB2ENR_HASHEN_Pos (5U)
14536 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
14537 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
14538 #define RCC_AHB2ENR_RNGEN_Pos (6U)
14539 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
14540 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
14541 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
14542 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
14543 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
14544 #define RCC_AHB2ENR_SRAM1EN_Pos (29U)
14545 #define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */
14546 #define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
14547 #define RCC_AHB2ENR_SRAM2EN_Pos (30U)
14548 #define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
14549 #define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
14550 #define RCC_AHB2ENR_SRAM3EN_Pos (31U)
14551 #define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) /*!< 0x80000000 */
14552 #define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
14553
14554 /* Legacy define */
14555 #define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
14556 #define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
14557 #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
14558 #define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
14559 #define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
14560 #define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
14561 #define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
14562 #define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
14563 #define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
14564
14565 /******************** Bit definition for RCC_AHB4ENR register ******************/
14566 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
14567 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
14568 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
14569 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
14570 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
14571 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
14572 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
14573 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
14574 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
14575 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
14576 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
14577 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
14578 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
14579 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
14580 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
14581 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
14582 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
14583 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
14584 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
14585 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
14586 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
14587 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
14588 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
14589 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
14590 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
14591 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
14592 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
14593 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
14594 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
14595 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
14596 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
14597 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
14598 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
14599 #define RCC_AHB4ENR_CRCEN_Pos (19U)
14600 #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
14601 #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
14602 #define RCC_AHB4ENR_BDMAEN_Pos (21U)
14603 #define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
14604 #define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
14605 #define RCC_AHB4ENR_ADC3EN_Pos (24U)
14606 #define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
14607 #define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
14608 #define RCC_AHB4ENR_HSEMEN_Pos (25U)
14609 #define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
14610 #define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
14611 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
14612 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
14613 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
14614
14615 /******************** Bit definition for RCC_APB3ENR register ******************/
14616 #define RCC_APB3ENR_WWDG1EN_Pos (6U)
14617 #define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
14618 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
14619
14620 /******************** Bit definition for RCC_APB1LENR register ******************/
14621
14622 #define RCC_APB1LENR_TIM2EN_Pos (0U)
14623 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
14624 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
14625 #define RCC_APB1LENR_TIM3EN_Pos (1U)
14626 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
14627 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
14628 #define RCC_APB1LENR_TIM4EN_Pos (2U)
14629 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
14630 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
14631 #define RCC_APB1LENR_TIM5EN_Pos (3U)
14632 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
14633 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
14634 #define RCC_APB1LENR_TIM6EN_Pos (4U)
14635 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
14636 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
14637 #define RCC_APB1LENR_TIM7EN_Pos (5U)
14638 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
14639 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
14640 #define RCC_APB1LENR_TIM12EN_Pos (6U)
14641 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
14642 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
14643 #define RCC_APB1LENR_TIM13EN_Pos (7U)
14644 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
14645 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
14646 #define RCC_APB1LENR_TIM14EN_Pos (8U)
14647 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
14648 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
14649 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
14650 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
14651 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
14652
14653
14654 #define RCC_APB1LENR_SPI2EN_Pos (14U)
14655 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
14656 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
14657 #define RCC_APB1LENR_SPI3EN_Pos (15U)
14658 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
14659 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
14660 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
14661 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
14662 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
14663 #define RCC_APB1LENR_USART2EN_Pos (17U)
14664 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
14665 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
14666 #define RCC_APB1LENR_USART3EN_Pos (18U)
14667 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
14668 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
14669 #define RCC_APB1LENR_UART4EN_Pos (19U)
14670 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
14671 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
14672 #define RCC_APB1LENR_UART5EN_Pos (20U)
14673 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
14674 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
14675 #define RCC_APB1LENR_I2C1EN_Pos (21U)
14676 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
14677 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
14678 #define RCC_APB1LENR_I2C2EN_Pos (22U)
14679 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
14680 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
14681 #define RCC_APB1LENR_I2C3EN_Pos (23U)
14682 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
14683 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
14684 #define RCC_APB1LENR_CECEN_Pos (27U)
14685 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
14686 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
14687 #define RCC_APB1LENR_DAC12EN_Pos (29U)
14688 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
14689 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
14690 #define RCC_APB1LENR_UART7EN_Pos (30U)
14691 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
14692 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
14693 #define RCC_APB1LENR_UART8EN_Pos (31U)
14694 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
14695 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
14696
14697 /* Legacy define */
14698 #define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
14699 #define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
14700 #define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
14701 /******************** Bit definition for RCC_APB1HENR register ******************/
14702 #define RCC_APB1HENR_CRSEN_Pos (1U)
14703 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
14704 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
14705 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
14706 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
14707 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
14708 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
14709 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
14710 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
14711 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
14712 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
14713 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
14714 #define RCC_APB1HENR_FDCANEN_Pos (8U)
14715 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
14716 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
14717
14718 /******************** Bit definition for RCC_APB2ENR register ******************/
14719 #define RCC_APB2ENR_TIM1EN_Pos (0U)
14720 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
14721 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
14722 #define RCC_APB2ENR_TIM8EN_Pos (1U)
14723 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14724 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14725 #define RCC_APB2ENR_USART1EN_Pos (4U)
14726 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14727 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14728 #define RCC_APB2ENR_USART6EN_Pos (5U)
14729 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14730 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14731 #define RCC_APB2ENR_SPI1EN_Pos (12U)
14732 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14733 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14734 #define RCC_APB2ENR_SPI4EN_Pos (13U)
14735 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14736 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14737 #define RCC_APB2ENR_TIM15EN_Pos (16U)
14738 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
14739 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
14740 #define RCC_APB2ENR_TIM16EN_Pos (17U)
14741 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
14742 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
14743 #define RCC_APB2ENR_TIM17EN_Pos (18U)
14744 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
14745 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
14746 #define RCC_APB2ENR_SPI5EN_Pos (20U)
14747 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14748 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14749 #define RCC_APB2ENR_SAI1EN_Pos (22U)
14750 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14751 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14752 #define RCC_APB2ENR_SAI2EN_Pos (23U)
14753 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
14754 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
14755 #define RCC_APB2ENR_SAI3EN_Pos (24U)
14756 #define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
14757 #define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
14758 #define RCC_APB2ENR_DFSDM1EN_Pos (28U)
14759 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
14760 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
14761 #define RCC_APB2ENR_HRTIMEN_Pos (29U)
14762 #define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
14763 #define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
14764
14765 /******************** Bit definition for RCC_APB4ENR register ******************/
14766 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
14767 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
14768 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
14769 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
14770 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
14771 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
14772 #define RCC_APB4ENR_SPI6EN_Pos (5U)
14773 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
14774 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
14775 #define RCC_APB4ENR_I2C4EN_Pos (7U)
14776 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
14777 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
14778 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
14779 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
14780 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
14781 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
14782 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
14783 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
14784 #define RCC_APB4ENR_LPTIM4EN_Pos (11U)
14785 #define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
14786 #define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
14787 #define RCC_APB4ENR_LPTIM5EN_Pos (12U)
14788 #define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
14789 #define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
14790 #define RCC_APB4ENR_COMP12EN_Pos (14U)
14791 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
14792 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
14793 #define RCC_APB4ENR_VREFEN_Pos (15U)
14794 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
14795 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
14796 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
14797 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
14798 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
14799 #define RCC_APB4ENR_SAI4EN_Pos (21U)
14800 #define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
14801 #define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
14802
14803
14804 /******************** Bit definition for RCC_AHB3RSTR register ***************/
14805 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
14806 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
14807 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
14808 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
14809 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
14810 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
14811 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
14812 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
14813 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14814 #define RCC_AHB3RSTR_QSPIRST_Pos (14U)
14815 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
14816 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
14817 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
14818 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
14819 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
14820
14821
14822 /******************** Bit definition for RCC_AHB1RSTR register ***************/
14823 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
14824 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
14825 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14826 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
14827 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
14828 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14829 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
14830 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
14831 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
14832 #define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
14833 #define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
14834 #define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
14835 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
14836 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
14837 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
14838 #define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
14839 #define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
14840 #define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
14841
14842 /* Legacy define */
14843 #define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
14844 #define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
14845 #define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
14846
14847 /******************** Bit definition for RCC_AHB2RSTR register ***************/
14848 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
14849 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
14850 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
14851 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14852 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
14853 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14854 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
14855 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
14856 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14857 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
14858 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
14859 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14860 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
14861 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
14862 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
14863
14864 /******************** Bit definition for RCC_AHB4RSTR register ******************/
14865 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
14866 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
14867 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
14868 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
14869 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
14870 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
14871 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
14872 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
14873 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
14874 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
14875 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
14876 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
14877 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
14878 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
14879 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
14880 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
14881 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
14882 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
14883 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
14884 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
14885 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
14886 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
14887 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
14888 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
14889 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
14890 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
14891 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
14892 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
14893 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
14894 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
14895 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
14896 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
14897 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
14898 #define RCC_AHB4RSTR_CRCRST_Pos (19U)
14899 #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
14900 #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
14901 #define RCC_AHB4RSTR_BDMARST_Pos (21U)
14902 #define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
14903 #define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
14904 #define RCC_AHB4RSTR_ADC3RST_Pos (24U)
14905 #define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
14906 #define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
14907 #define RCC_AHB4RSTR_HSEMRST_Pos (25U)
14908 #define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
14909 #define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
14910
14911
14912 /******************** Bit definition for RCC_APB3RSTR register ******************/
14913
14914 /******************** Bit definition for RCC_APB1LRSTR register ******************/
14915
14916 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
14917 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
14918 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
14919 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
14920 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
14921 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
14922 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
14923 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
14924 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
14925 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
14926 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
14927 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
14928 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
14929 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
14930 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
14931 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
14932 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
14933 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
14934 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
14935 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
14936 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
14937 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
14938 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
14939 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
14940 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
14941 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
14942 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
14943 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
14944 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
14945 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
14946 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
14947 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
14948 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
14949 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
14950 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
14951 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
14952 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
14953 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
14954 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
14955 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
14956 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
14957 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
14958 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
14959 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
14960 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
14961 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
14962 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
14963 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
14964 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
14965 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
14966 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
14967 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
14968 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
14969 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
14970 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
14971 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
14972 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
14973 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
14974 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
14975 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
14976 #define RCC_APB1LRSTR_CECRST_Pos (27U)
14977 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
14978 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
14979 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
14980 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
14981 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
14982 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
14983 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
14984 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
14985 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
14986 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
14987 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
14988
14989 /* Legacy define */
14990 #define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
14991 #define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
14992 #define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
14993 /******************** Bit definition for RCC_APB1HRSTR register ******************/
14994 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
14995 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
14996 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
14997 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
14998 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
14999 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
15000 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
15001 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
15002 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
15003 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
15004 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
15005 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
15006 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
15007 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
15008 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
15009
15010 /******************** Bit definition for RCC_APB2RSTR register ******************/
15011 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
15012 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
15013 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
15014 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
15015 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
15016 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
15017 #define RCC_APB2RSTR_USART1RST_Pos (4U)
15018 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
15019 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
15020 #define RCC_APB2RSTR_USART6RST_Pos (5U)
15021 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
15022 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
15023 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
15024 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
15025 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
15026 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
15027 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
15028 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
15029 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
15030 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
15031 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
15032 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
15033 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
15034 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
15035 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
15036 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
15037 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
15038 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
15039 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
15040 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
15041 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
15042 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
15043 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
15044 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
15045 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
15046 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
15047 #define RCC_APB2RSTR_SAI3RST_Pos (24U)
15048 #define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
15049 #define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
15050 #define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
15051 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
15052 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
15053 #define RCC_APB2RSTR_HRTIMRST_Pos (29U)
15054 #define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
15055 #define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
15056
15057 /******************** Bit definition for RCC_APB4RSTR register ******************/
15058 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
15059 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
15060 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
15061 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
15062 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
15063 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
15064 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
15065 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
15066 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
15067 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
15068 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
15069 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
15070 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
15071 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
15072 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
15073 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
15074 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
15075 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
15076 #define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
15077 #define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
15078 #define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
15079 #define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
15080 #define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
15081 #define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
15082 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
15083 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
15084 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
15085 #define RCC_APB4RSTR_VREFRST_Pos (15U)
15086 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
15087 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
15088 #define RCC_APB4RSTR_SAI4RST_Pos (21U)
15089 #define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
15090 #define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
15091
15092
15093 /******************** Bit definition for RCC_GCR register ********************/
15094 #define RCC_GCR_WW1RSC_Pos (0U)
15095 #define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
15096 #define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
15097
15098 /******************** Bit definition for RCC_D3AMR register ********************/
15099 #define RCC_D3AMR_BDMAAMEN_Pos (0U)
15100 #define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
15101 #define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
15102 #define RCC_D3AMR_LPUART1AMEN_Pos (3U)
15103 #define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
15104 #define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
15105 #define RCC_D3AMR_SPI6AMEN_Pos (5U)
15106 #define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
15107 #define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
15108 #define RCC_D3AMR_I2C4AMEN_Pos (7U)
15109 #define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
15110 #define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
15111 #define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
15112 #define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
15113 #define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
15114 #define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
15115 #define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
15116 #define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
15117 #define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
15118 #define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
15119 #define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
15120 #define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
15121 #define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
15122 #define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
15123 #define RCC_D3AMR_COMP12AMEN_Pos (14U)
15124 #define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
15125 #define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
15126 #define RCC_D3AMR_VREFAMEN_Pos (15U)
15127 #define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
15128 #define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
15129 #define RCC_D3AMR_RTCAMEN_Pos (16U)
15130 #define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
15131 #define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
15132 #define RCC_D3AMR_CRCAMEN_Pos (19U)
15133 #define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
15134 #define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
15135 #define RCC_D3AMR_SAI4AMEN_Pos (21U)
15136 #define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
15137 #define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
15138 #define RCC_D3AMR_ADC3AMEN_Pos (24U)
15139 #define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
15140 #define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
15141
15142
15143 #define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
15144 #define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
15145 #define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
15146 #define RCC_D3AMR_SRAM4AMEN_Pos (29U)
15147 #define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
15148 #define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
15149 /******************** Bit definition for RCC_AHB3LPENR register **************/
15150 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
15151 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
15152 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
15153 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
15154 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
15155 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
15156 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
15157 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
15158 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
15159 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
15160 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
15161 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
15162 #define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
15163 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
15164 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
15165 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
15166 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
15167 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
15168 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
15169 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
15170 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
15171 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
15172 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
15173 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
15174 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
15175 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
15176 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
15177 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
15178 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
15179 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
15180
15181
15182 /******************** Bit definition for RCC_AHB1LPENR register ***************/
15183 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
15184 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
15185 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
15186 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
15187 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
15188 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
15189 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
15190 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
15191 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
15192 #define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
15193 #define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
15194 #define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
15195 #define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
15196 #define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
15197 #define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
15198 #define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
15199 #define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
15200 #define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
15201 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
15202 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
15203 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
15204 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
15205 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
15206 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
15207 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
15208 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
15209 #define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15210 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
15211 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
15212 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15213
15214 /* Legacy define */
15215 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
15216 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
15217 #define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
15218 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
15219 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
15220 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
15221
15222 /******************** Bit definition for RCC_AHB2LPENR register ***************/
15223 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
15224 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
15225 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
15226 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
15227 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
15228 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
15229 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
15230 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
15231 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
15232 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
15233 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
15234 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
15235 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
15236 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
15237 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
15238 #define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
15239 #define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
15240 #define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
15241 #define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
15242 #define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
15243 #define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
15244 #define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
15245 #define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
15246 #define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
15247
15248 /* Legacy define */
15249 #define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
15250 #define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
15251 #define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
15252 #define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
15253 #define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
15254 #define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
15255 #define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
15256 #define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
15257 #define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
15258
15259 /******************** Bit definition for RCC_AHB4LPENR register ******************/
15260 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
15261 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
15262 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
15263 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
15264 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
15265 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
15266 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
15267 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
15268 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
15269 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
15270 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
15271 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
15272 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
15273 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
15274 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
15275 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
15276 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
15277 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
15278 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
15279 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
15280 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
15281 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
15282 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
15283 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
15284 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
15285 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
15286 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
15287 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
15288 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
15289 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
15290 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
15291 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
15292 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
15293 #define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
15294 #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
15295 #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
15296 #define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
15297 #define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
15298 #define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
15299 #define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
15300 #define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
15301 #define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
15302 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
15303 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
15304 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
15305 #define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
15306 #define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
15307 #define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
15308
15309 /* Legacy define */
15310 #define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
15311 #define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
15312 #define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
15313 /******************** Bit definition for RCC_APB3LPENR register ******************/
15314 #define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
15315 #define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
15316 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
15317
15318 /******************** Bit definition for RCC_APB1LLPENR register ******************/
15319
15320 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
15321 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
15322 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
15323 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
15324 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
15325 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
15326 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
15327 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
15328 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
15329 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
15330 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
15331 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
15332 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
15333 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
15334 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
15335 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
15336 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
15337 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
15338 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
15339 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
15340 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
15341 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
15342 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
15343 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
15344 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
15345 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
15346 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
15347 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
15348 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
15349 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
15350
15351
15352 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
15353 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
15354 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
15355 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
15356 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
15357 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
15358 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
15359 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
15360 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
15361 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
15362 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
15363 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
15364 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
15365 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
15366 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
15367 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
15368 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
15369 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
15370 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
15371 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
15372 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
15373 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
15374 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
15375 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
15376 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
15377 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
15378 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
15379 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
15380 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
15381 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
15382 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
15383 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
15384 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
15385 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
15386 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
15387 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
15388 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
15389 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
15390 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
15391 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
15392 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
15393 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
15394
15395 /* Legacy define */
15396 #define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
15397 #define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
15398 #define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
15399 /******************** Bit definition for RCC_APB1HLPENR register ******************/
15400 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
15401 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
15402 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
15403 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
15404 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
15405 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
15406 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
15407 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
15408 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
15409 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
15410 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
15411 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
15412 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
15413 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
15414 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
15415
15416 /******************** Bit definition for RCC_APB2LPENR register ******************/
15417 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
15418 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
15419 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
15420 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
15421 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
15422 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
15423 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
15424 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
15425 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
15426 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
15427 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
15428 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
15429 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
15430 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
15431 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
15432 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
15433 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
15434 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
15435 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
15436 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
15437 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
15438 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
15439 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
15440 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
15441 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
15442 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
15443 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
15444 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
15445 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
15446 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
15447 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
15448 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
15449 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
15450 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
15451 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
15452 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
15453 #define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
15454 #define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
15455 #define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
15456 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
15457 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
15458 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
15459 #define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
15460 #define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
15461 #define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
15462
15463 /******************** Bit definition for RCC_APB4LPENR register ******************/
15464 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
15465 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
15466 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
15467 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
15468 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
15469 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
15470 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
15471 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
15472 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
15473 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
15474 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
15475 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
15476 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
15477 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
15478 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
15479 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
15480 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
15481 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
15482 #define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
15483 #define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
15484 #define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
15485 #define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
15486 #define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
15487 #define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
15488 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
15489 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
15490 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
15491 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
15492 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
15493 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
15494 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
15495 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
15496 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
15497 #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
15498 #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
15499 #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
15500
15501
15502 /******************** Bit definition for RCC_RSR register *******************/
15503 #define RCC_RSR_RMVF_Pos (16U)
15504 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
15505 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
15506 #define RCC_RSR_CPURSTF_Pos (17U)
15507 #define RCC_RSR_CPURSTF_Msk (0x1UL << RCC_RSR_CPURSTF_Pos) /*!< 0x00020000 */
15508 #define RCC_RSR_CPURSTF RCC_RSR_CPURSTF_Msk
15509 #define RCC_RSR_D1RSTF_Pos (19U)
15510 #define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
15511 #define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
15512 #define RCC_RSR_D2RSTF_Pos (20U)
15513 #define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
15514 #define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
15515 #define RCC_RSR_BORRSTF_Pos (21U)
15516 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
15517 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
15518 #define RCC_RSR_PINRSTF_Pos (22U)
15519 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
15520 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
15521 #define RCC_RSR_PORRSTF_Pos (23U)
15522 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
15523 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
15524 #define RCC_RSR_SFTRSTF_Pos (24U)
15525 #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
15526 #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
15527 #define RCC_RSR_IWDG1RSTF_Pos (26U)
15528 #define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
15529 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
15530 #define RCC_RSR_WWDG1RSTF_Pos (28U)
15531 #define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
15532 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
15533
15534 #define RCC_RSR_LPWRRSTF_Pos (30U)
15535 #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
15536 #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
15537
15538
15539 /******************************************************************************/
15540 /* */
15541 /* RNG */
15542 /* */
15543 /******************************************************************************/
15544 /******************** Bits definition for RNG_CR register *******************/
15545 #define RNG_CR_RNGEN_Pos (2U)
15546 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
15547 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
15548 #define RNG_CR_IE_Pos (3U)
15549 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
15550 #define RNG_CR_IE RNG_CR_IE_Msk
15551 #define RNG_CR_CED_Pos (5U)
15552 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
15553 #define RNG_CR_CED RNG_CR_CED_Msk
15554
15555 /******************** Bits definition for RNG_SR register *******************/
15556 #define RNG_SR_DRDY_Pos (0U)
15557 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
15558 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
15559 #define RNG_SR_CECS_Pos (1U)
15560 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
15561 #define RNG_SR_CECS RNG_SR_CECS_Msk
15562 #define RNG_SR_SECS_Pos (2U)
15563 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
15564 #define RNG_SR_SECS RNG_SR_SECS_Msk
15565 #define RNG_SR_CEIS_Pos (5U)
15566 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
15567 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
15568 #define RNG_SR_SEIS_Pos (6U)
15569 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
15570 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
15571
15572 /******************************************************************************/
15573 /* */
15574 /* Real-Time Clock (RTC) */
15575 /* */
15576 /******************************************************************************/
15577 /******************** Bits definition for RTC_TR register *******************/
15578 #define RTC_TR_PM_Pos (22U)
15579 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
15580 #define RTC_TR_PM RTC_TR_PM_Msk
15581 #define RTC_TR_HT_Pos (20U)
15582 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
15583 #define RTC_TR_HT RTC_TR_HT_Msk
15584 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
15585 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
15586 #define RTC_TR_HU_Pos (16U)
15587 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
15588 #define RTC_TR_HU RTC_TR_HU_Msk
15589 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
15590 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
15591 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
15592 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
15593 #define RTC_TR_MNT_Pos (12U)
15594 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
15595 #define RTC_TR_MNT RTC_TR_MNT_Msk
15596 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
15597 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
15598 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
15599 #define RTC_TR_MNU_Pos (8U)
15600 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
15601 #define RTC_TR_MNU RTC_TR_MNU_Msk
15602 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
15603 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
15604 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
15605 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
15606 #define RTC_TR_ST_Pos (4U)
15607 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
15608 #define RTC_TR_ST RTC_TR_ST_Msk
15609 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
15610 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
15611 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
15612 #define RTC_TR_SU_Pos (0U)
15613 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
15614 #define RTC_TR_SU RTC_TR_SU_Msk
15615 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
15616 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
15617 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
15618 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
15619
15620 /******************** Bits definition for RTC_DR register *******************/
15621 #define RTC_DR_YT_Pos (20U)
15622 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
15623 #define RTC_DR_YT RTC_DR_YT_Msk
15624 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
15625 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
15626 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
15627 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
15628 #define RTC_DR_YU_Pos (16U)
15629 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
15630 #define RTC_DR_YU RTC_DR_YU_Msk
15631 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
15632 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
15633 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
15634 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
15635 #define RTC_DR_WDU_Pos (13U)
15636 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
15637 #define RTC_DR_WDU RTC_DR_WDU_Msk
15638 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
15639 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
15640 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
15641 #define RTC_DR_MT_Pos (12U)
15642 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
15643 #define RTC_DR_MT RTC_DR_MT_Msk
15644 #define RTC_DR_MU_Pos (8U)
15645 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
15646 #define RTC_DR_MU RTC_DR_MU_Msk
15647 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
15648 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
15649 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
15650 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
15651 #define RTC_DR_DT_Pos (4U)
15652 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
15653 #define RTC_DR_DT RTC_DR_DT_Msk
15654 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
15655 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
15656 #define RTC_DR_DU_Pos (0U)
15657 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
15658 #define RTC_DR_DU RTC_DR_DU_Msk
15659 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
15660 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
15661 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
15662 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
15663
15664 /******************** Bits definition for RTC_CR register *******************/
15665 #define RTC_CR_ITSE_Pos (24U)
15666 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
15667 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
15668 #define RTC_CR_COE_Pos (23U)
15669 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
15670 #define RTC_CR_COE RTC_CR_COE_Msk
15671 #define RTC_CR_OSEL_Pos (21U)
15672 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
15673 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
15674 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
15675 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
15676 #define RTC_CR_POL_Pos (20U)
15677 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
15678 #define RTC_CR_POL RTC_CR_POL_Msk
15679 #define RTC_CR_COSEL_Pos (19U)
15680 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
15681 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
15682 #define RTC_CR_BKP_Pos (18U)
15683 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
15684 #define RTC_CR_BKP RTC_CR_BKP_Msk
15685 #define RTC_CR_SUB1H_Pos (17U)
15686 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
15687 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15688 #define RTC_CR_ADD1H_Pos (16U)
15689 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
15690 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15691 #define RTC_CR_TSIE_Pos (15U)
15692 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
15693 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
15694 #define RTC_CR_WUTIE_Pos (14U)
15695 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
15696 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15697 #define RTC_CR_ALRBIE_Pos (13U)
15698 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
15699 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15700 #define RTC_CR_ALRAIE_Pos (12U)
15701 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
15702 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15703 #define RTC_CR_TSE_Pos (11U)
15704 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
15705 #define RTC_CR_TSE RTC_CR_TSE_Msk
15706 #define RTC_CR_WUTE_Pos (10U)
15707 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
15708 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
15709 #define RTC_CR_ALRBE_Pos (9U)
15710 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
15711 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15712 #define RTC_CR_ALRAE_Pos (8U)
15713 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
15714 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15715 #define RTC_CR_FMT_Pos (6U)
15716 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
15717 #define RTC_CR_FMT RTC_CR_FMT_Msk
15718 #define RTC_CR_BYPSHAD_Pos (5U)
15719 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
15720 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15721 #define RTC_CR_REFCKON_Pos (4U)
15722 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
15723 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15724 #define RTC_CR_TSEDGE_Pos (3U)
15725 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
15726 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15727 #define RTC_CR_WUCKSEL_Pos (0U)
15728 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
15729 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15730 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
15731 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
15732 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
15733
15734 /******************** Bits definition for RTC_ISR register ******************/
15735 #define RTC_ISR_ITSF_Pos (17U)
15736 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
15737 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
15738 #define RTC_ISR_RECALPF_Pos (16U)
15739 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
15740 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
15741 #define RTC_ISR_TAMP3F_Pos (15U)
15742 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
15743 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
15744 #define RTC_ISR_TAMP2F_Pos (14U)
15745 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
15746 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
15747 #define RTC_ISR_TAMP1F_Pos (13U)
15748 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
15749 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
15750 #define RTC_ISR_TSOVF_Pos (12U)
15751 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
15752 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
15753 #define RTC_ISR_TSF_Pos (11U)
15754 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
15755 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
15756 #define RTC_ISR_WUTF_Pos (10U)
15757 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
15758 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
15759 #define RTC_ISR_ALRBF_Pos (9U)
15760 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
15761 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
15762 #define RTC_ISR_ALRAF_Pos (8U)
15763 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
15764 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
15765 #define RTC_ISR_INIT_Pos (7U)
15766 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
15767 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
15768 #define RTC_ISR_INITF_Pos (6U)
15769 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
15770 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
15771 #define RTC_ISR_RSF_Pos (5U)
15772 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
15773 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
15774 #define RTC_ISR_INITS_Pos (4U)
15775 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
15776 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
15777 #define RTC_ISR_SHPF_Pos (3U)
15778 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
15779 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
15780 #define RTC_ISR_WUTWF_Pos (2U)
15781 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
15782 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
15783 #define RTC_ISR_ALRBWF_Pos (1U)
15784 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
15785 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
15786 #define RTC_ISR_ALRAWF_Pos (0U)
15787 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
15788 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
15789
15790 /******************** Bits definition for RTC_PRER register *****************/
15791 #define RTC_PRER_PREDIV_A_Pos (16U)
15792 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
15793 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15794 #define RTC_PRER_PREDIV_S_Pos (0U)
15795 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
15796 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15797
15798 /******************** Bits definition for RTC_WUTR register *****************/
15799 #define RTC_WUTR_WUT_Pos (0U)
15800 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
15801 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15802
15803 /******************** Bits definition for RTC_ALRMAR register ***************/
15804 #define RTC_ALRMAR_MSK4_Pos (31U)
15805 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
15806 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15807 #define RTC_ALRMAR_WDSEL_Pos (30U)
15808 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
15809 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15810 #define RTC_ALRMAR_DT_Pos (28U)
15811 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
15812 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15813 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
15814 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
15815 #define RTC_ALRMAR_DU_Pos (24U)
15816 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
15817 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15818 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
15819 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
15820 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
15821 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
15822 #define RTC_ALRMAR_MSK3_Pos (23U)
15823 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
15824 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15825 #define RTC_ALRMAR_PM_Pos (22U)
15826 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
15827 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15828 #define RTC_ALRMAR_HT_Pos (20U)
15829 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
15830 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15831 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
15832 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
15833 #define RTC_ALRMAR_HU_Pos (16U)
15834 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
15835 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15836 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
15837 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
15838 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
15839 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
15840 #define RTC_ALRMAR_MSK2_Pos (15U)
15841 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
15842 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15843 #define RTC_ALRMAR_MNT_Pos (12U)
15844 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
15845 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15846 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
15847 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
15848 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
15849 #define RTC_ALRMAR_MNU_Pos (8U)
15850 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
15851 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15852 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
15853 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
15854 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
15855 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
15856 #define RTC_ALRMAR_MSK1_Pos (7U)
15857 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
15858 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15859 #define RTC_ALRMAR_ST_Pos (4U)
15860 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
15861 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15862 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
15863 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
15864 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
15865 #define RTC_ALRMAR_SU_Pos (0U)
15866 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
15867 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15868 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
15869 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
15870 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
15871 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
15872
15873 /******************** Bits definition for RTC_ALRMBR register ***************/
15874 #define RTC_ALRMBR_MSK4_Pos (31U)
15875 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
15876 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15877 #define RTC_ALRMBR_WDSEL_Pos (30U)
15878 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
15879 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15880 #define RTC_ALRMBR_DT_Pos (28U)
15881 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
15882 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15883 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
15884 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
15885 #define RTC_ALRMBR_DU_Pos (24U)
15886 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
15887 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15888 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
15889 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
15890 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
15891 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
15892 #define RTC_ALRMBR_MSK3_Pos (23U)
15893 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
15894 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15895 #define RTC_ALRMBR_PM_Pos (22U)
15896 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
15897 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15898 #define RTC_ALRMBR_HT_Pos (20U)
15899 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
15900 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15901 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
15902 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
15903 #define RTC_ALRMBR_HU_Pos (16U)
15904 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
15905 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15906 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
15907 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
15908 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
15909 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
15910 #define RTC_ALRMBR_MSK2_Pos (15U)
15911 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
15912 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15913 #define RTC_ALRMBR_MNT_Pos (12U)
15914 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
15915 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15916 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
15917 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
15918 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
15919 #define RTC_ALRMBR_MNU_Pos (8U)
15920 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
15921 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15922 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
15923 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
15924 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
15925 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
15926 #define RTC_ALRMBR_MSK1_Pos (7U)
15927 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
15928 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15929 #define RTC_ALRMBR_ST_Pos (4U)
15930 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
15931 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15932 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
15933 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
15934 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
15935 #define RTC_ALRMBR_SU_Pos (0U)
15936 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
15937 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15938 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
15939 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
15940 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
15941 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
15942
15943 /******************** Bits definition for RTC_WPR register ******************/
15944 #define RTC_WPR_KEY_Pos (0U)
15945 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
15946 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
15947
15948 /******************** Bits definition for RTC_SSR register ******************/
15949 #define RTC_SSR_SS_Pos (0U)
15950 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
15951 #define RTC_SSR_SS RTC_SSR_SS_Msk
15952
15953 /******************** Bits definition for RTC_SHIFTR register ***************/
15954 #define RTC_SHIFTR_SUBFS_Pos (0U)
15955 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
15956 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15957 #define RTC_SHIFTR_ADD1S_Pos (31U)
15958 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
15959 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15960
15961 /******************** Bits definition for RTC_TSTR register *****************/
15962 #define RTC_TSTR_PM_Pos (22U)
15963 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
15964 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
15965 #define RTC_TSTR_HT_Pos (20U)
15966 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
15967 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
15968 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
15969 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
15970 #define RTC_TSTR_HU_Pos (16U)
15971 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
15972 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
15973 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
15974 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
15975 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
15976 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
15977 #define RTC_TSTR_MNT_Pos (12U)
15978 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
15979 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15980 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
15981 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
15982 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
15983 #define RTC_TSTR_MNU_Pos (8U)
15984 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
15985 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15986 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
15987 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
15988 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
15989 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
15990 #define RTC_TSTR_ST_Pos (4U)
15991 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
15992 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
15993 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
15994 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
15995 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
15996 #define RTC_TSTR_SU_Pos (0U)
15997 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
15998 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
15999 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
16000 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
16001 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
16002 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
16003
16004 /******************** Bits definition for RTC_TSDR register *****************/
16005 #define RTC_TSDR_WDU_Pos (13U)
16006 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
16007 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
16008 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
16009 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
16010 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
16011 #define RTC_TSDR_MT_Pos (12U)
16012 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
16013 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
16014 #define RTC_TSDR_MU_Pos (8U)
16015 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
16016 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
16017 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
16018 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
16019 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
16020 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
16021 #define RTC_TSDR_DT_Pos (4U)
16022 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
16023 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
16024 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
16025 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
16026 #define RTC_TSDR_DU_Pos (0U)
16027 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
16028 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
16029 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
16030 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
16031 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
16032 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
16033
16034 /******************** Bits definition for RTC_TSSSR register ****************/
16035 #define RTC_TSSSR_SS_Pos (0U)
16036 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
16037 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
16038
16039 /******************** Bits definition for RTC_CALR register *****************/
16040 #define RTC_CALR_CALP_Pos (15U)
16041 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
16042 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
16043 #define RTC_CALR_CALW8_Pos (14U)
16044 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
16045 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
16046 #define RTC_CALR_CALW16_Pos (13U)
16047 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
16048 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
16049 #define RTC_CALR_CALM_Pos (0U)
16050 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
16051 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
16052 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
16053 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
16054 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
16055 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
16056 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
16057 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
16058 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
16059 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
16060 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
16061
16062 /******************** Bits definition for RTC_TAMPCR register ***************/
16063 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
16064 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
16065 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
16066 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
16067 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
16068 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
16069 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
16070 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
16071 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
16072 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
16073 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
16074 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
16075 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
16076 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
16077 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
16078 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
16079 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
16080 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
16081 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
16082 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
16083 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
16084 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
16085 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
16086 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
16087 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
16088 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
16089 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
16090 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
16091 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
16092 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
16093 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
16094 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
16095 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
16096 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
16097 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
16098 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
16099 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
16100 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
16101 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
16102 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
16103 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
16104 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
16105 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
16106 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
16107 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
16108 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
16109 #define RTC_TAMPCR_TAMPTS_Pos (7U)
16110 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
16111 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
16112 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
16113 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
16114 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
16115 #define RTC_TAMPCR_TAMP3E_Pos (5U)
16116 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
16117 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
16118 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
16119 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
16120 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
16121 #define RTC_TAMPCR_TAMP2E_Pos (3U)
16122 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
16123 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
16124 #define RTC_TAMPCR_TAMPIE_Pos (2U)
16125 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
16126 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
16127 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
16128 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
16129 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
16130 #define RTC_TAMPCR_TAMP1E_Pos (0U)
16131 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
16132 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
16133
16134 /******************** Bits definition for RTC_ALRMASSR register *************/
16135 #define RTC_ALRMASSR_MASKSS_Pos (24U)
16136 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
16137 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
16138 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
16139 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
16140 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
16141 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
16142 #define RTC_ALRMASSR_SS_Pos (0U)
16143 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
16144 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
16145
16146 /******************** Bits definition for RTC_ALRMBSSR register *************/
16147 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
16148 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
16149 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
16150 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
16151 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
16152 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
16153 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
16154 #define RTC_ALRMBSSR_SS_Pos (0U)
16155 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
16156 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
16157
16158 /******************** Bits definition for RTC_OR register *******************/
16159 #define RTC_OR_OUT_RMP_Pos (1U)
16160 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
16161 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
16162 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
16163 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
16164 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
16165
16166 /******************** Bits definition for RTC_BKP0R register ****************/
16167 #define RTC_BKP0R_Pos (0U)
16168 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
16169 #define RTC_BKP0R RTC_BKP0R_Msk
16170
16171 /******************** Bits definition for RTC_BKP1R register ****************/
16172 #define RTC_BKP1R_Pos (0U)
16173 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
16174 #define RTC_BKP1R RTC_BKP1R_Msk
16175
16176 /******************** Bits definition for RTC_BKP2R register ****************/
16177 #define RTC_BKP2R_Pos (0U)
16178 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
16179 #define RTC_BKP2R RTC_BKP2R_Msk
16180
16181 /******************** Bits definition for RTC_BKP3R register ****************/
16182 #define RTC_BKP3R_Pos (0U)
16183 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
16184 #define RTC_BKP3R RTC_BKP3R_Msk
16185
16186 /******************** Bits definition for RTC_BKP4R register ****************/
16187 #define RTC_BKP4R_Pos (0U)
16188 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
16189 #define RTC_BKP4R RTC_BKP4R_Msk
16190
16191 /******************** Bits definition for RTC_BKP5R register ****************/
16192 #define RTC_BKP5R_Pos (0U)
16193 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
16194 #define RTC_BKP5R RTC_BKP5R_Msk
16195
16196 /******************** Bits definition for RTC_BKP6R register ****************/
16197 #define RTC_BKP6R_Pos (0U)
16198 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
16199 #define RTC_BKP6R RTC_BKP6R_Msk
16200
16201 /******************** Bits definition for RTC_BKP7R register ****************/
16202 #define RTC_BKP7R_Pos (0U)
16203 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
16204 #define RTC_BKP7R RTC_BKP7R_Msk
16205
16206 /******************** Bits definition for RTC_BKP8R register ****************/
16207 #define RTC_BKP8R_Pos (0U)
16208 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
16209 #define RTC_BKP8R RTC_BKP8R_Msk
16210
16211 /******************** Bits definition for RTC_BKP9R register ****************/
16212 #define RTC_BKP9R_Pos (0U)
16213 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
16214 #define RTC_BKP9R RTC_BKP9R_Msk
16215
16216 /******************** Bits definition for RTC_BKP10R register ***************/
16217 #define RTC_BKP10R_Pos (0U)
16218 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
16219 #define RTC_BKP10R RTC_BKP10R_Msk
16220
16221 /******************** Bits definition for RTC_BKP11R register ***************/
16222 #define RTC_BKP11R_Pos (0U)
16223 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
16224 #define RTC_BKP11R RTC_BKP11R_Msk
16225
16226 /******************** Bits definition for RTC_BKP12R register ***************/
16227 #define RTC_BKP12R_Pos (0U)
16228 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
16229 #define RTC_BKP12R RTC_BKP12R_Msk
16230
16231 /******************** Bits definition for RTC_BKP13R register ***************/
16232 #define RTC_BKP13R_Pos (0U)
16233 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
16234 #define RTC_BKP13R RTC_BKP13R_Msk
16235
16236 /******************** Bits definition for RTC_BKP14R register ***************/
16237 #define RTC_BKP14R_Pos (0U)
16238 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
16239 #define RTC_BKP14R RTC_BKP14R_Msk
16240
16241 /******************** Bits definition for RTC_BKP15R register ***************/
16242 #define RTC_BKP15R_Pos (0U)
16243 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
16244 #define RTC_BKP15R RTC_BKP15R_Msk
16245
16246 /******************** Bits definition for RTC_BKP16R register ***************/
16247 #define RTC_BKP16R_Pos (0U)
16248 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
16249 #define RTC_BKP16R RTC_BKP16R_Msk
16250
16251 /******************** Bits definition for RTC_BKP17R register ***************/
16252 #define RTC_BKP17R_Pos (0U)
16253 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
16254 #define RTC_BKP17R RTC_BKP17R_Msk
16255
16256 /******************** Bits definition for RTC_BKP18R register ***************/
16257 #define RTC_BKP18R_Pos (0U)
16258 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
16259 #define RTC_BKP18R RTC_BKP18R_Msk
16260
16261 /******************** Bits definition for RTC_BKP19R register ***************/
16262 #define RTC_BKP19R_Pos (0U)
16263 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
16264 #define RTC_BKP19R RTC_BKP19R_Msk
16265
16266 /******************** Bits definition for RTC_BKP20R register ***************/
16267 #define RTC_BKP20R_Pos (0U)
16268 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
16269 #define RTC_BKP20R RTC_BKP20R_Msk
16270
16271 /******************** Bits definition for RTC_BKP21R register ***************/
16272 #define RTC_BKP21R_Pos (0U)
16273 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
16274 #define RTC_BKP21R RTC_BKP21R_Msk
16275
16276 /******************** Bits definition for RTC_BKP22R register ***************/
16277 #define RTC_BKP22R_Pos (0U)
16278 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
16279 #define RTC_BKP22R RTC_BKP22R_Msk
16280
16281 /******************** Bits definition for RTC_BKP23R register ***************/
16282 #define RTC_BKP23R_Pos (0U)
16283 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
16284 #define RTC_BKP23R RTC_BKP23R_Msk
16285
16286 /******************** Bits definition for RTC_BKP24R register ***************/
16287 #define RTC_BKP24R_Pos (0U)
16288 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
16289 #define RTC_BKP24R RTC_BKP24R_Msk
16290
16291 /******************** Bits definition for RTC_BKP25R register ***************/
16292 #define RTC_BKP25R_Pos (0U)
16293 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
16294 #define RTC_BKP25R RTC_BKP25R_Msk
16295
16296 /******************** Bits definition for RTC_BKP26R register ***************/
16297 #define RTC_BKP26R_Pos (0U)
16298 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
16299 #define RTC_BKP26R RTC_BKP26R_Msk
16300
16301 /******************** Bits definition for RTC_BKP27R register ***************/
16302 #define RTC_BKP27R_Pos (0U)
16303 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
16304 #define RTC_BKP27R RTC_BKP27R_Msk
16305
16306 /******************** Bits definition for RTC_BKP28R register ***************/
16307 #define RTC_BKP28R_Pos (0U)
16308 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
16309 #define RTC_BKP28R RTC_BKP28R_Msk
16310
16311 /******************** Bits definition for RTC_BKP29R register ***************/
16312 #define RTC_BKP29R_Pos (0U)
16313 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
16314 #define RTC_BKP29R RTC_BKP29R_Msk
16315
16316 /******************** Bits definition for RTC_BKP30R register ***************/
16317 #define RTC_BKP30R_Pos (0U)
16318 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
16319 #define RTC_BKP30R RTC_BKP30R_Msk
16320
16321 /******************** Bits definition for RTC_BKP31R register ***************/
16322 #define RTC_BKP31R_Pos (0U)
16323 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
16324 #define RTC_BKP31R RTC_BKP31R_Msk
16325
16326 /******************** Number of backup registers ******************************/
16327 #define RTC_BKP_NUMBER_Pos (5U)
16328 #define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
16329 #define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
16330
16331 /******************************************************************************/
16332 /* */
16333 /* SPDIF-RX Interface */
16334 /* */
16335 /******************************************************************************/
16336 /******************** Bit definition for SPDIF_CR register ******************/
16337 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
16338 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
16339 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
16340 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
16341 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
16342 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
16343 #define SPDIFRX_CR_RXSTEO_Pos (3U)
16344 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
16345 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
16346 #define SPDIFRX_CR_DRFMT_Pos (4U)
16347 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
16348 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
16349 #define SPDIFRX_CR_PMSK_Pos (6U)
16350 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
16351 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
16352 #define SPDIFRX_CR_VMSK_Pos (7U)
16353 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
16354 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
16355 #define SPDIFRX_CR_CUMSK_Pos (8U)
16356 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
16357 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
16358 #define SPDIFRX_CR_PTMSK_Pos (9U)
16359 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
16360 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
16361 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
16362 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
16363 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
16364 #define SPDIFRX_CR_CHSEL_Pos (11U)
16365 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
16366 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
16367 #define SPDIFRX_CR_NBTR_Pos (12U)
16368 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
16369 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
16370 #define SPDIFRX_CR_WFA_Pos (14U)
16371 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
16372 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
16373 #define SPDIFRX_CR_INSEL_Pos (16U)
16374 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
16375 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
16376 #define SPDIFRX_CR_CKSEN_Pos (20U)
16377 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
16378 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
16379 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
16380 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
16381 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
16382
16383 /******************* Bit definition for SPDIFRX_IMR register *******************/
16384 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
16385 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
16386 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
16387 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
16388 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
16389 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
16390 #define SPDIFRX_IMR_PERRIE_Pos (2U)
16391 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
16392 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
16393 #define SPDIFRX_IMR_OVRIE_Pos (3U)
16394 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
16395 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
16396 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
16397 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
16398 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
16399 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
16400 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
16401 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
16402 #define SPDIFRX_IMR_IFEIE_Pos (6U)
16403 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
16404 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
16405
16406 /******************* Bit definition for SPDIFRX_SR register *******************/
16407 #define SPDIFRX_SR_RXNE_Pos (0U)
16408 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
16409 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
16410 #define SPDIFRX_SR_CSRNE_Pos (1U)
16411 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
16412 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
16413 #define SPDIFRX_SR_PERR_Pos (2U)
16414 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
16415 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
16416 #define SPDIFRX_SR_OVR_Pos (3U)
16417 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
16418 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
16419 #define SPDIFRX_SR_SBD_Pos (4U)
16420 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
16421 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
16422 #define SPDIFRX_SR_SYNCD_Pos (5U)
16423 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
16424 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
16425 #define SPDIFRX_SR_FERR_Pos (6U)
16426 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
16427 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
16428 #define SPDIFRX_SR_SERR_Pos (7U)
16429 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
16430 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
16431 #define SPDIFRX_SR_TERR_Pos (8U)
16432 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
16433 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
16434 #define SPDIFRX_SR_WIDTH5_Pos (16U)
16435 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
16436 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
16437
16438 /******************* Bit definition for SPDIFRX_IFCR register *******************/
16439 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
16440 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
16441 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
16442 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
16443 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
16444 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
16445 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
16446 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
16447 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
16448 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
16449 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
16450 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
16451
16452 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
16453 #define SPDIFRX_DR0_DR_Pos (0U)
16454 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
16455 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
16456 #define SPDIFRX_DR0_PE_Pos (24U)
16457 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
16458 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
16459 #define SPDIFRX_DR0_V_Pos (25U)
16460 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
16461 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
16462 #define SPDIFRX_DR0_U_Pos (26U)
16463 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
16464 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
16465 #define SPDIFRX_DR0_C_Pos (27U)
16466 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
16467 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
16468 #define SPDIFRX_DR0_PT_Pos (28U)
16469 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
16470 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
16471
16472 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
16473 #define SPDIFRX_DR1_DR_Pos (8U)
16474 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
16475 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
16476 #define SPDIFRX_DR1_PT_Pos (4U)
16477 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
16478 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
16479 #define SPDIFRX_DR1_C_Pos (3U)
16480 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
16481 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
16482 #define SPDIFRX_DR1_U_Pos (2U)
16483 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
16484 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
16485 #define SPDIFRX_DR1_V_Pos (1U)
16486 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
16487 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
16488 #define SPDIFRX_DR1_PE_Pos (0U)
16489 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
16490 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
16491
16492 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
16493 #define SPDIFRX_DR1_DRNL1_Pos (16U)
16494 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
16495 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
16496 #define SPDIFRX_DR1_DRNL2_Pos (0U)
16497 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
16498 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
16499
16500 /******************* Bit definition for SPDIFRX_CSR register *******************/
16501 #define SPDIFRX_CSR_USR_Pos (0U)
16502 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
16503 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
16504 #define SPDIFRX_CSR_CS_Pos (16U)
16505 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
16506 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
16507 #define SPDIFRX_CSR_SOB_Pos (24U)
16508 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
16509 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
16510
16511 /******************* Bit definition for SPDIFRX_DIR register *******************/
16512 #define SPDIFRX_DIR_THI_Pos (0U)
16513 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
16514 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
16515 #define SPDIFRX_DIR_TLO_Pos (16U)
16516 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
16517 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
16518
16519 /******************* Bit definition for SPDIFRX_VERR register *******************/
16520 #define SPDIFRX_VERR_MINREV_Pos (0U)
16521 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
16522 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
16523 #define SPDIFRX_VERR_MAJREV_Pos (4U)
16524 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
16525 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
16526
16527 /******************* Bit definition for SPDIFRX_IDR register *******************/
16528 #define SPDIFRX_IDR_ID_Pos (0U)
16529 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
16530 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
16531
16532 /******************* Bit definition for SPDIFRX_SIDR register *******************/
16533 #define SPDIFRX_SIDR_SID_Pos (0U)
16534 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
16535 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
16536
16537 /******************************************************************************/
16538 /* */
16539 /* Serial Audio Interface */
16540 /* */
16541 /******************************************************************************/
16542 /******************************* SAI VERSION ********************************/
16543 #define SAI_VER_V2_X
16544
16545 /******************** Bit definition for SAI_GCR register *******************/
16546 #define SAI_GCR_SYNCIN_Pos (0U)
16547 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
16548 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
16549 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
16550 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
16551
16552 #define SAI_GCR_SYNCOUT_Pos (4U)
16553 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
16554 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
16555 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
16556 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
16557
16558 /******************* Bit definition for SAI_xCR1 register *******************/
16559 #define SAI_xCR1_MODE_Pos (0U)
16560 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
16561 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
16562 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
16563 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
16564
16565 #define SAI_xCR1_PRTCFG_Pos (2U)
16566 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
16567 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
16568 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
16569 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
16570
16571 #define SAI_xCR1_DS_Pos (5U)
16572 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
16573 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
16574 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
16575 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
16576 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
16577
16578 #define SAI_xCR1_LSBFIRST_Pos (8U)
16579 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
16580 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
16581 #define SAI_xCR1_CKSTR_Pos (9U)
16582 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
16583 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
16584
16585 #define SAI_xCR1_SYNCEN_Pos (10U)
16586 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
16587 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
16588 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
16589 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
16590
16591 #define SAI_xCR1_MONO_Pos (12U)
16592 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
16593 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
16594 #define SAI_xCR1_OUTDRIV_Pos (13U)
16595 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
16596 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
16597 #define SAI_xCR1_SAIEN_Pos (16U)
16598 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
16599 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
16600 #define SAI_xCR1_DMAEN_Pos (17U)
16601 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
16602 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
16603 #define SAI_xCR1_NODIV_Pos (19U)
16604 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
16605 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
16606
16607 #define SAI_xCR1_MCKDIV_Pos (20U)
16608 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
16609 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
16610 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
16611 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
16612 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
16613 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
16614 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
16615 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
16616
16617 #define SAI_xCR1_MCKEN_Pos (27U)
16618 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
16619 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
16620
16621 #define SAI_xCR1_OSR_Pos (26U)
16622 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
16623 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
16624
16625 /* Legacy define */
16626 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
16627
16628 /******************* Bit definition for SAI_xCR2 register *******************/
16629 #define SAI_xCR2_FTH_Pos (0U)
16630 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
16631 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
16632 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
16633 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
16634 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
16635
16636 #define SAI_xCR2_FFLUSH_Pos (3U)
16637 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
16638 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
16639 #define SAI_xCR2_TRIS_Pos (4U)
16640 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
16641 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
16642 #define SAI_xCR2_MUTE_Pos (5U)
16643 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
16644 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
16645 #define SAI_xCR2_MUTEVAL_Pos (6U)
16646 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
16647 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
16648
16649 #define SAI_xCR2_MUTECNT_Pos (7U)
16650 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
16651 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
16652 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
16653 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
16654 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
16655 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
16656 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
16657 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
16658
16659 #define SAI_xCR2_CPL_Pos (13U)
16660 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
16661 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
16662
16663 #define SAI_xCR2_COMP_Pos (14U)
16664 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
16665 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
16666 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
16667 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
16668
16669 /****************** Bit definition for SAI_xFRCR register *******************/
16670 #define SAI_xFRCR_FRL_Pos (0U)
16671 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
16672 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
16673 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
16674 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
16675 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
16676 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
16677 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
16678 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
16679 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
16680 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
16681
16682 #define SAI_xFRCR_FSALL_Pos (8U)
16683 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
16684 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
16685 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
16686 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
16687 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
16688 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
16689 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
16690 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
16691 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
16692
16693 #define SAI_xFRCR_FSDEF_Pos (16U)
16694 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
16695 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
16696 #define SAI_xFRCR_FSPOL_Pos (17U)
16697 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
16698 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
16699 #define SAI_xFRCR_FSOFF_Pos (18U)
16700 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
16701 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
16702
16703 /* Legacy define */
16704 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
16705
16706 /****************** Bit definition for SAI_xSLOTR register *******************/
16707 #define SAI_xSLOTR_FBOFF_Pos (0U)
16708 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
16709 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
16710 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
16711 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
16712 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
16713 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
16714 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
16715
16716 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
16717 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
16718 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
16719 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
16720 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
16721
16722 #define SAI_xSLOTR_NBSLOT_Pos (8U)
16723 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
16724 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
16725 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
16726 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
16727 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
16728 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
16729
16730 #define SAI_xSLOTR_SLOTEN_Pos (16U)
16731 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
16732 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
16733
16734 /******************* Bit definition for SAI_xIMR register *******************/
16735 #define SAI_xIMR_OVRUDRIE_Pos (0U)
16736 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
16737 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
16738 #define SAI_xIMR_MUTEDETIE_Pos (1U)
16739 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
16740 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
16741 #define SAI_xIMR_WCKCFGIE_Pos (2U)
16742 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
16743 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
16744 #define SAI_xIMR_FREQIE_Pos (3U)
16745 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
16746 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
16747 #define SAI_xIMR_CNRDYIE_Pos (4U)
16748 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
16749 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
16750 #define SAI_xIMR_AFSDETIE_Pos (5U)
16751 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
16752 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
16753 #define SAI_xIMR_LFSDETIE_Pos (6U)
16754 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
16755 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
16756
16757 /******************** Bit definition for SAI_xSR register *******************/
16758 #define SAI_xSR_OVRUDR_Pos (0U)
16759 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
16760 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
16761 #define SAI_xSR_MUTEDET_Pos (1U)
16762 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
16763 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
16764 #define SAI_xSR_WCKCFG_Pos (2U)
16765 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
16766 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
16767 #define SAI_xSR_FREQ_Pos (3U)
16768 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
16769 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
16770 #define SAI_xSR_CNRDY_Pos (4U)
16771 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
16772 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
16773 #define SAI_xSR_AFSDET_Pos (5U)
16774 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
16775 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
16776 #define SAI_xSR_LFSDET_Pos (6U)
16777 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
16778 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
16779
16780 #define SAI_xSR_FLVL_Pos (16U)
16781 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
16782 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
16783 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
16784 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
16785 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
16786
16787 /****************** Bit definition for SAI_xCLRFR register ******************/
16788 #define SAI_xCLRFR_COVRUDR_Pos (0U)
16789 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
16790 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
16791 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
16792 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
16793 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
16794 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
16795 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
16796 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
16797 #define SAI_xCLRFR_CFREQ_Pos (3U)
16798 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
16799 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
16800 #define SAI_xCLRFR_CCNRDY_Pos (4U)
16801 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
16802 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
16803 #define SAI_xCLRFR_CAFSDET_Pos (5U)
16804 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
16805 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
16806 #define SAI_xCLRFR_CLFSDET_Pos (6U)
16807 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
16808 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
16809
16810 /****************** Bit definition for SAI_xDR register *********************/
16811 #define SAI_xDR_DATA_Pos (0U)
16812 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
16813 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
16814
16815 /******************* Bit definition for SAI_PDMCR register ******************/
16816 #define SAI_PDMCR_PDMEN_Pos (0U)
16817 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
16818 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
16819
16820 #define SAI_PDMCR_MICNBR_Pos (4U)
16821 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
16822 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
16823 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
16824 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
16825
16826 #define SAI_PDMCR_CKEN1_Pos (8U)
16827 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
16828 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
16829 #define SAI_PDMCR_CKEN2_Pos (9U)
16830 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
16831 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
16832 #define SAI_PDMCR_CKEN3_Pos (10U)
16833 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
16834 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
16835 #define SAI_PDMCR_CKEN4_Pos (11U)
16836 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
16837 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
16838
16839 /****************** Bit definition for SAI_PDMDLY register ******************/
16840 #define SAI_PDMDLY_DLYM1L_Pos (0U)
16841 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
16842 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
16843 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
16844 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
16845 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
16846
16847 #define SAI_PDMDLY_DLYM1R_Pos (4U)
16848 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
16849 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
16850 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
16851 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
16852 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
16853
16854 #define SAI_PDMDLY_DLYM2L_Pos (8U)
16855 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
16856 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
16857 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
16858 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
16859 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
16860
16861 #define SAI_PDMDLY_DLYM2R_Pos (12U)
16862 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
16863 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
16864 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
16865 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
16866 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
16867
16868 #define SAI_PDMDLY_DLYM3L_Pos (16U)
16869 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
16870 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
16871 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
16872 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
16873 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
16874
16875 #define SAI_PDMDLY_DLYM3R_Pos (20U)
16876 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
16877 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
16878 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
16879 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
16880 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
16881
16882 #define SAI_PDMDLY_DLYM4L_Pos (24U)
16883 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
16884 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
16885 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
16886 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
16887 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
16888
16889 #define SAI_PDMDLY_DLYM4R_Pos (28U)
16890 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
16891 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
16892 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
16893 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
16894 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
16895
16896 /******************************************************************************/
16897 /* */
16898 /* SDMMC Interface */
16899 /* */
16900 /******************************************************************************/
16901 /****************** Bit definition for SDMMC_POWER register ******************/
16902 #define SDMMC_POWER_PWRCTRL_Pos (0U)
16903 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
16904 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
16905 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
16906 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
16907 #define SDMMC_POWER_VSWITCH_Pos (2U)
16908 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
16909 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
16910 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
16911 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
16912 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
16913 #define SDMMC_POWER_DIRPOL_Pos (4U)
16914 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
16915 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
16916
16917 /****************** Bit definition for SDMMC_CLKCR register ******************/
16918 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
16919 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
16920 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
16921 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
16922 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
16923 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
16924
16925 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
16926 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
16927 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
16928 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
16929 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
16930
16931 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
16932 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
16933 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
16934 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
16935 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
16936 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
16937 #define SDMMC_CLKCR_DDR_Pos (18U)
16938 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
16939 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
16940 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
16941 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
16942 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
16943 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
16944 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
16945 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
16946 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
16947 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
16948
16949 /******************* Bit definition for SDMMC_ARG register *******************/
16950 #define SDMMC_ARG_CMDARG_Pos (0U)
16951 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
16952 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
16953
16954 /******************* Bit definition for SDMMC_CMD register *******************/
16955 #define SDMMC_CMD_CMDINDEX_Pos (0U)
16956 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
16957 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
16958 #define SDMMC_CMD_CMDTRANS_Pos (6U)
16959 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
16960 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
16961 #define SDMMC_CMD_CMDSTOP_Pos (7U)
16962 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
16963 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
16964
16965 #define SDMMC_CMD_WAITRESP_Pos (8U)
16966 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
16967 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
16968 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
16969 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
16970
16971 #define SDMMC_CMD_WAITINT_Pos (10U)
16972 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
16973 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
16974 #define SDMMC_CMD_WAITPEND_Pos (11U)
16975 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
16976 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
16977 #define SDMMC_CMD_CPSMEN_Pos (12U)
16978 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
16979 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
16980 #define SDMMC_CMD_DTHOLD_Pos (13U)
16981 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
16982 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
16983 #define SDMMC_CMD_BOOTMODE_Pos (14U)
16984 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
16985 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
16986 #define SDMMC_CMD_BOOTEN_Pos (15U)
16987 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
16988 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
16989 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
16990 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
16991 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
16992
16993 /***************** Bit definition for SDMMC_RESPCMD register *****************/
16994 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
16995 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
16996 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
16997
16998 /****************** Bit definition for SDMMC_RESP0 register ******************/
16999 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
17000 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
17001 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
17002
17003 /****************** Bit definition for SDMMC_RESP1 register ******************/
17004 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
17005 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
17006 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
17007
17008 /****************** Bit definition for SDMMC_RESP2 register ******************/
17009 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
17010 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
17011 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
17012
17013 /****************** Bit definition for SDMMC_RESP3 register ******************/
17014 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
17015 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
17016 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
17017
17018 /****************** Bit definition for SDMMC_RESP4 register ******************/
17019 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
17020 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
17021 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
17022
17023 /****************** Bit definition for SDMMC_DTIMER register *****************/
17024 #define SDMMC_DTIMER_DATATIME_Pos (0U)
17025 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
17026 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
17027
17028 /****************** Bit definition for SDMMC_DLEN register *******************/
17029 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
17030 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
17031 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
17032
17033 /****************** Bit definition for SDMMC_DCTRL register ******************/
17034 #define SDMMC_DCTRL_DTEN_Pos (0U)
17035 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
17036 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
17037 #define SDMMC_DCTRL_DTDIR_Pos (1U)
17038 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
17039 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
17040 #define SDMMC_DCTRL_DTMODE_Pos (2U)
17041 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
17042 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
17043 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
17044 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
17045
17046 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
17047 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
17048 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
17049 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
17050 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
17051 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
17052 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
17053
17054 #define SDMMC_DCTRL_RWSTART_Pos (8U)
17055 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
17056 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
17057 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
17058 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
17059 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
17060 #define SDMMC_DCTRL_RWMOD_Pos (10U)
17061 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
17062 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
17063 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
17064 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
17065 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
17066 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
17067 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
17068 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
17069 #define SDMMC_DCTRL_FIFORST_Pos (13U)
17070 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
17071 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
17072
17073 /****************** Bit definition for SDMMC_DCOUNT register *****************/
17074 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
17075 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
17076 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
17077
17078 /****************** Bit definition for SDMMC_STA register ********************/
17079 #define SDMMC_STA_CCRCFAIL_Pos (0U)
17080 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
17081 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
17082 #define SDMMC_STA_DCRCFAIL_Pos (1U)
17083 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
17084 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
17085 #define SDMMC_STA_CTIMEOUT_Pos (2U)
17086 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
17087 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
17088 #define SDMMC_STA_DTIMEOUT_Pos (3U)
17089 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
17090 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
17091 #define SDMMC_STA_TXUNDERR_Pos (4U)
17092 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
17093 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
17094 #define SDMMC_STA_RXOVERR_Pos (5U)
17095 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
17096 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
17097 #define SDMMC_STA_CMDREND_Pos (6U)
17098 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
17099 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
17100 #define SDMMC_STA_CMDSENT_Pos (7U)
17101 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
17102 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
17103 #define SDMMC_STA_DATAEND_Pos (8U)
17104 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
17105 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
17106 #define SDMMC_STA_DHOLD_Pos (9U)
17107 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
17108 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
17109 #define SDMMC_STA_DBCKEND_Pos (10U)
17110 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
17111 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
17112 #define SDMMC_STA_DABORT_Pos (11U)
17113 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
17114 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
17115 #define SDMMC_STA_DPSMACT_Pos (12U)
17116 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
17117 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
17118 #define SDMMC_STA_CPSMACT_Pos (13U)
17119 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
17120 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
17121 #define SDMMC_STA_TXFIFOHE_Pos (14U)
17122 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
17123 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
17124 #define SDMMC_STA_RXFIFOHF_Pos (15U)
17125 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
17126 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
17127 #define SDMMC_STA_TXFIFOF_Pos (16U)
17128 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
17129 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
17130 #define SDMMC_STA_RXFIFOF_Pos (17U)
17131 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
17132 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
17133 #define SDMMC_STA_TXFIFOE_Pos (18U)
17134 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
17135 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
17136 #define SDMMC_STA_RXFIFOE_Pos (19U)
17137 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
17138 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
17139 #define SDMMC_STA_BUSYD0_Pos (20U)
17140 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
17141 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
17142 #define SDMMC_STA_BUSYD0END_Pos (21U)
17143 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
17144 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
17145 #define SDMMC_STA_SDIOIT_Pos (22U)
17146 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
17147 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
17148 #define SDMMC_STA_ACKFAIL_Pos (23U)
17149 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
17150 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
17151 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
17152 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
17153 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
17154 #define SDMMC_STA_VSWEND_Pos (25U)
17155 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
17156 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
17157 #define SDMMC_STA_CKSTOP_Pos (26U)
17158 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
17159 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
17160 #define SDMMC_STA_IDMATE_Pos (27U)
17161 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
17162 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
17163 #define SDMMC_STA_IDMABTC_Pos (28U)
17164 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
17165 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
17166
17167 /******************* Bit definition for SDMMC_ICR register *******************/
17168 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
17169 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
17170 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
17171 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
17172 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
17173 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
17174 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
17175 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
17176 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
17177 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
17178 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
17179 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
17180 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
17181 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
17182 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
17183 #define SDMMC_ICR_RXOVERRC_Pos (5U)
17184 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
17185 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
17186 #define SDMMC_ICR_CMDRENDC_Pos (6U)
17187 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
17188 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
17189 #define SDMMC_ICR_CMDSENTC_Pos (7U)
17190 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
17191 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
17192 #define SDMMC_ICR_DATAENDC_Pos (8U)
17193 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
17194 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
17195 #define SDMMC_ICR_DHOLDC_Pos (9U)
17196 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
17197 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
17198 #define SDMMC_ICR_DBCKENDC_Pos (10U)
17199 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
17200 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
17201 #define SDMMC_ICR_DABORTC_Pos (11U)
17202 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
17203 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
17204 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
17205 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
17206 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
17207 #define SDMMC_ICR_SDIOITC_Pos (22U)
17208 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
17209 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
17210 #define SDMMC_ICR_ACKFAILC_Pos (23U)
17211 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
17212 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
17213 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
17214 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
17215 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
17216 #define SDMMC_ICR_VSWENDC_Pos (25U)
17217 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
17218 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
17219 #define SDMMC_ICR_CKSTOPC_Pos (26U)
17220 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
17221 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
17222 #define SDMMC_ICR_IDMATEC_Pos (27U)
17223 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
17224 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
17225 #define SDMMC_ICR_IDMABTCC_Pos (28U)
17226 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
17227 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
17228
17229 /****************** Bit definition for SDMMC_MASK register *******************/
17230 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
17231 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
17232 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
17233 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
17234 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
17235 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
17236 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
17237 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
17238 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
17239 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
17240 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
17241 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
17242 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
17243 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
17244 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
17245 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
17246 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
17247 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
17248 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
17249 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
17250 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
17251 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
17252 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
17253 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
17254 #define SDMMC_MASK_DATAENDIE_Pos (8U)
17255 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
17256 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
17257 #define SDMMC_MASK_DHOLDIE_Pos (9U)
17258 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
17259 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
17260 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
17261 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
17262 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
17263 #define SDMMC_MASK_DABORTIE_Pos (11U)
17264 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
17265 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
17266
17267 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
17268 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
17269 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
17270 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
17271 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
17272 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
17273
17274 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
17275 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
17276 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
17277 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
17278 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
17279 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
17280
17281 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
17282 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
17283 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
17284 #define SDMMC_MASK_SDIOITIE_Pos (22U)
17285 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
17286 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
17287 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
17288 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
17289 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
17290 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
17291 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
17292 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
17293 #define SDMMC_MASK_VSWENDIE_Pos (25U)
17294 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
17295 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
17296 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
17297 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
17298 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
17299 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
17300 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
17301 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
17302
17303 /***************** Bit definition for SDMMC_ACKTIME register *****************/
17304 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
17305 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
17306 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
17307
17308 /****************** Bit definition for SDMMC_FIFO register *******************/
17309 #define SDMMC_FIFO_FIFODATA_Pos (0U)
17310 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
17311 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
17312
17313 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
17314 #define SDMMC_IDMA_IDMAEN_Pos (0U)
17315 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
17316 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
17317 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
17318 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
17319 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
17320 #define SDMMC_IDMA_IDMABACT_Pos (2U)
17321 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
17322 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
17323
17324 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
17325 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
17326 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
17327 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
17328
17329 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
17330 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
17331
17332 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
17333 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
17334
17335 /******************************************************************************/
17336 /* */
17337 /* Delay Block Interface (DLYB) */
17338 /* */
17339 /******************************************************************************/
17340 /******************* Bit definition for DLYB_CR register ********************/
17341 #define DLYB_CR_DEN_Pos (0U)
17342 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
17343 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
17344 #define DLYB_CR_SEN_Pos (1U)
17345 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
17346 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
17347
17348
17349 /******************* Bit definition for DLYB_CFGR register ********************/
17350 #define DLYB_CFGR_SEL_Pos (0U)
17351 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
17352 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
17353 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
17354 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
17355 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
17356 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
17357
17358 #define DLYB_CFGR_UNIT_Pos (8U)
17359 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
17360 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
17361 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
17362 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
17363 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
17364 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
17365 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
17366 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
17367 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
17368
17369 #define DLYB_CFGR_LNG_Pos (16U)
17370 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
17371 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
17372 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
17373 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
17374 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
17375 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
17376 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
17377 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
17378 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
17379 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
17380 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
17381 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
17382 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
17383 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
17384
17385 #define DLYB_CFGR_LNGF_Pos (31U)
17386 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
17387 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
17388
17389 /******************************************************************************/
17390 /* */
17391 /* Serial Peripheral Interface (SPI/I2S) */
17392 /* */
17393 /******************************************************************************/
17394 /******************* Bit definition for SPI_CR1 register ********************/
17395 #define SPI_CR1_SPE_Pos (0U)
17396 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
17397 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
17398 #define SPI_CR1_MASRX_Pos (8U)
17399 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
17400 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
17401 #define SPI_CR1_CSTART_Pos (9U)
17402 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
17403 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
17404 #define SPI_CR1_CSUSP_Pos (10U)
17405 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
17406 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
17407 #define SPI_CR1_HDDIR_Pos (11U)
17408 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
17409 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
17410 #define SPI_CR1_SSI_Pos (12U)
17411 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
17412 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
17413 #define SPI_CR1_CRC33_17_Pos (13U)
17414 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
17415 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
17416 #define SPI_CR1_RCRCINI_Pos (14U)
17417 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
17418 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
17419 #define SPI_CR1_TCRCINI_Pos (15U)
17420 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
17421 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
17422 #define SPI_CR1_IOLOCK_Pos (16U)
17423 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
17424 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
17425
17426 /******************* Bit definition for SPI_CR2 register ********************/
17427 #define SPI_CR2_TSER_Pos (16U)
17428 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
17429 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
17430 #define SPI_CR2_TSIZE_Pos (0U)
17431 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
17432 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
17433
17434 /******************* Bit definition for SPI_CFG1 register ********************/
17435 #define SPI_CFG1_DSIZE_Pos (0U)
17436 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
17437 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
17438 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
17439 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
17440 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
17441 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
17442 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
17443
17444 #define SPI_CFG1_FTHLV_Pos (5U)
17445 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
17446 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
17447 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
17448 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
17449 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
17450 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
17451
17452 #define SPI_CFG1_UDRCFG_Pos (9U)
17453 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
17454 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
17455 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
17456 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
17457
17458
17459 #define SPI_CFG1_UDRDET_Pos (11U)
17460 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
17461 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
17462 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
17463 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
17464
17465 #define SPI_CFG1_RXDMAEN_Pos (14U)
17466 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
17467 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
17468 #define SPI_CFG1_TXDMAEN_Pos (15U)
17469 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
17470 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
17471
17472 #define SPI_CFG1_CRCSIZE_Pos (16U)
17473 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
17474 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
17475 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
17476 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
17477 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
17478 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
17479 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
17480
17481 #define SPI_CFG1_CRCEN_Pos (22U)
17482 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
17483 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
17484
17485 #define SPI_CFG1_MBR_Pos (28U)
17486 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
17487 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
17488 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
17489 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
17490 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
17491
17492 /******************* Bit definition for SPI_CFG2 register ********************/
17493 #define SPI_CFG2_MSSI_Pos (0U)
17494 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
17495 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
17496 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
17497 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
17498 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
17499 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
17500
17501 #define SPI_CFG2_MIDI_Pos (4U)
17502 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
17503 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
17504 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
17505 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
17506 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
17507 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
17508
17509 #define SPI_CFG2_IOSWP_Pos (15U)
17510 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
17511 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
17512
17513 #define SPI_CFG2_COMM_Pos (17U)
17514 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
17515 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
17516 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
17517 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
17518
17519 #define SPI_CFG2_SP_Pos (19U)
17520 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
17521 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
17522 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
17523 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
17524 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
17525
17526 #define SPI_CFG2_MASTER_Pos (22U)
17527 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
17528 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
17529 #define SPI_CFG2_LSBFRST_Pos (23U)
17530 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
17531 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
17532 #define SPI_CFG2_CPHA_Pos (24U)
17533 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
17534 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
17535 #define SPI_CFG2_CPOL_Pos (25U)
17536 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
17537 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
17538 #define SPI_CFG2_SSM_Pos (26U)
17539 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
17540 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
17541
17542 #define SPI_CFG2_SSIOP_Pos (28U)
17543 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
17544 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
17545 #define SPI_CFG2_SSOE_Pos (29U)
17546 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
17547 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
17548 #define SPI_CFG2_SSOM_Pos (30U)
17549 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
17550 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
17551
17552 #define SPI_CFG2_AFCNTR_Pos (31U)
17553 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
17554 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
17555
17556 /******************* Bit definition for SPI_IER register ********************/
17557 #define SPI_IER_RXPIE_Pos (0U)
17558 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
17559 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
17560 #define SPI_IER_TXPIE_Pos (1U)
17561 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
17562 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
17563 #define SPI_IER_DXPIE_Pos (2U)
17564 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
17565 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
17566 #define SPI_IER_EOTIE_Pos (3U)
17567 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
17568 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
17569 #define SPI_IER_TXTFIE_Pos (4U)
17570 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
17571 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
17572 #define SPI_IER_UDRIE_Pos (5U)
17573 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
17574 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
17575 #define SPI_IER_OVRIE_Pos (6U)
17576 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
17577 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
17578 #define SPI_IER_CRCEIE_Pos (7U)
17579 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
17580 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
17581 #define SPI_IER_TIFREIE_Pos (8U)
17582 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
17583 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
17584 #define SPI_IER_MODFIE_Pos (9U)
17585 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
17586 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
17587 #define SPI_IER_TSERFIE_Pos (10U)
17588 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
17589 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
17590
17591 /******************* Bit definition for SPI_SR register ********************/
17592 #define SPI_SR_RXP_Pos (0U)
17593 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
17594 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
17595 #define SPI_SR_TXP_Pos (1U)
17596 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
17597 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
17598 #define SPI_SR_DXP_Pos (2U)
17599 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
17600 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
17601 #define SPI_SR_EOT_Pos (3U)
17602 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
17603 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
17604 #define SPI_SR_TXTF_Pos (4U)
17605 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
17606 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
17607 #define SPI_SR_UDR_Pos (5U)
17608 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
17609 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
17610 #define SPI_SR_OVR_Pos (6U)
17611 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
17612 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
17613 #define SPI_SR_CRCE_Pos (7U)
17614 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
17615 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
17616 #define SPI_SR_TIFRE_Pos (8U)
17617 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
17618 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
17619 #define SPI_SR_MODF_Pos (9U)
17620 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
17621 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
17622 #define SPI_SR_TSERF_Pos (10U)
17623 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
17624 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
17625 #define SPI_SR_SUSP_Pos (11U)
17626 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
17627 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
17628 #define SPI_SR_TXC_Pos (12U)
17629 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
17630 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
17631 #define SPI_SR_RXPLVL_Pos (13U)
17632 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
17633 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
17634 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
17635 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
17636 #define SPI_SR_RXWNE_Pos (15U)
17637 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
17638 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
17639 #define SPI_SR_CTSIZE_Pos (16U)
17640 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
17641 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
17642
17643 /******************* Bit definition for SPI_IFCR register ********************/
17644 #define SPI_IFCR_EOTC_Pos (3U)
17645 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
17646 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
17647 #define SPI_IFCR_TXTFC_Pos (4U)
17648 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
17649 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
17650 #define SPI_IFCR_UDRC_Pos (5U)
17651 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
17652 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
17653 #define SPI_IFCR_OVRC_Pos (6U)
17654 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
17655 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
17656 #define SPI_IFCR_CRCEC_Pos (7U)
17657 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
17658 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
17659 #define SPI_IFCR_TIFREC_Pos (8U)
17660 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
17661 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
17662 #define SPI_IFCR_MODFC_Pos (9U)
17663 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
17664 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
17665 #define SPI_IFCR_TSERFC_Pos (10U)
17666 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
17667 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
17668 #define SPI_IFCR_SUSPC_Pos (11U)
17669 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
17670 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
17671
17672 /******************* Bit definition for SPI_TXDR register ********************/
17673 #define SPI_TXDR_TXDR_Pos (0U)
17674 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
17675 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
17676
17677 /******************* Bit definition for SPI_RXDR register ********************/
17678 #define SPI_RXDR_RXDR_Pos (0U)
17679 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
17680 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
17681
17682 /******************* Bit definition for SPI_CRCPOLY register ********************/
17683 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
17684 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
17685 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
17686
17687 /******************* Bit definition for SPI_TXCRC register ********************/
17688 #define SPI_TXCRC_TXCRC_Pos (0U)
17689 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
17690 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
17691
17692 /******************* Bit definition for SPI_RXCRC register ********************/
17693 #define SPI_RXCRC_RXCRC_Pos (0U)
17694 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
17695 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
17696
17697 /******************* Bit definition for SPI_UDRDR register ********************/
17698 #define SPI_UDRDR_UDRDR_Pos (0U)
17699 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
17700 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
17701
17702 /****************** Bit definition for SPI_I2SCFGR register *****************/
17703 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
17704 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
17705 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
17706 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
17707 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
17708 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
17709 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
17710 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
17711 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
17712 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
17713 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
17714 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
17715 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
17716 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
17717 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
17718 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
17719 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
17720 #define SPI_I2SCFGR_DATLEN_Pos (8U)
17721 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
17722 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
17723 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
17724 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
17725 #define SPI_I2SCFGR_CHLEN_Pos (10U)
17726 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
17727 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
17728 #define SPI_I2SCFGR_CKPOL_Pos (11U)
17729 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
17730 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
17731 #define SPI_I2SCFGR_FIXCH_Pos (12U)
17732 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
17733 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
17734 #define SPI_I2SCFGR_WSINV_Pos (13U)
17735 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
17736 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
17737 #define SPI_I2SCFGR_DATFMT_Pos (14U)
17738 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
17739 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
17740 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
17741 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
17742 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
17743 #define SPI_I2SCFGR_ODD_Pos (24U)
17744 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
17745 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
17746 #define SPI_I2SCFGR_MCKOE_Pos (25U)
17747 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
17748 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
17749
17750
17751 /******************************************************************************/
17752 /* */
17753 /* QUADSPI */
17754 /* */
17755 /******************************************************************************/
17756 /***************** Bit definition for QUADSPI_CR register *******************/
17757 #define QUADSPI_CR_EN_Pos (0U)
17758 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
17759 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
17760 #define QUADSPI_CR_ABORT_Pos (1U)
17761 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
17762 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
17763 #define QUADSPI_CR_DMAEN_Pos (2U)
17764 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
17765 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
17766 #define QUADSPI_CR_TCEN_Pos (3U)
17767 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
17768 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
17769 #define QUADSPI_CR_SSHIFT_Pos (4U)
17770 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
17771 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
17772 #define QUADSPI_CR_DFM_Pos (6U)
17773 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
17774 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
17775 #define QUADSPI_CR_FSEL_Pos (7U)
17776 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
17777 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
17778 #define QUADSPI_CR_FTHRES_Pos (8U)
17779 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
17780 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
17781 #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
17782 #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
17783 #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
17784 #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
17785 #define QUADSPI_CR_TEIE_Pos (16U)
17786 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
17787 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
17788 #define QUADSPI_CR_TCIE_Pos (17U)
17789 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
17790 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
17791 #define QUADSPI_CR_FTIE_Pos (18U)
17792 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
17793 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
17794 #define QUADSPI_CR_SMIE_Pos (19U)
17795 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
17796 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
17797 #define QUADSPI_CR_TOIE_Pos (20U)
17798 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
17799 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
17800 #define QUADSPI_CR_APMS_Pos (22U)
17801 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
17802 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
17803 #define QUADSPI_CR_PMM_Pos (23U)
17804 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
17805 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
17806 #define QUADSPI_CR_PRESCALER_Pos (24U)
17807 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
17808 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
17809 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
17810 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
17811 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
17812 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
17813 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
17814 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
17815 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
17816 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
17817
17818 /***************** Bit definition for QUADSPI_DCR register ******************/
17819 #define QUADSPI_DCR_CKMODE_Pos (0U)
17820 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
17821 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
17822 #define QUADSPI_DCR_CSHT_Pos (8U)
17823 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
17824 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
17825 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
17826 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
17827 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
17828 #define QUADSPI_DCR_FSIZE_Pos (16U)
17829 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
17830 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
17831 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
17832 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
17833 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
17834 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
17835 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
17836
17837 /****************** Bit definition for QUADSPI_SR register *******************/
17838 #define QUADSPI_SR_TEF_Pos (0U)
17839 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
17840 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
17841 #define QUADSPI_SR_TCF_Pos (1U)
17842 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
17843 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
17844 #define QUADSPI_SR_FTF_Pos (2U)
17845 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
17846 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
17847 #define QUADSPI_SR_SMF_Pos (3U)
17848 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
17849 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
17850 #define QUADSPI_SR_TOF_Pos (4U)
17851 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
17852 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
17853 #define QUADSPI_SR_BUSY_Pos (5U)
17854 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
17855 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
17856 #define QUADSPI_SR_FLEVEL_Pos (8U)
17857 #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
17858 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
17859 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
17860 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
17861 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
17862 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
17863 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
17864 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
17865
17866 /****************** Bit definition for QUADSPI_FCR register ******************/
17867 #define QUADSPI_FCR_CTEF_Pos (0U)
17868 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
17869 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
17870 #define QUADSPI_FCR_CTCF_Pos (1U)
17871 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
17872 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
17873 #define QUADSPI_FCR_CSMF_Pos (3U)
17874 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
17875 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
17876 #define QUADSPI_FCR_CTOF_Pos (4U)
17877 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
17878 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
17879
17880 /****************** Bit definition for QUADSPI_DLR register ******************/
17881 #define QUADSPI_DLR_DL_Pos (0U)
17882 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
17883 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
17884
17885 /****************** Bit definition for QUADSPI_CCR register ******************/
17886 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
17887 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
17888 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
17889 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
17890 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
17891 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
17892 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
17893 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
17894 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
17895 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
17896 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
17897 #define QUADSPI_CCR_IMODE_Pos (8U)
17898 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
17899 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
17900 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
17901 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
17902 #define QUADSPI_CCR_ADMODE_Pos (10U)
17903 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
17904 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
17905 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
17906 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
17907 #define QUADSPI_CCR_ADSIZE_Pos (12U)
17908 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
17909 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
17910 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
17911 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
17912 #define QUADSPI_CCR_ABMODE_Pos (14U)
17913 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
17914 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
17915 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
17916 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
17917 #define QUADSPI_CCR_ABSIZE_Pos (16U)
17918 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
17919 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
17920 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
17921 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
17922 #define QUADSPI_CCR_DCYC_Pos (18U)
17923 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
17924 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
17925 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
17926 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
17927 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
17928 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
17929 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
17930 #define QUADSPI_CCR_DMODE_Pos (24U)
17931 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
17932 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
17933 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
17934 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
17935 #define QUADSPI_CCR_FMODE_Pos (26U)
17936 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
17937 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
17938 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
17939 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
17940 #define QUADSPI_CCR_SIOO_Pos (28U)
17941 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
17942 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
17943 #define QUADSPI_CCR_DHHC_Pos (30U)
17944 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
17945 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
17946 #define QUADSPI_CCR_DDRM_Pos (31U)
17947 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
17948 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
17949
17950 /****************** Bit definition for QUADSPI_AR register *******************/
17951 #define QUADSPI_AR_ADDRESS_Pos (0U)
17952 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
17953 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
17954
17955 /****************** Bit definition for QUADSPI_ABR register ******************/
17956 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
17957 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
17958 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
17959
17960 /****************** Bit definition for QUADSPI_DR register *******************/
17961 #define QUADSPI_DR_DATA_Pos (0U)
17962 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
17963 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
17964
17965 /****************** Bit definition for QUADSPI_PSMKR register ****************/
17966 #define QUADSPI_PSMKR_MASK_Pos (0U)
17967 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
17968 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
17969
17970 /****************** Bit definition for QUADSPI_PSMAR register ****************/
17971 #define QUADSPI_PSMAR_MATCH_Pos (0U)
17972 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
17973 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
17974
17975 /****************** Bit definition for QUADSPI_PIR register *****************/
17976 #define QUADSPI_PIR_INTERVAL_Pos (0U)
17977 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
17978 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
17979
17980 /****************** Bit definition for QUADSPI_LPTR register *****************/
17981 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
17982 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
17983 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
17984
17985 /******************************************************************************/
17986 /* */
17987 /* SYSCFG */
17988 /* */
17989 /******************************************************************************/
17990
17991 /****************** Bit definition for SYSCFG_PMCR register ******************/
17992 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
17993 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
17994 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
17995 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
17996 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
17997 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
17998 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
17999 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
18000 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
18001 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
18002 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
18003 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
18004 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
18005 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
18006 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
18007 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
18008 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
18009 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
18010 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
18011 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
18012 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
18013 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
18014 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
18015 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
18016 #define SYSCFG_PMCR_BOOSTEN_Pos (8U)
18017 #define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
18018 #define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
18019
18020 #define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
18021 #define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
18022 #define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
18023
18024 #define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
18025 #define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
18026 #define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
18027 #define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
18028 #define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
18029 #define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */
18030 #define SYSCFG_PMCR_PA0SO_Pos (24U)
18031 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
18032 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
18033 #define SYSCFG_PMCR_PA1SO_Pos (25U)
18034 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
18035 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
18036 #define SYSCFG_PMCR_PC2SO_Pos (26U)
18037 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
18038 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
18039 #define SYSCFG_PMCR_PC3SO_Pos (27U)
18040 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
18041 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
18042
18043 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
18044 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
18045 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
18046 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
18047 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
18048 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
18049 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
18050 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
18051 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
18052 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
18053 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
18054 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
18055 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
18056 /**
18057 * @brief EXTI0 configuration
18058 */
18059 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
18060 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
18061 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
18062 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
18063 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
18064 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
18065 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
18066 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
18067 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
18068 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
18069 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
18070
18071 /**
18072 * @brief EXTI1 configuration
18073 */
18074 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
18075 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
18076 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
18077 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
18078 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
18079 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
18080 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
18081 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
18082 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
18083 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
18084 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
18085 /**
18086 * @brief EXTI2 configuration
18087 */
18088 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
18089 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
18090 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
18091 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
18092 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
18093 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
18094 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
18095 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
18096 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
18097 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
18098 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
18099
18100 /**
18101 * @brief EXTI3 configuration
18102 */
18103 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
18104 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
18105 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
18106 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
18107 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
18108 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
18109 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
18110 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
18111 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
18112 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
18113 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
18114
18115 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
18116 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
18117 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
18118 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
18119 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
18120 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
18121 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
18122 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
18123 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
18124 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
18125 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
18126 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
18127 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
18128 /**
18129 * @brief EXTI4 configuration
18130 */
18131 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
18132 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
18133 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
18134 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
18135 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
18136 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
18137 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
18138 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
18139 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
18140 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
18141 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
18142 /**
18143 * @brief EXTI5 configuration
18144 */
18145 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
18146 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
18147 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
18148 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
18149 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
18150 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
18151 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
18152 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
18153 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
18154 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
18155 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
18156 /**
18157 * @brief EXTI6 configuration
18158 */
18159 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
18160 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
18161 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
18162 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
18163 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
18164 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
18165 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
18166 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
18167 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
18168 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
18169 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
18170
18171 /**
18172 * @brief EXTI7 configuration
18173 */
18174 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
18175 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
18176 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
18177 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
18178 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
18179 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
18180 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
18181 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
18182 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
18183 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
18184 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
18185
18186 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
18187 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
18188 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
18189 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
18190 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
18191 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
18192 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
18193 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
18194 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
18195 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
18196 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
18197 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
18198 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
18199
18200 /**
18201 * @brief EXTI8 configuration
18202 */
18203 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
18204 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
18205 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
18206 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
18207 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
18208 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
18209 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
18210 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
18211 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
18212 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
18213 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
18214
18215 /**
18216 * @brief EXTI9 configuration
18217 */
18218 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
18219 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
18220 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
18221 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
18222 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
18223 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
18224 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
18225 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
18226 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
18227 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
18228 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
18229
18230 /**
18231 * @brief EXTI10 configuration
18232 */
18233 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
18234 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
18235 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
18236 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
18237 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
18238 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
18239 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
18240 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
18241 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
18242 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
18243 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
18244
18245 /**
18246 * @brief EXTI11 configuration
18247 */
18248 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
18249 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
18250 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
18251 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
18252 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
18253 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
18254 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
18255 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
18256 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
18257 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
18258 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
18259
18260 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
18261 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
18262 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
18263 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
18264 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
18265 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
18266 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
18267 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
18268 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
18269 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
18270 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
18271 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
18272 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
18273 /**
18274 * @brief EXTI12 configuration
18275 */
18276 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
18277 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
18278 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
18279 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
18280 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
18281 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
18282 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
18283 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
18284 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
18285 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
18286 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
18287 /**
18288 * @brief EXTI13 configuration
18289 */
18290 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
18291 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
18292 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
18293 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
18294 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
18295 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
18296 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
18297 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
18298 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
18299 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
18300 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
18301 /**
18302 * @brief EXTI14 configuration
18303 */
18304 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
18305 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
18306 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
18307 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
18308 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
18309 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
18310 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
18311 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
18312 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
18313 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
18314 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
18315 /**
18316 * @brief EXTI15 configuration
18317 */
18318 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
18319 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
18320 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
18321 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
18322 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
18323 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
18324 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
18325 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
18326 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
18327 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
18328 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
18329
18330 /****************** Bit definition for SYSCFG_CFGR register ******************/
18331 #define SYSCFG_CFGR_PVDL_Pos (2U)
18332 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
18333 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
18334 #define SYSCFG_CFGR_FLASHL_Pos (3U)
18335 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
18336 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
18337 #define SYSCFG_CFGR_CM7L_Pos (6U)
18338 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
18339 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
18340 #define SYSCFG_CFGR_BKRAML_Pos (7U)
18341 #define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */
18342 #define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */
18343 #define SYSCFG_CFGR_SRAM4L_Pos (9U)
18344 #define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */
18345 #define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */
18346 #define SYSCFG_CFGR_SRAM3L_Pos (10U)
18347 #define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */
18348 #define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */
18349 #define SYSCFG_CFGR_SRAM2L_Pos (11U)
18350 #define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */
18351 #define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */
18352 #define SYSCFG_CFGR_SRAM1L_Pos (12U)
18353 #define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */
18354 #define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */
18355 #define SYSCFG_CFGR_DTCML_Pos (13U)
18356 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
18357 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
18358 #define SYSCFG_CFGR_ITCML_Pos (14U)
18359 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
18360 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
18361 #define SYSCFG_CFGR_AXISRAML_Pos (15U)
18362 #define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */
18363 #define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */
18364
18365 /****************** Bit definition for SYSCFG_CCCSR register ******************/
18366 #define SYSCFG_CCCSR_EN_Pos (0U)
18367 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
18368 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
18369 #define SYSCFG_CCCSR_CS_Pos (1U)
18370 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
18371 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
18372 #define SYSCFG_CCCSR_READY_Pos (8U)
18373 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
18374 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
18375 #define SYSCFG_CCCSR_HSLV_Pos (16U)
18376 #define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
18377 #define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
18378
18379 /****************** Bit definition for SYSCFG_CCVR register *******************/
18380 #define SYSCFG_CCVR_NCV_Pos (0U)
18381 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
18382 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
18383 #define SYSCFG_CCVR_PCV_Pos (4U)
18384 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
18385 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
18386
18387 /****************** Bit definition for SYSCFG_CCCR register *******************/
18388 #define SYSCFG_CCCR_NCC_Pos (0U)
18389 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
18390 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
18391 #define SYSCFG_CCCR_PCC_Pos (4U)
18392 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
18393 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
18394 /****************** Bit definition for SYSCFG_PWRCR register *******************/
18395 #define SYSCFG_PWRCR_ODEN_Pos (0U)
18396 #define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */
18397 #define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */
18398
18399 /****************** Bit definition for SYSCFG_PKGR register *******************/
18400 #define SYSCFG_PKGR_PKG_Pos (0U)
18401 #define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
18402 #define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
18403
18404 /****************** Bit definition for SYSCFG_UR0 register *******************/
18405 #define SYSCFG_UR0_BKS_Pos (0U)
18406 #define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
18407 #define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
18408 #define SYSCFG_UR0_RDP_Pos (16U)
18409 #define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
18410 #define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
18411
18412 /****************** Bit definition for SYSCFG_UR2 register *******************/
18413 #define SYSCFG_UR2_BORH_Pos (0U)
18414 #define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
18415 #define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
18416 #define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */
18417 #define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */
18418 #define SYSCFG_UR2_BOOT_ADD0_Pos (16U)
18419 #define SYSCFG_UR2_BOOT_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BOOT_ADD0_Pos) /*!< 0xFFFF0000 */
18420 #define SYSCFG_UR2_BOOT_ADD0 SYSCFG_UR2_BOOT_ADD0_Msk /*!< Core Boot Address 0 */
18421 /****************** Bit definition for SYSCFG_UR3 register *******************/
18422 #define SYSCFG_UR3_BOOT_ADD1_Pos (0U)
18423 #define SYSCFG_UR3_BOOT_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BOOT_ADD1_Pos) /*!< 0x0000FFFF */
18424 #define SYSCFG_UR3_BOOT_ADD1 SYSCFG_UR3_BOOT_ADD1_Msk /*!< Core Boot Address 1 */
18425
18426 /****************** Bit definition for SYSCFG_UR4 register *******************/
18427
18428 #define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
18429 #define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
18430 #define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
18431
18432 /****************** Bit definition for SYSCFG_UR5 register *******************/
18433 #define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
18434 #define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
18435 #define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
18436 #define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
18437 #define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
18438 #define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
18439
18440 /****************** Bit definition for SYSCFG_UR6 register *******************/
18441 #define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
18442 #define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
18443 #define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
18444 #define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
18445 #define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
18446 #define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
18447
18448 /****************** Bit definition for SYSCFG_UR7 register *******************/
18449 #define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
18450 #define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
18451 #define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
18452 #define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
18453 #define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
18454 #define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
18455
18456 /****************** Bit definition for SYSCFG_UR8 register *******************/
18457 #define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
18458 #define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
18459 #define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
18460 #define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
18461 #define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
18462 #define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
18463
18464 /****************** Bit definition for SYSCFG_UR9 register *******************/
18465 #define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
18466 #define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
18467 #define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
18468 #define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
18469 #define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
18470 #define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
18471
18472 /****************** Bit definition for SYSCFG_UR10 register *******************/
18473 #define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
18474 #define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
18475 #define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
18476 #define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
18477 #define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
18478 #define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
18479
18480 /****************** Bit definition for SYSCFG_UR11 register *******************/
18481 #define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
18482 #define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
18483 #define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
18484 #define SYSCFG_UR11_IWDG1M_Pos (16U)
18485 #define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
18486 #define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
18487
18488 /****************** Bit definition for SYSCFG_UR12 register *******************/
18489
18490 #define SYSCFG_UR12_SECURE_Pos (16U)
18491 #define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
18492 #define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
18493
18494 /****************** Bit definition for SYSCFG_UR13 register *******************/
18495 #define SYSCFG_UR13_SDRS_Pos (0U)
18496 #define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
18497 #define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
18498 #define SYSCFG_UR13_D1SBRST_Pos (16U)
18499 #define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
18500 #define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
18501
18502 /****************** Bit definition for SYSCFG_UR14 register *******************/
18503 #define SYSCFG_UR14_D1STPRST_Pos (0U)
18504 #define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
18505 #define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
18506
18507 /****************** Bit definition for SYSCFG_UR15 register *******************/
18508 #define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
18509 #define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
18510 #define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
18511
18512 /****************** Bit definition for SYSCFG_UR16 register *******************/
18513 #define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
18514 #define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
18515 #define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
18516 #define SYSCFG_UR16_PKP_Pos (16U)
18517 #define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
18518 #define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
18519
18520 /****************** Bit definition for SYSCFG_UR17 register *******************/
18521 #define SYSCFG_UR17_IOHSLV_Pos (0U)
18522 #define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
18523 #define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
18524
18525
18526 /******************************************************************************/
18527 /* */
18528 /* TIM */
18529 /* */
18530 /******************************************************************************/
18531 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
18532
18533 /******************* Bit definition for TIM_CR1 register ********************/
18534 #define TIM_CR1_CEN_Pos (0U)
18535 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
18536 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
18537 #define TIM_CR1_UDIS_Pos (1U)
18538 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
18539 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
18540 #define TIM_CR1_URS_Pos (2U)
18541 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
18542 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
18543 #define TIM_CR1_OPM_Pos (3U)
18544 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
18545 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
18546 #define TIM_CR1_DIR_Pos (4U)
18547 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
18548 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
18549
18550 #define TIM_CR1_CMS_Pos (5U)
18551 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
18552 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
18553 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
18554 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
18555
18556 #define TIM_CR1_ARPE_Pos (7U)
18557 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
18558 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
18559
18560 #define TIM_CR1_CKD_Pos (8U)
18561 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
18562 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
18563 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
18564 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
18565
18566 #define TIM_CR1_UIFREMAP_Pos (11U)
18567 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
18568 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
18569
18570 /******************* Bit definition for TIM_CR2 register ********************/
18571 #define TIM_CR2_CCPC_Pos (0U)
18572 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
18573 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
18574 #define TIM_CR2_CCUS_Pos (2U)
18575 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
18576 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
18577 #define TIM_CR2_CCDS_Pos (3U)
18578 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
18579 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
18580
18581 #define TIM_CR2_MMS_Pos (4U)
18582 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
18583 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
18584 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
18585 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
18586 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
18587
18588 #define TIM_CR2_TI1S_Pos (7U)
18589 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
18590 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
18591 #define TIM_CR2_OIS1_Pos (8U)
18592 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
18593 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
18594 #define TIM_CR2_OIS1N_Pos (9U)
18595 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
18596 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
18597 #define TIM_CR2_OIS2_Pos (10U)
18598 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
18599 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
18600 #define TIM_CR2_OIS2N_Pos (11U)
18601 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
18602 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
18603 #define TIM_CR2_OIS3_Pos (12U)
18604 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
18605 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
18606 #define TIM_CR2_OIS3N_Pos (13U)
18607 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
18608 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
18609 #define TIM_CR2_OIS4_Pos (14U)
18610 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
18611 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
18612 #define TIM_CR2_OIS5_Pos (16U)
18613 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
18614 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
18615 #define TIM_CR2_OIS6_Pos (17U)
18616 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
18617 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
18618
18619 #define TIM_CR2_MMS2_Pos (20U)
18620 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
18621 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
18622 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
18623 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
18624 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
18625 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
18626
18627 /******************* Bit definition for TIM_SMCR register *******************/
18628 #define TIM_SMCR_SMS_Pos (0U)
18629 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
18630 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
18631 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
18632 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
18633 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
18634 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
18635
18636 #define TIM_SMCR_TS_Pos (4U)
18637 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
18638 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
18639 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
18640 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
18641 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
18642 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
18643 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
18644
18645 #define TIM_SMCR_MSM_Pos (7U)
18646 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
18647 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
18648
18649 #define TIM_SMCR_ETF_Pos (8U)
18650 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
18651 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
18652 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
18653 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
18654 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
18655 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
18656
18657 #define TIM_SMCR_ETPS_Pos (12U)
18658 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
18659 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
18660 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
18661 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
18662
18663 #define TIM_SMCR_ECE_Pos (14U)
18664 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
18665 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
18666 #define TIM_SMCR_ETP_Pos (15U)
18667 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
18668 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
18669
18670 /******************* Bit definition for TIM_DIER register *******************/
18671 #define TIM_DIER_UIE_Pos (0U)
18672 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
18673 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
18674 #define TIM_DIER_CC1IE_Pos (1U)
18675 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
18676 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
18677 #define TIM_DIER_CC2IE_Pos (2U)
18678 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
18679 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
18680 #define TIM_DIER_CC3IE_Pos (3U)
18681 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
18682 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
18683 #define TIM_DIER_CC4IE_Pos (4U)
18684 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
18685 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
18686 #define TIM_DIER_COMIE_Pos (5U)
18687 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
18688 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
18689 #define TIM_DIER_TIE_Pos (6U)
18690 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
18691 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
18692 #define TIM_DIER_BIE_Pos (7U)
18693 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
18694 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
18695 #define TIM_DIER_UDE_Pos (8U)
18696 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
18697 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
18698 #define TIM_DIER_CC1DE_Pos (9U)
18699 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
18700 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
18701 #define TIM_DIER_CC2DE_Pos (10U)
18702 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
18703 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
18704 #define TIM_DIER_CC3DE_Pos (11U)
18705 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
18706 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
18707 #define TIM_DIER_CC4DE_Pos (12U)
18708 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
18709 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
18710 #define TIM_DIER_COMDE_Pos (13U)
18711 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
18712 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
18713 #define TIM_DIER_TDE_Pos (14U)
18714 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
18715 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
18716
18717 /******************** Bit definition for TIM_SR register ********************/
18718 #define TIM_SR_UIF_Pos (0U)
18719 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
18720 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
18721 #define TIM_SR_CC1IF_Pos (1U)
18722 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
18723 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
18724 #define TIM_SR_CC2IF_Pos (2U)
18725 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
18726 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
18727 #define TIM_SR_CC3IF_Pos (3U)
18728 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
18729 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
18730 #define TIM_SR_CC4IF_Pos (4U)
18731 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
18732 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
18733 #define TIM_SR_COMIF_Pos (5U)
18734 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
18735 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
18736 #define TIM_SR_TIF_Pos (6U)
18737 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
18738 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
18739 #define TIM_SR_BIF_Pos (7U)
18740 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
18741 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
18742 #define TIM_SR_B2IF_Pos (8U)
18743 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
18744 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
18745 #define TIM_SR_CC1OF_Pos (9U)
18746 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
18747 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
18748 #define TIM_SR_CC2OF_Pos (10U)
18749 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
18750 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
18751 #define TIM_SR_CC3OF_Pos (11U)
18752 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
18753 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
18754 #define TIM_SR_CC4OF_Pos (12U)
18755 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
18756 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
18757 #define TIM_SR_CC5IF_Pos (16U)
18758 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
18759 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
18760 #define TIM_SR_CC6IF_Pos (17U)
18761 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
18762 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
18763 #define TIM_SR_SBIF_Pos (13U)
18764 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
18765 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
18766
18767 /******************* Bit definition for TIM_EGR register ********************/
18768 #define TIM_EGR_UG_Pos (0U)
18769 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
18770 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
18771 #define TIM_EGR_CC1G_Pos (1U)
18772 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
18773 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
18774 #define TIM_EGR_CC2G_Pos (2U)
18775 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
18776 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
18777 #define TIM_EGR_CC3G_Pos (3U)
18778 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
18779 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
18780 #define TIM_EGR_CC4G_Pos (4U)
18781 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
18782 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
18783 #define TIM_EGR_COMG_Pos (5U)
18784 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
18785 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
18786 #define TIM_EGR_TG_Pos (6U)
18787 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
18788 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
18789 #define TIM_EGR_BG_Pos (7U)
18790 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
18791 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
18792 #define TIM_EGR_B2G_Pos (8U)
18793 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
18794 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
18795
18796
18797 /****************** Bit definition for TIM_CCMR1 register *******************/
18798 #define TIM_CCMR1_CC1S_Pos (0U)
18799 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
18800 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
18801 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
18802 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
18803
18804 #define TIM_CCMR1_OC1FE_Pos (2U)
18805 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
18806 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
18807 #define TIM_CCMR1_OC1PE_Pos (3U)
18808 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
18809 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
18810
18811 #define TIM_CCMR1_OC1M_Pos (4U)
18812 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
18813 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
18814 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
18815 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
18816 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
18817 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
18818
18819 #define TIM_CCMR1_OC1CE_Pos (7U)
18820 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
18821 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
18822
18823 #define TIM_CCMR1_CC2S_Pos (8U)
18824 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
18825 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
18826 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
18827 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
18828
18829 #define TIM_CCMR1_OC2FE_Pos (10U)
18830 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
18831 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
18832 #define TIM_CCMR1_OC2PE_Pos (11U)
18833 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
18834 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
18835
18836 #define TIM_CCMR1_OC2M_Pos (12U)
18837 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
18838 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
18839 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
18840 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
18841 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
18842 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
18843
18844 #define TIM_CCMR1_OC2CE_Pos (15U)
18845 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
18846 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
18847
18848 /*----------------------------------------------------------------------------*/
18849
18850 #define TIM_CCMR1_IC1PSC_Pos (2U)
18851 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
18852 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
18853 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
18854 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
18855
18856 #define TIM_CCMR1_IC1F_Pos (4U)
18857 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
18858 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
18859 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
18860 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
18861 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
18862 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
18863
18864 #define TIM_CCMR1_IC2PSC_Pos (10U)
18865 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
18866 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
18867 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
18868 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
18869
18870 #define TIM_CCMR1_IC2F_Pos (12U)
18871 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
18872 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
18873 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
18874 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
18875 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
18876 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
18877
18878 /****************** Bit definition for TIM_CCMR2 register *******************/
18879 #define TIM_CCMR2_CC3S_Pos (0U)
18880 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
18881 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
18882 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
18883 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
18884
18885 #define TIM_CCMR2_OC3FE_Pos (2U)
18886 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
18887 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
18888 #define TIM_CCMR2_OC3PE_Pos (3U)
18889 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
18890 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
18891
18892 #define TIM_CCMR2_OC3M_Pos (4U)
18893 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
18894 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
18895 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
18896 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
18897 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
18898 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
18899
18900 #define TIM_CCMR2_OC3CE_Pos (7U)
18901 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
18902 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
18903
18904 #define TIM_CCMR2_CC4S_Pos (8U)
18905 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
18906 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
18907 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
18908 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
18909
18910 #define TIM_CCMR2_OC4FE_Pos (10U)
18911 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
18912 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
18913 #define TIM_CCMR2_OC4PE_Pos (11U)
18914 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
18915 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
18916
18917 #define TIM_CCMR2_OC4M_Pos (12U)
18918 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
18919 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
18920 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
18921 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
18922 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
18923 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
18924
18925 #define TIM_CCMR2_OC4CE_Pos (15U)
18926 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
18927 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
18928
18929 /*----------------------------------------------------------------------------*/
18930
18931 #define TIM_CCMR2_IC3PSC_Pos (2U)
18932 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
18933 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
18934 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
18935 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
18936
18937 #define TIM_CCMR2_IC3F_Pos (4U)
18938 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
18939 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
18940 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
18941 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
18942 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
18943 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
18944
18945 #define TIM_CCMR2_IC4PSC_Pos (10U)
18946 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
18947 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
18948 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
18949 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
18950
18951 #define TIM_CCMR2_IC4F_Pos (12U)
18952 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
18953 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
18954 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
18955 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
18956 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
18957 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
18958
18959 /******************* Bit definition for TIM_CCER register *******************/
18960 #define TIM_CCER_CC1E_Pos (0U)
18961 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
18962 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
18963 #define TIM_CCER_CC1P_Pos (1U)
18964 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
18965 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
18966 #define TIM_CCER_CC1NE_Pos (2U)
18967 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
18968 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
18969 #define TIM_CCER_CC1NP_Pos (3U)
18970 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
18971 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
18972 #define TIM_CCER_CC2E_Pos (4U)
18973 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
18974 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
18975 #define TIM_CCER_CC2P_Pos (5U)
18976 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
18977 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
18978 #define TIM_CCER_CC2NE_Pos (6U)
18979 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
18980 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
18981 #define TIM_CCER_CC2NP_Pos (7U)
18982 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
18983 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
18984 #define TIM_CCER_CC3E_Pos (8U)
18985 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
18986 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
18987 #define TIM_CCER_CC3P_Pos (9U)
18988 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
18989 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
18990 #define TIM_CCER_CC3NE_Pos (10U)
18991 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
18992 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
18993 #define TIM_CCER_CC3NP_Pos (11U)
18994 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
18995 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
18996 #define TIM_CCER_CC4E_Pos (12U)
18997 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
18998 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
18999 #define TIM_CCER_CC4P_Pos (13U)
19000 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
19001 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
19002 #define TIM_CCER_CC4NP_Pos (15U)
19003 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
19004 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
19005 #define TIM_CCER_CC5E_Pos (16U)
19006 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
19007 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
19008 #define TIM_CCER_CC5P_Pos (17U)
19009 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
19010 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
19011 #define TIM_CCER_CC6E_Pos (20U)
19012 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
19013 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
19014 #define TIM_CCER_CC6P_Pos (21U)
19015 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
19016 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
19017 /******************* Bit definition for TIM_CNT register ********************/
19018 #define TIM_CNT_CNT_Pos (0U)
19019 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
19020 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
19021 #define TIM_CNT_UIFCPY_Pos (31U)
19022 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
19023 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
19024 /******************* Bit definition for TIM_PSC register ********************/
19025 #define TIM_PSC_PSC_Pos (0U)
19026 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
19027 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
19028
19029 /******************* Bit definition for TIM_ARR register ********************/
19030 #define TIM_ARR_ARR_Pos (0U)
19031 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
19032 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
19033
19034 /******************* Bit definition for TIM_RCR register ********************/
19035 #define TIM_RCR_REP_Pos (0U)
19036 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
19037 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
19038
19039 /******************* Bit definition for TIM_CCR1 register *******************/
19040 #define TIM_CCR1_CCR1_Pos (0U)
19041 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
19042 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
19043
19044 /******************* Bit definition for TIM_CCR2 register *******************/
19045 #define TIM_CCR2_CCR2_Pos (0U)
19046 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
19047 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
19048
19049 /******************* Bit definition for TIM_CCR3 register *******************/
19050 #define TIM_CCR3_CCR3_Pos (0U)
19051 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
19052 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
19053
19054 /******************* Bit definition for TIM_CCR4 register *******************/
19055 #define TIM_CCR4_CCR4_Pos (0U)
19056 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
19057 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
19058
19059 /******************* Bit definition for TIM_CCR5 register *******************/
19060 #define TIM_CCR5_CCR5_Pos (0U)
19061 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
19062 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
19063 #define TIM_CCR5_GC5C1_Pos (29U)
19064 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
19065 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
19066 #define TIM_CCR5_GC5C2_Pos (30U)
19067 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
19068 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
19069 #define TIM_CCR5_GC5C3_Pos (31U)
19070 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
19071 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
19072
19073 /******************* Bit definition for TIM_CCR6 register *******************/
19074 #define TIM_CCR6_CCR6_Pos (0U)
19075 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
19076 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
19077
19078 /******************* Bit definition for TIM_BDTR register *******************/
19079 #define TIM_BDTR_DTG_Pos (0U)
19080 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
19081 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
19082 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
19083 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
19084 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
19085 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
19086 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
19087 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
19088 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
19089 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
19090
19091 #define TIM_BDTR_LOCK_Pos (8U)
19092 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
19093 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
19094 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
19095 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
19096
19097 #define TIM_BDTR_OSSI_Pos (10U)
19098 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
19099 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
19100 #define TIM_BDTR_OSSR_Pos (11U)
19101 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
19102 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
19103 #define TIM_BDTR_BKE_Pos (12U)
19104 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
19105 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
19106 #define TIM_BDTR_BKP_Pos (13U)
19107 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
19108 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
19109 #define TIM_BDTR_AOE_Pos (14U)
19110 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
19111 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
19112 #define TIM_BDTR_MOE_Pos (15U)
19113 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
19114 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
19115
19116 #define TIM_BDTR_BKF_Pos (16U)
19117 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
19118 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
19119 #define TIM_BDTR_BK2F_Pos (20U)
19120 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
19121 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
19122
19123 #define TIM_BDTR_BK2E_Pos (24U)
19124 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
19125 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
19126 #define TIM_BDTR_BK2P_Pos (25U)
19127 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
19128 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
19129
19130 /******************* Bit definition for TIM_DCR register ********************/
19131 #define TIM_DCR_DBA_Pos (0U)
19132 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
19133 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
19134 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
19135 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
19136 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
19137 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
19138 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
19139
19140 #define TIM_DCR_DBL_Pos (8U)
19141 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
19142 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
19143 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
19144 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
19145 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
19146 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
19147 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
19148
19149 /******************* Bit definition for TIM_DMAR register *******************/
19150 #define TIM_DMAR_DMAB_Pos (0U)
19151 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
19152 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
19153
19154 /****************** Bit definition for TIM_CCMR3 register *******************/
19155 #define TIM_CCMR3_OC5FE_Pos (2U)
19156 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
19157 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
19158 #define TIM_CCMR3_OC5PE_Pos (3U)
19159 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
19160 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
19161
19162 #define TIM_CCMR3_OC5M_Pos (4U)
19163 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
19164 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
19165 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
19166 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
19167 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
19168 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
19169
19170 #define TIM_CCMR3_OC5CE_Pos (7U)
19171 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
19172 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
19173
19174 #define TIM_CCMR3_OC6FE_Pos (10U)
19175 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
19176 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
19177 #define TIM_CCMR3_OC6PE_Pos (11U)
19178 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
19179 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
19180
19181 #define TIM_CCMR3_OC6M_Pos (12U)
19182 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
19183 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
19184 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
19185 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
19186 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
19187 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
19188
19189 #define TIM_CCMR3_OC6CE_Pos (15U)
19190 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
19191 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
19192 /******************* Bit definition for TIM1_AF1 register *********************/
19193 #define TIM1_AF1_BKINE_Pos (0U)
19194 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
19195 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19196 #define TIM1_AF1_BKCMP1E_Pos (1U)
19197 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19198 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19199 #define TIM1_AF1_BKCMP2E_Pos (2U)
19200 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19201 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19202 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
19203 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
19204 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
19205 #define TIM1_AF1_BKINP_Pos (9U)
19206 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
19207 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19208 #define TIM1_AF1_BKCMP1P_Pos (10U)
19209 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19210 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19211 #define TIM1_AF1_BKCMP2P_Pos (11U)
19212 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19213 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19214
19215 #define TIM1_AF1_ETRSEL_Pos (14U)
19216 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19217 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
19218 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19219 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19220 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19221 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19222
19223 /******************* Bit definition for TIM1_AF2 register *********************/
19224 #define TIM1_AF2_BK2INE_Pos (0U)
19225 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
19226 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
19227 #define TIM1_AF2_BK2CMP1E_Pos (1U)
19228 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
19229 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
19230 #define TIM1_AF2_BK2CMP2E_Pos (2U)
19231 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
19232 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
19233 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
19234 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
19235 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
19236 #define TIM1_AF2_BK2INP_Pos (9U)
19237 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
19238 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
19239 #define TIM1_AF2_BK2CMP1P_Pos (10U)
19240 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
19241 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
19242 #define TIM1_AF2_BK2CMP2P_Pos (11U)
19243 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
19244 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
19245
19246 /******************* Bit definition for TIM_TISEL register *********************/
19247 #define TIM_TISEL_TI1SEL_Pos (0U)
19248 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
19249 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
19250 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
19251 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
19252 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
19253 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
19254
19255 #define TIM_TISEL_TI2SEL_Pos (8U)
19256 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
19257 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
19258 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
19259 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
19260 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
19261 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
19262
19263 #define TIM_TISEL_TI3SEL_Pos (16U)
19264 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
19265 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
19266 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
19267 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
19268 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
19269 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
19270
19271 #define TIM_TISEL_TI4SEL_Pos (24U)
19272 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
19273 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
19274 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
19275 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
19276 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
19277 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
19278
19279 /******************* Bit definition for TIM8_AF1 register *********************/
19280 #define TIM8_AF1_BKINE_Pos (0U)
19281 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
19282 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19283 #define TIM8_AF1_BKCMP1E_Pos (1U)
19284 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19285 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19286 #define TIM8_AF1_BKCMP2E_Pos (2U)
19287 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19288 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19289 #define TIM8_AF1_BKDFBK2E_Pos (8U)
19290 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
19291 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
19292 #define TIM8_AF1_BKINP_Pos (9U)
19293 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
19294 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19295 #define TIM8_AF1_BKCMP1P_Pos (10U)
19296 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19297 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19298 #define TIM8_AF1_BKCMP2P_Pos (11U)
19299 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19300 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19301
19302 #define TIM8_AF1_ETRSEL_Pos (14U)
19303 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19304 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
19305 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19306 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19307 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19308 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19309 /******************* Bit definition for TIM8_AF2 register *********************/
19310 #define TIM8_AF2_BK2INE_Pos (0U)
19311 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
19312 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
19313 #define TIM8_AF2_BK2CMP1E_Pos (1U)
19314 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
19315 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
19316 #define TIM8_AF2_BK2CMP2E_Pos (2U)
19317 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
19318 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
19319 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
19320 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
19321 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
19322 #define TIM8_AF2_BK2INP_Pos (9U)
19323 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
19324 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
19325 #define TIM8_AF2_BK2CMP1P_Pos (10U)
19326 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
19327 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
19328 #define TIM8_AF2_BK2CMP2P_Pos (11U)
19329 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
19330 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
19331
19332 /******************* Bit definition for TIM2_AF1 register *********************/
19333 #define TIM2_AF1_ETRSEL_Pos (14U)
19334 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19335 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
19336 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19337 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19338 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19339 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19340
19341 /******************* Bit definition for TIM3_AF1 register *********************/
19342 #define TIM3_AF1_ETRSEL_Pos (14U)
19343 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19344 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
19345 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19346 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19347 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19348 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19349
19350 /******************* Bit definition for TIM5_AF1 register *********************/
19351 #define TIM5_AF1_ETRSEL_Pos (14U)
19352 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
19353 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
19354 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
19355 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
19356 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
19357 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
19358
19359 /******************* Bit definition for TIM15_AF1 register *********************/
19360 #define TIM15_AF1_BKINE_Pos (0U)
19361 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
19362 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19363 #define TIM15_AF1_BKCMP1E_Pos (1U)
19364 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19365 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19366 #define TIM15_AF1_BKCMP2E_Pos (2U)
19367 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19368 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19369 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
19370 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
19371 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
19372 #define TIM15_AF1_BKINP_Pos (9U)
19373 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
19374 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19375 #define TIM15_AF1_BKCMP1P_Pos (10U)
19376 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19377 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19378 #define TIM15_AF1_BKCMP2P_Pos (11U)
19379 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19380 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19381
19382 /******************* Bit definition for TIM16_ register *********************/
19383 #define TIM16_AF1_BKINE_Pos (0U)
19384 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
19385 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19386 #define TIM16_AF1_BKCMP1E_Pos (1U)
19387 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19388 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19389 #define TIM16_AF1_BKCMP2E_Pos (2U)
19390 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19391 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19392 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
19393 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
19394 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
19395 #define TIM16_AF1_BKINP_Pos (9U)
19396 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
19397 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19398 #define TIM16_AF1_BKCMP1P_Pos (10U)
19399 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19400 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19401 #define TIM16_AF1_BKCMP2P_Pos (11U)
19402 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19403 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19404
19405 /******************* Bit definition for TIM17_AF1 register *********************/
19406 #define TIM17_AF1_BKINE_Pos (0U)
19407 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
19408 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
19409 #define TIM17_AF1_BKCMP1E_Pos (1U)
19410 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
19411 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
19412 #define TIM17_AF1_BKCMP2E_Pos (2U)
19413 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
19414 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
19415 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
19416 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
19417 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
19418 #define TIM17_AF1_BKINP_Pos (9U)
19419 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
19420 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
19421 #define TIM17_AF1_BKCMP1P_Pos (10U)
19422 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
19423 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
19424 #define TIM17_AF1_BKCMP2P_Pos (11U)
19425 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
19426 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
19427
19428 /******************************************************************************/
19429 /* */
19430 /* Low Power Timer (LPTTIM) */
19431 /* */
19432 /******************************************************************************/
19433 /****************** Bit definition for LPTIM_ISR register *******************/
19434 #define LPTIM_ISR_CMPM_Pos (0U)
19435 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
19436 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
19437 #define LPTIM_ISR_ARRM_Pos (1U)
19438 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
19439 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
19440 #define LPTIM_ISR_EXTTRIG_Pos (2U)
19441 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
19442 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
19443 #define LPTIM_ISR_CMPOK_Pos (3U)
19444 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
19445 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
19446 #define LPTIM_ISR_ARROK_Pos (4U)
19447 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
19448 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
19449 #define LPTIM_ISR_UP_Pos (5U)
19450 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
19451 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
19452 #define LPTIM_ISR_DOWN_Pos (6U)
19453 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
19454 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
19455
19456 /****************** Bit definition for LPTIM_ICR register *******************/
19457 #define LPTIM_ICR_CMPMCF_Pos (0U)
19458 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
19459 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
19460 #define LPTIM_ICR_ARRMCF_Pos (1U)
19461 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
19462 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
19463 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
19464 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
19465 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
19466 #define LPTIM_ICR_CMPOKCF_Pos (3U)
19467 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
19468 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
19469 #define LPTIM_ICR_ARROKCF_Pos (4U)
19470 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
19471 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
19472 #define LPTIM_ICR_UPCF_Pos (5U)
19473 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
19474 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
19475 #define LPTIM_ICR_DOWNCF_Pos (6U)
19476 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
19477 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
19478
19479 /****************** Bit definition for LPTIM_IER register ********************/
19480 #define LPTIM_IER_CMPMIE_Pos (0U)
19481 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
19482 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
19483 #define LPTIM_IER_ARRMIE_Pos (1U)
19484 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
19485 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
19486 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
19487 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
19488 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
19489 #define LPTIM_IER_CMPOKIE_Pos (3U)
19490 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
19491 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
19492 #define LPTIM_IER_ARROKIE_Pos (4U)
19493 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
19494 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
19495 #define LPTIM_IER_UPIE_Pos (5U)
19496 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
19497 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
19498 #define LPTIM_IER_DOWNIE_Pos (6U)
19499 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
19500 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
19501
19502 /****************** Bit definition for LPTIM_CFGR register *******************/
19503 #define LPTIM_CFGR_CKSEL_Pos (0U)
19504 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
19505 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
19506
19507 #define LPTIM_CFGR_CKPOL_Pos (1U)
19508 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
19509 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
19510 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
19511 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
19512
19513 #define LPTIM_CFGR_CKFLT_Pos (3U)
19514 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
19515 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
19516 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
19517 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
19518
19519 #define LPTIM_CFGR_TRGFLT_Pos (6U)
19520 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
19521 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
19522 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
19523 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
19524
19525 #define LPTIM_CFGR_PRESC_Pos (9U)
19526 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
19527 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
19528 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
19529 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
19530 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
19531
19532 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
19533 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
19534 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
19535 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
19536 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
19537 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
19538
19539 #define LPTIM_CFGR_TRIGEN_Pos (17U)
19540 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
19541 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
19542 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
19543 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
19544
19545 #define LPTIM_CFGR_TIMOUT_Pos (19U)
19546 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
19547 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
19548 #define LPTIM_CFGR_WAVE_Pos (20U)
19549 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
19550 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
19551 #define LPTIM_CFGR_WAVPOL_Pos (21U)
19552 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
19553 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
19554 #define LPTIM_CFGR_PRELOAD_Pos (22U)
19555 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
19556 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
19557 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
19558 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
19559 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
19560 #define LPTIM_CFGR_ENC_Pos (24U)
19561 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
19562 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
19563
19564 /****************** Bit definition for LPTIM_CR register ********************/
19565 #define LPTIM_CR_ENABLE_Pos (0U)
19566 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
19567 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
19568 #define LPTIM_CR_SNGSTRT_Pos (1U)
19569 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
19570 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
19571 #define LPTIM_CR_CNTSTRT_Pos (2U)
19572 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
19573 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
19574 #define LPTIM_CR_COUNTRST_Pos (3U)
19575 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
19576 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
19577 #define LPTIM_CR_RSTARE_Pos (4U)
19578 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
19579 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
19580
19581
19582 /****************** Bit definition for LPTIM_CMP register *******************/
19583 #define LPTIM_CMP_CMP_Pos (0U)
19584 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
19585 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
19586
19587 /****************** Bit definition for LPTIM_ARR register *******************/
19588 #define LPTIM_ARR_ARR_Pos (0U)
19589 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
19590 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
19591
19592 /****************** Bit definition for LPTIM_CNT register *******************/
19593 #define LPTIM_CNT_CNT_Pos (0U)
19594 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
19595 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
19596
19597 /****************** Bit definition for LPTIM_CFGR2 register *****************/
19598 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
19599 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
19600 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
19601 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
19602 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
19603 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
19604 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
19605 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
19606 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
19607 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
19608
19609 /******************************************************************************/
19610 /* */
19611 /* Analog Comparators (COMP) */
19612 /* */
19613 /******************************************************************************/
19614
19615 /******************* Bit definition for COMP_SR register ********************/
19616 #define COMP_SR_C1VAL_Pos (0U)
19617 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
19618 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
19619 #define COMP_SR_C2VAL_Pos (1U)
19620 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
19621 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
19622 #define COMP_SR_C1IF_Pos (16U)
19623 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
19624 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
19625 #define COMP_SR_C2IF_Pos (17U)
19626 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
19627 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
19628 /******************* Bit definition for COMP_ICFR register ********************/
19629 #define COMP_ICFR_C1IF_Pos (16U)
19630 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
19631 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
19632 #define COMP_ICFR_C2IF_Pos (17U)
19633 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
19634 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
19635 /******************* Bit definition for COMP_OR register ********************/
19636 #define COMP_OR_AFOPA6_Pos (0U)
19637 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
19638 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
19639 #define COMP_OR_AFOPA8_Pos (1U)
19640 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
19641 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
19642 #define COMP_OR_AFOPB12_Pos (2U)
19643 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
19644 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
19645 #define COMP_OR_AFOPE6_Pos (3U)
19646 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
19647 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
19648 #define COMP_OR_AFOPE15_Pos (4U)
19649 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
19650 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
19651 #define COMP_OR_AFOPG2_Pos (5U)
19652 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
19653 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
19654 #define COMP_OR_AFOPG3_Pos (6U)
19655 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
19656 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
19657 #define COMP_OR_AFOPG4_Pos (7U)
19658 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
19659 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
19660 #define COMP_OR_AFOPI1_Pos (8U)
19661 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
19662 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
19663 #define COMP_OR_AFOPI4_Pos (9U)
19664 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
19665 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
19666 #define COMP_OR_AFOPK2_Pos (10U)
19667 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
19668 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
19669
19670 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
19671 #define COMP_CFGRx_EN_Pos (0U)
19672 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
19673 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
19674 #define COMP_CFGRx_BRGEN_Pos (1U)
19675 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
19676 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
19677 #define COMP_CFGRx_SCALEN_Pos (2U)
19678 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
19679 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
19680 #define COMP_CFGRx_POLARITY_Pos (3U)
19681 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
19682 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
19683 #define COMP_CFGRx_WINMODE_Pos (4U)
19684 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
19685 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
19686 #define COMP_CFGRx_ITEN_Pos (6U)
19687 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
19688 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
19689 #define COMP_CFGRx_HYST_Pos (8U)
19690 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
19691 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
19692 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
19693 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
19694 #define COMP_CFGRx_PWRMODE_Pos (12U)
19695 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
19696 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
19697 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
19698 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
19699 #define COMP_CFGRx_INMSEL_Pos (16U)
19700 #define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
19701 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
19702 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
19703 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
19704 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
19705 #define COMP_CFGRx_INPSEL_Pos (20U)
19706 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
19707 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
19708 #define COMP_CFGRx_BLANKING_Pos (24U)
19709 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
19710 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
19711 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
19712 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
19713 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
19714 #define COMP_CFGRx_LOCK_Pos (31U)
19715 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
19716 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
19717
19718
19719 /******************************************************************************/
19720 /* */
19721 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
19722 /* */
19723 /******************************************************************************/
19724 /****************** Bit definition for USART_CR1 register *******************/
19725 #define USART_CR1_UE_Pos (0U)
19726 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
19727 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
19728 #define USART_CR1_UESM_Pos (1U)
19729 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
19730 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
19731 #define USART_CR1_RE_Pos (2U)
19732 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
19733 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
19734 #define USART_CR1_TE_Pos (3U)
19735 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
19736 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
19737 #define USART_CR1_IDLEIE_Pos (4U)
19738 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
19739 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
19740 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
19741 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
19742 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
19743 #define USART_CR1_TCIE_Pos (6U)
19744 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
19745 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
19746 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
19747 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
19748 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
19749 #define USART_CR1_PEIE_Pos (8U)
19750 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
19751 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
19752 #define USART_CR1_PS_Pos (9U)
19753 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
19754 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
19755 #define USART_CR1_PCE_Pos (10U)
19756 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
19757 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
19758 #define USART_CR1_WAKE_Pos (11U)
19759 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
19760 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
19761 #define USART_CR1_M_Pos (12U)
19762 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
19763 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
19764 #define USART_CR1_M0_Pos (12U)
19765 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
19766 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
19767 #define USART_CR1_MME_Pos (13U)
19768 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
19769 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
19770 #define USART_CR1_CMIE_Pos (14U)
19771 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
19772 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
19773 #define USART_CR1_OVER8_Pos (15U)
19774 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
19775 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
19776 #define USART_CR1_DEDT_Pos (16U)
19777 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
19778 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
19779 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
19780 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
19781 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
19782 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
19783 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
19784 #define USART_CR1_DEAT_Pos (21U)
19785 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
19786 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
19787 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
19788 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
19789 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
19790 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
19791 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
19792 #define USART_CR1_RTOIE_Pos (26U)
19793 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
19794 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
19795 #define USART_CR1_EOBIE_Pos (27U)
19796 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
19797 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
19798 #define USART_CR1_M1_Pos (28U)
19799 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
19800 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
19801 #define USART_CR1_FIFOEN_Pos (29U)
19802 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
19803 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
19804 #define USART_CR1_TXFEIE_Pos (30U)
19805 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
19806 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
19807 #define USART_CR1_RXFFIE_Pos (31U)
19808 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
19809 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
19810
19811 /* Legacy define */
19812 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
19813 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
19814
19815 /****************** Bit definition for USART_CR2 register *******************/
19816 #define USART_CR2_SLVEN_Pos (0U)
19817 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
19818 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
19819 #define USART_CR2_DIS_NSS_Pos (3U)
19820 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
19821 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
19822 #define USART_CR2_ADDM7_Pos (4U)
19823 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
19824 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
19825 #define USART_CR2_LBDL_Pos (5U)
19826 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
19827 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
19828 #define USART_CR2_LBDIE_Pos (6U)
19829 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
19830 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
19831 #define USART_CR2_LBCL_Pos (8U)
19832 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
19833 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
19834 #define USART_CR2_CPHA_Pos (9U)
19835 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
19836 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
19837 #define USART_CR2_CPOL_Pos (10U)
19838 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
19839 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
19840 #define USART_CR2_CLKEN_Pos (11U)
19841 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
19842 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
19843 #define USART_CR2_STOP_Pos (12U)
19844 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
19845 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
19846 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
19847 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
19848 #define USART_CR2_LINEN_Pos (14U)
19849 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
19850 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
19851 #define USART_CR2_SWAP_Pos (15U)
19852 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
19853 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
19854 #define USART_CR2_RXINV_Pos (16U)
19855 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
19856 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
19857 #define USART_CR2_TXINV_Pos (17U)
19858 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
19859 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
19860 #define USART_CR2_DATAINV_Pos (18U)
19861 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
19862 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
19863 #define USART_CR2_MSBFIRST_Pos (19U)
19864 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
19865 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
19866 #define USART_CR2_ABREN_Pos (20U)
19867 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
19868 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
19869 #define USART_CR2_ABRMODE_Pos (21U)
19870 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
19871 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
19872 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
19873 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
19874 #define USART_CR2_RTOEN_Pos (23U)
19875 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
19876 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
19877 #define USART_CR2_ADD_Pos (24U)
19878 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
19879 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
19880
19881 /****************** Bit definition for USART_CR3 register *******************/
19882 #define USART_CR3_EIE_Pos (0U)
19883 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
19884 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
19885 #define USART_CR3_IREN_Pos (1U)
19886 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
19887 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
19888 #define USART_CR3_IRLP_Pos (2U)
19889 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
19890 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
19891 #define USART_CR3_HDSEL_Pos (3U)
19892 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
19893 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
19894 #define USART_CR3_NACK_Pos (4U)
19895 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
19896 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
19897 #define USART_CR3_SCEN_Pos (5U)
19898 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
19899 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
19900 #define USART_CR3_DMAR_Pos (6U)
19901 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
19902 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
19903 #define USART_CR3_DMAT_Pos (7U)
19904 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
19905 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
19906 #define USART_CR3_RTSE_Pos (8U)
19907 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
19908 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
19909 #define USART_CR3_CTSE_Pos (9U)
19910 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
19911 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
19912 #define USART_CR3_CTSIE_Pos (10U)
19913 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
19914 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
19915 #define USART_CR3_ONEBIT_Pos (11U)
19916 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
19917 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
19918 #define USART_CR3_OVRDIS_Pos (12U)
19919 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
19920 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
19921 #define USART_CR3_DDRE_Pos (13U)
19922 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
19923 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
19924 #define USART_CR3_DEM_Pos (14U)
19925 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
19926 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
19927 #define USART_CR3_DEP_Pos (15U)
19928 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
19929 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
19930 #define USART_CR3_SCARCNT_Pos (17U)
19931 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
19932 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
19933 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
19934 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
19935 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
19936 #define USART_CR3_WUS_Pos (20U)
19937 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
19938 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
19939 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
19940 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
19941 #define USART_CR3_WUFIE_Pos (22U)
19942 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
19943 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
19944 #define USART_CR3_TXFTIE_Pos (23U)
19945 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
19946 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
19947 #define USART_CR3_TCBGTIE_Pos (24U)
19948 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
19949 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
19950 #define USART_CR3_RXFTCFG_Pos (25U)
19951 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
19952 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
19953 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
19954 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
19955 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
19956 #define USART_CR3_RXFTIE_Pos (28U)
19957 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
19958 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
19959 #define USART_CR3_TXFTCFG_Pos (29U)
19960 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
19961 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
19962 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
19963 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
19964 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
19965
19966 /****************** Bit definition for USART_BRR register *******************/
19967 #define USART_BRR_DIV_FRACTION_Pos (0U)
19968 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
19969 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
19970 #define USART_BRR_DIV_MANTISSA_Pos (4U)
19971 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
19972 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
19973
19974 /****************** Bit definition for USART_GTPR register ******************/
19975 #define USART_GTPR_PSC_Pos (0U)
19976 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
19977 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
19978 #define USART_GTPR_GT_Pos (8U)
19979 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
19980 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
19981
19982 /******************* Bit definition for USART_RTOR register *****************/
19983 #define USART_RTOR_RTO_Pos (0U)
19984 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
19985 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
19986 #define USART_RTOR_BLEN_Pos (24U)
19987 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
19988 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
19989
19990 /******************* Bit definition for USART_RQR register ******************/
19991 #define USART_RQR_ABRRQ_Pos (0U)
19992 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
19993 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
19994 #define USART_RQR_SBKRQ_Pos (1U)
19995 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
19996 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
19997 #define USART_RQR_MMRQ_Pos (2U)
19998 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
19999 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
20000 #define USART_RQR_RXFRQ_Pos (3U)
20001 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
20002 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
20003 #define USART_RQR_TXFRQ_Pos (4U)
20004 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
20005 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
20006
20007 /******************* Bit definition for USART_ISR register ******************/
20008 #define USART_ISR_PE_Pos (0U)
20009 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
20010 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
20011 #define USART_ISR_FE_Pos (1U)
20012 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
20013 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
20014 #define USART_ISR_NE_Pos (2U)
20015 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
20016 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
20017 #define USART_ISR_ORE_Pos (3U)
20018 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
20019 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
20020 #define USART_ISR_IDLE_Pos (4U)
20021 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
20022 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
20023 #define USART_ISR_RXNE_RXFNE_Pos (5U)
20024 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
20025 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
20026 #define USART_ISR_TC_Pos (6U)
20027 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
20028 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
20029 #define USART_ISR_TXE_TXFNF_Pos (7U)
20030 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
20031 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
20032 #define USART_ISR_LBDF_Pos (8U)
20033 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
20034 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
20035 #define USART_ISR_CTSIF_Pos (9U)
20036 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
20037 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
20038 #define USART_ISR_CTS_Pos (10U)
20039 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
20040 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
20041 #define USART_ISR_RTOF_Pos (11U)
20042 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
20043 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
20044 #define USART_ISR_EOBF_Pos (12U)
20045 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
20046 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
20047 #define USART_ISR_UDR_Pos (13U)
20048 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
20049 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
20050 #define USART_ISR_ABRE_Pos (14U)
20051 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
20052 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
20053 #define USART_ISR_ABRF_Pos (15U)
20054 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
20055 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
20056 #define USART_ISR_BUSY_Pos (16U)
20057 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
20058 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
20059 #define USART_ISR_CMF_Pos (17U)
20060 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
20061 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
20062 #define USART_ISR_SBKF_Pos (18U)
20063 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
20064 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
20065 #define USART_ISR_RWU_Pos (19U)
20066 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
20067 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
20068 #define USART_ISR_WUF_Pos (20U)
20069 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
20070 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
20071 #define USART_ISR_TEACK_Pos (21U)
20072 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
20073 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
20074 #define USART_ISR_REACK_Pos (22U)
20075 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
20076 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
20077 #define USART_ISR_TXFE_Pos (23U)
20078 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
20079 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
20080 #define USART_ISR_RXFF_Pos (24U)
20081 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
20082 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
20083 #define USART_ISR_TCBGT_Pos (25U)
20084 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
20085 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
20086 #define USART_ISR_RXFT_Pos (26U)
20087 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
20088 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
20089 #define USART_ISR_TXFT_Pos (27U)
20090 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
20091 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
20092
20093 /******************* Bit definition for USART_ICR register ******************/
20094 #define USART_ICR_PECF_Pos (0U)
20095 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
20096 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
20097 #define USART_ICR_FECF_Pos (1U)
20098 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
20099 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
20100 #define USART_ICR_NECF_Pos (2U)
20101 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
20102 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
20103 #define USART_ICR_ORECF_Pos (3U)
20104 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
20105 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
20106 #define USART_ICR_IDLECF_Pos (4U)
20107 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
20108 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
20109 #define USART_ICR_TXFECF_Pos (5U)
20110 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
20111 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
20112 #define USART_ICR_TCCF_Pos (6U)
20113 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
20114 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
20115 #define USART_ICR_TCBGTCF_Pos (7U)
20116 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
20117 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
20118 #define USART_ICR_LBDCF_Pos (8U)
20119 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
20120 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
20121 #define USART_ICR_CTSCF_Pos (9U)
20122 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
20123 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
20124 #define USART_ICR_RTOCF_Pos (11U)
20125 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
20126 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
20127 #define USART_ICR_EOBCF_Pos (12U)
20128 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
20129 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
20130 #define USART_ICR_UDRCF_Pos (13U)
20131 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
20132 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
20133 #define USART_ICR_CMCF_Pos (17U)
20134 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
20135 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
20136 #define USART_ICR_WUCF_Pos (20U)
20137 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
20138 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
20139
20140 /******************* Bit definition for USART_RDR register ******************/
20141 #define USART_RDR_RDR_Pos (0U)
20142 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
20143 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
20144
20145 /******************* Bit definition for USART_TDR register ******************/
20146 #define USART_TDR_TDR_Pos (0U)
20147 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
20148 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
20149
20150 /******************* Bit definition for USART_PRESC register ******************/
20151 #define USART_PRESC_PRESCALER_Pos (0U)
20152 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
20153 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
20154 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
20155 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
20156 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
20157 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
20158
20159 /******************************************************************************/
20160 /* */
20161 /* Single Wire Protocol Master Interface (SWPMI) */
20162 /* */
20163 /******************************************************************************/
20164
20165 /******************* Bit definition for SWPMI_CR register ********************/
20166 #define SWPMI_CR_RXDMA_Pos (0U)
20167 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
20168 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
20169 #define SWPMI_CR_TXDMA_Pos (1U)
20170 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
20171 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
20172 #define SWPMI_CR_RXMODE_Pos (2U)
20173 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
20174 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
20175 #define SWPMI_CR_TXMODE_Pos (3U)
20176 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
20177 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
20178 #define SWPMI_CR_LPBK_Pos (4U)
20179 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
20180 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
20181 #define SWPMI_CR_SWPACT_Pos (5U)
20182 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
20183 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
20184 #define SWPMI_CR_DEACT_Pos (10U)
20185 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
20186 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
20187 #define SWPMI_CR_SWPEN_Pos (11U)
20188 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
20189 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
20190
20191 /******************* Bit definition for SWPMI_BRR register ********************/
20192 #define SWPMI_BRR_BR_Pos (0U)
20193 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
20194 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
20195
20196 /******************* Bit definition for SWPMI_ISR register ********************/
20197 #define SWPMI_ISR_RXBFF_Pos (0U)
20198 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
20199 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
20200 #define SWPMI_ISR_TXBEF_Pos (1U)
20201 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
20202 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
20203 #define SWPMI_ISR_RXBERF_Pos (2U)
20204 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
20205 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
20206 #define SWPMI_ISR_RXOVRF_Pos (3U)
20207 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
20208 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
20209 #define SWPMI_ISR_TXUNRF_Pos (4U)
20210 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
20211 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
20212 #define SWPMI_ISR_RXNE_Pos (5U)
20213 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
20214 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
20215 #define SWPMI_ISR_TXE_Pos (6U)
20216 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
20217 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
20218 #define SWPMI_ISR_TCF_Pos (7U)
20219 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
20220 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
20221 #define SWPMI_ISR_SRF_Pos (8U)
20222 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
20223 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
20224 #define SWPMI_ISR_SUSP_Pos (9U)
20225 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
20226 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
20227 #define SWPMI_ISR_DEACTF_Pos (10U)
20228 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
20229 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
20230 #define SWPMI_ISR_RDYF_Pos (11U)
20231 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
20232 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
20233
20234 /******************* Bit definition for SWPMI_ICR register ********************/
20235 #define SWPMI_ICR_CRXBFF_Pos (0U)
20236 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
20237 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
20238 #define SWPMI_ICR_CTXBEF_Pos (1U)
20239 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
20240 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
20241 #define SWPMI_ICR_CRXBERF_Pos (2U)
20242 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
20243 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
20244 #define SWPMI_ICR_CRXOVRF_Pos (3U)
20245 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
20246 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
20247 #define SWPMI_ICR_CTXUNRF_Pos (4U)
20248 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
20249 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
20250 #define SWPMI_ICR_CTCF_Pos (7U)
20251 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
20252 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
20253 #define SWPMI_ICR_CSRF_Pos (8U)
20254 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
20255 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
20256 #define SWPMI_ICR_CRDYF_Pos (11U)
20257 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
20258 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
20259
20260 /******************* Bit definition for SWPMI_IER register ********************/
20261 #define SWPMI_IER_RXBFIE_Pos (0U)
20262 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
20263 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
20264 #define SWPMI_IER_TXBEIE_Pos (1U)
20265 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
20266 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
20267 #define SWPMI_IER_RXBERIE_Pos (2U)
20268 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
20269 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
20270 #define SWPMI_IER_RXOVRIE_Pos (3U)
20271 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
20272 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
20273 #define SWPMI_IER_TXUNRIE_Pos (4U)
20274 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
20275 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
20276 #define SWPMI_IER_RIE_Pos (5U)
20277 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
20278 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
20279 #define SWPMI_IER_TIE_Pos (6U)
20280 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
20281 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
20282 #define SWPMI_IER_TCIE_Pos (7U)
20283 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
20284 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
20285 #define SWPMI_IER_SRIE_Pos (8U)
20286 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
20287 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
20288 #define SWPMI_IER_RDYIE_Pos (11U)
20289 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
20290 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
20291
20292 /******************* Bit definition for SWPMI_RFL register ********************/
20293 #define SWPMI_RFL_RFL_Pos (0U)
20294 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
20295 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
20296 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
20297
20298 /******************* Bit definition for SWPMI_TDR register ********************/
20299 #define SWPMI_TDR_TD_Pos (0U)
20300 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
20301 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
20302
20303 /******************* Bit definition for SWPMI_RDR register ********************/
20304 #define SWPMI_RDR_RD_Pos (0U)
20305 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
20306 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
20307
20308
20309 /******************* Bit definition for SWPMI_OR register ********************/
20310 #define SWPMI_OR_TBYP_Pos (0U)
20311 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
20312 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
20313 #define SWPMI_OR_CLASS_Pos (1U)
20314 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
20315 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
20316
20317 /******************************************************************************/
20318 /* */
20319 /* Window WATCHDOG */
20320 /* */
20321 /******************************************************************************/
20322 /******************* Bit definition for WWDG_CR register ********************/
20323 #define WWDG_CR_T_Pos (0U)
20324 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
20325 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
20326 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
20327 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
20328 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
20329 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
20330 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
20331 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
20332 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
20333
20334 #define WWDG_CR_WDGA_Pos (7U)
20335 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
20336 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
20337
20338 /******************* Bit definition for WWDG_CFR register *******************/
20339 #define WWDG_CFR_W_Pos (0U)
20340 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
20341 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
20342 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
20343 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
20344 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
20345 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
20346 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
20347 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
20348 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
20349
20350 #define WWDG_CFR_EWI_Pos (9U)
20351 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
20352 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
20353
20354 #define WWDG_CFR_WDGTB_Pos (11U)
20355 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
20356 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
20357 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
20358 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
20359 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
20360
20361 /******************* Bit definition for WWDG_SR register ********************/
20362 #define WWDG_SR_EWIF_Pos (0U)
20363 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
20364 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
20365
20366
20367 /******************************************************************************/
20368 /* */
20369 /* DBG */
20370 /* */
20371 /******************************************************************************/
20372
20373 /******************** Bit definition for DBGMCU_IDCODE register *************/
20374 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
20375 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
20376 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
20377 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
20378 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
20379 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
20380
20381 /******************** Bit definition for DBGMCU_CR register *****************/
20382 #define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
20383 #define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
20384 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
20385 #define DBGMCU_CR_DBG_STOPD1_Pos (1U)
20386 #define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
20387 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
20388 #define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
20389 #define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
20390 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
20391 #define DBGMCU_CR_DBG_STOPD3_Pos (7U)
20392 #define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
20393 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
20394 #define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
20395 #define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
20396 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
20397 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
20398 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
20399 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
20400 #define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
20401 #define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
20402 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
20403 #define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
20404 #define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
20405 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
20406 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
20407 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
20408 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
20409
20410 /******************** Bit definition for APB3FZ1 register ************/
20411 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
20412 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
20413 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
20414 /******************** Bit definition for APB1LFZ1 register ************/
20415 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
20416 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
20417 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
20418 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
20419 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
20420 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
20421 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
20422 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
20423 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
20424 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
20425 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
20426 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
20427 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
20428 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
20429 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
20430 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
20431 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
20432 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
20433 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
20434 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
20435 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
20436 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
20437 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
20438 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
20439 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
20440 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
20441 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
20442 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
20443 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
20444 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
20445 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
20446 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
20447 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
20448 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
20449 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
20450 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
20451 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
20452 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
20453 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
20454
20455 /******************** Bit definition for APB1HFZ1 register ************/
20456 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
20457 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
20458 #define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
20459 /******************** Bit definition for APB2FZ1 register ************/
20460 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
20461 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
20462 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
20463 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
20464 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
20465 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
20466 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
20467 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
20468 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
20469 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
20470 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
20471 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
20472 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
20473 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
20474 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
20475 #define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
20476 #define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
20477 #define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
20478
20479 /******************** Bit definition for APB4FZ1 register ************/
20480 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
20481 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
20482 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
20483 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
20484 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
20485 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
20486 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
20487 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
20488 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
20489 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
20490 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
20491 #define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
20492 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
20493 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
20494 #define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
20495 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
20496 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
20497 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
20498 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
20499 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
20500 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
20501 /******************************************************************************/
20502 /* */
20503 /* High Resolution Timer (HRTIM) */
20504 /* */
20505 /******************************************************************************/
20506 /******************** Master Timer control register ***************************/
20507 #define HRTIM_MCR_CK_PSC_Pos (0U)
20508 #define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
20509 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
20510 #define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
20511 #define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
20512 #define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
20513
20514 #define HRTIM_MCR_CONT_Pos (3U)
20515 #define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
20516 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
20517 #define HRTIM_MCR_RETRIG_Pos (4U)
20518 #define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
20519 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
20520 #define HRTIM_MCR_HALF_Pos (5U)
20521 #define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
20522 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
20523
20524 #define HRTIM_MCR_SYNC_IN_Pos (8U)
20525 #define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
20526 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
20527 #define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
20528 #define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
20529 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
20530 #define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
20531 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
20532 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
20533 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
20534 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
20535 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
20536 #define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
20537 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
20538 #define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
20539 #define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
20540 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
20541 #define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
20542 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
20543 #define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
20544 #define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
20545
20546 #define HRTIM_MCR_MCEN_Pos (16U)
20547 #define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
20548 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
20549 #define HRTIM_MCR_TACEN_Pos (17U)
20550 #define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
20551 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
20552 #define HRTIM_MCR_TBCEN_Pos (18U)
20553 #define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
20554 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
20555 #define HRTIM_MCR_TCCEN_Pos (19U)
20556 #define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
20557 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
20558 #define HRTIM_MCR_TDCEN_Pos (20U)
20559 #define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
20560 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
20561 #define HRTIM_MCR_TECEN_Pos (21U)
20562 #define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
20563 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
20564
20565 #define HRTIM_MCR_DACSYNC_Pos (25U)
20566 #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
20567 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
20568 #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
20569 #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
20570
20571 #define HRTIM_MCR_PREEN_Pos (27U)
20572 #define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
20573 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
20574 #define HRTIM_MCR_MREPU_Pos (29U)
20575 #define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
20576 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
20577
20578 #define HRTIM_MCR_BRSTDMA_Pos (30U)
20579 #define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
20580 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
20581 #define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
20582 #define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
20583
20584 /******************** Master Timer Interrupt status register ******************/
20585 #define HRTIM_MISR_MCMP1_Pos (0U)
20586 #define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
20587 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
20588 #define HRTIM_MISR_MCMP2_Pos (1U)
20589 #define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
20590 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
20591 #define HRTIM_MISR_MCMP3_Pos (2U)
20592 #define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
20593 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
20594 #define HRTIM_MISR_MCMP4_Pos (3U)
20595 #define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
20596 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
20597 #define HRTIM_MISR_MREP_Pos (4U)
20598 #define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
20599 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
20600 #define HRTIM_MISR_SYNC_Pos (5U)
20601 #define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
20602 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
20603 #define HRTIM_MISR_MUPD_Pos (6U)
20604 #define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
20605 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
20606
20607 /******************** Master Timer Interrupt clear register *******************/
20608 #define HRTIM_MICR_MCMP1_Pos (0U)
20609 #define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
20610 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
20611 #define HRTIM_MICR_MCMP2_Pos (1U)
20612 #define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
20613 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
20614 #define HRTIM_MICR_MCMP3_Pos (2U)
20615 #define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
20616 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
20617 #define HRTIM_MICR_MCMP4_Pos (3U)
20618 #define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
20619 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
20620 #define HRTIM_MICR_MREP_Pos (4U)
20621 #define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
20622 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
20623 #define HRTIM_MICR_SYNC_Pos (5U)
20624 #define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
20625 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
20626 #define HRTIM_MICR_MUPD_Pos (6U)
20627 #define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
20628 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
20629
20630 /******************** Master Timer DMA/Interrupt enable register **************/
20631 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
20632 #define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
20633 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
20634 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
20635 #define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
20636 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
20637 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
20638 #define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
20639 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
20640 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
20641 #define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
20642 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
20643 #define HRTIM_MDIER_MREPIE_Pos (4U)
20644 #define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
20645 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
20646 #define HRTIM_MDIER_SYNCIE_Pos (5U)
20647 #define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
20648 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
20649 #define HRTIM_MDIER_MUPDIE_Pos (6U)
20650 #define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
20651 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
20652
20653 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
20654 #define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
20655 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
20656 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
20657 #define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
20658 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
20659 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
20660 #define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
20661 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
20662 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
20663 #define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
20664 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
20665 #define HRTIM_MDIER_MREPDE_Pos (20U)
20666 #define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
20667 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
20668 #define HRTIM_MDIER_SYNCDE_Pos (21U)
20669 #define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
20670 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
20671 #define HRTIM_MDIER_MUPDDE_Pos (22U)
20672 #define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
20673 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
20674
20675 /******************* Bit definition for HRTIM_MCNTR register ****************/
20676 #define HRTIM_MCNTR_MCNTR_Pos (0U)
20677 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
20678 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
20679
20680 /******************* Bit definition for HRTIM_MPER register *****************/
20681 #define HRTIM_MPER_MPER_Pos (0U)
20682 #define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
20683 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
20684
20685 /******************* Bit definition for HRTIM_MREP register *****************/
20686 #define HRTIM_MREP_MREP_Pos (0U)
20687 #define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
20688 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
20689
20690 /******************* Bit definition for HRTIM_MCMP1R register *****************/
20691 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
20692 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
20693 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
20694
20695 /******************* Bit definition for HRTIM_MCMP2R register *****************/
20696 #define HRTIM_MCMP1R_MCMP2R_Pos (0U)
20697 #define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
20698 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
20699
20700 /******************* Bit definition for HRTIM_MCMP3R register *****************/
20701 #define HRTIM_MCMP1R_MCMP3R_Pos (0U)
20702 #define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
20703 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
20704
20705 /******************* Bit definition for HRTIM_MCMP4R register *****************/
20706 #define HRTIM_MCMP1R_MCMP4R_Pos (0U)
20707 #define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
20708 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
20709
20710 /******************** Slave control register **********************************/
20711 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
20712 #define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
20713 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
20714 #define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
20715 #define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
20716 #define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
20717
20718 #define HRTIM_TIMCR_CONT_Pos (3U)
20719 #define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
20720 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
20721 #define HRTIM_TIMCR_RETRIG_Pos (4U)
20722 #define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
20723 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
20724 #define HRTIM_TIMCR_HALF_Pos (5U)
20725 #define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
20726 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
20727 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
20728 #define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
20729 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
20730
20731 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
20732 #define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
20733 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
20734 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
20735 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
20736 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
20737
20738 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
20739 #define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
20740 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
20741 #define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
20742 #define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
20743 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
20744 #define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
20745 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
20746 #define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
20747 #define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
20748
20749 #define HRTIM_TIMCR_TREPU_Pos (17U)
20750 #define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
20751 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
20752 #define HRTIM_TIMCR_TRSTU_Pos (18U)
20753 #define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
20754 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
20755 #define HRTIM_TIMCR_TAU_Pos (19U)
20756 #define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
20757 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
20758 #define HRTIM_TIMCR_TBU_Pos (20U)
20759 #define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
20760 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
20761 #define HRTIM_TIMCR_TCU_Pos (21U)
20762 #define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
20763 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
20764 #define HRTIM_TIMCR_TDU_Pos (22U)
20765 #define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
20766 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
20767 #define HRTIM_TIMCR_TEU_Pos (23U)
20768 #define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
20769 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
20770 #define HRTIM_TIMCR_MSTU_Pos (24U)
20771 #define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
20772 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
20773
20774 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
20775 #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
20776 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
20777 #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
20778 #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
20779 #define HRTIM_TIMCR_PREEN_Pos (27U)
20780 #define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
20781 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
20782
20783 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
20784 #define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
20785 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
20786 #define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
20787 #define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
20788 #define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
20789 #define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
20790
20791 /******************** Slave Interrupt status register **************************/
20792 #define HRTIM_TIMISR_CMP1_Pos (0U)
20793 #define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
20794 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
20795 #define HRTIM_TIMISR_CMP2_Pos (1U)
20796 #define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
20797 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
20798 #define HRTIM_TIMISR_CMP3_Pos (2U)
20799 #define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
20800 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
20801 #define HRTIM_TIMISR_CMP4_Pos (3U)
20802 #define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
20803 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
20804 #define HRTIM_TIMISR_REP_Pos (4U)
20805 #define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
20806 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
20807 #define HRTIM_TIMISR_UPD_Pos (6U)
20808 #define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
20809 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
20810 #define HRTIM_TIMISR_CPT1_Pos (7U)
20811 #define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
20812 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
20813 #define HRTIM_TIMISR_CPT2_Pos (8U)
20814 #define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
20815 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
20816 #define HRTIM_TIMISR_SET1_Pos (9U)
20817 #define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
20818 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
20819 #define HRTIM_TIMISR_RST1_Pos (10U)
20820 #define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
20821 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
20822 #define HRTIM_TIMISR_SET2_Pos (11U)
20823 #define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
20824 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
20825 #define HRTIM_TIMISR_RST2_Pos (12U)
20826 #define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
20827 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
20828 #define HRTIM_TIMISR_RST_Pos (13U)
20829 #define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
20830 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
20831 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
20832 #define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
20833 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
20834 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
20835 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
20836 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
20837 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
20838 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
20839 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
20840 #define HRTIM_TIMISR_O1STAT_Pos (18U)
20841 #define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
20842 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
20843 #define HRTIM_TIMISR_O2STAT_Pos (19U)
20844 #define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
20845 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
20846 #define HRTIM_TIMISR_O1CPY_Pos (20U)
20847 #define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
20848 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
20849 #define HRTIM_TIMISR_O2CPY_Pos (21U)
20850 #define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
20851 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
20852
20853 /******************** Slave Interrupt clear register **************************/
20854 #define HRTIM_TIMICR_CMP1C_Pos (0U)
20855 #define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
20856 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
20857 #define HRTIM_TIMICR_CMP2C_Pos (1U)
20858 #define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
20859 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
20860 #define HRTIM_TIMICR_CMP3C_Pos (2U)
20861 #define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
20862 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
20863 #define HRTIM_TIMICR_CMP4C_Pos (3U)
20864 #define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
20865 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
20866 #define HRTIM_TIMICR_REPC_Pos (4U)
20867 #define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
20868 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
20869 #define HRTIM_TIMICR_UPDC_Pos (6U)
20870 #define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
20871 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
20872 #define HRTIM_TIMICR_CPT1C_Pos (7U)
20873 #define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
20874 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
20875 #define HRTIM_TIMICR_CPT2C_Pos (8U)
20876 #define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
20877 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
20878 #define HRTIM_TIMICR_SET1C_Pos (9U)
20879 #define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
20880 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
20881 #define HRTIM_TIMICR_RST1C_Pos (10U)
20882 #define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
20883 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
20884 #define HRTIM_TIMICR_SET2C_Pos (11U)
20885 #define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
20886 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
20887 #define HRTIM_TIMICR_RST2C_Pos (12U)
20888 #define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
20889 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
20890 #define HRTIM_TIMICR_RSTC_Pos (13U)
20891 #define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
20892 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
20893 #define HRTIM_TIMICR_DLYPRTC_Pos (14U)
20894 #define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
20895 #define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
20896
20897 /******************** Slave DMA/Interrupt enable register *********************/
20898 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
20899 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
20900 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
20901 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
20902 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
20903 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
20904 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
20905 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
20906 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
20907 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
20908 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
20909 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
20910 #define HRTIM_TIMDIER_REPIE_Pos (4U)
20911 #define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
20912 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
20913 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
20914 #define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
20915 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
20916 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
20917 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
20918 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
20919 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
20920 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
20921 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
20922 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
20923 #define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
20924 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
20925 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
20926 #define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
20927 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
20928 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
20929 #define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
20930 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
20931 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
20932 #define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
20933 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
20934 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
20935 #define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
20936 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
20937 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
20938 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
20939 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
20940
20941 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
20942 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
20943 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
20944 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
20945 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
20946 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
20947 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
20948 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
20949 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
20950 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
20951 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
20952 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
20953 #define HRTIM_TIMDIER_REPDE_Pos (20U)
20954 #define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
20955 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
20956 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
20957 #define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
20958 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
20959 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
20960 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
20961 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
20962 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
20963 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
20964 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
20965 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
20966 #define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
20967 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
20968 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
20969 #define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
20970 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
20971 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
20972 #define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
20973 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
20974 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
20975 #define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
20976 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
20977 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
20978 #define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
20979 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
20980 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
20981 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
20982 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
20983
20984 /****************** Bit definition for HRTIM_CNTR register ****************/
20985 #define HRTIM_CNTR_CNTR_Pos (0U)
20986 #define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
20987 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
20988
20989 /******************* Bit definition for HRTIM_PER register *****************/
20990 #define HRTIM_PER_PER_Pos (0U)
20991 #define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
20992 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
20993
20994 /******************* Bit definition for HRTIM_REP register *****************/
20995 #define HRTIM_REP_REP_Pos (0U)
20996 #define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
20997 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
20998
20999 /******************* Bit definition for HRTIM_CMP1R register *****************/
21000 #define HRTIM_CMP1R_CMP1R_Pos (0U)
21001 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
21002 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
21003
21004 /******************* Bit definition for HRTIM_CMP1CR register *****************/
21005 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
21006 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
21007 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
21008
21009 /******************* Bit definition for HRTIM_CMP2R register *****************/
21010 #define HRTIM_CMP2R_CMP2R_Pos (0U)
21011 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
21012 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
21013
21014 /******************* Bit definition for HRTIM_CMP3R register *****************/
21015 #define HRTIM_CMP3R_CMP3R_Pos (0U)
21016 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
21017 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
21018
21019 /******************* Bit definition for HRTIM_CMP4R register *****************/
21020 #define HRTIM_CMP4R_CMP4R_Pos (0U)
21021 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
21022 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
21023
21024 /******************* Bit definition for HRTIM_CPT1R register ****************/
21025 #define HRTIM_CPT1R_CPT1R_Pos (0U)
21026 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
21027 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
21028
21029 /******************* Bit definition for HRTIM_CPT2R register ****************/
21030 #define HRTIM_CPT2R_CPT2R_Pos (0U)
21031 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
21032 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
21033
21034 /******************** Bit definition for Slave Deadtime register **************/
21035 #define HRTIM_DTR_DTR_Pos (0U)
21036 #define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
21037 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
21038 #define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
21039 #define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
21040 #define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
21041 #define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
21042 #define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
21043 #define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
21044 #define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
21045 #define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
21046 #define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
21047 #define HRTIM_DTR_SDTR_Pos (9U)
21048 #define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
21049 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
21050 #define HRTIM_DTR_DTPRSC_Pos (10U)
21051 #define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
21052 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
21053 #define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
21054 #define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
21055 #define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
21056 #define HRTIM_DTR_DTRSLK_Pos (14U)
21057 #define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
21058 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
21059 #define HRTIM_DTR_DTRLK_Pos (15U)
21060 #define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
21061 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
21062 #define HRTIM_DTR_DTF_Pos (16U)
21063 #define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
21064 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
21065 #define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
21066 #define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
21067 #define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
21068 #define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
21069 #define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
21070 #define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
21071 #define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
21072 #define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
21073 #define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
21074 #define HRTIM_DTR_SDTF_Pos (25U)
21075 #define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
21076 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
21077 #define HRTIM_DTR_DTFSLK_Pos (30U)
21078 #define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
21079 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
21080 #define HRTIM_DTR_DTFLK_Pos (31U)
21081 #define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
21082 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
21083
21084 /**** Bit definition for Slave Output 1 set register **************************/
21085 #define HRTIM_SET1R_SST_Pos (0U)
21086 #define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
21087 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
21088 #define HRTIM_SET1R_RESYNC_Pos (1U)
21089 #define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
21090 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
21091 #define HRTIM_SET1R_PER_Pos (2U)
21092 #define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
21093 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
21094 #define HRTIM_SET1R_CMP1_Pos (3U)
21095 #define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
21096 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
21097 #define HRTIM_SET1R_CMP2_Pos (4U)
21098 #define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
21099 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
21100 #define HRTIM_SET1R_CMP3_Pos (5U)
21101 #define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
21102 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
21103 #define HRTIM_SET1R_CMP4_Pos (6U)
21104 #define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
21105 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
21106
21107 #define HRTIM_SET1R_MSTPER_Pos (7U)
21108 #define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
21109 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
21110 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
21111 #define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
21112 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
21113 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
21114 #define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
21115 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
21116 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
21117 #define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
21118 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
21119 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
21120 #define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
21121 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
21122
21123 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
21124 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
21125 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
21126 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
21127 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
21128 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
21129 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
21130 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
21131 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
21132 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
21133 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
21134 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
21135 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
21136 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
21137 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
21138 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
21139 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
21140 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
21141 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
21142 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
21143 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
21144 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
21145 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
21146 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
21147 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
21148 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
21149 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
21150
21151 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
21152 #define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
21153 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
21154 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
21155 #define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
21156 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
21157 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
21158 #define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
21159 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
21160 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
21161 #define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
21162 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
21163 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
21164 #define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
21165 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
21166 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
21167 #define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
21168 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
21169 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
21170 #define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
21171 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
21172 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
21173 #define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
21174 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
21175 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
21176 #define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
21177 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
21178 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
21179 #define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
21180 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
21181
21182 #define HRTIM_SET1R_UPDATE_Pos (31U)
21183 #define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
21184 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21185
21186 /**** Bit definition for Slave Output 1 reset register ************************/
21187 #define HRTIM_RST1R_SRT_Pos (0U)
21188 #define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
21189 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
21190 #define HRTIM_RST1R_RESYNC_Pos (1U)
21191 #define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
21192 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
21193 #define HRTIM_RST1R_PER_Pos (2U)
21194 #define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
21195 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
21196 #define HRTIM_RST1R_CMP1_Pos (3U)
21197 #define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
21198 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
21199 #define HRTIM_RST1R_CMP2_Pos (4U)
21200 #define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
21201 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
21202 #define HRTIM_RST1R_CMP3_Pos (5U)
21203 #define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
21204 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
21205 #define HRTIM_RST1R_CMP4_Pos (6U)
21206 #define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
21207 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
21208
21209 #define HRTIM_RST1R_MSTPER_Pos (7U)
21210 #define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
21211 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
21212 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
21213 #define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
21214 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
21215 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
21216 #define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
21217 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
21218 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
21219 #define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
21220 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
21221 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
21222 #define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
21223 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
21224
21225 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
21226 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
21227 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
21228 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
21229 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
21230 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
21231 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
21232 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
21233 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
21234 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
21235 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
21236 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
21237 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
21238 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
21239 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
21240 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
21241 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
21242 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
21243 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
21244 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
21245 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
21246 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
21247 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
21248 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
21249 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
21250 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
21251 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
21252
21253 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
21254 #define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
21255 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
21256 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
21257 #define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
21258 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
21259 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
21260 #define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
21261 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
21262 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
21263 #define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
21264 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
21265 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
21266 #define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
21267 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
21268 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
21269 #define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
21270 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
21271 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
21272 #define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
21273 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
21274 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
21275 #define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
21276 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
21277 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
21278 #define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
21279 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
21280 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
21281 #define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
21282 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
21283
21284 #define HRTIM_RST1R_UPDATE_Pos (31U)
21285 #define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
21286 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21287
21288
21289 /**** Bit definition for Slave Output 2 set register **************************/
21290 #define HRTIM_SET2R_SST_Pos (0U)
21291 #define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
21292 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
21293 #define HRTIM_SET2R_RESYNC_Pos (1U)
21294 #define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
21295 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
21296 #define HRTIM_SET2R_PER_Pos (2U)
21297 #define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
21298 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
21299 #define HRTIM_SET2R_CMP1_Pos (3U)
21300 #define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
21301 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
21302 #define HRTIM_SET2R_CMP2_Pos (4U)
21303 #define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
21304 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
21305 #define HRTIM_SET2R_CMP3_Pos (5U)
21306 #define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
21307 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
21308 #define HRTIM_SET2R_CMP4_Pos (6U)
21309 #define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
21310 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
21311
21312 #define HRTIM_SET2R_MSTPER_Pos (7U)
21313 #define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
21314 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
21315 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
21316 #define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
21317 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
21318 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
21319 #define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
21320 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
21321 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
21322 #define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
21323 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
21324 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
21325 #define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
21326 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
21327
21328 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
21329 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
21330 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
21331 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
21332 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
21333 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
21334 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
21335 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
21336 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
21337 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
21338 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
21339 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
21340 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
21341 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
21342 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
21343 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
21344 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
21345 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
21346 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
21347 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
21348 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
21349 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
21350 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
21351 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
21352 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
21353 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
21354 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
21355
21356 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
21357 #define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
21358 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
21359 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
21360 #define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
21361 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
21362 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
21363 #define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
21364 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
21365 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
21366 #define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
21367 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
21368 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
21369 #define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
21370 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
21371 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
21372 #define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
21373 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
21374 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
21375 #define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
21376 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
21377 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
21378 #define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
21379 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
21380 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
21381 #define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
21382 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
21383 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
21384 #define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
21385 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
21386
21387 #define HRTIM_SET2R_UPDATE_Pos (31U)
21388 #define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
21389 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21390
21391 /**** Bit definition for Slave Output 2 reset register ************************/
21392 #define HRTIM_RST2R_SRT_Pos (0U)
21393 #define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
21394 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
21395 #define HRTIM_RST2R_RESYNC_Pos (1U)
21396 #define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
21397 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
21398 #define HRTIM_RST2R_PER_Pos (2U)
21399 #define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
21400 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
21401 #define HRTIM_RST2R_CMP1_Pos (3U)
21402 #define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
21403 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
21404 #define HRTIM_RST2R_CMP2_Pos (4U)
21405 #define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
21406 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
21407 #define HRTIM_RST2R_CMP3_Pos (5U)
21408 #define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
21409 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
21410 #define HRTIM_RST2R_CMP4_Pos (6U)
21411 #define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
21412 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
21413
21414 #define HRTIM_RST2R_MSTPER_Pos (7U)
21415 #define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
21416 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
21417 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
21418 #define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
21419 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
21420 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
21421 #define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
21422 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
21423 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
21424 #define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
21425 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
21426 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
21427 #define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
21428 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
21429
21430 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
21431 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
21432 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
21433 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
21434 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
21435 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
21436 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
21437 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
21438 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
21439 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
21440 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
21441 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
21442 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
21443 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
21444 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
21445 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
21446 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
21447 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
21448 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
21449 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
21450 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
21451 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
21452 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
21453 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
21454 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
21455 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
21456 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
21457
21458 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
21459 #define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
21460 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
21461 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
21462 #define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
21463 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
21464 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
21465 #define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
21466 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
21467 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
21468 #define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
21469 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
21470 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
21471 #define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
21472 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
21473 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
21474 #define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
21475 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
21476 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
21477 #define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
21478 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
21479 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
21480 #define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
21481 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
21482 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
21483 #define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
21484 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
21485 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
21486 #define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
21487 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
21488
21489 #define HRTIM_RST2R_UPDATE_Pos (31U)
21490 #define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
21491 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
21492
21493 /**** Bit definition for Slave external event filtering register 1 ***********/
21494 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
21495 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
21496 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
21497 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
21498 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
21499 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
21500 #define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
21501 #define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
21502 #define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
21503 #define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
21504
21505 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
21506 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
21507 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
21508 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
21509 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
21510 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
21511 #define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
21512 #define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
21513 #define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
21514 #define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
21515
21516 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
21517 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
21518 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
21519 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
21520 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
21521 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
21522 #define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
21523 #define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
21524 #define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
21525 #define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
21526
21527 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
21528 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
21529 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
21530 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
21531 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
21532 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
21533 #define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
21534 #define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
21535 #define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
21536 #define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
21537
21538 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
21539 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
21540 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
21541 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
21542 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
21543 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
21544 #define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
21545 #define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
21546 #define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
21547 #define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
21548
21549 /**** Bit definition for Slave external event filtering register 2 ***********/
21550 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
21551 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
21552 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
21553 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
21554 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
21555 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
21556 #define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
21557 #define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
21558 #define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
21559 #define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
21560
21561 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
21562 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
21563 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
21564 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
21565 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
21566 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
21567 #define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
21568 #define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
21569 #define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
21570 #define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
21571
21572 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
21573 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
21574 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
21575 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
21576 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
21577 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
21578 #define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
21579 #define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
21580 #define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
21581 #define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
21582
21583 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
21584 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
21585 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
21586 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
21587 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
21588 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
21589 #define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
21590 #define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
21591 #define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
21592 #define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
21593
21594 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
21595 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
21596 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
21597 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
21598 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
21599 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
21600 #define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
21601 #define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
21602 #define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
21603 #define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
21604
21605 /**** Bit definition for Slave Timer reset register ***************************/
21606 #define HRTIM_RSTR_UPDATE_Pos (1U)
21607 #define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
21608 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
21609 #define HRTIM_RSTR_CMP2_Pos (2U)
21610 #define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
21611 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
21612 #define HRTIM_RSTR_CMP4_Pos (3U)
21613 #define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
21614 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
21615
21616 #define HRTIM_RSTR_MSTPER_Pos (4U)
21617 #define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
21618 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
21619 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
21620 #define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
21621 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
21622 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
21623 #define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
21624 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
21625 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
21626 #define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
21627 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
21628 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
21629 #define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
21630 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
21631
21632 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
21633 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
21634 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
21635 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
21636 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
21637 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
21638 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
21639 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
21640 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
21641 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
21642 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
21643 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
21644 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
21645 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
21646 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
21647 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
21648 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
21649 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
21650 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
21651 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
21652 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
21653 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
21654 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
21655 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
21656 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
21657 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
21658 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
21659 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
21660 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
21661 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
21662
21663 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
21664 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
21665 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
21666 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
21667 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
21668 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
21669 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
21670 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
21671 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
21672
21673 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
21674 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
21675 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
21676 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
21677 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
21678 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
21679 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
21680 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
21681 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
21682
21683 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
21684 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
21685 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
21686 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
21687 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
21688 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
21689 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
21690 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
21691 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
21692
21693 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
21694 #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
21695 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
21696 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
21697 #define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
21698 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
21699 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
21700 #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
21701 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
21702
21703 /**** Bit definition for Slave Timer Chopper register *************************/
21704 #define HRTIM_CHPR_CARFRQ_Pos (0U)
21705 #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
21706 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
21707 #define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
21708 #define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
21709 #define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
21710 #define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
21711
21712 #define HRTIM_CHPR_CARDTY_Pos (4U)
21713 #define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
21714 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
21715 #define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
21716 #define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
21717 #define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
21718
21719 #define HRTIM_CHPR_STRPW_Pos (7U)
21720 #define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
21721 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
21722 #define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
21723 #define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
21724 #define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
21725 #define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
21726
21727 /**** Bit definition for Slave Timer Capture 1 control register ***************/
21728 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
21729 #define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
21730 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
21731 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
21732 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
21733 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
21734 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
21735 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
21736 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
21737 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
21738 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
21739 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
21740 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
21741 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
21742 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
21743 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
21744 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
21745 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
21746 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
21747 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
21748 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
21749 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
21750 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
21751 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
21752 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
21753 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
21754 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
21755 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
21756 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
21757 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
21758 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
21759 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
21760 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
21761 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
21762 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
21763 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
21764
21765 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
21766 #define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
21767 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
21768 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
21769 #define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
21770 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
21771 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
21772 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
21773 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
21774 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
21775 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
21776 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
21777
21778 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
21779 #define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
21780 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
21781 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
21782 #define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
21783 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
21784 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
21785 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
21786 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
21787 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
21788 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
21789 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
21790
21791 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
21792 #define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
21793 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
21794 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
21795 #define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
21796 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
21797 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
21798 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
21799 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
21800 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
21801 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
21802 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
21803
21804 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
21805 #define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
21806 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
21807 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
21808 #define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
21809 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
21810 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
21811 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
21812 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
21813 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
21814 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
21815 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
21816
21817 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
21818 #define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
21819 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
21820 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
21821 #define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
21822 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
21823 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
21824 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
21825 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
21826 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
21827 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
21828 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
21829
21830 /**** Bit definition for Slave Timer Capture 2 control register ***************/
21831 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
21832 #define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
21833 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
21834 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
21835 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
21836 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
21837 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
21838 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
21839 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
21840 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
21841 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
21842 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
21843 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
21844 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
21845 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
21846 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
21847 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
21848 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
21849 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
21850 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
21851 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
21852 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
21853 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
21854 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
21855 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
21856 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
21857 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
21858 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
21859 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
21860 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
21861 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
21862 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
21863 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
21864 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
21865 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
21866 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
21867
21868 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
21869 #define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
21870 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
21871 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
21872 #define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
21873 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
21874 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
21875 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
21876 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
21877 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
21878 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
21879 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
21880
21881 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
21882 #define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
21883 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
21884 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
21885 #define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
21886 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
21887 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
21888 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
21889 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
21890 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
21891 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
21892 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
21893
21894 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
21895 #define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
21896 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
21897 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
21898 #define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
21899 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
21900 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
21901 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
21902 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
21903 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
21904 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
21905 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
21906
21907 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
21908 #define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
21909 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
21910 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
21911 #define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
21912 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
21913 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
21914 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
21915 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
21916 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
21917 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
21918 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
21919
21920 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
21921 #define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
21922 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
21923 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
21924 #define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
21925 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
21926 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
21927 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
21928 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
21929 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
21930 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
21931 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
21932
21933 /**** Bit definition for Slave Timer Output register **************************/
21934 #define HRTIM_OUTR_POL1_Pos (1U)
21935 #define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
21936 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
21937 #define HRTIM_OUTR_IDLM1_Pos (2U)
21938 #define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
21939 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
21940 #define HRTIM_OUTR_IDLES1_Pos (3U)
21941 #define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
21942 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
21943 #define HRTIM_OUTR_FAULT1_Pos (4U)
21944 #define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
21945 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
21946 #define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
21947 #define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
21948 #define HRTIM_OUTR_CHP1_Pos (6U)
21949 #define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
21950 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
21951 #define HRTIM_OUTR_DIDL1_Pos (7U)
21952 #define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
21953 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
21954
21955 #define HRTIM_OUTR_DTEN_Pos (8U)
21956 #define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
21957 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
21958 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
21959 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
21960 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
21961 #define HRTIM_OUTR_DLYPRT_Pos (10U)
21962 #define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
21963 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
21964 #define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
21965 #define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
21966 #define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
21967
21968 #define HRTIM_OUTR_POL2_Pos (17U)
21969 #define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
21970 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
21971 #define HRTIM_OUTR_IDLM2_Pos (18U)
21972 #define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
21973 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
21974 #define HRTIM_OUTR_IDLES2_Pos (19U)
21975 #define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
21976 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
21977 #define HRTIM_OUTR_FAULT2_Pos (20U)
21978 #define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
21979 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
21980 #define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
21981 #define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
21982 #define HRTIM_OUTR_CHP2_Pos (22U)
21983 #define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
21984 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
21985 #define HRTIM_OUTR_DIDL2_Pos (23U)
21986 #define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
21987 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
21988
21989 /**** Bit definition for Slave Timer Fault register ***************************/
21990 #define HRTIM_FLTR_FLT1EN_Pos (0U)
21991 #define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
21992 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
21993 #define HRTIM_FLTR_FLT2EN_Pos (1U)
21994 #define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
21995 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
21996 #define HRTIM_FLTR_FLT3EN_Pos (2U)
21997 #define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
21998 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
21999 #define HRTIM_FLTR_FLT4EN_Pos (3U)
22000 #define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
22001 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
22002 #define HRTIM_FLTR_FLT5EN_Pos (4U)
22003 #define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
22004 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
22005 #define HRTIM_FLTR_FLTLCK_Pos (31U)
22006 #define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
22007 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
22008
22009 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
22010 #define HRTIM_CR1_MUDIS_Pos (0U)
22011 #define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
22012 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
22013 #define HRTIM_CR1_TAUDIS_Pos (1U)
22014 #define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
22015 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
22016 #define HRTIM_CR1_TBUDIS_Pos (2U)
22017 #define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
22018 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
22019 #define HRTIM_CR1_TCUDIS_Pos (3U)
22020 #define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
22021 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
22022 #define HRTIM_CR1_TDUDIS_Pos (4U)
22023 #define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
22024 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
22025 #define HRTIM_CR1_TEUDIS_Pos (5U)
22026 #define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
22027 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
22028 #define HRTIM_CR1_ADC1USRC_Pos (16U)
22029 #define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
22030 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
22031 #define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
22032 #define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
22033 #define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
22034 #define HRTIM_CR1_ADC2USRC_Pos (19U)
22035 #define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
22036 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
22037 #define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
22038 #define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
22039 #define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
22040 #define HRTIM_CR1_ADC3USRC_Pos (22U)
22041 #define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
22042 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
22043 #define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
22044 #define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
22045 #define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
22046 #define HRTIM_CR1_ADC4USRC_Pos (25U)
22047 #define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
22048 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
22049 #define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
22050 #define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
22051 #define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
22052
22053 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
22054 #define HRTIM_CR2_MSWU_Pos (0U)
22055 #define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
22056 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
22057 #define HRTIM_CR2_TASWU_Pos (1U)
22058 #define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
22059 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
22060 #define HRTIM_CR2_TBSWU_Pos (2U)
22061 #define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
22062 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
22063 #define HRTIM_CR2_TCSWU_Pos (3U)
22064 #define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
22065 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
22066 #define HRTIM_CR2_TDSWU_Pos (4U)
22067 #define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
22068 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
22069 #define HRTIM_CR2_TESWU_Pos (5U)
22070 #define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
22071 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
22072 #define HRTIM_CR2_MRST_Pos (8U)
22073 #define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
22074 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
22075 #define HRTIM_CR2_TARST_Pos (9U)
22076 #define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
22077 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
22078 #define HRTIM_CR2_TBRST_Pos (10U)
22079 #define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
22080 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
22081 #define HRTIM_CR2_TCRST_Pos (11U)
22082 #define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
22083 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
22084 #define HRTIM_CR2_TDRST_Pos (12U)
22085 #define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
22086 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
22087 #define HRTIM_CR2_TERST_Pos (13U)
22088 #define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
22089 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
22090
22091 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
22092 #define HRTIM_ISR_FLT1_Pos (0U)
22093 #define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
22094 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
22095 #define HRTIM_ISR_FLT2_Pos (1U)
22096 #define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
22097 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
22098 #define HRTIM_ISR_FLT3_Pos (2U)
22099 #define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
22100 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
22101 #define HRTIM_ISR_FLT4_Pos (3U)
22102 #define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
22103 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
22104 #define HRTIM_ISR_FLT5_Pos (4U)
22105 #define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
22106 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
22107 #define HRTIM_ISR_SYSFLT_Pos (5U)
22108 #define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
22109 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
22110 #define HRTIM_ISR_BMPER_Pos (17U)
22111 #define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
22112 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
22113
22114 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
22115 #define HRTIM_ICR_FLT1C_Pos (0U)
22116 #define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
22117 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
22118 #define HRTIM_ICR_FLT2C_Pos (1U)
22119 #define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
22120 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
22121 #define HRTIM_ICR_FLT3C_Pos (2U)
22122 #define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
22123 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
22124 #define HRTIM_ICR_FLT4C_Pos (3U)
22125 #define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
22126 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
22127 #define HRTIM_ICR_FLT5C_Pos (4U)
22128 #define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
22129 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
22130 #define HRTIM_ICR_SYSFLTC_Pos (5U)
22131 #define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
22132 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
22133 #define HRTIM_ICR_BMPERC_Pos (17U)
22134 #define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
22135 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
22136
22137 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
22138 #define HRTIM_IER_FLT1_Pos (0U)
22139 #define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
22140 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
22141 #define HRTIM_IER_FLT2_Pos (1U)
22142 #define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
22143 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
22144 #define HRTIM_IER_FLT3_Pos (2U)
22145 #define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
22146 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
22147 #define HRTIM_IER_FLT4_Pos (3U)
22148 #define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
22149 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
22150 #define HRTIM_IER_FLT5_Pos (4U)
22151 #define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
22152 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
22153 #define HRTIM_IER_SYSFLT_Pos (5U)
22154 #define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
22155 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
22156 #define HRTIM_IER_BMPER_Pos (17U)
22157 #define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
22158 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
22159
22160 /**** Bit definition for Common HRTIM Timer output enable register ************/
22161 #define HRTIM_OENR_TA1OEN_Pos (0U)
22162 #define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
22163 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
22164 #define HRTIM_OENR_TA2OEN_Pos (1U)
22165 #define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
22166 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
22167 #define HRTIM_OENR_TB1OEN_Pos (2U)
22168 #define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
22169 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
22170 #define HRTIM_OENR_TB2OEN_Pos (3U)
22171 #define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
22172 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
22173 #define HRTIM_OENR_TC1OEN_Pos (4U)
22174 #define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
22175 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
22176 #define HRTIM_OENR_TC2OEN_Pos (5U)
22177 #define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
22178 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
22179 #define HRTIM_OENR_TD1OEN_Pos (6U)
22180 #define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
22181 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
22182 #define HRTIM_OENR_TD2OEN_Pos (7U)
22183 #define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
22184 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
22185 #define HRTIM_OENR_TE1OEN_Pos (8U)
22186 #define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
22187 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
22188 #define HRTIM_OENR_TE2OEN_Pos (9U)
22189 #define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
22190 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
22191
22192 /**** Bit definition for Common HRTIM Timer output disable register ***********/
22193 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
22194 #define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
22195 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
22196 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
22197 #define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
22198 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
22199 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
22200 #define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
22201 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
22202 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
22203 #define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
22204 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
22205 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
22206 #define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
22207 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
22208 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
22209 #define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
22210 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
22211 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
22212 #define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
22213 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
22214 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
22215 #define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
22216 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
22217 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
22218 #define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
22219 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
22220 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
22221 #define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
22222 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
22223
22224 /**** Bit definition for Common HRTIM Timer output disable status register *****/
22225 #define HRTIM_ODSR_TA1ODS_Pos (0U)
22226 #define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
22227 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
22228 #define HRTIM_ODSR_TA2ODS_Pos (1U)
22229 #define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
22230 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
22231 #define HRTIM_ODSR_TB1ODS_Pos (2U)
22232 #define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
22233 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
22234 #define HRTIM_ODSR_TB2ODS_Pos (3U)
22235 #define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
22236 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
22237 #define HRTIM_ODSR_TC1ODS_Pos (4U)
22238 #define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
22239 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
22240 #define HRTIM_ODSR_TC2ODS_Pos (5U)
22241 #define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
22242 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
22243 #define HRTIM_ODSR_TD1ODS_Pos (6U)
22244 #define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
22245 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
22246 #define HRTIM_ODSR_TD2ODS_Pos (7U)
22247 #define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
22248 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
22249 #define HRTIM_ODSR_TE1ODS_Pos (8U)
22250 #define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
22251 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
22252 #define HRTIM_ODSR_TE2ODS_Pos (9U)
22253 #define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
22254 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
22255
22256 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
22257 #define HRTIM_BMCR_BME_Pos (0U)
22258 #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
22259 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
22260 #define HRTIM_BMCR_BMOM_Pos (1U)
22261 #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
22262 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
22263 #define HRTIM_BMCR_BMCLK_Pos (2U)
22264 #define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
22265 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
22266 #define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
22267 #define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
22268 #define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
22269 #define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
22270 #define HRTIM_BMCR_BMPRSC_Pos (6U)
22271 #define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
22272 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
22273 #define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
22274 #define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
22275 #define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
22276 #define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
22277 #define HRTIM_BMCR_BMPREN_Pos (10U)
22278 #define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
22279 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
22280 #define HRTIM_BMCR_MTBM_Pos (16U)
22281 #define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
22282 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
22283 #define HRTIM_BMCR_TABM_Pos (17U)
22284 #define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
22285 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
22286 #define HRTIM_BMCR_TBBM_Pos (18U)
22287 #define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
22288 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
22289 #define HRTIM_BMCR_TCBM_Pos (19U)
22290 #define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
22291 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
22292 #define HRTIM_BMCR_TDBM_Pos (20U)
22293 #define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
22294 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
22295 #define HRTIM_BMCR_TEBM_Pos (21U)
22296 #define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
22297 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
22298 #define HRTIM_BMCR_BMSTAT_Pos (31U)
22299 #define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
22300 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
22301
22302 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
22303 #define HRTIM_BMTRGR_SW_Pos (0U)
22304 #define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
22305 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
22306 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
22307 #define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
22308 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
22309 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
22310 #define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
22311 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
22312 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
22313 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
22314 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
22315 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
22316 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
22317 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
22318 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
22319 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
22320 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
22321 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
22322 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
22323 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
22324 #define HRTIM_BMTRGR_TARST_Pos (7U)
22325 #define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
22326 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
22327 #define HRTIM_BMTRGR_TAREP_Pos (8U)
22328 #define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
22329 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
22330 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
22331 #define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
22332 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
22333 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
22334 #define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
22335 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
22336 #define HRTIM_BMTRGR_TBRST_Pos (11U)
22337 #define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
22338 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
22339 #define HRTIM_BMTRGR_TBREP_Pos (12U)
22340 #define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
22341 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
22342 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
22343 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
22344 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
22345 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
22346 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
22347 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
22348 #define HRTIM_BMTRGR_TCRST_Pos (15U)
22349 #define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
22350 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
22351 #define HRTIM_BMTRGR_TCREP_Pos (16U)
22352 #define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
22353 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
22354 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
22355 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
22356 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
22357 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
22358 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
22359 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
22360 #define HRTIM_BMTRGR_TDRST_Pos (19U)
22361 #define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
22362 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
22363 #define HRTIM_BMTRGR_TDREP_Pos (20U)
22364 #define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
22365 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
22366 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
22367 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
22368 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
22369 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
22370 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
22371 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
22372 #define HRTIM_BMTRGR_TERST_Pos (23U)
22373 #define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
22374 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
22375 #define HRTIM_BMTRGR_TEREP_Pos (24U)
22376 #define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
22377 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
22378 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
22379 #define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
22380 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
22381 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
22382 #define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
22383 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
22384 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
22385 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
22386 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
22387 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
22388 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
22389 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
22390 #define HRTIM_BMTRGR_EEV7_Pos (29U)
22391 #define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
22392 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
22393 #define HRTIM_BMTRGR_EEV8_Pos (30U)
22394 #define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
22395 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
22396 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
22397 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
22398 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
22399
22400 /******************* Bit definition for HRTIM_BMCMPR register ***************/
22401 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
22402 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
22403 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
22404
22405 /******************* Bit definition for HRTIM_BMPER register ****************/
22406 #define HRTIM_BMPER_BMPER_Pos (0U)
22407 #define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
22408 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
22409
22410 /******************* Bit definition for HRTIM_EECR1 register ****************/
22411 #define HRTIM_EECR1_EE1SRC_Pos (0U)
22412 #define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
22413 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
22414 #define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
22415 #define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
22416 #define HRTIM_EECR1_EE1POL_Pos (2U)
22417 #define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
22418 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
22419 #define HRTIM_EECR1_EE1SNS_Pos (3U)
22420 #define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
22421 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
22422 #define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
22423 #define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
22424 #define HRTIM_EECR1_EE1FAST_Pos (5U)
22425 #define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
22426 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
22427
22428 #define HRTIM_EECR1_EE2SRC_Pos (6U)
22429 #define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
22430 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
22431 #define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
22432 #define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
22433 #define HRTIM_EECR1_EE2POL_Pos (8U)
22434 #define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
22435 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
22436 #define HRTIM_EECR1_EE2SNS_Pos (9U)
22437 #define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
22438 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
22439 #define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
22440 #define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
22441 #define HRTIM_EECR1_EE2FAST_Pos (11U)
22442 #define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
22443 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
22444
22445 #define HRTIM_EECR1_EE3SRC_Pos (12U)
22446 #define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
22447 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
22448 #define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
22449 #define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
22450 #define HRTIM_EECR1_EE3POL_Pos (14U)
22451 #define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
22452 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
22453 #define HRTIM_EECR1_EE3SNS_Pos (15U)
22454 #define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
22455 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
22456 #define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
22457 #define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
22458 #define HRTIM_EECR1_EE3FAST_Pos (17U)
22459 #define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
22460 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
22461
22462 #define HRTIM_EECR1_EE4SRC_Pos (18U)
22463 #define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
22464 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
22465 #define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
22466 #define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
22467 #define HRTIM_EECR1_EE4POL_Pos (20U)
22468 #define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
22469 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
22470 #define HRTIM_EECR1_EE4SNS_Pos (21U)
22471 #define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
22472 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
22473 #define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
22474 #define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
22475 #define HRTIM_EECR1_EE4FAST_Pos (23U)
22476 #define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
22477 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
22478
22479 #define HRTIM_EECR1_EE5SRC_Pos (24U)
22480 #define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
22481 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
22482 #define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
22483 #define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
22484 #define HRTIM_EECR1_EE5POL_Pos (26U)
22485 #define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
22486 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
22487 #define HRTIM_EECR1_EE5SNS_Pos (27U)
22488 #define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
22489 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
22490 #define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
22491 #define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
22492 #define HRTIM_EECR1_EE5FAST_Pos (29U)
22493 #define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
22494 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
22495
22496 /******************* Bit definition for HRTIM_EECR2 register ****************/
22497 #define HRTIM_EECR2_EE6SRC_Pos (0U)
22498 #define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
22499 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
22500 #define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
22501 #define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
22502 #define HRTIM_EECR2_EE6POL_Pos (2U)
22503 #define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
22504 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
22505 #define HRTIM_EECR2_EE6SNS_Pos (3U)
22506 #define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
22507 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
22508 #define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
22509 #define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
22510
22511 #define HRTIM_EECR2_EE7SRC_Pos (6U)
22512 #define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
22513 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
22514 #define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
22515 #define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
22516 #define HRTIM_EECR2_EE7POL_Pos (8U)
22517 #define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
22518 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
22519 #define HRTIM_EECR2_EE7SNS_Pos (9U)
22520 #define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
22521 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
22522 #define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
22523 #define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
22524
22525 #define HRTIM_EECR2_EE8SRC_Pos (12U)
22526 #define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
22527 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
22528 #define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
22529 #define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
22530 #define HRTIM_EECR2_EE8POL_Pos (14U)
22531 #define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
22532 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
22533 #define HRTIM_EECR2_EE8SNS_Pos (15U)
22534 #define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
22535 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
22536 #define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
22537 #define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
22538
22539 #define HRTIM_EECR2_EE9SRC_Pos (18U)
22540 #define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
22541 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
22542 #define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
22543 #define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
22544 #define HRTIM_EECR2_EE9POL_Pos (20U)
22545 #define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
22546 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
22547 #define HRTIM_EECR2_EE9SNS_Pos (21U)
22548 #define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
22549 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
22550 #define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
22551 #define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
22552
22553 #define HRTIM_EECR2_EE10SRC_Pos (24U)
22554 #define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
22555 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
22556 #define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
22557 #define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
22558 #define HRTIM_EECR2_EE10POL_Pos (26U)
22559 #define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
22560 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
22561 #define HRTIM_EECR2_EE10SNS_Pos (27U)
22562 #define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
22563 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
22564 #define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
22565 #define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
22566
22567 /******************* Bit definition for HRTIM_EECR3 register ****************/
22568 #define HRTIM_EECR3_EE6F_Pos (0U)
22569 #define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
22570 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
22571 #define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
22572 #define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
22573 #define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
22574 #define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
22575 #define HRTIM_EECR3_EE7F_Pos (6U)
22576 #define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
22577 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
22578 #define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
22579 #define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
22580 #define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
22581 #define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
22582 #define HRTIM_EECR3_EE8F_Pos (12U)
22583 #define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
22584 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
22585 #define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
22586 #define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
22587 #define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
22588 #define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
22589 #define HRTIM_EECR3_EE9F_Pos (18U)
22590 #define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
22591 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
22592 #define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
22593 #define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
22594 #define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
22595 #define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
22596 #define HRTIM_EECR3_EE10F_Pos (24U)
22597 #define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
22598 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
22599 #define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
22600 #define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
22601 #define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
22602 #define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
22603 #define HRTIM_EECR3_EEVSD_Pos (30U)
22604 #define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
22605 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
22606 #define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
22607 #define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
22608
22609 /******************* Bit definition for HRTIM_ADC1R register ****************/
22610 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
22611 #define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
22612 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
22613 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
22614 #define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
22615 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
22616 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
22617 #define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
22618 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
22619 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
22620 #define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
22621 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
22622 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
22623 #define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
22624 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
22625 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
22626 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
22627 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
22628 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
22629 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
22630 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
22631 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
22632 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
22633 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
22634 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
22635 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
22636 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
22637 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
22638 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
22639 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
22640 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
22641 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
22642 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
22643 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
22644 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
22645 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
22646 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
22647 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
22648 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
22649 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
22650 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
22651 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
22652 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
22653 #define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
22654 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
22655 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
22656 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
22657 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
22658 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
22659 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
22660 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
22661 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
22662 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
22663 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
22664 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
22665 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
22666 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
22667 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
22668 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
22669 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
22670 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
22671 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
22672 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
22673 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
22674 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
22675 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
22676 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
22677 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
22678 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
22679 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
22680 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
22681 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
22682 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
22683 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
22684 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
22685 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
22686 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
22687 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
22688 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
22689 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
22690 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
22691 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
22692 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
22693 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
22694 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
22695 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
22696 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
22697 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
22698 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
22699 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
22700 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
22701 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
22702 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
22703 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
22704 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
22705 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
22706
22707 /******************* Bit definition for HRTIM_ADC2R register ****************/
22708 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
22709 #define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
22710 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
22711 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
22712 #define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
22713 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
22714 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
22715 #define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
22716 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
22717 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
22718 #define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
22719 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
22720 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
22721 #define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
22722 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
22723 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
22724 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
22725 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
22726 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
22727 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
22728 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
22729 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
22730 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
22731 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
22732 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
22733 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
22734 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
22735 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
22736 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
22737 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
22738 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
22739 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
22740 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
22741 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
22742 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
22743 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
22744 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
22745 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
22746 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
22747 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
22748 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
22749 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
22750 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
22751 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
22752 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
22753 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
22754 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
22755 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
22756 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
22757 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
22758 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
22759 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
22760 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
22761 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
22762 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
22763 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
22764 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
22765 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
22766 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
22767 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
22768 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
22769 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
22770 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
22771 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
22772 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
22773 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
22774 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
22775 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
22776 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
22777 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
22778 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
22779 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
22780 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
22781 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
22782 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
22783 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
22784 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
22785 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
22786 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
22787 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
22788 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
22789 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
22790 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
22791 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
22792 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
22793 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
22794 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
22795 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
22796 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
22797 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
22798 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
22799 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
22800 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
22801 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
22802 #define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
22803 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
22804
22805 /******************* Bit definition for HRTIM_ADC3R register ****************/
22806 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
22807 #define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
22808 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
22809 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
22810 #define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
22811 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
22812 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
22813 #define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
22814 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
22815 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
22816 #define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
22817 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
22818 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
22819 #define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
22820 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
22821 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
22822 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
22823 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
22824 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
22825 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
22826 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
22827 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
22828 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
22829 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
22830 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
22831 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
22832 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
22833 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
22834 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
22835 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
22836 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
22837 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
22838 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
22839 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
22840 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
22841 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
22842 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
22843 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
22844 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
22845 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
22846 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
22847 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
22848 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
22849 #define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
22850 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
22851 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
22852 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
22853 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
22854 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
22855 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
22856 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
22857 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
22858 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
22859 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
22860 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
22861 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
22862 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
22863 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
22864 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
22865 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
22866 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
22867 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
22868 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
22869 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
22870 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
22871 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
22872 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
22873 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
22874 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
22875 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
22876 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
22877 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
22878 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
22879 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
22880 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
22881 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
22882 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
22883 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
22884 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
22885 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
22886 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
22887 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
22888 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
22889 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
22890 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
22891 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
22892 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
22893 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
22894 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
22895 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
22896 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
22897 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
22898 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
22899 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
22900 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
22901 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
22902
22903 /******************* Bit definition for HRTIM_ADC4R register ****************/
22904 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
22905 #define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
22906 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
22907 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
22908 #define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
22909 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
22910 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
22911 #define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
22912 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
22913 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
22914 #define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
22915 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
22916 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
22917 #define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
22918 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
22919 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
22920 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
22921 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
22922 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
22923 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
22924 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
22925 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
22926 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
22927 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
22928 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
22929 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
22930 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
22931 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
22932 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
22933 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
22934 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
22935 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
22936 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
22937 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
22938 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
22939 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
22940 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
22941 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
22942 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
22943 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
22944 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
22945 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
22946 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
22947 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
22948 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
22949 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
22950 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
22951 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
22952 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
22953 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
22954 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
22955 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
22956 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
22957 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
22958 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
22959 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
22960 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
22961 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
22962 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
22963 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
22964 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
22965 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
22966 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
22967 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
22968 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
22969 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
22970 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
22971 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
22972 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
22973 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
22974 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
22975 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
22976 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
22977 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
22978 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
22979 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
22980 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
22981 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
22982 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
22983 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
22984 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
22985 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
22986 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
22987 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
22988 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
22989 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
22990 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
22991 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
22992 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
22993 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
22994 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
22995 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
22996 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
22997 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
22998 #define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
22999 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
23000
23001 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
23002 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
23003 #define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
23004 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
23005 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
23006 #define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
23007 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
23008 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
23009 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
23010 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
23011 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
23012 #define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
23013 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
23014 #define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
23015 #define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
23016 #define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
23017 #define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
23018 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
23019 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
23020 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
23021
23022 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
23023 #define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
23024 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
23025 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
23026 #define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
23027 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
23028 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
23029 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
23030 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
23031 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
23032 #define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
23033 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
23034 #define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
23035 #define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
23036 #define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
23037 #define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
23038 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
23039 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
23040 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
23041
23042 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
23043 #define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
23044 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
23045 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
23046 #define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
23047 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
23048 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
23049 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
23050 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
23051 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
23052 #define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
23053 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
23054 #define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
23055 #define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
23056 #define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
23057 #define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
23058 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
23059 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
23060 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
23061
23062 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
23063 #define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
23064 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
23065 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
23066 #define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
23067 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
23068 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
23069 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
23070 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
23071 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
23072 #define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
23073 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
23074 #define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
23075 #define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
23076 #define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
23077 #define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
23078 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
23079 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
23080 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
23081
23082 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
23083 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
23084 #define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
23085 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
23086 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
23087 #define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
23088 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
23089 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
23090 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
23091 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
23092 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
23093 #define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
23094 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
23095 #define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
23096 #define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
23097 #define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
23098 #define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
23099 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
23100 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
23101 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
23102 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
23103 #define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
23104 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
23105 #define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
23106 #define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
23107
23108 /******************* Bit definition for HRTIM_BDMUPR register ***************/
23109 #define HRTIM_BDMUPR_MCR_Pos (0U)
23110 #define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
23111 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
23112 #define HRTIM_BDMUPR_MICR_Pos (1U)
23113 #define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
23114 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
23115 #define HRTIM_BDMUPR_MDIER_Pos (2U)
23116 #define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
23117 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
23118 #define HRTIM_BDMUPR_MCNT_Pos (3U)
23119 #define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
23120 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
23121 #define HRTIM_BDMUPR_MPER_Pos (4U)
23122 #define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
23123 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
23124 #define HRTIM_BDMUPR_MREP_Pos (5U)
23125 #define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
23126 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
23127 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
23128 #define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
23129 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
23130 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
23131 #define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
23132 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
23133 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
23134 #define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
23135 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
23136 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
23137 #define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
23138 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
23139
23140 /******************* Bit definition for HRTIM_BDTUPR register ***************/
23141 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
23142 #define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
23143 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
23144 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
23145 #define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
23146 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
23147 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
23148 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
23149 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
23150 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
23151 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
23152 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
23153 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
23154 #define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
23155 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
23156 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
23157 #define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
23158 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
23159 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
23160 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
23161 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
23162 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
23163 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
23164 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
23165 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
23166 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
23167 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
23168 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
23169 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
23170 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
23171 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
23172 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
23173 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
23174 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
23175 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
23176 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
23177 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
23178 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
23179 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
23180 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
23181 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
23182 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
23183 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
23184 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
23185 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
23186 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
23187 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
23188 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
23189 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
23190 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
23191 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
23192 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
23193 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
23194 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
23195 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
23196 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
23197 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
23198 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
23199 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
23200 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
23201 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
23202 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
23203 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
23204
23205 /******************* Bit definition for HRTIM_BDMADR register ***************/
23206 #define HRTIM_BDMADR_BDMADR_Pos (0U)
23207 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
23208 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
23209
23210 /******************************************************************************/
23211 /* */
23212 /* RAM ECC monitoring */
23213 /* */
23214 /******************************************************************************/
23215 /****************** Bit definition for RAMECC_IER register ******************/
23216 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
23217 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
23218 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
23219 #define RAMECC_IER_GECCDEIE_Pos (2U)
23220 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
23221 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
23222 #define RAMECC_IER_GECCSEIE_Pos (1U)
23223 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
23224 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
23225 #define RAMECC_IER_GIE_Pos (0U)
23226 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
23227 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
23228
23229 /******************* Bit definition for RAMECC_CR register ******************/
23230 #define RAMECC_CR_ECCELEN_Pos (5U)
23231 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
23232 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
23233 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
23234 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
23235 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
23236 #define RAMECC_CR_ECCDEIE_Pos (3U)
23237 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
23238 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
23239 #define RAMECC_CR_ECCSEIE_Pos (2U)
23240 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
23241 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
23242
23243 /******************* Bit definition for RAMECC_SR register ******************/
23244 #define RAMECC_SR_DEBWDF_Pos (2U)
23245 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
23246 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
23247 #define RAMECC_SR_DEDF_Pos (1U)
23248 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
23249 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
23250 #define RAMECC_SR_SEDCF_Pos (0U)
23251 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
23252 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
23253
23254 /****************** Bit definition for RAMECC_FAR register ******************/
23255 #define RAMECC_FAR_FADD_Pos (0U)
23256 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
23257 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
23258
23259 /****************** Bit definition for RAMECC_FDRL register *****************/
23260 #define RAMECC_FAR_FDATAL_Pos (0U)
23261 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
23262 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
23263
23264 /****************** Bit definition for RAMECC_FDRH register *****************/
23265 #define RAMECC_FAR_FDATAH_Pos (0U)
23266 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
23267 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
23268
23269 /***************** Bit definition for RAMECC_FECR register ******************/
23270 #define RAMECC_FECR_FEC_Pos (0U)
23271 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
23272 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
23273
23274 /******************************************************************************/
23275 /* */
23276 /* MDIOS */
23277 /* */
23278 /******************************************************************************/
23279 /******************** Bit definition for MDIOS_CR register *******************/
23280 #define MDIOS_CR_EN_Pos (0U)
23281 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
23282 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
23283 #define MDIOS_CR_WRIE_Pos (1U)
23284 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
23285 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
23286 #define MDIOS_CR_RDIE_Pos (2U)
23287 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
23288 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
23289 #define MDIOS_CR_EIE_Pos (3U)
23290 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
23291 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
23292 #define MDIOS_CR_DPC_Pos (7U)
23293 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
23294 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
23295 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
23296 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
23297 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
23298 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
23299 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
23300 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
23301 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
23302 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
23303
23304 /******************** Bit definition for MDIOS_SR register *******************/
23305 #define MDIOS_SR_PERF_Pos (0U)
23306 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
23307 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
23308 #define MDIOS_SR_SERF_Pos (1U)
23309 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
23310 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
23311 #define MDIOS_SR_TERF_Pos (2U)
23312 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
23313 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
23314
23315 /******************** Bit definition for MDIOS_CLRFR register *******************/
23316 #define MDIOS_SR_CPERF_Pos (0U)
23317 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
23318 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
23319 #define MDIOS_SR_CSERF_Pos (1U)
23320 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
23321 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
23322 #define MDIOS_SR_CTERF_Pos (2U)
23323 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
23324 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
23325
23326 /******************************************************************************/
23327 /* */
23328 /* USB_OTG */
23329 /* */
23330 /******************************************************************************/
23331 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
23332 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
23333 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
23334 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
23335 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
23336 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
23337 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
23338 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
23339 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
23340 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
23341 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
23342 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
23343 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
23344 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
23345 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
23346 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
23347 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
23348 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
23349 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
23350 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
23351 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
23352 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
23353 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
23354 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
23355 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
23356 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
23357 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
23358 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
23359 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
23360 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
23361 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
23362 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
23363 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
23364 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
23365 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
23366 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
23367 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
23368 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
23369 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
23370 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
23371 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
23372 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
23373 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
23374 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
23375 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
23376 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
23377 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
23378 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
23379 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
23380 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
23381 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
23382 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
23383 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
23384 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
23385 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
23386
23387 /******************** Bit definition forUSB_OTG_HCFG register ********************/
23388
23389 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
23390 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
23391 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
23392 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
23393 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
23394 #define USB_OTG_HCFG_FSLSS_Pos (2U)
23395 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
23396 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
23397
23398 /******************** Bit definition forUSB_OTG_DCFG register ********************/
23399
23400 #define USB_OTG_DCFG_DSPD_Pos (0U)
23401 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
23402 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
23403 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
23404 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
23405 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
23406 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
23407 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
23408
23409 #define USB_OTG_DCFG_DAD_Pos (4U)
23410 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
23411 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
23412 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
23413 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
23414 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
23415 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
23416 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
23417 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
23418 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
23419
23420 #define USB_OTG_DCFG_PFIVL_Pos (11U)
23421 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
23422 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
23423 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
23424 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
23425
23426 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
23427 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
23428 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
23429 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
23430 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
23431
23432 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
23433 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
23434 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
23435 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
23436 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
23437 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
23438 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
23439 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
23440 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
23441 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
23442
23443 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
23444 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
23445 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
23446 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
23447 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
23448 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
23449 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
23450 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
23451 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
23452 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
23453 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
23454 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
23455 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
23456 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
23457 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
23458 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
23459 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
23460 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
23461 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
23462
23463 /******************** Bit definition forUSB_OTG_DCTL register ********************/
23464 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
23465 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
23466 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
23467 #define USB_OTG_DCTL_SDIS_Pos (1U)
23468 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
23469 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
23470 #define USB_OTG_DCTL_GINSTS_Pos (2U)
23471 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
23472 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
23473 #define USB_OTG_DCTL_GONSTS_Pos (3U)
23474 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
23475 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
23476
23477 #define USB_OTG_DCTL_TCTL_Pos (4U)
23478 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
23479 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
23480 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
23481 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
23482 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
23483 #define USB_OTG_DCTL_SGINAK_Pos (7U)
23484 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
23485 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
23486 #define USB_OTG_DCTL_CGINAK_Pos (8U)
23487 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
23488 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
23489 #define USB_OTG_DCTL_SGONAK_Pos (9U)
23490 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
23491 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
23492 #define USB_OTG_DCTL_CGONAK_Pos (10U)
23493 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
23494 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
23495 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
23496 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
23497 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
23498
23499 /******************** Bit definition forUSB_OTG_HFIR register ********************/
23500 #define USB_OTG_HFIR_FRIVL_Pos (0U)
23501 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
23502 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
23503
23504 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
23505 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
23506 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
23507 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
23508 #define USB_OTG_HFNUM_FTREM_Pos (16U)
23509 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
23510 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
23511
23512 /******************** Bit definition forUSB_OTG_DSTS register ********************/
23513 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
23514 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
23515 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
23516
23517 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
23518 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
23519 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
23520 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
23521 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
23522 #define USB_OTG_DSTS_EERR_Pos (3U)
23523 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
23524 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
23525 #define USB_OTG_DSTS_FNSOF_Pos (8U)
23526 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
23527 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
23528
23529 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
23530 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
23531 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
23532 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
23533
23534 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
23535 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
23536 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
23537 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
23538 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
23539 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
23540 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
23541 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
23542 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
23543 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
23544 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
23545 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
23546 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
23547 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
23548 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
23549 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
23550 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
23551
23552 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
23553
23554 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
23555 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
23556 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
23557 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
23558 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
23559 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
23560 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
23561 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
23562 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
23563 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
23564 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
23565 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
23566 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
23567 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
23568 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
23569
23570 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
23571 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
23572 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
23573 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
23574 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
23575 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
23576 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
23577 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
23578 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
23579 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
23580 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
23581 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
23582 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
23583 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
23584 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
23585 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
23586 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
23587 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
23588 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
23589 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
23590 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
23591 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
23592 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
23593 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
23594 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
23595 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
23596 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
23597 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
23598 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
23599 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
23600 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
23601 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
23602 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
23603 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
23604 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
23605 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
23606 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
23607 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
23608 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
23609 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
23610 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
23611 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
23612 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
23613 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
23614 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
23615 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
23616
23617 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
23618 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
23619 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
23620 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
23621 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
23622 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
23623 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
23624 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
23625 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
23626 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
23627 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
23628 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
23629 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
23630 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
23631 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
23632 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
23633
23634 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
23635 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
23636 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
23637 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
23638 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
23639 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
23640 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
23641 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
23642 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
23643 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
23644 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
23645 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
23646 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
23647 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
23648
23649 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
23650 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
23651 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
23652 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
23653 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
23654 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
23655 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
23656 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
23657 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
23658 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
23659 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
23660 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
23661 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
23662 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
23663 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
23664 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
23665 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
23666 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
23667 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
23668 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
23669 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
23670 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
23671 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
23672 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
23673 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
23674
23675 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
23676 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
23677 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
23678 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
23679
23680 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
23681 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
23682 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
23683 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
23684 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
23685 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
23686 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
23687 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
23688 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
23689 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
23690 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
23691
23692 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
23693 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
23694 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
23695 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
23696 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
23697 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
23698 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
23699 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
23700 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
23701 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
23702 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
23703
23704 /******************** Bit definition forUSB_OTG_HAINT register ********************/
23705 #define USB_OTG_HAINT_HAINT_Pos (0U)
23706 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
23707 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
23708
23709 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
23710 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
23711 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
23712 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
23713 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
23714 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
23715 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
23716 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
23717 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
23718 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
23719 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
23720 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
23721 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
23722 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
23723 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
23724 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
23725 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
23726 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
23727 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
23728 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
23729 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
23730 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
23731 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
23732 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
23733 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
23734 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
23735 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
23736 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
23737 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
23738 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
23739 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
23740 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
23741 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
23742 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
23743 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
23744 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
23745 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
23746
23747 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
23748 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
23749 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
23750 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
23751 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
23752 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
23753 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
23754 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
23755 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
23756 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
23757 #define USB_OTG_GINTSTS_SOF_Pos (3U)
23758 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
23759 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
23760 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
23761 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
23762 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
23763 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
23764 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
23765 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
23766 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
23767 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
23768 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
23769 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
23770 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
23771 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
23772 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
23773 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
23774 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
23775 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
23776 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
23777 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
23778 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
23779 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
23780 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
23781 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
23782 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
23783 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
23784 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
23785 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
23786 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
23787 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
23788 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
23789 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
23790 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
23791 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
23792 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
23793 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
23794 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
23795 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
23796 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
23797 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
23798 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
23799 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
23800 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
23801 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
23802 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
23803 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
23804 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
23805 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
23806 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
23807 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
23808 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
23809 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
23810 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
23811 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
23812 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
23813 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
23814 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
23815 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
23816 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
23817 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
23818 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
23819 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
23820 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
23821 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
23822 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
23823 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
23824 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
23825 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
23826 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
23827 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
23828 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
23829 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
23830 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
23831 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
23832
23833 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
23834 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
23835 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
23836 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
23837 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
23838 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
23839 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
23840 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
23841 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
23842 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
23843 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
23844 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
23845 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
23846 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
23847 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
23848 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
23849 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
23850 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
23851 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
23852 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
23853 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
23854 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
23855 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
23856 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
23857 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
23858 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
23859 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
23860 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
23861 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
23862 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
23863 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
23864 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
23865 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
23866 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
23867 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
23868 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
23869 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
23870 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
23871 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
23872 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
23873 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
23874 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
23875 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
23876 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
23877 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
23878 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
23879 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
23880 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
23881 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
23882 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
23883 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
23884 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
23885 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
23886 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
23887 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
23888 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
23889 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
23890 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
23891 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
23892 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
23893 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
23894 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
23895 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
23896 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
23897 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
23898 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
23899 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
23900 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
23901 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
23902 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
23903 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
23904 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
23905 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
23906 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
23907 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
23908 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
23909 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
23910 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
23911 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
23912 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
23913 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
23914 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
23915 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
23916 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
23917 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
23918
23919 /******************** Bit definition forUSB_OTG_DAINT register ********************/
23920 #define USB_OTG_DAINT_IEPINT_Pos (0U)
23921 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
23922 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
23923 #define USB_OTG_DAINT_OEPINT_Pos (16U)
23924 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
23925 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
23926
23927 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
23928 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
23929 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
23930 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
23931
23932 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
23933 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
23934 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
23935 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
23936 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
23937 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
23938 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
23939 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
23940 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
23941 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
23942 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
23943 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
23944 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
23945
23946 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
23947 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
23948 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
23949 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
23950 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
23951 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
23952 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
23953
23954 /******************** Bit definition for OTG register ********************/
23955
23956 #define USB_OTG_CHNUM_Pos (0U)
23957 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
23958 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
23959 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
23960 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
23961 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
23962 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
23963 #define USB_OTG_BCNT_Pos (4U)
23964 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
23965 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
23966
23967 #define USB_OTG_DPID_Pos (15U)
23968 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
23969 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
23970 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
23971 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
23972
23973 #define USB_OTG_PKTSTS_Pos (17U)
23974 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
23975 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
23976 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
23977 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
23978 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
23979 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
23980
23981 #define USB_OTG_EPNUM_Pos (0U)
23982 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
23983 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
23984 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
23985 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
23986 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
23987 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
23988
23989 #define USB_OTG_FRMNUM_Pos (21U)
23990 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
23991 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
23992 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
23993 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
23994 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
23995 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
23996
23997 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
23998 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
23999 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
24000 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
24001
24002 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
24003 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
24004 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
24005 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
24006
24007 /******************** Bit definition for OTG register ********************/
24008 #define USB_OTG_NPTXFSA_Pos (0U)
24009 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
24010 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
24011 #define USB_OTG_NPTXFD_Pos (16U)
24012 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
24013 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
24014 #define USB_OTG_TX0FSA_Pos (0U)
24015 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
24016 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
24017 #define USB_OTG_TX0FD_Pos (16U)
24018 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
24019 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
24020
24021 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
24022 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
24023 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
24024 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
24025
24026 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
24027 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
24028 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
24029 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
24030
24031 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
24032 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
24033 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
24034 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
24035 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
24036 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
24037 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
24038 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
24039 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
24040 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
24041 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
24042
24043 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
24044 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
24045 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
24046 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
24047 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
24048 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
24049 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
24050 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
24051 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
24052 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
24053
24054 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
24055 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
24056 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
24057 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
24058 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
24059 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
24060 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
24061
24062 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
24063 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
24064 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
24065 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
24066 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
24067 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
24068 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
24069 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
24070 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
24071 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
24072 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
24073 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
24074 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
24075 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
24076 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
24077
24078 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
24079 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
24080 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
24081 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
24082 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
24083 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
24084 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
24085 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
24086 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
24087 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
24088 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
24089 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
24090 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
24091 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
24092 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
24093
24094 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
24095 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
24096 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
24097 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
24098
24099 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
24100 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
24101 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
24102 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
24103 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
24104 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
24105 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
24106
24107 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
24108 #define USB_OTG_GCCFG_DCDET_Pos (0U)
24109 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
24110 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
24111 #define USB_OTG_GCCFG_PDET_Pos (1U)
24112 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
24113 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
24114 #define USB_OTG_GCCFG_SDET_Pos (2U)
24115 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
24116 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
24117 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
24118 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
24119 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
24120 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
24121 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
24122 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
24123 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
24124 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
24125 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
24126 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
24127 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
24128 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
24129 #define USB_OTG_GCCFG_PDEN_Pos (19U)
24130 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
24131 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
24132 #define USB_OTG_GCCFG_SDEN_Pos (20U)
24133 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
24134 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
24135 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
24136 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
24137 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
24138
24139 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
24140 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
24141 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
24142 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
24143 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
24144 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
24145 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
24146
24147 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
24148 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
24149 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
24150 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
24151 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
24152 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
24153 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
24154
24155 /******************** Bit definition forUSB_OTG_CID register ********************/
24156 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
24157 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
24158 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
24159
24160 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
24161 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
24162 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
24163 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
24164 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
24165 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
24166 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
24167 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
24168 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
24169 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
24170 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
24171 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
24172 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
24173 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
24174 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
24175 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
24176 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
24177 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
24178 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
24179 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
24180 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
24181 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
24182 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
24183 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
24184 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
24185 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
24186 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
24187 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
24188 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
24189 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
24190 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
24191 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
24192 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
24193 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
24194 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
24195 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
24196 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
24197 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
24198 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
24199 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
24200 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
24201 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
24202 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
24203 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
24204 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
24205 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
24206
24207 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
24208 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
24209 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
24210 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
24211 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
24212 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
24213 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24214 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
24215 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
24216 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
24217 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
24218 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
24219 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
24220 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
24221 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
24222 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
24223 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
24224 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
24225 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
24226 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
24227 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
24228 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
24229 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
24230 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
24231 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
24232 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
24233 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
24234 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
24235
24236 /******************** Bit definition forUSB_OTG_HPRT register ********************/
24237 #define USB_OTG_HPRT_PCSTS_Pos (0U)
24238 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
24239 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
24240 #define USB_OTG_HPRT_PCDET_Pos (1U)
24241 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
24242 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
24243 #define USB_OTG_HPRT_PENA_Pos (2U)
24244 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
24245 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
24246 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
24247 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
24248 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
24249 #define USB_OTG_HPRT_POCA_Pos (4U)
24250 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
24251 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
24252 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
24253 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
24254 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
24255 #define USB_OTG_HPRT_PRES_Pos (6U)
24256 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
24257 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
24258 #define USB_OTG_HPRT_PSUSP_Pos (7U)
24259 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
24260 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
24261 #define USB_OTG_HPRT_PRST_Pos (8U)
24262 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
24263 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
24264
24265 #define USB_OTG_HPRT_PLSTS_Pos (10U)
24266 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
24267 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
24268 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
24269 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
24270 #define USB_OTG_HPRT_PPWR_Pos (12U)
24271 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
24272 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
24273
24274 #define USB_OTG_HPRT_PTCTL_Pos (13U)
24275 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
24276 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
24277 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
24278 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
24279 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
24280 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
24281
24282 #define USB_OTG_HPRT_PSPD_Pos (17U)
24283 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
24284 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
24285 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
24286 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
24287
24288 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
24289 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
24290 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
24291 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
24292 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
24293 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
24294 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
24295 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
24296 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
24297 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
24298 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
24299 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
24300 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
24301 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
24302 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
24303 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
24304 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
24305 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
24306 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
24307 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
24308 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
24309 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
24310 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
24311 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
24312 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
24313 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
24314 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
24315 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
24316 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
24317 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
24318 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
24319 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
24320 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
24321 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
24322
24323 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
24324 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
24325 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
24326 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
24327 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
24328 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
24329 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
24330
24331 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
24332 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
24333 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
24334 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
24335 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
24336 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
24337 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
24338 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
24339 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
24340 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
24341 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
24342 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
24343 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
24344
24345 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
24346 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
24347 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
24348 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
24349 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
24350 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
24351 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
24352 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
24353
24354 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
24355 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
24356 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
24357 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
24358 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
24359 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
24360 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
24361 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
24362 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
24363 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
24364 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
24365 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
24366 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
24367 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
24368 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
24369 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
24370 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
24371 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
24372 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
24373 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
24374 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
24375 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
24376 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
24377 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
24378 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
24379
24380 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
24381 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
24382 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
24383 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
24384
24385 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
24386 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
24387 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
24388 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
24389 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
24390 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
24391 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
24392 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
24393 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
24394 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
24395 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
24396 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
24397 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
24398
24399 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
24400 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
24401 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
24402 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
24403 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
24404
24405 #define USB_OTG_HCCHAR_MC_Pos (20U)
24406 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
24407 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
24408 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
24409 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
24410
24411 #define USB_OTG_HCCHAR_DAD_Pos (22U)
24412 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
24413 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
24414 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
24415 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
24416 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
24417 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
24418 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
24419 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
24420 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
24421 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
24422 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
24423 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
24424 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
24425 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
24426 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
24427 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
24428 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
24429 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
24430
24431 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
24432
24433 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
24434 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
24435 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
24436 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
24437 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
24438 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
24439 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
24440 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
24441 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
24442 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
24443
24444 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
24445 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
24446 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
24447 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
24448 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
24449 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
24450 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
24451 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
24452 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
24453 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
24454
24455 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
24456 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
24457 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
24458 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
24459 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
24460 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
24461 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
24462 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
24463 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
24464 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
24465 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
24466
24467 /******************** Bit definition forUSB_OTG_HCINT register ********************/
24468 #define USB_OTG_HCINT_XFRC_Pos (0U)
24469 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
24470 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
24471 #define USB_OTG_HCINT_CHH_Pos (1U)
24472 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
24473 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
24474 #define USB_OTG_HCINT_AHBERR_Pos (2U)
24475 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
24476 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
24477 #define USB_OTG_HCINT_STALL_Pos (3U)
24478 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
24479 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
24480 #define USB_OTG_HCINT_NAK_Pos (4U)
24481 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
24482 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
24483 #define USB_OTG_HCINT_ACK_Pos (5U)
24484 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
24485 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
24486 #define USB_OTG_HCINT_NYET_Pos (6U)
24487 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
24488 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
24489 #define USB_OTG_HCINT_TXERR_Pos (7U)
24490 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
24491 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
24492 #define USB_OTG_HCINT_BBERR_Pos (8U)
24493 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
24494 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
24495 #define USB_OTG_HCINT_FRMOR_Pos (9U)
24496 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
24497 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
24498 #define USB_OTG_HCINT_DTERR_Pos (10U)
24499 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
24500 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
24501
24502 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
24503 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
24504 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
24505 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
24506 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
24507 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
24508 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
24509 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
24510 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
24511 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
24512 #define USB_OTG_DIEPINT_TOC_Pos (3U)
24513 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
24514 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
24515 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
24516 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
24517 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
24518 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
24519 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
24520 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
24521 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
24522 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
24523 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
24524 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
24525 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
24526 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
24527 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
24528 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
24529 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
24530 #define USB_OTG_DIEPINT_BNA_Pos (9U)
24531 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
24532 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
24533 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
24534 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
24535 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
24536 #define USB_OTG_DIEPINT_BERR_Pos (12U)
24537 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
24538 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
24539 #define USB_OTG_DIEPINT_NAK_Pos (13U)
24540 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
24541 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
24542
24543 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
24544 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
24545 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
24546 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
24547 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
24548 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
24549 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
24550 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
24551 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
24552 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
24553 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
24554 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
24555 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
24556 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
24557 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
24558 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
24559 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
24560 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
24561 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
24562 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
24563 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
24564 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
24565 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
24566 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
24567 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
24568 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
24569 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
24570 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
24571 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
24572 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
24573 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
24574 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
24575 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
24576 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
24577
24578 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
24579
24580 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
24581 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
24582 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
24583 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
24584 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
24585 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
24586 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
24587 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
24588 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
24589 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
24590 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
24591 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
24592 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
24593 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
24594 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
24595 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
24596 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
24597 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
24598 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
24599 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
24600 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
24601 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
24602 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
24603 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
24604
24605 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
24606 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
24607 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
24608 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
24609
24610 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
24611 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
24612 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
24613 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
24614
24615 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
24616 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
24617 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
24618 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
24619
24620 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
24621 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
24622 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
24623 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
24624 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
24625 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
24626 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
24627
24628 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
24629
24630 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
24631 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
24632 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
24633 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
24634 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
24635 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
24636 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
24637 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
24638 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
24639 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
24640 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
24641 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
24642 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
24643 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
24644 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
24645 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
24646 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
24647 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
24648 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
24649 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
24650 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
24651 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
24652 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
24653 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
24654 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
24655 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
24656 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
24657 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
24658 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
24659 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
24660 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
24661 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
24662 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
24663 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
24664 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
24665 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
24666 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
24667 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
24668
24669 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
24670 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
24671 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
24672 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
24673 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
24674 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
24675 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
24676 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
24677 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
24678 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
24679 #define USB_OTG_DOEPINT_STUP_Pos (3U)
24680 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
24681 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
24682 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
24683 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
24684 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
24685 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
24686 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
24687 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
24688 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
24689 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
24690 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
24691 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
24692 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
24693 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
24694 #define USB_OTG_DOEPINT_BERR_Pos (12U)
24695 #define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
24696 #define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
24697 #define USB_OTG_DOEPINT_NAK_Pos (13U)
24698 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
24699 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
24700 #define USB_OTG_DOEPINT_NYET_Pos (14U)
24701 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
24702 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
24703 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
24704 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
24705 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
24706
24707 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
24708
24709 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
24710 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
24711 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
24712 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
24713 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
24714 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
24715
24716 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
24717 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
24718 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
24719 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
24720 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
24721
24722 /******************** Bit definition for PCGCCTL register ********************/
24723 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
24724 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
24725 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
24726 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
24727 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
24728 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
24729 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
24730 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
24731 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
24732
24733 /**
24734 * @}
24735 */
24736
24737 /**
24738 * @}
24739 */
24740
24741 /** @addtogroup Exported_macros
24742 * @{
24743 */
24744
24745 /******************************* ADC Instances ********************************/
24746 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
24747 ((INSTANCE) == ADC2) || \
24748 ((INSTANCE) == ADC3))
24749
24750 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
24751
24752 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
24753 ((INSTANCE) == ADC3_COMMON))
24754
24755 /******************************** COMP Instances ******************************/
24756 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
24757 ((INSTANCE) == COMP2))
24758
24759 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
24760 /******************** COMP Instances with window mode capability **************/
24761 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
24762
24763
24764 /******************************* CRC Instances ********************************/
24765 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
24766
24767 /******************************* DAC Instances ********************************/
24768 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
24769 /******************************* DCMI Instances *******************************/
24770 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
24771
24772 /******************************* DELAYBLOCK Instances *******************************/
24773 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
24774 ((INSTANCE) == DLYB_SDMMC2) || \
24775 ((INSTANCE) == DLYB_QUADSPI))
24776 /****************************** DFSDM Instances *******************************/
24777 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
24778 ((INSTANCE) == DFSDM1_Filter1) || \
24779 ((INSTANCE) == DFSDM1_Filter2) || \
24780 ((INSTANCE) == DFSDM1_Filter3))
24781
24782 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
24783 ((INSTANCE) == DFSDM1_Channel1) || \
24784 ((INSTANCE) == DFSDM1_Channel2) || \
24785 ((INSTANCE) == DFSDM1_Channel3) || \
24786 ((INSTANCE) == DFSDM1_Channel4) || \
24787 ((INSTANCE) == DFSDM1_Channel5) || \
24788 ((INSTANCE) == DFSDM1_Channel6) || \
24789 ((INSTANCE) == DFSDM1_Channel7))
24790 /****************************** RAMECC Instances ******************************/
24791 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
24792 ((INSTANCE) == RAMECC1_Monitor2) || \
24793 ((INSTANCE) == RAMECC1_Monitor3) || \
24794 ((INSTANCE) == RAMECC1_Monitor4) || \
24795 ((INSTANCE) == RAMECC1_Monitor5) || \
24796 ((INSTANCE) == RAMECC2_Monitor1) || \
24797 ((INSTANCE) == RAMECC2_Monitor2) || \
24798 ((INSTANCE) == RAMECC2_Monitor3) || \
24799 ((INSTANCE) == RAMECC2_Monitor4) || \
24800 ((INSTANCE) == RAMECC2_Monitor5) || \
24801 ((INSTANCE) == RAMECC3_Monitor1) || \
24802 ((INSTANCE) == RAMECC3_Monitor2))
24803
24804 /******************************** DMA Instances *******************************/
24805 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
24806 ((INSTANCE) == DMA1_Stream1) || \
24807 ((INSTANCE) == DMA1_Stream2) || \
24808 ((INSTANCE) == DMA1_Stream3) || \
24809 ((INSTANCE) == DMA1_Stream4) || \
24810 ((INSTANCE) == DMA1_Stream5) || \
24811 ((INSTANCE) == DMA1_Stream6) || \
24812 ((INSTANCE) == DMA1_Stream7) || \
24813 ((INSTANCE) == DMA2_Stream0) || \
24814 ((INSTANCE) == DMA2_Stream1) || \
24815 ((INSTANCE) == DMA2_Stream2) || \
24816 ((INSTANCE) == DMA2_Stream3) || \
24817 ((INSTANCE) == DMA2_Stream4) || \
24818 ((INSTANCE) == DMA2_Stream5) || \
24819 ((INSTANCE) == DMA2_Stream6) || \
24820 ((INSTANCE) == DMA2_Stream7) || \
24821 ((INSTANCE) == BDMA_Channel0) || \
24822 ((INSTANCE) == BDMA_Channel1) || \
24823 ((INSTANCE) == BDMA_Channel2) || \
24824 ((INSTANCE) == BDMA_Channel3) || \
24825 ((INSTANCE) == BDMA_Channel4) || \
24826 ((INSTANCE) == BDMA_Channel5) || \
24827 ((INSTANCE) == BDMA_Channel6) || \
24828 ((INSTANCE) == BDMA_Channel7))
24829
24830 /****************************** BDMA CHANNEL Instances ***************************/
24831 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
24832 ((INSTANCE) == BDMA_Channel1) || \
24833 ((INSTANCE) == BDMA_Channel2) || \
24834 ((INSTANCE) == BDMA_Channel3) || \
24835 ((INSTANCE) == BDMA_Channel4) || \
24836 ((INSTANCE) == BDMA_Channel5) || \
24837 ((INSTANCE) == BDMA_Channel6) || \
24838 ((INSTANCE) == BDMA_Channel7))
24839
24840 /****************************** DMA DMAMUX ALL Instances ***************************/
24841 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
24842 ((INSTANCE) == DMA1_Stream1) || \
24843 ((INSTANCE) == DMA1_Stream2) || \
24844 ((INSTANCE) == DMA1_Stream3) || \
24845 ((INSTANCE) == DMA1_Stream4) || \
24846 ((INSTANCE) == DMA1_Stream5) || \
24847 ((INSTANCE) == DMA1_Stream6) || \
24848 ((INSTANCE) == DMA1_Stream7) || \
24849 ((INSTANCE) == DMA2_Stream0) || \
24850 ((INSTANCE) == DMA2_Stream1) || \
24851 ((INSTANCE) == DMA2_Stream2) || \
24852 ((INSTANCE) == DMA2_Stream3) || \
24853 ((INSTANCE) == DMA2_Stream4) || \
24854 ((INSTANCE) == DMA2_Stream5) || \
24855 ((INSTANCE) == DMA2_Stream6) || \
24856 ((INSTANCE) == DMA2_Stream7) || \
24857 ((INSTANCE) == BDMA_Channel0) || \
24858 ((INSTANCE) == BDMA_Channel1) || \
24859 ((INSTANCE) == BDMA_Channel2) || \
24860 ((INSTANCE) == BDMA_Channel3) || \
24861 ((INSTANCE) == BDMA_Channel4) || \
24862 ((INSTANCE) == BDMA_Channel5) || \
24863 ((INSTANCE) == BDMA_Channel6) || \
24864 ((INSTANCE) == BDMA_Channel7))
24865
24866 /****************************** BDMA DMAMUX Instances ***************************/
24867 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
24868 ((INSTANCE) == BDMA_Channel1) || \
24869 ((INSTANCE) == BDMA_Channel2) || \
24870 ((INSTANCE) == BDMA_Channel3) || \
24871 ((INSTANCE) == BDMA_Channel4) || \
24872 ((INSTANCE) == BDMA_Channel5) || \
24873 ((INSTANCE) == BDMA_Channel6) || \
24874 ((INSTANCE) == BDMA_Channel7))
24875
24876 /****************************** DMA STREAM Instances ***************************/
24877 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
24878 ((INSTANCE) == DMA1_Stream1) || \
24879 ((INSTANCE) == DMA1_Stream2) || \
24880 ((INSTANCE) == DMA1_Stream3) || \
24881 ((INSTANCE) == DMA1_Stream4) || \
24882 ((INSTANCE) == DMA1_Stream5) || \
24883 ((INSTANCE) == DMA1_Stream6) || \
24884 ((INSTANCE) == DMA1_Stream7) || \
24885 ((INSTANCE) == DMA2_Stream0) || \
24886 ((INSTANCE) == DMA2_Stream1) || \
24887 ((INSTANCE) == DMA2_Stream2) || \
24888 ((INSTANCE) == DMA2_Stream3) || \
24889 ((INSTANCE) == DMA2_Stream4) || \
24890 ((INSTANCE) == DMA2_Stream5) || \
24891 ((INSTANCE) == DMA2_Stream6) || \
24892 ((INSTANCE) == DMA2_Stream7))
24893
24894 /****************************** DMA DMAMUX Instances ***************************/
24895 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
24896 ((INSTANCE) == DMA1_Stream1) || \
24897 ((INSTANCE) == DMA1_Stream2) || \
24898 ((INSTANCE) == DMA1_Stream3) || \
24899 ((INSTANCE) == DMA1_Stream4) || \
24900 ((INSTANCE) == DMA1_Stream5) || \
24901 ((INSTANCE) == DMA1_Stream6) || \
24902 ((INSTANCE) == DMA1_Stream7) || \
24903 ((INSTANCE) == DMA2_Stream0) || \
24904 ((INSTANCE) == DMA2_Stream1) || \
24905 ((INSTANCE) == DMA2_Stream2) || \
24906 ((INSTANCE) == DMA2_Stream3) || \
24907 ((INSTANCE) == DMA2_Stream4) || \
24908 ((INSTANCE) == DMA2_Stream5) || \
24909 ((INSTANCE) == DMA2_Stream6) || \
24910 ((INSTANCE) == DMA2_Stream7))
24911
24912 /******************************** DMA Request Generator Instances **************/
24913 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
24914 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
24915 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
24916 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
24917 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
24918 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
24919 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
24920 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
24921 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
24922 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
24923 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
24924 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
24925 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
24926 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
24927 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
24928 ((INSTANCE) == DMAMUX2_RequestGenerator7))
24929
24930 /******************************* DMA2D Instances *******************************/
24931 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
24932
24933 /******************************** MDMA Request Generator Instances **************/
24934 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
24935 ((INSTANCE) == MDMA_Channel1) || \
24936 ((INSTANCE) == MDMA_Channel2) || \
24937 ((INSTANCE) == MDMA_Channel3) || \
24938 ((INSTANCE) == MDMA_Channel4) || \
24939 ((INSTANCE) == MDMA_Channel5) || \
24940 ((INSTANCE) == MDMA_Channel6) || \
24941 ((INSTANCE) == MDMA_Channel7) || \
24942 ((INSTANCE) == MDMA_Channel8) || \
24943 ((INSTANCE) == MDMA_Channel9) || \
24944 ((INSTANCE) == MDMA_Channel10) || \
24945 ((INSTANCE) == MDMA_Channel11) || \
24946 ((INSTANCE) == MDMA_Channel12) || \
24947 ((INSTANCE) == MDMA_Channel13) || \
24948 ((INSTANCE) == MDMA_Channel14) || \
24949 ((INSTANCE) == MDMA_Channel15))
24950
24951 /******************************* QUADSPI Instances *******************************/
24952 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
24953
24954 /******************************* FDCAN Instances ******************************/
24955 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
24956 ((__INSTANCE__) == FDCAN2))
24957
24958 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
24959
24960 /******************************* GPIO Instances *******************************/
24961 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
24962 ((INSTANCE) == GPIOB) || \
24963 ((INSTANCE) == GPIOC) || \
24964 ((INSTANCE) == GPIOD) || \
24965 ((INSTANCE) == GPIOE) || \
24966 ((INSTANCE) == GPIOF) || \
24967 ((INSTANCE) == GPIOG) || \
24968 ((INSTANCE) == GPIOH) || \
24969 ((INSTANCE) == GPIOI) || \
24970 ((INSTANCE) == GPIOJ) || \
24971 ((INSTANCE) == GPIOK))
24972
24973 /******************************* GPIO AF Instances ****************************/
24974 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
24975
24976 /**************************** GPIO Lock Instances *****************************/
24977 /* On H7, all GPIO Bank support the Lock mechanism */
24978 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
24979
24980 /******************************** HSEM Instances *******************************/
24981 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
24982 #define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
24983 #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
24984 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
24985
24986 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
24987 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
24988
24989 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
24990 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
24991
24992 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
24993 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
24994
24995 /******************************** I2C Instances *******************************/
24996 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
24997 ((INSTANCE) == I2C2) || \
24998 ((INSTANCE) == I2C3) || \
24999 ((INSTANCE) == I2C4))
25000 /************** I2C Instances : wakeup capability from stop modes *************/
25001 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
25002
25003 /****************************** SMBUS Instances *******************************/
25004 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
25005 ((INSTANCE) == I2C2) || \
25006 ((INSTANCE) == I2C3) || \
25007 ((INSTANCE) == I2C4))
25008 /******************************** I2S Instances *******************************/
25009 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25010 ((INSTANCE) == SPI2) || \
25011 ((INSTANCE) == SPI3))
25012
25013
25014 /******************************* RNG Instances ********************************/
25015 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
25016
25017 /****************************** RTC Instances *********************************/
25018 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
25019
25020 /****************************** SDMMC Instances *********************************/
25021 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
25022 ((_INSTANCE_) == SDMMC2))
25023
25024 /******************************** SMBUS Instances *****************************/
25025 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
25026
25027 /******************************** SPI Instances *******************************/
25028 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25029 ((INSTANCE) == SPI2) || \
25030 ((INSTANCE) == SPI3) || \
25031 ((INSTANCE) == SPI4) || \
25032 ((INSTANCE) == SPI5) || \
25033 ((INSTANCE) == SPI6))
25034
25035 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
25036 ((INSTANCE) == SPI2) || \
25037 ((INSTANCE) == SPI3))
25038
25039 /******************************** SWPMI Instances *****************************/
25040 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
25041
25042 /****************** LPTIM Instances : All supported instances *****************/
25043 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25044 ((INSTANCE) == LPTIM2) || \
25045 ((INSTANCE) == LPTIM3) || \
25046 ((INSTANCE) == LPTIM4) || \
25047 ((INSTANCE) == LPTIM5))
25048
25049 /****************** LPTIM Instances : supporting encoder interface **************/
25050 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
25051 ((INSTANCE) == LPTIM2))
25052
25053 /****************** TIM Instances : All supported instances *******************/
25054 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25055 ((INSTANCE) == TIM2) || \
25056 ((INSTANCE) == TIM3) || \
25057 ((INSTANCE) == TIM4) || \
25058 ((INSTANCE) == TIM5) || \
25059 ((INSTANCE) == TIM6) || \
25060 ((INSTANCE) == TIM7) || \
25061 ((INSTANCE) == TIM8) || \
25062 ((INSTANCE) == TIM12) || \
25063 ((INSTANCE) == TIM13) || \
25064 ((INSTANCE) == TIM14) || \
25065 ((INSTANCE) == TIM15) || \
25066 ((INSTANCE) == TIM16) || \
25067 ((INSTANCE) == TIM17))
25068
25069 /************* TIM Instances : at least 1 capture/compare channel *************/
25070 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25071 ((INSTANCE) == TIM2) || \
25072 ((INSTANCE) == TIM3) || \
25073 ((INSTANCE) == TIM4) || \
25074 ((INSTANCE) == TIM5) || \
25075 ((INSTANCE) == TIM8) || \
25076 ((INSTANCE) == TIM12) || \
25077 ((INSTANCE) == TIM13) || \
25078 ((INSTANCE) == TIM14) || \
25079 ((INSTANCE) == TIM15) || \
25080 ((INSTANCE) == TIM16) || \
25081 ((INSTANCE) == TIM17))
25082
25083 /************ TIM Instances : at least 2 capture/compare channels *************/
25084 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25085 ((INSTANCE) == TIM2) || \
25086 ((INSTANCE) == TIM3) || \
25087 ((INSTANCE) == TIM4) || \
25088 ((INSTANCE) == TIM5) || \
25089 ((INSTANCE) == TIM8) || \
25090 ((INSTANCE) == TIM12) || \
25091 ((INSTANCE) == TIM15))
25092
25093 /************ TIM Instances : at least 3 capture/compare channels *************/
25094 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25095 ((INSTANCE) == TIM2) || \
25096 ((INSTANCE) == TIM3) || \
25097 ((INSTANCE) == TIM4) || \
25098 ((INSTANCE) == TIM5) || \
25099 ((INSTANCE) == TIM8))
25100
25101 /************ TIM Instances : at least 4 capture/compare channels *************/
25102 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25103 ((INSTANCE) == TIM2) || \
25104 ((INSTANCE) == TIM3) || \
25105 ((INSTANCE) == TIM4) || \
25106 ((INSTANCE) == TIM5) || \
25107 ((INSTANCE) == TIM8))
25108
25109 /************ TIM Instances : at least 5 capture/compare channels *************/
25110 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25111 ((INSTANCE) == TIM8))
25112 /************ TIM Instances : at least 6 capture/compare channels *************/
25113 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25114 ((INSTANCE) == TIM8))
25115
25116 /******************** TIM Instances : Advanced-control timers *****************/
25117 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25118 ((__INSTANCE__) == TIM8))
25119
25120 /******************** TIM Instances : Advanced-control timers *****************/
25121
25122 /******************* TIM Instances : Timer input XOR function *****************/
25123 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25124 ((INSTANCE) == TIM2) || \
25125 ((INSTANCE) == TIM3) || \
25126 ((INSTANCE) == TIM4) || \
25127 ((INSTANCE) == TIM5) || \
25128 ((INSTANCE) == TIM8) || \
25129 ((INSTANCE) == TIM15))
25130
25131 /****************** TIM Instances : DMA requests generation (UDE) *************/
25132 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25133 ((INSTANCE) == TIM2) || \
25134 ((INSTANCE) == TIM3) || \
25135 ((INSTANCE) == TIM4) || \
25136 ((INSTANCE) == TIM5) || \
25137 ((INSTANCE) == TIM6) || \
25138 ((INSTANCE) == TIM7) || \
25139 ((INSTANCE) == TIM8) || \
25140 ((INSTANCE) == TIM15) || \
25141 ((INSTANCE) == TIM16) || \
25142 ((INSTANCE) == TIM17))
25143
25144 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
25145 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25146 ((INSTANCE) == TIM2) || \
25147 ((INSTANCE) == TIM3) || \
25148 ((INSTANCE) == TIM4) || \
25149 ((INSTANCE) == TIM5) || \
25150 ((INSTANCE) == TIM8) || \
25151 ((INSTANCE) == TIM15) || \
25152 ((INSTANCE) == TIM16) || \
25153 ((INSTANCE) == TIM17))
25154
25155 /************ TIM Instances : DMA requests generation (COMDE) *****************/
25156 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25157 ((INSTANCE) == TIM2) || \
25158 ((INSTANCE) == TIM3) || \
25159 ((INSTANCE) == TIM4) || \
25160 ((INSTANCE) == TIM5) || \
25161 ((INSTANCE) == TIM8) || \
25162 ((INSTANCE) == TIM15))
25163
25164 /******************** TIM Instances : DMA burst feature ***********************/
25165 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25166 ((INSTANCE) == TIM2) || \
25167 ((INSTANCE) == TIM3) || \
25168 ((INSTANCE) == TIM4) || \
25169 ((INSTANCE) == TIM5) || \
25170 ((INSTANCE) == TIM8))
25171
25172 /*************** TIM Instances : external trigger reamp input available *******/
25173 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25174 ((INSTANCE) == TIM2) || \
25175 ((INSTANCE) == TIM3) || \
25176 ((INSTANCE) == TIM4) || \
25177 ((INSTANCE) == TIM5) || \
25178 ((INSTANCE) == TIM8))
25179
25180 /****************** TIM Instances : remapping capability **********************/
25181 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25182 ((INSTANCE) == TIM2) || \
25183 ((INSTANCE) == TIM3) || \
25184 ((INSTANCE) == TIM5) || \
25185 ((INSTANCE) == TIM8) || \
25186 ((INSTANCE) == TIM16) || \
25187 ((INSTANCE) == TIM17))
25188
25189 /*************** TIM Instances : external trigger reamp input available *******/
25190 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25191 ((INSTANCE) == TIM2) || \
25192 ((INSTANCE) == TIM3) || \
25193 ((INSTANCE) == TIM5) || \
25194 ((INSTANCE) == TIM8))
25195
25196 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
25197 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25198 ((INSTANCE) == TIM2) || \
25199 ((INSTANCE) == TIM3) || \
25200 ((INSTANCE) == TIM4) || \
25201 ((INSTANCE) == TIM5) || \
25202 ((INSTANCE) == TIM6) || \
25203 ((INSTANCE) == TIM7) || \
25204 ((INSTANCE) == TIM8) || \
25205 ((INSTANCE) == TIM15))
25206
25207 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
25208 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25209 ((INSTANCE) == TIM2) || \
25210 ((INSTANCE) == TIM3) || \
25211 ((INSTANCE) == TIM4) || \
25212 ((INSTANCE) == TIM5) || \
25213 ((INSTANCE) == TIM8) || \
25214 ((INSTANCE) == TIM12))
25215
25216 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
25217 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25218 ((INSTANCE) == TIM8))
25219
25220 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
25221 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25222 ((INSTANCE) == TIM2) || \
25223 ((INSTANCE) == TIM3) || \
25224 ((INSTANCE) == TIM4) || \
25225 ((INSTANCE) == TIM5) || \
25226 ((INSTANCE) == TIM8) || \
25227 ((INSTANCE) == TIM15) || \
25228 ((INSTANCE) == TIM16) || \
25229 ((INSTANCE) == TIM17))
25230
25231 /****************** TIM Instances : supporting commutation event *************/
25232 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25233 ((INSTANCE) == TIM8) || \
25234 ((INSTANCE) == TIM15) || \
25235 ((INSTANCE) == TIM16) || \
25236 ((INSTANCE) == TIM17))
25237
25238 /****************** TIM Instances : supporting encoder interface **************/
25239 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25240 ((__INSTANCE__) == TIM2) || \
25241 ((__INSTANCE__) == TIM3) || \
25242 ((__INSTANCE__) == TIM4) || \
25243 ((__INSTANCE__) == TIM5) || \
25244 ((__INSTANCE__) == TIM8))
25245
25246 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
25247 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25248 ((INSTANCE) == TIM8))
25249 /******************* TIM Instances : output(s) available **********************/
25250 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
25251 ((((INSTANCE) == TIM1) && \
25252 (((CHANNEL) == TIM_CHANNEL_1) || \
25253 ((CHANNEL) == TIM_CHANNEL_2) || \
25254 ((CHANNEL) == TIM_CHANNEL_3) || \
25255 ((CHANNEL) == TIM_CHANNEL_4) || \
25256 ((CHANNEL) == TIM_CHANNEL_5) || \
25257 ((CHANNEL) == TIM_CHANNEL_6))) \
25258 || \
25259 (((INSTANCE) == TIM2) && \
25260 (((CHANNEL) == TIM_CHANNEL_1) || \
25261 ((CHANNEL) == TIM_CHANNEL_2) || \
25262 ((CHANNEL) == TIM_CHANNEL_3) || \
25263 ((CHANNEL) == TIM_CHANNEL_4))) \
25264 || \
25265 (((INSTANCE) == TIM3) && \
25266 (((CHANNEL) == TIM_CHANNEL_1)|| \
25267 ((CHANNEL) == TIM_CHANNEL_2) || \
25268 ((CHANNEL) == TIM_CHANNEL_3) || \
25269 ((CHANNEL) == TIM_CHANNEL_4))) \
25270 || \
25271 (((INSTANCE) == TIM4) && \
25272 (((CHANNEL) == TIM_CHANNEL_1) || \
25273 ((CHANNEL) == TIM_CHANNEL_2) || \
25274 ((CHANNEL) == TIM_CHANNEL_3) || \
25275 ((CHANNEL) == TIM_CHANNEL_4))) \
25276 || \
25277 (((INSTANCE) == TIM5) && \
25278 (((CHANNEL) == TIM_CHANNEL_1) || \
25279 ((CHANNEL) == TIM_CHANNEL_2) || \
25280 ((CHANNEL) == TIM_CHANNEL_3) || \
25281 ((CHANNEL) == TIM_CHANNEL_4))) \
25282 || \
25283 (((INSTANCE) == TIM8) && \
25284 (((CHANNEL) == TIM_CHANNEL_1) || \
25285 ((CHANNEL) == TIM_CHANNEL_2) || \
25286 ((CHANNEL) == TIM_CHANNEL_3) || \
25287 ((CHANNEL) == TIM_CHANNEL_4) || \
25288 ((CHANNEL) == TIM_CHANNEL_5) || \
25289 ((CHANNEL) == TIM_CHANNEL_6))) \
25290 || \
25291 (((INSTANCE) == TIM12) && \
25292 (((CHANNEL) == TIM_CHANNEL_1) || \
25293 ((CHANNEL) == TIM_CHANNEL_2))) \
25294 || \
25295 (((INSTANCE) == TIM13) && \
25296 (((CHANNEL) == TIM_CHANNEL_1))) \
25297 || \
25298 (((INSTANCE) == TIM14) && \
25299 (((CHANNEL) == TIM_CHANNEL_1))) \
25300 || \
25301 (((INSTANCE) == TIM15) && \
25302 (((CHANNEL) == TIM_CHANNEL_1) || \
25303 ((CHANNEL) == TIM_CHANNEL_2))) \
25304 || \
25305 (((INSTANCE) == TIM16) && \
25306 (((CHANNEL) == TIM_CHANNEL_1))) \
25307 || \
25308 (((INSTANCE) == TIM17) && \
25309 (((CHANNEL) == TIM_CHANNEL_1))))
25310
25311 /****************** TIM Instances : supporting the break function *************/
25312 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
25313 (((INSTANCE) == TIM1) || \
25314 ((INSTANCE) == TIM8) || \
25315 ((INSTANCE) == TIM15) || \
25316 ((INSTANCE) == TIM16) || \
25317 ((INSTANCE) == TIM17))
25318
25319 /************** TIM Instances : supporting Break source selection *************/
25320 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
25321 ((INSTANCE) == TIM8))
25322
25323 /****************** TIM Instances : supporting complementary output(s) ********/
25324 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
25325 ((((INSTANCE) == TIM1) && \
25326 (((CHANNEL) == TIM_CHANNEL_1) || \
25327 ((CHANNEL) == TIM_CHANNEL_2) || \
25328 ((CHANNEL) == TIM_CHANNEL_3))) \
25329 || \
25330 (((INSTANCE) == TIM8) && \
25331 (((CHANNEL) == TIM_CHANNEL_1) || \
25332 ((CHANNEL) == TIM_CHANNEL_2) || \
25333 ((CHANNEL) == TIM_CHANNEL_3))) \
25334 || \
25335 (((INSTANCE) == TIM15) && \
25336 ((CHANNEL) == TIM_CHANNEL_1)) \
25337 || \
25338 (((INSTANCE) == TIM16) && \
25339 ((CHANNEL) == TIM_CHANNEL_1)) \
25340 || \
25341 (((INSTANCE) == TIM17) && \
25342 ((CHANNEL) == TIM_CHANNEL_1)))
25343
25344 /****************** TIM Instances : supporting counting mode selection ********/
25345 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
25346 (((INSTANCE) == TIM1) || \
25347 ((INSTANCE) == TIM2) || \
25348 ((INSTANCE) == TIM3) || \
25349 ((INSTANCE) == TIM4) || \
25350 ((INSTANCE) == TIM5) || \
25351 ((INSTANCE) == TIM8))
25352
25353 /****************** TIM Instances : supporting repetition counter *************/
25354 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
25355 (((INSTANCE) == TIM1) || \
25356 ((INSTANCE) == TIM8) || \
25357 ((INSTANCE) == TIM15) || \
25358 ((INSTANCE) == TIM16) || \
25359 ((INSTANCE) == TIM17))
25360
25361 /****************** TIM Instances : supporting synchronization ****************/
25362 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
25363 (((__INSTANCE__) == TIM1) || \
25364 ((__INSTANCE__) == TIM2) || \
25365 ((__INSTANCE__) == TIM3) || \
25366 ((__INSTANCE__) == TIM4) || \
25367 ((__INSTANCE__) == TIM5) || \
25368 ((__INSTANCE__) == TIM6) || \
25369 ((__INSTANCE__) == TIM8) || \
25370 ((__INSTANCE__) == TIM12) || \
25371 ((__INSTANCE__) == TIM15))
25372
25373 /****************** TIM Instances : supporting clock division *****************/
25374 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
25375 (((INSTANCE) == TIM1) || \
25376 ((INSTANCE) == TIM2) || \
25377 ((INSTANCE) == TIM3) || \
25378 ((INSTANCE) == TIM4) || \
25379 ((INSTANCE) == TIM5) || \
25380 ((INSTANCE) == TIM8) || \
25381 ((INSTANCE) == TIM15) || \
25382 ((INSTANCE) == TIM16) || \
25383 ((INSTANCE) == TIM17))
25384
25385 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
25386 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
25387 (((INSTANCE) == TIM1) || \
25388 ((INSTANCE) == TIM2) || \
25389 ((INSTANCE) == TIM3) || \
25390 ((INSTANCE) == TIM4) || \
25391 ((INSTANCE) == TIM5) || \
25392 ((INSTANCE) == TIM8))
25393
25394 /****************** TIM Instances : supporting external clock mode 2 **********/
25395 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
25396 (((INSTANCE) == TIM1) || \
25397 ((INSTANCE) == TIM2) || \
25398 ((INSTANCE) == TIM3) || \
25399 ((INSTANCE) == TIM4) || \
25400 ((INSTANCE) == TIM5) || \
25401 ((INSTANCE) == TIM8))
25402
25403 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
25404 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
25405 (((INSTANCE) == TIM1) || \
25406 ((INSTANCE) == TIM2) || \
25407 ((INSTANCE) == TIM3) || \
25408 ((INSTANCE) == TIM4) || \
25409 ((INSTANCE) == TIM5) || \
25410 ((INSTANCE) == TIM8) || \
25411 ((INSTANCE) == TIM15))
25412
25413 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
25414 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
25415 (((INSTANCE) == TIM1) || \
25416 ((INSTANCE) == TIM2) || \
25417 ((INSTANCE) == TIM3) || \
25418 ((INSTANCE) == TIM4) || \
25419 ((INSTANCE) == TIM5) || \
25420 ((INSTANCE) == TIM8) || \
25421 ((INSTANCE) == TIM15))
25422
25423 /****************** TIM Instances : supporting OCxREF clear *******************/
25424 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
25425 (((INSTANCE) == TIM1) || \
25426 ((INSTANCE) == TIM2) || \
25427 ((INSTANCE) == TIM3))
25428
25429 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
25430 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
25431 (((INSTANCE) == TIM2) || \
25432 ((INSTANCE) == TIM5))
25433
25434 /****************** TIM Instances : TIM_BKIN2 ***************************/
25435 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
25436 (((INSTANCE) == TIM1) || \
25437 ((INSTANCE) == TIM8))
25438
25439 /****************** TIM Instances : supporting Hall sensor interface **********/
25440 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
25441 ((__INSTANCE__) == TIM2) || \
25442 ((__INSTANCE__) == TIM3) || \
25443 ((__INSTANCE__) == TIM4) || \
25444 ((__INSTANCE__) == TIM5) || \
25445 ((__INSTANCE__) == TIM15) || \
25446 ((__INSTANCE__) == TIM8))
25447
25448 /****************************** HRTIM Instances *******************************/
25449 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
25450
25451 /******************** USART Instances : Synchronous mode **********************/
25452 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25453 ((INSTANCE) == USART2) || \
25454 ((INSTANCE) == USART3) || \
25455 ((INSTANCE) == USART6))
25456
25457 /******************** USART Instances : SPI slave mode ************************/
25458 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25459 ((INSTANCE) == USART2) || \
25460 ((INSTANCE) == USART3) || \
25461 ((INSTANCE) == USART6))
25462
25463 /******************** UART Instances : Asynchronous mode **********************/
25464 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25465 ((INSTANCE) == USART2) || \
25466 ((INSTANCE) == USART3) || \
25467 ((INSTANCE) == UART4) || \
25468 ((INSTANCE) == UART5) || \
25469 ((INSTANCE) == USART6) || \
25470 ((INSTANCE) == UART7) || \
25471 ((INSTANCE) == UART8))
25472
25473 /******************** UART Instances : FIFO mode.******************************/
25474 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25475 ((INSTANCE) == USART2) || \
25476 ((INSTANCE) == USART3) || \
25477 ((INSTANCE) == UART4) || \
25478 ((INSTANCE) == UART5) || \
25479 ((INSTANCE) == USART6) || \
25480 ((INSTANCE) == UART7) || \
25481 ((INSTANCE) == UART8))
25482
25483 /****************** UART Instances : Auto Baud Rate detection *****************/
25484 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25485 ((INSTANCE) == USART2) || \
25486 ((INSTANCE) == USART3) || \
25487 ((INSTANCE) == UART4) || \
25488 ((INSTANCE) == UART5) || \
25489 ((INSTANCE) == USART6) || \
25490 ((INSTANCE) == UART7) || \
25491 ((INSTANCE) == UART8))
25492
25493 /*********************** UART Instances : Driver Enable ***********************/
25494 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25495 ((INSTANCE) == USART2) || \
25496 ((INSTANCE) == USART3) || \
25497 ((INSTANCE) == UART4) || \
25498 ((INSTANCE) == UART5) || \
25499 ((INSTANCE) == USART6) || \
25500 ((INSTANCE) == UART7) || \
25501 ((INSTANCE) == UART8) || \
25502 ((INSTANCE) == LPUART1))
25503
25504 /********************* UART Instances : Half-Duplex mode **********************/
25505 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25506 ((INSTANCE) == USART2) || \
25507 ((INSTANCE) == USART3) || \
25508 ((INSTANCE) == UART4) || \
25509 ((INSTANCE) == UART5) || \
25510 ((INSTANCE) == USART6) || \
25511 ((INSTANCE) == UART7) || \
25512 ((INSTANCE) == UART8) || \
25513 ((INSTANCE) == LPUART1))
25514
25515 /******************* UART Instances : Hardware Flow control *******************/
25516 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25517 ((INSTANCE) == USART2) || \
25518 ((INSTANCE) == USART3) || \
25519 ((INSTANCE) == UART4) || \
25520 ((INSTANCE) == UART5) || \
25521 ((INSTANCE) == USART6) || \
25522 ((INSTANCE) == UART7) || \
25523 ((INSTANCE) == UART8) || \
25524 ((INSTANCE) == LPUART1))
25525
25526 /************************* UART Instances : LIN mode **************************/
25527 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25528 ((INSTANCE) == USART2) || \
25529 ((INSTANCE) == USART3) || \
25530 ((INSTANCE) == UART4) || \
25531 ((INSTANCE) == UART5) || \
25532 ((INSTANCE) == USART6) || \
25533 ((INSTANCE) == UART7) || \
25534 ((INSTANCE) == UART8))
25535
25536 /****************** UART Instances : Wake-up from Stop mode *******************/
25537 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25538 ((INSTANCE) == USART2) || \
25539 ((INSTANCE) == USART3) || \
25540 ((INSTANCE) == UART4) || \
25541 ((INSTANCE) == UART5) || \
25542 ((INSTANCE) == USART6) || \
25543 ((INSTANCE) == UART7) || \
25544 ((INSTANCE) == UART8) || \
25545 ((INSTANCE) == LPUART1))
25546
25547 /************************* UART Instances : IRDA mode *************************/
25548 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25549 ((INSTANCE) == USART2) || \
25550 ((INSTANCE) == USART3) || \
25551 ((INSTANCE) == UART4) || \
25552 ((INSTANCE) == UART5) || \
25553 ((INSTANCE) == USART6) || \
25554 ((INSTANCE) == UART7) || \
25555 ((INSTANCE) == UART8))
25556
25557 /********************* USART Instances : Smard card mode **********************/
25558 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
25559 ((INSTANCE) == USART2) || \
25560 ((INSTANCE) == USART3) || \
25561 ((INSTANCE) == USART6))
25562
25563 /****************************** LPUART Instance *******************************/
25564 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
25565
25566 /****************************** IWDG Instances ********************************/
25567 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
25568 /****************************** USB Instances ********************************/
25569 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
25570
25571 /****************************** WWDG Instances ********************************/
25572 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
25573 /****************************** MDIOS Instances ********************************/
25574 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
25575
25576 /****************************** CEC Instances *********************************/
25577 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
25578
25579 /****************************** SAI Instances ********************************/
25580 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
25581 ((INSTANCE) == SAI1_Block_B) || \
25582 ((INSTANCE) == SAI2_Block_A) || \
25583 ((INSTANCE) == SAI2_Block_B) || \
25584 ((INSTANCE) == SAI3_Block_A) || \
25585 ((INSTANCE) == SAI3_Block_B) || \
25586 ((INSTANCE) == SAI4_Block_A) || \
25587 ((INSTANCE) == SAI4_Block_B))
25588
25589 /****************************** SPDIFRX Instances ********************************/
25590 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
25591
25592 /****************************** OPAMP Instances *******************************/
25593 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
25594 ((INSTANCE) == OPAMP2))
25595
25596 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
25597
25598 /*********************** USB OTG PCD Instances ********************************/
25599 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
25600 ((INSTANCE) == USB_OTG_HS))
25601
25602 /*********************** USB OTG HCD Instances ********************************/
25603 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
25604 ((INSTANCE) == USB_OTG_HS))
25605
25606 /******************************************************************************/
25607 /* For a painless codes migration between the STM32H7xx device product */
25608 /* lines, or with STM32F7xx devices the aliases defined below are put */
25609 /* in place to overcome the differences in the interrupt handlers and IRQn */
25610 /* definitions. No need to update developed interrupt code when moving */
25611 /* across product lines within the same STM32H7 Family */
25612 /******************************************************************************/
25613
25614 /* Aliases for __IRQn */
25615 #define HASH_RNG_IRQn RNG_IRQn
25616 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
25617 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
25618 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
25619 #define PVD_IRQn PVD_AVD_IRQn
25620
25621
25622
25623 /* Aliases for __IRQHandler */
25624 #define HASH_RNG_IRQHandler RNG_IRQHandler
25625 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
25626 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
25627 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
25628 #define PVD_IRQHandler PVD_AVD_IRQHandler
25629
25630 /* Aliases for COMP __IRQHandler */
25631 #define COMP_IRQHandler COMP1_IRQHandler
25632
25633 /**
25634 * @}
25635 */
25636
25637 /**
25638 * @}
25639 */
25640
25641 /**
25642 * @}
25643 */
25644
25645 #ifdef __cplusplus
25646 }
25647 #endif /* __cplusplus */
25648
25649 #endif /* STM32H742xx_H */
25650
25651 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software