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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / CMSIS / Device / ST / STM32H7xx / Include / stm32h747xx.h
blobee6ff5338e6427cd455c65652ca24fe705981b46
1 /**
2 ******************************************************************************
3 * @file stm32h747xx.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H747xx Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32h747xx
31 * @{
32 */
33
34 #ifndef STM32H747xx_H
35 #define STM32H747xx_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45 /**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49 typedef enum
50 {
51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_AVD_IRQn = 1, /*!< PVD/AVD through EXTI Line detection Interrupt */
64 TAMP_STAMP_IRQn = 2, /*!< Tamper and TimeStamp interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
105 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
106 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
107 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
108 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
109 FMC_IRQn = 48, /*!< FMC global Interrupt */
110 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
111 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
112 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
113 UART4_IRQn = 52, /*!< UART4 global Interrupt */
114 UART5_IRQn = 53, /*!< UART5 global Interrupt */
115 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
116 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
117 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
118 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
119 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
120 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
121 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
122 ETH_IRQn = 61, /*!< Ethernet global Interrupt */
123 ETH_WKUP_IRQn = 62, /*!< Ethernet Wakeup through EXTI line Interrupt */
124 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
125 CM7_SEV_IRQn = 64, /*!< CM7 Send event interrupt for CM4 */
126 CM4_SEV_IRQn = 65, /*!< CM4 Send event interrupt for CM7 */
127 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
128 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
129 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
130 USART6_IRQn = 71, /*!< USART6 global interrupt */
131 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
132 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
133 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
134 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
135 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
136 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
137 DCMI_IRQn = 78, /*!< DCMI global interrupt */
138 RNG_IRQn = 80, /*!< RNG global interrupt */
139 FPU_IRQn = 81, /*!< FPU global interrupt */
140 UART7_IRQn = 82, /*!< UART7 global interrupt */
141 UART8_IRQn = 83, /*!< UART8 global interrupt */
142 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
143 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
144 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
145 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
146 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
147 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
148 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
149 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
150 QUADSPI_IRQn = 92, /*!< Quad SPI global interrupt */
151 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
152 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
153 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
154 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
155 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
156 OTG_FS_EP1_OUT_IRQn = 98, /*!< USB OTG HS2 global interrupt */
157 OTG_FS_EP1_IN_IRQn = 99, /*!< USB OTG HS2 End Point 1 Out global interrupt */
158 OTG_FS_WKUP_IRQn = 100, /*!< USB OTG HS2 End Point 1 In global interrupt */
159 OTG_FS_IRQn = 101, /*!< USB OTG HS2 Wakeup through EXTI interrupt */
160 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
161 HRTIM1_Master_IRQn = 103, /*!< HRTIM Master Timer global Interrupts */
162 HRTIM1_TIMA_IRQn = 104, /*!< HRTIM Timer A global Interrupt */
163 HRTIM1_TIMB_IRQn = 105, /*!< HRTIM Timer B global Interrupt */
164 HRTIM1_TIMC_IRQn = 106, /*!< HRTIM Timer C global Interrupt */
165 HRTIM1_TIMD_IRQn = 107, /*!< HRTIM Timer D global Interrupt */
166 HRTIM1_TIME_IRQn = 108, /*!< HRTIM Timer E global Interrupt */
167 HRTIM1_FLT_IRQn = 109, /*!< HRTIM Fault global Interrupt */
168 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
169 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
170 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
171 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
172 SAI3_IRQn = 114, /*!< SAI3 global Interrupt */
173 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
174 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
175 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
176 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
177 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
178 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
179 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
180 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
181 DSI_IRQn = 123, /*!< DSI global Interrupt */
182 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
183 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
184 HSEM2_IRQn = 126, /*!< HSEM2 global Interrupt */
185 ADC3_IRQn = 127, /*!< ADC3 global Interrupt */
186 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
187 BDMA_Channel0_IRQn = 129, /*!< BDMA Channel 0 global Interrupt */
188 BDMA_Channel1_IRQn = 130, /*!< BDMA Channel 1 global Interrupt */
189 BDMA_Channel2_IRQn = 131, /*!< BDMA Channel 2 global Interrupt */
190 BDMA_Channel3_IRQn = 132, /*!< BDMA Channel 3 global Interrupt */
191 BDMA_Channel4_IRQn = 133, /*!< BDMA Channel 4 global Interrupt */
192 BDMA_Channel5_IRQn = 134, /*!< BDMA Channel 5 global Interrupt */
193 BDMA_Channel6_IRQn = 135, /*!< BDMA Channel 6 global Interrupt */
194 BDMA_Channel7_IRQn = 136, /*!< BDMA Channel 7 global Interrupt */
195 COMP_IRQn = 137 , /*!< COMP global Interrupt */
196 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
197 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
198 LPTIM4_IRQn = 140, /*!< LP TIM4 global interrupt */
199 LPTIM5_IRQn = 141, /*!< LP TIM5 global interrupt */
200 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
201 WWDG_RST_IRQn = 143, /*!<Window Watchdog reset interrupt (exti_d2_wwdg_it, exti_d1_wwdg_it) */
202 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
203 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
204 SAI4_IRQn = 146, /*!< SAI4 global interrupt */
205 HOLD_CORE_IRQn = 148, /*!< Hold core interrupt */
206 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
207 } IRQn_Type;
208
209 /**
210 * @}
211 */
212
213 /** @addtogroup Configuration_section_for_CMSIS
214 * @{
215 */
216 #define DUAL_CORE /*!< Dual core line feature */
217
218 #define SMPS /*!< Switched mode power supply feature */
219
220
221
222 /**
223 * @brief Configuration of the Cortex-M4/ Cortex-M7 Processor and Core Peripherals
224 */
225 #ifdef CORE_CM4
226 #define __CM4_REV 0x0001 /*!< Cortex-M4 revision r0p1 */
227 #define __MPU_PRESENT 1 /*!< CM4 provides an MPU */
228 #define __NVIC_PRIO_BITS 4 /*!< CM4 uses 4 Bits for the Priority Levels */
229 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
230 #define __FPU_PRESENT 1 /*!< FPU present */
231
232 #include "core_cm4.h" /*!< Cortex-M4 processor and core peripherals */
233 #else /* CORE_CM7 */
234 #ifdef CORE_CM7
235 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
236 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
237 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
238 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
239 #define __FPU_PRESENT 1 /*!< FPU present */
240 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
241 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
242 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
243 #else /* UNKNOWN_CORE */
244 #error Please #define CORE_CM4 or CORE_CM7
245 #endif /* CORE_CM7 */
246 #endif /* CORE_CM4 */
247
248 /**
249 * @}
250 */
251
252
253
254
255
256 #include "system_stm32h7xx.h"
257 #include <stdint.h>
258
259 /** @addtogroup Peripheral_registers_structures
260 * @{
261 */
262
263 /**
264 * @brief Analog to Digital Converter
265 */
266
267 typedef struct
268 {
269 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
270 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
271 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
272 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
273 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
274 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
275 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
276 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
277 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
278 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
279 uint32_t RESERVED1; /*!< Reserved, 0x028 */
280 uint32_t RESERVED2; /*!< Reserved, 0x02C */
281 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
282 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
283 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
284 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
285 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
286 uint32_t RESERVED3; /*!< Reserved, 0x044 */
287 uint32_t RESERVED4; /*!< Reserved, 0x048 */
288 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
289 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
290 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
291 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
292 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
293 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
294 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
295 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
296 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
297 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
298 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
299 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
300 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
301 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
302 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
303 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
304 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
305 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
306 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
307 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
308 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
309 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
310 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
311 } ADC_TypeDef;
312
313
314 typedef struct
315 {
316 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
317 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
318 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
319 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
320 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
321
322 } ADC_Common_TypeDef;
323
324 /**
325 * @brief ART
326 */
327
328 typedef struct
329 {
330 __IO uint32_t CTR; /*!< ART accelerator - control register */
331 }ART_TypeDef;
332
333 /**
334 * @brief VREFBUF
335 */
336
337 typedef struct
338 {
339 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
340 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
341 } VREFBUF_TypeDef;
342
343
344 /**
345 * @brief FD Controller Area Network
346 */
347
348 typedef struct
349 {
350 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
351 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
352 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
353 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
354 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
355 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
356 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
357 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
358 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
359 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
360 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
361 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
362 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
363 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
364 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
365 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
366 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
367 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
368 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
369 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
370 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
371 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
372 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
373 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
374 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
375 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
376 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
377 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
378 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
379 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
380 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
381 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
382 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
383 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
384 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
385 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
386 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
387 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
388 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
389 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
390 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
391 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
392 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
393 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
394 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
395 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
396 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
397 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
398 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
399 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
400 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
401 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
402 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
403 } FDCAN_GlobalTypeDef;
404
405 /**
406 * @brief TTFD Controller Area Network
407 */
408
409 typedef struct
410 {
411 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
412 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
413 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
414 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
415 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
416 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
417 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
418 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
419 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
420 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
421 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
422 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
423 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
424 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
425 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
426 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
427 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
428 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
429 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
430 } TTCAN_TypeDef;
431
432 /**
433 * @brief FD Controller Area Network
434 */
435
436 typedef struct
437 {
438 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
439 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
440 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
441 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
442 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
443 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
444 } FDCAN_ClockCalibrationUnit_TypeDef;
445
446
447 /**
448 * @brief Consumer Electronics Control
449 */
450
451 typedef struct
452 {
453 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
454 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
455 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
456 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
457 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
458 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
459 }CEC_TypeDef;
460
461 /**
462 * @brief CRC calculation unit
463 */
464
465 typedef struct
466 {
467 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
468 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
469 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
470 uint32_t RESERVED2; /*!< Reserved, 0x0C */
471 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
472 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
473 } CRC_TypeDef;
474
475
476 /**
477 * @brief Clock Recovery System
478 */
479 typedef struct
480 {
481 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
482 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
483 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
484 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
485 } CRS_TypeDef;
486
487
488 /**
489 * @brief Digital to Analog Converter
490 */
491
492 typedef struct
493 {
494 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
495 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
496 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
497 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
498 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
499 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
500 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
501 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
502 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
503 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
504 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
505 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
506 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
507 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
508 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
509 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
510 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
511 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
512 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
513 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
514 } DAC_TypeDef;
515
516 /**
517 * @brief DFSDM module registers
518 */
519 typedef struct
520 {
521 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
522 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
523 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
524 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
525 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
526 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
527 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
528 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
529 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
530 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
531 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
532 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
533 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
534 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
535 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
536 } DFSDM_Filter_TypeDef;
537
538 /**
539 * @brief DFSDM channel configuration registers
540 */
541 typedef struct
542 {
543 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
544 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
545 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
546 short circuit detector register, Address offset: 0x08 */
547 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
548 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
549 } DFSDM_Channel_TypeDef;
550
551 /**
552 * @brief Debug MCU
553 */
554 typedef struct
555 {
556 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
557 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
558 __IO uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
559 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
560 __IO uint32_t APB3FZ2; /*!< Debug MCU APB3FZ2 freeze register, Address offset: 0x38 */
561 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
562 __IO uint32_t APB1LFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x40 */
563 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
564 __IO uint32_t APB1HFZ2; /*!< Debug MCU APB1LFZ2 freeze register, Address offset: 0x48 */
565 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
566 __IO uint32_t APB2FZ2; /*!< Debug MCU APB2FZ2 freeze register, Address offset: 0x50 */
567 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
568 __IO uint32_t APB4FZ2; /*!< Debug MCU APB4FZ2 freeze register, Address offset: 0x58 */
569
570 }DBGMCU_TypeDef;
571 /**
572 * @brief DCMI
573 */
574
575 typedef struct
576 {
577 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
578 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
579 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
580 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
581 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
582 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
583 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
584 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
585 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
586 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
587 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
588 } DCMI_TypeDef;
589
590 /**
591 * @brief DMA Controller
592 */
593
594 typedef struct
595 {
596 __IO uint32_t CR; /*!< DMA stream x configuration register */
597 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
598 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
599 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
600 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
601 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
602 } DMA_Stream_TypeDef;
603
604 typedef struct
605 {
606 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
607 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
608 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
609 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
610 } DMA_TypeDef;
611
612 typedef struct
613 {
614 __IO uint32_t CCR; /*!< DMA channel x configuration register */
615 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
616 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
617 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
618 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
619 } BDMA_Channel_TypeDef;
620
621 typedef struct
622 {
623 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
624 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
625 } BDMA_TypeDef;
626
627 typedef struct
628 {
629 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
630 }DMAMUX_Channel_TypeDef;
631
632 typedef struct
633 {
634 __IO uint32_t CSR; /*!< DMA Channel Status Register */
635 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
636 }DMAMUX_ChannelStatus_TypeDef;
637
638 typedef struct
639 {
640 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
641 }DMAMUX_RequestGen_TypeDef;
642
643 typedef struct
644 {
645 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
646 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
647 }DMAMUX_RequestGenStatus_TypeDef;
648
649 /**
650 * @brief MDMA Controller
651 */
652 typedef struct
653 {
654 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
655 }MDMA_TypeDef;
656
657 typedef struct
658 {
659 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
660 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
661 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
662 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
663 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
664 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
665 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
666 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
667 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
668 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
669 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
670 uint32_t RESERVED0; /*!< Reserved, 0x68 */
671 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
672 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
673 }MDMA_Channel_TypeDef;
674
675 /**
676 * @brief DMA2D Controller
677 */
678
679 typedef struct
680 {
681 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
682 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
683 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
684 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
685 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
686 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
687 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
688 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
689 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
690 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
691 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
692 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
693 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
694 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
695 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
696 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
697 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
698 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
699 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
700 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
701 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
702 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
703 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
704 } DMA2D_TypeDef;
705
706 /**
707 * @brief DSI Controller
708 */
709
710 typedef struct
711 {
712 __IO uint32_t VR; /*!< DSI Host Version Register, Address offset: 0x00 */
713 __IO uint32_t CR; /*!< DSI Host Control Register, Address offset: 0x04 */
714 __IO uint32_t CCR; /*!< DSI HOST Clock Control Register, Address offset: 0x08 */
715 __IO uint32_t LVCIDR; /*!< DSI Host LTDC VCID Register, Address offset: 0x0C */
716 __IO uint32_t LCOLCR; /*!< DSI Host LTDC Color Coding Register, Address offset: 0x10 */
717 __IO uint32_t LPCR; /*!< DSI Host LTDC Polarity Configuration Register, Address offset: 0x14 */
718 __IO uint32_t LPMCR; /*!< DSI Host Low-Power Mode Configuration Register, Address offset: 0x18 */
719 uint32_t RESERVED0[4]; /*!< Reserved, 0x1C - 0x2B */
720 __IO uint32_t PCR; /*!< DSI Host Protocol Configuration Register, Address offset: 0x2C */
721 __IO uint32_t GVCIDR; /*!< DSI Host Generic VCID Register, Address offset: 0x30 */
722 __IO uint32_t MCR; /*!< DSI Host Mode Configuration Register, Address offset: 0x34 */
723 __IO uint32_t VMCR; /*!< DSI Host Video Mode Configuration Register, Address offset: 0x38 */
724 __IO uint32_t VPCR; /*!< DSI Host Video Packet Configuration Register, Address offset: 0x3C */
725 __IO uint32_t VCCR; /*!< DSI Host Video Chunks Configuration Register, Address offset: 0x40 */
726 __IO uint32_t VNPCR; /*!< DSI Host Video Null Packet Configuration Register, Address offset: 0x44 */
727 __IO uint32_t VHSACR; /*!< DSI Host Video HSA Configuration Register, Address offset: 0x48 */
728 __IO uint32_t VHBPCR; /*!< DSI Host Video HBP Configuration Register, Address offset: 0x4C */
729 __IO uint32_t VLCR; /*!< DSI Host Video Line Configuration Register, Address offset: 0x50 */
730 __IO uint32_t VVSACR; /*!< DSI Host Video VSA Configuration Register, Address offset: 0x54 */
731 __IO uint32_t VVBPCR; /*!< DSI Host Video VBP Configuration Register, Address offset: 0x58 */
732 __IO uint32_t VVFPCR; /*!< DSI Host Video VFP Configuration Register, Address offset: 0x5C */
733 __IO uint32_t VVACR; /*!< DSI Host Video VA Configuration Register, Address offset: 0x60 */
734 __IO uint32_t LCCR; /*!< DSI Host LTDC Command Configuration Register, Address offset: 0x64 */
735 __IO uint32_t CMCR; /*!< DSI Host Command Mode Configuration Register, Address offset: 0x68 */
736 __IO uint32_t GHCR; /*!< DSI Host Generic Header Configuration Register, Address offset: 0x6C */
737 __IO uint32_t GPDR; /*!< DSI Host Generic Payload Data Register, Address offset: 0x70 */
738 __IO uint32_t GPSR; /*!< DSI Host Generic Packet Status Register, Address offset: 0x74 */
739 __IO uint32_t TCCR[6]; /*!< DSI Host Timeout Counter Configuration Register, Address offset: 0x78-0x8F */
740 __IO uint32_t TDCR; /*!< DSI Host 3D Configuration Register, Address offset: 0x90 */
741 __IO uint32_t CLCR; /*!< DSI Host Clock Lane Configuration Register, Address offset: 0x94 */
742 __IO uint32_t CLTCR; /*!< DSI Host Clock Lane Timer Configuration Register, Address offset: 0x98 */
743 __IO uint32_t DLTCR; /*!< DSI Host Data Lane Timer Configuration Register, Address offset: 0x9C */
744 __IO uint32_t PCTLR; /*!< DSI Host PHY Control Register, Address offset: 0xA0 */
745 __IO uint32_t PCONFR; /*!< DSI Host PHY Configuration Register, Address offset: 0xA4 */
746 __IO uint32_t PUCR; /*!< DSI Host PHY ULPS Control Register, Address offset: 0xA8 */
747 __IO uint32_t PTTCR; /*!< DSI Host PHY TX Triggers Configuration Register, Address offset: 0xAC */
748 __IO uint32_t PSR; /*!< DSI Host PHY Status Register, Address offset: 0xB0 */
749 uint32_t RESERVED1[2]; /*!< Reserved, 0xB4 - 0xBB */
750 __IO uint32_t ISR[2]; /*!< DSI Host Interrupt & Status Register, Address offset: 0xBC-0xC3 */
751 __IO uint32_t IER[2]; /*!< DSI Host Interrupt Enable Register, Address offset: 0xC4-0xCB */
752 uint32_t RESERVED2[3]; /*!< Reserved, 0xD0 - 0xD7 */
753 __IO uint32_t FIR[2]; /*!< DSI Host Force Interrupt Register, Address offset: 0xD8-0xDF */
754 uint32_t RESERVED3[8]; /*!< Reserved, 0xE0 - 0xFF */
755 __IO uint32_t VSCR; /*!< DSI Host Video Shadow Control Register, Address offset: 0x100 */
756 uint32_t RESERVED4[2]; /*!< Reserved, 0x104 - 0x10B */
757 __IO uint32_t LCVCIDR; /*!< DSI Host LTDC Current VCID Register, Address offset: 0x10C */
758 __IO uint32_t LCCCR; /*!< DSI Host LTDC Current Color Coding Register, Address offset: 0x110 */
759 uint32_t RESERVED5; /*!< Reserved, 0x114 */
760 __IO uint32_t LPMCCR; /*!< DSI Host Low-power Mode Current Configuration Register, Address offset: 0x118 */
761 uint32_t RESERVED6[7]; /*!< Reserved, 0x11C - 0x137 */
762 __IO uint32_t VMCCR; /*!< DSI Host Video Mode Current Configuration Register, Address offset: 0x138 */
763 __IO uint32_t VPCCR; /*!< DSI Host Video Packet Current Configuration Register, Address offset: 0x13C */
764 __IO uint32_t VCCCR; /*!< DSI Host Video Chuncks Current Configuration Register, Address offset: 0x140 */
765 __IO uint32_t VNPCCR; /*!< DSI Host Video Null Packet Current Configuration Register, Address offset: 0x144 */
766 __IO uint32_t VHSACCR; /*!< DSI Host Video HSA Current Configuration Register, Address offset: 0x148 */
767 __IO uint32_t VHBPCCR; /*!< DSI Host Video HBP Current Configuration Register, Address offset: 0x14C */
768 __IO uint32_t VLCCR; /*!< DSI Host Video Line Current Configuration Register, Address offset: 0x150 */
769 __IO uint32_t VVSACCR; /*!< DSI Host Video VSA Current Configuration Register, Address offset: 0x154 */
770 __IO uint32_t VVBPCCR; /*!< DSI Host Video VBP Current Configuration Register, Address offset: 0x158 */
771 __IO uint32_t VVFPCCR; /*!< DSI Host Video VFP Current Configuration Register, Address offset: 0x15C */
772 __IO uint32_t VVACCR; /*!< DSI Host Video VA Current Configuration Register, Address offset: 0x160 */
773 uint32_t RESERVED7[11]; /*!< Reserved, 0x164 - 0x18F */
774 __IO uint32_t TDCCR; /*!< DSI Host 3D Current Configuration Register, Address offset: 0x190 */
775 uint32_t RESERVED8[155]; /*!< Reserved, 0x194 - 0x3FF */
776 __IO uint32_t WCFGR; /*!< DSI Wrapper Configuration Register, Address offset: 0x400 */
777 __IO uint32_t WCR; /*!< DSI Wrapper Control Register, Address offset: 0x404 */
778 __IO uint32_t WIER; /*!< DSI Wrapper Interrupt Enable Register, Address offset: 0x408 */
779 __IO uint32_t WISR; /*!< DSI Wrapper Interrupt and Status Register, Address offset: 0x40C */
780 __IO uint32_t WIFCR; /*!< DSI Wrapper Interrupt Flag Clear Register, Address offset: 0x410 */
781 uint32_t RESERVED9; /*!< Reserved, 0x414 */
782 __IO uint32_t WPCR[5]; /*!< DSI Wrapper PHY Configuration Register, Address offset: 0x418-0x42B */
783 uint32_t RESERVED10; /*!< Reserved, 0x42C */
784 __IO uint32_t WRPCR; /*!< DSI Wrapper Regulator and PLL Control Register, Address offset: 0x430 */
785 } DSI_TypeDef;
786
787 /**
788 * @brief Ethernet MAC
789 */
790 typedef struct
791 {
792 __IO uint32_t MACCR;
793 __IO uint32_t MACECR;
794 __IO uint32_t MACPFR;
795 __IO uint32_t MACWTR;
796 __IO uint32_t MACHT0R;
797 __IO uint32_t MACHT1R;
798 uint32_t RESERVED1[14];
799 __IO uint32_t MACVTR;
800 uint32_t RESERVED2;
801 __IO uint32_t MACVHTR;
802 uint32_t RESERVED3;
803 __IO uint32_t MACVIR;
804 __IO uint32_t MACIVIR;
805 uint32_t RESERVED4[2];
806 __IO uint32_t MACTFCR;
807 uint32_t RESERVED5[7];
808 __IO uint32_t MACRFCR;
809 uint32_t RESERVED6[7];
810 __IO uint32_t MACISR;
811 __IO uint32_t MACIER;
812 __IO uint32_t MACRXTXSR;
813 uint32_t RESERVED7;
814 __IO uint32_t MACPCSR;
815 __IO uint32_t MACRWKPFR;
816 uint32_t RESERVED8[2];
817 __IO uint32_t MACLCSR;
818 __IO uint32_t MACLTCR;
819 __IO uint32_t MACLETR;
820 __IO uint32_t MAC1USTCR;
821 uint32_t RESERVED9[12];
822 __IO uint32_t MACVR;
823 __IO uint32_t MACDR;
824 uint32_t RESERVED10;
825 __IO uint32_t MACHWF0R;
826 __IO uint32_t MACHWF1R;
827 __IO uint32_t MACHWF2R;
828 uint32_t RESERVED11[54];
829 __IO uint32_t MACMDIOAR;
830 __IO uint32_t MACMDIODR;
831 uint32_t RESERVED12[2];
832 __IO uint32_t MACARPAR;
833 uint32_t RESERVED13[59];
834 __IO uint32_t MACA0HR;
835 __IO uint32_t MACA0LR;
836 __IO uint32_t MACA1HR;
837 __IO uint32_t MACA1LR;
838 __IO uint32_t MACA2HR;
839 __IO uint32_t MACA2LR;
840 __IO uint32_t MACA3HR;
841 __IO uint32_t MACA3LR;
842 uint32_t RESERVED14[248];
843 __IO uint32_t MMCCR;
844 __IO uint32_t MMCRIR;
845 __IO uint32_t MMCTIR;
846 __IO uint32_t MMCRIMR;
847 __IO uint32_t MMCTIMR;
848 uint32_t RESERVED15[14];
849 __IO uint32_t MMCTSCGPR;
850 __IO uint32_t MMCTMCGPR;
851 uint32_t RESERVED16[5];
852 __IO uint32_t MMCTPCGR;
853 uint32_t RESERVED17[10];
854 __IO uint32_t MMCRCRCEPR;
855 __IO uint32_t MMCRAEPR;
856 uint32_t RESERVED18[10];
857 __IO uint32_t MMCRUPGR;
858 uint32_t RESERVED19[9];
859 __IO uint32_t MMCTLPIMSTR;
860 __IO uint32_t MMCTLPITCR;
861 __IO uint32_t MMCRLPIMSTR;
862 __IO uint32_t MMCRLPITCR;
863 uint32_t RESERVED20[65];
864 __IO uint32_t MACL3L4C0R;
865 __IO uint32_t MACL4A0R;
866 uint32_t RESERVED21[2];
867 __IO uint32_t MACL3A0R0R;
868 __IO uint32_t MACL3A1R0R;
869 __IO uint32_t MACL3A2R0R;
870 __IO uint32_t MACL3A3R0R;
871 uint32_t RESERVED22[4];
872 __IO uint32_t MACL3L4C1R;
873 __IO uint32_t MACL4A1R;
874 uint32_t RESERVED23[2];
875 __IO uint32_t MACL3A0R1R;
876 __IO uint32_t MACL3A1R1R;
877 __IO uint32_t MACL3A2R1R;
878 __IO uint32_t MACL3A3R1R;
879 uint32_t RESERVED24[108];
880 __IO uint32_t MACTSCR;
881 __IO uint32_t MACSSIR;
882 __IO uint32_t MACSTSR;
883 __IO uint32_t MACSTNR;
884 __IO uint32_t MACSTSUR;
885 __IO uint32_t MACSTNUR;
886 __IO uint32_t MACTSAR;
887 uint32_t RESERVED25;
888 __IO uint32_t MACTSSR;
889 uint32_t RESERVED26[3];
890 __IO uint32_t MACTTSSNR;
891 __IO uint32_t MACTTSSSR;
892 uint32_t RESERVED27[2];
893 __IO uint32_t MACACR;
894 uint32_t RESERVED28;
895 __IO uint32_t MACATSNR;
896 __IO uint32_t MACATSSR;
897 __IO uint32_t MACTSIACR;
898 __IO uint32_t MACTSEACR;
899 __IO uint32_t MACTSICNR;
900 __IO uint32_t MACTSECNR;
901 uint32_t RESERVED29[4];
902 __IO uint32_t MACPPSCR;
903 uint32_t RESERVED30[3];
904 __IO uint32_t MACPPSTTSR;
905 __IO uint32_t MACPPSTTNR;
906 __IO uint32_t MACPPSIR;
907 __IO uint32_t MACPPSWR;
908 uint32_t RESERVED31[12];
909 __IO uint32_t MACPOCR;
910 __IO uint32_t MACSPI0R;
911 __IO uint32_t MACSPI1R;
912 __IO uint32_t MACSPI2R;
913 __IO uint32_t MACLMIR;
914 uint32_t RESERVED32[11];
915 __IO uint32_t MTLOMR;
916 uint32_t RESERVED33[7];
917 __IO uint32_t MTLISR;
918 uint32_t RESERVED34[55];
919 __IO uint32_t MTLTQOMR;
920 __IO uint32_t MTLTQUR;
921 __IO uint32_t MTLTQDR;
922 uint32_t RESERVED35[8];
923 __IO uint32_t MTLQICSR;
924 __IO uint32_t MTLRQOMR;
925 __IO uint32_t MTLRQMPOCR;
926 __IO uint32_t MTLRQDR;
927 uint32_t RESERVED36[177];
928 __IO uint32_t DMAMR;
929 __IO uint32_t DMASBMR;
930 __IO uint32_t DMAISR;
931 __IO uint32_t DMADSR;
932 uint32_t RESERVED37[60];
933 __IO uint32_t DMACCR;
934 __IO uint32_t DMACTCR;
935 __IO uint32_t DMACRCR;
936 uint32_t RESERVED38[2];
937 __IO uint32_t DMACTDLAR;
938 uint32_t RESERVED39;
939 __IO uint32_t DMACRDLAR;
940 __IO uint32_t DMACTDTPR;
941 uint32_t RESERVED40;
942 __IO uint32_t DMACRDTPR;
943 __IO uint32_t DMACTDRLR;
944 __IO uint32_t DMACRDRLR;
945 __IO uint32_t DMACIER;
946 __IO uint32_t DMACRIWTR;
947 __IO uint32_t DMACSFCSR;
948 uint32_t RESERVED41;
949 __IO uint32_t DMACCATDR;
950 uint32_t RESERVED42;
951 __IO uint32_t DMACCARDR;
952 uint32_t RESERVED43;
953 __IO uint32_t DMACCATBR;
954 uint32_t RESERVED44;
955 __IO uint32_t DMACCARBR;
956 __IO uint32_t DMACSR;
957 uint32_t RESERVED45[2];
958 __IO uint32_t DMACMFCR;
959 }ETH_TypeDef;
960 /**
961 * @brief External Interrupt/Event Controller
962 */
963
964 typedef struct
965 {
966 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
967 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
968 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
969 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
970 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
971 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
972 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
973 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
974 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
975 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
976 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
977 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
978 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
979 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
980 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
981 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
982 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
983 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
984 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
985 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
986 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
987 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
988 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
989 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
990 uint32_t RESERVED4; /*!< Reserved, 0x8C */
991 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
992 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
993 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
994 uint32_t RESERVED5; /*!< Reserved, 0x9C */
995 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
996 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
997 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
998 uint32_t RESERVED6[5]; /*!< Reserved, 0xAC to 0xBC */
999 __IO uint32_t C2IMR1; /*!< EXTI Interrupt mask register, Address offset: 0xC0 */
1000 __IO uint32_t C2EMR1; /*!< EXTI Event mask register, Address offset: 0xC4 */
1001 __IO uint32_t C2PR1; /*!< EXTI Pending register, Address offset: 0xC8 */
1002 uint32_t RESERVED7; /*!< Reserved, 0xCC */
1003 __IO uint32_t C2IMR2; /*!< EXTI Interrupt mask register, Address offset: 0xD0 */
1004 __IO uint32_t C2EMR2; /*!< EXTI Event mask register, Address offset: 0xD4 */
1005 __IO uint32_t C2PR2; /*!< EXTI Pending register, Address offset: 0xD8 */
1006 uint32_t RESERVED8; /*!< Reserved, 0xDC */
1007 __IO uint32_t C2IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xE0 */
1008 __IO uint32_t C2EMR3; /*!< EXTI Event mask register, Address offset: 0xE4 */
1009 __IO uint32_t C2PR3; /*!< EXTI Pending register, Address offset: 0xE8 */
1010
1011 }EXTI_TypeDef;
1012
1013 typedef struct
1014 {
1015 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
1016 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
1017 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
1018 uint32_t RESERVED1; /*!< Reserved, 0x0C */
1019 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
1020 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
1021 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
1022 uint32_t RESERVED2; /*!< Reserved, 0x1C */
1023 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
1024 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
1025 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
1026 }EXTI_Core_TypeDef;
1027
1028
1029 /**
1030 * @brief FLASH Registers
1031 */
1032
1033 typedef struct
1034 {
1035 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
1036 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
1037 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
1038 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
1039 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
1040 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
1041 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
1042 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
1043 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
1044 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
1045 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
1046 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
1047 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
1048 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
1049 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
1050 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
1051 __IO uint32_t BOOT7_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
1052 __IO uint32_t BOOT7_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
1053 __IO uint32_t BOOT4_CUR; /*!< Flash Current Boot Address for M4 Core Register, Address offset: 0x48 */
1054 __IO uint32_t BOOT4_PRG; /*!< Flash Boot Address to Program for M4 Core Register, Address offset: 0x4C */
1055 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
1056 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
1057 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
1058 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
1059 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
1060 uint32_t RESERVED1[40]; /*!< Reserved, 0x64 to 0x100 */
1061 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
1062 uint32_t RESERVED2; /*!< Reserved, 0x108 */
1063 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
1064 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
1065 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
1066 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
1067 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
1068 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
1069 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
1070 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
1071 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
1072 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
1073 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
1074 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
1075 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
1076 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
1077 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
1078 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
1079 } FLASH_TypeDef;
1080
1081 /**
1082 * @brief Flexible Memory Controller
1083 */
1084
1085 typedef struct
1086 {
1087 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
1088 } FMC_Bank1_TypeDef;
1089
1090 /**
1091 * @brief Flexible Memory Controller Bank1E
1092 */
1093
1094 typedef struct
1095 {
1096 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
1097 } FMC_Bank1E_TypeDef;
1098
1099 /**
1100 * @brief Flexible Memory Controller Bank2
1101 */
1102
1103 typedef struct
1104 {
1105 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
1106 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
1107 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
1108 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
1109 uint32_t RESERVED0; /*!< Reserved, 0x70 */
1110 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
1111 } FMC_Bank2_TypeDef;
1112
1113 /**
1114 * @brief Flexible Memory Controller Bank3
1115 */
1116
1117 typedef struct
1118 {
1119 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
1120 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
1121 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
1122 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
1123 uint32_t RESERVED; /*!< Reserved, 0x90 */
1124 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
1125 } FMC_Bank3_TypeDef;
1126
1127 /**
1128 * @brief Flexible Memory Controller Bank5 and 6
1129 */
1130
1131
1132 typedef struct
1133 {
1134 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
1135 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
1136 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
1137 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
1138 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
1139 } FMC_Bank5_6_TypeDef;
1140
1141 /**
1142 * @brief General Purpose I/O
1143 */
1144
1145 typedef struct
1146 {
1147 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
1148 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
1149 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
1150 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
1151 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
1152 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
1153 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
1154 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
1155 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
1156 } GPIO_TypeDef;
1157
1158 /**
1159 * @brief Operational Amplifier (OPAMP)
1160 */
1161
1162 typedef struct
1163 {
1164 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
1165 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
1166 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
1167 } OPAMP_TypeDef;
1168
1169 /**
1170 * @brief System configuration controller
1171 */
1172
1173 typedef struct
1174 {
1175 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
1176 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
1177 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
1178 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
1179 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
1180 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
1181 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
1182 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
1183 __IO uint32_t PWRCR; /*!< PWR control register, Address offset: 0x2C */
1184 uint32_t RESERVED3[61]; /*!< Reserved, 0x30-0x120 */
1185 __IO uint32_t PKGR; /*!< SYSCFG package register, Address offset: 0x124 */
1186 uint32_t RESERVED4[118]; /*!< Reserved, 0x128-0x2FC */
1187 __IO uint32_t UR0; /*!< SYSCFG user register 0, Address offset: 0x300 */
1188 __IO uint32_t UR1; /*!< SYSCFG user register 1, Address offset: 0x304 */
1189 __IO uint32_t UR2; /*!< SYSCFG user register 2, Address offset: 0x308 */
1190 __IO uint32_t UR3; /*!< SYSCFG user register 3, Address offset: 0x30C */
1191 __IO uint32_t UR4; /*!< SYSCFG user register 4, Address offset: 0x310 */
1192 __IO uint32_t UR5; /*!< SYSCFG user register 5, Address offset: 0x314 */
1193 __IO uint32_t UR6; /*!< SYSCFG user register 6, Address offset: 0x318 */
1194 __IO uint32_t UR7; /*!< SYSCFG user register 7, Address offset: 0x31C */
1195 __IO uint32_t UR8; /*!< SYSCFG user register 8, Address offset: 0x320 */
1196 __IO uint32_t UR9; /*!< SYSCFG user register 9, Address offset: 0x324 */
1197 __IO uint32_t UR10; /*!< SYSCFG user register 10, Address offset: 0x328 */
1198 __IO uint32_t UR11; /*!< SYSCFG user register 11, Address offset: 0x32C */
1199 __IO uint32_t UR12; /*!< SYSCFG user register 12, Address offset: 0x330 */
1200 __IO uint32_t UR13; /*!< SYSCFG user register 13, Address offset: 0x334 */
1201 __IO uint32_t UR14; /*!< SYSCFG user register 14, Address offset: 0x338 */
1202 __IO uint32_t UR15; /*!< SYSCFG user register 15, Address offset: 0x33C */
1203 __IO uint32_t UR16; /*!< SYSCFG user register 16, Address offset: 0x340 */
1204 __IO uint32_t UR17; /*!< SYSCFG user register 17, Address offset: 0x344 */
1205
1206 } SYSCFG_TypeDef;
1207
1208 /**
1209 * @brief Inter-integrated Circuit Interface
1210 */
1211
1212 typedef struct
1213 {
1214 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
1215 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
1216 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
1217 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
1218 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
1219 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
1220 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
1221 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
1222 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
1223 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
1224 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
1225 } I2C_TypeDef;
1226
1227 /**
1228 * @brief Independent WATCHDOG
1229 */
1230
1231 typedef struct
1232 {
1233 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
1234 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
1235 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
1236 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
1237 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
1238 } IWDG_TypeDef;
1239
1240
1241 /**
1242 * @brief JPEG Codec
1243 */
1244 typedef struct
1245 {
1246 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
1247 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
1248 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
1249 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
1250 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
1251 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
1252 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
1253 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
1254 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
1255 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
1256 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
1257 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
1258 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
1259 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
1260 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
1261 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
1262 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
1263 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
1264 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
1265 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
1266 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
1267 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
1268 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
1269 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
1270 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
1271 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
1272 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
1273 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1274 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1275
1276 } JPEG_TypeDef;
1277
1278 /**
1279 * @brief LCD-TFT Display Controller
1280 */
1281
1282 typedef struct
1283 {
1284 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1285 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1286 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1287 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1288 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1289 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1290 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1291 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1292 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1293 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1294 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1295 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1296 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1297 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1298 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1299 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1300 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1301 } LTDC_TypeDef;
1302
1303 /**
1304 * @brief LCD-TFT Display layer x Controller
1305 */
1306
1307 typedef struct
1308 {
1309 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1310 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1311 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1312 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1313 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1314 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1315 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1316 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1317 uint32_t RESERVED0[2]; /*!< Reserved */
1318 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1319 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1320 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1321 uint32_t RESERVED1[3]; /*!< Reserved */
1322 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1323
1324 } LTDC_Layer_TypeDef;
1325
1326 /**
1327 * @brief Power Control
1328 */
1329
1330 typedef struct
1331 {
1332 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1333 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1334 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1335 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1336 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1337 __IO uint32_t CPU2CR; /*!< PWR CPU2 control register, Address offset: 0x14 */
1338 __IO uint32_t D3CR; /*!< PWR D3 domain control register, Address offset: 0x18 */
1339 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1340 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1341 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1342 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1343 } PWR_TypeDef;
1344
1345 /**
1346 * @brief Reset and Clock Control
1347 */
1348
1349 typedef struct
1350 {
1351 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1352 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1353 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1354 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1355 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1356 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1357 __IO uint32_t D1CFGR; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1358 __IO uint32_t D2CFGR; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1359 __IO uint32_t D3CFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1360 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1361 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1362 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1363 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1364 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1365 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1366 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1367 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1368 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1369 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1370 __IO uint32_t D1CCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1371 __IO uint32_t D2CCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1372 __IO uint32_t D2CCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1373 __IO uint32_t D3CCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1374 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1375 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1376 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1377 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1378 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1379 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1380 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1381 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1382 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1383 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1384 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1385 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1386 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1387 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1388 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1389 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1390 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1391 __IO uint32_t GCR; /*!< RCC RCC Global Control Register, Address offset: 0xA0 */
1392 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1393 __IO uint32_t D3AMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1394 uint32_t RESERVED11[9]; /*!< Reserved, 0xAC-0xCC Address offset: 0xAC */
1395 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1396 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1397 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1398 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1399 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1400 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1401 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1402 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1403 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1404 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1405 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1406 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1407 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1408 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1409 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1410 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1411 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1412 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1413 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1414 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1415 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1416
1417 } RCC_TypeDef;
1418
1419 typedef struct
1420 {
1421 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0x00 */
1422 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0x04 */
1423 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0x08 */
1424 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0x0C */
1425 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0x10 */
1426 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0x14 */
1427 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0x18 */
1428 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0x1C */
1429 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0x20 */
1430 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0x24 */
1431 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x28 */
1432 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0x3C */
1433 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x40 */
1434 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x44 */
1435 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x48 */
1436 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x4C */
1437 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x50 */
1438 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x54 */
1439 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x58 */
1440 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x5C */
1441 uint32_t RESERVED10[4]; /*!< Reserved, 0x60-0x6C Address offset: 0x60 */
1442
1443 } RCC_Core_TypeDef;
1444
1445 /**
1446 * @brief Real-Time Clock
1447 */
1448 typedef struct
1449 {
1450 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1451 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1452 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x08 */
1453 __IO uint32_t ISR; /*!< RTC initialization and status register, Address offset: 0x0C */
1454 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1455 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1456 uint32_t RESERVED; /*!< Reserved, Address offset: 0x18 */
1457 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x1C */
1458 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x20 */
1459 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1460 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x28 */
1461 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1462 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1463 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1464 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1465 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x3C */
1466 __IO uint32_t TAMPCR; /*!< RTC tamper configuration register, Address offset: 0x40 */
1467 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1468 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x48 */
1469 __IO uint32_t OR; /*!< RTC option register, Address offset: 0x4C */
1470 __IO uint32_t BKP0R; /*!< RTC backup register 0, Address offset: 0x50 */
1471 __IO uint32_t BKP1R; /*!< RTC backup register 1, Address offset: 0x54 */
1472 __IO uint32_t BKP2R; /*!< RTC backup register 2, Address offset: 0x58 */
1473 __IO uint32_t BKP3R; /*!< RTC backup register 3, Address offset: 0x5C */
1474 __IO uint32_t BKP4R; /*!< RTC backup register 4, Address offset: 0x60 */
1475 __IO uint32_t BKP5R; /*!< RTC backup register 5, Address offset: 0x64 */
1476 __IO uint32_t BKP6R; /*!< RTC backup register 6, Address offset: 0x68 */
1477 __IO uint32_t BKP7R; /*!< RTC backup register 7, Address offset: 0x6C */
1478 __IO uint32_t BKP8R; /*!< RTC backup register 8, Address offset: 0x70 */
1479 __IO uint32_t BKP9R; /*!< RTC backup register 9, Address offset: 0x74 */
1480 __IO uint32_t BKP10R; /*!< RTC backup register 10, Address offset: 0x78 */
1481 __IO uint32_t BKP11R; /*!< RTC backup register 11, Address offset: 0x7C */
1482 __IO uint32_t BKP12R; /*!< RTC backup register 12, Address offset: 0x80 */
1483 __IO uint32_t BKP13R; /*!< RTC backup register 13, Address offset: 0x84 */
1484 __IO uint32_t BKP14R; /*!< RTC backup register 14, Address offset: 0x88 */
1485 __IO uint32_t BKP15R; /*!< RTC backup register 15, Address offset: 0x8C */
1486 __IO uint32_t BKP16R; /*!< RTC backup register 16, Address offset: 0x90 */
1487 __IO uint32_t BKP17R; /*!< RTC backup register 17, Address offset: 0x94 */
1488 __IO uint32_t BKP18R; /*!< RTC backup register 18, Address offset: 0x98 */
1489 __IO uint32_t BKP19R; /*!< RTC backup register 19, Address offset: 0x9C */
1490 __IO uint32_t BKP20R; /*!< RTC backup register 20, Address offset: 0xA0 */
1491 __IO uint32_t BKP21R; /*!< RTC backup register 21, Address offset: 0xA4 */
1492 __IO uint32_t BKP22R; /*!< RTC backup register 22, Address offset: 0xA8 */
1493 __IO uint32_t BKP23R; /*!< RTC backup register 23, Address offset: 0xAC */
1494 __IO uint32_t BKP24R; /*!< RTC backup register 24, Address offset: 0xB0 */
1495 __IO uint32_t BKP25R; /*!< RTC backup register 25, Address offset: 0xB4 */
1496 __IO uint32_t BKP26R; /*!< RTC backup register 26, Address offset: 0xB8 */
1497 __IO uint32_t BKP27R; /*!< RTC backup register 27, Address offset: 0xBC */
1498 __IO uint32_t BKP28R; /*!< RTC backup register 28, Address offset: 0xC0 */
1499 __IO uint32_t BKP29R; /*!< RTC backup register 29, Address offset: 0xC4 */
1500 __IO uint32_t BKP30R; /*!< RTC backup register 30, Address offset: 0xC8 */
1501 __IO uint32_t BKP31R; /*!< RTC backup register 31, Address offset: 0xCC */
1502 } RTC_TypeDef;
1503
1504 /**
1505 * @brief Serial Audio Interface
1506 */
1507
1508 typedef struct
1509 {
1510 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1511 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1512 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1513 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1514 } SAI_TypeDef;
1515
1516 typedef struct
1517 {
1518 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1519 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1520 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1521 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1522 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1523 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1524 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1525 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1526 } SAI_Block_TypeDef;
1527
1528 /**
1529 * @brief SPDIF-RX Interface
1530 */
1531
1532 typedef struct
1533 {
1534 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1535 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1536 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1537 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1538 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1539 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1540 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1541 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1542 } SPDIFRX_TypeDef;
1543
1544
1545 /**
1546 * @brief Secure digital input/output Interface
1547 */
1548
1549 typedef struct
1550 {
1551 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1552 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1553 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1554 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1555 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1556 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1557 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1558 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1559 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1560 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1561 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1562 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1563 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1564 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1565 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1566 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1567 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1568 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1569 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1570 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1571 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1572 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1573 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1574 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1575 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1576 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1577 } SDMMC_TypeDef;
1578
1579
1580 /**
1581 * @brief Delay Block DLYB
1582 */
1583
1584 typedef struct
1585 {
1586 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1587 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1588 } DLYB_TypeDef;
1589
1590 /**
1591 * @brief HW Semaphore HSEM
1592 */
1593
1594 typedef struct
1595 {
1596 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1597 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1598 __IO uint32_t C1IER; /*!< HSEM Interrupt 0 enable register , Address offset: 100h */
1599 __IO uint32_t C1ICR; /*!< HSEM Interrupt 0 clear register , Address offset: 104h */
1600 __IO uint32_t C1ISR; /*!< HSEM Interrupt 0 Status register , Address offset: 108h */
1601 __IO uint32_t C1MISR; /*!< HSEM Interrupt 0 Masked Status register , Address offset: 10Ch */
1602 __IO uint32_t C2IER; /*!< HSEM Interrupt 1 enable register , Address offset: 110h */
1603 __IO uint32_t C2ICR; /*!< HSEM Interrupt 1 clear register , Address offset: 114h */
1604 __IO uint32_t C2ISR; /*!< HSEM Interrupt 1 Status register , Address offset: 118h */
1605 __IO uint32_t C2MISR; /*!< HSEM Interrupt 1 Masked Status register , Address offset: 11Ch */
1606 uint32_t Reserved[8]; /* Reserved Address offset: 120h-13Ch*/
1607 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1608 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1609
1610 } HSEM_TypeDef;
1611
1612 typedef struct
1613 {
1614 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1615 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1616 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1617 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1618 } HSEM_Common_TypeDef;
1619
1620 /**
1621 * @brief Serial Peripheral Interface
1622 */
1623
1624 typedef struct
1625 {
1626 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1627 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1628 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1629 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1630 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1631 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1632 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1633 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1634 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1635 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1636 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1637 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1638 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1639 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1640 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1641 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1642 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1643
1644 } SPI_TypeDef;
1645 /**
1646 * @brief QUAD Serial Peripheral Interface
1647 */
1648
1649 typedef struct
1650 {
1651 __IO uint32_t CR; /*!< QUADSPI Control register, Address offset: 0x00 */
1652 __IO uint32_t DCR; /*!< QUADSPI Device Configuration register, Address offset: 0x04 */
1653 __IO uint32_t SR; /*!< QUADSPI Status register, Address offset: 0x08 */
1654 __IO uint32_t FCR; /*!< QUADSPI Flag Clear register, Address offset: 0x0C */
1655 __IO uint32_t DLR; /*!< QUADSPI Data Length register, Address offset: 0x10 */
1656 __IO uint32_t CCR; /*!< QUADSPI Communication Configuration register, Address offset: 0x14 */
1657 __IO uint32_t AR; /*!< QUADSPI Address register, Address offset: 0x18 */
1658 __IO uint32_t ABR; /*!< QUADSPI Alternate Bytes register, Address offset: 0x1C */
1659 __IO uint32_t DR; /*!< QUADSPI Data register, Address offset: 0x20 */
1660 __IO uint32_t PSMKR; /*!< QUADSPI Polling Status Mask register, Address offset: 0x24 */
1661 __IO uint32_t PSMAR; /*!< QUADSPI Polling Status Match register, Address offset: 0x28 */
1662 __IO uint32_t PIR; /*!< QUADSPI Polling Interval register, Address offset: 0x2C */
1663 __IO uint32_t LPTR; /*!< QUADSPI Low Power Timeout register, Address offset: 0x30 */
1664 } QUADSPI_TypeDef;
1665
1666 /**
1667 * @brief TIM
1668 */
1669
1670 typedef struct
1671 {
1672 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1673 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1674 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1675 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1676 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1677 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1678 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1679 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1680 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1681 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1682 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1683 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1684 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1685 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1686 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1687 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1688 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1689 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1690 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1691 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1692 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1693 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1694 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1695 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1696 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1697 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1698 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1699 } TIM_TypeDef;
1700
1701 /**
1702 * @brief LPTIMIMER
1703 */
1704 typedef struct
1705 {
1706 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1707 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1708 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1709 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1710 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1711 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1712 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1713 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1714 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1715 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1716 } LPTIM_TypeDef;
1717
1718 /**
1719 * @brief Comparator
1720 */
1721 typedef struct
1722 {
1723 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1724 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1725 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1726 } COMPOPT_TypeDef;
1727
1728 typedef struct
1729 {
1730 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1731 } COMP_TypeDef;
1732
1733 typedef struct
1734 {
1735 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1736 } COMP_Common_TypeDef;
1737 /**
1738 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1739 */
1740
1741 typedef struct
1742 {
1743 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1744 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1745 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1746 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1747 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1748 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1749 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1750 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1751 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1752 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1753 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1754 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1755 } USART_TypeDef;
1756
1757 /**
1758 * @brief Single Wire Protocol Master Interface SPWMI
1759 */
1760 typedef struct
1761 {
1762 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1763 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1764 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1765 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1766 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1767 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1768 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1769 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1770 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1771 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1772 } SWPMI_TypeDef;
1773
1774 /**
1775 * @brief Window WATCHDOG
1776 */
1777
1778 typedef struct
1779 {
1780 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1781 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1782 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1783 } WWDG_TypeDef;
1784
1785
1786 /**
1787 * @brief RAM_ECC_Specific_Registers
1788 */
1789 typedef struct
1790 {
1791 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1792 __IO uint32_t SR; /*!< RAMECC monitor status register */
1793 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1794 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1795 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1796 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1797 } RAMECC_MonitorTypeDef;
1798
1799 typedef struct
1800 {
1801 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1802 } RAMECC_TypeDef;
1803 /**
1804 * @}
1805 */
1806
1807
1808
1809 /**
1810 * @brief High resolution Timer (HRTIM)
1811 */
1812 /* HRTIM master registers definition */
1813 typedef struct
1814 {
1815 __IO uint32_t MCR; /*!< HRTIM Master Timer control register, Address offset: 0x00 */
1816 __IO uint32_t MISR; /*!< HRTIM Master Timer interrupt status register, Address offset: 0x04 */
1817 __IO uint32_t MICR; /*!< HRTIM Master Timer interupt clear register, Address offset: 0x08 */
1818 __IO uint32_t MDIER; /*!< HRTIM Master Timer DMA/interrupt enable register Address offset: 0x0C */
1819 __IO uint32_t MCNTR; /*!< HRTIM Master Timer counter register, Address offset: 0x10 */
1820 __IO uint32_t MPER; /*!< HRTIM Master Timer period register, Address offset: 0x14 */
1821 __IO uint32_t MREP; /*!< HRTIM Master Timer repetition register, Address offset: 0x18 */
1822 __IO uint32_t MCMP1R; /*!< HRTIM Master Timer compare 1 register, Address offset: 0x1C */
1823 uint32_t RESERVED0; /*!< Reserved, 0x20 */
1824 __IO uint32_t MCMP2R; /*!< HRTIM Master Timer compare 2 register, Address offset: 0x24 */
1825 __IO uint32_t MCMP3R; /*!< HRTIM Master Timer compare 3 register, Address offset: 0x28 */
1826 __IO uint32_t MCMP4R; /*!< HRTIM Master Timer compare 4 register, Address offset: 0x2C */
1827 uint32_t RESERVED1[20]; /*!< Reserved, 0x30..0x7C */
1828 }HRTIM_Master_TypeDef;
1829
1830 /* HRTIM Timer A to E registers definition */
1831 typedef struct
1832 {
1833 __IO uint32_t TIMxCR; /*!< HRTIM Timerx control register, Address offset: 0x00 */
1834 __IO uint32_t TIMxISR; /*!< HRTIM Timerx interrupt status register, Address offset: 0x04 */
1835 __IO uint32_t TIMxICR; /*!< HRTIM Timerx interrupt clear register, Address offset: 0x08 */
1836 __IO uint32_t TIMxDIER; /*!< HRTIM Timerx DMA/interrupt enable register, Address offset: 0x0C */
1837 __IO uint32_t CNTxR; /*!< HRTIM Timerx counter register, Address offset: 0x10 */
1838 __IO uint32_t PERxR; /*!< HRTIM Timerx period register, Address offset: 0x14 */
1839 __IO uint32_t REPxR; /*!< HRTIM Timerx repetition register, Address offset: 0x18 */
1840 __IO uint32_t CMP1xR; /*!< HRTIM Timerx compare 1 register, Address offset: 0x1C */
1841 __IO uint32_t CMP1CxR; /*!< HRTIM Timerx compare 1 compound register, Address offset: 0x20 */
1842 __IO uint32_t CMP2xR; /*!< HRTIM Timerx compare 2 register, Address offset: 0x24 */
1843 __IO uint32_t CMP3xR; /*!< HRTIM Timerx compare 3 register, Address offset: 0x28 */
1844 __IO uint32_t CMP4xR; /*!< HRTIM Timerx compare 4 register, Address offset: 0x2C */
1845 __IO uint32_t CPT1xR; /*!< HRTIM Timerx capture 1 register, Address offset: 0x30 */
1846 __IO uint32_t CPT2xR; /*!< HRTIM Timerx capture 2 register, Address offset: 0x34 */
1847 __IO uint32_t DTxR; /*!< HRTIM Timerx dead time register, Address offset: 0x38 */
1848 __IO uint32_t SETx1R; /*!< HRTIM Timerx output 1 set register, Address offset: 0x3C */
1849 __IO uint32_t RSTx1R; /*!< HRTIM Timerx output 1 reset register, Address offset: 0x40 */
1850 __IO uint32_t SETx2R; /*!< HRTIM Timerx output 2 set register, Address offset: 0x44 */
1851 __IO uint32_t RSTx2R; /*!< HRTIM Timerx output 2 reset register, Address offset: 0x48 */
1852 __IO uint32_t EEFxR1; /*!< HRTIM Timerx external event filtering 1 register, Address offset: 0x4C */
1853 __IO uint32_t EEFxR2; /*!< HRTIM Timerx external event filtering 2 register, Address offset: 0x50 */
1854 __IO uint32_t RSTxR; /*!< HRTIM Timerx Reset register, Address offset: 0x54 */
1855 __IO uint32_t CHPxR; /*!< HRTIM Timerx Chopper register, Address offset: 0x58 */
1856 __IO uint32_t CPT1xCR; /*!< HRTIM Timerx Capture 1 register, Address offset: 0x5C */
1857 __IO uint32_t CPT2xCR; /*!< HRTIM Timerx Capture 2 register, Address offset: 0x60 */
1858 __IO uint32_t OUTxR; /*!< HRTIM Timerx Output register, Address offset: 0x64 */
1859 __IO uint32_t FLTxR; /*!< HRTIM Timerx Fault register, Address offset: 0x68 */
1860 uint32_t RESERVED0[5]; /*!< Reserved, 0x6C..0x7C */
1861 }HRTIM_Timerx_TypeDef;
1862
1863 /* HRTIM common register definition */
1864 typedef struct
1865 {
1866 __IO uint32_t CR1; /*!< HRTIM control register1, Address offset: 0x00 */
1867 __IO uint32_t CR2; /*!< HRTIM control register2, Address offset: 0x04 */
1868 __IO uint32_t ISR; /*!< HRTIM interrupt status register, Address offset: 0x08 */
1869 __IO uint32_t ICR; /*!< HRTIM interrupt clear register, Address offset: 0x0C */
1870 __IO uint32_t IER; /*!< HRTIM interrupt enable register, Address offset: 0x10 */
1871 __IO uint32_t OENR; /*!< HRTIM Output enable register, Address offset: 0x14 */
1872 __IO uint32_t ODISR; /*!< HRTIM Output disable register, Address offset: 0x18 */
1873 __IO uint32_t ODSR; /*!< HRTIM Output disable status register, Address offset: 0x1C */
1874 __IO uint32_t BMCR; /*!< HRTIM Burst mode control register, Address offset: 0x20 */
1875 __IO uint32_t BMTRGR; /*!< HRTIM Busrt mode trigger register, Address offset: 0x24 */
1876 __IO uint32_t BMCMPR; /*!< HRTIM Burst mode compare register, Address offset: 0x28 */
1877 __IO uint32_t BMPER; /*!< HRTIM Burst mode period register, Address offset: 0x2C */
1878 __IO uint32_t EECR1; /*!< HRTIM Timer external event control register1, Address offset: 0x30 */
1879 __IO uint32_t EECR2; /*!< HRTIM Timer external event control register2, Address offset: 0x34 */
1880 __IO uint32_t EECR3; /*!< HRTIM Timer external event control register3, Address offset: 0x38 */
1881 __IO uint32_t ADC1R; /*!< HRTIM ADC Trigger 1 register, Address offset: 0x3C */
1882 __IO uint32_t ADC2R; /*!< HRTIM ADC Trigger 2 register, Address offset: 0x40 */
1883 __IO uint32_t ADC3R; /*!< HRTIM ADC Trigger 3 register, Address offset: 0x44 */
1884 __IO uint32_t ADC4R; /*!< HRTIM ADC Trigger 4 register, Address offset: 0x48 */
1885 __IO uint32_t RESERVED0; /*!< Reserved, Address offset: 0x4C */
1886 __IO uint32_t FLTINR1; /*!< HRTIM Fault input register1, Address offset: 0x50 */
1887 __IO uint32_t FLTINR2; /*!< HRTIM Fault input register2, Address offset: 0x54 */
1888 __IO uint32_t BDMUPR; /*!< HRTIM Burst DMA Master Timer update register, Address offset: 0x58 */
1889 __IO uint32_t BDTAUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x5C */
1890 __IO uint32_t BDTBUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x60 */
1891 __IO uint32_t BDTCUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x64 */
1892 __IO uint32_t BDTDUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x68 */
1893 __IO uint32_t BDTEUPR; /*!< HRTIM Burst DMA Timerx update register, Address offset: 0x6C */
1894 __IO uint32_t BDMADR; /*!< HRTIM Burst DMA Master Data register, Address offset: 0x70 */
1895 }HRTIM_Common_TypeDef;
1896
1897 /* HRTIM register definition */
1898 typedef struct {
1899 HRTIM_Master_TypeDef sMasterRegs;
1900 HRTIM_Timerx_TypeDef sTimerxRegs[5];
1901 uint32_t RESERVED0[32];
1902 HRTIM_Common_TypeDef sCommonRegs;
1903 }HRTIM_TypeDef;
1904 /**
1905 * @brief RNG
1906 */
1907
1908 typedef struct
1909 {
1910 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1911 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1912 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1913 } RNG_TypeDef;
1914
1915 /**
1916 * @brief MDIOS
1917 */
1918
1919 typedef struct
1920 {
1921 __IO uint32_t CR;
1922 __IO uint32_t WRFR;
1923 __IO uint32_t CWRFR;
1924 __IO uint32_t RDFR;
1925 __IO uint32_t CRDFR;
1926 __IO uint32_t SR;
1927 __IO uint32_t CLRFR;
1928 uint32_t RESERVED[57];
1929 __IO uint32_t DINR0;
1930 __IO uint32_t DINR1;
1931 __IO uint32_t DINR2;
1932 __IO uint32_t DINR3;
1933 __IO uint32_t DINR4;
1934 __IO uint32_t DINR5;
1935 __IO uint32_t DINR6;
1936 __IO uint32_t DINR7;
1937 __IO uint32_t DINR8;
1938 __IO uint32_t DINR9;
1939 __IO uint32_t DINR10;
1940 __IO uint32_t DINR11;
1941 __IO uint32_t DINR12;
1942 __IO uint32_t DINR13;
1943 __IO uint32_t DINR14;
1944 __IO uint32_t DINR15;
1945 __IO uint32_t DINR16;
1946 __IO uint32_t DINR17;
1947 __IO uint32_t DINR18;
1948 __IO uint32_t DINR19;
1949 __IO uint32_t DINR20;
1950 __IO uint32_t DINR21;
1951 __IO uint32_t DINR22;
1952 __IO uint32_t DINR23;
1953 __IO uint32_t DINR24;
1954 __IO uint32_t DINR25;
1955 __IO uint32_t DINR26;
1956 __IO uint32_t DINR27;
1957 __IO uint32_t DINR28;
1958 __IO uint32_t DINR29;
1959 __IO uint32_t DINR30;
1960 __IO uint32_t DINR31;
1961 __IO uint32_t DOUTR0;
1962 __IO uint32_t DOUTR1;
1963 __IO uint32_t DOUTR2;
1964 __IO uint32_t DOUTR3;
1965 __IO uint32_t DOUTR4;
1966 __IO uint32_t DOUTR5;
1967 __IO uint32_t DOUTR6;
1968 __IO uint32_t DOUTR7;
1969 __IO uint32_t DOUTR8;
1970 __IO uint32_t DOUTR9;
1971 __IO uint32_t DOUTR10;
1972 __IO uint32_t DOUTR11;
1973 __IO uint32_t DOUTR12;
1974 __IO uint32_t DOUTR13;
1975 __IO uint32_t DOUTR14;
1976 __IO uint32_t DOUTR15;
1977 __IO uint32_t DOUTR16;
1978 __IO uint32_t DOUTR17;
1979 __IO uint32_t DOUTR18;
1980 __IO uint32_t DOUTR19;
1981 __IO uint32_t DOUTR20;
1982 __IO uint32_t DOUTR21;
1983 __IO uint32_t DOUTR22;
1984 __IO uint32_t DOUTR23;
1985 __IO uint32_t DOUTR24;
1986 __IO uint32_t DOUTR25;
1987 __IO uint32_t DOUTR26;
1988 __IO uint32_t DOUTR27;
1989 __IO uint32_t DOUTR28;
1990 __IO uint32_t DOUTR29;
1991 __IO uint32_t DOUTR30;
1992 __IO uint32_t DOUTR31;
1993 } MDIOS_TypeDef;
1994
1995
1996 /**
1997 * @brief USB_OTG_Core_Registers
1998 */
1999 typedef struct
2000 {
2001 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
2002 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
2003 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
2004 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
2005 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
2006 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
2007 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
2008 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
2009 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
2010 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
2011 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
2012 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
2013 uint32_t Reserved30[2]; /*!< Reserved 030h */
2014 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
2015 __IO uint32_t CID; /*!< User ID Register 03Ch */
2016 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
2017 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
2018 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
2019 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
2020 uint32_t Reserved6; /*!< Reserved 050h */
2021 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
2022 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
2023 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
2024 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
2025 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
2026 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
2027 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
2028 } USB_OTG_GlobalTypeDef;
2029
2030
2031 /**
2032 * @brief USB_OTG_device_Registers
2033 */
2034 typedef struct
2035 {
2036 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
2037 __IO uint32_t DCTL; /*!< dev Control Register 804h */
2038 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
2039 uint32_t Reserved0C; /*!< Reserved 80Ch */
2040 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
2041 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
2042 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
2043 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
2044 uint32_t Reserved20; /*!< Reserved 820h */
2045 uint32_t Reserved9; /*!< Reserved 824h */
2046 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
2047 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
2048 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
2049 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
2050 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
2051 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
2052 uint32_t Reserved40; /*!< dedicated EP mask 840h */
2053 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
2054 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
2055 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
2056 } USB_OTG_DeviceTypeDef;
2057
2058
2059 /**
2060 * @brief USB_OTG_IN_Endpoint-Specific_Register
2061 */
2062 typedef struct
2063 {
2064 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
2065 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
2066 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
2067 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
2068 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
2069 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
2070 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
2071 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
2072 } USB_OTG_INEndpointTypeDef;
2073
2074
2075 /**
2076 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
2077 */
2078 typedef struct
2079 {
2080 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
2081 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
2082 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
2083 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
2084 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
2085 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
2086 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
2087 } USB_OTG_OUTEndpointTypeDef;
2088
2089
2090 /**
2091 * @brief USB_OTG_Host_Mode_Register_Structures
2092 */
2093 typedef struct
2094 {
2095 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
2096 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
2097 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
2098 uint32_t Reserved40C; /*!< Reserved 40Ch */
2099 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
2100 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
2101 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
2102 } USB_OTG_HostTypeDef;
2103
2104 /**
2105 * @brief USB_OTG_Host_Channel_Specific_Registers
2106 */
2107 typedef struct
2108 {
2109 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
2110 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
2111 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
2112 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
2113 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
2114 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
2115 uint32_t Reserved[2]; /*!< Reserved */
2116 } USB_OTG_HostChannelTypeDef;
2117 /**
2118 * @}
2119 */
2120
2121
2122 /** @addtogroup Peripheral_memory_map
2123 * @{
2124 */
2125 #define D1_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
2126 #define D1_ITCMICP_BASE (0x00100000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over ITCM */
2127 #define D1_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB system data RAM accessible over DTCM */
2128 #define D1_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
2129 #define D1_AXIICP_BASE (0x1FF00000UL) /*!< Base address of : (up to 128KB) embedded Test FLASH memory accessible over AXI */
2130 #define D1_AXISRAM_BASE (0x24000000UL) /*!< Base address of : (up to 512KB) system data RAM accessible over over AXI */
2131
2132 #define D2_AXISRAM_BASE (0x10000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI */
2133 #define D2_AHBSRAM_BASE (0x30000000UL) /*!< Base address of : (up to 288KB) system data RAM accessible over over AXI->AHB Bridge */
2134
2135 #define D3_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
2136 #define D3_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(64 KB) over AXI->AHB Bridge */
2137
2138 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/APB Peripherals */
2139 #define QSPI_BASE (0x90000000UL) /*!< Base address of : QSPI memories accessible over AXI */
2140
2141 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
2142 #define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
2143 #define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
2144
2145 /* Legacy define */
2146 #define FLASH_BASE FLASH_BANK1_BASE
2147
2148 /*!< Device electronic signature memory map */
2149 #define UID_BASE (0x1FF1E800UL) /*!< Unique device ID register base address */
2150 #define FLASHSIZE_BASE (0x1FF1E880UL) /*!< FLASH Size register base address */
2151
2152
2153 /*!< Peripheral memory map */
2154 #define D2_APB1PERIPH_BASE PERIPH_BASE
2155 #define D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2156 #define D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2157 #define D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
2158
2159 #define D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL)
2160 #define D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL)
2161
2162 #define D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL)
2163 #define D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL)
2164
2165 /*!< Legacy Peripheral memory map */
2166 #define APB1PERIPH_BASE PERIPH_BASE
2167 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
2168 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
2169 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08000000UL)
2170
2171
2172 /*!< D1_AHB1PERIPH peripherals */
2173
2174 #define MDMA_BASE (D1_AHB1PERIPH_BASE + 0x0000UL)
2175 #define DMA2D_BASE (D1_AHB1PERIPH_BASE + 0x1000UL)
2176 #define JPGDEC_BASE (D1_AHB1PERIPH_BASE + 0x3000UL)
2177 #define FLASH_R_BASE (D1_AHB1PERIPH_BASE + 0x2000UL)
2178 #define FMC_R_BASE (D1_AHB1PERIPH_BASE + 0x4000UL)
2179 #define QSPI_R_BASE (D1_AHB1PERIPH_BASE + 0x5000UL)
2180 #define DLYB_QSPI_BASE (D1_AHB1PERIPH_BASE + 0x6000UL)
2181 #define SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x7000UL)
2182 #define DLYB_SDMMC1_BASE (D1_AHB1PERIPH_BASE + 0x8000UL)
2183 #define RAMECC1_BASE (D1_AHB1PERIPH_BASE + 0x9000UL)
2184
2185 /*!< D2_AHB1PERIPH peripherals */
2186
2187 #define DMA1_BASE (D2_AHB1PERIPH_BASE + 0x0000UL)
2188 #define DMA2_BASE (D2_AHB1PERIPH_BASE + 0x0400UL)
2189 #define DMAMUX1_BASE (D2_AHB1PERIPH_BASE + 0x0800UL)
2190 #define ADC1_BASE (D2_AHB1PERIPH_BASE + 0x2000UL)
2191 #define ADC2_BASE (D2_AHB1PERIPH_BASE + 0x2100UL)
2192 #define ADC12_COMMON_BASE (D2_AHB1PERIPH_BASE + 0x2300UL)
2193 #define ART_BASE (D2_AHB1PERIPH_BASE + 0x4400UL)
2194 #define ETH_BASE (D2_AHB1PERIPH_BASE + 0x8000UL)
2195 #define ETH_MAC_BASE (ETH_BASE)
2196
2197 /*!< USB registers base address */
2198 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2199 #define USB2_OTG_FS_PERIPH_BASE (0x40080000UL)
2200 #define USB_OTG_GLOBAL_BASE (0x000UL)
2201 #define USB_OTG_DEVICE_BASE (0x800UL)
2202 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2203 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2204 #define USB_OTG_EP_REG_SIZE (0x20UL)
2205 #define USB_OTG_HOST_BASE (0x400UL)
2206 #define USB_OTG_HOST_PORT_BASE (0x440UL)
2207 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2208 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2209 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
2210 #define USB_OTG_FIFO_BASE (0x1000UL)
2211 #define USB_OTG_FIFO_SIZE (0x1000UL)
2212
2213 /*!< D2_AHB2PERIPH peripherals */
2214
2215 #define DCMI_BASE (D2_AHB2PERIPH_BASE + 0x0000UL)
2216 #define RNG_BASE (D2_AHB2PERIPH_BASE + 0x1800UL)
2217 #define SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2400UL)
2218 #define DLYB_SDMMC2_BASE (D2_AHB2PERIPH_BASE + 0x2800UL)
2219 #define RAMECC2_BASE (D2_AHB2PERIPH_BASE + 0x3000UL)
2220
2221 /*!< D3_AHB1PERIPH peripherals */
2222 #define GPIOA_BASE (D3_AHB1PERIPH_BASE + 0x0000UL)
2223 #define GPIOB_BASE (D3_AHB1PERIPH_BASE + 0x0400UL)
2224 #define GPIOC_BASE (D3_AHB1PERIPH_BASE + 0x0800UL)
2225 #define GPIOD_BASE (D3_AHB1PERIPH_BASE + 0x0C00UL)
2226 #define GPIOE_BASE (D3_AHB1PERIPH_BASE + 0x1000UL)
2227 #define GPIOF_BASE (D3_AHB1PERIPH_BASE + 0x1400UL)
2228 #define GPIOG_BASE (D3_AHB1PERIPH_BASE + 0x1800UL)
2229 #define GPIOH_BASE (D3_AHB1PERIPH_BASE + 0x1C00UL)
2230 #define GPIOI_BASE (D3_AHB1PERIPH_BASE + 0x2000UL)
2231 #define GPIOJ_BASE (D3_AHB1PERIPH_BASE + 0x2400UL)
2232 #define GPIOK_BASE (D3_AHB1PERIPH_BASE + 0x2800UL)
2233 #define RCC_BASE (D3_AHB1PERIPH_BASE + 0x4400UL)
2234 #define RCC_C1_BASE (RCC_BASE + 0x130UL)
2235 #define RCC_C2_BASE (RCC_BASE + 0x190UL)
2236 #define PWR_BASE (D3_AHB1PERIPH_BASE + 0x4800UL)
2237 #define CRC_BASE (D3_AHB1PERIPH_BASE + 0x4C00UL)
2238 #define BDMA_BASE (D3_AHB1PERIPH_BASE + 0x5400UL)
2239 #define DMAMUX2_BASE (D3_AHB1PERIPH_BASE + 0x5800UL)
2240 #define ADC3_BASE (D3_AHB1PERIPH_BASE + 0x6000UL)
2241 #define ADC3_COMMON_BASE (D3_AHB1PERIPH_BASE + 0x6300UL)
2242 #define HSEM_BASE (D3_AHB1PERIPH_BASE + 0x6400UL)
2243 #define RAMECC3_BASE (D3_AHB1PERIPH_BASE + 0x7000UL)
2244
2245 /*!< D1_APB1PERIPH peripherals */
2246 #define LTDC_BASE (D1_APB1PERIPH_BASE + 0x1000UL)
2247 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2248 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2249 #define DSI_BASE (D1_APB1PERIPH_BASE)
2250 #define WWDG1_BASE (D1_APB1PERIPH_BASE + 0x3000UL)
2251
2252 /*!< D2_APB1PERIPH peripherals */
2253 #define TIM2_BASE (D2_APB1PERIPH_BASE + 0x0000UL)
2254 #define TIM3_BASE (D2_APB1PERIPH_BASE + 0x0400UL)
2255 #define TIM4_BASE (D2_APB1PERIPH_BASE + 0x0800UL)
2256 #define TIM5_BASE (D2_APB1PERIPH_BASE + 0x0C00UL)
2257 #define TIM6_BASE (D2_APB1PERIPH_BASE + 0x1000UL)
2258 #define TIM7_BASE (D2_APB1PERIPH_BASE + 0x1400UL)
2259 #define TIM12_BASE (D2_APB1PERIPH_BASE + 0x1800UL)
2260 #define TIM13_BASE (D2_APB1PERIPH_BASE + 0x1C00UL)
2261 #define TIM14_BASE (D2_APB1PERIPH_BASE + 0x2000UL)
2262 #define LPTIM1_BASE (D2_APB1PERIPH_BASE + 0x2400UL)
2263
2264 #define WWDG2_BASE (D2_APB1PERIPH_BASE + 0x2C00UL)
2265
2266 #define SPI2_BASE (D2_APB1PERIPH_BASE + 0x3800UL)
2267 #define SPI3_BASE (D2_APB1PERIPH_BASE + 0x3C00UL)
2268 #define SPDIFRX_BASE (D2_APB1PERIPH_BASE + 0x4000UL)
2269 #define USART2_BASE (D2_APB1PERIPH_BASE + 0x4400UL)
2270 #define USART3_BASE (D2_APB1PERIPH_BASE + 0x4800UL)
2271 #define UART4_BASE (D2_APB1PERIPH_BASE + 0x4C00UL)
2272 #define UART5_BASE (D2_APB1PERIPH_BASE + 0x5000UL)
2273 #define I2C1_BASE (D2_APB1PERIPH_BASE + 0x5400UL)
2274 #define I2C2_BASE (D2_APB1PERIPH_BASE + 0x5800UL)
2275 #define I2C3_BASE (D2_APB1PERIPH_BASE + 0x5C00UL)
2276 #define CEC_BASE (D2_APB1PERIPH_BASE + 0x6C00UL)
2277 #define DAC1_BASE (D2_APB1PERIPH_BASE + 0x7400UL)
2278 #define UART7_BASE (D2_APB1PERIPH_BASE + 0x7800UL)
2279 #define UART8_BASE (D2_APB1PERIPH_BASE + 0x7C00UL)
2280 #define CRS_BASE (D2_APB1PERIPH_BASE + 0x8400UL)
2281 #define SWPMI1_BASE (D2_APB1PERIPH_BASE + 0x8800UL)
2282 #define OPAMP_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2283 #define OPAMP1_BASE (D2_APB1PERIPH_BASE + 0x9000UL)
2284 #define OPAMP2_BASE (D2_APB1PERIPH_BASE + 0x9010UL)
2285 #define MDIOS_BASE (D2_APB1PERIPH_BASE + 0x9400UL)
2286 #define FDCAN1_BASE (D2_APB1PERIPH_BASE + 0xA000UL)
2287 #define FDCAN2_BASE (D2_APB1PERIPH_BASE + 0xA400UL)
2288 #define FDCAN_CCU_BASE (D2_APB1PERIPH_BASE + 0xA800UL)
2289 #define SRAMCAN_BASE (D2_APB1PERIPH_BASE + 0xAC00UL)
2290
2291 /*!< D2_APB2PERIPH peripherals */
2292
2293 #define TIM1_BASE (D2_APB2PERIPH_BASE + 0x0000UL)
2294 #define TIM8_BASE (D2_APB2PERIPH_BASE + 0x0400UL)
2295 #define USART1_BASE (D2_APB2PERIPH_BASE + 0x1000UL)
2296 #define USART6_BASE (D2_APB2PERIPH_BASE + 0x1400UL)
2297 #define SPI1_BASE (D2_APB2PERIPH_BASE + 0x3000UL)
2298 #define SPI4_BASE (D2_APB2PERIPH_BASE + 0x3400UL)
2299 #define TIM15_BASE (D2_APB2PERIPH_BASE + 0x4000UL)
2300 #define TIM16_BASE (D2_APB2PERIPH_BASE + 0x4400UL)
2301 #define TIM17_BASE (D2_APB2PERIPH_BASE + 0x4800UL)
2302 #define SPI5_BASE (D2_APB2PERIPH_BASE + 0x5000UL)
2303 #define SAI1_BASE (D2_APB2PERIPH_BASE + 0x5800UL)
2304 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2305 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2306 #define SAI2_BASE (D2_APB2PERIPH_BASE + 0x5C00UL)
2307 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2308 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2309 #define SAI3_BASE (D2_APB2PERIPH_BASE + 0x6000UL)
2310 #define SAI3_Block_A_BASE (SAI3_BASE + 0x004UL)
2311 #define SAI3_Block_B_BASE (SAI3_BASE + 0x024UL)
2312 #define DFSDM1_BASE (D2_APB2PERIPH_BASE + 0x7000UL)
2313 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2314 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2315 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2316 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2317 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2318 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2319 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2320 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2321 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2322 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2323 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2324 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2325 #define HRTIM1_BASE (D2_APB2PERIPH_BASE + 0x7400UL)
2326 #define HRTIM1_TIMA_BASE (HRTIM1_BASE + 0x00000080UL)
2327 #define HRTIM1_TIMB_BASE (HRTIM1_BASE + 0x00000100UL)
2328 #define HRTIM1_TIMC_BASE (HRTIM1_BASE + 0x00000180UL)
2329 #define HRTIM1_TIMD_BASE (HRTIM1_BASE + 0x00000200UL)
2330 #define HRTIM1_TIME_BASE (HRTIM1_BASE + 0x00000280UL)
2331 #define HRTIM1_COMMON_BASE (HRTIM1_BASE + 0x00000380UL)
2332
2333
2334 /*!< D3_APB1PERIPH peripherals */
2335 #define EXTI_BASE (D3_APB1PERIPH_BASE + 0x0000UL)
2336 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2337 #define EXTI_D2_BASE (EXTI_BASE + 0x00C0UL)
2338 #define SYSCFG_BASE (D3_APB1PERIPH_BASE + 0x0400UL)
2339 #define LPUART1_BASE (D3_APB1PERIPH_BASE + 0x0C00UL)
2340 #define SPI6_BASE (D3_APB1PERIPH_BASE + 0x1400UL)
2341 #define I2C4_BASE (D3_APB1PERIPH_BASE + 0x1C00UL)
2342 #define LPTIM2_BASE (D3_APB1PERIPH_BASE + 0x2400UL)
2343 #define LPTIM3_BASE (D3_APB1PERIPH_BASE + 0x2800UL)
2344 #define LPTIM4_BASE (D3_APB1PERIPH_BASE + 0x2C00UL)
2345 #define LPTIM5_BASE (D3_APB1PERIPH_BASE + 0x3000UL)
2346 #define COMP12_BASE (D3_APB1PERIPH_BASE + 0x3800UL)
2347 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
2348 #define COMP2_BASE (COMP12_BASE + 0x10UL)
2349 #define VREFBUF_BASE (D3_APB1PERIPH_BASE + 0x3C00UL)
2350 #define RTC_BASE (D3_APB1PERIPH_BASE + 0x4000UL)
2351 #define IWDG1_BASE (D3_APB1PERIPH_BASE + 0x4800UL)
2352
2353 #define IWDG2_BASE (D3_APB1PERIPH_BASE + 0x4C00UL)
2354
2355 #define SAI4_BASE (D3_APB1PERIPH_BASE + 0x5400UL)
2356 #define SAI4_Block_A_BASE (SAI4_BASE + 0x004UL)
2357 #define SAI4_Block_B_BASE (SAI4_BASE + 0x024UL)
2358
2359
2360
2361
2362 #define BDMA_Channel0_BASE (BDMA_BASE + 0x0008UL)
2363 #define BDMA_Channel1_BASE (BDMA_BASE + 0x001CUL)
2364 #define BDMA_Channel2_BASE (BDMA_BASE + 0x0030UL)
2365 #define BDMA_Channel3_BASE (BDMA_BASE + 0x0044UL)
2366 #define BDMA_Channel4_BASE (BDMA_BASE + 0x0058UL)
2367 #define BDMA_Channel5_BASE (BDMA_BASE + 0x006CUL)
2368 #define BDMA_Channel6_BASE (BDMA_BASE + 0x0080UL)
2369 #define BDMA_Channel7_BASE (BDMA_BASE + 0x0094UL)
2370
2371 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2372 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2373 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2374 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2375 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2376 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2377 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2378 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2379
2380 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2381 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2382 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2383 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2384 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2385 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2386 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2387 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2388
2389 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2390 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2391
2392 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2393 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2394 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2395 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2396 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2397 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2398 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2399 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2400
2401 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2402 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2403 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2404 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2405 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2406 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2407 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2408 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2409
2410 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2411 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2412 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2413 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2414 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2415 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2416 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2417 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2418 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2419 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2420 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2421 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2422 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2423 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2424 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2425 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2426
2427 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2428 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2429 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2430 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2431 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2432 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2433 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2434 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2435
2436 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2437 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2438
2439 /*!< FMC Banks registers base address */
2440 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2441 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2442 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2443 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2444 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2445
2446 /* Debug MCU registers base address */
2447 #define DBGMCU_BASE (0x5C001000UL)
2448
2449 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2450 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2451 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2452 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2453 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2454 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2455 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2456 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2457 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2458 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2459 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2460 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2461 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2462 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2463 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2464 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2465
2466 #define RAMECC1_Monitor1_BASE (RAMECC1_BASE + 0x20UL)
2467 #define RAMECC1_Monitor2_BASE (RAMECC1_BASE + 0x40UL)
2468 #define RAMECC1_Monitor3_BASE (RAMECC1_BASE + 0x60UL)
2469 #define RAMECC1_Monitor4_BASE (RAMECC1_BASE + 0x80UL)
2470 #define RAMECC1_Monitor5_BASE (RAMECC1_BASE + 0xA0UL)
2471
2472 #define RAMECC2_Monitor1_BASE (RAMECC2_BASE + 0x20UL)
2473 #define RAMECC2_Monitor2_BASE (RAMECC2_BASE + 0x40UL)
2474 #define RAMECC2_Monitor3_BASE (RAMECC2_BASE + 0x60UL)
2475 #define RAMECC2_Monitor4_BASE (RAMECC2_BASE + 0x80UL)
2476 #define RAMECC2_Monitor5_BASE (RAMECC2_BASE + 0xA0UL)
2477
2478 #define RAMECC3_Monitor1_BASE (RAMECC3_BASE + 0x20UL)
2479 #define RAMECC3_Monitor2_BASE (RAMECC3_BASE + 0x40UL)
2480
2481
2482 /**
2483 * @}
2484 */
2485
2486 /** @addtogroup Peripheral_declaration
2487 * @{
2488 */
2489 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2490 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2491 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2492 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2493 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2494 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2495 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2496 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2497 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2498 #define RTC ((RTC_TypeDef *) RTC_BASE)
2499 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2500
2501 #define WWDG2 ((WWDG_TypeDef *) WWDG2_BASE)
2502 #define IWDG2 ((IWDG_TypeDef *) IWDG2_BASE)
2503
2504 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2505 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2506 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2507 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2508 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2509 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2510 #define USART2 ((USART_TypeDef *) USART2_BASE)
2511 #define USART3 ((USART_TypeDef *) USART3_BASE)
2512 #define USART6 ((USART_TypeDef *) USART6_BASE)
2513 #define UART7 ((USART_TypeDef *) UART7_BASE)
2514 #define UART8 ((USART_TypeDef *) UART8_BASE)
2515 #define CRS ((CRS_TypeDef *) CRS_BASE)
2516 #define UART4 ((USART_TypeDef *) UART4_BASE)
2517 #define UART5 ((USART_TypeDef *) UART5_BASE)
2518 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2519 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2520 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2521 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2522 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2523 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2524 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2525 #define CEC ((CEC_TypeDef *) CEC_BASE)
2526 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2527 #define PWR ((PWR_TypeDef *) PWR_BASE)
2528 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2529 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2530 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2531 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2532 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2533 #define LPTIM4 ((LPTIM_TypeDef *) LPTIM4_BASE)
2534 #define LPTIM5 ((LPTIM_TypeDef *) LPTIM5_BASE)
2535
2536 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2537 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2538 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2539 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2540 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2541 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2542 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2543 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2544
2545
2546 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2547 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2548 #define EXTI_D2 ((EXTI_Core_TypeDef *) EXTI_D2_BASE)
2549 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2550 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2551 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2552 #define USART1 ((USART_TypeDef *) USART1_BASE)
2553 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2554 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2555 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2556 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2557 #define HRTIM1 ((HRTIM_TypeDef *) HRTIM1_BASE)
2558 #define HRTIM1_TIMA ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMA_BASE)
2559 #define HRTIM1_TIMB ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMB_BASE)
2560 #define HRTIM1_TIMC ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMC_BASE)
2561 #define HRTIM1_TIMD ((HRTIM_Timerx_TypeDef *) HRTIM1_TIMD_BASE)
2562 #define HRTIM1_TIME ((HRTIM_Timerx_TypeDef *) HRTIM1_TIME_BASE)
2563 #define HRTIM1_COMMON ((HRTIM_Common_TypeDef *) HRTIM1_COMMON_BASE)
2564 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2565 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2566 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2567 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2568 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2569 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2570 #define SAI3 ((SAI_TypeDef *) SAI3_BASE)
2571 #define SAI3_Block_A ((SAI_Block_TypeDef *)SAI3_Block_A_BASE)
2572 #define SAI3_Block_B ((SAI_Block_TypeDef *)SAI3_Block_B_BASE)
2573 #define SAI4 ((SAI_TypeDef *) SAI4_BASE)
2574 #define SAI4_Block_A ((SAI_Block_TypeDef *)SAI4_Block_A_BASE)
2575 #define SAI4_Block_B ((SAI_Block_TypeDef *)SAI4_Block_B_BASE)
2576
2577 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2578 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2579 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2580 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2581 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2582 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2583 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2584 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2585 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2586 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2587 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2588 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2589 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2590 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2591 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2592 #define RCC ((RCC_TypeDef *) RCC_BASE)
2593 #define RCC_C1 ((RCC_Core_TypeDef *) RCC_C1_BASE)
2594 #define RCC_C2 ((RCC_Core_TypeDef *) RCC_C2_BASE)
2595
2596 #define ART ((ART_TypeDef *) ART_BASE)
2597 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2598 #define CRC ((CRC_TypeDef *) CRC_BASE)
2599
2600 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2601 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2602 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2603 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2604 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2605 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2606 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2607 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2608 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2609 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2610 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2611
2612 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2613 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2614 #define ADC3 ((ADC_TypeDef *) ADC3_BASE)
2615 #define ADC3_COMMON ((ADC_Common_TypeDef *) ADC3_COMMON_BASE)
2616 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2617
2618 #define RNG ((RNG_TypeDef *) RNG_BASE)
2619 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2620 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2621
2622 #define BDMA ((BDMA_TypeDef *) BDMA_BASE)
2623 #define BDMA_Channel0 ((BDMA_Channel_TypeDef *) BDMA_Channel0_BASE)
2624 #define BDMA_Channel1 ((BDMA_Channel_TypeDef *) BDMA_Channel1_BASE)
2625 #define BDMA_Channel2 ((BDMA_Channel_TypeDef *) BDMA_Channel2_BASE)
2626 #define BDMA_Channel3 ((BDMA_Channel_TypeDef *) BDMA_Channel3_BASE)
2627 #define BDMA_Channel4 ((BDMA_Channel_TypeDef *) BDMA_Channel4_BASE)
2628 #define BDMA_Channel5 ((BDMA_Channel_TypeDef *) BDMA_Channel5_BASE)
2629 #define BDMA_Channel6 ((BDMA_Channel_TypeDef *) BDMA_Channel6_BASE)
2630 #define BDMA_Channel7 ((BDMA_Channel_TypeDef *) BDMA_Channel7_BASE)
2631
2632 #define RAMECC1 ((RAMECC_TypeDef *)RAMECC1_BASE)
2633 #define RAMECC1_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor1_BASE)
2634 #define RAMECC1_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor2_BASE)
2635 #define RAMECC1_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor3_BASE)
2636 #define RAMECC1_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor4_BASE)
2637 #define RAMECC1_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC1_Monitor5_BASE)
2638
2639 #define RAMECC2 ((RAMECC_TypeDef *)RAMECC2_BASE)
2640 #define RAMECC2_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor1_BASE)
2641 #define RAMECC2_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor2_BASE)
2642 #define RAMECC2_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor3_BASE)
2643 #define RAMECC2_Monitor4 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor4_BASE)
2644 #define RAMECC2_Monitor5 ((RAMECC_MonitorTypeDef *)RAMECC2_Monitor5_BASE)
2645
2646 #define RAMECC3 ((RAMECC_TypeDef *)RAMECC3_BASE)
2647 #define RAMECC3_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor1_BASE)
2648 #define RAMECC3_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC3_Monitor2_BASE)
2649
2650 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2651 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2652 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2653 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2654 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2655 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2656 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2657 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2658 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2659
2660
2661 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2662 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2663 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2664 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2665 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2666 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2667 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2668 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2669
2670 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2671 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2672
2673 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2674 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2675 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2676 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2677 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2678 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2679 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2680 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2681 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2682
2683 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2684 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2685 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2686 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2687 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2688 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2689 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2690 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2691 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2692
2693
2694 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2695 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2696 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2697 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2698 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2699 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2700 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2701 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2702 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2703 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2704 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2705 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2706 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2707 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2708 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2709 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2710 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2711
2712 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2713 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2714 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2715 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2716 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2717 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2718 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2719 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2720
2721 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2722 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2723
2724
2725 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2726 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2727 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2728 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2729 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2730
2731
2732 #define QUADSPI ((QUADSPI_TypeDef *) QSPI_R_BASE)
2733 #define DLYB_QUADSPI ((DLYB_TypeDef *) DLYB_QSPI_BASE)
2734 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2735 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2736
2737 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2738
2739 #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2740 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2741 #if defined(CORE_CM4)
2742 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x110UL))
2743 #else /* CORE_CM7 */
2744 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2745 #endif /* CORE_CM4 */
2746
2747 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2748 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2749 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2750 #define DSI ((DSI_TypeDef *)DSI_BASE)
2751
2752 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2753
2754 #define ETH ((ETH_TypeDef *)ETH_BASE)
2755 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2756 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2757 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2758 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2759 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2760 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2761 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2762 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2763 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2764 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2765 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2766 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2767 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2768 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2769 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2770 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2771 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2772
2773
2774 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2775 #define USB2_OTG_FS ((USB_OTG_GlobalTypeDef *) USB2_OTG_FS_PERIPH_BASE)
2776
2777 /* Legacy defines */
2778 #define USB_OTG_HS USB1_OTG_HS
2779 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2780 #define USB_OTG_FS USB2_OTG_FS
2781 #define USB_OTG_FS_PERIPH_BASE USB2_OTG_FS_PERIPH_BASE
2782
2783 /**
2784 * @}
2785 */
2786
2787 /** @addtogroup Exported_constants
2788 * @{
2789 */
2790
2791 /** @addtogroup Peripheral_Registers_Bits_Definition
2792 * @{
2793 */
2794
2795 /******************************************************************************/
2796 /* Peripheral Registers_Bits_Definition */
2797 /******************************************************************************/
2798
2799 /******************************************************************************/
2800 /* */
2801 /* Analog to Digital Converter */
2802 /* */
2803 /******************************************************************************/
2804 /******************************* ADC VERSION ********************************/
2805 #define ADC_VER_V5_X
2806 /******************** Bit definition for ADC_ISR register ********************/
2807 #define ADC_ISR_ADRDY_Pos (0U)
2808 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2809 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2810 #define ADC_ISR_EOSMP_Pos (1U)
2811 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2812 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2813 #define ADC_ISR_EOC_Pos (2U)
2814 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2815 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2816 #define ADC_ISR_EOS_Pos (3U)
2817 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2818 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2819 #define ADC_ISR_OVR_Pos (4U)
2820 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2821 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2822 #define ADC_ISR_JEOC_Pos (5U)
2823 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2824 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2825 #define ADC_ISR_JEOS_Pos (6U)
2826 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2827 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2828 #define ADC_ISR_AWD1_Pos (7U)
2829 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2830 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2831 #define ADC_ISR_AWD2_Pos (8U)
2832 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2833 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2834 #define ADC_ISR_AWD3_Pos (9U)
2835 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2836 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2837 #define ADC_ISR_JQOVF_Pos (10U)
2838 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2839 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2840
2841 /******************** Bit definition for ADC_IER register ********************/
2842 #define ADC_IER_ADRDYIE_Pos (0U)
2843 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2844 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2845 #define ADC_IER_EOSMPIE_Pos (1U)
2846 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2847 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2848 #define ADC_IER_EOCIE_Pos (2U)
2849 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2850 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2851 #define ADC_IER_EOSIE_Pos (3U)
2852 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2853 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2854 #define ADC_IER_OVRIE_Pos (4U)
2855 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2856 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2857 #define ADC_IER_JEOCIE_Pos (5U)
2858 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2859 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2860 #define ADC_IER_JEOSIE_Pos (6U)
2861 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2862 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2863 #define ADC_IER_AWD1IE_Pos (7U)
2864 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2865 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2866 #define ADC_IER_AWD2IE_Pos (8U)
2867 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2868 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2869 #define ADC_IER_AWD3IE_Pos (9U)
2870 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2871 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2872 #define ADC_IER_JQOVFIE_Pos (10U)
2873 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2874 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2875
2876 /******************** Bit definition for ADC_CR register ********************/
2877 #define ADC_CR_ADEN_Pos (0U)
2878 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2879 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2880 #define ADC_CR_ADDIS_Pos (1U)
2881 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2882 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2883 #define ADC_CR_ADSTART_Pos (2U)
2884 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2885 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2886 #define ADC_CR_JADSTART_Pos (3U)
2887 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2888 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2889 #define ADC_CR_ADSTP_Pos (4U)
2890 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2891 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2892 #define ADC_CR_JADSTP_Pos (5U)
2893 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2894 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2895 #define ADC_CR_BOOST_Pos (8U)
2896 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2897 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2898 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2899 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2900 #define ADC_CR_ADCALLIN_Pos (16U)
2901 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2902 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2903 #define ADC_CR_LINCALRDYW1_Pos (22U)
2904 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2905 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2906 #define ADC_CR_LINCALRDYW2_Pos (23U)
2907 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2908 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2909 #define ADC_CR_LINCALRDYW3_Pos (24U)
2910 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2911 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2912 #define ADC_CR_LINCALRDYW4_Pos (25U)
2913 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2914 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2915 #define ADC_CR_LINCALRDYW5_Pos (26U)
2916 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2917 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2918 #define ADC_CR_LINCALRDYW6_Pos (27U)
2919 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2920 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2921 #define ADC_CR_ADVREGEN_Pos (28U)
2922 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2923 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2924 #define ADC_CR_DEEPPWD_Pos (29U)
2925 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2926 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2927 #define ADC_CR_ADCALDIF_Pos (30U)
2928 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2929 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2930 #define ADC_CR_ADCAL_Pos (31U)
2931 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2932 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2933
2934 /******************** Bit definition for ADC_CFGR register ********************/
2935 #define ADC_CFGR_DMNGT_Pos (0U)
2936 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2937 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2938 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2939 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2940
2941 #define ADC_CFGR_RES_Pos (2U)
2942 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2943 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2944 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2945 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2946 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2947
2948 #define ADC_CFGR_EXTSEL_Pos (5U)
2949 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2950 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2951 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2952 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2953 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2954 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2955 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2956
2957 #define ADC_CFGR_EXTEN_Pos (10U)
2958 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2959 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2960 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2961 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2962
2963 #define ADC_CFGR_OVRMOD_Pos (12U)
2964 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2965 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2966 #define ADC_CFGR_CONT_Pos (13U)
2967 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2968 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2969 #define ADC_CFGR_AUTDLY_Pos (14U)
2970 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2971 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2972
2973 #define ADC_CFGR_DISCEN_Pos (16U)
2974 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2975 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2976
2977 #define ADC_CFGR_DISCNUM_Pos (17U)
2978 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2979 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2980 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2981 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2982 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2983
2984 #define ADC_CFGR_JDISCEN_Pos (20U)
2985 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2986 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2987 #define ADC_CFGR_JQM_Pos (21U)
2988 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2989 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2990 #define ADC_CFGR_AWD1SGL_Pos (22U)
2991 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2992 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2993 #define ADC_CFGR_AWD1EN_Pos (23U)
2994 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2995 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2996 #define ADC_CFGR_JAWD1EN_Pos (24U)
2997 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2998 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2999 #define ADC_CFGR_JAUTO_Pos (25U)
3000 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
3001 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
3002
3003 #define ADC_CFGR_AWD1CH_Pos (26U)
3004 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
3005 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
3006 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
3007 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
3008 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
3009 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
3010 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
3011
3012 #define ADC_CFGR_JQDIS_Pos (31U)
3013 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
3014 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
3015
3016 /******************** Bit definition for ADC_CFGR2 register ********************/
3017 #define ADC_CFGR2_ROVSE_Pos (0U)
3018 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
3019 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
3020 #define ADC_CFGR2_JOVSE_Pos (1U)
3021 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
3022 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
3023
3024 #define ADC_CFGR2_OVSS_Pos (5U)
3025 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
3026 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
3027 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
3028 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
3029 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
3030 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
3031
3032 #define ADC_CFGR2_TROVS_Pos (9U)
3033 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
3034 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
3035 #define ADC_CFGR2_ROVSM_Pos (10U)
3036 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
3037 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
3038
3039 #define ADC_CFGR2_RSHIFT1_Pos (11U)
3040 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
3041 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
3042 #define ADC_CFGR2_RSHIFT2_Pos (12U)
3043 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
3044 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
3045 #define ADC_CFGR2_RSHIFT3_Pos (13U)
3046 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
3047 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
3048 #define ADC_CFGR2_RSHIFT4_Pos (14U)
3049 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
3050 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
3051
3052 #define ADC_CFGR2_OVSR_Pos (16U)
3053 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
3054 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
3055 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
3056 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
3057 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
3058 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
3059 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
3060 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
3061 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
3062 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
3063 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
3064 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
3065
3066 #define ADC_CFGR2_LSHIFT_Pos (28U)
3067 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
3068 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
3069 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
3070 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
3071 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
3072 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
3073
3074 /******************** Bit definition for ADC_SMPR1 register ********************/
3075 #define ADC_SMPR1_SMP0_Pos (0U)
3076 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
3077 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
3078 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
3079 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
3080 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
3081
3082 #define ADC_SMPR1_SMP1_Pos (3U)
3083 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
3084 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
3085 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
3086 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
3087 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
3088
3089 #define ADC_SMPR1_SMP2_Pos (6U)
3090 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
3091 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
3092 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
3093 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
3094 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
3095
3096 #define ADC_SMPR1_SMP3_Pos (9U)
3097 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
3098 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
3099 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
3100 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
3101 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
3102
3103 #define ADC_SMPR1_SMP4_Pos (12U)
3104 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
3105 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
3106 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
3107 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
3108 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
3109
3110 #define ADC_SMPR1_SMP5_Pos (15U)
3111 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
3112 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
3113 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
3114 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
3115 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
3116
3117 #define ADC_SMPR1_SMP6_Pos (18U)
3118 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
3119 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
3120 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
3121 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
3122 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
3123
3124 #define ADC_SMPR1_SMP7_Pos (21U)
3125 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
3126 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
3127 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
3128 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
3129 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
3130
3131 #define ADC_SMPR1_SMP8_Pos (24U)
3132 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
3133 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
3134 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
3135 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
3136 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
3137
3138 #define ADC_SMPR1_SMP9_Pos (27U)
3139 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
3140 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
3141 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
3142 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
3143 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
3144
3145 /******************** Bit definition for ADC_SMPR2 register ********************/
3146 #define ADC_SMPR2_SMP10_Pos (0U)
3147 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
3148 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
3149 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
3150 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
3151 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
3152
3153 #define ADC_SMPR2_SMP11_Pos (3U)
3154 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
3155 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
3156 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
3157 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
3158 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
3159
3160 #define ADC_SMPR2_SMP12_Pos (6U)
3161 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
3162 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
3163 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
3164 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
3165 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
3166
3167 #define ADC_SMPR2_SMP13_Pos (9U)
3168 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
3169 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
3170 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
3171 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
3172 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
3173
3174 #define ADC_SMPR2_SMP14_Pos (12U)
3175 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
3176 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3177 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3178 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3179 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3180
3181 #define ADC_SMPR2_SMP15_Pos (15U)
3182 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3183 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3184 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3185 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3186 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3187
3188 #define ADC_SMPR2_SMP16_Pos (18U)
3189 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3190 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3191 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3192 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3193 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3194
3195 #define ADC_SMPR2_SMP17_Pos (21U)
3196 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3197 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3198 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3199 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3200 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3201
3202 #define ADC_SMPR2_SMP18_Pos (24U)
3203 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3204 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3205 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3206 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3207 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3208
3209 #define ADC_SMPR2_SMP19_Pos (27U)
3210 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3211 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3212 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3213 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3214 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3215
3216 /******************** Bit definition for ADC_PCSEL register ********************/
3217 #define ADC_PCSEL_PCSEL_Pos (0U)
3218 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3219 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3220 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3221 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3222 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3223 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3224 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3225 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3226 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3227 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3228 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3229 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3230 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3231 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3232 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3233 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3234 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3235 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3236 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3237 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3238 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3239 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3240
3241 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3242 #define ADC_LTR_LT_Pos (0U)
3243 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3244 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3245
3246 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3247 #define ADC_HTR_HT_Pos (0U)
3248 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3249 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3250
3251
3252 /******************** Bit definition for ADC_SQR1 register ********************/
3253 #define ADC_SQR1_L_Pos (0U)
3254 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3255 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3256 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3257 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3258 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3259 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3260
3261 #define ADC_SQR1_SQ1_Pos (6U)
3262 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3263 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3264 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3265 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3266 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3267 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3268 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3269
3270 #define ADC_SQR1_SQ2_Pos (12U)
3271 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3272 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3273 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3274 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3275 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3276 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3277 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3278
3279 #define ADC_SQR1_SQ3_Pos (18U)
3280 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3281 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3282 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3283 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3284 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3285 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3286 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3287
3288 #define ADC_SQR1_SQ4_Pos (24U)
3289 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3290 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3291 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3292 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3293 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3294 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3295 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3296
3297 /******************** Bit definition for ADC_SQR2 register ********************/
3298 #define ADC_SQR2_SQ5_Pos (0U)
3299 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3300 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3301 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3302 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3303 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3304 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3305 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3306
3307 #define ADC_SQR2_SQ6_Pos (6U)
3308 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3309 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3310 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3311 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3312 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3313 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3314 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3315
3316 #define ADC_SQR2_SQ7_Pos (12U)
3317 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3318 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3319 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3320 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3321 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3322 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3323 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3324
3325 #define ADC_SQR2_SQ8_Pos (18U)
3326 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3327 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3328 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3329 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3330 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3331 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3332 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3333
3334 #define ADC_SQR2_SQ9_Pos (24U)
3335 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3336 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3337 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3338 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3339 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3340 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3341 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3342
3343 /******************** Bit definition for ADC_SQR3 register ********************/
3344 #define ADC_SQR3_SQ10_Pos (0U)
3345 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3346 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3347 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3348 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3349 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3350 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3351 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3352
3353 #define ADC_SQR3_SQ11_Pos (6U)
3354 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3355 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3356 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3357 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3358 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3359 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3360 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3361
3362 #define ADC_SQR3_SQ12_Pos (12U)
3363 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3364 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3365 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3366 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3367 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3368 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3369 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3370
3371 #define ADC_SQR3_SQ13_Pos (18U)
3372 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3373 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3374 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3375 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3376 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3377 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3378 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3379
3380 #define ADC_SQR3_SQ14_Pos (24U)
3381 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3382 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3383 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3384 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3385 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3386 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3387 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3388
3389 /******************** Bit definition for ADC_SQR4 register ********************/
3390 #define ADC_SQR4_SQ15_Pos (0U)
3391 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3392 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3393 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3394 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3395 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3396 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3397 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3398
3399 #define ADC_SQR4_SQ16_Pos (6U)
3400 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3401 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3402 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3403 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3404 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3405 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3406 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3407 /******************** Bit definition for ADC_DR register ********************/
3408 #define ADC_DR_RDATA_Pos (0U)
3409 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3410 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3411
3412 /******************** Bit definition for ADC_JSQR register ********************/
3413 #define ADC_JSQR_JL_Pos (0U)
3414 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3415 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3416 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3417 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3418
3419 #define ADC_JSQR_JEXTSEL_Pos (2U)
3420 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3421 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3422 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3423 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3424 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3425 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3426 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3427
3428 #define ADC_JSQR_JEXTEN_Pos (7U)
3429 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3430 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3431 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3432 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3433
3434 #define ADC_JSQR_JSQ1_Pos (9U)
3435 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3436 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3437 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3438 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3439 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3440 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3441 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3442
3443 #define ADC_JSQR_JSQ2_Pos (15U)
3444 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3445 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3446 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3447 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3448 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3449 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3450 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3451
3452 #define ADC_JSQR_JSQ3_Pos (21U)
3453 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3454 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3455 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3456 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3457 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3458 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3459 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3460
3461 #define ADC_JSQR_JSQ4_Pos (27U)
3462 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3463 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3464 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3465 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3466 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3467 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3468 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3469
3470 /******************** Bit definition for ADC_OFR1 register ********************/
3471 #define ADC_OFR1_OFFSET1_Pos (0U)
3472 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3473 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3474 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3475 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3476 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3477 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3478 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3479 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3480 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3481 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3482 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3483 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3484 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3485 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3486 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3487 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3488 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3489 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3490 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3491 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3492 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3493 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3494 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3495 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3496 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3497 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3498 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3499 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3500
3501 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
3502 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3503 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3504 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3505 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3506 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3507 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3508 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3509
3510 #define ADC_OFR1_SSATE_Pos (31U)
3511 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3512 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3513
3514
3515 /******************** Bit definition for ADC_OFR2 register ********************/
3516 #define ADC_OFR2_OFFSET2_Pos (0U)
3517 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3518 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3519 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3520 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3521 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3522 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3523 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3524 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3525 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3526 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3527 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3528 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3529 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3530 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3531 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3532 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3533 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3534 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3535 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3536 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3537 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3538 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3539 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3540 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3541 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3542 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3543 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3544 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3545
3546 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
3547 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3548 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3549 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3550 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3551 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3552 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3553 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3554
3555 #define ADC_OFR2_SSATE_Pos (31U)
3556 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3557 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3558
3559
3560 /******************** Bit definition for ADC_OFR3 register ********************/
3561 #define ADC_OFR3_OFFSET3_Pos (0U)
3562 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3563 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3564 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3565 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3566 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3567 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3568 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3569 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3570 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3571 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3572 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3573 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3574 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3575 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3576 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3577 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3578 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3579 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3580 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3581 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3582 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3583 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3584 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3585 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3586 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3587 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3588 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3589 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3590
3591 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
3592 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3593 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3594 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3595 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3596 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3597 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3598 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3599
3600 #define ADC_OFR3_SSATE_Pos (31U)
3601 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3602 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3603
3604
3605 /******************** Bit definition for ADC_OFR4 register ********************/
3606 #define ADC_OFR4_OFFSET4_Pos (0U)
3607 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3608 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3609 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3610 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3611 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3612 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3613 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3614 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3615 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3616 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3617 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3618 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3619 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3620 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3621 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3622 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3623 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3624 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3625 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3626 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3627 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3628 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3629 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3630 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3631 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3632 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3633 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3634 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3635
3636 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
3637 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3638 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3639 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3640 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3641 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3642 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3643 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3644
3645 #define ADC_OFR4_SSATE_Pos (31U)
3646 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3647 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3648
3649
3650 /******************** Bit definition for ADC_JDR1 register ********************/
3651 #define ADC_JDR1_JDATA_Pos (0U)
3652 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3653 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3654 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3655 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3656 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3657 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3658 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3659 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3660 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3661 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3662 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3663 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3664 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3665 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3666 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3667 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3668 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3669 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3670 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3671 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3672 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3673 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3674 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3675 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3676 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3677 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3678 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3679 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3680 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3681 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3682 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3683 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3684 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3685 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3686
3687 /******************** Bit definition for ADC_JDR2 register ********************/
3688 #define ADC_JDR2_JDATA_Pos (0U)
3689 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3690 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3691 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3692 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3693 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3694 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3695 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3696 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3697 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3698 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3699 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3700 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3701 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3702 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3703 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3704 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3705 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3706 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3707 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3708 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3709 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3710 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3711 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3712 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3713 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3714 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3715 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3716 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3717 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3718 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3719 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3720 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3721 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3722 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3723
3724 /******************** Bit definition for ADC_JDR3 register ********************/
3725 #define ADC_JDR3_JDATA_Pos (0U)
3726 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3727 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3728 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3729 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3730 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3731 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3732 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3733 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3734 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3735 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3736 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3737 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3738 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3739 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3740 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3741 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3742 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3743 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3744 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3745 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3746 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3747 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3748 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3749 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3750 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3751 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3752 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3753 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3754 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3755 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3756 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3757 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3758 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3759 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3760
3761 /******************** Bit definition for ADC_JDR4 register ********************/
3762 #define ADC_JDR4_JDATA_Pos (0U)
3763 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3764 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3765 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3766 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3767 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3768 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3769 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3770 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3771 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3772 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3773 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3774 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3775 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3776 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3777 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3778 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3779 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3780 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3781 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3782 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3783 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3784 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3785 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3786 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3787 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3788 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3789 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3790 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3791 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3792 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3793 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3794 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3795 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3796 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3797
3798 /******************** Bit definition for ADC_AWD2CR register ********************/
3799 #define ADC_AWD2CR_AWD2CH_Pos (0U)
3800 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3801 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3802 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3803 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3804 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3805 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3806 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3807 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3808 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3809 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3810 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3811 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3812 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3813 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3814 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3815 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3816 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3817 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3818 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3819 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3820 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3821 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3822
3823 /******************** Bit definition for ADC_AWD3CR register ********************/
3824 #define ADC_AWD3CR_AWD3CH_Pos (0U)
3825 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3826 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3827 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3828 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3829 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3830 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3831 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3832 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3833 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3834 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3835 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3836 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3837 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3838 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3839 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3840 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3841 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3842 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3843 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3844 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3845 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3846 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3847
3848 /******************** Bit definition for ADC_DIFSEL register ********************/
3849 #define ADC_DIFSEL_DIFSEL_Pos (0U)
3850 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3851 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3852 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3853 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3854 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3855 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3856 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3857 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3858 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3859 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3860 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3861 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3862 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3863 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3864 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3865 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3866 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3867 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3868 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3869 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3870 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3871 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3872
3873 /******************** Bit definition for ADC_CALFACT register ********************/
3874 #define ADC_CALFACT_CALFACT_S_Pos (0U)
3875 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3876 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3877 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3878 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3879 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3880 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3881 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3882 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3883 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3884 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3885 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3886 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3887 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3888 #define ADC_CALFACT_CALFACT_D_Pos (16U)
3889 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3890 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3891 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3892 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3893 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3894 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3895 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3896 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3897 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3898 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3899 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3900 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3901 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3902
3903 /******************** Bit definition for ADC_CALFACT2 register ********************/
3904 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
3905 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3906 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3907 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3908 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3909 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3910 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3911 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3912 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3913 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3914 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3915 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3916 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3917 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3918 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3919 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3920 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3921 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3922 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3923 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3924 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3925 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3926 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3927 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3928 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3929 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3930 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3931 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3932 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3933 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3934 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3935 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3936 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3937
3938 /************************* ADC Common registers *****************************/
3939 /******************** Bit definition for ADC_CSR register ********************/
3940 #define ADC_CSR_ADRDY_MST_Pos (0U)
3941 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3942 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3943 #define ADC_CSR_EOSMP_MST_Pos (1U)
3944 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3945 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3946 #define ADC_CSR_EOC_MST_Pos (2U)
3947 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3948 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3949 #define ADC_CSR_EOS_MST_Pos (3U)
3950 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3951 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3952 #define ADC_CSR_OVR_MST_Pos (4U)
3953 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3954 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3955 #define ADC_CSR_JEOC_MST_Pos (5U)
3956 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3957 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3958 #define ADC_CSR_JEOS_MST_Pos (6U)
3959 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3960 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3961 #define ADC_CSR_AWD1_MST_Pos (7U)
3962 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3963 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3964 #define ADC_CSR_AWD2_MST_Pos (8U)
3965 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3966 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3967 #define ADC_CSR_AWD3_MST_Pos (9U)
3968 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3969 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3970 #define ADC_CSR_JQOVF_MST_Pos (10U)
3971 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3972 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3973 #define ADC_CSR_ADRDY_SLV_Pos (16U)
3974 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3975 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3976 #define ADC_CSR_EOSMP_SLV_Pos (17U)
3977 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3978 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3979 #define ADC_CSR_EOC_SLV_Pos (18U)
3980 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3981 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3982 #define ADC_CSR_EOS_SLV_Pos (19U)
3983 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3984 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3985 #define ADC_CSR_OVR_SLV_Pos (20U)
3986 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3987 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3988 #define ADC_CSR_JEOC_SLV_Pos (21U)
3989 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3990 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3991 #define ADC_CSR_JEOS_SLV_Pos (22U)
3992 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3993 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3994 #define ADC_CSR_AWD1_SLV_Pos (23U)
3995 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3996 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3997 #define ADC_CSR_AWD2_SLV_Pos (24U)
3998 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3999 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
4000 #define ADC_CSR_AWD3_SLV_Pos (25U)
4001 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
4002 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
4003 #define ADC_CSR_JQOVF_SLV_Pos (26U)
4004 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
4005 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
4006
4007 /******************** Bit definition for ADC_CCR register ********************/
4008 #define ADC_CCR_DUAL_Pos (0U)
4009 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
4010 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
4011 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
4012 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
4013 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
4014 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
4015 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
4016
4017 #define ADC_CCR_DELAY_Pos (8U)
4018 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
4019 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
4020 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
4021 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
4022 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
4023 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
4024
4025
4026 #define ADC_CCR_DAMDF_Pos (14U)
4027 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
4028 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
4029 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
4030 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
4031
4032 #define ADC_CCR_CKMODE_Pos (16U)
4033 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
4034 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
4035 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
4036 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
4037
4038 #define ADC_CCR_PRESC_Pos (18U)
4039 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
4040 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
4041 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
4042 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
4043 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
4044 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
4045
4046 #define ADC_CCR_VREFEN_Pos (22U)
4047 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
4048 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
4049 #define ADC_CCR_TSEN_Pos (23U)
4050 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
4051 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
4052 #define ADC_CCR_VBATEN_Pos (24U)
4053 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
4054 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
4055
4056 /******************** Bit definition for ADC_CDR register *******************/
4057 #define ADC_CDR_RDATA_MST_Pos (0U)
4058 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
4059 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
4060
4061 #define ADC_CDR_RDATA_SLV_Pos (16U)
4062 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
4063 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
4064
4065 /******************** Bit definition for ADC_CDR2 register ******************/
4066 #define ADC_CDR2_RDATA_ALT_Pos (0U)
4067 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
4068 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
4069
4070 /******************************************************************************/
4071 /* */
4072 /* ART accelerator */
4073 /* */
4074 /******************************************************************************/
4075 /******************* Bit definition for ART_CTR register ********************/
4076 #define ART_CTR_EN_Pos (0U)
4077 #define ART_CTR_EN_Msk (0x1UL << ART_CTR_EN_Pos) /*!< 0x00000001 */
4078 #define ART_CTR_EN ART_CTR_EN_Msk /*!< Cache enable*/
4079
4080 #define ART_CTR_PCACHEADDR_Pos (8U)
4081 #define ART_CTR_PCACHEADDR_Msk (0xFFFUL << ART_CTR_PCACHEADDR_Pos) /*!< 0x000FFF00 */
4082 #define ART_CTR_PCACHEADDR ART_CTR_PCACHEADDR_Msk /*!< Cacheable page index */
4083
4084 /******************************************************************************/
4085 /* */
4086 /* VREFBUF */
4087 /* */
4088 /******************************************************************************/
4089 /******************* Bit definition for VREFBUF_CSR register ****************/
4090 #define VREFBUF_CSR_ENVR_Pos (0U)
4091 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
4092 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
4093 #define VREFBUF_CSR_HIZ_Pos (1U)
4094 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
4095 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
4096 #define VREFBUF_CSR_VRR_Pos (3U)
4097 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
4098 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
4099 #define VREFBUF_CSR_VRS_Pos (4U)
4100 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
4101 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
4102
4103 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
4104 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
4105 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
4106 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
4107 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
4108 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
4109 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
4110 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
4111 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
4112 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
4113
4114 /******************* Bit definition for VREFBUF_CCR register ****************/
4115 #define VREFBUF_CCR_TRIM_Pos (0U)
4116 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
4117 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
4118
4119 /******************************************************************************/
4120 /* */
4121 /* Flexible Datarate Controller Area Network */
4122 /* */
4123 /******************************************************************************/
4124 /*!<FDCAN control and status registers */
4125 /***************** Bit definition for FDCAN_CREL register *******************/
4126 #define FDCAN_CREL_DAY_Pos (0U)
4127 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
4128 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
4129 #define FDCAN_CREL_MON_Pos (8U)
4130 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
4131 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
4132 #define FDCAN_CREL_YEAR_Pos (16U)
4133 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
4134 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
4135 #define FDCAN_CREL_SUBSTEP_Pos (20U)
4136 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
4137 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
4138 #define FDCAN_CREL_STEP_Pos (24U)
4139 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
4140 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
4141 #define FDCAN_CREL_REL_Pos (28U)
4142 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
4143 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
4144
4145 /***************** Bit definition for FDCAN_ENDN register *******************/
4146 #define FDCAN_ENDN_ETV_Pos (0U)
4147 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
4148 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
4149
4150 /***************** Bit definition for FDCAN_DBTP register *******************/
4151 #define FDCAN_DBTP_DSJW_Pos (0U)
4152 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
4153 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
4154 #define FDCAN_DBTP_DTSEG2_Pos (4U)
4155 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
4156 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
4157 #define FDCAN_DBTP_DTSEG1_Pos (8U)
4158 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
4159 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
4160 #define FDCAN_DBTP_DBRP_Pos (16U)
4161 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
4162 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
4163 #define FDCAN_DBTP_TDC_Pos (23U)
4164 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
4165 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
4166
4167 /***************** Bit definition for FDCAN_TEST register *******************/
4168 #define FDCAN_TEST_LBCK_Pos (4U)
4169 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
4170 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
4171 #define FDCAN_TEST_TX_Pos (5U)
4172 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
4173 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
4174 #define FDCAN_TEST_RX_Pos (7U)
4175 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
4176 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
4177
4178 /***************** Bit definition for FDCAN_RWD register ********************/
4179 #define FDCAN_RWD_WDC_Pos (0U)
4180 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
4181 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
4182 #define FDCAN_RWD_WDV_Pos (8U)
4183 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
4184 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
4185
4186 /***************** Bit definition for FDCAN_CCCR register ********************/
4187 #define FDCAN_CCCR_INIT_Pos (0U)
4188 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
4189 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4190 #define FDCAN_CCCR_CCE_Pos (1U)
4191 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4192 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4193 #define FDCAN_CCCR_ASM_Pos (2U)
4194 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4195 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4196 #define FDCAN_CCCR_CSA_Pos (3U)
4197 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4198 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4199 #define FDCAN_CCCR_CSR_Pos (4U)
4200 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4201 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4202 #define FDCAN_CCCR_MON_Pos (5U)
4203 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4204 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4205 #define FDCAN_CCCR_DAR_Pos (6U)
4206 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4207 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4208 #define FDCAN_CCCR_TEST_Pos (7U)
4209 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4210 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4211 #define FDCAN_CCCR_FDOE_Pos (8U)
4212 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4213 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4214 #define FDCAN_CCCR_BRSE_Pos (9U)
4215 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4216 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4217 #define FDCAN_CCCR_PXHD_Pos (12U)
4218 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4219 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4220 #define FDCAN_CCCR_EFBI_Pos (13U)
4221 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4222 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4223 #define FDCAN_CCCR_TXP_Pos (14U)
4224 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4225 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4226 #define FDCAN_CCCR_NISO_Pos (15U)
4227 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4228 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4229
4230 /***************** Bit definition for FDCAN_NBTP register ********************/
4231 #define FDCAN_NBTP_NTSEG2_Pos (0U)
4232 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4233 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4234 #define FDCAN_NBTP_NTSEG1_Pos (8U)
4235 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4236 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4237 #define FDCAN_NBTP_NBRP_Pos (16U)
4238 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4239 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4240 #define FDCAN_NBTP_NSJW_Pos (25U)
4241 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4242 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4243
4244 /***************** Bit definition for FDCAN_TSCC register ********************/
4245 #define FDCAN_TSCC_TSS_Pos (0U)
4246 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4247 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4248 #define FDCAN_TSCC_TCP_Pos (16U)
4249 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4250 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4251
4252 /***************** Bit definition for FDCAN_TSCV register ********************/
4253 #define FDCAN_TSCV_TSC_Pos (0U)
4254 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4255 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4256
4257 /***************** Bit definition for FDCAN_TOCC register ********************/
4258 #define FDCAN_TOCC_ETOC_Pos (0U)
4259 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4260 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4261 #define FDCAN_TOCC_TOS_Pos (1U)
4262 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4263 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4264 #define FDCAN_TOCC_TOP_Pos (16U)
4265 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4266 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4267
4268 /***************** Bit definition for FDCAN_TOCV register ********************/
4269 #define FDCAN_TOCV_TOC_Pos (0U)
4270 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4271 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4272
4273 /***************** Bit definition for FDCAN_ECR register *********************/
4274 #define FDCAN_ECR_TEC_Pos (0U)
4275 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4276 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4277 #define FDCAN_ECR_REC_Pos (8U)
4278 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4279 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4280 #define FDCAN_ECR_RP_Pos (15U)
4281 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4282 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4283 #define FDCAN_ECR_CEL_Pos (16U)
4284 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4285 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4286
4287 /***************** Bit definition for FDCAN_PSR register *********************/
4288 #define FDCAN_PSR_LEC_Pos (0U)
4289 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4290 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4291 #define FDCAN_PSR_ACT_Pos (3U)
4292 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4293 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4294 #define FDCAN_PSR_EP_Pos (5U)
4295 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4296 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4297 #define FDCAN_PSR_EW_Pos (6U)
4298 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4299 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4300 #define FDCAN_PSR_BO_Pos (7U)
4301 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4302 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4303 #define FDCAN_PSR_DLEC_Pos (8U)
4304 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4305 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4306 #define FDCAN_PSR_RESI_Pos (11U)
4307 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4308 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4309 #define FDCAN_PSR_RBRS_Pos (12U)
4310 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4311 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4312 #define FDCAN_PSR_REDL_Pos (13U)
4313 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4314 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4315 #define FDCAN_PSR_PXE_Pos (14U)
4316 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4317 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4318 #define FDCAN_PSR_TDCV_Pos (16U)
4319 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4320 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4321
4322 /***************** Bit definition for FDCAN_TDCR register ********************/
4323 #define FDCAN_TDCR_TDCF_Pos (0U)
4324 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4325 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4326 #define FDCAN_TDCR_TDCO_Pos (8U)
4327 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4328 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4329
4330 /***************** Bit definition for FDCAN_IR register **********************/
4331 #define FDCAN_IR_RF0N_Pos (0U)
4332 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4333 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4334 #define FDCAN_IR_RF0W_Pos (1U)
4335 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4336 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4337 #define FDCAN_IR_RF0F_Pos (2U)
4338 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4339 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4340 #define FDCAN_IR_RF0L_Pos (3U)
4341 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4342 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4343 #define FDCAN_IR_RF1N_Pos (4U)
4344 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4345 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4346 #define FDCAN_IR_RF1W_Pos (5U)
4347 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4348 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4349 #define FDCAN_IR_RF1F_Pos (6U)
4350 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4351 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4352 #define FDCAN_IR_RF1L_Pos (7U)
4353 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4354 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4355 #define FDCAN_IR_HPM_Pos (8U)
4356 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4357 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4358 #define FDCAN_IR_TC_Pos (9U)
4359 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4360 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4361 #define FDCAN_IR_TCF_Pos (10U)
4362 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4363 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4364 #define FDCAN_IR_TFE_Pos (11U)
4365 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4366 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4367 #define FDCAN_IR_TEFN_Pos (12U)
4368 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4369 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4370 #define FDCAN_IR_TEFW_Pos (13U)
4371 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4372 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4373 #define FDCAN_IR_TEFF_Pos (14U)
4374 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4375 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4376 #define FDCAN_IR_TEFL_Pos (15U)
4377 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4378 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4379 #define FDCAN_IR_TSW_Pos (16U)
4380 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4381 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4382 #define FDCAN_IR_MRAF_Pos (17U)
4383 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4384 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4385 #define FDCAN_IR_TOO_Pos (18U)
4386 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4387 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4388 #define FDCAN_IR_DRX_Pos (19U)
4389 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4390 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4391 #define FDCAN_IR_ELO_Pos (22U)
4392 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4393 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4394 #define FDCAN_IR_EP_Pos (23U)
4395 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4396 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4397 #define FDCAN_IR_EW_Pos (24U)
4398 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4399 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4400 #define FDCAN_IR_BO_Pos (25U)
4401 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4402 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4403 #define FDCAN_IR_WDI_Pos (26U)
4404 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4405 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4406 #define FDCAN_IR_PEA_Pos (27U)
4407 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4408 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4409 #define FDCAN_IR_PED_Pos (28U)
4410 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4411 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4412 #define FDCAN_IR_ARA_Pos (29U)
4413 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4414 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4415
4416 /***************** Bit definition for FDCAN_IE register **********************/
4417 #define FDCAN_IE_RF0NE_Pos (0U)
4418 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4419 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4420 #define FDCAN_IE_RF0WE_Pos (1U)
4421 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4422 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4423 #define FDCAN_IE_RF0FE_Pos (2U)
4424 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4425 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4426 #define FDCAN_IE_RF0LE_Pos (3U)
4427 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4428 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4429 #define FDCAN_IE_RF1NE_Pos (4U)
4430 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4431 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4432 #define FDCAN_IE_RF1WE_Pos (5U)
4433 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4434 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4435 #define FDCAN_IE_RF1FE_Pos (6U)
4436 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4437 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4438 #define FDCAN_IE_RF1LE_Pos (7U)
4439 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4440 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4441 #define FDCAN_IE_HPME_Pos (8U)
4442 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4443 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4444 #define FDCAN_IE_TCE_Pos (9U)
4445 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4446 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4447 #define FDCAN_IE_TCFE_Pos (10U)
4448 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4449 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4450 #define FDCAN_IE_TFEE_Pos (11U)
4451 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4452 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4453 #define FDCAN_IE_TEFNE_Pos (12U)
4454 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4455 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4456 #define FDCAN_IE_TEFWE_Pos (13U)
4457 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4458 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4459 #define FDCAN_IE_TEFFE_Pos (14U)
4460 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4461 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4462 #define FDCAN_IE_TEFLE_Pos (15U)
4463 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4464 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4465 #define FDCAN_IE_TSWE_Pos (16U)
4466 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4467 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4468 #define FDCAN_IE_MRAFE_Pos (17U)
4469 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4470 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4471 #define FDCAN_IE_TOOE_Pos (18U)
4472 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4473 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4474 #define FDCAN_IE_DRXE_Pos (19U)
4475 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4476 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4477 #define FDCAN_IE_BECE_Pos (20U)
4478 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4479 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4480 #define FDCAN_IE_BEUE_Pos (21U)
4481 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4482 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4483 #define FDCAN_IE_ELOE_Pos (22U)
4484 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4485 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4486 #define FDCAN_IE_EPE_Pos (23U)
4487 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4488 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4489 #define FDCAN_IE_EWE_Pos (24U)
4490 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4491 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4492 #define FDCAN_IE_BOE_Pos (25U)
4493 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4494 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4495 #define FDCAN_IE_WDIE_Pos (26U)
4496 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4497 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4498 #define FDCAN_IE_PEAE_Pos (27U)
4499 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4500 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4501 #define FDCAN_IE_PEDE_Pos (28U)
4502 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4503 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4504 #define FDCAN_IE_ARAE_Pos (29U)
4505 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4506 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4507
4508 /***************** Bit definition for FDCAN_ILS register **********************/
4509 #define FDCAN_ILS_RF0NL_Pos (0U)
4510 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4511 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4512 #define FDCAN_ILS_RF0WL_Pos (1U)
4513 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4514 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4515 #define FDCAN_ILS_RF0FL_Pos (2U)
4516 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4517 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4518 #define FDCAN_ILS_RF0LL_Pos (3U)
4519 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4520 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4521 #define FDCAN_ILS_RF1NL_Pos (4U)
4522 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4523 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4524 #define FDCAN_ILS_RF1WL_Pos (5U)
4525 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4526 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4527 #define FDCAN_ILS_RF1FL_Pos (6U)
4528 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4529 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4530 #define FDCAN_ILS_RF1LL_Pos (7U)
4531 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4532 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4533 #define FDCAN_ILS_HPML_Pos (8U)
4534 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4535 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4536 #define FDCAN_ILS_TCL_Pos (9U)
4537 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4538 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4539 #define FDCAN_ILS_TCFL_Pos (10U)
4540 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4541 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4542 #define FDCAN_ILS_TFEL_Pos (11U)
4543 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4544 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4545 #define FDCAN_ILS_TEFNL_Pos (12U)
4546 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4547 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4548 #define FDCAN_ILS_TEFWL_Pos (13U)
4549 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4550 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4551 #define FDCAN_ILS_TEFFL_Pos (14U)
4552 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4553 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4554 #define FDCAN_ILS_TEFLL_Pos (15U)
4555 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4556 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4557 #define FDCAN_ILS_TSWL_Pos (16U)
4558 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4559 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4560 #define FDCAN_ILS_MRAFE_Pos (17U)
4561 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4562 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4563 #define FDCAN_ILS_TOOE_Pos (18U)
4564 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4565 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4566 #define FDCAN_ILS_DRXE_Pos (19U)
4567 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4568 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4569 #define FDCAN_ILS_BECE_Pos (20U)
4570 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4571 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4572 #define FDCAN_ILS_BEUE_Pos (21U)
4573 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4574 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4575 #define FDCAN_ILS_ELOE_Pos (22U)
4576 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4577 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4578 #define FDCAN_ILS_EPE_Pos (23U)
4579 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4580 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4581 #define FDCAN_ILS_EWE_Pos (24U)
4582 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4583 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4584 #define FDCAN_ILS_BOE_Pos (25U)
4585 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4586 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4587 #define FDCAN_ILS_WDIE_Pos (26U)
4588 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4589 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4590 #define FDCAN_ILS_PEAE_Pos (27U)
4591 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4592 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4593 #define FDCAN_ILS_PEDE_Pos (28U)
4594 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4595 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4596 #define FDCAN_ILS_ARAE_Pos (29U)
4597 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4598 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4599
4600 /***************** Bit definition for FDCAN_ILE register **********************/
4601 #define FDCAN_ILE_EINT0_Pos (0U)
4602 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4603 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4604 #define FDCAN_ILE_EINT1_Pos (1U)
4605 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4606 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4607
4608 /***************** Bit definition for FDCAN_GFC register **********************/
4609 #define FDCAN_GFC_RRFE_Pos (0U)
4610 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4611 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4612 #define FDCAN_GFC_RRFS_Pos (1U)
4613 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4614 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4615 #define FDCAN_GFC_ANFE_Pos (2U)
4616 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4617 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4618 #define FDCAN_GFC_ANFS_Pos (4U)
4619 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4620 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4621
4622 /***************** Bit definition for FDCAN_SIDFC register ********************/
4623 #define FDCAN_SIDFC_FLSSA_Pos (2U)
4624 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4625 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4626 #define FDCAN_SIDFC_LSS_Pos (16U)
4627 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4628 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4629
4630 /***************** Bit definition for FDCAN_XIDFC register ********************/
4631 #define FDCAN_XIDFC_FLESA_Pos (2U)
4632 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4633 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4634 #define FDCAN_XIDFC_LSE_Pos (16U)
4635 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4636 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4637
4638 /***************** Bit definition for FDCAN_XIDAM register ********************/
4639 #define FDCAN_XIDAM_EIDM_Pos (0U)
4640 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4641 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4642
4643 /***************** Bit definition for FDCAN_HPMS register *********************/
4644 #define FDCAN_HPMS_BIDX_Pos (0U)
4645 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4646 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4647 #define FDCAN_HPMS_MSI_Pos (6U)
4648 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4649 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4650 #define FDCAN_HPMS_FIDX_Pos (8U)
4651 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4652 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4653 #define FDCAN_HPMS_FLST_Pos (15U)
4654 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4655 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4656
4657 /***************** Bit definition for FDCAN_NDAT1 register ********************/
4658 #define FDCAN_NDAT1_ND0_Pos (0U)
4659 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4660 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4661 #define FDCAN_NDAT1_ND1_Pos (1U)
4662 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4663 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4664 #define FDCAN_NDAT1_ND2_Pos (2U)
4665 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4666 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4667 #define FDCAN_NDAT1_ND3_Pos (3U)
4668 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4669 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4670 #define FDCAN_NDAT1_ND4_Pos (4U)
4671 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4672 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4673 #define FDCAN_NDAT1_ND5_Pos (5U)
4674 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4675 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4676 #define FDCAN_NDAT1_ND6_Pos (6U)
4677 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4678 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4679 #define FDCAN_NDAT1_ND7_Pos (7U)
4680 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4681 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4682 #define FDCAN_NDAT1_ND8_Pos (8U)
4683 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4684 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4685 #define FDCAN_NDAT1_ND9_Pos (9U)
4686 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4687 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4688 #define FDCAN_NDAT1_ND10_Pos (10U)
4689 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4690 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4691 #define FDCAN_NDAT1_ND11_Pos (11U)
4692 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4693 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4694 #define FDCAN_NDAT1_ND12_Pos (12U)
4695 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4696 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4697 #define FDCAN_NDAT1_ND13_Pos (13U)
4698 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4699 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4700 #define FDCAN_NDAT1_ND14_Pos (14U)
4701 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4702 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4703 #define FDCAN_NDAT1_ND15_Pos (15U)
4704 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4705 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4706 #define FDCAN_NDAT1_ND16_Pos (16U)
4707 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4708 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4709 #define FDCAN_NDAT1_ND17_Pos (17U)
4710 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4711 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4712 #define FDCAN_NDAT1_ND18_Pos (18U)
4713 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4714 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4715 #define FDCAN_NDAT1_ND19_Pos (19U)
4716 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4717 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4718 #define FDCAN_NDAT1_ND20_Pos (20U)
4719 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4720 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4721 #define FDCAN_NDAT1_ND21_Pos (21U)
4722 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4723 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4724 #define FDCAN_NDAT1_ND22_Pos (22U)
4725 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4726 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4727 #define FDCAN_NDAT1_ND23_Pos (23U)
4728 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4729 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4730 #define FDCAN_NDAT1_ND24_Pos (24U)
4731 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4732 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4733 #define FDCAN_NDAT1_ND25_Pos (25U)
4734 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4735 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4736 #define FDCAN_NDAT1_ND26_Pos (26U)
4737 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4738 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4739 #define FDCAN_NDAT1_ND27_Pos (27U)
4740 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4741 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4742 #define FDCAN_NDAT1_ND28_Pos (28U)
4743 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4744 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4745 #define FDCAN_NDAT1_ND29_Pos (29U)
4746 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4747 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4748 #define FDCAN_NDAT1_ND30_Pos (30U)
4749 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4750 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4751 #define FDCAN_NDAT1_ND31_Pos (31U)
4752 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4753 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4754
4755 /***************** Bit definition for FDCAN_NDAT2 register ********************/
4756 #define FDCAN_NDAT2_ND32_Pos (0U)
4757 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4758 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4759 #define FDCAN_NDAT2_ND33_Pos (1U)
4760 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4761 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4762 #define FDCAN_NDAT2_ND34_Pos (2U)
4763 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4764 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4765 #define FDCAN_NDAT2_ND35_Pos (3U)
4766 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4767 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4768 #define FDCAN_NDAT2_ND36_Pos (4U)
4769 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4770 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4771 #define FDCAN_NDAT2_ND37_Pos (5U)
4772 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4773 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4774 #define FDCAN_NDAT2_ND38_Pos (6U)
4775 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4776 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4777 #define FDCAN_NDAT2_ND39_Pos (7U)
4778 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4779 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4780 #define FDCAN_NDAT2_ND40_Pos (8U)
4781 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4782 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4783 #define FDCAN_NDAT2_ND41_Pos (9U)
4784 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4785 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4786 #define FDCAN_NDAT2_ND42_Pos (10U)
4787 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4788 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4789 #define FDCAN_NDAT2_ND43_Pos (11U)
4790 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4791 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4792 #define FDCAN_NDAT2_ND44_Pos (12U)
4793 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4794 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4795 #define FDCAN_NDAT2_ND45_Pos (13U)
4796 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4797 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4798 #define FDCAN_NDAT2_ND46_Pos (14U)
4799 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4800 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4801 #define FDCAN_NDAT2_ND47_Pos (15U)
4802 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4803 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4804 #define FDCAN_NDAT2_ND48_Pos (16U)
4805 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4806 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4807 #define FDCAN_NDAT2_ND49_Pos (17U)
4808 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4809 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4810 #define FDCAN_NDAT2_ND50_Pos (18U)
4811 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4812 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4813 #define FDCAN_NDAT2_ND51_Pos (19U)
4814 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4815 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4816 #define FDCAN_NDAT2_ND52_Pos (20U)
4817 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4818 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4819 #define FDCAN_NDAT2_ND53_Pos (21U)
4820 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4821 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4822 #define FDCAN_NDAT2_ND54_Pos (22U)
4823 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4824 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4825 #define FDCAN_NDAT2_ND55_Pos (23U)
4826 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4827 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4828 #define FDCAN_NDAT2_ND56_Pos (24U)
4829 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4830 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4831 #define FDCAN_NDAT2_ND57_Pos (25U)
4832 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4833 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4834 #define FDCAN_NDAT2_ND58_Pos (26U)
4835 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4836 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4837 #define FDCAN_NDAT2_ND59_Pos (27U)
4838 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4839 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4840 #define FDCAN_NDAT2_ND60_Pos (28U)
4841 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4842 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4843 #define FDCAN_NDAT2_ND61_Pos (29U)
4844 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4845 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4846 #define FDCAN_NDAT2_ND62_Pos (30U)
4847 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4848 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4849 #define FDCAN_NDAT2_ND63_Pos (31U)
4850 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4851 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4852
4853 /***************** Bit definition for FDCAN_RXF0C register ********************/
4854 #define FDCAN_RXF0C_F0SA_Pos (2U)
4855 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4856 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4857 #define FDCAN_RXF0C_F0S_Pos (16U)
4858 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4859 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4860 #define FDCAN_RXF0C_F0WM_Pos (24U)
4861 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4862 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4863 #define FDCAN_RXF0C_F0OM_Pos (31U)
4864 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4865 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4866
4867 /***************** Bit definition for FDCAN_RXF0S register ********************/
4868 #define FDCAN_RXF0S_F0FL_Pos (0U)
4869 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4870 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4871 #define FDCAN_RXF0S_F0GI_Pos (8U)
4872 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4873 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4874 #define FDCAN_RXF0S_F0PI_Pos (16U)
4875 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4876 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4877 #define FDCAN_RXF0S_F0F_Pos (24U)
4878 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4879 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4880 #define FDCAN_RXF0S_RF0L_Pos (25U)
4881 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4882 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4883
4884 /***************** Bit definition for FDCAN_RXF0A register ********************/
4885 #define FDCAN_RXF0A_F0AI_Pos (0U)
4886 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4887 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4888
4889 /***************** Bit definition for FDCAN_RXBC register ********************/
4890 #define FDCAN_RXBC_RBSA_Pos (2U)
4891 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4892 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4893
4894 /***************** Bit definition for FDCAN_RXF1C register ********************/
4895 #define FDCAN_RXF1C_F1SA_Pos (2U)
4896 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4897 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4898 #define FDCAN_RXF1C_F1S_Pos (16U)
4899 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4900 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4901 #define FDCAN_RXF1C_F1WM_Pos (24U)
4902 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4903 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4904 #define FDCAN_RXF1C_F1OM_Pos (31U)
4905 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4906 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4907
4908 /***************** Bit definition for FDCAN_RXF1S register ********************/
4909 #define FDCAN_RXF1S_F1FL_Pos (0U)
4910 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4911 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4912 #define FDCAN_RXF1S_F1GI_Pos (8U)
4913 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4914 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4915 #define FDCAN_RXF1S_F1PI_Pos (16U)
4916 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4917 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4918 #define FDCAN_RXF1S_F1F_Pos (24U)
4919 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4920 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4921 #define FDCAN_RXF1S_RF1L_Pos (25U)
4922 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4923 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4924
4925 /***************** Bit definition for FDCAN_RXF1A register ********************/
4926 #define FDCAN_RXF1A_F1AI_Pos (0U)
4927 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4928 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4929
4930 /***************** Bit definition for FDCAN_RXESC register ********************/
4931 #define FDCAN_RXESC_F0DS_Pos (0U)
4932 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4933 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4934 #define FDCAN_RXESC_F1DS_Pos (4U)
4935 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4936 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4937 #define FDCAN_RXESC_RBDS_Pos (8U)
4938 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4939 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4940
4941 /***************** Bit definition for FDCAN_TXBC register *********************/
4942 #define FDCAN_TXBC_TBSA_Pos (2U)
4943 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4944 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4945 #define FDCAN_TXBC_NDTB_Pos (16U)
4946 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4947 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4948 #define FDCAN_TXBC_TFQS_Pos (24U)
4949 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4950 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4951 #define FDCAN_TXBC_TFQM_Pos (30U)
4952 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4953 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4954
4955 /***************** Bit definition for FDCAN_TXFQS register *********************/
4956 #define FDCAN_TXFQS_TFFL_Pos (0U)
4957 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4958 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4959 #define FDCAN_TXFQS_TFGI_Pos (8U)
4960 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4961 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4962 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4963 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4964 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4965 #define FDCAN_TXFQS_TFQF_Pos (21U)
4966 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4967 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4968
4969 /***************** Bit definition for FDCAN_TXESC register *********************/
4970 #define FDCAN_TXESC_TBDS_Pos (0U)
4971 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4972 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4973
4974 /***************** Bit definition for FDCAN_TXBRP register *********************/
4975 #define FDCAN_TXBRP_TRP_Pos (0U)
4976 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4977 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4978
4979 /***************** Bit definition for FDCAN_TXBAR register *********************/
4980 #define FDCAN_TXBAR_AR_Pos (0U)
4981 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4982 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4983
4984 /***************** Bit definition for FDCAN_TXBCR register *********************/
4985 #define FDCAN_TXBCR_CR_Pos (0U)
4986 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4987 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4988
4989 /***************** Bit definition for FDCAN_TXBTO register *********************/
4990 #define FDCAN_TXBTO_TO_Pos (0U)
4991 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4992 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4993
4994 /***************** Bit definition for FDCAN_TXBCF register *********************/
4995 #define FDCAN_TXBCF_CF_Pos (0U)
4996 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4997 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4998
4999 /***************** Bit definition for FDCAN_TXBTIE register ********************/
5000 #define FDCAN_TXBTIE_TIE_Pos (0U)
5001 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
5002 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
5003
5004 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
5005 #define FDCAN_TXBCIE_CFIE_Pos (0U)
5006 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
5007 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
5008
5009 /***************** Bit definition for FDCAN_TXEFC register *********************/
5010 #define FDCAN_TXEFC_EFSA_Pos (2U)
5011 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
5012 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
5013 #define FDCAN_TXEFC_EFS_Pos (16U)
5014 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
5015 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
5016 #define FDCAN_TXEFC_EFWM_Pos (24U)
5017 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
5018 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
5019
5020 /***************** Bit definition for FDCAN_TXEFS register *********************/
5021 #define FDCAN_TXEFS_EFFL_Pos (0U)
5022 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
5023 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
5024 #define FDCAN_TXEFS_EFGI_Pos (8U)
5025 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
5026 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
5027 #define FDCAN_TXEFS_EFPI_Pos (16U)
5028 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
5029 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
5030 #define FDCAN_TXEFS_EFF_Pos (24U)
5031 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
5032 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
5033 #define FDCAN_TXEFS_TEFL_Pos (25U)
5034 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
5035 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
5036
5037 /***************** Bit definition for FDCAN_TXEFA register *********************/
5038 #define FDCAN_TXEFA_EFAI_Pos (0U)
5039 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
5040 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
5041
5042 /***************** Bit definition for FDCAN_TTTMC register *********************/
5043 #define FDCAN_TTTMC_TMSA_Pos (2U)
5044 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
5045 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
5046 #define FDCAN_TTTMC_TME_Pos (16U)
5047 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
5048 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
5049
5050 /***************** Bit definition for FDCAN_TTRMC register *********************/
5051 #define FDCAN_TTRMC_RID_Pos (0U)
5052 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
5053 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
5054 #define FDCAN_TTRMC_XTD_Pos (30U)
5055 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
5056 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
5057 #define FDCAN_TTRMC_RMPS_Pos (31U)
5058 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
5059 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
5060
5061 /***************** Bit definition for FDCAN_TTOCF register *********************/
5062 #define FDCAN_TTOCF_OM_Pos (0U)
5063 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
5064 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
5065 #define FDCAN_TTOCF_GEN_Pos (3U)
5066 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
5067 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
5068 #define FDCAN_TTOCF_TM_Pos (4U)
5069 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
5070 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
5071 #define FDCAN_TTOCF_LDSDL_Pos (5U)
5072 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
5073 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
5074 #define FDCAN_TTOCF_IRTO_Pos (8U)
5075 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
5076 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
5077 #define FDCAN_TTOCF_EECS_Pos (15U)
5078 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
5079 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
5080 #define FDCAN_TTOCF_AWL_Pos (16U)
5081 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
5082 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
5083 #define FDCAN_TTOCF_EGTF_Pos (24U)
5084 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
5085 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
5086 #define FDCAN_TTOCF_ECC_Pos (25U)
5087 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
5088 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
5089 #define FDCAN_TTOCF_EVTP_Pos (26U)
5090 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
5091 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
5092
5093 /***************** Bit definition for FDCAN_TTMLM register *********************/
5094 #define FDCAN_TTMLM_CCM_Pos (0U)
5095 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
5096 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
5097 #define FDCAN_TTMLM_CSS_Pos (6U)
5098 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
5099 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
5100 #define FDCAN_TTMLM_TXEW_Pos (8U)
5101 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
5102 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
5103 #define FDCAN_TTMLM_ENTT_Pos (16U)
5104 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
5105 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
5106
5107 /***************** Bit definition for FDCAN_TURCF register *********************/
5108 #define FDCAN_TURCF_NCL_Pos (0U)
5109 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
5110 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
5111 #define FDCAN_TURCF_DC_Pos (16U)
5112 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
5113 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
5114 #define FDCAN_TURCF_ELT_Pos (31U)
5115 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
5116 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
5117
5118 /***************** Bit definition for FDCAN_TTOCN register ********************/
5119 #define FDCAN_TTOCN_SGT_Pos (0U)
5120 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
5121 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
5122 #define FDCAN_TTOCN_ECS_Pos (1U)
5123 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
5124 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
5125 #define FDCAN_TTOCN_SWP_Pos (2U)
5126 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
5127 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
5128 #define FDCAN_TTOCN_SWS_Pos (3U)
5129 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
5130 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
5131 #define FDCAN_TTOCN_RTIE_Pos (5U)
5132 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
5133 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
5134 #define FDCAN_TTOCN_TMC_Pos (6U)
5135 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
5136 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
5137 #define FDCAN_TTOCN_TTIE_Pos (8U)
5138 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
5139 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
5140 #define FDCAN_TTOCN_GCS_Pos (9U)
5141 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
5142 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
5143 #define FDCAN_TTOCN_FGP_Pos (10U)
5144 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
5145 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
5146 #define FDCAN_TTOCN_TMG_Pos (11U)
5147 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
5148 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
5149 #define FDCAN_TTOCN_NIG_Pos (12U)
5150 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
5151 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
5152 #define FDCAN_TTOCN_ESCN_Pos (13U)
5153 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
5154 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
5155 #define FDCAN_TTOCN_LCKC_Pos (15U)
5156 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
5157 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
5158
5159 /***************** Bit definition for FDCAN_TTGTP register ********************/
5160 #define FDCAN_TTGTP_TP_Pos (0U)
5161 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
5162 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
5163 #define FDCAN_TTGTP_CTP_Pos (16U)
5164 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
5165 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
5166
5167 /***************** Bit definition for FDCAN_TTTMK register ********************/
5168 #define FDCAN_TTTMK_TM_Pos (0U)
5169 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
5170 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
5171 #define FDCAN_TTTMK_TICC_Pos (16U)
5172 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
5173 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
5174 #define FDCAN_TTTMK_LCKM_Pos (31U)
5175 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
5176 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
5177
5178 /***************** Bit definition for FDCAN_TTIR register ********************/
5179 #define FDCAN_TTIR_SBC_Pos (0U)
5180 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
5181 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
5182 #define FDCAN_TTIR_SMC_Pos (1U)
5183 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
5184 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
5185 #define FDCAN_TTIR_CSM_Pos (2U)
5186 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
5187 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
5188 #define FDCAN_TTIR_SOG_Pos (3U)
5189 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
5190 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
5191 #define FDCAN_TTIR_RTMI_Pos (4U)
5192 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
5193 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
5194 #define FDCAN_TTIR_TTMI_Pos (5U)
5195 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
5196 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
5197 #define FDCAN_TTIR_SWE_Pos (6U)
5198 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
5199 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
5200 #define FDCAN_TTIR_GTW_Pos (7U)
5201 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
5202 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
5203 #define FDCAN_TTIR_GTD_Pos (8U)
5204 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
5205 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
5206 #define FDCAN_TTIR_GTE_Pos (9U)
5207 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
5208 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
5209 #define FDCAN_TTIR_TXU_Pos (10U)
5210 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
5211 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
5212 #define FDCAN_TTIR_TXO_Pos (11U)
5213 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
5214 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
5215 #define FDCAN_TTIR_SE1_Pos (12U)
5216 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
5217 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
5218 #define FDCAN_TTIR_SE2_Pos (13U)
5219 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
5220 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
5221 #define FDCAN_TTIR_ELC_Pos (14U)
5222 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
5223 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
5224 #define FDCAN_TTIR_IWT_Pos (15U)
5225 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
5226 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
5227 #define FDCAN_TTIR_WT_Pos (16U)
5228 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
5229 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
5230 #define FDCAN_TTIR_AW_Pos (17U)
5231 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
5232 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
5233 #define FDCAN_TTIR_CER_Pos (18U)
5234 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
5235 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
5236
5237 /***************** Bit definition for FDCAN_TTIE register ********************/
5238 #define FDCAN_TTIE_SBCE_Pos (0U)
5239 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
5240 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
5241 #define FDCAN_TTIE_SMCE_Pos (1U)
5242 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
5243 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
5244 #define FDCAN_TTIE_CSME_Pos (2U)
5245 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
5246 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
5247 #define FDCAN_TTIE_SOGE_Pos (3U)
5248 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
5249 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
5250 #define FDCAN_TTIE_RTMIE_Pos (4U)
5251 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
5252 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
5253 #define FDCAN_TTIE_TTMIE_Pos (5U)
5254 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
5255 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
5256 #define FDCAN_TTIE_SWEE_Pos (6U)
5257 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
5258 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
5259 #define FDCAN_TTIE_GTWE_Pos (7U)
5260 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
5261 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
5262 #define FDCAN_TTIE_GTDE_Pos (8U)
5263 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
5264 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
5265 #define FDCAN_TTIE_GTEE_Pos (9U)
5266 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
5267 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
5268 #define FDCAN_TTIE_TXUE_Pos (10U)
5269 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
5270 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
5271 #define FDCAN_TTIE_TXOE_Pos (11U)
5272 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
5273 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
5274 #define FDCAN_TTIE_SE1E_Pos (12U)
5275 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
5276 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
5277 #define FDCAN_TTIE_SE2E_Pos (13U)
5278 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
5279 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
5280 #define FDCAN_TTIE_ELCE_Pos (14U)
5281 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5282 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5283 #define FDCAN_TTIE_IWTE_Pos (15U)
5284 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5285 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5286 #define FDCAN_TTIE_WTE_Pos (16U)
5287 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5288 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5289 #define FDCAN_TTIE_AWE_Pos (17U)
5290 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5291 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5292 #define FDCAN_TTIE_CERE_Pos (18U)
5293 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5294 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5295
5296 /***************** Bit definition for FDCAN_TTILS register ********************/
5297 #define FDCAN_TTILS_SBCS_Pos (0U)
5298 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5299 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5300 #define FDCAN_TTILS_SMCS_Pos (1U)
5301 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5302 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5303 #define FDCAN_TTILS_CSMS_Pos (2U)
5304 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5305 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5306 #define FDCAN_TTILS_SOGS_Pos (3U)
5307 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5308 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5309 #define FDCAN_TTILS_RTMIS_Pos (4U)
5310 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5311 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5312 #define FDCAN_TTILS_TTMIS_Pos (5U)
5313 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5314 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5315 #define FDCAN_TTILS_SWES_Pos (6U)
5316 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5317 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5318 #define FDCAN_TTILS_GTWS_Pos (7U)
5319 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5320 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5321 #define FDCAN_TTILS_GTDS_Pos (8U)
5322 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5323 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5324 #define FDCAN_TTILS_GTES_Pos (9U)
5325 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5326 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5327 #define FDCAN_TTILS_TXUS_Pos (10U)
5328 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5329 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5330 #define FDCAN_TTILS_TXOS_Pos (11U)
5331 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5332 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5333 #define FDCAN_TTILS_SE1S_Pos (12U)
5334 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5335 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5336 #define FDCAN_TTILS_SE2S_Pos (13U)
5337 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5338 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5339 #define FDCAN_TTILS_ELCS_Pos (14U)
5340 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5341 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5342 #define FDCAN_TTILS_IWTS_Pos (15U)
5343 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5344 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5345 #define FDCAN_TTILS_WTS_Pos (16U)
5346 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5347 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5348 #define FDCAN_TTILS_AWS_Pos (17U)
5349 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5350 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5351 #define FDCAN_TTILS_CERS_Pos (18U)
5352 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5353 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5354
5355 /***************** Bit definition for FDCAN_TTOST register ********************/
5356 #define FDCAN_TTOST_EL_Pos (0U)
5357 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5358 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5359 #define FDCAN_TTOST_MS_Pos (2U)
5360 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5361 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5362 #define FDCAN_TTOST_SYS_Pos (4U)
5363 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5364 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5365 #define FDCAN_TTOST_QGTP_Pos (6U)
5366 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5367 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5368 #define FDCAN_TTOST_QCS_Pos (7U)
5369 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5370 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5371 #define FDCAN_TTOST_RTO_Pos (8U)
5372 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5373 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5374 #define FDCAN_TTOST_WGTD_Pos (22U)
5375 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5376 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5377 #define FDCAN_TTOST_GFI_Pos (23U)
5378 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5379 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5380 #define FDCAN_TTOST_TMP_Pos (24U)
5381 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5382 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5383 #define FDCAN_TTOST_GSI_Pos (27U)
5384 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5385 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5386 #define FDCAN_TTOST_WFE_Pos (28U)
5387 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5388 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5389 #define FDCAN_TTOST_AWE_Pos (29U)
5390 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5391 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5392 #define FDCAN_TTOST_WECS_Pos (30U)
5393 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5394 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5395 #define FDCAN_TTOST_SPL_Pos (31U)
5396 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5397 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5398
5399 /***************** Bit definition for FDCAN_TURNA register ********************/
5400 #define FDCAN_TURNA_NAV_Pos (0U)
5401 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5402 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5403
5404 /***************** Bit definition for FDCAN_TTLGT register ********************/
5405 #define FDCAN_TTLGT_LT_Pos (0U)
5406 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5407 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5408 #define FDCAN_TTLGT_GT_Pos (16U)
5409 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5410 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5411
5412 /***************** Bit definition for FDCAN_TTCTC register ********************/
5413 #define FDCAN_TTCTC_CT_Pos (0U)
5414 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5415 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5416 #define FDCAN_TTCTC_CC_Pos (16U)
5417 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5418 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5419
5420 /***************** Bit definition for FDCAN_TTCPT register ********************/
5421 #define FDCAN_TTCPT_CCV_Pos (0U)
5422 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5423 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5424 #define FDCAN_TTCPT_SWV_Pos (16U)
5425 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5426 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5427
5428 /***************** Bit definition for FDCAN_TTCSM register ********************/
5429 #define FDCAN_TTCSM_CSM_Pos (0U)
5430 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5431 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5432
5433 /***************** Bit definition for FDCAN_TTTS register *********************/
5434 #define FDCAN_TTTS_SWTSEL_Pos (0U)
5435 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5436 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5437 #define FDCAN_TTTS_EVTSEL_Pos (4U)
5438 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5439 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5440
5441 /********************************************************************************/
5442 /* */
5443 /* FDCANCCU (Clock Calibration unit) */
5444 /* */
5445 /********************************************************************************/
5446
5447 /***************** Bit definition for FDCANCCU_CREL register ******************/
5448 #define FDCANCCU_CREL_DAY_Pos (0U)
5449 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5450 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5451 #define FDCANCCU_CREL_MON_Pos (8U)
5452 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5453 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5454 #define FDCANCCU_CREL_YEAR_Pos (16U)
5455 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5456 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5457 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5458 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5459 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5460 #define FDCANCCU_CREL_STEP_Pos (24U)
5461 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5462 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5463 #define FDCANCCU_CREL_REL_Pos (28U)
5464 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5465 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5466
5467 /***************** Bit definition for FDCANCCU_CCFG register ******************/
5468 #define FDCANCCU_CCFG_TQBT_Pos (0U)
5469 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5470 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5471 #define FDCANCCU_CCFG_BCC_Pos (6U)
5472 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5473 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5474 #define FDCANCCU_CCFG_CFL_Pos (7U)
5475 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5476 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5477 #define FDCANCCU_CCFG_OCPM_Pos (8U)
5478 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5479 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5480 #define FDCANCCU_CCFG_CDIV_Pos (16U)
5481 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5482 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5483 #define FDCANCCU_CCFG_SWR_Pos (31U)
5484 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5485 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5486
5487 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
5488 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
5489 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5490 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5491 #define FDCANCCU_CSTAT_TQC_Pos (18U)
5492 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5493 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5494 #define FDCANCCU_CSTAT_CALS_Pos (30U)
5495 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5496 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5497
5498 /****************** Bit definition for FDCANCCU_CWD register ******************/
5499 #define FDCANCCU_CWD_WDC_Pos (0U)
5500 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5501 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5502 #define FDCANCCU_CWD_WDV_Pos (16U)
5503 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5504 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5505
5506 /****************** Bit definition for FDCANCCU_IR register *******************/
5507 #define FDCANCCU_IR_CWE_Pos (0U)
5508 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5509 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5510 #define FDCANCCU_IR_CSC_Pos (1U)
5511 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5512 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5513
5514 /****************** Bit definition for FDCANCCU_IE register *******************/
5515 #define FDCANCCU_IE_CWEE_Pos (0U)
5516 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5517 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5518 #define FDCANCCU_IE_CSCE_Pos (1U)
5519 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5520 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5521
5522 /******************************************************************************/
5523 /* */
5524 /* HDMI-CEC (CEC) */
5525 /* */
5526 /******************************************************************************/
5527
5528 /******************* Bit definition for CEC_CR register *********************/
5529 #define CEC_CR_CECEN_Pos (0U)
5530 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5531 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5532 #define CEC_CR_TXSOM_Pos (1U)
5533 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5534 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5535 #define CEC_CR_TXEOM_Pos (2U)
5536 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5537 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5538
5539 /******************* Bit definition for CEC_CFGR register *******************/
5540 #define CEC_CFGR_SFT_Pos (0U)
5541 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5542 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5543 #define CEC_CFGR_RXTOL_Pos (3U)
5544 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5545 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5546 #define CEC_CFGR_BRESTP_Pos (4U)
5547 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5548 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5549 #define CEC_CFGR_BREGEN_Pos (5U)
5550 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5551 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5552 #define CEC_CFGR_LBPEGEN_Pos (6U)
5553 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5554 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5555 #define CEC_CFGR_SFTOPT_Pos (8U)
5556 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5557 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5558 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5559 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5560 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5561 #define CEC_CFGR_OAR_Pos (16U)
5562 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5563 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5564 #define CEC_CFGR_LSTN_Pos (31U)
5565 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5566 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5567
5568 /******************* Bit definition for CEC_TXDR register *******************/
5569 #define CEC_TXDR_TXD_Pos (0U)
5570 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5571 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5572
5573 /******************* Bit definition for CEC_RXDR register *******************/
5574 #define CEC_RXDR_RXD_Pos (0U)
5575 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5576 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5577
5578 /******************* Bit definition for CEC_ISR register ********************/
5579 #define CEC_ISR_RXBR_Pos (0U)
5580 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5581 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5582 #define CEC_ISR_RXEND_Pos (1U)
5583 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5584 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5585 #define CEC_ISR_RXOVR_Pos (2U)
5586 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5587 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5588 #define CEC_ISR_BRE_Pos (3U)
5589 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5590 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5591 #define CEC_ISR_SBPE_Pos (4U)
5592 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5593 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5594 #define CEC_ISR_LBPE_Pos (5U)
5595 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5596 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5597 #define CEC_ISR_RXACKE_Pos (6U)
5598 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5599 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5600 #define CEC_ISR_ARBLST_Pos (7U)
5601 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5602 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5603 #define CEC_ISR_TXBR_Pos (8U)
5604 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5605 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5606 #define CEC_ISR_TXEND_Pos (9U)
5607 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5608 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5609 #define CEC_ISR_TXUDR_Pos (10U)
5610 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5611 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5612 #define CEC_ISR_TXERR_Pos (11U)
5613 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5614 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5615 #define CEC_ISR_TXACKE_Pos (12U)
5616 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5617 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5618
5619 /******************* Bit definition for CEC_IER register ********************/
5620 #define CEC_IER_RXBRIE_Pos (0U)
5621 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5622 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5623 #define CEC_IER_RXENDIE_Pos (1U)
5624 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5625 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5626 #define CEC_IER_RXOVRIE_Pos (2U)
5627 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5628 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5629 #define CEC_IER_BREIE_Pos (3U)
5630 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5631 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5632 #define CEC_IER_SBPEIE_Pos (4U)
5633 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5634 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5635 #define CEC_IER_LBPEIE_Pos (5U)
5636 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5637 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5638 #define CEC_IER_RXACKEIE_Pos (6U)
5639 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5640 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5641 #define CEC_IER_ARBLSTIE_Pos (7U)
5642 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5643 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5644 #define CEC_IER_TXBRIE_Pos (8U)
5645 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5646 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5647 #define CEC_IER_TXENDIE_Pos (9U)
5648 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5649 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5650 #define CEC_IER_TXUDRIE_Pos (10U)
5651 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5652 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5653 #define CEC_IER_TXERRIE_Pos (11U)
5654 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5655 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5656 #define CEC_IER_TXACKEIE_Pos (12U)
5657 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5658 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5659
5660 /******************************************************************************/
5661 /* */
5662 /* CRC calculation unit */
5663 /* */
5664 /******************************************************************************/
5665 /******************* Bit definition for CRC_DR register *********************/
5666 #define CRC_DR_DR_Pos (0U)
5667 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5668 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5669
5670 /******************* Bit definition for CRC_IDR register ********************/
5671 #define CRC_IDR_IDR_Pos (0U)
5672 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5673 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5674
5675 /******************** Bit definition for CRC_CR register ********************/
5676 #define CRC_CR_RESET_Pos (0U)
5677 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5678 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5679 #define CRC_CR_POLYSIZE_Pos (3U)
5680 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5681 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5682 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5683 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5684 #define CRC_CR_REV_IN_Pos (5U)
5685 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5686 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5687 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5688 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5689 #define CRC_CR_REV_OUT_Pos (7U)
5690 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5691 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5692
5693 /******************* Bit definition for CRC_INIT register *******************/
5694 #define CRC_INIT_INIT_Pos (0U)
5695 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5696 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5697
5698 /******************* Bit definition for CRC_POL register ********************/
5699 #define CRC_POL_POL_Pos (0U)
5700 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5701 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5702
5703 /******************************************************************************/
5704 /* */
5705 /* CRS Clock Recovery System */
5706 /******************************************************************************/
5707
5708 /******************* Bit definition for CRS_CR register *********************/
5709 #define CRS_CR_SYNCOKIE_Pos (0U)
5710 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5711 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5712 #define CRS_CR_SYNCWARNIE_Pos (1U)
5713 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5714 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5715 #define CRS_CR_ERRIE_Pos (2U)
5716 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5717 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5718 #define CRS_CR_ESYNCIE_Pos (3U)
5719 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5720 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5721 #define CRS_CR_CEN_Pos (5U)
5722 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5723 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5724 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5725 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5726 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5727 #define CRS_CR_SWSYNC_Pos (7U)
5728 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5729 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5730 #define CRS_CR_TRIM_Pos (8U)
5731 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5732 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5733
5734 /******************* Bit definition for CRS_CFGR register *********************/
5735 #define CRS_CFGR_RELOAD_Pos (0U)
5736 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5737 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5738 #define CRS_CFGR_FELIM_Pos (16U)
5739 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5740 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5741
5742 #define CRS_CFGR_SYNCDIV_Pos (24U)
5743 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5744 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5745 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5746 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5747 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5748
5749 #define CRS_CFGR_SYNCSRC_Pos (28U)
5750 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5751 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5752 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5753 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5754
5755 #define CRS_CFGR_SYNCPOL_Pos (31U)
5756 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5757 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5758
5759 /******************* Bit definition for CRS_ISR register *********************/
5760 #define CRS_ISR_SYNCOKF_Pos (0U)
5761 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5762 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5763 #define CRS_ISR_SYNCWARNF_Pos (1U)
5764 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5765 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5766 #define CRS_ISR_ERRF_Pos (2U)
5767 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5768 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5769 #define CRS_ISR_ESYNCF_Pos (3U)
5770 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5771 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5772 #define CRS_ISR_SYNCERR_Pos (8U)
5773 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5774 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5775 #define CRS_ISR_SYNCMISS_Pos (9U)
5776 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5777 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5778 #define CRS_ISR_TRIMOVF_Pos (10U)
5779 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5780 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5781 #define CRS_ISR_FEDIR_Pos (15U)
5782 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5783 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5784 #define CRS_ISR_FECAP_Pos (16U)
5785 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5786 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5787
5788 /******************* Bit definition for CRS_ICR register *********************/
5789 #define CRS_ICR_SYNCOKC_Pos (0U)
5790 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5791 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5792 #define CRS_ICR_SYNCWARNC_Pos (1U)
5793 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5794 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5795 #define CRS_ICR_ERRC_Pos (2U)
5796 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5797 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5798 #define CRS_ICR_ESYNCC_Pos (3U)
5799 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5800 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5801
5802 /******************************************************************************/
5803 /* */
5804 /* Digital to Analog Converter */
5805 /* */
5806 /******************************************************************************/
5807 /******************** Bit definition for DAC_CR register ********************/
5808 #define DAC_CR_EN1_Pos (0U)
5809 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5810 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5811 #define DAC_CR_TEN1_Pos (1U)
5812 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5813 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5814
5815 #define DAC_CR_TSEL1_Pos (2U)
5816 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5817 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5818 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5819 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5820 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5821 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5822
5823
5824 #define DAC_CR_WAVE1_Pos (6U)
5825 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5826 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5827 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5828 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5829
5830 #define DAC_CR_MAMP1_Pos (8U)
5831 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5832 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5833 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5834 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5835 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5836 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5837
5838 #define DAC_CR_DMAEN1_Pos (12U)
5839 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5840 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5841 #define DAC_CR_DMAUDRIE1_Pos (13U)
5842 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5843 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5844 #define DAC_CR_CEN1_Pos (14U)
5845 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5846 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5847
5848 #define DAC_CR_EN2_Pos (16U)
5849 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5850 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5851 #define DAC_CR_TEN2_Pos (17U)
5852 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5853 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5854
5855 #define DAC_CR_TSEL2_Pos (18U)
5856 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5857 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5858 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5859 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5860 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5861 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5862
5863
5864 #define DAC_CR_WAVE2_Pos (22U)
5865 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5866 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5867 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5868 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5869
5870 #define DAC_CR_MAMP2_Pos (24U)
5871 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5872 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5873 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5874 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5875 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5876 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5877
5878 #define DAC_CR_DMAEN2_Pos (28U)
5879 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5880 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5881 #define DAC_CR_DMAUDRIE2_Pos (29U)
5882 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5883 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5884 #define DAC_CR_CEN2_Pos (30U)
5885 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5886 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5887
5888 /***************** Bit definition for DAC_SWTRIGR register ******************/
5889 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5890 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5891 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5892 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5893 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5894 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5895
5896 /***************** Bit definition for DAC_DHR12R1 register ******************/
5897 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5898 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5899 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5900
5901 /***************** Bit definition for DAC_DHR12L1 register ******************/
5902 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5903 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5904 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5905
5906 /****************** Bit definition for DAC_DHR8R1 register ******************/
5907 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5908 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5909 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5910
5911 /***************** Bit definition for DAC_DHR12R2 register ******************/
5912 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5913 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5914 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5915
5916 /***************** Bit definition for DAC_DHR12L2 register ******************/
5917 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5918 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5919 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5920
5921 /****************** Bit definition for DAC_DHR8R2 register ******************/
5922 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5923 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5924 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5925
5926 /***************** Bit definition for DAC_DHR12RD register ******************/
5927 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5928 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5929 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5930 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5931 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5932 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5933
5934 /***************** Bit definition for DAC_DHR12LD register ******************/
5935 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5936 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5937 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5938 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5939 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5940 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5941
5942 /****************** Bit definition for DAC_DHR8RD register ******************/
5943 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5944 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5945 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5946 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5947 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5948 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5949
5950 /******************* Bit definition for DAC_DOR1 register *******************/
5951 #define DAC_DOR1_DACC1DOR_Pos (0U)
5952 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5953 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5954
5955 /******************* Bit definition for DAC_DOR2 register *******************/
5956 #define DAC_DOR2_DACC2DOR_Pos (0U)
5957 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5958 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5959
5960 /******************** Bit definition for DAC_SR register ********************/
5961 #define DAC_SR_DMAUDR1_Pos (13U)
5962 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5963 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5964 #define DAC_SR_CAL_FLAG1_Pos (14U)
5965 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5966 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5967 #define DAC_SR_BWST1_Pos (15U)
5968 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5969 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5970
5971 #define DAC_SR_DMAUDR2_Pos (29U)
5972 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5973 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5974 #define DAC_SR_CAL_FLAG2_Pos (30U)
5975 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5976 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5977 #define DAC_SR_BWST2_Pos (31U)
5978 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5979 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5980
5981 /******************* Bit definition for DAC_CCR register ********************/
5982 #define DAC_CCR_OTRIM1_Pos (0U)
5983 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5984 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5985 #define DAC_CCR_OTRIM2_Pos (16U)
5986 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5987 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5988
5989 /******************* Bit definition for DAC_MCR register *******************/
5990 #define DAC_MCR_MODE1_Pos (0U)
5991 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5992 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5993 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5994 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5995 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5996
5997 #define DAC_MCR_MODE2_Pos (16U)
5998 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5999 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
6000 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
6001 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
6002 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
6003
6004 /****************** Bit definition for DAC_SHSR1 register ******************/
6005 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
6006 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
6007 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
6008
6009 /****************** Bit definition for DAC_SHSR2 register ******************/
6010 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
6011 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
6012 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
6013
6014 /****************** Bit definition for DAC_SHHR register ******************/
6015 #define DAC_SHHR_THOLD1_Pos (0U)
6016 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
6017 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
6018 #define DAC_SHHR_THOLD2_Pos (16U)
6019 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
6020 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
6021
6022 /****************** Bit definition for DAC_SHRR register ******************/
6023 #define DAC_SHRR_TREFRESH1_Pos (0U)
6024 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
6025 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
6026 #define DAC_SHRR_TREFRESH2_Pos (16U)
6027 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
6028 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
6029
6030 /******************************************************************************/
6031 /* */
6032 /* DCMI */
6033 /* */
6034 /******************************************************************************/
6035 /******************** Bits definition for DCMI_CR register ******************/
6036 #define DCMI_CR_CAPTURE_Pos (0U)
6037 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
6038 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
6039 #define DCMI_CR_CM_Pos (1U)
6040 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
6041 #define DCMI_CR_CM DCMI_CR_CM_Msk
6042 #define DCMI_CR_CROP_Pos (2U)
6043 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
6044 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
6045 #define DCMI_CR_JPEG_Pos (3U)
6046 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
6047 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
6048 #define DCMI_CR_ESS_Pos (4U)
6049 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
6050 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
6051 #define DCMI_CR_PCKPOL_Pos (5U)
6052 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
6053 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
6054 #define DCMI_CR_HSPOL_Pos (6U)
6055 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
6056 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
6057 #define DCMI_CR_VSPOL_Pos (7U)
6058 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
6059 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
6060 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
6061 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
6062 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
6063 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
6064 #define DCMI_CR_CRE_Pos (12U)
6065 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
6066 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
6067 #define DCMI_CR_ENABLE_Pos (14U)
6068 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
6069 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
6070 #define DCMI_CR_BSM_Pos (16U)
6071 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6072 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
6073 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6074 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6075 #define DCMI_CR_OEBS_Pos (18U)
6076 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6077 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6078 #define DCMI_CR_LSM_Pos (19U)
6079 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6080 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
6081 #define DCMI_CR_OELS_Pos (20U)
6082 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6083 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
6084
6085 /******************** Bits definition for DCMI_SR register ******************/
6086 #define DCMI_SR_HSYNC_Pos (0U)
6087 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6088 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6089 #define DCMI_SR_VSYNC_Pos (1U)
6090 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6091 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6092 #define DCMI_SR_FNE_Pos (2U)
6093 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6094 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
6095
6096 /******************** Bits definition for DCMI_RIS register ****************/
6097 #define DCMI_RIS_FRAME_RIS_Pos (0U)
6098 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6099 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6100 #define DCMI_RIS_OVR_RIS_Pos (1U)
6101 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6102 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6103 #define DCMI_RIS_ERR_RIS_Pos (2U)
6104 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6105 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6106 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
6107 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6108 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6109 #define DCMI_RIS_LINE_RIS_Pos (4U)
6110 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6111 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6112
6113 /******************** Bits definition for DCMI_IER register *****************/
6114 #define DCMI_IER_FRAME_IE_Pos (0U)
6115 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6116 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6117 #define DCMI_IER_OVR_IE_Pos (1U)
6118 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6119 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6120 #define DCMI_IER_ERR_IE_Pos (2U)
6121 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6122 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6123 #define DCMI_IER_VSYNC_IE_Pos (3U)
6124 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6125 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6126 #define DCMI_IER_LINE_IE_Pos (4U)
6127 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6128 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6129
6130
6131 /******************** Bits definition for DCMI_MIS register *****************/
6132 #define DCMI_MIS_FRAME_MIS_Pos (0U)
6133 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6134 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6135 #define DCMI_MIS_OVR_MIS_Pos (1U)
6136 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6137 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6138 #define DCMI_MIS_ERR_MIS_Pos (2U)
6139 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6140 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6141 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6142 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6143 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6144 #define DCMI_MIS_LINE_MIS_Pos (4U)
6145 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6146 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6147
6148
6149 /******************** Bits definition for DCMI_ICR register *****************/
6150 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6151 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6152 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6153 #define DCMI_ICR_OVR_ISC_Pos (1U)
6154 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6155 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6156 #define DCMI_ICR_ERR_ISC_Pos (2U)
6157 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6158 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6159 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6160 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6161 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6162 #define DCMI_ICR_LINE_ISC_Pos (4U)
6163 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6164 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6165
6166
6167 /******************** Bits definition for DCMI_ESCR register ******************/
6168 #define DCMI_ESCR_FSC_Pos (0U)
6169 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6170 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6171 #define DCMI_ESCR_LSC_Pos (8U)
6172 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6173 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6174 #define DCMI_ESCR_LEC_Pos (16U)
6175 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6176 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6177 #define DCMI_ESCR_FEC_Pos (24U)
6178 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6179 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6180
6181 /******************** Bits definition for DCMI_ESUR register ******************/
6182 #define DCMI_ESUR_FSU_Pos (0U)
6183 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6184 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6185 #define DCMI_ESUR_LSU_Pos (8U)
6186 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6187 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6188 #define DCMI_ESUR_LEU_Pos (16U)
6189 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6190 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6191 #define DCMI_ESUR_FEU_Pos (24U)
6192 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6193 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6194
6195 /******************** Bits definition for DCMI_CWSTRT register ******************/
6196 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6197 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6198 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6199 #define DCMI_CWSTRT_VST_Pos (16U)
6200 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6201 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6202
6203 /******************** Bits definition for DCMI_CWSIZE register ******************/
6204 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6205 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6206 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6207 #define DCMI_CWSIZE_VLINE_Pos (16U)
6208 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6209 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6210
6211 /******************** Bits definition for DCMI_DR register ******************/
6212 #define DCMI_DR_BYTE0_Pos (0U)
6213 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6214 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6215 #define DCMI_DR_BYTE1_Pos (8U)
6216 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6217 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6218 #define DCMI_DR_BYTE2_Pos (16U)
6219 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6220 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6221 #define DCMI_DR_BYTE3_Pos (24U)
6222 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6223 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6224
6225 /******************************************************************************/
6226 /* */
6227 /* Digital Filter for Sigma Delta Modulators */
6228 /* */
6229 /******************************************************************************/
6230
6231 /**************** DFSDM channel configuration registers ********************/
6232
6233 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6234 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6235 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6236 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6237 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6238 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6239 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6240 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6241 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6242 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6243 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6244 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6245 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6246 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6247 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6248 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6249 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6250 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6251 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6252 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6253 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6254 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6255 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6256 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6257 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6258 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6259 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6260 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6261 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6262 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6263 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6264 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6265 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6266 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6267 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6268 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6269 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6270 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6271 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6272 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6273 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6274 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6275
6276 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6277 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6278 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6279 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6280 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6281 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6282 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6283
6284 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6285 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6286 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6287 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6288 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6289 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6290 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6291 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6292 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6293 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6294 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6295 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6296 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6297 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6298 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6299
6300 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6301 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6302 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6303 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6304
6305 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6306 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6307 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6308 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6309 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6310 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6311 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6312
6313 /************************ DFSDM module registers ****************************/
6314
6315 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
6316 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6317 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6318 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6319 #define DFSDM_FLTCR1_FAST_Pos (29U)
6320 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6321 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6322 #define DFSDM_FLTCR1_RCH_Pos (24U)
6323 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6324 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6325 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6326 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6327 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6328 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6329 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6330 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6331 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6332 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6333 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6334 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6335 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6336 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6337 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6338 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6339 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6340 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6341 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6342 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6343 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6344 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6345 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6346 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6347 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6348 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6349 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6350
6351 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6352 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6353 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6354 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6355 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6356 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6357 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6358 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6359 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6360 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6361 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6362 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6363 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6364 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6365 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6366
6367 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6368 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6369 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6370 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6371 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6372 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6373 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6374 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6375 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6376 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6377 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6378 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6379 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6380 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6381 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6382 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6383 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6384 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6385 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6386 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6387 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6388 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6389 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6390 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6391 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6392 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6393 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6394 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6395
6396 /******************** Bit definition for DFSDM_FLTISR register *******************/
6397 #define DFSDM_FLTISR_SCDF_Pos (24U)
6398 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6399 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6400 #define DFSDM_FLTISR_CKABF_Pos (16U)
6401 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6402 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6403 #define DFSDM_FLTISR_RCIP_Pos (14U)
6404 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6405 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6406 #define DFSDM_FLTISR_JCIP_Pos (13U)
6407 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6408 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6409 #define DFSDM_FLTISR_AWDF_Pos (4U)
6410 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6411 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6412 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6413 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6414 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6415 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6416 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6417 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6418 #define DFSDM_FLTISR_REOCF_Pos (1U)
6419 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6420 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6421 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6422 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6423 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6424
6425 /******************** Bit definition for DFSDM_FLTICR register *******************/
6426 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6427 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6428 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6429 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6430 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6431 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6432 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6433 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6434 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6435 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6436 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6437 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6438
6439 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6440 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6441 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6442 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6443
6444 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6445 #define DFSDM_FLTFCR_FORD_Pos (29U)
6446 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6447 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6448 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6449 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6450 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6451 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6452 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6453 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6454 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6455 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6456 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6457
6458 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6459 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6460 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6461 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6462 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6463 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6464 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6465
6466 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6467 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6468 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6469 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6470 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6471 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6472 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6473 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6474 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6475 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6476
6477 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6478 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6479 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6480 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6481 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6482 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6483 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6484
6485 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6486 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6487 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6488 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6489 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6490 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6491 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6492
6493 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6494 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6495 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6496 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6497 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6498 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6499 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6500
6501 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6502 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6503 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6504 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6505 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6506 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6507 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6508
6509 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6510 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6511 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6512 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6513 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6514 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6515 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6516
6517 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6518 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6519 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6520 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6521 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6522 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6523 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6524
6525 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6526 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6527 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6528 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6529
6530 /******************************************************************************/
6531 /* */
6532 /* BDMA Controller */
6533 /* */
6534 /******************************************************************************/
6535
6536 /******************* Bit definition for BDMA_ISR register ********************/
6537 #define BDMA_ISR_GIF0_Pos (0U)
6538 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6539 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6540 #define BDMA_ISR_TCIF0_Pos (1U)
6541 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6542 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6543 #define BDMA_ISR_HTIF0_Pos (2U)
6544 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6545 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6546 #define BDMA_ISR_TEIF0_Pos (3U)
6547 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6548 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6549 #define BDMA_ISR_GIF1_Pos (4U)
6550 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6551 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6552 #define BDMA_ISR_TCIF1_Pos (5U)
6553 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6554 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6555 #define BDMA_ISR_HTIF1_Pos (6U)
6556 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6557 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6558 #define BDMA_ISR_TEIF1_Pos (7U)
6559 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6560 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6561 #define BDMA_ISR_GIF2_Pos (8U)
6562 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6563 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6564 #define BDMA_ISR_TCIF2_Pos (9U)
6565 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6566 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6567 #define BDMA_ISR_HTIF2_Pos (10U)
6568 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6569 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6570 #define BDMA_ISR_TEIF2_Pos (11U)
6571 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6572 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6573 #define BDMA_ISR_GIF3_Pos (12U)
6574 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6575 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6576 #define BDMA_ISR_TCIF3_Pos (13U)
6577 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6578 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6579 #define BDMA_ISR_HTIF3_Pos (14U)
6580 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6581 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6582 #define BDMA_ISR_TEIF3_Pos (15U)
6583 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6584 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6585 #define BDMA_ISR_GIF4_Pos (16U)
6586 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6587 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6588 #define BDMA_ISR_TCIF4_Pos (17U)
6589 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6590 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6591 #define BDMA_ISR_HTIF4_Pos (18U)
6592 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6593 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6594 #define BDMA_ISR_TEIF4_Pos (19U)
6595 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6596 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6597 #define BDMA_ISR_GIF5_Pos (20U)
6598 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6599 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6600 #define BDMA_ISR_TCIF5_Pos (21U)
6601 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6602 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6603 #define BDMA_ISR_HTIF5_Pos (22U)
6604 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6605 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6606 #define BDMA_ISR_TEIF5_Pos (23U)
6607 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6608 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6609 #define BDMA_ISR_GIF6_Pos (24U)
6610 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6611 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6612 #define BDMA_ISR_TCIF6_Pos (25U)
6613 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6614 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6615 #define BDMA_ISR_HTIF6_Pos (26U)
6616 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6617 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6618 #define BDMA_ISR_TEIF6_Pos (27U)
6619 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6620 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6621 #define BDMA_ISR_GIF7_Pos (28U)
6622 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6623 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6624 #define BDMA_ISR_TCIF7_Pos (29U)
6625 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6626 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6627 #define BDMA_ISR_HTIF7_Pos (30U)
6628 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6629 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6630 #define BDMA_ISR_TEIF7_Pos (31U)
6631 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6632 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6633
6634 /******************* Bit definition for BDMA_IFCR register *******************/
6635 #define BDMA_IFCR_CGIF0_Pos (0U)
6636 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6637 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6638 #define BDMA_IFCR_CTCIF0_Pos (1U)
6639 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6640 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6641 #define BDMA_IFCR_CHTIF0_Pos (2U)
6642 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6643 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6644 #define BDMA_IFCR_CTEIF0_Pos (3U)
6645 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6646 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6647 #define BDMA_IFCR_CGIF1_Pos (4U)
6648 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6649 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6650 #define BDMA_IFCR_CTCIF1_Pos (5U)
6651 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6652 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6653 #define BDMA_IFCR_CHTIF1_Pos (6U)
6654 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6655 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6656 #define BDMA_IFCR_CTEIF1_Pos (7U)
6657 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6658 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6659 #define BDMA_IFCR_CGIF2_Pos (8U)
6660 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6661 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6662 #define BDMA_IFCR_CTCIF2_Pos (9U)
6663 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6664 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6665 #define BDMA_IFCR_CHTIF2_Pos (10U)
6666 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6667 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6668 #define BDMA_IFCR_CTEIF2_Pos (11U)
6669 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6670 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6671 #define BDMA_IFCR_CGIF3_Pos (12U)
6672 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6673 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6674 #define BDMA_IFCR_CTCIF3_Pos (13U)
6675 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6676 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6677 #define BDMA_IFCR_CHTIF3_Pos (14U)
6678 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6679 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6680 #define BDMA_IFCR_CTEIF3_Pos (15U)
6681 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6682 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6683 #define BDMA_IFCR_CGIF4_Pos (16U)
6684 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6685 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6686 #define BDMA_IFCR_CTCIF4_Pos (17U)
6687 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6688 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6689 #define BDMA_IFCR_CHTIF4_Pos (18U)
6690 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6691 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6692 #define BDMA_IFCR_CTEIF4_Pos (19U)
6693 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6694 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6695 #define BDMA_IFCR_CGIF5_Pos (20U)
6696 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6697 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6698 #define BDMA_IFCR_CTCIF5_Pos (21U)
6699 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6700 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6701 #define BDMA_IFCR_CHTIF5_Pos (22U)
6702 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6703 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6704 #define BDMA_IFCR_CTEIF5_Pos (23U)
6705 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6706 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6707 #define BDMA_IFCR_CGIF6_Pos (24U)
6708 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6709 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6710 #define BDMA_IFCR_CTCIF6_Pos (25U)
6711 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6712 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6713 #define BDMA_IFCR_CHTIF6_Pos (26U)
6714 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6715 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6716 #define BDMA_IFCR_CTEIF6_Pos (27U)
6717 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6718 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6719 #define BDMA_IFCR_CGIF7_Pos (28U)
6720 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6721 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6722 #define BDMA_IFCR_CTCIF7_Pos (29U)
6723 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6724 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6725 #define BDMA_IFCR_CHTIF7_Pos (30U)
6726 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6727 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6728 #define BDMA_IFCR_CTEIF7_Pos (31U)
6729 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6730 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6731
6732 /******************* Bit definition for BDMA_CCR register ********************/
6733 #define BDMA_CCR_EN_Pos (0U)
6734 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6735 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6736 #define BDMA_CCR_TCIE_Pos (1U)
6737 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6738 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6739 #define BDMA_CCR_HTIE_Pos (2U)
6740 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6741 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6742 #define BDMA_CCR_TEIE_Pos (3U)
6743 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6744 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6745 #define BDMA_CCR_DIR_Pos (4U)
6746 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6747 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6748 #define BDMA_CCR_CIRC_Pos (5U)
6749 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6750 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6751 #define BDMA_CCR_PINC_Pos (6U)
6752 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6753 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6754 #define BDMA_CCR_MINC_Pos (7U)
6755 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6756 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6757
6758 #define BDMA_CCR_PSIZE_Pos (8U)
6759 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6760 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6761 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6762 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6763
6764 #define BDMA_CCR_MSIZE_Pos (10U)
6765 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6766 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6767 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6768 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6769
6770 #define BDMA_CCR_PL_Pos (12U)
6771 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6772 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6773 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6774 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6775
6776 #define BDMA_CCR_MEM2MEM_Pos (14U)
6777 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6778 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6779 #define BDMA_CCR_DBM_Pos (15U)
6780 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6781 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6782 #define BDMA_CCR_CT_Pos (16U)
6783 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6784 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6785
6786 /****************** Bit definition for BDMA_CNDTR register *******************/
6787 #define BDMA_CNDTR_NDT_Pos (0U)
6788 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6789 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6790
6791 /****************** Bit definition for BDMA_CPAR register ********************/
6792 #define BDMA_CPAR_PA_Pos (0U)
6793 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6794 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6795
6796 /****************** Bit definition for BDMA_CM0AR register ********************/
6797 #define BDMA_CM0AR_MA_Pos (0U)
6798 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6799 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6800
6801 /****************** Bit definition for BDMA_CM1AR register ********************/
6802 #define BDMA_CM1AR_MA_Pos (0U)
6803 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6804 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6805
6806 /******************************************************************************/
6807 /* */
6808 /* Ethernet MAC Registers bits definitions */
6809 /* */
6810 /******************************************************************************/
6811 /* Bit definition for Ethernet MAC Configuration Register register */
6812 #define ETH_MACCR_ARP_Pos (31U)
6813 #define ETH_MACCR_ARP_Msk (0x1UL << ETH_MACCR_ARP_Pos) /*!< 0x80000000 */
6814 #define ETH_MACCR_ARP ETH_MACCR_ARP_Msk /* ARP Offload Enable */
6815 #define ETH_MACCR_SARC_Pos (28U)
6816 #define ETH_MACCR_SARC_Msk (0x7UL << ETH_MACCR_SARC_Pos) /*!< 0x70000000 */
6817 #define ETH_MACCR_SARC ETH_MACCR_SARC_Msk /* Source Address Insertion or Replacement Control */
6818 #define ETH_MACCR_SARC_MTIATI ((uint32_t)0x00000000) /* The mti_sa_ctrl_i and ati_sa_ctrl_i input signals control the SA field generation. */
6819 #define ETH_MACCR_SARC_INSADDR0_Pos (29U)
6820 #define ETH_MACCR_SARC_INSADDR0_Msk (0x1UL << ETH_MACCR_SARC_INSADDR0_Pos) /*!< 0x20000000 */
6821 #define ETH_MACCR_SARC_INSADDR0 ETH_MACCR_SARC_INSADDR0_Msk /* Insert MAC Address0 in the SA field of all transmitted packets. */
6822 #define ETH_MACCR_SARC_INSADDR1_Pos (29U)
6823 #define ETH_MACCR_SARC_INSADDR1_Msk (0x3UL << ETH_MACCR_SARC_INSADDR1_Pos) /*!< 0x60000000 */
6824 #define ETH_MACCR_SARC_INSADDR1 ETH_MACCR_SARC_INSADDR1_Msk /* Insert MAC Address1 in the SA field of all transmitted packets. */
6825 #define ETH_MACCR_SARC_REPADDR0_Pos (28U)
6826 #define ETH_MACCR_SARC_REPADDR0_Msk (0x3UL << ETH_MACCR_SARC_REPADDR0_Pos) /*!< 0x30000000 */
6827 #define ETH_MACCR_SARC_REPADDR0 ETH_MACCR_SARC_REPADDR0_Msk /* Replace MAC Address0 in the SA field of all transmitted packets. */
6828 #define ETH_MACCR_SARC_REPADDR1_Pos (28U)
6829 #define ETH_MACCR_SARC_REPADDR1_Msk (0x7UL << ETH_MACCR_SARC_REPADDR1_Pos) /*!< 0x70000000 */
6830 #define ETH_MACCR_SARC_REPADDR1 ETH_MACCR_SARC_REPADDR1_Msk /* Replace MAC Address1 in the SA field of all transmitted packets. */
6831 #define ETH_MACCR_IPC_Pos (27U)
6832 #define ETH_MACCR_IPC_Msk (0x1UL << ETH_MACCR_IPC_Pos) /*!< 0x08000000 */
6833 #define ETH_MACCR_IPC ETH_MACCR_IPC_Msk /* Checksum Offload */
6834 #define ETH_MACCR_IPG_Pos (24U)
6835 #define ETH_MACCR_IPG_Msk (0x7UL << ETH_MACCR_IPG_Pos) /*!< 0x07000000 */
6836 #define ETH_MACCR_IPG ETH_MACCR_IPG_Msk /* Inter-Packet Gap */
6837 #define ETH_MACCR_IPG_96BIT ((uint32_t)0x00000000) /* Minimum IFG between Packets during transmission is 96Bit */
6838 #define ETH_MACCR_IPG_88BIT ((uint32_t)0x01000000) /* Minimum IFG between Packets during transmission is 88Bit */
6839 #define ETH_MACCR_IPG_80BIT ((uint32_t)0x02000000) /* Minimum IFG between Packets during transmission is 80Bit */
6840 #define ETH_MACCR_IPG_72BIT ((uint32_t)0x03000000) /* Minimum IFG between Packets during transmission is 72Bit */
6841 #define ETH_MACCR_IPG_64BIT ((uint32_t)0x04000000) /* Minimum IFG between Packets during transmission is 64Bit */
6842 #define ETH_MACCR_IPG_56BIT ((uint32_t)0x05000000) /* Minimum IFG between Packets during transmission is 56Bit */
6843 #define ETH_MACCR_IPG_48BIT ((uint32_t)0x06000000) /* Minimum IFG between Packets during transmission is 48Bit */
6844 #define ETH_MACCR_IPG_40BIT ((uint32_t)0x07000000) /* Minimum IFG between Packets during transmission is 40Bit */
6845 #define ETH_MACCR_GPSLCE_Pos (23U)
6846 #define ETH_MACCR_GPSLCE_Msk (0x1UL << ETH_MACCR_GPSLCE_Pos) /*!< 0x00800000 */
6847 #define ETH_MACCR_GPSLCE ETH_MACCR_GPSLCE_Msk /* Giant Packet Size Limit Control Enable */
6848 #define ETH_MACCR_S2KP_Pos (22U)
6849 #define ETH_MACCR_S2KP_Msk (0x1UL << ETH_MACCR_S2KP_Pos) /*!< 0x00400000 */
6850 #define ETH_MACCR_S2KP ETH_MACCR_S2KP_Msk /* IEEE 802.3as Support for 2K Packets */
6851 #define ETH_MACCR_CST_Pos (21U)
6852 #define ETH_MACCR_CST_Msk (0x1UL << ETH_MACCR_CST_Pos) /*!< 0x00200000 */
6853 #define ETH_MACCR_CST ETH_MACCR_CST_Msk /* CRC stripping for Type packets */
6854 #define ETH_MACCR_ACS_Pos (20U)
6855 #define ETH_MACCR_ACS_Msk (0x1UL << ETH_MACCR_ACS_Pos) /*!< 0x00100000 */
6856 #define ETH_MACCR_ACS ETH_MACCR_ACS_Msk /* Automatic Pad or CRC Stripping */
6857 #define ETH_MACCR_WD_Pos (19U)
6858 #define ETH_MACCR_WD_Msk (0x1UL << ETH_MACCR_WD_Pos) /*!< 0x00080000 */
6859 #define ETH_MACCR_WD ETH_MACCR_WD_Msk /* Watchdog disable */
6860 #define ETH_MACCR_JD_Pos (17U)
6861 #define ETH_MACCR_JD_Msk (0x1UL << ETH_MACCR_JD_Pos) /*!< 0x00020000 */
6862 #define ETH_MACCR_JD ETH_MACCR_JD_Msk /* Jabber disable */
6863 #define ETH_MACCR_JE_Pos (16U)
6864 #define ETH_MACCR_JE_Msk (0x1UL << ETH_MACCR_JE_Pos) /*!< 0x00010000 */
6865 #define ETH_MACCR_JE ETH_MACCR_JE_Msk /* Jumbo Packet Enable */
6866 #define ETH_MACCR_FES_Pos (14U)
6867 #define ETH_MACCR_FES_Msk (0x1UL << ETH_MACCR_FES_Pos) /*!< 0x00004000 */
6868 #define ETH_MACCR_FES ETH_MACCR_FES_Msk /* Fast ethernet speed */
6869 #define ETH_MACCR_DM_Pos (13U)
6870 #define ETH_MACCR_DM_Msk (0x1UL << ETH_MACCR_DM_Pos) /*!< 0x00002000 */
6871 #define ETH_MACCR_DM ETH_MACCR_DM_Msk /* Duplex mode */
6872 #define ETH_MACCR_LM_Pos (12U)
6873 #define ETH_MACCR_LM_Msk (0x1UL << ETH_MACCR_LM_Pos) /*!< 0x00001000 */
6874 #define ETH_MACCR_LM ETH_MACCR_LM_Msk /* loopback mode */
6875 #define ETH_MACCR_ECRSFD_Pos (11U)
6876 #define ETH_MACCR_ECRSFD_Msk (0x1UL << ETH_MACCR_ECRSFD_Pos) /*!< 0x00000800 */
6877 #define ETH_MACCR_ECRSFD ETH_MACCR_ECRSFD_Msk /* Enable Carrier Sense Before Transmission in Full-Duplex Mode */
6878 #define ETH_MACCR_DO_Pos (10U)
6879 #define ETH_MACCR_DO_Msk (0x1UL << ETH_MACCR_DO_Pos) /*!< 0x00000400 */
6880 #define ETH_MACCR_DO ETH_MACCR_DO_Msk /* Disable Receive own */
6881 #define ETH_MACCR_DCRS_Pos (9U)
6882 #define ETH_MACCR_DCRS_Msk (0x1UL << ETH_MACCR_DCRS_Pos) /*!< 0x00000200 */
6883 #define ETH_MACCR_DCRS ETH_MACCR_DCRS_Msk /* Disable Carrier Sense During Transmission */
6884 #define ETH_MACCR_DR_Pos (8U)
6885 #define ETH_MACCR_DR_Msk (0x1UL << ETH_MACCR_DR_Pos) /*!< 0x00000100 */
6886 #define ETH_MACCR_DR ETH_MACCR_DR_Msk /* Disable Retry */
6887 #define ETH_MACCR_BL_Pos (5U)
6888 #define ETH_MACCR_BL_Msk (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6889 #define ETH_MACCR_BL ETH_MACCR_BL_Msk /* Back-off limit mask */
6890 #define ETH_MACCR_BL_10 (0x0UL << ETH_MACCR_BL_Pos) /*!< 0x00000000 */
6891 #define ETH_MACCR_BL_8 (0x1UL << ETH_MACCR_BL_Pos) /*!< 0x00000020 */
6892 #define ETH_MACCR_BL_4 (0x2UL << ETH_MACCR_BL_Pos) /*!< 0x00000040 */
6893 #define ETH_MACCR_BL_1 (0x3UL << ETH_MACCR_BL_Pos) /*!< 0x00000060 */
6894 #define ETH_MACCR_DC_Pos (4U)
6895 #define ETH_MACCR_DC_Msk (0x1UL << ETH_MACCR_DC_Pos) /*!< 0x00000010 */
6896 #define ETH_MACCR_DC ETH_MACCR_DC_Msk /* Defferal check */
6897 #define ETH_MACCR_PRELEN_Pos (2U)
6898 #define ETH_MACCR_PRELEN_Msk (0x3UL << ETH_MACCR_PRELEN_Pos) /*!< 0x0000000C */
6899 #define ETH_MACCR_PRELEN ETH_MACCR_PRELEN_Msk /* Preamble Length for Transmit packets */
6900 #define ETH_MACCR_PRELEN_7 (0x0UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000000 */
6901 #define ETH_MACCR_PRELEN_5 (0x1UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000004 */
6902 #define ETH_MACCR_PRELEN_3 (0x2UL << ETH_MACCR_PRELEN_Pos) /*!< 0x00000008 */
6903 #define ETH_MACCR_TE_Pos (1U)
6904 #define ETH_MACCR_TE_Msk (0x1UL << ETH_MACCR_TE_Pos) /*!< 0x00000002 */
6905 #define ETH_MACCR_TE ETH_MACCR_TE_Msk /* Transmitter enable */
6906 #define ETH_MACCR_RE_Pos (0U)
6907 #define ETH_MACCR_RE_Msk (0x1UL << ETH_MACCR_RE_Pos) /*!< 0x00000001 */
6908 #define ETH_MACCR_RE ETH_MACCR_RE_Msk /* Receiver enable */
6909
6910 /* Bit definition for Ethernet MAC Extended Configuration Register register */
6911 #define ETH_MACECR_EIPG_Pos (25U)
6912 #define ETH_MACECR_EIPG_Msk (0x1FUL << ETH_MACECR_EIPG_Pos) /*!< 0x3E000000 */
6913 #define ETH_MACECR_EIPG ETH_MACECR_EIPG_Msk /* Extended Inter-Packet Gap */
6914 #define ETH_MACECR_EIPGEN_Pos (24U)
6915 #define ETH_MACECR_EIPGEN_Msk (0x1UL << ETH_MACECR_EIPGEN_Pos) /*!< 0x01000000 */
6916 #define ETH_MACECR_EIPGEN ETH_MACECR_EIPGEN_Msk /* Extended Inter-Packet Gap Enable */
6917 #define ETH_MACECR_USP_Pos (18U)
6918 #define ETH_MACECR_USP_Msk (0x1UL << ETH_MACECR_USP_Pos) /*!< 0x00040000 */
6919 #define ETH_MACECR_USP ETH_MACECR_USP_Msk /* Unicast Slow Protocol Packet Detect */
6920 #define ETH_MACECR_SPEN_Pos (17U)
6921 #define ETH_MACECR_SPEN_Msk (0x1UL << ETH_MACECR_SPEN_Pos) /*!< 0x00020000 */
6922 #define ETH_MACECR_SPEN ETH_MACECR_SPEN_Msk /* Slow Protocol Detection Enable */
6923 #define ETH_MACECR_DCRCC_Pos (16U)
6924 #define ETH_MACECR_DCRCC_Msk (0x1UL << ETH_MACECR_DCRCC_Pos) /*!< 0x00010000 */
6925 #define ETH_MACECR_DCRCC ETH_MACECR_DCRCC_Msk /* Disable CRC Checking for Received Packets */
6926 #define ETH_MACECR_GPSL_Pos (0U)
6927 #define ETH_MACECR_GPSL_Msk (0x3FFFUL << ETH_MACECR_GPSL_Pos) /*!< 0x00003FFF */
6928 #define ETH_MACECR_GPSL ETH_MACECR_GPSL_Msk /* Giant Packet Size Limit */
6929
6930 /* Bit definition for Ethernet MAC Packet Filter Register */
6931 #define ETH_MACPFR_RA_Pos (31U)
6932 #define ETH_MACPFR_RA_Msk (0x1UL << ETH_MACPFR_RA_Pos) /*!< 0x80000000 */
6933 #define ETH_MACPFR_RA ETH_MACPFR_RA_Msk /* Receive all */
6934 #define ETH_MACPFR_DNTU_Pos (21U)
6935 #define ETH_MACPFR_DNTU_Msk (0x1UL << ETH_MACPFR_DNTU_Pos) /*!< 0x00200000 */
6936 #define ETH_MACPFR_DNTU ETH_MACPFR_DNTU_Msk /* Drop Non-TCP/UDP over IP Packets */
6937 #define ETH_MACPFR_IPFE_Pos (20U)
6938 #define ETH_MACPFR_IPFE_Msk (0x1UL << ETH_MACPFR_IPFE_Pos) /*!< 0x00100000 */
6939 #define ETH_MACPFR_IPFE ETH_MACPFR_IPFE_Msk /* Layer 3 and Layer 4 Filter Enable */
6940 #define ETH_MACPFR_VTFE_Pos (16U)
6941 #define ETH_MACPFR_VTFE_Msk (0x1UL << ETH_MACPFR_VTFE_Pos) /*!< 0x00010000 */
6942 #define ETH_MACPFR_VTFE ETH_MACPFR_VTFE_Msk /* VLAN Tag Filter Enable */
6943 #define ETH_MACPFR_HPF_Pos (10U)
6944 #define ETH_MACPFR_HPF_Msk (0x1UL << ETH_MACPFR_HPF_Pos) /*!< 0x00000400 */
6945 #define ETH_MACPFR_HPF ETH_MACPFR_HPF_Msk /* Hash or perfect filter */
6946 #define ETH_MACPFR_SAF_Pos (9U)
6947 #define ETH_MACPFR_SAF_Msk (0x1UL << ETH_MACPFR_SAF_Pos) /*!< 0x00000200 */
6948 #define ETH_MACPFR_SAF ETH_MACPFR_SAF_Msk /* Source address filter enable */
6949 #define ETH_MACPFR_SAIF_Pos (8U)
6950 #define ETH_MACPFR_SAIF_Msk (0x1UL << ETH_MACPFR_SAIF_Pos) /*!< 0x00000100 */
6951 #define ETH_MACPFR_SAIF ETH_MACPFR_SAIF_Msk /* SA inverse filtering */
6952 #define ETH_MACPFR_PCF_Pos (6U)
6953 #define ETH_MACPFR_PCF_Msk (0x3UL << ETH_MACPFR_PCF_Pos) /*!< 0x000000C0 */
6954 #define ETH_MACPFR_PCF ETH_MACPFR_PCF_Msk /* Pass control frames: 4 cases */
6955 #define ETH_MACPFR_PCF_BLOCKALL ((uint32_t)0x00000000) /* MAC filters all control frames from reaching the application */
6956 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos (6U)
6957 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Pos) /*!< 0x00000040 */
6958 #define ETH_MACPFR_PCF_FORWARDALLEXCEPTPA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA_Msk /* MAC forwards all control frames except Pause packets to application even if they fail the Address Filter */
6959 #define ETH_MACPFR_PCF_FORWARDALL_Pos (7U)
6960 #define ETH_MACPFR_PCF_FORWARDALL_Msk (0x1UL << ETH_MACPFR_PCF_FORWARDALL_Pos) /*!< 0x00000080 */
6961 #define ETH_MACPFR_PCF_FORWARDALL ETH_MACPFR_PCF_FORWARDALL_Msk /* MAC forwards all control frames to application even if they fail the Address Filter */
6962 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos (6U)
6963 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk (0x3UL << ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Pos) /*!< 0x000000C0 */
6964 #define ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER_Msk /* MAC forwards control frames that pass the Address Filter. */
6965 #define ETH_MACPFR_DBF_Pos (5U)
6966 #define ETH_MACPFR_DBF_Msk (0x1UL << ETH_MACPFR_DBF_Pos) /*!< 0x00000020 */
6967 #define ETH_MACPFR_DBF ETH_MACPFR_DBF_Msk /* Disable Broadcast Packets */
6968 #define ETH_MACPFR_PM_Pos (4U)
6969 #define ETH_MACPFR_PM_Msk (0x1UL << ETH_MACPFR_PM_Pos) /*!< 0x00000010 */
6970 #define ETH_MACPFR_PM ETH_MACPFR_PM_Msk /* Pass all mutlicast */
6971 #define ETH_MACPFR_DAIF_Pos (3U)
6972 #define ETH_MACPFR_DAIF_Msk (0x1UL << ETH_MACPFR_DAIF_Pos) /*!< 0x00000008 */
6973 #define ETH_MACPFR_DAIF ETH_MACPFR_DAIF_Msk /* DA Inverse filtering */
6974 #define ETH_MACPFR_HMC_Pos (2U)
6975 #define ETH_MACPFR_HMC_Msk (0x1UL << ETH_MACPFR_HMC_Pos) /*!< 0x00000004 */
6976 #define ETH_MACPFR_HMC ETH_MACPFR_HMC_Msk /* Hash multicast */
6977 #define ETH_MACPFR_HUC_Pos (1U)
6978 #define ETH_MACPFR_HUC_Msk (0x1UL << ETH_MACPFR_HUC_Pos) /*!< 0x00000002 */
6979 #define ETH_MACPFR_HUC ETH_MACPFR_HUC_Msk /* Hash unicast */
6980 #define ETH_MACPFR_PR_Pos (0U)
6981 #define ETH_MACPFR_PR_Msk (0x1UL << ETH_MACPFR_PR_Pos) /*!< 0x00000001 */
6982 #define ETH_MACPFR_PR ETH_MACPFR_PR_Msk /* Promiscuous mode */
6983
6984 /* Bit definition for Ethernet MAC Watchdog Timeout Register */
6985 #define ETH_MACWTR_PWE_Pos (8U)
6986 #define ETH_MACWTR_PWE_Msk (0x1UL << ETH_MACWTR_PWE_Pos) /*!< 0x00000100 */
6987 #define ETH_MACWTR_PWE ETH_MACWTR_PWE_Msk /* Programmable Watchdog Enable */
6988 #define ETH_MACWTR_WTO_Pos (0U)
6989 #define ETH_MACWTR_WTO_Msk (0xFUL << ETH_MACWTR_WTO_Pos) /*!< 0x0000000F */
6990 #define ETH_MACWTR_WTO ETH_MACWTR_WTO_Msk /* Watchdog Timeout */
6991 #define ETH_MACWTR_WTO_2KB ((uint32_t)0x00000000) /* Maximum received packet length 2KB*/
6992 #define ETH_MACWTR_WTO_3KB ((uint32_t)0x00000001) /* Maximum received packet length 3KB */
6993 #define ETH_MACWTR_WTO_4KB ((uint32_t)0x00000002) /* Maximum received packet length 4KB */
6994 #define ETH_MACWTR_WTO_5KB ((uint32_t)0x00000003) /* Maximum received packet length 5KB */
6995 #define ETH_MACWTR_WTO_6KB ((uint32_t)0x00000004) /* Maximum received packet length 6KB */
6996 #define ETH_MACWTR_WTO_7KB ((uint32_t)0x00000005) /* Maximum received packet length 7KB */
6997 #define ETH_MACWTR_WTO_8KB ((uint32_t)0x00000006) /* Maximum received packet length 8KB */
6998 #define ETH_MACWTR_WTO_9KB ((uint32_t)0x00000007) /* Maximum received packet length 9KB */
6999 #define ETH_MACWTR_WTO_10KB ((uint32_t)0x00000008) /* Maximum received packet length 10KB */
7000 #define ETH_MACWTR_WTO_11KB ((uint32_t)0x00000009) /* Maximum received packet length 11KB */
7001 #define ETH_MACWTR_WTO_12KB ((uint32_t)0x0000000A) /* Maximum received packet length 12KB */
7002 #define ETH_MACWTR_WTO_13KB ((uint32_t)0x0000000B) /* Maximum received packet length 13KB */
7003 #define ETH_MACWTR_WTO_14KB ((uint32_t)0x0000000C) /* Maximum received packet length 14KB */
7004 #define ETH_MACWTR_WTO_15KB ((uint32_t)0x0000000D) /* Maximum received packet length 15KB */
7005 #define ETH_MACWTR_WTO_16KB ((uint32_t)0x0000000E) /* Maximum received packet length 16KB */
7006
7007 /* Bit definition for Ethernet MAC Hash Table High Register */
7008 #define ETH_MACHTHR_HTH_Pos (0U)
7009 #define ETH_MACHTHR_HTH_Msk (0xFFFFFFFFUL << ETH_MACHTHR_HTH_Pos) /*!< 0xFFFFFFFF */
7010 #define ETH_MACHTHR_HTH ETH_MACHTHR_HTH_Msk /* Hash table high */
7011
7012 /* Bit definition for Ethernet MAC Hash Table Low Register */
7013 #define ETH_MACHTLR_HTL_Pos (0U)
7014 #define ETH_MACHTLR_HTL_Msk (0xFFFFFFFFUL << ETH_MACHTLR_HTL_Pos) /*!< 0xFFFFFFFF */
7015 #define ETH_MACHTLR_HTL ETH_MACHTLR_HTL_Msk /* Hash table low */
7016
7017 /* Bit definition for Ethernet MAC VLAN Tag Register */
7018 #define ETH_MACVTR_EIVLRXS_Pos (31U)
7019 #define ETH_MACVTR_EIVLRXS_Msk (0x1UL << ETH_MACVTR_EIVLRXS_Pos) /*!< 0x80000000 */
7020 #define ETH_MACVTR_EIVLRXS ETH_MACVTR_EIVLRXS_Msk /* Enable Inner VLAN Tag in Rx Status */
7021 #define ETH_MACVTR_EIVLS_Pos (28U)
7022 #define ETH_MACVTR_EIVLS_Msk (0x3UL << ETH_MACVTR_EIVLS_Pos) /*!< 0x30000000 */
7023 #define ETH_MACVTR_EIVLS ETH_MACVTR_EIVLS_Msk /* Enable Inner VLAN Tag Stripping on Receive */
7024 #define ETH_MACVTR_EIVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7025 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Pos (28U)
7026 #define ETH_MACVTR_EIVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFPASS_Pos) /*!< 0x10000000 */
7027 #define ETH_MACVTR_EIVLS_STRIPIFPASS ETH_MACVTR_EIVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7028 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos (29U)
7029 #define ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EIVLS_STRIPIFFAILS_Pos) /*!< 0x20000000 */
7030 #define ETH_MACVTR_EIVLS_STRIPIFFAILS ETH_MACVTR_EIVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7031 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos (28U)
7032 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EIVLS_ALWAYSSTRIP_Pos) /*!< 0x30000000 */
7033 #define ETH_MACVTR_EIVLS_ALWAYSSTRIP ETH_MACVTR_EIVLS_ALWAYSSTRIP_Msk /* Always strip */
7034 #define ETH_MACVTR_ERIVLT_Pos (27U)
7035 #define ETH_MACVTR_ERIVLT_Msk (0x1UL << ETH_MACVTR_ERIVLT_Pos) /*!< 0x08000000 */
7036 #define ETH_MACVTR_ERIVLT ETH_MACVTR_ERIVLT_Msk /* Enable Inner VLAN Tag */
7037 #define ETH_MACVTR_EDVLP_Pos (26U)
7038 #define ETH_MACVTR_EDVLP_Msk (0x1UL << ETH_MACVTR_EDVLP_Pos) /*!< 0x04000000 */
7039 #define ETH_MACVTR_EDVLP ETH_MACVTR_EDVLP_Msk /* Enable Double VLAN Processing */
7040 #define ETH_MACVTR_VTHM_Pos (25U)
7041 #define ETH_MACVTR_VTHM_Msk (0x1UL << ETH_MACVTR_VTHM_Pos) /*!< 0x02000000 */
7042 #define ETH_MACVTR_VTHM ETH_MACVTR_VTHM_Msk /* VLAN Tag Hash Table Match Enable */
7043 #define ETH_MACVTR_EVLRXS_Pos (24U)
7044 #define ETH_MACVTR_EVLRXS_Msk (0x1UL << ETH_MACVTR_EVLRXS_Pos) /*!< 0x01000000 */
7045 #define ETH_MACVTR_EVLRXS ETH_MACVTR_EVLRXS_Msk /* Enable VLAN Tag in Rx status */
7046 #define ETH_MACVTR_EVLS_Pos (21U)
7047 #define ETH_MACVTR_EVLS_Msk (0x3UL << ETH_MACVTR_EVLS_Pos) /*!< 0x00600000 */
7048 #define ETH_MACVTR_EVLS ETH_MACVTR_EVLS_Msk /* Enable VLAN Tag Stripping on Receive */
7049 #define ETH_MACVTR_EVLS_DONOTSTRIP ((uint32_t)0x00000000) /* Do not strip */
7050 #define ETH_MACVTR_EVLS_STRIPIFPASS_Pos (21U)
7051 #define ETH_MACVTR_EVLS_STRIPIFPASS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFPASS_Pos) /*!< 0x00200000 */
7052 #define ETH_MACVTR_EVLS_STRIPIFPASS ETH_MACVTR_EVLS_STRIPIFPASS_Msk /* Strip if VLAN filter passes */
7053 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Pos (22U)
7054 #define ETH_MACVTR_EVLS_STRIPIFFAILS_Msk (0x1UL << ETH_MACVTR_EVLS_STRIPIFFAILS_Pos) /*!< 0x00400000 */
7055 #define ETH_MACVTR_EVLS_STRIPIFFAILS ETH_MACVTR_EVLS_STRIPIFFAILS_Msk /* Strip if VLAN filter fails */
7056 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos (21U)
7057 #define ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk (0x3UL << ETH_MACVTR_EVLS_ALWAYSSTRIP_Pos) /*!< 0x00600000 */
7058 #define ETH_MACVTR_EVLS_ALWAYSSTRIP ETH_MACVTR_EVLS_ALWAYSSTRIP_Msk /* Always strip */
7059 #define ETH_MACVTR_DOVLTC_Pos (20U)
7060 #define ETH_MACVTR_DOVLTC_Msk (0x1UL << ETH_MACVTR_DOVLTC_Pos) /*!< 0x00100000 */
7061 #define ETH_MACVTR_DOVLTC ETH_MACVTR_DOVLTC_Msk /* Disable VLAN Type Check */
7062 #define ETH_MACVTR_ERSVLM_Pos (19U)
7063 #define ETH_MACVTR_ERSVLM_Msk (0x1UL << ETH_MACVTR_ERSVLM_Pos) /*!< 0x00080000 */
7064 #define ETH_MACVTR_ERSVLM ETH_MACVTR_ERSVLM_Msk /* Enable Receive S-VLAN Match */
7065 #define ETH_MACVTR_ESVL_Pos (18U)
7066 #define ETH_MACVTR_ESVL_Msk (0x1UL << ETH_MACVTR_ESVL_Pos) /*!< 0x00040000 */
7067 #define ETH_MACVTR_ESVL ETH_MACVTR_ESVL_Msk /* Enable S-VLAN */
7068 #define ETH_MACVTR_VTIM_Pos (17U)
7069 #define ETH_MACVTR_VTIM_Msk (0x1UL << ETH_MACVTR_VTIM_Pos) /*!< 0x00020000 */
7070 #define ETH_MACVTR_VTIM ETH_MACVTR_VTIM_Msk /* VLAN Tag Inverse Match Enable */
7071 #define ETH_MACVTR_ETV_Pos (16U)
7072 #define ETH_MACVTR_ETV_Msk (0x1UL << ETH_MACVTR_ETV_Pos) /*!< 0x00010000 */
7073 #define ETH_MACVTR_ETV ETH_MACVTR_ETV_Msk /* Enable 12-Bit VLAN Tag Comparison */
7074 #define ETH_MACVTR_VL_Pos (0U)
7075 #define ETH_MACVTR_VL_Msk (0xFFFFUL << ETH_MACVTR_VL_Pos) /*!< 0x0000FFFF */
7076 #define ETH_MACVTR_VL ETH_MACVTR_VL_Msk /* VLAN Tag Identifier for Receive Packets */
7077 #define ETH_MACVTR_VL_UP_Pos (13U)
7078 #define ETH_MACVTR_VL_UP_Msk (0x7UL << ETH_MACVTR_VL_UP_Pos) /*!< 0x0000E000 */
7079 #define ETH_MACVTR_VL_UP ETH_MACVTR_VL_UP_Msk /* User Priority */
7080 #define ETH_MACVTR_VL_CFIDEI_Pos (12U)
7081 #define ETH_MACVTR_VL_CFIDEI_Msk (0x1UL << ETH_MACVTR_VL_CFIDEI_Pos) /*!< 0x00001000 */
7082 #define ETH_MACVTR_VL_CFIDEI ETH_MACVTR_VL_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7083 #define ETH_MACVTR_VL_VID_Pos (0U)
7084 #define ETH_MACVTR_VL_VID_Msk (0xFFFUL << ETH_MACVTR_VL_VID_Pos) /*!< 0x00000FFF */
7085 #define ETH_MACVTR_VL_VID ETH_MACVTR_VL_VID_Msk /* VLAN Identifier field of VLAN tag */
7086
7087 /* Bit definition for Ethernet MAC VLAN Hash Table Register */
7088 #define ETH_MACVHTR_VLHT_Pos (0U)
7089 #define ETH_MACVHTR_VLHT_Msk (0xFFFFUL << ETH_MACVHTR_VLHT_Pos) /*!< 0x0000FFFF */
7090 #define ETH_MACVHTR_VLHT ETH_MACVHTR_VLHT_Msk /* VLAN Hash Table */
7091
7092 /* Bit definition for Ethernet MAC VLAN Incl Register */
7093 #define ETH_MACVIR_VLTI_Pos (20U)
7094 #define ETH_MACVIR_VLTI_Msk (0x1UL << ETH_MACVIR_VLTI_Pos) /*!< 0x00100000 */
7095 #define ETH_MACVIR_VLTI ETH_MACVIR_VLTI_Msk /* VLAN Tag Input */
7096 #define ETH_MACVIR_CSVL_Pos (19U)
7097 #define ETH_MACVIR_CSVL_Msk (0x1UL << ETH_MACVIR_CSVL_Pos) /*!< 0x00080000 */
7098 #define ETH_MACVIR_CSVL ETH_MACVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7099 #define ETH_MACVIR_VLP_Pos (18U)
7100 #define ETH_MACVIR_VLP_Msk (0x1UL << ETH_MACVIR_VLP_Pos) /*!< 0x00040000 */
7101 #define ETH_MACVIR_VLP ETH_MACVIR_VLP_Msk /* VLAN Priority Control */
7102 #define ETH_MACVIR_VLC_Pos (16U)
7103 #define ETH_MACVIR_VLC_Msk (0x3UL << ETH_MACVIR_VLC_Pos) /*!< 0x00030000 */
7104 #define ETH_MACVIR_VLC ETH_MACVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7105 #define ETH_MACVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7106 #define ETH_MACVIR_VLC_VLANTAGDELETE_Pos (16U)
7107 #define ETH_MACVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
7108 #define ETH_MACVIR_VLC_VLANTAGDELETE ETH_MACVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7109 #define ETH_MACVIR_VLC_VLANTAGINSERT_Pos (17U)
7110 #define ETH_MACVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
7111 #define ETH_MACVIR_VLC_VLANTAGINSERT ETH_MACVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7112 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Pos (16U)
7113 #define ETH_MACVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
7114 #define ETH_MACVIR_VLC_VLANTAGREPLACE ETH_MACVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7115 #define ETH_MACVIR_VLT_Pos (0U)
7116 #define ETH_MACVIR_VLT_Msk (0xFFFFUL << ETH_MACVIR_VLT_Pos) /*!< 0x0000FFFF */
7117 #define ETH_MACVIR_VLT ETH_MACVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7118 #define ETH_MACVIR_VLT_UP_Pos (13U)
7119 #define ETH_MACVIR_VLT_UP_Msk (0x7UL << ETH_MACVIR_VLT_UP_Pos) /*!< 0x0000E000 */
7120 #define ETH_MACVIR_VLT_UP ETH_MACVIR_VLT_UP_Msk /* User Priority */
7121 #define ETH_MACVIR_VLT_CFIDEI_Pos (12U)
7122 #define ETH_MACVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
7123 #define ETH_MACVIR_VLT_CFIDEI ETH_MACVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7124 #define ETH_MACVIR_VLT_VID_Pos (0U)
7125 #define ETH_MACVIR_VLT_VID_Msk (0xFFFUL << ETH_MACVIR_VLT_VID_Pos) /*!< 0x00000FFF */
7126 #define ETH_MACVIR_VLT_VID ETH_MACVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7127
7128 /* Bit definition for Ethernet MAC Inner_VLAN Incl Register */
7129 #define ETH_MACIVIR_VLTI_Pos (20U)
7130 #define ETH_MACIVIR_VLTI_Msk (0x1UL << ETH_MACIVIR_VLTI_Pos) /*!< 0x00100000 */
7131 #define ETH_MACIVIR_VLTI ETH_MACIVIR_VLTI_Msk /* VLAN Tag Input */
7132 #define ETH_MACIVIR_CSVL_Pos (19U)
7133 #define ETH_MACIVIR_CSVL_Msk (0x1UL << ETH_MACIVIR_CSVL_Pos) /*!< 0x00080000 */
7134 #define ETH_MACIVIR_CSVL ETH_MACIVIR_CSVL_Msk /* C-VLAN or S-VLAN */
7135 #define ETH_MACIVIR_VLP_Pos (18U)
7136 #define ETH_MACIVIR_VLP_Msk (0x1UL << ETH_MACIVIR_VLP_Pos) /*!< 0x00040000 */
7137 #define ETH_MACIVIR_VLP ETH_MACIVIR_VLP_Msk /* VLAN Priority Control */
7138 #define ETH_MACIVIR_VLC_Pos (16U)
7139 #define ETH_MACIVIR_VLC_Msk (0x3UL << ETH_MACIVIR_VLC_Pos) /*!< 0x00030000 */
7140 #define ETH_MACIVIR_VLC ETH_MACIVIR_VLC_Msk /* VLAN Tag Control in Transmit Packets */
7141 #define ETH_MACIVIR_VLC_NOVLANTAG ((uint32_t)0x00000000) /* No VLAN tag deletion, insertion, or replacement */
7142 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Pos (16U)
7143 #define ETH_MACIVIR_VLC_VLANTAGDELETE_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGDELETE_Pos) /*!< 0x00010000 */
7144 #define ETH_MACIVIR_VLC_VLANTAGDELETE ETH_MACIVIR_VLC_VLANTAGDELETE_Msk /* VLAN tag deletion */
7145 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Pos (17U)
7146 #define ETH_MACIVIR_VLC_VLANTAGINSERT_Msk (0x1UL << ETH_MACIVIR_VLC_VLANTAGINSERT_Pos) /*!< 0x00020000 */
7147 #define ETH_MACIVIR_VLC_VLANTAGINSERT ETH_MACIVIR_VLC_VLANTAGINSERT_Msk /* VLAN tag insertion */
7148 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos (16U)
7149 #define ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk (0x3UL << ETH_MACIVIR_VLC_VLANTAGREPLACE_Pos) /*!< 0x00030000 */
7150 #define ETH_MACIVIR_VLC_VLANTAGREPLACE ETH_MACIVIR_VLC_VLANTAGREPLACE_Msk /* VLAN tag replacement */
7151 #define ETH_MACIVIR_VLT_Pos (0U)
7152 #define ETH_MACIVIR_VLT_Msk (0xFFFFUL << ETH_MACIVIR_VLT_Pos) /*!< 0x0000FFFF */
7153 #define ETH_MACIVIR_VLT ETH_MACIVIR_VLT_Msk /* VLAN Tag for Transmit Packets */
7154 #define ETH_MACIVIR_VLT_UP_Pos (13U)
7155 #define ETH_MACIVIR_VLT_UP_Msk (0x7UL << ETH_MACIVIR_VLT_UP_Pos) /*!< 0x0000E000 */
7156 #define ETH_MACIVIR_VLT_UP ETH_MACIVIR_VLT_UP_Msk /* User Priority */
7157 #define ETH_MACIVIR_VLT_CFIDEI_Pos (12U)
7158 #define ETH_MACIVIR_VLT_CFIDEI_Msk (0x1UL << ETH_MACIVIR_VLT_CFIDEI_Pos) /*!< 0x00001000 */
7159 #define ETH_MACIVIR_VLT_CFIDEI ETH_MACIVIR_VLT_CFIDEI_Msk /* Canonical Format Indicator or Drop Eligible Indicator */
7160 #define ETH_MACIVIR_VLT_VID_Pos (0U)
7161 #define ETH_MACIVIR_VLT_VID_Msk (0xFFFUL << ETH_MACIVIR_VLT_VID_Pos) /*!< 0x00000FFF */
7162 #define ETH_MACIVIR_VLT_VID ETH_MACIVIR_VLT_VID_Msk /* VLAN Identifier field of VLAN tag */
7163
7164 /* Bit definition for Ethernet MAC Tx Flow Ctrl Register */
7165 #define ETH_MACTFCR_PT_Pos (16U)
7166 #define ETH_MACTFCR_PT_Msk (0xFFFFUL << ETH_MACTFCR_PT_Pos) /*!< 0xFFFF0000 */
7167 #define ETH_MACTFCR_PT ETH_MACTFCR_PT_Msk /* Pause Time */
7168 #define ETH_MACTFCR_DZPQ_Pos (7U)
7169 #define ETH_MACTFCR_DZPQ_Msk (0x1UL << ETH_MACTFCR_DZPQ_Pos) /*!< 0x00000080 */
7170 #define ETH_MACTFCR_DZPQ ETH_MACTFCR_DZPQ_Msk /* Disable Zero-Quanta Pause */
7171 #define ETH_MACTFCR_PLT_Pos (4U)
7172 #define ETH_MACTFCR_PLT_Msk (0x7UL << ETH_MACTFCR_PLT_Pos) /*!< 0x00000070 */
7173 #define ETH_MACTFCR_PLT ETH_MACTFCR_PLT_Msk /* Pause Low Threshold */
7174 #define ETH_MACTFCR_PLT_MINUS4 ((uint32_t)0x00000000) /* Pause time minus 4 slot times */
7175 #define ETH_MACTFCR_PLT_MINUS28_Pos (4U)
7176 #define ETH_MACTFCR_PLT_MINUS28_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS28_Pos) /*!< 0x00000010 */
7177 #define ETH_MACTFCR_PLT_MINUS28 ETH_MACTFCR_PLT_MINUS28_Msk /* Pause time minus 28 slot times */
7178 #define ETH_MACTFCR_PLT_MINUS36_Pos (5U)
7179 #define ETH_MACTFCR_PLT_MINUS36_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS36_Pos) /*!< 0x00000020 */
7180 #define ETH_MACTFCR_PLT_MINUS36 ETH_MACTFCR_PLT_MINUS36_Msk /* Pause time minus 36 slot times */
7181 #define ETH_MACTFCR_PLT_MINUS144_Pos (4U)
7182 #define ETH_MACTFCR_PLT_MINUS144_Msk (0x3UL << ETH_MACTFCR_PLT_MINUS144_Pos) /*!< 0x00000030 */
7183 #define ETH_MACTFCR_PLT_MINUS144 ETH_MACTFCR_PLT_MINUS144_Msk /* Pause time minus 144 slot times */
7184 #define ETH_MACTFCR_PLT_MINUS256_Pos (6U)
7185 #define ETH_MACTFCR_PLT_MINUS256_Msk (0x1UL << ETH_MACTFCR_PLT_MINUS256_Pos) /*!< 0x00000040 */
7186 #define ETH_MACTFCR_PLT_MINUS256 ETH_MACTFCR_PLT_MINUS256_Msk /* Pause time minus 256 slot times */
7187 #define ETH_MACTFCR_PLT_MINUS512_Pos (4U)
7188 #define ETH_MACTFCR_PLT_MINUS512_Msk (0x5UL << ETH_MACTFCR_PLT_MINUS512_Pos) /*!< 0x00000050 */
7189 #define ETH_MACTFCR_PLT_MINUS512 ETH_MACTFCR_PLT_MINUS512_Msk /* Pause time minus 512 slot times */
7190 #define ETH_MACTFCR_TFE_Pos (1U)
7191 #define ETH_MACTFCR_TFE_Msk (0x1UL << ETH_MACTFCR_TFE_Pos) /*!< 0x00000002 */
7192 #define ETH_MACTFCR_TFE ETH_MACTFCR_TFE_Msk /* Transmit Flow Control Enable */
7193 #define ETH_MACTFCR_FCB_Pos (0U)
7194 #define ETH_MACTFCR_FCB_Msk (0x1UL << ETH_MACTFCR_FCB_Pos) /*!< 0x00000001 */
7195 #define ETH_MACTFCR_FCB ETH_MACTFCR_FCB_Msk /* Flow Control Busy or Backpressure Activate */
7196
7197 /* Bit definition for Ethernet MAC Rx Flow Ctrl Register */
7198 #define ETH_MACRFCR_UP_Pos (1U)
7199 #define ETH_MACRFCR_UP_Msk (0x1UL << ETH_MACRFCR_UP_Pos) /*!< 0x00000002 */
7200 #define ETH_MACRFCR_UP ETH_MACRFCR_UP_Msk /* Unicast Pause Packet Detect */
7201 #define ETH_MACRFCR_RFE_Pos (0U)
7202 #define ETH_MACRFCR_RFE_Msk (0x1UL << ETH_MACRFCR_RFE_Pos) /*!< 0x00000001 */
7203 #define ETH_MACRFCR_RFE ETH_MACRFCR_RFE_Msk /* Receive Flow Control Enable */
7204
7205 /* Bit definition for Ethernet MAC Interrupt Status Register */
7206 #define ETH_MACISR_RXSTSIS_Pos (14U)
7207 #define ETH_MACISR_RXSTSIS_Msk (0x1UL << ETH_MACISR_RXSTSIS_Pos) /*!< 0x00004000 */
7208 #define ETH_MACISR_RXSTSIS ETH_MACISR_RXSTSIS_Msk /* Receive Status Interrupt */
7209 #define ETH_MACISR_TXSTSIS_Pos (13U)
7210 #define ETH_MACISR_TXSTSIS_Msk (0x1UL << ETH_MACISR_TXSTSIS_Pos) /*!< 0x00002000 */
7211 #define ETH_MACISR_TXSTSIS ETH_MACISR_TXSTSIS_Msk /* Transmit Status Interrupt */
7212 #define ETH_MACISR_TSIS_Pos (12U)
7213 #define ETH_MACISR_TSIS_Msk (0x1UL << ETH_MACISR_TSIS_Pos) /*!< 0x00001000 */
7214 #define ETH_MACISR_TSIS ETH_MACISR_TSIS_Msk /* Timestamp Interrupt Status */
7215 #define ETH_MACISR_MMCTXIS_Pos (10U)
7216 #define ETH_MACISR_MMCTXIS_Msk (0x1UL << ETH_MACISR_MMCTXIS_Pos) /*!< 0x00000400 */
7217 #define ETH_MACISR_MMCTXIS ETH_MACISR_MMCTXIS_Msk /* MMC Transmit Interrupt Status */
7218 #define ETH_MACISR_MMCRXIS_Pos (9U)
7219 #define ETH_MACISR_MMCRXIS_Msk (0x1UL << ETH_MACISR_MMCRXIS_Pos) /*!< 0x00000200 */
7220 #define ETH_MACISR_MMCRXIS ETH_MACISR_MMCRXIS_Msk /* MMC Receive Interrupt Status */
7221 #define ETH_MACISR_MMCIS_Pos (8U)
7222 #define ETH_MACISR_MMCIS_Msk (0x1UL << ETH_MACISR_MMCIS_Pos) /*!< 0x00000100 */
7223 #define ETH_MACISR_MMCIS ETH_MACISR_MMCIS_Msk /* MMC Interrupt Status */
7224 #define ETH_MACISR_LPIIS_Pos (5U)
7225 #define ETH_MACISR_LPIIS_Msk (0x1UL << ETH_MACISR_LPIIS_Pos) /*!< 0x00000020 */
7226 #define ETH_MACISR_LPIIS ETH_MACISR_LPIIS_Msk /* LPI Interrupt Status */
7227 #define ETH_MACISR_PMTIS_Pos (4U)
7228 #define ETH_MACISR_PMTIS_Msk (0x1UL << ETH_MACISR_PMTIS_Pos) /*!< 0x00000010 */
7229 #define ETH_MACISR_PMTIS ETH_MACISR_PMTIS_Msk /* PMT Interrupt Status */
7230 #define ETH_MACISR_PHYIS_Pos (3U)
7231 #define ETH_MACISR_PHYIS_Msk (0x1UL << ETH_MACISR_PHYIS_Pos) /*!< 0x00000008 */
7232 #define ETH_MACISR_PHYIS ETH_MACISR_PHYIS_Msk /* PHY Interrupt */
7233
7234 /* Bit definition for Ethernet MAC Interrupt Enable Register */
7235 #define ETH_MACIER_RXSTSIE_Pos (14U)
7236 #define ETH_MACIER_RXSTSIE_Msk (0x1UL << ETH_MACIER_RXSTSIE_Pos) /*!< 0x00004000 */
7237 #define ETH_MACIER_RXSTSIE ETH_MACIER_RXSTSIE_Msk /* Receive Status Interrupt Enable */
7238 #define ETH_MACIER_TXSTSIE_Pos (13U)
7239 #define ETH_MACIER_TXSTSIE_Msk (0x1UL << ETH_MACIER_TXSTSIE_Pos) /*!< 0x00002000 */
7240 #define ETH_MACIER_TXSTSIE ETH_MACIER_TXSTSIE_Msk /* Transmit Status Interrupt Enable */
7241 #define ETH_MACIER_TSIE_Pos (12U)
7242 #define ETH_MACIER_TSIE_Msk (0x1UL << ETH_MACIER_TSIE_Pos) /*!< 0x00001000 */
7243 #define ETH_MACIER_TSIE ETH_MACIER_TSIE_Msk /* Timestamp Interrupt Enable */
7244 #define ETH_MACIER_LPIIE_Pos (5U)
7245 #define ETH_MACIER_LPIIE_Msk (0x1UL << ETH_MACIER_LPIIE_Pos) /*!< 0x00000020 */
7246 #define ETH_MACIER_LPIIE ETH_MACIER_LPIIE_Msk /* LPI Interrupt Enable */
7247 #define ETH_MACIER_PMTIE_Pos (4U)
7248 #define ETH_MACIER_PMTIE_Msk (0x1UL << ETH_MACIER_PMTIE_Pos) /*!< 0x00000010 */
7249 #define ETH_MACIER_PMTIE ETH_MACIER_PMTIE_Msk /* PMT Interrupt Enable */
7250 #define ETH_MACIER_PHYIE_Pos (3U)
7251 #define ETH_MACIER_PHYIE_Msk (0x1UL << ETH_MACIER_PHYIE_Pos) /*!< 0x00000008 */
7252 #define ETH_MACIER_PHYIE ETH_MACIER_PHYIE_Msk /* PHY Interrupt Enable */
7253
7254 /* Bit definition for Ethernet MAC Rx Tx Status Register */
7255 #define ETH_MACRXTXSR_RWT_Pos (8U)
7256 #define ETH_MACRXTXSR_RWT_Msk (0x1UL << ETH_MACRXTXSR_RWT_Pos) /*!< 0x00000100 */
7257 #define ETH_MACRXTXSR_RWT ETH_MACRXTXSR_RWT_Msk /* Receive Watchdog Timeout */
7258 #define ETH_MACRXTXSR_EXCOL_Pos (5U)
7259 #define ETH_MACRXTXSR_EXCOL_Msk (0x1UL << ETH_MACRXTXSR_EXCOL_Pos) /*!< 0x00000020 */
7260 #define ETH_MACRXTXSR_EXCOL ETH_MACRXTXSR_EXCOL_Msk /* Excessive Collisions */
7261 #define ETH_MACRXTXSR_LCOL_Pos (4U)
7262 #define ETH_MACRXTXSR_LCOL_Msk (0x1UL << ETH_MACRXTXSR_LCOL_Pos) /*!< 0x00000010 */
7263 #define ETH_MACRXTXSR_LCOL ETH_MACRXTXSR_LCOL_Msk /* Late Collision */
7264 #define ETH_MACRXTXSR_EXDEF_Pos (3U)
7265 #define ETH_MACRXTXSR_EXDEF_Msk (0x1UL << ETH_MACRXTXSR_EXDEF_Pos) /*!< 0x00000008 */
7266 #define ETH_MACRXTXSR_EXDEF ETH_MACRXTXSR_EXDEF_Msk /* Excessive Deferral */
7267 #define ETH_MACRXTXSR_LCARR_Pos (2U)
7268 #define ETH_MACRXTXSR_LCARR_Msk (0x1UL << ETH_MACRXTXSR_LCARR_Pos) /*!< 0x00000004 */
7269 #define ETH_MACRXTXSR_LCARR ETH_MACRXTXSR_LCARR_Msk /* Loss of Carrier */
7270 #define ETH_MACRXTXSR_NCARR_Pos (1U)
7271 #define ETH_MACRXTXSR_NCARR_Msk (0x1UL << ETH_MACRXTXSR_NCARR_Pos) /*!< 0x00000002 */
7272 #define ETH_MACRXTXSR_NCARR ETH_MACRXTXSR_NCARR_Msk /* No Carrier */
7273 #define ETH_MACRXTXSR_TJT_Pos (0U)
7274 #define ETH_MACRXTXSR_TJT_Msk (0x1UL << ETH_MACRXTXSR_TJT_Pos) /*!< 0x00000001 */
7275 #define ETH_MACRXTXSR_TJT ETH_MACRXTXSR_TJT_Msk /* Transmit Jabber Timeout */
7276
7277 /* Bit definition for Ethernet MAC PMT Control Status Register */
7278 #define ETH_MACPCSR_RWKFILTRST_Pos (31U)
7279 #define ETH_MACPCSR_RWKFILTRST_Msk (0x1UL << ETH_MACPCSR_RWKFILTRST_Pos) /*!< 0x80000000 */
7280 #define ETH_MACPCSR_RWKFILTRST ETH_MACPCSR_RWKFILTRST_Msk /* Remote Wake-Up Packet Filter Register Pointer Reset */
7281 #define ETH_MACPCSR_RWKPTR_Pos (24U)
7282 #define ETH_MACPCSR_RWKPTR_Msk (0x1FUL << ETH_MACPCSR_RWKPTR_Pos) /*!< 0x1F000000 */
7283 #define ETH_MACPCSR_RWKPTR ETH_MACPCSR_RWKPTR_Msk /* Remote Wake-up FIFO Pointer */
7284 #define ETH_MACPCSR_RWKPFE_Pos (10U)
7285 #define ETH_MACPCSR_RWKPFE_Msk (0x1UL << ETH_MACPCSR_RWKPFE_Pos) /*!< 0x00000400 */
7286 #define ETH_MACPCSR_RWKPFE ETH_MACPCSR_RWKPFE_Msk /* Remote Wake-up Packet Forwarding Enable */
7287 #define ETH_MACPCSR_GLBLUCAST_Pos (9U)
7288 #define ETH_MACPCSR_GLBLUCAST_Msk (0x1UL << ETH_MACPCSR_GLBLUCAST_Pos) /*!< 0x00000200 */
7289 #define ETH_MACPCSR_GLBLUCAST ETH_MACPCSR_GLBLUCAST_Msk /* Global Unicast */
7290 #define ETH_MACPCSR_RWKPRCVD_Pos (6U)
7291 #define ETH_MACPCSR_RWKPRCVD_Msk (0x1UL << ETH_MACPCSR_RWKPRCVD_Pos) /*!< 0x00000040 */
7292 #define ETH_MACPCSR_RWKPRCVD ETH_MACPCSR_RWKPRCVD_Msk /* Remote Wake-Up Packet Received */
7293 #define ETH_MACPCSR_MGKPRCVD_Pos (5U)
7294 #define ETH_MACPCSR_MGKPRCVD_Msk (0x1UL << ETH_MACPCSR_MGKPRCVD_Pos) /*!< 0x00000020 */
7295 #define ETH_MACPCSR_MGKPRCVD ETH_MACPCSR_MGKPRCVD_Msk /* Magic Packet Received */
7296 #define ETH_MACPCSR_RWKPKTEN_Pos (2U)
7297 #define ETH_MACPCSR_RWKPKTEN_Msk (0x1UL << ETH_MACPCSR_RWKPKTEN_Pos) /*!< 0x00000004 */
7298 #define ETH_MACPCSR_RWKPKTEN ETH_MACPCSR_RWKPKTEN_Msk /* Remote Wake-Up Packet Enable */
7299 #define ETH_MACPCSR_MGKPKTEN_Pos (1U)
7300 #define ETH_MACPCSR_MGKPKTEN_Msk (0x1UL << ETH_MACPCSR_MGKPKTEN_Pos) /*!< 0x00000002 */
7301 #define ETH_MACPCSR_MGKPKTEN ETH_MACPCSR_MGKPKTEN_Msk /* Magic Packet Enable */
7302 #define ETH_MACPCSR_PWRDWN_Pos (0U)
7303 #define ETH_MACPCSR_PWRDWN_Msk (0x1UL << ETH_MACPCSR_PWRDWN_Pos) /*!< 0x00000001 */
7304 #define ETH_MACPCSR_PWRDWN ETH_MACPCSR_PWRDWN_Msk /* Power Down */
7305
7306 /* Bit definition for Ethernet MAC Remote Wake-Up Packet Filter Register */
7307 #define ETH_MACRWUPFR_D_Pos (0U)
7308 #define ETH_MACRWUPFR_D_Msk (0xFFFFFFFFUL << ETH_MACRWUPFR_D_Pos) /*!< 0xFFFFFFFF */
7309 #define ETH_MACRWUPFR_D ETH_MACRWUPFR_D_Msk /* Wake-up Packet filter register data */
7310
7311 /* Bit definition for Ethernet MAC LPI Control Status Register */
7312 #define ETH_MACLCSR_LPITCSE_Pos (21U)
7313 #define ETH_MACLCSR_LPITCSE_Msk (0x1UL << ETH_MACLCSR_LPITCSE_Pos) /*!< 0x00200000 */
7314 #define ETH_MACLCSR_LPITCSE ETH_MACLCSR_LPITCSE_Msk /* LPI Tx Clock Stop Enable */
7315 #define ETH_MACLCSR_LPITE_Pos (20U)
7316 #define ETH_MACLCSR_LPITE_Msk (0x1UL << ETH_MACLCSR_LPITE_Pos) /*!< 0x00100000 */
7317 #define ETH_MACLCSR_LPITE ETH_MACLCSR_LPITE_Msk /* LPI Timer Enable */
7318 #define ETH_MACLCSR_LPITXA_Pos (19U)
7319 #define ETH_MACLCSR_LPITXA_Msk (0x1UL << ETH_MACLCSR_LPITXA_Pos) /*!< 0x00080000 */
7320 #define ETH_MACLCSR_LPITXA ETH_MACLCSR_LPITXA_Msk /* LPI Tx Automate */
7321 #define ETH_MACLCSR_PLS_Pos (17U)
7322 #define ETH_MACLCSR_PLS_Msk (0x1UL << ETH_MACLCSR_PLS_Pos) /*!< 0x00020000 */
7323 #define ETH_MACLCSR_PLS ETH_MACLCSR_PLS_Msk /* PHY Link Status */
7324 #define ETH_MACLCSR_LPIEN_Pos (16U)
7325 #define ETH_MACLCSR_LPIEN_Msk (0x1UL << ETH_MACLCSR_LPIEN_Pos) /*!< 0x00010000 */
7326 #define ETH_MACLCSR_LPIEN ETH_MACLCSR_LPIEN_Msk /* LPI Enable */
7327 #define ETH_MACLCSR_RLPIST_Pos (9U)
7328 #define ETH_MACLCSR_RLPIST_Msk (0x1UL << ETH_MACLCSR_RLPIST_Pos) /*!< 0x00000200 */
7329 #define ETH_MACLCSR_RLPIST ETH_MACLCSR_RLPIST_Msk /* Receive LPI State */
7330 #define ETH_MACLCSR_TLPIST_Pos (8U)
7331 #define ETH_MACLCSR_TLPIST_Msk (0x1UL << ETH_MACLCSR_TLPIST_Pos) /*!< 0x00000100 */
7332 #define ETH_MACLCSR_TLPIST ETH_MACLCSR_TLPIST_Msk /* Transmit LPI State */
7333 #define ETH_MACLCSR_RLPIEX_Pos (3U)
7334 #define ETH_MACLCSR_RLPIEX_Msk (0x1UL << ETH_MACLCSR_RLPIEX_Pos) /*!< 0x00000008 */
7335 #define ETH_MACLCSR_RLPIEX ETH_MACLCSR_RLPIEX_Msk /* Receive LPI Exit */
7336 #define ETH_MACLCSR_RLPIEN_Pos (2U)
7337 #define ETH_MACLCSR_RLPIEN_Msk (0x1UL << ETH_MACLCSR_RLPIEN_Pos) /*!< 0x00000004 */
7338 #define ETH_MACLCSR_RLPIEN ETH_MACLCSR_RLPIEN_Msk /* Receive LPI Entry */
7339 #define ETH_MACLCSR_TLPIEX_Pos (1U)
7340 #define ETH_MACLCSR_TLPIEX_Msk (0x1UL << ETH_MACLCSR_TLPIEX_Pos) /*!< 0x00000002 */
7341 #define ETH_MACLCSR_TLPIEX ETH_MACLCSR_TLPIEX_Msk /* Transmit LPI Exit */
7342 #define ETH_MACLCSR_TLPIEN_Pos (0U)
7343 #define ETH_MACLCSR_TLPIEN_Msk (0x1UL << ETH_MACLCSR_TLPIEN_Pos) /*!< 0x00000001 */
7344 #define ETH_MACLCSR_TLPIEN ETH_MACLCSR_TLPIEN_Msk /* Transmit LPI Entry */
7345
7346 /* Bit definition for Ethernet MAC LPI Timers Control Register */
7347 #define ETH_MACLTCR_LST_Pos (16U)
7348 #define ETH_MACLTCR_LST_Msk (0x3FFUL << ETH_MACLTCR_LST_Pos) /*!< 0x03FF0000 */
7349 #define ETH_MACLTCR_LST ETH_MACLTCR_LST_Msk /* LPI LS TIMER */
7350 #define ETH_MACLTCR_TWT_Pos (0U)
7351 #define ETH_MACLTCR_TWT_Msk (0xFFFFUL << ETH_MACLTCR_TWT_Pos) /*!< 0x0000FFFF */
7352 #define ETH_MACLTCR_TWT ETH_MACLTCR_TWT_Msk /* LPI TW TIMER */
7353
7354 /* Bit definition for Ethernet MAC LPI Entry Timer Register */
7355 #define ETH_MACLETR_LPIET_Pos (0U)
7356 #define ETH_MACLETR_LPIET_Msk (0xFFFFFUL << ETH_MACLETR_LPIET_Pos) /*!< 0x000FFFFF */
7357 #define ETH_MACLETR_LPIET ETH_MACLETR_LPIET_Msk /* LPI Entry Timer */
7358
7359 /* Bit definition for Ethernet MAC 1US Tic Counter Register */
7360 #define ETH_MAC1USTCR_TIC1USCNTR_Pos (0U)
7361 #define ETH_MAC1USTCR_TIC1USCNTR_Msk (0xFFFUL << ETH_MAC1USTCR_TIC1USCNTR_Pos) /*!< 0x00000FFF */
7362 #define ETH_MAC1USTCR_TIC1USCNTR ETH_MAC1USTCR_TIC1USCNTR_Msk /* 1US TIC Counter */
7363
7364 /* Bit definition for Ethernet MAC Version Register */
7365 #define ETH_MACVR_USERVER_Pos (8U)
7366 #define ETH_MACVR_USERVER_Msk (0xFFUL << ETH_MACVR_USERVER_Pos) /*!< 0x0000FF00 */
7367 #define ETH_MACVR_USERVER ETH_MACVR_USERVER_Msk /* User-defined Version */
7368 #define ETH_MACVR_SNPSVER_Pos (0U)
7369 #define ETH_MACVR_SNPSVER_Msk (0xFFUL << ETH_MACVR_SNPSVER_Pos) /*!< 0x000000FF */
7370 #define ETH_MACVR_SNPSVER ETH_MACVR_SNPSVER_Msk /* Synopsys-defined Version */
7371
7372 /* Bit definition for Ethernet MAC Debug Register */
7373 #define ETH_MACDR_TFCSTS_Pos (17U)
7374 #define ETH_MACDR_TFCSTS_Msk (0x3UL << ETH_MACDR_TFCSTS_Pos) /*!< 0x00060000 */
7375 #define ETH_MACDR_TFCSTS ETH_MACDR_TFCSTS_Msk /* MAC Transmit Packet Controller Status */
7376 #define ETH_MACDR_TFCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
7377 #define ETH_MACDR_TFCSTS_WAIT_Pos (17U)
7378 #define ETH_MACDR_TFCSTS_WAIT_Msk (0x1UL << ETH_MACDR_TFCSTS_WAIT_Pos) /*!< 0x00020000 */
7379 #define ETH_MACDR_TFCSTS_WAIT ETH_MACDR_TFCSTS_WAIT_Msk /* Waiting for status of the previous packet, IPG or backoff period to be over */
7380 #define ETH_MACDR_TFCSTS_GENERATEPCP_Pos (18U)
7381 #define ETH_MACDR_TFCSTS_GENERATEPCP_Msk (0x1UL << ETH_MACDR_TFCSTS_GENERATEPCP_Pos) /*!< 0x00040000 */
7382 #define ETH_MACDR_TFCSTS_GENERATEPCP ETH_MACDR_TFCSTS_GENERATEPCP_Msk /* Generating and transmitting a Pause control packet */
7383 #define ETH_MACDR_TFCSTS_TRASFERIP_Pos (17U)
7384 #define ETH_MACDR_TFCSTS_TRASFERIP_Msk (0x3UL << ETH_MACDR_TFCSTS_TRASFERIP_Pos) /*!< 0x00060000 */
7385 #define ETH_MACDR_TFCSTS_TRASFERIP ETH_MACDR_TFCSTS_TRASFERIP_Msk /* Transferring input packet for transmission */
7386 #define ETH_MACDR_TPESTS_Pos (16U)
7387 #define ETH_MACDR_TPESTS_Msk (0x1UL << ETH_MACDR_TPESTS_Pos) /*!< 0x00010000 */
7388 #define ETH_MACDR_TPESTS ETH_MACDR_TPESTS_Msk /* MAC Receive Packet Controller FIFO Status */
7389 #define ETH_MACDR_RFCFCSTS_Pos (1U)
7390 #define ETH_MACDR_RFCFCSTS_Msk (0x3UL << ETH_MACDR_RFCFCSTS_Pos) /*!< 0x00000006 */
7391 #define ETH_MACDR_RFCFCSTS ETH_MACDR_RFCFCSTS_Msk /* MAC MII Transmit Protocol Engine Status */
7392 #define ETH_MACDR_RPESTS_Pos (0U)
7393 #define ETH_MACDR_RPESTS_Msk (0x1UL << ETH_MACDR_RPESTS_Pos) /*!< 0x00000001 */
7394 #define ETH_MACDR_RPESTS ETH_MACDR_RPESTS_Msk /* MAC MII Receive Protocol Engine Status */
7395
7396 /* Bit definition for Ethernet MAC HW Feature0 Register */
7397 #define ETH_MACHWF0R_ACTPHYSEL_Pos (28U)
7398 #define ETH_MACHWF0R_ACTPHYSEL_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_Pos) /*!< 0x70000000 */
7399 #define ETH_MACHWF0R_ACTPHYSEL ETH_MACHWF0R_ACTPHYSEL_Msk /* Active PHY Selected */
7400 #define ETH_MACHWF0R_ACTPHYSEL_MII ((uint32_t)0x00000000) /* MII */
7401 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Pos (30U)
7402 #define ETH_MACHWF0R_ACTPHYSEL_RMII_Msk (0x1UL << ETH_MACHWF0R_ACTPHYSEL_RMII_Pos) /*!< 0x40000000 */
7403 #define ETH_MACHWF0R_ACTPHYSEL_RMII ETH_MACHWF0R_ACTPHYSEL_RMII_Msk /* RMII */
7404 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos (28U)
7405 #define ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk (0x7UL << ETH_MACHWF0R_ACTPHYSEL_REVMII_Pos) /*!< 0x70000000 */
7406 #define ETH_MACHWF0R_ACTPHYSEL_REVMII ETH_MACHWF0R_ACTPHYSEL_REVMII_Msk /* RevMII */
7407 #define ETH_MACHWF0R_SAVLANINS_Pos (27U)
7408 #define ETH_MACHWF0R_SAVLANINS_Msk (0x1UL << ETH_MACHWF0R_SAVLANINS_Pos) /*!< 0x08000000 */
7409 #define ETH_MACHWF0R_SAVLANINS ETH_MACHWF0R_SAVLANINS_Msk /* Source Address or VLAN Insertion Enable */
7410 #define ETH_MACHWF0R_TSSTSSEL_Pos (25U)
7411 #define ETH_MACHWF0R_TSSTSSEL_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_Pos) /*!< 0x06000000 */
7412 #define ETH_MACHWF0R_TSSTSSEL ETH_MACHWF0R_TSSTSSEL_Msk /* Timestamp System Time Source */
7413 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos (25U)
7414 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_INTERNAL_Pos) /*!< 0x02000000 */
7415 #define ETH_MACHWF0R_TSSTSSEL_INTERNAL ETH_MACHWF0R_TSSTSSEL_INTERNAL_Msk /* Timestamp System Time Source: Internal */
7416 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos (26U)
7417 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk (0x1UL << ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Pos) /*!< 0x04000000 */
7418 #define ETH_MACHWF0R_TSSTSSEL_EXTERNAL ETH_MACHWF0R_TSSTSSEL_EXTERNAL_Msk /* Timestamp System Time Source: External */
7419 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Pos (25U)
7420 #define ETH_MACHWF0R_TSSTSSEL_BOTH_Msk (0x3UL << ETH_MACHWF0R_TSSTSSEL_BOTH_Pos) /*!< 0x06000000 */
7421 #define ETH_MACHWF0R_TSSTSSEL_BOTH ETH_MACHWF0R_TSSTSSEL_BOTH_Msk /* Timestamp System Time Source: Internal & External */
7422 #define ETH_MACHWF0R_MACADR64SEL_Pos (24U)
7423 #define ETH_MACHWF0R_MACADR64SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR64SEL_Pos) /*!< 0x01000000 */
7424 #define ETH_MACHWF0R_MACADR64SEL ETH_MACHWF0R_MACADR64SEL_Msk /* MAC Addresses 64-127 Selected */
7425 #define ETH_MACHWF0R_MACADR32SEL_Pos (23U)
7426 #define ETH_MACHWF0R_MACADR32SEL_Msk (0x1UL << ETH_MACHWF0R_MACADR32SEL_Pos) /*!< 0x00800000 */
7427 #define ETH_MACHWF0R_MACADR32SEL ETH_MACHWF0R_MACADR32SEL_Msk /* MAC Addresses 32-63 Selected */
7428 #define ETH_MACHWF0R_ADDMACADRSEL_Pos (18U)
7429 #define ETH_MACHWF0R_ADDMACADRSEL_Msk (0x1FUL << ETH_MACHWF0R_ADDMACADRSEL_Pos) /*!< 0x007C0000 */
7430 #define ETH_MACHWF0R_ADDMACADRSEL ETH_MACHWF0R_ADDMACADRSEL_Msk /* MAC Addresses 1- 31 Selected */
7431 #define ETH_MACHWF0R_RXCOESEL_Pos (16U)
7432 #define ETH_MACHWF0R_RXCOESEL_Msk (0x1UL << ETH_MACHWF0R_RXCOESEL_Pos) /*!< 0x00010000 */
7433 #define ETH_MACHWF0R_RXCOESEL ETH_MACHWF0R_RXCOESEL_Msk /* Receive Checksum Offload Enabled */
7434 #define ETH_MACHWF0R_TXCOESEL_Pos (14U)
7435 #define ETH_MACHWF0R_TXCOESEL_Msk (0x1UL << ETH_MACHWF0R_TXCOESEL_Pos) /*!< 0x00004000 */
7436 #define ETH_MACHWF0R_TXCOESEL ETH_MACHWF0R_TXCOESEL_Msk /* Transmit Checksum Offload Enabled */
7437 #define ETH_MACHWF0R_EEESEL_Pos (13U)
7438 #define ETH_MACHWF0R_EEESEL_Msk (0x1UL << ETH_MACHWF0R_EEESEL_Pos) /*!< 0x00002000 */
7439 #define ETH_MACHWF0R_EEESEL ETH_MACHWF0R_EEESEL_Msk /* Energy Efficient Ethernet Enabled */
7440 #define ETH_MACHWF0R_TSSEL_Pos (12U)
7441 #define ETH_MACHWF0R_TSSEL_Msk (0x1UL << ETH_MACHWF0R_TSSEL_Pos) /*!< 0x00001000 */
7442 #define ETH_MACHWF0R_TSSEL ETH_MACHWF0R_TSSEL_Msk /* IEEE 1588-2008 Timestamp Enabled */
7443 #define ETH_MACHWF0R_ARPOFFSEL_Pos (9U)
7444 #define ETH_MACHWF0R_ARPOFFSEL_Msk (0x1UL << ETH_MACHWF0R_ARPOFFSEL_Pos) /*!< 0x00000200 */
7445 #define ETH_MACHWF0R_ARPOFFSEL ETH_MACHWF0R_ARPOFFSEL_Msk /* ARP Offload Enabled */
7446 #define ETH_MACHWF0R_MMCSEL_Pos (8U)
7447 #define ETH_MACHWF0R_MMCSEL_Msk (0x1UL << ETH_MACHWF0R_MMCSEL_Pos) /*!< 0x00000100 */
7448 #define ETH_MACHWF0R_MMCSEL ETH_MACHWF0R_MMCSEL_Msk /* RMON Module Enable */
7449 #define ETH_MACHWF0R_MGKSEL_Pos (7U)
7450 #define ETH_MACHWF0R_MGKSEL_Msk (0x1UL << ETH_MACHWF0R_MGKSEL_Pos) /*!< 0x00000080 */
7451 #define ETH_MACHWF0R_MGKSEL ETH_MACHWF0R_MGKSEL_Msk /* PMT Magic Packet Enable */
7452 #define ETH_MACHWF0R_RWKSEL_Pos (6U)
7453 #define ETH_MACHWF0R_RWKSEL_Msk (0x1UL << ETH_MACHWF0R_RWKSEL_Pos) /*!< 0x00000040 */
7454 #define ETH_MACHWF0R_RWKSEL ETH_MACHWF0R_RWKSEL_Msk /* PMT Remote Wake-up Packet Enable */
7455 #define ETH_MACHWF0R_SMASEL_Pos (5U)
7456 #define ETH_MACHWF0R_SMASEL_Msk (0x1UL << ETH_MACHWF0R_SMASEL_Pos) /*!< 0x00000020 */
7457 #define ETH_MACHWF0R_SMASEL ETH_MACHWF0R_SMASEL_Msk /* SMA (MDIO) Interface */
7458 #define ETH_MACHWF0R_VLHASH_Pos (4U)
7459 #define ETH_MACHWF0R_VLHASH_Msk (0x1UL << ETH_MACHWF0R_VLHASH_Pos) /*!< 0x00000010 */
7460 #define ETH_MACHWF0R_VLHASH ETH_MACHWF0R_VLHASH_Msk /* VLAN Hash Filter Selected */
7461 #define ETH_MACHWF0R_PCSSEL_Pos (3U)
7462 #define ETH_MACHWF0R_PCSSEL_Msk (0x1UL << ETH_MACHWF0R_PCSSEL_Pos) /*!< 0x00000008 */
7463 #define ETH_MACHWF0R_PCSSEL ETH_MACHWF0R_PCSSEL_Msk /* PCS Registers (TBI, SGMII, or RTBI PHY interface) */
7464 #define ETH_MACHWF0R_HDSEL_Pos (2U)
7465 #define ETH_MACHWF0R_HDSEL_Msk (0x1UL << ETH_MACHWF0R_HDSEL_Pos) /*!< 0x00000004 */
7466 #define ETH_MACHWF0R_HDSEL ETH_MACHWF0R_HDSEL_Msk /* Half-duplex Support */
7467 #define ETH_MACHWF0R_GMIISEL_Pos (1U)
7468 #define ETH_MACHWF0R_GMIISEL_Msk (0x1UL << ETH_MACHWF0R_GMIISEL_Pos) /*!< 0x00000002 */
7469 #define ETH_MACHWF0R_GMIISEL ETH_MACHWF0R_GMIISEL_Msk /* 1000 Mbps Support */
7470 #define ETH_MACHWF0R_MIISEL_Pos (0U)
7471 #define ETH_MACHWF0R_MIISEL_Msk (0x1UL << ETH_MACHWF0R_MIISEL_Pos) /*!< 0x00000001 */
7472 #define ETH_MACHWF0R_MIISEL ETH_MACHWF0R_MIISEL_Msk /* 10 or 100 Mbps Support */
7473
7474 /* Bit definition for Ethernet MAC HW Feature1 Register */
7475 #define ETH_MACHWF1R_L3L4FNUM_Pos (27U)
7476 #define ETH_MACHWF1R_L3L4FNUM_Msk (0xFUL << ETH_MACHWF1R_L3L4FNUM_Pos) /*!< 0x78000000 */
7477 #define ETH_MACHWF1R_L3L4FNUM ETH_MACHWF1R_L3L4FNUM_Msk /* Total number of L3 or L4 Filters */
7478 #define ETH_MACHWF1R_HASHTBLSZ_Pos (24U)
7479 #define ETH_MACHWF1R_HASHTBLSZ_Msk (0x3UL << ETH_MACHWF1R_HASHTBLSZ_Pos) /*!< 0x03000000 */
7480 #define ETH_MACHWF1R_HASHTBLSZ ETH_MACHWF1R_HASHTBLSZ_Msk /* Hash Table Size */
7481 #define ETH_MACHWF1R_AVSEL_Pos (20U)
7482 #define ETH_MACHWF1R_AVSEL_Msk (0x1UL << ETH_MACHWF1R_AVSEL_Pos) /*!< 0x00100000 */
7483 #define ETH_MACHWF1R_AVSEL ETH_MACHWF1R_AVSEL_Msk /* AV Feature Enabled */
7484 #define ETH_MACHWF1R_DBGMEMA_Pos (19U)
7485 #define ETH_MACHWF1R_DBGMEMA_Msk (0x1UL << ETH_MACHWF1R_DBGMEMA_Pos) /*!< 0x00080000 */
7486 #define ETH_MACHWF1R_DBGMEMA ETH_MACHWF1R_DBGMEMA_Msk /* Debug Memory Interface Enabled */
7487 #define ETH_MACHWF1R_TSOEN_Pos (18U)
7488 #define ETH_MACHWF1R_TSOEN_Msk (0x1UL << ETH_MACHWF1R_TSOEN_Pos) /*!< 0x00040000 */
7489 #define ETH_MACHWF1R_TSOEN ETH_MACHWF1R_TSOEN_Msk /* TCP Segmentation Offload Enable */
7490 #define ETH_MACHWF1R_SPHEN_Pos (17U)
7491 #define ETH_MACHWF1R_SPHEN_Msk (0x1UL << ETH_MACHWF1R_SPHEN_Pos) /*!< 0x00020000 */
7492 #define ETH_MACHWF1R_SPHEN ETH_MACHWF1R_SPHEN_Msk /* Split Header Feature Enable */
7493 #define ETH_MACHWF1R_DCBEN_Pos (16U)
7494 #define ETH_MACHWF1R_DCBEN_Msk (0x1UL << ETH_MACHWF1R_DCBEN_Pos) /*!< 0x00010000 */
7495 #define ETH_MACHWF1R_DCBEN ETH_MACHWF1R_DCBEN_Msk /* DCB Feature Enable */
7496 #define ETH_MACHWF1R_ADDR64_Pos (14U)
7497 #define ETH_MACHWF1R_ADDR64_Msk (0x3UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x0000C000 */
7498 #define ETH_MACHWF1R_ADDR64 ETH_MACHWF1R_ADDR64_Msk /* Address Width */
7499 #define ETH_MACHWF1R_ADDR64_32 (0x0UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00000000 */
7500 #define ETH_MACHWF1R_ADDR64_40 (0x1UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00004000 */
7501 #define ETH_MACHWF1R_ADDR64_48 (0x2UL << ETH_MACHWF1R_ADDR64_Pos) /*!< 0x00008000 */
7502 #define ETH_MACHWF1R_ADVTHWORD_Pos (13U)
7503 #define ETH_MACHWF1R_ADVTHWORD_Msk (0x1UL << ETH_MACHWF1R_ADVTHWORD_Pos) /*!< 0x00002000 */
7504 #define ETH_MACHWF1R_ADVTHWORD ETH_MACHWF1R_ADVTHWORD_Msk /* IEEE 1588 High Word Register Enable */
7505 #define ETH_MACHWF1R_PTOEN_Pos (12U)
7506 #define ETH_MACHWF1R_PTOEN_Msk (0x1UL << ETH_MACHWF1R_PTOEN_Pos) /*!< 0x00001000 */
7507 #define ETH_MACHWF1R_PTOEN ETH_MACHWF1R_PTOEN_Msk /* PTP Offload Enable */
7508 #define ETH_MACHWF1R_OSTEN_Pos (11U)
7509 #define ETH_MACHWF1R_OSTEN_Msk (0x1UL << ETH_MACHWF1R_OSTEN_Pos) /*!< 0x00000800 */
7510 #define ETH_MACHWF1R_OSTEN ETH_MACHWF1R_OSTEN_Msk /* One-Step Timestamping Enable */
7511 #define ETH_MACHWF1R_TXFIFOSIZE_Pos (6U)
7512 #define ETH_MACHWF1R_TXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_TXFIFOSIZE_Pos) /*!< 0x000007C0 */
7513 #define ETH_MACHWF1R_TXFIFOSIZE ETH_MACHWF1R_TXFIFOSIZE_Msk /* MTL Transmit FIFO Size */
7514 #define ETH_MACHWF1R_RXFIFOSIZE_Pos (0U)
7515 #define ETH_MACHWF1R_RXFIFOSIZE_Msk (0x1FUL << ETH_MACHWF1R_RXFIFOSIZE_Pos) /*!< 0x0000001F */
7516 #define ETH_MACHWF1R_RXFIFOSIZE ETH_MACHWF1R_RXFIFOSIZE_Msk /* MTL Receive FIFO Size */
7517
7518 /* Bit definition for Ethernet MAC HW Feature2 Register */
7519 #define ETH_MACHWF2R_AUXSNAPNUM_Pos (28U)
7520 #define ETH_MACHWF2R_AUXSNAPNUM_Msk (0x7UL << ETH_MACHWF2R_AUXSNAPNUM_Pos) /*!< 0x70000000 */
7521 #define ETH_MACHWF2R_AUXSNAPNUM ETH_MACHWF2R_AUXSNAPNUM_Msk /* Number of Auxiliary Snapshot Inputs */
7522 #define ETH_MACHWF2R_PPSOUTNUM_Pos (24U)
7523 #define ETH_MACHWF2R_PPSOUTNUM_Msk (0x7UL << ETH_MACHWF2R_PPSOUTNUM_Pos) /*!< 0x07000000 */
7524 #define ETH_MACHWF2R_PPSOUTNUM ETH_MACHWF2R_PPSOUTNUM_Msk /* Number of PPS Outputs */
7525 #define ETH_MACHWF2R_TXCHCNT_Pos (18U)
7526 #define ETH_MACHWF2R_TXCHCNT_Msk (0xFUL << ETH_MACHWF2R_TXCHCNT_Pos) /*!< 0x003C0000 */
7527 #define ETH_MACHWF2R_TXCHCNT ETH_MACHWF2R_TXCHCNT_Msk /* Number of DMA Transmit Channels */
7528 #define ETH_MACHWF2R_RXCHCNT_Pos (13U)
7529 #define ETH_MACHWF2R_RXCHCNT_Msk (0x7UL << ETH_MACHWF2R_RXCHCNT_Pos) /*!< 0x0000E000 */
7530 #define ETH_MACHWF2R_RXCHCNT ETH_MACHWF2R_RXCHCNT_Msk /* Number of DMA Receive Channels */
7531 #define ETH_MACHWF2R_TXQCNT_Pos (6U)
7532 #define ETH_MACHWF2R_TXQCNT_Msk (0xFUL << ETH_MACHWF2R_TXQCNT_Pos) /*!< 0x000003C0 */
7533 #define ETH_MACHWF2R_TXQCNT ETH_MACHWF2R_TXQCNT_Msk /* Number of MTL Transmit Queues */
7534 #define ETH_MACHWF2R_RXQCNT_Pos (0U)
7535 #define ETH_MACHWF2R_RXQCNT_Msk (0xFUL << ETH_MACHWF2R_RXQCNT_Pos) /*!< 0x0000000F */
7536 #define ETH_MACHWF2R_RXQCNT ETH_MACHWF2R_RXQCNT_Msk /* Number of MTL Receive Queues */
7537
7538 /* Bit definition for Ethernet MAC MDIO Address Register */
7539 #define ETH_MACMDIOAR_PSE_Pos (27U)
7540 #define ETH_MACMDIOAR_PSE_Msk (0x1UL << ETH_MACMDIOAR_PSE_Pos) /*!< 0x08000000 */
7541 #define ETH_MACMDIOAR_PSE ETH_MACMDIOAR_PSE_Msk /* Preamble Suppression Enable */
7542 #define ETH_MACMDIOAR_BTB_Pos (26U)
7543 #define ETH_MACMDIOAR_BTB_Msk (0x1UL << ETH_MACMDIOAR_BTB_Pos) /*!< 0x04000000 */
7544 #define ETH_MACMDIOAR_BTB ETH_MACMDIOAR_BTB_Msk /* Back to Back transactions */
7545 #define ETH_MACMDIOAR_PA_Pos (21U)
7546 #define ETH_MACMDIOAR_PA_Msk (0x1FUL << ETH_MACMDIOAR_PA_Pos) /*!< 0x03E00000 */
7547 #define ETH_MACMDIOAR_PA ETH_MACMDIOAR_PA_Msk /* Physical Layer Address */
7548 #define ETH_MACMDIOAR_RDA_Pos (16U)
7549 #define ETH_MACMDIOAR_RDA_Msk (0x1FUL << ETH_MACMDIOAR_RDA_Pos) /*!< 0x001F0000 */
7550 #define ETH_MACMDIOAR_RDA ETH_MACMDIOAR_RDA_Msk /* Register/Device Address */
7551 #define ETH_MACMDIOAR_NTC_Pos (12U)
7552 #define ETH_MACMDIOAR_NTC_Msk (0x7UL << ETH_MACMDIOAR_NTC_Pos) /*!< 0x00007000 */
7553 #define ETH_MACMDIOAR_NTC ETH_MACMDIOAR_NTC_Msk /* Number of Trailing Clocks */
7554 #define ETH_MACMDIOAR_CR_Pos (8U)
7555 #define ETH_MACMDIOAR_CR_Msk (0xFUL << ETH_MACMDIOAR_CR_Pos) /*!< 0x00000F00 */
7556 #define ETH_MACMDIOAR_CR ETH_MACMDIOAR_CR_Msk /* CSR Clock Range */
7557 #define ETH_MACMDIOAR_CR_DIV42 ((uint32_t)0x00000000) /* CSR clock/42 */
7558 #define ETH_MACMDIOAR_CR_DIV62_Pos (8U)
7559 #define ETH_MACMDIOAR_CR_DIV62_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV62_Pos) /*!< 0x00000100 */
7560 #define ETH_MACMDIOAR_CR_DIV62 ETH_MACMDIOAR_CR_DIV62_Msk /* CSR clock/62 */
7561 #define ETH_MACMDIOAR_CR_DIV16_Pos (9U)
7562 #define ETH_MACMDIOAR_CR_DIV16_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV16_Pos) /*!< 0x00000200 */
7563 #define ETH_MACMDIOAR_CR_DIV16 ETH_MACMDIOAR_CR_DIV16_Msk /* CSR clock/16 */
7564 #define ETH_MACMDIOAR_CR_DIV26_Pos (8U)
7565 #define ETH_MACMDIOAR_CR_DIV26_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV26_Pos) /*!< 0x00000300 */
7566 #define ETH_MACMDIOAR_CR_DIV26 ETH_MACMDIOAR_CR_DIV26_Msk /* CSR clock/26 */
7567 #define ETH_MACMDIOAR_CR_DIV102_Pos (10U)
7568 #define ETH_MACMDIOAR_CR_DIV102_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV102_Pos) /*!< 0x00000400 */
7569 #define ETH_MACMDIOAR_CR_DIV102 ETH_MACMDIOAR_CR_DIV102_Msk /* CSR clock/102 */
7570 #define ETH_MACMDIOAR_CR_DIV124_Pos (8U)
7571 #define ETH_MACMDIOAR_CR_DIV124_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV124_Pos) /*!< 0x00000500 */
7572 #define ETH_MACMDIOAR_CR_DIV124 ETH_MACMDIOAR_CR_DIV124_Msk /* CSR clock/124 */
7573 #define ETH_MACMDIOAR_CR_DIV4AR_Pos (11U)
7574 #define ETH_MACMDIOAR_CR_DIV4AR_Msk (0x1UL << ETH_MACMDIOAR_CR_DIV4AR_Pos) /*!< 0x00000800 */
7575 #define ETH_MACMDIOAR_CR_DIV4AR ETH_MACMDIOAR_CR_DIV4AR_Msk /* CSR clock/4: MDC clock above range specified in IEEE */
7576 #define ETH_MACMDIOAR_CR_DIV6AR_Pos (8U)
7577 #define ETH_MACMDIOAR_CR_DIV6AR_Msk (0x9UL << ETH_MACMDIOAR_CR_DIV6AR_Pos) /*!< 0x00000900 */
7578 #define ETH_MACMDIOAR_CR_DIV6AR ETH_MACMDIOAR_CR_DIV6AR_Msk /* CSR clock/6: MDC clock above range specified in IEEE */
7579 #define ETH_MACMDIOAR_CR_DIV8AR_Pos (9U)
7580 #define ETH_MACMDIOAR_CR_DIV8AR_Msk (0x5UL << ETH_MACMDIOAR_CR_DIV8AR_Pos) /*!< 0x00000A00 */
7581 #define ETH_MACMDIOAR_CR_DIV8AR ETH_MACMDIOAR_CR_DIV8AR_Msk /* CSR clock/8: MDC clock above range specified in IEEE */
7582 #define ETH_MACMDIOAR_CR_DIV10AR_Pos (8U)
7583 #define ETH_MACMDIOAR_CR_DIV10AR_Msk (0xBUL << ETH_MACMDIOAR_CR_DIV10AR_Pos) /*!< 0x00000B00 */
7584 #define ETH_MACMDIOAR_CR_DIV10AR ETH_MACMDIOAR_CR_DIV10AR_Msk /* CSR clock/10: MDC clock above range specified in IEEE */
7585 #define ETH_MACMDIOAR_CR_DIV12AR_Pos (10U)
7586 #define ETH_MACMDIOAR_CR_DIV12AR_Msk (0x3UL << ETH_MACMDIOAR_CR_DIV12AR_Pos) /*!< 0x00000C00 */
7587 #define ETH_MACMDIOAR_CR_DIV12AR ETH_MACMDIOAR_CR_DIV12AR_Msk /* CSR clock/12: MDC clock above range specified in IEEE */
7588 #define ETH_MACMDIOAR_CR_DIV14AR_Pos (8U)
7589 #define ETH_MACMDIOAR_CR_DIV14AR_Msk (0xDUL << ETH_MACMDIOAR_CR_DIV14AR_Pos) /*!< 0x00000D00 */
7590 #define ETH_MACMDIOAR_CR_DIV14AR ETH_MACMDIOAR_CR_DIV14AR_Msk /* CSR clock/14: MDC clock above range specified in IEEE */
7591 #define ETH_MACMDIOAR_CR_DIV16AR_Pos (9U)
7592 #define ETH_MACMDIOAR_CR_DIV16AR_Msk (0x7UL << ETH_MACMDIOAR_CR_DIV16AR_Pos) /*!< 0x00000E00 */
7593 #define ETH_MACMDIOAR_CR_DIV16AR ETH_MACMDIOAR_CR_DIV16AR_Msk /* CSR clock/16: MDC clock above range specified in IEEE */
7594 #define ETH_MACMDIOAR_CR_DIV18AR_Pos (8U)
7595 #define ETH_MACMDIOAR_CR_DIV18AR_Msk (0xFUL << ETH_MACMDIOAR_CR_DIV18AR_Pos) /*!< 0x00000F00 */
7596 #define ETH_MACMDIOAR_CR_DIV18AR ETH_MACMDIOAR_CR_DIV18AR_Msk /* CSR clock/18: MDC clock above range specified in IEEE */
7597 #define ETH_MACMDIOAR_SKAP_Pos (4U)
7598 #define ETH_MACMDIOAR_SKAP_Msk (0x1UL << ETH_MACMDIOAR_SKAP_Pos) /*!< 0x00000010 */
7599 #define ETH_MACMDIOAR_SKAP ETH_MACMDIOAR_SKAP_Msk /* Skip Address Packet */
7600 #define ETH_MACMDIOAR_MOC_Pos (2U)
7601 #define ETH_MACMDIOAR_MOC_Msk (0x3UL << ETH_MACMDIOAR_MOC_Pos) /*!< 0x0000000C */
7602 #define ETH_MACMDIOAR_MOC ETH_MACMDIOAR_MOC_Msk /* MII Operation Command */
7603 #define ETH_MACMDIOAR_MOC_WR_Pos (2U)
7604 #define ETH_MACMDIOAR_MOC_WR_Msk (0x1UL << ETH_MACMDIOAR_MOC_WR_Pos) /*!< 0x00000004 */
7605 #define ETH_MACMDIOAR_MOC_WR ETH_MACMDIOAR_MOC_WR_Msk /* Write */
7606 #define ETH_MACMDIOAR_MOC_PRDIA_Pos (3U)
7607 #define ETH_MACMDIOAR_MOC_PRDIA_Msk (0x1UL << ETH_MACMDIOAR_MOC_PRDIA_Pos) /*!< 0x00000008 */
7608 #define ETH_MACMDIOAR_MOC_PRDIA ETH_MACMDIOAR_MOC_PRDIA_Msk /* Post Read Increment Address for Clause 45 PHY */
7609 #define ETH_MACMDIOAR_MOC_RD_Pos (2U)
7610 #define ETH_MACMDIOAR_MOC_RD_Msk (0x3UL << ETH_MACMDIOAR_MOC_RD_Pos) /*!< 0x0000000C */
7611 #define ETH_MACMDIOAR_MOC_RD ETH_MACMDIOAR_MOC_RD_Msk /* Read */
7612 #define ETH_MACMDIOAR_C45E_Pos (1U)
7613 #define ETH_MACMDIOAR_C45E_Msk (0x1UL << ETH_MACMDIOAR_C45E_Pos) /*!< 0x00000002 */
7614 #define ETH_MACMDIOAR_C45E ETH_MACMDIOAR_C45E_Msk /* Clause 45 PHY Enable */
7615 #define ETH_MACMDIOAR_MB_Pos (0U)
7616 #define ETH_MACMDIOAR_MB_Msk (0x1UL << ETH_MACMDIOAR_MB_Pos) /*!< 0x00000001 */
7617 #define ETH_MACMDIOAR_MB ETH_MACMDIOAR_MB_Msk /* MII Busy */
7618
7619 /* Bit definition for Ethernet MAC MDIO Data Register */
7620 #define ETH_MACMDIODR_RA_Pos (16U)
7621 #define ETH_MACMDIODR_RA_Msk (0xFFFFUL << ETH_MACMDIODR_RA_Pos) /*!< 0xFFFF0000 */
7622 #define ETH_MACMDIODR_RA ETH_MACMDIODR_RA_Msk /* Register Address */
7623 #define ETH_MACMDIODR_MD_Pos (0U)
7624 #define ETH_MACMDIODR_MD_Msk (0xFFFFUL << ETH_MACMDIODR_MD_Pos) /*!< 0x0000FFFF */
7625 #define ETH_MACMDIODR_MD ETH_MACMDIODR_MD_Msk /* MII Data */
7626
7627 /* Bit definition for Ethernet ARP Address Register */
7628 #define ETH_MACARPAR_ARPPA_Pos (0U)
7629 #define ETH_MACARPAR_ARPPA_Msk (0xFFFFFFFFUL << ETH_MACARPAR_ARPPA_Pos) /*!< 0xFFFFFFFF */
7630 #define ETH_MACARPAR_ARPPA ETH_MACARPAR_ARPPA_Msk /* ARP Protocol Address */
7631
7632 /* Bit definition for Ethernet MAC Address 0 High Register */
7633 #define ETH_MACA0HR_AE_Pos (31U)
7634 #define ETH_MACA0HR_AE_Msk (0x1UL << ETH_MACA0HR_AE_Pos) /*!< 0x80000000 */
7635 #define ETH_MACA0HR_AE ETH_MACA0HR_AE_Msk /* Address Enable*/
7636 #define ETH_MACA0HR_ADDRHI_Pos (0U)
7637 #define ETH_MACA0HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA0HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7638 #define ETH_MACA0HR_ADDRHI ETH_MACA0HR_ADDRHI_Msk /* MAC Address 0*/
7639
7640 /* Bit definition for Ethernet MAC Address 0 Low Register */
7641 #define ETH_MACA0LR_ADDRLO_Pos (0U)
7642 #define ETH_MACA0LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA0LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7643 #define ETH_MACA0LR_ADDRLO ETH_MACA0LR_ADDRLO_Msk /* MAC Address 0*/
7644
7645 /* Bit definition for Ethernet MAC Address 1 High Register */
7646 #define ETH_MACA1HR_AE_Pos (31U)
7647 #define ETH_MACA1HR_AE_Msk (0x1UL << ETH_MACA1HR_AE_Pos) /*!< 0x80000000 */
7648 #define ETH_MACA1HR_AE ETH_MACA1HR_AE_Msk /* Address Enable*/
7649 #define ETH_MACA1HR_SA_Pos (30U)
7650 #define ETH_MACA1HR_SA_Msk (0x1UL << ETH_MACA1HR_SA_Pos) /*!< 0x40000000 */
7651 #define ETH_MACA1HR_SA ETH_MACA1HR_SA_Msk /* Source Address */
7652 #define ETH_MACA1HR_MBC_Pos (24U)
7653 #define ETH_MACA1HR_MBC_Msk (0x3FUL << ETH_MACA1HR_MBC_Pos) /*!< 0x3F000000 */
7654 #define ETH_MACA1HR_MBC ETH_MACA1HR_MBC_Msk /* Mask Byte Control */
7655 #define ETH_MACA1HR_ADDRHI_Pos (0U)
7656 #define ETH_MACA1HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA1HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7657 #define ETH_MACA1HR_ADDRHI ETH_MACA1HR_ADDRHI_Msk /* MAC Address 1*/
7658
7659 /* Bit definition for Ethernet MAC Address 1 Low Register */
7660 #define ETH_MACA1LR_ADDRLO_Pos (0U)
7661 #define ETH_MACA1LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA1LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7662 #define ETH_MACA1LR_ADDRLO ETH_MACA1LR_ADDRLO_Msk /* MAC Address 1*/
7663
7664 /* Bit definition for Ethernet MAC Address 2 High Register */
7665 #define ETH_MACA2HR_AE_Pos (31U)
7666 #define ETH_MACA2HR_AE_Msk (0x1UL << ETH_MACA2HR_AE_Pos) /*!< 0x80000000 */
7667 #define ETH_MACA2HR_AE ETH_MACA2HR_AE_Msk /* Address Enable*/
7668 #define ETH_MACA2HR_SA_Pos (30U)
7669 #define ETH_MACA2HR_SA_Msk (0x1UL << ETH_MACA2HR_SA_Pos) /*!< 0x40000000 */
7670 #define ETH_MACA2HR_SA ETH_MACA2HR_SA_Msk /* Source Address */
7671 #define ETH_MACA2HR_MBC_Pos (24U)
7672 #define ETH_MACA2HR_MBC_Msk (0x3FUL << ETH_MACA2HR_MBC_Pos) /*!< 0x3F000000 */
7673 #define ETH_MACA2HR_MBC ETH_MACA2HR_MBC_Msk /* Mask Byte Control */
7674 #define ETH_MACA2HR_ADDRHI_Pos (0U)
7675 #define ETH_MACA2HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA2HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7676 #define ETH_MACA2HR_ADDRHI ETH_MACA2HR_ADDRHI_Msk /* MAC Address 1*/
7677
7678 /* Bit definition for Ethernet MAC Address 2 Low Register */
7679 #define ETH_MACA2LR_ADDRLO_Pos (0U)
7680 #define ETH_MACA2LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA2LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7681 #define ETH_MACA2LR_ADDRLO ETH_MACA2LR_ADDRLO_Msk /* MAC Address 2*/
7682
7683 /* Bit definition for Ethernet MAC Address 3 High Register */
7684 #define ETH_MACA3HR_AE_Pos (31U)
7685 #define ETH_MACA3HR_AE_Msk (0x1UL << ETH_MACA3HR_AE_Pos) /*!< 0x80000000 */
7686 #define ETH_MACA3HR_AE ETH_MACA3HR_AE_Msk /* Address Enable*/
7687 #define ETH_MACA3HR_SA_Pos (30U)
7688 #define ETH_MACA3HR_SA_Msk (0x1UL << ETH_MACA3HR_SA_Pos) /*!< 0x40000000 */
7689 #define ETH_MACA3HR_SA ETH_MACA3HR_SA_Msk /* Source Address */
7690 #define ETH_MACA3HR_MBC_Pos (24U)
7691 #define ETH_MACA3HR_MBC_Msk (0x3FUL << ETH_MACA3HR_MBC_Pos) /*!< 0x3F000000 */
7692 #define ETH_MACA3HR_MBC ETH_MACA3HR_MBC_Msk /* Mask Byte Control */
7693 #define ETH_MACA3HR_ADDRHI_Pos (0U)
7694 #define ETH_MACA3HR_ADDRHI_Msk (0xFFFFUL << ETH_MACA3HR_ADDRHI_Pos) /*!< 0x0000FFFF */
7695 #define ETH_MACA3HR_ADDRHI ETH_MACA3HR_ADDRHI_Msk /* MAC Address 1*/
7696
7697 /* Bit definition for Ethernet MAC Address 3 Low Register */
7698 #define ETH_MACA3LR_ADDRLO_Pos (0U)
7699 #define ETH_MACA3LR_ADDRLO_Msk (0xFFFFFFFFUL << ETH_MACA3LR_ADDRLO_Pos) /*!< 0xFFFFFFFF */
7700 #define ETH_MACA3LR_ADDRLO ETH_MACA3LR_ADDRLO_Msk /* MAC Address 3*/
7701
7702 /* Bit definition for Ethernet MAC Address High Register */
7703 #define ETH_MACAHR_AE_Pos (31U)
7704 #define ETH_MACAHR_AE_Msk (0x1UL << ETH_MACAHR_AE_Pos) /*!< 0x80000000 */
7705 #define ETH_MACAHR_AE ETH_MACAHR_AE_Msk /* Address enable */
7706 #define ETH_MACAHR_SA_Pos (30U)
7707 #define ETH_MACAHR_SA_Msk (0x1UL << ETH_MACAHR_SA_Pos) /*!< 0x40000000 */
7708 #define ETH_MACAHR_SA ETH_MACAHR_SA_Msk /* Source address */
7709 #define ETH_MACAHR_MBC_Pos (24U)
7710 #define ETH_MACAHR_MBC_Msk (0x3FUL << ETH_MACAHR_MBC_Pos) /*!< 0x3F000000 */
7711 #define ETH_MACAHR_MBC ETH_MACAHR_MBC_Msk /* Mask byte control: bits to mask for comparison of the MAC Address bytes */
7712 #define ETH_MACAHR_MBC_HBITS15_8 ((uint32_t)0x20000000) /* Mask MAC Address high reg bits [15:8] */
7713 #define ETH_MACAHR_MBC_HBITS7_0 ((uint32_t)0x10000000) /* Mask MAC Address high reg bits [7:0] */
7714 #define ETH_MACAHR_MBC_LBITS31_24 ((uint32_t)0x08000000) /* Mask MAC Address low reg bits [31:24] */
7715 #define ETH_MACAHR_MBC_LBITS23_16 ((uint32_t)0x04000000) /* Mask MAC Address low reg bits [23:16] */
7716 #define ETH_MACAHR_MBC_LBITS15_8 ((uint32_t)0x02000000) /* Mask MAC Address low reg bits [15:8] */
7717 #define ETH_MACAHR_MBC_LBITS7_0 ((uint32_t)0x01000000) /* Mask MAC Address low reg bits [7:0] */
7718 #define ETH_MACAHR_MACAH_Pos (0U)
7719 #define ETH_MACAHR_MACAH_Msk (0xFFFFUL << ETH_MACAHR_MACAH_Pos) /*!< 0x0000FFFF */
7720 #define ETH_MACAHR_MACAH ETH_MACAHR_MACAH_Msk /* MAC address high */
7721
7722 /* Bit definition for Ethernet MAC Address Low Register */
7723 #define ETH_MACALR_MACAL_Pos (0U)
7724 #define ETH_MACALR_MACAL_Msk (0xFFFFFFFFUL << ETH_MACALR_MACAL_Pos) /*!< 0xFFFFFFFF */
7725 #define ETH_MACALR_MACAL ETH_MACALR_MACAL_Msk /* MAC address low */
7726
7727 /* Bit definition for Ethernet MMC Control Register */
7728 #define ETH_MMCCR_UCDBC_Pos (8U)
7729 #define ETH_MMCCR_UCDBC_Msk (0x1UL << ETH_MMCCR_UCDBC_Pos) /*!< 0x00000100 */
7730 #define ETH_MMCCR_UCDBC ETH_MMCCR_UCDBC_Msk /* Update MMC Counters for Dropped Broadcast Packets */
7731 #define ETH_MMCCR_CNTPRSTLVL_Pos (5U)
7732 #define ETH_MMCCR_CNTPRSTLVL_Msk (0x1UL << ETH_MMCCR_CNTPRSTLVL_Pos) /*!< 0x00000020 */
7733 #define ETH_MMCCR_CNTPRSTLVL ETH_MMCCR_CNTPRSTLVL_Msk /* Full-Half Preset */
7734 #define ETH_MMCCR_CNTPRST_Pos (4U)
7735 #define ETH_MMCCR_CNTPRST_Msk (0x1UL << ETH_MMCCR_CNTPRST_Pos) /*!< 0x00000010 */
7736 #define ETH_MMCCR_CNTPRST ETH_MMCCR_CNTPRST_Msk /* Counters Reset */
7737 #define ETH_MMCCR_CNTFREEZ_Pos (3U)
7738 #define ETH_MMCCR_CNTFREEZ_Msk (0x1UL << ETH_MMCCR_CNTFREEZ_Pos) /*!< 0x00000008 */
7739 #define ETH_MMCCR_CNTFREEZ ETH_MMCCR_CNTFREEZ_Msk /* MMC Counter Freeze */
7740 #define ETH_MMCCR_RSTONRD_Pos (2U)
7741 #define ETH_MMCCR_RSTONRD_Msk (0x1UL << ETH_MMCCR_RSTONRD_Pos) /*!< 0x00000004 */
7742 #define ETH_MMCCR_RSTONRD ETH_MMCCR_RSTONRD_Msk /* Reset On Read */
7743 #define ETH_MMCCR_CNTSTOPRO_Pos (1U)
7744 #define ETH_MMCCR_CNTSTOPRO_Msk (0x1UL << ETH_MMCCR_CNTSTOPRO_Pos) /*!< 0x00000002 */
7745 #define ETH_MMCCR_CNTSTOPRO ETH_MMCCR_CNTSTOPRO_Msk /* Counter Stop Rollover */
7746 #define ETH_MMCCR_CNTRST_Pos (0U)
7747 #define ETH_MMCCR_CNTRST_Msk (0x1UL << ETH_MMCCR_CNTRST_Pos) /*!< 0x00000001 */
7748 #define ETH_MMCCR_CNTRST ETH_MMCCR_CNTRST_Msk /* Counters Reset */
7749
7750 /* Bit definition for Ethernet MMC Rx Interrupt Register */
7751 #define ETH_MMCRIR_RXLPITRCIS_Pos (27U)
7752 #define ETH_MMCRIR_RXLPITRCIS_Msk (0x1UL << ETH_MMCRIR_RXLPITRCIS_Pos) /*!< 0x08000000 */
7753 #define ETH_MMCRIR_RXLPITRCIS ETH_MMCRIR_RXLPITRCIS_Msk /* MMC Receive LPI transition counter interrupt status */
7754 #define ETH_MMCRIR_RXLPIUSCIS_Pos (26U)
7755 #define ETH_MMCRIR_RXLPIUSCIS_Msk (0x1UL << ETH_MMCRIR_RXLPIUSCIS_Pos) /*!< 0x04000000 */
7756 #define ETH_MMCRIR_RXLPIUSCIS ETH_MMCRIR_RXLPIUSCIS_Msk /* MMC Receive LPI microsecond counter interrupt status */
7757 #define ETH_MMCRIR_RXUCGPIS_Pos (17U)
7758 #define ETH_MMCRIR_RXUCGPIS_Msk (0x1UL << ETH_MMCRIR_RXUCGPIS_Pos) /*!< 0x00020000 */
7759 #define ETH_MMCRIR_RXUCGPIS ETH_MMCRIR_RXUCGPIS_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Status */
7760 #define ETH_MMCRIR_RXALGNERPIS_Pos (6U)
7761 #define ETH_MMCRIR_RXALGNERPIS_Msk (0x1UL << ETH_MMCRIR_RXALGNERPIS_Pos) /*!< 0x00000040 */
7762 #define ETH_MMCRIR_RXALGNERPIS ETH_MMCRIR_RXALGNERPIS_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Status */
7763 #define ETH_MMCRIR_RXCRCERPIS_Pos (5U)
7764 #define ETH_MMCRIR_RXCRCERPIS_Msk (0x1UL << ETH_MMCRIR_RXCRCERPIS_Pos) /*!< 0x00000020 */
7765 #define ETH_MMCRIR_RXCRCERPIS ETH_MMCRIR_RXCRCERPIS_Msk /* MMC Receive CRC Error Packet Counter Interrupt Status */
7766
7767 /* Bit definition for Ethernet MMC Tx Interrupt Register */
7768 #define ETH_MMCTIR_TXLPITRCIS_Pos (27U)
7769 #define ETH_MMCTIR_TXLPITRCIS_Msk (0x1UL << ETH_MMCTIR_TXLPITRCIS_Pos) /*!< 0x08000000 */
7770 #define ETH_MMCTIR_TXLPITRCIS ETH_MMCTIR_TXLPITRCIS_Msk /* MMC Transmit LPI transition counter interrupt status */
7771 #define ETH_MMCTIR_TXLPIUSCIS_Pos (26U)
7772 #define ETH_MMCTIR_TXLPIUSCIS_Msk (0x1UL << ETH_MMCTIR_TXLPIUSCIS_Pos) /*!< 0x04000000 */
7773 #define ETH_MMCTIR_TXLPIUSCIS ETH_MMCTIR_TXLPIUSCIS_Msk /* MMC Transmit LPI microsecond counter interrupt status */
7774 #define ETH_MMCTIR_TXGPKTIS_Pos (21U)
7775 #define ETH_MMCTIR_TXGPKTIS_Msk (0x1UL << ETH_MMCTIR_TXGPKTIS_Pos) /*!< 0x00200000 */
7776 #define ETH_MMCTIR_TXGPKTIS ETH_MMCTIR_TXGPKTIS_Msk /* MMC Transmit Good Packet Counter Interrupt Status */
7777 #define ETH_MMCTIR_TXMCOLGPIS_Pos (15U)
7778 #define ETH_MMCTIR_TXMCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXMCOLGPIS_Pos) /*!< 0x00008000 */
7779 #define ETH_MMCTIR_TXMCOLGPIS ETH_MMCTIR_TXMCOLGPIS_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Status */
7780 #define ETH_MMCTIR_TXSCOLGPIS_Pos (14U)
7781 #define ETH_MMCTIR_TXSCOLGPIS_Msk (0x1UL << ETH_MMCTIR_TXSCOLGPIS_Pos) /*!< 0x00004000 */
7782 #define ETH_MMCTIR_TXSCOLGPIS ETH_MMCTIR_TXSCOLGPIS_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Status */
7783
7784 /* Bit definition for Ethernet MMC Rx interrupt Mask register */
7785 #define ETH_MMCRIMR_RXLPITRCIM_Pos (27U)
7786 #define ETH_MMCRIMR_RXLPITRCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPITRCIM_Pos) /*!< 0x08000000 */
7787 #define ETH_MMCRIMR_RXLPITRCIM ETH_MMCRIMR_RXLPITRCIM_Msk /* MMC Receive LPI transition counter interrupt Mask */
7788 #define ETH_MMCRIMR_RXLPIUSCIM_Pos (26U)
7789 #define ETH_MMCRIMR_RXLPIUSCIM_Msk (0x1UL << ETH_MMCRIMR_RXLPIUSCIM_Pos) /*!< 0x04000000 */
7790 #define ETH_MMCRIMR_RXLPIUSCIM ETH_MMCRIMR_RXLPIUSCIM_Msk /* MMC Receive LPI microsecond counter interrupt Mask */
7791 #define ETH_MMCRIMR_RXUCGPIM_Pos (17U)
7792 #define ETH_MMCRIMR_RXUCGPIM_Msk (0x1UL << ETH_MMCRIMR_RXUCGPIM_Pos) /*!< 0x00020000 */
7793 #define ETH_MMCRIMR_RXUCGPIM ETH_MMCRIMR_RXUCGPIM_Msk /* MMC Receive Unicast Good Packet Counter Interrupt Mask */
7794 #define ETH_MMCRIMR_RXALGNERPIM_Pos (6U)
7795 #define ETH_MMCRIMR_RXALGNERPIM_Msk (0x1UL << ETH_MMCRIMR_RXALGNERPIM_Pos) /*!< 0x00000040 */
7796 #define ETH_MMCRIMR_RXALGNERPIM ETH_MMCRIMR_RXALGNERPIM_Msk /* MMC Receive Alignment Error Packet Counter Interrupt Mask */
7797 #define ETH_MMCRIMR_RXCRCERPIM_Pos (5U)
7798 #define ETH_MMCRIMR_RXCRCERPIM_Msk (0x1UL << ETH_MMCRIMR_RXCRCERPIM_Pos) /*!< 0x00000020 */
7799 #define ETH_MMCRIMR_RXCRCERPIM ETH_MMCRIMR_RXCRCERPIM_Msk /* MMC Receive CRC Error Packet Counter Interrupt Mask */
7800
7801 /* Bit definition for Ethernet MMC Tx Interrupt Mask Register */
7802 #define ETH_MMCTIMR_TXLPITRCIM_Pos (27U)
7803 #define ETH_MMCTIMR_TXLPITRCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPITRCIM_Pos) /*!< 0x08000000 */
7804 #define ETH_MMCTIMR_TXLPITRCIM ETH_MMCTIMR_TXLPITRCIM_Msk /* MMC Transmit LPI transition counter interrupt Mask*/
7805 #define ETH_MMCTIMR_TXLPIUSCIM_Pos (26U)
7806 #define ETH_MMCTIMR_TXLPIUSCIM_Msk (0x1UL << ETH_MMCTIMR_TXLPIUSCIM_Pos) /*!< 0x04000000 */
7807 #define ETH_MMCTIMR_TXLPIUSCIM ETH_MMCTIMR_TXLPIUSCIM_Msk /* MMC Transmit LPI microsecond counter interrupt Mask*/
7808 #define ETH_MMCTIMR_TXGPKTIM_Pos (21U)
7809 #define ETH_MMCTIMR_TXGPKTIM_Msk (0x1UL << ETH_MMCTIMR_TXGPKTIM_Pos) /*!< 0x00200000 */
7810 #define ETH_MMCTIMR_TXGPKTIM ETH_MMCTIMR_TXGPKTIM_Msk /* MMC Transmit Good Packet Counter Interrupt Mask*/
7811 #define ETH_MMCTIMR_TXMCOLGPIM_Pos (15U)
7812 #define ETH_MMCTIMR_TXMCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXMCOLGPIM_Pos) /*!< 0x00008000 */
7813 #define ETH_MMCTIMR_TXMCOLGPIM ETH_MMCTIMR_TXMCOLGPIM_Msk /* MMC Transmit Multiple Collision Good Packet Counter Interrupt Mask */
7814 #define ETH_MMCTIMR_TXSCOLGPIM_Pos (14U)
7815 #define ETH_MMCTIMR_TXSCOLGPIM_Msk (0x1UL << ETH_MMCTIMR_TXSCOLGPIM_Pos) /*!< 0x00004000 */
7816 #define ETH_MMCTIMR_TXSCOLGPIM ETH_MMCTIMR_TXSCOLGPIM_Msk /* MMC Transmit Single Collision Good Packet Counter Interrupt Mask */
7817
7818 /* Bit definition for Ethernet MMC Tx Single Collision Good Packets Register */
7819 #define ETH_MMCTSCGPR_TXSNGLCOLG_Pos (0U)
7820 #define ETH_MMCTSCGPR_TXSNGLCOLG_msk (0xFFFFFFFFUL << ETH_MMCTSCGPR_TXSNGLCOLG_Pos) /*!< 0xFFFFFFFF */
7821 #define ETH_MMCTSCGPR_TXSNGLCOLG ETH_MMCTSCGPR_TXSNGLCOLG_msk /* Tx Single Collision Good Packets */
7822
7823 /* Bit definition for Ethernet MMC Tx Multiple Collision Good Packets Register */
7824 #define ETH_MMCTMCGPR_TXMULTCOLG_Pos (0U)
7825 #define ETH_MMCTMCGPR_TXMULTCOLG_msk (0xFFFFFFFFUL << ETH_MMCTMCGPR_TXMULTCOLG_Pos) /*!< 0xFFFFFFFF */
7826 #define ETH_MMCTMCGPR_TXMULTCOLG ETH_MMCTMCGPR_TXMULTCOLG_msk /* Tx Multiple Collision Good Packets */
7827
7828 /* Bit definition for Ethernet MMC Tx Packet Count Good Register */
7829 #define ETH_MMCTPCGR_TXPKTG_Pos (0U)
7830 #define ETH_MMCTPCGR_TXPKTG_msk (0xFFFFFFFFUL << ETH_MMCTPCGR_TXPKTG_Pos) /*!< 0xFFFFFFFF */
7831 #define ETH_MMCTPCGR_TXPKTG ETH_MMCTPCGR_TXPKTG_msk /* Tx Packet Count Good */
7832
7833 /* Bit definition for Ethernet MMC Rx CRC Error Packets Register */
7834 #define ETH_MMCRCRCEPR_RXCRCERR_Pos (0U)
7835 #define ETH_MMCRCRCEPR_RXCRCERR_msk (0xFFFFFFFFUL << ETH_MMCRCRCEPR_RXCRCERR_Pos) /*!< 0xFFFFFFFF */
7836 #define ETH_MMCRCRCEPR_RXCRCERR ETH_MMCRCRCEPR_RXCRCERR_msk /* Rx CRC Error Packets */
7837
7838 /* Bit definition for Ethernet MMC Rx alignment error packets register */
7839 #define ETH_MMCRAEPR_RXALGNERR_Pos (0U)
7840 #define ETH_MMCRAEPR_RXALGNERR_msk (0xFFFFFFFFUL << ETH_MMCRAEPR_RXALGNERR_Pos) /*!< 0xFFFFFFFF */
7841 #define ETH_MMCRAEPR_RXALGNERR ETH_MMCRAEPR_RXALGNERR_msk /* Rx Alignment Error Packets */
7842
7843 /* Bit definition for Ethernet MMC Rx Unicast Packets Good Register */
7844 #define ETH_MMCRUPGR_RXUCASTG_Pos (0U)
7845 #define ETH_MMCRUPGR_RXUCASTG_msk (0xFFFFFFFFUL << ETH_MMCRUPGR_RXUCASTG_Pos) /*!< 0xFFFFFFFF */
7846 #define ETH_MMCRUPGR_RXUCASTG ETH_MMCRUPGR_RXUCASTG_msk /* Rx Unicast Packets Good */
7847
7848 /* Bit definition for Ethernet MMC Tx LPI Microsecond Timer Register */
7849 #define ETH_MMCTLPIMSTR_TXLPIUSC_Pos (0U)
7850 #define ETH_MMCTLPIMSTR_TXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCTLPIMSTR_TXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7851 #define ETH_MMCTLPIMSTR_TXLPIUSC ETH_MMCTLPIMSTR_TXLPIUSC_msk /* Tx LPI Microseconds Counter */
7852
7853 /* Bit definition for Ethernet MMC Tx LPI Transition Counter Register */
7854 #define ETH_MMCTLPITCR_TXLPITRC_Pos (0U)
7855 #define ETH_MMCTLPITCR_TXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCTLPITCR_TXLPITRC_Pos) /*!< 0xFFFFFFFF */
7856 #define ETH_MMCTLPITCR_TXLPITRC ETH_MMCTLPITCR_TXLPITRC_msk /* Tx LPI Transition counter */
7857
7858 /* Bit definition for Ethernet MMC Rx LPI Microsecond Counter Register */
7859 #define ETH_MMCRLPIMSTR_RXLPIUSC_Pos (0U)
7860 #define ETH_MMCRLPIMSTR_RXLPIUSC_msk (0xFFFFFFFFUL << ETH_MMCRLPIMSTR_RXLPIUSC_Pos) /*!< 0xFFFFFFFF */
7861 #define ETH_MMCRLPIMSTR_RXLPIUSC ETH_MMCRLPIMSTR_RXLPIUSC_msk /* Rx LPI Microseconds Counter */
7862
7863 /* Bit definition for Ethernet MMC Rx LPI Transition Counter Register */
7864 #define ETH_MMCRLPITCR_RXLPITRC_Pos (0U)
7865 #define ETH_MMCRLPITCR_RXLPITRC_msk (0xFFFFFFFFUL << ETH_MMCRLPITCR_RXLPITRC_Pos) /*!< 0xFFFFFFFF */
7866 #define ETH_MMCRLPITCR_RXLPITRC ETH_MMCRLPITCR_RXLPITRC_msk /* Rx LPI Transition counter */
7867
7868 /* Bit definition for Ethernet MAC L3 L4 Control Register */
7869 #define ETH_MACL3L4CR_L4DPIM_Pos (21U)
7870 #define ETH_MACL3L4CR_L4DPIM_Msk (0x1UL << ETH_MACL3L4CR_L4DPIM_Pos) /*!< 0x00200000 */
7871 #define ETH_MACL3L4CR_L4DPIM ETH_MACL3L4CR_L4DPIM_Msk /* Layer 4 Destination Port Inverse Match Enable */
7872 #define ETH_MACL3L4CR_L4DPM_Pos (20U)
7873 #define ETH_MACL3L4CR_L4DPM_Msk (0x1UL << ETH_MACL3L4CR_L4DPM_Pos) /*!< 0x00100000 */
7874 #define ETH_MACL3L4CR_L4DPM ETH_MACL3L4CR_L4DPM_Msk /* Layer 4 Destination Port Match Enable */
7875 #define ETH_MACL3L4CR_L4SPIM_Pos (19U)
7876 #define ETH_MACL3L4CR_L4SPIM_Msk (0x1UL << ETH_MACL3L4CR_L4SPIM_Pos) /*!< 0x00080000 */
7877 #define ETH_MACL3L4CR_L4SPIM ETH_MACL3L4CR_L4SPIM_Msk /* Layer 4 Source Port Inverse Match Enable */
7878 #define ETH_MACL3L4CR_L4SPM_Pos (18U)
7879 #define ETH_MACL3L4CR_L4SPM_Msk (0x1UL << ETH_MACL3L4CR_L4SPM_Pos) /*!< 0x00040000 */
7880 #define ETH_MACL3L4CR_L4SPM ETH_MACL3L4CR_L4SPM_Msk /* Layer 4 Source Port Match Enable */
7881 #define ETH_MACL3L4CR_L4PEN_Pos (16U)
7882 #define ETH_MACL3L4CR_L4PEN_Msk (0x1UL << ETH_MACL3L4CR_L4PEN_Pos) /*!< 0x00010000 */
7883 #define ETH_MACL3L4CR_L4PEN ETH_MACL3L4CR_L4PEN_Msk /* Layer 4 Protocol Enable */
7884 #define ETH_MACL3L4CR_L3HDBM_Pos (11U)
7885 #define ETH_MACL3L4CR_L3HDBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HDBM_Pos) /*!< 0x0000F800 */
7886 #define ETH_MACL3L4CR_L3HDBM ETH_MACL3L4CR_L3HDBM_Msk /* Layer 3 IP DA Higher Bits Match */
7887 #define ETH_MACL3L4CR_L3HSBM_Pos (6U)
7888 #define ETH_MACL3L4CR_L3HSBM_Msk (0x1FUL << ETH_MACL3L4CR_L3HSBM_Pos) /*!< 0x000007C0 */
7889 #define ETH_MACL3L4CR_L3HSBM ETH_MACL3L4CR_L3HSBM_Msk /* Layer 3 IP SA Higher Bits Match */
7890 #define ETH_MACL3L4CR_L3DAIM_Pos (5U)
7891 #define ETH_MACL3L4CR_L3DAIM_Msk (0x1UL << ETH_MACL3L4CR_L3DAIM_Pos) /*!< 0x00000020 */
7892 #define ETH_MACL3L4CR_L3DAIM ETH_MACL3L4CR_L3DAIM_Msk /* Layer 3 IP DA Inverse Match Enable */
7893 #define ETH_MACL3L4CR_L3DAM_Pos (4U)
7894 #define ETH_MACL3L4CR_L3DAM_Msk (0x1UL << ETH_MACL3L4CR_L3DAM_Pos) /*!< 0x00000010 */
7895 #define ETH_MACL3L4CR_L3DAM ETH_MACL3L4CR_L3DAM_Msk /* Layer 3 IP DA Match Enable */
7896 #define ETH_MACL3L4CR_L3SAIM_Pos (3U)
7897 #define ETH_MACL3L4CR_L3SAIM_Msk (0x1UL << ETH_MACL3L4CR_L3SAIM_Pos) /*!< 0x00000008 */
7898 #define ETH_MACL3L4CR_L3SAIM ETH_MACL3L4CR_L3SAIM_Msk /* Layer 3 IP SA Inverse Match Enable */
7899 #define ETH_MACL3L4CR_L3SAM_Pos (2U)
7900 #define ETH_MACL3L4CR_L3SAM_Msk (0x1UL << ETH_MACL3L4CR_L3SAM_Pos) /*!< 0x00000004 */
7901 #define ETH_MACL3L4CR_L3SAM ETH_MACL3L4CR_L3SAM_Msk /* Layer 3 IP SA Match Enable*/
7902 #define ETH_MACL3L4CR_L3PEN_Pos (0U)
7903 #define ETH_MACL3L4CR_L3PEN_Msk (0x1UL << ETH_MACL3L4CR_L3PEN_Pos) /*!< 0x00000001 */
7904 #define ETH_MACL3L4CR_L3PEN ETH_MACL3L4CR_L3PEN_Msk /* Layer 3 Protocol Enable */
7905
7906 /* Bit definition for Ethernet MAC L4 Address Register */
7907 #define ETH_MACL4AR_L4DP_Pos (16U)
7908 #define ETH_MACL4AR_L4DP_Msk (0xFFFFUL << ETH_MACL4AR_L4DP_Pos) /*!< 0xFFFF0000 */
7909 #define ETH_MACL4AR_L4DP ETH_MACL4AR_L4DP_Msk /* Layer 4 Destination Port Number Field */
7910 #define ETH_MACL4AR_L4SP_Pos (0U)
7911 #define ETH_MACL4AR_L4SP_Msk (0xFFFFUL << ETH_MACL4AR_L4SP_Pos) /*!< 0x0000FFFF */
7912 #define ETH_MACL4AR_L4SP ETH_MACL4AR_L4SP_Msk /* Layer 4 Source Port Number Field */
7913
7914 /* Bit definition for Ethernet MAC L3 Address0 Register */
7915 #define ETH_MACL3A0R_L3A0_Pos (0U)
7916 #define ETH_MACL3A0R_L3A0_Msk (0xFFFFFFFFUL << ETH_MACL3A0R_L3A0_Pos) /*!< 0xFFFFFFFF */
7917 #define ETH_MACL3A0R_L3A0 ETH_MACL3A0R_L3A0_Msk /* Layer 3 Address 0 Field */
7918
7919 /* Bit definition for Ethernet MAC L4 Address1 Register */
7920 #define ETH_MACL3A1R_L3A1_Pos (0U)
7921 #define ETH_MACL3A1R_L3A1_Msk (0xFFFFFFFFUL << ETH_MACL3A1R_L3A1_Pos) /*!< 0xFFFFFFFF */
7922 #define ETH_MACL3A1R_L3A1 ETH_MACL3A1R_L3A1_Msk /* Layer 3 Address 1 Field */
7923
7924 /* Bit definition for Ethernet MAC L4 Address2 Register */
7925 #define ETH_MACL3A2R_L3A2_Pos (0U)
7926 #define ETH_MACL3A2R_L3A2_Msk (0xFFFFFFFFUL << ETH_MACL3A2R_L3A2_Pos) /*!< 0xFFFFFFFF */
7927 #define ETH_MACL3A2R_L3A2 ETH_MACL3A2R_L3A2_Msk /* Layer 3 Address 2 Field */
7928
7929 /* Bit definition for Ethernet MAC L4 Address3 Register */
7930 #define ETH_MACL3A3R_L3A3_Pos (0U)
7931 #define ETH_MACL3A3R_L3A3_Msk (0xFFFFFFFFUL << ETH_MACL3A3R_L3A3_Pos) /*!< 0xFFFFFFFF */
7932 #define ETH_MACL3A3R_L3A3 ETH_MACL3A3R_L3A3_Msk /* Layer 3 Address 3 Field */
7933
7934 /* Bit definition for Ethernet MAC Timestamp Control Register */
7935 #define ETH_MACTSCR_TXTSSTSM_Pos (24U)
7936 #define ETH_MACTSCR_TXTSSTSM_Msk (0x1UL << ETH_MACTSCR_TXTSSTSM_Pos) /*!< 0x01000000 */
7937 #define ETH_MACTSCR_TXTSSTSM ETH_MACTSCR_TXTSSTSM_Msk /* Transmit Timestamp Status Mode */
7938 #define ETH_MACTSCR_CSC_Pos (19U)
7939 #define ETH_MACTSCR_CSC_Msk (0x1UL << ETH_MACTSCR_CSC_Pos) /*!< 0x00080000 */
7940 #define ETH_MACTSCR_CSC ETH_MACTSCR_CSC_Msk /* Enable checksum correction during OST for PTP over UDP/IPv4 packets */
7941 #define ETH_MACTSCR_TSENMACADDR_Pos (18U)
7942 #define ETH_MACTSCR_TSENMACADDR_Msk (0x1UL << ETH_MACTSCR_TSENMACADDR_Pos) /*!< 0x00040000 */
7943 #define ETH_MACTSCR_TSENMACADDR ETH_MACTSCR_TSENMACADDR_Msk /* Enable MAC Address for PTP Packet Filtering */
7944 #define ETH_MACTSCR_SNAPTYPSEL_Pos (16U)
7945 #define ETH_MACTSCR_SNAPTYPSEL_Msk (0x3UL << ETH_MACTSCR_SNAPTYPSEL_Pos) /*!< 0x00030000 */
7946 #define ETH_MACTSCR_SNAPTYPSEL ETH_MACTSCR_SNAPTYPSEL_Msk /* Select PTP packets for Taking Snapshots */
7947 #define ETH_MACTSCR_TSMSTRENA_Pos (15U)
7948 #define ETH_MACTSCR_TSMSTRENA_Msk (0x1UL << ETH_MACTSCR_TSMSTRENA_Pos) /*!< 0x00008000 */
7949 #define ETH_MACTSCR_TSMSTRENA ETH_MACTSCR_TSMSTRENA_Msk /* Enable Snapshot for Messages Relevant to Master */
7950 #define ETH_MACTSCR_TSEVNTENA_Pos (14U)
7951 #define ETH_MACTSCR_TSEVNTENA_Msk (0x1UL << ETH_MACTSCR_TSEVNTENA_Pos) /*!< 0x00004000 */
7952 #define ETH_MACTSCR_TSEVNTENA ETH_MACTSCR_TSEVNTENA_Msk /* Enable Timestamp Snapshot for Event Messages */
7953 #define ETH_MACTSCR_TSIPV4ENA_Pos (13U)
7954 #define ETH_MACTSCR_TSIPV4ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV4ENA_Pos) /*!< 0x00002000 */
7955 #define ETH_MACTSCR_TSIPV4ENA ETH_MACTSCR_TSIPV4ENA_Msk /* Enable Processing of PTP Packets Sent over IPv4-UDP */
7956 #define ETH_MACTSCR_TSIPV6ENA_Pos (12U)
7957 #define ETH_MACTSCR_TSIPV6ENA_Msk (0x1UL << ETH_MACTSCR_TSIPV6ENA_Pos) /*!< 0x00001000 */
7958 #define ETH_MACTSCR_TSIPV6ENA ETH_MACTSCR_TSIPV6ENA_Msk /* Enable Processing of PTP Packets Sent over IPv6-UDP */
7959 #define ETH_MACTSCR_TSIPENA_Pos (11U)
7960 #define ETH_MACTSCR_TSIPENA_Msk (0x1UL << ETH_MACTSCR_TSIPENA_Pos) /*!< 0x00000800 */
7961 #define ETH_MACTSCR_TSIPENA ETH_MACTSCR_TSIPENA_Msk /* Enable Processing of PTP over Ethernet Packets */
7962 #define ETH_MACTSCR_TSVER2ENA_Pos (10U)
7963 #define ETH_MACTSCR_TSVER2ENA_Msk (0x1UL << ETH_MACTSCR_TSVER2ENA_Pos) /*!< 0x00000400 */
7964 #define ETH_MACTSCR_TSVER2ENA ETH_MACTSCR_TSVER2ENA_Msk /* Enable PTP Packet Processing for Version 2 Format */
7965 #define ETH_MACTSCR_TSCTRLSSR_Pos (9U)
7966 #define ETH_MACTSCR_TSCTRLSSR_Msk (0x1UL << ETH_MACTSCR_TSCTRLSSR_Pos) /*!< 0x00000200 */
7967 #define ETH_MACTSCR_TSCTRLSSR ETH_MACTSCR_TSCTRLSSR_Msk /* Timestamp Digital or Binary Rollover Control */
7968 #define ETH_MACTSCR_TSENALL_Pos (8U)
7969 #define ETH_MACTSCR_TSENALL_Msk (0x1UL << ETH_MACTSCR_TSENALL_Pos) /*!< 0x00000100 */
7970 #define ETH_MACTSCR_TSENALL ETH_MACTSCR_TSENALL_Msk /* Enable Timestamp for All Packets */
7971 #define ETH_MACTSCR_TSADDREG_Pos (5U)
7972 #define ETH_MACTSCR_TSADDREG_Msk (0x1UL << ETH_MACTSCR_TSADDREG_Pos) /*!< 0x00000020 */
7973 #define ETH_MACTSCR_TSADDREG ETH_MACTSCR_TSADDREG_Msk /* Update Addend Register */
7974 #define ETH_MACTSCR_TSUPDT_Pos (3U)
7975 #define ETH_MACTSCR_TSUPDT_Msk (0x1UL << ETH_MACTSCR_TSUPDT_Pos) /*!< 0x00000008 */
7976 #define ETH_MACTSCR_TSUPDT ETH_MACTSCR_TSUPDT_Msk /* Update Timestamp */
7977 #define ETH_MACTSCR_TSINIT_Pos (2U)
7978 #define ETH_MACTSCR_TSINIT_Msk (0x1UL << ETH_MACTSCR_TSINIT_Pos) /*!< 0x00000004 */
7979 #define ETH_MACTSCR_TSINIT ETH_MACTSCR_TSINIT_Msk /* Initialize Timestamp */
7980 #define ETH_MACTSCR_TSCFUPDT_Pos (1U)
7981 #define ETH_MACTSCR_TSCFUPDT_Msk (0x1UL << ETH_MACTSCR_TSCFUPDT_Pos) /*!< 0x00000002 */
7982 #define ETH_MACTSCR_TSCFUPDT ETH_MACTSCR_TSCFUPDT_Msk /* Fine or Coarse Timestamp Update*/
7983 #define ETH_MACTSCR_TSENA_Pos (0U)
7984 #define ETH_MACTSCR_TSENA_Msk (0x1UL << ETH_MACTSCR_TSENA_Pos) /*!< 0x00000001 */
7985 #define ETH_MACTSCR_TSENA ETH_MACTSCR_TSENA_Msk /* Enable Timestamp */
7986
7987 /* Bit definition for Ethernet MAC Sub-second Increment Register */
7988 #define ETH_MACMACSSIR_SSINC_Pos (16U)
7989 #define ETH_MACMACSSIR_SSINC_Msk (0xFFUL << ETH_MACMACSSIR_SSINC_Pos) /*!< 0x0000FF00 */
7990 #define ETH_MACMACSSIR_SSINC ETH_MACMACSSIR_SSINC_Msk /* Sub-second Increment Value */
7991 #define ETH_MACMACSSIR_SNSINC_Pos (8U)
7992 #define ETH_MACMACSSIR_SNSINC_Msk (0xFFUL << ETH_MACMACSSIR_SNSINC_Pos) /*!< 0x000000FF */
7993 #define ETH_MACMACSSIR_SNSINC ETH_MACMACSSIR_SNSINC_Msk /* Sub-nanosecond Increment Value */
7994
7995 /* Bit definition for Ethernet MAC System Time Seconds Register */
7996 #define ETH_MACSTSR_TSS_Pos (0U)
7997 #define ETH_MACSTSR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSR_TSS_Pos) /*!< 0xFFFFFFFF */
7998 #define ETH_MACSTSR_TSS ETH_MACSTSR_TSS_Msk /* Timestamp Second */
7999
8000 /* Bit definition for Ethernet MAC System Time Nanoseconds Register */
8001 #define ETH_MACSTNR_TSSS_Pos (0U)
8002 #define ETH_MACSTNR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNR_TSSS_Pos) /*!< 0x7FFFFFFF */
8003 #define ETH_MACSTNR_TSSS ETH_MACSTNR_TSSS_Msk /* Timestamp Sub-seconds */
8004
8005 /* Bit definition for Ethernet MAC System Time Seconds Update Register */
8006 #define ETH_MACSTSUR_TSS_Pos (0U)
8007 #define ETH_MACSTSUR_TSS_Msk (0xFFFFFFFFUL << ETH_MACSTSUR_TSS_Pos) /*!< 0xFFFFFFFF */
8008 #define ETH_MACSTSUR_TSS ETH_MACSTSUR_TSS_Msk /* Timestamp Seconds */
8009
8010 /* Bit definition for Ethernet MAC System Time Nanoseconds Update Register */
8011 #define ETH_MACSTNUR_ADDSUB_Pos (31U)
8012 #define ETH_MACSTNUR_ADDSUB_Msk (0x1UL << ETH_MACSTNUR_ADDSUB_Pos) /*!< 0x80000000 */
8013 #define ETH_MACSTNUR_ADDSUB ETH_MACSTNUR_ADDSUB_Msk /* Add or Subtract Time */
8014 #define ETH_MACSTNUR_TSSS_Pos (0U)
8015 #define ETH_MACSTNUR_TSSS_Msk (0x7FFFFFFFUL << ETH_MACSTNUR_TSSS_Pos) /*!< 0x7FFFFFFF */
8016 #define ETH_MACSTNUR_TSSS ETH_MACSTNUR_TSSS_Msk /* Timestamp Sub-seconds */
8017
8018 /* Bit definition for Ethernet MAC Timestamp Addend Register */
8019 #define ETH_MACTSAR_TSAR_Pos (0U)
8020 #define ETH_MACTSAR_TSAR_Msk (0xFFFFFFFFUL << ETH_MACTSAR_TSAR_Pos) /*!< 0xFFFFFFFF */
8021 #define ETH_MACTSAR_TSAR ETH_MACTSAR_TSAR_Msk /* Timestamp Addend Register */
8022
8023 /* Bit definition for Ethernet MAC Timestamp Status Register */
8024 #define ETH_MACTSSR_ATSNS_Pos (25U)
8025 #define ETH_MACTSSR_ATSNS_Msk (0x1FUL << ETH_MACTSSR_ATSNS_Pos) /*!< 0x3E000000 */
8026 #define ETH_MACTSSR_ATSNS ETH_MACTSSR_ATSNS_Msk /* Number of Auxiliary Timestamp Snapshots */
8027 #define ETH_MACTSSR_ATSSTM_Pos (24U)
8028 #define ETH_MACTSSR_ATSSTM_Msk (0x1UL << ETH_MACTSSR_ATSSTM_Pos) /*!< 0x01000000 */
8029 #define ETH_MACTSSR_ATSSTM ETH_MACTSSR_ATSSTM_Msk /* Auxiliary Timestamp Snapshot Trigger Missed */
8030 #define ETH_MACTSSR_ATSSTN_Pos (16U)
8031 #define ETH_MACTSSR_ATSSTN_Msk (0xFUL << ETH_MACTSSR_ATSSTN_Pos) /*!< 0x000F0000 */
8032 #define ETH_MACTSSR_ATSSTN ETH_MACTSSR_ATSSTN_Msk /* Auxiliary Timestamp Snapshot Trigger Identifier */
8033 #define ETH_MACTSSR_TXTSSIS_Pos (15U)
8034 #define ETH_MACTSSR_TXTSSIS_Msk (0x1UL << ETH_MACTSSR_TXTSSIS_Pos) /*!< 0x00008000 */
8035 #define ETH_MACTSSR_TXTSSIS ETH_MACTSSR_TXTSSIS_Msk /* Tx Timestamp Status Interrupt Status */
8036 #define ETH_MACTSSR_TSTRGTERR0_Pos (3U)
8037 #define ETH_MACTSSR_TSTRGTERR0_Msk (0x1UL << ETH_MACTSSR_TSTRGTERR0_Pos) /*!< 0x00000008 */
8038 #define ETH_MACTSSR_TSTRGTERR0 ETH_MACTSSR_TSTRGTERR0_Msk /* Timestamp Target Time Error */
8039 #define ETH_MACTSSR_AUXTSTRIG_Pos (2U)
8040 #define ETH_MACTSSR_AUXTSTRIG_Msk (0x1UL << ETH_MACTSSR_AUXTSTRIG_Pos) /*!< 0x00000004 */
8041 #define ETH_MACTSSR_AUXTSTRIG ETH_MACTSSR_AUXTSTRIG_Msk /* Auxiliary Timestamp Trigger Snapshot*/
8042 #define ETH_MACTSSR_TSTARGT0_Pos (1U)
8043 #define ETH_MACTSSR_TSTARGT0_Msk (0x1UL << ETH_MACTSSR_TSTARGT0_Pos) /*!< 0x00000002 */
8044 #define ETH_MACTSSR_TSTARGT0 ETH_MACTSSR_TSTARGT0_Msk /* Timestamp Target Time Reached */
8045 #define ETH_MACTSSR_TSSOVF_Pos (0U)
8046 #define ETH_MACTSSR_TSSOVF_Msk (0x1UL << ETH_MACTSSR_TSSOVF_Pos) /*!< 0x00000001 */
8047 #define ETH_MACTSSR_TSSOVF ETH_MACTSSR_TSSOVF_Msk /* Timestamp Seconds Overflow */
8048
8049 /* Bit definition for Ethernet MAC Tx Timestamp Status Nanoseconds Register */
8050 #define ETH_MACTTSSNR_TXTSSMIS_Pos (31U)
8051 #define ETH_MACTTSSNR_TXTSSMIS_Msk (0x1UL << ETH_MACTTSSNR_TXTSSMIS_Pos) /*!< 0x80000000 */
8052 #define ETH_MACTTSSNR_TXTSSMIS ETH_MACTTSSNR_TXTSSMIS_Msk /* Transmit Timestamp Status Missed */
8053 #define ETH_MACTTSSNR_TXTSSLO_Pos (0U)
8054 #define ETH_MACTTSSNR_TXTSSLO_Msk (0x7FFFFFFFUL << ETH_MACTTSSNR_TXTSSLO_Pos) /*!< 0x7FFFFFFF */
8055 #define ETH_MACTTSSNR_TXTSSLO ETH_MACTTSSNR_TXTSSLO_Msk /* Transmit Timestamp Status Low */
8056
8057 /* Bit definition for Ethernet MAC Tx Timestamp Status Seconds Register */
8058 #define ETH_MACTTSSSR_TXTSSHI_Pos (0U)
8059 #define ETH_MACTTSSSR_TXTSSHI_Msk (0xFFFFFFFFUL << ETH_MACTTSSSR_TXTSSHI_Pos) /*!< 0xFFFFFFFF */
8060 #define ETH_MACTTSSSR_TXTSSHI ETH_MACTTSSSR_TXTSSHI_Msk /* Transmit Timestamp Status High */
8061
8062 /* Bit definition for Ethernet MAC Auxiliary Control Register*/
8063 #define ETH_MACACR_ATSEN3_Pos (7U)
8064 #define ETH_MACACR_ATSEN3_Msk (0x1UL << ETH_MACACR_ATSEN3_Pos) /*!< 0x00000080 */
8065 #define ETH_MACACR_ATSEN3 ETH_MACACR_ATSEN3_Msk /* Auxiliary Snapshot 3 Enable */
8066 #define ETH_MACACR_ATSEN2_Pos (6U)
8067 #define ETH_MACACR_ATSEN2_Msk (0x1UL << ETH_MACACR_ATSEN2_Pos) /*!< 0x00000040 */
8068 #define ETH_MACACR_ATSEN2 ETH_MACACR_ATSEN2_Msk /* Auxiliary Snapshot 2 Enable */
8069 #define ETH_MACACR_ATSEN1_Pos (5U)
8070 #define ETH_MACACR_ATSEN1_Msk (0x1UL << ETH_MACACR_ATSEN1_Pos) /*!< 0x00000020 */
8071 #define ETH_MACACR_ATSEN1 ETH_MACACR_ATSEN1_Msk /* Auxiliary Snapshot 1 Enable */
8072 #define ETH_MACACR_ATSEN0_Pos (4U)
8073 #define ETH_MACACR_ATSEN0_Msk (0x1UL << ETH_MACACR_ATSEN0_Pos) /*!< 0x00000010 */
8074 #define ETH_MACACR_ATSEN0 ETH_MACACR_ATSEN0_Msk /* Auxiliary Snapshot 0 Enable */
8075 #define ETH_MACACR_ATSFC_Pos (0U)
8076 #define ETH_MACACR_ATSFC_Msk (0x1UL << ETH_MACACR_ATSFC_Pos) /*!< 0x00000001 */
8077 #define ETH_MACACR_ATSFC ETH_MACACR_ATSFC_Msk /* Auxiliary Snapshot FIFO Clear */
8078
8079 /* Bit definition for Ethernet MAC Auxiliary Timestamp Nanoseconds Register */
8080 #define ETH_MACATSNR_AUXTSLO_Pos (0U)
8081 #define ETH_MACATSNR_AUXTSLO_Msk (0x7FFFFFFFUL << ETH_MACATSNR_AUXTSLO_Pos) /*!< 0x7FFFFFFF */
8082 #define ETH_MACATSNR_AUXTSLO ETH_MACATSNR_AUXTSLO_Msk /* Auxiliary Timestamp */
8083
8084 /* Bit definition for Ethernet MAC Auxiliary Timestamp Seconds Register */
8085 #define ETH_MACATSSR_AUXTSHI_Pos (0U)
8086 #define ETH_MACATSSR_AUXTSHI_Msk (0xFFFFFFFFUL << ETH_MACATSSR_AUXTSHI_Pos) /*!< 0xFFFFFFFF */
8087 #define ETH_MACATSSR_AUXTSHI ETH_MACATSSR_AUXTSHI_Msk /* Auxiliary Timestamp */
8088
8089 /* Bit definition for Ethernet MAC Timestamp Ingress Asymmetric Correction Register */
8090 #define ETH_MACTSIACR_OSTIAC_Pos (0U)
8091 #define ETH_MACTSIACR_OSTIAC_Msk (0xFFFFFFFFUL << ETH_MACTSIACR_OSTIAC_Pos) /*!< 0xFFFFFFFF */
8092 #define ETH_MACTSIACR_OSTIAC ETH_MACTSIACR_OSTIAC_Msk /* One-Step Timestamp Ingress Asymmetry Correction */
8093
8094 /* Bit definition for Ethernet MAC Timestamp Egress Asymmetric Correction Register */
8095 #define ETH_MACTSEACR_OSTEAC_Pos (0U)
8096 #define ETH_MACTSEACR_OSTEAC_Msk (0xFFFFFFFFUL << ETH_MACTSEACR_OSTEAC_Pos) /*!< 0xFFFFFFFF */
8097 #define ETH_MACTSEACR_OSTEAC ETH_MACTSEACR_OSTEAC_Msk /* One-Step Timestamp Egress Asymmetry Correction */
8098
8099 /* Bit definition for Ethernet MAC Timestamp Ingress Correction Nanosecond Register */
8100 #define ETH_MACTSICNR_TSIC_Pos (0U)
8101 #define ETH_MACTSICNR_TSIC_Msk (0xFFFFFFFFUL << ETH_MACTSICNR_TSIC_Pos) /*!< 0xFFFFFFFF */
8102 #define ETH_MACTSICNR_TSIC ETH_MACTSICNR_TSIC_Msk /* Timestamp Ingress Correction */
8103
8104 /* Bit definition for Ethernet MAC Timestamp Egress correction Nanosecond Register */
8105 #define ETH_MACTSECNR_TSEC_Pos (0U)
8106 #define ETH_MACTSECNR_TSEC_Msk (0xFFFFFFFFUL << ETH_MACTSECNR_TSEC_Pos) /*!< 0xFFFFFFFF */
8107 #define ETH_MACTSECNR_TSEC ETH_MACTSECNR_TSEC_Msk /* Timestamp Egress Correction */
8108
8109 /* Bit definition for Ethernet MAC PPS Control Register */
8110 #define ETH_MACPPSCR_TRGTMODSEL0_Pos (5U)
8111 #define ETH_MACPPSCR_TRGTMODSEL0_Msk (0x3UL << ETH_MACPPSCR_TRGTMODSEL0_Pos) /*!< 0x00000060 */
8112 #define ETH_MACPPSCR_TRGTMODSEL0 ETH_MACPPSCR_TRGTMODSEL0_Msk /* Target Time Register Mode for PPS Output */
8113 #define ETH_MACPPSCR_PPSEN0_Pos (4U)
8114 #define ETH_MACPPSCR_PPSEN0_Msk (0x1UL << ETH_MACPPSCR_PPSEN0_Pos) /*!< 0x00000010 */
8115 #define ETH_MACPPSCR_PPSEN0 ETH_MACPPSCR_PPSEN0_Msk /* Flexible PPS Output Mode Enable */
8116 #define ETH_MACPPSCR_PPSCTRL_Pos (0U)
8117 #define ETH_MACPPSCR_PPSCTRL_Msk (0xFUL << ETH_MACPPSCR_PPSCTRL_Pos) /*!< 0x0000000F */
8118 #define ETH_MACPPSCR_PPSCTRL ETH_MACPPSCR_PPSCTRL_Msk /* PPS Output Frequency Control */
8119
8120 /* Bit definition for Ethernet MAC PPS Target Time Seconds Register */
8121 #define ETH_MACPPSTTSR_TSTRH0_Pos (0U)
8122 #define ETH_MACPPSTTSR_TSTRH0_Msk (0xFFFFFFFFUL << ETH_MACPPSTTSR_TSTRH0_Pos) /*!< 0xFFFFFFFF */
8123 #define ETH_MACPPSTTSR_TSTRH0 ETH_MACPPSTTSR_TSTRH0_Msk /* PPS Target Time Seconds Register */
8124
8125 /* Bit definition for Ethernet MAC PPS Target Time Nanoseconds Register */
8126 #define ETH_MACPPSTTNR_TRGTBUSY0_Pos (31U)
8127 #define ETH_MACPPSTTNR_TRGTBUSY0_Msk (0x1UL << ETH_MACPPSTTNR_TRGTBUSY0_Pos) /*!< 0x80000000 */
8128 #define ETH_MACPPSTTNR_TRGTBUSY0 ETH_MACPPSTTNR_TRGTBUSY0_Msk /* PPS Target Time Register Busy */
8129 #define ETH_MACPPSTTNR_TTSL0_Pos (0U)
8130 #define ETH_MACPPSTTNR_TTSL0_Msk (0x7FFFFFFFUL << ETH_MACPPSTTNR_TTSL0_Pos) /*!< 0x7FFFFFFF */
8131 #define ETH_MACPPSTTNR_TTSL0 ETH_MACPPSTTNR_TTSL0_Msk /* Target Time Low for PPS Register */
8132
8133 /* Bit definition for Ethernet MAC PPS Interval Register */
8134 #define ETH_MACPPSIR_PPSINT0_Pos (0U)
8135 #define ETH_MACPPSIR_PPSINT0_Msk (0xFFFFFFFFUL << ETH_MACPPSIR_PPSINT0_Pos) /*!< 0xFFFFFFFF */
8136 #define ETH_MACPPSIR_PPSINT0 ETH_MACPPSIR_PPSINT0_Msk /* PPS Output Signal Interval */
8137
8138 /* Bit definition for Ethernet MAC PPS Width Register */
8139 #define ETH_MACPPSWR_PPSWIDTH0_Pos (0U)
8140 #define ETH_MACPPSWR_PPSWIDTH0_Msk (0xFFFFFFFFUL << ETH_MACPPSWR_PPSWIDTH0_Pos) /*!< 0xFFFFFFFF */
8141 #define ETH_MACPPSWR_PPSWIDTH0 ETH_MACPPSWR_PPSWIDTH0_Msk /* PPS Output Signal Width */
8142
8143 /* Bit definition for Ethernet MAC PTP Offload Control Register */
8144 #define ETH_MACPOCR_DN_Pos (8U)
8145 #define ETH_MACPOCR_DN_Msk (0xFFUL << ETH_MACPOCR_DN_Pos) /*!< 0x0000FF00 */
8146 #define ETH_MACPOCR_DN ETH_MACPOCR_DN_Msk /* Domain Number */
8147 #define ETH_MACPOCR_DRRDIS_Pos (6U)
8148 #define ETH_MACPOCR_DRRDIS_Msk (0x1UL << ETH_MACPOCR_DRRDIS_Pos) /*!< 0x00000040 */
8149 #define ETH_MACPOCR_DRRDIS ETH_MACPOCR_DRRDIS_Msk /* Disable PTO Delay Request/Response response generation */
8150 #define ETH_MACPOCR_APDREQTRIG_Pos (5U)
8151 #define ETH_MACPOCR_APDREQTRIG_Msk (0x1UL << ETH_MACPOCR_APDREQTRIG_Pos) /*!< 0x00000020 */
8152 #define ETH_MACPOCR_APDREQTRIG ETH_MACPOCR_APDREQTRIG_Msk /* Automatic PTP Pdelay_Req message Trigger */
8153 #define ETH_MACPOCR_ASYNCTRIG_Pos (4U)
8154 #define ETH_MACPOCR_ASYNCTRIG_Msk (0x1UL << ETH_MACPOCR_ASYNCTRIG_Pos) /*!< 0x00000010 */
8155 #define ETH_MACPOCR_ASYNCTRIG ETH_MACPOCR_ASYNCTRIG_Msk /* Automatic PTP SYNC message Trigger */
8156 #define ETH_MACPOCR_APDREQEN_Pos (2U)
8157 #define ETH_MACPOCR_APDREQEN_Msk (0x1UL << ETH_MACPOCR_APDREQEN_Pos) /*!< 0x00000004 */
8158 #define ETH_MACPOCR_APDREQEN ETH_MACPOCR_APDREQEN_Msk /* Automatic PTP Pdelay_Req message Enable */
8159 #define ETH_MACPOCR_ASYNCEN_Pos (1U)
8160 #define ETH_MACPOCR_ASYNCEN_Msk (0x1UL << ETH_MACPOCR_ASYNCEN_Pos) /*!< 0x00000002 */
8161 #define ETH_MACPOCR_ASYNCEN ETH_MACPOCR_ASYNCEN_Msk /* Automatic PTP SYNC message Enable */
8162 #define ETH_MACPOCR_PTOEN_Pos (0U)
8163 #define ETH_MACPOCR_PTOEN_Msk (0x1UL << ETH_MACPOCR_PTOEN_Pos) /*!< 0x00000001 */
8164 #define ETH_MACPOCR_PTOEN ETH_MACPOCR_PTOEN_Msk /* PTP Offload Enable */
8165
8166 /* Bit definition for Ethernet MAC PTP Source Port Identity 0 Register */
8167 #define ETH_MACSPI0R_SPI0_Pos (0U)
8168 #define ETH_MACSPI0R_SPI0_Msk (0xFFFFFFFFUL << ETH_MACSPI0R_SPI0_Pos) /*!< 0xFFFFFFFF */
8169 #define ETH_MACSPI0R_SPI0 ETH_MACSPI0R_SPI0_Msk /* Source Port Identity 0 */
8170
8171 /* Bit definition for Ethernet MAC PTP Source Port Identity 1 Register */
8172 #define ETH_MACSPI1R_SPI1_Pos (0U)
8173 #define ETH_MACSPI1R_SPI1_Msk (0xFFFFFFFFUL << ETH_MACSPI1R_SPI1_Pos) /*!< 0xFFFFFFFF */
8174 #define ETH_MACSPI1R_SPI1 ETH_MACSPI1R_SPI1_Msk /* Source Port Identity 1 */
8175
8176 /* Bit definition for Ethernet MAC PTP Source Port Identity 2 Register */
8177 #define ETH_MACSPI2R_SPI2_Pos (0U)
8178 #define ETH_MACSPI2R_SPI2_Msk (0xFFFFUL << ETH_MACSPI2R_SPI2_Pos) /*!< 0x0000FFFF */
8179 #define ETH_MACSPI2R_SPI2 ETH_MACSPI2R_SPI2_Msk /* Source Port Identity 2 */
8180
8181 /* Bit definition for Ethernet MAC Log Message Interval Register */
8182 #define ETH_MACLMIR_LMPDRI_Pos (24U)
8183 #define ETH_MACLMIR_LMPDRI_Msk (0xFFUL << ETH_MACLMIR_LMPDRI_Pos) /*!< 0xFF000000 */
8184 #define ETH_MACLMIR_LMPDRI ETH_MACLMIR_LMPDRI_Msk /* Log Min Pdelay_Req Interval */
8185 #define ETH_MACLMIR_DRSYNCR_Pos (8U)
8186 #define ETH_MACLMIR_DRSYNCR_Msk (0x7UL << ETH_MACLMIR_DRSYNCR_Pos) /*!< 0x00000700 */
8187 #define ETH_MACLMIR_DRSYNCR ETH_MACLMIR_DRSYNCR_Msk /* Delay_Req to SYNC Ratio */
8188 #define ETH_MACLMIR_LSI_Pos (0U)
8189 #define ETH_MACLMIR_LSI_Msk (0xFFUL << ETH_MACLMIR_LSI_Pos) /*!< 0x000000FF */
8190 #define ETH_MACLMIR_LSI ETH_MACLMIR_LSI_Msk /* Log Sync Interval */
8191
8192 /* Bit definition for Ethernet MTL Operation Mode Register */
8193 #define ETH_MTLOMR_CNTCLR_Pos (9U)
8194 #define ETH_MTLOMR_CNTCLR_Msk (0x1UL << ETH_MTLOMR_CNTCLR_Pos) /*!< 0x00000200 */
8195 #define ETH_MTLOMR_CNTCLR ETH_MTLOMR_CNTCLR_Msk /* Counters Reset */
8196 #define ETH_MTLOMR_CNTPRST_Pos (8U)
8197 #define ETH_MTLOMR_CNTPRST_Msk (0x1UL << ETH_MTLOMR_CNTPRST_Pos) /*!< 0x00000100 */
8198 #define ETH_MTLOMR_CNTPRST ETH_MTLOMR_CNTPRST_Msk /* Counters Preset */
8199 #define ETH_MTLOMR_DTXSTS_Pos (1U)
8200 #define ETH_MTLOMR_DTXSTS_Msk (0x1UL << ETH_MTLOMR_DTXSTS_Pos) /*!< 0x00000002 */
8201 #define ETH_MTLOMR_DTXSTS ETH_MTLOMR_DTXSTS_Msk /* Drop Transmit Status */
8202
8203 /* Bit definition for Ethernet MTL Interrupt Status Register */
8204 #define ETH_MTLISR_MACIS_Pos (16U)
8205 #define ETH_MTLISR_MACIS_Msk (0x1UL << ETH_MTLISR_MACIS_Pos) /*!< 0x00010000 */
8206 #define ETH_MTLISR_MACIS ETH_MTLISR_MACIS_Msk /* MAC Interrupt Status */
8207 #define ETH_MTLISR_QIS_Pos (0U)
8208 #define ETH_MTLISR_QIS_Msk (0x1UL << ETH_MTLISR_QIS_Pos) /*!< 0x00000001 */
8209 #define ETH_MTLISR_QIS ETH_MTLISR_QIS_Msk /* Queue Interrupt status */
8210
8211 /* Bit definition for Ethernet MTL Tx Queue Operation Mode Register */
8212 #define ETH_MTLTQOMR_TTC_Pos (4U)
8213 #define ETH_MTLTQOMR_TTC_Msk (0x7UL << ETH_MTLTQOMR_TTC_Pos) /*!< 0x00000070 */
8214 #define ETH_MTLTQOMR_TTC ETH_MTLTQOMR_TTC_Msk /* Transmit Threshold Control */
8215 #define ETH_MTLTQOMR_TTC_32BITS ((uint32_t)0x00000000) /* 32 bits Threshold */
8216 #define ETH_MTLTQOMR_TTC_64BITS ((uint32_t)0x00000010) /* 64 bits Threshold */
8217 #define ETH_MTLTQOMR_TTC_96BITS ((uint32_t)0x00000020) /* 96 bits Threshold */
8218 #define ETH_MTLTQOMR_TTC_128BITS ((uint32_t)0x00000030) /* 128 bits Threshold */
8219 #define ETH_MTLTQOMR_TTC_192BITS ((uint32_t)0x00000040) /* 192 bits Threshold */
8220 #define ETH_MTLTQOMR_TTC_256BITS ((uint32_t)0x00000050) /* 256 bits Threshold */
8221 #define ETH_MTLTQOMR_TTC_384BITS ((uint32_t)0x00000060) /* 384 bits Threshold */
8222 #define ETH_MTLTQOMR_TTC_512BITS ((uint32_t)0x00000070) /* 512 bits Threshold */
8223 #define ETH_MTLTQOMR_TSF_Pos (1U)
8224 #define ETH_MTLTQOMR_TSF_Msk (0x1UL << ETH_MTLTQOMR_TSF_Pos) /*!< 0x00000002 */
8225 #define ETH_MTLTQOMR_TSF ETH_MTLTQOMR_TSF_Msk /* Transmit Store and Forward */
8226 #define ETH_MTLTQOMR_FTQ_Pos (0U)
8227 #define ETH_MTLTQOMR_FTQ_Msk (0x1UL << ETH_MTLTQOMR_FTQ_Pos) /*!< 0x00000001 */
8228 #define ETH_MTLTQOMR_FTQ ETH_MTLTQOMR_FTQ_Msk /* Flush Transmit Queue */
8229
8230 /* Bit definition for Ethernet MTL Tx Queue Underflow Register */
8231 #define ETH_MTLTQUR_UFCNTOVF_Pos (11U)
8232 #define ETH_MTLTQUR_UFCNTOVF_Msk (0x1UL << ETH_MTLTQUR_UFCNTOVF_Pos) /*!< 0x00000800 */
8233 #define ETH_MTLTQUR_UFCNTOVF ETH_MTLTQUR_UFCNTOVF_Msk /* Overflow Bit for Underflow Packet Counter */
8234 #define ETH_MTLTQUR_UFPKTCNT_Pos (0U)
8235 #define ETH_MTLTQUR_UFPKTCNT_Msk (0x7FFUL << ETH_MTLTQUR_UFPKTCNT_Pos) /*!< 0x000007FF */
8236 #define ETH_MTLTQUR_UFPKTCNT ETH_MTLTQUR_UFPKTCNT_Msk /* Underflow Packet Counter */
8237
8238 /* Bit definition for Ethernet MTL Tx Queue Debug Register */
8239 #define ETH_MTLTQDR_STXSTSF_Pos (20U)
8240 #define ETH_MTLTQDR_STXSTSF_Msk (0x7UL << ETH_MTLTQDR_STXSTSF_Pos) /*!< 0x00700000 */
8241 #define ETH_MTLTQDR_STXSTSF ETH_MTLTQDR_STXSTSF_Msk /* Number of Status Words in the Tx Status FIFO of Queue */
8242 #define ETH_MTLTQDR_PTXQ_Pos (16U)
8243 #define ETH_MTLTQDR_PTXQ_Msk (0x7UL << ETH_MTLTQDR_PTXQ_Pos) /*!< 0x00070000 */
8244 #define ETH_MTLTQDR_PTXQ ETH_MTLTQDR_PTXQ_Msk /* Number of Packets in the Transmit Queue */
8245 #define ETH_MTLTQDR_TXSTSFSTS_Pos (5U)
8246 #define ETH_MTLTQDR_TXSTSFSTS_Msk (0x1UL << ETH_MTLTQDR_TXSTSFSTS_Pos) /*!< 0x00000020 */
8247 #define ETH_MTLTQDR_TXSTSFSTS ETH_MTLTQDR_TXSTSFSTS_Msk /* MTL Tx Status FIFO Full Status */
8248 #define ETH_MTLTQDR_TXQSTS_Pos (4U)
8249 #define ETH_MTLTQDR_TXQSTS_Msk (0x1UL << ETH_MTLTQDR_TXQSTS_Pos) /*!< 0x00000010 */
8250 #define ETH_MTLTQDR_TXQSTS ETH_MTLTQDR_TXQSTS_Msk /* MTL Tx Queue Not Empty Status */
8251 #define ETH_MTLTQDR_TWCSTS_Pos (3U)
8252 #define ETH_MTLTQDR_TWCSTS_Msk (0x1UL << ETH_MTLTQDR_TWCSTS_Pos) /*!< 0x00000008 */
8253 #define ETH_MTLTQDR_TWCSTS ETH_MTLTQDR_TWCSTS_Msk /* MTL Tx Queue Write Controller Status */
8254 #define ETH_MTLTQDR_TRCSTS_Pos (1U)
8255 #define ETH_MTLTQDR_TRCSTS_Msk (0x3UL << ETH_MTLTQDR_TRCSTS_Pos) /*!< 0x00000006 */
8256 #define ETH_MTLTQDR_TRCSTS ETH_MTLTQDR_TRCSTS_Msk /* MTL Tx Queue Read Controller Status */
8257 #define ETH_MTLTQDR_TRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8258 #define ETH_MTLTQDR_TRCSTS_READ ((uint32_t)0x00000002) /* Read state (transferring data to the MAC transmitter) */
8259 #define ETH_MTLTQDR_TRCSTS_WAITING ((uint32_t)0x00000004) /* Waiting for pending Tx Status from the MAC transmitter */
8260 #define ETH_MTLTQDR_TRCSTS_FLUSHING ((uint32_t)0x00000006) /* Flushing the Tx queue because of the Packet Abort request from the MAC */
8261 #define ETH_MTLTQDR_TXQPAUSED_Pos (0U)
8262 #define ETH_MTLTQDR_TXQPAUSED_Msk (0x1UL << ETH_MTLTQDR_TXQPAUSED_Pos) /*!< 0x00000001 */
8263 #define ETH_MTLTQDR_TXQPAUSED ETH_MTLTQDR_TXQPAUSED_Msk /* Transmit Queue in Pause */
8264
8265 /* Bit definition for Ethernet MTL Queue Interrupt Control Status Register */
8266 #define ETH_MTLQICSR_RXOIE_Pos (24U)
8267 #define ETH_MTLQICSR_RXOIE_Msk (0x1UL << ETH_MTLQICSR_RXOIE_Pos) /*!< 0x01000000 */
8268 #define ETH_MTLQICSR_RXOIE ETH_MTLQICSR_RXOIE_Msk /* Receive Queue Overflow Interrupt Enable */
8269 #define ETH_MTLQICSR_RXOVFIS_Pos (16U)
8270 #define ETH_MTLQICSR_RXOVFIS_Msk (0x1UL << ETH_MTLQICSR_RXOVFIS_Pos) /*!< 0x00010000 */
8271 #define ETH_MTLQICSR_RXOVFIS ETH_MTLQICSR_RXOVFIS_Msk /* Receive Queue Overflow Interrupt Status */
8272 #define ETH_MTLQICSR_TXUIE_Pos (8U)
8273 #define ETH_MTLQICSR_TXUIE_Msk (0x1UL << ETH_MTLQICSR_TXUIE_Pos) /*!< 0x00000100 */
8274 #define ETH_MTLQICSR_TXUIE ETH_MTLQICSR_TXUIE_Msk /* Transmit Queue Underflow Interrupt Enable */
8275 #define ETH_MTLQICSR_TXUNFIS_Pos (0U)
8276 #define ETH_MTLQICSR_TXUNFIS_Msk (0x1UL << ETH_MTLQICSR_TXUNFIS_Pos) /*!< 0x00000001 */
8277 #define ETH_MTLQICSR_TXUNFIS ETH_MTLQICSR_TXUNFIS_Msk /* Transmit Queue Underflow Interrupt Status */
8278
8279 /* Bit definition for Ethernet MTL Rx Queue Operation Mode Register */
8280 #define ETH_MTLRQOMR_RQS_Pos (20U)
8281 #define ETH_MTLRQOMR_RQS_Msk (0x7UL << ETH_MTLRQOMR_RQS_Pos) /*!< 0x00700000 */
8282 #define ETH_MTLRQOMR_RQS ETH_MTLRQOMR_RQS_Msk /* Receive Queue Size */
8283 #define ETH_MTLRQOMR_RFD_Pos (14U)
8284 #define ETH_MTLRQOMR_RFD_Msk (0x7UL << ETH_MTLRQOMR_RFD_Pos) /*!< 0x0001C000 */
8285 #define ETH_MTLRQOMR_RFD ETH_MTLRQOMR_RFD_Msk /* Threshold for Deactivating Flow Control (in half-duplex and full-duplex modes) */
8286 #define ETH_MTLRQOMR_RFA_Pos (8U)
8287 #define ETH_MTLRQOMR_RFA_Msk (0x7UL << ETH_MTLRQOMR_RFA_Pos) /*!< 0x00000700 */
8288 #define ETH_MTLRQOMR_RFA ETH_MTLRQOMR_RFA_Msk /* Threshold for Activating Flow Control (in half-duplex and full-duplex */
8289 #define ETH_MTLRQOMR_EHFC_Pos (7U)
8290 #define ETH_MTLRQOMR_EHFC_Msk (0x1UL << ETH_MTLRQOMR_EHFC_Pos) /*!< 0x00000080 */
8291 #define ETH_MTLRQOMR_EHFC ETH_MTLRQOMR_EHFC_Msk /* DEnable Hardware Flow Control */
8292 #define ETH_MTLRQOMR_DISTCPEF_Pos (6U)
8293 #define ETH_MTLRQOMR_DISTCPEF_Msk (0x1UL << ETH_MTLRQOMR_DISTCPEF_Pos) /*!< 0x00000040 */
8294 #define ETH_MTLRQOMR_DISTCPEF ETH_MTLRQOMR_DISTCPEF_Msk /* Disable Dropping of TCP/IP Checksum Error Packets */
8295 #define ETH_MTLRQOMR_RSF_Pos (5U)
8296 #define ETH_MTLRQOMR_RSF_Msk (0x1UL << ETH_MTLRQOMR_RSF_Pos) /*!< 0x00000020 */
8297 #define ETH_MTLRQOMR_RSF ETH_MTLRQOMR_RSF_Msk /* Receive Queue Store and Forward */
8298 #define ETH_MTLRQOMR_FEP_Pos (4U)
8299 #define ETH_MTLRQOMR_FEP_Msk (0x1UL << ETH_MTLRQOMR_FEP_Pos) /*!< 0x00000010 */
8300 #define ETH_MTLRQOMR_FEP ETH_MTLRQOMR_FEP_Msk /* Forward Error Packets */
8301 #define ETH_MTLRQOMR_FUP_Pos (3U)
8302 #define ETH_MTLRQOMR_FUP_Msk (0x1UL << ETH_MTLRQOMR_FUP_Pos) /*!< 0x00000008 */
8303 #define ETH_MTLRQOMR_FUP ETH_MTLRQOMR_FUP_Msk /* Forward Undersized Good Packets */
8304 #define ETH_MTLRQOMR_RTC_Pos (0U)
8305 #define ETH_MTLRQOMR_RTC_Msk (0x3UL << ETH_MTLRQOMR_RTC_Pos) /*!< 0x00000003 */
8306 #define ETH_MTLRQOMR_RTC ETH_MTLRQOMR_RTC_Msk /* Receive Queue Threshold Control */
8307 #define ETH_MTLRQOMR_RTC_64BITS ((uint32_t)0x00000000) /* 64 bits Threshold */
8308 #define ETH_MTLRQOMR_RTC_32BITS ((uint32_t)0x00000001) /* 32 bits Threshold */
8309 #define ETH_MTLRQOMR_RTC_96BITS ((uint32_t)0x00000002) /* 96 bits Threshold */
8310 #define ETH_MTLRQOMR_RTC_128BITS ((uint32_t)0x00000003) /* 128 bits Threshold */
8311
8312 /* Bit definition for Ethernet MTL Rx Queue Missed Packet Overflow Cnt Register */
8313 #define ETH_MTLRQMPOCR_MISCNTOVF_Pos (27U)
8314 #define ETH_MTLRQMPOCR_MISCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_MISCNTOVF_Pos) /*!< 0x08000000 */
8315 #define ETH_MTLRQMPOCR_MISCNTOVF ETH_MTLRQMPOCR_MISCNTOVF_Msk /* Missed Packet Counter Overflow Bit */
8316 #define ETH_MTLRQMPOCR_MISPKTCNT_Pos (16U)
8317 #define ETH_MTLRQMPOCR_MISPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_MISPKTCNT_Pos) /*!< 0x07FF0000 */
8318 #define ETH_MTLRQMPOCR_MISPKTCNT ETH_MTLRQMPOCR_MISPKTCNT_Msk /* Missed Packet Counter */
8319 #define ETH_MTLRQMPOCR_OVFCNTOVF_Pos (11U)
8320 #define ETH_MTLRQMPOCR_OVFCNTOVF_Msk (0x1UL << ETH_MTLRQMPOCR_OVFCNTOVF_Pos) /*!< 0x00000800 */
8321 #define ETH_MTLRQMPOCR_OVFCNTOVF ETH_MTLRQMPOCR_OVFCNTOVF_Msk /* Overflow Counter Overflow Bit */
8322 #define ETH_MTLRQMPOCR_OVFPKTCNT_Pos (0U)
8323 #define ETH_MTLRQMPOCR_OVFPKTCNT_Msk (0x7FFUL << ETH_MTLRQMPOCR_OVFPKTCNT_Pos) /*!< 0x000007FF */
8324 #define ETH_MTLRQMPOCR_OVFPKTCNT ETH_MTLRQMPOCR_OVFPKTCNT_Msk /* Overflow Packet Counter */
8325
8326 /* Bit definition for Ethernet MTL Rx Queue Debug Register */
8327 #define ETH_MTLRQDR_PRXQ_Pos (16U)
8328 #define ETH_MTLRQDR_PRXQ_Msk (0x3FFFUL << ETH_MTLRQDR_PRXQ_Pos) /*!< 0x3FFF0000 */
8329 #define ETH_MTLRQDR_PRXQ ETH_MTLRQDR_PRXQ_Msk /* Number of Packets in Receive Queue */
8330 #define ETH_MTLRQDR_RXQSTS_Pos (4U)
8331 #define ETH_MTLRQDR_RXQSTS_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_Pos) /*!< 0x00000030 */
8332 #define ETH_MTLRQDR_RXQSTS ETH_MTLRQDR_RXQSTS_Msk /* MTL Rx Queue Fill-Level Status */
8333 #define ETH_MTLRQDR_RXQSTS_EMPTY ((uint32_t)0x00000000) /* Rx Queue empty */
8334 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos (4U)
8335 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Pos) /*!< 0x00000010 */
8336 #define ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD ETH_MTLRQDR_RXQSTS_BELOWTHRESHOLD_Msk /* Rx Queue fill-level below flow-control deactivate threshold */
8337 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos (5U)
8338 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk (0x1UL << ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Pos) /*!< 0x00000020 */
8339 #define ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD ETH_MTLRQDR_RXQSTS_ABOVETHRESHOLD_Msk /* Rx Queue fill-level above flow-control activate threshold */
8340 #define ETH_MTLRQDR_RXQSTS_FULL_Pos (4U)
8341 #define ETH_MTLRQDR_RXQSTS_FULL_Msk (0x3UL << ETH_MTLRQDR_RXQSTS_FULL_Pos) /*!< 0x00000030 */
8342 #define ETH_MTLRQDR_RXQSTS_FULL ETH_MTLRQDR_RXQSTS_FULL_Msk /* Rx Queue full */
8343 #define ETH_MTLRQDR_RRCSTS_Pos (1U)
8344 #define ETH_MTLRQDR_RRCSTS_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_Pos) /*!< 0x00000006 */
8345 #define ETH_MTLRQDR_RRCSTS ETH_MTLRQDR_RRCSTS_Msk /* MTL Rx Queue Read Controller State */
8346 #define ETH_MTLRQDR_RRCSTS_IDLE ((uint32_t)0x00000000) /* Idle state */
8347 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Pos (1U)
8348 #define ETH_MTLRQDR_RRCSTS_READINGDATA_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGDATA_Pos) /*!< 0x00000002 */
8349 #define ETH_MTLRQDR_RRCSTS_READINGDATA ETH_MTLRQDR_RRCSTS_READINGDATA_Msk /* Reading packet data */
8350 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos (2U)
8351 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk (0x1UL << ETH_MTLRQDR_RRCSTS_READINGSTATUS_Pos) /*!< 0x00000004 */
8352 #define ETH_MTLRQDR_RRCSTS_READINGSTATUS ETH_MTLRQDR_RRCSTS_READINGSTATUS_Msk /* Reading packet status (or timestamp) */
8353 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Pos (1U)
8354 #define ETH_MTLRQDR_RRCSTS_FLUSHING_Msk (0x3UL << ETH_MTLRQDR_RRCSTS_FLUSHING_Pos) /*!< 0x00000006 */
8355 #define ETH_MTLRQDR_RRCSTS_FLUSHING ETH_MTLRQDR_RRCSTS_FLUSHING_Msk /* Flushing the packet data and status */
8356 #define ETH_MTLRQDR_RWCSTS_Pos (0U)
8357 #define ETH_MTLRQDR_RWCSTS_Msk (0x1UL << ETH_MTLRQDR_RWCSTS_Pos) /*!< 0x00000001 */
8358 #define ETH_MTLRQDR_RWCSTS ETH_MTLRQDR_RWCSTS_Msk /* MTL Rx Queue Write Controller Active Status */
8359
8360 /* Bit definition for Ethernet MTL Rx Queue Control Register */
8361 #define ETH_MTLRQCR_RQPA_Pos (3U)
8362 #define ETH_MTLRQCR_RQPA_Msk (0x1UL << ETH_MTLRQCR_RQPA_Pos) /*!< 0x00000008 */
8363 #define ETH_MTLRQCR_RQPA ETH_MTLRQCR_RQPA_Msk /* Receive Queue Packet Arbitration */
8364 #define ETH_MTLRQCR_RQW_Pos (0U)
8365 #define ETH_MTLRQCR_RQW_Msk (0x7UL << ETH_MTLRQCR_RQW_Pos) /*!< 0x00000007 */
8366 #define ETH_MTLRQCR_RQW ETH_MTLRQCR_RQW_Msk /* Receive Queue Weight */
8367
8368 /* Bit definition for Ethernet DMA Mode Register */
8369 #define ETH_DMAMR_INTM_Pos (16U)
8370 #define ETH_DMAMR_INTM_Msk (0x3UL << ETH_DMAMR_INTM_Pos) /*!< 0x00030000 */
8371 #define ETH_DMAMR_INTM ETH_DMAMR_INTM_Msk /* This field defines the interrupt mode */
8372 #define ETH_DMAMR_INTM_0 (0x0UL << ETH_DMAMR_INTM_Pos) /*!< 0x00000000 */
8373 #define ETH_DMAMR_INTM_1 (0x1UL << ETH_DMAMR_INTM_Pos) /*!< 0x00010000 */
8374 #define ETH_DMAMR_INTM_2 (0x2UL << ETH_DMAMR_INTM_Pos) /*!< 0x00020000 */
8375 #define ETH_DMAMR_PR_Pos (12U)
8376 #define ETH_DMAMR_PR_Msk (0x7UL << ETH_DMAMR_PR_Pos) /*!< 0x00007000 */
8377 #define ETH_DMAMR_PR ETH_DMAMR_PR_Msk /* Priority Ratio */
8378 #define ETH_DMAMR_PR_1_1 ((uint32_t)0x00000000) /* The priority ratio is 1:1 */
8379 #define ETH_DMAMR_PR_2_1 ((uint32_t)0x00001000) /* The priority ratio is 2:1 */
8380 #define ETH_DMAMR_PR_3_1 ((uint32_t)0x00002000) /* The priority ratio is 3:1 */
8381 #define ETH_DMAMR_PR_4_1 ((uint32_t)0x00003000) /* The priority ratio is 4:1 */
8382 #define ETH_DMAMR_PR_5_1 ((uint32_t)0x00004000) /* The priority ratio is 5:1 */
8383 #define ETH_DMAMR_PR_6_1 ((uint32_t)0x00005000) /* The priority ratio is 6:1 */
8384 #define ETH_DMAMR_PR_7_1 ((uint32_t)0x00006000) /* The priority ratio is 7:1 */
8385 #define ETH_DMAMR_PR_8_1 ((uint32_t)0x00007000) /* The priority ratio is 8:1 */
8386 #define ETH_DMAMR_TXPR_Pos (11U)
8387 #define ETH_DMAMR_TXPR_Msk (0x1UL << ETH_DMAMR_TXPR_Pos) /*!< 0x00000800 */
8388 #define ETH_DMAMR_TXPR ETH_DMAMR_TXPR_Msk /* Transmit Priority */
8389 #define ETH_DMAMR_DA_Pos (1U)
8390 #define ETH_DMAMR_DA_Msk (0x1UL << ETH_DMAMR_DA_Pos) /*!< 0x00000002 */
8391 #define ETH_DMAMR_DA ETH_DMAMR_DA_Msk /* DMA Tx or Rx Arbitration Scheme */
8392 #define ETH_DMAMR_SWR_Pos (0U)
8393 #define ETH_DMAMR_SWR_Msk (0x1UL << ETH_DMAMR_SWR_Pos) /*!< 0x00000001 */
8394 #define ETH_DMAMR_SWR ETH_DMAMR_SWR_Msk /* Software Reset */
8395
8396 /* Bit definition for Ethernet DMA SysBus Mode Register */
8397 #define ETH_DMASBMR_RB_Pos (15U)
8398 #define ETH_DMASBMR_RB_Msk (0x1UL << ETH_DMASBMR_RB_Pos) /*!< 0x00008000 */
8399 #define ETH_DMASBMR_RB ETH_DMASBMR_RB_Msk /* Rebuild INCRx Burst */
8400 #define ETH_DMASBMR_MB_Pos (14U)
8401 #define ETH_DMASBMR_MB_Msk (0x1UL << ETH_DMASBMR_MB_Pos) /*!< 0x00004000 */
8402 #define ETH_DMASBMR_MB ETH_DMASBMR_MB_Msk /* Mixed Burst */
8403 #define ETH_DMASBMR_AAL_Pos (12U)
8404 #define ETH_DMASBMR_AAL_Msk (0x1UL << ETH_DMASBMR_AAL_Pos) /*!< 0x00001000 */
8405 #define ETH_DMASBMR_AAL ETH_DMASBMR_AAL_Msk /* Address-Aligned Beats */
8406 #define ETH_DMASBMR_FB_Pos (0U)
8407 #define ETH_DMASBMR_FB_Msk (0x1UL << ETH_DMASBMR_FB_Pos) /*!< 0x00000001 */
8408 #define ETH_DMASBMR_FB ETH_DMASBMR_FB_Msk /* Fixed Burst Length */
8409
8410 /* Bit definition for Ethernet DMA Interrupt Status Register */
8411 #define ETH_DMAISR_MACIS_Pos (17U)
8412 #define ETH_DMAISR_MACIS_Msk (0x1UL << ETH_DMAISR_MACIS_Pos) /*!< 0x00020000 */
8413 #define ETH_DMAISR_MACIS ETH_DMAISR_MACIS_Msk /* MAC Interrupt Status */
8414 #define ETH_DMAISR_MTLIS_Pos (16U)
8415 #define ETH_DMAISR_MTLIS_Msk (0x1UL << ETH_DMAISR_MTLIS_Pos) /*!< 0x00010000 */
8416 #define ETH_DMAISR_MTLIS ETH_DMAISR_MTLIS_Msk /* MAC Interrupt Status */
8417 #define ETH_DMAISR_DMACIS_Pos (0U)
8418 #define ETH_DMAISR_DMACIS_Msk (0x1UL << ETH_DMAISR_DMACIS_Pos) /*!< 0x00000001 */
8419 #define ETH_DMAISR_DMACIS ETH_DMAISR_DMACIS_Msk /* DMA Channel Interrupt Status */
8420
8421 /* Bit definition for Ethernet DMA Debug Status Register */
8422 #define ETH_DMADSR_TPS_Pos (12U)
8423 #define ETH_DMADSR_TPS_Msk (0xFUL << ETH_DMADSR_TPS_Pos) /*!< 0x0000F000 */
8424 #define ETH_DMADSR_TPS ETH_DMADSR_TPS_Msk /* DMA Channel Transmit Process State */
8425 #define ETH_DMADSR_TPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Transmit Command issued) */
8426 #define ETH_DMADSR_TPS_FETCHING_Pos (12U)
8427 #define ETH_DMADSR_TPS_FETCHING_Msk (0x1UL << ETH_DMADSR_TPS_FETCHING_Pos) /*!< 0x00001000 */
8428 #define ETH_DMADSR_TPS_FETCHING ETH_DMADSR_TPS_FETCHING_Msk /* Running (Fetching Tx Transfer Descriptor) */
8429 #define ETH_DMADSR_TPS_WAITING_Pos (13U)
8430 #define ETH_DMADSR_TPS_WAITING_Msk (0x1UL << ETH_DMADSR_TPS_WAITING_Pos) /*!< 0x00002000 */
8431 #define ETH_DMADSR_TPS_WAITING ETH_DMADSR_TPS_WAITING_Msk /* Running (Waiting for status) */
8432 #define ETH_DMADSR_TPS_READING_Pos (12U)
8433 #define ETH_DMADSR_TPS_READING_Msk (0x3UL << ETH_DMADSR_TPS_READING_Pos) /*!< 0x00003000 */
8434 #define ETH_DMADSR_TPS_READING ETH_DMADSR_TPS_READING_Msk /* Running (Reading Data from system memory buffer and queuing it to the Tx buffer (Tx FIFO)) */
8435 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Pos (14U)
8436 #define ETH_DMADSR_TPS_TIMESTAMP_WR_Msk (0x1UL << ETH_DMADSR_TPS_TIMESTAMP_WR_Pos) /*!< 0x00004000 */
8437 #define ETH_DMADSR_TPS_TIMESTAMP_WR ETH_DMADSR_TPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8438 #define ETH_DMADSR_TPS_SUSPENDED_Pos (13U)
8439 #define ETH_DMADSR_TPS_SUSPENDED_Msk (0x3UL << ETH_DMADSR_TPS_SUSPENDED_Pos) /*!< 0x00006000 */
8440 #define ETH_DMADSR_TPS_SUSPENDED ETH_DMADSR_TPS_SUSPENDED_Msk /* Suspended (Tx Descriptor Unavailable or Tx Buffer Underflow) */
8441 #define ETH_DMADSR_TPS_CLOSING_Pos (12U)
8442 #define ETH_DMADSR_TPS_CLOSING_Msk (0x7UL << ETH_DMADSR_TPS_CLOSING_Pos) /*!< 0x00007000 */
8443 #define ETH_DMADSR_TPS_CLOSING ETH_DMADSR_TPS_CLOSING_Msk /* Running (Closing Tx Descriptor) */
8444 #define ETH_DMADSR_RPS_Pos (8U)
8445 #define ETH_DMADSR_RPS_Msk (0xFUL << ETH_DMADSR_RPS_Pos) /*!< 0x00000F00 */
8446 #define ETH_DMADSR_RPS ETH_DMADSR_RPS_Msk /* DMA Channel Receive Process State */
8447 #define ETH_DMADSR_RPS_STOPPED ((uint32_t)0x00000000) /* Stopped (Reset or Stop Receive Command issued) */
8448 #define ETH_DMADSR_RPS_FETCHING_Pos (12U)
8449 #define ETH_DMADSR_RPS_FETCHING_Msk (0x1UL << ETH_DMADSR_RPS_FETCHING_Pos) /*!< 0x00001000 */
8450 #define ETH_DMADSR_RPS_FETCHING ETH_DMADSR_RPS_FETCHING_Msk /* Running (Fetching Rx Transfer Descriptor) */
8451 #define ETH_DMADSR_RPS_WAITING_Pos (12U)
8452 #define ETH_DMADSR_RPS_WAITING_Msk (0x3UL << ETH_DMADSR_RPS_WAITING_Pos) /*!< 0x00003000 */
8453 #define ETH_DMADSR_RPS_WAITING ETH_DMADSR_RPS_WAITING_Msk /* Running (Waiting for status) */
8454 #define ETH_DMADSR_RPS_SUSPENDED_Pos (14U)
8455 #define ETH_DMADSR_RPS_SUSPENDED_Msk (0x1UL << ETH_DMADSR_RPS_SUSPENDED_Pos) /*!< 0x00004000 */
8456 #define ETH_DMADSR_RPS_SUSPENDED ETH_DMADSR_RPS_SUSPENDED_Msk /* Suspended (Rx Descriptor Unavailable) */
8457 #define ETH_DMADSR_RPS_CLOSING_Pos (12U)
8458 #define ETH_DMADSR_RPS_CLOSING_Msk (0x5UL << ETH_DMADSR_RPS_CLOSING_Pos) /*!< 0x00005000 */
8459 #define ETH_DMADSR_RPS_CLOSING ETH_DMADSR_RPS_CLOSING_Msk /* Running (Closing the Rx Descriptor) */
8460 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Pos (13U)
8461 #define ETH_DMADSR_RPS_TIMESTAMP_WR_Msk (0x3UL << ETH_DMADSR_RPS_TIMESTAMP_WR_Pos) /*!< 0x00006000 */
8462 #define ETH_DMADSR_RPS_TIMESTAMP_WR ETH_DMADSR_RPS_TIMESTAMP_WR_Msk /* Timestamp write state */
8463 #define ETH_DMADSR_RPS_TRANSFERRING_Pos (12U)
8464 #define ETH_DMADSR_RPS_TRANSFERRING_Msk (0x7UL << ETH_DMADSR_RPS_TRANSFERRING_Pos) /*!< 0x00007000 */
8465 #define ETH_DMADSR_RPS_TRANSFERRING ETH_DMADSR_RPS_TRANSFERRING_Msk /* Running (Transferring the received packet data from the Rx buffer to the system memory) */
8466
8467 /* Bit definition for Ethernet DMA Channel Control Register */
8468 #define ETH_DMACCR_DSL_Pos (18U)
8469 #define ETH_DMACCR_DSL_Msk (0x7UL << ETH_DMACCR_DSL_Pos) /*!< 0x001C0000 */
8470 #define ETH_DMACCR_DSL ETH_DMACCR_DSL_Msk /* Descriptor Skip Length */
8471 #define ETH_DMACCR_DSL_0BIT ((uint32_t)0x00000000)
8472 #define ETH_DMACCR_DSL_32BIT ((uint32_t)0x00040000)
8473 #define ETH_DMACCR_DSL_64BIT ((uint32_t)0x00080000)
8474 #define ETH_DMACCR_DSL_128BIT ((uint32_t)0x00100000)
8475 #define ETH_DMACCR_8PBL ((uint32_t)0x00010000) /* 8xPBL mode */
8476 #define ETH_DMACCR_MSS_Pos (0U)
8477 #define ETH_DMACCR_MSS_Msk (0x3FFFUL << ETH_DMACCR_MSS_Pos) /*!< 0x00003FFF */
8478 #define ETH_DMACCR_MSS ETH_DMACCR_MSS_Msk /* Maximum Segment Size */
8479
8480 /* Bit definition for Ethernet DMA Channel Tx Control Register */
8481 #define ETH_DMACTCR_TPBL_Pos (16U)
8482 #define ETH_DMACTCR_TPBL_Msk (0x3FUL << ETH_DMACTCR_TPBL_Pos) /*!< 0x003F0000 */
8483 #define ETH_DMACTCR_TPBL ETH_DMACTCR_TPBL_Msk /* Transmit Programmable Burst Length */
8484 #define ETH_DMACTCR_TPBL_1PBL ((uint32_t)0x00010000) /* Transmit Programmable Burst Length 1 */
8485 #define ETH_DMACTCR_TPBL_2PBL ((uint32_t)0x00020000) /* Transmit Programmable Burst Length 2 */
8486 #define ETH_DMACTCR_TPBL_4PBL ((uint32_t)0x00040000) /* Transmit Programmable Burst Length 4 */
8487 #define ETH_DMACTCR_TPBL_8PBL ((uint32_t)0x00080000) /* Transmit Programmable Burst Length 8 */
8488 #define ETH_DMACTCR_TPBL_16PBL ((uint32_t)0x00100000) /* Transmit Programmable Burst Length 16 */
8489 #define ETH_DMACTCR_TPBL_32PBL ((uint32_t)0x00200000) /* Transmit Programmable Burst Length 32 */
8490 #define ETH_DMACTCR_TSE_Pos (12U)
8491 #define ETH_DMACTCR_TSE_Msk (0x1UL << ETH_DMACTCR_TSE_Pos) /*!< 0x00001000 */
8492 #define ETH_DMACTCR_TSE ETH_DMACTCR_TSE_Msk /* TCP Segmentation Enabled */
8493 #define ETH_DMACTCR_OSP_Pos (4U)
8494 #define ETH_DMACTCR_OSP_Msk (0x1UL << ETH_DMACTCR_OSP_Pos) /*!< 0x00000010 */
8495 #define ETH_DMACTCR_OSP ETH_DMACTCR_OSP_Msk /* Operate on Second Packet */
8496 #define ETH_DMACTCR_ST_Pos (0U)
8497 #define ETH_DMACTCR_ST_Msk (0x1UL << ETH_DMACTCR_ST_Pos) /*!< 0x00000001 */
8498 #define ETH_DMACTCR_ST ETH_DMACTCR_ST_Msk /* Start or Stop Transmission Command */
8499
8500 /* Bit definition for Ethernet DMA Channel Rx Control Register */
8501 #define ETH_DMACRCR_RPF_Pos (31U)
8502 #define ETH_DMACRCR_RPF_Msk (0x1UL << ETH_DMACRCR_RPF_Pos) /*!< 0x80000000 */
8503 #define ETH_DMACRCR_RPF ETH_DMACRCR_RPF_Msk /* Rx Packet Flush */
8504 #define ETH_DMACRCR_RPBL_Pos (16U)
8505 #define ETH_DMACRCR_RPBL_Msk (0x3FUL << ETH_DMACRCR_RPBL_Pos) /*!< 0x003F0000 */
8506 #define ETH_DMACRCR_RPBL ETH_DMACRCR_RPBL_Msk /* Receive Programmable Burst Length */
8507 #define ETH_DMACRCR_RPBL_1PBL ((uint32_t)0x00010000) /* Receive Programmable Burst Length 1 */
8508 #define ETH_DMACRCR_RPBL_2PBL ((uint32_t)0x00020000) /* Receive Programmable Burst Length 2 */
8509 #define ETH_DMACRCR_RPBL_4PBL ((uint32_t)0x00040000) /* Receive Programmable Burst Length 4 */
8510 #define ETH_DMACRCR_RPBL_8PBL ((uint32_t)0x00080000) /* Receive Programmable Burst Length 8 */
8511 #define ETH_DMACRCR_RPBL_16PBL ((uint32_t)0x00100000) /* Receive Programmable Burst Length 16 */
8512 #define ETH_DMACRCR_RPBL_32PBL ((uint32_t)0x00200000) /* Receive Programmable Burst Length 32 */
8513 #define ETH_DMACRCR_RBSZ_Pos (1U)
8514 #define ETH_DMACRCR_RBSZ_Msk (0x3FFFUL << ETH_DMACRCR_RBSZ_Pos) /*!< 0x00007FFE */
8515 #define ETH_DMACRCR_RBSZ ETH_DMACRCR_RBSZ_Msk /* Receive Buffer size */
8516 #define ETH_DMACRCR_SR_Pos (0U)
8517 #define ETH_DMACRCR_SR_Msk (0x1UL << ETH_DMACRCR_SR_Pos) /*!< 0x00000001 */
8518 #define ETH_DMACRCR_SR ETH_DMACRCR_SR_Msk /* Start or Stop Receive */
8519
8520 /* Bit definition for Ethernet DMA CH Tx Desc List Address Register */
8521 #define ETH_DMACTDLAR_TDESLA_Pos (2U)
8522 #define ETH_DMACTDLAR_TDESLA_Msk (0x3FFFFFFFUL << ETH_DMACTDLAR_TDESLA_Pos) /*!< 0xFFFFFFFC */
8523 #define ETH_DMACTDLAR_TDESLA ETH_DMACTDLAR_TDESLA_Msk /* Start of Transmit List */
8524
8525 /* Bit definition for Ethernet DMA CH Rx Desc List Address Register */
8526 #define ETH_DMACRDLAR_RDESLA_Pos (2U)
8527 #define ETH_DMACRDLAR_RDESLA_Msk (0x3FFFFFFFUL << ETH_DMACRDLAR_RDESLA_Pos) /*!< 0xFFFFFFFC */
8528 #define ETH_DMACRDLAR_RDESLA ETH_DMACRDLAR_RDESLA_Msk /* Start of Receive List */
8529
8530 /* Bit definition for Ethernet DMA CH Tx Desc Tail Pointer Register */
8531 #define ETH_DMACTDTPR_TDT_Pos (2U)
8532 #define ETH_DMACTDTPR_TDT_Msk (0x3FFFFFFFUL << ETH_DMACTDTPR_TDT_Pos) /*!< 0xFFFFFFFC */
8533 #define ETH_DMACTDTPR_TDT ETH_DMACTDTPR_TDT_Msk /* Transmit Descriptor Tail Pointer */
8534
8535 /* Bit definition for Ethernet DMA CH Rx Desc Tail Pointer Register */
8536 #define ETH_DMACRDTPR_RDT_Pos (2U)
8537 #define ETH_DMACRDTPR_RDT_Msk (0x3FFFFFFFUL << ETH_DMACRDTPR_RDT_Pos) /*!< 0xFFFFFFFC */
8538 #define ETH_DMACRDTPR_RDT ETH_DMACRDTPR_RDT_Msk /* Receive Descriptor Tail Pointer */
8539
8540 /* Bit definition for Ethernet DMA CH Tx Desc Ring Length Register */
8541 #define ETH_DMACTDRLR_TDRL_Pos (0U)
8542 #define ETH_DMACTDRLR_TDRL_Msk (0x3FFUL << ETH_DMACTDRLR_TDRL_Pos) /*!< 0x000003FF */
8543 #define ETH_DMACTDRLR_TDRL ETH_DMACTDRLR_TDRL_Msk /* Transmit Descriptor Ring Length */
8544
8545 /* Bit definition for Ethernet DMA CH Rx Desc Ring Length Register */
8546 #define ETH_DMACRDRLR_RDRL_Pos (0U)
8547 #define ETH_DMACRDRLR_RDRL_Msk (0x3FFUL << ETH_DMACRDRLR_RDRL_Pos) /*!< 0x000003FF */
8548 #define ETH_DMACRDRLR_RDRL ETH_DMACRDRLR_RDRL_Msk /* Receive Descriptor Ring Length */
8549
8550 /* Bit definition for Ethernet DMA Channel Interrupt Enable Register */
8551 #define ETH_DMACIER_NIE_Pos (15U)
8552 #define ETH_DMACIER_NIE_Msk (0x1UL << ETH_DMACIER_NIE_Pos) /*!< 0x00008000 */
8553 #define ETH_DMACIER_NIE ETH_DMACIER_NIE_Msk /* Normal Interrupt Summary Enable */
8554 #define ETH_DMACIER_AIE_Pos (14U)
8555 #define ETH_DMACIER_AIE_Msk (0x1UL << ETH_DMACIER_AIE_Pos) /*!< 0x00004000 */
8556 #define ETH_DMACIER_AIE ETH_DMACIER_AIE_Msk /* Abnormal Interrupt Summary Enable */
8557 #define ETH_DMACIER_CDEE_Pos (13U)
8558 #define ETH_DMACIER_CDEE_Msk (0x1UL << ETH_DMACIER_CDEE_Pos) /*!< 0x00002000 */
8559 #define ETH_DMACIER_CDEE ETH_DMACIER_CDEE_Msk /* Context Descriptor Error Enable */
8560 #define ETH_DMACIER_FBEE_Pos (12U)
8561 #define ETH_DMACIER_FBEE_Msk (0x1UL << ETH_DMACIER_FBEE_Pos) /*!< 0x00001000 */
8562 #define ETH_DMACIER_FBEE ETH_DMACIER_FBEE_Msk /* Fatal Bus Error Enable */
8563 #define ETH_DMACIER_ERIE_Pos (11U)
8564 #define ETH_DMACIER_ERIE_Msk (0x1UL << ETH_DMACIER_ERIE_Pos) /*!< 0x00000800 */
8565 #define ETH_DMACIER_ERIE ETH_DMACIER_ERIE_Msk /* Early Receive Interrupt Enable */
8566 #define ETH_DMACIER_ETIE_Pos (10U)
8567 #define ETH_DMACIER_ETIE_Msk (0x1UL << ETH_DMACIER_ETIE_Pos) /*!< 0x00000400 */
8568 #define ETH_DMACIER_ETIE ETH_DMACIER_ETIE_Msk /* Early Transmit Interrupt Enable */
8569 #define ETH_DMACIER_RWTE_Pos (9U)
8570 #define ETH_DMACIER_RWTE_Msk (0x1UL << ETH_DMACIER_RWTE_Pos) /*!< 0x00000200 */
8571 #define ETH_DMACIER_RWTE ETH_DMACIER_RWTE_Msk /* Receive Watchdog Timeout Enable */
8572 #define ETH_DMACIER_RSE_Pos (8U)
8573 #define ETH_DMACIER_RSE_Msk (0x1UL << ETH_DMACIER_RSE_Pos) /*!< 0x00000100 */
8574 #define ETH_DMACIER_RSE ETH_DMACIER_RSE_Msk /* Receive Stopped Enable */
8575 #define ETH_DMACIER_RBUE_Pos (7U)
8576 #define ETH_DMACIER_RBUE_Msk (0x1UL << ETH_DMACIER_RBUE_Pos) /*!< 0x00000080 */
8577 #define ETH_DMACIER_RBUE ETH_DMACIER_RBUE_Msk /* Receive Buffer Unavailable Enable */
8578 #define ETH_DMACIER_RIE_Pos (6U)
8579 #define ETH_DMACIER_RIE_Msk (0x1UL << ETH_DMACIER_RIE_Pos) /*!< 0x00000040 */
8580 #define ETH_DMACIER_RIE ETH_DMACIER_RIE_Msk /* Receive Interrupt Enable */
8581 #define ETH_DMACIER_TBUE_Pos (2U)
8582 #define ETH_DMACIER_TBUE_Msk (0x1UL << ETH_DMACIER_TBUE_Pos) /*!< 0x00000004 */
8583 #define ETH_DMACIER_TBUE ETH_DMACIER_TBUE_Msk /* Transmit Buffer Unavailable Enable */
8584 #define ETH_DMACIER_TXSE_Pos (1U)
8585 #define ETH_DMACIER_TXSE_Msk (0x1UL << ETH_DMACIER_TXSE_Pos) /*!< 0x00000002 */
8586 #define ETH_DMACIER_TXSE ETH_DMACIER_TXSE_Msk /* Transmit Stopped Enable */
8587 #define ETH_DMACIER_TIE_Pos (0U)
8588 #define ETH_DMACIER_TIE_Msk (0x1UL << ETH_DMACIER_TIE_Pos) /*!< 0x00000001 */
8589 #define ETH_DMACIER_TIE ETH_DMACIER_TIE_Msk /* Transmit Interrupt Enable */
8590
8591 /* Bit definition for Ethernet DMA Channel Rx Interrupt Watchdog Timer Register */
8592 #define ETH_DMACRIWTR_RWT_Pos (0U)
8593 #define ETH_DMACRIWTR_RWT_Msk (0xFFUL << ETH_DMACRIWTR_RWT_Pos) /*!< 0x000000FF */
8594 #define ETH_DMACRIWTR_RWT ETH_DMACRIWTR_RWT_Msk /* Receive Interrupt Watchdog Timer Count */
8595
8596 /* Bit definition for Ethernet DMA Channel Current App Tx Desc Register */
8597 #define ETH_DMACCATDR_CURTDESAPTR_Pos (0U)
8598 #define ETH_DMACCATDR_CURTDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATDR_CURTDESAPTR_Pos) /*!< 0xFFFFFFFF */
8599 #define ETH_DMACCATDR_CURTDESAPTR ETH_DMACCATDR_CURTDESAPTR_Msk /* Application Transmit Descriptor Address Pointer */
8600
8601 /* Bit definition for Ethernet DMA Channel Current App Rx Desc Register */
8602 #define ETH_DMACCARDR_CURRDESAPTR_Pos (0U)
8603 #define ETH_DMACCARDR_CURRDESAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARDR_CURRDESAPTR_Pos) /*!< 0xFFFFFFFF */
8604 #define ETH_DMACCARDR_CURRDESAPTR ETH_DMACCARDR_CURRDESAPTR_Msk /* Application Receive Descriptor Address Pointer */
8605
8606 /* Bit definition for Ethernet DMA Channel Current App Tx Buffer Register */
8607 #define ETH_DMACCATBR_CURTBUFAPTR_Pos (0U)
8608 #define ETH_DMACCATBR_CURTBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCATBR_CURTBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8609 #define ETH_DMACCATBR_CURTBUFAPTR ETH_DMACCATBR_CURTBUFAPTR_Msk /* Application Transmit Buffer Address Pointer */
8610
8611 /* Bit definition for Ethernet DMA Channel Current App Rx Buffer Register */
8612 #define ETH_DMACCARBR_CURRBUFAPTR_Pos (0U)
8613 #define ETH_DMACCARBR_CURRBUFAPTR_Msk (0xFFFFFFFFUL << ETH_DMACCARBR_CURRBUFAPTR_Pos) /*!< 0xFFFFFFFF */
8614 #define ETH_DMACCARBR_CURRBUFAPTR ETH_DMACCARBR_CURRBUFAPTR_Msk /* Application Receive Buffer Address Pointer */
8615
8616 /* Bit definition for Ethernet DMA Channel Status Register */
8617 #define ETH_DMACSR_REB_Pos (19U)
8618 #define ETH_DMACSR_REB_Msk (0x7UL << ETH_DMACSR_REB_Pos) /*!< 0x00380000 */
8619 #define ETH_DMACSR_REB ETH_DMACSR_REB_Msk /* Rx DMA Error Bits */
8620 #define ETH_DMACSR_TEB_Pos (16U)
8621 #define ETH_DMACSR_TEB_Msk (0x7UL << ETH_DMACSR_TEB_Pos) /*!< 0x00070000 */
8622 #define ETH_DMACSR_TEB ETH_DMACSR_TEB_Msk /* Tx DMA Error Bits */
8623 #define ETH_DMACSR_NIS_Pos (15U)
8624 #define ETH_DMACSR_NIS_Msk (0x1UL << ETH_DMACSR_NIS_Pos) /*!< 0x00008000 */
8625 #define ETH_DMACSR_NIS ETH_DMACSR_NIS_Msk /* Normal Interrupt Summary */
8626 #define ETH_DMACSR_AIS_Pos (14U)
8627 #define ETH_DMACSR_AIS_Msk (0x1UL << ETH_DMACSR_AIS_Pos) /*!< 0x00004000 */
8628 #define ETH_DMACSR_AIS ETH_DMACSR_AIS_Msk /* Abnormal Interrupt Summary */
8629 #define ETH_DMACSR_CDE_Pos (13U)
8630 #define ETH_DMACSR_CDE_Msk (0x1UL << ETH_DMACSR_CDE_Pos) /*!< 0x00002000 */
8631 #define ETH_DMACSR_CDE ETH_DMACSR_CDE_Msk /* Context Descriptor Error */
8632 #define ETH_DMACSR_FBE_Pos (12U)
8633 #define ETH_DMACSR_FBE_Msk (0x1UL << ETH_DMACSR_FBE_Pos) /*!< 0x00001000 */
8634 #define ETH_DMACSR_FBE ETH_DMACSR_FBE_Msk /* Fatal Bus Error */
8635 #define ETH_DMACSR_ERI_Pos (11U)
8636 #define ETH_DMACSR_ERI_Msk (0x1UL << ETH_DMACSR_ERI_Pos) /*!< 0x00000800 */
8637 #define ETH_DMACSR_ERI ETH_DMACSR_ERI_Msk /* Early Receive Interrupt */
8638 #define ETH_DMACSR_ETI_Pos (10U)
8639 #define ETH_DMACSR_ETI_Msk (0x1UL << ETH_DMACSR_ETI_Pos) /*!< 0x00000400 */
8640 #define ETH_DMACSR_ETI ETH_DMACSR_ETI_Msk /* Early Transmit Interrupt */
8641 #define ETH_DMACSR_RWT_Pos (9U)
8642 #define ETH_DMACSR_RWT_Msk (0x1UL << ETH_DMACSR_RWT_Pos) /*!< 0x00000200 */
8643 #define ETH_DMACSR_RWT ETH_DMACSR_RWT_Msk /* Receive Watchdog Timeout */
8644 #define ETH_DMACSR_RPS_Pos (8U)
8645 #define ETH_DMACSR_RPS_Msk (0x1UL << ETH_DMACSR_RPS_Pos) /*!< 0x00000100 */
8646 #define ETH_DMACSR_RPS ETH_DMACSR_RPS_Msk /* Receive Process Stopped */
8647 #define ETH_DMACSR_RBU_Pos (7U)
8648 #define ETH_DMACSR_RBU_Msk (0x1UL << ETH_DMACSR_RBU_Pos) /*!< 0x00000080 */
8649 #define ETH_DMACSR_RBU ETH_DMACSR_RBU_Msk /* Receive Buffer Unavailable */
8650 #define ETH_DMACSR_RI_Pos (6U)
8651 #define ETH_DMACSR_RI_Msk (0x1UL << ETH_DMACSR_RI_Pos) /*!< 0x00000040 */
8652 #define ETH_DMACSR_RI ETH_DMACSR_RI_Msk /* Receive Interrupt */
8653 #define ETH_DMACSR_TBU_Pos (2U)
8654 #define ETH_DMACSR_TBU_Msk (0x1UL << ETH_DMACSR_TBU_Pos) /*!< 0x00000004 */
8655 #define ETH_DMACSR_TBU ETH_DMACSR_TBU_Msk /* Transmit Buffer Unavailable */
8656 #define ETH_DMACSR_TPS_Pos (1U)
8657 #define ETH_DMACSR_TPS_Msk (0x1UL << ETH_DMACSR_TPS_Pos) /*!< 0x00000002 */
8658 #define ETH_DMACSR_TPS ETH_DMACSR_TPS_Msk /* Transmit Process Stopped */
8659 #define ETH_DMACSR_TI_Pos (0U)
8660 #define ETH_DMACSR_TI_Msk (0x1UL << ETH_DMACSR_TI_Pos) /*!< 0x00000001 */
8661 #define ETH_DMACSR_TI ETH_DMACSR_TI_Msk /* Transmit Interrupt */
8662
8663 /* Bit definition for Ethernet DMA Channel missed frame count register */
8664 #define ETH_DMACMFCR_MFCO_Pos (15U)
8665 #define ETH_DMACMFCR_MFCO_Msk (0x1UL << ETH_DMACMFCR_MFCO_Pos) /*!< 0x00008000 */
8666 #define ETH_DMACMFCR_MFCO ETH_DMACMFCR_MFCO_Msk /* Overflow status of the MFC Counter */
8667 #define ETH_DMACMFCR_MFC_Pos (0U)
8668 #define ETH_DMACMFCR_MFC_Msk (0x7FFUL << ETH_DMACMFCR_MFC_Pos) /*!< 0x000007FF */
8669 #define ETH_DMACMFCR_MFC ETH_DMACMFCR_MFC_Msk /* The number of packet counters dropped by the DMA */
8670
8671 /******************************************************************************/
8672 /* */
8673 /* DMA Controller */
8674 /* */
8675 /******************************************************************************/
8676 /******************** Bits definition for DMA_SxCR register *****************/
8677 #define DMA_SxCR_MBURST_Pos (23U)
8678 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
8679 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
8680 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
8681 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
8682 #define DMA_SxCR_PBURST_Pos (21U)
8683 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
8684 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
8685 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
8686 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
8687 #define DMA_SxCR_CT_Pos (19U)
8688 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
8689 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
8690 #define DMA_SxCR_DBM_Pos (18U)
8691 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
8692 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
8693 #define DMA_SxCR_PL_Pos (16U)
8694 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
8695 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
8696 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
8697 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
8698 #define DMA_SxCR_PINCOS_Pos (15U)
8699 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
8700 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
8701 #define DMA_SxCR_MSIZE_Pos (13U)
8702 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
8703 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
8704 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
8705 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
8706 #define DMA_SxCR_PSIZE_Pos (11U)
8707 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
8708 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
8709 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
8710 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
8711 #define DMA_SxCR_MINC_Pos (10U)
8712 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
8713 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
8714 #define DMA_SxCR_PINC_Pos (9U)
8715 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
8716 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
8717 #define DMA_SxCR_CIRC_Pos (8U)
8718 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
8719 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
8720 #define DMA_SxCR_DIR_Pos (6U)
8721 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
8722 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
8723 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
8724 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
8725 #define DMA_SxCR_PFCTRL_Pos (5U)
8726 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
8727 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
8728 #define DMA_SxCR_TCIE_Pos (4U)
8729 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
8730 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
8731 #define DMA_SxCR_HTIE_Pos (3U)
8732 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
8733 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
8734 #define DMA_SxCR_TEIE_Pos (2U)
8735 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
8736 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
8737 #define DMA_SxCR_DMEIE_Pos (1U)
8738 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
8739 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
8740 #define DMA_SxCR_EN_Pos (0U)
8741 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
8742 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
8743
8744 /******************** Bits definition for DMA_SxCNDTR register **************/
8745 #define DMA_SxNDT_Pos (0U)
8746 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
8747 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
8748 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
8749 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
8750 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
8751 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
8752 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
8753 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
8754 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
8755 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
8756 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
8757 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
8758 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
8759 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
8760 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
8761 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
8762 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
8763 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
8764
8765 /******************** Bits definition for DMA_SxFCR register ****************/
8766 #define DMA_SxFCR_FEIE_Pos (7U)
8767 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
8768 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
8769 #define DMA_SxFCR_FS_Pos (3U)
8770 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
8771 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
8772 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
8773 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
8774 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
8775 #define DMA_SxFCR_DMDIS_Pos (2U)
8776 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
8777 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
8778 #define DMA_SxFCR_FTH_Pos (0U)
8779 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
8780 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
8781 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
8782 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
8783
8784 /******************** Bits definition for DMA_LISR register *****************/
8785 #define DMA_LISR_TCIF3_Pos (27U)
8786 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
8787 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
8788 #define DMA_LISR_HTIF3_Pos (26U)
8789 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
8790 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
8791 #define DMA_LISR_TEIF3_Pos (25U)
8792 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
8793 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
8794 #define DMA_LISR_DMEIF3_Pos (24U)
8795 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
8796 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
8797 #define DMA_LISR_FEIF3_Pos (22U)
8798 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
8799 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
8800 #define DMA_LISR_TCIF2_Pos (21U)
8801 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
8802 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
8803 #define DMA_LISR_HTIF2_Pos (20U)
8804 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
8805 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
8806 #define DMA_LISR_TEIF2_Pos (19U)
8807 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
8808 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
8809 #define DMA_LISR_DMEIF2_Pos (18U)
8810 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
8811 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
8812 #define DMA_LISR_FEIF2_Pos (16U)
8813 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
8814 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
8815 #define DMA_LISR_TCIF1_Pos (11U)
8816 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
8817 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
8818 #define DMA_LISR_HTIF1_Pos (10U)
8819 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
8820 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
8821 #define DMA_LISR_TEIF1_Pos (9U)
8822 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
8823 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
8824 #define DMA_LISR_DMEIF1_Pos (8U)
8825 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
8826 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
8827 #define DMA_LISR_FEIF1_Pos (6U)
8828 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
8829 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
8830 #define DMA_LISR_TCIF0_Pos (5U)
8831 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
8832 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
8833 #define DMA_LISR_HTIF0_Pos (4U)
8834 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
8835 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
8836 #define DMA_LISR_TEIF0_Pos (3U)
8837 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
8838 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
8839 #define DMA_LISR_DMEIF0_Pos (2U)
8840 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
8841 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
8842 #define DMA_LISR_FEIF0_Pos (0U)
8843 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
8844 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
8845
8846 /******************** Bits definition for DMA_HISR register *****************/
8847 #define DMA_HISR_TCIF7_Pos (27U)
8848 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
8849 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
8850 #define DMA_HISR_HTIF7_Pos (26U)
8851 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
8852 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
8853 #define DMA_HISR_TEIF7_Pos (25U)
8854 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
8855 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
8856 #define DMA_HISR_DMEIF7_Pos (24U)
8857 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
8858 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
8859 #define DMA_HISR_FEIF7_Pos (22U)
8860 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
8861 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
8862 #define DMA_HISR_TCIF6_Pos (21U)
8863 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
8864 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
8865 #define DMA_HISR_HTIF6_Pos (20U)
8866 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
8867 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
8868 #define DMA_HISR_TEIF6_Pos (19U)
8869 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
8870 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
8871 #define DMA_HISR_DMEIF6_Pos (18U)
8872 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
8873 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
8874 #define DMA_HISR_FEIF6_Pos (16U)
8875 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
8876 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
8877 #define DMA_HISR_TCIF5_Pos (11U)
8878 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
8879 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
8880 #define DMA_HISR_HTIF5_Pos (10U)
8881 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
8882 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
8883 #define DMA_HISR_TEIF5_Pos (9U)
8884 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
8885 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
8886 #define DMA_HISR_DMEIF5_Pos (8U)
8887 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
8888 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
8889 #define DMA_HISR_FEIF5_Pos (6U)
8890 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
8891 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
8892 #define DMA_HISR_TCIF4_Pos (5U)
8893 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
8894 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
8895 #define DMA_HISR_HTIF4_Pos (4U)
8896 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
8897 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
8898 #define DMA_HISR_TEIF4_Pos (3U)
8899 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
8900 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
8901 #define DMA_HISR_DMEIF4_Pos (2U)
8902 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
8903 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
8904 #define DMA_HISR_FEIF4_Pos (0U)
8905 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
8906 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
8907
8908 /******************** Bits definition for DMA_LIFCR register ****************/
8909 #define DMA_LIFCR_CTCIF3_Pos (27U)
8910 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
8911 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
8912 #define DMA_LIFCR_CHTIF3_Pos (26U)
8913 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
8914 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
8915 #define DMA_LIFCR_CTEIF3_Pos (25U)
8916 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
8917 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
8918 #define DMA_LIFCR_CDMEIF3_Pos (24U)
8919 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
8920 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
8921 #define DMA_LIFCR_CFEIF3_Pos (22U)
8922 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
8923 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
8924 #define DMA_LIFCR_CTCIF2_Pos (21U)
8925 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
8926 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
8927 #define DMA_LIFCR_CHTIF2_Pos (20U)
8928 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
8929 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
8930 #define DMA_LIFCR_CTEIF2_Pos (19U)
8931 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
8932 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
8933 #define DMA_LIFCR_CDMEIF2_Pos (18U)
8934 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
8935 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
8936 #define DMA_LIFCR_CFEIF2_Pos (16U)
8937 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
8938 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
8939 #define DMA_LIFCR_CTCIF1_Pos (11U)
8940 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
8941 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
8942 #define DMA_LIFCR_CHTIF1_Pos (10U)
8943 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
8944 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
8945 #define DMA_LIFCR_CTEIF1_Pos (9U)
8946 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
8947 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
8948 #define DMA_LIFCR_CDMEIF1_Pos (8U)
8949 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
8950 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
8951 #define DMA_LIFCR_CFEIF1_Pos (6U)
8952 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
8953 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
8954 #define DMA_LIFCR_CTCIF0_Pos (5U)
8955 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
8956 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
8957 #define DMA_LIFCR_CHTIF0_Pos (4U)
8958 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
8959 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
8960 #define DMA_LIFCR_CTEIF0_Pos (3U)
8961 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
8962 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
8963 #define DMA_LIFCR_CDMEIF0_Pos (2U)
8964 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
8965 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
8966 #define DMA_LIFCR_CFEIF0_Pos (0U)
8967 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
8968 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
8969
8970 /******************** Bits definition for DMA_HIFCR register ****************/
8971 #define DMA_HIFCR_CTCIF7_Pos (27U)
8972 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
8973 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
8974 #define DMA_HIFCR_CHTIF7_Pos (26U)
8975 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
8976 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
8977 #define DMA_HIFCR_CTEIF7_Pos (25U)
8978 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
8979 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
8980 #define DMA_HIFCR_CDMEIF7_Pos (24U)
8981 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
8982 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
8983 #define DMA_HIFCR_CFEIF7_Pos (22U)
8984 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
8985 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
8986 #define DMA_HIFCR_CTCIF6_Pos (21U)
8987 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
8988 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
8989 #define DMA_HIFCR_CHTIF6_Pos (20U)
8990 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
8991 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
8992 #define DMA_HIFCR_CTEIF6_Pos (19U)
8993 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
8994 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
8995 #define DMA_HIFCR_CDMEIF6_Pos (18U)
8996 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
8997 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
8998 #define DMA_HIFCR_CFEIF6_Pos (16U)
8999 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
9000 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
9001 #define DMA_HIFCR_CTCIF5_Pos (11U)
9002 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
9003 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
9004 #define DMA_HIFCR_CHTIF5_Pos (10U)
9005 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
9006 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
9007 #define DMA_HIFCR_CTEIF5_Pos (9U)
9008 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
9009 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
9010 #define DMA_HIFCR_CDMEIF5_Pos (8U)
9011 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
9012 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
9013 #define DMA_HIFCR_CFEIF5_Pos (6U)
9014 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
9015 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
9016 #define DMA_HIFCR_CTCIF4_Pos (5U)
9017 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
9018 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
9019 #define DMA_HIFCR_CHTIF4_Pos (4U)
9020 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
9021 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
9022 #define DMA_HIFCR_CTEIF4_Pos (3U)
9023 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
9024 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
9025 #define DMA_HIFCR_CDMEIF4_Pos (2U)
9026 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
9027 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
9028 #define DMA_HIFCR_CFEIF4_Pos (0U)
9029 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
9030 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
9031
9032 /****************** Bit definition for DMA_SxPAR register ********************/
9033 #define DMA_SxPAR_PA_Pos (0U)
9034 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
9035 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
9036
9037 /****************** Bit definition for DMA_SxM0AR register ********************/
9038 #define DMA_SxM0AR_M0A_Pos (0U)
9039 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
9040 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
9041
9042 /****************** Bit definition for DMA_SxM1AR register ********************/
9043 #define DMA_SxM1AR_M1A_Pos (0U)
9044 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
9045 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
9046
9047 /******************************************************************************/
9048 /* */
9049 /* DMAMUX Controller */
9050 /* */
9051 /******************************************************************************/
9052 /******************** Bits definition for DMAMUX_CxCR register **************/
9053 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
9054 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
9055 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
9056 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
9057 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
9058 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
9059 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
9060 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
9061 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
9062 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
9063 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
9064 #define DMAMUX_CxCR_SOIE_Pos (8U)
9065 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
9066 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
9067 #define DMAMUX_CxCR_EGE_Pos (9U)
9068 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
9069 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
9070 #define DMAMUX_CxCR_SE_Pos (16U)
9071 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
9072 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
9073 #define DMAMUX_CxCR_SPOL_Pos (17U)
9074 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
9075 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
9076 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
9077 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
9078 #define DMAMUX_CxCR_NBREQ_Pos (19U)
9079 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
9080 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
9081 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
9082 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
9083 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
9084 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
9085 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
9086 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
9087 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
9088 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
9089 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
9090 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
9091 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
9092 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
9093 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
9094
9095 /******************** Bits definition for DMAMUX_CSR register **************/
9096 #define DMAMUX_CSR_SOF0_Pos (0U)
9097 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
9098 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
9099 #define DMAMUX_CSR_SOF1_Pos (1U)
9100 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
9101 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
9102 #define DMAMUX_CSR_SOF2_Pos (2U)
9103 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
9104 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
9105 #define DMAMUX_CSR_SOF3_Pos (3U)
9106 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
9107 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
9108 #define DMAMUX_CSR_SOF4_Pos (4U)
9109 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
9110 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
9111 #define DMAMUX_CSR_SOF5_Pos (5U)
9112 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
9113 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
9114 #define DMAMUX_CSR_SOF6_Pos (6U)
9115 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
9116 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
9117 #define DMAMUX_CSR_SOF7_Pos (7U)
9118 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
9119 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
9120 #define DMAMUX_CSR_SOF8_Pos (8U)
9121 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
9122 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
9123 #define DMAMUX_CSR_SOF9_Pos (9U)
9124 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
9125 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
9126 #define DMAMUX_CSR_SOF10_Pos (10U)
9127 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
9128 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
9129 #define DMAMUX_CSR_SOF11_Pos (11U)
9130 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
9131 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
9132 #define DMAMUX_CSR_SOF12_Pos (12U)
9133 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
9134 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
9135 #define DMAMUX_CSR_SOF13_Pos (13U)
9136 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
9137 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
9138 #define DMAMUX_CSR_SOF14_Pos (14U)
9139 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
9140 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
9141 #define DMAMUX_CSR_SOF15_Pos (15U)
9142 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
9143 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
9144
9145 /******************** Bits definition for DMAMUX_CFR register **************/
9146 #define DMAMUX_CFR_CSOF0_Pos (0U)
9147 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
9148 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
9149 #define DMAMUX_CFR_CSOF1_Pos (1U)
9150 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
9151 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
9152 #define DMAMUX_CFR_CSOF2_Pos (2U)
9153 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
9154 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
9155 #define DMAMUX_CFR_CSOF3_Pos (3U)
9156 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
9157 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
9158 #define DMAMUX_CFR_CSOF4_Pos (4U)
9159 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
9160 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
9161 #define DMAMUX_CFR_CSOF5_Pos (5U)
9162 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
9163 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
9164 #define DMAMUX_CFR_CSOF6_Pos (6U)
9165 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
9166 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
9167 #define DMAMUX_CFR_CSOF7_Pos (7U)
9168 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
9169 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
9170 #define DMAMUX_CFR_CSOF8_Pos (8U)
9171 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
9172 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
9173 #define DMAMUX_CFR_CSOF9_Pos (9U)
9174 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
9175 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
9176 #define DMAMUX_CFR_CSOF10_Pos (10U)
9177 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
9178 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
9179 #define DMAMUX_CFR_CSOF11_Pos (11U)
9180 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
9181 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
9182 #define DMAMUX_CFR_CSOF12_Pos (12U)
9183 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
9184 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
9185 #define DMAMUX_CFR_CSOF13_Pos (13U)
9186 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
9187 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
9188 #define DMAMUX_CFR_CSOF14_Pos (14U)
9189 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
9190 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
9191 #define DMAMUX_CFR_CSOF15_Pos (15U)
9192 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
9193 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
9194
9195 /******************** Bits definition for DMAMUX_RGxCR register ************/
9196 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
9197 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
9198 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
9199 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
9200 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
9201 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
9202 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
9203 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
9204 #define DMAMUX_RGxCR_OIE_Pos (8U)
9205 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
9206 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
9207 #define DMAMUX_RGxCR_GE_Pos (16U)
9208 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
9209 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
9210 #define DMAMUX_RGxCR_GPOL_Pos (17U)
9211 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
9212 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
9213 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
9214 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
9215 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
9216 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
9217 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
9218 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
9219 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
9220 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
9221 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
9222 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
9223
9224 /******************** Bits definition for DMAMUX_RGSR register **************/
9225 #define DMAMUX_RGSR_OF0_Pos (0U)
9226 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
9227 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
9228 #define DMAMUX_RGSR_OF1_Pos (1U)
9229 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
9230 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
9231 #define DMAMUX_RGSR_OF2_Pos (2U)
9232 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
9233 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
9234 #define DMAMUX_RGSR_OF3_Pos (3U)
9235 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
9236 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
9237 #define DMAMUX_RGSR_OF4_Pos (4U)
9238 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
9239 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
9240 #define DMAMUX_RGSR_OF5_Pos (5U)
9241 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
9242 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
9243 #define DMAMUX_RGSR_OF6_Pos (6U)
9244 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
9245 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
9246 #define DMAMUX_RGSR_OF7_Pos (7U)
9247 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
9248 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
9249
9250 /******************** Bits definition for DMAMUX_RGCFR register **************/
9251 #define DMAMUX_RGCFR_COF0_Pos (0U)
9252 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
9253 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
9254 #define DMAMUX_RGCFR_COF1_Pos (1U)
9255 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
9256 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
9257 #define DMAMUX_RGCFR_COF2_Pos (2U)
9258 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
9259 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
9260 #define DMAMUX_RGCFR_COF3_Pos (3U)
9261 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
9262 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
9263 #define DMAMUX_RGCFR_COF4_Pos (4U)
9264 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
9265 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
9266 #define DMAMUX_RGCFR_COF5_Pos (5U)
9267 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
9268 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
9269 #define DMAMUX_RGCFR_COF6_Pos (6U)
9270 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
9271 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
9272 #define DMAMUX_RGCFR_COF7_Pos (7U)
9273 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
9274 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
9275
9276 /******************************************************************************/
9277 /* */
9278 /* AHB Master DMA2D Controller (DMA2D) */
9279 /* */
9280 /******************************************************************************/
9281
9282 /******************** Bit definition for DMA2D_CR register ******************/
9283
9284 #define DMA2D_CR_START_Pos (0U)
9285 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
9286 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
9287 #define DMA2D_CR_SUSP_Pos (1U)
9288 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
9289 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
9290 #define DMA2D_CR_ABORT_Pos (2U)
9291 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
9292 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
9293 #define DMA2D_CR_LOM_Pos (6U)
9294 #define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
9295 #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
9296 #define DMA2D_CR_TEIE_Pos (8U)
9297 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
9298 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
9299 #define DMA2D_CR_TCIE_Pos (9U)
9300 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
9301 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
9302 #define DMA2D_CR_TWIE_Pos (10U)
9303 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
9304 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
9305 #define DMA2D_CR_CAEIE_Pos (11U)
9306 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
9307 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
9308 #define DMA2D_CR_CTCIE_Pos (12U)
9309 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
9310 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
9311 #define DMA2D_CR_CEIE_Pos (13U)
9312 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
9313 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
9314 #define DMA2D_CR_MODE_Pos (16U)
9315 #define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
9316 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
9317 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
9318 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
9319 #define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
9320
9321 /******************** Bit definition for DMA2D_ISR register *****************/
9322
9323 #define DMA2D_ISR_TEIF_Pos (0U)
9324 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
9325 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
9326 #define DMA2D_ISR_TCIF_Pos (1U)
9327 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
9328 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
9329 #define DMA2D_ISR_TWIF_Pos (2U)
9330 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
9331 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
9332 #define DMA2D_ISR_CAEIF_Pos (3U)
9333 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
9334 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
9335 #define DMA2D_ISR_CTCIF_Pos (4U)
9336 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
9337 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
9338 #define DMA2D_ISR_CEIF_Pos (5U)
9339 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
9340 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
9341
9342 /******************** Bit definition for DMA2D_IFCR register ****************/
9343
9344 #define DMA2D_IFCR_CTEIF_Pos (0U)
9345 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
9346 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
9347 #define DMA2D_IFCR_CTCIF_Pos (1U)
9348 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
9349 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
9350 #define DMA2D_IFCR_CTWIF_Pos (2U)
9351 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
9352 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
9353 #define DMA2D_IFCR_CAECIF_Pos (3U)
9354 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
9355 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
9356 #define DMA2D_IFCR_CCTCIF_Pos (4U)
9357 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
9358 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
9359 #define DMA2D_IFCR_CCEIF_Pos (5U)
9360 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
9361 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
9362
9363 /******************** Bit definition for DMA2D_FGMAR register ***************/
9364
9365 #define DMA2D_FGMAR_MA_Pos (0U)
9366 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9367 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
9368
9369 /******************** Bit definition for DMA2D_FGOR register ****************/
9370
9371 #define DMA2D_FGOR_LO_Pos (0U)
9372 #define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
9373 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
9374
9375 /******************** Bit definition for DMA2D_BGMAR register ***************/
9376
9377 #define DMA2D_BGMAR_MA_Pos (0U)
9378 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
9379 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
9380
9381 /******************** Bit definition for DMA2D_BGOR register ****************/
9382
9383 #define DMA2D_BGOR_LO_Pos (0U)
9384 #define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
9385 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
9386
9387 /******************** Bit definition for DMA2D_FGPFCCR register *************/
9388
9389 #define DMA2D_FGPFCCR_CM_Pos (0U)
9390 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
9391 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9392 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
9393 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
9394 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
9395 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
9396 #define DMA2D_FGPFCCR_CCM_Pos (4U)
9397 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
9398 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
9399 #define DMA2D_FGPFCCR_START_Pos (5U)
9400 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
9401 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
9402 #define DMA2D_FGPFCCR_CS_Pos (8U)
9403 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9404 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
9405 #define DMA2D_FGPFCCR_AM_Pos (16U)
9406 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
9407 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9408 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
9409 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
9410 #define DMA2D_FGPFCCR_CSS_Pos (18U)
9411 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
9412 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
9413 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
9414 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
9415 #define DMA2D_FGPFCCR_AI_Pos (20U)
9416 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
9417 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
9418 #define DMA2D_FGPFCCR_RBS_Pos (21U)
9419 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
9420 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
9421 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
9422 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9423 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
9424
9425 /******************** Bit definition for DMA2D_FGCOLR register **************/
9426
9427 #define DMA2D_FGCOLR_BLUE_Pos (0U)
9428 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
9429 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
9430 #define DMA2D_FGCOLR_GREEN_Pos (8U)
9431 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9432 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
9433 #define DMA2D_FGCOLR_RED_Pos (16U)
9434 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
9435 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
9436
9437 /******************** Bit definition for DMA2D_BGPFCCR register *************/
9438
9439 #define DMA2D_BGPFCCR_CM_Pos (0U)
9440 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
9441 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
9442 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
9443 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
9444 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
9445 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
9446 #define DMA2D_BGPFCCR_CCM_Pos (4U)
9447 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
9448 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
9449 #define DMA2D_BGPFCCR_START_Pos (5U)
9450 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
9451 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
9452 #define DMA2D_BGPFCCR_CS_Pos (8U)
9453 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
9454 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
9455 #define DMA2D_BGPFCCR_AM_Pos (16U)
9456 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
9457 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
9458 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
9459 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
9460 #define DMA2D_BGPFCCR_AI_Pos (20U)
9461 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
9462 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
9463 #define DMA2D_BGPFCCR_RBS_Pos (21U)
9464 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
9465 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
9466 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
9467 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
9468 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
9469
9470 /******************** Bit definition for DMA2D_BGCOLR register **************/
9471
9472 #define DMA2D_BGCOLR_BLUE_Pos (0U)
9473 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
9474 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
9475 #define DMA2D_BGCOLR_GREEN_Pos (8U)
9476 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
9477 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
9478 #define DMA2D_BGCOLR_RED_Pos (16U)
9479 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
9480 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
9481
9482 /******************** Bit definition for DMA2D_FGCMAR register **************/
9483
9484 #define DMA2D_FGCMAR_MA_Pos (0U)
9485 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9486 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
9487
9488 /******************** Bit definition for DMA2D_BGCMAR register **************/
9489
9490 #define DMA2D_BGCMAR_MA_Pos (0U)
9491 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
9492 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
9493
9494 /******************** Bit definition for DMA2D_OPFCCR register **************/
9495
9496 #define DMA2D_OPFCCR_CM_Pos (0U)
9497 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
9498 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
9499 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
9500 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
9501 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
9502 #define DMA2D_OPFCCR_SB_Pos (8U)
9503 #define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
9504 #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
9505 #define DMA2D_OPFCCR_AI_Pos (20U)
9506 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
9507 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
9508 #define DMA2D_OPFCCR_RBS_Pos (21U)
9509 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
9510 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
9511
9512 /******************** Bit definition for DMA2D_OCOLR register ***************/
9513
9514 /*!<Mode_ARGB8888/RGB888 */
9515
9516 #define DMA2D_OCOLR_BLUE_1_Pos (0U)
9517 #define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
9518 #define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
9519 #define DMA2D_OCOLR_GREEN_1_Pos (8U)
9520 #define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
9521 #define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
9522 #define DMA2D_OCOLR_RED_1_Pos (16U)
9523 #define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
9524 #define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
9525 #define DMA2D_OCOLR_ALPHA_1_Pos (24U)
9526 #define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
9527 #define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
9528
9529 /*!<Mode_RGB565 */
9530 #define DMA2D_OCOLR_BLUE_2_Pos (0U)
9531 #define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
9532 #define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
9533 #define DMA2D_OCOLR_GREEN_2_Pos (5U)
9534 #define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
9535 #define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
9536 #define DMA2D_OCOLR_RED_2_Pos (11U)
9537 #define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
9538 #define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
9539
9540 /*!<Mode_ARGB1555 */
9541 #define DMA2D_OCOLR_BLUE_3_Pos (0U)
9542 #define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
9543 #define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
9544 #define DMA2D_OCOLR_GREEN_3_Pos (5U)
9545 #define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
9546 #define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
9547 #define DMA2D_OCOLR_RED_3_Pos (10U)
9548 #define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
9549 #define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
9550 #define DMA2D_OCOLR_ALPHA_3_Pos (15U)
9551 #define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
9552 #define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
9553
9554 /*!<Mode_ARGB4444 */
9555 #define DMA2D_OCOLR_BLUE_4_Pos (0U)
9556 #define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
9557 #define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
9558 #define DMA2D_OCOLR_GREEN_4_Pos (4U)
9559 #define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
9560 #define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
9561 #define DMA2D_OCOLR_RED_4_Pos (8U)
9562 #define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
9563 #define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
9564 #define DMA2D_OCOLR_ALPHA_4_Pos (12U)
9565 #define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
9566 #define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
9567
9568 /******************** Bit definition for DMA2D_OMAR register ****************/
9569
9570 #define DMA2D_OMAR_MA_Pos (0U)
9571 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
9572 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
9573
9574 /******************** Bit definition for DMA2D_OOR register *****************/
9575
9576 #define DMA2D_OOR_LO_Pos (0U)
9577 #define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
9578 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
9579
9580 /******************** Bit definition for DMA2D_NLR register *****************/
9581
9582 #define DMA2D_NLR_NL_Pos (0U)
9583 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
9584 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
9585 #define DMA2D_NLR_PL_Pos (16U)
9586 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
9587 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
9588
9589 /******************** Bit definition for DMA2D_LWR register *****************/
9590
9591 #define DMA2D_LWR_LW_Pos (0U)
9592 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
9593 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
9594
9595 /******************** Bit definition for DMA2D_AMTCR register ***************/
9596
9597 #define DMA2D_AMTCR_EN_Pos (0U)
9598 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
9599 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
9600 #define DMA2D_AMTCR_DT_Pos (8U)
9601 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
9602 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
9603
9604
9605 /******************** Bit definition for DMA2D_FGCLUT register **************/
9606
9607 /******************** Bit definition for DMA2D_BGCLUT register **************/
9608
9609 /******************************************************************************/
9610 /* */
9611 /* Display Serial Interface (DSI) */
9612 /* */
9613 /******************************************************************************/
9614 /******************* Bit definition for DSI_VR register *****************/
9615 #define DSI_VR_Pos (1U)
9616 #define DSI_VR_Msk (0x18999815UL << DSI_VR_Pos) /*!< 0x3133302A */
9617 #define DSI_VR DSI_VR_Msk /*!< DSI Host Version */
9618
9619 /******************* Bit definition for DSI_CR register *****************/
9620 #define DSI_CR_EN_Pos (0U)
9621 #define DSI_CR_EN_Msk (0x1UL << DSI_CR_EN_Pos) /*!< 0x00000001 */
9622 #define DSI_CR_EN DSI_CR_EN_Msk /*!< DSI Host power up and reset */
9623
9624 /******************* Bit definition for DSI_CCR register ****************/
9625 #define DSI_CCR_TXECKDIV_Pos (0U)
9626 #define DSI_CCR_TXECKDIV_Msk (0xFFUL << DSI_CCR_TXECKDIV_Pos) /*!< 0x000000FF */
9627 #define DSI_CCR_TXECKDIV DSI_CCR_TXECKDIV_Msk /*!< TX Escape Clock Division */
9628 #define DSI_CCR_TXECKDIV0_Pos (0U)
9629 #define DSI_CCR_TXECKDIV0_Msk (0x1UL << DSI_CCR_TXECKDIV0_Pos) /*!< 0x00000001 */
9630 #define DSI_CCR_TXECKDIV0 DSI_CCR_TXECKDIV0_Msk
9631 #define DSI_CCR_TXECKDIV1_Pos (1U)
9632 #define DSI_CCR_TXECKDIV1_Msk (0x1UL << DSI_CCR_TXECKDIV1_Pos) /*!< 0x00000002 */
9633 #define DSI_CCR_TXECKDIV1 DSI_CCR_TXECKDIV1_Msk
9634 #define DSI_CCR_TXECKDIV2_Pos (2U)
9635 #define DSI_CCR_TXECKDIV2_Msk (0x1UL << DSI_CCR_TXECKDIV2_Pos) /*!< 0x00000004 */
9636 #define DSI_CCR_TXECKDIV2 DSI_CCR_TXECKDIV2_Msk
9637 #define DSI_CCR_TXECKDIV3_Pos (3U)
9638 #define DSI_CCR_TXECKDIV3_Msk (0x1UL << DSI_CCR_TXECKDIV3_Pos) /*!< 0x00000008 */
9639 #define DSI_CCR_TXECKDIV3 DSI_CCR_TXECKDIV3_Msk
9640 #define DSI_CCR_TXECKDIV4_Pos (4U)
9641 #define DSI_CCR_TXECKDIV4_Msk (0x1UL << DSI_CCR_TXECKDIV4_Pos) /*!< 0x00000010 */
9642 #define DSI_CCR_TXECKDIV4 DSI_CCR_TXECKDIV4_Msk
9643 #define DSI_CCR_TXECKDIV5_Pos (5U)
9644 #define DSI_CCR_TXECKDIV5_Msk (0x1UL << DSI_CCR_TXECKDIV5_Pos) /*!< 0x00000020 */
9645 #define DSI_CCR_TXECKDIV5 DSI_CCR_TXECKDIV5_Msk
9646 #define DSI_CCR_TXECKDIV6_Pos (6U)
9647 #define DSI_CCR_TXECKDIV6_Msk (0x1UL << DSI_CCR_TXECKDIV6_Pos) /*!< 0x00000040 */
9648 #define DSI_CCR_TXECKDIV6 DSI_CCR_TXECKDIV6_Msk
9649 #define DSI_CCR_TXECKDIV7_Pos (7U)
9650 #define DSI_CCR_TXECKDIV7_Msk (0x1UL << DSI_CCR_TXECKDIV7_Pos) /*!< 0x00000080 */
9651 #define DSI_CCR_TXECKDIV7 DSI_CCR_TXECKDIV7_Msk
9652
9653 #define DSI_CCR_TOCKDIV_Pos (8U)
9654 #define DSI_CCR_TOCKDIV_Msk (0xFFUL << DSI_CCR_TOCKDIV_Pos) /*!< 0x0000FF00 */
9655 #define DSI_CCR_TOCKDIV DSI_CCR_TOCKDIV_Msk /*!< Timeout Clock Division */
9656 #define DSI_CCR_TOCKDIV0_Pos (8U)
9657 #define DSI_CCR_TOCKDIV0_Msk (0x1UL << DSI_CCR_TOCKDIV0_Pos) /*!< 0x00000100 */
9658 #define DSI_CCR_TOCKDIV0 DSI_CCR_TOCKDIV0_Msk
9659 #define DSI_CCR_TOCKDIV1_Pos (9U)
9660 #define DSI_CCR_TOCKDIV1_Msk (0x1UL << DSI_CCR_TOCKDIV1_Pos) /*!< 0x00000200 */
9661 #define DSI_CCR_TOCKDIV1 DSI_CCR_TOCKDIV1_Msk
9662 #define DSI_CCR_TOCKDIV2_Pos (10U)
9663 #define DSI_CCR_TOCKDIV2_Msk (0x1UL << DSI_CCR_TOCKDIV2_Pos) /*!< 0x00000400 */
9664 #define DSI_CCR_TOCKDIV2 DSI_CCR_TOCKDIV2_Msk
9665 #define DSI_CCR_TOCKDIV3_Pos (11U)
9666 #define DSI_CCR_TOCKDIV3_Msk (0x1UL << DSI_CCR_TOCKDIV3_Pos) /*!< 0x00000800 */
9667 #define DSI_CCR_TOCKDIV3 DSI_CCR_TOCKDIV3_Msk
9668 #define DSI_CCR_TOCKDIV4_Pos (12U)
9669 #define DSI_CCR_TOCKDIV4_Msk (0x1UL << DSI_CCR_TOCKDIV4_Pos) /*!< 0x00001000 */
9670 #define DSI_CCR_TOCKDIV4 DSI_CCR_TOCKDIV4_Msk
9671 #define DSI_CCR_TOCKDIV5_Pos (13U)
9672 #define DSI_CCR_TOCKDIV5_Msk (0x1UL << DSI_CCR_TOCKDIV5_Pos) /*!< 0x00002000 */
9673 #define DSI_CCR_TOCKDIV5 DSI_CCR_TOCKDIV5_Msk
9674 #define DSI_CCR_TOCKDIV6_Pos (14U)
9675 #define DSI_CCR_TOCKDIV6_Msk (0x1UL << DSI_CCR_TOCKDIV6_Pos) /*!< 0x00004000 */
9676 #define DSI_CCR_TOCKDIV6 DSI_CCR_TOCKDIV6_Msk
9677 #define DSI_CCR_TOCKDIV7_Pos (15U)
9678 #define DSI_CCR_TOCKDIV7_Msk (0x1UL << DSI_CCR_TOCKDIV7_Pos) /*!< 0x00008000 */
9679 #define DSI_CCR_TOCKDIV7 DSI_CCR_TOCKDIV7_Msk
9680
9681 /******************* Bit definition for DSI_LVCIDR register *************/
9682 #define DSI_LVCIDR_VCID_Pos (0U)
9683 #define DSI_LVCIDR_VCID_Msk (0x3UL << DSI_LVCIDR_VCID_Pos) /*!< 0x00000003 */
9684 #define DSI_LVCIDR_VCID DSI_LVCIDR_VCID_Msk /*!< Virtual Channel ID */
9685 #define DSI_LVCIDR_VCID0_Pos (0U)
9686 #define DSI_LVCIDR_VCID0_Msk (0x1UL << DSI_LVCIDR_VCID0_Pos) /*!< 0x00000001 */
9687 #define DSI_LVCIDR_VCID0 DSI_LVCIDR_VCID0_Msk
9688 #define DSI_LVCIDR_VCID1_Pos (1U)
9689 #define DSI_LVCIDR_VCID1_Msk (0x1UL << DSI_LVCIDR_VCID1_Pos) /*!< 0x00000002 */
9690 #define DSI_LVCIDR_VCID1 DSI_LVCIDR_VCID1_Msk
9691
9692 /******************* Bit definition for DSI_LCOLCR register *************/
9693 #define DSI_LCOLCR_COLC_Pos (0U)
9694 #define DSI_LCOLCR_COLC_Msk (0xFUL << DSI_LCOLCR_COLC_Pos) /*!< 0x0000000F */
9695 #define DSI_LCOLCR_COLC DSI_LCOLCR_COLC_Msk /*!< Color Coding */
9696 #define DSI_LCOLCR_COLC0_Pos (0U)
9697 #define DSI_LCOLCR_COLC0_Msk (0x1UL << DSI_LCOLCR_COLC0_Pos) /*!< 0x00000001 */
9698 #define DSI_LCOLCR_COLC0 DSI_LCOLCR_COLC0_Msk
9699 #define DSI_LCOLCR_COLC1_Pos (5U)
9700 #define DSI_LCOLCR_COLC1_Msk (0x1UL << DSI_LCOLCR_COLC1_Pos) /*!< 0x00000020 */
9701 #define DSI_LCOLCR_COLC1 DSI_LCOLCR_COLC1_Msk
9702 #define DSI_LCOLCR_COLC2_Pos (6U)
9703 #define DSI_LCOLCR_COLC2_Msk (0x1UL << DSI_LCOLCR_COLC2_Pos) /*!< 0x00000040 */
9704 #define DSI_LCOLCR_COLC2 DSI_LCOLCR_COLC2_Msk
9705 #define DSI_LCOLCR_COLC3_Pos (7U)
9706 #define DSI_LCOLCR_COLC3_Msk (0x1UL << DSI_LCOLCR_COLC3_Pos) /*!< 0x00000080 */
9707 #define DSI_LCOLCR_COLC3 DSI_LCOLCR_COLC3_Msk
9708
9709 #define DSI_LCOLCR_LPE_Pos (8U)
9710 #define DSI_LCOLCR_LPE_Msk (0x1UL << DSI_LCOLCR_LPE_Pos) /*!< 0x00000100 */
9711 #define DSI_LCOLCR_LPE DSI_LCOLCR_LPE_Msk /*!< Loosly Packet Enable */
9712
9713 /******************* Bit definition for DSI_LPCR register ***************/
9714 #define DSI_LPCR_DEP_Pos (0U)
9715 #define DSI_LPCR_DEP_Msk (0x1UL << DSI_LPCR_DEP_Pos) /*!< 0x00000001 */
9716 #define DSI_LPCR_DEP DSI_LPCR_DEP_Msk /*!< Data Enable Polarity */
9717 #define DSI_LPCR_VSP_Pos (1U)
9718 #define DSI_LPCR_VSP_Msk (0x1UL << DSI_LPCR_VSP_Pos) /*!< 0x00000002 */
9719 #define DSI_LPCR_VSP DSI_LPCR_VSP_Msk /*!< VSYNC Polarity */
9720 #define DSI_LPCR_HSP_Pos (2U)
9721 #define DSI_LPCR_HSP_Msk (0x1UL << DSI_LPCR_HSP_Pos) /*!< 0x00000004 */
9722 #define DSI_LPCR_HSP DSI_LPCR_HSP_Msk /*!< HSYNC Polarity */
9723
9724 /******************* Bit definition for DSI_LPMCR register **************/
9725 #define DSI_LPMCR_VLPSIZE_Pos (0U)
9726 #define DSI_LPMCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCR_VLPSIZE_Pos) /*!< 0x000000FF */
9727 #define DSI_LPMCR_VLPSIZE DSI_LPMCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
9728 #define DSI_LPMCR_VLPSIZE0_Pos (0U)
9729 #define DSI_LPMCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCR_VLPSIZE0_Pos) /*!< 0x00000001 */
9730 #define DSI_LPMCR_VLPSIZE0 DSI_LPMCR_VLPSIZE0_Msk
9731 #define DSI_LPMCR_VLPSIZE1_Pos (1U)
9732 #define DSI_LPMCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCR_VLPSIZE1_Pos) /*!< 0x00000002 */
9733 #define DSI_LPMCR_VLPSIZE1 DSI_LPMCR_VLPSIZE1_Msk
9734 #define DSI_LPMCR_VLPSIZE2_Pos (2U)
9735 #define DSI_LPMCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCR_VLPSIZE2_Pos) /*!< 0x00000004 */
9736 #define DSI_LPMCR_VLPSIZE2 DSI_LPMCR_VLPSIZE2_Msk
9737 #define DSI_LPMCR_VLPSIZE3_Pos (3U)
9738 #define DSI_LPMCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCR_VLPSIZE3_Pos) /*!< 0x00000008 */
9739 #define DSI_LPMCR_VLPSIZE3 DSI_LPMCR_VLPSIZE3_Msk
9740 #define DSI_LPMCR_VLPSIZE4_Pos (4U)
9741 #define DSI_LPMCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCR_VLPSIZE4_Pos) /*!< 0x00000010 */
9742 #define DSI_LPMCR_VLPSIZE4 DSI_LPMCR_VLPSIZE4_Msk
9743 #define DSI_LPMCR_VLPSIZE5_Pos (5U)
9744 #define DSI_LPMCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCR_VLPSIZE5_Pos) /*!< 0x00000020 */
9745 #define DSI_LPMCR_VLPSIZE5 DSI_LPMCR_VLPSIZE5_Msk
9746 #define DSI_LPMCR_VLPSIZE6_Pos (6U)
9747 #define DSI_LPMCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCR_VLPSIZE6_Pos) /*!< 0x00000040 */
9748 #define DSI_LPMCR_VLPSIZE6 DSI_LPMCR_VLPSIZE6_Msk
9749 #define DSI_LPMCR_VLPSIZE7_Pos (7U)
9750 #define DSI_LPMCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCR_VLPSIZE7_Pos) /*!< 0x00000080 */
9751 #define DSI_LPMCR_VLPSIZE7 DSI_LPMCR_VLPSIZE7_Msk
9752
9753 #define DSI_LPMCR_LPSIZE_Pos (16U)
9754 #define DSI_LPMCR_LPSIZE_Msk (0xFFUL << DSI_LPMCR_LPSIZE_Pos) /*!< 0x00FF0000 */
9755 #define DSI_LPMCR_LPSIZE DSI_LPMCR_LPSIZE_Msk /*!< Largest Packet Size */
9756 #define DSI_LPMCR_LPSIZE0_Pos (16U)
9757 #define DSI_LPMCR_LPSIZE0_Msk (0x1UL << DSI_LPMCR_LPSIZE0_Pos) /*!< 0x00010000 */
9758 #define DSI_LPMCR_LPSIZE0 DSI_LPMCR_LPSIZE0_Msk
9759 #define DSI_LPMCR_LPSIZE1_Pos (17U)
9760 #define DSI_LPMCR_LPSIZE1_Msk (0x1UL << DSI_LPMCR_LPSIZE1_Pos) /*!< 0x00020000 */
9761 #define DSI_LPMCR_LPSIZE1 DSI_LPMCR_LPSIZE1_Msk
9762 #define DSI_LPMCR_LPSIZE2_Pos (18U)
9763 #define DSI_LPMCR_LPSIZE2_Msk (0x1UL << DSI_LPMCR_LPSIZE2_Pos) /*!< 0x00040000 */
9764 #define DSI_LPMCR_LPSIZE2 DSI_LPMCR_LPSIZE2_Msk
9765 #define DSI_LPMCR_LPSIZE3_Pos (19U)
9766 #define DSI_LPMCR_LPSIZE3_Msk (0x1UL << DSI_LPMCR_LPSIZE3_Pos) /*!< 0x00080000 */
9767 #define DSI_LPMCR_LPSIZE3 DSI_LPMCR_LPSIZE3_Msk
9768 #define DSI_LPMCR_LPSIZE4_Pos (20U)
9769 #define DSI_LPMCR_LPSIZE4_Msk (0x1UL << DSI_LPMCR_LPSIZE4_Pos) /*!< 0x00100000 */
9770 #define DSI_LPMCR_LPSIZE4 DSI_LPMCR_LPSIZE4_Msk
9771 #define DSI_LPMCR_LPSIZE5_Pos (21U)
9772 #define DSI_LPMCR_LPSIZE5_Msk (0x1UL << DSI_LPMCR_LPSIZE5_Pos) /*!< 0x00200000 */
9773 #define DSI_LPMCR_LPSIZE5 DSI_LPMCR_LPSIZE5_Msk
9774 #define DSI_LPMCR_LPSIZE6_Pos (22U)
9775 #define DSI_LPMCR_LPSIZE6_Msk (0x1UL << DSI_LPMCR_LPSIZE6_Pos) /*!< 0x00400000 */
9776 #define DSI_LPMCR_LPSIZE6 DSI_LPMCR_LPSIZE6_Msk
9777 #define DSI_LPMCR_LPSIZE7_Pos (23U)
9778 #define DSI_LPMCR_LPSIZE7_Msk (0x1UL << DSI_LPMCR_LPSIZE7_Pos) /*!< 0x00800000 */
9779 #define DSI_LPMCR_LPSIZE7 DSI_LPMCR_LPSIZE7_Msk
9780
9781 /******************* Bit definition for DSI_PCR register ****************/
9782 #define DSI_PCR_ETTXE_Pos (0U)
9783 #define DSI_PCR_ETTXE_Msk (0x1UL << DSI_PCR_ETTXE_Pos) /*!< 0x00000001 */
9784 #define DSI_PCR_ETTXE DSI_PCR_ETTXE_Msk /*!< EoTp Transmission Enable */
9785 #define DSI_PCR_ETRXE_Pos (1U)
9786 #define DSI_PCR_ETRXE_Msk (0x1UL << DSI_PCR_ETRXE_Pos) /*!< 0x00000002 */
9787 #define DSI_PCR_ETRXE DSI_PCR_ETRXE_Msk /*!< EoTp Reception Enable */
9788 #define DSI_PCR_BTAE_Pos (2U)
9789 #define DSI_PCR_BTAE_Msk (0x1UL << DSI_PCR_BTAE_Pos) /*!< 0x00000004 */
9790 #define DSI_PCR_BTAE DSI_PCR_BTAE_Msk /*!< Bus Turn Around Enable */
9791 #define DSI_PCR_ECCRXE_Pos (3U)
9792 #define DSI_PCR_ECCRXE_Msk (0x1UL << DSI_PCR_ECCRXE_Pos) /*!< 0x00000008 */
9793 #define DSI_PCR_ECCRXE DSI_PCR_ECCRXE_Msk /*!< ECC Reception Enable */
9794 #define DSI_PCR_CRCRXE_Pos (4U)
9795 #define DSI_PCR_CRCRXE_Msk (0x1UL << DSI_PCR_CRCRXE_Pos) /*!< 0x00000010 */
9796 #define DSI_PCR_CRCRXE DSI_PCR_CRCRXE_Msk /*!< CRC Reception Enable */
9797
9798 /******************* Bit definition for DSI_GVCIDR register *************/
9799 #define DSI_GVCIDR_VCID_Pos (0U)
9800 #define DSI_GVCIDR_VCID_Msk (0x3UL << DSI_GVCIDR_VCID_Pos) /*!< 0x00000003 */
9801 #define DSI_GVCIDR_VCID DSI_GVCIDR_VCID_Msk /*!< Virtual Channel ID */
9802 #define DSI_GVCIDR_VCID0_Pos (0U)
9803 #define DSI_GVCIDR_VCID0_Msk (0x1UL << DSI_GVCIDR_VCID0_Pos) /*!< 0x00000001 */
9804 #define DSI_GVCIDR_VCID0 DSI_GVCIDR_VCID0_Msk
9805 #define DSI_GVCIDR_VCID1_Pos (1U)
9806 #define DSI_GVCIDR_VCID1_Msk (0x1UL << DSI_GVCIDR_VCID1_Pos) /*!< 0x00000002 */
9807 #define DSI_GVCIDR_VCID1 DSI_GVCIDR_VCID1_Msk
9808
9809 /******************* Bit definition for DSI_MCR register ****************/
9810 #define DSI_MCR_CMDM_Pos (0U)
9811 #define DSI_MCR_CMDM_Msk (0x1UL << DSI_MCR_CMDM_Pos) /*!< 0x00000001 */
9812 #define DSI_MCR_CMDM DSI_MCR_CMDM_Msk /*!< Command Mode */
9813
9814 /******************* Bit definition for DSI_VMCR register ***************/
9815 #define DSI_VMCR_VMT_Pos (0U)
9816 #define DSI_VMCR_VMT_Msk (0x3UL << DSI_VMCR_VMT_Pos) /*!< 0x00000003 */
9817 #define DSI_VMCR_VMT DSI_VMCR_VMT_Msk /*!< Video Mode Type */
9818 #define DSI_VMCR_VMT0_Pos (0U)
9819 #define DSI_VMCR_VMT0_Msk (0x1UL << DSI_VMCR_VMT0_Pos) /*!< 0x00000001 */
9820 #define DSI_VMCR_VMT0 DSI_VMCR_VMT0_Msk
9821 #define DSI_VMCR_VMT1_Pos (1U)
9822 #define DSI_VMCR_VMT1_Msk (0x1UL << DSI_VMCR_VMT1_Pos) /*!< 0x00000002 */
9823 #define DSI_VMCR_VMT1 DSI_VMCR_VMT1_Msk
9824
9825 #define DSI_VMCR_LPVSAE_Pos (8U)
9826 #define DSI_VMCR_LPVSAE_Msk (0x1UL << DSI_VMCR_LPVSAE_Pos) /*!< 0x00000100 */
9827 #define DSI_VMCR_LPVSAE DSI_VMCR_LPVSAE_Msk /*!< Low-Power Vertical Sync Active Enable */
9828 #define DSI_VMCR_LPVBPE_Pos (9U)
9829 #define DSI_VMCR_LPVBPE_Msk (0x1UL << DSI_VMCR_LPVBPE_Pos) /*!< 0x00000200 */
9830 #define DSI_VMCR_LPVBPE DSI_VMCR_LPVBPE_Msk /*!< Low-power Vertical Back-Porch Enable */
9831 #define DSI_VMCR_LPVFPE_Pos (10U)
9832 #define DSI_VMCR_LPVFPE_Msk (0x1UL << DSI_VMCR_LPVFPE_Pos) /*!< 0x00000400 */
9833 #define DSI_VMCR_LPVFPE DSI_VMCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
9834 #define DSI_VMCR_LPVAE_Pos (11U)
9835 #define DSI_VMCR_LPVAE_Msk (0x1UL << DSI_VMCR_LPVAE_Pos) /*!< 0x00000800 */
9836 #define DSI_VMCR_LPVAE DSI_VMCR_LPVAE_Msk /*!< Low-Power Vertical Active Enable */
9837 #define DSI_VMCR_LPHBPE_Pos (12U)
9838 #define DSI_VMCR_LPHBPE_Msk (0x1UL << DSI_VMCR_LPHBPE_Pos) /*!< 0x00001000 */
9839 #define DSI_VMCR_LPHBPE DSI_VMCR_LPHBPE_Msk /*!< Low-Power Horizontal Back-Porch Enable */
9840 #define DSI_VMCR_LPHFPE_Pos (13U)
9841 #define DSI_VMCR_LPHFPE_Msk (0x1UL << DSI_VMCR_LPHFPE_Pos) /*!< 0x00002000 */
9842 #define DSI_VMCR_LPHFPE DSI_VMCR_LPHFPE_Msk /*!< Low-Power Horizontal Front-Porch Enable */
9843 #define DSI_VMCR_FBTAAE_Pos (14U)
9844 #define DSI_VMCR_FBTAAE_Msk (0x1UL << DSI_VMCR_FBTAAE_Pos) /*!< 0x00004000 */
9845 #define DSI_VMCR_FBTAAE DSI_VMCR_FBTAAE_Msk /*!< Frame Bus-Turn-Around Acknowledge Enable */
9846 #define DSI_VMCR_LPCE_Pos (15U)
9847 #define DSI_VMCR_LPCE_Msk (0x1UL << DSI_VMCR_LPCE_Pos) /*!< 0x00008000 */
9848 #define DSI_VMCR_LPCE DSI_VMCR_LPCE_Msk /*!< Low-Power Command Enable */
9849 #define DSI_VMCR_PGE_Pos (16U)
9850 #define DSI_VMCR_PGE_Msk (0x1UL << DSI_VMCR_PGE_Pos) /*!< 0x00010000 */
9851 #define DSI_VMCR_PGE DSI_VMCR_PGE_Msk /*!< Pattern Generator Enable */
9852 #define DSI_VMCR_PGM_Pos (20U)
9853 #define DSI_VMCR_PGM_Msk (0x1UL << DSI_VMCR_PGM_Pos) /*!< 0x00100000 */
9854 #define DSI_VMCR_PGM DSI_VMCR_PGM_Msk /*!< Pattern Generator Mode */
9855 #define DSI_VMCR_PGO_Pos (24U)
9856 #define DSI_VMCR_PGO_Msk (0x1UL << DSI_VMCR_PGO_Pos) /*!< 0x01000000 */
9857 #define DSI_VMCR_PGO DSI_VMCR_PGO_Msk /*!< Pattern Generator Orientation */
9858
9859 /******************* Bit definition for DSI_VPCR register ***************/
9860 #define DSI_VPCR_VPSIZE_Pos (0U)
9861 #define DSI_VPCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCR_VPSIZE_Pos) /*!< 0x00003FFF */
9862 #define DSI_VPCR_VPSIZE DSI_VPCR_VPSIZE_Msk /*!< Video Packet Size */
9863 #define DSI_VPCR_VPSIZE0_Pos (0U)
9864 #define DSI_VPCR_VPSIZE0_Msk (0x1UL << DSI_VPCR_VPSIZE0_Pos) /*!< 0x00000001 */
9865 #define DSI_VPCR_VPSIZE0 DSI_VPCR_VPSIZE0_Msk
9866 #define DSI_VPCR_VPSIZE1_Pos (1U)
9867 #define DSI_VPCR_VPSIZE1_Msk (0x1UL << DSI_VPCR_VPSIZE1_Pos) /*!< 0x00000002 */
9868 #define DSI_VPCR_VPSIZE1 DSI_VPCR_VPSIZE1_Msk
9869 #define DSI_VPCR_VPSIZE2_Pos (2U)
9870 #define DSI_VPCR_VPSIZE2_Msk (0x1UL << DSI_VPCR_VPSIZE2_Pos) /*!< 0x00000004 */
9871 #define DSI_VPCR_VPSIZE2 DSI_VPCR_VPSIZE2_Msk
9872 #define DSI_VPCR_VPSIZE3_Pos (3U)
9873 #define DSI_VPCR_VPSIZE3_Msk (0x1UL << DSI_VPCR_VPSIZE3_Pos) /*!< 0x00000008 */
9874 #define DSI_VPCR_VPSIZE3 DSI_VPCR_VPSIZE3_Msk
9875 #define DSI_VPCR_VPSIZE4_Pos (4U)
9876 #define DSI_VPCR_VPSIZE4_Msk (0x1UL << DSI_VPCR_VPSIZE4_Pos) /*!< 0x00000010 */
9877 #define DSI_VPCR_VPSIZE4 DSI_VPCR_VPSIZE4_Msk
9878 #define DSI_VPCR_VPSIZE5_Pos (5U)
9879 #define DSI_VPCR_VPSIZE5_Msk (0x1UL << DSI_VPCR_VPSIZE5_Pos) /*!< 0x00000020 */
9880 #define DSI_VPCR_VPSIZE5 DSI_VPCR_VPSIZE5_Msk
9881 #define DSI_VPCR_VPSIZE6_Pos (6U)
9882 #define DSI_VPCR_VPSIZE6_Msk (0x1UL << DSI_VPCR_VPSIZE6_Pos) /*!< 0x00000040 */
9883 #define DSI_VPCR_VPSIZE6 DSI_VPCR_VPSIZE6_Msk
9884 #define DSI_VPCR_VPSIZE7_Pos (7U)
9885 #define DSI_VPCR_VPSIZE7_Msk (0x1UL << DSI_VPCR_VPSIZE7_Pos) /*!< 0x00000080 */
9886 #define DSI_VPCR_VPSIZE7 DSI_VPCR_VPSIZE7_Msk
9887 #define DSI_VPCR_VPSIZE8_Pos (8U)
9888 #define DSI_VPCR_VPSIZE8_Msk (0x1UL << DSI_VPCR_VPSIZE8_Pos) /*!< 0x00000100 */
9889 #define DSI_VPCR_VPSIZE8 DSI_VPCR_VPSIZE8_Msk
9890 #define DSI_VPCR_VPSIZE9_Pos (9U)
9891 #define DSI_VPCR_VPSIZE9_Msk (0x1UL << DSI_VPCR_VPSIZE9_Pos) /*!< 0x00000200 */
9892 #define DSI_VPCR_VPSIZE9 DSI_VPCR_VPSIZE9_Msk
9893 #define DSI_VPCR_VPSIZE10_Pos (10U)
9894 #define DSI_VPCR_VPSIZE10_Msk (0x1UL << DSI_VPCR_VPSIZE10_Pos) /*!< 0x00000400 */
9895 #define DSI_VPCR_VPSIZE10 DSI_VPCR_VPSIZE10_Msk
9896 #define DSI_VPCR_VPSIZE11_Pos (11U)
9897 #define DSI_VPCR_VPSIZE11_Msk (0x1UL << DSI_VPCR_VPSIZE11_Pos) /*!< 0x00000800 */
9898 #define DSI_VPCR_VPSIZE11 DSI_VPCR_VPSIZE11_Msk
9899 #define DSI_VPCR_VPSIZE12_Pos (12U)
9900 #define DSI_VPCR_VPSIZE12_Msk (0x1UL << DSI_VPCR_VPSIZE12_Pos) /*!< 0x00001000 */
9901 #define DSI_VPCR_VPSIZE12 DSI_VPCR_VPSIZE12_Msk
9902 #define DSI_VPCR_VPSIZE13_Pos (13U)
9903 #define DSI_VPCR_VPSIZE13_Msk (0x1UL << DSI_VPCR_VPSIZE13_Pos) /*!< 0x00002000 */
9904 #define DSI_VPCR_VPSIZE13 DSI_VPCR_VPSIZE13_Msk
9905
9906 /******************* Bit definition for DSI_VCCR register ***************/
9907 #define DSI_VCCR_NUMC_Pos (0U)
9908 #define DSI_VCCR_NUMC_Msk (0x1FFFUL << DSI_VCCR_NUMC_Pos) /*!< 0x00001FFF */
9909 #define DSI_VCCR_NUMC DSI_VCCR_NUMC_Msk /*!< Number of Chunks */
9910 #define DSI_VCCR_NUMC0_Pos (0U)
9911 #define DSI_VCCR_NUMC0_Msk (0x1UL << DSI_VCCR_NUMC0_Pos) /*!< 0x00000001 */
9912 #define DSI_VCCR_NUMC0 DSI_VCCR_NUMC0_Msk
9913 #define DSI_VCCR_NUMC1_Pos (1U)
9914 #define DSI_VCCR_NUMC1_Msk (0x1UL << DSI_VCCR_NUMC1_Pos) /*!< 0x00000002 */
9915 #define DSI_VCCR_NUMC1 DSI_VCCR_NUMC1_Msk
9916 #define DSI_VCCR_NUMC2_Pos (2U)
9917 #define DSI_VCCR_NUMC2_Msk (0x1UL << DSI_VCCR_NUMC2_Pos) /*!< 0x00000004 */
9918 #define DSI_VCCR_NUMC2 DSI_VCCR_NUMC2_Msk
9919 #define DSI_VCCR_NUMC3_Pos (3U)
9920 #define DSI_VCCR_NUMC3_Msk (0x1UL << DSI_VCCR_NUMC3_Pos) /*!< 0x00000008 */
9921 #define DSI_VCCR_NUMC3 DSI_VCCR_NUMC3_Msk
9922 #define DSI_VCCR_NUMC4_Pos (4U)
9923 #define DSI_VCCR_NUMC4_Msk (0x1UL << DSI_VCCR_NUMC4_Pos) /*!< 0x00000010 */
9924 #define DSI_VCCR_NUMC4 DSI_VCCR_NUMC4_Msk
9925 #define DSI_VCCR_NUMC5_Pos (5U)
9926 #define DSI_VCCR_NUMC5_Msk (0x1UL << DSI_VCCR_NUMC5_Pos) /*!< 0x00000020 */
9927 #define DSI_VCCR_NUMC5 DSI_VCCR_NUMC5_Msk
9928 #define DSI_VCCR_NUMC6_Pos (6U)
9929 #define DSI_VCCR_NUMC6_Msk (0x1UL << DSI_VCCR_NUMC6_Pos) /*!< 0x00000040 */
9930 #define DSI_VCCR_NUMC6 DSI_VCCR_NUMC6_Msk
9931 #define DSI_VCCR_NUMC7_Pos (7U)
9932 #define DSI_VCCR_NUMC7_Msk (0x1UL << DSI_VCCR_NUMC7_Pos) /*!< 0x00000080 */
9933 #define DSI_VCCR_NUMC7 DSI_VCCR_NUMC7_Msk
9934 #define DSI_VCCR_NUMC8_Pos (8U)
9935 #define DSI_VCCR_NUMC8_Msk (0x1UL << DSI_VCCR_NUMC8_Pos) /*!< 0x00000100 */
9936 #define DSI_VCCR_NUMC8 DSI_VCCR_NUMC8_Msk
9937 #define DSI_VCCR_NUMC9_Pos (9U)
9938 #define DSI_VCCR_NUMC9_Msk (0x1UL << DSI_VCCR_NUMC9_Pos) /*!< 0x00000200 */
9939 #define DSI_VCCR_NUMC9 DSI_VCCR_NUMC9_Msk
9940 #define DSI_VCCR_NUMC10_Pos (10U)
9941 #define DSI_VCCR_NUMC10_Msk (0x1UL << DSI_VCCR_NUMC10_Pos) /*!< 0x00000400 */
9942 #define DSI_VCCR_NUMC10 DSI_VCCR_NUMC10_Msk
9943 #define DSI_VCCR_NUMC11_Pos (11U)
9944 #define DSI_VCCR_NUMC11_Msk (0x1UL << DSI_VCCR_NUMC11_Pos) /*!< 0x00000800 */
9945 #define DSI_VCCR_NUMC11 DSI_VCCR_NUMC11_Msk
9946 #define DSI_VCCR_NUMC12_Pos (12U)
9947 #define DSI_VCCR_NUMC12_Msk (0x1UL << DSI_VCCR_NUMC12_Pos) /*!< 0x00001000 */
9948 #define DSI_VCCR_NUMC12 DSI_VCCR_NUMC12_Msk
9949
9950 /******************* Bit definition for DSI_VNPCR register **************/
9951 #define DSI_VNPCR_NPSIZE_Pos (0U)
9952 #define DSI_VNPCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCR_NPSIZE_Pos) /*!< 0x00001FFF */
9953 #define DSI_VNPCR_NPSIZE DSI_VNPCR_NPSIZE_Msk /*!< Null Packet Size */
9954 #define DSI_VNPCR_NPSIZE0_Pos (0U)
9955 #define DSI_VNPCR_NPSIZE0_Msk (0x1UL << DSI_VNPCR_NPSIZE0_Pos) /*!< 0x00000001 */
9956 #define DSI_VNPCR_NPSIZE0 DSI_VNPCR_NPSIZE0_Msk
9957 #define DSI_VNPCR_NPSIZE1_Pos (1U)
9958 #define DSI_VNPCR_NPSIZE1_Msk (0x1UL << DSI_VNPCR_NPSIZE1_Pos) /*!< 0x00000002 */
9959 #define DSI_VNPCR_NPSIZE1 DSI_VNPCR_NPSIZE1_Msk
9960 #define DSI_VNPCR_NPSIZE2_Pos (2U)
9961 #define DSI_VNPCR_NPSIZE2_Msk (0x1UL << DSI_VNPCR_NPSIZE2_Pos) /*!< 0x00000004 */
9962 #define DSI_VNPCR_NPSIZE2 DSI_VNPCR_NPSIZE2_Msk
9963 #define DSI_VNPCR_NPSIZE3_Pos (3U)
9964 #define DSI_VNPCR_NPSIZE3_Msk (0x1UL << DSI_VNPCR_NPSIZE3_Pos) /*!< 0x00000008 */
9965 #define DSI_VNPCR_NPSIZE3 DSI_VNPCR_NPSIZE3_Msk
9966 #define DSI_VNPCR_NPSIZE4_Pos (4U)
9967 #define DSI_VNPCR_NPSIZE4_Msk (0x1UL << DSI_VNPCR_NPSIZE4_Pos) /*!< 0x00000010 */
9968 #define DSI_VNPCR_NPSIZE4 DSI_VNPCR_NPSIZE4_Msk
9969 #define DSI_VNPCR_NPSIZE5_Pos (5U)
9970 #define DSI_VNPCR_NPSIZE5_Msk (0x1UL << DSI_VNPCR_NPSIZE5_Pos) /*!< 0x00000020 */
9971 #define DSI_VNPCR_NPSIZE5 DSI_VNPCR_NPSIZE5_Msk
9972 #define DSI_VNPCR_NPSIZE6_Pos (6U)
9973 #define DSI_VNPCR_NPSIZE6_Msk (0x1UL << DSI_VNPCR_NPSIZE6_Pos) /*!< 0x00000040 */
9974 #define DSI_VNPCR_NPSIZE6 DSI_VNPCR_NPSIZE6_Msk
9975 #define DSI_VNPCR_NPSIZE7_Pos (7U)
9976 #define DSI_VNPCR_NPSIZE7_Msk (0x1UL << DSI_VNPCR_NPSIZE7_Pos) /*!< 0x00000080 */
9977 #define DSI_VNPCR_NPSIZE7 DSI_VNPCR_NPSIZE7_Msk
9978 #define DSI_VNPCR_NPSIZE8_Pos (8U)
9979 #define DSI_VNPCR_NPSIZE8_Msk (0x1UL << DSI_VNPCR_NPSIZE8_Pos) /*!< 0x00000100 */
9980 #define DSI_VNPCR_NPSIZE8 DSI_VNPCR_NPSIZE8_Msk
9981 #define DSI_VNPCR_NPSIZE9_Pos (9U)
9982 #define DSI_VNPCR_NPSIZE9_Msk (0x1UL << DSI_VNPCR_NPSIZE9_Pos) /*!< 0x00000200 */
9983 #define DSI_VNPCR_NPSIZE9 DSI_VNPCR_NPSIZE9_Msk
9984 #define DSI_VNPCR_NPSIZE10_Pos (10U)
9985 #define DSI_VNPCR_NPSIZE10_Msk (0x1UL << DSI_VNPCR_NPSIZE10_Pos) /*!< 0x00000400 */
9986 #define DSI_VNPCR_NPSIZE10 DSI_VNPCR_NPSIZE10_Msk
9987 #define DSI_VNPCR_NPSIZE11_Pos (11U)
9988 #define DSI_VNPCR_NPSIZE11_Msk (0x1UL << DSI_VNPCR_NPSIZE11_Pos) /*!< 0x00000800 */
9989 #define DSI_VNPCR_NPSIZE11 DSI_VNPCR_NPSIZE11_Msk
9990 #define DSI_VNPCR_NPSIZE12_Pos (12U)
9991 #define DSI_VNPCR_NPSIZE12_Msk (0x1UL << DSI_VNPCR_NPSIZE12_Pos) /*!< 0x00001000 */
9992 #define DSI_VNPCR_NPSIZE12 DSI_VNPCR_NPSIZE12_Msk
9993
9994 /******************* Bit definition for DSI_VHSACR register *************/
9995 #define DSI_VHSACR_HSA_Pos (0U)
9996 #define DSI_VHSACR_HSA_Msk (0xFFFUL << DSI_VHSACR_HSA_Pos) /*!< 0x00000FFF */
9997 #define DSI_VHSACR_HSA DSI_VHSACR_HSA_Msk /*!< Horizontal Synchronism Active duration */
9998 #define DSI_VHSACR_HSA0_Pos (0U)
9999 #define DSI_VHSACR_HSA0_Msk (0x1UL << DSI_VHSACR_HSA0_Pos) /*!< 0x00000001 */
10000 #define DSI_VHSACR_HSA0 DSI_VHSACR_HSA0_Msk
10001 #define DSI_VHSACR_HSA1_Pos (1U)
10002 #define DSI_VHSACR_HSA1_Msk (0x1UL << DSI_VHSACR_HSA1_Pos) /*!< 0x00000002 */
10003 #define DSI_VHSACR_HSA1 DSI_VHSACR_HSA1_Msk
10004 #define DSI_VHSACR_HSA2_Pos (2U)
10005 #define DSI_VHSACR_HSA2_Msk (0x1UL << DSI_VHSACR_HSA2_Pos) /*!< 0x00000004 */
10006 #define DSI_VHSACR_HSA2 DSI_VHSACR_HSA2_Msk
10007 #define DSI_VHSACR_HSA3_Pos (3U)
10008 #define DSI_VHSACR_HSA3_Msk (0x1UL << DSI_VHSACR_HSA3_Pos) /*!< 0x00000008 */
10009 #define DSI_VHSACR_HSA3 DSI_VHSACR_HSA3_Msk
10010 #define DSI_VHSACR_HSA4_Pos (4U)
10011 #define DSI_VHSACR_HSA4_Msk (0x1UL << DSI_VHSACR_HSA4_Pos) /*!< 0x00000010 */
10012 #define DSI_VHSACR_HSA4 DSI_VHSACR_HSA4_Msk
10013 #define DSI_VHSACR_HSA5_Pos (5U)
10014 #define DSI_VHSACR_HSA5_Msk (0x1UL << DSI_VHSACR_HSA5_Pos) /*!< 0x00000020 */
10015 #define DSI_VHSACR_HSA5 DSI_VHSACR_HSA5_Msk
10016 #define DSI_VHSACR_HSA6_Pos (6U)
10017 #define DSI_VHSACR_HSA6_Msk (0x1UL << DSI_VHSACR_HSA6_Pos) /*!< 0x00000040 */
10018 #define DSI_VHSACR_HSA6 DSI_VHSACR_HSA6_Msk
10019 #define DSI_VHSACR_HSA7_Pos (7U)
10020 #define DSI_VHSACR_HSA7_Msk (0x1UL << DSI_VHSACR_HSA7_Pos) /*!< 0x00000080 */
10021 #define DSI_VHSACR_HSA7 DSI_VHSACR_HSA7_Msk
10022 #define DSI_VHSACR_HSA8_Pos (8U)
10023 #define DSI_VHSACR_HSA8_Msk (0x1UL << DSI_VHSACR_HSA8_Pos) /*!< 0x00000100 */
10024 #define DSI_VHSACR_HSA8 DSI_VHSACR_HSA8_Msk
10025 #define DSI_VHSACR_HSA9_Pos (9U)
10026 #define DSI_VHSACR_HSA9_Msk (0x1UL << DSI_VHSACR_HSA9_Pos) /*!< 0x00000200 */
10027 #define DSI_VHSACR_HSA9 DSI_VHSACR_HSA9_Msk
10028 #define DSI_VHSACR_HSA10_Pos (10U)
10029 #define DSI_VHSACR_HSA10_Msk (0x1UL << DSI_VHSACR_HSA10_Pos) /*!< 0x00000400 */
10030 #define DSI_VHSACR_HSA10 DSI_VHSACR_HSA10_Msk
10031 #define DSI_VHSACR_HSA11_Pos (11U)
10032 #define DSI_VHSACR_HSA11_Msk (0x1UL << DSI_VHSACR_HSA11_Pos) /*!< 0x00000800 */
10033 #define DSI_VHSACR_HSA11 DSI_VHSACR_HSA11_Msk
10034
10035 /******************* Bit definition for DSI_VHBPCR register *************/
10036 #define DSI_VHBPCR_HBP_Pos (0U)
10037 #define DSI_VHBPCR_HBP_Msk (0xFFFUL << DSI_VHBPCR_HBP_Pos) /*!< 0x00000FFF */
10038 #define DSI_VHBPCR_HBP DSI_VHBPCR_HBP_Msk /*!< Horizontal Back-Porch duration */
10039 #define DSI_VHBPCR_HBP0_Pos (0U)
10040 #define DSI_VHBPCR_HBP0_Msk (0x1UL << DSI_VHBPCR_HBP0_Pos) /*!< 0x00000001 */
10041 #define DSI_VHBPCR_HBP0 DSI_VHBPCR_HBP0_Msk
10042 #define DSI_VHBPCR_HBP1_Pos (1U)
10043 #define DSI_VHBPCR_HBP1_Msk (0x1UL << DSI_VHBPCR_HBP1_Pos) /*!< 0x00000002 */
10044 #define DSI_VHBPCR_HBP1 DSI_VHBPCR_HBP1_Msk
10045 #define DSI_VHBPCR_HBP2_Pos (2U)
10046 #define DSI_VHBPCR_HBP2_Msk (0x1UL << DSI_VHBPCR_HBP2_Pos) /*!< 0x00000004 */
10047 #define DSI_VHBPCR_HBP2 DSI_VHBPCR_HBP2_Msk
10048 #define DSI_VHBPCR_HBP3_Pos (3U)
10049 #define DSI_VHBPCR_HBP3_Msk (0x1UL << DSI_VHBPCR_HBP3_Pos) /*!< 0x00000008 */
10050 #define DSI_VHBPCR_HBP3 DSI_VHBPCR_HBP3_Msk
10051 #define DSI_VHBPCR_HBP4_Pos (4U)
10052 #define DSI_VHBPCR_HBP4_Msk (0x1UL << DSI_VHBPCR_HBP4_Pos) /*!< 0x00000010 */
10053 #define DSI_VHBPCR_HBP4 DSI_VHBPCR_HBP4_Msk
10054 #define DSI_VHBPCR_HBP5_Pos (5U)
10055 #define DSI_VHBPCR_HBP5_Msk (0x1UL << DSI_VHBPCR_HBP5_Pos) /*!< 0x00000020 */
10056 #define DSI_VHBPCR_HBP5 DSI_VHBPCR_HBP5_Msk
10057 #define DSI_VHBPCR_HBP6_Pos (6U)
10058 #define DSI_VHBPCR_HBP6_Msk (0x1UL << DSI_VHBPCR_HBP6_Pos) /*!< 0x00000040 */
10059 #define DSI_VHBPCR_HBP6 DSI_VHBPCR_HBP6_Msk
10060 #define DSI_VHBPCR_HBP7_Pos (7U)
10061 #define DSI_VHBPCR_HBP7_Msk (0x1UL << DSI_VHBPCR_HBP7_Pos) /*!< 0x00000080 */
10062 #define DSI_VHBPCR_HBP7 DSI_VHBPCR_HBP7_Msk
10063 #define DSI_VHBPCR_HBP8_Pos (8U)
10064 #define DSI_VHBPCR_HBP8_Msk (0x1UL << DSI_VHBPCR_HBP8_Pos) /*!< 0x00000100 */
10065 #define DSI_VHBPCR_HBP8 DSI_VHBPCR_HBP8_Msk
10066 #define DSI_VHBPCR_HBP9_Pos (9U)
10067 #define DSI_VHBPCR_HBP9_Msk (0x1UL << DSI_VHBPCR_HBP9_Pos) /*!< 0x00000200 */
10068 #define DSI_VHBPCR_HBP9 DSI_VHBPCR_HBP9_Msk
10069 #define DSI_VHBPCR_HBP10_Pos (10U)
10070 #define DSI_VHBPCR_HBP10_Msk (0x1UL << DSI_VHBPCR_HBP10_Pos) /*!< 0x00000400 */
10071 #define DSI_VHBPCR_HBP10 DSI_VHBPCR_HBP10_Msk
10072 #define DSI_VHBPCR_HBP11_Pos (11U)
10073 #define DSI_VHBPCR_HBP11_Msk (0x1UL << DSI_VHBPCR_HBP11_Pos) /*!< 0x00000800 */
10074 #define DSI_VHBPCR_HBP11 DSI_VHBPCR_HBP11_Msk
10075
10076 /******************* Bit definition for DSI_VLCR register ***************/
10077 #define DSI_VLCR_HLINE_Pos (0U)
10078 #define DSI_VLCR_HLINE_Msk (0x7FFFUL << DSI_VLCR_HLINE_Pos) /*!< 0x00007FFF */
10079 #define DSI_VLCR_HLINE DSI_VLCR_HLINE_Msk /*!< Horizontal Line duration */
10080 #define DSI_VLCR_HLINE0_Pos (0U)
10081 #define DSI_VLCR_HLINE0_Msk (0x1UL << DSI_VLCR_HLINE0_Pos) /*!< 0x00000001 */
10082 #define DSI_VLCR_HLINE0 DSI_VLCR_HLINE0_Msk
10083 #define DSI_VLCR_HLINE1_Pos (1U)
10084 #define DSI_VLCR_HLINE1_Msk (0x1UL << DSI_VLCR_HLINE1_Pos) /*!< 0x00000002 */
10085 #define DSI_VLCR_HLINE1 DSI_VLCR_HLINE1_Msk
10086 #define DSI_VLCR_HLINE2_Pos (2U)
10087 #define DSI_VLCR_HLINE2_Msk (0x1UL << DSI_VLCR_HLINE2_Pos) /*!< 0x00000004 */
10088 #define DSI_VLCR_HLINE2 DSI_VLCR_HLINE2_Msk
10089 #define DSI_VLCR_HLINE3_Pos (3U)
10090 #define DSI_VLCR_HLINE3_Msk (0x1UL << DSI_VLCR_HLINE3_Pos) /*!< 0x00000008 */
10091 #define DSI_VLCR_HLINE3 DSI_VLCR_HLINE3_Msk
10092 #define DSI_VLCR_HLINE4_Pos (4U)
10093 #define DSI_VLCR_HLINE4_Msk (0x1UL << DSI_VLCR_HLINE4_Pos) /*!< 0x00000010 */
10094 #define DSI_VLCR_HLINE4 DSI_VLCR_HLINE4_Msk
10095 #define DSI_VLCR_HLINE5_Pos (5U)
10096 #define DSI_VLCR_HLINE5_Msk (0x1UL << DSI_VLCR_HLINE5_Pos) /*!< 0x00000020 */
10097 #define DSI_VLCR_HLINE5 DSI_VLCR_HLINE5_Msk
10098 #define DSI_VLCR_HLINE6_Pos (6U)
10099 #define DSI_VLCR_HLINE6_Msk (0x1UL << DSI_VLCR_HLINE6_Pos) /*!< 0x00000040 */
10100 #define DSI_VLCR_HLINE6 DSI_VLCR_HLINE6_Msk
10101 #define DSI_VLCR_HLINE7_Pos (7U)
10102 #define DSI_VLCR_HLINE7_Msk (0x1UL << DSI_VLCR_HLINE7_Pos) /*!< 0x00000080 */
10103 #define DSI_VLCR_HLINE7 DSI_VLCR_HLINE7_Msk
10104 #define DSI_VLCR_HLINE8_Pos (8U)
10105 #define DSI_VLCR_HLINE8_Msk (0x1UL << DSI_VLCR_HLINE8_Pos) /*!< 0x00000100 */
10106 #define DSI_VLCR_HLINE8 DSI_VLCR_HLINE8_Msk
10107 #define DSI_VLCR_HLINE9_Pos (9U)
10108 #define DSI_VLCR_HLINE9_Msk (0x1UL << DSI_VLCR_HLINE9_Pos) /*!< 0x00000200 */
10109 #define DSI_VLCR_HLINE9 DSI_VLCR_HLINE9_Msk
10110 #define DSI_VLCR_HLINE10_Pos (10U)
10111 #define DSI_VLCR_HLINE10_Msk (0x1UL << DSI_VLCR_HLINE10_Pos) /*!< 0x00000400 */
10112 #define DSI_VLCR_HLINE10 DSI_VLCR_HLINE10_Msk
10113 #define DSI_VLCR_HLINE11_Pos (11U)
10114 #define DSI_VLCR_HLINE11_Msk (0x1UL << DSI_VLCR_HLINE11_Pos) /*!< 0x00000800 */
10115 #define DSI_VLCR_HLINE11 DSI_VLCR_HLINE11_Msk
10116 #define DSI_VLCR_HLINE12_Pos (12U)
10117 #define DSI_VLCR_HLINE12_Msk (0x1UL << DSI_VLCR_HLINE12_Pos) /*!< 0x00001000 */
10118 #define DSI_VLCR_HLINE12 DSI_VLCR_HLINE12_Msk
10119 #define DSI_VLCR_HLINE13_Pos (13U)
10120 #define DSI_VLCR_HLINE13_Msk (0x1UL << DSI_VLCR_HLINE13_Pos) /*!< 0x00002000 */
10121 #define DSI_VLCR_HLINE13 DSI_VLCR_HLINE13_Msk
10122 #define DSI_VLCR_HLINE14_Pos (14U)
10123 #define DSI_VLCR_HLINE14_Msk (0x1UL << DSI_VLCR_HLINE14_Pos) /*!< 0x00004000 */
10124 #define DSI_VLCR_HLINE14 DSI_VLCR_HLINE14_Msk
10125
10126 /******************* Bit definition for DSI_VVSACR register *************/
10127 #define DSI_VVSACR_VSA_Pos (0U)
10128 #define DSI_VVSACR_VSA_Msk (0x3FFUL << DSI_VVSACR_VSA_Pos) /*!< 0x000003FF */
10129 #define DSI_VVSACR_VSA DSI_VVSACR_VSA_Msk /*!< Vertical Synchronism Active duration */
10130 #define DSI_VVSACR_VSA0_Pos (0U)
10131 #define DSI_VVSACR_VSA0_Msk (0x1UL << DSI_VVSACR_VSA0_Pos) /*!< 0x00000001 */
10132 #define DSI_VVSACR_VSA0 DSI_VVSACR_VSA0_Msk
10133 #define DSI_VVSACR_VSA1_Pos (1U)
10134 #define DSI_VVSACR_VSA1_Msk (0x1UL << DSI_VVSACR_VSA1_Pos) /*!< 0x00000002 */
10135 #define DSI_VVSACR_VSA1 DSI_VVSACR_VSA1_Msk
10136 #define DSI_VVSACR_VSA2_Pos (2U)
10137 #define DSI_VVSACR_VSA2_Msk (0x1UL << DSI_VVSACR_VSA2_Pos) /*!< 0x00000004 */
10138 #define DSI_VVSACR_VSA2 DSI_VVSACR_VSA2_Msk
10139 #define DSI_VVSACR_VSA3_Pos (3U)
10140 #define DSI_VVSACR_VSA3_Msk (0x1UL << DSI_VVSACR_VSA3_Pos) /*!< 0x00000008 */
10141 #define DSI_VVSACR_VSA3 DSI_VVSACR_VSA3_Msk
10142 #define DSI_VVSACR_VSA4_Pos (4U)
10143 #define DSI_VVSACR_VSA4_Msk (0x1UL << DSI_VVSACR_VSA4_Pos) /*!< 0x00000010 */
10144 #define DSI_VVSACR_VSA4 DSI_VVSACR_VSA4_Msk
10145 #define DSI_VVSACR_VSA5_Pos (5U)
10146 #define DSI_VVSACR_VSA5_Msk (0x1UL << DSI_VVSACR_VSA5_Pos) /*!< 0x00000020 */
10147 #define DSI_VVSACR_VSA5 DSI_VVSACR_VSA5_Msk
10148 #define DSI_VVSACR_VSA6_Pos (6U)
10149 #define DSI_VVSACR_VSA6_Msk (0x1UL << DSI_VVSACR_VSA6_Pos) /*!< 0x00000040 */
10150 #define DSI_VVSACR_VSA6 DSI_VVSACR_VSA6_Msk
10151 #define DSI_VVSACR_VSA7_Pos (7U)
10152 #define DSI_VVSACR_VSA7_Msk (0x1UL << DSI_VVSACR_VSA7_Pos) /*!< 0x00000080 */
10153 #define DSI_VVSACR_VSA7 DSI_VVSACR_VSA7_Msk
10154 #define DSI_VVSACR_VSA8_Pos (8U)
10155 #define DSI_VVSACR_VSA8_Msk (0x1UL << DSI_VVSACR_VSA8_Pos) /*!< 0x00000100 */
10156 #define DSI_VVSACR_VSA8 DSI_VVSACR_VSA8_Msk
10157 #define DSI_VVSACR_VSA9_Pos (9U)
10158 #define DSI_VVSACR_VSA9_Msk (0x1UL << DSI_VVSACR_VSA9_Pos) /*!< 0x00000200 */
10159 #define DSI_VVSACR_VSA9 DSI_VVSACR_VSA9_Msk
10160
10161 /******************* Bit definition for DSI_VVBPCR register *************/
10162 #define DSI_VVBPCR_VBP_Pos (0U)
10163 #define DSI_VVBPCR_VBP_Msk (0x3FFUL << DSI_VVBPCR_VBP_Pos) /*!< 0x000003FF */
10164 #define DSI_VVBPCR_VBP DSI_VVBPCR_VBP_Msk /*!< Vertical Back-Porch duration */
10165 #define DSI_VVBPCR_VBP0_Pos (0U)
10166 #define DSI_VVBPCR_VBP0_Msk (0x1UL << DSI_VVBPCR_VBP0_Pos) /*!< 0x00000001 */
10167 #define DSI_VVBPCR_VBP0 DSI_VVBPCR_VBP0_Msk
10168 #define DSI_VVBPCR_VBP1_Pos (1U)
10169 #define DSI_VVBPCR_VBP1_Msk (0x1UL << DSI_VVBPCR_VBP1_Pos) /*!< 0x00000002 */
10170 #define DSI_VVBPCR_VBP1 DSI_VVBPCR_VBP1_Msk
10171 #define DSI_VVBPCR_VBP2_Pos (2U)
10172 #define DSI_VVBPCR_VBP2_Msk (0x1UL << DSI_VVBPCR_VBP2_Pos) /*!< 0x00000004 */
10173 #define DSI_VVBPCR_VBP2 DSI_VVBPCR_VBP2_Msk
10174 #define DSI_VVBPCR_VBP3_Pos (3U)
10175 #define DSI_VVBPCR_VBP3_Msk (0x1UL << DSI_VVBPCR_VBP3_Pos) /*!< 0x00000008 */
10176 #define DSI_VVBPCR_VBP3 DSI_VVBPCR_VBP3_Msk
10177 #define DSI_VVBPCR_VBP4_Pos (4U)
10178 #define DSI_VVBPCR_VBP4_Msk (0x1UL << DSI_VVBPCR_VBP4_Pos) /*!< 0x00000010 */
10179 #define DSI_VVBPCR_VBP4 DSI_VVBPCR_VBP4_Msk
10180 #define DSI_VVBPCR_VBP5_Pos (5U)
10181 #define DSI_VVBPCR_VBP5_Msk (0x1UL << DSI_VVBPCR_VBP5_Pos) /*!< 0x00000020 */
10182 #define DSI_VVBPCR_VBP5 DSI_VVBPCR_VBP5_Msk
10183 #define DSI_VVBPCR_VBP6_Pos (6U)
10184 #define DSI_VVBPCR_VBP6_Msk (0x1UL << DSI_VVBPCR_VBP6_Pos) /*!< 0x00000040 */
10185 #define DSI_VVBPCR_VBP6 DSI_VVBPCR_VBP6_Msk
10186 #define DSI_VVBPCR_VBP7_Pos (7U)
10187 #define DSI_VVBPCR_VBP7_Msk (0x1UL << DSI_VVBPCR_VBP7_Pos) /*!< 0x00000080 */
10188 #define DSI_VVBPCR_VBP7 DSI_VVBPCR_VBP7_Msk
10189 #define DSI_VVBPCR_VBP8_Pos (8U)
10190 #define DSI_VVBPCR_VBP8_Msk (0x1UL << DSI_VVBPCR_VBP8_Pos) /*!< 0x00000100 */
10191 #define DSI_VVBPCR_VBP8 DSI_VVBPCR_VBP8_Msk
10192 #define DSI_VVBPCR_VBP9_Pos (9U)
10193 #define DSI_VVBPCR_VBP9_Msk (0x1UL << DSI_VVBPCR_VBP9_Pos) /*!< 0x00000200 */
10194 #define DSI_VVBPCR_VBP9 DSI_VVBPCR_VBP9_Msk
10195
10196 /******************* Bit definition for DSI_VVFPCR register *************/
10197 #define DSI_VVFPCR_VFP_Pos (0U)
10198 #define DSI_VVFPCR_VFP_Msk (0x3FFUL << DSI_VVFPCR_VFP_Pos) /*!< 0x000003FF */
10199 #define DSI_VVFPCR_VFP DSI_VVFPCR_VFP_Msk /*!< Vertical Front-Porch duration */
10200 #define DSI_VVFPCR_VFP0_Pos (0U)
10201 #define DSI_VVFPCR_VFP0_Msk (0x1UL << DSI_VVFPCR_VFP0_Pos) /*!< 0x00000001 */
10202 #define DSI_VVFPCR_VFP0 DSI_VVFPCR_VFP0_Msk
10203 #define DSI_VVFPCR_VFP1_Pos (1U)
10204 #define DSI_VVFPCR_VFP1_Msk (0x1UL << DSI_VVFPCR_VFP1_Pos) /*!< 0x00000002 */
10205 #define DSI_VVFPCR_VFP1 DSI_VVFPCR_VFP1_Msk
10206 #define DSI_VVFPCR_VFP2_Pos (2U)
10207 #define DSI_VVFPCR_VFP2_Msk (0x1UL << DSI_VVFPCR_VFP2_Pos) /*!< 0x00000004 */
10208 #define DSI_VVFPCR_VFP2 DSI_VVFPCR_VFP2_Msk
10209 #define DSI_VVFPCR_VFP3_Pos (3U)
10210 #define DSI_VVFPCR_VFP3_Msk (0x1UL << DSI_VVFPCR_VFP3_Pos) /*!< 0x00000008 */
10211 #define DSI_VVFPCR_VFP3 DSI_VVFPCR_VFP3_Msk
10212 #define DSI_VVFPCR_VFP4_Pos (4U)
10213 #define DSI_VVFPCR_VFP4_Msk (0x1UL << DSI_VVFPCR_VFP4_Pos) /*!< 0x00000010 */
10214 #define DSI_VVFPCR_VFP4 DSI_VVFPCR_VFP4_Msk
10215 #define DSI_VVFPCR_VFP5_Pos (5U)
10216 #define DSI_VVFPCR_VFP5_Msk (0x1UL << DSI_VVFPCR_VFP5_Pos) /*!< 0x00000020 */
10217 #define DSI_VVFPCR_VFP5 DSI_VVFPCR_VFP5_Msk
10218 #define DSI_VVFPCR_VFP6_Pos (6U)
10219 #define DSI_VVFPCR_VFP6_Msk (0x1UL << DSI_VVFPCR_VFP6_Pos) /*!< 0x00000040 */
10220 #define DSI_VVFPCR_VFP6 DSI_VVFPCR_VFP6_Msk
10221 #define DSI_VVFPCR_VFP7_Pos (7U)
10222 #define DSI_VVFPCR_VFP7_Msk (0x1UL << DSI_VVFPCR_VFP7_Pos) /*!< 0x00000080 */
10223 #define DSI_VVFPCR_VFP7 DSI_VVFPCR_VFP7_Msk
10224 #define DSI_VVFPCR_VFP8_Pos (8U)
10225 #define DSI_VVFPCR_VFP8_Msk (0x1UL << DSI_VVFPCR_VFP8_Pos) /*!< 0x00000100 */
10226 #define DSI_VVFPCR_VFP8 DSI_VVFPCR_VFP8_Msk
10227 #define DSI_VVFPCR_VFP9_Pos (9U)
10228 #define DSI_VVFPCR_VFP9_Msk (0x1UL << DSI_VVFPCR_VFP9_Pos) /*!< 0x00000200 */
10229 #define DSI_VVFPCR_VFP9 DSI_VVFPCR_VFP9_Msk
10230
10231 /******************* Bit definition for DSI_VVACR register **************/
10232 #define DSI_VVACR_VA_Pos (0U)
10233 #define DSI_VVACR_VA_Msk (0x3FFFUL << DSI_VVACR_VA_Pos) /*!< 0x00003FFF */
10234 #define DSI_VVACR_VA DSI_VVACR_VA_Msk /*!< Vertical Active duration */
10235 #define DSI_VVACR_VA0_Pos (0U)
10236 #define DSI_VVACR_VA0_Msk (0x1UL << DSI_VVACR_VA0_Pos) /*!< 0x00000001 */
10237 #define DSI_VVACR_VA0 DSI_VVACR_VA0_Msk
10238 #define DSI_VVACR_VA1_Pos (1U)
10239 #define DSI_VVACR_VA1_Msk (0x1UL << DSI_VVACR_VA1_Pos) /*!< 0x00000002 */
10240 #define DSI_VVACR_VA1 DSI_VVACR_VA1_Msk
10241 #define DSI_VVACR_VA2_Pos (2U)
10242 #define DSI_VVACR_VA2_Msk (0x1UL << DSI_VVACR_VA2_Pos) /*!< 0x00000004 */
10243 #define DSI_VVACR_VA2 DSI_VVACR_VA2_Msk
10244 #define DSI_VVACR_VA3_Pos (3U)
10245 #define DSI_VVACR_VA3_Msk (0x1UL << DSI_VVACR_VA3_Pos) /*!< 0x00000008 */
10246 #define DSI_VVACR_VA3 DSI_VVACR_VA3_Msk
10247 #define DSI_VVACR_VA4_Pos (4U)
10248 #define DSI_VVACR_VA4_Msk (0x1UL << DSI_VVACR_VA4_Pos) /*!< 0x00000010 */
10249 #define DSI_VVACR_VA4 DSI_VVACR_VA4_Msk
10250 #define DSI_VVACR_VA5_Pos (5U)
10251 #define DSI_VVACR_VA5_Msk (0x1UL << DSI_VVACR_VA5_Pos) /*!< 0x00000020 */
10252 #define DSI_VVACR_VA5 DSI_VVACR_VA5_Msk
10253 #define DSI_VVACR_VA6_Pos (6U)
10254 #define DSI_VVACR_VA6_Msk (0x1UL << DSI_VVACR_VA6_Pos) /*!< 0x00000040 */
10255 #define DSI_VVACR_VA6 DSI_VVACR_VA6_Msk
10256 #define DSI_VVACR_VA7_Pos (7U)
10257 #define DSI_VVACR_VA7_Msk (0x1UL << DSI_VVACR_VA7_Pos) /*!< 0x00000080 */
10258 #define DSI_VVACR_VA7 DSI_VVACR_VA7_Msk
10259 #define DSI_VVACR_VA8_Pos (8U)
10260 #define DSI_VVACR_VA8_Msk (0x1UL << DSI_VVACR_VA8_Pos) /*!< 0x00000100 */
10261 #define DSI_VVACR_VA8 DSI_VVACR_VA8_Msk
10262 #define DSI_VVACR_VA9_Pos (9U)
10263 #define DSI_VVACR_VA9_Msk (0x1UL << DSI_VVACR_VA9_Pos) /*!< 0x00000200 */
10264 #define DSI_VVACR_VA9 DSI_VVACR_VA9_Msk
10265 #define DSI_VVACR_VA10_Pos (10U)
10266 #define DSI_VVACR_VA10_Msk (0x1UL << DSI_VVACR_VA10_Pos) /*!< 0x00000400 */
10267 #define DSI_VVACR_VA10 DSI_VVACR_VA10_Msk
10268 #define DSI_VVACR_VA11_Pos (11U)
10269 #define DSI_VVACR_VA11_Msk (0x1UL << DSI_VVACR_VA11_Pos) /*!< 0x00000800 */
10270 #define DSI_VVACR_VA11 DSI_VVACR_VA11_Msk
10271 #define DSI_VVACR_VA12_Pos (12U)
10272 #define DSI_VVACR_VA12_Msk (0x1UL << DSI_VVACR_VA12_Pos) /*!< 0x00001000 */
10273 #define DSI_VVACR_VA12 DSI_VVACR_VA12_Msk
10274 #define DSI_VVACR_VA13_Pos (13U)
10275 #define DSI_VVACR_VA13_Msk (0x1UL << DSI_VVACR_VA13_Pos) /*!< 0x00002000 */
10276 #define DSI_VVACR_VA13 DSI_VVACR_VA13_Msk
10277
10278 /******************* Bit definition for DSI_LCCR register ***************/
10279 #define DSI_LCCR_CMDSIZE_Pos (0U)
10280 #define DSI_LCCR_CMDSIZE_Msk (0xFFFFUL << DSI_LCCR_CMDSIZE_Pos) /*!< 0x0000FFFF */
10281 #define DSI_LCCR_CMDSIZE DSI_LCCR_CMDSIZE_Msk /*!< Command Size */
10282 #define DSI_LCCR_CMDSIZE0_Pos (0U)
10283 #define DSI_LCCR_CMDSIZE0_Msk (0x1UL << DSI_LCCR_CMDSIZE0_Pos) /*!< 0x00000001 */
10284 #define DSI_LCCR_CMDSIZE0 DSI_LCCR_CMDSIZE0_Msk
10285 #define DSI_LCCR_CMDSIZE1_Pos (1U)
10286 #define DSI_LCCR_CMDSIZE1_Msk (0x1UL << DSI_LCCR_CMDSIZE1_Pos) /*!< 0x00000002 */
10287 #define DSI_LCCR_CMDSIZE1 DSI_LCCR_CMDSIZE1_Msk
10288 #define DSI_LCCR_CMDSIZE2_Pos (2U)
10289 #define DSI_LCCR_CMDSIZE2_Msk (0x1UL << DSI_LCCR_CMDSIZE2_Pos) /*!< 0x00000004 */
10290 #define DSI_LCCR_CMDSIZE2 DSI_LCCR_CMDSIZE2_Msk
10291 #define DSI_LCCR_CMDSIZE3_Pos (3U)
10292 #define DSI_LCCR_CMDSIZE3_Msk (0x1UL << DSI_LCCR_CMDSIZE3_Pos) /*!< 0x00000008 */
10293 #define DSI_LCCR_CMDSIZE3 DSI_LCCR_CMDSIZE3_Msk
10294 #define DSI_LCCR_CMDSIZE4_Pos (4U)
10295 #define DSI_LCCR_CMDSIZE4_Msk (0x1UL << DSI_LCCR_CMDSIZE4_Pos) /*!< 0x00000010 */
10296 #define DSI_LCCR_CMDSIZE4 DSI_LCCR_CMDSIZE4_Msk
10297 #define DSI_LCCR_CMDSIZE5_Pos (5U)
10298 #define DSI_LCCR_CMDSIZE5_Msk (0x1UL << DSI_LCCR_CMDSIZE5_Pos) /*!< 0x00000020 */
10299 #define DSI_LCCR_CMDSIZE5 DSI_LCCR_CMDSIZE5_Msk
10300 #define DSI_LCCR_CMDSIZE6_Pos (6U)
10301 #define DSI_LCCR_CMDSIZE6_Msk (0x1UL << DSI_LCCR_CMDSIZE6_Pos) /*!< 0x00000040 */
10302 #define DSI_LCCR_CMDSIZE6 DSI_LCCR_CMDSIZE6_Msk
10303 #define DSI_LCCR_CMDSIZE7_Pos (7U)
10304 #define DSI_LCCR_CMDSIZE7_Msk (0x1UL << DSI_LCCR_CMDSIZE7_Pos) /*!< 0x00000080 */
10305 #define DSI_LCCR_CMDSIZE7 DSI_LCCR_CMDSIZE7_Msk
10306 #define DSI_LCCR_CMDSIZE8_Pos (8U)
10307 #define DSI_LCCR_CMDSIZE8_Msk (0x1UL << DSI_LCCR_CMDSIZE8_Pos) /*!< 0x00000100 */
10308 #define DSI_LCCR_CMDSIZE8 DSI_LCCR_CMDSIZE8_Msk
10309 #define DSI_LCCR_CMDSIZE9_Pos (9U)
10310 #define DSI_LCCR_CMDSIZE9_Msk (0x1UL << DSI_LCCR_CMDSIZE9_Pos) /*!< 0x00000200 */
10311 #define DSI_LCCR_CMDSIZE9 DSI_LCCR_CMDSIZE9_Msk
10312 #define DSI_LCCR_CMDSIZE10_Pos (10U)
10313 #define DSI_LCCR_CMDSIZE10_Msk (0x1UL << DSI_LCCR_CMDSIZE10_Pos) /*!< 0x00000400 */
10314 #define DSI_LCCR_CMDSIZE10 DSI_LCCR_CMDSIZE10_Msk
10315 #define DSI_LCCR_CMDSIZE11_Pos (11U)
10316 #define DSI_LCCR_CMDSIZE11_Msk (0x1UL << DSI_LCCR_CMDSIZE11_Pos) /*!< 0x00000800 */
10317 #define DSI_LCCR_CMDSIZE11 DSI_LCCR_CMDSIZE11_Msk
10318 #define DSI_LCCR_CMDSIZE12_Pos (12U)
10319 #define DSI_LCCR_CMDSIZE12_Msk (0x1UL << DSI_LCCR_CMDSIZE12_Pos) /*!< 0x00001000 */
10320 #define DSI_LCCR_CMDSIZE12 DSI_LCCR_CMDSIZE12_Msk
10321 #define DSI_LCCR_CMDSIZE13_Pos (13U)
10322 #define DSI_LCCR_CMDSIZE13_Msk (0x1UL << DSI_LCCR_CMDSIZE13_Pos) /*!< 0x00002000 */
10323 #define DSI_LCCR_CMDSIZE13 DSI_LCCR_CMDSIZE13_Msk
10324 #define DSI_LCCR_CMDSIZE14_Pos (14U)
10325 #define DSI_LCCR_CMDSIZE14_Msk (0x1UL << DSI_LCCR_CMDSIZE14_Pos) /*!< 0x00004000 */
10326 #define DSI_LCCR_CMDSIZE14 DSI_LCCR_CMDSIZE14_Msk
10327 #define DSI_LCCR_CMDSIZE15_Pos (15U)
10328 #define DSI_LCCR_CMDSIZE15_Msk (0x1UL << DSI_LCCR_CMDSIZE15_Pos) /*!< 0x00008000 */
10329 #define DSI_LCCR_CMDSIZE15 DSI_LCCR_CMDSIZE15_Msk
10330
10331 /******************* Bit definition for DSI_CMCR register ***************/
10332 #define DSI_CMCR_TEARE_Pos (0U)
10333 #define DSI_CMCR_TEARE_Msk (0x1UL << DSI_CMCR_TEARE_Pos) /*!< 0x00000001 */
10334 #define DSI_CMCR_TEARE DSI_CMCR_TEARE_Msk /*!< Tearing Effect Acknowledge Request Enable */
10335 #define DSI_CMCR_ARE_Pos (1U)
10336 #define DSI_CMCR_ARE_Msk (0x1UL << DSI_CMCR_ARE_Pos) /*!< 0x00000002 */
10337 #define DSI_CMCR_ARE DSI_CMCR_ARE_Msk /*!< Acknowledge Request Enable */
10338 #define DSI_CMCR_GSW0TX_Pos (8U)
10339 #define DSI_CMCR_GSW0TX_Msk (0x1UL << DSI_CMCR_GSW0TX_Pos) /*!< 0x00000100 */
10340 #define DSI_CMCR_GSW0TX DSI_CMCR_GSW0TX_Msk /*!< Generic Short Write Zero parameters Transmission */
10341 #define DSI_CMCR_GSW1TX_Pos (9U)
10342 #define DSI_CMCR_GSW1TX_Msk (0x1UL << DSI_CMCR_GSW1TX_Pos) /*!< 0x00000200 */
10343 #define DSI_CMCR_GSW1TX DSI_CMCR_GSW1TX_Msk /*!< Generic Short Write One parameters Transmission */
10344 #define DSI_CMCR_GSW2TX_Pos (10U)
10345 #define DSI_CMCR_GSW2TX_Msk (0x1UL << DSI_CMCR_GSW2TX_Pos) /*!< 0x00000400 */
10346 #define DSI_CMCR_GSW2TX DSI_CMCR_GSW2TX_Msk /*!< Generic Short Write Two parameters Transmission */
10347 #define DSI_CMCR_GSR0TX_Pos (11U)
10348 #define DSI_CMCR_GSR0TX_Msk (0x1UL << DSI_CMCR_GSR0TX_Pos) /*!< 0x00000800 */
10349 #define DSI_CMCR_GSR0TX DSI_CMCR_GSR0TX_Msk /*!< Generic Short Read Zero parameters Transmission */
10350 #define DSI_CMCR_GSR1TX_Pos (12U)
10351 #define DSI_CMCR_GSR1TX_Msk (0x1UL << DSI_CMCR_GSR1TX_Pos) /*!< 0x00001000 */
10352 #define DSI_CMCR_GSR1TX DSI_CMCR_GSR1TX_Msk /*!< Generic Short Read One parameters Transmission */
10353 #define DSI_CMCR_GSR2TX_Pos (13U)
10354 #define DSI_CMCR_GSR2TX_Msk (0x1UL << DSI_CMCR_GSR2TX_Pos) /*!< 0x00002000 */
10355 #define DSI_CMCR_GSR2TX DSI_CMCR_GSR2TX_Msk /*!< Generic Short Read Two parameters Transmission */
10356 #define DSI_CMCR_GLWTX_Pos (14U)
10357 #define DSI_CMCR_GLWTX_Msk (0x1UL << DSI_CMCR_GLWTX_Pos) /*!< 0x00004000 */
10358 #define DSI_CMCR_GLWTX DSI_CMCR_GLWTX_Msk /*!< Generic Long Write Transmission */
10359 #define DSI_CMCR_DSW0TX_Pos (16U)
10360 #define DSI_CMCR_DSW0TX_Msk (0x1UL << DSI_CMCR_DSW0TX_Pos) /*!< 0x00010000 */
10361 #define DSI_CMCR_DSW0TX DSI_CMCR_DSW0TX_Msk /*!< DCS Short Write Zero parameter Transmission */
10362 #define DSI_CMCR_DSW1TX_Pos (17U)
10363 #define DSI_CMCR_DSW1TX_Msk (0x1UL << DSI_CMCR_DSW1TX_Pos) /*!< 0x00020000 */
10364 #define DSI_CMCR_DSW1TX DSI_CMCR_DSW1TX_Msk /*!< DCS Short Read One parameter Transmission */
10365 #define DSI_CMCR_DSR0TX_Pos (18U)
10366 #define DSI_CMCR_DSR0TX_Msk (0x1UL << DSI_CMCR_DSR0TX_Pos) /*!< 0x00040000 */
10367 #define DSI_CMCR_DSR0TX DSI_CMCR_DSR0TX_Msk /*!< DCS Short Read Zero parameter Transmission */
10368 #define DSI_CMCR_DLWTX_Pos (19U)
10369 #define DSI_CMCR_DLWTX_Msk (0x1UL << DSI_CMCR_DLWTX_Pos) /*!< 0x00080000 */
10370 #define DSI_CMCR_DLWTX DSI_CMCR_DLWTX_Msk /*!< DCS Long Write Transmission */
10371 #define DSI_CMCR_MRDPS_Pos (24U)
10372 #define DSI_CMCR_MRDPS_Msk (0x1UL << DSI_CMCR_MRDPS_Pos) /*!< 0x01000000 */
10373 #define DSI_CMCR_MRDPS DSI_CMCR_MRDPS_Msk /*!< Maximum Read Packet Size */
10374
10375 /******************* Bit definition for DSI_GHCR register ***************/
10376 #define DSI_GHCR_DT_Pos (0U)
10377 #define DSI_GHCR_DT_Msk (0x3FUL << DSI_GHCR_DT_Pos) /*!< 0x0000003F */
10378 #define DSI_GHCR_DT DSI_GHCR_DT_Msk /*!< Type */
10379 #define DSI_GHCR_DT0_Pos (0U)
10380 #define DSI_GHCR_DT0_Msk (0x1UL << DSI_GHCR_DT0_Pos) /*!< 0x00000001 */
10381 #define DSI_GHCR_DT0 DSI_GHCR_DT0_Msk
10382 #define DSI_GHCR_DT1_Pos (1U)
10383 #define DSI_GHCR_DT1_Msk (0x1UL << DSI_GHCR_DT1_Pos) /*!< 0x00000002 */
10384 #define DSI_GHCR_DT1 DSI_GHCR_DT1_Msk
10385 #define DSI_GHCR_DT2_Pos (2U)
10386 #define DSI_GHCR_DT2_Msk (0x1UL << DSI_GHCR_DT2_Pos) /*!< 0x00000004 */
10387 #define DSI_GHCR_DT2 DSI_GHCR_DT2_Msk
10388 #define DSI_GHCR_DT3_Pos (3U)
10389 #define DSI_GHCR_DT3_Msk (0x1UL << DSI_GHCR_DT3_Pos) /*!< 0x00000008 */
10390 #define DSI_GHCR_DT3 DSI_GHCR_DT3_Msk
10391 #define DSI_GHCR_DT4_Pos (4U)
10392 #define DSI_GHCR_DT4_Msk (0x1UL << DSI_GHCR_DT4_Pos) /*!< 0x00000010 */
10393 #define DSI_GHCR_DT4 DSI_GHCR_DT4_Msk
10394 #define DSI_GHCR_DT5_Pos (5U)
10395 #define DSI_GHCR_DT5_Msk (0x1UL << DSI_GHCR_DT5_Pos) /*!< 0x00000020 */
10396 #define DSI_GHCR_DT5 DSI_GHCR_DT5_Msk
10397
10398 #define DSI_GHCR_VCID_Pos (6U)
10399 #define DSI_GHCR_VCID_Msk (0x3UL << DSI_GHCR_VCID_Pos) /*!< 0x000000C0 */
10400 #define DSI_GHCR_VCID DSI_GHCR_VCID_Msk /*!< Channel */
10401 #define DSI_GHCR_VCID0_Pos (6U)
10402 #define DSI_GHCR_VCID0_Msk (0x1UL << DSI_GHCR_VCID0_Pos) /*!< 0x00000040 */
10403 #define DSI_GHCR_VCID0 DSI_GHCR_VCID0_Msk
10404 #define DSI_GHCR_VCID1_Pos (7U)
10405 #define DSI_GHCR_VCID1_Msk (0x1UL << DSI_GHCR_VCID1_Pos) /*!< 0x00000080 */
10406 #define DSI_GHCR_VCID1 DSI_GHCR_VCID1_Msk
10407
10408 #define DSI_GHCR_WCLSB_Pos (8U)
10409 #define DSI_GHCR_WCLSB_Msk (0xFFUL << DSI_GHCR_WCLSB_Pos) /*!< 0x0000FF00 */
10410 #define DSI_GHCR_WCLSB DSI_GHCR_WCLSB_Msk /*!< WordCount LSB */
10411 #define DSI_GHCR_WCLSB0_Pos (8U)
10412 #define DSI_GHCR_WCLSB0_Msk (0x1UL << DSI_GHCR_WCLSB0_Pos) /*!< 0x00000100 */
10413 #define DSI_GHCR_WCLSB0 DSI_GHCR_WCLSB0_Msk
10414 #define DSI_GHCR_WCLSB1_Pos (9U)
10415 #define DSI_GHCR_WCLSB1_Msk (0x1UL << DSI_GHCR_WCLSB1_Pos) /*!< 0x00000200 */
10416 #define DSI_GHCR_WCLSB1 DSI_GHCR_WCLSB1_Msk
10417 #define DSI_GHCR_WCLSB2_Pos (10U)
10418 #define DSI_GHCR_WCLSB2_Msk (0x1UL << DSI_GHCR_WCLSB2_Pos) /*!< 0x00000400 */
10419 #define DSI_GHCR_WCLSB2 DSI_GHCR_WCLSB2_Msk
10420 #define DSI_GHCR_WCLSB3_Pos (11U)
10421 #define DSI_GHCR_WCLSB3_Msk (0x1UL << DSI_GHCR_WCLSB3_Pos) /*!< 0x00000800 */
10422 #define DSI_GHCR_WCLSB3 DSI_GHCR_WCLSB3_Msk
10423 #define DSI_GHCR_WCLSB4_Pos (12U)
10424 #define DSI_GHCR_WCLSB4_Msk (0x1UL << DSI_GHCR_WCLSB4_Pos) /*!< 0x00001000 */
10425 #define DSI_GHCR_WCLSB4 DSI_GHCR_WCLSB4_Msk
10426 #define DSI_GHCR_WCLSB5_Pos (13U)
10427 #define DSI_GHCR_WCLSB5_Msk (0x1UL << DSI_GHCR_WCLSB5_Pos) /*!< 0x00002000 */
10428 #define DSI_GHCR_WCLSB5 DSI_GHCR_WCLSB5_Msk
10429 #define DSI_GHCR_WCLSB6_Pos (14U)
10430 #define DSI_GHCR_WCLSB6_Msk (0x1UL << DSI_GHCR_WCLSB6_Pos) /*!< 0x00004000 */
10431 #define DSI_GHCR_WCLSB6 DSI_GHCR_WCLSB6_Msk
10432 #define DSI_GHCR_WCLSB7_Pos (15U)
10433 #define DSI_GHCR_WCLSB7_Msk (0x1UL << DSI_GHCR_WCLSB7_Pos) /*!< 0x00008000 */
10434 #define DSI_GHCR_WCLSB7 DSI_GHCR_WCLSB7_Msk
10435
10436 #define DSI_GHCR_WCMSB_Pos (16U)
10437 #define DSI_GHCR_WCMSB_Msk (0xFFUL << DSI_GHCR_WCMSB_Pos) /*!< 0x00FF0000 */
10438 #define DSI_GHCR_WCMSB DSI_GHCR_WCMSB_Msk /*!< WordCount MSB */
10439 #define DSI_GHCR_WCMSB0_Pos (16U)
10440 #define DSI_GHCR_WCMSB0_Msk (0x1UL << DSI_GHCR_WCMSB0_Pos) /*!< 0x00010000 */
10441 #define DSI_GHCR_WCMSB0 DSI_GHCR_WCMSB0_Msk
10442 #define DSI_GHCR_WCMSB1_Pos (17U)
10443 #define DSI_GHCR_WCMSB1_Msk (0x1UL << DSI_GHCR_WCMSB1_Pos) /*!< 0x00020000 */
10444 #define DSI_GHCR_WCMSB1 DSI_GHCR_WCMSB1_Msk
10445 #define DSI_GHCR_WCMSB2_Pos (18U)
10446 #define DSI_GHCR_WCMSB2_Msk (0x1UL << DSI_GHCR_WCMSB2_Pos) /*!< 0x00040000 */
10447 #define DSI_GHCR_WCMSB2 DSI_GHCR_WCMSB2_Msk
10448 #define DSI_GHCR_WCMSB3_Pos (19U)
10449 #define DSI_GHCR_WCMSB3_Msk (0x1UL << DSI_GHCR_WCMSB3_Pos) /*!< 0x00080000 */
10450 #define DSI_GHCR_WCMSB3 DSI_GHCR_WCMSB3_Msk
10451 #define DSI_GHCR_WCMSB4_Pos (20U)
10452 #define DSI_GHCR_WCMSB4_Msk (0x1UL << DSI_GHCR_WCMSB4_Pos) /*!< 0x00100000 */
10453 #define DSI_GHCR_WCMSB4 DSI_GHCR_WCMSB4_Msk
10454 #define DSI_GHCR_WCMSB5_Pos (21U)
10455 #define DSI_GHCR_WCMSB5_Msk (0x1UL << DSI_GHCR_WCMSB5_Pos) /*!< 0x00200000 */
10456 #define DSI_GHCR_WCMSB5 DSI_GHCR_WCMSB5_Msk
10457 #define DSI_GHCR_WCMSB6_Pos (22U)
10458 #define DSI_GHCR_WCMSB6_Msk (0x1UL << DSI_GHCR_WCMSB6_Pos) /*!< 0x00400000 */
10459 #define DSI_GHCR_WCMSB6 DSI_GHCR_WCMSB6_Msk
10460 #define DSI_GHCR_WCMSB7_Pos (23U)
10461 #define DSI_GHCR_WCMSB7_Msk (0x1UL << DSI_GHCR_WCMSB7_Pos) /*!< 0x00800000 */
10462 #define DSI_GHCR_WCMSB7 DSI_GHCR_WCMSB7_Msk
10463
10464 /******************* Bit definition for DSI_GPDR register ***************/
10465 #define DSI_GPDR_DATA1_Pos (0U)
10466 #define DSI_GPDR_DATA1_Msk (0xFFUL << DSI_GPDR_DATA1_Pos) /*!< 0x000000FF */
10467 #define DSI_GPDR_DATA1 DSI_GPDR_DATA1_Msk /*!< Payload Byte 1 */
10468 #define DSI_GPDR_DATA1_0 (0x01UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000001 */
10469 #define DSI_GPDR_DATA1_1 (0x02UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000002 */
10470 #define DSI_GPDR_DATA1_2 (0x04UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000004 */
10471 #define DSI_GPDR_DATA1_3 (0x08UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000008 */
10472 #define DSI_GPDR_DATA1_4 (0x10UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000010 */
10473 #define DSI_GPDR_DATA1_5 (0x20UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000020 */
10474 #define DSI_GPDR_DATA1_6 (0x40UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000040 */
10475 #define DSI_GPDR_DATA1_7 (0x80UL << DSI_GPDR_DATA1_Pos) /*!< 0x00000080 */
10476
10477 #define DSI_GPDR_DATA2_Pos (8U)
10478 #define DSI_GPDR_DATA2_Msk (0xFFUL << DSI_GPDR_DATA2_Pos) /*!< 0x0000FF00 */
10479 #define DSI_GPDR_DATA2 DSI_GPDR_DATA2_Msk /*!< Payload Byte 2 */
10480 #define DSI_GPDR_DATA2_0 (0x01UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000100 */
10481 #define DSI_GPDR_DATA2_1 (0x02UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000200 */
10482 #define DSI_GPDR_DATA2_2 (0x04UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000400 */
10483 #define DSI_GPDR_DATA2_3 (0x08UL << DSI_GPDR_DATA2_Pos) /*!< 0x00000800 */
10484 #define DSI_GPDR_DATA2_4 (0x10UL << DSI_GPDR_DATA2_Pos) /*!< 0x00001000 */
10485 #define DSI_GPDR_DATA2_5 (0x20UL << DSI_GPDR_DATA2_Pos) /*!< 0x00002000 */
10486 #define DSI_GPDR_DATA2_6 (0x40UL << DSI_GPDR_DATA2_Pos) /*!< 0x00004000 */
10487 #define DSI_GPDR_DATA2_7 (0x80UL << DSI_GPDR_DATA2_Pos) /*!< 0x00008000 */
10488
10489 #define DSI_GPDR_DATA3_Pos (16U)
10490 #define DSI_GPDR_DATA3_Msk (0xFFUL << DSI_GPDR_DATA3_Pos) /*!< 0x00FF0000 */
10491 #define DSI_GPDR_DATA3 DSI_GPDR_DATA3_Msk /*!< Payload Byte 3 */
10492 #define DSI_GPDR_DATA3_0 (0x01UL << DSI_GPDR_DATA3_Pos) /*!< 0x00010000 */
10493 #define DSI_GPDR_DATA3_1 (0x02UL << DSI_GPDR_DATA3_Pos) /*!< 0x00020000 */
10494 #define DSI_GPDR_DATA3_2 (0x04UL << DSI_GPDR_DATA3_Pos) /*!< 0x00040000 */
10495 #define DSI_GPDR_DATA3_3 (0x08UL << DSI_GPDR_DATA3_Pos) /*!< 0x00080000 */
10496 #define DSI_GPDR_DATA3_4 (0x10UL << DSI_GPDR_DATA3_Pos) /*!< 0x00100000 */
10497 #define DSI_GPDR_DATA3_5 (0x20UL << DSI_GPDR_DATA3_Pos) /*!< 0x00200000 */
10498 #define DSI_GPDR_DATA3_6 (0x40UL << DSI_GPDR_DATA3_Pos) /*!< 0x00400000 */
10499 #define DSI_GPDR_DATA3_7 (0x80UL << DSI_GPDR_DATA3_Pos) /*!< 0x00800000 */
10500
10501 #define DSI_GPDR_DATA4_Pos (24U)
10502 #define DSI_GPDR_DATA4_Msk (0xFFUL << DSI_GPDR_DATA4_Pos) /*!< 0xFF000000 */
10503 #define DSI_GPDR_DATA4 DSI_GPDR_DATA4_Msk /*!< Payload Byte 4 */
10504 #define DSI_GPDR_DATA4_0 (0x01UL << DSI_GPDR_DATA4_Pos) /*!< 0x01000000 */
10505 #define DSI_GPDR_DATA4_1 (0x02UL << DSI_GPDR_DATA4_Pos) /*!< 0x02000000 */
10506 #define DSI_GPDR_DATA4_2 (0x04UL << DSI_GPDR_DATA4_Pos) /*!< 0x04000000 */
10507 #define DSI_GPDR_DATA4_3 (0x08UL << DSI_GPDR_DATA4_Pos) /*!< 0x08000000 */
10508 #define DSI_GPDR_DATA4_4 (0x10UL << DSI_GPDR_DATA4_Pos) /*!< 0x10000000 */
10509 #define DSI_GPDR_DATA4_5 (0x20UL << DSI_GPDR_DATA4_Pos) /*!< 0x20000000 */
10510 #define DSI_GPDR_DATA4_6 (0x40UL << DSI_GPDR_DATA4_Pos) /*!< 0x40000000 */
10511 #define DSI_GPDR_DATA4_7 (0x80UL << DSI_GPDR_DATA4_Pos) /*!< 0x80000000 */
10512
10513 /******************* Bit definition for DSI_GPSR register ***************/
10514 #define DSI_GPSR_CMDFE_Pos (0U)
10515 #define DSI_GPSR_CMDFE_Msk (0x1UL << DSI_GPSR_CMDFE_Pos) /*!< 0x00000001 */
10516 #define DSI_GPSR_CMDFE DSI_GPSR_CMDFE_Msk /*!< Command FIFO Empty */
10517 #define DSI_GPSR_CMDFF_Pos (1U)
10518 #define DSI_GPSR_CMDFF_Msk (0x1UL << DSI_GPSR_CMDFF_Pos) /*!< 0x00000002 */
10519 #define DSI_GPSR_CMDFF DSI_GPSR_CMDFF_Msk /*!< Command FIFO Full */
10520 #define DSI_GPSR_PWRFE_Pos (2U)
10521 #define DSI_GPSR_PWRFE_Msk (0x1UL << DSI_GPSR_PWRFE_Pos) /*!< 0x00000004 */
10522 #define DSI_GPSR_PWRFE DSI_GPSR_PWRFE_Msk /*!< Payload Write FIFO Empty */
10523 #define DSI_GPSR_PWRFF_Pos (3U)
10524 #define DSI_GPSR_PWRFF_Msk (0x1UL << DSI_GPSR_PWRFF_Pos) /*!< 0x00000008 */
10525 #define DSI_GPSR_PWRFF DSI_GPSR_PWRFF_Msk /*!< Payload Write FIFO Full */
10526 #define DSI_GPSR_PRDFE_Pos (4U)
10527 #define DSI_GPSR_PRDFE_Msk (0x1UL << DSI_GPSR_PRDFE_Pos) /*!< 0x00000010 */
10528 #define DSI_GPSR_PRDFE DSI_GPSR_PRDFE_Msk /*!< Payload Read FIFO Empty */
10529 #define DSI_GPSR_PRDFF_Pos (5U)
10530 #define DSI_GPSR_PRDFF_Msk (0x1UL << DSI_GPSR_PRDFF_Pos) /*!< 0x00000020 */
10531 #define DSI_GPSR_PRDFF DSI_GPSR_PRDFF_Msk /*!< Payload Read FIFO Full */
10532 #define DSI_GPSR_RCB_Pos (6U)
10533 #define DSI_GPSR_RCB_Msk (0x1UL << DSI_GPSR_RCB_Pos) /*!< 0x00000040 */
10534 #define DSI_GPSR_RCB DSI_GPSR_RCB_Msk /*!< Read Command Busy */
10535
10536 /******************* Bit definition for DSI_TCCR0 register **************/
10537 #define DSI_TCCR0_LPRX_TOCNT_Pos (0U)
10538 #define DSI_TCCR0_LPRX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_LPRX_TOCNT_Pos) /*!< 0x0000FFFF */
10539 #define DSI_TCCR0_LPRX_TOCNT DSI_TCCR0_LPRX_TOCNT_Msk /*!< Low-power Reception Timeout Counter */
10540 #define DSI_TCCR0_LPRX_TOCNT0_Pos (0U)
10541 #define DSI_TCCR0_LPRX_TOCNT0_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT0_Pos) /*!< 0x00000001 */
10542 #define DSI_TCCR0_LPRX_TOCNT0 DSI_TCCR0_LPRX_TOCNT0_Msk
10543 #define DSI_TCCR0_LPRX_TOCNT1_Pos (1U)
10544 #define DSI_TCCR0_LPRX_TOCNT1_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT1_Pos) /*!< 0x00000002 */
10545 #define DSI_TCCR0_LPRX_TOCNT1 DSI_TCCR0_LPRX_TOCNT1_Msk
10546 #define DSI_TCCR0_LPRX_TOCNT2_Pos (2U)
10547 #define DSI_TCCR0_LPRX_TOCNT2_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT2_Pos) /*!< 0x00000004 */
10548 #define DSI_TCCR0_LPRX_TOCNT2 DSI_TCCR0_LPRX_TOCNT2_Msk
10549 #define DSI_TCCR0_LPRX_TOCNT3_Pos (3U)
10550 #define DSI_TCCR0_LPRX_TOCNT3_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT3_Pos) /*!< 0x00000008 */
10551 #define DSI_TCCR0_LPRX_TOCNT3 DSI_TCCR0_LPRX_TOCNT3_Msk
10552 #define DSI_TCCR0_LPRX_TOCNT4_Pos (4U)
10553 #define DSI_TCCR0_LPRX_TOCNT4_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT4_Pos) /*!< 0x00000010 */
10554 #define DSI_TCCR0_LPRX_TOCNT4 DSI_TCCR0_LPRX_TOCNT4_Msk
10555 #define DSI_TCCR0_LPRX_TOCNT5_Pos (5U)
10556 #define DSI_TCCR0_LPRX_TOCNT5_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT5_Pos) /*!< 0x00000020 */
10557 #define DSI_TCCR0_LPRX_TOCNT5 DSI_TCCR0_LPRX_TOCNT5_Msk
10558 #define DSI_TCCR0_LPRX_TOCNT6_Pos (6U)
10559 #define DSI_TCCR0_LPRX_TOCNT6_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT6_Pos) /*!< 0x00000040 */
10560 #define DSI_TCCR0_LPRX_TOCNT6 DSI_TCCR0_LPRX_TOCNT6_Msk
10561 #define DSI_TCCR0_LPRX_TOCNT7_Pos (7U)
10562 #define DSI_TCCR0_LPRX_TOCNT7_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT7_Pos) /*!< 0x00000080 */
10563 #define DSI_TCCR0_LPRX_TOCNT7 DSI_TCCR0_LPRX_TOCNT7_Msk
10564 #define DSI_TCCR0_LPRX_TOCNT8_Pos (8U)
10565 #define DSI_TCCR0_LPRX_TOCNT8_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT8_Pos) /*!< 0x00000100 */
10566 #define DSI_TCCR0_LPRX_TOCNT8 DSI_TCCR0_LPRX_TOCNT8_Msk
10567 #define DSI_TCCR0_LPRX_TOCNT9_Pos (9U)
10568 #define DSI_TCCR0_LPRX_TOCNT9_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT9_Pos) /*!< 0x00000200 */
10569 #define DSI_TCCR0_LPRX_TOCNT9 DSI_TCCR0_LPRX_TOCNT9_Msk
10570 #define DSI_TCCR0_LPRX_TOCNT10_Pos (10U)
10571 #define DSI_TCCR0_LPRX_TOCNT10_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT10_Pos) /*!< 0x00000400 */
10572 #define DSI_TCCR0_LPRX_TOCNT10 DSI_TCCR0_LPRX_TOCNT10_Msk
10573 #define DSI_TCCR0_LPRX_TOCNT11_Pos (11U)
10574 #define DSI_TCCR0_LPRX_TOCNT11_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT11_Pos) /*!< 0x00000800 */
10575 #define DSI_TCCR0_LPRX_TOCNT11 DSI_TCCR0_LPRX_TOCNT11_Msk
10576 #define DSI_TCCR0_LPRX_TOCNT12_Pos (12U)
10577 #define DSI_TCCR0_LPRX_TOCNT12_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT12_Pos) /*!< 0x00001000 */
10578 #define DSI_TCCR0_LPRX_TOCNT12 DSI_TCCR0_LPRX_TOCNT12_Msk
10579 #define DSI_TCCR0_LPRX_TOCNT13_Pos (13U)
10580 #define DSI_TCCR0_LPRX_TOCNT13_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT13_Pos) /*!< 0x00002000 */
10581 #define DSI_TCCR0_LPRX_TOCNT13 DSI_TCCR0_LPRX_TOCNT13_Msk
10582 #define DSI_TCCR0_LPRX_TOCNT14_Pos (14U)
10583 #define DSI_TCCR0_LPRX_TOCNT14_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT14_Pos) /*!< 0x00004000 */
10584 #define DSI_TCCR0_LPRX_TOCNT14 DSI_TCCR0_LPRX_TOCNT14_Msk
10585 #define DSI_TCCR0_LPRX_TOCNT15_Pos (15U)
10586 #define DSI_TCCR0_LPRX_TOCNT15_Msk (0x1UL << DSI_TCCR0_LPRX_TOCNT15_Pos) /*!< 0x00008000 */
10587 #define DSI_TCCR0_LPRX_TOCNT15 DSI_TCCR0_LPRX_TOCNT15_Msk
10588
10589 #define DSI_TCCR0_HSTX_TOCNT_Pos (16U)
10590 #define DSI_TCCR0_HSTX_TOCNT_Msk (0xFFFFUL << DSI_TCCR0_HSTX_TOCNT_Pos) /*!< 0xFFFF0000 */
10591 #define DSI_TCCR0_HSTX_TOCNT DSI_TCCR0_HSTX_TOCNT_Msk /*!< High-Speed Transmission Timeout Counter */
10592 #define DSI_TCCR0_HSTX_TOCNT0_Pos (16U)
10593 #define DSI_TCCR0_HSTX_TOCNT0_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT0_Pos) /*!< 0x00010000 */
10594 #define DSI_TCCR0_HSTX_TOCNT0 DSI_TCCR0_HSTX_TOCNT0_Msk
10595 #define DSI_TCCR0_HSTX_TOCNT1_Pos (17U)
10596 #define DSI_TCCR0_HSTX_TOCNT1_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT1_Pos) /*!< 0x00020000 */
10597 #define DSI_TCCR0_HSTX_TOCNT1 DSI_TCCR0_HSTX_TOCNT1_Msk
10598 #define DSI_TCCR0_HSTX_TOCNT2_Pos (18U)
10599 #define DSI_TCCR0_HSTX_TOCNT2_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT2_Pos) /*!< 0x00040000 */
10600 #define DSI_TCCR0_HSTX_TOCNT2 DSI_TCCR0_HSTX_TOCNT2_Msk
10601 #define DSI_TCCR0_HSTX_TOCNT3_Pos (19U)
10602 #define DSI_TCCR0_HSTX_TOCNT3_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT3_Pos) /*!< 0x00080000 */
10603 #define DSI_TCCR0_HSTX_TOCNT3 DSI_TCCR0_HSTX_TOCNT3_Msk
10604 #define DSI_TCCR0_HSTX_TOCNT4_Pos (20U)
10605 #define DSI_TCCR0_HSTX_TOCNT4_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT4_Pos) /*!< 0x00100000 */
10606 #define DSI_TCCR0_HSTX_TOCNT4 DSI_TCCR0_HSTX_TOCNT4_Msk
10607 #define DSI_TCCR0_HSTX_TOCNT5_Pos (21U)
10608 #define DSI_TCCR0_HSTX_TOCNT5_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT5_Pos) /*!< 0x00200000 */
10609 #define DSI_TCCR0_HSTX_TOCNT5 DSI_TCCR0_HSTX_TOCNT5_Msk
10610 #define DSI_TCCR0_HSTX_TOCNT6_Pos (22U)
10611 #define DSI_TCCR0_HSTX_TOCNT6_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT6_Pos) /*!< 0x00400000 */
10612 #define DSI_TCCR0_HSTX_TOCNT6 DSI_TCCR0_HSTX_TOCNT6_Msk
10613 #define DSI_TCCR0_HSTX_TOCNT7_Pos (23U)
10614 #define DSI_TCCR0_HSTX_TOCNT7_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT7_Pos) /*!< 0x00800000 */
10615 #define DSI_TCCR0_HSTX_TOCNT7 DSI_TCCR0_HSTX_TOCNT7_Msk
10616 #define DSI_TCCR0_HSTX_TOCNT8_Pos (24U)
10617 #define DSI_TCCR0_HSTX_TOCNT8_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT8_Pos) /*!< 0x01000000 */
10618 #define DSI_TCCR0_HSTX_TOCNT8 DSI_TCCR0_HSTX_TOCNT8_Msk
10619 #define DSI_TCCR0_HSTX_TOCNT9_Pos (25U)
10620 #define DSI_TCCR0_HSTX_TOCNT9_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT9_Pos) /*!< 0x02000000 */
10621 #define DSI_TCCR0_HSTX_TOCNT9 DSI_TCCR0_HSTX_TOCNT9_Msk
10622 #define DSI_TCCR0_HSTX_TOCNT10_Pos (26U)
10623 #define DSI_TCCR0_HSTX_TOCNT10_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT10_Pos) /*!< 0x04000000 */
10624 #define DSI_TCCR0_HSTX_TOCNT10 DSI_TCCR0_HSTX_TOCNT10_Msk
10625 #define DSI_TCCR0_HSTX_TOCNT11_Pos (27U)
10626 #define DSI_TCCR0_HSTX_TOCNT11_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT11_Pos) /*!< 0x08000000 */
10627 #define DSI_TCCR0_HSTX_TOCNT11 DSI_TCCR0_HSTX_TOCNT11_Msk
10628 #define DSI_TCCR0_HSTX_TOCNT12_Pos (28U)
10629 #define DSI_TCCR0_HSTX_TOCNT12_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT12_Pos) /*!< 0x10000000 */
10630 #define DSI_TCCR0_HSTX_TOCNT12 DSI_TCCR0_HSTX_TOCNT12_Msk
10631 #define DSI_TCCR0_HSTX_TOCNT13_Pos (29U)
10632 #define DSI_TCCR0_HSTX_TOCNT13_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT13_Pos) /*!< 0x20000000 */
10633 #define DSI_TCCR0_HSTX_TOCNT13 DSI_TCCR0_HSTX_TOCNT13_Msk
10634 #define DSI_TCCR0_HSTX_TOCNT14_Pos (30U)
10635 #define DSI_TCCR0_HSTX_TOCNT14_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT14_Pos) /*!< 0x40000000 */
10636 #define DSI_TCCR0_HSTX_TOCNT14 DSI_TCCR0_HSTX_TOCNT14_Msk
10637 #define DSI_TCCR0_HSTX_TOCNT15_Pos (31U)
10638 #define DSI_TCCR0_HSTX_TOCNT15_Msk (0x1UL << DSI_TCCR0_HSTX_TOCNT15_Pos) /*!< 0x80000000 */
10639 #define DSI_TCCR0_HSTX_TOCNT15 DSI_TCCR0_HSTX_TOCNT15_Msk
10640
10641 /******************* Bit definition for DSI_TCCR1 register **************/
10642 #define DSI_TCCR1_HSRD_TOCNT_Pos (0U)
10643 #define DSI_TCCR1_HSRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR1_HSRD_TOCNT_Pos) /*!< 0x0000FFFF */
10644 #define DSI_TCCR1_HSRD_TOCNT DSI_TCCR1_HSRD_TOCNT_Msk /*!< High-Speed Read Timeout Counter */
10645 #define DSI_TCCR1_HSRD_TOCNT0_Pos (0U)
10646 #define DSI_TCCR1_HSRD_TOCNT0_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT0_Pos) /*!< 0x00000001 */
10647 #define DSI_TCCR1_HSRD_TOCNT0 DSI_TCCR1_HSRD_TOCNT0_Msk
10648 #define DSI_TCCR1_HSRD_TOCNT1_Pos (1U)
10649 #define DSI_TCCR1_HSRD_TOCNT1_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT1_Pos) /*!< 0x00000002 */
10650 #define DSI_TCCR1_HSRD_TOCNT1 DSI_TCCR1_HSRD_TOCNT1_Msk
10651 #define DSI_TCCR1_HSRD_TOCNT2_Pos (2U)
10652 #define DSI_TCCR1_HSRD_TOCNT2_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT2_Pos) /*!< 0x00000004 */
10653 #define DSI_TCCR1_HSRD_TOCNT2 DSI_TCCR1_HSRD_TOCNT2_Msk
10654 #define DSI_TCCR1_HSRD_TOCNT3_Pos (3U)
10655 #define DSI_TCCR1_HSRD_TOCNT3_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT3_Pos) /*!< 0x00000008 */
10656 #define DSI_TCCR1_HSRD_TOCNT3 DSI_TCCR1_HSRD_TOCNT3_Msk
10657 #define DSI_TCCR1_HSRD_TOCNT4_Pos (4U)
10658 #define DSI_TCCR1_HSRD_TOCNT4_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT4_Pos) /*!< 0x00000010 */
10659 #define DSI_TCCR1_HSRD_TOCNT4 DSI_TCCR1_HSRD_TOCNT4_Msk
10660 #define DSI_TCCR1_HSRD_TOCNT5_Pos (5U)
10661 #define DSI_TCCR1_HSRD_TOCNT5_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT5_Pos) /*!< 0x00000020 */
10662 #define DSI_TCCR1_HSRD_TOCNT5 DSI_TCCR1_HSRD_TOCNT5_Msk
10663 #define DSI_TCCR1_HSRD_TOCNT6_Pos (6U)
10664 #define DSI_TCCR1_HSRD_TOCNT6_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT6_Pos) /*!< 0x00000040 */
10665 #define DSI_TCCR1_HSRD_TOCNT6 DSI_TCCR1_HSRD_TOCNT6_Msk
10666 #define DSI_TCCR1_HSRD_TOCNT7_Pos (7U)
10667 #define DSI_TCCR1_HSRD_TOCNT7_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT7_Pos) /*!< 0x00000080 */
10668 #define DSI_TCCR1_HSRD_TOCNT7 DSI_TCCR1_HSRD_TOCNT7_Msk
10669 #define DSI_TCCR1_HSRD_TOCNT8_Pos (8U)
10670 #define DSI_TCCR1_HSRD_TOCNT8_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT8_Pos) /*!< 0x00000100 */
10671 #define DSI_TCCR1_HSRD_TOCNT8 DSI_TCCR1_HSRD_TOCNT8_Msk
10672 #define DSI_TCCR1_HSRD_TOCNT9_Pos (9U)
10673 #define DSI_TCCR1_HSRD_TOCNT9_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT9_Pos) /*!< 0x00000200 */
10674 #define DSI_TCCR1_HSRD_TOCNT9 DSI_TCCR1_HSRD_TOCNT9_Msk
10675 #define DSI_TCCR1_HSRD_TOCNT10_Pos (10U)
10676 #define DSI_TCCR1_HSRD_TOCNT10_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT10_Pos) /*!< 0x00000400 */
10677 #define DSI_TCCR1_HSRD_TOCNT10 DSI_TCCR1_HSRD_TOCNT10_Msk
10678 #define DSI_TCCR1_HSRD_TOCNT11_Pos (11U)
10679 #define DSI_TCCR1_HSRD_TOCNT11_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT11_Pos) /*!< 0x00000800 */
10680 #define DSI_TCCR1_HSRD_TOCNT11 DSI_TCCR1_HSRD_TOCNT11_Msk
10681 #define DSI_TCCR1_HSRD_TOCNT12_Pos (12U)
10682 #define DSI_TCCR1_HSRD_TOCNT12_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT12_Pos) /*!< 0x00001000 */
10683 #define DSI_TCCR1_HSRD_TOCNT12 DSI_TCCR1_HSRD_TOCNT12_Msk
10684 #define DSI_TCCR1_HSRD_TOCNT13_Pos (13U)
10685 #define DSI_TCCR1_HSRD_TOCNT13_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT13_Pos) /*!< 0x00002000 */
10686 #define DSI_TCCR1_HSRD_TOCNT13 DSI_TCCR1_HSRD_TOCNT13_Msk
10687 #define DSI_TCCR1_HSRD_TOCNT14_Pos (14U)
10688 #define DSI_TCCR1_HSRD_TOCNT14_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT14_Pos) /*!< 0x00004000 */
10689 #define DSI_TCCR1_HSRD_TOCNT14 DSI_TCCR1_HSRD_TOCNT14_Msk
10690 #define DSI_TCCR1_HSRD_TOCNT15_Pos (15U)
10691 #define DSI_TCCR1_HSRD_TOCNT15_Msk (0x1UL << DSI_TCCR1_HSRD_TOCNT15_Pos) /*!< 0x00008000 */
10692 #define DSI_TCCR1_HSRD_TOCNT15 DSI_TCCR1_HSRD_TOCNT15_Msk
10693
10694 /******************* Bit definition for DSI_TCCR2 register **************/
10695 #define DSI_TCCR2_LPRD_TOCNT_Pos (0U)
10696 #define DSI_TCCR2_LPRD_TOCNT_Msk (0xFFFFUL << DSI_TCCR2_LPRD_TOCNT_Pos) /*!< 0x0000FFFF */
10697 #define DSI_TCCR2_LPRD_TOCNT DSI_TCCR2_LPRD_TOCNT_Msk /*!< Low-Power Read Timeout Counter */
10698 #define DSI_TCCR2_LPRD_TOCNT0_Pos (0U)
10699 #define DSI_TCCR2_LPRD_TOCNT0_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT0_Pos) /*!< 0x00000001 */
10700 #define DSI_TCCR2_LPRD_TOCNT0 DSI_TCCR2_LPRD_TOCNT0_Msk
10701 #define DSI_TCCR2_LPRD_TOCNT1_Pos (1U)
10702 #define DSI_TCCR2_LPRD_TOCNT1_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT1_Pos) /*!< 0x00000002 */
10703 #define DSI_TCCR2_LPRD_TOCNT1 DSI_TCCR2_LPRD_TOCNT1_Msk
10704 #define DSI_TCCR2_LPRD_TOCNT2_Pos (2U)
10705 #define DSI_TCCR2_LPRD_TOCNT2_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT2_Pos) /*!< 0x00000004 */
10706 #define DSI_TCCR2_LPRD_TOCNT2 DSI_TCCR2_LPRD_TOCNT2_Msk
10707 #define DSI_TCCR2_LPRD_TOCNT3_Pos (3U)
10708 #define DSI_TCCR2_LPRD_TOCNT3_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT3_Pos) /*!< 0x00000008 */
10709 #define DSI_TCCR2_LPRD_TOCNT3 DSI_TCCR2_LPRD_TOCNT3_Msk
10710 #define DSI_TCCR2_LPRD_TOCNT4_Pos (4U)
10711 #define DSI_TCCR2_LPRD_TOCNT4_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT4_Pos) /*!< 0x00000010 */
10712 #define DSI_TCCR2_LPRD_TOCNT4 DSI_TCCR2_LPRD_TOCNT4_Msk
10713 #define DSI_TCCR2_LPRD_TOCNT5_Pos (5U)
10714 #define DSI_TCCR2_LPRD_TOCNT5_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT5_Pos) /*!< 0x00000020 */
10715 #define DSI_TCCR2_LPRD_TOCNT5 DSI_TCCR2_LPRD_TOCNT5_Msk
10716 #define DSI_TCCR2_LPRD_TOCNT6_Pos (6U)
10717 #define DSI_TCCR2_LPRD_TOCNT6_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT6_Pos) /*!< 0x00000040 */
10718 #define DSI_TCCR2_LPRD_TOCNT6 DSI_TCCR2_LPRD_TOCNT6_Msk
10719 #define DSI_TCCR2_LPRD_TOCNT7_Pos (7U)
10720 #define DSI_TCCR2_LPRD_TOCNT7_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT7_Pos) /*!< 0x00000080 */
10721 #define DSI_TCCR2_LPRD_TOCNT7 DSI_TCCR2_LPRD_TOCNT7_Msk
10722 #define DSI_TCCR2_LPRD_TOCNT8_Pos (8U)
10723 #define DSI_TCCR2_LPRD_TOCNT8_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT8_Pos) /*!< 0x00000100 */
10724 #define DSI_TCCR2_LPRD_TOCNT8 DSI_TCCR2_LPRD_TOCNT8_Msk
10725 #define DSI_TCCR2_LPRD_TOCNT9_Pos (9U)
10726 #define DSI_TCCR2_LPRD_TOCNT9_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT9_Pos) /*!< 0x00000200 */
10727 #define DSI_TCCR2_LPRD_TOCNT9 DSI_TCCR2_LPRD_TOCNT9_Msk
10728 #define DSI_TCCR2_LPRD_TOCNT10_Pos (10U)
10729 #define DSI_TCCR2_LPRD_TOCNT10_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT10_Pos) /*!< 0x00000400 */
10730 #define DSI_TCCR2_LPRD_TOCNT10 DSI_TCCR2_LPRD_TOCNT10_Msk
10731 #define DSI_TCCR2_LPRD_TOCNT11_Pos (11U)
10732 #define DSI_TCCR2_LPRD_TOCNT11_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT11_Pos) /*!< 0x00000800 */
10733 #define DSI_TCCR2_LPRD_TOCNT11 DSI_TCCR2_LPRD_TOCNT11_Msk
10734 #define DSI_TCCR2_LPRD_TOCNT12_Pos (12U)
10735 #define DSI_TCCR2_LPRD_TOCNT12_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT12_Pos) /*!< 0x00001000 */
10736 #define DSI_TCCR2_LPRD_TOCNT12 DSI_TCCR2_LPRD_TOCNT12_Msk
10737 #define DSI_TCCR2_LPRD_TOCNT13_Pos (13U)
10738 #define DSI_TCCR2_LPRD_TOCNT13_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT13_Pos) /*!< 0x00002000 */
10739 #define DSI_TCCR2_LPRD_TOCNT13 DSI_TCCR2_LPRD_TOCNT13_Msk
10740 #define DSI_TCCR2_LPRD_TOCNT14_Pos (14U)
10741 #define DSI_TCCR2_LPRD_TOCNT14_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT14_Pos) /*!< 0x00004000 */
10742 #define DSI_TCCR2_LPRD_TOCNT14 DSI_TCCR2_LPRD_TOCNT14_Msk
10743 #define DSI_TCCR2_LPRD_TOCNT15_Pos (15U)
10744 #define DSI_TCCR2_LPRD_TOCNT15_Msk (0x1UL << DSI_TCCR2_LPRD_TOCNT15_Pos) /*!< 0x00008000 */
10745 #define DSI_TCCR2_LPRD_TOCNT15 DSI_TCCR2_LPRD_TOCNT15_Msk
10746
10747 /******************* Bit definition for DSI_TCCR3 register **************/
10748 #define DSI_TCCR3_HSWR_TOCNT_Pos (0U)
10749 #define DSI_TCCR3_HSWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR3_HSWR_TOCNT_Pos) /*!< 0x0000FFFF */
10750 #define DSI_TCCR3_HSWR_TOCNT DSI_TCCR3_HSWR_TOCNT_Msk /*!< High-Speed Write Timeout Counter */
10751 #define DSI_TCCR3_HSWR_TOCNT0_Pos (0U)
10752 #define DSI_TCCR3_HSWR_TOCNT0_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT0_Pos) /*!< 0x00000001 */
10753 #define DSI_TCCR3_HSWR_TOCNT0 DSI_TCCR3_HSWR_TOCNT0_Msk
10754 #define DSI_TCCR3_HSWR_TOCNT1_Pos (1U)
10755 #define DSI_TCCR3_HSWR_TOCNT1_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT1_Pos) /*!< 0x00000002 */
10756 #define DSI_TCCR3_HSWR_TOCNT1 DSI_TCCR3_HSWR_TOCNT1_Msk
10757 #define DSI_TCCR3_HSWR_TOCNT2_Pos (2U)
10758 #define DSI_TCCR3_HSWR_TOCNT2_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT2_Pos) /*!< 0x00000004 */
10759 #define DSI_TCCR3_HSWR_TOCNT2 DSI_TCCR3_HSWR_TOCNT2_Msk
10760 #define DSI_TCCR3_HSWR_TOCNT3_Pos (3U)
10761 #define DSI_TCCR3_HSWR_TOCNT3_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT3_Pos) /*!< 0x00000008 */
10762 #define DSI_TCCR3_HSWR_TOCNT3 DSI_TCCR3_HSWR_TOCNT3_Msk
10763 #define DSI_TCCR3_HSWR_TOCNT4_Pos (4U)
10764 #define DSI_TCCR3_HSWR_TOCNT4_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT4_Pos) /*!< 0x00000010 */
10765 #define DSI_TCCR3_HSWR_TOCNT4 DSI_TCCR3_HSWR_TOCNT4_Msk
10766 #define DSI_TCCR3_HSWR_TOCNT5_Pos (5U)
10767 #define DSI_TCCR3_HSWR_TOCNT5_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT5_Pos) /*!< 0x00000020 */
10768 #define DSI_TCCR3_HSWR_TOCNT5 DSI_TCCR3_HSWR_TOCNT5_Msk
10769 #define DSI_TCCR3_HSWR_TOCNT6_Pos (6U)
10770 #define DSI_TCCR3_HSWR_TOCNT6_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT6_Pos) /*!< 0x00000040 */
10771 #define DSI_TCCR3_HSWR_TOCNT6 DSI_TCCR3_HSWR_TOCNT6_Msk
10772 #define DSI_TCCR3_HSWR_TOCNT7_Pos (7U)
10773 #define DSI_TCCR3_HSWR_TOCNT7_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT7_Pos) /*!< 0x00000080 */
10774 #define DSI_TCCR3_HSWR_TOCNT7 DSI_TCCR3_HSWR_TOCNT7_Msk
10775 #define DSI_TCCR3_HSWR_TOCNT8_Pos (8U)
10776 #define DSI_TCCR3_HSWR_TOCNT8_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT8_Pos) /*!< 0x00000100 */
10777 #define DSI_TCCR3_HSWR_TOCNT8 DSI_TCCR3_HSWR_TOCNT8_Msk
10778 #define DSI_TCCR3_HSWR_TOCNT9_Pos (9U)
10779 #define DSI_TCCR3_HSWR_TOCNT9_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT9_Pos) /*!< 0x00000200 */
10780 #define DSI_TCCR3_HSWR_TOCNT9 DSI_TCCR3_HSWR_TOCNT9_Msk
10781 #define DSI_TCCR3_HSWR_TOCNT10_Pos (10U)
10782 #define DSI_TCCR3_HSWR_TOCNT10_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT10_Pos) /*!< 0x00000400 */
10783 #define DSI_TCCR3_HSWR_TOCNT10 DSI_TCCR3_HSWR_TOCNT10_Msk
10784 #define DSI_TCCR3_HSWR_TOCNT11_Pos (11U)
10785 #define DSI_TCCR3_HSWR_TOCNT11_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT11_Pos) /*!< 0x00000800 */
10786 #define DSI_TCCR3_HSWR_TOCNT11 DSI_TCCR3_HSWR_TOCNT11_Msk
10787 #define DSI_TCCR3_HSWR_TOCNT12_Pos (12U)
10788 #define DSI_TCCR3_HSWR_TOCNT12_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT12_Pos) /*!< 0x00001000 */
10789 #define DSI_TCCR3_HSWR_TOCNT12 DSI_TCCR3_HSWR_TOCNT12_Msk
10790 #define DSI_TCCR3_HSWR_TOCNT13_Pos (13U)
10791 #define DSI_TCCR3_HSWR_TOCNT13_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT13_Pos) /*!< 0x00002000 */
10792 #define DSI_TCCR3_HSWR_TOCNT13 DSI_TCCR3_HSWR_TOCNT13_Msk
10793 #define DSI_TCCR3_HSWR_TOCNT14_Pos (14U)
10794 #define DSI_TCCR3_HSWR_TOCNT14_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT14_Pos) /*!< 0x00004000 */
10795 #define DSI_TCCR3_HSWR_TOCNT14 DSI_TCCR3_HSWR_TOCNT14_Msk
10796 #define DSI_TCCR3_HSWR_TOCNT15_Pos (15U)
10797 #define DSI_TCCR3_HSWR_TOCNT15_Msk (0x1UL << DSI_TCCR3_HSWR_TOCNT15_Pos) /*!< 0x00008000 */
10798 #define DSI_TCCR3_HSWR_TOCNT15 DSI_TCCR3_HSWR_TOCNT15_Msk
10799
10800 #define DSI_TCCR3_PM_Pos (24U)
10801 #define DSI_TCCR3_PM_Msk (0x1UL << DSI_TCCR3_PM_Pos) /*!< 0x01000000 */
10802 #define DSI_TCCR3_PM DSI_TCCR3_PM_Msk /*!< Presp Mode */
10803
10804 /******************* Bit definition for DSI_TCCR4 register **************/
10805 #define DSI_TCCR4_LPWR_TOCNT_Pos (0U)
10806 #define DSI_TCCR4_LPWR_TOCNT_Msk (0xFFFFUL << DSI_TCCR4_LPWR_TOCNT_Pos) /*!< 0x0000FFFF */
10807 #define DSI_TCCR4_LPWR_TOCNT DSI_TCCR4_LPWR_TOCNT_Msk /*!< Low-Power Write Timeout Counter */
10808 #define DSI_TCCR4_LPWR_TOCNT0_Pos (0U)
10809 #define DSI_TCCR4_LPWR_TOCNT0_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT0_Pos) /*!< 0x00000001 */
10810 #define DSI_TCCR4_LPWR_TOCNT0 DSI_TCCR4_LPWR_TOCNT0_Msk
10811 #define DSI_TCCR4_LPWR_TOCNT1_Pos (1U)
10812 #define DSI_TCCR4_LPWR_TOCNT1_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT1_Pos) /*!< 0x00000002 */
10813 #define DSI_TCCR4_LPWR_TOCNT1 DSI_TCCR4_LPWR_TOCNT1_Msk
10814 #define DSI_TCCR4_LPWR_TOCNT2_Pos (2U)
10815 #define DSI_TCCR4_LPWR_TOCNT2_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT2_Pos) /*!< 0x00000004 */
10816 #define DSI_TCCR4_LPWR_TOCNT2 DSI_TCCR4_LPWR_TOCNT2_Msk
10817 #define DSI_TCCR4_LPWR_TOCNT3_Pos (3U)
10818 #define DSI_TCCR4_LPWR_TOCNT3_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT3_Pos) /*!< 0x00000008 */
10819 #define DSI_TCCR4_LPWR_TOCNT3 DSI_TCCR4_LPWR_TOCNT3_Msk
10820 #define DSI_TCCR4_LPWR_TOCNT4_Pos (4U)
10821 #define DSI_TCCR4_LPWR_TOCNT4_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT4_Pos) /*!< 0x00000010 */
10822 #define DSI_TCCR4_LPWR_TOCNT4 DSI_TCCR4_LPWR_TOCNT4_Msk
10823 #define DSI_TCCR4_LPWR_TOCNT5_Pos (5U)
10824 #define DSI_TCCR4_LPWR_TOCNT5_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT5_Pos) /*!< 0x00000020 */
10825 #define DSI_TCCR4_LPWR_TOCNT5 DSI_TCCR4_LPWR_TOCNT5_Msk
10826 #define DSI_TCCR4_LPWR_TOCNT6_Pos (6U)
10827 #define DSI_TCCR4_LPWR_TOCNT6_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT6_Pos) /*!< 0x00000040 */
10828 #define DSI_TCCR4_LPWR_TOCNT6 DSI_TCCR4_LPWR_TOCNT6_Msk
10829 #define DSI_TCCR4_LPWR_TOCNT7_Pos (7U)
10830 #define DSI_TCCR4_LPWR_TOCNT7_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT7_Pos) /*!< 0x00000080 */
10831 #define DSI_TCCR4_LPWR_TOCNT7 DSI_TCCR4_LPWR_TOCNT7_Msk
10832 #define DSI_TCCR4_LPWR_TOCNT8_Pos (8U)
10833 #define DSI_TCCR4_LPWR_TOCNT8_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT8_Pos) /*!< 0x00000100 */
10834 #define DSI_TCCR4_LPWR_TOCNT8 DSI_TCCR4_LPWR_TOCNT8_Msk
10835 #define DSI_TCCR4_LPWR_TOCNT9_Pos (9U)
10836 #define DSI_TCCR4_LPWR_TOCNT9_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT9_Pos) /*!< 0x00000200 */
10837 #define DSI_TCCR4_LPWR_TOCNT9 DSI_TCCR4_LPWR_TOCNT9_Msk
10838 #define DSI_TCCR4_LPWR_TOCNT10_Pos (10U)
10839 #define DSI_TCCR4_LPWR_TOCNT10_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT10_Pos) /*!< 0x00000400 */
10840 #define DSI_TCCR4_LPWR_TOCNT10 DSI_TCCR4_LPWR_TOCNT10_Msk
10841 #define DSI_TCCR4_LPWR_TOCNT11_Pos (11U)
10842 #define DSI_TCCR4_LPWR_TOCNT11_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT11_Pos) /*!< 0x00000800 */
10843 #define DSI_TCCR4_LPWR_TOCNT11 DSI_TCCR4_LPWR_TOCNT11_Msk
10844 #define DSI_TCCR4_LPWR_TOCNT12_Pos (12U)
10845 #define DSI_TCCR4_LPWR_TOCNT12_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT12_Pos) /*!< 0x00001000 */
10846 #define DSI_TCCR4_LPWR_TOCNT12 DSI_TCCR4_LPWR_TOCNT12_Msk
10847 #define DSI_TCCR4_LPWR_TOCNT13_Pos (13U)
10848 #define DSI_TCCR4_LPWR_TOCNT13_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT13_Pos) /*!< 0x00002000 */
10849 #define DSI_TCCR4_LPWR_TOCNT13 DSI_TCCR4_LPWR_TOCNT13_Msk
10850 #define DSI_TCCR4_LPWR_TOCNT14_Pos (14U)
10851 #define DSI_TCCR4_LPWR_TOCNT14_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT14_Pos) /*!< 0x00004000 */
10852 #define DSI_TCCR4_LPWR_TOCNT14 DSI_TCCR4_LPWR_TOCNT14_Msk
10853 #define DSI_TCCR4_LPWR_TOCNT15_Pos (15U)
10854 #define DSI_TCCR4_LPWR_TOCNT15_Msk (0x1UL << DSI_TCCR4_LPWR_TOCNT15_Pos) /*!< 0x00008000 */
10855 #define DSI_TCCR4_LPWR_TOCNT15 DSI_TCCR4_LPWR_TOCNT15_Msk
10856
10857 /******************* Bit definition for DSI_TCCR5 register **************/
10858 #define DSI_TCCR5_BTA_TOCNT_Pos (0U)
10859 #define DSI_TCCR5_BTA_TOCNT_Msk (0xFFFFUL << DSI_TCCR5_BTA_TOCNT_Pos) /*!< 0x0000FFFF */
10860 #define DSI_TCCR5_BTA_TOCNT DSI_TCCR5_BTA_TOCNT_Msk /*!< Bus-Turn-Around Timeout Counter */
10861 #define DSI_TCCR5_BTA_TOCNT0_Pos (0U)
10862 #define DSI_TCCR5_BTA_TOCNT0_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT0_Pos) /*!< 0x00000001 */
10863 #define DSI_TCCR5_BTA_TOCNT0 DSI_TCCR5_BTA_TOCNT0_Msk
10864 #define DSI_TCCR5_BTA_TOCNT1_Pos (1U)
10865 #define DSI_TCCR5_BTA_TOCNT1_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT1_Pos) /*!< 0x00000002 */
10866 #define DSI_TCCR5_BTA_TOCNT1 DSI_TCCR5_BTA_TOCNT1_Msk
10867 #define DSI_TCCR5_BTA_TOCNT2_Pos (2U)
10868 #define DSI_TCCR5_BTA_TOCNT2_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT2_Pos) /*!< 0x00000004 */
10869 #define DSI_TCCR5_BTA_TOCNT2 DSI_TCCR5_BTA_TOCNT2_Msk
10870 #define DSI_TCCR5_BTA_TOCNT3_Pos (3U)
10871 #define DSI_TCCR5_BTA_TOCNT3_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT3_Pos) /*!< 0x00000008 */
10872 #define DSI_TCCR5_BTA_TOCNT3 DSI_TCCR5_BTA_TOCNT3_Msk
10873 #define DSI_TCCR5_BTA_TOCNT4_Pos (4U)
10874 #define DSI_TCCR5_BTA_TOCNT4_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT4_Pos) /*!< 0x00000010 */
10875 #define DSI_TCCR5_BTA_TOCNT4 DSI_TCCR5_BTA_TOCNT4_Msk
10876 #define DSI_TCCR5_BTA_TOCNT5_Pos (5U)
10877 #define DSI_TCCR5_BTA_TOCNT5_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT5_Pos) /*!< 0x00000020 */
10878 #define DSI_TCCR5_BTA_TOCNT5 DSI_TCCR5_BTA_TOCNT5_Msk
10879 #define DSI_TCCR5_BTA_TOCNT6_Pos (6U)
10880 #define DSI_TCCR5_BTA_TOCNT6_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT6_Pos) /*!< 0x00000040 */
10881 #define DSI_TCCR5_BTA_TOCNT6 DSI_TCCR5_BTA_TOCNT6_Msk
10882 #define DSI_TCCR5_BTA_TOCNT7_Pos (7U)
10883 #define DSI_TCCR5_BTA_TOCNT7_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT7_Pos) /*!< 0x00000080 */
10884 #define DSI_TCCR5_BTA_TOCNT7 DSI_TCCR5_BTA_TOCNT7_Msk
10885 #define DSI_TCCR5_BTA_TOCNT8_Pos (8U)
10886 #define DSI_TCCR5_BTA_TOCNT8_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT8_Pos) /*!< 0x00000100 */
10887 #define DSI_TCCR5_BTA_TOCNT8 DSI_TCCR5_BTA_TOCNT8_Msk
10888 #define DSI_TCCR5_BTA_TOCNT9_Pos (9U)
10889 #define DSI_TCCR5_BTA_TOCNT9_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT9_Pos) /*!< 0x00000200 */
10890 #define DSI_TCCR5_BTA_TOCNT9 DSI_TCCR5_BTA_TOCNT9_Msk
10891 #define DSI_TCCR5_BTA_TOCNT10_Pos (10U)
10892 #define DSI_TCCR5_BTA_TOCNT10_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT10_Pos) /*!< 0x00000400 */
10893 #define DSI_TCCR5_BTA_TOCNT10 DSI_TCCR5_BTA_TOCNT10_Msk
10894 #define DSI_TCCR5_BTA_TOCNT11_Pos (11U)
10895 #define DSI_TCCR5_BTA_TOCNT11_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT11_Pos) /*!< 0x00000800 */
10896 #define DSI_TCCR5_BTA_TOCNT11 DSI_TCCR5_BTA_TOCNT11_Msk
10897 #define DSI_TCCR5_BTA_TOCNT12_Pos (12U)
10898 #define DSI_TCCR5_BTA_TOCNT12_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT12_Pos) /*!< 0x00001000 */
10899 #define DSI_TCCR5_BTA_TOCNT12 DSI_TCCR5_BTA_TOCNT12_Msk
10900 #define DSI_TCCR5_BTA_TOCNT13_Pos (13U)
10901 #define DSI_TCCR5_BTA_TOCNT13_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT13_Pos) /*!< 0x00002000 */
10902 #define DSI_TCCR5_BTA_TOCNT13 DSI_TCCR5_BTA_TOCNT13_Msk
10903 #define DSI_TCCR5_BTA_TOCNT14_Pos (14U)
10904 #define DSI_TCCR5_BTA_TOCNT14_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT14_Pos) /*!< 0x00004000 */
10905 #define DSI_TCCR5_BTA_TOCNT14 DSI_TCCR5_BTA_TOCNT14_Msk
10906 #define DSI_TCCR5_BTA_TOCNT15_Pos (15U)
10907 #define DSI_TCCR5_BTA_TOCNT15_Msk (0x1UL << DSI_TCCR5_BTA_TOCNT15_Pos) /*!< 0x00008000 */
10908 #define DSI_TCCR5_BTA_TOCNT15 DSI_TCCR5_BTA_TOCNT15_Msk
10909
10910 /******************* Bit definition for DSI_TDCR register ***************/
10911 #define DSI_TDCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
10912 #define DSI_TDCR_3DM0 ((uint32_t)0x00000001U)
10913 #define DSI_TDCR_3DM1 ((uint32_t)0x00000002U)
10914
10915 #define DSI_TDCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
10916 #define DSI_TDCR_3DF0 ((uint32_t)0x00000004U)
10917 #define DSI_TDCR_3DF1 ((uint32_t)0x00000008U)
10918
10919 #define DSI_TDCR_SVS_Pos (4U)
10920 #define DSI_TDCR_SVS_Msk (0x1UL << DSI_TDCR_SVS_Pos) /*!< 0x00000010 */
10921 #define DSI_TDCR_SVS DSI_TDCR_SVS_Msk /*!< Second VSYNC */
10922 #define DSI_TDCR_RF_Pos (5U)
10923 #define DSI_TDCR_RF_Msk (0x1UL << DSI_TDCR_RF_Pos) /*!< 0x00000020 */
10924 #define DSI_TDCR_RF DSI_TDCR_RF_Msk /*!< Right First */
10925 #define DSI_TDCR_S3DC_Pos (16U)
10926 #define DSI_TDCR_S3DC_Msk (0x1UL << DSI_TDCR_S3DC_Pos) /*!< 0x00010000 */
10927 #define DSI_TDCR_S3DC DSI_TDCR_S3DC_Msk /*!< Send 3D Control */
10928
10929 /******************* Bit definition for DSI_CLCR register ***************/
10930 #define DSI_CLCR_DPCC_Pos (0U)
10931 #define DSI_CLCR_DPCC_Msk (0x1UL << DSI_CLCR_DPCC_Pos) /*!< 0x00000001 */
10932 #define DSI_CLCR_DPCC DSI_CLCR_DPCC_Msk /*!< D-PHY Clock Control */
10933 #define DSI_CLCR_ACR_Pos (1U)
10934 #define DSI_CLCR_ACR_Msk (0x1UL << DSI_CLCR_ACR_Pos) /*!< 0x00000002 */
10935 #define DSI_CLCR_ACR DSI_CLCR_ACR_Msk /*!< Automatic Clocklane Control */
10936
10937 /******************* Bit definition for DSI_CLTCR register **************/
10938 #define DSI_CLTCR_LP2HS_TIME_Pos (0U)
10939 #define DSI_CLTCR_LP2HS_TIME_Msk (0x3FFUL << DSI_CLTCR_LP2HS_TIME_Pos) /*!< 0x000003FF */
10940 #define DSI_CLTCR_LP2HS_TIME DSI_CLTCR_LP2HS_TIME_Msk /*!< Low-Power to High-Speed Time */
10941 #define DSI_CLTCR_LP2HS_TIME0_Pos (0U)
10942 #define DSI_CLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME0_Pos) /*!< 0x00000001 */
10943 #define DSI_CLTCR_LP2HS_TIME0 DSI_CLTCR_LP2HS_TIME0_Msk
10944 #define DSI_CLTCR_LP2HS_TIME1_Pos (1U)
10945 #define DSI_CLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME1_Pos) /*!< 0x00000002 */
10946 #define DSI_CLTCR_LP2HS_TIME1 DSI_CLTCR_LP2HS_TIME1_Msk
10947 #define DSI_CLTCR_LP2HS_TIME2_Pos (2U)
10948 #define DSI_CLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME2_Pos) /*!< 0x00000004 */
10949 #define DSI_CLTCR_LP2HS_TIME2 DSI_CLTCR_LP2HS_TIME2_Msk
10950 #define DSI_CLTCR_LP2HS_TIME3_Pos (3U)
10951 #define DSI_CLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME3_Pos) /*!< 0x00000008 */
10952 #define DSI_CLTCR_LP2HS_TIME3 DSI_CLTCR_LP2HS_TIME3_Msk
10953 #define DSI_CLTCR_LP2HS_TIME4_Pos (4U)
10954 #define DSI_CLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME4_Pos) /*!< 0x00000010 */
10955 #define DSI_CLTCR_LP2HS_TIME4 DSI_CLTCR_LP2HS_TIME4_Msk
10956 #define DSI_CLTCR_LP2HS_TIME5_Pos (5U)
10957 #define DSI_CLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME5_Pos) /*!< 0x00000020 */
10958 #define DSI_CLTCR_LP2HS_TIME5 DSI_CLTCR_LP2HS_TIME5_Msk
10959 #define DSI_CLTCR_LP2HS_TIME6_Pos (6U)
10960 #define DSI_CLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME6_Pos) /*!< 0x00000040 */
10961 #define DSI_CLTCR_LP2HS_TIME6 DSI_CLTCR_LP2HS_TIME6_Msk
10962 #define DSI_CLTCR_LP2HS_TIME7_Pos (7U)
10963 #define DSI_CLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME7_Pos) /*!< 0x00000080 */
10964 #define DSI_CLTCR_LP2HS_TIME7 DSI_CLTCR_LP2HS_TIME7_Msk
10965 #define DSI_CLTCR_LP2HS_TIME8_Pos (8U)
10966 #define DSI_CLTCR_LP2HS_TIME8_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME8_Pos) /*!< 0x00000100 */
10967 #define DSI_CLTCR_LP2HS_TIME8 DSI_CLTCR_LP2HS_TIME8_Msk
10968 #define DSI_CLTCR_LP2HS_TIME9_Pos (9U)
10969 #define DSI_CLTCR_LP2HS_TIME9_Msk (0x1UL << DSI_CLTCR_LP2HS_TIME9_Pos) /*!< 0x00000200 */
10970 #define DSI_CLTCR_LP2HS_TIME9 DSI_CLTCR_LP2HS_TIME9_Msk
10971
10972 #define DSI_CLTCR_HS2LP_TIME_Pos (16U)
10973 #define DSI_CLTCR_HS2LP_TIME_Msk (0x3FFUL << DSI_CLTCR_HS2LP_TIME_Pos) /*!< 0x03FF0000 */
10974 #define DSI_CLTCR_HS2LP_TIME DSI_CLTCR_HS2LP_TIME_Msk /*!< High-Speed to Low-Power Time */
10975 #define DSI_CLTCR_HS2LP_TIME0_Pos (16U)
10976 #define DSI_CLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME0_Pos) /*!< 0x00010000 */
10977 #define DSI_CLTCR_HS2LP_TIME0 DSI_CLTCR_HS2LP_TIME0_Msk
10978 #define DSI_CLTCR_HS2LP_TIME1_Pos (17U)
10979 #define DSI_CLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME1_Pos) /*!< 0x00020000 */
10980 #define DSI_CLTCR_HS2LP_TIME1 DSI_CLTCR_HS2LP_TIME1_Msk
10981 #define DSI_CLTCR_HS2LP_TIME2_Pos (18U)
10982 #define DSI_CLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME2_Pos) /*!< 0x00040000 */
10983 #define DSI_CLTCR_HS2LP_TIME2 DSI_CLTCR_HS2LP_TIME2_Msk
10984 #define DSI_CLTCR_HS2LP_TIME3_Pos (19U)
10985 #define DSI_CLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME3_Pos) /*!< 0x00080000 */
10986 #define DSI_CLTCR_HS2LP_TIME3 DSI_CLTCR_HS2LP_TIME3_Msk
10987 #define DSI_CLTCR_HS2LP_TIME4_Pos (20U)
10988 #define DSI_CLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME4_Pos) /*!< 0x00100000 */
10989 #define DSI_CLTCR_HS2LP_TIME4 DSI_CLTCR_HS2LP_TIME4_Msk
10990 #define DSI_CLTCR_HS2LP_TIME5_Pos (21U)
10991 #define DSI_CLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME5_Pos) /*!< 0x00200000 */
10992 #define DSI_CLTCR_HS2LP_TIME5 DSI_CLTCR_HS2LP_TIME5_Msk
10993 #define DSI_CLTCR_HS2LP_TIME6_Pos (22U)
10994 #define DSI_CLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME6_Pos) /*!< 0x00400000 */
10995 #define DSI_CLTCR_HS2LP_TIME6 DSI_CLTCR_HS2LP_TIME6_Msk
10996 #define DSI_CLTCR_HS2LP_TIME7_Pos (23U)
10997 #define DSI_CLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME7_Pos) /*!< 0x00800000 */
10998 #define DSI_CLTCR_HS2LP_TIME7 DSI_CLTCR_HS2LP_TIME7_Msk
10999 #define DSI_CLTCR_HS2LP_TIME8_Pos (24U)
11000 #define DSI_CLTCR_HS2LP_TIME8_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME8_Pos) /*!< 0x01000000 */
11001 #define DSI_CLTCR_HS2LP_TIME8 DSI_CLTCR_HS2LP_TIME8_Msk
11002 #define DSI_CLTCR_HS2LP_TIME9_Pos (25U)
11003 #define DSI_CLTCR_HS2LP_TIME9_Msk (0x1UL << DSI_CLTCR_HS2LP_TIME9_Pos) /*!< 0x02000000 */
11004 #define DSI_CLTCR_HS2LP_TIME9 DSI_CLTCR_HS2LP_TIME9_Msk
11005
11006 /******************* Bit definition for DSI_DLTCR register **************/
11007 #define DSI_DLTCR_MRD_TIME_Pos (0U)
11008 #define DSI_DLTCR_MRD_TIME_Msk (0x7FFFUL << DSI_DLTCR_MRD_TIME_Pos) /*!< 0x00007FFF */
11009 #define DSI_DLTCR_MRD_TIME DSI_DLTCR_MRD_TIME_Msk /*!< Maximum Read Time */
11010 #define DSI_DLTCR_MRD_TIME0_Pos (0U)
11011 #define DSI_DLTCR_MRD_TIME0_Msk (0x1UL << DSI_DLTCR_MRD_TIME0_Pos) /*!< 0x00000001 */
11012 #define DSI_DLTCR_MRD_TIME0 DSI_DLTCR_MRD_TIME0_Msk
11013 #define DSI_DLTCR_MRD_TIME1_Pos (1U)
11014 #define DSI_DLTCR_MRD_TIME1_Msk (0x1UL << DSI_DLTCR_MRD_TIME1_Pos) /*!< 0x00000002 */
11015 #define DSI_DLTCR_MRD_TIME1 DSI_DLTCR_MRD_TIME1_Msk
11016 #define DSI_DLTCR_MRD_TIME2_Pos (2U)
11017 #define DSI_DLTCR_MRD_TIME2_Msk (0x1UL << DSI_DLTCR_MRD_TIME2_Pos) /*!< 0x00000004 */
11018 #define DSI_DLTCR_MRD_TIME2 DSI_DLTCR_MRD_TIME2_Msk
11019 #define DSI_DLTCR_MRD_TIME3_Pos (3U)
11020 #define DSI_DLTCR_MRD_TIME3_Msk (0x1UL << DSI_DLTCR_MRD_TIME3_Pos) /*!< 0x00000008 */
11021 #define DSI_DLTCR_MRD_TIME3 DSI_DLTCR_MRD_TIME3_Msk
11022 #define DSI_DLTCR_MRD_TIME4_Pos (4U)
11023 #define DSI_DLTCR_MRD_TIME4_Msk (0x1UL << DSI_DLTCR_MRD_TIME4_Pos) /*!< 0x00000010 */
11024 #define DSI_DLTCR_MRD_TIME4 DSI_DLTCR_MRD_TIME4_Msk
11025 #define DSI_DLTCR_MRD_TIME5_Pos (5U)
11026 #define DSI_DLTCR_MRD_TIME5_Msk (0x1UL << DSI_DLTCR_MRD_TIME5_Pos) /*!< 0x00000020 */
11027 #define DSI_DLTCR_MRD_TIME5 DSI_DLTCR_MRD_TIME5_Msk
11028 #define DSI_DLTCR_MRD_TIME6_Pos (6U)
11029 #define DSI_DLTCR_MRD_TIME6_Msk (0x1UL << DSI_DLTCR_MRD_TIME6_Pos) /*!< 0x00000040 */
11030 #define DSI_DLTCR_MRD_TIME6 DSI_DLTCR_MRD_TIME6_Msk
11031 #define DSI_DLTCR_MRD_TIME7_Pos (7U)
11032 #define DSI_DLTCR_MRD_TIME7_Msk (0x1UL << DSI_DLTCR_MRD_TIME7_Pos) /*!< 0x00000080 */
11033 #define DSI_DLTCR_MRD_TIME7 DSI_DLTCR_MRD_TIME7_Msk
11034 #define DSI_DLTCR_MRD_TIME8_Pos (8U)
11035 #define DSI_DLTCR_MRD_TIME8_Msk (0x1UL << DSI_DLTCR_MRD_TIME8_Pos) /*!< 0x00000100 */
11036 #define DSI_DLTCR_MRD_TIME8 DSI_DLTCR_MRD_TIME8_Msk
11037 #define DSI_DLTCR_MRD_TIME9_Pos (9U)
11038 #define DSI_DLTCR_MRD_TIME9_Msk (0x1UL << DSI_DLTCR_MRD_TIME9_Pos) /*!< 0x00000200 */
11039 #define DSI_DLTCR_MRD_TIME9 DSI_DLTCR_MRD_TIME9_Msk
11040 #define DSI_DLTCR_MRD_TIME10_Pos (10U)
11041 #define DSI_DLTCR_MRD_TIME10_Msk (0x1UL << DSI_DLTCR_MRD_TIME10_Pos) /*!< 0x00000400 */
11042 #define DSI_DLTCR_MRD_TIME10 DSI_DLTCR_MRD_TIME10_Msk
11043 #define DSI_DLTCR_MRD_TIME11_Pos (11U)
11044 #define DSI_DLTCR_MRD_TIME11_Msk (0x1UL << DSI_DLTCR_MRD_TIME11_Pos) /*!< 0x00000800 */
11045 #define DSI_DLTCR_MRD_TIME11 DSI_DLTCR_MRD_TIME11_Msk
11046 #define DSI_DLTCR_MRD_TIME12_Pos (12U)
11047 #define DSI_DLTCR_MRD_TIME12_Msk (0x1UL << DSI_DLTCR_MRD_TIME12_Pos) /*!< 0x00001000 */
11048 #define DSI_DLTCR_MRD_TIME12 DSI_DLTCR_MRD_TIME12_Msk
11049 #define DSI_DLTCR_MRD_TIME13_Pos (13U)
11050 #define DSI_DLTCR_MRD_TIME13_Msk (0x1UL << DSI_DLTCR_MRD_TIME13_Pos) /*!< 0x00002000 */
11051 #define DSI_DLTCR_MRD_TIME13 DSI_DLTCR_MRD_TIME13_Msk
11052 #define DSI_DLTCR_MRD_TIME14_Pos (14U)
11053 #define DSI_DLTCR_MRD_TIME14_Msk (0x1UL << DSI_DLTCR_MRD_TIME14_Pos) /*!< 0x00004000 */
11054 #define DSI_DLTCR_MRD_TIME14 DSI_DLTCR_MRD_TIME14_Msk
11055
11056 #define DSI_DLTCR_LP2HS_TIME_Pos (16U)
11057 #define DSI_DLTCR_LP2HS_TIME_Msk (0xFFUL << DSI_DLTCR_LP2HS_TIME_Pos) /*!< 0x00FF0000 */
11058 #define DSI_DLTCR_LP2HS_TIME DSI_DLTCR_LP2HS_TIME_Msk /*!< Low-Power To High-Speed Time */
11059 #define DSI_DLTCR_LP2HS_TIME0_Pos (16U)
11060 #define DSI_DLTCR_LP2HS_TIME0_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME0_Pos) /*!< 0x00010000 */
11061 #define DSI_DLTCR_LP2HS_TIME0 DSI_DLTCR_LP2HS_TIME0_Msk
11062 #define DSI_DLTCR_LP2HS_TIME1_Pos (17U)
11063 #define DSI_DLTCR_LP2HS_TIME1_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME1_Pos) /*!< 0x00020000 */
11064 #define DSI_DLTCR_LP2HS_TIME1 DSI_DLTCR_LP2HS_TIME1_Msk
11065 #define DSI_DLTCR_LP2HS_TIME2_Pos (18U)
11066 #define DSI_DLTCR_LP2HS_TIME2_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME2_Pos) /*!< 0x00040000 */
11067 #define DSI_DLTCR_LP2HS_TIME2 DSI_DLTCR_LP2HS_TIME2_Msk
11068 #define DSI_DLTCR_LP2HS_TIME3_Pos (19U)
11069 #define DSI_DLTCR_LP2HS_TIME3_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME3_Pos) /*!< 0x00080000 */
11070 #define DSI_DLTCR_LP2HS_TIME3 DSI_DLTCR_LP2HS_TIME3_Msk
11071 #define DSI_DLTCR_LP2HS_TIME4_Pos (20U)
11072 #define DSI_DLTCR_LP2HS_TIME4_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME4_Pos) /*!< 0x00100000 */
11073 #define DSI_DLTCR_LP2HS_TIME4 DSI_DLTCR_LP2HS_TIME4_Msk
11074 #define DSI_DLTCR_LP2HS_TIME5_Pos (21U)
11075 #define DSI_DLTCR_LP2HS_TIME5_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME5_Pos) /*!< 0x00200000 */
11076 #define DSI_DLTCR_LP2HS_TIME5 DSI_DLTCR_LP2HS_TIME5_Msk
11077 #define DSI_DLTCR_LP2HS_TIME6_Pos (22U)
11078 #define DSI_DLTCR_LP2HS_TIME6_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME6_Pos) /*!< 0x00400000 */
11079 #define DSI_DLTCR_LP2HS_TIME6 DSI_DLTCR_LP2HS_TIME6_Msk
11080 #define DSI_DLTCR_LP2HS_TIME7_Pos (23U)
11081 #define DSI_DLTCR_LP2HS_TIME7_Msk (0x1UL << DSI_DLTCR_LP2HS_TIME7_Pos) /*!< 0x00800000 */
11082 #define DSI_DLTCR_LP2HS_TIME7 DSI_DLTCR_LP2HS_TIME7_Msk
11083
11084 #define DSI_DLTCR_HS2LP_TIME_Pos (24U)
11085 #define DSI_DLTCR_HS2LP_TIME_Msk (0xFFUL << DSI_DLTCR_HS2LP_TIME_Pos) /*!< 0xFF000000 */
11086 #define DSI_DLTCR_HS2LP_TIME DSI_DLTCR_HS2LP_TIME_Msk /*!< High-Speed To Low-Power Time */
11087 #define DSI_DLTCR_HS2LP_TIME0_Pos (24U)
11088 #define DSI_DLTCR_HS2LP_TIME0_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME0_Pos) /*!< 0x01000000 */
11089 #define DSI_DLTCR_HS2LP_TIME0 DSI_DLTCR_HS2LP_TIME0_Msk
11090 #define DSI_DLTCR_HS2LP_TIME1_Pos (25U)
11091 #define DSI_DLTCR_HS2LP_TIME1_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME1_Pos) /*!< 0x02000000 */
11092 #define DSI_DLTCR_HS2LP_TIME1 DSI_DLTCR_HS2LP_TIME1_Msk
11093 #define DSI_DLTCR_HS2LP_TIME2_Pos (26U)
11094 #define DSI_DLTCR_HS2LP_TIME2_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME2_Pos) /*!< 0x04000000 */
11095 #define DSI_DLTCR_HS2LP_TIME2 DSI_DLTCR_HS2LP_TIME2_Msk
11096 #define DSI_DLTCR_HS2LP_TIME3_Pos (27U)
11097 #define DSI_DLTCR_HS2LP_TIME3_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME3_Pos) /*!< 0x08000000 */
11098 #define DSI_DLTCR_HS2LP_TIME3 DSI_DLTCR_HS2LP_TIME3_Msk
11099 #define DSI_DLTCR_HS2LP_TIME4_Pos (28U)
11100 #define DSI_DLTCR_HS2LP_TIME4_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME4_Pos) /*!< 0x10000000 */
11101 #define DSI_DLTCR_HS2LP_TIME4 DSI_DLTCR_HS2LP_TIME4_Msk
11102 #define DSI_DLTCR_HS2LP_TIME5_Pos (29U)
11103 #define DSI_DLTCR_HS2LP_TIME5_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME5_Pos) /*!< 0x20000000 */
11104 #define DSI_DLTCR_HS2LP_TIME5 DSI_DLTCR_HS2LP_TIME5_Msk
11105 #define DSI_DLTCR_HS2LP_TIME6_Pos (30U)
11106 #define DSI_DLTCR_HS2LP_TIME6_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME6_Pos) /*!< 0x40000000 */
11107 #define DSI_DLTCR_HS2LP_TIME6 DSI_DLTCR_HS2LP_TIME6_Msk
11108 #define DSI_DLTCR_HS2LP_TIME7_Pos (31U)
11109 #define DSI_DLTCR_HS2LP_TIME7_Msk (0x1UL << DSI_DLTCR_HS2LP_TIME7_Pos) /*!< 0x80000000 */
11110 #define DSI_DLTCR_HS2LP_TIME7 DSI_DLTCR_HS2LP_TIME7_Msk
11111
11112 /******************* Bit definition for DSI_PCTLR register **************/
11113 #define DSI_PCTLR_DEN_Pos (1U)
11114 #define DSI_PCTLR_DEN_Msk (0x1UL << DSI_PCTLR_DEN_Pos) /*!< 0x00000002 */
11115 #define DSI_PCTLR_DEN DSI_PCTLR_DEN_Msk /*!< Digital Enable */
11116 #define DSI_PCTLR_CKE_Pos (2U)
11117 #define DSI_PCTLR_CKE_Msk (0x1UL << DSI_PCTLR_CKE_Pos) /*!< 0x00000004 */
11118 #define DSI_PCTLR_CKE DSI_PCTLR_CKE_Msk /*!< Clock Enable */
11119
11120 /******************* Bit definition for DSI_PCONFR register *************/
11121 #define DSI_PCONFR_NL_Pos (0U)
11122 #define DSI_PCONFR_NL_Msk (0x3UL << DSI_PCONFR_NL_Pos) /*!< 0x00000003 */
11123 #define DSI_PCONFR_NL DSI_PCONFR_NL_Msk /*!< Number of Lanes */
11124 #define DSI_PCONFR_NL0_Pos (0U)
11125 #define DSI_PCONFR_NL0_Msk (0x1UL << DSI_PCONFR_NL0_Pos) /*!< 0x00000001 */
11126 #define DSI_PCONFR_NL0 DSI_PCONFR_NL0_Msk
11127 #define DSI_PCONFR_NL1_Pos (1U)
11128 #define DSI_PCONFR_NL1_Msk (0x1UL << DSI_PCONFR_NL1_Pos) /*!< 0x00000002 */
11129 #define DSI_PCONFR_NL1 DSI_PCONFR_NL1_Msk
11130
11131 #define DSI_PCONFR_SW_TIME_Pos (8U)
11132 #define DSI_PCONFR_SW_TIME_Msk (0xFFUL << DSI_PCONFR_SW_TIME_Pos) /*!< 0x0000FF00 */
11133 #define DSI_PCONFR_SW_TIME DSI_PCONFR_SW_TIME_Msk /*!< Stop Wait Time */
11134 #define DSI_PCONFR_SW_TIME0_Pos (8U)
11135 #define DSI_PCONFR_SW_TIME0_Msk (0x1UL << DSI_PCONFR_SW_TIME0_Pos) /*!< 0x00000100 */
11136 #define DSI_PCONFR_SW_TIME0 DSI_PCONFR_SW_TIME0_Msk
11137 #define DSI_PCONFR_SW_TIME1_Pos (9U)
11138 #define DSI_PCONFR_SW_TIME1_Msk (0x1UL << DSI_PCONFR_SW_TIME1_Pos) /*!< 0x00000200 */
11139 #define DSI_PCONFR_SW_TIME1 DSI_PCONFR_SW_TIME1_Msk
11140 #define DSI_PCONFR_SW_TIME2_Pos (10U)
11141 #define DSI_PCONFR_SW_TIME2_Msk (0x1UL << DSI_PCONFR_SW_TIME2_Pos) /*!< 0x00000400 */
11142 #define DSI_PCONFR_SW_TIME2 DSI_PCONFR_SW_TIME2_Msk
11143 #define DSI_PCONFR_SW_TIME3_Pos (11U)
11144 #define DSI_PCONFR_SW_TIME3_Msk (0x1UL << DSI_PCONFR_SW_TIME3_Pos) /*!< 0x00000800 */
11145 #define DSI_PCONFR_SW_TIME3 DSI_PCONFR_SW_TIME3_Msk
11146 #define DSI_PCONFR_SW_TIME4_Pos (12U)
11147 #define DSI_PCONFR_SW_TIME4_Msk (0x1UL << DSI_PCONFR_SW_TIME4_Pos) /*!< 0x00001000 */
11148 #define DSI_PCONFR_SW_TIME4 DSI_PCONFR_SW_TIME4_Msk
11149 #define DSI_PCONFR_SW_TIME5_Pos (13U)
11150 #define DSI_PCONFR_SW_TIME5_Msk (0x1UL << DSI_PCONFR_SW_TIME5_Pos) /*!< 0x00002000 */
11151 #define DSI_PCONFR_SW_TIME5 DSI_PCONFR_SW_TIME5_Msk
11152 #define DSI_PCONFR_SW_TIME6_Pos (14U)
11153 #define DSI_PCONFR_SW_TIME6_Msk (0x1UL << DSI_PCONFR_SW_TIME6_Pos) /*!< 0x00004000 */
11154 #define DSI_PCONFR_SW_TIME6 DSI_PCONFR_SW_TIME6_Msk
11155 #define DSI_PCONFR_SW_TIME7_Pos (15U)
11156 #define DSI_PCONFR_SW_TIME7_Msk (0x1UL << DSI_PCONFR_SW_TIME7_Pos) /*!< 0x00008000 */
11157 #define DSI_PCONFR_SW_TIME7 DSI_PCONFR_SW_TIME7_Msk
11158
11159 /******************* Bit definition for DSI_PUCR register ***************/
11160 #define DSI_PUCR_URCL_Pos (0U)
11161 #define DSI_PUCR_URCL_Msk (0x1UL << DSI_PUCR_URCL_Pos) /*!< 0x00000001 */
11162 #define DSI_PUCR_URCL DSI_PUCR_URCL_Msk /*!< ULPS Request on Clock Lane */
11163 #define DSI_PUCR_UECL_Pos (1U)
11164 #define DSI_PUCR_UECL_Msk (0x1UL << DSI_PUCR_UECL_Pos) /*!< 0x00000002 */
11165 #define DSI_PUCR_UECL DSI_PUCR_UECL_Msk /*!< ULPS Exit on Clock Lane */
11166 #define DSI_PUCR_URDL_Pos (2U)
11167 #define DSI_PUCR_URDL_Msk (0x1UL << DSI_PUCR_URDL_Pos) /*!< 0x00000004 */
11168 #define DSI_PUCR_URDL DSI_PUCR_URDL_Msk /*!< ULPS Request on Data Lane */
11169 #define DSI_PUCR_UEDL_Pos (3U)
11170 #define DSI_PUCR_UEDL_Msk (0x1UL << DSI_PUCR_UEDL_Pos) /*!< 0x00000008 */
11171 #define DSI_PUCR_UEDL DSI_PUCR_UEDL_Msk /*!< ULPS Exit on Data Lane */
11172
11173 /******************* Bit definition for DSI_PTTCR register **************/
11174 #define DSI_PTTCR_TX_TRIG_Pos (0U)
11175 #define DSI_PTTCR_TX_TRIG_Msk (0xFUL << DSI_PTTCR_TX_TRIG_Pos) /*!< 0x0000000F */
11176 #define DSI_PTTCR_TX_TRIG DSI_PTTCR_TX_TRIG_Msk /*!< Transmission Trigger */
11177 #define DSI_PTTCR_TX_TRIG0_Pos (0U)
11178 #define DSI_PTTCR_TX_TRIG0_Msk (0x1UL << DSI_PTTCR_TX_TRIG0_Pos) /*!< 0x00000001 */
11179 #define DSI_PTTCR_TX_TRIG0 DSI_PTTCR_TX_TRIG0_Msk
11180 #define DSI_PTTCR_TX_TRIG1_Pos (1U)
11181 #define DSI_PTTCR_TX_TRIG1_Msk (0x1UL << DSI_PTTCR_TX_TRIG1_Pos) /*!< 0x00000002 */
11182 #define DSI_PTTCR_TX_TRIG1 DSI_PTTCR_TX_TRIG1_Msk
11183 #define DSI_PTTCR_TX_TRIG2_Pos (2U)
11184 #define DSI_PTTCR_TX_TRIG2_Msk (0x1UL << DSI_PTTCR_TX_TRIG2_Pos) /*!< 0x00000004 */
11185 #define DSI_PTTCR_TX_TRIG2 DSI_PTTCR_TX_TRIG2_Msk
11186 #define DSI_PTTCR_TX_TRIG3_Pos (3U)
11187 #define DSI_PTTCR_TX_TRIG3_Msk (0x1UL << DSI_PTTCR_TX_TRIG3_Pos) /*!< 0x00000008 */
11188 #define DSI_PTTCR_TX_TRIG3 DSI_PTTCR_TX_TRIG3_Msk
11189
11190 /******************* Bit definition for DSI_PSR register ****************/
11191 #define DSI_PSR_PD_Pos (1U)
11192 #define DSI_PSR_PD_Msk (0x1UL << DSI_PSR_PD_Pos) /*!< 0x00000002 */
11193 #define DSI_PSR_PD DSI_PSR_PD_Msk /*!< PHY Direction */
11194 #define DSI_PSR_PSSC_Pos (2U)
11195 #define DSI_PSR_PSSC_Msk (0x1UL << DSI_PSR_PSSC_Pos) /*!< 0x00000004 */
11196 #define DSI_PSR_PSSC DSI_PSR_PSSC_Msk /*!< PHY Stop State Clock lane */
11197 #define DSI_PSR_UANC_Pos (3U)
11198 #define DSI_PSR_UANC_Msk (0x1UL << DSI_PSR_UANC_Pos) /*!< 0x00000008 */
11199 #define DSI_PSR_UANC DSI_PSR_UANC_Msk /*!< ULPS Active Not Clock lane */
11200 #define DSI_PSR_PSS0_Pos (4U)
11201 #define DSI_PSR_PSS0_Msk (0x1UL << DSI_PSR_PSS0_Pos) /*!< 0x00000010 */
11202 #define DSI_PSR_PSS0 DSI_PSR_PSS0_Msk /*!< PHY Stop State lane 0 */
11203 #define DSI_PSR_UAN0_Pos (5U)
11204 #define DSI_PSR_UAN0_Msk (0x1UL << DSI_PSR_UAN0_Pos) /*!< 0x00000020 */
11205 #define DSI_PSR_UAN0 DSI_PSR_UAN0_Msk /*!< ULPS Active Not lane 0 */
11206 #define DSI_PSR_RUE0_Pos (6U)
11207 #define DSI_PSR_RUE0_Msk (0x1UL << DSI_PSR_RUE0_Pos) /*!< 0x00000040 */
11208 #define DSI_PSR_RUE0 DSI_PSR_RUE0_Msk /*!< RX ULPS Escape lane 0 */
11209 #define DSI_PSR_PSS1_Pos (7U)
11210 #define DSI_PSR_PSS1_Msk (0x1UL << DSI_PSR_PSS1_Pos) /*!< 0x00000080 */
11211 #define DSI_PSR_PSS1 DSI_PSR_PSS1_Msk /*!< PHY Stop State lane 1 */
11212 #define DSI_PSR_UAN1_Pos (8U)
11213 #define DSI_PSR_UAN1_Msk (0x1UL << DSI_PSR_UAN1_Pos) /*!< 0x00000100 */
11214 #define DSI_PSR_UAN1 DSI_PSR_UAN1_Msk /*!< ULPS Active Not lane 1 */
11215
11216 /******************* Bit definition for DSI_ISR0 register ***************/
11217 #define DSI_ISR0_AE0_Pos (0U)
11218 #define DSI_ISR0_AE0_Msk (0x1UL << DSI_ISR0_AE0_Pos) /*!< 0x00000001 */
11219 #define DSI_ISR0_AE0 DSI_ISR0_AE0_Msk /*!< Acknowledge Error 0 */
11220 #define DSI_ISR0_AE1_Pos (1U)
11221 #define DSI_ISR0_AE1_Msk (0x1UL << DSI_ISR0_AE1_Pos) /*!< 0x00000002 */
11222 #define DSI_ISR0_AE1 DSI_ISR0_AE1_Msk /*!< Acknowledge Error 1 */
11223 #define DSI_ISR0_AE2_Pos (2U)
11224 #define DSI_ISR0_AE2_Msk (0x1UL << DSI_ISR0_AE2_Pos) /*!< 0x00000004 */
11225 #define DSI_ISR0_AE2 DSI_ISR0_AE2_Msk /*!< Acknowledge Error 2 */
11226 #define DSI_ISR0_AE3_Pos (3U)
11227 #define DSI_ISR0_AE3_Msk (0x1UL << DSI_ISR0_AE3_Pos) /*!< 0x00000008 */
11228 #define DSI_ISR0_AE3 DSI_ISR0_AE3_Msk /*!< Acknowledge Error 3 */
11229 #define DSI_ISR0_AE4_Pos (4U)
11230 #define DSI_ISR0_AE4_Msk (0x1UL << DSI_ISR0_AE4_Pos) /*!< 0x00000010 */
11231 #define DSI_ISR0_AE4 DSI_ISR0_AE4_Msk /*!< Acknowledge Error 4 */
11232 #define DSI_ISR0_AE5_Pos (5U)
11233 #define DSI_ISR0_AE5_Msk (0x1UL << DSI_ISR0_AE5_Pos) /*!< 0x00000020 */
11234 #define DSI_ISR0_AE5 DSI_ISR0_AE5_Msk /*!< Acknowledge Error 5 */
11235 #define DSI_ISR0_AE6_Pos (6U)
11236 #define DSI_ISR0_AE6_Msk (0x1UL << DSI_ISR0_AE6_Pos) /*!< 0x00000040 */
11237 #define DSI_ISR0_AE6 DSI_ISR0_AE6_Msk /*!< Acknowledge Error 6 */
11238 #define DSI_ISR0_AE7_Pos (7U)
11239 #define DSI_ISR0_AE7_Msk (0x1UL << DSI_ISR0_AE7_Pos) /*!< 0x00000080 */
11240 #define DSI_ISR0_AE7 DSI_ISR0_AE7_Msk /*!< Acknowledge Error 7 */
11241 #define DSI_ISR0_AE8_Pos (8U)
11242 #define DSI_ISR0_AE8_Msk (0x1UL << DSI_ISR0_AE8_Pos) /*!< 0x00000100 */
11243 #define DSI_ISR0_AE8 DSI_ISR0_AE8_Msk /*!< Acknowledge Error 8 */
11244 #define DSI_ISR0_AE9_Pos (9U)
11245 #define DSI_ISR0_AE9_Msk (0x1UL << DSI_ISR0_AE9_Pos) /*!< 0x00000200 */
11246 #define DSI_ISR0_AE9 DSI_ISR0_AE9_Msk /*!< Acknowledge Error 9 */
11247 #define DSI_ISR0_AE10_Pos (10U)
11248 #define DSI_ISR0_AE10_Msk (0x1UL << DSI_ISR0_AE10_Pos) /*!< 0x00000400 */
11249 #define DSI_ISR0_AE10 DSI_ISR0_AE10_Msk /*!< Acknowledge Error 10 */
11250 #define DSI_ISR0_AE11_Pos (11U)
11251 #define DSI_ISR0_AE11_Msk (0x1UL << DSI_ISR0_AE11_Pos) /*!< 0x00000800 */
11252 #define DSI_ISR0_AE11 DSI_ISR0_AE11_Msk /*!< Acknowledge Error 11 */
11253 #define DSI_ISR0_AE12_Pos (12U)
11254 #define DSI_ISR0_AE12_Msk (0x1UL << DSI_ISR0_AE12_Pos) /*!< 0x00001000 */
11255 #define DSI_ISR0_AE12 DSI_ISR0_AE12_Msk /*!< Acknowledge Error 12 */
11256 #define DSI_ISR0_AE13_Pos (13U)
11257 #define DSI_ISR0_AE13_Msk (0x1UL << DSI_ISR0_AE13_Pos) /*!< 0x00002000 */
11258 #define DSI_ISR0_AE13 DSI_ISR0_AE13_Msk /*!< Acknowledge Error 13 */
11259 #define DSI_ISR0_AE14_Pos (14U)
11260 #define DSI_ISR0_AE14_Msk (0x1UL << DSI_ISR0_AE14_Pos) /*!< 0x00004000 */
11261 #define DSI_ISR0_AE14 DSI_ISR0_AE14_Msk /*!< Acknowledge Error 14 */
11262 #define DSI_ISR0_AE15_Pos (15U)
11263 #define DSI_ISR0_AE15_Msk (0x1UL << DSI_ISR0_AE15_Pos) /*!< 0x00008000 */
11264 #define DSI_ISR0_AE15 DSI_ISR0_AE15_Msk /*!< Acknowledge Error 15 */
11265 #define DSI_ISR0_PE0_Pos (16U)
11266 #define DSI_ISR0_PE0_Msk (0x1UL << DSI_ISR0_PE0_Pos) /*!< 0x00010000 */
11267 #define DSI_ISR0_PE0 DSI_ISR0_PE0_Msk /*!< PHY Error 0 */
11268 #define DSI_ISR0_PE1_Pos (17U)
11269 #define DSI_ISR0_PE1_Msk (0x1UL << DSI_ISR0_PE1_Pos) /*!< 0x00020000 */
11270 #define DSI_ISR0_PE1 DSI_ISR0_PE1_Msk /*!< PHY Error 1 */
11271 #define DSI_ISR0_PE2_Pos (18U)
11272 #define DSI_ISR0_PE2_Msk (0x1UL << DSI_ISR0_PE2_Pos) /*!< 0x00040000 */
11273 #define DSI_ISR0_PE2 DSI_ISR0_PE2_Msk /*!< PHY Error 2 */
11274 #define DSI_ISR0_PE3_Pos (19U)
11275 #define DSI_ISR0_PE3_Msk (0x1UL << DSI_ISR0_PE3_Pos) /*!< 0x00080000 */
11276 #define DSI_ISR0_PE3 DSI_ISR0_PE3_Msk /*!< PHY Error 3 */
11277 #define DSI_ISR0_PE4_Pos (20U)
11278 #define DSI_ISR0_PE4_Msk (0x1UL << DSI_ISR0_PE4_Pos) /*!< 0x00100000 */
11279 #define DSI_ISR0_PE4 DSI_ISR0_PE4_Msk /*!< PHY Error 4 */
11280
11281 /******************* Bit definition for DSI_ISR1 register ***************/
11282 #define DSI_ISR1_TOHSTX_Pos (0U)
11283 #define DSI_ISR1_TOHSTX_Msk (0x1UL << DSI_ISR1_TOHSTX_Pos) /*!< 0x00000001 */
11284 #define DSI_ISR1_TOHSTX DSI_ISR1_TOHSTX_Msk /*!< Timeout High-Speed Transmission */
11285 #define DSI_ISR1_TOLPRX_Pos (1U)
11286 #define DSI_ISR1_TOLPRX_Msk (0x1UL << DSI_ISR1_TOLPRX_Pos) /*!< 0x00000002 */
11287 #define DSI_ISR1_TOLPRX DSI_ISR1_TOLPRX_Msk /*!< Timeout Low-Power Reception */
11288 #define DSI_ISR1_ECCSE_Pos (2U)
11289 #define DSI_ISR1_ECCSE_Msk (0x1UL << DSI_ISR1_ECCSE_Pos) /*!< 0x00000004 */
11290 #define DSI_ISR1_ECCSE DSI_ISR1_ECCSE_Msk /*!< ECC Single-bit Error */
11291 #define DSI_ISR1_ECCME_Pos (3U)
11292 #define DSI_ISR1_ECCME_Msk (0x1UL << DSI_ISR1_ECCME_Pos) /*!< 0x00000008 */
11293 #define DSI_ISR1_ECCME DSI_ISR1_ECCME_Msk /*!< ECC Multi-bit Error */
11294 #define DSI_ISR1_CRCE_Pos (4U)
11295 #define DSI_ISR1_CRCE_Msk (0x1UL << DSI_ISR1_CRCE_Pos) /*!< 0x00000010 */
11296 #define DSI_ISR1_CRCE DSI_ISR1_CRCE_Msk /*!< CRC Error */
11297 #define DSI_ISR1_PSE_Pos (5U)
11298 #define DSI_ISR1_PSE_Msk (0x1UL << DSI_ISR1_PSE_Pos) /*!< 0x00000020 */
11299 #define DSI_ISR1_PSE DSI_ISR1_PSE_Msk /*!< Packet Size Error */
11300 #define DSI_ISR1_EOTPE_Pos (6U)
11301 #define DSI_ISR1_EOTPE_Msk (0x1UL << DSI_ISR1_EOTPE_Pos) /*!< 0x00000040 */
11302 #define DSI_ISR1_EOTPE DSI_ISR1_EOTPE_Msk /*!< EoTp Error */
11303 #define DSI_ISR1_LPWRE_Pos (7U)
11304 #define DSI_ISR1_LPWRE_Msk (0x1UL << DSI_ISR1_LPWRE_Pos) /*!< 0x00000080 */
11305 #define DSI_ISR1_LPWRE DSI_ISR1_LPWRE_Msk /*!< LTDC Payload Write Error */
11306 #define DSI_ISR1_GCWRE_Pos (8U)
11307 #define DSI_ISR1_GCWRE_Msk (0x1UL << DSI_ISR1_GCWRE_Pos) /*!< 0x00000100 */
11308 #define DSI_ISR1_GCWRE DSI_ISR1_GCWRE_Msk /*!< Generic Command Write Error */
11309 #define DSI_ISR1_GPWRE_Pos (9U)
11310 #define DSI_ISR1_GPWRE_Msk (0x1UL << DSI_ISR1_GPWRE_Pos) /*!< 0x00000200 */
11311 #define DSI_ISR1_GPWRE DSI_ISR1_GPWRE_Msk /*!< Generic Payload Write Error */
11312 #define DSI_ISR1_GPTXE_Pos (10U)
11313 #define DSI_ISR1_GPTXE_Msk (0x1UL << DSI_ISR1_GPTXE_Pos) /*!< 0x00000400 */
11314 #define DSI_ISR1_GPTXE DSI_ISR1_GPTXE_Msk /*!< Generic Payload Transmit Error */
11315 #define DSI_ISR1_GPRDE_Pos (11U)
11316 #define DSI_ISR1_GPRDE_Msk (0x1UL << DSI_ISR1_GPRDE_Pos) /*!< 0x00000800 */
11317 #define DSI_ISR1_GPRDE DSI_ISR1_GPRDE_Msk /*!< Generic Payload Read Error */
11318 #define DSI_ISR1_GPRXE_Pos (12U)
11319 #define DSI_ISR1_GPRXE_Msk (0x1UL << DSI_ISR1_GPRXE_Pos) /*!< 0x00001000 */
11320 #define DSI_ISR1_GPRXE DSI_ISR1_GPRXE_Msk /*!< Generic Payload Receive Error */
11321
11322 /******************* Bit definition for DSI_IER0 register ***************/
11323 #define DSI_IER0_AE0IE_Pos (0U)
11324 #define DSI_IER0_AE0IE_Msk (0x1UL << DSI_IER0_AE0IE_Pos) /*!< 0x00000001 */
11325 #define DSI_IER0_AE0IE DSI_IER0_AE0IE_Msk /*!< Acknowledge Error 0 Interrupt Enable */
11326 #define DSI_IER0_AE1IE_Pos (1U)
11327 #define DSI_IER0_AE1IE_Msk (0x1UL << DSI_IER0_AE1IE_Pos) /*!< 0x00000002 */
11328 #define DSI_IER0_AE1IE DSI_IER0_AE1IE_Msk /*!< Acknowledge Error 1 Interrupt Enable */
11329 #define DSI_IER0_AE2IE_Pos (2U)
11330 #define DSI_IER0_AE2IE_Msk (0x1UL << DSI_IER0_AE2IE_Pos) /*!< 0x00000004 */
11331 #define DSI_IER0_AE2IE DSI_IER0_AE2IE_Msk /*!< Acknowledge Error 2 Interrupt Enable */
11332 #define DSI_IER0_AE3IE_Pos (3U)
11333 #define DSI_IER0_AE3IE_Msk (0x1UL << DSI_IER0_AE3IE_Pos) /*!< 0x00000008 */
11334 #define DSI_IER0_AE3IE DSI_IER0_AE3IE_Msk /*!< Acknowledge Error 3 Interrupt Enable */
11335 #define DSI_IER0_AE4IE_Pos (4U)
11336 #define DSI_IER0_AE4IE_Msk (0x1UL << DSI_IER0_AE4IE_Pos) /*!< 0x00000010 */
11337 #define DSI_IER0_AE4IE DSI_IER0_AE4IE_Msk /*!< Acknowledge Error 4 Interrupt Enable */
11338 #define DSI_IER0_AE5IE_Pos (5U)
11339 #define DSI_IER0_AE5IE_Msk (0x1UL << DSI_IER0_AE5IE_Pos) /*!< 0x00000020 */
11340 #define DSI_IER0_AE5IE DSI_IER0_AE5IE_Msk /*!< Acknowledge Error 5 Interrupt Enable */
11341 #define DSI_IER0_AE6IE_Pos (6U)
11342 #define DSI_IER0_AE6IE_Msk (0x1UL << DSI_IER0_AE6IE_Pos) /*!< 0x00000040 */
11343 #define DSI_IER0_AE6IE DSI_IER0_AE6IE_Msk /*!< Acknowledge Error 6 Interrupt Enable */
11344 #define DSI_IER0_AE7IE_Pos (7U)
11345 #define DSI_IER0_AE7IE_Msk (0x1UL << DSI_IER0_AE7IE_Pos) /*!< 0x00000080 */
11346 #define DSI_IER0_AE7IE DSI_IER0_AE7IE_Msk /*!< Acknowledge Error 7 Interrupt Enable */
11347 #define DSI_IER0_AE8IE_Pos (8U)
11348 #define DSI_IER0_AE8IE_Msk (0x1UL << DSI_IER0_AE8IE_Pos) /*!< 0x00000100 */
11349 #define DSI_IER0_AE8IE DSI_IER0_AE8IE_Msk /*!< Acknowledge Error 8 Interrupt Enable */
11350 #define DSI_IER0_AE9IE_Pos (9U)
11351 #define DSI_IER0_AE9IE_Msk (0x1UL << DSI_IER0_AE9IE_Pos) /*!< 0x00000200 */
11352 #define DSI_IER0_AE9IE DSI_IER0_AE9IE_Msk /*!< Acknowledge Error 9 Interrupt Enable */
11353 #define DSI_IER0_AE10IE_Pos (10U)
11354 #define DSI_IER0_AE10IE_Msk (0x1UL << DSI_IER0_AE10IE_Pos) /*!< 0x00000400 */
11355 #define DSI_IER0_AE10IE DSI_IER0_AE10IE_Msk /*!< Acknowledge Error 10 Interrupt Enable */
11356 #define DSI_IER0_AE11IE_Pos (11U)
11357 #define DSI_IER0_AE11IE_Msk (0x1UL << DSI_IER0_AE11IE_Pos) /*!< 0x00000800 */
11358 #define DSI_IER0_AE11IE DSI_IER0_AE11IE_Msk /*!< Acknowledge Error 11 Interrupt Enable */
11359 #define DSI_IER0_AE12IE_Pos (12U)
11360 #define DSI_IER0_AE12IE_Msk (0x1UL << DSI_IER0_AE12IE_Pos) /*!< 0x00001000 */
11361 #define DSI_IER0_AE12IE DSI_IER0_AE12IE_Msk /*!< Acknowledge Error 12 Interrupt Enable */
11362 #define DSI_IER0_AE13IE_Pos (13U)
11363 #define DSI_IER0_AE13IE_Msk (0x1UL << DSI_IER0_AE13IE_Pos) /*!< 0x00002000 */
11364 #define DSI_IER0_AE13IE DSI_IER0_AE13IE_Msk /*!< Acknowledge Error 13 Interrupt Enable */
11365 #define DSI_IER0_AE14IE_Pos (14U)
11366 #define DSI_IER0_AE14IE_Msk (0x1UL << DSI_IER0_AE14IE_Pos) /*!< 0x00004000 */
11367 #define DSI_IER0_AE14IE DSI_IER0_AE14IE_Msk /*!< Acknowledge Error 14 Interrupt Enable */
11368 #define DSI_IER0_AE15IE_Pos (15U)
11369 #define DSI_IER0_AE15IE_Msk (0x1UL << DSI_IER0_AE15IE_Pos) /*!< 0x00008000 */
11370 #define DSI_IER0_AE15IE DSI_IER0_AE15IE_Msk /*!< Acknowledge Error 15 Interrupt Enable */
11371 #define DSI_IER0_PE0IE_Pos (16U)
11372 #define DSI_IER0_PE0IE_Msk (0x1UL << DSI_IER0_PE0IE_Pos) /*!< 0x00010000 */
11373 #define DSI_IER0_PE0IE DSI_IER0_PE0IE_Msk /*!< PHY Error 0 Interrupt Enable */
11374 #define DSI_IER0_PE1IE_Pos (17U)
11375 #define DSI_IER0_PE1IE_Msk (0x1UL << DSI_IER0_PE1IE_Pos) /*!< 0x00020000 */
11376 #define DSI_IER0_PE1IE DSI_IER0_PE1IE_Msk /*!< PHY Error 1 Interrupt Enable */
11377 #define DSI_IER0_PE2IE_Pos (18U)
11378 #define DSI_IER0_PE2IE_Msk (0x1UL << DSI_IER0_PE2IE_Pos) /*!< 0x00040000 */
11379 #define DSI_IER0_PE2IE DSI_IER0_PE2IE_Msk /*!< PHY Error 2 Interrupt Enable */
11380 #define DSI_IER0_PE3IE_Pos (19U)
11381 #define DSI_IER0_PE3IE_Msk (0x1UL << DSI_IER0_PE3IE_Pos) /*!< 0x00080000 */
11382 #define DSI_IER0_PE3IE DSI_IER0_PE3IE_Msk /*!< PHY Error 3 Interrupt Enable */
11383 #define DSI_IER0_PE4IE_Pos (20U)
11384 #define DSI_IER0_PE4IE_Msk (0x1UL << DSI_IER0_PE4IE_Pos) /*!< 0x00100000 */
11385 #define DSI_IER0_PE4IE DSI_IER0_PE4IE_Msk /*!< PHY Error 4 Interrupt Enable */
11386
11387 /******************* Bit definition for DSI_IER1 register ***************/
11388 #define DSI_IER1_TOHSTXIE_Pos (0U)
11389 #define DSI_IER1_TOHSTXIE_Msk (0x1UL << DSI_IER1_TOHSTXIE_Pos) /*!< 0x00000001 */
11390 #define DSI_IER1_TOHSTXIE DSI_IER1_TOHSTXIE_Msk /*!< Timeout High-Speed Transmission Interrupt Enable */
11391 #define DSI_IER1_TOLPRXIE_Pos (1U)
11392 #define DSI_IER1_TOLPRXIE_Msk (0x1UL << DSI_IER1_TOLPRXIE_Pos) /*!< 0x00000002 */
11393 #define DSI_IER1_TOLPRXIE DSI_IER1_TOLPRXIE_Msk /*!< Timeout Low-Power Reception Interrupt Enable */
11394 #define DSI_IER1_ECCSEIE_Pos (2U)
11395 #define DSI_IER1_ECCSEIE_Msk (0x1UL << DSI_IER1_ECCSEIE_Pos) /*!< 0x00000004 */
11396 #define DSI_IER1_ECCSEIE DSI_IER1_ECCSEIE_Msk /*!< ECC Single-bit Error Interrupt Enable */
11397 #define DSI_IER1_ECCMEIE_Pos (3U)
11398 #define DSI_IER1_ECCMEIE_Msk (0x1UL << DSI_IER1_ECCMEIE_Pos) /*!< 0x00000008 */
11399 #define DSI_IER1_ECCMEIE DSI_IER1_ECCMEIE_Msk /*!< ECC Multi-bit Error Interrupt Enable */
11400 #define DSI_IER1_CRCEIE_Pos (4U)
11401 #define DSI_IER1_CRCEIE_Msk (0x1UL << DSI_IER1_CRCEIE_Pos) /*!< 0x00000010 */
11402 #define DSI_IER1_CRCEIE DSI_IER1_CRCEIE_Msk /*!< CRC Error Interrupt Enable */
11403 #define DSI_IER1_PSEIE_Pos (5U)
11404 #define DSI_IER1_PSEIE_Msk (0x1UL << DSI_IER1_PSEIE_Pos) /*!< 0x00000020 */
11405 #define DSI_IER1_PSEIE DSI_IER1_PSEIE_Msk /*!< Packet Size Error Interrupt Enable */
11406 #define DSI_IER1_EOTPEIE_Pos (6U)
11407 #define DSI_IER1_EOTPEIE_Msk (0x1UL << DSI_IER1_EOTPEIE_Pos) /*!< 0x00000040 */
11408 #define DSI_IER1_EOTPEIE DSI_IER1_EOTPEIE_Msk /*!< EoTp Error Interrupt Enable */
11409 #define DSI_IER1_LPWREIE_Pos (7U)
11410 #define DSI_IER1_LPWREIE_Msk (0x1UL << DSI_IER1_LPWREIE_Pos) /*!< 0x00000080 */
11411 #define DSI_IER1_LPWREIE DSI_IER1_LPWREIE_Msk /*!< LTDC Payload Write Error Interrupt Enable */
11412 #define DSI_IER1_GCWREIE_Pos (8U)
11413 #define DSI_IER1_GCWREIE_Msk (0x1UL << DSI_IER1_GCWREIE_Pos) /*!< 0x00000100 */
11414 #define DSI_IER1_GCWREIE DSI_IER1_GCWREIE_Msk /*!< Generic Command Write Error Interrupt Enable */
11415 #define DSI_IER1_GPWREIE_Pos (9U)
11416 #define DSI_IER1_GPWREIE_Msk (0x1UL << DSI_IER1_GPWREIE_Pos) /*!< 0x00000200 */
11417 #define DSI_IER1_GPWREIE DSI_IER1_GPWREIE_Msk /*!< Generic Payload Write Error Interrupt Enable */
11418 #define DSI_IER1_GPTXEIE_Pos (10U)
11419 #define DSI_IER1_GPTXEIE_Msk (0x1UL << DSI_IER1_GPTXEIE_Pos) /*!< 0x00000400 */
11420 #define DSI_IER1_GPTXEIE DSI_IER1_GPTXEIE_Msk /*!< Generic Payload Transmit Error Interrupt Enable */
11421 #define DSI_IER1_GPRDEIE_Pos (11U)
11422 #define DSI_IER1_GPRDEIE_Msk (0x1UL << DSI_IER1_GPRDEIE_Pos) /*!< 0x00000800 */
11423 #define DSI_IER1_GPRDEIE DSI_IER1_GPRDEIE_Msk /*!< Generic Payload Read Error Interrupt Enable */
11424 #define DSI_IER1_GPRXEIE_Pos (12U)
11425 #define DSI_IER1_GPRXEIE_Msk (0x1UL << DSI_IER1_GPRXEIE_Pos) /*!< 0x00001000 */
11426 #define DSI_IER1_GPRXEIE DSI_IER1_GPRXEIE_Msk /*!< Generic Payload Receive Error Interrupt Enable */
11427
11428 /******************* Bit definition for DSI_FIR0 register ***************/
11429 #define DSI_FIR0_FAE0_Pos (0U)
11430 #define DSI_FIR0_FAE0_Msk (0x1UL << DSI_FIR0_FAE0_Pos) /*!< 0x00000001 */
11431 #define DSI_FIR0_FAE0 DSI_FIR0_FAE0_Msk /*!< Force Acknowledge Error 0 */
11432 #define DSI_FIR0_FAE1_Pos (1U)
11433 #define DSI_FIR0_FAE1_Msk (0x1UL << DSI_FIR0_FAE1_Pos) /*!< 0x00000002 */
11434 #define DSI_FIR0_FAE1 DSI_FIR0_FAE1_Msk /*!< Force Acknowledge Error 1 */
11435 #define DSI_FIR0_FAE2_Pos (2U)
11436 #define DSI_FIR0_FAE2_Msk (0x1UL << DSI_FIR0_FAE2_Pos) /*!< 0x00000004 */
11437 #define DSI_FIR0_FAE2 DSI_FIR0_FAE2_Msk /*!< Force Acknowledge Error 2 */
11438 #define DSI_FIR0_FAE3_Pos (3U)
11439 #define DSI_FIR0_FAE3_Msk (0x1UL << DSI_FIR0_FAE3_Pos) /*!< 0x00000008 */
11440 #define DSI_FIR0_FAE3 DSI_FIR0_FAE3_Msk /*!< Force Acknowledge Error 3 */
11441 #define DSI_FIR0_FAE4_Pos (4U)
11442 #define DSI_FIR0_FAE4_Msk (0x1UL << DSI_FIR0_FAE4_Pos) /*!< 0x00000010 */
11443 #define DSI_FIR0_FAE4 DSI_FIR0_FAE4_Msk /*!< Force Acknowledge Error 4 */
11444 #define DSI_FIR0_FAE5_Pos (5U)
11445 #define DSI_FIR0_FAE5_Msk (0x1UL << DSI_FIR0_FAE5_Pos) /*!< 0x00000020 */
11446 #define DSI_FIR0_FAE5 DSI_FIR0_FAE5_Msk /*!< Force Acknowledge Error 5 */
11447 #define DSI_FIR0_FAE6_Pos (6U)
11448 #define DSI_FIR0_FAE6_Msk (0x1UL << DSI_FIR0_FAE6_Pos) /*!< 0x00000040 */
11449 #define DSI_FIR0_FAE6 DSI_FIR0_FAE6_Msk /*!< Force Acknowledge Error 6 */
11450 #define DSI_FIR0_FAE7_Pos (7U)
11451 #define DSI_FIR0_FAE7_Msk (0x1UL << DSI_FIR0_FAE7_Pos) /*!< 0x00000080 */
11452 #define DSI_FIR0_FAE7 DSI_FIR0_FAE7_Msk /*!< Force Acknowledge Error 7 */
11453 #define DSI_FIR0_FAE8_Pos (8U)
11454 #define DSI_FIR0_FAE8_Msk (0x1UL << DSI_FIR0_FAE8_Pos) /*!< 0x00000100 */
11455 #define DSI_FIR0_FAE8 DSI_FIR0_FAE8_Msk /*!< Force Acknowledge Error 8 */
11456 #define DSI_FIR0_FAE9_Pos (9U)
11457 #define DSI_FIR0_FAE9_Msk (0x1UL << DSI_FIR0_FAE9_Pos) /*!< 0x00000200 */
11458 #define DSI_FIR0_FAE9 DSI_FIR0_FAE9_Msk /*!< Force Acknowledge Error 9 */
11459 #define DSI_FIR0_FAE10_Pos (10U)
11460 #define DSI_FIR0_FAE10_Msk (0x1UL << DSI_FIR0_FAE10_Pos) /*!< 0x00000400 */
11461 #define DSI_FIR0_FAE10 DSI_FIR0_FAE10_Msk /*!< Force Acknowledge Error 10 */
11462 #define DSI_FIR0_FAE11_Pos (11U)
11463 #define DSI_FIR0_FAE11_Msk (0x1UL << DSI_FIR0_FAE11_Pos) /*!< 0x00000800 */
11464 #define DSI_FIR0_FAE11 DSI_FIR0_FAE11_Msk /*!< Force Acknowledge Error 11 */
11465 #define DSI_FIR0_FAE12_Pos (12U)
11466 #define DSI_FIR0_FAE12_Msk (0x1UL << DSI_FIR0_FAE12_Pos) /*!< 0x00001000 */
11467 #define DSI_FIR0_FAE12 DSI_FIR0_FAE12_Msk /*!< Force Acknowledge Error 12 */
11468 #define DSI_FIR0_FAE13_Pos (13U)
11469 #define DSI_FIR0_FAE13_Msk (0x1UL << DSI_FIR0_FAE13_Pos) /*!< 0x00002000 */
11470 #define DSI_FIR0_FAE13 DSI_FIR0_FAE13_Msk /*!< Force Acknowledge Error 13 */
11471 #define DSI_FIR0_FAE14_Pos (14U)
11472 #define DSI_FIR0_FAE14_Msk (0x1UL << DSI_FIR0_FAE14_Pos) /*!< 0x00004000 */
11473 #define DSI_FIR0_FAE14 DSI_FIR0_FAE14_Msk /*!< Force Acknowledge Error 14 */
11474 #define DSI_FIR0_FAE15_Pos (15U)
11475 #define DSI_FIR0_FAE15_Msk (0x1UL << DSI_FIR0_FAE15_Pos) /*!< 0x00008000 */
11476 #define DSI_FIR0_FAE15 DSI_FIR0_FAE15_Msk /*!< Force Acknowledge Error 15 */
11477 #define DSI_FIR0_FPE0_Pos (16U)
11478 #define DSI_FIR0_FPE0_Msk (0x1UL << DSI_FIR0_FPE0_Pos) /*!< 0x00010000 */
11479 #define DSI_FIR0_FPE0 DSI_FIR0_FPE0_Msk /*!< Force PHY Error 0 */
11480 #define DSI_FIR0_FPE1_Pos (17U)
11481 #define DSI_FIR0_FPE1_Msk (0x1UL << DSI_FIR0_FPE1_Pos) /*!< 0x00020000 */
11482 #define DSI_FIR0_FPE1 DSI_FIR0_FPE1_Msk /*!< Force PHY Error 1 */
11483 #define DSI_FIR0_FPE2_Pos (18U)
11484 #define DSI_FIR0_FPE2_Msk (0x1UL << DSI_FIR0_FPE2_Pos) /*!< 0x00040000 */
11485 #define DSI_FIR0_FPE2 DSI_FIR0_FPE2_Msk /*!< Force PHY Error 2 */
11486 #define DSI_FIR0_FPE3_Pos (19U)
11487 #define DSI_FIR0_FPE3_Msk (0x1UL << DSI_FIR0_FPE3_Pos) /*!< 0x00080000 */
11488 #define DSI_FIR0_FPE3 DSI_FIR0_FPE3_Msk /*!< Force PHY Error 3 */
11489 #define DSI_FIR0_FPE4_Pos (20U)
11490 #define DSI_FIR0_FPE4_Msk (0x1UL << DSI_FIR0_FPE4_Pos) /*!< 0x00100000 */
11491 #define DSI_FIR0_FPE4 DSI_FIR0_FPE4_Msk /*!< Force PHY Error 4 */
11492
11493 /******************* Bit definition for DSI_FIR1 register ***************/
11494 #define DSI_FIR1_FTOHSTX_Pos (0U)
11495 #define DSI_FIR1_FTOHSTX_Msk (0x1UL << DSI_FIR1_FTOHSTX_Pos) /*!< 0x00000001 */
11496 #define DSI_FIR1_FTOHSTX DSI_FIR1_FTOHSTX_Msk /*!< Force Timeout High-Speed Transmission */
11497 #define DSI_FIR1_FTOLPRX_Pos (1U)
11498 #define DSI_FIR1_FTOLPRX_Msk (0x1UL << DSI_FIR1_FTOLPRX_Pos) /*!< 0x00000002 */
11499 #define DSI_FIR1_FTOLPRX DSI_FIR1_FTOLPRX_Msk /*!< Force Timeout Low-Power Reception */
11500 #define DSI_FIR1_FECCSE_Pos (2U)
11501 #define DSI_FIR1_FECCSE_Msk (0x1UL << DSI_FIR1_FECCSE_Pos) /*!< 0x00000004 */
11502 #define DSI_FIR1_FECCSE DSI_FIR1_FECCSE_Msk /*!< Force ECC Single-bit Error */
11503 #define DSI_FIR1_FECCME_Pos (3U)
11504 #define DSI_FIR1_FECCME_Msk (0x1UL << DSI_FIR1_FECCME_Pos) /*!< 0x00000008 */
11505 #define DSI_FIR1_FECCME DSI_FIR1_FECCME_Msk /*!< Force ECC Multi-bit Error */
11506 #define DSI_FIR1_FCRCE_Pos (4U)
11507 #define DSI_FIR1_FCRCE_Msk (0x1UL << DSI_FIR1_FCRCE_Pos) /*!< 0x00000010 */
11508 #define DSI_FIR1_FCRCE DSI_FIR1_FCRCE_Msk /*!< Force CRC Error */
11509 #define DSI_FIR1_FPSE_Pos (5U)
11510 #define DSI_FIR1_FPSE_Msk (0x1UL << DSI_FIR1_FPSE_Pos) /*!< 0x00000020 */
11511 #define DSI_FIR1_FPSE DSI_FIR1_FPSE_Msk /*!< Force Packet Size Error */
11512 #define DSI_FIR1_FEOTPE_Pos (6U)
11513 #define DSI_FIR1_FEOTPE_Msk (0x1UL << DSI_FIR1_FEOTPE_Pos) /*!< 0x00000040 */
11514 #define DSI_FIR1_FEOTPE DSI_FIR1_FEOTPE_Msk /*!< Force EoTp Error */
11515 #define DSI_FIR1_FLPWRE_Pos (7U)
11516 #define DSI_FIR1_FLPWRE_Msk (0x1UL << DSI_FIR1_FLPWRE_Pos) /*!< 0x00000080 */
11517 #define DSI_FIR1_FLPWRE DSI_FIR1_FLPWRE_Msk /*!< Force LTDC Payload Write Error */
11518 #define DSI_FIR1_FGCWRE_Pos (8U)
11519 #define DSI_FIR1_FGCWRE_Msk (0x1UL << DSI_FIR1_FGCWRE_Pos) /*!< 0x00000100 */
11520 #define DSI_FIR1_FGCWRE DSI_FIR1_FGCWRE_Msk /*!< Force Generic Command Write Error */
11521 #define DSI_FIR1_FGPWRE_Pos (9U)
11522 #define DSI_FIR1_FGPWRE_Msk (0x1UL << DSI_FIR1_FGPWRE_Pos) /*!< 0x00000200 */
11523 #define DSI_FIR1_FGPWRE DSI_FIR1_FGPWRE_Msk /*!< Force Generic Payload Write Error */
11524 #define DSI_FIR1_FGPTXE_Pos (10U)
11525 #define DSI_FIR1_FGPTXE_Msk (0x1UL << DSI_FIR1_FGPTXE_Pos) /*!< 0x00000400 */
11526 #define DSI_FIR1_FGPTXE DSI_FIR1_FGPTXE_Msk /*!< Force Generic Payload Transmit Error */
11527 #define DSI_FIR1_FGPRDE_Pos (11U)
11528 #define DSI_FIR1_FGPRDE_Msk (0x1UL << DSI_FIR1_FGPRDE_Pos) /*!< 0x00000800 */
11529 #define DSI_FIR1_FGPRDE DSI_FIR1_FGPRDE_Msk /*!< Force Generic Payload Read Error */
11530 #define DSI_FIR1_FGPRXE_Pos (12U)
11531 #define DSI_FIR1_FGPRXE_Msk (0x1UL << DSI_FIR1_FGPRXE_Pos) /*!< 0x00001000 */
11532 #define DSI_FIR1_FGPRXE DSI_FIR1_FGPRXE_Msk /*!< Force Generic Payload Receive Error */
11533
11534 /******************* Bit definition for DSI_VSCR register ***************/
11535 #define DSI_VSCR_EN_Pos (0U)
11536 #define DSI_VSCR_EN_Msk (0x1UL << DSI_VSCR_EN_Pos) /*!< 0x00000001 */
11537 #define DSI_VSCR_EN DSI_VSCR_EN_Msk /*!< Enable */
11538 #define DSI_VSCR_UR_Pos (8U)
11539 #define DSI_VSCR_UR_Msk (0x1UL << DSI_VSCR_UR_Pos) /*!< 0x00000100 */
11540 #define DSI_VSCR_UR DSI_VSCR_UR_Msk /*!< Update Register */
11541
11542 /******************* Bit definition for DSI_LCVCIDR register ************/
11543 #define DSI_LCVCIDR_VCID_Pos (0U)
11544 #define DSI_LCVCIDR_VCID_Msk (0x3UL << DSI_LCVCIDR_VCID_Pos) /*!< 0x00000003 */
11545 #define DSI_LCVCIDR_VCID DSI_LCVCIDR_VCID_Msk /*!< Virtual Channel ID */
11546 #define DSI_LCVCIDR_VCID0_Pos (0U)
11547 #define DSI_LCVCIDR_VCID0_Msk (0x1UL << DSI_LCVCIDR_VCID0_Pos) /*!< 0x00000001 */
11548 #define DSI_LCVCIDR_VCID0 DSI_LCVCIDR_VCID0_Msk
11549 #define DSI_LCVCIDR_VCID1_Pos (1U)
11550 #define DSI_LCVCIDR_VCID1_Msk (0x1UL << DSI_LCVCIDR_VCID1_Pos) /*!< 0x00000002 */
11551 #define DSI_LCVCIDR_VCID1 DSI_LCVCIDR_VCID1_Msk
11552
11553 /******************* Bit definition for DSI_LCCCR register **************/
11554 #define DSI_LCCCR_COLC_Pos (0U)
11555 #define DSI_LCCCR_COLC_Msk (0xFUL << DSI_LCCCR_COLC_Pos) /*!< 0x0000000F */
11556 #define DSI_LCCCR_COLC DSI_LCCCR_COLC_Msk /*!< Color Coding */
11557 #define DSI_LCCCR_COLC0_Pos (0U)
11558 #define DSI_LCCCR_COLC0_Msk (0x1UL << DSI_LCCCR_COLC0_Pos) /*!< 0x00000001 */
11559 #define DSI_LCCCR_COLC0 DSI_LCCCR_COLC0_Msk
11560 #define DSI_LCCCR_COLC1_Pos (1U)
11561 #define DSI_LCCCR_COLC1_Msk (0x1UL << DSI_LCCCR_COLC1_Pos) /*!< 0x00000002 */
11562 #define DSI_LCCCR_COLC1 DSI_LCCCR_COLC1_Msk
11563 #define DSI_LCCCR_COLC2_Pos (2U)
11564 #define DSI_LCCCR_COLC2_Msk (0x1UL << DSI_LCCCR_COLC2_Pos) /*!< 0x00000004 */
11565 #define DSI_LCCCR_COLC2 DSI_LCCCR_COLC2_Msk
11566 #define DSI_LCCCR_COLC3_Pos (3U)
11567 #define DSI_LCCCR_COLC3_Msk (0x1UL << DSI_LCCCR_COLC3_Pos) /*!< 0x00000008 */
11568 #define DSI_LCCCR_COLC3 DSI_LCCCR_COLC3_Msk
11569
11570 #define DSI_LCCCR_LPE_Pos (8U)
11571 #define DSI_LCCCR_LPE_Msk (0x1UL << DSI_LCCCR_LPE_Pos) /*!< 0x00000100 */
11572 #define DSI_LCCCR_LPE DSI_LCCCR_LPE_Msk /*!< Loosely Packed Enable */
11573
11574 /******************* Bit definition for DSI_LPMCCR register *************/
11575 #define DSI_LPMCCR_VLPSIZE_Pos (0U)
11576 #define DSI_LPMCCR_VLPSIZE_Msk (0xFFUL << DSI_LPMCCR_VLPSIZE_Pos) /*!< 0x000000FF */
11577 #define DSI_LPMCCR_VLPSIZE DSI_LPMCCR_VLPSIZE_Msk /*!< VACT Largest Packet Size */
11578 #define DSI_LPMCCR_VLPSIZE0_Pos (0U)
11579 #define DSI_LPMCCR_VLPSIZE0_Msk (0x1UL << DSI_LPMCCR_VLPSIZE0_Pos) /*!< 0x00000001 */
11580 #define DSI_LPMCCR_VLPSIZE0 DSI_LPMCCR_VLPSIZE0_Msk
11581 #define DSI_LPMCCR_VLPSIZE1_Pos (1U)
11582 #define DSI_LPMCCR_VLPSIZE1_Msk (0x1UL << DSI_LPMCCR_VLPSIZE1_Pos) /*!< 0x00000002 */
11583 #define DSI_LPMCCR_VLPSIZE1 DSI_LPMCCR_VLPSIZE1_Msk
11584 #define DSI_LPMCCR_VLPSIZE2_Pos (2U)
11585 #define DSI_LPMCCR_VLPSIZE2_Msk (0x1UL << DSI_LPMCCR_VLPSIZE2_Pos) /*!< 0x00000004 */
11586 #define DSI_LPMCCR_VLPSIZE2 DSI_LPMCCR_VLPSIZE2_Msk
11587 #define DSI_LPMCCR_VLPSIZE3_Pos (3U)
11588 #define DSI_LPMCCR_VLPSIZE3_Msk (0x1UL << DSI_LPMCCR_VLPSIZE3_Pos) /*!< 0x00000008 */
11589 #define DSI_LPMCCR_VLPSIZE3 DSI_LPMCCR_VLPSIZE3_Msk
11590 #define DSI_LPMCCR_VLPSIZE4_Pos (4U)
11591 #define DSI_LPMCCR_VLPSIZE4_Msk (0x1UL << DSI_LPMCCR_VLPSIZE4_Pos) /*!< 0x00000010 */
11592 #define DSI_LPMCCR_VLPSIZE4 DSI_LPMCCR_VLPSIZE4_Msk
11593 #define DSI_LPMCCR_VLPSIZE5_Pos (5U)
11594 #define DSI_LPMCCR_VLPSIZE5_Msk (0x1UL << DSI_LPMCCR_VLPSIZE5_Pos) /*!< 0x00000020 */
11595 #define DSI_LPMCCR_VLPSIZE5 DSI_LPMCCR_VLPSIZE5_Msk
11596 #define DSI_LPMCCR_VLPSIZE6_Pos (6U)
11597 #define DSI_LPMCCR_VLPSIZE6_Msk (0x1UL << DSI_LPMCCR_VLPSIZE6_Pos) /*!< 0x00000040 */
11598 #define DSI_LPMCCR_VLPSIZE6 DSI_LPMCCR_VLPSIZE6_Msk
11599 #define DSI_LPMCCR_VLPSIZE7_Pos (7U)
11600 #define DSI_LPMCCR_VLPSIZE7_Msk (0x1UL << DSI_LPMCCR_VLPSIZE7_Pos) /*!< 0x00000080 */
11601 #define DSI_LPMCCR_VLPSIZE7 DSI_LPMCCR_VLPSIZE7_Msk
11602
11603 #define DSI_LPMCCR_LPSIZE_Pos (16U)
11604 #define DSI_LPMCCR_LPSIZE_Msk (0xFFUL << DSI_LPMCCR_LPSIZE_Pos) /*!< 0x00FF0000 */
11605 #define DSI_LPMCCR_LPSIZE DSI_LPMCCR_LPSIZE_Msk /*!< Largest Packet Size */
11606 #define DSI_LPMCCR_LPSIZE0_Pos (16U)
11607 #define DSI_LPMCCR_LPSIZE0_Msk (0x1UL << DSI_LPMCCR_LPSIZE0_Pos) /*!< 0x00010000 */
11608 #define DSI_LPMCCR_LPSIZE0 DSI_LPMCCR_LPSIZE0_Msk
11609 #define DSI_LPMCCR_LPSIZE1_Pos (17U)
11610 #define DSI_LPMCCR_LPSIZE1_Msk (0x1UL << DSI_LPMCCR_LPSIZE1_Pos) /*!< 0x00020000 */
11611 #define DSI_LPMCCR_LPSIZE1 DSI_LPMCCR_LPSIZE1_Msk
11612 #define DSI_LPMCCR_LPSIZE2_Pos (18U)
11613 #define DSI_LPMCCR_LPSIZE2_Msk (0x1UL << DSI_LPMCCR_LPSIZE2_Pos) /*!< 0x00040000 */
11614 #define DSI_LPMCCR_LPSIZE2 DSI_LPMCCR_LPSIZE2_Msk
11615 #define DSI_LPMCCR_LPSIZE3_Pos (19U)
11616 #define DSI_LPMCCR_LPSIZE3_Msk (0x1UL << DSI_LPMCCR_LPSIZE3_Pos) /*!< 0x00080000 */
11617 #define DSI_LPMCCR_LPSIZE3 DSI_LPMCCR_LPSIZE3_Msk
11618 #define DSI_LPMCCR_LPSIZE4_Pos (20U)
11619 #define DSI_LPMCCR_LPSIZE4_Msk (0x1UL << DSI_LPMCCR_LPSIZE4_Pos) /*!< 0x00100000 */
11620 #define DSI_LPMCCR_LPSIZE4 DSI_LPMCCR_LPSIZE4_Msk
11621 #define DSI_LPMCCR_LPSIZE5_Pos (21U)
11622 #define DSI_LPMCCR_LPSIZE5_Msk (0x1UL << DSI_LPMCCR_LPSIZE5_Pos) /*!< 0x00200000 */
11623 #define DSI_LPMCCR_LPSIZE5 DSI_LPMCCR_LPSIZE5_Msk
11624 #define DSI_LPMCCR_LPSIZE6_Pos (22U)
11625 #define DSI_LPMCCR_LPSIZE6_Msk (0x1UL << DSI_LPMCCR_LPSIZE6_Pos) /*!< 0x00400000 */
11626 #define DSI_LPMCCR_LPSIZE6 DSI_LPMCCR_LPSIZE6_Msk
11627 #define DSI_LPMCCR_LPSIZE7_Pos (23U)
11628 #define DSI_LPMCCR_LPSIZE7_Msk (0x1UL << DSI_LPMCCR_LPSIZE7_Pos) /*!< 0x00800000 */
11629 #define DSI_LPMCCR_LPSIZE7 DSI_LPMCCR_LPSIZE7_Msk
11630
11631 /******************* Bit definition for DSI_VMCCR register **************/
11632 #define DSI_VMCCR_VMT_Pos (0U)
11633 #define DSI_VMCCR_VMT_Msk (0x3UL << DSI_VMCCR_VMT_Pos) /*!< 0x00000003 */
11634 #define DSI_VMCCR_VMT DSI_VMCCR_VMT_Msk /*!< Video Mode Type */
11635 #define DSI_VMCCR_VMT0_Pos (0U)
11636 #define DSI_VMCCR_VMT0_Msk (0x1UL << DSI_VMCCR_VMT0_Pos) /*!< 0x00000001 */
11637 #define DSI_VMCCR_VMT0 DSI_VMCCR_VMT0_Msk
11638 #define DSI_VMCCR_VMT1_Pos (1U)
11639 #define DSI_VMCCR_VMT1_Msk (0x1UL << DSI_VMCCR_VMT1_Pos) /*!< 0x00000002 */
11640 #define DSI_VMCCR_VMT1 DSI_VMCCR_VMT1_Msk
11641
11642 #define DSI_VMCCR_LPVSAE_Pos (8U)
11643 #define DSI_VMCCR_LPVSAE_Msk (0x1UL << DSI_VMCCR_LPVSAE_Pos) /*!< 0x00000100 */
11644 #define DSI_VMCCR_LPVSAE DSI_VMCCR_LPVSAE_Msk /*!< Low-power Vertical Sync time Enable */
11645 #define DSI_VMCCR_LPVBPE_Pos (9U)
11646 #define DSI_VMCCR_LPVBPE_Msk (0x1UL << DSI_VMCCR_LPVBPE_Pos) /*!< 0x00000200 */
11647 #define DSI_VMCCR_LPVBPE DSI_VMCCR_LPVBPE_Msk /*!< Low-power Vertical Back-porch Enable */
11648 #define DSI_VMCCR_LPVFPE_Pos (10U)
11649 #define DSI_VMCCR_LPVFPE_Msk (0x1UL << DSI_VMCCR_LPVFPE_Pos) /*!< 0x00000400 */
11650 #define DSI_VMCCR_LPVFPE DSI_VMCCR_LPVFPE_Msk /*!< Low-power Vertical Front-porch Enable */
11651 #define DSI_VMCCR_LPVAE_Pos (11U)
11652 #define DSI_VMCCR_LPVAE_Msk (0x1UL << DSI_VMCCR_LPVAE_Pos) /*!< 0x00000800 */
11653 #define DSI_VMCCR_LPVAE DSI_VMCCR_LPVAE_Msk /*!< Low-power Vertical Active Enable */
11654 #define DSI_VMCCR_LPHBPE_Pos (12U)
11655 #define DSI_VMCCR_LPHBPE_Msk (0x1UL << DSI_VMCCR_LPHBPE_Pos) /*!< 0x00001000 */
11656 #define DSI_VMCCR_LPHBPE DSI_VMCCR_LPHBPE_Msk /*!< Low-power Horizontal Back-porch Enable */
11657 #define DSI_VMCCR_LPHFE_Pos (13U)
11658 #define DSI_VMCCR_LPHFE_Msk (0x1UL << DSI_VMCCR_LPHFE_Pos) /*!< 0x00002000 */
11659 #define DSI_VMCCR_LPHFE DSI_VMCCR_LPHFE_Msk /*!< Low-power Horizontal Front-porch Enable */
11660 #define DSI_VMCCR_FBTAAE_Pos (14U)
11661 #define DSI_VMCCR_FBTAAE_Msk (0x1UL << DSI_VMCCR_FBTAAE_Pos) /*!< 0x00004000 */
11662 #define DSI_VMCCR_FBTAAE DSI_VMCCR_FBTAAE_Msk /*!< Frame BTA Acknowledge Enable */
11663 #define DSI_VMCCR_LPCE_Pos (15U)
11664 #define DSI_VMCCR_LPCE_Msk (0x1UL << DSI_VMCCR_LPCE_Pos) /*!< 0x00008000 */
11665 #define DSI_VMCCR_LPCE DSI_VMCCR_LPCE_Msk /*!< Low-power Command Enable */
11666
11667 /******************* Bit definition for DSI_VPCCR register **************/
11668 #define DSI_VPCCR_VPSIZE_Pos (0U)
11669 #define DSI_VPCCR_VPSIZE_Msk (0x3FFFUL << DSI_VPCCR_VPSIZE_Pos) /*!< 0x00003FFF */
11670 #define DSI_VPCCR_VPSIZE DSI_VPCCR_VPSIZE_Msk /*!< Video Packet Size */
11671 #define DSI_VPCCR_VPSIZE0_Pos (0U)
11672 #define DSI_VPCCR_VPSIZE0_Msk (0x1UL << DSI_VPCCR_VPSIZE0_Pos) /*!< 0x00000001 */
11673 #define DSI_VPCCR_VPSIZE0 DSI_VPCCR_VPSIZE0_Msk
11674 #define DSI_VPCCR_VPSIZE1_Pos (1U)
11675 #define DSI_VPCCR_VPSIZE1_Msk (0x1UL << DSI_VPCCR_VPSIZE1_Pos) /*!< 0x00000002 */
11676 #define DSI_VPCCR_VPSIZE1 DSI_VPCCR_VPSIZE1_Msk
11677 #define DSI_VPCCR_VPSIZE2_Pos (2U)
11678 #define DSI_VPCCR_VPSIZE2_Msk (0x1UL << DSI_VPCCR_VPSIZE2_Pos) /*!< 0x00000004 */
11679 #define DSI_VPCCR_VPSIZE2 DSI_VPCCR_VPSIZE2_Msk
11680 #define DSI_VPCCR_VPSIZE3_Pos (3U)
11681 #define DSI_VPCCR_VPSIZE3_Msk (0x1UL << DSI_VPCCR_VPSIZE3_Pos) /*!< 0x00000008 */
11682 #define DSI_VPCCR_VPSIZE3 DSI_VPCCR_VPSIZE3_Msk
11683 #define DSI_VPCCR_VPSIZE4_Pos (4U)
11684 #define DSI_VPCCR_VPSIZE4_Msk (0x1UL << DSI_VPCCR_VPSIZE4_Pos) /*!< 0x00000010 */
11685 #define DSI_VPCCR_VPSIZE4 DSI_VPCCR_VPSIZE4_Msk
11686 #define DSI_VPCCR_VPSIZE5_Pos (5U)
11687 #define DSI_VPCCR_VPSIZE5_Msk (0x1UL << DSI_VPCCR_VPSIZE5_Pos) /*!< 0x00000020 */
11688 #define DSI_VPCCR_VPSIZE5 DSI_VPCCR_VPSIZE5_Msk
11689 #define DSI_VPCCR_VPSIZE6_Pos (6U)
11690 #define DSI_VPCCR_VPSIZE6_Msk (0x1UL << DSI_VPCCR_VPSIZE6_Pos) /*!< 0x00000040 */
11691 #define DSI_VPCCR_VPSIZE6 DSI_VPCCR_VPSIZE6_Msk
11692 #define DSI_VPCCR_VPSIZE7_Pos (7U)
11693 #define DSI_VPCCR_VPSIZE7_Msk (0x1UL << DSI_VPCCR_VPSIZE7_Pos) /*!< 0x00000080 */
11694 #define DSI_VPCCR_VPSIZE7 DSI_VPCCR_VPSIZE7_Msk
11695 #define DSI_VPCCR_VPSIZE8_Pos (8U)
11696 #define DSI_VPCCR_VPSIZE8_Msk (0x1UL << DSI_VPCCR_VPSIZE8_Pos) /*!< 0x00000100 */
11697 #define DSI_VPCCR_VPSIZE8 DSI_VPCCR_VPSIZE8_Msk
11698 #define DSI_VPCCR_VPSIZE9_Pos (9U)
11699 #define DSI_VPCCR_VPSIZE9_Msk (0x1UL << DSI_VPCCR_VPSIZE9_Pos) /*!< 0x00000200 */
11700 #define DSI_VPCCR_VPSIZE9 DSI_VPCCR_VPSIZE9_Msk
11701 #define DSI_VPCCR_VPSIZE10_Pos (10U)
11702 #define DSI_VPCCR_VPSIZE10_Msk (0x1UL << DSI_VPCCR_VPSIZE10_Pos) /*!< 0x00000400 */
11703 #define DSI_VPCCR_VPSIZE10 DSI_VPCCR_VPSIZE10_Msk
11704 #define DSI_VPCCR_VPSIZE11_Pos (11U)
11705 #define DSI_VPCCR_VPSIZE11_Msk (0x1UL << DSI_VPCCR_VPSIZE11_Pos) /*!< 0x00000800 */
11706 #define DSI_VPCCR_VPSIZE11 DSI_VPCCR_VPSIZE11_Msk
11707 #define DSI_VPCCR_VPSIZE12_Pos (12U)
11708 #define DSI_VPCCR_VPSIZE12_Msk (0x1UL << DSI_VPCCR_VPSIZE12_Pos) /*!< 0x00001000 */
11709 #define DSI_VPCCR_VPSIZE12 DSI_VPCCR_VPSIZE12_Msk
11710 #define DSI_VPCCR_VPSIZE13_Pos (13U)
11711 #define DSI_VPCCR_VPSIZE13_Msk (0x1UL << DSI_VPCCR_VPSIZE13_Pos) /*!< 0x00002000 */
11712 #define DSI_VPCCR_VPSIZE13 DSI_VPCCR_VPSIZE13_Msk
11713
11714 /******************* Bit definition for DSI_VCCCR register **************/
11715 #define DSI_VCCCR_NUMC_Pos (0U)
11716 #define DSI_VCCCR_NUMC_Msk (0x1FFFUL << DSI_VCCCR_NUMC_Pos) /*!< 0x00001FFF */
11717 #define DSI_VCCCR_NUMC DSI_VCCCR_NUMC_Msk /*!< Number of Chunks */
11718 #define DSI_VCCCR_NUMC0_Pos (0U)
11719 #define DSI_VCCCR_NUMC0_Msk (0x1UL << DSI_VCCCR_NUMC0_Pos) /*!< 0x00000001 */
11720 #define DSI_VCCCR_NUMC0 DSI_VCCCR_NUMC0_Msk
11721 #define DSI_VCCCR_NUMC1_Pos (1U)
11722 #define DSI_VCCCR_NUMC1_Msk (0x1UL << DSI_VCCCR_NUMC1_Pos) /*!< 0x00000002 */
11723 #define DSI_VCCCR_NUMC1 DSI_VCCCR_NUMC1_Msk
11724 #define DSI_VCCCR_NUMC2_Pos (2U)
11725 #define DSI_VCCCR_NUMC2_Msk (0x1UL << DSI_VCCCR_NUMC2_Pos) /*!< 0x00000004 */
11726 #define DSI_VCCCR_NUMC2 DSI_VCCCR_NUMC2_Msk
11727 #define DSI_VCCCR_NUMC3_Pos (3U)
11728 #define DSI_VCCCR_NUMC3_Msk (0x1UL << DSI_VCCCR_NUMC3_Pos) /*!< 0x00000008 */
11729 #define DSI_VCCCR_NUMC3 DSI_VCCCR_NUMC3_Msk
11730 #define DSI_VCCCR_NUMC4_Pos (4U)
11731 #define DSI_VCCCR_NUMC4_Msk (0x1UL << DSI_VCCCR_NUMC4_Pos) /*!< 0x00000010 */
11732 #define DSI_VCCCR_NUMC4 DSI_VCCCR_NUMC4_Msk
11733 #define DSI_VCCCR_NUMC5_Pos (5U)
11734 #define DSI_VCCCR_NUMC5_Msk (0x1UL << DSI_VCCCR_NUMC5_Pos) /*!< 0x00000020 */
11735 #define DSI_VCCCR_NUMC5 DSI_VCCCR_NUMC5_Msk
11736 #define DSI_VCCCR_NUMC6_Pos (6U)
11737 #define DSI_VCCCR_NUMC6_Msk (0x1UL << DSI_VCCCR_NUMC6_Pos) /*!< 0x00000040 */
11738 #define DSI_VCCCR_NUMC6 DSI_VCCCR_NUMC6_Msk
11739 #define DSI_VCCCR_NUMC7_Pos (7U)
11740 #define DSI_VCCCR_NUMC7_Msk (0x1UL << DSI_VCCCR_NUMC7_Pos) /*!< 0x00000080 */
11741 #define DSI_VCCCR_NUMC7 DSI_VCCCR_NUMC7_Msk
11742 #define DSI_VCCCR_NUMC8_Pos (8U)
11743 #define DSI_VCCCR_NUMC8_Msk (0x1UL << DSI_VCCCR_NUMC8_Pos) /*!< 0x00000100 */
11744 #define DSI_VCCCR_NUMC8 DSI_VCCCR_NUMC8_Msk
11745 #define DSI_VCCCR_NUMC9_Pos (9U)
11746 #define DSI_VCCCR_NUMC9_Msk (0x1UL << DSI_VCCCR_NUMC9_Pos) /*!< 0x00000200 */
11747 #define DSI_VCCCR_NUMC9 DSI_VCCCR_NUMC9_Msk
11748 #define DSI_VCCCR_NUMC10_Pos (10U)
11749 #define DSI_VCCCR_NUMC10_Msk (0x1UL << DSI_VCCCR_NUMC10_Pos) /*!< 0x00000400 */
11750 #define DSI_VCCCR_NUMC10 DSI_VCCCR_NUMC10_Msk
11751 #define DSI_VCCCR_NUMC11_Pos (11U)
11752 #define DSI_VCCCR_NUMC11_Msk (0x1UL << DSI_VCCCR_NUMC11_Pos) /*!< 0x00000800 */
11753 #define DSI_VCCCR_NUMC11 DSI_VCCCR_NUMC11_Msk
11754 #define DSI_VCCCR_NUMC12_Pos (12U)
11755 #define DSI_VCCCR_NUMC12_Msk (0x1UL << DSI_VCCCR_NUMC12_Pos) /*!< 0x00001000 */
11756 #define DSI_VCCCR_NUMC12 DSI_VCCCR_NUMC12_Msk
11757
11758 /******************* Bit definition for DSI_VNPCCR register *************/
11759 #define DSI_VNPCCR_NPSIZE_Pos (0U)
11760 #define DSI_VNPCCR_NPSIZE_Msk (0x1FFFUL << DSI_VNPCCR_NPSIZE_Pos) /*!< 0x00001FFF */
11761 #define DSI_VNPCCR_NPSIZE DSI_VNPCCR_NPSIZE_Msk /*!< Number of Chunks */
11762 #define DSI_VNPCCR_NPSIZE0_Pos (0U)
11763 #define DSI_VNPCCR_NPSIZE0_Msk (0x1UL << DSI_VNPCCR_NPSIZE0_Pos) /*!< 0x00000001 */
11764 #define DSI_VNPCCR_NPSIZE0 DSI_VNPCCR_NPSIZE0_Msk
11765 #define DSI_VNPCCR_NPSIZE1_Pos (1U)
11766 #define DSI_VNPCCR_NPSIZE1_Msk (0x1UL << DSI_VNPCCR_NPSIZE1_Pos) /*!< 0x00000002 */
11767 #define DSI_VNPCCR_NPSIZE1 DSI_VNPCCR_NPSIZE1_Msk
11768 #define DSI_VNPCCR_NPSIZE2_Pos (2U)
11769 #define DSI_VNPCCR_NPSIZE2_Msk (0x1UL << DSI_VNPCCR_NPSIZE2_Pos) /*!< 0x00000004 */
11770 #define DSI_VNPCCR_NPSIZE2 DSI_VNPCCR_NPSIZE2_Msk
11771 #define DSI_VNPCCR_NPSIZE3_Pos (3U)
11772 #define DSI_VNPCCR_NPSIZE3_Msk (0x1UL << DSI_VNPCCR_NPSIZE3_Pos) /*!< 0x00000008 */
11773 #define DSI_VNPCCR_NPSIZE3 DSI_VNPCCR_NPSIZE3_Msk
11774 #define DSI_VNPCCR_NPSIZE4_Pos (4U)
11775 #define DSI_VNPCCR_NPSIZE4_Msk (0x1UL << DSI_VNPCCR_NPSIZE4_Pos) /*!< 0x00000010 */
11776 #define DSI_VNPCCR_NPSIZE4 DSI_VNPCCR_NPSIZE4_Msk
11777 #define DSI_VNPCCR_NPSIZE5_Pos (5U)
11778 #define DSI_VNPCCR_NPSIZE5_Msk (0x1UL << DSI_VNPCCR_NPSIZE5_Pos) /*!< 0x00000020 */
11779 #define DSI_VNPCCR_NPSIZE5 DSI_VNPCCR_NPSIZE5_Msk
11780 #define DSI_VNPCCR_NPSIZE6_Pos (6U)
11781 #define DSI_VNPCCR_NPSIZE6_Msk (0x1UL << DSI_VNPCCR_NPSIZE6_Pos) /*!< 0x00000040 */
11782 #define DSI_VNPCCR_NPSIZE6 DSI_VNPCCR_NPSIZE6_Msk
11783 #define DSI_VNPCCR_NPSIZE7_Pos (7U)
11784 #define DSI_VNPCCR_NPSIZE7_Msk (0x1UL << DSI_VNPCCR_NPSIZE7_Pos) /*!< 0x00000080 */
11785 #define DSI_VNPCCR_NPSIZE7 DSI_VNPCCR_NPSIZE7_Msk
11786 #define DSI_VNPCCR_NPSIZE8_Pos (8U)
11787 #define DSI_VNPCCR_NPSIZE8_Msk (0x1UL << DSI_VNPCCR_NPSIZE8_Pos) /*!< 0x00000100 */
11788 #define DSI_VNPCCR_NPSIZE8 DSI_VNPCCR_NPSIZE8_Msk
11789 #define DSI_VNPCCR_NPSIZE9_Pos (9U)
11790 #define DSI_VNPCCR_NPSIZE9_Msk (0x1UL << DSI_VNPCCR_NPSIZE9_Pos) /*!< 0x00000200 */
11791 #define DSI_VNPCCR_NPSIZE9 DSI_VNPCCR_NPSIZE9_Msk
11792 #define DSI_VNPCCR_NPSIZE10_Pos (10U)
11793 #define DSI_VNPCCR_NPSIZE10_Msk (0x1UL << DSI_VNPCCR_NPSIZE10_Pos) /*!< 0x00000400 */
11794 #define DSI_VNPCCR_NPSIZE10 DSI_VNPCCR_NPSIZE10_Msk
11795 #define DSI_VNPCCR_NPSIZE11_Pos (11U)
11796 #define DSI_VNPCCR_NPSIZE11_Msk (0x1UL << DSI_VNPCCR_NPSIZE11_Pos) /*!< 0x00000800 */
11797 #define DSI_VNPCCR_NPSIZE11 DSI_VNPCCR_NPSIZE11_Msk
11798 #define DSI_VNPCCR_NPSIZE12_Pos (12U)
11799 #define DSI_VNPCCR_NPSIZE12_Msk (0x1UL << DSI_VNPCCR_NPSIZE12_Pos) /*!< 0x00001000 */
11800 #define DSI_VNPCCR_NPSIZE12 DSI_VNPCCR_NPSIZE12_Msk
11801
11802 /******************* Bit definition for DSI_VHSACCR register ************/
11803 #define DSI_VHSACCR_HSA_Pos (0U)
11804 #define DSI_VHSACCR_HSA_Msk (0xFFFUL << DSI_VHSACCR_HSA_Pos) /*!< 0x00000FFF */
11805 #define DSI_VHSACCR_HSA DSI_VHSACCR_HSA_Msk /*!< Horizontal Synchronism Active duration */
11806 #define DSI_VHSACCR_HSA0_Pos (0U)
11807 #define DSI_VHSACCR_HSA0_Msk (0x1UL << DSI_VHSACCR_HSA0_Pos) /*!< 0x00000001 */
11808 #define DSI_VHSACCR_HSA0 DSI_VHSACCR_HSA0_Msk
11809 #define DSI_VHSACCR_HSA1_Pos (1U)
11810 #define DSI_VHSACCR_HSA1_Msk (0x1UL << DSI_VHSACCR_HSA1_Pos) /*!< 0x00000002 */
11811 #define DSI_VHSACCR_HSA1 DSI_VHSACCR_HSA1_Msk
11812 #define DSI_VHSACCR_HSA2_Pos (2U)
11813 #define DSI_VHSACCR_HSA2_Msk (0x1UL << DSI_VHSACCR_HSA2_Pos) /*!< 0x00000004 */
11814 #define DSI_VHSACCR_HSA2 DSI_VHSACCR_HSA2_Msk
11815 #define DSI_VHSACCR_HSA3_Pos (3U)
11816 #define DSI_VHSACCR_HSA3_Msk (0x1UL << DSI_VHSACCR_HSA3_Pos) /*!< 0x00000008 */
11817 #define DSI_VHSACCR_HSA3 DSI_VHSACCR_HSA3_Msk
11818 #define DSI_VHSACCR_HSA4_Pos (4U)
11819 #define DSI_VHSACCR_HSA4_Msk (0x1UL << DSI_VHSACCR_HSA4_Pos) /*!< 0x00000010 */
11820 #define DSI_VHSACCR_HSA4 DSI_VHSACCR_HSA4_Msk
11821 #define DSI_VHSACCR_HSA5_Pos (5U)
11822 #define DSI_VHSACCR_HSA5_Msk (0x1UL << DSI_VHSACCR_HSA5_Pos) /*!< 0x00000020 */
11823 #define DSI_VHSACCR_HSA5 DSI_VHSACCR_HSA5_Msk
11824 #define DSI_VHSACCR_HSA6_Pos (6U)
11825 #define DSI_VHSACCR_HSA6_Msk (0x1UL << DSI_VHSACCR_HSA6_Pos) /*!< 0x00000040 */
11826 #define DSI_VHSACCR_HSA6 DSI_VHSACCR_HSA6_Msk
11827 #define DSI_VHSACCR_HSA7_Pos (7U)
11828 #define DSI_VHSACCR_HSA7_Msk (0x1UL << DSI_VHSACCR_HSA7_Pos) /*!< 0x00000080 */
11829 #define DSI_VHSACCR_HSA7 DSI_VHSACCR_HSA7_Msk
11830 #define DSI_VHSACCR_HSA8_Pos (8U)
11831 #define DSI_VHSACCR_HSA8_Msk (0x1UL << DSI_VHSACCR_HSA8_Pos) /*!< 0x00000100 */
11832 #define DSI_VHSACCR_HSA8 DSI_VHSACCR_HSA8_Msk
11833 #define DSI_VHSACCR_HSA9_Pos (9U)
11834 #define DSI_VHSACCR_HSA9_Msk (0x1UL << DSI_VHSACCR_HSA9_Pos) /*!< 0x00000200 */
11835 #define DSI_VHSACCR_HSA9 DSI_VHSACCR_HSA9_Msk
11836 #define DSI_VHSACCR_HSA10_Pos (10U)
11837 #define DSI_VHSACCR_HSA10_Msk (0x1UL << DSI_VHSACCR_HSA10_Pos) /*!< 0x00000400 */
11838 #define DSI_VHSACCR_HSA10 DSI_VHSACCR_HSA10_Msk
11839 #define DSI_VHSACCR_HSA11_Pos (11U)
11840 #define DSI_VHSACCR_HSA11_Msk (0x1UL << DSI_VHSACCR_HSA11_Pos) /*!< 0x00000800 */
11841 #define DSI_VHSACCR_HSA11 DSI_VHSACCR_HSA11_Msk
11842
11843 /******************* Bit definition for DSI_VHBPCCR register ************/
11844 #define DSI_VHBPCCR_HBP_Pos (0U)
11845 #define DSI_VHBPCCR_HBP_Msk (0xFFFUL << DSI_VHBPCCR_HBP_Pos) /*!< 0x00000FFF */
11846 #define DSI_VHBPCCR_HBP DSI_VHBPCCR_HBP_Msk /*!< Horizontal Back-Porch duration */
11847 #define DSI_VHBPCCR_HBP0_Pos (0U)
11848 #define DSI_VHBPCCR_HBP0_Msk (0x1UL << DSI_VHBPCCR_HBP0_Pos) /*!< 0x00000001 */
11849 #define DSI_VHBPCCR_HBP0 DSI_VHBPCCR_HBP0_Msk
11850 #define DSI_VHBPCCR_HBP1_Pos (1U)
11851 #define DSI_VHBPCCR_HBP1_Msk (0x1UL << DSI_VHBPCCR_HBP1_Pos) /*!< 0x00000002 */
11852 #define DSI_VHBPCCR_HBP1 DSI_VHBPCCR_HBP1_Msk
11853 #define DSI_VHBPCCR_HBP2_Pos (2U)
11854 #define DSI_VHBPCCR_HBP2_Msk (0x1UL << DSI_VHBPCCR_HBP2_Pos) /*!< 0x00000004 */
11855 #define DSI_VHBPCCR_HBP2 DSI_VHBPCCR_HBP2_Msk
11856 #define DSI_VHBPCCR_HBP3_Pos (3U)
11857 #define DSI_VHBPCCR_HBP3_Msk (0x1UL << DSI_VHBPCCR_HBP3_Pos) /*!< 0x00000008 */
11858 #define DSI_VHBPCCR_HBP3 DSI_VHBPCCR_HBP3_Msk
11859 #define DSI_VHBPCCR_HBP4_Pos (4U)
11860 #define DSI_VHBPCCR_HBP4_Msk (0x1UL << DSI_VHBPCCR_HBP4_Pos) /*!< 0x00000010 */
11861 #define DSI_VHBPCCR_HBP4 DSI_VHBPCCR_HBP4_Msk
11862 #define DSI_VHBPCCR_HBP5_Pos (5U)
11863 #define DSI_VHBPCCR_HBP5_Msk (0x1UL << DSI_VHBPCCR_HBP5_Pos) /*!< 0x00000020 */
11864 #define DSI_VHBPCCR_HBP5 DSI_VHBPCCR_HBP5_Msk
11865 #define DSI_VHBPCCR_HBP6_Pos (6U)
11866 #define DSI_VHBPCCR_HBP6_Msk (0x1UL << DSI_VHBPCCR_HBP6_Pos) /*!< 0x00000040 */
11867 #define DSI_VHBPCCR_HBP6 DSI_VHBPCCR_HBP6_Msk
11868 #define DSI_VHBPCCR_HBP7_Pos (7U)
11869 #define DSI_VHBPCCR_HBP7_Msk (0x1UL << DSI_VHBPCCR_HBP7_Pos) /*!< 0x00000080 */
11870 #define DSI_VHBPCCR_HBP7 DSI_VHBPCCR_HBP7_Msk
11871 #define DSI_VHBPCCR_HBP8_Pos (8U)
11872 #define DSI_VHBPCCR_HBP8_Msk (0x1UL << DSI_VHBPCCR_HBP8_Pos) /*!< 0x00000100 */
11873 #define DSI_VHBPCCR_HBP8 DSI_VHBPCCR_HBP8_Msk
11874 #define DSI_VHBPCCR_HBP9_Pos (9U)
11875 #define DSI_VHBPCCR_HBP9_Msk (0x1UL << DSI_VHBPCCR_HBP9_Pos) /*!< 0x00000200 */
11876 #define DSI_VHBPCCR_HBP9 DSI_VHBPCCR_HBP9_Msk
11877 #define DSI_VHBPCCR_HBP10_Pos (10U)
11878 #define DSI_VHBPCCR_HBP10_Msk (0x1UL << DSI_VHBPCCR_HBP10_Pos) /*!< 0x00000400 */
11879 #define DSI_VHBPCCR_HBP10 DSI_VHBPCCR_HBP10_Msk
11880 #define DSI_VHBPCCR_HBP11_Pos (11U)
11881 #define DSI_VHBPCCR_HBP11_Msk (0x1UL << DSI_VHBPCCR_HBP11_Pos) /*!< 0x00000800 */
11882 #define DSI_VHBPCCR_HBP11 DSI_VHBPCCR_HBP11_Msk
11883
11884 /******************* Bit definition for DSI_VLCCR register **************/
11885 #define DSI_VLCCR_HLINE_Pos (0U)
11886 #define DSI_VLCCR_HLINE_Msk (0x7FFFUL << DSI_VLCCR_HLINE_Pos) /*!< 0x00007FFF */
11887 #define DSI_VLCCR_HLINE DSI_VLCCR_HLINE_Msk /*!< Horizontal Line duration */
11888 #define DSI_VLCCR_HLINE0_Pos (0U)
11889 #define DSI_VLCCR_HLINE0_Msk (0x1UL << DSI_VLCCR_HLINE0_Pos) /*!< 0x00000001 */
11890 #define DSI_VLCCR_HLINE0 DSI_VLCCR_HLINE0_Msk
11891 #define DSI_VLCCR_HLINE1_Pos (1U)
11892 #define DSI_VLCCR_HLINE1_Msk (0x1UL << DSI_VLCCR_HLINE1_Pos) /*!< 0x00000002 */
11893 #define DSI_VLCCR_HLINE1 DSI_VLCCR_HLINE1_Msk
11894 #define DSI_VLCCR_HLINE2_Pos (2U)
11895 #define DSI_VLCCR_HLINE2_Msk (0x1UL << DSI_VLCCR_HLINE2_Pos) /*!< 0x00000004 */
11896 #define DSI_VLCCR_HLINE2 DSI_VLCCR_HLINE2_Msk
11897 #define DSI_VLCCR_HLINE3_Pos (3U)
11898 #define DSI_VLCCR_HLINE3_Msk (0x1UL << DSI_VLCCR_HLINE3_Pos) /*!< 0x00000008 */
11899 #define DSI_VLCCR_HLINE3 DSI_VLCCR_HLINE3_Msk
11900 #define DSI_VLCCR_HLINE4_Pos (4U)
11901 #define DSI_VLCCR_HLINE4_Msk (0x1UL << DSI_VLCCR_HLINE4_Pos) /*!< 0x00000010 */
11902 #define DSI_VLCCR_HLINE4 DSI_VLCCR_HLINE4_Msk
11903 #define DSI_VLCCR_HLINE5_Pos (5U)
11904 #define DSI_VLCCR_HLINE5_Msk (0x1UL << DSI_VLCCR_HLINE5_Pos) /*!< 0x00000020 */
11905 #define DSI_VLCCR_HLINE5 DSI_VLCCR_HLINE5_Msk
11906 #define DSI_VLCCR_HLINE6_Pos (6U)
11907 #define DSI_VLCCR_HLINE6_Msk (0x1UL << DSI_VLCCR_HLINE6_Pos) /*!< 0x00000040 */
11908 #define DSI_VLCCR_HLINE6 DSI_VLCCR_HLINE6_Msk
11909 #define DSI_VLCCR_HLINE7_Pos (7U)
11910 #define DSI_VLCCR_HLINE7_Msk (0x1UL << DSI_VLCCR_HLINE7_Pos) /*!< 0x00000080 */
11911 #define DSI_VLCCR_HLINE7 DSI_VLCCR_HLINE7_Msk
11912 #define DSI_VLCCR_HLINE8_Pos (8U)
11913 #define DSI_VLCCR_HLINE8_Msk (0x1UL << DSI_VLCCR_HLINE8_Pos) /*!< 0x00000100 */
11914 #define DSI_VLCCR_HLINE8 DSI_VLCCR_HLINE8_Msk
11915 #define DSI_VLCCR_HLINE9_Pos (9U)
11916 #define DSI_VLCCR_HLINE9_Msk (0x1UL << DSI_VLCCR_HLINE9_Pos) /*!< 0x00000200 */
11917 #define DSI_VLCCR_HLINE9 DSI_VLCCR_HLINE9_Msk
11918 #define DSI_VLCCR_HLINE10_Pos (10U)
11919 #define DSI_VLCCR_HLINE10_Msk (0x1UL << DSI_VLCCR_HLINE10_Pos) /*!< 0x00000400 */
11920 #define DSI_VLCCR_HLINE10 DSI_VLCCR_HLINE10_Msk
11921 #define DSI_VLCCR_HLINE11_Pos (11U)
11922 #define DSI_VLCCR_HLINE11_Msk (0x1UL << DSI_VLCCR_HLINE11_Pos) /*!< 0x00000800 */
11923 #define DSI_VLCCR_HLINE11 DSI_VLCCR_HLINE11_Msk
11924 #define DSI_VLCCR_HLINE12_Pos (12U)
11925 #define DSI_VLCCR_HLINE12_Msk (0x1UL << DSI_VLCCR_HLINE12_Pos) /*!< 0x00001000 */
11926 #define DSI_VLCCR_HLINE12 DSI_VLCCR_HLINE12_Msk
11927 #define DSI_VLCCR_HLINE13_Pos (13U)
11928 #define DSI_VLCCR_HLINE13_Msk (0x1UL << DSI_VLCCR_HLINE13_Pos) /*!< 0x00002000 */
11929 #define DSI_VLCCR_HLINE13 DSI_VLCCR_HLINE13_Msk
11930 #define DSI_VLCCR_HLINE14_Pos (14U)
11931 #define DSI_VLCCR_HLINE14_Msk (0x1UL << DSI_VLCCR_HLINE14_Pos) /*!< 0x00004000 */
11932 #define DSI_VLCCR_HLINE14 DSI_VLCCR_HLINE14_Msk
11933
11934 /******************* Bit definition for DSI_VVSACCR register ***************/
11935 #define DSI_VVSACCR_VSA_Pos (0U)
11936 #define DSI_VVSACCR_VSA_Msk (0x3FFUL << DSI_VVSACCR_VSA_Pos) /*!< 0x000003FF */
11937 #define DSI_VVSACCR_VSA DSI_VVSACCR_VSA_Msk /*!< Vertical Synchronism Active duration */
11938 #define DSI_VVSACCR_VSA0_Pos (0U)
11939 #define DSI_VVSACCR_VSA0_Msk (0x1UL << DSI_VVSACCR_VSA0_Pos) /*!< 0x00000001 */
11940 #define DSI_VVSACCR_VSA0 DSI_VVSACCR_VSA0_Msk
11941 #define DSI_VVSACCR_VSA1_Pos (1U)
11942 #define DSI_VVSACCR_VSA1_Msk (0x1UL << DSI_VVSACCR_VSA1_Pos) /*!< 0x00000002 */
11943 #define DSI_VVSACCR_VSA1 DSI_VVSACCR_VSA1_Msk
11944 #define DSI_VVSACCR_VSA2_Pos (2U)
11945 #define DSI_VVSACCR_VSA2_Msk (0x1UL << DSI_VVSACCR_VSA2_Pos) /*!< 0x00000004 */
11946 #define DSI_VVSACCR_VSA2 DSI_VVSACCR_VSA2_Msk
11947 #define DSI_VVSACCR_VSA3_Pos (3U)
11948 #define DSI_VVSACCR_VSA3_Msk (0x1UL << DSI_VVSACCR_VSA3_Pos) /*!< 0x00000008 */
11949 #define DSI_VVSACCR_VSA3 DSI_VVSACCR_VSA3_Msk
11950 #define DSI_VVSACCR_VSA4_Pos (4U)
11951 #define DSI_VVSACCR_VSA4_Msk (0x1UL << DSI_VVSACCR_VSA4_Pos) /*!< 0x00000010 */
11952 #define DSI_VVSACCR_VSA4 DSI_VVSACCR_VSA4_Msk
11953 #define DSI_VVSACCR_VSA5_Pos (5U)
11954 #define DSI_VVSACCR_VSA5_Msk (0x1UL << DSI_VVSACCR_VSA5_Pos) /*!< 0x00000020 */
11955 #define DSI_VVSACCR_VSA5 DSI_VVSACCR_VSA5_Msk
11956 #define DSI_VVSACCR_VSA6_Pos (6U)
11957 #define DSI_VVSACCR_VSA6_Msk (0x1UL << DSI_VVSACCR_VSA6_Pos) /*!< 0x00000040 */
11958 #define DSI_VVSACCR_VSA6 DSI_VVSACCR_VSA6_Msk
11959 #define DSI_VVSACCR_VSA7_Pos (7U)
11960 #define DSI_VVSACCR_VSA7_Msk (0x1UL << DSI_VVSACCR_VSA7_Pos) /*!< 0x00000080 */
11961 #define DSI_VVSACCR_VSA7 DSI_VVSACCR_VSA7_Msk
11962 #define DSI_VVSACCR_VSA8_Pos (8U)
11963 #define DSI_VVSACCR_VSA8_Msk (0x1UL << DSI_VVSACCR_VSA8_Pos) /*!< 0x00000100 */
11964 #define DSI_VVSACCR_VSA8 DSI_VVSACCR_VSA8_Msk
11965 #define DSI_VVSACCR_VSA9_Pos (9U)
11966 #define DSI_VVSACCR_VSA9_Msk (0x1UL << DSI_VVSACCR_VSA9_Pos) /*!< 0x00000200 */
11967 #define DSI_VVSACCR_VSA9 DSI_VVSACCR_VSA9_Msk
11968
11969 /******************* Bit definition for DSI_VVBPCCR register ************/
11970 #define DSI_VVBPCCR_VBP_Pos (0U)
11971 #define DSI_VVBPCCR_VBP_Msk (0x3FFUL << DSI_VVBPCCR_VBP_Pos) /*!< 0x000003FF */
11972 #define DSI_VVBPCCR_VBP DSI_VVBPCCR_VBP_Msk /*!< Vertical Back-Porch duration */
11973 #define DSI_VVBPCCR_VBP0_Pos (0U)
11974 #define DSI_VVBPCCR_VBP0_Msk (0x1UL << DSI_VVBPCCR_VBP0_Pos) /*!< 0x00000001 */
11975 #define DSI_VVBPCCR_VBP0 DSI_VVBPCCR_VBP0_Msk
11976 #define DSI_VVBPCCR_VBP1_Pos (1U)
11977 #define DSI_VVBPCCR_VBP1_Msk (0x1UL << DSI_VVBPCCR_VBP1_Pos) /*!< 0x00000002 */
11978 #define DSI_VVBPCCR_VBP1 DSI_VVBPCCR_VBP1_Msk
11979 #define DSI_VVBPCCR_VBP2_Pos (2U)
11980 #define DSI_VVBPCCR_VBP2_Msk (0x1UL << DSI_VVBPCCR_VBP2_Pos) /*!< 0x00000004 */
11981 #define DSI_VVBPCCR_VBP2 DSI_VVBPCCR_VBP2_Msk
11982 #define DSI_VVBPCCR_VBP3_Pos (3U)
11983 #define DSI_VVBPCCR_VBP3_Msk (0x1UL << DSI_VVBPCCR_VBP3_Pos) /*!< 0x00000008 */
11984 #define DSI_VVBPCCR_VBP3 DSI_VVBPCCR_VBP3_Msk
11985 #define DSI_VVBPCCR_VBP4_Pos (4U)
11986 #define DSI_VVBPCCR_VBP4_Msk (0x1UL << DSI_VVBPCCR_VBP4_Pos) /*!< 0x00000010 */
11987 #define DSI_VVBPCCR_VBP4 DSI_VVBPCCR_VBP4_Msk
11988 #define DSI_VVBPCCR_VBP5_Pos (5U)
11989 #define DSI_VVBPCCR_VBP5_Msk (0x1UL << DSI_VVBPCCR_VBP5_Pos) /*!< 0x00000020 */
11990 #define DSI_VVBPCCR_VBP5 DSI_VVBPCCR_VBP5_Msk
11991 #define DSI_VVBPCCR_VBP6_Pos (6U)
11992 #define DSI_VVBPCCR_VBP6_Msk (0x1UL << DSI_VVBPCCR_VBP6_Pos) /*!< 0x00000040 */
11993 #define DSI_VVBPCCR_VBP6 DSI_VVBPCCR_VBP6_Msk
11994 #define DSI_VVBPCCR_VBP7_Pos (7U)
11995 #define DSI_VVBPCCR_VBP7_Msk (0x1UL << DSI_VVBPCCR_VBP7_Pos) /*!< 0x00000080 */
11996 #define DSI_VVBPCCR_VBP7 DSI_VVBPCCR_VBP7_Msk
11997 #define DSI_VVBPCCR_VBP8_Pos (8U)
11998 #define DSI_VVBPCCR_VBP8_Msk (0x1UL << DSI_VVBPCCR_VBP8_Pos) /*!< 0x00000100 */
11999 #define DSI_VVBPCCR_VBP8 DSI_VVBPCCR_VBP8_Msk
12000 #define DSI_VVBPCCR_VBP9_Pos (9U)
12001 #define DSI_VVBPCCR_VBP9_Msk (0x1UL << DSI_VVBPCCR_VBP9_Pos) /*!< 0x00000200 */
12002 #define DSI_VVBPCCR_VBP9 DSI_VVBPCCR_VBP9_Msk
12003
12004 /******************* Bit definition for DSI_VVFPCCR register ************/
12005 #define DSI_VVFPCCR_VFP_Pos (0U)
12006 #define DSI_VVFPCCR_VFP_Msk (0x3FFUL << DSI_VVFPCCR_VFP_Pos) /*!< 0x000003FF */
12007 #define DSI_VVFPCCR_VFP DSI_VVFPCCR_VFP_Msk /*!< Vertical Front-Porch duration */
12008 #define DSI_VVFPCCR_VFP0_Pos (0U)
12009 #define DSI_VVFPCCR_VFP0_Msk (0x1UL << DSI_VVFPCCR_VFP0_Pos) /*!< 0x00000001 */
12010 #define DSI_VVFPCCR_VFP0 DSI_VVFPCCR_VFP0_Msk
12011 #define DSI_VVFPCCR_VFP1_Pos (1U)
12012 #define DSI_VVFPCCR_VFP1_Msk (0x1UL << DSI_VVFPCCR_VFP1_Pos) /*!< 0x00000002 */
12013 #define DSI_VVFPCCR_VFP1 DSI_VVFPCCR_VFP1_Msk
12014 #define DSI_VVFPCCR_VFP2_Pos (2U)
12015 #define DSI_VVFPCCR_VFP2_Msk (0x1UL << DSI_VVFPCCR_VFP2_Pos) /*!< 0x00000004 */
12016 #define DSI_VVFPCCR_VFP2 DSI_VVFPCCR_VFP2_Msk
12017 #define DSI_VVFPCCR_VFP3_Pos (3U)
12018 #define DSI_VVFPCCR_VFP3_Msk (0x1UL << DSI_VVFPCCR_VFP3_Pos) /*!< 0x00000008 */
12019 #define DSI_VVFPCCR_VFP3 DSI_VVFPCCR_VFP3_Msk
12020 #define DSI_VVFPCCR_VFP4_Pos (4U)
12021 #define DSI_VVFPCCR_VFP4_Msk (0x1UL << DSI_VVFPCCR_VFP4_Pos) /*!< 0x00000010 */
12022 #define DSI_VVFPCCR_VFP4 DSI_VVFPCCR_VFP4_Msk
12023 #define DSI_VVFPCCR_VFP5_Pos (5U)
12024 #define DSI_VVFPCCR_VFP5_Msk (0x1UL << DSI_VVFPCCR_VFP5_Pos) /*!< 0x00000020 */
12025 #define DSI_VVFPCCR_VFP5 DSI_VVFPCCR_VFP5_Msk
12026 #define DSI_VVFPCCR_VFP6_Pos (6U)
12027 #define DSI_VVFPCCR_VFP6_Msk (0x1UL << DSI_VVFPCCR_VFP6_Pos) /*!< 0x00000040 */
12028 #define DSI_VVFPCCR_VFP6 DSI_VVFPCCR_VFP6_Msk
12029 #define DSI_VVFPCCR_VFP7_Pos (7U)
12030 #define DSI_VVFPCCR_VFP7_Msk (0x1UL << DSI_VVFPCCR_VFP7_Pos) /*!< 0x00000080 */
12031 #define DSI_VVFPCCR_VFP7 DSI_VVFPCCR_VFP7_Msk
12032 #define DSI_VVFPCCR_VFP8_Pos (8U)
12033 #define DSI_VVFPCCR_VFP8_Msk (0x1UL << DSI_VVFPCCR_VFP8_Pos) /*!< 0x00000100 */
12034 #define DSI_VVFPCCR_VFP8 DSI_VVFPCCR_VFP8_Msk
12035 #define DSI_VVFPCCR_VFP9_Pos (9U)
12036 #define DSI_VVFPCCR_VFP9_Msk (0x1UL << DSI_VVFPCCR_VFP9_Pos) /*!< 0x00000200 */
12037 #define DSI_VVFPCCR_VFP9 DSI_VVFPCCR_VFP9_Msk
12038
12039 /******************* Bit definition for DSI_VVACCR register *************/
12040 #define DSI_VVACCR_VA_Pos (0U)
12041 #define DSI_VVACCR_VA_Msk (0x3FFFUL << DSI_VVACCR_VA_Pos) /*!< 0x00003FFF */
12042 #define DSI_VVACCR_VA DSI_VVACCR_VA_Msk /*!< Vertical Active duration */
12043 #define DSI_VVACCR_VA0_Pos (0U)
12044 #define DSI_VVACCR_VA0_Msk (0x1UL << DSI_VVACCR_VA0_Pos) /*!< 0x00000001 */
12045 #define DSI_VVACCR_VA0 DSI_VVACCR_VA0_Msk
12046 #define DSI_VVACCR_VA1_Pos (1U)
12047 #define DSI_VVACCR_VA1_Msk (0x1UL << DSI_VVACCR_VA1_Pos) /*!< 0x00000002 */
12048 #define DSI_VVACCR_VA1 DSI_VVACCR_VA1_Msk
12049 #define DSI_VVACCR_VA2_Pos (2U)
12050 #define DSI_VVACCR_VA2_Msk (0x1UL << DSI_VVACCR_VA2_Pos) /*!< 0x00000004 */
12051 #define DSI_VVACCR_VA2 DSI_VVACCR_VA2_Msk
12052 #define DSI_VVACCR_VA3_Pos (3U)
12053 #define DSI_VVACCR_VA3_Msk (0x1UL << DSI_VVACCR_VA3_Pos) /*!< 0x00000008 */
12054 #define DSI_VVACCR_VA3 DSI_VVACCR_VA3_Msk
12055 #define DSI_VVACCR_VA4_Pos (4U)
12056 #define DSI_VVACCR_VA4_Msk (0x1UL << DSI_VVACCR_VA4_Pos) /*!< 0x00000010 */
12057 #define DSI_VVACCR_VA4 DSI_VVACCR_VA4_Msk
12058 #define DSI_VVACCR_VA5_Pos (5U)
12059 #define DSI_VVACCR_VA5_Msk (0x1UL << DSI_VVACCR_VA5_Pos) /*!< 0x00000020 */
12060 #define DSI_VVACCR_VA5 DSI_VVACCR_VA5_Msk
12061 #define DSI_VVACCR_VA6_Pos (6U)
12062 #define DSI_VVACCR_VA6_Msk (0x1UL << DSI_VVACCR_VA6_Pos) /*!< 0x00000040 */
12063 #define DSI_VVACCR_VA6 DSI_VVACCR_VA6_Msk
12064 #define DSI_VVACCR_VA7_Pos (7U)
12065 #define DSI_VVACCR_VA7_Msk (0x1UL << DSI_VVACCR_VA7_Pos) /*!< 0x00000080 */
12066 #define DSI_VVACCR_VA7 DSI_VVACCR_VA7_Msk
12067 #define DSI_VVACCR_VA8_Pos (8U)
12068 #define DSI_VVACCR_VA8_Msk (0x1UL << DSI_VVACCR_VA8_Pos) /*!< 0x00000100 */
12069 #define DSI_VVACCR_VA8 DSI_VVACCR_VA8_Msk
12070 #define DSI_VVACCR_VA9_Pos (9U)
12071 #define DSI_VVACCR_VA9_Msk (0x1UL << DSI_VVACCR_VA9_Pos) /*!< 0x00000200 */
12072 #define DSI_VVACCR_VA9 DSI_VVACCR_VA9_Msk
12073 #define DSI_VVACCR_VA10_Pos (10U)
12074 #define DSI_VVACCR_VA10_Msk (0x1UL << DSI_VVACCR_VA10_Pos) /*!< 0x00000400 */
12075 #define DSI_VVACCR_VA10 DSI_VVACCR_VA10_Msk
12076 #define DSI_VVACCR_VA11_Pos (11U)
12077 #define DSI_VVACCR_VA11_Msk (0x1UL << DSI_VVACCR_VA11_Pos) /*!< 0x00000800 */
12078 #define DSI_VVACCR_VA11 DSI_VVACCR_VA11_Msk
12079 #define DSI_VVACCR_VA12_Pos (12U)
12080 #define DSI_VVACCR_VA12_Msk (0x1UL << DSI_VVACCR_VA12_Pos) /*!< 0x00001000 */
12081 #define DSI_VVACCR_VA12 DSI_VVACCR_VA12_Msk
12082 #define DSI_VVACCR_VA13_Pos (13U)
12083 #define DSI_VVACCR_VA13_Msk (0x1UL << DSI_VVACCR_VA13_Pos) /*!< 0x00002000 */
12084 #define DSI_VVACCR_VA13 DSI_VVACCR_VA13_Msk
12085
12086 /******************* Bit definition for DSI_TDCCR register **************/
12087 #define DSI_TDCCR_3DM ((uint32_t)0x00000003U) /*!< 3D Mode */
12088 #define DSI_TDCCR_3DM0 ((uint32_t)0x00000001U)
12089 #define DSI_TDCCR_3DM1 ((uint32_t)0x00000002U)
12090
12091 #define DSI_TDCCR_3DF ((uint32_t)0x0000000CU) /*!< 3D Format */
12092 #define DSI_TDCCR_3DF0 ((uint32_t)0x00000004U)
12093 #define DSI_TDCCR_3DF1 ((uint32_t)0x00000008U)
12094
12095 #define DSI_TDCCR_SVS_Pos (4U)
12096 #define DSI_TDCCR_SVS_Msk (0x1UL << DSI_TDCCR_SVS_Pos) /*!< 0x00000010 */
12097 #define DSI_TDCCR_SVS DSI_TDCCR_SVS_Msk /*!< Second VSYNC */
12098 #define DSI_TDCCR_RF_Pos (5U)
12099 #define DSI_TDCCR_RF_Msk (0x1UL << DSI_TDCCR_RF_Pos) /*!< 0x00000020 */
12100 #define DSI_TDCCR_RF DSI_TDCCR_RF_Msk /*!< Right First */
12101 #define DSI_TDCCR_S3DC_Pos (16U)
12102 #define DSI_TDCCR_S3DC_Msk (0x1UL << DSI_TDCCR_S3DC_Pos) /*!< 0x00010000 */
12103 #define DSI_TDCCR_S3DC DSI_TDCCR_S3DC_Msk /*!< Send 3D Control */
12104
12105 /******************* Bit definition for DSI_WCFGR register ***************/
12106 #define DSI_WCFGR_DSIM_Pos (0U)
12107 #define DSI_WCFGR_DSIM_Msk (0x1UL << DSI_WCFGR_DSIM_Pos) /*!< 0x00000001 */
12108 #define DSI_WCFGR_DSIM DSI_WCFGR_DSIM_Msk /*!< DSI Mode */
12109 #define DSI_WCFGR_COLMUX_Pos (1U)
12110 #define DSI_WCFGR_COLMUX_Msk (0x7UL << DSI_WCFGR_COLMUX_Pos) /*!< 0x0000000E */
12111 #define DSI_WCFGR_COLMUX DSI_WCFGR_COLMUX_Msk /*!< Color Multiplexing */
12112 #define DSI_WCFGR_COLMUX0_Pos (1U)
12113 #define DSI_WCFGR_COLMUX0_Msk (0x1UL << DSI_WCFGR_COLMUX0_Pos) /*!< 0x00000002 */
12114 #define DSI_WCFGR_COLMUX0 DSI_WCFGR_COLMUX0_Msk
12115 #define DSI_WCFGR_COLMUX1_Pos (2U)
12116 #define DSI_WCFGR_COLMUX1_Msk (0x1UL << DSI_WCFGR_COLMUX1_Pos) /*!< 0x00000004 */
12117 #define DSI_WCFGR_COLMUX1 DSI_WCFGR_COLMUX1_Msk
12118 #define DSI_WCFGR_COLMUX2_Pos (3U)
12119 #define DSI_WCFGR_COLMUX2_Msk (0x1UL << DSI_WCFGR_COLMUX2_Pos) /*!< 0x00000008 */
12120 #define DSI_WCFGR_COLMUX2 DSI_WCFGR_COLMUX2_Msk
12121
12122 #define DSI_WCFGR_TESRC_Pos (4U)
12123 #define DSI_WCFGR_TESRC_Msk (0x1UL << DSI_WCFGR_TESRC_Pos) /*!< 0x00000010 */
12124 #define DSI_WCFGR_TESRC DSI_WCFGR_TESRC_Msk /*!< Tearing Effect Source */
12125 #define DSI_WCFGR_TEPOL_Pos (5U)
12126 #define DSI_WCFGR_TEPOL_Msk (0x1UL << DSI_WCFGR_TEPOL_Pos) /*!< 0x00000020 */
12127 #define DSI_WCFGR_TEPOL DSI_WCFGR_TEPOL_Msk /*!< Tearing Effect Polarity */
12128 #define DSI_WCFGR_AR_Pos (6U)
12129 #define DSI_WCFGR_AR_Msk (0x1UL << DSI_WCFGR_AR_Pos) /*!< 0x00000040 */
12130 #define DSI_WCFGR_AR DSI_WCFGR_AR_Msk /*!< Automatic Refresh */
12131 #define DSI_WCFGR_VSPOL_Pos (7U)
12132 #define DSI_WCFGR_VSPOL_Msk (0x1UL << DSI_WCFGR_VSPOL_Pos) /*!< 0x00000080 */
12133 #define DSI_WCFGR_VSPOL DSI_WCFGR_VSPOL_Msk /*!< VSync Polarity */
12134
12135 /******************* Bit definition for DSI_WCR register *****************/
12136 #define DSI_WCR_COLM_Pos (0U)
12137 #define DSI_WCR_COLM_Msk (0x1UL << DSI_WCR_COLM_Pos) /*!< 0x00000001 */
12138 #define DSI_WCR_COLM DSI_WCR_COLM_Msk /*!< Color Mode */
12139 #define DSI_WCR_SHTDN_Pos (1U)
12140 #define DSI_WCR_SHTDN_Msk (0x1UL << DSI_WCR_SHTDN_Pos) /*!< 0x00000002 */
12141 #define DSI_WCR_SHTDN DSI_WCR_SHTDN_Msk /*!< Shutdown */
12142 #define DSI_WCR_LTDCEN_Pos (2U)
12143 #define DSI_WCR_LTDCEN_Msk (0x1UL << DSI_WCR_LTDCEN_Pos) /*!< 0x00000004 */
12144 #define DSI_WCR_LTDCEN DSI_WCR_LTDCEN_Msk /*!< LTDC Enable */
12145 #define DSI_WCR_DSIEN_Pos (3U)
12146 #define DSI_WCR_DSIEN_Msk (0x1UL << DSI_WCR_DSIEN_Pos) /*!< 0x00000008 */
12147 #define DSI_WCR_DSIEN DSI_WCR_DSIEN_Msk /*!< DSI Enable */
12148
12149 /******************* Bit definition for DSI_WIER register ****************/
12150 #define DSI_WIER_TEIE_Pos (0U)
12151 #define DSI_WIER_TEIE_Msk (0x1UL << DSI_WIER_TEIE_Pos) /*!< 0x00000001 */
12152 #define DSI_WIER_TEIE DSI_WIER_TEIE_Msk /*!< Tearing Effect Interrupt Enable */
12153 #define DSI_WIER_ERIE_Pos (1U)
12154 #define DSI_WIER_ERIE_Msk (0x1UL << DSI_WIER_ERIE_Pos) /*!< 0x00000002 */
12155 #define DSI_WIER_ERIE DSI_WIER_ERIE_Msk /*!< End of Refresh Interrupt Enable */
12156 #define DSI_WIER_PLLLIE_Pos (9U)
12157 #define DSI_WIER_PLLLIE_Msk (0x1UL << DSI_WIER_PLLLIE_Pos) /*!< 0x00000200 */
12158 #define DSI_WIER_PLLLIE DSI_WIER_PLLLIE_Msk /*!< PLL Lock Interrupt Enable */
12159 #define DSI_WIER_PLLUIE_Pos (10U)
12160 #define DSI_WIER_PLLUIE_Msk (0x1UL << DSI_WIER_PLLUIE_Pos) /*!< 0x00000400 */
12161 #define DSI_WIER_PLLUIE DSI_WIER_PLLUIE_Msk /*!< PLL Unlock Interrupt Enable */
12162 #define DSI_WIER_RRIE_Pos (13U)
12163 #define DSI_WIER_RRIE_Msk (0x1UL << DSI_WIER_RRIE_Pos) /*!< 0x00002000 */
12164 #define DSI_WIER_RRIE DSI_WIER_RRIE_Msk /*!< Regulator Ready Interrupt Enable */
12165
12166 /******************* Bit definition for DSI_WISR register ****************/
12167 #define DSI_WISR_TEIF_Pos (0U)
12168 #define DSI_WISR_TEIF_Msk (0x1UL << DSI_WISR_TEIF_Pos) /*!< 0x00000001 */
12169 #define DSI_WISR_TEIF DSI_WISR_TEIF_Msk /*!< Tearing Effect Interrupt Flag */
12170 #define DSI_WISR_ERIF_Pos (1U)
12171 #define DSI_WISR_ERIF_Msk (0x1UL << DSI_WISR_ERIF_Pos) /*!< 0x00000002 */
12172 #define DSI_WISR_ERIF DSI_WISR_ERIF_Msk /*!< End of Refresh Interrupt Flag */
12173 #define DSI_WISR_BUSY_Pos (2U)
12174 #define DSI_WISR_BUSY_Msk (0x1UL << DSI_WISR_BUSY_Pos) /*!< 0x00000004 */
12175 #define DSI_WISR_BUSY DSI_WISR_BUSY_Msk /*!< Busy Flag */
12176 #define DSI_WISR_PLLLS_Pos (8U)
12177 #define DSI_WISR_PLLLS_Msk (0x1UL << DSI_WISR_PLLLS_Pos) /*!< 0x00000100 */
12178 #define DSI_WISR_PLLLS DSI_WISR_PLLLS_Msk /*!< PLL Lock Status */
12179 #define DSI_WISR_PLLLIF_Pos (9U)
12180 #define DSI_WISR_PLLLIF_Msk (0x1UL << DSI_WISR_PLLLIF_Pos) /*!< 0x00000200 */
12181 #define DSI_WISR_PLLLIF DSI_WISR_PLLLIF_Msk /*!< PLL Lock Interrupt Flag */
12182 #define DSI_WISR_PLLUIF_Pos (10U)
12183 #define DSI_WISR_PLLUIF_Msk (0x1UL << DSI_WISR_PLLUIF_Pos) /*!< 0x00000400 */
12184 #define DSI_WISR_PLLUIF DSI_WISR_PLLUIF_Msk /*!< PLL Unlock Interrupt Flag */
12185 #define DSI_WISR_RRS_Pos (12U)
12186 #define DSI_WISR_RRS_Msk (0x1UL << DSI_WISR_RRS_Pos) /*!< 0x00001000 */
12187 #define DSI_WISR_RRS DSI_WISR_RRS_Msk /*!< Regulator Ready Flag */
12188 #define DSI_WISR_RRIF_Pos (13U)
12189 #define DSI_WISR_RRIF_Msk (0x1UL << DSI_WISR_RRIF_Pos) /*!< 0x00002000 */
12190 #define DSI_WISR_RRIF DSI_WISR_RRIF_Msk /*!< Regulator Ready Interrupt Flag */
12191
12192 /******************* Bit definition for DSI_WIFCR register ***************/
12193 #define DSI_WIFCR_CTEIF_Pos (0U)
12194 #define DSI_WIFCR_CTEIF_Msk (0x1UL << DSI_WIFCR_CTEIF_Pos) /*!< 0x00000001 */
12195 #define DSI_WIFCR_CTEIF DSI_WIFCR_CTEIF_Msk /*!< Clear Tearing Effect Interrupt Flag */
12196 #define DSI_WIFCR_CERIF_Pos (1U)
12197 #define DSI_WIFCR_CERIF_Msk (0x1UL << DSI_WIFCR_CERIF_Pos) /*!< 0x00000002 */
12198 #define DSI_WIFCR_CERIF DSI_WIFCR_CERIF_Msk /*!< Clear End of Refresh Interrupt Flag */
12199 #define DSI_WIFCR_CPLLLIF_Pos (9U)
12200 #define DSI_WIFCR_CPLLLIF_Msk (0x1UL << DSI_WIFCR_CPLLLIF_Pos) /*!< 0x00000200 */
12201 #define DSI_WIFCR_CPLLLIF DSI_WIFCR_CPLLLIF_Msk /*!< Clear PLL Lock Interrupt Flag */
12202 #define DSI_WIFCR_CPLLUIF_Pos (10U)
12203 #define DSI_WIFCR_CPLLUIF_Msk (0x1UL << DSI_WIFCR_CPLLUIF_Pos) /*!< 0x00000400 */
12204 #define DSI_WIFCR_CPLLUIF DSI_WIFCR_CPLLUIF_Msk /*!< Clear PLL Unlock Interrupt Flag */
12205 #define DSI_WIFCR_CRRIF_Pos (13U)
12206 #define DSI_WIFCR_CRRIF_Msk (0x1UL << DSI_WIFCR_CRRIF_Pos) /*!< 0x00002000 */
12207 #define DSI_WIFCR_CRRIF DSI_WIFCR_CRRIF_Msk /*!< Clear Regulator Ready Interrupt Flag */
12208
12209 /******************* Bit definition for DSI_WPCR0 register ***************/
12210 #define DSI_WPCR0_UIX4_Pos (0U)
12211 #define DSI_WPCR0_UIX4_Msk (0x3FUL << DSI_WPCR0_UIX4_Pos) /*!< 0x0000003F */
12212 #define DSI_WPCR0_UIX4 DSI_WPCR0_UIX4_Msk /*!< Unit Interval multiplied by 4 */
12213 #define DSI_WPCR0_UIX4_0 (0x01UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000001 */
12214 #define DSI_WPCR0_UIX4_1 (0x02UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000002 */
12215 #define DSI_WPCR0_UIX4_2 (0x04UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000004 */
12216 #define DSI_WPCR0_UIX4_3 (0x08UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000008 */
12217 #define DSI_WPCR0_UIX4_4 (0x10UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000010 */
12218 #define DSI_WPCR0_UIX4_5 (0x20UL << DSI_WPCR0_UIX4_Pos) /*!< 0x00000020 */
12219
12220 #define DSI_WPCR0_SWCL_Pos (6U)
12221 #define DSI_WPCR0_SWCL_Msk (0x1UL << DSI_WPCR0_SWCL_Pos) /*!< 0x00000040 */
12222 #define DSI_WPCR0_SWCL DSI_WPCR0_SWCL_Msk /*!< Swap pins on clock lane */
12223 #define DSI_WPCR0_SWDL0_Pos (7U)
12224 #define DSI_WPCR0_SWDL0_Msk (0x1UL << DSI_WPCR0_SWDL0_Pos) /*!< 0x00000080 */
12225 #define DSI_WPCR0_SWDL0 DSI_WPCR0_SWDL0_Msk /*!< Swap pins on data lane 1 */
12226 #define DSI_WPCR0_SWDL1_Pos (8U)
12227 #define DSI_WPCR0_SWDL1_Msk (0x1UL << DSI_WPCR0_SWDL1_Pos) /*!< 0x00000100 */
12228 #define DSI_WPCR0_SWDL1 DSI_WPCR0_SWDL1_Msk /*!< Swap pins on data lane 2 */
12229 #define DSI_WPCR0_HSICL_Pos (9U)
12230 #define DSI_WPCR0_HSICL_Msk (0x1UL << DSI_WPCR0_HSICL_Pos) /*!< 0x00000200 */
12231 #define DSI_WPCR0_HSICL DSI_WPCR0_HSICL_Msk /*!< Invert the high-speed data signal on clock lane */
12232 #define DSI_WPCR0_HSIDL0_Pos (10U)
12233 #define DSI_WPCR0_HSIDL0_Msk (0x1UL << DSI_WPCR0_HSIDL0_Pos) /*!< 0x00000400 */
12234 #define DSI_WPCR0_HSIDL0 DSI_WPCR0_HSIDL0_Msk /*!< Invert the high-speed data signal on lane 1 */
12235 #define DSI_WPCR0_HSIDL1_Pos (11U)
12236 #define DSI_WPCR0_HSIDL1_Msk (0x1UL << DSI_WPCR0_HSIDL1_Pos) /*!< 0x00000800 */
12237 #define DSI_WPCR0_HSIDL1 DSI_WPCR0_HSIDL1_Msk /*!< Invert the high-speed data signal on lane 2 */
12238 #define DSI_WPCR0_FTXSMCL_Pos (12U)
12239 #define DSI_WPCR0_FTXSMCL_Msk (0x1UL << DSI_WPCR0_FTXSMCL_Pos) /*!< 0x00001000 */
12240 #define DSI_WPCR0_FTXSMCL DSI_WPCR0_FTXSMCL_Msk /*!< Force clock lane in TX stop mode */
12241 #define DSI_WPCR0_FTXSMDL_Pos (13U)
12242 #define DSI_WPCR0_FTXSMDL_Msk (0x1UL << DSI_WPCR0_FTXSMDL_Pos) /*!< 0x00002000 */
12243 #define DSI_WPCR0_FTXSMDL DSI_WPCR0_FTXSMDL_Msk /*!< Force data lanes in TX stop mode */
12244 #define DSI_WPCR0_CDOFFDL_Pos (14U)
12245 #define DSI_WPCR0_CDOFFDL_Msk (0x1UL << DSI_WPCR0_CDOFFDL_Pos) /*!< 0x00004000 */
12246 #define DSI_WPCR0_CDOFFDL DSI_WPCR0_CDOFFDL_Msk /*!< Contention detection OFF */
12247 #define DSI_WPCR0_TDDL_Pos (16U)
12248 #define DSI_WPCR0_TDDL_Msk (0x1UL << DSI_WPCR0_TDDL_Pos) /*!< 0x00010000 */
12249 #define DSI_WPCR0_TDDL DSI_WPCR0_TDDL_Msk /*!< Turn Disable Data Lanes */
12250 #define DSI_WPCR0_PDEN_Pos (18U)
12251 #define DSI_WPCR0_PDEN_Msk (0x1UL << DSI_WPCR0_PDEN_Pos) /*!< 0x00040000 */
12252 #define DSI_WPCR0_PDEN DSI_WPCR0_PDEN_Msk /*!< Pull-Down Enable */
12253 #define DSI_WPCR0_TCLKPREPEN_Pos (19U)
12254 #define DSI_WPCR0_TCLKPREPEN_Msk (0x1UL << DSI_WPCR0_TCLKPREPEN_Pos) /*!< 0x00080000 */
12255 #define DSI_WPCR0_TCLKPREPEN DSI_WPCR0_TCLKPREPEN_Msk /*!< Timer for t-CLKPREP Enable */
12256 #define DSI_WPCR0_TCLKZEROEN_Pos (20U)
12257 #define DSI_WPCR0_TCLKZEROEN_Msk (0x1UL << DSI_WPCR0_TCLKZEROEN_Pos) /*!< 0x00100000 */
12258 #define DSI_WPCR0_TCLKZEROEN DSI_WPCR0_TCLKZEROEN_Msk /*!< Timer for t-CLKZERO Enable */
12259 #define DSI_WPCR0_THSPREPEN_Pos (21U)
12260 #define DSI_WPCR0_THSPREPEN_Msk (0x1UL << DSI_WPCR0_THSPREPEN_Pos) /*!< 0x00200000 */
12261 #define DSI_WPCR0_THSPREPEN DSI_WPCR0_THSPREPEN_Msk /*!< Timer for t-HSPREP Enable */
12262 #define DSI_WPCR0_THSTRAILEN_Pos (22U)
12263 #define DSI_WPCR0_THSTRAILEN_Msk (0x1UL << DSI_WPCR0_THSTRAILEN_Pos) /*!< 0x00400000 */
12264 #define DSI_WPCR0_THSTRAILEN DSI_WPCR0_THSTRAILEN_Msk /*!< Timer for t-HSTRAIL Enable */
12265 #define DSI_WPCR0_THSZEROEN_Pos (23U)
12266 #define DSI_WPCR0_THSZEROEN_Msk (0x1UL << DSI_WPCR0_THSZEROEN_Pos) /*!< 0x00800000 */
12267 #define DSI_WPCR0_THSZEROEN DSI_WPCR0_THSZEROEN_Msk /*!< Timer for t-HSZERO Enable */
12268 #define DSI_WPCR0_TLPXDEN_Pos (24U)
12269 #define DSI_WPCR0_TLPXDEN_Msk (0x1UL << DSI_WPCR0_TLPXDEN_Pos) /*!< 0x01000000 */
12270 #define DSI_WPCR0_TLPXDEN DSI_WPCR0_TLPXDEN_Msk /*!< Timer for t-LPXD Enable */
12271 #define DSI_WPCR0_THSEXITEN_Pos (25U)
12272 #define DSI_WPCR0_THSEXITEN_Msk (0x1UL << DSI_WPCR0_THSEXITEN_Pos) /*!< 0x02000000 */
12273 #define DSI_WPCR0_THSEXITEN DSI_WPCR0_THSEXITEN_Msk /*!< Timer for t-HSEXIT Enable */
12274 #define DSI_WPCR0_TLPXCEN_Pos (26U)
12275 #define DSI_WPCR0_TLPXCEN_Msk (0x1UL << DSI_WPCR0_TLPXCEN_Pos) /*!< 0x04000000 */
12276 #define DSI_WPCR0_TLPXCEN DSI_WPCR0_TLPXCEN_Msk /*!< Timer for t-LPXC Enable */
12277 #define DSI_WPCR0_TCLKPOSTEN_Pos (27U)
12278 #define DSI_WPCR0_TCLKPOSTEN_Msk (0x1UL << DSI_WPCR0_TCLKPOSTEN_Pos) /*!< 0x08000000 */
12279 #define DSI_WPCR0_TCLKPOSTEN DSI_WPCR0_TCLKPOSTEN_Msk /*!< Timer for t-CLKPOST Enable */
12280
12281 /******************* Bit definition for DSI_WPCR1 register ***************/
12282 #define DSI_WPCR1_HSTXDCL_Pos (0U)
12283 #define DSI_WPCR1_HSTXDCL_Msk (0x3UL << DSI_WPCR1_HSTXDCL_Pos) /*!< 0x00000003 */
12284 #define DSI_WPCR1_HSTXDCL DSI_WPCR1_HSTXDCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
12285 #define DSI_WPCR1_HSTXDCL0_Pos (0U)
12286 #define DSI_WPCR1_HSTXDCL0_Msk (0x1UL << DSI_WPCR1_HSTXDCL0_Pos) /*!< 0x00000001 */
12287 #define DSI_WPCR1_HSTXDCL0 DSI_WPCR1_HSTXDCL0_Msk
12288 #define DSI_WPCR1_HSTXDCL1_Pos (1U)
12289 #define DSI_WPCR1_HSTXDCL1_Msk (0x1UL << DSI_WPCR1_HSTXDCL1_Pos) /*!< 0x00000002 */
12290 #define DSI_WPCR1_HSTXDCL1 DSI_WPCR1_HSTXDCL1_Msk
12291
12292 #define DSI_WPCR1_HSTXDDL_Pos (2U)
12293 #define DSI_WPCR1_HSTXDDL_Msk (0x3UL << DSI_WPCR1_HSTXDDL_Pos) /*!< 0x0000000C */
12294 #define DSI_WPCR1_HSTXDDL DSI_WPCR1_HSTXDDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
12295 #define DSI_WPCR1_HSTXDDL0_Pos (2U)
12296 #define DSI_WPCR1_HSTXDDL0_Msk (0x1UL << DSI_WPCR1_HSTXDDL0_Pos) /*!< 0x00000004 */
12297 #define DSI_WPCR1_HSTXDDL0 DSI_WPCR1_HSTXDDL0_Msk
12298 #define DSI_WPCR1_HSTXDDL1_Pos (3U)
12299 #define DSI_WPCR1_HSTXDDL1_Msk (0x1UL << DSI_WPCR1_HSTXDDL1_Pos) /*!< 0x00000008 */
12300 #define DSI_WPCR1_HSTXDDL1 DSI_WPCR1_HSTXDDL1_Msk
12301
12302 #define DSI_WPCR1_LPSRCCL_Pos (6U)
12303 #define DSI_WPCR1_LPSRCCL_Msk (0x3UL << DSI_WPCR1_LPSRCCL_Pos) /*!< 0x000000C0 */
12304 #define DSI_WPCR1_LPSRCCL DSI_WPCR1_LPSRCCL_Msk /*!< Low-Power transmission Slew Rate Compensation on Clock Lane */
12305 #define DSI_WPCR1_LPSRCCL0_Pos (6U)
12306 #define DSI_WPCR1_LPSRCCL0_Msk (0x1UL << DSI_WPCR1_LPSRCCL0_Pos) /*!< 0x00000040 */
12307 #define DSI_WPCR1_LPSRCCL0 DSI_WPCR1_LPSRCCL0_Msk
12308 #define DSI_WPCR1_LPSRCCL1_Pos (7U)
12309 #define DSI_WPCR1_LPSRCCL1_Msk (0x1UL << DSI_WPCR1_LPSRCCL1_Pos) /*!< 0x00000080 */
12310 #define DSI_WPCR1_LPSRCCL1 DSI_WPCR1_LPSRCCL1_Msk
12311
12312 #define DSI_WPCR1_LPSRCDL_Pos (8U)
12313 #define DSI_WPCR1_LPSRCDL_Msk (0x3UL << DSI_WPCR1_LPSRCDL_Pos) /*!< 0x00000300 */
12314 #define DSI_WPCR1_LPSRCDL DSI_WPCR1_LPSRCDL_Msk /*!< Low-Power transmission Slew Rate Compensation on Data Lane */
12315 #define DSI_WPCR1_LPSRCDL0_Pos (8U)
12316 #define DSI_WPCR1_LPSRCDL0_Msk (0x1UL << DSI_WPCR1_LPSRCDL0_Pos) /*!< 0x00000100 */
12317 #define DSI_WPCR1_LPSRCDL0 DSI_WPCR1_LPSRCDL0_Msk
12318 #define DSI_WPCR1_LPSRCDL1_Pos (9U)
12319 #define DSI_WPCR1_LPSRCDL1_Msk (0x1UL << DSI_WPCR1_LPSRCDL1_Pos) /*!< 0x00000200 */
12320 #define DSI_WPCR1_LPSRCDL1 DSI_WPCR1_LPSRCDL1_Msk
12321
12322 #define DSI_WPCR1_SDDC_Pos (12U)
12323 #define DSI_WPCR1_SDDC_Msk (0x1UL << DSI_WPCR1_SDDC_Pos) /*!< 0x00001000 */
12324 #define DSI_WPCR1_SDDC DSI_WPCR1_SDDC_Msk /*!< SDD Control */
12325
12326 #define DSI_WPCR1_LPRXVCDL_Pos (14U)
12327 #define DSI_WPCR1_LPRXVCDL_Msk (0x3UL << DSI_WPCR1_LPRXVCDL_Pos) /*!< 0x0000C000 */
12328 #define DSI_WPCR1_LPRXVCDL DSI_WPCR1_LPRXVCDL_Msk /*!< Low-Power Reception V-IL Compensation on Data Lanes */
12329 #define DSI_WPCR1_LPRXVCDL0_Pos (14U)
12330 #define DSI_WPCR1_LPRXVCDL0_Msk (0x1UL << DSI_WPCR1_LPRXVCDL0_Pos) /*!< 0x00004000 */
12331 #define DSI_WPCR1_LPRXVCDL0 DSI_WPCR1_LPRXVCDL0_Msk
12332 #define DSI_WPCR1_LPRXVCDL1_Pos (15U)
12333 #define DSI_WPCR1_LPRXVCDL1_Msk (0x1UL << DSI_WPCR1_LPRXVCDL1_Pos) /*!< 0x00008000 */
12334 #define DSI_WPCR1_LPRXVCDL1 DSI_WPCR1_LPRXVCDL1_Msk
12335
12336 #define DSI_WPCR1_HSTXSRCCL_Pos (16U)
12337 #define DSI_WPCR1_HSTXSRCCL_Msk (0x3UL << DSI_WPCR1_HSTXSRCCL_Pos) /*!< 0x00030000 */
12338 #define DSI_WPCR1_HSTXSRCCL DSI_WPCR1_HSTXSRCCL_Msk /*!< High-Speed Transmission Delay on Clock Lane */
12339 #define DSI_WPCR1_HSTXSRCCL0_Pos (16U)
12340 #define DSI_WPCR1_HSTXSRCCL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL0_Pos) /*!< 0x00010000 */
12341 #define DSI_WPCR1_HSTXSRCCL0 DSI_WPCR1_HSTXSRCCL0_Msk
12342 #define DSI_WPCR1_HSTXSRCCL1_Pos (17U)
12343 #define DSI_WPCR1_HSTXSRCCL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCCL1_Pos) /*!< 0x00020000 */
12344 #define DSI_WPCR1_HSTXSRCCL1 DSI_WPCR1_HSTXSRCCL1_Msk
12345
12346 #define DSI_WPCR1_HSTXSRCDL_Pos (18U)
12347 #define DSI_WPCR1_HSTXSRCDL_Msk (0x3UL << DSI_WPCR1_HSTXSRCDL_Pos) /*!< 0x000C0000 */
12348 #define DSI_WPCR1_HSTXSRCDL DSI_WPCR1_HSTXSRCDL_Msk /*!< High-Speed Transmission Delay on Data Lane */
12349 #define DSI_WPCR1_HSTXSRCDL0_Pos (18U)
12350 #define DSI_WPCR1_HSTXSRCDL0_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL0_Pos) /*!< 0x00040000 */
12351 #define DSI_WPCR1_HSTXSRCDL0 DSI_WPCR1_HSTXSRCDL0_Msk
12352 #define DSI_WPCR1_HSTXSRCDL1_Pos (19U)
12353 #define DSI_WPCR1_HSTXSRCDL1_Msk (0x1UL << DSI_WPCR1_HSTXSRCDL1_Pos) /*!< 0x00080000 */
12354 #define DSI_WPCR1_HSTXSRCDL1 DSI_WPCR1_HSTXSRCDL1_Msk
12355
12356 #define DSI_WPCR1_FLPRXLPM_Pos (22U)
12357 #define DSI_WPCR1_FLPRXLPM_Msk (0x1UL << DSI_WPCR1_FLPRXLPM_Pos) /*!< 0x00400000 */
12358 #define DSI_WPCR1_FLPRXLPM DSI_WPCR1_FLPRXLPM_Msk /*!< Forces LP Receiver in Low-Power Mode */
12359
12360 #define DSI_WPCR1_LPRXFT_Pos (25U)
12361 #define DSI_WPCR1_LPRXFT_Msk (0x3UL << DSI_WPCR1_LPRXFT_Pos) /*!< 0x06000000 */
12362 #define DSI_WPCR1_LPRXFT DSI_WPCR1_LPRXFT_Msk /*!< Low-Power RX low-pass Filtering Tuning */
12363 #define DSI_WPCR1_LPRXFT0_Pos (25U)
12364 #define DSI_WPCR1_LPRXFT0_Msk (0x1UL << DSI_WPCR1_LPRXFT0_Pos) /*!< 0x02000000 */
12365 #define DSI_WPCR1_LPRXFT0 DSI_WPCR1_LPRXFT0_Msk
12366 #define DSI_WPCR1_LPRXFT1_Pos (26U)
12367 #define DSI_WPCR1_LPRXFT1_Msk (0x1UL << DSI_WPCR1_LPRXFT1_Pos) /*!< 0x04000000 */
12368 #define DSI_WPCR1_LPRXFT1 DSI_WPCR1_LPRXFT1_Msk
12369
12370 /******************* Bit definition for DSI_WPCR2 register ***************/
12371 #define DSI_WPCR2_TCLKPREP_Pos (0U)
12372 #define DSI_WPCR2_TCLKPREP_Msk (0xFFUL << DSI_WPCR2_TCLKPREP_Pos) /*!< 0x000000FF */
12373 #define DSI_WPCR2_TCLKPREP DSI_WPCR2_TCLKPREP_Msk /*!< t-CLKPREP */
12374 #define DSI_WPCR2_TCLKPREP0_Pos (0U)
12375 #define DSI_WPCR2_TCLKPREP0_Msk (0x1UL << DSI_WPCR2_TCLKPREP0_Pos) /*!< 0x00000001 */
12376 #define DSI_WPCR2_TCLKPREP0 DSI_WPCR2_TCLKPREP0_Msk
12377 #define DSI_WPCR2_TCLKPREP1_Pos (1U)
12378 #define DSI_WPCR2_TCLKPREP1_Msk (0x1UL << DSI_WPCR2_TCLKPREP1_Pos) /*!< 0x00000002 */
12379 #define DSI_WPCR2_TCLKPREP1 DSI_WPCR2_TCLKPREP1_Msk
12380 #define DSI_WPCR2_TCLKPREP2_Pos (2U)
12381 #define DSI_WPCR2_TCLKPREP2_Msk (0x1UL << DSI_WPCR2_TCLKPREP2_Pos) /*!< 0x00000004 */
12382 #define DSI_WPCR2_TCLKPREP2 DSI_WPCR2_TCLKPREP2_Msk
12383 #define DSI_WPCR2_TCLKPREP3_Pos (3U)
12384 #define DSI_WPCR2_TCLKPREP3_Msk (0x1UL << DSI_WPCR2_TCLKPREP3_Pos) /*!< 0x00000008 */
12385 #define DSI_WPCR2_TCLKPREP3 DSI_WPCR2_TCLKPREP3_Msk
12386 #define DSI_WPCR2_TCLKPREP4_Pos (4U)
12387 #define DSI_WPCR2_TCLKPREP4_Msk (0x1UL << DSI_WPCR2_TCLKPREP4_Pos) /*!< 0x00000010 */
12388 #define DSI_WPCR2_TCLKPREP4 DSI_WPCR2_TCLKPREP4_Msk
12389 #define DSI_WPCR2_TCLKPREP5_Pos (5U)
12390 #define DSI_WPCR2_TCLKPREP5_Msk (0x1UL << DSI_WPCR2_TCLKPREP5_Pos) /*!< 0x00000020 */
12391 #define DSI_WPCR2_TCLKPREP5 DSI_WPCR2_TCLKPREP5_Msk
12392 #define DSI_WPCR2_TCLKPREP6_Pos (6U)
12393 #define DSI_WPCR2_TCLKPREP6_Msk (0x1UL << DSI_WPCR2_TCLKPREP6_Pos) /*!< 0x00000040 */
12394 #define DSI_WPCR2_TCLKPREP6 DSI_WPCR2_TCLKPREP6_Msk
12395 #define DSI_WPCR2_TCLKPREP7_Pos (7U)
12396 #define DSI_WPCR2_TCLKPREP7_Msk (0x1UL << DSI_WPCR2_TCLKPREP7_Pos) /*!< 0x00000080 */
12397 #define DSI_WPCR2_TCLKPREP7 DSI_WPCR2_TCLKPREP7_Msk
12398
12399 #define DSI_WPCR2_TCLKZERO_Pos (8U)
12400 #define DSI_WPCR2_TCLKZERO_Msk (0xFFUL << DSI_WPCR2_TCLKZERO_Pos) /*!< 0x0000FF00 */
12401 #define DSI_WPCR2_TCLKZERO DSI_WPCR2_TCLKZERO_Msk /*!< t-CLKZERO */
12402 #define DSI_WPCR2_TCLKZERO0_Pos (8U)
12403 #define DSI_WPCR2_TCLKZERO0_Msk (0x1UL << DSI_WPCR2_TCLKZERO0_Pos) /*!< 0x00000100 */
12404 #define DSI_WPCR2_TCLKZERO0 DSI_WPCR2_TCLKZERO0_Msk
12405 #define DSI_WPCR2_TCLKZERO1_Pos (9U)
12406 #define DSI_WPCR2_TCLKZERO1_Msk (0x1UL << DSI_WPCR2_TCLKZERO1_Pos) /*!< 0x00000200 */
12407 #define DSI_WPCR2_TCLKZERO1 DSI_WPCR2_TCLKZERO1_Msk
12408 #define DSI_WPCR2_TCLKZERO2_Pos (10U)
12409 #define DSI_WPCR2_TCLKZERO2_Msk (0x1UL << DSI_WPCR2_TCLKZERO2_Pos) /*!< 0x00000400 */
12410 #define DSI_WPCR2_TCLKZERO2 DSI_WPCR2_TCLKZERO2_Msk
12411 #define DSI_WPCR2_TCLKZERO3_Pos (11U)
12412 #define DSI_WPCR2_TCLKZERO3_Msk (0x1UL << DSI_WPCR2_TCLKZERO3_Pos) /*!< 0x00000800 */
12413 #define DSI_WPCR2_TCLKZERO3 DSI_WPCR2_TCLKZERO3_Msk
12414 #define DSI_WPCR2_TCLKZERO4_Pos (12U)
12415 #define DSI_WPCR2_TCLKZERO4_Msk (0x1UL << DSI_WPCR2_TCLKZERO4_Pos) /*!< 0x00001000 */
12416 #define DSI_WPCR2_TCLKZERO4 DSI_WPCR2_TCLKZERO4_Msk
12417 #define DSI_WPCR2_TCLKZERO5_Pos (13U)
12418 #define DSI_WPCR2_TCLKZERO5_Msk (0x1UL << DSI_WPCR2_TCLKZERO5_Pos) /*!< 0x00002000 */
12419 #define DSI_WPCR2_TCLKZERO5 DSI_WPCR2_TCLKZERO5_Msk
12420 #define DSI_WPCR2_TCLKZERO6_Pos (14U)
12421 #define DSI_WPCR2_TCLKZERO6_Msk (0x1UL << DSI_WPCR2_TCLKZERO6_Pos) /*!< 0x00004000 */
12422 #define DSI_WPCR2_TCLKZERO6 DSI_WPCR2_TCLKZERO6_Msk
12423 #define DSI_WPCR2_TCLKZERO7_Pos (15U)
12424 #define DSI_WPCR2_TCLKZERO7_Msk (0x1UL << DSI_WPCR2_TCLKZERO7_Pos) /*!< 0x00008000 */
12425 #define DSI_WPCR2_TCLKZERO7 DSI_WPCR2_TCLKZERO7_Msk
12426
12427 #define DSI_WPCR2_THSPREP_Pos (16U)
12428 #define DSI_WPCR2_THSPREP_Msk (0xFFUL << DSI_WPCR2_THSPREP_Pos) /*!< 0x00FF0000 */
12429 #define DSI_WPCR2_THSPREP DSI_WPCR2_THSPREP_Msk /*!< t-HSPREP */
12430 #define DSI_WPCR2_THSPREP0_Pos (16U)
12431 #define DSI_WPCR2_THSPREP0_Msk (0x1UL << DSI_WPCR2_THSPREP0_Pos) /*!< 0x00010000 */
12432 #define DSI_WPCR2_THSPREP0 DSI_WPCR2_THSPREP0_Msk
12433 #define DSI_WPCR2_THSPREP1_Pos (17U)
12434 #define DSI_WPCR2_THSPREP1_Msk (0x1UL << DSI_WPCR2_THSPREP1_Pos) /*!< 0x00020000 */
12435 #define DSI_WPCR2_THSPREP1 DSI_WPCR2_THSPREP1_Msk
12436 #define DSI_WPCR2_THSPREP2_Pos (18U)
12437 #define DSI_WPCR2_THSPREP2_Msk (0x1UL << DSI_WPCR2_THSPREP2_Pos) /*!< 0x00040000 */
12438 #define DSI_WPCR2_THSPREP2 DSI_WPCR2_THSPREP2_Msk
12439 #define DSI_WPCR2_THSPREP3_Pos (19U)
12440 #define DSI_WPCR2_THSPREP3_Msk (0x1UL << DSI_WPCR2_THSPREP3_Pos) /*!< 0x00080000 */
12441 #define DSI_WPCR2_THSPREP3 DSI_WPCR2_THSPREP3_Msk
12442 #define DSI_WPCR2_THSPREP4_Pos (20U)
12443 #define DSI_WPCR2_THSPREP4_Msk (0x1UL << DSI_WPCR2_THSPREP4_Pos) /*!< 0x00100000 */
12444 #define DSI_WPCR2_THSPREP4 DSI_WPCR2_THSPREP4_Msk
12445 #define DSI_WPCR2_THSPREP5_Pos (21U)
12446 #define DSI_WPCR2_THSPREP5_Msk (0x1UL << DSI_WPCR2_THSPREP5_Pos) /*!< 0x00200000 */
12447 #define DSI_WPCR2_THSPREP5 DSI_WPCR2_THSPREP5_Msk
12448 #define DSI_WPCR2_THSPREP6_Pos (22U)
12449 #define DSI_WPCR2_THSPREP6_Msk (0x1UL << DSI_WPCR2_THSPREP6_Pos) /*!< 0x00400000 */
12450 #define DSI_WPCR2_THSPREP6 DSI_WPCR2_THSPREP6_Msk
12451 #define DSI_WPCR2_THSPREP7_Pos (23U)
12452 #define DSI_WPCR2_THSPREP7_Msk (0x1UL << DSI_WPCR2_THSPREP7_Pos) /*!< 0x00800000 */
12453 #define DSI_WPCR2_THSPREP7 DSI_WPCR2_THSPREP7_Msk
12454
12455 #define DSI_WPCR2_THSTRAIL_Pos (24U)
12456 #define DSI_WPCR2_THSTRAIL_Msk (0xFFUL << DSI_WPCR2_THSTRAIL_Pos) /*!< 0xFF000000 */
12457 #define DSI_WPCR2_THSTRAIL DSI_WPCR2_THSTRAIL_Msk /*!< t-HSTRAIL */
12458 #define DSI_WPCR2_THSTRAIL0_Pos (24U)
12459 #define DSI_WPCR2_THSTRAIL0_Msk (0x1UL << DSI_WPCR2_THSTRAIL0_Pos) /*!< 0x01000000 */
12460 #define DSI_WPCR2_THSTRAIL0 DSI_WPCR2_THSTRAIL0_Msk
12461 #define DSI_WPCR2_THSTRAIL1_Pos (25U)
12462 #define DSI_WPCR2_THSTRAIL1_Msk (0x1UL << DSI_WPCR2_THSTRAIL1_Pos) /*!< 0x02000000 */
12463 #define DSI_WPCR2_THSTRAIL1 DSI_WPCR2_THSTRAIL1_Msk
12464 #define DSI_WPCR2_THSTRAIL2_Pos (26U)
12465 #define DSI_WPCR2_THSTRAIL2_Msk (0x1UL << DSI_WPCR2_THSTRAIL2_Pos) /*!< 0x04000000 */
12466 #define DSI_WPCR2_THSTRAIL2 DSI_WPCR2_THSTRAIL2_Msk
12467 #define DSI_WPCR2_THSTRAIL3_Pos (27U)
12468 #define DSI_WPCR2_THSTRAIL3_Msk (0x1UL << DSI_WPCR2_THSTRAIL3_Pos) /*!< 0x08000000 */
12469 #define DSI_WPCR2_THSTRAIL3 DSI_WPCR2_THSTRAIL3_Msk
12470 #define DSI_WPCR2_THSTRAIL4_Pos (28U)
12471 #define DSI_WPCR2_THSTRAIL4_Msk (0x1UL << DSI_WPCR2_THSTRAIL4_Pos) /*!< 0x10000000 */
12472 #define DSI_WPCR2_THSTRAIL4 DSI_WPCR2_THSTRAIL4_Msk
12473 #define DSI_WPCR2_THSTRAIL5_Pos (29U)
12474 #define DSI_WPCR2_THSTRAIL5_Msk (0x1UL << DSI_WPCR2_THSTRAIL5_Pos) /*!< 0x20000000 */
12475 #define DSI_WPCR2_THSTRAIL5 DSI_WPCR2_THSTRAIL5_Msk
12476 #define DSI_WPCR2_THSTRAIL6_Pos (30U)
12477 #define DSI_WPCR2_THSTRAIL6_Msk (0x1UL << DSI_WPCR2_THSTRAIL6_Pos) /*!< 0x40000000 */
12478 #define DSI_WPCR2_THSTRAIL6 DSI_WPCR2_THSTRAIL6_Msk
12479 #define DSI_WPCR2_THSTRAIL7_Pos (31U)
12480 #define DSI_WPCR2_THSTRAIL7_Msk (0x1UL << DSI_WPCR2_THSTRAIL7_Pos) /*!< 0x80000000 */
12481 #define DSI_WPCR2_THSTRAIL7 DSI_WPCR2_THSTRAIL7_Msk
12482
12483 /******************* Bit definition for DSI_WPCR3 register ***************/
12484 #define DSI_WPCR3_THSZERO_Pos (0U)
12485 #define DSI_WPCR3_THSZERO_Msk (0xFFUL << DSI_WPCR3_THSZERO_Pos) /*!< 0x000000FF */
12486 #define DSI_WPCR3_THSZERO DSI_WPCR3_THSZERO_Msk /*!< t-HSZERO */
12487 #define DSI_WPCR3_THSZERO0_Pos (0U)
12488 #define DSI_WPCR3_THSZERO0_Msk (0x1UL << DSI_WPCR3_THSZERO0_Pos) /*!< 0x00000001 */
12489 #define DSI_WPCR3_THSZERO0 DSI_WPCR3_THSZERO0_Msk
12490 #define DSI_WPCR3_THSZERO1_Pos (1U)
12491 #define DSI_WPCR3_THSZERO1_Msk (0x1UL << DSI_WPCR3_THSZERO1_Pos) /*!< 0x00000002 */
12492 #define DSI_WPCR3_THSZERO1 DSI_WPCR3_THSZERO1_Msk
12493 #define DSI_WPCR3_THSZERO2_Pos (2U)
12494 #define DSI_WPCR3_THSZERO2_Msk (0x1UL << DSI_WPCR3_THSZERO2_Pos) /*!< 0x00000004 */
12495 #define DSI_WPCR3_THSZERO2 DSI_WPCR3_THSZERO2_Msk
12496 #define DSI_WPCR3_THSZERO3_Pos (3U)
12497 #define DSI_WPCR3_THSZERO3_Msk (0x1UL << DSI_WPCR3_THSZERO3_Pos) /*!< 0x00000008 */
12498 #define DSI_WPCR3_THSZERO3 DSI_WPCR3_THSZERO3_Msk
12499 #define DSI_WPCR3_THSZERO4_Pos (4U)
12500 #define DSI_WPCR3_THSZERO4_Msk (0x1UL << DSI_WPCR3_THSZERO4_Pos) /*!< 0x00000010 */
12501 #define DSI_WPCR3_THSZERO4 DSI_WPCR3_THSZERO4_Msk
12502 #define DSI_WPCR3_THSZERO5_Pos (5U)
12503 #define DSI_WPCR3_THSZERO5_Msk (0x1UL << DSI_WPCR3_THSZERO5_Pos) /*!< 0x00000020 */
12504 #define DSI_WPCR3_THSZERO5 DSI_WPCR3_THSZERO5_Msk
12505 #define DSI_WPCR3_THSZERO6_Pos (6U)
12506 #define DSI_WPCR3_THSZERO6_Msk (0x1UL << DSI_WPCR3_THSZERO6_Pos) /*!< 0x00000040 */
12507 #define DSI_WPCR3_THSZERO6 DSI_WPCR3_THSZERO6_Msk
12508 #define DSI_WPCR3_THSZERO7_Pos (7U)
12509 #define DSI_WPCR3_THSZERO7_Msk (0x1UL << DSI_WPCR3_THSZERO7_Pos) /*!< 0x00000080 */
12510 #define DSI_WPCR3_THSZERO7 DSI_WPCR3_THSZERO7_Msk
12511
12512 #define DSI_WPCR3_TLPXD_Pos (8U)
12513 #define DSI_WPCR3_TLPXD_Msk (0xFFUL << DSI_WPCR3_TLPXD_Pos) /*!< 0x0000FF00 */
12514 #define DSI_WPCR3_TLPXD DSI_WPCR3_TLPXD_Msk /*!< t-LPXD */
12515 #define DSI_WPCR3_TLPXD0_Pos (8U)
12516 #define DSI_WPCR3_TLPXD0_Msk (0x1UL << DSI_WPCR3_TLPXD0_Pos) /*!< 0x00000100 */
12517 #define DSI_WPCR3_TLPXD0 DSI_WPCR3_TLPXD0_Msk
12518 #define DSI_WPCR3_TLPXD1_Pos (9U)
12519 #define DSI_WPCR3_TLPXD1_Msk (0x1UL << DSI_WPCR3_TLPXD1_Pos) /*!< 0x00000200 */
12520 #define DSI_WPCR3_TLPXD1 DSI_WPCR3_TLPXD1_Msk
12521 #define DSI_WPCR3_TLPXD2_Pos (10U)
12522 #define DSI_WPCR3_TLPXD2_Msk (0x1UL << DSI_WPCR3_TLPXD2_Pos) /*!< 0x00000400 */
12523 #define DSI_WPCR3_TLPXD2 DSI_WPCR3_TLPXD2_Msk
12524 #define DSI_WPCR3_TLPXD3_Pos (11U)
12525 #define DSI_WPCR3_TLPXD3_Msk (0x1UL << DSI_WPCR3_TLPXD3_Pos) /*!< 0x00000800 */
12526 #define DSI_WPCR3_TLPXD3 DSI_WPCR3_TLPXD3_Msk
12527 #define DSI_WPCR3_TLPXD4_Pos (12U)
12528 #define DSI_WPCR3_TLPXD4_Msk (0x1UL << DSI_WPCR3_TLPXD4_Pos) /*!< 0x00001000 */
12529 #define DSI_WPCR3_TLPXD4 DSI_WPCR3_TLPXD4_Msk
12530 #define DSI_WPCR3_TLPXD5_Pos (13U)
12531 #define DSI_WPCR3_TLPXD5_Msk (0x1UL << DSI_WPCR3_TLPXD5_Pos) /*!< 0x00002000 */
12532 #define DSI_WPCR3_TLPXD5 DSI_WPCR3_TLPXD5_Msk
12533 #define DSI_WPCR3_TLPXD6_Pos (14U)
12534 #define DSI_WPCR3_TLPXD6_Msk (0x1UL << DSI_WPCR3_TLPXD6_Pos) /*!< 0x00004000 */
12535 #define DSI_WPCR3_TLPXD6 DSI_WPCR3_TLPXD6_Msk
12536 #define DSI_WPCR3_TLPXD7_Pos (15U)
12537 #define DSI_WPCR3_TLPXD7_Msk (0x1UL << DSI_WPCR3_TLPXD7_Pos) /*!< 0x00008000 */
12538 #define DSI_WPCR3_TLPXD7 DSI_WPCR3_TLPXD7_Msk
12539
12540 #define DSI_WPCR3_THSEXIT_Pos (16U)
12541 #define DSI_WPCR3_THSEXIT_Msk (0xFFUL << DSI_WPCR3_THSEXIT_Pos) /*!< 0x00FF0000 */
12542 #define DSI_WPCR3_THSEXIT DSI_WPCR3_THSEXIT_Msk /*!< t-HSEXIT */
12543 #define DSI_WPCR3_THSEXIT0_Pos (16U)
12544 #define DSI_WPCR3_THSEXIT0_Msk (0x1UL << DSI_WPCR3_THSEXIT0_Pos) /*!< 0x00010000 */
12545 #define DSI_WPCR3_THSEXIT0 DSI_WPCR3_THSEXIT0_Msk
12546 #define DSI_WPCR3_THSEXIT1_Pos (17U)
12547 #define DSI_WPCR3_THSEXIT1_Msk (0x1UL << DSI_WPCR3_THSEXIT1_Pos) /*!< 0x00020000 */
12548 #define DSI_WPCR3_THSEXIT1 DSI_WPCR3_THSEXIT1_Msk
12549 #define DSI_WPCR3_THSEXIT2_Pos (18U)
12550 #define DSI_WPCR3_THSEXIT2_Msk (0x1UL << DSI_WPCR3_THSEXIT2_Pos) /*!< 0x00040000 */
12551 #define DSI_WPCR3_THSEXIT2 DSI_WPCR3_THSEXIT2_Msk
12552 #define DSI_WPCR3_THSEXIT3_Pos (19U)
12553 #define DSI_WPCR3_THSEXIT3_Msk (0x1UL << DSI_WPCR3_THSEXIT3_Pos) /*!< 0x00080000 */
12554 #define DSI_WPCR3_THSEXIT3 DSI_WPCR3_THSEXIT3_Msk
12555 #define DSI_WPCR3_THSEXIT4_Pos (20U)
12556 #define DSI_WPCR3_THSEXIT4_Msk (0x1UL << DSI_WPCR3_THSEXIT4_Pos) /*!< 0x00100000 */
12557 #define DSI_WPCR3_THSEXIT4 DSI_WPCR3_THSEXIT4_Msk
12558 #define DSI_WPCR3_THSEXIT5_Pos (21U)
12559 #define DSI_WPCR3_THSEXIT5_Msk (0x1UL << DSI_WPCR3_THSEXIT5_Pos) /*!< 0x00200000 */
12560 #define DSI_WPCR3_THSEXIT5 DSI_WPCR3_THSEXIT5_Msk
12561 #define DSI_WPCR3_THSEXIT6_Pos (22U)
12562 #define DSI_WPCR3_THSEXIT6_Msk (0x1UL << DSI_WPCR3_THSEXIT6_Pos) /*!< 0x00400000 */
12563 #define DSI_WPCR3_THSEXIT6 DSI_WPCR3_THSEXIT6_Msk
12564 #define DSI_WPCR3_THSEXIT7_Pos (23U)
12565 #define DSI_WPCR3_THSEXIT7_Msk (0x1UL << DSI_WPCR3_THSEXIT7_Pos) /*!< 0x00800000 */
12566 #define DSI_WPCR3_THSEXIT7 DSI_WPCR3_THSEXIT7_Msk
12567
12568 #define DSI_WPCR3_TLPXC_Pos (24U)
12569 #define DSI_WPCR3_TLPXC_Msk (0xFFUL << DSI_WPCR3_TLPXC_Pos) /*!< 0xFF000000 */
12570 #define DSI_WPCR3_TLPXC DSI_WPCR3_TLPXC_Msk /*!< t-LPXC */
12571 #define DSI_WPCR3_TLPXC0_Pos (24U)
12572 #define DSI_WPCR3_TLPXC0_Msk (0x1UL << DSI_WPCR3_TLPXC0_Pos) /*!< 0x01000000 */
12573 #define DSI_WPCR3_TLPXC0 DSI_WPCR3_TLPXC0_Msk
12574 #define DSI_WPCR3_TLPXC1_Pos (25U)
12575 #define DSI_WPCR3_TLPXC1_Msk (0x1UL << DSI_WPCR3_TLPXC1_Pos) /*!< 0x02000000 */
12576 #define DSI_WPCR3_TLPXC1 DSI_WPCR3_TLPXC1_Msk
12577 #define DSI_WPCR3_TLPXC2_Pos (26U)
12578 #define DSI_WPCR3_TLPXC2_Msk (0x1UL << DSI_WPCR3_TLPXC2_Pos) /*!< 0x04000000 */
12579 #define DSI_WPCR3_TLPXC2 DSI_WPCR3_TLPXC2_Msk
12580 #define DSI_WPCR3_TLPXC3_Pos (27U)
12581 #define DSI_WPCR3_TLPXC3_Msk (0x1UL << DSI_WPCR3_TLPXC3_Pos) /*!< 0x08000000 */
12582 #define DSI_WPCR3_TLPXC3 DSI_WPCR3_TLPXC3_Msk
12583 #define DSI_WPCR3_TLPXC4_Pos (28U)
12584 #define DSI_WPCR3_TLPXC4_Msk (0x1UL << DSI_WPCR3_TLPXC4_Pos) /*!< 0x10000000 */
12585 #define DSI_WPCR3_TLPXC4 DSI_WPCR3_TLPXC4_Msk
12586 #define DSI_WPCR3_TLPXC5_Pos (29U)
12587 #define DSI_WPCR3_TLPXC5_Msk (0x1UL << DSI_WPCR3_TLPXC5_Pos) /*!< 0x20000000 */
12588 #define DSI_WPCR3_TLPXC5 DSI_WPCR3_TLPXC5_Msk
12589 #define DSI_WPCR3_TLPXC6_Pos (30U)
12590 #define DSI_WPCR3_TLPXC6_Msk (0x1UL << DSI_WPCR3_TLPXC6_Pos) /*!< 0x40000000 */
12591 #define DSI_WPCR3_TLPXC6 DSI_WPCR3_TLPXC6_Msk
12592 #define DSI_WPCR3_TLPXC7_Pos (31U)
12593 #define DSI_WPCR3_TLPXC7_Msk (0x1UL << DSI_WPCR3_TLPXC7_Pos) /*!< 0x80000000 */
12594 #define DSI_WPCR3_TLPXC7 DSI_WPCR3_TLPXC7_Msk
12595
12596 /******************* Bit definition for DSI_WPCR4 register ***************/
12597 #define DSI_WPCR4_TCLKPOST_Pos (0U)
12598 #define DSI_WPCR4_TCLKPOST_Msk (0xFFUL << DSI_WPCR4_TCLKPOST_Pos) /*!< 0x000000FF */
12599 #define DSI_WPCR4_TCLKPOST DSI_WPCR4_TCLKPOST_Msk /*!< t-CLKPOST */
12600 #define DSI_WPCR4_TCLKPOST0_Pos (0U)
12601 #define DSI_WPCR4_TCLKPOST0_Msk (0x1UL << DSI_WPCR4_TCLKPOST0_Pos) /*!< 0x00000001 */
12602 #define DSI_WPCR4_TCLKPOST0 DSI_WPCR4_TCLKPOST0_Msk
12603 #define DSI_WPCR4_TCLKPOST1_Pos (1U)
12604 #define DSI_WPCR4_TCLKPOST1_Msk (0x1UL << DSI_WPCR4_TCLKPOST1_Pos) /*!< 0x00000002 */
12605 #define DSI_WPCR4_TCLKPOST1 DSI_WPCR4_TCLKPOST1_Msk
12606 #define DSI_WPCR4_TCLKPOST2_Pos (2U)
12607 #define DSI_WPCR4_TCLKPOST2_Msk (0x1UL << DSI_WPCR4_TCLKPOST2_Pos) /*!< 0x00000004 */
12608 #define DSI_WPCR4_TCLKPOST2 DSI_WPCR4_TCLKPOST2_Msk
12609 #define DSI_WPCR4_TCLKPOST3_Pos (3U)
12610 #define DSI_WPCR4_TCLKPOST3_Msk (0x1UL << DSI_WPCR4_TCLKPOST3_Pos) /*!< 0x00000008 */
12611 #define DSI_WPCR4_TCLKPOST3 DSI_WPCR4_TCLKPOST3_Msk
12612 #define DSI_WPCR4_TCLKPOST4_Pos (4U)
12613 #define DSI_WPCR4_TCLKPOST4_Msk (0x1UL << DSI_WPCR4_TCLKPOST4_Pos) /*!< 0x00000010 */
12614 #define DSI_WPCR4_TCLKPOST4 DSI_WPCR4_TCLKPOST4_Msk
12615 #define DSI_WPCR4_TCLKPOST5_Pos (5U)
12616 #define DSI_WPCR4_TCLKPOST5_Msk (0x1UL << DSI_WPCR4_TCLKPOST5_Pos) /*!< 0x00000020 */
12617 #define DSI_WPCR4_TCLKPOST5 DSI_WPCR4_TCLKPOST5_Msk
12618 #define DSI_WPCR4_TCLKPOST6_Pos (6U)
12619 #define DSI_WPCR4_TCLKPOST6_Msk (0x1UL << DSI_WPCR4_TCLKPOST6_Pos) /*!< 0x00000040 */
12620 #define DSI_WPCR4_TCLKPOST6 DSI_WPCR4_TCLKPOST6_Msk
12621 #define DSI_WPCR4_TCLKPOST7_Pos (7U)
12622 #define DSI_WPCR4_TCLKPOST7_Msk (0x1UL << DSI_WPCR4_TCLKPOST7_Pos) /*!< 0x00000080 */
12623 #define DSI_WPCR4_TCLKPOST7 DSI_WPCR4_TCLKPOST7_Msk
12624
12625 /******************* Bit definition for DSI_WRPCR register ***************/
12626 #define DSI_WRPCR_PLLEN_Pos (0U)
12627 #define DSI_WRPCR_PLLEN_Msk (0x1UL << DSI_WRPCR_PLLEN_Pos) /*!< 0x00000001 */
12628 #define DSI_WRPCR_PLLEN DSI_WRPCR_PLLEN_Msk /*!< PLL Enable */
12629 #define DSI_WRPCR_PLL_NDIV_Pos (2U)
12630 #define DSI_WRPCR_PLL_NDIV_Msk (0x7FUL << DSI_WRPCR_PLL_NDIV_Pos) /*!< 0x000001FC */
12631 #define DSI_WRPCR_PLL_NDIV DSI_WRPCR_PLL_NDIV_Msk /*!< PLL Loop Division Factor */
12632 #define DSI_WRPCR_PLL_NDIV0_Pos (2U)
12633 #define DSI_WRPCR_PLL_NDIV0_Msk (0x1UL << DSI_WRPCR_PLL_NDIV0_Pos) /*!< 0x00000004 */
12634 #define DSI_WRPCR_PLL_NDIV0 DSI_WRPCR_PLL_NDIV0_Msk
12635 #define DSI_WRPCR_PLL_NDIV1_Pos (3U)
12636 #define DSI_WRPCR_PLL_NDIV1_Msk (0x1UL << DSI_WRPCR_PLL_NDIV1_Pos) /*!< 0x00000008 */
12637 #define DSI_WRPCR_PLL_NDIV1 DSI_WRPCR_PLL_NDIV1_Msk
12638 #define DSI_WRPCR_PLL_NDIV2_Pos (4U)
12639 #define DSI_WRPCR_PLL_NDIV2_Msk (0x1UL << DSI_WRPCR_PLL_NDIV2_Pos) /*!< 0x00000010 */
12640 #define DSI_WRPCR_PLL_NDIV2 DSI_WRPCR_PLL_NDIV2_Msk
12641 #define DSI_WRPCR_PLL_NDIV3_Pos (5U)
12642 #define DSI_WRPCR_PLL_NDIV3_Msk (0x1UL << DSI_WRPCR_PLL_NDIV3_Pos) /*!< 0x00000020 */
12643 #define DSI_WRPCR_PLL_NDIV3 DSI_WRPCR_PLL_NDIV3_Msk
12644 #define DSI_WRPCR_PLL_NDIV4_Pos (6U)
12645 #define DSI_WRPCR_PLL_NDIV4_Msk (0x1UL << DSI_WRPCR_PLL_NDIV4_Pos) /*!< 0x00000040 */
12646 #define DSI_WRPCR_PLL_NDIV4 DSI_WRPCR_PLL_NDIV4_Msk
12647 #define DSI_WRPCR_PLL_NDIV5_Pos (7U)
12648 #define DSI_WRPCR_PLL_NDIV5_Msk (0x1UL << DSI_WRPCR_PLL_NDIV5_Pos) /*!< 0x00000080 */
12649 #define DSI_WRPCR_PLL_NDIV5 DSI_WRPCR_PLL_NDIV5_Msk
12650 #define DSI_WRPCR_PLL_NDIV6_Pos (8U)
12651 #define DSI_WRPCR_PLL_NDIV6_Msk (0x1UL << DSI_WRPCR_PLL_NDIV6_Pos) /*!< 0x00000100 */
12652 #define DSI_WRPCR_PLL_NDIV6 DSI_WRPCR_PLL_NDIV6_Msk
12653
12654 #define DSI_WRPCR_PLL_IDF_Pos (11U)
12655 #define DSI_WRPCR_PLL_IDF_Msk (0xFUL << DSI_WRPCR_PLL_IDF_Pos) /*!< 0x00007800 */
12656 #define DSI_WRPCR_PLL_IDF DSI_WRPCR_PLL_IDF_Msk /*!< PLL Input Division Factor */
12657 #define DSI_WRPCR_PLL_IDF0_Pos (11U)
12658 #define DSI_WRPCR_PLL_IDF0_Msk (0x1UL << DSI_WRPCR_PLL_IDF0_Pos) /*!< 0x00000800 */
12659 #define DSI_WRPCR_PLL_IDF0 DSI_WRPCR_PLL_IDF0_Msk
12660 #define DSI_WRPCR_PLL_IDF1_Pos (12U)
12661 #define DSI_WRPCR_PLL_IDF1_Msk (0x1UL << DSI_WRPCR_PLL_IDF1_Pos) /*!< 0x00001000 */
12662 #define DSI_WRPCR_PLL_IDF1 DSI_WRPCR_PLL_IDF1_Msk
12663 #define DSI_WRPCR_PLL_IDF2_Pos (13U)
12664 #define DSI_WRPCR_PLL_IDF2_Msk (0x1UL << DSI_WRPCR_PLL_IDF2_Pos) /*!< 0x00002000 */
12665 #define DSI_WRPCR_PLL_IDF2 DSI_WRPCR_PLL_IDF2_Msk
12666 #define DSI_WRPCR_PLL_IDF3_Pos (14U)
12667 #define DSI_WRPCR_PLL_IDF3_Msk (0x1UL << DSI_WRPCR_PLL_IDF3_Pos) /*!< 0x00004000 */
12668 #define DSI_WRPCR_PLL_IDF3 DSI_WRPCR_PLL_IDF3_Msk
12669
12670 #define DSI_WRPCR_PLL_ODF_Pos (16U)
12671 #define DSI_WRPCR_PLL_ODF_Msk (0x3UL << DSI_WRPCR_PLL_ODF_Pos) /*!< 0x00030000 */
12672 #define DSI_WRPCR_PLL_ODF DSI_WRPCR_PLL_ODF_Msk /*!< PLL Output Division Factor */
12673 #define DSI_WRPCR_PLL_ODF0_Pos (16U)
12674 #define DSI_WRPCR_PLL_ODF0_Msk (0x1UL << DSI_WRPCR_PLL_ODF0_Pos) /*!< 0x00010000 */
12675 #define DSI_WRPCR_PLL_ODF0 DSI_WRPCR_PLL_ODF0_Msk
12676 #define DSI_WRPCR_PLL_ODF1_Pos (17U)
12677 #define DSI_WRPCR_PLL_ODF1_Msk (0x1UL << DSI_WRPCR_PLL_ODF1_Pos) /*!< 0x00020000 */
12678 #define DSI_WRPCR_PLL_ODF1 DSI_WRPCR_PLL_ODF1_Msk
12679
12680 #define DSI_WRPCR_REGEN_Pos (24U)
12681 #define DSI_WRPCR_REGEN_Msk (0x1UL << DSI_WRPCR_REGEN_Pos) /*!< 0x01000000 */
12682 #define DSI_WRPCR_REGEN DSI_WRPCR_REGEN_Msk /*!< Regulator Enable */
12683
12684 /******************************************************************************/
12685 /* */
12686 /* External Interrupt/Event Controller */
12687 /* */
12688 /******************************************************************************/
12689 /****************** Bit definition for EXTI_RTSR1 register *******************/
12690 #define EXTI_RTSR1_TR_Pos (0U)
12691 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
12692 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
12693 #define EXTI_RTSR1_TR0_Pos (0U)
12694 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
12695 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
12696 #define EXTI_RTSR1_TR1_Pos (1U)
12697 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
12698 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
12699 #define EXTI_RTSR1_TR2_Pos (2U)
12700 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
12701 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
12702 #define EXTI_RTSR1_TR3_Pos (3U)
12703 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
12704 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
12705 #define EXTI_RTSR1_TR4_Pos (4U)
12706 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
12707 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
12708 #define EXTI_RTSR1_TR5_Pos (5U)
12709 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
12710 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
12711 #define EXTI_RTSR1_TR6_Pos (6U)
12712 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
12713 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
12714 #define EXTI_RTSR1_TR7_Pos (7U)
12715 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
12716 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
12717 #define EXTI_RTSR1_TR8_Pos (8U)
12718 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
12719 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
12720 #define EXTI_RTSR1_TR9_Pos (9U)
12721 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
12722 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
12723 #define EXTI_RTSR1_TR10_Pos (10U)
12724 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
12725 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
12726 #define EXTI_RTSR1_TR11_Pos (11U)
12727 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
12728 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
12729 #define EXTI_RTSR1_TR12_Pos (12U)
12730 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
12731 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
12732 #define EXTI_RTSR1_TR13_Pos (13U)
12733 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
12734 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
12735 #define EXTI_RTSR1_TR14_Pos (14U)
12736 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
12737 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
12738 #define EXTI_RTSR1_TR15_Pos (15U)
12739 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
12740 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
12741 #define EXTI_RTSR1_TR16_Pos (16U)
12742 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
12743 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
12744 #define EXTI_RTSR1_TR17_Pos (17U)
12745 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
12746 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
12747 #define EXTI_RTSR1_TR18_Pos (18U)
12748 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
12749 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
12750 #define EXTI_RTSR1_TR19_Pos (19U)
12751 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
12752 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
12753 #define EXTI_RTSR1_TR20_Pos (20U)
12754 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
12755 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
12756 #define EXTI_RTSR1_TR21_Pos (21U)
12757 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
12758 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
12759
12760 /****************** Bit definition for EXTI_FTSR1 register *******************/
12761 #define EXTI_FTSR1_TR_Pos (0U)
12762 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
12763 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
12764 #define EXTI_FTSR1_TR0_Pos (0U)
12765 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
12766 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
12767 #define EXTI_FTSR1_TR1_Pos (1U)
12768 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
12769 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
12770 #define EXTI_FTSR1_TR2_Pos (2U)
12771 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
12772 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
12773 #define EXTI_FTSR1_TR3_Pos (3U)
12774 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
12775 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
12776 #define EXTI_FTSR1_TR4_Pos (4U)
12777 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
12778 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
12779 #define EXTI_FTSR1_TR5_Pos (5U)
12780 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
12781 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
12782 #define EXTI_FTSR1_TR6_Pos (6U)
12783 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
12784 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
12785 #define EXTI_FTSR1_TR7_Pos (7U)
12786 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
12787 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
12788 #define EXTI_FTSR1_TR8_Pos (8U)
12789 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
12790 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
12791 #define EXTI_FTSR1_TR9_Pos (9U)
12792 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
12793 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
12794 #define EXTI_FTSR1_TR10_Pos (10U)
12795 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
12796 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
12797 #define EXTI_FTSR1_TR11_Pos (11U)
12798 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
12799 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
12800 #define EXTI_FTSR1_TR12_Pos (12U)
12801 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
12802 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
12803 #define EXTI_FTSR1_TR13_Pos (13U)
12804 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
12805 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
12806 #define EXTI_FTSR1_TR14_Pos (14U)
12807 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
12808 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
12809 #define EXTI_FTSR1_TR15_Pos (15U)
12810 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
12811 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
12812 #define EXTI_FTSR1_TR16_Pos (16U)
12813 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
12814 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
12815 #define EXTI_FTSR1_TR17_Pos (17U)
12816 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
12817 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
12818 #define EXTI_FTSR1_TR18_Pos (18U)
12819 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
12820 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
12821 #define EXTI_FTSR1_TR19_Pos (19U)
12822 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
12823 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
12824 #define EXTI_FTSR1_TR20_Pos (20U)
12825 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
12826 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
12827 #define EXTI_FTSR1_TR21_Pos (21U)
12828 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
12829 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
12830
12831 /****************** Bit definition for EXTI_SWIER1 register ******************/
12832 #define EXTI_SWIER1_SWIER0_Pos (0U)
12833 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
12834 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
12835 #define EXTI_SWIER1_SWIER1_Pos (1U)
12836 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
12837 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
12838 #define EXTI_SWIER1_SWIER2_Pos (2U)
12839 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
12840 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
12841 #define EXTI_SWIER1_SWIER3_Pos (3U)
12842 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
12843 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
12844 #define EXTI_SWIER1_SWIER4_Pos (4U)
12845 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
12846 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
12847 #define EXTI_SWIER1_SWIER5_Pos (5U)
12848 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
12849 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
12850 #define EXTI_SWIER1_SWIER6_Pos (6U)
12851 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
12852 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
12853 #define EXTI_SWIER1_SWIER7_Pos (7U)
12854 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
12855 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
12856 #define EXTI_SWIER1_SWIER8_Pos (8U)
12857 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
12858 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
12859 #define EXTI_SWIER1_SWIER9_Pos (9U)
12860 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
12861 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
12862 #define EXTI_SWIER1_SWIER10_Pos (10U)
12863 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
12864 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
12865 #define EXTI_SWIER1_SWIER11_Pos (11U)
12866 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
12867 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
12868 #define EXTI_SWIER1_SWIER12_Pos (12U)
12869 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
12870 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
12871 #define EXTI_SWIER1_SWIER13_Pos (13U)
12872 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
12873 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
12874 #define EXTI_SWIER1_SWIER14_Pos (14U)
12875 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
12876 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
12877 #define EXTI_SWIER1_SWIER15_Pos (15U)
12878 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
12879 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
12880 #define EXTI_SWIER1_SWIER16_Pos (16U)
12881 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
12882 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
12883 #define EXTI_SWIER1_SWIER17_Pos (17U)
12884 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
12885 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
12886 #define EXTI_SWIER1_SWIER18_Pos (18U)
12887 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
12888 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
12889 #define EXTI_SWIER1_SWIER19_Pos (19U)
12890 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
12891 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
12892 #define EXTI_SWIER1_SWIER20_Pos (20U)
12893 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
12894 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
12895 #define EXTI_SWIER1_SWIER21_Pos (21U)
12896 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
12897 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
12898
12899 /****************** Bit definition for EXTI_D3PMR1 register ******************/
12900 #define EXTI_D3PMR1_MR0_Pos (0U)
12901 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
12902 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
12903 #define EXTI_D3PMR1_MR1_Pos (1U)
12904 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
12905 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
12906 #define EXTI_D3PMR1_MR2_Pos (2U)
12907 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
12908 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
12909 #define EXTI_D3PMR1_MR3_Pos (3U)
12910 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
12911 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
12912 #define EXTI_D3PMR1_MR4_Pos (4U)
12913 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
12914 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
12915 #define EXTI_D3PMR1_MR5_Pos (5U)
12916 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
12917 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
12918 #define EXTI_D3PMR1_MR6_Pos (6U)
12919 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
12920 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
12921 #define EXTI_D3PMR1_MR7_Pos (7U)
12922 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
12923 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
12924 #define EXTI_D3PMR1_MR8_Pos (8U)
12925 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
12926 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
12927 #define EXTI_D3PMR1_MR9_Pos (9U)
12928 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
12929 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
12930 #define EXTI_D3PMR1_MR10_Pos (10U)
12931 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
12932 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
12933 #define EXTI_D3PMR1_MR11_Pos (11U)
12934 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
12935 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
12936 #define EXTI_D3PMR1_MR12_Pos (12U)
12937 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
12938 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
12939 #define EXTI_D3PMR1_MR13_Pos (13U)
12940 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
12941 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
12942 #define EXTI_D3PMR1_MR14_Pos (14U)
12943 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
12944 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
12945 #define EXTI_D3PMR1_MR15_Pos (15U)
12946 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
12947 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
12948 #define EXTI_D3PMR1_MR19_Pos (19U)
12949 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
12950 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
12951 #define EXTI_D3PMR1_MR20_Pos (20U)
12952 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
12953 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
12954 #define EXTI_D3PMR1_MR21_Pos (21U)
12955 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
12956 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
12957 #define EXTI_D3PMR1_MR25_Pos (24U)
12958 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
12959 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
12960
12961 /******************* Bit definition for EXTI_D3PCR1L register ****************/
12962 #define EXTI_D3PCR1L_PCS0_Pos (0U)
12963 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
12964 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
12965 #define EXTI_D3PCR1L_PCS1_Pos (2U)
12966 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
12967 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
12968 #define EXTI_D3PCR1L_PCS2_Pos (4U)
12969 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
12970 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
12971 #define EXTI_D3PCR1L_PCS3_Pos (6U)
12972 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
12973 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
12974 #define EXTI_D3PCR1L_PCS4_Pos (8U)
12975 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
12976 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
12977 #define EXTI_D3PCR1L_PCS5_Pos (10U)
12978 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
12979 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
12980 #define EXTI_D3PCR1L_PCS6_Pos (12U)
12981 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
12982 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
12983 #define EXTI_D3PCR1L_PCS7_Pos (14U)
12984 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
12985 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
12986 #define EXTI_D3PCR1L_PCS8_Pos (16U)
12987 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
12988 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
12989 #define EXTI_D3PCR1L_PCS9_Pos (18U)
12990 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
12991 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
12992 #define EXTI_D3PCR1L_PCS10_Pos (20U)
12993 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
12994 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
12995 #define EXTI_D3PCR1L_PCS11_Pos (22U)
12996 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
12997 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
12998 #define EXTI_D3PCR1L_PCS12_Pos (24U)
12999 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
13000 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
13001 #define EXTI_D3PCR1L_PCS13_Pos (26U)
13002 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
13003 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
13004 #define EXTI_D3PCR1L_PCS14_Pos (28U)
13005 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
13006 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
13007 #define EXTI_D3PCR1L_PCS15_Pos (30U)
13008 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
13009 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
13010
13011 /******************* Bit definition for EXTI_D3PCR1H register ****************/
13012 #define EXTI_D3PCR1H_PCS19_Pos (6U)
13013 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
13014 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
13015 #define EXTI_D3PCR1H_PCS20_Pos (8U)
13016 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
13017 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
13018 #define EXTI_D3PCR1H_PCS21_Pos (10U)
13019 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
13020 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
13021 #define EXTI_D3PCR1H_PCS25_Pos (18U)
13022 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
13023 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
13024
13025 /****************** Bit definition for EXTI_RTSR2 register *******************/
13026 #define EXTI_RTSR2_TR_Pos (17U)
13027 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
13028 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
13029 #define EXTI_RTSR2_TR49_Pos (17U)
13030 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
13031 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
13032 #define EXTI_RTSR2_TR51_Pos (19U)
13033 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
13034 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
13035
13036 /****************** Bit definition for EXTI_FTSR2 register *******************/
13037 #define EXTI_FTSR2_TR_Pos (17U)
13038 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
13039 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
13040 #define EXTI_FTSR2_TR49_Pos (17U)
13041 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
13042 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
13043 #define EXTI_FTSR2_TR51_Pos (19U)
13044 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
13045 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
13046
13047 /****************** Bit definition for EXTI_SWIER2 register ******************/
13048 #define EXTI_SWIER2_SWIER49_Pos (17U)
13049 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
13050 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
13051 #define EXTI_SWIER2_SWIER51_Pos (19U)
13052 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
13053 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
13054
13055 /****************** Bit definition for EXTI_D3PMR2 register ******************/
13056 #define EXTI_D3PMR2_MR34_Pos (2U)
13057 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
13058 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
13059 #define EXTI_D3PMR2_MR35_Pos (3U)
13060 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
13061 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
13062 #define EXTI_D3PMR2_MR41_Pos (9U)
13063 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
13064 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
13065 #define EXTI_D3PMR2_MR48_Pos (16U)
13066 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
13067 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
13068 #define EXTI_D3PMR2_MR49_Pos (17U)
13069 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
13070 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
13071 #define EXTI_D3PMR2_MR50_Pos (18U)
13072 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
13073 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
13074 #define EXTI_D3PMR2_MR51_Pos (19U)
13075 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
13076 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
13077 #define EXTI_D3PMR2_MR52_Pos (20U)
13078 #define EXTI_D3PMR2_MR52_Msk (0x1UL << EXTI_D3PMR2_MR52_Pos) /*!< 0x00100000 */
13079 #define EXTI_D3PMR2_MR52 EXTI_D3PMR2_MR52_Msk /*!< Pending Mask Event for line 52 */
13080 #define EXTI_D3PMR2_MR53_Pos (21U)
13081 #define EXTI_D3PMR2_MR53_Msk (0x1UL << EXTI_D3PMR2_MR53_Pos) /*!< 0x00200000 */
13082 #define EXTI_D3PMR2_MR53 EXTI_D3PMR2_MR53_Msk /*!< Pending Mask Event for line 53 */
13083 /******************* Bit definition for EXTI_D3PCR2L register ****************/
13084 #define EXTI_D3PCR2L_PCS34_Pos (4U)
13085 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
13086 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
13087 #define EXTI_D3PCR2L_PCS35_Pos (6U)
13088 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
13089 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
13090 #define EXTI_D3PCR2L_PCS41_Pos (18U)
13091 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
13092 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
13093
13094
13095 /******************* Bit definition for EXTI_D3PCR2H register ****************/
13096 #define EXTI_D3PCR2H_PCS48_Pos (0U)
13097 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
13098 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
13099 #define EXTI_D3PCR2H_PCS49_Pos (2U)
13100 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
13101 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
13102 #define EXTI_D3PCR2H_PCS50_Pos (4U)
13103 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
13104 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
13105 #define EXTI_D3PCR2H_PCS51_Pos (6U)
13106 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
13107 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
13108 #define EXTI_D3PCR2H_PCS52_Pos (8U)
13109 #define EXTI_D3PCR2H_PCS52_Msk (0x3UL << EXTI_D3PCR2H_PCS52_Pos) /*!< 0x00000300 */
13110 #define EXTI_D3PCR2H_PCS52 EXTI_D3PCR2H_PCS52_Msk /*!< D3 Pending request clear input signal selection on line 52 */
13111 #define EXTI_D3PCR2H_PCS53_Pos (10U)
13112 #define EXTI_D3PCR2H_PCS53_Msk (0x3UL << EXTI_D3PCR2H_PCS53_Pos) /*!< 0x00000C00 */
13113 #define EXTI_D3PCR2H_PCS53 EXTI_D3PCR2H_PCS53_Msk /*!< D3 Pending request clear input signal selection on line 53 */
13114 /****************** Bit definition for EXTI_RTSR3 register *******************/
13115 #define EXTI_RTSR3_TR_Pos (18U)
13116 #define EXTI_RTSR3_TR_Msk (0x1DUL << EXTI_RTSR3_TR_Pos) /*!< 0x00740000 */
13117 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
13118 #define EXTI_RTSR3_TR82_Pos (18U)
13119 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
13120 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
13121 #define EXTI_RTSR3_TR84_Pos (20U)
13122 #define EXTI_RTSR3_TR84_Msk (0x1UL << EXTI_RTSR3_TR84_Pos) /*!< 0x00100000 */
13123 #define EXTI_RTSR3_TR84 EXTI_RTSR3_TR84_Msk /*!< Rising trigger event configuration bit of line 84 */
13124 #define EXTI_RTSR3_TR85_Pos (21U)
13125 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
13126 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
13127 #define EXTI_RTSR3_TR86_Pos (22U)
13128 #define EXTI_RTSR3_TR86_Msk (0x1UL << EXTI_RTSR3_TR86_Pos) /*!< 0x00400000 */
13129 #define EXTI_RTSR3_TR86 EXTI_RTSR3_TR86_Msk /*!< Rising trigger event configuration bit of line 86 */
13130
13131 /****************** Bit definition for EXTI_FTSR3 register *******************/
13132 #define EXTI_FTSR3_TR_Pos (18U)
13133 #define EXTI_FTSR3_TR_Msk (0x1DUL << EXTI_FTSR3_TR_Pos) /*!< 0x00740000 */
13134 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
13135 #define EXTI_FTSR3_TR82_Pos (18U)
13136 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
13137 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
13138 #define EXTI_FTSR3_TR84_Pos (20U)
13139 #define EXTI_FTSR3_TR84_Msk (0x1UL << EXTI_FTSR3_TR84_Pos) /*!< 0x00100000 */
13140 #define EXTI_FTSR3_TR84 EXTI_FTSR3_TR84_Msk /*!< Falling trigger event configuration bit of line 84 */
13141 #define EXTI_FTSR3_TR85_Pos (21U)
13142 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
13143 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
13144 #define EXTI_FTSR3_TR86_Pos (22U)
13145 #define EXTI_FTSR3_TR86_Msk (0x1UL << EXTI_FTSR3_TR86_Pos) /*!< 0x00400000 */
13146 #define EXTI_FTSR3_TR86 EXTI_FTSR3_TR86_Msk /*!< Falling trigger event configuration bit of line 86 */
13147
13148 /****************** Bit definition for EXTI_SWIER3 register ******************/
13149 #define EXTI_SWIER3_SWI_Pos (18U)
13150 #define EXTI_SWIER3_SWI_Msk (0x1DUL << EXTI_SWIER3_SWI_Pos) /*!< 0x00740000 */
13151 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
13152 #define EXTI_SWIER3_SWIER82_Pos (18U)
13153 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
13154 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
13155 #define EXTI_SWIER3_SWIER84_Pos (20U)
13156 #define EXTI_SWIER3_SWIER84_Msk (0x1UL << EXTI_SWIER3_SWIER84_Pos) /*!< 0x00100000 */
13157 #define EXTI_SWIER3_SWIER84 EXTI_SWIER3_SWIER84_Msk /*!< Software Interrupt on line 84 */
13158 #define EXTI_SWIER3_SWIER85_Pos (21U)
13159 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
13160 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
13161 #define EXTI_SWIER3_SWIER86_Pos (22U)
13162 #define EXTI_SWIER3_SWIER86_Msk (0x1UL << EXTI_SWIER3_SWIER86_Pos) /*!< 0x00400000 */
13163 #define EXTI_SWIER3_SWIER86 EXTI_SWIER3_SWIER86_Msk /*!< Software Interrupt on line 86 */
13164
13165 /******************* Bit definition for EXTI_IMR1 register *******************/
13166 #define EXTI_IMR1_IM_Pos (0U)
13167 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
13168 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
13169 #define EXTI_IMR1_IM0_Pos (0U)
13170 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
13171 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
13172 #define EXTI_IMR1_IM1_Pos (1U)
13173 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
13174 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
13175 #define EXTI_IMR1_IM2_Pos (2U)
13176 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
13177 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
13178 #define EXTI_IMR1_IM3_Pos (3U)
13179 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
13180 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
13181 #define EXTI_IMR1_IM4_Pos (4U)
13182 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
13183 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
13184 #define EXTI_IMR1_IM5_Pos (5U)
13185 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
13186 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
13187 #define EXTI_IMR1_IM6_Pos (6U)
13188 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
13189 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
13190 #define EXTI_IMR1_IM7_Pos (7U)
13191 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
13192 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
13193 #define EXTI_IMR1_IM8_Pos (8U)
13194 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
13195 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
13196 #define EXTI_IMR1_IM9_Pos (9U)
13197 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
13198 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
13199 #define EXTI_IMR1_IM10_Pos (10U)
13200 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
13201 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
13202 #define EXTI_IMR1_IM11_Pos (11U)
13203 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
13204 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
13205 #define EXTI_IMR1_IM12_Pos (12U)
13206 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
13207 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
13208 #define EXTI_IMR1_IM13_Pos (13U)
13209 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
13210 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
13211 #define EXTI_IMR1_IM14_Pos (14U)
13212 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
13213 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
13214 #define EXTI_IMR1_IM15_Pos (15U)
13215 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
13216 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
13217 #define EXTI_IMR1_IM16_Pos (16U)
13218 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
13219 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
13220 #define EXTI_IMR1_IM17_Pos (17U)
13221 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
13222 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
13223 #define EXTI_IMR1_IM18_Pos (18U)
13224 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
13225 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
13226 #define EXTI_IMR1_IM19_Pos (19U)
13227 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
13228 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
13229 #define EXTI_IMR1_IM20_Pos (20U)
13230 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
13231 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
13232 #define EXTI_IMR1_IM21_Pos (21U)
13233 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
13234 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
13235 #define EXTI_IMR1_IM22_Pos (22U)
13236 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
13237 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
13238 #define EXTI_IMR1_IM23_Pos (23U)
13239 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
13240 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
13241 #define EXTI_IMR1_IM24_Pos (24U)
13242 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
13243 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
13244 #define EXTI_IMR1_IM25_Pos (25U)
13245 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
13246 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
13247 #define EXTI_IMR1_IM26_Pos (26U)
13248 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
13249 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
13250 #define EXTI_IMR1_IM27_Pos (27U)
13251 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
13252 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
13253 #define EXTI_IMR1_IM28_Pos (28U)
13254 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
13255 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
13256 #define EXTI_IMR1_IM29_Pos (29U)
13257 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
13258 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
13259 #define EXTI_IMR1_IM30_Pos (30U)
13260 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
13261 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
13262 #define EXTI_IMR1_IM31_Pos (31U)
13263 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
13264 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
13265
13266 /******************* Bit definition for EXTI_EMR1 register *******************/
13267 #define EXTI_EMR1_EM_Pos (0U)
13268 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
13269 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
13270 #define EXTI_EMR1_EM0_Pos (0U)
13271 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
13272 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
13273 #define EXTI_EMR1_EM1_Pos (1U)
13274 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
13275 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
13276 #define EXTI_EMR1_EM2_Pos (2U)
13277 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
13278 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
13279 #define EXTI_EMR1_EM3_Pos (3U)
13280 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
13281 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
13282 #define EXTI_EMR1_EM4_Pos (4U)
13283 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
13284 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
13285 #define EXTI_EMR1_EM5_Pos (5U)
13286 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
13287 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
13288 #define EXTI_EMR1_EM6_Pos (6U)
13289 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
13290 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
13291 #define EXTI_EMR1_EM7_Pos (7U)
13292 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
13293 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
13294 #define EXTI_EMR1_EM8_Pos (8U)
13295 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
13296 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
13297 #define EXTI_EMR1_EM9_Pos (9U)
13298 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
13299 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
13300 #define EXTI_EMR1_EM10_Pos (10U)
13301 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
13302 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
13303 #define EXTI_EMR1_EM11_Pos (11U)
13304 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
13305 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
13306 #define EXTI_EMR1_EM12_Pos (12U)
13307 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
13308 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
13309 #define EXTI_EMR1_EM13_Pos (13U)
13310 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
13311 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
13312 #define EXTI_EMR1_EM14_Pos (14U)
13313 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
13314 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
13315 #define EXTI_EMR1_EM15_Pos (15U)
13316 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
13317 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
13318 #define EXTI_EMR1_EM16_Pos (16U)
13319 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
13320 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
13321 #define EXTI_EMR1_EM17_Pos (17U)
13322 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
13323 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
13324 #define EXTI_EMR1_EM18_Pos (18U)
13325 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
13326 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
13327 #define EXTI_EMR1_EM20_Pos (20U)
13328 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
13329 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
13330 #define EXTI_EMR1_EM21_Pos (21U)
13331 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
13332 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
13333 #define EXTI_EMR1_EM22_Pos (22U)
13334 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
13335 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
13336 #define EXTI_EMR1_EM23_Pos (23U)
13337 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
13338 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
13339 #define EXTI_EMR1_EM24_Pos (24U)
13340 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
13341 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
13342 #define EXTI_EMR1_EM25_Pos (25U)
13343 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
13344 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
13345 #define EXTI_EMR1_EM26_Pos (26U)
13346 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
13347 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
13348 #define EXTI_EMR1_EM27_Pos (27U)
13349 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
13350 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
13351 #define EXTI_EMR1_EM28_Pos (28U)
13352 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
13353 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
13354 #define EXTI_EMR1_EM29_Pos (29U)
13355 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
13356 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
13357 #define EXTI_EMR1_EM30_Pos (30U)
13358 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
13359 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
13360 #define EXTI_EMR1_EM31_Pos (31U)
13361 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
13362 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
13363
13364 /******************* Bit definition for EXTI_PR1 register ********************/
13365 #define EXTI_PR1_PR_Pos (0U)
13366 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
13367 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
13368 #define EXTI_PR1_PR0_Pos (0U)
13369 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
13370 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
13371 #define EXTI_PR1_PR1_Pos (1U)
13372 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
13373 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
13374 #define EXTI_PR1_PR2_Pos (2U)
13375 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
13376 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
13377 #define EXTI_PR1_PR3_Pos (3U)
13378 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
13379 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
13380 #define EXTI_PR1_PR4_Pos (4U)
13381 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
13382 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
13383 #define EXTI_PR1_PR5_Pos (5U)
13384 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
13385 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
13386 #define EXTI_PR1_PR6_Pos (6U)
13387 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
13388 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
13389 #define EXTI_PR1_PR7_Pos (7U)
13390 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
13391 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
13392 #define EXTI_PR1_PR8_Pos (8U)
13393 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
13394 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
13395 #define EXTI_PR1_PR9_Pos (9U)
13396 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
13397 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
13398 #define EXTI_PR1_PR10_Pos (10U)
13399 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
13400 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
13401 #define EXTI_PR1_PR11_Pos (11U)
13402 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
13403 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
13404 #define EXTI_PR1_PR12_Pos (12U)
13405 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
13406 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
13407 #define EXTI_PR1_PR13_Pos (13U)
13408 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
13409 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
13410 #define EXTI_PR1_PR14_Pos (14U)
13411 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
13412 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
13413 #define EXTI_PR1_PR15_Pos (15U)
13414 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
13415 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
13416 #define EXTI_PR1_PR16_Pos (16U)
13417 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
13418 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
13419 #define EXTI_PR1_PR17_Pos (17U)
13420 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
13421 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
13422 #define EXTI_PR1_PR18_Pos (18U)
13423 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
13424 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
13425 #define EXTI_PR1_PR19_Pos (19U)
13426 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
13427 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
13428 #define EXTI_PR1_PR20_Pos (20U)
13429 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
13430 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
13431 #define EXTI_PR1_PR21_Pos (21U)
13432 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
13433 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
13434
13435 /******************* Bit definition for EXTI_IMR2 register *******************/
13436 #define EXTI_IMR2_IM_Pos (0U)
13437 #define EXTI_IMR2_IM_Msk (0xFFFFDFFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFFDFFF */
13438 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
13439 #define EXTI_IMR2_IM32_Pos (0U)
13440 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
13441 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
13442 #define EXTI_IMR2_IM33_Pos (1U)
13443 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
13444 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
13445 #define EXTI_IMR2_IM34_Pos (2U)
13446 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
13447 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
13448 #define EXTI_IMR2_IM35_Pos (3U)
13449 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
13450 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
13451 #define EXTI_IMR2_IM36_Pos (4U)
13452 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
13453 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
13454 #define EXTI_IMR2_IM37_Pos (5U)
13455 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
13456 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
13457 #define EXTI_IMR2_IM38_Pos (6U)
13458 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
13459 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
13460 #define EXTI_IMR2_IM39_Pos (7U)
13461 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
13462 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
13463 #define EXTI_IMR2_IM40_Pos (8U)
13464 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
13465 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
13466 #define EXTI_IMR2_IM41_Pos (9U)
13467 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
13468 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
13469 #define EXTI_IMR2_IM42_Pos (10U)
13470 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
13471 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
13472 #define EXTI_IMR2_IM43_Pos (11U)
13473 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
13474 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
13475 #define EXTI_IMR2_IM44_Pos (12U)
13476 #define EXTI_IMR2_IM44_Msk (0x1UL << EXTI_IMR2_IM44_Pos) /*!< 0x00001000 */
13477 #define EXTI_IMR2_IM44 EXTI_IMR2_IM44_Msk /*!< Interrupt Mask on line 44 */
13478 #define EXTI_IMR2_IM46_Pos (14U)
13479 #define EXTI_IMR2_IM46_Msk (0x1UL << EXTI_IMR2_IM46_Pos) /*!< 0x00004000 */
13480 #define EXTI_IMR2_IM46 EXTI_IMR2_IM46_Msk /*!< Interrupt Mask on line 46 */
13481 #define EXTI_IMR2_IM47_Pos (15U)
13482 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
13483 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
13484 #define EXTI_IMR2_IM48_Pos (16U)
13485 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
13486 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
13487 #define EXTI_IMR2_IM49_Pos (17U)
13488 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
13489 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
13490 #define EXTI_IMR2_IM50_Pos (18U)
13491 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
13492 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
13493 #define EXTI_IMR2_IM51_Pos (19U)
13494 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
13495 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
13496 #define EXTI_IMR2_IM52_Pos (20U)
13497 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
13498 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
13499 #define EXTI_IMR2_IM53_Pos (21U)
13500 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
13501 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
13502 #define EXTI_IMR2_IM54_Pos (22U)
13503 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
13504 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
13505 #define EXTI_IMR2_IM55_Pos (23U)
13506 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
13507 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
13508 #define EXTI_IMR2_IM56_Pos (24U)
13509 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
13510 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
13511 #define EXTI_IMR2_IM57_Pos (25U)
13512 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
13513 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
13514 #define EXTI_IMR2_IM58_Pos (26U)
13515 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
13516 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
13517 #define EXTI_IMR2_IM59_Pos (27U)
13518 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
13519 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
13520 #define EXTI_IMR2_IM60_Pos (28U)
13521 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
13522 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
13523 #define EXTI_IMR2_IM61_Pos (29U)
13524 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
13525 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
13526 #define EXTI_IMR2_IM62_Pos (30U)
13527 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
13528 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
13529 #define EXTI_IMR2_IM63_Pos (31U)
13530 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
13531 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
13532
13533 /******************* Bit definition for EXTI_EMR2 register *******************/
13534 #define EXTI_EMR2_EM_Pos (0U)
13535 #define EXTI_EMR2_EM_Msk (0xFFFFDFFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFFDFFF */
13536 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
13537 #define EXTI_EMR2_EM32_Pos (0U)
13538 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
13539 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
13540 #define EXTI_EMR2_EM33_Pos (1U)
13541 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
13542 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
13543 #define EXTI_EMR2_EM34_Pos (2U)
13544 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
13545 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
13546 #define EXTI_EMR2_EM35_Pos (3U)
13547 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
13548 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
13549 #define EXTI_EMR2_EM36_Pos (4U)
13550 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
13551 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
13552 #define EXTI_EMR2_EM37_Pos (5U)
13553 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
13554 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
13555 #define EXTI_EMR2_EM38_Pos (6U)
13556 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
13557 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
13558 #define EXTI_EMR2_EM39_Pos (7U)
13559 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
13560 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
13561 #define EXTI_EMR2_EM40_Pos (8U)
13562 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
13563 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
13564 #define EXTI_EMR2_EM41_Pos (9U)
13565 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
13566 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
13567 #define EXTI_EMR2_EM42_Pos (10U)
13568 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
13569 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
13570 #define EXTI_EMR2_EM43_Pos (11U)
13571 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
13572 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
13573 #define EXTI_EMR2_EM44_Pos (12U)
13574 #define EXTI_EMR2_EM44_Msk (0x1UL << EXTI_EMR2_EM44_Pos) /*!< 0x00001000 */
13575 #define EXTI_EMR2_EM44 EXTI_EMR2_EM44_Msk /*!< Event Mask on line 44 */
13576 #define EXTI_EMR2_EM46_Pos (14U)
13577 #define EXTI_EMR2_EM46_Msk (0x1UL << EXTI_EMR2_EM46_Pos) /*!< 0x00004000 */
13578 #define EXTI_EMR2_EM46 EXTI_EMR2_EM46_Msk /*!< Event Mask on line 46 */
13579 #define EXTI_EMR2_EM47_Pos (15U)
13580 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
13581 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
13582 #define EXTI_EMR2_EM48_Pos (16U)
13583 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
13584 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
13585 #define EXTI_EMR2_EM49_Pos (17U)
13586 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
13587 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
13588 #define EXTI_EMR2_EM50_Pos (18U)
13589 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
13590 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
13591 #define EXTI_EMR2_EM51_Pos (19U)
13592 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
13593 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
13594 #define EXTI_EMR2_EM52_Pos (20U)
13595 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
13596 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
13597 #define EXTI_EMR2_EM53_Pos (21U)
13598 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
13599 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
13600 #define EXTI_EMR2_EM54_Pos (22U)
13601 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
13602 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
13603 #define EXTI_EMR2_EM55_Pos (23U)
13604 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
13605 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
13606 #define EXTI_EMR2_EM56_Pos (24U)
13607 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
13608 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
13609 #define EXTI_EMR2_EM57_Pos (25U)
13610 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
13611 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
13612 #define EXTI_EMR2_EM58_Pos (26U)
13613 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
13614 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
13615 #define EXTI_EMR2_EM59_Pos (27U)
13616 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
13617 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
13618 #define EXTI_EMR2_EM60_Pos (28U)
13619 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
13620 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
13621 #define EXTI_EMR2_EM61_Pos (29U)
13622 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
13623 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
13624 #define EXTI_EMR2_EM62_Pos (30U)
13625 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
13626 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
13627 #define EXTI_EMR2_EM63_Pos (31U)
13628 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
13629 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
13630
13631 /******************* Bit definition for EXTI_PR2 register ********************/
13632 #define EXTI_PR2_PR_Pos (17U)
13633 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
13634 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
13635 #define EXTI_PR2_PR49_Pos (17U)
13636 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
13637 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
13638 #define EXTI_PR2_PR51_Pos (19U)
13639 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
13640 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
13641
13642 /******************* Bit definition for EXTI_IMR3 register *******************/
13643 #define EXTI_IMR3_IM_Pos (0U)
13644 #define EXTI_IMR3_IM_Msk (0x00F5FFFFUL << EXTI_IMR3_IM_Pos) /*!< 0x00F5FFFF */
13645 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
13646 #define EXTI_IMR3_IM64_Pos (0U)
13647 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
13648 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
13649 #define EXTI_IMR3_IM65_Pos (1U)
13650 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
13651 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
13652 #define EXTI_IMR3_IM66_Pos (2U)
13653 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
13654 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
13655 #define EXTI_IMR3_IM67_Pos (3U)
13656 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
13657 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
13658 #define EXTI_IMR3_IM68_Pos (4U)
13659 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
13660 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
13661 #define EXTI_IMR3_IM69_Pos (5U)
13662 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
13663 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
13664 #define EXTI_IMR3_IM70_Pos (6U)
13665 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
13666 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
13667 #define EXTI_IMR3_IM71_Pos (7U)
13668 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
13669 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
13670 #define EXTI_IMR3_IM72_Pos (8U)
13671 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
13672 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
13673 #define EXTI_IMR3_IM73_Pos (9U)
13674 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
13675 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
13676 #define EXTI_IMR3_IM74_Pos (10U)
13677 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
13678 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
13679 #define EXTI_IMR3_IM75_Pos (11U)
13680 #define EXTI_IMR3_IM75_Msk (0x1UL << EXTI_IMR3_IM75_Pos) /*!< 0x00000800 */
13681 #define EXTI_IMR3_IM75 EXTI_IMR3_IM75_Msk /*!< Interrupt Mask on line 75 */
13682 #define EXTI_IMR3_IM76_Pos (12U)
13683 #define EXTI_IMR3_IM76_Msk (0x1UL << EXTI_IMR3_IM76_Pos) /*!< 0x00001000 */
13684 #define EXTI_IMR3_IM76 EXTI_IMR3_IM76_Msk /*!< Interrupt Mask on line 76 */
13685 #define EXTI_IMR3_IM77_Pos (13U)
13686 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
13687 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
13688 #define EXTI_IMR3_IM78_Pos (14U)
13689 #define EXTI_IMR3_IM78_Msk (0x1UL << EXTI_IMR3_IM78_Pos) /*!< 0x00004000 */
13690 #define EXTI_IMR3_IM78 EXTI_IMR3_IM78_Msk /*!< Interrupt Mask on line 78 */
13691 #define EXTI_IMR3_IM79_Pos (15U)
13692 #define EXTI_IMR3_IM79_Msk (0x1UL << EXTI_IMR3_IM79_Pos) /*!< 0x00008000 */
13693 #define EXTI_IMR3_IM79 EXTI_IMR3_IM79_Msk /*!< Interrupt Mask on line 79 */
13694 #define EXTI_IMR3_IM80_Pos (16U)
13695 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
13696 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
13697 #define EXTI_IMR3_IM82_Pos (18U)
13698 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
13699 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
13700 #define EXTI_IMR3_IM84_Pos (20U)
13701 #define EXTI_IMR3_IM84_Msk (0x1UL << EXTI_IMR3_IM84_Pos) /*!< 0x00100000 */
13702 #define EXTI_IMR3_IM84 EXTI_IMR3_IM84_Msk /*!< Interrupt Mask on line 84 */
13703 #define EXTI_IMR3_IM85_Pos (21U)
13704 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
13705 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
13706 #define EXTI_IMR3_IM86_Pos (22U)
13707 #define EXTI_IMR3_IM86_Msk (0x1UL << EXTI_IMR3_IM86_Pos) /*!< 0x00400000 */
13708 #define EXTI_IMR3_IM86 EXTI_IMR3_IM86_Msk /*!< Interrupt Mask on line 86 */
13709 #define EXTI_IMR3_IM87_Pos (23U)
13710 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
13711 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
13712
13713
13714 /******************* Bit definition for EXTI_EMR3 register *******************/
13715 #define EXTI_EMR3_EM_Pos (0U)
13716 #define EXTI_EMR3_EM_Msk (0x00F5FFFFUL << EXTI_EMR3_EM_Pos) /*!< 0x00F5FFFF */
13717 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
13718 #define EXTI_EMR3_EM64_Pos (0U)
13719 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
13720 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
13721 #define EXTI_EMR3_EM65_Pos (1U)
13722 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
13723 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
13724 #define EXTI_EMR3_EM66_Pos (2U)
13725 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
13726 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
13727 #define EXTI_EMR3_EM67_Pos (3U)
13728 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
13729 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
13730 #define EXTI_EMR3_EM68_Pos (4U)
13731 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
13732 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
13733 #define EXTI_EMR3_EM69_Pos (5U)
13734 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
13735 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
13736 #define EXTI_EMR3_EM70_Pos (6U)
13737 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
13738 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
13739 #define EXTI_EMR3_EM71_Pos (7U)
13740 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
13741 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
13742 #define EXTI_EMR3_EM72_Pos (8U)
13743 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
13744 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
13745 #define EXTI_EMR3_EM73_Pos (9U)
13746 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
13747 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
13748 #define EXTI_EMR3_EM74_Pos (10U)
13749 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
13750 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
13751 #define EXTI_EMR3_EM75_Pos (11U)
13752 #define EXTI_EMR3_EM75_Msk (0x1UL << EXTI_EMR3_EM75_Pos) /*!< 0x00000800 */
13753 #define EXTI_EMR3_EM75 EXTI_EMR3_EM75_Msk /*!< Event Mask on line 75 */
13754 #define EXTI_EMR3_EM76_Pos (12U)
13755 #define EXTI_EMR3_EM76_Msk (0x1UL << EXTI_EMR3_EM76_Pos) /*!< 0x00001000 */
13756 #define EXTI_EMR3_EM76 EXTI_EMR3_EM76_Msk /*!< Event Mask on line 76 */
13757 #define EXTI_EMR3_EM77_Pos (13U)
13758 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
13759 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
13760 #define EXTI_EMR3_EM78_Pos (14U)
13761 #define EXTI_EMR3_EM78_Msk (0x1UL << EXTI_EMR3_EM78_Pos) /*!< 0x00004000 */
13762 #define EXTI_EMR3_EM78 EXTI_EMR3_EM78_Msk /*!< Event Mask on line 78 */
13763 #define EXTI_EMR3_EM79_Pos (15U)
13764 #define EXTI_EMR3_EM79_Msk (0x1UL << EXTI_EMR3_EM79_Pos) /*!< 0x00008000 */
13765 #define EXTI_EMR3_EM79 EXTI_EMR3_EM79_Msk /*!< Event Mask on line 79 */
13766 #define EXTI_EMR3_EM80_Pos (16U)
13767 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
13768 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
13769 #define EXTI_EMR3_EM81_Pos (17U)
13770 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
13771 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
13772 #define EXTI_EMR3_EM82_Pos (18U)
13773 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
13774 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
13775 #define EXTI_EMR3_EM84_Pos (20U)
13776 #define EXTI_EMR3_EM84_Msk (0x1UL << EXTI_EMR3_EM84_Pos) /*!< 0x00100000 */
13777 #define EXTI_EMR3_EM84 EXTI_EMR3_EM84_Msk /*!< Event Mask on line 84 */
13778 #define EXTI_EMR3_EM85_Pos (21U)
13779 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
13780 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
13781 #define EXTI_EMR3_EM86_Pos (22U)
13782 #define EXTI_EMR3_EM86_Msk (0x1UL << EXTI_EMR3_EM86_Pos) /*!< 0x00400000 */
13783 #define EXTI_EMR3_EM86 EXTI_EMR3_EM86_Msk /*!< Event Mask on line 86 */
13784 #define EXTI_EMR3_EM87_Pos (23U)
13785 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
13786 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
13787
13788 /******************* Bit definition for EXTI_PR3 register ********************/
13789 #define EXTI_PR3_PR_Pos (18U)
13790 #define EXTI_PR3_PR_Msk (0x1DUL << EXTI_PR3_PR_Pos) /*!< 0x00740000 */
13791 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
13792 #define EXTI_PR3_PR82_Pos (18U)
13793 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
13794 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
13795 #define EXTI_PR3_PR84_Pos (20U)
13796 #define EXTI_PR3_PR84_Msk (0x1UL << EXTI_PR3_PR84_Pos) /*!< 0x00100000 */
13797 #define EXTI_PR3_PR84 EXTI_PR3_PR84_Msk /*!< Pending bit for line 84 */
13798 #define EXTI_PR3_PR85_Pos (21U)
13799 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
13800 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
13801 #define EXTI_PR3_PR86_Pos (22U)
13802 #define EXTI_PR3_PR86_Msk (0x1UL << EXTI_PR3_PR86_Pos) /*!< 0x00400000 */
13803 #define EXTI_PR3_PR86 EXTI_PR3_PR86_Msk /*!< Pending bit for line 86 */
13804 /******************************************************************************/
13805 /* */
13806 /* FLASH */
13807 /* */
13808 /******************************************************************************/
13809 /*
13810 * @brief FLASH Global Defines
13811 */
13812 #define FLASH_SECTOR_TOTAL 8U /* 8 sectors */
13813 #define FLASH_SIZE 0x200000UL /* 2 MB */
13814 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
13815 #define FLASH_SECTOR_SIZE 0x00020000UL /* 128 KB */
13816 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_7WS /* FLASH Seven Latency cycles */
13817 #define FLASH_NB_32BITWORD_IN_FLASHWORD 8U /* 256 bits */
13818 #define DUAL_BANK /* Dual-bank Flash */
13819
13820 /******************* Bits definition for FLASH_ACR register **********************/
13821 #define FLASH_ACR_LATENCY_Pos (0U)
13822 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
13823 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
13824 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
13825 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
13826 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
13827 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
13828 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
13829 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
13830 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
13831 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
13832 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
13833 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
13834 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
13835 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
13836 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
13837 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
13838 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
13839 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
13840 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
13841 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
13842 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
13843 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
13844 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
13845
13846 /******************* Bits definition for FLASH_CR register ***********************/
13847 #define FLASH_CR_LOCK_Pos (0U)
13848 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
13849 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
13850 #define FLASH_CR_PG_Pos (1U)
13851 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
13852 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
13853 #define FLASH_CR_SER_Pos (2U)
13854 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
13855 #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
13856 #define FLASH_CR_BER_Pos (3U)
13857 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
13858 #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
13859 #define FLASH_CR_PSIZE_Pos (4U)
13860 #define FLASH_CR_PSIZE_Msk (0x3UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000030 */
13861 #define FLASH_CR_PSIZE FLASH_CR_PSIZE_Msk /*!< Program size */
13862 #define FLASH_CR_PSIZE_0 (0x1UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000010 */
13863 #define FLASH_CR_PSIZE_1 (0x2UL << FLASH_CR_PSIZE_Pos) /*!< 0x00000020 */
13864 #define FLASH_CR_FW_Pos (6U)
13865 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000040 */
13866 #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
13867 #define FLASH_CR_START_Pos (7U)
13868 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000080 */
13869 #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
13870 #define FLASH_CR_SNB_Pos (8U)
13871 #define FLASH_CR_SNB_Msk (0x7UL << FLASH_CR_SNB_Pos) /*!< 0x00000700 */
13872 #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
13873 #define FLASH_CR_SNB_0 (0x1UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
13874 #define FLASH_CR_SNB_1 (0x2UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
13875 #define FLASH_CR_SNB_2 (0x4UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
13876 #define FLASH_CR_CRC_EN_Pos (15U)
13877 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
13878 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
13879 #define FLASH_CR_EOPIE_Pos (16U)
13880 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
13881 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
13882 #define FLASH_CR_WRPERRIE_Pos (17U)
13883 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
13884 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
13885 #define FLASH_CR_PGSERRIE_Pos (18U)
13886 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
13887 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
13888 #define FLASH_CR_STRBERRIE_Pos (19U)
13889 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
13890 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
13891 #define FLASH_CR_INCERRIE_Pos (21U)
13892 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
13893 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
13894 #define FLASH_CR_OPERRIE_Pos (22U)
13895 #define FLASH_CR_OPERRIE_Msk (0x1UL << FLASH_CR_OPERRIE_Pos) /*!< 0x00400000 */
13896 #define FLASH_CR_OPERRIE FLASH_CR_OPERRIE_Msk /*!< Write/erase error interrupt enable bit */
13897 #define FLASH_CR_RDPERRIE_Pos (23U)
13898 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
13899 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
13900 #define FLASH_CR_RDSERRIE_Pos (24U)
13901 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
13902 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
13903 #define FLASH_CR_SNECCERRIE_Pos (25U)
13904 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
13905 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
13906 #define FLASH_CR_DBECCERRIE_Pos (26U)
13907 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
13908 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
13909 #define FLASH_CR_CRCENDIE_Pos (27U)
13910 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
13911 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
13912 #define FLASH_CR_CRCRDERRIE_Pos (28U)
13913 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
13914 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
13915
13916 /******************* Bits definition for FLASH_SR register ***********************/
13917 #define FLASH_SR_BSY_Pos (0U)
13918 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
13919 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
13920 #define FLASH_SR_WBNE_Pos (1U)
13921 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
13922 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
13923 #define FLASH_SR_QW_Pos (2U)
13924 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
13925 #define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
13926 #define FLASH_SR_CRC_BUSY_Pos (3U)
13927 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
13928 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
13929 #define FLASH_SR_EOP_Pos (16U)
13930 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
13931 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
13932 #define FLASH_SR_WRPERR_Pos (17U)
13933 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
13934 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
13935 #define FLASH_SR_PGSERR_Pos (18U)
13936 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
13937 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
13938 #define FLASH_SR_STRBERR_Pos (19U)
13939 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
13940 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
13941 #define FLASH_SR_INCERR_Pos (21U)
13942 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
13943 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
13944 #define FLASH_SR_OPERR_Pos (22U)
13945 #define FLASH_SR_OPERR_Msk (0x1UL << FLASH_SR_OPERR_Pos) /*!< 0x00400000 */
13946 #define FLASH_SR_OPERR FLASH_SR_OPERR_Msk /*!< Write/erase error flag */
13947 #define FLASH_SR_RDPERR_Pos (23U)
13948 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
13949 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
13950 #define FLASH_SR_RDSERR_Pos (24U)
13951 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
13952 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
13953 #define FLASH_SR_SNECCERR_Pos (25U)
13954 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
13955 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
13956 #define FLASH_SR_DBECCERR_Pos (26U)
13957 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
13958 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
13959 #define FLASH_SR_CRCEND_Pos (27U)
13960 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
13961 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
13962 #define FLASH_SR_CRCRDERR_Pos (28U)
13963 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
13964 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
13965
13966 /******************* Bits definition for FLASH_CCR register *******************/
13967 #define FLASH_CCR_CLR_EOP_Pos (16U)
13968 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
13969 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
13970 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
13971 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
13972 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
13973 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
13974 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
13975 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
13976 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
13977 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
13978 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
13979 #define FLASH_CCR_CLR_INCERR_Pos (21U)
13980 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
13981 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
13982 #define FLASH_CCR_CLR_OPERR_Pos (22U)
13983 #define FLASH_CCR_CLR_OPERR_Msk (0x1UL << FLASH_CCR_CLR_OPERR_Pos) /*!< 0x00400000 */
13984 #define FLASH_CCR_CLR_OPERR FLASH_CCR_CLR_OPERR_Msk /*!< OPERR flag clear bit */
13985 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
13986 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
13987 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
13988 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
13989 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
13990 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
13991 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
13992 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
13993 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
13994 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
13995 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
13996 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
13997 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
13998 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
13999 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
14000 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
14001 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
14002 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
14003
14004 /******************* Bits definition for FLASH_OPTCR register *******************/
14005 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
14006 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
14007 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
14008 #define FLASH_OPTCR_OPTSTART_Pos (1U)
14009 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
14010 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
14011 #define FLASH_OPTCR_MER_Pos (4U)
14012 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
14013 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
14014 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
14015 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
14016 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
14017 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
14018 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
14019 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
14020
14021 /******************* Bits definition for FLASH_OPTSR register ***************/
14022 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
14023 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
14024 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
14025 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
14026 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
14027 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
14028 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
14029 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
14030 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
14031 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
14032 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
14033 #define FLASH_OPTSR_IWDG2_SW_Pos (5U)
14034 #define FLASH_OPTSR_IWDG2_SW_Msk (0x1UL << FLASH_OPTSR_IWDG2_SW_Pos) /*!< 0x00000020 */
14035 #define FLASH_OPTSR_IWDG2_SW FLASH_OPTSR_IWDG2_SW_Msk /*!< IWDG2 control mode option status bit */
14036 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
14037 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
14038 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
14039 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
14040 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
14041 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
14042 #define FLASH_OPTSR_RDP_Pos (8U)
14043 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
14044 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
14045 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
14046 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
14047 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
14048 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
14049 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
14050 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
14051 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
14052 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
14053 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
14054 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
14055 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
14056 #define FLASH_OPTSR_SECURITY_Pos (21U)
14057 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
14058 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
14059 #define FLASH_OPTSR_BCM4_Pos (22U)
14060 #define FLASH_OPTSR_BCM4_Msk (0x1UL << FLASH_OPTSR_BCM4_Pos) /*!< 0x00400000 */
14061 #define FLASH_OPTSR_BCM4 FLASH_OPTSR_BCM4_Msk /*!< Arm Cortex-M4 boot option status bit */
14062 #define FLASH_OPTSR_BCM7_Pos (23U)
14063 #define FLASH_OPTSR_BCM7_Msk (0x1UL << FLASH_OPTSR_BCM7_Pos) /*!< 0x00800000 */
14064 #define FLASH_OPTSR_BCM7 FLASH_OPTSR_BCM7_Msk /*!< Arm Cortex-M7 boot option status bit */
14065 #define FLASH_OPTSR_NRST_STOP_D2_Pos (24U)
14066 #define FLASH_OPTSR_NRST_STOP_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D2_Pos) /*!< 0x01000000 */
14067 #define FLASH_OPTSR_NRST_STOP_D2 FLASH_OPTSR_NRST_STOP_D2_Msk /*!< D2 domain DStop entry reset option status bit */
14068 #define FLASH_OPTSR_NRST_STBY_D2_Pos (25U)
14069 #define FLASH_OPTSR_NRST_STBY_D2_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D2_Pos) /*!< 0x02000000 */
14070 #define FLASH_OPTSR_NRST_STBY_D2 FLASH_OPTSR_NRST_STBY_D2_Msk /*!< D2 domain DStandby entry reset option status bit */
14071 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
14072 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
14073 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
14074 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
14075 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
14076 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
14077 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
14078 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
14079 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
14080
14081 /******************* Bits definition for FLASH_OPTCCR register *******************/
14082 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
14083 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
14084 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
14085
14086 /******************* Bits definition for FLASH_PRAR register *********************/
14087 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
14088 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
14089 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
14090 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
14091 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
14092 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
14093 #define FLASH_PRAR_DMEP_Pos (31U)
14094 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
14095 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
14096
14097 /******************* Bits definition for FLASH_SCAR register *********************/
14098 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
14099 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
14100 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
14101 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
14102 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
14103 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
14104 #define FLASH_SCAR_DMES_Pos (31U)
14105 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
14106 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
14107
14108 /******************* Bits definition for FLASH_WPSN register *********************/
14109 #define FLASH_WPSN_WRPSN_Pos (0U)
14110 #define FLASH_WPSN_WRPSN_Msk (0xFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0x000000FF */
14111 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
14112
14113 /******************* Bits definition for FLASH_BOOT7_CUR register ****************/
14114 #define FLASH_BOOT7_BCM7_ADD0_Pos (0U)
14115 #define FLASH_BOOT7_BCM7_ADD0_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD0_Pos) /*!< 0x0000FFFF */
14116 #define FLASH_BOOT7_BCM7_ADD0 FLASH_BOOT7_BCM7_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
14117 #define FLASH_BOOT7_BCM7_ADD1_Pos (16U)
14118 #define FLASH_BOOT7_BCM7_ADD1_Msk (0xFFFFUL << FLASH_BOOT7_BCM7_ADD1_Pos) /*!< 0xFFFF0000 */
14119 #define FLASH_BOOT7_BCM7_ADD1 FLASH_BOOT7_BCM7_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
14120
14121 /******************* Bits definition for FLASH_BOOT4 register ********************/
14122 #define FLASH_BOOT4_BCM4_ADD0_Pos (0U)
14123 #define FLASH_BOOT4_BCM4_ADD0_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD0_Pos) /*!< 0x0000FFFF */
14124 #define FLASH_BOOT4_BCM4_ADD0 FLASH_BOOT4_BCM4_ADD0_Msk /*!< Arm Cortex-M4 boot address 0 */
14125 #define FLASH_BOOT4_BCM4_ADD1_Pos (16U)
14126 #define FLASH_BOOT4_BCM4_ADD1_Msk (0xFFFFUL << FLASH_BOOT4_BCM4_ADD1_Pos) /*!< 0xFFFF0000 */
14127 #define FLASH_BOOT4_BCM4_ADD1 FLASH_BOOT4_BCM4_ADD1_Msk /*!< Arm Cortex-M4 boot address 1 */
14128
14129 /******************* Bits definition for FLASH_CRCCR register ********************/
14130 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
14131 #define FLASH_CRCCR_CRC_SECT_Msk (0x7UL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x00000007 */
14132 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
14133 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
14134 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
14135 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
14136 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
14137 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
14138 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
14139 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
14140 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
14141 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
14142 #define FLASH_CRCCR_START_CRC_Pos (16U)
14143 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
14144 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
14145 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
14146 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
14147 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
14148 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
14149 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
14150 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
14151 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
14152 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
14153 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
14154 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
14155 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
14156
14157 /******************* Bits definition for FLASH_CRCSADD register ****************/
14158 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
14159 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
14160 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
14161
14162 /******************* Bits definition for FLASH_CRCEADD register ****************/
14163 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
14164 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
14165 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
14166
14167 /******************* Bits definition for FLASH_CRCDATA register ***************/
14168 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
14169 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
14170 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
14171
14172 /******************* Bits definition for FLASH_ECC_FA register *******************/
14173 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
14174 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0x7FFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x00007FFF */
14175 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
14176
14177 /******************************************************************************/
14178 /* */
14179 /* Flexible Memory Controller */
14180 /* */
14181 /******************************************************************************/
14182 /****************** Bit definition for FMC_BCR1 register *******************/
14183 #define FMC_BCR1_CCLKEN_Pos (20U)
14184 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
14185 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
14186 #define FMC_BCR1_WFDIS_Pos (21U)
14187 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
14188 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
14189
14190 #define FMC_BCR1_BMAP_Pos (24U)
14191 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
14192 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
14193 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
14194 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
14195
14196 #define FMC_BCR1_FMCEN_Pos (31U)
14197 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
14198 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
14199 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
14200 #define FMC_BCRx_MBKEN_Pos (0U)
14201 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
14202 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
14203 #define FMC_BCRx_MUXEN_Pos (1U)
14204 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
14205 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
14206
14207 #define FMC_BCRx_MTYP_Pos (2U)
14208 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
14209 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
14210 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
14211 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
14212
14213 #define FMC_BCRx_MWID_Pos (4U)
14214 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
14215 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
14216 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
14217 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
14218
14219 #define FMC_BCRx_FACCEN_Pos (6U)
14220 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
14221 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
14222 #define FMC_BCRx_BURSTEN_Pos (8U)
14223 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
14224 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
14225 #define FMC_BCRx_WAITPOL_Pos (9U)
14226 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
14227 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
14228 #define FMC_BCRx_WAITCFG_Pos (11U)
14229 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
14230 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
14231 #define FMC_BCRx_WREN_Pos (12U)
14232 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
14233 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
14234 #define FMC_BCRx_WAITEN_Pos (13U)
14235 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
14236 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
14237 #define FMC_BCRx_EXTMOD_Pos (14U)
14238 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
14239 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
14240 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
14241 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
14242 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
14243
14244 #define FMC_BCRx_CPSIZE_Pos (16U)
14245 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
14246 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
14247 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
14248 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
14249 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
14250
14251 #define FMC_BCRx_CBURSTRW_Pos (19U)
14252 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
14253 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
14254
14255 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
14256 #define FMC_BTRx_ADDSET_Pos (0U)
14257 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
14258 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
14259 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
14260 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
14261 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
14262 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
14263
14264 #define FMC_BTRx_ADDHLD_Pos (4U)
14265 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
14266 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
14267 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
14268 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
14269 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
14270 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
14271
14272 #define FMC_BTRx_DATAST_Pos (8U)
14273 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
14274 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
14275 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
14276 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
14277 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
14278 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
14279 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
14280 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
14281 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
14282 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
14283
14284 #define FMC_BTRx_BUSTURN_Pos (16U)
14285 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
14286 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
14287 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
14288 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
14289 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
14290 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
14291
14292 #define FMC_BTRx_CLKDIV_Pos (20U)
14293 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
14294 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
14295 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
14296 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
14297 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
14298 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
14299
14300 #define FMC_BTRx_DATLAT_Pos (24U)
14301 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
14302 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
14303 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
14304 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
14305 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
14306 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
14307
14308 #define FMC_BTRx_ACCMOD_Pos (28U)
14309 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
14310 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
14311 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
14312 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
14313
14314 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
14315 #define FMC_BWTRx_ADDSET_Pos (0U)
14316 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
14317 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
14318 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
14319 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
14320 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
14321 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
14322
14323 #define FMC_BWTRx_ADDHLD_Pos (4U)
14324 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
14325 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
14326 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
14327 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
14328 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
14329 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
14330
14331 #define FMC_BWTRx_DATAST_Pos (8U)
14332 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
14333 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
14334 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
14335 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
14336 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
14337 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
14338 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
14339 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
14340 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
14341 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
14342
14343 #define FMC_BWTRx_BUSTURN_Pos (16U)
14344 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
14345 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
14346 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
14347 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
14348 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
14349 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
14350
14351 #define FMC_BWTRx_ACCMOD_Pos (28U)
14352 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
14353 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
14354 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
14355 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
14356
14357 /****************** Bit definition for FMC_PCR register *******************/
14358 #define FMC_PCR_PWAITEN_Pos (1U)
14359 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
14360 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
14361 #define FMC_PCR_PBKEN_Pos (2U)
14362 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
14363 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
14364
14365 #define FMC_PCR_PWID_Pos (4U)
14366 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
14367 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
14368 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
14369 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
14370
14371 #define FMC_PCR_ECCEN_Pos (6U)
14372 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
14373 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
14374
14375 #define FMC_PCR_TCLR_Pos (9U)
14376 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
14377 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
14378 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
14379 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
14380 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
14381 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
14382
14383 #define FMC_PCR_TAR_Pos (13U)
14384 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
14385 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
14386 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
14387 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
14388 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
14389 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
14390
14391 #define FMC_PCR_ECCPS_Pos (17U)
14392 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
14393 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
14394 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
14395 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
14396 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
14397
14398 /******************* Bit definition for FMC_SR register *******************/
14399 #define FMC_SR_IRS_Pos (0U)
14400 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
14401 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
14402 #define FMC_SR_ILS_Pos (1U)
14403 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
14404 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
14405 #define FMC_SR_IFS_Pos (2U)
14406 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
14407 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
14408 #define FMC_SR_IREN_Pos (3U)
14409 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
14410 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
14411 #define FMC_SR_ILEN_Pos (4U)
14412 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
14413 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
14414 #define FMC_SR_IFEN_Pos (5U)
14415 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
14416 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
14417 #define FMC_SR_FEMPT_Pos (6U)
14418 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
14419 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
14420
14421 /****************** Bit definition for FMC_PMEM register ******************/
14422 #define FMC_PMEM_MEMSET_Pos (0U)
14423 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
14424 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
14425 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
14426 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
14427 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
14428 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
14429 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
14430 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
14431 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
14432 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
14433
14434 #define FMC_PMEM_MEMWAIT_Pos (8U)
14435 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
14436 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
14437 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
14438 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
14439 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
14440 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
14441 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
14442 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
14443 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
14444 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
14445
14446 #define FMC_PMEM_MEMHOLD_Pos (16U)
14447 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
14448 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
14449 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
14450 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
14451 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
14452 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
14453 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
14454 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
14455 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
14456 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
14457
14458 #define FMC_PMEM_MEMHIZ_Pos (24U)
14459 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
14460 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
14461 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
14462 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
14463 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
14464 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
14465 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
14466 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
14467 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
14468 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
14469
14470 /****************** Bit definition for FMC_PATT register ******************/
14471 #define FMC_PATT_ATTSET_Pos (0U)
14472 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
14473 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
14474 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
14475 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
14476 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
14477 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
14478 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
14479 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
14480 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
14481 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
14482
14483 #define FMC_PATT_ATTWAIT_Pos (8U)
14484 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
14485 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
14486 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
14487 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
14488 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
14489 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
14490 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
14491 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
14492 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
14493 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
14494
14495 #define FMC_PATT_ATTHOLD_Pos (16U)
14496 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
14497 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
14498 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
14499 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
14500 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
14501 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
14502 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
14503 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
14504 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
14505 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
14506
14507 #define FMC_PATT_ATTHIZ_Pos (24U)
14508 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
14509 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
14510 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
14511 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
14512 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
14513 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
14514 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
14515 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
14516 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
14517 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
14518
14519 /****************** Bit definition for FMC_ECCR3 register ******************/
14520 #define FMC_ECCR3_ECC3_Pos (0U)
14521 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
14522 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
14523
14524 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
14525 #define FMC_SDCRx_NC_Pos (0U)
14526 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
14527 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
14528 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
14529 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
14530
14531 #define FMC_SDCRx_NR_Pos (2U)
14532 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
14533 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
14534 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
14535 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
14536
14537 #define FMC_SDCRx_MWID_Pos (4U)
14538 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
14539 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
14540 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
14541 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
14542
14543 #define FMC_SDCRx_NB_Pos (6U)
14544 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
14545 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
14546
14547 #define FMC_SDCRx_CAS_Pos (7U)
14548 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
14549 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
14550 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
14551 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
14552
14553 #define FMC_SDCRx_WP_Pos (9U)
14554 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
14555 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
14556
14557 #define FMC_SDCRx_SDCLK_Pos (10U)
14558 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
14559 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
14560 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
14561 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
14562
14563 #define FMC_SDCRx_RBURST_Pos (12U)
14564 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
14565 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
14566
14567 #define FMC_SDCRx_RPIPE_Pos (13U)
14568 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
14569 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
14570 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
14571 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
14572
14573 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
14574 #define FMC_SDTRx_TMRD_Pos (0U)
14575 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
14576 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
14577 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
14578 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
14579 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
14580 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
14581
14582 #define FMC_SDTRx_TXSR_Pos (4U)
14583 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
14584 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
14585 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
14586 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
14587 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
14588 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
14589
14590 #define FMC_SDTRx_TRAS_Pos (8U)
14591 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
14592 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
14593 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
14594 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
14595 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
14596 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
14597
14598 #define FMC_SDTRx_TRC_Pos (12U)
14599 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
14600 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
14601 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
14602 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
14603 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
14604
14605 #define FMC_SDTRx_TWR_Pos (16U)
14606 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
14607 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
14608 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
14609 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
14610 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
14611
14612 #define FMC_SDTRx_TRP_Pos (20U)
14613 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
14614 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
14615 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
14616 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
14617 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
14618
14619 #define FMC_SDTRx_TRCD_Pos (24U)
14620 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
14621 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
14622 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
14623 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
14624 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
14625
14626 /****************** Bit definition for FMC_SDCMR register ******************/
14627 #define FMC_SDCMR_MODE_Pos (0U)
14628 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
14629 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
14630 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
14631 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
14632 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
14633
14634 #define FMC_SDCMR_CTB2_Pos (3U)
14635 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
14636 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
14637
14638 #define FMC_SDCMR_CTB1_Pos (4U)
14639 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
14640 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
14641
14642 #define FMC_SDCMR_NRFS_Pos (5U)
14643 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
14644 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
14645 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
14646 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
14647 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
14648 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
14649
14650 #define FMC_SDCMR_MRD_Pos (9U)
14651 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
14652 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
14653
14654 /****************** Bit definition for FMC_SDRTR register ******************/
14655 #define FMC_SDRTR_CRE_Pos (0U)
14656 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
14657 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
14658
14659 #define FMC_SDRTR_COUNT_Pos (1U)
14660 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
14661 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
14662
14663 #define FMC_SDRTR_REIE_Pos (14U)
14664 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
14665 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
14666
14667 /****************** Bit definition for FMC_SDSR register ******************/
14668 #define FMC_SDSR_RE_Pos (0U)
14669 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
14670 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
14671
14672 #define FMC_SDSR_MODES1_Pos (1U)
14673 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
14674 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
14675 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
14676 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
14677
14678 #define FMC_SDSR_MODES2_Pos (3U)
14679 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
14680 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
14681 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
14682 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
14683
14684 /******************************************************************************/
14685 /* */
14686 /* General Purpose I/O */
14687 /* */
14688 /******************************************************************************/
14689 /****************** Bits definition for GPIO_MODER register *****************/
14690 #define GPIO_MODER_MODE0_Pos (0U)
14691 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
14692 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
14693 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
14694 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
14695
14696 #define GPIO_MODER_MODE1_Pos (2U)
14697 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
14698 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
14699 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
14700 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
14701
14702 #define GPIO_MODER_MODE2_Pos (4U)
14703 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
14704 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
14705 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
14706 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
14707
14708 #define GPIO_MODER_MODE3_Pos (6U)
14709 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
14710 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
14711 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
14712 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
14713
14714 #define GPIO_MODER_MODE4_Pos (8U)
14715 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
14716 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
14717 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
14718 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
14719
14720 #define GPIO_MODER_MODE5_Pos (10U)
14721 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
14722 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
14723 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
14724 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
14725
14726 #define GPIO_MODER_MODE6_Pos (12U)
14727 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
14728 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
14729 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
14730 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
14731
14732 #define GPIO_MODER_MODE7_Pos (14U)
14733 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
14734 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
14735 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
14736 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
14737
14738 #define GPIO_MODER_MODE8_Pos (16U)
14739 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
14740 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
14741 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
14742 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
14743
14744 #define GPIO_MODER_MODE9_Pos (18U)
14745 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
14746 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
14747 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
14748 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
14749
14750 #define GPIO_MODER_MODE10_Pos (20U)
14751 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
14752 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
14753 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
14754 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
14755
14756 #define GPIO_MODER_MODE11_Pos (22U)
14757 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
14758 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
14759 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
14760 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
14761
14762 #define GPIO_MODER_MODE12_Pos (24U)
14763 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
14764 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
14765 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
14766 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
14767
14768 #define GPIO_MODER_MODE13_Pos (26U)
14769 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
14770 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
14771 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
14772 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
14773
14774 #define GPIO_MODER_MODE14_Pos (28U)
14775 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
14776 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
14777 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
14778 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
14779
14780 #define GPIO_MODER_MODE15_Pos (30U)
14781 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
14782 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
14783 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
14784 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
14785
14786 /****************** Bits definition for GPIO_OTYPER register ****************/
14787 #define GPIO_OTYPER_OT0_Pos (0U)
14788 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
14789 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
14790 #define GPIO_OTYPER_OT1_Pos (1U)
14791 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
14792 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
14793 #define GPIO_OTYPER_OT2_Pos (2U)
14794 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
14795 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
14796 #define GPIO_OTYPER_OT3_Pos (3U)
14797 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
14798 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
14799 #define GPIO_OTYPER_OT4_Pos (4U)
14800 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
14801 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
14802 #define GPIO_OTYPER_OT5_Pos (5U)
14803 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
14804 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
14805 #define GPIO_OTYPER_OT6_Pos (6U)
14806 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
14807 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
14808 #define GPIO_OTYPER_OT7_Pos (7U)
14809 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
14810 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
14811 #define GPIO_OTYPER_OT8_Pos (8U)
14812 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
14813 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
14814 #define GPIO_OTYPER_OT9_Pos (9U)
14815 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
14816 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
14817 #define GPIO_OTYPER_OT10_Pos (10U)
14818 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
14819 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
14820 #define GPIO_OTYPER_OT11_Pos (11U)
14821 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
14822 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
14823 #define GPIO_OTYPER_OT12_Pos (12U)
14824 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
14825 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
14826 #define GPIO_OTYPER_OT13_Pos (13U)
14827 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
14828 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
14829 #define GPIO_OTYPER_OT14_Pos (14U)
14830 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
14831 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
14832 #define GPIO_OTYPER_OT15_Pos (15U)
14833 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
14834 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
14835
14836 /****************** Bits definition for GPIO_OSPEEDR register ***************/
14837 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
14838 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
14839 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
14840 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
14841 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
14842
14843 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
14844 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
14845 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
14846 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
14847 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
14848
14849 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
14850 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
14851 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
14852 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
14853 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
14854
14855 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
14856 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
14857 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
14858 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
14859 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
14860
14861 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
14862 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
14863 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
14864 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
14865 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
14866
14867 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
14868 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
14869 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
14870 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
14871 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
14872
14873 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
14874 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
14875 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
14876 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
14877 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
14878
14879 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
14880 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
14881 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
14882 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
14883 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
14884
14885 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
14886 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
14887 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
14888 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
14889 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
14890
14891 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
14892 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
14893 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
14894 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
14895 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
14896
14897 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
14898 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
14899 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
14900 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
14901 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
14902
14903 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
14904 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
14905 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
14906 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
14907 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
14908
14909 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
14910 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
14911 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
14912 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
14913 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
14914
14915 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
14916 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
14917 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
14918 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
14919 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
14920
14921 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
14922 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
14923 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
14924 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
14925 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
14926
14927 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
14928 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
14929 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
14930 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
14931 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
14932
14933 /****************** Bits definition for GPIO_PUPDR register *****************/
14934 #define GPIO_PUPDR_PUPD0_Pos (0U)
14935 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
14936 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
14937 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
14938 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
14939
14940 #define GPIO_PUPDR_PUPD1_Pos (2U)
14941 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
14942 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
14943 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
14944 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
14945
14946 #define GPIO_PUPDR_PUPD2_Pos (4U)
14947 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
14948 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
14949 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
14950 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
14951
14952 #define GPIO_PUPDR_PUPD3_Pos (6U)
14953 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
14954 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
14955 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
14956 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
14957
14958 #define GPIO_PUPDR_PUPD4_Pos (8U)
14959 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
14960 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
14961 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
14962 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
14963
14964 #define GPIO_PUPDR_PUPD5_Pos (10U)
14965 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
14966 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
14967 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
14968 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
14969
14970 #define GPIO_PUPDR_PUPD6_Pos (12U)
14971 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
14972 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
14973 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
14974 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
14975
14976 #define GPIO_PUPDR_PUPD7_Pos (14U)
14977 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
14978 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
14979 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
14980 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
14981
14982 #define GPIO_PUPDR_PUPD8_Pos (16U)
14983 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
14984 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
14985 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
14986 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
14987
14988 #define GPIO_PUPDR_PUPD9_Pos (18U)
14989 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
14990 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
14991 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
14992 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
14993
14994 #define GPIO_PUPDR_PUPD10_Pos (20U)
14995 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
14996 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
14997 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
14998 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
14999
15000 #define GPIO_PUPDR_PUPD11_Pos (22U)
15001 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
15002 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
15003 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
15004 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
15005
15006 #define GPIO_PUPDR_PUPD12_Pos (24U)
15007 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
15008 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
15009 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
15010 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
15011
15012 #define GPIO_PUPDR_PUPD13_Pos (26U)
15013 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
15014 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
15015 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
15016 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
15017
15018 #define GPIO_PUPDR_PUPD14_Pos (28U)
15019 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
15020 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
15021 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
15022 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
15023
15024 #define GPIO_PUPDR_PUPD15_Pos (30U)
15025 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
15026 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
15027 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
15028 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
15029
15030 /****************** Bits definition for GPIO_IDR register *******************/
15031 #define GPIO_IDR_ID0_Pos (0U)
15032 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
15033 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
15034 #define GPIO_IDR_ID1_Pos (1U)
15035 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
15036 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
15037 #define GPIO_IDR_ID2_Pos (2U)
15038 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
15039 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
15040 #define GPIO_IDR_ID3_Pos (3U)
15041 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
15042 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
15043 #define GPIO_IDR_ID4_Pos (4U)
15044 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
15045 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
15046 #define GPIO_IDR_ID5_Pos (5U)
15047 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
15048 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
15049 #define GPIO_IDR_ID6_Pos (6U)
15050 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
15051 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
15052 #define GPIO_IDR_ID7_Pos (7U)
15053 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
15054 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
15055 #define GPIO_IDR_ID8_Pos (8U)
15056 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
15057 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
15058 #define GPIO_IDR_ID9_Pos (9U)
15059 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
15060 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
15061 #define GPIO_IDR_ID10_Pos (10U)
15062 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
15063 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
15064 #define GPIO_IDR_ID11_Pos (11U)
15065 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
15066 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
15067 #define GPIO_IDR_ID12_Pos (12U)
15068 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
15069 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
15070 #define GPIO_IDR_ID13_Pos (13U)
15071 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
15072 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
15073 #define GPIO_IDR_ID14_Pos (14U)
15074 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
15075 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
15076 #define GPIO_IDR_ID15_Pos (15U)
15077 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
15078 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
15079
15080 /****************** Bits definition for GPIO_ODR register *******************/
15081 #define GPIO_ODR_OD0_Pos (0U)
15082 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
15083 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
15084 #define GPIO_ODR_OD1_Pos (1U)
15085 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
15086 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
15087 #define GPIO_ODR_OD2_Pos (2U)
15088 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
15089 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
15090 #define GPIO_ODR_OD3_Pos (3U)
15091 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
15092 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
15093 #define GPIO_ODR_OD4_Pos (4U)
15094 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
15095 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
15096 #define GPIO_ODR_OD5_Pos (5U)
15097 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
15098 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
15099 #define GPIO_ODR_OD6_Pos (6U)
15100 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
15101 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
15102 #define GPIO_ODR_OD7_Pos (7U)
15103 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
15104 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
15105 #define GPIO_ODR_OD8_Pos (8U)
15106 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
15107 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
15108 #define GPIO_ODR_OD9_Pos (9U)
15109 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
15110 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
15111 #define GPIO_ODR_OD10_Pos (10U)
15112 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
15113 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
15114 #define GPIO_ODR_OD11_Pos (11U)
15115 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
15116 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
15117 #define GPIO_ODR_OD12_Pos (12U)
15118 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
15119 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
15120 #define GPIO_ODR_OD13_Pos (13U)
15121 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
15122 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
15123 #define GPIO_ODR_OD14_Pos (14U)
15124 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
15125 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
15126 #define GPIO_ODR_OD15_Pos (15U)
15127 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
15128 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
15129
15130 /****************** Bits definition for GPIO_BSRR register ******************/
15131 #define GPIO_BSRR_BS0_Pos (0U)
15132 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
15133 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
15134 #define GPIO_BSRR_BS1_Pos (1U)
15135 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
15136 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
15137 #define GPIO_BSRR_BS2_Pos (2U)
15138 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
15139 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
15140 #define GPIO_BSRR_BS3_Pos (3U)
15141 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
15142 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
15143 #define GPIO_BSRR_BS4_Pos (4U)
15144 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
15145 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
15146 #define GPIO_BSRR_BS5_Pos (5U)
15147 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
15148 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
15149 #define GPIO_BSRR_BS6_Pos (6U)
15150 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
15151 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
15152 #define GPIO_BSRR_BS7_Pos (7U)
15153 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
15154 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
15155 #define GPIO_BSRR_BS8_Pos (8U)
15156 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
15157 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
15158 #define GPIO_BSRR_BS9_Pos (9U)
15159 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
15160 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
15161 #define GPIO_BSRR_BS10_Pos (10U)
15162 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
15163 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
15164 #define GPIO_BSRR_BS11_Pos (11U)
15165 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
15166 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
15167 #define GPIO_BSRR_BS12_Pos (12U)
15168 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
15169 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
15170 #define GPIO_BSRR_BS13_Pos (13U)
15171 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
15172 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
15173 #define GPIO_BSRR_BS14_Pos (14U)
15174 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
15175 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
15176 #define GPIO_BSRR_BS15_Pos (15U)
15177 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
15178 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
15179 #define GPIO_BSRR_BR0_Pos (16U)
15180 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
15181 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
15182 #define GPIO_BSRR_BR1_Pos (17U)
15183 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
15184 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
15185 #define GPIO_BSRR_BR2_Pos (18U)
15186 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
15187 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
15188 #define GPIO_BSRR_BR3_Pos (19U)
15189 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
15190 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
15191 #define GPIO_BSRR_BR4_Pos (20U)
15192 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
15193 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
15194 #define GPIO_BSRR_BR5_Pos (21U)
15195 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
15196 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
15197 #define GPIO_BSRR_BR6_Pos (22U)
15198 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
15199 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
15200 #define GPIO_BSRR_BR7_Pos (23U)
15201 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
15202 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
15203 #define GPIO_BSRR_BR8_Pos (24U)
15204 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
15205 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
15206 #define GPIO_BSRR_BR9_Pos (25U)
15207 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
15208 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
15209 #define GPIO_BSRR_BR10_Pos (26U)
15210 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
15211 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
15212 #define GPIO_BSRR_BR11_Pos (27U)
15213 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
15214 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
15215 #define GPIO_BSRR_BR12_Pos (28U)
15216 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
15217 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
15218 #define GPIO_BSRR_BR13_Pos (29U)
15219 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
15220 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
15221 #define GPIO_BSRR_BR14_Pos (30U)
15222 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
15223 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
15224 #define GPIO_BSRR_BR15_Pos (31U)
15225 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
15226 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
15227
15228 /****************** Bit definition for GPIO_LCKR register *********************/
15229 #define GPIO_LCKR_LCK0_Pos (0U)
15230 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
15231 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
15232 #define GPIO_LCKR_LCK1_Pos (1U)
15233 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
15234 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
15235 #define GPIO_LCKR_LCK2_Pos (2U)
15236 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
15237 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
15238 #define GPIO_LCKR_LCK3_Pos (3U)
15239 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
15240 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
15241 #define GPIO_LCKR_LCK4_Pos (4U)
15242 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
15243 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
15244 #define GPIO_LCKR_LCK5_Pos (5U)
15245 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
15246 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
15247 #define GPIO_LCKR_LCK6_Pos (6U)
15248 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
15249 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
15250 #define GPIO_LCKR_LCK7_Pos (7U)
15251 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
15252 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
15253 #define GPIO_LCKR_LCK8_Pos (8U)
15254 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
15255 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
15256 #define GPIO_LCKR_LCK9_Pos (9U)
15257 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
15258 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
15259 #define GPIO_LCKR_LCK10_Pos (10U)
15260 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
15261 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
15262 #define GPIO_LCKR_LCK11_Pos (11U)
15263 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
15264 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
15265 #define GPIO_LCKR_LCK12_Pos (12U)
15266 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
15267 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
15268 #define GPIO_LCKR_LCK13_Pos (13U)
15269 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
15270 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
15271 #define GPIO_LCKR_LCK14_Pos (14U)
15272 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
15273 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
15274 #define GPIO_LCKR_LCK15_Pos (15U)
15275 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
15276 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
15277 #define GPIO_LCKR_LCKK_Pos (16U)
15278 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
15279 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
15280
15281 /****************** Bit definition for GPIO_AFRL register ********************/
15282 #define GPIO_AFRL_AFSEL0_Pos (0U)
15283 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
15284 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
15285 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
15286 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
15287 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
15288 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
15289 #define GPIO_AFRL_AFSEL1_Pos (4U)
15290 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
15291 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
15292 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
15293 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
15294 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
15295 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
15296 #define GPIO_AFRL_AFSEL2_Pos (8U)
15297 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
15298 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
15299 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
15300 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
15301 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
15302 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
15303 #define GPIO_AFRL_AFSEL3_Pos (12U)
15304 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
15305 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
15306 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
15307 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
15308 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
15309 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
15310 #define GPIO_AFRL_AFSEL4_Pos (16U)
15311 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
15312 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
15313 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
15314 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
15315 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
15316 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
15317 #define GPIO_AFRL_AFSEL5_Pos (20U)
15318 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
15319 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
15320 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
15321 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
15322 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
15323 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
15324 #define GPIO_AFRL_AFSEL6_Pos (24U)
15325 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
15326 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
15327 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
15328 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
15329 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
15330 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
15331 #define GPIO_AFRL_AFSEL7_Pos (28U)
15332 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
15333 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
15334 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
15335 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
15336 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
15337 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
15338
15339 /* Legacy defines */
15340 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
15341 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
15342 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
15343 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
15344 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
15345 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
15346 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
15347 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
15348
15349 /****************** Bit definition for GPIO_AFRH register ********************/
15350 #define GPIO_AFRH_AFSEL8_Pos (0U)
15351 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
15352 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
15353 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
15354 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
15355 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
15356 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
15357 #define GPIO_AFRH_AFSEL9_Pos (4U)
15358 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
15359 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
15360 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
15361 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
15362 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
15363 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
15364 #define GPIO_AFRH_AFSEL10_Pos (8U)
15365 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
15366 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
15367 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
15368 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
15369 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
15370 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
15371 #define GPIO_AFRH_AFSEL11_Pos (12U)
15372 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
15373 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
15374 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
15375 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
15376 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
15377 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
15378 #define GPIO_AFRH_AFSEL12_Pos (16U)
15379 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
15380 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
15381 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
15382 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
15383 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
15384 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
15385 #define GPIO_AFRH_AFSEL13_Pos (20U)
15386 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
15387 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
15388 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
15389 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
15390 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
15391 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
15392 #define GPIO_AFRH_AFSEL14_Pos (24U)
15393 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
15394 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
15395 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
15396 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
15397 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
15398 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
15399 #define GPIO_AFRH_AFSEL15_Pos (28U)
15400 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
15401 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
15402 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
15403 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
15404 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
15405 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
15406
15407 /* Legacy defines */
15408 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
15409 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
15410 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
15411 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
15412 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
15413 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
15414 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
15415 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
15416
15417 /******************************************************************************/
15418 /* */
15419 /* HSEM HW Semaphore */
15420 /* */
15421 /******************************************************************************/
15422 /******************** Bit definition for HSEM_R register ********************/
15423 #define HSEM_R_PROCID_Pos (0U)
15424 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
15425 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
15426 #define HSEM_R_COREID_Pos (8U)
15427 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
15428 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
15429 #define HSEM_R_LOCK_Pos (31U)
15430 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
15431 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
15432
15433 /******************** Bit definition for HSEM_RLR register ******************/
15434 #define HSEM_RLR_PROCID_Pos (0U)
15435 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
15436 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
15437 #define HSEM_RLR_COREID_Pos (8U)
15438 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
15439 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
15440 #define HSEM_RLR_LOCK_Pos (31U)
15441 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
15442 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
15443
15444 /******************** Bit definition for HSEM_C1IER register *****************/
15445 #define HSEM_C1IER_ISE0_Pos (0U)
15446 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
15447 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
15448 #define HSEM_C1IER_ISE1_Pos (1U)
15449 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
15450 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
15451 #define HSEM_C1IER_ISE2_Pos (2U)
15452 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
15453 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
15454 #define HSEM_C1IER_ISE3_Pos (3U)
15455 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
15456 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
15457 #define HSEM_C1IER_ISE4_Pos (4U)
15458 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
15459 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
15460 #define HSEM_C1IER_ISE5_Pos (5U)
15461 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
15462 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
15463 #define HSEM_C1IER_ISE6_Pos (6U)
15464 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
15465 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
15466 #define HSEM_C1IER_ISE7_Pos (7U)
15467 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
15468 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
15469 #define HSEM_C1IER_ISE8_Pos (8U)
15470 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
15471 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
15472 #define HSEM_C1IER_ISE9_Pos (9U)
15473 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
15474 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
15475 #define HSEM_C1IER_ISE10_Pos (10U)
15476 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
15477 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
15478 #define HSEM_C1IER_ISE11_Pos (11U)
15479 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
15480 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
15481 #define HSEM_C1IER_ISE12_Pos (12U)
15482 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
15483 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
15484 #define HSEM_C1IER_ISE13_Pos (13U)
15485 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
15486 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
15487 #define HSEM_C1IER_ISE14_Pos (14U)
15488 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
15489 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
15490 #define HSEM_C1IER_ISE15_Pos (15U)
15491 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
15492 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
15493 #define HSEM_C1IER_ISE16_Pos (16U)
15494 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
15495 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
15496 #define HSEM_C1IER_ISE17_Pos (17U)
15497 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
15498 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
15499 #define HSEM_C1IER_ISE18_Pos (18U)
15500 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
15501 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
15502 #define HSEM_C1IER_ISE19_Pos (19U)
15503 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
15504 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
15505 #define HSEM_C1IER_ISE20_Pos (20U)
15506 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
15507 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
15508 #define HSEM_C1IER_ISE21_Pos (21U)
15509 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
15510 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
15511 #define HSEM_C1IER_ISE22_Pos (22U)
15512 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
15513 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
15514 #define HSEM_C1IER_ISE23_Pos (23U)
15515 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
15516 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
15517 #define HSEM_C1IER_ISE24_Pos (24U)
15518 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
15519 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
15520 #define HSEM_C1IER_ISE25_Pos (25U)
15521 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
15522 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
15523 #define HSEM_C1IER_ISE26_Pos (26U)
15524 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
15525 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
15526 #define HSEM_C1IER_ISE27_Pos (27U)
15527 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
15528 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
15529 #define HSEM_C1IER_ISE28_Pos (28U)
15530 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
15531 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
15532 #define HSEM_C1IER_ISE29_Pos (29U)
15533 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
15534 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
15535 #define HSEM_C1IER_ISE30_Pos (30U)
15536 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
15537 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
15538 #define HSEM_C1IER_ISE31_Pos (31U)
15539 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
15540 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
15541
15542 /******************** Bit definition for HSEM_C1ICR register *****************/
15543 #define HSEM_C1ICR_ISC0_Pos (0U)
15544 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
15545 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
15546 #define HSEM_C1ICR_ISC1_Pos (1U)
15547 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
15548 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
15549 #define HSEM_C1ICR_ISC2_Pos (2U)
15550 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
15551 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
15552 #define HSEM_C1ICR_ISC3_Pos (3U)
15553 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
15554 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
15555 #define HSEM_C1ICR_ISC4_Pos (4U)
15556 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
15557 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
15558 #define HSEM_C1ICR_ISC5_Pos (5U)
15559 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
15560 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
15561 #define HSEM_C1ICR_ISC6_Pos (6U)
15562 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
15563 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
15564 #define HSEM_C1ICR_ISC7_Pos (7U)
15565 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
15566 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
15567 #define HSEM_C1ICR_ISC8_Pos (8U)
15568 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
15569 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
15570 #define HSEM_C1ICR_ISC9_Pos (9U)
15571 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
15572 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
15573 #define HSEM_C1ICR_ISC10_Pos (10U)
15574 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
15575 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
15576 #define HSEM_C1ICR_ISC11_Pos (11U)
15577 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
15578 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
15579 #define HSEM_C1ICR_ISC12_Pos (12U)
15580 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
15581 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
15582 #define HSEM_C1ICR_ISC13_Pos (13U)
15583 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
15584 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
15585 #define HSEM_C1ICR_ISC14_Pos (14U)
15586 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
15587 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
15588 #define HSEM_C1ICR_ISC15_Pos (15U)
15589 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
15590 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
15591 #define HSEM_C1ICR_ISC16_Pos (16U)
15592 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
15593 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
15594 #define HSEM_C1ICR_ISC17_Pos (17U)
15595 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
15596 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
15597 #define HSEM_C1ICR_ISC18_Pos (18U)
15598 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
15599 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
15600 #define HSEM_C1ICR_ISC19_Pos (19U)
15601 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
15602 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
15603 #define HSEM_C1ICR_ISC20_Pos (20U)
15604 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
15605 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
15606 #define HSEM_C1ICR_ISC21_Pos (21U)
15607 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
15608 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
15609 #define HSEM_C1ICR_ISC22_Pos (22U)
15610 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
15611 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
15612 #define HSEM_C1ICR_ISC23_Pos (23U)
15613 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
15614 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
15615 #define HSEM_C1ICR_ISC24_Pos (24U)
15616 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
15617 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
15618 #define HSEM_C1ICR_ISC25_Pos (25U)
15619 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
15620 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
15621 #define HSEM_C1ICR_ISC26_Pos (26U)
15622 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
15623 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
15624 #define HSEM_C1ICR_ISC27_Pos (27U)
15625 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
15626 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
15627 #define HSEM_C1ICR_ISC28_Pos (28U)
15628 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
15629 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
15630 #define HSEM_C1ICR_ISC29_Pos (29U)
15631 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
15632 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
15633 #define HSEM_C1ICR_ISC30_Pos (30U)
15634 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
15635 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
15636 #define HSEM_C1ICR_ISC31_Pos (31U)
15637 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
15638 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
15639
15640 /******************** Bit definition for HSEM_C1ISR register *****************/
15641 #define HSEM_C1ISR_ISF0_Pos (0U)
15642 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
15643 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
15644 #define HSEM_C1ISR_ISF1_Pos (1U)
15645 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
15646 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
15647 #define HSEM_C1ISR_ISF2_Pos (2U)
15648 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
15649 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
15650 #define HSEM_C1ISR_ISF3_Pos (3U)
15651 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
15652 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
15653 #define HSEM_C1ISR_ISF4_Pos (4U)
15654 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
15655 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
15656 #define HSEM_C1ISR_ISF5_Pos (5U)
15657 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
15658 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
15659 #define HSEM_C1ISR_ISF6_Pos (6U)
15660 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
15661 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
15662 #define HSEM_C1ISR_ISF7_Pos (7U)
15663 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
15664 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
15665 #define HSEM_C1ISR_ISF8_Pos (8U)
15666 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
15667 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
15668 #define HSEM_C1ISR_ISF9_Pos (9U)
15669 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
15670 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
15671 #define HSEM_C1ISR_ISF10_Pos (10U)
15672 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
15673 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
15674 #define HSEM_C1ISR_ISF11_Pos (11U)
15675 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
15676 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
15677 #define HSEM_C1ISR_ISF12_Pos (12U)
15678 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
15679 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
15680 #define HSEM_C1ISR_ISF13_Pos (13U)
15681 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
15682 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
15683 #define HSEM_C1ISR_ISF14_Pos (14U)
15684 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
15685 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
15686 #define HSEM_C1ISR_ISF15_Pos (15U)
15687 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
15688 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
15689 #define HSEM_C1ISR_ISF16_Pos (16U)
15690 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
15691 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
15692 #define HSEM_C1ISR_ISF17_Pos (17U)
15693 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
15694 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
15695 #define HSEM_C1ISR_ISF18_Pos (18U)
15696 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
15697 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
15698 #define HSEM_C1ISR_ISF19_Pos (19U)
15699 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
15700 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
15701 #define HSEM_C1ISR_ISF20_Pos (20U)
15702 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
15703 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
15704 #define HSEM_C1ISR_ISF21_Pos (21U)
15705 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
15706 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
15707 #define HSEM_C1ISR_ISF22_Pos (22U)
15708 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
15709 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
15710 #define HSEM_C1ISR_ISF23_Pos (23U)
15711 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
15712 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
15713 #define HSEM_C1ISR_ISF24_Pos (24U)
15714 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
15715 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
15716 #define HSEM_C1ISR_ISF25_Pos (25U)
15717 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
15718 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
15719 #define HSEM_C1ISR_ISF26_Pos (26U)
15720 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
15721 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
15722 #define HSEM_C1ISR_ISF27_Pos (27U)
15723 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
15724 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
15725 #define HSEM_C1ISR_ISF28_Pos (28U)
15726 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
15727 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
15728 #define HSEM_C1ISR_ISF29_Pos (29U)
15729 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
15730 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
15731 #define HSEM_C1ISR_ISF30_Pos (30U)
15732 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
15733 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
15734 #define HSEM_C1ISR_ISF31_Pos (31U)
15735 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
15736 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
15737
15738 /******************** Bit definition for HSEM_C1MISR register *****************/
15739 #define HSEM_C1MISR_MISF0_Pos (0U)
15740 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
15741 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
15742 #define HSEM_C1MISR_MISF1_Pos (1U)
15743 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
15744 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
15745 #define HSEM_C1MISR_MISF2_Pos (2U)
15746 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
15747 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
15748 #define HSEM_C1MISR_MISF3_Pos (3U)
15749 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
15750 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
15751 #define HSEM_C1MISR_MISF4_Pos (4U)
15752 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
15753 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
15754 #define HSEM_C1MISR_MISF5_Pos (5U)
15755 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
15756 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
15757 #define HSEM_C1MISR_MISF6_Pos (6U)
15758 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
15759 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
15760 #define HSEM_C1MISR_MISF7_Pos (7U)
15761 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
15762 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
15763 #define HSEM_C1MISR_MISF8_Pos (8U)
15764 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
15765 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
15766 #define HSEM_C1MISR_MISF9_Pos (9U)
15767 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
15768 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
15769 #define HSEM_C1MISR_MISF10_Pos (10U)
15770 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
15771 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
15772 #define HSEM_C1MISR_MISF11_Pos (11U)
15773 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
15774 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
15775 #define HSEM_C1MISR_MISF12_Pos (12U)
15776 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
15777 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
15778 #define HSEM_C1MISR_MISF13_Pos (13U)
15779 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
15780 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
15781 #define HSEM_C1MISR_MISF14_Pos (14U)
15782 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
15783 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
15784 #define HSEM_C1MISR_MISF15_Pos (15U)
15785 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
15786 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
15787 #define HSEM_C1MISR_MISF16_Pos (16U)
15788 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
15789 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
15790 #define HSEM_C1MISR_MISF17_Pos (17U)
15791 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
15792 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
15793 #define HSEM_C1MISR_MISF18_Pos (18U)
15794 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
15795 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
15796 #define HSEM_C1MISR_MISF19_Pos (19U)
15797 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
15798 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
15799 #define HSEM_C1MISR_MISF20_Pos (20U)
15800 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
15801 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
15802 #define HSEM_C1MISR_MISF21_Pos (21U)
15803 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
15804 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
15805 #define HSEM_C1MISR_MISF22_Pos (22U)
15806 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
15807 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
15808 #define HSEM_C1MISR_MISF23_Pos (23U)
15809 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
15810 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
15811 #define HSEM_C1MISR_MISF24_Pos (24U)
15812 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
15813 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
15814 #define HSEM_C1MISR_MISF25_Pos (25U)
15815 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
15816 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
15817 #define HSEM_C1MISR_MISF26_Pos (26U)
15818 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
15819 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
15820 #define HSEM_C1MISR_MISF27_Pos (27U)
15821 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
15822 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
15823 #define HSEM_C1MISR_MISF28_Pos (28U)
15824 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
15825 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
15826 #define HSEM_C1MISR_MISF29_Pos (29U)
15827 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
15828 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
15829 #define HSEM_C1MISR_MISF30_Pos (30U)
15830 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
15831 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
15832 #define HSEM_C1MISR_MISF31_Pos (31U)
15833 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
15834 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
15835
15836 /******************** Bit definition for HSEM_C2IER register *****************/
15837 #define HSEM_C2IER_ISE0_Pos (0U)
15838 #define HSEM_C2IER_ISE0_Msk (0x1UL << HSEM_C2IER_ISE0_Pos) /*!< 0x00000001 */
15839 #define HSEM_C2IER_ISE0 HSEM_C2IER_ISE0_Msk /*!<semaphore 0 , interrupt 1 enable bit. */
15840 #define HSEM_C2IER_ISE1_Pos (1U)
15841 #define HSEM_C2IER_ISE1_Msk (0x1UL << HSEM_C2IER_ISE1_Pos) /*!< 0x00000002 */
15842 #define HSEM_C2IER_ISE1 HSEM_C2IER_ISE1_Msk /*!<semaphore 1 , interrupt 1 enable bit. */
15843 #define HSEM_C2IER_ISE2_Pos (2U)
15844 #define HSEM_C2IER_ISE2_Msk (0x1UL << HSEM_C2IER_ISE2_Pos) /*!< 0x00000004 */
15845 #define HSEM_C2IER_ISE2 HSEM_C2IER_ISE2_Msk /*!<semaphore 2 , interrupt 1 enable bit. */
15846 #define HSEM_C2IER_ISE3_Pos (3U)
15847 #define HSEM_C2IER_ISE3_Msk (0x1UL << HSEM_C2IER_ISE3_Pos) /*!< 0x00000008 */
15848 #define HSEM_C2IER_ISE3 HSEM_C2IER_ISE3_Msk /*!<semaphore 3 , interrupt 1 enable bit. */
15849 #define HSEM_C2IER_ISE4_Pos (4U)
15850 #define HSEM_C2IER_ISE4_Msk (0x1UL << HSEM_C2IER_ISE4_Pos) /*!< 0x00000010 */
15851 #define HSEM_C2IER_ISE4 HSEM_C2IER_ISE4_Msk /*!<semaphore 4 , interrupt 1 enable bit. */
15852 #define HSEM_C2IER_ISE5_Pos (5U)
15853 #define HSEM_C2IER_ISE5_Msk (0x1UL << HSEM_C2IER_ISE5_Pos) /*!< 0x00000020 */
15854 #define HSEM_C2IER_ISE5 HSEM_C2IER_ISE5_Msk /*!<semaphore 5 interrupt 1 enable bit. */
15855 #define HSEM_C2IER_ISE6_Pos (6U)
15856 #define HSEM_C2IER_ISE6_Msk (0x1UL << HSEM_C2IER_ISE6_Pos) /*!< 0x00000040 */
15857 #define HSEM_C2IER_ISE6 HSEM_C2IER_ISE6_Msk /*!<semaphore 6 interrupt 1 enable bit. */
15858 #define HSEM_C2IER_ISE7_Pos (7U)
15859 #define HSEM_C2IER_ISE7_Msk (0x1UL << HSEM_C2IER_ISE7_Pos) /*!< 0x00000080 */
15860 #define HSEM_C2IER_ISE7 HSEM_C2IER_ISE7_Msk /*!<semaphore 7 interrupt 1 enable bit. */
15861 #define HSEM_C2IER_ISE8_Pos (8U)
15862 #define HSEM_C2IER_ISE8_Msk (0x1UL << HSEM_C2IER_ISE8_Pos) /*!< 0x00000100 */
15863 #define HSEM_C2IER_ISE8 HSEM_C2IER_ISE8_Msk /*!<semaphore 8 interrupt 1 enable bit. */
15864 #define HSEM_C2IER_ISE9_Pos (9U)
15865 #define HSEM_C2IER_ISE9_Msk (0x1UL << HSEM_C2IER_ISE9_Pos) /*!< 0x00000200 */
15866 #define HSEM_C2IER_ISE9 HSEM_C2IER_ISE9_Msk /*!<semaphore 9 interrupt 1 enable bit. */
15867 #define HSEM_C2IER_ISE10_Pos (10U)
15868 #define HSEM_C2IER_ISE10_Msk (0x1UL << HSEM_C2IER_ISE10_Pos) /*!< 0x00000400 */
15869 #define HSEM_C2IER_ISE10 HSEM_C2IER_ISE10_Msk /*!<semaphore 10 interrupt 1 enable bit. */
15870 #define HSEM_C2IER_ISE11_Pos (11U)
15871 #define HSEM_C2IER_ISE11_Msk (0x1UL << HSEM_C2IER_ISE11_Pos) /*!< 0x00000800 */
15872 #define HSEM_C2IER_ISE11 HSEM_C2IER_ISE11_Msk /*!<semaphore 11 interrupt 1 enable bit. */
15873 #define HSEM_C2IER_ISE12_Pos (12U)
15874 #define HSEM_C2IER_ISE12_Msk (0x1UL << HSEM_C2IER_ISE12_Pos) /*!< 0x00001000 */
15875 #define HSEM_C2IER_ISE12 HSEM_C2IER_ISE12_Msk /*!<semaphore 12 interrupt 1 enable bit. */
15876 #define HSEM_C2IER_ISE13_Pos (13U)
15877 #define HSEM_C2IER_ISE13_Msk (0x1UL << HSEM_C2IER_ISE13_Pos) /*!< 0x00002000 */
15878 #define HSEM_C2IER_ISE13 HSEM_C2IER_ISE13_Msk /*!<semaphore 13 interrupt 1 enable bit. */
15879 #define HSEM_C2IER_ISE14_Pos (14U)
15880 #define HSEM_C2IER_ISE14_Msk (0x1UL << HSEM_C2IER_ISE14_Pos) /*!< 0x00004000 */
15881 #define HSEM_C2IER_ISE14 HSEM_C2IER_ISE14_Msk /*!<semaphore 14 interrupt 1 enable bit. */
15882 #define HSEM_C2IER_ISE15_Pos (15U)
15883 #define HSEM_C2IER_ISE15_Msk (0x1UL << HSEM_C2IER_ISE15_Pos) /*!< 0x00008000 */
15884 #define HSEM_C2IER_ISE15 HSEM_C2IER_ISE15_Msk /*!<semaphore 15 interrupt 1 enable bit. */
15885 #define HSEM_C2IER_ISE16_Pos (16U)
15886 #define HSEM_C2IER_ISE16_Msk (0x1UL << HSEM_C2IER_ISE16_Pos) /*!< 0x00010000 */
15887 #define HSEM_C2IER_ISE16 HSEM_C2IER_ISE16_Msk /*!<semaphore 16 interrupt 1 enable bit. */
15888 #define HSEM_C2IER_ISE17_Pos (17U)
15889 #define HSEM_C2IER_ISE17_Msk (0x1UL << HSEM_C2IER_ISE17_Pos) /*!< 0x00020000 */
15890 #define HSEM_C2IER_ISE17 HSEM_C2IER_ISE17_Msk /*!<semaphore 17 interrupt 1 enable bit. */
15891 #define HSEM_C2IER_ISE18_Pos (18U)
15892 #define HSEM_C2IER_ISE18_Msk (0x1UL << HSEM_C2IER_ISE18_Pos) /*!< 0x00040000 */
15893 #define HSEM_C2IER_ISE18 HSEM_C2IER_ISE18_Msk /*!<semaphore 18 interrupt 1 enable bit. */
15894 #define HSEM_C2IER_ISE19_Pos (19U)
15895 #define HSEM_C2IER_ISE19_Msk (0x1UL << HSEM_C2IER_ISE19_Pos) /*!< 0x00080000 */
15896 #define HSEM_C2IER_ISE19 HSEM_C2IER_ISE19_Msk /*!<semaphore 19 interrupt 1 enable bit. */
15897 #define HSEM_C2IER_ISE20_Pos (20U)
15898 #define HSEM_C2IER_ISE20_Msk (0x1UL << HSEM_C2IER_ISE20_Pos) /*!< 0x00100000 */
15899 #define HSEM_C2IER_ISE20 HSEM_C2IER_ISE20_Msk /*!<semaphore 20 interrupt 1 enable bit. */
15900 #define HSEM_C2IER_ISE21_Pos (21U)
15901 #define HSEM_C2IER_ISE21_Msk (0x1UL << HSEM_C2IER_ISE21_Pos) /*!< 0x00200000 */
15902 #define HSEM_C2IER_ISE21 HSEM_C2IER_ISE21_Msk /*!<semaphore 21 interrupt 1 enable bit. */
15903 #define HSEM_C2IER_ISE22_Pos (22U)
15904 #define HSEM_C2IER_ISE22_Msk (0x1UL << HSEM_C2IER_ISE22_Pos) /*!< 0x00400000 */
15905 #define HSEM_C2IER_ISE22 HSEM_C2IER_ISE22_Msk /*!<semaphore 22 interrupt 1 enable bit. */
15906 #define HSEM_C2IER_ISE23_Pos (23U)
15907 #define HSEM_C2IER_ISE23_Msk (0x1UL << HSEM_C2IER_ISE23_Pos) /*!< 0x00800000 */
15908 #define HSEM_C2IER_ISE23 HSEM_C2IER_ISE23_Msk /*!<semaphore 23 interrupt 1 enable bit. */
15909 #define HSEM_C2IER_ISE24_Pos (24U)
15910 #define HSEM_C2IER_ISE24_Msk (0x1UL << HSEM_C2IER_ISE24_Pos) /*!< 0x01000000 */
15911 #define HSEM_C2IER_ISE24 HSEM_C2IER_ISE24_Msk /*!<semaphore 24 interrupt 1 enable bit. */
15912 #define HSEM_C2IER_ISE25_Pos (25U)
15913 #define HSEM_C2IER_ISE25_Msk (0x1UL << HSEM_C2IER_ISE25_Pos) /*!< 0x02000000 */
15914 #define HSEM_C2IER_ISE25 HSEM_C2IER_ISE25_Msk /*!<semaphore 25 interrupt 1 enable bit. */
15915 #define HSEM_C2IER_ISE26_Pos (26U)
15916 #define HSEM_C2IER_ISE26_Msk (0x1UL << HSEM_C2IER_ISE26_Pos) /*!< 0x04000000 */
15917 #define HSEM_C2IER_ISE26 HSEM_C2IER_ISE26_Msk /*!<semaphore 26 interrupt 1 enable bit. */
15918 #define HSEM_C2IER_ISE27_Pos (27U)
15919 #define HSEM_C2IER_ISE27_Msk (0x1UL << HSEM_C2IER_ISE27_Pos) /*!< 0x08000000 */
15920 #define HSEM_C2IER_ISE27 HSEM_C2IER_ISE27_Msk /*!<semaphore 27 interrupt 1 enable bit. */
15921 #define HSEM_C2IER_ISE28_Pos (28U)
15922 #define HSEM_C2IER_ISE28_Msk (0x1UL << HSEM_C2IER_ISE28_Pos) /*!< 0x10000000 */
15923 #define HSEM_C2IER_ISE28 HSEM_C2IER_ISE28_Msk /*!<semaphore 28 interrupt 1 enable bit. */
15924 #define HSEM_C2IER_ISE29_Pos (29U)
15925 #define HSEM_C2IER_ISE29_Msk (0x1UL << HSEM_C2IER_ISE29_Pos) /*!< 0x20000000 */
15926 #define HSEM_C2IER_ISE29 HSEM_C2IER_ISE29_Msk /*!<semaphore 29 interrupt 1 enable bit. */
15927 #define HSEM_C2IER_ISE30_Pos (30U)
15928 #define HSEM_C2IER_ISE30_Msk (0x1UL << HSEM_C2IER_ISE30_Pos) /*!< 0x40000000 */
15929 #define HSEM_C2IER_ISE30 HSEM_C2IER_ISE30_Msk /*!<semaphore 30 interrupt 1 enable bit. */
15930 #define HSEM_C2IER_ISE31_Pos (31U)
15931 #define HSEM_C2IER_ISE31_Msk (0x1UL << HSEM_C2IER_ISE31_Pos) /*!< 0x80000000 */
15932 #define HSEM_C2IER_ISE31 HSEM_C2IER_ISE31_Msk /*!<semaphore 31 interrupt 1 enable bit. */
15933
15934 /******************** Bit definition for HSEM_C2ICR register *****************/
15935 #define HSEM_C2ICR_ISC0_Pos (0U)
15936 #define HSEM_C2ICR_ISC0_Msk (0x1UL << HSEM_C2ICR_ISC0_Pos) /*!< 0x00000001 */
15937 #define HSEM_C2ICR_ISC0 HSEM_C2ICR_ISC0_Msk /*!<semaphore 0 , interrupt 1 clear bit. */
15938 #define HSEM_C2ICR_ISC1_Pos (1U)
15939 #define HSEM_C2ICR_ISC1_Msk (0x1UL << HSEM_C2ICR_ISC1_Pos) /*!< 0x00000002 */
15940 #define HSEM_C2ICR_ISC1 HSEM_C2ICR_ISC1_Msk /*!<semaphore 1 , interrupt 1 clear bit. */
15941 #define HSEM_C2ICR_ISC2_Pos (2U)
15942 #define HSEM_C2ICR_ISC2_Msk (0x1UL << HSEM_C2ICR_ISC2_Pos) /*!< 0x00000004 */
15943 #define HSEM_C2ICR_ISC2 HSEM_C2ICR_ISC2_Msk /*!<semaphore 2 , interrupt 1 clear bit. */
15944 #define HSEM_C2ICR_ISC3_Pos (3U)
15945 #define HSEM_C2ICR_ISC3_Msk (0x1UL << HSEM_C2ICR_ISC3_Pos) /*!< 0x00000008 */
15946 #define HSEM_C2ICR_ISC3 HSEM_C2ICR_ISC3_Msk /*!<semaphore 3 , interrupt 1 clear bit. */
15947 #define HSEM_C2ICR_ISC4_Pos (4U)
15948 #define HSEM_C2ICR_ISC4_Msk (0x1UL << HSEM_C2ICR_ISC4_Pos) /*!< 0x00000010 */
15949 #define HSEM_C2ICR_ISC4 HSEM_C2ICR_ISC4_Msk /*!<semaphore 4 , interrupt 1 clear bit. */
15950 #define HSEM_C2ICR_ISC5_Pos (5U)
15951 #define HSEM_C2ICR_ISC5_Msk (0x1UL << HSEM_C2ICR_ISC5_Pos) /*!< 0x00000020 */
15952 #define HSEM_C2ICR_ISC5 HSEM_C2ICR_ISC5_Msk /*!<semaphore 5 interrupt 1 clear bit. */
15953 #define HSEM_C2ICR_ISC6_Pos (6U)
15954 #define HSEM_C2ICR_ISC6_Msk (0x1UL << HSEM_C2ICR_ISC6_Pos) /*!< 0x00000040 */
15955 #define HSEM_C2ICR_ISC6 HSEM_C2ICR_ISC6_Msk /*!<semaphore 6 interrupt 1 clear bit. */
15956 #define HSEM_C2ICR_ISC7_Pos (7U)
15957 #define HSEM_C2ICR_ISC7_Msk (0x1UL << HSEM_C2ICR_ISC7_Pos) /*!< 0x00000080 */
15958 #define HSEM_C2ICR_ISC7 HSEM_C2ICR_ISC7_Msk /*!<semaphore 7 interrupt 1 clear bit. */
15959 #define HSEM_C2ICR_ISC8_Pos (8U)
15960 #define HSEM_C2ICR_ISC8_Msk (0x1UL << HSEM_C2ICR_ISC8_Pos) /*!< 0x00000100 */
15961 #define HSEM_C2ICR_ISC8 HSEM_C2ICR_ISC8_Msk /*!<semaphore 8 interrupt 1 clear bit. */
15962 #define HSEM_C2ICR_ISC9_Pos (9U)
15963 #define HSEM_C2ICR_ISC9_Msk (0x1UL << HSEM_C2ICR_ISC9_Pos) /*!< 0x00000200 */
15964 #define HSEM_C2ICR_ISC9 HSEM_C2ICR_ISC9_Msk /*!<semaphore 9 interrupt 1 clear bit. */
15965 #define HSEM_C2ICR_ISC10_Pos (10U)
15966 #define HSEM_C2ICR_ISC10_Msk (0x1UL << HSEM_C2ICR_ISC10_Pos) /*!< 0x00000400 */
15967 #define HSEM_C2ICR_ISC10 HSEM_C2ICR_ISC10_Msk /*!<semaphore 10 interrupt 1 clear bit. */
15968 #define HSEM_C2ICR_ISC11_Pos (11U)
15969 #define HSEM_C2ICR_ISC11_Msk (0x1UL << HSEM_C2ICR_ISC11_Pos) /*!< 0x00000800 */
15970 #define HSEM_C2ICR_ISC11 HSEM_C2ICR_ISC11_Msk /*!<semaphore 11 interrupt 1 clear bit. */
15971 #define HSEM_C2ICR_ISC12_Pos (12U)
15972 #define HSEM_C2ICR_ISC12_Msk (0x1UL << HSEM_C2ICR_ISC12_Pos) /*!< 0x00001000 */
15973 #define HSEM_C2ICR_ISC12 HSEM_C2ICR_ISC12_Msk /*!<semaphore 12 interrupt 1 clear bit. */
15974 #define HSEM_C2ICR_ISC13_Pos (13U)
15975 #define HSEM_C2ICR_ISC13_Msk (0x1UL << HSEM_C2ICR_ISC13_Pos) /*!< 0x00002000 */
15976 #define HSEM_C2ICR_ISC13 HSEM_C2ICR_ISC13_Msk /*!<semaphore 13 interrupt 1 clear bit. */
15977 #define HSEM_C2ICR_ISC14_Pos (14U)
15978 #define HSEM_C2ICR_ISC14_Msk (0x1UL << HSEM_C2ICR_ISC14_Pos) /*!< 0x00004000 */
15979 #define HSEM_C2ICR_ISC14 HSEM_C2ICR_ISC14_Msk /*!<semaphore 14 interrupt 1 clear bit. */
15980 #define HSEM_C2ICR_ISC15_Pos (15U)
15981 #define HSEM_C2ICR_ISC15_Msk (0x1UL << HSEM_C2ICR_ISC15_Pos) /*!< 0x00008000 */
15982 #define HSEM_C2ICR_ISC15 HSEM_C2ICR_ISC15_Msk /*!<semaphore 15 interrupt 1 clear bit. */
15983 #define HSEM_C2ICR_ISC16_Pos (16U)
15984 #define HSEM_C2ICR_ISC16_Msk (0x1UL << HSEM_C2ICR_ISC16_Pos) /*!< 0x00010000 */
15985 #define HSEM_C2ICR_ISC16 HSEM_C2ICR_ISC16_Msk /*!<semaphore 16 interrupt 1 clear bit. */
15986 #define HSEM_C2ICR_ISC17_Pos (17U)
15987 #define HSEM_C2ICR_ISC17_Msk (0x1UL << HSEM_C2ICR_ISC17_Pos) /*!< 0x00020000 */
15988 #define HSEM_C2ICR_ISC17 HSEM_C2ICR_ISC17_Msk /*!<semaphore 17 interrupt 1 clear bit. */
15989 #define HSEM_C2ICR_ISC18_Pos (18U)
15990 #define HSEM_C2ICR_ISC18_Msk (0x1UL << HSEM_C2ICR_ISC18_Pos) /*!< 0x00040000 */
15991 #define HSEM_C2ICR_ISC18 HSEM_C2ICR_ISC18_Msk /*!<semaphore 18 interrupt 1 clear bit. */
15992 #define HSEM_C2ICR_ISC19_Pos (19U)
15993 #define HSEM_C2ICR_ISC19_Msk (0x1UL << HSEM_C2ICR_ISC19_Pos) /*!< 0x00080000 */
15994 #define HSEM_C2ICR_ISC19 HSEM_C2ICR_ISC19_Msk /*!<semaphore 19 interrupt 1 clear bit. */
15995 #define HSEM_C2ICR_ISC20_Pos (20U)
15996 #define HSEM_C2ICR_ISC20_Msk (0x1UL << HSEM_C2ICR_ISC20_Pos) /*!< 0x00100000 */
15997 #define HSEM_C2ICR_ISC20 HSEM_C2ICR_ISC20_Msk /*!<semaphore 20 interrupt 1 clear bit. */
15998 #define HSEM_C2ICR_ISC21_Pos (21U)
15999 #define HSEM_C2ICR_ISC21_Msk (0x1UL << HSEM_C2ICR_ISC21_Pos) /*!< 0x00200000 */
16000 #define HSEM_C2ICR_ISC21 HSEM_C2ICR_ISC21_Msk /*!<semaphore 21 interrupt 1 clear bit. */
16001 #define HSEM_C2ICR_ISC22_Pos (22U)
16002 #define HSEM_C2ICR_ISC22_Msk (0x1UL << HSEM_C2ICR_ISC22_Pos) /*!< 0x00400000 */
16003 #define HSEM_C2ICR_ISC22 HSEM_C2ICR_ISC22_Msk /*!<semaphore 22 interrupt 1 clear bit. */
16004 #define HSEM_C2ICR_ISC23_Pos (23U)
16005 #define HSEM_C2ICR_ISC23_Msk (0x1UL << HSEM_C2ICR_ISC23_Pos) /*!< 0x00800000 */
16006 #define HSEM_C2ICR_ISC23 HSEM_C2ICR_ISC23_Msk /*!<semaphore 23 interrupt 1 clear bit. */
16007 #define HSEM_C2ICR_ISC24_Pos (24U)
16008 #define HSEM_C2ICR_ISC24_Msk (0x1UL << HSEM_C2ICR_ISC24_Pos) /*!< 0x01000000 */
16009 #define HSEM_C2ICR_ISC24 HSEM_C2ICR_ISC24_Msk /*!<semaphore 24 interrupt 1 clear bit. */
16010 #define HSEM_C2ICR_ISC25_Pos (25U)
16011 #define HSEM_C2ICR_ISC25_Msk (0x1UL << HSEM_C2ICR_ISC25_Pos) /*!< 0x02000000 */
16012 #define HSEM_C2ICR_ISC25 HSEM_C2ICR_ISC25_Msk /*!<semaphore 25 interrupt 1 clear bit. */
16013 #define HSEM_C2ICR_ISC26_Pos (26U)
16014 #define HSEM_C2ICR_ISC26_Msk (0x1UL << HSEM_C2ICR_ISC26_Pos) /*!< 0x04000000 */
16015 #define HSEM_C2ICR_ISC26 HSEM_C2ICR_ISC26_Msk /*!<semaphore 26 interrupt 1 clear bit. */
16016 #define HSEM_C2ICR_ISC27_Pos (27U)
16017 #define HSEM_C2ICR_ISC27_Msk (0x1UL << HSEM_C2ICR_ISC27_Pos) /*!< 0x08000000 */
16018 #define HSEM_C2ICR_ISC27 HSEM_C2ICR_ISC27_Msk /*!<semaphore 27 interrupt 1 clear bit. */
16019 #define HSEM_C2ICR_ISC28_Pos (28U)
16020 #define HSEM_C2ICR_ISC28_Msk (0x1UL << HSEM_C2ICR_ISC28_Pos) /*!< 0x10000000 */
16021 #define HSEM_C2ICR_ISC28 HSEM_C2ICR_ISC28_Msk /*!<semaphore 28 interrupt 1 clear bit. */
16022 #define HSEM_C2ICR_ISC29_Pos (29U)
16023 #define HSEM_C2ICR_ISC29_Msk (0x1UL << HSEM_C2ICR_ISC29_Pos) /*!< 0x20000000 */
16024 #define HSEM_C2ICR_ISC29 HSEM_C2ICR_ISC29_Msk /*!<semaphore 29 interrupt 1 clear bit. */
16025 #define HSEM_C2ICR_ISC30_Pos (30U)
16026 #define HSEM_C2ICR_ISC30_Msk (0x1UL << HSEM_C2ICR_ISC30_Pos) /*!< 0x40000000 */
16027 #define HSEM_C2ICR_ISC30 HSEM_C2ICR_ISC30_Msk /*!<semaphore 30 interrupt 1 clear bit. */
16028 #define HSEM_C2ICR_ISC31_Pos (31U)
16029 #define HSEM_C2ICR_ISC31_Msk (0x1UL << HSEM_C2ICR_ISC31_Pos) /*!< 0x80000000 */
16030 #define HSEM_C2ICR_ISC31 HSEM_C2ICR_ISC31_Msk /*!<semaphore 31 interrupt 1 clear bit. */
16031
16032 /******************** Bit definition for HSEM_C2ISR register *****************/
16033 #define HSEM_C2ISR_ISF0_Pos (0U)
16034 #define HSEM_C2ISR_ISF0_Msk (0x1UL << HSEM_C2ISR_ISF0_Pos) /*!< 0x00000001 */
16035 #define HSEM_C2ISR_ISF0 HSEM_C2ISR_ISF0_Msk /*!<semaphore 0 interrupt 1 status bit. */
16036 #define HSEM_C2ISR_ISF1_Pos (1U)
16037 #define HSEM_C2ISR_ISF1_Msk (0x1UL << HSEM_C2ISR_ISF1_Pos) /*!< 0x00000002 */
16038 #define HSEM_C2ISR_ISF1 HSEM_C2ISR_ISF1_Msk /*!<semaphore 1 interrupt 1 status bit. */
16039 #define HSEM_C2ISR_ISF2_Pos (2U)
16040 #define HSEM_C2ISR_ISF2_Msk (0x1UL << HSEM_C2ISR_ISF2_Pos) /*!< 0x00000004 */
16041 #define HSEM_C2ISR_ISF2 HSEM_C2ISR_ISF2_Msk /*!<semaphore 2 interrupt 1 status bit. */
16042 #define HSEM_C2ISR_ISF3_Pos (3U)
16043 #define HSEM_C2ISR_ISF3_Msk (0x1UL << HSEM_C2ISR_ISF3_Pos) /*!< 0x00000008 */
16044 #define HSEM_C2ISR_ISF3 HSEM_C2ISR_ISF3_Msk /*!<semaphore 3 interrupt 1 status bit. */
16045 #define HSEM_C2ISR_ISF4_Pos (4U)
16046 #define HSEM_C2ISR_ISF4_Msk (0x1UL << HSEM_C2ISR_ISF4_Pos) /*!< 0x00000010 */
16047 #define HSEM_C2ISR_ISF4 HSEM_C2ISR_ISF4_Msk /*!<semaphore 4 interrupt 1 status bit. */
16048 #define HSEM_C2ISR_ISF5_Pos (5U)
16049 #define HSEM_C2ISR_ISF5_Msk (0x1UL << HSEM_C2ISR_ISF5_Pos) /*!< 0x00000020 */
16050 #define HSEM_C2ISR_ISF5 HSEM_C2ISR_ISF5_Msk /*!<semaphore 5 interrupt 1 status bit. */
16051 #define HSEM_C2ISR_ISF6_Pos (6U)
16052 #define HSEM_C2ISR_ISF6_Msk (0x1UL << HSEM_C2ISR_ISF6_Pos) /*!< 0x00000040 */
16053 #define HSEM_C2ISR_ISF6 HSEM_C2ISR_ISF6_Msk /*!<semaphore 6 interrupt 1 status bit. */
16054 #define HSEM_C2ISR_ISF7_Pos (7U)
16055 #define HSEM_C2ISR_ISF7_Msk (0x1UL << HSEM_C2ISR_ISF7_Pos) /*!< 0x00000080 */
16056 #define HSEM_C2ISR_ISF7 HSEM_C2ISR_ISF7_Msk /*!<semaphore 7 interrupt 1 status bit. */
16057 #define HSEM_C2ISR_ISF8_Pos (8U)
16058 #define HSEM_C2ISR_ISF8_Msk (0x1UL << HSEM_C2ISR_ISF8_Pos) /*!< 0x00000100 */
16059 #define HSEM_C2ISR_ISF8 HSEM_C2ISR_ISF8_Msk /*!<semaphore 8 interrupt 1 status bit. */
16060 #define HSEM_C2ISR_ISF9_Pos (9U)
16061 #define HSEM_C2ISR_ISF9_Msk (0x1UL << HSEM_C2ISR_ISF9_Pos) /*!< 0x00000200 */
16062 #define HSEM_C2ISR_ISF9 HSEM_C2ISR_ISF9_Msk /*!<semaphore 9 interrupt 1 status bit. */
16063 #define HSEM_C2ISR_ISF10_Pos (10U)
16064 #define HSEM_C2ISR_ISF10_Msk (0x1UL << HSEM_C2ISR_ISF10_Pos) /*!< 0x00000400 */
16065 #define HSEM_C2ISR_ISF10 HSEM_C2ISR_ISF10_Msk /*!<semaphore 10 interrupt 1 status bit. */
16066 #define HSEM_C2ISR_ISF11_Pos (11U)
16067 #define HSEM_C2ISR_ISF11_Msk (0x1UL << HSEM_C2ISR_ISF11_Pos) /*!< 0x00000800 */
16068 #define HSEM_C2ISR_ISF11 HSEM_C2ISR_ISF11_Msk /*!<semaphore 11 interrupt 1 status bit. */
16069 #define HSEM_C2ISR_ISF12_Pos (12U)
16070 #define HSEM_C2ISR_ISF12_Msk (0x1UL << HSEM_C2ISR_ISF12_Pos) /*!< 0x00001000 */
16071 #define HSEM_C2ISR_ISF12 HSEM_C2ISR_ISF12_Msk /*!<semaphore 12 interrupt 1 status bit. */
16072 #define HSEM_C2ISR_ISF13_Pos (13U)
16073 #define HSEM_C2ISR_ISF13_Msk (0x1UL << HSEM_C2ISR_ISF13_Pos) /*!< 0x00002000 */
16074 #define HSEM_C2ISR_ISF13 HSEM_C2ISR_ISF13_Msk /*!<semaphore 13 interrupt 1 status bit. */
16075 #define HSEM_C2ISR_ISF14_Pos (14U)
16076 #define HSEM_C2ISR_ISF14_Msk (0x1UL << HSEM_C2ISR_ISF14_Pos) /*!< 0x00004000 */
16077 #define HSEM_C2ISR_ISF14 HSEM_C2ISR_ISF14_Msk /*!<semaphore 14 interrupt 1 status bit. */
16078 #define HSEM_C2ISR_ISF15_Pos (15U)
16079 #define HSEM_C2ISR_ISF15_Msk (0x1UL << HSEM_C2ISR_ISF15_Pos) /*!< 0x00008000 */
16080 #define HSEM_C2ISR_ISF15 HSEM_C2ISR_ISF15_Msk /*!<semaphore 15 interrupt 1 status bit. */
16081 #define HSEM_C2ISR_ISF16_Pos (16U)
16082 #define HSEM_C2ISR_ISF16_Msk (0x1UL << HSEM_C2ISR_ISF16_Pos) /*!< 0x00010000 */
16083 #define HSEM_C2ISR_ISF16 HSEM_C2ISR_ISF16_Msk /*!<semaphore 16 interrupt 1 status bit. */
16084 #define HSEM_C2ISR_ISF17_Pos (17U)
16085 #define HSEM_C2ISR_ISF17_Msk (0x1UL << HSEM_C2ISR_ISF17_Pos) /*!< 0x00020000 */
16086 #define HSEM_C2ISR_ISF17 HSEM_C2ISR_ISF17_Msk /*!<semaphore 17 interrupt 1 status bit. */
16087 #define HSEM_C2ISR_ISF18_Pos (18U)
16088 #define HSEM_C2ISR_ISF18_Msk (0x1UL << HSEM_C2ISR_ISF18_Pos) /*!< 0x00040000 */
16089 #define HSEM_C2ISR_ISF18 HSEM_C2ISR_ISF18_Msk /*!<semaphore 18 interrupt 1 status bit. */
16090 #define HSEM_C2ISR_ISF19_Pos (19U)
16091 #define HSEM_C2ISR_ISF19_Msk (0x1UL << HSEM_C2ISR_ISF19_Pos) /*!< 0x00080000 */
16092 #define HSEM_C2ISR_ISF19 HSEM_C2ISR_ISF19_Msk /*!<semaphore 19 interrupt 1 status bit. */
16093 #define HSEM_C2ISR_ISF20_Pos (20U)
16094 #define HSEM_C2ISR_ISF20_Msk (0x1UL << HSEM_C2ISR_ISF20_Pos) /*!< 0x00100000 */
16095 #define HSEM_C2ISR_ISF20 HSEM_C2ISR_ISF20_Msk /*!<semaphore 20 interrupt 1 status bit. */
16096 #define HSEM_C2ISR_ISF21_Pos (21U)
16097 #define HSEM_C2ISR_ISF21_Msk (0x1UL << HSEM_C2ISR_ISF21_Pos) /*!< 0x00200000 */
16098 #define HSEM_C2ISR_ISF21 HSEM_C2ISR_ISF21_Msk /*!<semaphore 21 interrupt 1 status bit. */
16099 #define HSEM_C2ISR_ISF22_Pos (22U)
16100 #define HSEM_C2ISR_ISF22_Msk (0x1UL << HSEM_C2ISR_ISF22_Pos) /*!< 0x00400000 */
16101 #define HSEM_C2ISR_ISF22 HSEM_C2ISR_ISF22_Msk /*!<semaphore 22 interrupt 1 status bit. */
16102 #define HSEM_C2ISR_ISF23_Pos (23U)
16103 #define HSEM_C2ISR_ISF23_Msk (0x1UL << HSEM_C2ISR_ISF23_Pos) /*!< 0x00800000 */
16104 #define HSEM_C2ISR_ISF23 HSEM_C2ISR_ISF23_Msk /*!<semaphore 23 interrupt 1 status bit. */
16105 #define HSEM_C2ISR_ISF24_Pos (24U)
16106 #define HSEM_C2ISR_ISF24_Msk (0x1UL << HSEM_C2ISR_ISF24_Pos) /*!< 0x01000000 */
16107 #define HSEM_C2ISR_ISF24 HSEM_C2ISR_ISF24_Msk /*!<semaphore 24 interrupt 1 status bit. */
16108 #define HSEM_C2ISR_ISF25_Pos (25U)
16109 #define HSEM_C2ISR_ISF25_Msk (0x1UL << HSEM_C2ISR_ISF25_Pos) /*!< 0x02000000 */
16110 #define HSEM_C2ISR_ISF25 HSEM_C2ISR_ISF25_Msk /*!<semaphore 25 interrupt 1 status bit. */
16111 #define HSEM_C2ISR_ISF26_Pos (26U)
16112 #define HSEM_C2ISR_ISF26_Msk (0x1UL << HSEM_C2ISR_ISF26_Pos) /*!< 0x04000000 */
16113 #define HSEM_C2ISR_ISF26 HSEM_C2ISR_ISF26_Msk /*!<semaphore 26 interrupt 1 status bit. */
16114 #define HSEM_C2ISR_ISF27_Pos (27U)
16115 #define HSEM_C2ISR_ISF27_Msk (0x1UL << HSEM_C2ISR_ISF27_Pos) /*!< 0x08000000 */
16116 #define HSEM_C2ISR_ISF27 HSEM_C2ISR_ISF27_Msk /*!<semaphore 27 interrupt 1 status bit. */
16117 #define HSEM_C2ISR_ISF28_Pos (28U)
16118 #define HSEM_C2ISR_ISF28_Msk (0x1UL << HSEM_C2ISR_ISF28_Pos) /*!< 0x10000000 */
16119 #define HSEM_C2ISR_ISF28 HSEM_C2ISR_ISF28_Msk /*!<semaphore 28 interrupt 1 status bit. */
16120 #define HSEM_C2ISR_ISF29_Pos (29U)
16121 #define HSEM_C2ISR_ISF29_Msk (0x1UL << HSEM_C2ISR_ISF29_Pos) /*!< 0x20000000 */
16122 #define HSEM_C2ISR_ISF29 HSEM_C2ISR_ISF29_Msk /*!<semaphore 29 interrupt 1 status bit. */
16123 #define HSEM_C2ISR_ISF30_Pos (30U)
16124 #define HSEM_C2ISR_ISF30_Msk (0x1UL << HSEM_C2ISR_ISF30_Pos) /*!< 0x40000000 */
16125 #define HSEM_C2ISR_ISF30 HSEM_C2ISR_ISF30_Msk /*!<semaphore 30 interrupt 1 status bit. */
16126 #define HSEM_C2ISR_ISF31_Pos (31U)
16127 #define HSEM_C2ISR_ISF31_Msk (0x1UL << HSEM_C2ISR_ISF31_Pos) /*!< 0x80000000 */
16128 #define HSEM_C2ISR_ISF31 HSEM_C2ISR_ISF31_Msk /*!<semaphore 31 interrupt 1 status bit. */
16129
16130 /******************** Bit definition for HSEM_C2MISR register *****************/
16131 #define HSEM_C2MISR_MISF0_Pos (0U)
16132 #define HSEM_C2MISR_MISF0_Msk (0x1UL << HSEM_C2MISR_MISF0_Pos) /*!< 0x00000001 */
16133 #define HSEM_C2MISR_MISF0 HSEM_C2MISR_MISF0_Msk /*!<semaphore 0 interrupt 1 masked status bit. */
16134 #define HSEM_C2MISR_MISF1_Pos (1U)
16135 #define HSEM_C2MISR_MISF1_Msk (0x1UL << HSEM_C2MISR_MISF1_Pos) /*!< 0x00000002 */
16136 #define HSEM_C2MISR_MISF1 HSEM_C2MISR_MISF1_Msk /*!<semaphore 1 interrupt 1 masked status bit. */
16137 #define HSEM_C2MISR_MISF2_Pos (2U)
16138 #define HSEM_C2MISR_MISF2_Msk (0x1UL << HSEM_C2MISR_MISF2_Pos) /*!< 0x00000004 */
16139 #define HSEM_C2MISR_MISF2 HSEM_C2MISR_MISF2_Msk /*!<semaphore 2 interrupt 1 masked status bit. */
16140 #define HSEM_C2MISR_MISF3_Pos (3U)
16141 #define HSEM_C2MISR_MISF3_Msk (0x1UL << HSEM_C2MISR_MISF3_Pos) /*!< 0x00000008 */
16142 #define HSEM_C2MISR_MISF3 HSEM_C2MISR_MISF3_Msk /*!<semaphore 3 interrupt 1 masked status bit. */
16143 #define HSEM_C2MISR_MISF4_Pos (4U)
16144 #define HSEM_C2MISR_MISF4_Msk (0x1UL << HSEM_C2MISR_MISF4_Pos) /*!< 0x00000010 */
16145 #define HSEM_C2MISR_MISF4 HSEM_C2MISR_MISF4_Msk /*!<semaphore 4 interrupt 1 masked status bit. */
16146 #define HSEM_C2MISR_MISF5_Pos (5U)
16147 #define HSEM_C2MISR_MISF5_Msk (0x1UL << HSEM_C2MISR_MISF5_Pos) /*!< 0x00000020 */
16148 #define HSEM_C2MISR_MISF5 HSEM_C2MISR_MISF5_Msk /*!<semaphore 5 interrupt 1 masked status bit. */
16149 #define HSEM_C2MISR_MISF6_Pos (6U)
16150 #define HSEM_C2MISR_MISF6_Msk (0x1UL << HSEM_C2MISR_MISF6_Pos) /*!< 0x00000040 */
16151 #define HSEM_C2MISR_MISF6 HSEM_C2MISR_MISF6_Msk /*!<semaphore 6 interrupt 1 masked status bit. */
16152 #define HSEM_C2MISR_MISF7_Pos (7U)
16153 #define HSEM_C2MISR_MISF7_Msk (0x1UL << HSEM_C2MISR_MISF7_Pos) /*!< 0x00000080 */
16154 #define HSEM_C2MISR_MISF7 HSEM_C2MISR_MISF7_Msk /*!<semaphore 7 interrupt 1 masked status bit. */
16155 #define HSEM_C2MISR_MISF8_Pos (8U)
16156 #define HSEM_C2MISR_MISF8_Msk (0x1UL << HSEM_C2MISR_MISF8_Pos) /*!< 0x00000100 */
16157 #define HSEM_C2MISR_MISF8 HSEM_C2MISR_MISF8_Msk /*!<semaphore 8 interrupt 1 masked status bit. */
16158 #define HSEM_C2MISR_MISF9_Pos (9U)
16159 #define HSEM_C2MISR_MISF9_Msk (0x1UL << HSEM_C2MISR_MISF9_Pos) /*!< 0x00000200 */
16160 #define HSEM_C2MISR_MISF9 HSEM_C2MISR_MISF9_Msk /*!<semaphore 9 interrupt 1 masked status bit. */
16161 #define HSEM_C2MISR_MISF10_Pos (10U)
16162 #define HSEM_C2MISR_MISF10_Msk (0x1UL << HSEM_C2MISR_MISF10_Pos) /*!< 0x00000400 */
16163 #define HSEM_C2MISR_MISF10 HSEM_C2MISR_MISF10_Msk /*!<semaphore 10 interrupt 1 masked status bit. */
16164 #define HSEM_C2MISR_MISF11_Pos (11U)
16165 #define HSEM_C2MISR_MISF11_Msk (0x1UL << HSEM_C2MISR_MISF11_Pos) /*!< 0x00000800 */
16166 #define HSEM_C2MISR_MISF11 HSEM_C2MISR_MISF11_Msk /*!<semaphore 11 interrupt 1 masked status bit. */
16167 #define HSEM_C2MISR_MISF12_Pos (12U)
16168 #define HSEM_C2MISR_MISF12_Msk (0x1UL << HSEM_C2MISR_MISF12_Pos) /*!< 0x00001000 */
16169 #define HSEM_C2MISR_MISF12 HSEM_C2MISR_MISF12_Msk /*!<semaphore 12 interrupt 1 masked status bit. */
16170 #define HSEM_C2MISR_MISF13_Pos (13U)
16171 #define HSEM_C2MISR_MISF13_Msk (0x1UL << HSEM_C2MISR_MISF13_Pos) /*!< 0x00002000 */
16172 #define HSEM_C2MISR_MISF13 HSEM_C2MISR_MISF13_Msk /*!<semaphore 13 interrupt 1 masked status bit. */
16173 #define HSEM_C2MISR_MISF14_Pos (14U)
16174 #define HSEM_C2MISR_MISF14_Msk (0x1UL << HSEM_C2MISR_MISF14_Pos) /*!< 0x00004000 */
16175 #define HSEM_C2MISR_MISF14 HSEM_C2MISR_MISF14_Msk /*!<semaphore 14 interrupt 1 masked status bit. */
16176 #define HSEM_C2MISR_MISF15_Pos (15U)
16177 #define HSEM_C2MISR_MISF15_Msk (0x1UL << HSEM_C2MISR_MISF15_Pos) /*!< 0x00008000 */
16178 #define HSEM_C2MISR_MISF15 HSEM_C2MISR_MISF15_Msk /*!<semaphore 15 interrupt 1 masked status bit. */
16179 #define HSEM_C2MISR_MISF16_Pos (16U)
16180 #define HSEM_C2MISR_MISF16_Msk (0x1UL << HSEM_C2MISR_MISF16_Pos) /*!< 0x00010000 */
16181 #define HSEM_C2MISR_MISF16 HSEM_C2MISR_MISF16_Msk /*!<semaphore 16 interrupt 1 masked status bit. */
16182 #define HSEM_C2MISR_MISF17_Pos (17U)
16183 #define HSEM_C2MISR_MISF17_Msk (0x1UL << HSEM_C2MISR_MISF17_Pos) /*!< 0x00020000 */
16184 #define HSEM_C2MISR_MISF17 HSEM_C2MISR_MISF17_Msk /*!<semaphore 17 interrupt 1 masked status bit. */
16185 #define HSEM_C2MISR_MISF18_Pos (18U)
16186 #define HSEM_C2MISR_MISF18_Msk (0x1UL << HSEM_C2MISR_MISF18_Pos) /*!< 0x00040000 */
16187 #define HSEM_C2MISR_MISF18 HSEM_C2MISR_MISF18_Msk /*!<semaphore 18 interrupt 1 masked status bit. */
16188 #define HSEM_C2MISR_MISF19_Pos (19U)
16189 #define HSEM_C2MISR_MISF19_Msk (0x1UL << HSEM_C2MISR_MISF19_Pos) /*!< 0x00080000 */
16190 #define HSEM_C2MISR_MISF19 HSEM_C2MISR_MISF19_Msk /*!<semaphore 19 interrupt 1 masked status bit. */
16191 #define HSEM_C2MISR_MISF20_Pos (20U)
16192 #define HSEM_C2MISR_MISF20_Msk (0x1UL << HSEM_C2MISR_MISF20_Pos) /*!< 0x00100000 */
16193 #define HSEM_C2MISR_MISF20 HSEM_C2MISR_MISF20_Msk /*!<semaphore 20 interrupt 1 masked status bit. */
16194 #define HSEM_C2MISR_MISF21_Pos (21U)
16195 #define HSEM_C2MISR_MISF21_Msk (0x1UL << HSEM_C2MISR_MISF21_Pos) /*!< 0x00200000 */
16196 #define HSEM_C2MISR_MISF21 HSEM_C2MISR_MISF21_Msk /*!<semaphore 21 interrupt 1 masked status bit. */
16197 #define HSEM_C2MISR_MISF22_Pos (22U)
16198 #define HSEM_C2MISR_MISF22_Msk (0x1UL << HSEM_C2MISR_MISF22_Pos) /*!< 0x00400000 */
16199 #define HSEM_C2MISR_MISF22 HSEM_C2MISR_MISF22_Msk /*!<semaphore 22 interrupt 1 masked status bit. */
16200 #define HSEM_C2MISR_MISF23_Pos (23U)
16201 #define HSEM_C2MISR_MISF23_Msk (0x1UL << HSEM_C2MISR_MISF23_Pos) /*!< 0x00800000 */
16202 #define HSEM_C2MISR_MISF23 HSEM_C2MISR_MISF23_Msk /*!<semaphore 23 interrupt 1 masked status bit. */
16203 #define HSEM_C2MISR_MISF24_Pos (24U)
16204 #define HSEM_C2MISR_MISF24_Msk (0x1UL << HSEM_C2MISR_MISF24_Pos) /*!< 0x01000000 */
16205 #define HSEM_C2MISR_MISF24 HSEM_C2MISR_MISF24_Msk /*!<semaphore 24 interrupt 1 masked status bit. */
16206 #define HSEM_C2MISR_MISF25_Pos (25U)
16207 #define HSEM_C2MISR_MISF25_Msk (0x1UL << HSEM_C2MISR_MISF25_Pos) /*!< 0x02000000 */
16208 #define HSEM_C2MISR_MISF25 HSEM_C2MISR_MISF25_Msk /*!<semaphore 25 interrupt 1 masked status bit. */
16209 #define HSEM_C2MISR_MISF26_Pos (26U)
16210 #define HSEM_C2MISR_MISF26_Msk (0x1UL << HSEM_C2MISR_MISF26_Pos) /*!< 0x04000000 */
16211 #define HSEM_C2MISR_MISF26 HSEM_C2MISR_MISF26_Msk /*!<semaphore 26 interrupt 1 masked status bit. */
16212 #define HSEM_C2MISR_MISF27_Pos (27U)
16213 #define HSEM_C2MISR_MISF27_Msk (0x1UL << HSEM_C2MISR_MISF27_Pos) /*!< 0x08000000 */
16214 #define HSEM_C2MISR_MISF27 HSEM_C2MISR_MISF27_Msk /*!<semaphore 27 interrupt 1 masked status bit. */
16215 #define HSEM_C2MISR_MISF28_Pos (28U)
16216 #define HSEM_C2MISR_MISF28_Msk (0x1UL << HSEM_C2MISR_MISF28_Pos) /*!< 0x10000000 */
16217 #define HSEM_C2MISR_MISF28 HSEM_C2MISR_MISF28_Msk /*!<semaphore 28 interrupt 1 masked status bit. */
16218 #define HSEM_C2MISR_MISF29_Pos (29U)
16219 #define HSEM_C2MISR_MISF29_Msk (0x1UL << HSEM_C2MISR_MISF29_Pos) /*!< 0x20000000 */
16220 #define HSEM_C2MISR_MISF29 HSEM_C2MISR_MISF29_Msk /*!<semaphore 29 interrupt 1 masked status bit. */
16221 #define HSEM_C2MISR_MISF30_Pos (30U)
16222 #define HSEM_C2MISR_MISF30_Msk (0x1UL << HSEM_C2MISR_MISF30_Pos) /*!< 0x40000000 */
16223 #define HSEM_C2MISR_MISF30 HSEM_C2MISR_MISF30_Msk /*!<semaphore 30 interrupt 1 masked status bit. */
16224 #define HSEM_C2MISR_MISF31_Pos (31U)
16225 #define HSEM_C2MISR_MISF31_Msk (0x1UL << HSEM_C2MISR_MISF31_Pos) /*!< 0x80000000 */
16226 #define HSEM_C2MISR_MISF31 HSEM_C2MISR_MISF31_Msk /*!<semaphore 31 interrupt 1 masked status bit. */
16227 /******************** Bit definition for HSEM_CR register *****************/
16228 #define HSEM_CR_COREID_Pos (8U)
16229 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
16230 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
16231 #define HSEM_CR_KEY_Pos (16U)
16232 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
16233 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
16234
16235 /******************** Bit definition for HSEM_KEYR register *****************/
16236 #define HSEM_KEYR_KEY_Pos (16U)
16237 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
16238 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
16239
16240 /******************************************************************************/
16241 /* */
16242 /* Inter-integrated Circuit Interface (I2C) */
16243 /* */
16244 /******************************************************************************/
16245 /******************* Bit definition for I2C_CR1 register *******************/
16246 #define I2C_CR1_PE_Pos (0U)
16247 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
16248 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
16249 #define I2C_CR1_TXIE_Pos (1U)
16250 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
16251 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
16252 #define I2C_CR1_RXIE_Pos (2U)
16253 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
16254 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
16255 #define I2C_CR1_ADDRIE_Pos (3U)
16256 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
16257 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
16258 #define I2C_CR1_NACKIE_Pos (4U)
16259 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
16260 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
16261 #define I2C_CR1_STOPIE_Pos (5U)
16262 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
16263 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
16264 #define I2C_CR1_TCIE_Pos (6U)
16265 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
16266 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
16267 #define I2C_CR1_ERRIE_Pos (7U)
16268 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
16269 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
16270 #define I2C_CR1_DNF_Pos (8U)
16271 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
16272 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
16273 #define I2C_CR1_ANFOFF_Pos (12U)
16274 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
16275 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
16276 #define I2C_CR1_TXDMAEN_Pos (14U)
16277 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
16278 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
16279 #define I2C_CR1_RXDMAEN_Pos (15U)
16280 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
16281 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
16282 #define I2C_CR1_SBC_Pos (16U)
16283 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
16284 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
16285 #define I2C_CR1_NOSTRETCH_Pos (17U)
16286 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
16287 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
16288 #define I2C_CR1_WUPEN_Pos (18U)
16289 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
16290 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
16291 #define I2C_CR1_GCEN_Pos (19U)
16292 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
16293 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
16294 #define I2C_CR1_SMBHEN_Pos (20U)
16295 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
16296 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
16297 #define I2C_CR1_SMBDEN_Pos (21U)
16298 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
16299 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
16300 #define I2C_CR1_ALERTEN_Pos (22U)
16301 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
16302 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
16303 #define I2C_CR1_PECEN_Pos (23U)
16304 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
16305 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
16306
16307 /****************** Bit definition for I2C_CR2 register ********************/
16308 #define I2C_CR2_SADD_Pos (0U)
16309 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
16310 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
16311 #define I2C_CR2_RD_WRN_Pos (10U)
16312 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
16313 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
16314 #define I2C_CR2_ADD10_Pos (11U)
16315 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
16316 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
16317 #define I2C_CR2_HEAD10R_Pos (12U)
16318 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
16319 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
16320 #define I2C_CR2_START_Pos (13U)
16321 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
16322 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
16323 #define I2C_CR2_STOP_Pos (14U)
16324 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
16325 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
16326 #define I2C_CR2_NACK_Pos (15U)
16327 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
16328 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
16329 #define I2C_CR2_NBYTES_Pos (16U)
16330 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
16331 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
16332 #define I2C_CR2_RELOAD_Pos (24U)
16333 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
16334 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
16335 #define I2C_CR2_AUTOEND_Pos (25U)
16336 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
16337 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
16338 #define I2C_CR2_PECBYTE_Pos (26U)
16339 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
16340 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
16341
16342 /******************* Bit definition for I2C_OAR1 register ******************/
16343 #define I2C_OAR1_OA1_Pos (0U)
16344 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
16345 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
16346 #define I2C_OAR1_OA1MODE_Pos (10U)
16347 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
16348 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
16349 #define I2C_OAR1_OA1EN_Pos (15U)
16350 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
16351 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
16352
16353 /******************* Bit definition for I2C_OAR2 register ******************/
16354 #define I2C_OAR2_OA2_Pos (1U)
16355 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
16356 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
16357 #define I2C_OAR2_OA2MSK_Pos (8U)
16358 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
16359 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
16360 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
16361 #define I2C_OAR2_OA2MASK01_Pos (8U)
16362 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
16363 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
16364 #define I2C_OAR2_OA2MASK02_Pos (9U)
16365 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
16366 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
16367 #define I2C_OAR2_OA2MASK03_Pos (8U)
16368 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
16369 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
16370 #define I2C_OAR2_OA2MASK04_Pos (10U)
16371 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
16372 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
16373 #define I2C_OAR2_OA2MASK05_Pos (8U)
16374 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
16375 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
16376 #define I2C_OAR2_OA2MASK06_Pos (9U)
16377 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
16378 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
16379 #define I2C_OAR2_OA2MASK07_Pos (8U)
16380 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
16381 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
16382 #define I2C_OAR2_OA2EN_Pos (15U)
16383 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
16384 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
16385
16386 /******************* Bit definition for I2C_TIMINGR register *******************/
16387 #define I2C_TIMINGR_SCLL_Pos (0U)
16388 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
16389 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
16390 #define I2C_TIMINGR_SCLH_Pos (8U)
16391 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
16392 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
16393 #define I2C_TIMINGR_SDADEL_Pos (16U)
16394 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
16395 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
16396 #define I2C_TIMINGR_SCLDEL_Pos (20U)
16397 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
16398 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
16399 #define I2C_TIMINGR_PRESC_Pos (28U)
16400 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
16401 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
16402
16403 /******************* Bit definition for I2C_TIMEOUTR register *******************/
16404 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
16405 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
16406 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
16407 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
16408 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
16409 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
16410 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
16411 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
16412 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
16413 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
16414 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
16415 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
16416 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
16417 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
16418 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
16419
16420 /****************** Bit definition for I2C_ISR register *********************/
16421 #define I2C_ISR_TXE_Pos (0U)
16422 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
16423 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
16424 #define I2C_ISR_TXIS_Pos (1U)
16425 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
16426 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
16427 #define I2C_ISR_RXNE_Pos (2U)
16428 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
16429 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
16430 #define I2C_ISR_ADDR_Pos (3U)
16431 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
16432 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
16433 #define I2C_ISR_NACKF_Pos (4U)
16434 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
16435 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
16436 #define I2C_ISR_STOPF_Pos (5U)
16437 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
16438 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
16439 #define I2C_ISR_TC_Pos (6U)
16440 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
16441 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
16442 #define I2C_ISR_TCR_Pos (7U)
16443 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
16444 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
16445 #define I2C_ISR_BERR_Pos (8U)
16446 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
16447 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
16448 #define I2C_ISR_ARLO_Pos (9U)
16449 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
16450 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
16451 #define I2C_ISR_OVR_Pos (10U)
16452 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
16453 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
16454 #define I2C_ISR_PECERR_Pos (11U)
16455 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
16456 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
16457 #define I2C_ISR_TIMEOUT_Pos (12U)
16458 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
16459 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
16460 #define I2C_ISR_ALERT_Pos (13U)
16461 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
16462 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
16463 #define I2C_ISR_BUSY_Pos (15U)
16464 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
16465 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
16466 #define I2C_ISR_DIR_Pos (16U)
16467 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
16468 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
16469 #define I2C_ISR_ADDCODE_Pos (17U)
16470 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
16471 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
16472
16473 /****************** Bit definition for I2C_ICR register *********************/
16474 #define I2C_ICR_ADDRCF_Pos (3U)
16475 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
16476 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
16477 #define I2C_ICR_NACKCF_Pos (4U)
16478 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
16479 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
16480 #define I2C_ICR_STOPCF_Pos (5U)
16481 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
16482 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
16483 #define I2C_ICR_BERRCF_Pos (8U)
16484 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
16485 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
16486 #define I2C_ICR_ARLOCF_Pos (9U)
16487 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
16488 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
16489 #define I2C_ICR_OVRCF_Pos (10U)
16490 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
16491 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
16492 #define I2C_ICR_PECCF_Pos (11U)
16493 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
16494 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
16495 #define I2C_ICR_TIMOUTCF_Pos (12U)
16496 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
16497 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
16498 #define I2C_ICR_ALERTCF_Pos (13U)
16499 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
16500 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
16501
16502 /****************** Bit definition for I2C_PECR register *********************/
16503 #define I2C_PECR_PEC_Pos (0U)
16504 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
16505 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
16506
16507 /****************** Bit definition for I2C_RXDR register *********************/
16508 #define I2C_RXDR_RXDATA_Pos (0U)
16509 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
16510 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
16511
16512 /****************** Bit definition for I2C_TXDR register *********************/
16513 #define I2C_TXDR_TXDATA_Pos (0U)
16514 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
16515 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
16516
16517 /******************************************************************************/
16518 /* */
16519 /* Independent WATCHDOG */
16520 /* */
16521 /******************************************************************************/
16522 /******************* Bit definition for IWDG_KR register ********************/
16523 #define IWDG_KR_KEY_Pos (0U)
16524 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
16525 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
16526
16527 /******************* Bit definition for IWDG_PR register ********************/
16528 #define IWDG_PR_PR_Pos (0U)
16529 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
16530 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
16531 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
16532 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
16533 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
16534
16535 /******************* Bit definition for IWDG_RLR register *******************/
16536 #define IWDG_RLR_RL_Pos (0U)
16537 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
16538 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
16539
16540 /******************* Bit definition for IWDG_SR register ********************/
16541 #define IWDG_SR_PVU_Pos (0U)
16542 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
16543 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
16544 #define IWDG_SR_RVU_Pos (1U)
16545 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
16546 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
16547 #define IWDG_SR_WVU_Pos (2U)
16548 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
16549 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
16550
16551 /******************* Bit definition for IWDG_KR register ********************/
16552 #define IWDG_WINR_WIN_Pos (0U)
16553 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
16554 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
16555
16556 /******************************************************************************/
16557 /* */
16558 /* JPEG Encoder/Decoder */
16559 /* */
16560 /******************************************************************************/
16561 /******************** Bit definition for CONFR0 register ********************/
16562 #define JPEG_CONFR0_START_Pos (0U)
16563 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
16564 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
16565
16566 /******************** Bit definition for CONFR1 register ********************/
16567 #define JPEG_CONFR1_NF_Pos (0U)
16568 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
16569 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
16570 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
16571 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
16572 #define JPEG_CONFR1_DE_Pos (3U)
16573 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
16574 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
16575 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
16576 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
16577 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
16578 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
16579 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
16580 #define JPEG_CONFR1_NS_Pos (6U)
16581 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
16582 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
16583 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
16584 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
16585 #define JPEG_CONFR1_HDR_Pos (8U)
16586 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
16587 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
16588 #define JPEG_CONFR1_YSIZE_Pos (16U)
16589 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
16590 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
16591
16592 /******************** Bit definition for CONFR2 register ********************/
16593 #define JPEG_CONFR2_NMCU_Pos (0U)
16594 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
16595 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
16596
16597 /******************** Bit definition for CONFR3 register ********************/
16598 #define JPEG_CONFR3_XSIZE_Pos (16U)
16599 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
16600 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
16601
16602 /******************** Bit definition for CONFR4 register ********************/
16603 #define JPEG_CONFR4_HD_Pos (0U)
16604 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
16605 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
16606 #define JPEG_CONFR4_HA_Pos (1U)
16607 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
16608 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
16609 #define JPEG_CONFR4_QT_Pos (2U)
16610 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
16611 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
16612 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
16613 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
16614 #define JPEG_CONFR4_NB_Pos (4U)
16615 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
16616 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
16617 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
16618 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
16619 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
16620 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
16621 #define JPEG_CONFR4_VSF_Pos (8U)
16622 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
16623 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
16624 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
16625 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
16626 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
16627 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
16628 #define JPEG_CONFR4_HSF_Pos (12U)
16629 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
16630 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
16631 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
16632 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
16633 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
16634 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
16635
16636 /******************** Bit definition for CONFR5 register ********************/
16637 #define JPEG_CONFR5_HD_Pos (0U)
16638 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
16639 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
16640 #define JPEG_CONFR5_HA_Pos (1U)
16641 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
16642 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
16643 #define JPEG_CONFR5_QT_Pos (2U)
16644 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
16645 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
16646 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
16647 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
16648 #define JPEG_CONFR5_NB_Pos (4U)
16649 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
16650 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
16651 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
16652 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
16653 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
16654 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
16655 #define JPEG_CONFR5_VSF_Pos (8U)
16656 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
16657 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
16658 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
16659 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
16660 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
16661 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
16662 #define JPEG_CONFR5_HSF_Pos (12U)
16663 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
16664 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
16665 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
16666 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
16667 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
16668 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
16669
16670 /******************** Bit definition for CONFR6 register ********************/
16671 #define JPEG_CONFR6_HD_Pos (0U)
16672 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
16673 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
16674 #define JPEG_CONFR6_HA_Pos (1U)
16675 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
16676 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
16677 #define JPEG_CONFR6_QT_Pos (2U)
16678 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
16679 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
16680 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
16681 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
16682 #define JPEG_CONFR6_NB_Pos (4U)
16683 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
16684 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
16685 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
16686 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
16687 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
16688 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
16689 #define JPEG_CONFR6_VSF_Pos (8U)
16690 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
16691 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
16692 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
16693 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
16694 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
16695 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
16696 #define JPEG_CONFR6_HSF_Pos (12U)
16697 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
16698 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
16699 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
16700 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
16701 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
16702 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
16703
16704 /******************** Bit definition for CONFR7 register ********************/
16705 #define JPEG_CONFR7_HD_Pos (0U)
16706 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
16707 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
16708 #define JPEG_CONFR7_HA_Pos (1U)
16709 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
16710 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
16711 #define JPEG_CONFR7_QT_Pos (2U)
16712 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
16713 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
16714 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
16715 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
16716 #define JPEG_CONFR7_NB_Pos (4U)
16717 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
16718 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
16719 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
16720 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
16721 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
16722 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
16723 #define JPEG_CONFR7_VSF_Pos (8U)
16724 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
16725 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
16726 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
16727 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
16728 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
16729 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
16730 #define JPEG_CONFR7_HSF_Pos (12U)
16731 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
16732 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
16733 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
16734 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
16735 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
16736 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
16737
16738 /******************** Bit definition for CR register ********************/
16739 #define JPEG_CR_JCEN_Pos (0U)
16740 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
16741 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
16742 #define JPEG_CR_IFTIE_Pos (1U)
16743 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
16744 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
16745 #define JPEG_CR_IFNFIE_Pos (2U)
16746 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
16747 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
16748 #define JPEG_CR_OFTIE_Pos (3U)
16749 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
16750 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
16751 #define JPEG_CR_OFNEIE_Pos (4U)
16752 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
16753 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
16754 #define JPEG_CR_EOCIE_Pos (5U)
16755 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
16756 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
16757 #define JPEG_CR_HPDIE_Pos (6U)
16758 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
16759 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
16760 #define JPEG_CR_IFF_Pos (13U)
16761 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
16762 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
16763 #define JPEG_CR_OFF_Pos (14U)
16764 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
16765 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
16766
16767 /******************** Bit definition for SR register ********************/
16768 #define JPEG_SR_IFTF_Pos (1U)
16769 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
16770 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
16771 #define JPEG_SR_IFNFF_Pos (2U)
16772 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
16773 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
16774 #define JPEG_SR_OFTF_Pos (3U)
16775 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
16776 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
16777 #define JPEG_SR_OFNEF_Pos (4U)
16778 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
16779 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
16780 #define JPEG_SR_EOCF_Pos (5U)
16781 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
16782 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
16783 #define JPEG_SR_HPDF_Pos (6U)
16784 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
16785 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
16786 #define JPEG_SR_COF_Pos (7U)
16787 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
16788 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
16789
16790 /******************** Bit definition for CFR register ********************/
16791 #define JPEG_CFR_CEOCF_Pos (4U)
16792 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
16793 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
16794 #define JPEG_CFR_CHPDF_Pos (5U)
16795 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
16796 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
16797
16798 /******************** Bit definition for DIR register ********************/
16799 #define JPEG_DIR_DATAIN_Pos (0U)
16800 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
16801 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
16802
16803 /******************** Bit definition for DOR register ********************/
16804 #define JPEG_DOR_DATAOUT_Pos (0U)
16805 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
16806 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
16807
16808 /******************************************************************************/
16809 /* */
16810 /* LCD-TFT Display Controller (LTDC) */
16811 /* */
16812 /******************************************************************************/
16813
16814 /******************** Bit definition for LTDC_SSCR register *****************/
16815
16816 #define LTDC_SSCR_VSH_Pos (0U)
16817 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
16818 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
16819 #define LTDC_SSCR_HSW_Pos (16U)
16820 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
16821 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
16822
16823 /******************** Bit definition for LTDC_BPCR register *****************/
16824
16825 #define LTDC_BPCR_AVBP_Pos (0U)
16826 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
16827 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
16828 #define LTDC_BPCR_AHBP_Pos (16U)
16829 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
16830 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
16831
16832 /******************** Bit definition for LTDC_AWCR register *****************/
16833
16834 #define LTDC_AWCR_AAH_Pos (0U)
16835 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
16836 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
16837 #define LTDC_AWCR_AAW_Pos (16U)
16838 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
16839 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
16840
16841 /******************** Bit definition for LTDC_TWCR register *****************/
16842
16843 #define LTDC_TWCR_TOTALH_Pos (0U)
16844 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
16845 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
16846 #define LTDC_TWCR_TOTALW_Pos (16U)
16847 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
16848 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
16849
16850 /******************** Bit definition for LTDC_GCR register ******************/
16851
16852 #define LTDC_GCR_LTDCEN_Pos (0U)
16853 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
16854 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
16855 #define LTDC_GCR_DBW_Pos (4U)
16856 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
16857 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
16858 #define LTDC_GCR_DGW_Pos (8U)
16859 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
16860 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
16861 #define LTDC_GCR_DRW_Pos (12U)
16862 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
16863 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
16864 #define LTDC_GCR_DEN_Pos (16U)
16865 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
16866 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
16867 #define LTDC_GCR_PCPOL_Pos (28U)
16868 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
16869 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
16870 #define LTDC_GCR_DEPOL_Pos (29U)
16871 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
16872 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
16873 #define LTDC_GCR_VSPOL_Pos (30U)
16874 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
16875 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
16876 #define LTDC_GCR_HSPOL_Pos (31U)
16877 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
16878 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
16879
16880
16881 /******************** Bit definition for LTDC_SRCR register *****************/
16882
16883 #define LTDC_SRCR_IMR_Pos (0U)
16884 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
16885 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
16886 #define LTDC_SRCR_VBR_Pos (1U)
16887 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
16888 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
16889
16890 /******************** Bit definition for LTDC_BCCR register *****************/
16891
16892 #define LTDC_BCCR_BCBLUE_Pos (0U)
16893 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
16894 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
16895 #define LTDC_BCCR_BCGREEN_Pos (8U)
16896 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
16897 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
16898 #define LTDC_BCCR_BCRED_Pos (16U)
16899 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
16900 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
16901
16902 /******************** Bit definition for LTDC_IER register ******************/
16903
16904 #define LTDC_IER_LIE_Pos (0U)
16905 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
16906 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
16907 #define LTDC_IER_FUIE_Pos (1U)
16908 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
16909 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
16910 #define LTDC_IER_TERRIE_Pos (2U)
16911 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
16912 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
16913 #define LTDC_IER_RRIE_Pos (3U)
16914 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
16915 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
16916
16917 /******************** Bit definition for LTDC_ISR register ******************/
16918
16919 #define LTDC_ISR_LIF_Pos (0U)
16920 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
16921 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
16922 #define LTDC_ISR_FUIF_Pos (1U)
16923 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
16924 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
16925 #define LTDC_ISR_TERRIF_Pos (2U)
16926 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
16927 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
16928 #define LTDC_ISR_RRIF_Pos (3U)
16929 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
16930 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
16931
16932 /******************** Bit definition for LTDC_ICR register ******************/
16933
16934 #define LTDC_ICR_CLIF_Pos (0U)
16935 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
16936 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
16937 #define LTDC_ICR_CFUIF_Pos (1U)
16938 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
16939 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
16940 #define LTDC_ICR_CTERRIF_Pos (2U)
16941 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
16942 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
16943 #define LTDC_ICR_CRRIF_Pos (3U)
16944 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
16945 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
16946
16947 /******************** Bit definition for LTDC_LIPCR register ****************/
16948
16949 #define LTDC_LIPCR_LIPOS_Pos (0U)
16950 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
16951 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
16952
16953 /******************** Bit definition for LTDC_CPSR register *****************/
16954
16955 #define LTDC_CPSR_CYPOS_Pos (0U)
16956 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
16957 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
16958 #define LTDC_CPSR_CXPOS_Pos (16U)
16959 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
16960 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
16961
16962 /******************** Bit definition for LTDC_CDSR register *****************/
16963
16964 #define LTDC_CDSR_VDES_Pos (0U)
16965 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
16966 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
16967 #define LTDC_CDSR_HDES_Pos (1U)
16968 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
16969 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
16970 #define LTDC_CDSR_VSYNCS_Pos (2U)
16971 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
16972 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
16973 #define LTDC_CDSR_HSYNCS_Pos (3U)
16974 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
16975 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
16976
16977 /******************** Bit definition for LTDC_LxCR register *****************/
16978
16979 #define LTDC_LxCR_LEN_Pos (0U)
16980 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
16981 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
16982 #define LTDC_LxCR_COLKEN_Pos (1U)
16983 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
16984 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
16985 #define LTDC_LxCR_CLUTEN_Pos (4U)
16986 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
16987 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
16988
16989 /******************** Bit definition for LTDC_LxWHPCR register **************/
16990
16991 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
16992 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
16993 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
16994 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
16995 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
16996 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
16997
16998 /******************** Bit definition for LTDC_LxWVPCR register **************/
16999
17000 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
17001 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
17002 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
17003 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
17004 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
17005 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
17006
17007 /******************** Bit definition for LTDC_LxCKCR register ***************/
17008
17009 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
17010 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
17011 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
17012 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
17013 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
17014 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
17015 #define LTDC_LxCKCR_CKRED_Pos (16U)
17016 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
17017 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
17018
17019 /******************** Bit definition for LTDC_LxPFCR register ***************/
17020
17021 #define LTDC_LxPFCR_PF_Pos (0U)
17022 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
17023 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
17024
17025 /******************** Bit definition for LTDC_LxCACR register ***************/
17026
17027 #define LTDC_LxCACR_CONSTA_Pos (0U)
17028 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
17029 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
17030
17031 /******************** Bit definition for LTDC_LxDCCR register ***************/
17032
17033 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
17034 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
17035 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
17036 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
17037 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
17038 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
17039 #define LTDC_LxDCCR_DCRED_Pos (16U)
17040 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
17041 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
17042 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
17043 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
17044 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
17045
17046 /******************** Bit definition for LTDC_LxBFCR register ***************/
17047
17048 #define LTDC_LxBFCR_BF2_Pos (0U)
17049 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
17050 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
17051 #define LTDC_LxBFCR_BF1_Pos (8U)
17052 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
17053 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
17054
17055 /******************** Bit definition for LTDC_LxCFBAR register **************/
17056
17057 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
17058 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
17059 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
17060
17061 /******************** Bit definition for LTDC_LxCFBLR register **************/
17062
17063 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
17064 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
17065 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
17066 #define LTDC_LxCFBLR_CFBP_Pos (16U)
17067 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
17068 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
17069
17070 /******************** Bit definition for LTDC_LxCFBLNR register *************/
17071
17072 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
17073 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
17074 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
17075
17076 /******************** Bit definition for LTDC_LxCLUTWR register *************/
17077
17078 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
17079 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
17080 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
17081 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
17082 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
17083 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
17084 #define LTDC_LxCLUTWR_RED_Pos (16U)
17085 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
17086 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
17087 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
17088 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
17089 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
17090
17091 /******************************************************************************/
17092 /* */
17093 /* MDMA */
17094 /* */
17095 /******************************************************************************/
17096 /******************** Bit definition for MDMA_GISR0 register ****************/
17097 #define MDMA_GISR0_GIF0_Pos (0U)
17098 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
17099 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
17100 #define MDMA_GISR0_GIF1_Pos (1U)
17101 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
17102 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
17103 #define MDMA_GISR0_GIF2_Pos (2U)
17104 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
17105 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
17106 #define MDMA_GISR0_GIF3_Pos (3U)
17107 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
17108 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
17109 #define MDMA_GISR0_GIF4_Pos (4U)
17110 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
17111 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
17112 #define MDMA_GISR0_GIF5_Pos (5U)
17113 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
17114 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
17115 #define MDMA_GISR0_GIF6_Pos (6U)
17116 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
17117 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
17118 #define MDMA_GISR0_GIF7_Pos (7U)
17119 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
17120 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
17121 #define MDMA_GISR0_GIF8_Pos (8U)
17122 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
17123 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
17124 #define MDMA_GISR0_GIF9_Pos (9U)
17125 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
17126 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
17127 #define MDMA_GISR0_GIF10_Pos (10U)
17128 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
17129 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
17130 #define MDMA_GISR0_GIF11_Pos (11U)
17131 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
17132 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
17133 #define MDMA_GISR0_GIF12_Pos (12U)
17134 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
17135 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
17136 #define MDMA_GISR0_GIF13_Pos (13U)
17137 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
17138 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
17139 #define MDMA_GISR0_GIF14_Pos (14U)
17140 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
17141 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
17142 #define MDMA_GISR0_GIF15_Pos (15U)
17143 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
17144 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
17145
17146 /******************** Bit definition for MDMA_CxISR register ****************/
17147 #define MDMA_CISR_TEIF_Pos (0U)
17148 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
17149 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
17150 #define MDMA_CISR_CTCIF_Pos (1U)
17151 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
17152 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
17153 #define MDMA_CISR_BRTIF_Pos (2U)
17154 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
17155 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
17156 #define MDMA_CISR_BTIF_Pos (3U)
17157 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
17158 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
17159 #define MDMA_CISR_TCIF_Pos (4U)
17160 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
17161 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
17162 #define MDMA_CISR_CRQA_Pos (16U)
17163 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
17164 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
17165
17166 /******************** Bit definition for MDMA_CxIFCR register ****************/
17167 #define MDMA_CIFCR_CTEIF_Pos (0U)
17168 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
17169 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
17170 #define MDMA_CIFCR_CCTCIF_Pos (1U)
17171 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
17172 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
17173 #define MDMA_CIFCR_CBRTIF_Pos (2U)
17174 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
17175 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
17176 #define MDMA_CIFCR_CBTIF_Pos (3U)
17177 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
17178 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
17179 #define MDMA_CIFCR_CLTCIF_Pos (4U)
17180 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
17181 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
17182
17183 /******************** Bit definition for MDMA_CxESR register ****************/
17184 #define MDMA_CESR_TEA_Pos (0U)
17185 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
17186 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
17187 #define MDMA_CESR_TED_Pos (7U)
17188 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
17189 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
17190 #define MDMA_CESR_TELD_Pos (8U)
17191 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
17192 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
17193 #define MDMA_CESR_TEMD_Pos (9U)
17194 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
17195 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
17196 #define MDMA_CESR_ASE_Pos (10U)
17197 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
17198 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
17199 #define MDMA_CESR_BSE_Pos (11U)
17200 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
17201 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
17202
17203 /******************** Bit definition for MDMA_CxCR register ****************/
17204 #define MDMA_CCR_EN_Pos (0U)
17205 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
17206 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
17207 #define MDMA_CCR_TEIE_Pos (1U)
17208 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
17209 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
17210 #define MDMA_CCR_CTCIE_Pos (2U)
17211 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
17212 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
17213 #define MDMA_CCR_BRTIE_Pos (3U)
17214 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
17215 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
17216 #define MDMA_CCR_BTIE_Pos (4U)
17217 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
17218 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
17219 #define MDMA_CCR_TCIE_Pos (5U)
17220 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
17221 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
17222 #define MDMA_CCR_PL_Pos (6U)
17223 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
17224 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
17225 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
17226 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
17227 #define MDMA_CCR_BEX_Pos (12U)
17228 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
17229 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
17230 #define MDMA_CCR_HEX_Pos (13U)
17231 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
17232 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
17233 #define MDMA_CCR_WEX_Pos (14U)
17234 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
17235 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
17236 #define MDMA_CCR_SWRQ_Pos (16U)
17237 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
17238 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
17239
17240 /******************** Bit definition for MDMA_CxTCR register ****************/
17241 #define MDMA_CTCR_SINC_Pos (0U)
17242 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
17243 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
17244 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
17245 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
17246 #define MDMA_CTCR_DINC_Pos (2U)
17247 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
17248 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
17249 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
17250 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
17251 #define MDMA_CTCR_SSIZE_Pos (4U)
17252 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
17253 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
17254 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
17255 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
17256 #define MDMA_CTCR_DSIZE_Pos (6U)
17257 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
17258 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
17259 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
17260 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
17261 #define MDMA_CTCR_SINCOS_Pos (8U)
17262 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
17263 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
17264 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
17265 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
17266 #define MDMA_CTCR_DINCOS_Pos (10U)
17267 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
17268 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
17269 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
17270 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
17271 #define MDMA_CTCR_SBURST_Pos (12U)
17272 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
17273 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
17274 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
17275 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
17276 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
17277 #define MDMA_CTCR_DBURST_Pos (15U)
17278 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
17279 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
17280 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
17281 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
17282 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
17283 #define MDMA_CTCR_TLEN_Pos (18U)
17284 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
17285 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
17286 #define MDMA_CTCR_PKE_Pos (25U)
17287 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
17288 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
17289 #define MDMA_CTCR_PAM_Pos (26U)
17290 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
17291 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
17292 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
17293 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
17294 #define MDMA_CTCR_TRGM_Pos (28U)
17295 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
17296 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
17297 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
17298 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
17299 #define MDMA_CTCR_SWRM_Pos (30U)
17300 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
17301 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
17302 #define MDMA_CTCR_BWM_Pos (31U)
17303 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
17304 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
17305
17306 /******************** Bit definition for MDMA_CxBNDTR register ****************/
17307 #define MDMA_CBNDTR_BNDT_Pos (0U)
17308 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
17309 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
17310 #define MDMA_CBNDTR_BRSUM_Pos (18U)
17311 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
17312 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
17313 #define MDMA_CBNDTR_BRDUM_Pos (19U)
17314 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
17315 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
17316 #define MDMA_CBNDTR_BRC_Pos (20U)
17317 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
17318 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
17319
17320 /******************** Bit definition for MDMA_CxSAR register ****************/
17321 #define MDMA_CSAR_SAR_Pos (0U)
17322 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
17323 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
17324
17325 /******************** Bit definition for MDMA_CxDAR register ****************/
17326 #define MDMA_CDAR_DAR_Pos (0U)
17327 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
17328 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
17329
17330 /******************** Bit definition for MDMA_CxBRUR ************************/
17331 #define MDMA_CBRUR_SUV_Pos (0U)
17332 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
17333 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
17334 #define MDMA_CBRUR_DUV_Pos (16U)
17335 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
17336 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
17337
17338 /******************** Bit definition for MDMA_CxLAR *************************/
17339 #define MDMA_CLAR_LAR_Pos (0U)
17340 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
17341 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
17342
17343 /******************** Bit definition for MDMA_CxTBR) ************************/
17344 #define MDMA_CTBR_TSEL_Pos (0U)
17345 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
17346 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
17347 #define MDMA_CTBR_SBUS_Pos (16U)
17348 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
17349 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
17350 #define MDMA_CTBR_DBUS_Pos (17U)
17351 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
17352 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
17353
17354 /******************** Bit definition for MDMA_CxMAR) ************************/
17355 #define MDMA_CMAR_MAR_Pos (0U)
17356 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
17357 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
17358
17359 /******************** Bit definition for MDMA_CxMDR) ************************/
17360 #define MDMA_CMDR_MDR_Pos (0U)
17361 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
17362 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
17363
17364 /******************************************************************************/
17365 /* */
17366 /* Operational Amplifier (OPAMP) */
17367 /* */
17368 /******************************************************************************/
17369 /********************* Bit definition for OPAMPx_CSR register ***************/
17370 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
17371 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
17372 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
17373 #define OPAMP_CSR_FORCEVP_Pos (1U)
17374 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
17375 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
17376
17377 #define OPAMP_CSR_VPSEL_Pos (2U)
17378 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
17379 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
17380 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
17381 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
17382
17383 #define OPAMP_CSR_VMSEL_Pos (5U)
17384 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
17385 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
17386 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
17387 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
17388
17389 #define OPAMP_CSR_OPAHSM_Pos (8U)
17390 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
17391 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
17392 #define OPAMP_CSR_CALON_Pos (11U)
17393 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
17394 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
17395
17396 #define OPAMP_CSR_CALSEL_Pos (12U)
17397 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
17398 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
17399 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
17400 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
17401
17402 #define OPAMP_CSR_PGGAIN_Pos (14U)
17403 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
17404 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
17405 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
17406 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
17407 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
17408 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
17409
17410 #define OPAMP_CSR_USERTRIM_Pos (18U)
17411 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
17412 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
17413 #define OPAMP_CSR_TSTREF_Pos (29U)
17414 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
17415 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
17416 #define OPAMP_CSR_CALOUT_Pos (30U)
17417 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
17418 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
17419
17420 /********************* Bit definition for OPAMP1_CSR register ***************/
17421 #define OPAMP1_CSR_OPAEN_Pos (0U)
17422 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
17423 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
17424 #define OPAMP1_CSR_FORCEVP_Pos (1U)
17425 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
17426 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
17427
17428 #define OPAMP1_CSR_VPSEL_Pos (2U)
17429 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
17430 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
17431 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
17432 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
17433
17434 #define OPAMP1_CSR_VMSEL_Pos (5U)
17435 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
17436 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
17437 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
17438 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
17439
17440 #define OPAMP1_CSR_OPAHSM_Pos (8U)
17441 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
17442 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
17443 #define OPAMP1_CSR_CALON_Pos (11U)
17444 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
17445 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
17446
17447 #define OPAMP1_CSR_CALSEL_Pos (12U)
17448 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
17449 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
17450 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
17451 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
17452
17453 #define OPAMP1_CSR_PGGAIN_Pos (14U)
17454 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
17455 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
17456 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
17457 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
17458 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
17459 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
17460
17461 #define OPAMP1_CSR_USERTRIM_Pos (18U)
17462 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
17463 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
17464 #define OPAMP1_CSR_TSTREF_Pos (29U)
17465 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
17466 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
17467 #define OPAMP1_CSR_CALOUT_Pos (30U)
17468 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
17469 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
17470
17471 /********************* Bit definition for OPAMP2_CSR register ***************/
17472 #define OPAMP2_CSR_OPAEN_Pos (0U)
17473 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
17474 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
17475 #define OPAMP2_CSR_FORCEVP_Pos (1U)
17476 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
17477 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
17478
17479 #define OPAMP2_CSR_VPSEL_Pos (2U)
17480 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
17481 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
17482 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
17483 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
17484
17485 #define OPAMP2_CSR_VMSEL_Pos (5U)
17486 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
17487 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
17488 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
17489 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
17490
17491 #define OPAMP2_CSR_OPAHSM_Pos (8U)
17492 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
17493 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
17494 #define OPAMP2_CSR_CALON_Pos (11U)
17495 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
17496 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
17497
17498 #define OPAMP2_CSR_CALSEL_Pos (12U)
17499 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
17500 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
17501 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
17502 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
17503
17504 #define OPAMP2_CSR_PGGAIN_Pos (14U)
17505 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
17506 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
17507 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
17508 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
17509 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
17510 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
17511
17512 #define OPAMP2_CSR_USERTRIM_Pos (18U)
17513 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
17514 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
17515 #define OPAMP2_CSR_TSTREF_Pos (29U)
17516 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
17517 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
17518 #define OPAMP2_CSR_CALOUT_Pos (30U)
17519 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
17520 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
17521
17522 /******************* Bit definition for OPAMP_OTR register ******************/
17523 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
17524 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17525 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17526 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
17527 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17528 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17529
17530 /******************* Bit definition for OPAMP1_OTR register ******************/
17531 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
17532 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17533 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17534 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
17535 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17536 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17537
17538 /******************* Bit definition for OPAMP2_OTR register ******************/
17539 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
17540 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
17541 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17542 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
17543 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
17544 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17545
17546 /******************* Bit definition for OPAMP_HSOTR register ****************/
17547 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
17548 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
17549 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17550 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
17551 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
17552 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17553
17554 /******************* Bit definition for OPAMP1_HSOTR register ****************/
17555 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
17556 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
17557 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17558 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
17559 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
17560 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17561
17562 /******************* Bit definition for OPAMP2_HSOTR register ****************/
17563 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
17564 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
17565 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
17566 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
17567 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
17568 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
17569
17570 /******************************************************************************/
17571 /* */
17572 /* Power Control */
17573 /* */
17574 /******************************************************************************/
17575 /************************* NUMBER OF POWER DOMAINS **************************/
17576 #define POWER_DOMAINS_NUMBER 3U /*!< 3 Domains */
17577
17578 /******************** Bit definition for PWR_CR1 register *******************/
17579 #define PWR_CR1_ALS_Pos (17U)
17580 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
17581 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
17582 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
17583 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
17584 #define PWR_CR1_AVDEN_Pos (16U)
17585 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
17586 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
17587 #define PWR_CR1_SVOS_Pos (14U)
17588 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
17589 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
17590 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
17591 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
17592 #define PWR_CR1_FLPS_Pos (9U)
17593 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
17594 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
17595 #define PWR_CR1_DBP_Pos (8U)
17596 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
17597 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
17598 #define PWR_CR1_PLS_Pos (5U)
17599 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
17600 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
17601 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
17602 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
17603 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
17604 #define PWR_CR1_PVDEN_Pos (4U)
17605 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
17606 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
17607 #define PWR_CR1_LPDS_Pos (0U)
17608 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
17609 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
17610
17611 /*!< PVD level configuration */
17612 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
17613 #define PWR_CR1_PLS_LEV1_Pos (5U)
17614 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
17615 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
17616 #define PWR_CR1_PLS_LEV2_Pos (6U)
17617 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
17618 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
17619 #define PWR_CR1_PLS_LEV3_Pos (5U)
17620 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
17621 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
17622 #define PWR_CR1_PLS_LEV4_Pos (7U)
17623 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
17624 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
17625 #define PWR_CR1_PLS_LEV5_Pos (5U)
17626 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
17627 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
17628 #define PWR_CR1_PLS_LEV6_Pos (6U)
17629 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
17630 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
17631 #define PWR_CR1_PLS_LEV7_Pos (5U)
17632 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
17633 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
17634
17635 /*!< AVD level configuration */
17636 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
17637 #define PWR_CR1_ALS_LEV1_Pos (17U)
17638 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
17639 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
17640 #define PWR_CR1_ALS_LEV2_Pos (18U)
17641 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
17642 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
17643 #define PWR_CR1_ALS_LEV3_Pos (17U)
17644 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
17645 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
17646
17647 /******************** Bit definition for PWR_CSR1 register ******************/
17648 #define PWR_CSR1_AVDO_Pos (16U)
17649 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
17650 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
17651 #define PWR_CSR1_ACTVOS_Pos (14U)
17652 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
17653 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
17654 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
17655 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
17656 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
17657 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
17658 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
17659 #define PWR_CSR1_PVDO_Pos (4U)
17660 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
17661 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
17662
17663 /******************** Bit definition for PWR_CR2 register *******************/
17664 #define PWR_CR2_TEMPH_Pos (23U)
17665 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
17666 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
17667 #define PWR_CR2_TEMPL_Pos (22U)
17668 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
17669 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
17670 #define PWR_CR2_VBATH_Pos (21U)
17671 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
17672 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
17673 #define PWR_CR2_VBATL_Pos (20U)
17674 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
17675 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
17676 #define PWR_CR2_BRRDY_Pos (16U)
17677 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
17678 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
17679 #define PWR_CR2_MONEN_Pos (4U)
17680 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
17681 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
17682 #define PWR_CR2_BREN_Pos (0U)
17683 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
17684 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
17685
17686 /******************** Bit definition for PWR_CR3 register *******************/
17687 #define PWR_CR3_USB33RDY_Pos (26U)
17688 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
17689 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
17690 #define PWR_CR3_USBREGEN_Pos (25U)
17691 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
17692 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
17693 #define PWR_CR3_USB33DEN_Pos (24U)
17694 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
17695 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
17696 #define PWR_CR3_SMPSEXTRDY_Pos (16U)
17697 #define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */
17698 #define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */
17699 #define PWR_CR3_VBRS_Pos (9U)
17700 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
17701 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
17702 #define PWR_CR3_VBE_Pos (8U)
17703 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
17704 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
17705 #define PWR_CR3_SMPSLEVEL_Pos (4U)
17706 #define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */
17707 #define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */
17708 #define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */
17709 #define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */
17710 #define PWR_CR3_SMPSEXTHP_Pos (3U)
17711 #define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */
17712 #define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */
17713 #define PWR_CR3_SMPSEN_Pos (2U)
17714 #define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */
17715 #define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */
17716 #define PWR_CR3_LDOEN_Pos (1U)
17717 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
17718 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
17719 #define PWR_CR3_BYPASS_Pos (0U)
17720 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
17721 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
17722
17723 /******************** Bit definition for PWR_CPUCR register *****************/
17724 #define PWR_CPUCR_RUN_D3_Pos (11U)
17725 #define PWR_CPUCR_RUN_D3_Msk (0x1UL << PWR_CPUCR_RUN_D3_Pos) /*!< 0x00000800 */
17726 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
17727 #define PWR_CPUCR_HOLD2_Pos (10U)
17728 #define PWR_CPUCR_HOLD2_Msk (0x1UL << PWR_CPUCR_HOLD2_Pos) /*!< 0x00000400 */
17729 #define PWR_CPUCR_HOLD2 PWR_CPUCR_HOLD2_Msk /*!< Hold the CPU2 and allocated peripherals when exiting STOP mode */
17730 #define PWR_CPUCR_CSSF_Pos (9U)
17731 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
17732 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
17733 #define PWR_CPUCR_SBF_D2_Pos (8U)
17734 #define PWR_CPUCR_SBF_D2_Msk (0x1UL << PWR_CPUCR_SBF_D2_Pos) /*!< 0x00000100 */
17735 #define PWR_CPUCR_SBF_D2 PWR_CPUCR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
17736 #define PWR_CPUCR_SBF_D1_Pos (7U)
17737 #define PWR_CPUCR_SBF_D1_Msk (0x1UL << PWR_CPUCR_SBF_D1_Pos) /*!< 0x00000080 */
17738 #define PWR_CPUCR_SBF_D1 PWR_CPUCR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
17739 #define PWR_CPUCR_SBF_Pos (6U)
17740 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
17741 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
17742 #define PWR_CPUCR_STOPF_Pos (5U)
17743 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
17744 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
17745 #define PWR_CPUCR_HOLD2F_Pos (4U)
17746 #define PWR_CPUCR_HOLD2F_Msk (0x1UL << PWR_CPUCR_HOLD2F_Pos) /*!< 0x00000010 */
17747 #define PWR_CPUCR_HOLD2F PWR_CPUCR_HOLD2F_Msk /*!< CPU2 in hold wakeup flag */
17748 #define PWR_CPUCR_PDDS_D3_Pos (2U)
17749 #define PWR_CPUCR_PDDS_D3_Msk (0x1UL << PWR_CPUCR_PDDS_D3_Pos) /*!< 0x00000004 */
17750 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
17751 #define PWR_CPUCR_PDDS_D2_Pos (1U)
17752 #define PWR_CPUCR_PDDS_D2_Msk (0x1UL << PWR_CPUCR_PDDS_D2_Pos) /*!< 0x00000002 */
17753 #define PWR_CPUCR_PDDS_D2 PWR_CPUCR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
17754 #define PWR_CPUCR_PDDS_D1_Pos (0U)
17755 #define PWR_CPUCR_PDDS_D1_Msk (0x1UL << PWR_CPUCR_PDDS_D1_Pos) /*!< 0x00000001 */
17756 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
17757
17758 /******************** Bit definition for PWR_CPU2CR register ****************/
17759 #define PWR_CPU2CR_RUN_D3_Pos (11U)
17760 #define PWR_CPU2CR_RUN_D3_Msk (0x1UL << PWR_CPU2CR_RUN_D3_Pos) /*!< 0x00000800 */
17761 #define PWR_CPU2CR_RUN_D3 PWR_CPU2CR_RUN_D3_Msk /*!< Keep system D3 domain in RUN mode regardless of the CPU sub-systems modes */
17762 #define PWR_CPU2CR_HOLD1_Pos (10U)
17763 #define PWR_CPU2CR_HOLD1_Msk (0x1UL << PWR_CPU2CR_HOLD1_Pos) /*!< 0x00000400 */
17764 #define PWR_CPU2CR_HOLD1 PWR_CPU2CR_HOLD1_Msk /*!< Hold the CPU1 and allocated peripherals when exiting STOP mode */
17765 #define PWR_CPU2CR_CSSF_Pos (9U)
17766 #define PWR_CPU2CR_CSSF_Msk (0x1UL << PWR_CPU2CR_CSSF_Pos) /*!< 0x00000200 */
17767 #define PWR_CPU2CR_CSSF PWR_CPU2CR_CSSF_Msk /*!< Clear D2 domain CPU2 STANDBY, STOP and HOLD flags */
17768 #define PWR_CPU2CR_SBF_D2_Pos (8U)
17769 #define PWR_CPU2CR_SBF_D2_Msk (0x1UL << PWR_CPU2CR_SBF_D2_Pos) /*!< 0x00000100 */
17770 #define PWR_CPU2CR_SBF_D2 PWR_CPU2CR_SBF_D2_Msk /*!< D2 domain DSTANDBY Flag */
17771 #define PWR_CPU2CR_SBF_D1_Pos (7U)
17772 #define PWR_CPU2CR_SBF_D1_Msk (0x1UL << PWR_CPU2CR_SBF_D1_Pos) /*!< 0x00000080 */
17773 #define PWR_CPU2CR_SBF_D1 PWR_CPU2CR_SBF_D1_Msk /*!< D1 domain DSTANDBY Flag */
17774 #define PWR_CPU2CR_SBF_Pos (6U)
17775 #define PWR_CPU2CR_SBF_Msk (0x1UL << PWR_CPU2CR_SBF_Pos) /*!< 0x00000040 */
17776 #define PWR_CPU2CR_SBF PWR_CPU2CR_SBF_Msk /*!< System STANDBY Flag */
17777 #define PWR_CPU2CR_STOPF_Pos (5U)
17778 #define PWR_CPU2CR_STOPF_Msk (0x1UL << PWR_CPU2CR_STOPF_Pos) /*!< 0x00000020 */
17779 #define PWR_CPU2CR_STOPF PWR_CPU2CR_STOPF_Msk /*!< STOP Flag */
17780 #define PWR_CPU2CR_HOLD1F_Pos (4U)
17781 #define PWR_CPU2CR_HOLD1F_Msk (0x1UL << PWR_CPU2CR_HOLD1F_Pos) /*!< 0x00000010 */
17782 #define PWR_CPU2CR_HOLD1F PWR_CPU2CR_HOLD1F_Msk /*!< CPU1 in hold wakeup flag */
17783 #define PWR_CPU2CR_PDDS_D3_Pos (2U)
17784 #define PWR_CPU2CR_PDDS_D3_Msk (0x1UL << PWR_CPU2CR_PDDS_D3_Pos) /*!< 0x00000004 */
17785 #define PWR_CPU2CR_PDDS_D3 PWR_CPU2CR_PDDS_D3_Msk /*!< System D3 domain Power Down Deepsleep */
17786 #define PWR_CPU2CR_PDDS_D2_Pos (1U)
17787 #define PWR_CPU2CR_PDDS_D2_Msk (0x1UL << PWR_CPU2CR_PDDS_D2_Pos) /*!< 0x00000002 */
17788 #define PWR_CPU2CR_PDDS_D2 PWR_CPU2CR_PDDS_D2_Msk /*!< D2 domain Power Down Deepsleep */
17789 #define PWR_CPU2CR_PDDS_D1_Pos (0U)
17790 #define PWR_CPU2CR_PDDS_D1_Msk (0x1UL << PWR_CPU2CR_PDDS_D1_Pos) /*!< 0x00000001 */
17791 #define PWR_CPU2CR_PDDS_D1 PWR_CPU2CR_PDDS_D1_Msk /*!< D1 domain Power Down Deepsleep selection */
17792
17793
17794 /******************** Bit definition for PWR_D3CR register ******************/
17795 #define PWR_D3CR_VOS_Pos (14U)
17796 #define PWR_D3CR_VOS_Msk (0x3UL << PWR_D3CR_VOS_Pos) /*!< 0x0000C000 */
17797 #define PWR_D3CR_VOS PWR_D3CR_VOS_Msk /*!< Voltage Scaling selection according performance */
17798 #define PWR_D3CR_VOS_0 (0x1UL << PWR_D3CR_VOS_Pos) /*!< 0x00004000 */
17799 #define PWR_D3CR_VOS_1 (0x2UL << PWR_D3CR_VOS_Pos) /*!< 0x00008000 */
17800 #define PWR_D3CR_VOSRDY_Pos (13U)
17801 #define PWR_D3CR_VOSRDY_Msk (0x1UL << PWR_D3CR_VOSRDY_Pos) /*!< 0x00002000 */
17802 #define PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
17803
17804 /****************** Bit definition for PWR_WKUPCR register ******************/
17805 #define PWR_WKUPCR_WKUPC6_Pos (5U)
17806 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
17807 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
17808 #define PWR_WKUPCR_WKUPC5_Pos (4U)
17809 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
17810 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
17811 #define PWR_WKUPCR_WKUPC4_Pos (3U)
17812 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
17813 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
17814 #define PWR_WKUPCR_WKUPC3_Pos (2U)
17815 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
17816 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
17817 #define PWR_WKUPCR_WKUPC2_Pos (1U)
17818 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
17819 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
17820 #define PWR_WKUPCR_WKUPC1_Pos (0U)
17821 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
17822 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
17823
17824 /******************** Bit definition for PWR_WKUPFR register ****************/
17825 #define PWR_WKUPFR_WKUPF6_Pos (5U)
17826 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
17827 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
17828 #define PWR_WKUPFR_WKUPF5_Pos (4U)
17829 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
17830 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
17831 #define PWR_WKUPFR_WKUPF4_Pos (3U)
17832 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
17833 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
17834 #define PWR_WKUPFR_WKUPF3_Pos (2U)
17835 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
17836 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
17837 #define PWR_WKUPFR_WKUPF2_Pos (1U)
17838 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
17839 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
17840 #define PWR_WKUPFR_WKUPF1_Pos (0U)
17841 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
17842 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
17843
17844 /****************** Bit definition for PWR_WKUPEPR register *****************/
17845 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
17846 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
17847 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
17848 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
17849 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
17850 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
17851 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
17852 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
17853 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
17854 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
17855 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
17856 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
17857 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
17858 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
17859 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
17860 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
17861 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
17862 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
17863 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
17864 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
17865 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
17866 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
17867 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
17868 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
17869 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
17870 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
17871 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
17872 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
17873 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
17874 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
17875 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
17876 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
17877 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
17878 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
17879 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
17880 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
17881 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
17882 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
17883 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
17884 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
17885 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
17886 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
17887 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
17888 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
17889 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
17890 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
17891 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
17892 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
17893 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
17894 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
17895 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
17896 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
17897 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
17898 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
17899 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
17900 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
17901 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
17902 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
17903 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
17904 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
17905 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
17906 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
17907 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
17908 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
17909 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
17910 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
17911 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
17912 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
17913 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
17914
17915 /******************************************************************************/
17916 /* */
17917 /* Reset and Clock Control */
17918 /* */
17919 /******************************************************************************/
17920 /******************************* RCC VERSION ********************************/
17921 #define RCC_VER_X
17922
17923 /******************** Bit definition for RCC_CR register ********************/
17924 #define RCC_CR_HSION_Pos (0U)
17925 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
17926 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
17927 #define RCC_CR_HSIKERON_Pos (1U)
17928 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
17929 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
17930 #define RCC_CR_HSIRDY_Pos (2U)
17931 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
17932 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
17933 #define RCC_CR_HSIDIV_Pos (3U)
17934 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
17935 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
17936 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
17937 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
17938 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
17939 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
17940
17941 #define RCC_CR_HSIDIVF_Pos (5U)
17942 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
17943 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
17944 #define RCC_CR_CSION_Pos (7U)
17945 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
17946 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
17947 #define RCC_CR_CSIRDY_Pos (8U)
17948 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
17949 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
17950 #define RCC_CR_CSIKERON_Pos (9U)
17951 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
17952 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
17953 #define RCC_CR_HSI48ON_Pos (12U)
17954 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
17955 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
17956 #define RCC_CR_HSI48RDY_Pos (13U)
17957 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
17958 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
17959
17960 #define RCC_CR_D1CKRDY_Pos (14U)
17961 #define RCC_CR_D1CKRDY_Msk (0x1UL << RCC_CR_D1CKRDY_Pos) /*!< 0x00004000 */
17962 #define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_Msk /*!< D1 domain clocks ready flag */
17963 #define RCC_CR_D2CKRDY_Pos (15U)
17964 #define RCC_CR_D2CKRDY_Msk (0x1UL << RCC_CR_D2CKRDY_Pos) /*!< 0x00008000 */
17965 #define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_Msk /*!< D2 domain clocks ready flag */
17966
17967 #define RCC_CR_HSEON_Pos (16U)
17968 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
17969 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
17970 #define RCC_CR_HSERDY_Pos (17U)
17971 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
17972 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
17973 #define RCC_CR_HSEBYP_Pos (18U)
17974 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
17975 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
17976 #define RCC_CR_CSSHSEON_Pos (19U)
17977 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
17978 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
17979
17980
17981 #define RCC_CR_PLL1ON_Pos (24U)
17982 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
17983 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
17984 #define RCC_CR_PLL1RDY_Pos (25U)
17985 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
17986 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
17987 #define RCC_CR_PLL2ON_Pos (26U)
17988 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
17989 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
17990 #define RCC_CR_PLL2RDY_Pos (27U)
17991 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
17992 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
17993 #define RCC_CR_PLL3ON_Pos (28U)
17994 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
17995 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
17996 #define RCC_CR_PLL3RDY_Pos (29U)
17997 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
17998 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
17999
18000 /*Legacy */
18001 #define RCC_CR_PLLON_Pos (24U)
18002 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
18003 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
18004 #define RCC_CR_PLLRDY_Pos (25U)
18005 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
18006 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
18007
18008 /******************** Bit definition for RCC_HSICFGR register ***************/
18009 /*!< HSICAL configuration */
18010 #define RCC_HSICFGR_HSICAL_Pos (0U)
18011 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
18012 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
18013 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
18014 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
18015 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
18016 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
18017 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
18018 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
18019 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
18020 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
18021 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
18022 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
18023 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
18024 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
18025
18026 /*!< HSITRIM configuration */
18027 #define RCC_HSICFGR_HSITRIM_Pos (24U)
18028 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
18029 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
18030 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
18031 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
18032 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
18033 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
18034 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
18035 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
18036 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
18037
18038
18039 /******************** Bit definition for RCC_CRRCR register *****************/
18040
18041 /*!< HSI48CAL configuration */
18042 #define RCC_CRRCR_HSI48CAL_Pos (0U)
18043 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
18044 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
18045 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
18046 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
18047 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
18048 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
18049 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
18050 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
18051 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
18052 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
18053 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
18054 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
18055
18056
18057 /******************** Bit definition for RCC_CSICFGR register *****************/
18058 /*!< CSICAL configuration */
18059 #define RCC_CSICFGR_CSICAL_Pos (0U)
18060 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
18061 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
18062 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
18063 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
18064 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
18065 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
18066 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
18067 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
18068 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
18069 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
18070
18071 /*!< CSITRIM configuration */
18072 #define RCC_CSICFGR_CSITRIM_Pos (24U)
18073 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
18074 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
18075 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
18076 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
18077 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
18078 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
18079 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
18080 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
18081
18082 /******************** Bit definition for RCC_CFGR register ******************/
18083 /*!< SW configuration */
18084 #define RCC_CFGR_SW_Pos (0U)
18085 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
18086 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
18087 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
18088 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
18089 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
18090
18091 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
18092 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
18093 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
18094 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
18095
18096 /*!< SWS configuration */
18097 #define RCC_CFGR_SWS_Pos (3U)
18098 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
18099 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
18100 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
18101 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
18102 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
18103
18104 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
18105 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
18106 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
18107 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
18108
18109 #define RCC_CFGR_STOPWUCK_Pos (6U)
18110 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
18111 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
18112
18113 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
18114 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
18115 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
18116
18117 /*!< RTCPRE configuration */
18118 #define RCC_CFGR_RTCPRE_Pos (8U)
18119 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
18120 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
18121 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
18122 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
18123 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
18124 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
18125 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
18126 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
18127
18128 /*!< HRTIMSEL configuration */
18129 #define RCC_CFGR_HRTIMSEL_Pos (14U)
18130 #define RCC_CFGR_HRTIMSEL_Msk (0x1UL << RCC_CFGR_HRTIMSEL_Pos)
18131 #define RCC_CFGR_HRTIMSEL RCC_CFGR_HRTIMSEL_Msk /*!< 0x00004000 */
18132
18133 /*!< TIMPRE configuration */
18134 #define RCC_CFGR_TIMPRE_Pos (15U)
18135 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
18136 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
18137
18138 /*!< MCO1 configuration */
18139 #define RCC_CFGR_MCO1_Pos (22U)
18140 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
18141 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
18142 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
18143 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
18144 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
18145
18146 #define RCC_CFGR_MCO1PRE_Pos (18U)
18147 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
18148 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
18149 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
18150 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
18151 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
18152 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
18153
18154 #define RCC_CFGR_MCO2PRE_Pos (25U)
18155 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
18156 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
18157 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
18158 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
18159 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
18160 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
18161
18162 #define RCC_CFGR_MCO2_Pos (29U)
18163 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
18164 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
18165 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
18166 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
18167 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
18168
18169 /******************** Bit definition for RCC_D1CFGR register ******************/
18170 /*!< D1HPRE configuration */
18171 #define RCC_D1CFGR_HPRE_Pos (0U)
18172 #define RCC_D1CFGR_HPRE_Msk (0xFUL << RCC_D1CFGR_HPRE_Pos) /*!< 0x0000000F */
18173 #define RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
18174 #define RCC_D1CFGR_HPRE_0 (0x1UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000001 */
18175 #define RCC_D1CFGR_HPRE_1 (0x2UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000002 */
18176 #define RCC_D1CFGR_HPRE_2 (0x4UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000004 */
18177 #define RCC_D1CFGR_HPRE_3 (0x8UL << RCC_D1CFGR_HPRE_Pos) /*!< 0x00000008 */
18178
18179
18180 #define RCC_D1CFGR_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
18181 #define RCC_D1CFGR_HPRE_DIV2_Pos (3U)
18182 #define RCC_D1CFGR_HPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_HPRE_DIV2_Pos) /*!< 0x00000008 */
18183 #define RCC_D1CFGR_HPRE_DIV2 RCC_D1CFGR_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
18184 #define RCC_D1CFGR_HPRE_DIV4_Pos (0U)
18185 #define RCC_D1CFGR_HPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_HPRE_DIV4_Pos) /*!< 0x00000009 */
18186 #define RCC_D1CFGR_HPRE_DIV4 RCC_D1CFGR_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
18187 #define RCC_D1CFGR_HPRE_DIV8_Pos (1U)
18188 #define RCC_D1CFGR_HPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_HPRE_DIV8_Pos) /*!< 0x0000000A */
18189 #define RCC_D1CFGR_HPRE_DIV8 RCC_D1CFGR_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
18190 #define RCC_D1CFGR_HPRE_DIV16_Pos (0U)
18191 #define RCC_D1CFGR_HPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_HPRE_DIV16_Pos) /*!< 0x0000000B */
18192 #define RCC_D1CFGR_HPRE_DIV16 RCC_D1CFGR_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
18193 #define RCC_D1CFGR_HPRE_DIV64_Pos (2U)
18194 #define RCC_D1CFGR_HPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_HPRE_DIV64_Pos) /*!< 0x0000000C */
18195 #define RCC_D1CFGR_HPRE_DIV64 RCC_D1CFGR_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
18196 #define RCC_D1CFGR_HPRE_DIV128_Pos (0U)
18197 #define RCC_D1CFGR_HPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_HPRE_DIV128_Pos) /*!< 0x0000000D */
18198 #define RCC_D1CFGR_HPRE_DIV128 RCC_D1CFGR_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
18199 #define RCC_D1CFGR_HPRE_DIV256_Pos (1U)
18200 #define RCC_D1CFGR_HPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_HPRE_DIV256_Pos) /*!< 0x0000000E */
18201 #define RCC_D1CFGR_HPRE_DIV256 RCC_D1CFGR_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
18202 #define RCC_D1CFGR_HPRE_DIV512_Pos (0U)
18203 #define RCC_D1CFGR_HPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_HPRE_DIV512_Pos) /*!< 0x0000000F */
18204 #define RCC_D1CFGR_HPRE_DIV512 RCC_D1CFGR_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
18205
18206 /*!< D1PPRE configuration */
18207 #define RCC_D1CFGR_D1PPRE_Pos (4U)
18208 #define RCC_D1CFGR_D1PPRE_Msk (0x7UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000070 */
18209 #define RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_Msk /*!< D1PRE[2:0] bits (APB3 prescaler) */
18210 #define RCC_D1CFGR_D1PPRE_0 (0x1UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000010 */
18211 #define RCC_D1CFGR_D1PPRE_1 (0x2UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000020 */
18212 #define RCC_D1CFGR_D1PPRE_2 (0x4UL << RCC_D1CFGR_D1PPRE_Pos) /*!< 0x00000040 */
18213
18214 #define RCC_D1CFGR_D1PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
18215 #define RCC_D1CFGR_D1PPRE_DIV2_Pos (6U)
18216 #define RCC_D1CFGR_D1PPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1PPRE_DIV2_Pos) /*!< 0x00000040 */
18217 #define RCC_D1CFGR_D1PPRE_DIV2 RCC_D1CFGR_D1PPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
18218 #define RCC_D1CFGR_D1PPRE_DIV4_Pos (4U)
18219 #define RCC_D1CFGR_D1PPRE_DIV4_Msk (0x5UL << RCC_D1CFGR_D1PPRE_DIV4_Pos) /*!< 0x00000050 */
18220 #define RCC_D1CFGR_D1PPRE_DIV4 RCC_D1CFGR_D1PPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
18221 #define RCC_D1CFGR_D1PPRE_DIV8_Pos (5U)
18222 #define RCC_D1CFGR_D1PPRE_DIV8_Msk (0x3UL << RCC_D1CFGR_D1PPRE_DIV8_Pos) /*!< 0x00000060 */
18223 #define RCC_D1CFGR_D1PPRE_DIV8 RCC_D1CFGR_D1PPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
18224 #define RCC_D1CFGR_D1PPRE_DIV16_Pos (4U)
18225 #define RCC_D1CFGR_D1PPRE_DIV16_Msk (0x7UL << RCC_D1CFGR_D1PPRE_DIV16_Pos) /*!< 0x00000070 */
18226 #define RCC_D1CFGR_D1PPRE_DIV16 RCC_D1CFGR_D1PPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
18227
18228 #define RCC_D1CFGR_D1CPRE_Pos (8U)
18229 #define RCC_D1CFGR_D1CPRE_Msk (0xFUL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000F00 */
18230 #define RCC_D1CFGR_D1CPRE RCC_D1CFGR_D1CPRE_Msk /*!< D1CPRE[2:0] bits (Domain 1 Core prescaler) */
18231 #define RCC_D1CFGR_D1CPRE_0 (0x1UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000100 */
18232 #define RCC_D1CFGR_D1CPRE_1 (0x2UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000200 */
18233 #define RCC_D1CFGR_D1CPRE_2 (0x4UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000400 */
18234 #define RCC_D1CFGR_D1CPRE_3 (0x8UL << RCC_D1CFGR_D1CPRE_Pos) /*!< 0x00000800 */
18235
18236 #define RCC_D1CFGR_D1CPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
18237 #define RCC_D1CFGR_D1CPRE_DIV2_Pos (11U)
18238 #define RCC_D1CFGR_D1CPRE_DIV2_Msk (0x1UL << RCC_D1CFGR_D1CPRE_DIV2_Pos) /*!< 0x00000800 */
18239 #define RCC_D1CFGR_D1CPRE_DIV2 RCC_D1CFGR_D1CPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
18240 #define RCC_D1CFGR_D1CPRE_DIV4_Pos (8U)
18241 #define RCC_D1CFGR_D1CPRE_DIV4_Msk (0x9UL << RCC_D1CFGR_D1CPRE_DIV4_Pos) /*!< 0x00000900 */
18242 #define RCC_D1CFGR_D1CPRE_DIV4 RCC_D1CFGR_D1CPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
18243 #define RCC_D1CFGR_D1CPRE_DIV8_Pos (9U)
18244 #define RCC_D1CFGR_D1CPRE_DIV8_Msk (0x5UL << RCC_D1CFGR_D1CPRE_DIV8_Pos) /*!< 0x00000A00 */
18245 #define RCC_D1CFGR_D1CPRE_DIV8 RCC_D1CFGR_D1CPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
18246 #define RCC_D1CFGR_D1CPRE_DIV16_Pos (8U)
18247 #define RCC_D1CFGR_D1CPRE_DIV16_Msk (0xBUL << RCC_D1CFGR_D1CPRE_DIV16_Pos) /*!< 0x00000B00 */
18248 #define RCC_D1CFGR_D1CPRE_DIV16 RCC_D1CFGR_D1CPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
18249 #define RCC_D1CFGR_D1CPRE_DIV64_Pos (10U)
18250 #define RCC_D1CFGR_D1CPRE_DIV64_Msk (0x3UL << RCC_D1CFGR_D1CPRE_DIV64_Pos) /*!< 0x00000C00 */
18251 #define RCC_D1CFGR_D1CPRE_DIV64 RCC_D1CFGR_D1CPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
18252 #define RCC_D1CFGR_D1CPRE_DIV128_Pos (8U)
18253 #define RCC_D1CFGR_D1CPRE_DIV128_Msk (0xDUL << RCC_D1CFGR_D1CPRE_DIV128_Pos) /*!< 0x00000D00 */
18254 #define RCC_D1CFGR_D1CPRE_DIV128 RCC_D1CFGR_D1CPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
18255 #define RCC_D1CFGR_D1CPRE_DIV256_Pos (9U)
18256 #define RCC_D1CFGR_D1CPRE_DIV256_Msk (0x7UL << RCC_D1CFGR_D1CPRE_DIV256_Pos) /*!< 0x00000E00 */
18257 #define RCC_D1CFGR_D1CPRE_DIV256 RCC_D1CFGR_D1CPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
18258 #define RCC_D1CFGR_D1CPRE_DIV512_Pos (8U)
18259 #define RCC_D1CFGR_D1CPRE_DIV512_Msk (0xFUL << RCC_D1CFGR_D1CPRE_DIV512_Pos) /*!< 0x00000F00 */
18260 #define RCC_D1CFGR_D1CPRE_DIV512 RCC_D1CFGR_D1CPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
18261
18262 /******************** Bit definition for RCC_D2CFGR register ******************/
18263 /*!< D2PPRE1 configuration */
18264 #define RCC_D2CFGR_D2PPRE1_Pos (4U)
18265 #define RCC_D2CFGR_D2PPRE1_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000070 */
18266 #define RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
18267 #define RCC_D2CFGR_D2PPRE1_0 (0x1UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000010 */
18268 #define RCC_D2CFGR_D2PPRE1_1 (0x2UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000020 */
18269 #define RCC_D2CFGR_D2PPRE1_2 (0x4UL << RCC_D2CFGR_D2PPRE1_Pos) /*!< 0x00000040 */
18270
18271 #define RCC_D2CFGR_D2PPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
18272 #define RCC_D2CFGR_D2PPRE1_DIV2_Pos (6U)
18273 #define RCC_D2CFGR_D2PPRE1_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE1_DIV2_Pos) /*!< 0x00000040 */
18274 #define RCC_D2CFGR_D2PPRE1_DIV2 RCC_D2CFGR_D2PPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
18275 #define RCC_D2CFGR_D2PPRE1_DIV4_Pos (4U)
18276 #define RCC_D2CFGR_D2PPRE1_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE1_DIV4_Pos) /*!< 0x00000050 */
18277 #define RCC_D2CFGR_D2PPRE1_DIV4 RCC_D2CFGR_D2PPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
18278 #define RCC_D2CFGR_D2PPRE1_DIV8_Pos (5U)
18279 #define RCC_D2CFGR_D2PPRE1_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE1_DIV8_Pos) /*!< 0x00000060 */
18280 #define RCC_D2CFGR_D2PPRE1_DIV8 RCC_D2CFGR_D2PPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
18281 #define RCC_D2CFGR_D2PPRE1_DIV16_Pos (4U)
18282 #define RCC_D2CFGR_D2PPRE1_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE1_DIV16_Pos) /*!< 0x00000070 */
18283 #define RCC_D2CFGR_D2PPRE1_DIV16 RCC_D2CFGR_D2PPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
18284
18285 /*!< D2PPRE2 configuration */
18286 #define RCC_D2CFGR_D2PPRE2_Pos (8U)
18287 #define RCC_D2CFGR_D2PPRE2_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000700 */
18288 #define RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_Msk /*!< D2PPRE2[2:0] bits (APB2 prescaler) */
18289 #define RCC_D2CFGR_D2PPRE2_0 (0x1UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000100 */
18290 #define RCC_D2CFGR_D2PPRE2_1 (0x2UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000200 */
18291 #define RCC_D2CFGR_D2PPRE2_2 (0x4UL << RCC_D2CFGR_D2PPRE2_Pos) /*!< 0x00000400 */
18292
18293 #define RCC_D2CFGR_D2PPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
18294 #define RCC_D2CFGR_D2PPRE2_DIV2_Pos (10U)
18295 #define RCC_D2CFGR_D2PPRE2_DIV2_Msk (0x1UL << RCC_D2CFGR_D2PPRE2_DIV2_Pos) /*!< 0x00000400 */
18296 #define RCC_D2CFGR_D2PPRE2_DIV2 RCC_D2CFGR_D2PPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
18297 #define RCC_D2CFGR_D2PPRE2_DIV4_Pos (8U)
18298 #define RCC_D2CFGR_D2PPRE2_DIV4_Msk (0x5UL << RCC_D2CFGR_D2PPRE2_DIV4_Pos) /*!< 0x00000500 */
18299 #define RCC_D2CFGR_D2PPRE2_DIV4 RCC_D2CFGR_D2PPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
18300 #define RCC_D2CFGR_D2PPRE2_DIV8_Pos (9U)
18301 #define RCC_D2CFGR_D2PPRE2_DIV8_Msk (0x3UL << RCC_D2CFGR_D2PPRE2_DIV8_Pos) /*!< 0x00000600 */
18302 #define RCC_D2CFGR_D2PPRE2_DIV8 RCC_D2CFGR_D2PPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
18303 #define RCC_D2CFGR_D2PPRE2_DIV16_Pos (8U)
18304 #define RCC_D2CFGR_D2PPRE2_DIV16_Msk (0x7UL << RCC_D2CFGR_D2PPRE2_DIV16_Pos) /*!< 0x00000700 */
18305 #define RCC_D2CFGR_D2PPRE2_DIV16 RCC_D2CFGR_D2PPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
18306
18307 /******************** Bit definition for RCC_D3CFGR register ******************/
18308 /*!< D3PPRE configuration */
18309 #define RCC_D3CFGR_D3PPRE_Pos (4U)
18310 #define RCC_D3CFGR_D3PPRE_Msk (0x7UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000070 */
18311 #define RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_Msk /*!< D3PPRE1[2:0] bits (APB4 prescaler) */
18312 #define RCC_D3CFGR_D3PPRE_0 (0x1UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000010 */
18313 #define RCC_D3CFGR_D3PPRE_1 (0x2UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000020 */
18314 #define RCC_D3CFGR_D3PPRE_2 (0x4UL << RCC_D3CFGR_D3PPRE_Pos) /*!< 0x00000040 */
18315
18316 #define RCC_D3CFGR_D3PPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
18317 #define RCC_D3CFGR_D3PPRE_DIV2_Pos (6U)
18318 #define RCC_D3CFGR_D3PPRE_DIV2_Msk (0x1UL << RCC_D3CFGR_D3PPRE_DIV2_Pos) /*!< 0x00000040 */
18319 #define RCC_D3CFGR_D3PPRE_DIV2 RCC_D3CFGR_D3PPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
18320 #define RCC_D3CFGR_D3PPRE_DIV4_Pos (4U)
18321 #define RCC_D3CFGR_D3PPRE_DIV4_Msk (0x5UL << RCC_D3CFGR_D3PPRE_DIV4_Pos) /*!< 0x00000050 */
18322 #define RCC_D3CFGR_D3PPRE_DIV4 RCC_D3CFGR_D3PPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
18323 #define RCC_D3CFGR_D3PPRE_DIV8_Pos (5U)
18324 #define RCC_D3CFGR_D3PPRE_DIV8_Msk (0x3UL << RCC_D3CFGR_D3PPRE_DIV8_Pos) /*!< 0x00000060 */
18325 #define RCC_D3CFGR_D3PPRE_DIV8 RCC_D3CFGR_D3PPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
18326 #define RCC_D3CFGR_D3PPRE_DIV16_Pos (4U)
18327 #define RCC_D3CFGR_D3PPRE_DIV16_Msk (0x7UL << RCC_D3CFGR_D3PPRE_DIV16_Pos) /*!< 0x00000070 */
18328 #define RCC_D3CFGR_D3PPRE_DIV16 RCC_D3CFGR_D3PPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
18329
18330 /******************** Bit definition for RCC_PLLCKSELR register *************/
18331
18332 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
18333 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
18334 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
18335
18336 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
18337 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
18338 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
18339 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
18340 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
18341 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
18342 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
18343 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
18344 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
18345 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
18346
18347 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
18348 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
18349 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
18350 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
18351 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
18352 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
18353 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
18354 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
18355 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
18356
18357 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
18358 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
18359 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
18360 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
18361 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
18362 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
18363 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
18364 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
18365 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
18366
18367 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
18368 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
18369 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
18370 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
18371 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
18372 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
18373 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
18374 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
18375 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
18376
18377 /******************** Bit definition for RCC_PLLCFGR register ***************/
18378
18379 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
18380 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
18381 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
18382 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
18383 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
18384 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
18385 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
18386 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
18387 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
18388 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
18389 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
18390 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
18391 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
18392
18393 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
18394 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
18395 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
18396 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
18397 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
18398 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
18399 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
18400 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
18401 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
18402 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
18403 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
18404 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
18405 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
18406
18407 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
18408 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
18409 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
18410 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
18411 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
18412 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
18413 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
18414 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
18415 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
18416 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
18417 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
18418 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
18419 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
18420
18421 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
18422 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
18423 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
18424 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
18425 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
18426 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
18427 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
18428 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
18429 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
18430
18431 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
18432 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
18433 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
18434 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
18435 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
18436 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
18437 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
18438 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
18439 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
18440
18441 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
18442 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
18443 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
18444 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
18445 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
18446 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
18447 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
18448 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
18449 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
18450
18451
18452 /******************** Bit definition for RCC_PLL1DIVR register ***************/
18453 #define RCC_PLL1DIVR_N1_Pos (0U)
18454 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
18455 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
18456 #define RCC_PLL1DIVR_P1_Pos (9U)
18457 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
18458 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
18459 #define RCC_PLL1DIVR_Q1_Pos (16U)
18460 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
18461 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
18462 #define RCC_PLL1DIVR_R1_Pos (24U)
18463 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
18464 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
18465
18466 /******************** Bit definition for RCC_PLL1FRACR register ***************/
18467 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
18468 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
18469 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
18470
18471 /******************** Bit definition for RCC_PLL2DIVR register ***************/
18472 #define RCC_PLL2DIVR_N2_Pos (0U)
18473 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
18474 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
18475 #define RCC_PLL2DIVR_P2_Pos (9U)
18476 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
18477 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
18478 #define RCC_PLL2DIVR_Q2_Pos (16U)
18479 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
18480 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
18481 #define RCC_PLL2DIVR_R2_Pos (24U)
18482 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
18483 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
18484
18485 /******************** Bit definition for RCC_PLL2FRACR register ***************/
18486 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
18487 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
18488 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
18489
18490 /******************** Bit definition for RCC_PLL3DIVR register ***************/
18491 #define RCC_PLL3DIVR_N3_Pos (0U)
18492 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
18493 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
18494 #define RCC_PLL3DIVR_P3_Pos (9U)
18495 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
18496 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
18497 #define RCC_PLL3DIVR_Q3_Pos (16U)
18498 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
18499 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
18500 #define RCC_PLL3DIVR_R3_Pos (24U)
18501 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
18502 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
18503
18504 /******************** Bit definition for RCC_PLL3FRACR register ***************/
18505 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
18506 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
18507 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
18508
18509 /******************** Bit definition for RCC_D1CCIPR register ***************/
18510 #define RCC_D1CCIPR_FMCSEL_Pos (0U)
18511 #define RCC_D1CCIPR_FMCSEL_Msk (0x3UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000003 */
18512 #define RCC_D1CCIPR_FMCSEL RCC_D1CCIPR_FMCSEL_Msk
18513 #define RCC_D1CCIPR_FMCSEL_0 (0x1UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000001 */
18514 #define RCC_D1CCIPR_FMCSEL_1 (0x2UL << RCC_D1CCIPR_FMCSEL_Pos) /*!< 0x00000002 */
18515 #define RCC_D1CCIPR_QSPISEL_Pos (4U)
18516 #define RCC_D1CCIPR_QSPISEL_Msk (0x3UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000030 */
18517 #define RCC_D1CCIPR_QSPISEL RCC_D1CCIPR_QSPISEL_Msk
18518 #define RCC_D1CCIPR_QSPISEL_0 (0x1UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000010 */
18519 #define RCC_D1CCIPR_QSPISEL_1 (0x2UL << RCC_D1CCIPR_QSPISEL_Pos) /*!< 0x00000020 */
18520 #define RCC_D1CCIPR_DSISEL_Pos (8U)
18521 #define RCC_D1CCIPR_DSISEL_Msk (0x1UL << RCC_D1CCIPR_DSISEL_Pos) /*!< 0x00000100 */
18522 #define RCC_D1CCIPR_DSISEL RCC_D1CCIPR_DSISEL_Msk
18523 #define RCC_D1CCIPR_SDMMCSEL_Pos (16U)
18524 #define RCC_D1CCIPR_SDMMCSEL_Msk (0x1UL << RCC_D1CCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
18525 #define RCC_D1CCIPR_SDMMCSEL RCC_D1CCIPR_SDMMCSEL_Msk
18526 #define RCC_D1CCIPR_CKPERSEL_Pos (28U)
18527 #define RCC_D1CCIPR_CKPERSEL_Msk (0x3UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
18528 #define RCC_D1CCIPR_CKPERSEL RCC_D1CCIPR_CKPERSEL_Msk
18529 #define RCC_D1CCIPR_CKPERSEL_0 (0x1UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
18530 #define RCC_D1CCIPR_CKPERSEL_1 (0x2UL << RCC_D1CCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
18531
18532 /******************** Bit definition for RCC_D2CCIP1R register ***************/
18533 #define RCC_D2CCIP1R_SAI1SEL_Pos (0U)
18534 #define RCC_D2CCIP1R_SAI1SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
18535 #define RCC_D2CCIP1R_SAI1SEL RCC_D2CCIP1R_SAI1SEL_Msk
18536 #define RCC_D2CCIP1R_SAI1SEL_0 (0x1UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
18537 #define RCC_D2CCIP1R_SAI1SEL_1 (0x2UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
18538 #define RCC_D2CCIP1R_SAI1SEL_2 (0x4UL << RCC_D2CCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
18539
18540 #define RCC_D2CCIP1R_SAI23SEL_Pos (6U)
18541 #define RCC_D2CCIP1R_SAI23SEL_Msk (0x7UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x000001C0 */
18542 #define RCC_D2CCIP1R_SAI23SEL RCC_D2CCIP1R_SAI23SEL_Msk
18543 #define RCC_D2CCIP1R_SAI23SEL_0 (0x1UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000040 */
18544 #define RCC_D2CCIP1R_SAI23SEL_1 (0x2UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000080 */
18545 #define RCC_D2CCIP1R_SAI23SEL_2 (0x4UL << RCC_D2CCIP1R_SAI23SEL_Pos) /*!< 0x00000100 */
18546
18547 #define RCC_D2CCIP1R_SPI123SEL_Pos (12U)
18548 #define RCC_D2CCIP1R_SPI123SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
18549 #define RCC_D2CCIP1R_SPI123SEL RCC_D2CCIP1R_SPI123SEL_Msk
18550 #define RCC_D2CCIP1R_SPI123SEL_0 (0x1UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
18551 #define RCC_D2CCIP1R_SPI123SEL_1 (0x2UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
18552 #define RCC_D2CCIP1R_SPI123SEL_2 (0x4UL << RCC_D2CCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
18553
18554 #define RCC_D2CCIP1R_SPI45SEL_Pos (16U)
18555 #define RCC_D2CCIP1R_SPI45SEL_Msk (0x7UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
18556 #define RCC_D2CCIP1R_SPI45SEL RCC_D2CCIP1R_SPI45SEL_Msk
18557 #define RCC_D2CCIP1R_SPI45SEL_0 (0x1UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
18558 #define RCC_D2CCIP1R_SPI45SEL_1 (0x2UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
18559 #define RCC_D2CCIP1R_SPI45SEL_2 (0x4UL << RCC_D2CCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
18560
18561 #define RCC_D2CCIP1R_SPDIFSEL_Pos (20U)
18562 #define RCC_D2CCIP1R_SPDIFSEL_Msk (0x3UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
18563 #define RCC_D2CCIP1R_SPDIFSEL RCC_D2CCIP1R_SPDIFSEL_Msk
18564 #define RCC_D2CCIP1R_SPDIFSEL_0 (0x1UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
18565 #define RCC_D2CCIP1R_SPDIFSEL_1 (0x2UL << RCC_D2CCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
18566
18567 #define RCC_D2CCIP1R_DFSDM1SEL_Pos (24U)
18568 #define RCC_D2CCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_D2CCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
18569 #define RCC_D2CCIP1R_DFSDM1SEL RCC_D2CCIP1R_DFSDM1SEL_Msk
18570
18571 #define RCC_D2CCIP1R_FDCANSEL_Pos (28U)
18572 #define RCC_D2CCIP1R_FDCANSEL_Msk (0x3UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
18573 #define RCC_D2CCIP1R_FDCANSEL RCC_D2CCIP1R_FDCANSEL_Msk
18574 #define RCC_D2CCIP1R_FDCANSEL_0 (0x1UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
18575 #define RCC_D2CCIP1R_FDCANSEL_1 (0x2UL << RCC_D2CCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
18576
18577 #define RCC_D2CCIP1R_SWPSEL_Pos (31U)
18578 #define RCC_D2CCIP1R_SWPSEL_Msk (0x1UL << RCC_D2CCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
18579 #define RCC_D2CCIP1R_SWPSEL RCC_D2CCIP1R_SWPSEL_Msk
18580
18581 /******************** Bit definition for RCC_D2CCIP2R register ***************/
18582 #define RCC_D2CCIP2R_USART16SEL_Pos (3U)
18583 #define RCC_D2CCIP2R_USART16SEL_Msk (0x7UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000038 */
18584 #define RCC_D2CCIP2R_USART16SEL RCC_D2CCIP2R_USART16SEL_Msk
18585 #define RCC_D2CCIP2R_USART16SEL_0 (0x1UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000008 */
18586 #define RCC_D2CCIP2R_USART16SEL_1 (0x2UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000010 */
18587 #define RCC_D2CCIP2R_USART16SEL_2 (0x4UL << RCC_D2CCIP2R_USART16SEL_Pos) /*!< 0x00000020 */
18588
18589 #define RCC_D2CCIP2R_USART28SEL_Pos (0U)
18590 #define RCC_D2CCIP2R_USART28SEL_Msk (0x7UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000007 */
18591 #define RCC_D2CCIP2R_USART28SEL RCC_D2CCIP2R_USART28SEL_Msk
18592 #define RCC_D2CCIP2R_USART28SEL_0 (0x1UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000001 */
18593 #define RCC_D2CCIP2R_USART28SEL_1 (0x2UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000002 */
18594 #define RCC_D2CCIP2R_USART28SEL_2 (0x4UL << RCC_D2CCIP2R_USART28SEL_Pos) /*!< 0x00000004 */
18595
18596 #define RCC_D2CCIP2R_RNGSEL_Pos (8U)
18597 #define RCC_D2CCIP2R_RNGSEL_Msk (0x3UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
18598 #define RCC_D2CCIP2R_RNGSEL RCC_D2CCIP2R_RNGSEL_Msk
18599 #define RCC_D2CCIP2R_RNGSEL_0 (0x1UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
18600 #define RCC_D2CCIP2R_RNGSEL_1 (0x2UL << RCC_D2CCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
18601
18602 #define RCC_D2CCIP2R_I2C123SEL_Pos (12U)
18603 #define RCC_D2CCIP2R_I2C123SEL_Msk (0x3UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
18604 #define RCC_D2CCIP2R_I2C123SEL RCC_D2CCIP2R_I2C123SEL_Msk
18605 #define RCC_D2CCIP2R_I2C123SEL_0 (0x1UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
18606 #define RCC_D2CCIP2R_I2C123SEL_1 (0x2UL << RCC_D2CCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
18607
18608 #define RCC_D2CCIP2R_USBSEL_Pos (20U)
18609 #define RCC_D2CCIP2R_USBSEL_Msk (0x3UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00300000 */
18610 #define RCC_D2CCIP2R_USBSEL RCC_D2CCIP2R_USBSEL_Msk
18611 #define RCC_D2CCIP2R_USBSEL_0 (0x1UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00100000 */
18612 #define RCC_D2CCIP2R_USBSEL_1 (0x2UL << RCC_D2CCIP2R_USBSEL_Pos) /*!< 0x00200000 */
18613
18614 #define RCC_D2CCIP2R_CECSEL_Pos (22U)
18615 #define RCC_D2CCIP2R_CECSEL_Msk (0x3UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
18616 #define RCC_D2CCIP2R_CECSEL RCC_D2CCIP2R_CECSEL_Msk
18617 #define RCC_D2CCIP2R_CECSEL_0 (0x1UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00400000 */
18618 #define RCC_D2CCIP2R_CECSEL_1 (0x2UL << RCC_D2CCIP2R_CECSEL_Pos) /*!< 0x00800000 */
18619
18620 #define RCC_D2CCIP2R_LPTIM1SEL_Pos (28U)
18621 #define RCC_D2CCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
18622 #define RCC_D2CCIP2R_LPTIM1SEL RCC_D2CCIP2R_LPTIM1SEL_Msk
18623 #define RCC_D2CCIP2R_LPTIM1SEL_0 (0x1UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
18624 #define RCC_D2CCIP2R_LPTIM1SEL_1 (0x2UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
18625 #define RCC_D2CCIP2R_LPTIM1SEL_2 (0x4UL << RCC_D2CCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
18626
18627 /******************** Bit definition for RCC_D3CCIPR register ***************/
18628 #define RCC_D3CCIPR_LPUART1SEL_Pos (0U)
18629 #define RCC_D3CCIPR_LPUART1SEL_Msk (0x7UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
18630 #define RCC_D3CCIPR_LPUART1SEL RCC_D3CCIPR_LPUART1SEL_Msk
18631 #define RCC_D3CCIPR_LPUART1SEL_0 (0x1UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
18632 #define RCC_D3CCIPR_LPUART1SEL_1 (0x2UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
18633 #define RCC_D3CCIPR_LPUART1SEL_2 (0x4UL << RCC_D3CCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
18634
18635 #define RCC_D3CCIPR_I2C4SEL_Pos (8U)
18636 #define RCC_D3CCIPR_I2C4SEL_Msk (0x3UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
18637 #define RCC_D3CCIPR_I2C4SEL RCC_D3CCIPR_I2C4SEL_Msk
18638 #define RCC_D3CCIPR_I2C4SEL_0 (0x1UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
18639 #define RCC_D3CCIPR_I2C4SEL_1 (0x2UL << RCC_D3CCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
18640
18641 #define RCC_D3CCIPR_LPTIM2SEL_Pos (10U)
18642 #define RCC_D3CCIPR_LPTIM2SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
18643 #define RCC_D3CCIPR_LPTIM2SEL RCC_D3CCIPR_LPTIM2SEL_Msk
18644 #define RCC_D3CCIPR_LPTIM2SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
18645 #define RCC_D3CCIPR_LPTIM2SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
18646 #define RCC_D3CCIPR_LPTIM2SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
18647
18648 #define RCC_D3CCIPR_LPTIM345SEL_Pos (13U)
18649 #define RCC_D3CCIPR_LPTIM345SEL_Msk (0x7UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x0000E000 */
18650 #define RCC_D3CCIPR_LPTIM345SEL RCC_D3CCIPR_LPTIM345SEL_Msk
18651 #define RCC_D3CCIPR_LPTIM345SEL_0 (0x1UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00002000 */
18652 #define RCC_D3CCIPR_LPTIM345SEL_1 (0x2UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00004000 */
18653 #define RCC_D3CCIPR_LPTIM345SEL_2 (0x4UL << RCC_D3CCIPR_LPTIM345SEL_Pos) /*!< 0x00008000 */
18654
18655 #define RCC_D3CCIPR_SAI4ASEL_Pos (21U)
18656 #define RCC_D3CCIPR_SAI4ASEL_Msk (0x7UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00E00000 */
18657 #define RCC_D3CCIPR_SAI4ASEL RCC_D3CCIPR_SAI4ASEL_Msk
18658 #define RCC_D3CCIPR_SAI4ASEL_0 (0x1UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00200000 */
18659 #define RCC_D3CCIPR_SAI4ASEL_1 (0x2UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00400000 */
18660 #define RCC_D3CCIPR_SAI4ASEL_2 (0x4UL << RCC_D3CCIPR_SAI4ASEL_Pos) /*!< 0x00800000 */
18661
18662 #define RCC_D3CCIPR_SAI4BSEL_Pos (24U)
18663 #define RCC_D3CCIPR_SAI4BSEL_Msk (0x7UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x07000000 */
18664 #define RCC_D3CCIPR_SAI4BSEL RCC_D3CCIPR_SAI4BSEL_Msk
18665 #define RCC_D3CCIPR_SAI4BSEL_0 (0x1UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x01000000 */
18666 #define RCC_D3CCIPR_SAI4BSEL_1 (0x2UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x02000000 */
18667 #define RCC_D3CCIPR_SAI4BSEL_2 (0x4UL << RCC_D3CCIPR_SAI4BSEL_Pos) /*!< 0x04000000 */
18668
18669 #define RCC_D3CCIPR_ADCSEL_Pos (16U)
18670 #define RCC_D3CCIPR_ADCSEL_Msk (0x3UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00030000 */
18671 #define RCC_D3CCIPR_ADCSEL RCC_D3CCIPR_ADCSEL_Msk
18672 #define RCC_D3CCIPR_ADCSEL_0 (0x1UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00010000 */
18673 #define RCC_D3CCIPR_ADCSEL_1 (0x2UL << RCC_D3CCIPR_ADCSEL_Pos) /*!< 0x00020000 */
18674
18675 #define RCC_D3CCIPR_SPI6SEL_Pos (28U)
18676 #define RCC_D3CCIPR_SPI6SEL_Msk (0x7UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
18677 #define RCC_D3CCIPR_SPI6SEL RCC_D3CCIPR_SPI6SEL_Msk
18678 #define RCC_D3CCIPR_SPI6SEL_0 (0x1UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
18679 #define RCC_D3CCIPR_SPI6SEL_1 (0x2UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
18680 #define RCC_D3CCIPR_SPI6SEL_2 (0x4UL << RCC_D3CCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
18681 /******************** Bit definition for RCC_CIER register ******************/
18682 #define RCC_CIER_LSIRDYIE_Pos (0U)
18683 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
18684 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
18685 #define RCC_CIER_LSERDYIE_Pos (1U)
18686 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
18687 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
18688 #define RCC_CIER_HSIRDYIE_Pos (2U)
18689 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
18690 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
18691 #define RCC_CIER_HSERDYIE_Pos (3U)
18692 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
18693 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
18694 #define RCC_CIER_CSIRDYIE_Pos (4U)
18695 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
18696 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
18697 #define RCC_CIER_HSI48RDYIE_Pos (5U)
18698 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
18699 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
18700 #define RCC_CIER_PLL1RDYIE_Pos (6U)
18701 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
18702 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
18703 #define RCC_CIER_PLL2RDYIE_Pos (7U)
18704 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
18705 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
18706 #define RCC_CIER_PLL3RDYIE_Pos (8U)
18707 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
18708 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
18709 #define RCC_CIER_LSECSSIE_Pos (9U)
18710 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
18711 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
18712
18713 /******************** Bit definition for RCC_CIFR register ******************/
18714 #define RCC_CIFR_LSIRDYF_Pos (0U)
18715 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
18716 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
18717 #define RCC_CIFR_LSERDYF_Pos (1U)
18718 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
18719 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
18720 #define RCC_CIFR_HSIRDYF_Pos (2U)
18721 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
18722 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
18723 #define RCC_CIFR_HSERDYF_Pos (3U)
18724 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
18725 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
18726 #define RCC_CIFR_CSIRDYF_Pos (4U)
18727 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
18728 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
18729 #define RCC_CIFR_HSI48RDYF_Pos (5U)
18730 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
18731 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
18732 #define RCC_CIFR_PLLRDYF_Pos (6U)
18733 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
18734 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
18735 #define RCC_CIFR_PLL2RDYF_Pos (7U)
18736 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
18737 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
18738 #define RCC_CIFR_PLL3RDYF_Pos (8U)
18739 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
18740 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
18741 #define RCC_CIFR_LSECSSF_Pos (9U)
18742 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
18743 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
18744 #define RCC_CIFR_HSECSSF_Pos (10U)
18745 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
18746 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
18747
18748 /******************** Bit definition for RCC_CICR register ******************/
18749 #define RCC_CICR_LSIRDYC_Pos (0U)
18750 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
18751 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
18752 #define RCC_CICR_LSERDYC_Pos (1U)
18753 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
18754 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
18755 #define RCC_CICR_HSIRDYC_Pos (2U)
18756 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
18757 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
18758 #define RCC_CICR_HSERDYC_Pos (3U)
18759 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
18760 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
18761 #define RCC_CICR_CSIRDYC_Pos (4U)
18762 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
18763 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
18764 #define RCC_CICR_HSI48RDYC_Pos (5U)
18765 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
18766 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
18767 #define RCC_CICR_PLLRDYC_Pos (6U)
18768 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
18769 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
18770 #define RCC_CICR_PLL2RDYC_Pos (7U)
18771 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
18772 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
18773 #define RCC_CICR_PLL3RDYC_Pos (8U)
18774 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
18775 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
18776 #define RCC_CICR_LSECSSC_Pos (9U)
18777 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
18778 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
18779 #define RCC_CICR_HSECSSC_Pos (10U)
18780 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
18781 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
18782
18783 /******************** Bit definition for RCC_BDCR register ******************/
18784 #define RCC_BDCR_LSEON_Pos (0U)
18785 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
18786 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
18787 #define RCC_BDCR_LSERDY_Pos (1U)
18788 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
18789 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
18790 #define RCC_BDCR_LSEBYP_Pos (2U)
18791 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
18792 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
18793
18794 #define RCC_BDCR_LSEDRV_Pos (3U)
18795 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
18796 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
18797 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
18798 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
18799
18800 #define RCC_BDCR_LSECSSON_Pos (5U)
18801 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
18802 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
18803 #define RCC_BDCR_LSECSSD_Pos (6U)
18804 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
18805 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
18806
18807 #define RCC_BDCR_RTCSEL_Pos (8U)
18808 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
18809 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
18810 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
18811 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
18812
18813 #define RCC_BDCR_RTCEN_Pos (15U)
18814 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
18815 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
18816 #define RCC_BDCR_BDRST_Pos (16U)
18817 #define RCC_BDCR_BDRST_Msk (0x1UL << RCC_BDCR_BDRST_Pos) /*!< 0x00010000 */
18818 #define RCC_BDCR_BDRST RCC_BDCR_BDRST_Msk
18819 /******************** Bit definition for RCC_CSR register *******************/
18820 #define RCC_CSR_LSION_Pos (0U)
18821 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
18822 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
18823 #define RCC_CSR_LSIRDY_Pos (1U)
18824 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
18825 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
18826
18827
18828 /******************** Bit definition for RCC_AHB3ENR register **************/
18829 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
18830 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
18831 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
18832 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
18833 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
18834 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
18835 #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
18836 #define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
18837 #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
18838 #define RCC_AHB3ENR_FMCEN_Pos (12U)
18839 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
18840 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
18841 #define RCC_AHB3ENR_QSPIEN_Pos (14U)
18842 #define RCC_AHB3ENR_QSPIEN_Msk (0x1UL << RCC_AHB3ENR_QSPIEN_Pos) /*!< 0x00004000 */
18843 #define RCC_AHB3ENR_QSPIEN RCC_AHB3ENR_QSPIEN_Msk
18844 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
18845 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
18846 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
18847 #define RCC_AHB3ENR_FLASHEN_Pos (8U)
18848 #define RCC_AHB3ENR_FLASHEN_Msk (0x1UL << RCC_AHB3ENR_FLASHEN_Pos) /*!< 0x00000100 */
18849 #define RCC_AHB3ENR_FLASHEN RCC_AHB3ENR_FLASHEN_Msk
18850 #define RCC_AHB3ENR_DTCM1EN_Pos (28U)
18851 #define RCC_AHB3ENR_DTCM1EN_Msk (0x1UL << RCC_AHB3ENR_DTCM1EN_Pos) /*!< 0x10000000 */
18852 #define RCC_AHB3ENR_DTCM1EN RCC_AHB3ENR_DTCM1EN_Msk
18853 #define RCC_AHB3ENR_DTCM2EN_Pos (29U)
18854 #define RCC_AHB3ENR_DTCM2EN_Msk (0x1UL << RCC_AHB3ENR_DTCM2EN_Pos) /*!< 0x20000000 */
18855 #define RCC_AHB3ENR_DTCM2EN RCC_AHB3ENR_DTCM2EN_Msk
18856 #define RCC_AHB3ENR_ITCMEN_Pos (30U)
18857 #define RCC_AHB3ENR_ITCMEN_Msk (0x1UL << RCC_AHB3ENR_ITCMEN_Pos) /*!< 0x40000000 */
18858 #define RCC_AHB3ENR_ITCMEN RCC_AHB3ENR_ITCMEN_Msk
18859 #define RCC_AHB3ENR_AXISRAMEN_Pos (31U)
18860 #define RCC_AHB3ENR_AXISRAMEN_Msk (0x1UL << RCC_AHB3ENR_AXISRAMEN_Pos) /*!< 0x80000000 */
18861 #define RCC_AHB3ENR_AXISRAMEN RCC_AHB3ENR_AXISRAMEN_Msk
18862
18863 /* Legacy define */
18864 #define RCC_AHB3ENR_D1SRAM1EN_Pos RCC_AHB3ENR_AXISRAMEN_Pos
18865 #define RCC_AHB3ENR_D1SRAM1EN_Msk RCC_AHB3ENR_AXISRAMEN_Msk
18866 #define RCC_AHB3ENR_D1SRAM1EN RCC_AHB3ENR_AXISRAMEN
18867
18868 /******************** Bit definition for RCC_AHB1ENR register ***************/
18869 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
18870 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
18871 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
18872 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
18873 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
18874 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
18875 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
18876 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
18877 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
18878 #define RCC_AHB1ENR_ARTEN_Pos (14U)
18879 #define RCC_AHB1ENR_ARTEN_Msk (0x1UL << RCC_AHB1ENR_ARTEN_Pos) /*!< 0x00004000 */
18880 #define RCC_AHB1ENR_ARTEN RCC_AHB1ENR_ARTEN_Msk
18881 #define RCC_AHB1ENR_ETH1MACEN_Pos (15U)
18882 #define RCC_AHB1ENR_ETH1MACEN_Msk (0x1UL << RCC_AHB1ENR_ETH1MACEN_Pos) /*!< 0x00008000 */
18883 #define RCC_AHB1ENR_ETH1MACEN RCC_AHB1ENR_ETH1MACEN_Msk
18884 #define RCC_AHB1ENR_ETH1TXEN_Pos (16U)
18885 #define RCC_AHB1ENR_ETH1TXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1TXEN_Pos) /*!< 0x00010000 */
18886 #define RCC_AHB1ENR_ETH1TXEN RCC_AHB1ENR_ETH1TXEN_Msk
18887 #define RCC_AHB1ENR_ETH1RXEN_Pos (17U)
18888 #define RCC_AHB1ENR_ETH1RXEN_Msk (0x1UL << RCC_AHB1ENR_ETH1RXEN_Pos) /*!< 0x00020000 */
18889 #define RCC_AHB1ENR_ETH1RXEN RCC_AHB1ENR_ETH1RXEN_Msk
18890 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
18891 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
18892 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
18893 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
18894 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
18895 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
18896 #define RCC_AHB1ENR_USB2OTGFSEN_Pos (27U)
18897 #define RCC_AHB1ENR_USB2OTGFSEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSEN_Pos) /*!< 0x08000000 */
18898 #define RCC_AHB1ENR_USB2OTGFSEN RCC_AHB1ENR_USB2OTGFSEN_Msk
18899 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Pos (28U)
18900 #define RCC_AHB1ENR_USB2OTGFSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB2OTGFSULPIEN_Pos) /*!< 0x10000000 */
18901 #define RCC_AHB1ENR_USB2OTGFSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
18902
18903 /* Legacy define */
18904 #define RCC_AHB1ENR_USB2OTGHSEN_Pos RCC_AHB1ENR_USB2OTGFSEN_Pos
18905 #define RCC_AHB1ENR_USB2OTGHSEN_Msk RCC_AHB1ENR_USB2OTGFSEN_Msk
18906 #define RCC_AHB1ENR_USB2OTGHSEN RCC_AHB1ENR_USB2OTGFSEN
18907 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Pos RCC_AHB1ENR_USB2OTGFSULPIEN_Pos
18908 #define RCC_AHB1ENR_USB2OTGHSULPIEN_Msk RCC_AHB1ENR_USB2OTGFSULPIEN_Msk
18909 #define RCC_AHB1ENR_USB2OTGHSULPIEN RCC_AHB1ENR_USB2OTGFSULPIEN
18910
18911
18912 /******************** Bit definition for RCC_AHB2ENR register ***************/
18913 #define RCC_AHB2ENR_DCMIEN_Pos (0U)
18914 #define RCC_AHB2ENR_DCMIEN_Msk (0x1UL << RCC_AHB2ENR_DCMIEN_Pos) /*!< 0x00000001 */
18915 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMIEN_Msk
18916 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
18917 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
18918 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
18919 #define RCC_AHB2ENR_HASHEN_Pos (5U)
18920 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
18921 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
18922 #define RCC_AHB2ENR_RNGEN_Pos (6U)
18923 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
18924 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
18925 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
18926 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
18927 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
18928 #define RCC_AHB2ENR_SRAM1EN_Pos (29U)
18929 #define RCC_AHB2ENR_SRAM1EN_Msk (0x1UL << RCC_AHB2ENR_SRAM1EN_Pos) /*!< 0x20000000 */
18930 #define RCC_AHB2ENR_SRAM1EN RCC_AHB2ENR_SRAM1EN_Msk
18931 #define RCC_AHB2ENR_SRAM2EN_Pos (30U)
18932 #define RCC_AHB2ENR_SRAM2EN_Msk (0x1UL << RCC_AHB2ENR_SRAM2EN_Pos) /*!< 0x40000000 */
18933 #define RCC_AHB2ENR_SRAM2EN RCC_AHB2ENR_SRAM2EN_Msk
18934 #define RCC_AHB2ENR_SRAM3EN_Pos (31U)
18935 #define RCC_AHB2ENR_SRAM3EN_Msk (0x1UL << RCC_AHB2ENR_SRAM3EN_Pos) /*!< 0x80000000 */
18936 #define RCC_AHB2ENR_SRAM3EN RCC_AHB2ENR_SRAM3EN_Msk
18937
18938 /* Legacy define */
18939 #define RCC_AHB2ENR_D2SRAM1EN_Pos RCC_AHB2ENR_SRAM1EN_Pos
18940 #define RCC_AHB2ENR_D2SRAM1EN_Msk RCC_AHB2ENR_SRAM1EN_Msk
18941 #define RCC_AHB2ENR_D2SRAM1EN RCC_AHB2ENR_SRAM1EN
18942 #define RCC_AHB2ENR_D2SRAM2EN_Pos RCC_AHB2ENR_SRAM2EN_Pos
18943 #define RCC_AHB2ENR_D2SRAM2EN_Msk RCC_AHB2ENR_SRAM2EN_Msk
18944 #define RCC_AHB2ENR_D2SRAM2EN RCC_AHB2ENR_SRAM2EN
18945 #define RCC_AHB2ENR_D2SRAM3EN_Pos RCC_AHB2ENR_SRAM3EN_Pos
18946 #define RCC_AHB2ENR_D2SRAM3EN_Msk RCC_AHB2ENR_SRAM3EN_Msk
18947 #define RCC_AHB2ENR_D2SRAM3EN RCC_AHB2ENR_SRAM3EN
18948
18949 /******************** Bit definition for RCC_AHB4ENR register ******************/
18950 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
18951 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
18952 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
18953 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
18954 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
18955 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
18956 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
18957 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
18958 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
18959 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
18960 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
18961 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
18962 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
18963 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
18964 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
18965 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
18966 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
18967 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
18968 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
18969 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
18970 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
18971 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
18972 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
18973 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
18974 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
18975 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
18976 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
18977 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
18978 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
18979 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
18980 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
18981 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
18982 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
18983 #define RCC_AHB4ENR_CRCEN_Pos (19U)
18984 #define RCC_AHB4ENR_CRCEN_Msk (0x1UL << RCC_AHB4ENR_CRCEN_Pos) /*!< 0x00080000 */
18985 #define RCC_AHB4ENR_CRCEN RCC_AHB4ENR_CRCEN_Msk
18986 #define RCC_AHB4ENR_BDMAEN_Pos (21U)
18987 #define RCC_AHB4ENR_BDMAEN_Msk (0x1UL << RCC_AHB4ENR_BDMAEN_Pos) /*!< 0x00200000 */
18988 #define RCC_AHB4ENR_BDMAEN RCC_AHB4ENR_BDMAEN_Msk
18989 #define RCC_AHB4ENR_ADC3EN_Pos (24U)
18990 #define RCC_AHB4ENR_ADC3EN_Msk (0x1UL << RCC_AHB4ENR_ADC3EN_Pos) /*!< 0x01000000 */
18991 #define RCC_AHB4ENR_ADC3EN RCC_AHB4ENR_ADC3EN_Msk
18992 #define RCC_AHB4ENR_HSEMEN_Pos (25U)
18993 #define RCC_AHB4ENR_HSEMEN_Msk (0x1UL << RCC_AHB4ENR_HSEMEN_Pos) /*!< 0x02000000 */
18994 #define RCC_AHB4ENR_HSEMEN RCC_AHB4ENR_HSEMEN_Msk
18995 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
18996 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
18997 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
18998
18999 /******************** Bit definition for RCC_APB3ENR register ******************/
19000 #define RCC_APB3ENR_LTDCEN_Pos (3U)
19001 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
19002 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
19003 #define RCC_APB3ENR_DSIEN_Pos (4U)
19004 #define RCC_APB3ENR_DSIEN_Msk (0x1UL << RCC_APB3ENR_DSIEN_Pos) /*!< 0x00000010 */
19005 #define RCC_APB3ENR_DSIEN RCC_APB3ENR_DSIEN_Msk
19006 #define RCC_APB3ENR_WWDG1EN_Pos (6U)
19007 #define RCC_APB3ENR_WWDG1EN_Msk (0x1UL << RCC_APB3ENR_WWDG1EN_Pos) /*!< 0x00000040 */
19008 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDG1EN_Msk
19009
19010 /******************** Bit definition for RCC_APB1LENR register ******************/
19011
19012 #define RCC_APB1LENR_TIM2EN_Pos (0U)
19013 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
19014 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
19015 #define RCC_APB1LENR_TIM3EN_Pos (1U)
19016 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
19017 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
19018 #define RCC_APB1LENR_TIM4EN_Pos (2U)
19019 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
19020 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
19021 #define RCC_APB1LENR_TIM5EN_Pos (3U)
19022 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
19023 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
19024 #define RCC_APB1LENR_TIM6EN_Pos (4U)
19025 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
19026 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
19027 #define RCC_APB1LENR_TIM7EN_Pos (5U)
19028 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
19029 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
19030 #define RCC_APB1LENR_TIM12EN_Pos (6U)
19031 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
19032 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
19033 #define RCC_APB1LENR_TIM13EN_Pos (7U)
19034 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
19035 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
19036 #define RCC_APB1LENR_TIM14EN_Pos (8U)
19037 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
19038 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
19039 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
19040 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
19041 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
19042
19043 #define RCC_APB1LENR_WWDG2EN_Pos (11U)
19044 #define RCC_APB1LENR_WWDG2EN_Msk (0x1UL << RCC_APB1LENR_WWDG2EN_Pos) /*!< 0x00000800 */
19045 #define RCC_APB1LENR_WWDG2EN RCC_APB1LENR_WWDG2EN_Msk
19046
19047 #define RCC_APB1LENR_SPI2EN_Pos (14U)
19048 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
19049 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
19050 #define RCC_APB1LENR_SPI3EN_Pos (15U)
19051 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
19052 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
19053 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
19054 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
19055 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
19056 #define RCC_APB1LENR_USART2EN_Pos (17U)
19057 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
19058 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
19059 #define RCC_APB1LENR_USART3EN_Pos (18U)
19060 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
19061 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
19062 #define RCC_APB1LENR_UART4EN_Pos (19U)
19063 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
19064 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
19065 #define RCC_APB1LENR_UART5EN_Pos (20U)
19066 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
19067 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
19068 #define RCC_APB1LENR_I2C1EN_Pos (21U)
19069 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
19070 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
19071 #define RCC_APB1LENR_I2C2EN_Pos (22U)
19072 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
19073 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
19074 #define RCC_APB1LENR_I2C3EN_Pos (23U)
19075 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
19076 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
19077 #define RCC_APB1LENR_CECEN_Pos (27U)
19078 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
19079 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
19080 #define RCC_APB1LENR_DAC12EN_Pos (29U)
19081 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
19082 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
19083 #define RCC_APB1LENR_UART7EN_Pos (30U)
19084 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
19085 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
19086 #define RCC_APB1LENR_UART8EN_Pos (31U)
19087 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
19088 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
19089
19090 /* Legacy define */
19091 #define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
19092 #define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
19093 #define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
19094 /******************** Bit definition for RCC_APB1HENR register ******************/
19095 #define RCC_APB1HENR_CRSEN_Pos (1U)
19096 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
19097 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
19098 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
19099 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
19100 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
19101 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
19102 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
19103 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
19104 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
19105 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
19106 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
19107 #define RCC_APB1HENR_FDCANEN_Pos (8U)
19108 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
19109 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
19110
19111 /******************** Bit definition for RCC_APB2ENR register ******************/
19112 #define RCC_APB2ENR_TIM1EN_Pos (0U)
19113 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
19114 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
19115 #define RCC_APB2ENR_TIM8EN_Pos (1U)
19116 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
19117 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
19118 #define RCC_APB2ENR_USART1EN_Pos (4U)
19119 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
19120 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
19121 #define RCC_APB2ENR_USART6EN_Pos (5U)
19122 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
19123 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
19124 #define RCC_APB2ENR_SPI1EN_Pos (12U)
19125 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
19126 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
19127 #define RCC_APB2ENR_SPI4EN_Pos (13U)
19128 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
19129 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
19130 #define RCC_APB2ENR_TIM15EN_Pos (16U)
19131 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
19132 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
19133 #define RCC_APB2ENR_TIM16EN_Pos (17U)
19134 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
19135 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
19136 #define RCC_APB2ENR_TIM17EN_Pos (18U)
19137 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
19138 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
19139 #define RCC_APB2ENR_SPI5EN_Pos (20U)
19140 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
19141 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
19142 #define RCC_APB2ENR_SAI1EN_Pos (22U)
19143 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
19144 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
19145 #define RCC_APB2ENR_SAI2EN_Pos (23U)
19146 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
19147 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
19148 #define RCC_APB2ENR_SAI3EN_Pos (24U)
19149 #define RCC_APB2ENR_SAI3EN_Msk (0x1UL << RCC_APB2ENR_SAI3EN_Pos) /*!< 0x01000000 */
19150 #define RCC_APB2ENR_SAI3EN RCC_APB2ENR_SAI3EN_Msk
19151 #define RCC_APB2ENR_DFSDM1EN_Pos (28U)
19152 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x10000000 */
19153 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
19154 #define RCC_APB2ENR_HRTIMEN_Pos (29U)
19155 #define RCC_APB2ENR_HRTIMEN_Msk (0x1UL << RCC_APB2ENR_HRTIMEN_Pos) /*!< 0x20000000 */
19156 #define RCC_APB2ENR_HRTIMEN RCC_APB2ENR_HRTIMEN_Msk
19157
19158 /******************** Bit definition for RCC_APB4ENR register ******************/
19159 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
19160 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
19161 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
19162 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
19163 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
19164 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
19165 #define RCC_APB4ENR_SPI6EN_Pos (5U)
19166 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
19167 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
19168 #define RCC_APB4ENR_I2C4EN_Pos (7U)
19169 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
19170 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
19171 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
19172 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
19173 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
19174 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
19175 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
19176 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
19177 #define RCC_APB4ENR_LPTIM4EN_Pos (11U)
19178 #define RCC_APB4ENR_LPTIM4EN_Msk (0x1UL << RCC_APB4ENR_LPTIM4EN_Pos) /*!< 0x00000800 */
19179 #define RCC_APB4ENR_LPTIM4EN RCC_APB4ENR_LPTIM4EN_Msk
19180 #define RCC_APB4ENR_LPTIM5EN_Pos (12U)
19181 #define RCC_APB4ENR_LPTIM5EN_Msk (0x1UL << RCC_APB4ENR_LPTIM5EN_Pos) /*!< 0x00001000 */
19182 #define RCC_APB4ENR_LPTIM5EN RCC_APB4ENR_LPTIM5EN_Msk
19183 #define RCC_APB4ENR_COMP12EN_Pos (14U)
19184 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
19185 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
19186 #define RCC_APB4ENR_VREFEN_Pos (15U)
19187 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
19188 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
19189 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
19190 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
19191 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
19192 #define RCC_APB4ENR_SAI4EN_Pos (21U)
19193 #define RCC_APB4ENR_SAI4EN_Msk (0x1UL << RCC_APB4ENR_SAI4EN_Pos) /*!< 0x00200000 */
19194 #define RCC_APB4ENR_SAI4EN RCC_APB4ENR_SAI4EN_Msk
19195
19196
19197 /******************** Bit definition for RCC_AHB3RSTR register ***************/
19198 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
19199 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
19200 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
19201 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
19202 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
19203 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
19204 #define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
19205 #define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
19206 #define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
19207 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
19208 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
19209 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
19210 #define RCC_AHB3RSTR_QSPIRST_Pos (14U)
19211 #define RCC_AHB3RSTR_QSPIRST_Msk (0x1UL << RCC_AHB3RSTR_QSPIRST_Pos) /*!< 0x00004000 */
19212 #define RCC_AHB3RSTR_QSPIRST RCC_AHB3RSTR_QSPIRST_Msk
19213 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
19214 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
19215 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
19216
19217
19218 /******************** Bit definition for RCC_AHB1RSTR register ***************/
19219 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
19220 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
19221 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
19222 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
19223 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
19224 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
19225 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
19226 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
19227 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
19228 #define RCC_AHB1RSTR_ARTRST_Pos (14U)
19229 #define RCC_AHB1RSTR_ARTRST_Msk (0x1UL << RCC_AHB1RSTR_ARTRST_Pos) /*!< 0x00004000 */
19230 #define RCC_AHB1RSTR_ARTRST RCC_AHB1RSTR_ARTRST_Msk
19231 #define RCC_AHB1RSTR_ETH1MACRST_Pos (15U)
19232 #define RCC_AHB1RSTR_ETH1MACRST_Msk (0x1UL << RCC_AHB1RSTR_ETH1MACRST_Pos) /*!< 0x00008000 */
19233 #define RCC_AHB1RSTR_ETH1MACRST RCC_AHB1RSTR_ETH1MACRST_Msk
19234 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
19235 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
19236 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
19237 #define RCC_AHB1RSTR_USB2OTGFSRST_Pos (27U)
19238 #define RCC_AHB1RSTR_USB2OTGFSRST_Msk (0x1UL << RCC_AHB1RSTR_USB2OTGFSRST_Pos) /*!< 0x08000000 */
19239 #define RCC_AHB1RSTR_USB2OTGFSRST RCC_AHB1RSTR_USB2OTGFSRST_Msk
19240
19241 /* Legacy define */
19242 #define RCC_AHB1RSTR_USB2OTGHSRST_Pos RCC_AHB1RSTR_USB2OTGFSRST_Pos
19243 #define RCC_AHB1RSTR_USB2OTGHSRST_Msk RCC_AHB1RSTR_USB2OTGFSRST_Msk
19244 #define RCC_AHB1RSTR_USB2OTGHSRST RCC_AHB1RSTR_USB2OTGFSRST
19245
19246 /******************** Bit definition for RCC_AHB2RSTR register ***************/
19247 #define RCC_AHB2RSTR_DCMIRST_Pos (0U)
19248 #define RCC_AHB2RSTR_DCMIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMIRST_Pos) /*!< 0x00000001 */
19249 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMIRST_Msk
19250 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
19251 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
19252 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
19253 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
19254 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
19255 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
19256 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
19257 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
19258 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
19259 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
19260 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
19261 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
19262
19263 /******************** Bit definition for RCC_AHB4RSTR register ******************/
19264 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
19265 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
19266 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
19267 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
19268 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
19269 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
19270 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
19271 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
19272 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
19273 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
19274 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
19275 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
19276 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
19277 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
19278 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
19279 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
19280 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
19281 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
19282 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
19283 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
19284 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
19285 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
19286 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
19287 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
19288 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
19289 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
19290 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
19291 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
19292 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
19293 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
19294 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
19295 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
19296 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
19297 #define RCC_AHB4RSTR_CRCRST_Pos (19U)
19298 #define RCC_AHB4RSTR_CRCRST_Msk (0x1UL << RCC_AHB4RSTR_CRCRST_Pos) /*!< 0x00080000 */
19299 #define RCC_AHB4RSTR_CRCRST RCC_AHB4RSTR_CRCRST_Msk
19300 #define RCC_AHB4RSTR_BDMARST_Pos (21U)
19301 #define RCC_AHB4RSTR_BDMARST_Msk (0x1UL << RCC_AHB4RSTR_BDMARST_Pos) /*!< 0x00200000 */
19302 #define RCC_AHB4RSTR_BDMARST RCC_AHB4RSTR_BDMARST_Msk
19303 #define RCC_AHB4RSTR_ADC3RST_Pos (24U)
19304 #define RCC_AHB4RSTR_ADC3RST_Msk (0x1UL << RCC_AHB4RSTR_ADC3RST_Pos) /*!< 0x01000000 */
19305 #define RCC_AHB4RSTR_ADC3RST RCC_AHB4RSTR_ADC3RST_Msk
19306 #define RCC_AHB4RSTR_HSEMRST_Pos (25U)
19307 #define RCC_AHB4RSTR_HSEMRST_Msk (0x1UL << RCC_AHB4RSTR_HSEMRST_Pos) /*!< 0x02000000 */
19308 #define RCC_AHB4RSTR_HSEMRST RCC_AHB4RSTR_HSEMRST_Msk
19309
19310
19311 /******************** Bit definition for RCC_APB3RSTR register ******************/
19312 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
19313 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
19314 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
19315 #define RCC_APB3RSTR_DSIRST_Pos (4U)
19316 #define RCC_APB3RSTR_DSIRST_Msk (0x1UL << RCC_APB3RSTR_DSIRST_Pos) /*!< 0x00000010 */
19317 #define RCC_APB3RSTR_DSIRST RCC_APB3RSTR_DSIRST_Msk
19318
19319 /******************** Bit definition for RCC_APB1LRSTR register ******************/
19320
19321 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
19322 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
19323 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
19324 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
19325 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
19326 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
19327 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
19328 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
19329 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
19330 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
19331 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
19332 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
19333 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
19334 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
19335 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
19336 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
19337 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
19338 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
19339 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
19340 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
19341 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
19342 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
19343 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
19344 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
19345 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
19346 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
19347 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
19348 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
19349 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
19350 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
19351 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
19352 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
19353 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
19354 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
19355 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
19356 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
19357 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
19358 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
19359 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
19360 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
19361 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
19362 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
19363 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
19364 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
19365 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
19366 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
19367 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
19368 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
19369 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
19370 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
19371 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
19372 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
19373 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
19374 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
19375 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
19376 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
19377 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
19378 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
19379 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
19380 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
19381 #define RCC_APB1LRSTR_CECRST_Pos (27U)
19382 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
19383 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
19384 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
19385 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
19386 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
19387 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
19388 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
19389 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
19390 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
19391 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
19392 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
19393
19394 /* Legacy define */
19395 #define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
19396 #define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
19397 #define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
19398 /******************** Bit definition for RCC_APB1HRSTR register ******************/
19399 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
19400 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
19401 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
19402 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
19403 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
19404 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
19405 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
19406 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
19407 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
19408 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
19409 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
19410 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
19411 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
19412 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
19413 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
19414
19415 /******************** Bit definition for RCC_APB2RSTR register ******************/
19416 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
19417 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
19418 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
19419 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
19420 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
19421 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
19422 #define RCC_APB2RSTR_USART1RST_Pos (4U)
19423 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
19424 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
19425 #define RCC_APB2RSTR_USART6RST_Pos (5U)
19426 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
19427 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
19428 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
19429 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
19430 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
19431 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
19432 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
19433 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
19434 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
19435 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
19436 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
19437 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
19438 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
19439 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
19440 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
19441 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
19442 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
19443 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
19444 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
19445 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
19446 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
19447 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
19448 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
19449 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
19450 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
19451 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
19452 #define RCC_APB2RSTR_SAI3RST_Pos (24U)
19453 #define RCC_APB2RSTR_SAI3RST_Msk (0x1UL << RCC_APB2RSTR_SAI3RST_Pos) /*!< 0x01000000 */
19454 #define RCC_APB2RSTR_SAI3RST RCC_APB2RSTR_SAI3RST_Msk
19455 #define RCC_APB2RSTR_DFSDM1RST_Pos (28U)
19456 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
19457 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
19458 #define RCC_APB2RSTR_HRTIMRST_Pos (29U)
19459 #define RCC_APB2RSTR_HRTIMRST_Msk (0x1UL << RCC_APB2RSTR_HRTIMRST_Pos) /*!< 0x20000000 */
19460 #define RCC_APB2RSTR_HRTIMRST RCC_APB2RSTR_HRTIMRST_Msk
19461
19462 /******************** Bit definition for RCC_APB4RSTR register ******************/
19463 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
19464 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
19465 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
19466 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
19467 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
19468 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
19469 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
19470 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
19471 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
19472 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
19473 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
19474 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
19475 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
19476 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
19477 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
19478 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
19479 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
19480 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
19481 #define RCC_APB4RSTR_LPTIM4RST_Pos (11U)
19482 #define RCC_APB4RSTR_LPTIM4RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM4RST_Pos) /*!< 0x00000800 */
19483 #define RCC_APB4RSTR_LPTIM4RST RCC_APB4RSTR_LPTIM4RST_Msk
19484 #define RCC_APB4RSTR_LPTIM5RST_Pos (12U)
19485 #define RCC_APB4RSTR_LPTIM5RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM5RST_Pos) /*!< 0x00001000 */
19486 #define RCC_APB4RSTR_LPTIM5RST RCC_APB4RSTR_LPTIM5RST_Msk
19487 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
19488 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
19489 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
19490 #define RCC_APB4RSTR_VREFRST_Pos (15U)
19491 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
19492 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
19493 #define RCC_APB4RSTR_SAI4RST_Pos (21U)
19494 #define RCC_APB4RSTR_SAI4RST_Msk (0x1UL << RCC_APB4RSTR_SAI4RST_Pos) /*!< 0x00200000 */
19495 #define RCC_APB4RSTR_SAI4RST RCC_APB4RSTR_SAI4RST_Msk
19496
19497
19498 /******************** Bit definition for RCC_GCR register ********************/
19499 #define RCC_GCR_WW1RSC_Pos (0U)
19500 #define RCC_GCR_WW1RSC_Msk (0x1UL << RCC_GCR_WW1RSC_Pos) /*!< 0x00000001 */
19501 #define RCC_GCR_WW1RSC RCC_GCR_WW1RSC_Msk
19502 #define RCC_GCR_WW2RSC_Pos (1U)
19503 #define RCC_GCR_WW2RSC_Msk (0x1UL << RCC_GCR_WW2RSC_Pos) /*!< 0x00000002 */
19504 #define RCC_GCR_WW2RSC RCC_GCR_WW2RSC_Msk
19505 #define RCC_GCR_BOOT_C1_Pos (2U)
19506 #define RCC_GCR_BOOT_C1_Msk (0x1UL << RCC_GCR_BOOT_C1_Pos) /*!< 0x00000004 */
19507 #define RCC_GCR_BOOT_C1 RCC_GCR_BOOT_C1_Msk
19508 #define RCC_GCR_BOOT_C2_Pos (3U)
19509 #define RCC_GCR_BOOT_C2_Msk (0x1UL << RCC_GCR_BOOT_C2_Pos) /*!< 0x00000008 */
19510 #define RCC_GCR_BOOT_C2 RCC_GCR_BOOT_C2_Msk
19511
19512 /******************** Bit definition for RCC_D3AMR register ********************/
19513 #define RCC_D3AMR_BDMAAMEN_Pos (0U)
19514 #define RCC_D3AMR_BDMAAMEN_Msk (0x1UL << RCC_D3AMR_BDMAAMEN_Pos) /*!< 0x00000001 */
19515 #define RCC_D3AMR_BDMAAMEN RCC_D3AMR_BDMAAMEN_Msk
19516 #define RCC_D3AMR_LPUART1AMEN_Pos (3U)
19517 #define RCC_D3AMR_LPUART1AMEN_Msk (0x1UL << RCC_D3AMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
19518 #define RCC_D3AMR_LPUART1AMEN RCC_D3AMR_LPUART1AMEN_Msk
19519 #define RCC_D3AMR_SPI6AMEN_Pos (5U)
19520 #define RCC_D3AMR_SPI6AMEN_Msk (0x1UL << RCC_D3AMR_SPI6AMEN_Pos) /*!< 0x00000020 */
19521 #define RCC_D3AMR_SPI6AMEN RCC_D3AMR_SPI6AMEN_Msk
19522 #define RCC_D3AMR_I2C4AMEN_Pos (7U)
19523 #define RCC_D3AMR_I2C4AMEN_Msk (0x1UL << RCC_D3AMR_I2C4AMEN_Pos) /*!< 0x00000080 */
19524 #define RCC_D3AMR_I2C4AMEN RCC_D3AMR_I2C4AMEN_Msk
19525 #define RCC_D3AMR_LPTIM2AMEN_Pos (9U)
19526 #define RCC_D3AMR_LPTIM2AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
19527 #define RCC_D3AMR_LPTIM2AMEN RCC_D3AMR_LPTIM2AMEN_Msk
19528 #define RCC_D3AMR_LPTIM3AMEN_Pos (10U)
19529 #define RCC_D3AMR_LPTIM3AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
19530 #define RCC_D3AMR_LPTIM3AMEN RCC_D3AMR_LPTIM3AMEN_Msk
19531 #define RCC_D3AMR_LPTIM4AMEN_Pos (11U)
19532 #define RCC_D3AMR_LPTIM4AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM4AMEN_Pos) /*!< 0x00000800 */
19533 #define RCC_D3AMR_LPTIM4AMEN RCC_D3AMR_LPTIM4AMEN_Msk
19534 #define RCC_D3AMR_LPTIM5AMEN_Pos (12U)
19535 #define RCC_D3AMR_LPTIM5AMEN_Msk (0x1UL << RCC_D3AMR_LPTIM5AMEN_Pos) /*!< 0x00001000 */
19536 #define RCC_D3AMR_LPTIM5AMEN RCC_D3AMR_LPTIM5AMEN_Msk
19537 #define RCC_D3AMR_COMP12AMEN_Pos (14U)
19538 #define RCC_D3AMR_COMP12AMEN_Msk (0x1UL << RCC_D3AMR_COMP12AMEN_Pos) /*!< 0x00004000 */
19539 #define RCC_D3AMR_COMP12AMEN RCC_D3AMR_COMP12AMEN_Msk
19540 #define RCC_D3AMR_VREFAMEN_Pos (15U)
19541 #define RCC_D3AMR_VREFAMEN_Msk (0x1UL << RCC_D3AMR_VREFAMEN_Pos) /*!< 0x00008000 */
19542 #define RCC_D3AMR_VREFAMEN RCC_D3AMR_VREFAMEN_Msk
19543 #define RCC_D3AMR_RTCAMEN_Pos (16U)
19544 #define RCC_D3AMR_RTCAMEN_Msk (0x1UL << RCC_D3AMR_RTCAMEN_Pos) /*!< 0x00010000 */
19545 #define RCC_D3AMR_RTCAMEN RCC_D3AMR_RTCAMEN_Msk
19546 #define RCC_D3AMR_CRCAMEN_Pos (19U)
19547 #define RCC_D3AMR_CRCAMEN_Msk (0x1UL << RCC_D3AMR_CRCAMEN_Pos) /*!< 0x00080000 */
19548 #define RCC_D3AMR_CRCAMEN RCC_D3AMR_CRCAMEN_Msk
19549 #define RCC_D3AMR_SAI4AMEN_Pos (21U)
19550 #define RCC_D3AMR_SAI4AMEN_Msk (0x1UL << RCC_D3AMR_SAI4AMEN_Pos) /*!< 0x00200000 */
19551 #define RCC_D3AMR_SAI4AMEN RCC_D3AMR_SAI4AMEN_Msk
19552 #define RCC_D3AMR_ADC3AMEN_Pos (24U)
19553 #define RCC_D3AMR_ADC3AMEN_Msk (0x1UL << RCC_D3AMR_ADC3AMEN_Pos) /*!< 0x01000000 */
19554 #define RCC_D3AMR_ADC3AMEN RCC_D3AMR_ADC3AMEN_Msk
19555
19556
19557 #define RCC_D3AMR_BKPRAMAMEN_Pos (28U)
19558 #define RCC_D3AMR_BKPRAMAMEN_Msk (0x1UL << RCC_D3AMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
19559 #define RCC_D3AMR_BKPRAMAMEN RCC_D3AMR_BKPRAMAMEN_Msk
19560 #define RCC_D3AMR_SRAM4AMEN_Pos (29U)
19561 #define RCC_D3AMR_SRAM4AMEN_Msk (0x1UL << RCC_D3AMR_SRAM4AMEN_Pos) /*!< 0x20000000 */
19562 #define RCC_D3AMR_SRAM4AMEN RCC_D3AMR_SRAM4AMEN_Msk
19563 /******************** Bit definition for RCC_AHB3LPENR register **************/
19564 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
19565 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
19566 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
19567 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
19568 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
19569 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
19570 #define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
19571 #define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
19572 #define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
19573 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
19574 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
19575 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
19576 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
19577 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
19578 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
19579 #define RCC_AHB3LPENR_QSPILPEN_Pos (14U)
19580 #define RCC_AHB3LPENR_QSPILPEN_Msk (0x1UL << RCC_AHB3LPENR_QSPILPEN_Pos) /*!< 0x00004000 */
19581 #define RCC_AHB3LPENR_QSPILPEN RCC_AHB3LPENR_QSPILPEN_Msk
19582 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
19583 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
19584 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
19585 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
19586 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
19587 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
19588 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
19589 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
19590 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
19591 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
19592 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
19593 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
19594 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos (31U)
19595 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAMLPEN_Pos) /*!< 0x80000000 */
19596 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAMLPEN_Msk
19597
19598
19599 /******************** Bit definition for RCC_AHB1LPENR register ***************/
19600 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
19601 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
19602 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
19603 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
19604 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
19605 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
19606 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
19607 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
19608 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
19609 #define RCC_AHB1LPENR_ARTLPEN_Pos (14U)
19610 #define RCC_AHB1LPENR_ARTLPEN_Msk (0x1UL << RCC_AHB1LPENR_ARTLPEN_Pos) /*!< 0x00004000 */
19611 #define RCC_AHB1LPENR_ARTLPEN RCC_AHB1LPENR_ARTLPEN_Msk
19612 #define RCC_AHB1LPENR_ETH1MACLPEN_Pos (15U)
19613 #define RCC_AHB1LPENR_ETH1MACLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1MACLPEN_Pos) /*!< 0x00008000 */
19614 #define RCC_AHB1LPENR_ETH1MACLPEN RCC_AHB1LPENR_ETH1MACLPEN_Msk
19615 #define RCC_AHB1LPENR_ETH1TXLPEN_Pos (16U)
19616 #define RCC_AHB1LPENR_ETH1TXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1TXLPEN_Pos) /*!< 0x00010000 */
19617 #define RCC_AHB1LPENR_ETH1TXLPEN RCC_AHB1LPENR_ETH1TXLPEN_Msk
19618 #define RCC_AHB1LPENR_ETH1RXLPEN_Pos (17U)
19619 #define RCC_AHB1LPENR_ETH1RXLPEN_Msk (0x1UL << RCC_AHB1LPENR_ETH1RXLPEN_Pos) /*!< 0x00020000 */
19620 #define RCC_AHB1LPENR_ETH1RXLPEN RCC_AHB1LPENR_ETH1RXLPEN_Msk
19621 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
19622 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
19623 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
19624 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
19625 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
19626 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
19627 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Pos (27U)
19628 #define RCC_AHB1LPENR_USB2OTGFSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSLPEN_Pos) /*!< 0x08000000 */
19629 #define RCC_AHB1LPENR_USB2OTGFSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
19630 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos (28U)
19631 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos) /*!< 0x10000000 */
19632 #define RCC_AHB1LPENR_USB2OTGFSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
19633
19634 /* Legacy define */
19635 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Pos RCC_AHB1LPENR_USB2OTGFSLPEN_Pos
19636 #define RCC_AHB1LPENR_USB2OTGHSLPEN_Msk RCC_AHB1LPENR_USB2OTGFSLPEN_Msk
19637 #define RCC_AHB1LPENR_USB2OTGHSLPEN RCC_AHB1LPENR_USB2OTGFSLPEN
19638 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Pos RCC_AHB1LPENR_USB2OTGFSULPILPEN_Pos
19639 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN_Msk RCC_AHB1LPENR_USB2OTGFSULPILPEN_Msk
19640 #define RCC_AHB1LPENR_USB2OTGHSULPILPEN RCC_AHB1LPENR_USB2OTGFSULPILPEN
19641
19642 /******************** Bit definition for RCC_AHB2LPENR register ***************/
19643 #define RCC_AHB2LPENR_DCMILPEN_Pos (0U)
19644 #define RCC_AHB2LPENR_DCMILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMILPEN_Pos) /*!< 0x00000001 */
19645 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMILPEN_Msk
19646 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
19647 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
19648 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
19649 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
19650 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
19651 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
19652 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
19653 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
19654 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
19655 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
19656 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
19657 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
19658 #define RCC_AHB2LPENR_SRAM1LPEN_Pos (29U)
19659 #define RCC_AHB2LPENR_SRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM1LPEN_Pos) /*!< 0x20000000 */
19660 #define RCC_AHB2LPENR_SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN_Msk
19661 #define RCC_AHB2LPENR_SRAM2LPEN_Pos (30U)
19662 #define RCC_AHB2LPENR_SRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM2LPEN_Pos) /*!< 0x40000000 */
19663 #define RCC_AHB2LPENR_SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN_Msk
19664 #define RCC_AHB2LPENR_SRAM3LPEN_Pos (31U)
19665 #define RCC_AHB2LPENR_SRAM3LPEN_Msk (0x1UL << RCC_AHB2LPENR_SRAM3LPEN_Pos) /*!< 0x80000000 */
19666 #define RCC_AHB2LPENR_SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN_Msk
19667
19668 /* Legacy define */
19669 #define RCC_AHB2LPENR_D2SRAM1LPEN_Pos RCC_AHB2LPENR_SRAM1LPEN_Pos
19670 #define RCC_AHB2LPENR_D2SRAM1LPEN_Msk RCC_AHB2LPENR_SRAM1LPEN_Msk
19671 #define RCC_AHB2LPENR_D2SRAM1LPEN RCC_AHB2LPENR_SRAM1LPEN
19672 #define RCC_AHB2LPENR_D2SRAM2LPEN_Pos RCC_AHB2LPENR_SRAM2LPEN_Pos
19673 #define RCC_AHB2LPENR_D2SRAM2LPEN_Msk RCC_AHB2LPENR_SRAM2LPEN_Msk
19674 #define RCC_AHB2LPENR_D2SRAM2LPEN RCC_AHB2LPENR_SRAM2LPEN
19675 #define RCC_AHB2LPENR_D2SRAM3LPEN_Pos RCC_AHB2LPENR_SRAM3LPEN_Pos
19676 #define RCC_AHB2LPENR_D2SRAM3LPEN_Msk RCC_AHB2LPENR_SRAM3LPEN_Msk
19677 #define RCC_AHB2LPENR_D2SRAM3LPEN RCC_AHB2LPENR_SRAM3LPEN
19678
19679 /******************** Bit definition for RCC_AHB4LPENR register ******************/
19680 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
19681 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
19682 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
19683 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
19684 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
19685 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
19686 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
19687 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
19688 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
19689 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
19690 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
19691 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
19692 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
19693 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
19694 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
19695 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
19696 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
19697 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
19698 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
19699 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
19700 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
19701 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
19702 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
19703 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
19704 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
19705 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
19706 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
19707 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
19708 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
19709 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
19710 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
19711 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
19712 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
19713 #define RCC_AHB4LPENR_CRCLPEN_Pos (19U)
19714 #define RCC_AHB4LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB4LPENR_CRCLPEN_Pos) /*!< 0x00080000 */
19715 #define RCC_AHB4LPENR_CRCLPEN RCC_AHB4LPENR_CRCLPEN_Msk
19716 #define RCC_AHB4LPENR_BDMALPEN_Pos (21U)
19717 #define RCC_AHB4LPENR_BDMALPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMALPEN_Pos) /*!< 0x00200000 */
19718 #define RCC_AHB4LPENR_BDMALPEN RCC_AHB4LPENR_BDMALPEN_Msk
19719 #define RCC_AHB4LPENR_ADC3LPEN_Pos (24U)
19720 #define RCC_AHB4LPENR_ADC3LPEN_Msk (0x1UL << RCC_AHB4LPENR_ADC3LPEN_Pos) /*!< 0x01000000 */
19721 #define RCC_AHB4LPENR_ADC3LPEN RCC_AHB4LPENR_ADC3LPEN_Msk
19722 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
19723 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
19724 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
19725 #define RCC_AHB4LPENR_SRAM4LPEN_Pos (29U)
19726 #define RCC_AHB4LPENR_SRAM4LPEN_Msk (0x1UL << RCC_AHB4LPENR_SRAM4LPEN_Pos) /*!< 0x20000000 */
19727 #define RCC_AHB4LPENR_SRAM4LPEN RCC_AHB4LPENR_SRAM4LPEN_Msk
19728
19729 /* Legacy define */
19730 #define RCC_AHB4LPENR_D3SRAM1LPEN_Pos RCC_AHB4LPENR_SRAM4LPEN_Pos
19731 #define RCC_AHB4LPENR_D3SRAM1LPEN_Msk RCC_AHB4LPENR_SRAM4LPEN_Msk
19732 #define RCC_AHB4LPENR_D3SRAM1LPEN RCC_AHB4LPENR_SRAM4LPEN
19733 /******************** Bit definition for RCC_APB3LPENR register ******************/
19734 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
19735 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
19736 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
19737 #define RCC_APB3LPENR_DSILPEN_Pos (4U)
19738 #define RCC_APB3LPENR_DSILPEN_Msk (0x1UL << RCC_APB3LPENR_DSILPEN_Pos) /*!< 0x00000010 */
19739 #define RCC_APB3LPENR_DSILPEN RCC_APB3LPENR_DSILPEN_Msk
19740 #define RCC_APB3LPENR_WWDG1LPEN_Pos (6U)
19741 #define RCC_APB3LPENR_WWDG1LPEN_Msk (0x1UL << RCC_APB3LPENR_WWDG1LPEN_Pos) /*!< 0x00000040 */
19742 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDG1LPEN_Msk
19743
19744 /******************** Bit definition for RCC_APB1LLPENR register ******************/
19745
19746 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
19747 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
19748 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
19749 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
19750 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
19751 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
19752 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
19753 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
19754 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
19755 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
19756 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
19757 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
19758 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
19759 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
19760 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
19761 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
19762 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
19763 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
19764 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
19765 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
19766 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
19767 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
19768 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
19769 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
19770 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
19771 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
19772 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
19773 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
19774 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
19775 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
19776
19777 #define RCC_APB1LLPENR_WWDG2LPEN_Pos (11U)
19778 #define RCC_APB1LLPENR_WWDG2LPEN_Msk (0x1UL << RCC_APB1LLPENR_WWDG2LPEN_Pos) /*!< 0x00000800 */
19779 #define RCC_APB1LLPENR_WWDG2LPEN RCC_APB1LLPENR_WWDG2LPEN_Msk
19780
19781 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
19782 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
19783 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
19784 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
19785 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
19786 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
19787 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
19788 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
19789 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
19790 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
19791 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
19792 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
19793 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
19794 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
19795 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
19796 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
19797 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
19798 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
19799 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
19800 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
19801 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
19802 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
19803 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
19804 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
19805 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
19806 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
19807 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
19808 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
19809 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
19810 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
19811 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
19812 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
19813 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
19814 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
19815 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
19816 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
19817 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
19818 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
19819 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
19820 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
19821 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
19822 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
19823
19824 /* Legacy define */
19825 #define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
19826 #define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
19827 #define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
19828 /******************** Bit definition for RCC_APB1HLPENR register ******************/
19829 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
19830 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
19831 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
19832 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
19833 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
19834 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
19835 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
19836 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
19837 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
19838 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
19839 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
19840 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
19841 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
19842 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
19843 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
19844
19845 /******************** Bit definition for RCC_APB2LPENR register ******************/
19846 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
19847 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
19848 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
19849 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
19850 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
19851 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
19852 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
19853 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
19854 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
19855 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
19856 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
19857 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
19858 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
19859 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
19860 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
19861 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
19862 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
19863 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
19864 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
19865 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
19866 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
19867 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
19868 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
19869 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
19870 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
19871 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
19872 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
19873 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
19874 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
19875 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
19876 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
19877 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
19878 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
19879 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
19880 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
19881 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
19882 #define RCC_APB2LPENR_SAI3LPEN_Pos (24U)
19883 #define RCC_APB2LPENR_SAI3LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI3LPEN_Pos) /*!< 0x01000000 */
19884 #define RCC_APB2LPENR_SAI3LPEN RCC_APB2LPENR_SAI3LPEN_Msk
19885 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (28U)
19886 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x10000000 */
19887 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
19888 #define RCC_APB2LPENR_HRTIMLPEN_Pos (29U)
19889 #define RCC_APB2LPENR_HRTIMLPEN_Msk (0x1UL << RCC_APB2LPENR_HRTIMLPEN_Pos) /*!< 0x20000000 */
19890 #define RCC_APB2LPENR_HRTIMLPEN RCC_APB2LPENR_HRTIMLPEN_Msk
19891
19892 /******************** Bit definition for RCC_APB4LPENR register ******************/
19893 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
19894 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
19895 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
19896 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
19897 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
19898 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
19899 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
19900 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
19901 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
19902 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
19903 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
19904 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
19905 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
19906 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
19907 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
19908 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
19909 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
19910 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
19911 #define RCC_APB4LPENR_LPTIM4LPEN_Pos (11U)
19912 #define RCC_APB4LPENR_LPTIM4LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM4LPEN_Pos) /*!< 0x00000800 */
19913 #define RCC_APB4LPENR_LPTIM4LPEN RCC_APB4LPENR_LPTIM4LPEN_Msk
19914 #define RCC_APB4LPENR_LPTIM5LPEN_Pos (12U)
19915 #define RCC_APB4LPENR_LPTIM5LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM5LPEN_Pos) /*!< 0x00001000 */
19916 #define RCC_APB4LPENR_LPTIM5LPEN RCC_APB4LPENR_LPTIM5LPEN_Msk
19917 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
19918 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
19919 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
19920 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
19921 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
19922 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
19923 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
19924 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
19925 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
19926 #define RCC_APB4LPENR_SAI4LPEN_Pos (21U)
19927 #define RCC_APB4LPENR_SAI4LPEN_Msk (0x1UL << RCC_APB4LPENR_SAI4LPEN_Pos) /*!< 0x00200000 */
19928 #define RCC_APB4LPENR_SAI4LPEN RCC_APB4LPENR_SAI4LPEN_Msk
19929
19930 /******************** Bit definition for RCC_D1CCIPR register ****************/
19931 #define RCC_D1CCIPR_DSISRC_Pos (8U)
19932 #define RCC_D1CCIPR_DSISRC_Msk (0x1UL << RCC_D1CCIPR_DSISRC_Pos) /*!< 0x00000100 */
19933 #define RCC_D1CCIPR_DSISRC RCC_D1CCIPR_DSISRC_Msk
19934
19935 /******************** Bit definition for RCC_RSR register *******************/
19936 #define RCC_RSR_RMVF_Pos (16U)
19937 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
19938 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
19939 #define RCC_RSR_C1RSTF_Pos (17U)
19940 #define RCC_RSR_C1RSTF_Msk (0x1UL << RCC_RSR_C1RSTF_Pos) /*!< 0x00020000 */
19941 #define RCC_RSR_C1RSTF RCC_RSR_C1RSTF_Msk
19942 #define RCC_RSR_D1RSTF_Pos (19U)
19943 #define RCC_RSR_D1RSTF_Msk (0x1UL << RCC_RSR_D1RSTF_Pos) /*!< 0x00080000 */
19944 #define RCC_RSR_D1RSTF RCC_RSR_D1RSTF_Msk
19945 #define RCC_RSR_D2RSTF_Pos (20U)
19946 #define RCC_RSR_D2RSTF_Msk (0x1UL << RCC_RSR_D2RSTF_Pos) /*!< 0x00100000 */
19947 #define RCC_RSR_D2RSTF RCC_RSR_D2RSTF_Msk
19948 #define RCC_RSR_BORRSTF_Pos (21U)
19949 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
19950 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
19951 #define RCC_RSR_PINRSTF_Pos (22U)
19952 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
19953 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
19954 #define RCC_RSR_PORRSTF_Pos (23U)
19955 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
19956 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
19957 #define RCC_RSR_SFT1RSTF_Pos (24U)
19958 #define RCC_RSR_SFT1RSTF_Msk (0x1UL << RCC_RSR_SFT1RSTF_Pos) /*!< 0x01000000 */
19959 #define RCC_RSR_SFT1RSTF RCC_RSR_SFT1RSTF_Msk
19960 #define RCC_RSR_IWDG1RSTF_Pos (26U)
19961 #define RCC_RSR_IWDG1RSTF_Msk (0x1UL << RCC_RSR_IWDG1RSTF_Pos) /*!< 0x04000000 */
19962 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDG1RSTF_Msk
19963 #define RCC_RSR_WWDG1RSTF_Pos (28U)
19964 #define RCC_RSR_WWDG1RSTF_Msk (0x1UL << RCC_RSR_WWDG1RSTF_Pos) /*!< 0x10000000 */
19965 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDG1RSTF_Msk
19966
19967 #define RCC_RSR_WWDG2RSTF_Pos (29U)
19968 #define RCC_RSR_WWDG2RSTF_Msk (0x1UL << RCC_RSR_WWDG2RSTF_Pos) /*!< 0x20000000 */
19969 #define RCC_RSR_WWDG2RSTF RCC_RSR_WWDG2RSTF_Msk
19970 #define RCC_RSR_IWDG2RSTF_Pos (27U)
19971 #define RCC_RSR_IWDG2RSTF_Msk (0x1UL << RCC_RSR_IWDG2RSTF_Pos) /*!< 0x08000000 */
19972 #define RCC_RSR_IWDG2RSTF RCC_RSR_IWDG2RSTF_Msk
19973 #define RCC_RSR_SFT2RSTF_Pos (25U)
19974 #define RCC_RSR_SFT2RSTF_Msk (0x1UL << RCC_RSR_SFT2RSTF_Pos) /*!< 0x02000000 */
19975 #define RCC_RSR_SFT2RSTF RCC_RSR_SFT2RSTF_Msk
19976 #define RCC_RSR_C2RSTF_Pos (18U)
19977 #define RCC_RSR_C2RSTF_Msk (0x1UL << RCC_RSR_C2RSTF_Pos) /*!< 0x00040000 */
19978 #define RCC_RSR_C2RSTF RCC_RSR_C2RSTF_Msk
19979 #define RCC_RSR_LPWR1RSTF_Pos (30U)
19980 #define RCC_RSR_LPWR1RSTF_Msk (0x1UL << RCC_RSR_LPWR1RSTF_Pos) /*!< 0x40000000 */
19981 #define RCC_RSR_LPWR1RSTF RCC_RSR_LPWR1RSTF_Msk
19982 #define RCC_RSR_LPWR2RSTF_Pos (31U)
19983 #define RCC_RSR_LPWR2RSTF_Msk (0x1UL << RCC_RSR_LPWR2RSTF_Pos) /*!< 0x80000000 */
19984 #define RCC_RSR_LPWR2RSTF RCC_RSR_LPWR2RSTF_Msk
19985
19986
19987 /******************************************************************************/
19988 /* */
19989 /* RNG */
19990 /* */
19991 /******************************************************************************/
19992 /******************** Bits definition for RNG_CR register *******************/
19993 #define RNG_CR_RNGEN_Pos (2U)
19994 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
19995 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
19996 #define RNG_CR_IE_Pos (3U)
19997 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
19998 #define RNG_CR_IE RNG_CR_IE_Msk
19999 #define RNG_CR_CED_Pos (5U)
20000 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
20001 #define RNG_CR_CED RNG_CR_CED_Msk
20002
20003 /******************** Bits definition for RNG_SR register *******************/
20004 #define RNG_SR_DRDY_Pos (0U)
20005 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
20006 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
20007 #define RNG_SR_CECS_Pos (1U)
20008 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
20009 #define RNG_SR_CECS RNG_SR_CECS_Msk
20010 #define RNG_SR_SECS_Pos (2U)
20011 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
20012 #define RNG_SR_SECS RNG_SR_SECS_Msk
20013 #define RNG_SR_CEIS_Pos (5U)
20014 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
20015 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
20016 #define RNG_SR_SEIS_Pos (6U)
20017 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
20018 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
20019
20020 /******************************************************************************/
20021 /* */
20022 /* Real-Time Clock (RTC) */
20023 /* */
20024 /******************************************************************************/
20025 /******************** Bits definition for RTC_TR register *******************/
20026 #define RTC_TR_PM_Pos (22U)
20027 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
20028 #define RTC_TR_PM RTC_TR_PM_Msk
20029 #define RTC_TR_HT_Pos (20U)
20030 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
20031 #define RTC_TR_HT RTC_TR_HT_Msk
20032 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
20033 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
20034 #define RTC_TR_HU_Pos (16U)
20035 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
20036 #define RTC_TR_HU RTC_TR_HU_Msk
20037 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
20038 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
20039 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
20040 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
20041 #define RTC_TR_MNT_Pos (12U)
20042 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
20043 #define RTC_TR_MNT RTC_TR_MNT_Msk
20044 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
20045 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
20046 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
20047 #define RTC_TR_MNU_Pos (8U)
20048 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
20049 #define RTC_TR_MNU RTC_TR_MNU_Msk
20050 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
20051 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
20052 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
20053 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
20054 #define RTC_TR_ST_Pos (4U)
20055 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
20056 #define RTC_TR_ST RTC_TR_ST_Msk
20057 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
20058 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
20059 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
20060 #define RTC_TR_SU_Pos (0U)
20061 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
20062 #define RTC_TR_SU RTC_TR_SU_Msk
20063 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
20064 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
20065 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
20066 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
20067
20068 /******************** Bits definition for RTC_DR register *******************/
20069 #define RTC_DR_YT_Pos (20U)
20070 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
20071 #define RTC_DR_YT RTC_DR_YT_Msk
20072 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
20073 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
20074 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
20075 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
20076 #define RTC_DR_YU_Pos (16U)
20077 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
20078 #define RTC_DR_YU RTC_DR_YU_Msk
20079 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
20080 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
20081 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
20082 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
20083 #define RTC_DR_WDU_Pos (13U)
20084 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
20085 #define RTC_DR_WDU RTC_DR_WDU_Msk
20086 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
20087 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
20088 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
20089 #define RTC_DR_MT_Pos (12U)
20090 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
20091 #define RTC_DR_MT RTC_DR_MT_Msk
20092 #define RTC_DR_MU_Pos (8U)
20093 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
20094 #define RTC_DR_MU RTC_DR_MU_Msk
20095 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
20096 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
20097 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
20098 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
20099 #define RTC_DR_DT_Pos (4U)
20100 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
20101 #define RTC_DR_DT RTC_DR_DT_Msk
20102 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
20103 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
20104 #define RTC_DR_DU_Pos (0U)
20105 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
20106 #define RTC_DR_DU RTC_DR_DU_Msk
20107 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
20108 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
20109 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
20110 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
20111
20112 /******************** Bits definition for RTC_CR register *******************/
20113 #define RTC_CR_ITSE_Pos (24U)
20114 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
20115 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
20116 #define RTC_CR_COE_Pos (23U)
20117 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
20118 #define RTC_CR_COE RTC_CR_COE_Msk
20119 #define RTC_CR_OSEL_Pos (21U)
20120 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
20121 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
20122 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
20123 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
20124 #define RTC_CR_POL_Pos (20U)
20125 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
20126 #define RTC_CR_POL RTC_CR_POL_Msk
20127 #define RTC_CR_COSEL_Pos (19U)
20128 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
20129 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
20130 #define RTC_CR_BKP_Pos (18U)
20131 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
20132 #define RTC_CR_BKP RTC_CR_BKP_Msk
20133 #define RTC_CR_SUB1H_Pos (17U)
20134 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
20135 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
20136 #define RTC_CR_ADD1H_Pos (16U)
20137 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
20138 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
20139 #define RTC_CR_TSIE_Pos (15U)
20140 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
20141 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
20142 #define RTC_CR_WUTIE_Pos (14U)
20143 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
20144 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
20145 #define RTC_CR_ALRBIE_Pos (13U)
20146 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
20147 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
20148 #define RTC_CR_ALRAIE_Pos (12U)
20149 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
20150 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
20151 #define RTC_CR_TSE_Pos (11U)
20152 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
20153 #define RTC_CR_TSE RTC_CR_TSE_Msk
20154 #define RTC_CR_WUTE_Pos (10U)
20155 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
20156 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
20157 #define RTC_CR_ALRBE_Pos (9U)
20158 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
20159 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
20160 #define RTC_CR_ALRAE_Pos (8U)
20161 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
20162 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
20163 #define RTC_CR_FMT_Pos (6U)
20164 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
20165 #define RTC_CR_FMT RTC_CR_FMT_Msk
20166 #define RTC_CR_BYPSHAD_Pos (5U)
20167 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
20168 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
20169 #define RTC_CR_REFCKON_Pos (4U)
20170 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
20171 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
20172 #define RTC_CR_TSEDGE_Pos (3U)
20173 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
20174 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
20175 #define RTC_CR_WUCKSEL_Pos (0U)
20176 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
20177 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
20178 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
20179 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
20180 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
20181
20182 /******************** Bits definition for RTC_ISR register ******************/
20183 #define RTC_ISR_ITSF_Pos (17U)
20184 #define RTC_ISR_ITSF_Msk (0x1UL << RTC_ISR_ITSF_Pos) /*!< 0x00020000 */
20185 #define RTC_ISR_ITSF RTC_ISR_ITSF_Msk
20186 #define RTC_ISR_RECALPF_Pos (16U)
20187 #define RTC_ISR_RECALPF_Msk (0x1UL << RTC_ISR_RECALPF_Pos) /*!< 0x00010000 */
20188 #define RTC_ISR_RECALPF RTC_ISR_RECALPF_Msk
20189 #define RTC_ISR_TAMP3F_Pos (15U)
20190 #define RTC_ISR_TAMP3F_Msk (0x1UL << RTC_ISR_TAMP3F_Pos) /*!< 0x00008000 */
20191 #define RTC_ISR_TAMP3F RTC_ISR_TAMP3F_Msk
20192 #define RTC_ISR_TAMP2F_Pos (14U)
20193 #define RTC_ISR_TAMP2F_Msk (0x1UL << RTC_ISR_TAMP2F_Pos) /*!< 0x00004000 */
20194 #define RTC_ISR_TAMP2F RTC_ISR_TAMP2F_Msk
20195 #define RTC_ISR_TAMP1F_Pos (13U)
20196 #define RTC_ISR_TAMP1F_Msk (0x1UL << RTC_ISR_TAMP1F_Pos) /*!< 0x00002000 */
20197 #define RTC_ISR_TAMP1F RTC_ISR_TAMP1F_Msk
20198 #define RTC_ISR_TSOVF_Pos (12U)
20199 #define RTC_ISR_TSOVF_Msk (0x1UL << RTC_ISR_TSOVF_Pos) /*!< 0x00001000 */
20200 #define RTC_ISR_TSOVF RTC_ISR_TSOVF_Msk
20201 #define RTC_ISR_TSF_Pos (11U)
20202 #define RTC_ISR_TSF_Msk (0x1UL << RTC_ISR_TSF_Pos) /*!< 0x00000800 */
20203 #define RTC_ISR_TSF RTC_ISR_TSF_Msk
20204 #define RTC_ISR_WUTF_Pos (10U)
20205 #define RTC_ISR_WUTF_Msk (0x1UL << RTC_ISR_WUTF_Pos) /*!< 0x00000400 */
20206 #define RTC_ISR_WUTF RTC_ISR_WUTF_Msk
20207 #define RTC_ISR_ALRBF_Pos (9U)
20208 #define RTC_ISR_ALRBF_Msk (0x1UL << RTC_ISR_ALRBF_Pos) /*!< 0x00000200 */
20209 #define RTC_ISR_ALRBF RTC_ISR_ALRBF_Msk
20210 #define RTC_ISR_ALRAF_Pos (8U)
20211 #define RTC_ISR_ALRAF_Msk (0x1UL << RTC_ISR_ALRAF_Pos) /*!< 0x00000100 */
20212 #define RTC_ISR_ALRAF RTC_ISR_ALRAF_Msk
20213 #define RTC_ISR_INIT_Pos (7U)
20214 #define RTC_ISR_INIT_Msk (0x1UL << RTC_ISR_INIT_Pos) /*!< 0x00000080 */
20215 #define RTC_ISR_INIT RTC_ISR_INIT_Msk
20216 #define RTC_ISR_INITF_Pos (6U)
20217 #define RTC_ISR_INITF_Msk (0x1UL << RTC_ISR_INITF_Pos) /*!< 0x00000040 */
20218 #define RTC_ISR_INITF RTC_ISR_INITF_Msk
20219 #define RTC_ISR_RSF_Pos (5U)
20220 #define RTC_ISR_RSF_Msk (0x1UL << RTC_ISR_RSF_Pos) /*!< 0x00000020 */
20221 #define RTC_ISR_RSF RTC_ISR_RSF_Msk
20222 #define RTC_ISR_INITS_Pos (4U)
20223 #define RTC_ISR_INITS_Msk (0x1UL << RTC_ISR_INITS_Pos) /*!< 0x00000010 */
20224 #define RTC_ISR_INITS RTC_ISR_INITS_Msk
20225 #define RTC_ISR_SHPF_Pos (3U)
20226 #define RTC_ISR_SHPF_Msk (0x1UL << RTC_ISR_SHPF_Pos) /*!< 0x00000008 */
20227 #define RTC_ISR_SHPF RTC_ISR_SHPF_Msk
20228 #define RTC_ISR_WUTWF_Pos (2U)
20229 #define RTC_ISR_WUTWF_Msk (0x1UL << RTC_ISR_WUTWF_Pos) /*!< 0x00000004 */
20230 #define RTC_ISR_WUTWF RTC_ISR_WUTWF_Msk
20231 #define RTC_ISR_ALRBWF_Pos (1U)
20232 #define RTC_ISR_ALRBWF_Msk (0x1UL << RTC_ISR_ALRBWF_Pos) /*!< 0x00000002 */
20233 #define RTC_ISR_ALRBWF RTC_ISR_ALRBWF_Msk
20234 #define RTC_ISR_ALRAWF_Pos (0U)
20235 #define RTC_ISR_ALRAWF_Msk (0x1UL << RTC_ISR_ALRAWF_Pos) /*!< 0x00000001 */
20236 #define RTC_ISR_ALRAWF RTC_ISR_ALRAWF_Msk
20237
20238 /******************** Bits definition for RTC_PRER register *****************/
20239 #define RTC_PRER_PREDIV_A_Pos (16U)
20240 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
20241 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
20242 #define RTC_PRER_PREDIV_S_Pos (0U)
20243 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
20244 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
20245
20246 /******************** Bits definition for RTC_WUTR register *****************/
20247 #define RTC_WUTR_WUT_Pos (0U)
20248 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
20249 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
20250
20251 /******************** Bits definition for RTC_ALRMAR register ***************/
20252 #define RTC_ALRMAR_MSK4_Pos (31U)
20253 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
20254 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
20255 #define RTC_ALRMAR_WDSEL_Pos (30U)
20256 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
20257 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
20258 #define RTC_ALRMAR_DT_Pos (28U)
20259 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
20260 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
20261 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
20262 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
20263 #define RTC_ALRMAR_DU_Pos (24U)
20264 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
20265 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
20266 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
20267 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
20268 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
20269 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
20270 #define RTC_ALRMAR_MSK3_Pos (23U)
20271 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
20272 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
20273 #define RTC_ALRMAR_PM_Pos (22U)
20274 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
20275 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
20276 #define RTC_ALRMAR_HT_Pos (20U)
20277 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
20278 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
20279 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
20280 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
20281 #define RTC_ALRMAR_HU_Pos (16U)
20282 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
20283 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
20284 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
20285 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
20286 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
20287 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
20288 #define RTC_ALRMAR_MSK2_Pos (15U)
20289 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
20290 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
20291 #define RTC_ALRMAR_MNT_Pos (12U)
20292 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
20293 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
20294 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
20295 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
20296 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
20297 #define RTC_ALRMAR_MNU_Pos (8U)
20298 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
20299 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
20300 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
20301 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
20302 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
20303 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
20304 #define RTC_ALRMAR_MSK1_Pos (7U)
20305 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
20306 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
20307 #define RTC_ALRMAR_ST_Pos (4U)
20308 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
20309 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
20310 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
20311 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
20312 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
20313 #define RTC_ALRMAR_SU_Pos (0U)
20314 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
20315 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
20316 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
20317 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
20318 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
20319 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
20320
20321 /******************** Bits definition for RTC_ALRMBR register ***************/
20322 #define RTC_ALRMBR_MSK4_Pos (31U)
20323 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
20324 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
20325 #define RTC_ALRMBR_WDSEL_Pos (30U)
20326 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
20327 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
20328 #define RTC_ALRMBR_DT_Pos (28U)
20329 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
20330 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
20331 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
20332 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
20333 #define RTC_ALRMBR_DU_Pos (24U)
20334 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
20335 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
20336 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
20337 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
20338 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
20339 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
20340 #define RTC_ALRMBR_MSK3_Pos (23U)
20341 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
20342 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
20343 #define RTC_ALRMBR_PM_Pos (22U)
20344 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
20345 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
20346 #define RTC_ALRMBR_HT_Pos (20U)
20347 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
20348 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
20349 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
20350 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
20351 #define RTC_ALRMBR_HU_Pos (16U)
20352 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
20353 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
20354 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
20355 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
20356 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
20357 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
20358 #define RTC_ALRMBR_MSK2_Pos (15U)
20359 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
20360 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
20361 #define RTC_ALRMBR_MNT_Pos (12U)
20362 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
20363 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
20364 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
20365 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
20366 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
20367 #define RTC_ALRMBR_MNU_Pos (8U)
20368 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
20369 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
20370 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
20371 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
20372 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
20373 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
20374 #define RTC_ALRMBR_MSK1_Pos (7U)
20375 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
20376 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
20377 #define RTC_ALRMBR_ST_Pos (4U)
20378 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
20379 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
20380 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
20381 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
20382 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
20383 #define RTC_ALRMBR_SU_Pos (0U)
20384 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
20385 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
20386 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
20387 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
20388 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
20389 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
20390
20391 /******************** Bits definition for RTC_WPR register ******************/
20392 #define RTC_WPR_KEY_Pos (0U)
20393 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
20394 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
20395
20396 /******************** Bits definition for RTC_SSR register ******************/
20397 #define RTC_SSR_SS_Pos (0U)
20398 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
20399 #define RTC_SSR_SS RTC_SSR_SS_Msk
20400
20401 /******************** Bits definition for RTC_SHIFTR register ***************/
20402 #define RTC_SHIFTR_SUBFS_Pos (0U)
20403 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
20404 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
20405 #define RTC_SHIFTR_ADD1S_Pos (31U)
20406 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
20407 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
20408
20409 /******************** Bits definition for RTC_TSTR register *****************/
20410 #define RTC_TSTR_PM_Pos (22U)
20411 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
20412 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
20413 #define RTC_TSTR_HT_Pos (20U)
20414 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
20415 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
20416 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
20417 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
20418 #define RTC_TSTR_HU_Pos (16U)
20419 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
20420 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
20421 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
20422 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
20423 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
20424 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
20425 #define RTC_TSTR_MNT_Pos (12U)
20426 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
20427 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
20428 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
20429 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
20430 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
20431 #define RTC_TSTR_MNU_Pos (8U)
20432 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
20433 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
20434 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
20435 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
20436 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
20437 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
20438 #define RTC_TSTR_ST_Pos (4U)
20439 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
20440 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
20441 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
20442 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
20443 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
20444 #define RTC_TSTR_SU_Pos (0U)
20445 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
20446 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
20447 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
20448 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
20449 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
20450 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
20451
20452 /******************** Bits definition for RTC_TSDR register *****************/
20453 #define RTC_TSDR_WDU_Pos (13U)
20454 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
20455 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
20456 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
20457 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
20458 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
20459 #define RTC_TSDR_MT_Pos (12U)
20460 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
20461 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
20462 #define RTC_TSDR_MU_Pos (8U)
20463 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
20464 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
20465 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
20466 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
20467 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
20468 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
20469 #define RTC_TSDR_DT_Pos (4U)
20470 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
20471 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
20472 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
20473 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
20474 #define RTC_TSDR_DU_Pos (0U)
20475 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
20476 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
20477 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
20478 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
20479 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
20480 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
20481
20482 /******************** Bits definition for RTC_TSSSR register ****************/
20483 #define RTC_TSSSR_SS_Pos (0U)
20484 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
20485 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
20486
20487 /******************** Bits definition for RTC_CALR register *****************/
20488 #define RTC_CALR_CALP_Pos (15U)
20489 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
20490 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
20491 #define RTC_CALR_CALW8_Pos (14U)
20492 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
20493 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
20494 #define RTC_CALR_CALW16_Pos (13U)
20495 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
20496 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
20497 #define RTC_CALR_CALM_Pos (0U)
20498 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
20499 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
20500 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
20501 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
20502 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
20503 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
20504 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
20505 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
20506 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
20507 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
20508 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
20509
20510 /******************** Bits definition for RTC_TAMPCR register ***************/
20511 #define RTC_TAMPCR_TAMP3MF_Pos (24U)
20512 #define RTC_TAMPCR_TAMP3MF_Msk (0x1UL << RTC_TAMPCR_TAMP3MF_Pos) /*!< 0x01000000 */
20513 #define RTC_TAMPCR_TAMP3MF RTC_TAMPCR_TAMP3MF_Msk
20514 #define RTC_TAMPCR_TAMP3NOERASE_Pos (23U)
20515 #define RTC_TAMPCR_TAMP3NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP3NOERASE_Pos) /*!< 0x00800000 */
20516 #define RTC_TAMPCR_TAMP3NOERASE RTC_TAMPCR_TAMP3NOERASE_Msk
20517 #define RTC_TAMPCR_TAMP3IE_Pos (22U)
20518 #define RTC_TAMPCR_TAMP3IE_Msk (0x1UL << RTC_TAMPCR_TAMP3IE_Pos) /*!< 0x00400000 */
20519 #define RTC_TAMPCR_TAMP3IE RTC_TAMPCR_TAMP3IE_Msk
20520 #define RTC_TAMPCR_TAMP2MF_Pos (21U)
20521 #define RTC_TAMPCR_TAMP2MF_Msk (0x1UL << RTC_TAMPCR_TAMP2MF_Pos) /*!< 0x00200000 */
20522 #define RTC_TAMPCR_TAMP2MF RTC_TAMPCR_TAMP2MF_Msk
20523 #define RTC_TAMPCR_TAMP2NOERASE_Pos (20U)
20524 #define RTC_TAMPCR_TAMP2NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP2NOERASE_Pos) /*!< 0x00100000 */
20525 #define RTC_TAMPCR_TAMP2NOERASE RTC_TAMPCR_TAMP2NOERASE_Msk
20526 #define RTC_TAMPCR_TAMP2IE_Pos (19U)
20527 #define RTC_TAMPCR_TAMP2IE_Msk (0x1UL << RTC_TAMPCR_TAMP2IE_Pos) /*!< 0x00080000 */
20528 #define RTC_TAMPCR_TAMP2IE RTC_TAMPCR_TAMP2IE_Msk
20529 #define RTC_TAMPCR_TAMP1MF_Pos (18U)
20530 #define RTC_TAMPCR_TAMP1MF_Msk (0x1UL << RTC_TAMPCR_TAMP1MF_Pos) /*!< 0x00040000 */
20531 #define RTC_TAMPCR_TAMP1MF RTC_TAMPCR_TAMP1MF_Msk
20532 #define RTC_TAMPCR_TAMP1NOERASE_Pos (17U)
20533 #define RTC_TAMPCR_TAMP1NOERASE_Msk (0x1UL << RTC_TAMPCR_TAMP1NOERASE_Pos) /*!< 0x00020000 */
20534 #define RTC_TAMPCR_TAMP1NOERASE RTC_TAMPCR_TAMP1NOERASE_Msk
20535 #define RTC_TAMPCR_TAMP1IE_Pos (16U)
20536 #define RTC_TAMPCR_TAMP1IE_Msk (0x1UL << RTC_TAMPCR_TAMP1IE_Pos) /*!< 0x00010000 */
20537 #define RTC_TAMPCR_TAMP1IE RTC_TAMPCR_TAMP1IE_Msk
20538 #define RTC_TAMPCR_TAMPPUDIS_Pos (15U)
20539 #define RTC_TAMPCR_TAMPPUDIS_Msk (0x1UL << RTC_TAMPCR_TAMPPUDIS_Pos) /*!< 0x00008000 */
20540 #define RTC_TAMPCR_TAMPPUDIS RTC_TAMPCR_TAMPPUDIS_Msk
20541 #define RTC_TAMPCR_TAMPPRCH_Pos (13U)
20542 #define RTC_TAMPCR_TAMPPRCH_Msk (0x3UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00006000 */
20543 #define RTC_TAMPCR_TAMPPRCH RTC_TAMPCR_TAMPPRCH_Msk
20544 #define RTC_TAMPCR_TAMPPRCH_0 (0x1UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00002000 */
20545 #define RTC_TAMPCR_TAMPPRCH_1 (0x2UL << RTC_TAMPCR_TAMPPRCH_Pos) /*!< 0x00004000 */
20546 #define RTC_TAMPCR_TAMPFLT_Pos (11U)
20547 #define RTC_TAMPCR_TAMPFLT_Msk (0x3UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001800 */
20548 #define RTC_TAMPCR_TAMPFLT RTC_TAMPCR_TAMPFLT_Msk
20549 #define RTC_TAMPCR_TAMPFLT_0 (0x1UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00000800 */
20550 #define RTC_TAMPCR_TAMPFLT_1 (0x2UL << RTC_TAMPCR_TAMPFLT_Pos) /*!< 0x00001000 */
20551 #define RTC_TAMPCR_TAMPFREQ_Pos (8U)
20552 #define RTC_TAMPCR_TAMPFREQ_Msk (0x7UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000700 */
20553 #define RTC_TAMPCR_TAMPFREQ RTC_TAMPCR_TAMPFREQ_Msk
20554 #define RTC_TAMPCR_TAMPFREQ_0 (0x1UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000100 */
20555 #define RTC_TAMPCR_TAMPFREQ_1 (0x2UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000200 */
20556 #define RTC_TAMPCR_TAMPFREQ_2 (0x4UL << RTC_TAMPCR_TAMPFREQ_Pos) /*!< 0x00000400 */
20557 #define RTC_TAMPCR_TAMPTS_Pos (7U)
20558 #define RTC_TAMPCR_TAMPTS_Msk (0x1UL << RTC_TAMPCR_TAMPTS_Pos) /*!< 0x00000080 */
20559 #define RTC_TAMPCR_TAMPTS RTC_TAMPCR_TAMPTS_Msk
20560 #define RTC_TAMPCR_TAMP3TRG_Pos (6U)
20561 #define RTC_TAMPCR_TAMP3TRG_Msk (0x1UL << RTC_TAMPCR_TAMP3TRG_Pos) /*!< 0x00000040 */
20562 #define RTC_TAMPCR_TAMP3TRG RTC_TAMPCR_TAMP3TRG_Msk
20563 #define RTC_TAMPCR_TAMP3E_Pos (5U)
20564 #define RTC_TAMPCR_TAMP3E_Msk (0x1UL << RTC_TAMPCR_TAMP3E_Pos) /*!< 0x00000020 */
20565 #define RTC_TAMPCR_TAMP3E RTC_TAMPCR_TAMP3E_Msk
20566 #define RTC_TAMPCR_TAMP2TRG_Pos (4U)
20567 #define RTC_TAMPCR_TAMP2TRG_Msk (0x1UL << RTC_TAMPCR_TAMP2TRG_Pos) /*!< 0x00000010 */
20568 #define RTC_TAMPCR_TAMP2TRG RTC_TAMPCR_TAMP2TRG_Msk
20569 #define RTC_TAMPCR_TAMP2E_Pos (3U)
20570 #define RTC_TAMPCR_TAMP2E_Msk (0x1UL << RTC_TAMPCR_TAMP2E_Pos) /*!< 0x00000008 */
20571 #define RTC_TAMPCR_TAMP2E RTC_TAMPCR_TAMP2E_Msk
20572 #define RTC_TAMPCR_TAMPIE_Pos (2U)
20573 #define RTC_TAMPCR_TAMPIE_Msk (0x1UL << RTC_TAMPCR_TAMPIE_Pos) /*!< 0x00000004 */
20574 #define RTC_TAMPCR_TAMPIE RTC_TAMPCR_TAMPIE_Msk
20575 #define RTC_TAMPCR_TAMP1TRG_Pos (1U)
20576 #define RTC_TAMPCR_TAMP1TRG_Msk (0x1UL << RTC_TAMPCR_TAMP1TRG_Pos) /*!< 0x00000002 */
20577 #define RTC_TAMPCR_TAMP1TRG RTC_TAMPCR_TAMP1TRG_Msk
20578 #define RTC_TAMPCR_TAMP1E_Pos (0U)
20579 #define RTC_TAMPCR_TAMP1E_Msk (0x1UL << RTC_TAMPCR_TAMP1E_Pos) /*!< 0x00000001 */
20580 #define RTC_TAMPCR_TAMP1E RTC_TAMPCR_TAMP1E_Msk
20581
20582 /******************** Bits definition for RTC_ALRMASSR register *************/
20583 #define RTC_ALRMASSR_MASKSS_Pos (24U)
20584 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
20585 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
20586 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
20587 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
20588 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
20589 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
20590 #define RTC_ALRMASSR_SS_Pos (0U)
20591 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
20592 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
20593
20594 /******************** Bits definition for RTC_ALRMBSSR register *************/
20595 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
20596 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
20597 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
20598 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
20599 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
20600 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
20601 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
20602 #define RTC_ALRMBSSR_SS_Pos (0U)
20603 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
20604 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
20605
20606 /******************** Bits definition for RTC_OR register *******************/
20607 #define RTC_OR_OUT_RMP_Pos (1U)
20608 #define RTC_OR_OUT_RMP_Msk (0x1UL << RTC_OR_OUT_RMP_Pos) /*!< 0x00000002 */
20609 #define RTC_OR_OUT_RMP RTC_OR_OUT_RMP_Msk
20610 #define RTC_OR_ALARMOUTTYPE_Pos (0U)
20611 #define RTC_OR_ALARMOUTTYPE_Msk (0x1UL << RTC_OR_ALARMOUTTYPE_Pos) /*!< 0x00000001 */
20612 #define RTC_OR_ALARMOUTTYPE RTC_OR_ALARMOUTTYPE_Msk
20613
20614 /******************** Bits definition for RTC_BKP0R register ****************/
20615 #define RTC_BKP0R_Pos (0U)
20616 #define RTC_BKP0R_Msk (0xFFFFFFFFUL << RTC_BKP0R_Pos) /*!< 0xFFFFFFFF */
20617 #define RTC_BKP0R RTC_BKP0R_Msk
20618
20619 /******************** Bits definition for RTC_BKP1R register ****************/
20620 #define RTC_BKP1R_Pos (0U)
20621 #define RTC_BKP1R_Msk (0xFFFFFFFFUL << RTC_BKP1R_Pos) /*!< 0xFFFFFFFF */
20622 #define RTC_BKP1R RTC_BKP1R_Msk
20623
20624 /******************** Bits definition for RTC_BKP2R register ****************/
20625 #define RTC_BKP2R_Pos (0U)
20626 #define RTC_BKP2R_Msk (0xFFFFFFFFUL << RTC_BKP2R_Pos) /*!< 0xFFFFFFFF */
20627 #define RTC_BKP2R RTC_BKP2R_Msk
20628
20629 /******************** Bits definition for RTC_BKP3R register ****************/
20630 #define RTC_BKP3R_Pos (0U)
20631 #define RTC_BKP3R_Msk (0xFFFFFFFFUL << RTC_BKP3R_Pos) /*!< 0xFFFFFFFF */
20632 #define RTC_BKP3R RTC_BKP3R_Msk
20633
20634 /******************** Bits definition for RTC_BKP4R register ****************/
20635 #define RTC_BKP4R_Pos (0U)
20636 #define RTC_BKP4R_Msk (0xFFFFFFFFUL << RTC_BKP4R_Pos) /*!< 0xFFFFFFFF */
20637 #define RTC_BKP4R RTC_BKP4R_Msk
20638
20639 /******************** Bits definition for RTC_BKP5R register ****************/
20640 #define RTC_BKP5R_Pos (0U)
20641 #define RTC_BKP5R_Msk (0xFFFFFFFFUL << RTC_BKP5R_Pos) /*!< 0xFFFFFFFF */
20642 #define RTC_BKP5R RTC_BKP5R_Msk
20643
20644 /******************** Bits definition for RTC_BKP6R register ****************/
20645 #define RTC_BKP6R_Pos (0U)
20646 #define RTC_BKP6R_Msk (0xFFFFFFFFUL << RTC_BKP6R_Pos) /*!< 0xFFFFFFFF */
20647 #define RTC_BKP6R RTC_BKP6R_Msk
20648
20649 /******************** Bits definition for RTC_BKP7R register ****************/
20650 #define RTC_BKP7R_Pos (0U)
20651 #define RTC_BKP7R_Msk (0xFFFFFFFFUL << RTC_BKP7R_Pos) /*!< 0xFFFFFFFF */
20652 #define RTC_BKP7R RTC_BKP7R_Msk
20653
20654 /******************** Bits definition for RTC_BKP8R register ****************/
20655 #define RTC_BKP8R_Pos (0U)
20656 #define RTC_BKP8R_Msk (0xFFFFFFFFUL << RTC_BKP8R_Pos) /*!< 0xFFFFFFFF */
20657 #define RTC_BKP8R RTC_BKP8R_Msk
20658
20659 /******************** Bits definition for RTC_BKP9R register ****************/
20660 #define RTC_BKP9R_Pos (0U)
20661 #define RTC_BKP9R_Msk (0xFFFFFFFFUL << RTC_BKP9R_Pos) /*!< 0xFFFFFFFF */
20662 #define RTC_BKP9R RTC_BKP9R_Msk
20663
20664 /******************** Bits definition for RTC_BKP10R register ***************/
20665 #define RTC_BKP10R_Pos (0U)
20666 #define RTC_BKP10R_Msk (0xFFFFFFFFUL << RTC_BKP10R_Pos) /*!< 0xFFFFFFFF */
20667 #define RTC_BKP10R RTC_BKP10R_Msk
20668
20669 /******************** Bits definition for RTC_BKP11R register ***************/
20670 #define RTC_BKP11R_Pos (0U)
20671 #define RTC_BKP11R_Msk (0xFFFFFFFFUL << RTC_BKP11R_Pos) /*!< 0xFFFFFFFF */
20672 #define RTC_BKP11R RTC_BKP11R_Msk
20673
20674 /******************** Bits definition for RTC_BKP12R register ***************/
20675 #define RTC_BKP12R_Pos (0U)
20676 #define RTC_BKP12R_Msk (0xFFFFFFFFUL << RTC_BKP12R_Pos) /*!< 0xFFFFFFFF */
20677 #define RTC_BKP12R RTC_BKP12R_Msk
20678
20679 /******************** Bits definition for RTC_BKP13R register ***************/
20680 #define RTC_BKP13R_Pos (0U)
20681 #define RTC_BKP13R_Msk (0xFFFFFFFFUL << RTC_BKP13R_Pos) /*!< 0xFFFFFFFF */
20682 #define RTC_BKP13R RTC_BKP13R_Msk
20683
20684 /******************** Bits definition for RTC_BKP14R register ***************/
20685 #define RTC_BKP14R_Pos (0U)
20686 #define RTC_BKP14R_Msk (0xFFFFFFFFUL << RTC_BKP14R_Pos) /*!< 0xFFFFFFFF */
20687 #define RTC_BKP14R RTC_BKP14R_Msk
20688
20689 /******************** Bits definition for RTC_BKP15R register ***************/
20690 #define RTC_BKP15R_Pos (0U)
20691 #define RTC_BKP15R_Msk (0xFFFFFFFFUL << RTC_BKP15R_Pos) /*!< 0xFFFFFFFF */
20692 #define RTC_BKP15R RTC_BKP15R_Msk
20693
20694 /******************** Bits definition for RTC_BKP16R register ***************/
20695 #define RTC_BKP16R_Pos (0U)
20696 #define RTC_BKP16R_Msk (0xFFFFFFFFUL << RTC_BKP16R_Pos) /*!< 0xFFFFFFFF */
20697 #define RTC_BKP16R RTC_BKP16R_Msk
20698
20699 /******************** Bits definition for RTC_BKP17R register ***************/
20700 #define RTC_BKP17R_Pos (0U)
20701 #define RTC_BKP17R_Msk (0xFFFFFFFFUL << RTC_BKP17R_Pos) /*!< 0xFFFFFFFF */
20702 #define RTC_BKP17R RTC_BKP17R_Msk
20703
20704 /******************** Bits definition for RTC_BKP18R register ***************/
20705 #define RTC_BKP18R_Pos (0U)
20706 #define RTC_BKP18R_Msk (0xFFFFFFFFUL << RTC_BKP18R_Pos) /*!< 0xFFFFFFFF */
20707 #define RTC_BKP18R RTC_BKP18R_Msk
20708
20709 /******************** Bits definition for RTC_BKP19R register ***************/
20710 #define RTC_BKP19R_Pos (0U)
20711 #define RTC_BKP19R_Msk (0xFFFFFFFFUL << RTC_BKP19R_Pos) /*!< 0xFFFFFFFF */
20712 #define RTC_BKP19R RTC_BKP19R_Msk
20713
20714 /******************** Bits definition for RTC_BKP20R register ***************/
20715 #define RTC_BKP20R_Pos (0U)
20716 #define RTC_BKP20R_Msk (0xFFFFFFFFUL << RTC_BKP20R_Pos) /*!< 0xFFFFFFFF */
20717 #define RTC_BKP20R RTC_BKP20R_Msk
20718
20719 /******************** Bits definition for RTC_BKP21R register ***************/
20720 #define RTC_BKP21R_Pos (0U)
20721 #define RTC_BKP21R_Msk (0xFFFFFFFFUL << RTC_BKP21R_Pos) /*!< 0xFFFFFFFF */
20722 #define RTC_BKP21R RTC_BKP21R_Msk
20723
20724 /******************** Bits definition for RTC_BKP22R register ***************/
20725 #define RTC_BKP22R_Pos (0U)
20726 #define RTC_BKP22R_Msk (0xFFFFFFFFUL << RTC_BKP22R_Pos) /*!< 0xFFFFFFFF */
20727 #define RTC_BKP22R RTC_BKP22R_Msk
20728
20729 /******************** Bits definition for RTC_BKP23R register ***************/
20730 #define RTC_BKP23R_Pos (0U)
20731 #define RTC_BKP23R_Msk (0xFFFFFFFFUL << RTC_BKP23R_Pos) /*!< 0xFFFFFFFF */
20732 #define RTC_BKP23R RTC_BKP23R_Msk
20733
20734 /******************** Bits definition for RTC_BKP24R register ***************/
20735 #define RTC_BKP24R_Pos (0U)
20736 #define RTC_BKP24R_Msk (0xFFFFFFFFUL << RTC_BKP24R_Pos) /*!< 0xFFFFFFFF */
20737 #define RTC_BKP24R RTC_BKP24R_Msk
20738
20739 /******************** Bits definition for RTC_BKP25R register ***************/
20740 #define RTC_BKP25R_Pos (0U)
20741 #define RTC_BKP25R_Msk (0xFFFFFFFFUL << RTC_BKP25R_Pos) /*!< 0xFFFFFFFF */
20742 #define RTC_BKP25R RTC_BKP25R_Msk
20743
20744 /******************** Bits definition for RTC_BKP26R register ***************/
20745 #define RTC_BKP26R_Pos (0U)
20746 #define RTC_BKP26R_Msk (0xFFFFFFFFUL << RTC_BKP26R_Pos) /*!< 0xFFFFFFFF */
20747 #define RTC_BKP26R RTC_BKP26R_Msk
20748
20749 /******************** Bits definition for RTC_BKP27R register ***************/
20750 #define RTC_BKP27R_Pos (0U)
20751 #define RTC_BKP27R_Msk (0xFFFFFFFFUL << RTC_BKP27R_Pos) /*!< 0xFFFFFFFF */
20752 #define RTC_BKP27R RTC_BKP27R_Msk
20753
20754 /******************** Bits definition for RTC_BKP28R register ***************/
20755 #define RTC_BKP28R_Pos (0U)
20756 #define RTC_BKP28R_Msk (0xFFFFFFFFUL << RTC_BKP28R_Pos) /*!< 0xFFFFFFFF */
20757 #define RTC_BKP28R RTC_BKP28R_Msk
20758
20759 /******************** Bits definition for RTC_BKP29R register ***************/
20760 #define RTC_BKP29R_Pos (0U)
20761 #define RTC_BKP29R_Msk (0xFFFFFFFFUL << RTC_BKP29R_Pos) /*!< 0xFFFFFFFF */
20762 #define RTC_BKP29R RTC_BKP29R_Msk
20763
20764 /******************** Bits definition for RTC_BKP30R register ***************/
20765 #define RTC_BKP30R_Pos (0U)
20766 #define RTC_BKP30R_Msk (0xFFFFFFFFUL << RTC_BKP30R_Pos) /*!< 0xFFFFFFFF */
20767 #define RTC_BKP30R RTC_BKP30R_Msk
20768
20769 /******************** Bits definition for RTC_BKP31R register ***************/
20770 #define RTC_BKP31R_Pos (0U)
20771 #define RTC_BKP31R_Msk (0xFFFFFFFFUL << RTC_BKP31R_Pos) /*!< 0xFFFFFFFF */
20772 #define RTC_BKP31R RTC_BKP31R_Msk
20773
20774 /******************** Number of backup registers ******************************/
20775 #define RTC_BKP_NUMBER_Pos (5U)
20776 #define RTC_BKP_NUMBER_Msk (0x1UL << RTC_BKP_NUMBER_Pos) /*!< 0x00000020 */
20777 #define RTC_BKP_NUMBER RTC_BKP_NUMBER_Msk
20778
20779 /******************************************************************************/
20780 /* */
20781 /* SPDIF-RX Interface */
20782 /* */
20783 /******************************************************************************/
20784 /******************** Bit definition for SPDIF_CR register ******************/
20785 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
20786 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
20787 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
20788 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
20789 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
20790 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
20791 #define SPDIFRX_CR_RXSTEO_Pos (3U)
20792 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
20793 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
20794 #define SPDIFRX_CR_DRFMT_Pos (4U)
20795 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
20796 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
20797 #define SPDIFRX_CR_PMSK_Pos (6U)
20798 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
20799 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
20800 #define SPDIFRX_CR_VMSK_Pos (7U)
20801 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
20802 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
20803 #define SPDIFRX_CR_CUMSK_Pos (8U)
20804 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
20805 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
20806 #define SPDIFRX_CR_PTMSK_Pos (9U)
20807 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
20808 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
20809 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
20810 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
20811 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
20812 #define SPDIFRX_CR_CHSEL_Pos (11U)
20813 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
20814 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
20815 #define SPDIFRX_CR_NBTR_Pos (12U)
20816 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
20817 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
20818 #define SPDIFRX_CR_WFA_Pos (14U)
20819 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
20820 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
20821 #define SPDIFRX_CR_INSEL_Pos (16U)
20822 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
20823 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
20824 #define SPDIFRX_CR_CKSEN_Pos (20U)
20825 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
20826 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
20827 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
20828 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
20829 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
20830
20831 /******************* Bit definition for SPDIFRX_IMR register *******************/
20832 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
20833 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
20834 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
20835 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
20836 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
20837 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
20838 #define SPDIFRX_IMR_PERRIE_Pos (2U)
20839 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
20840 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
20841 #define SPDIFRX_IMR_OVRIE_Pos (3U)
20842 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
20843 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
20844 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
20845 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
20846 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
20847 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
20848 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
20849 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
20850 #define SPDIFRX_IMR_IFEIE_Pos (6U)
20851 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
20852 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
20853
20854 /******************* Bit definition for SPDIFRX_SR register *******************/
20855 #define SPDIFRX_SR_RXNE_Pos (0U)
20856 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
20857 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
20858 #define SPDIFRX_SR_CSRNE_Pos (1U)
20859 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
20860 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
20861 #define SPDIFRX_SR_PERR_Pos (2U)
20862 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
20863 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
20864 #define SPDIFRX_SR_OVR_Pos (3U)
20865 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
20866 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
20867 #define SPDIFRX_SR_SBD_Pos (4U)
20868 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
20869 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
20870 #define SPDIFRX_SR_SYNCD_Pos (5U)
20871 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
20872 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
20873 #define SPDIFRX_SR_FERR_Pos (6U)
20874 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
20875 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
20876 #define SPDIFRX_SR_SERR_Pos (7U)
20877 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
20878 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
20879 #define SPDIFRX_SR_TERR_Pos (8U)
20880 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
20881 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
20882 #define SPDIFRX_SR_WIDTH5_Pos (16U)
20883 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
20884 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
20885
20886 /******************* Bit definition for SPDIFRX_IFCR register *******************/
20887 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
20888 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
20889 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
20890 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
20891 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
20892 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
20893 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
20894 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
20895 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
20896 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
20897 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
20898 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
20899
20900 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
20901 #define SPDIFRX_DR0_DR_Pos (0U)
20902 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
20903 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
20904 #define SPDIFRX_DR0_PE_Pos (24U)
20905 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
20906 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
20907 #define SPDIFRX_DR0_V_Pos (25U)
20908 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
20909 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
20910 #define SPDIFRX_DR0_U_Pos (26U)
20911 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
20912 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
20913 #define SPDIFRX_DR0_C_Pos (27U)
20914 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
20915 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
20916 #define SPDIFRX_DR0_PT_Pos (28U)
20917 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
20918 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
20919
20920 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
20921 #define SPDIFRX_DR1_DR_Pos (8U)
20922 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
20923 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
20924 #define SPDIFRX_DR1_PT_Pos (4U)
20925 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
20926 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
20927 #define SPDIFRX_DR1_C_Pos (3U)
20928 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
20929 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
20930 #define SPDIFRX_DR1_U_Pos (2U)
20931 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
20932 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
20933 #define SPDIFRX_DR1_V_Pos (1U)
20934 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
20935 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
20936 #define SPDIFRX_DR1_PE_Pos (0U)
20937 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
20938 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
20939
20940 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
20941 #define SPDIFRX_DR1_DRNL1_Pos (16U)
20942 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
20943 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
20944 #define SPDIFRX_DR1_DRNL2_Pos (0U)
20945 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
20946 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
20947
20948 /******************* Bit definition for SPDIFRX_CSR register *******************/
20949 #define SPDIFRX_CSR_USR_Pos (0U)
20950 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
20951 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
20952 #define SPDIFRX_CSR_CS_Pos (16U)
20953 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
20954 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
20955 #define SPDIFRX_CSR_SOB_Pos (24U)
20956 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
20957 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
20958
20959 /******************* Bit definition for SPDIFRX_DIR register *******************/
20960 #define SPDIFRX_DIR_THI_Pos (0U)
20961 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
20962 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
20963 #define SPDIFRX_DIR_TLO_Pos (16U)
20964 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
20965 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
20966
20967 /******************* Bit definition for SPDIFRX_VERR register *******************/
20968 #define SPDIFRX_VERR_MINREV_Pos (0U)
20969 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
20970 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
20971 #define SPDIFRX_VERR_MAJREV_Pos (4U)
20972 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
20973 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
20974
20975 /******************* Bit definition for SPDIFRX_IDR register *******************/
20976 #define SPDIFRX_IDR_ID_Pos (0U)
20977 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
20978 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
20979
20980 /******************* Bit definition for SPDIFRX_SIDR register *******************/
20981 #define SPDIFRX_SIDR_SID_Pos (0U)
20982 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
20983 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
20984
20985 /******************************************************************************/
20986 /* */
20987 /* Serial Audio Interface */
20988 /* */
20989 /******************************************************************************/
20990 /******************************* SAI VERSION ********************************/
20991 #define SAI_VER_V2_X
20992
20993 /******************** Bit definition for SAI_GCR register *******************/
20994 #define SAI_GCR_SYNCIN_Pos (0U)
20995 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
20996 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
20997 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
20998 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
20999
21000 #define SAI_GCR_SYNCOUT_Pos (4U)
21001 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
21002 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
21003 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
21004 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
21005
21006 /******************* Bit definition for SAI_xCR1 register *******************/
21007 #define SAI_xCR1_MODE_Pos (0U)
21008 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
21009 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
21010 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
21011 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
21012
21013 #define SAI_xCR1_PRTCFG_Pos (2U)
21014 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
21015 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
21016 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
21017 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
21018
21019 #define SAI_xCR1_DS_Pos (5U)
21020 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
21021 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
21022 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
21023 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
21024 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
21025
21026 #define SAI_xCR1_LSBFIRST_Pos (8U)
21027 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
21028 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
21029 #define SAI_xCR1_CKSTR_Pos (9U)
21030 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
21031 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
21032
21033 #define SAI_xCR1_SYNCEN_Pos (10U)
21034 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
21035 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
21036 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
21037 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
21038
21039 #define SAI_xCR1_MONO_Pos (12U)
21040 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
21041 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
21042 #define SAI_xCR1_OUTDRIV_Pos (13U)
21043 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
21044 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
21045 #define SAI_xCR1_SAIEN_Pos (16U)
21046 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
21047 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
21048 #define SAI_xCR1_DMAEN_Pos (17U)
21049 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
21050 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
21051 #define SAI_xCR1_NODIV_Pos (19U)
21052 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
21053 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
21054
21055 #define SAI_xCR1_MCKDIV_Pos (20U)
21056 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
21057 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
21058 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
21059 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
21060 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
21061 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
21062 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
21063 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
21064
21065 #define SAI_xCR1_MCKEN_Pos (27U)
21066 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
21067 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
21068
21069 #define SAI_xCR1_OSR_Pos (26U)
21070 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
21071 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
21072
21073 /* Legacy define */
21074 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
21075
21076 /******************* Bit definition for SAI_xCR2 register *******************/
21077 #define SAI_xCR2_FTH_Pos (0U)
21078 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
21079 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
21080 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
21081 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
21082 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
21083
21084 #define SAI_xCR2_FFLUSH_Pos (3U)
21085 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
21086 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
21087 #define SAI_xCR2_TRIS_Pos (4U)
21088 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
21089 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
21090 #define SAI_xCR2_MUTE_Pos (5U)
21091 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
21092 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
21093 #define SAI_xCR2_MUTEVAL_Pos (6U)
21094 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
21095 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
21096
21097 #define SAI_xCR2_MUTECNT_Pos (7U)
21098 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
21099 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
21100 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
21101 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
21102 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
21103 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
21104 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
21105 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
21106
21107 #define SAI_xCR2_CPL_Pos (13U)
21108 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
21109 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
21110
21111 #define SAI_xCR2_COMP_Pos (14U)
21112 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
21113 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
21114 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
21115 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
21116
21117 /****************** Bit definition for SAI_xFRCR register *******************/
21118 #define SAI_xFRCR_FRL_Pos (0U)
21119 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
21120 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
21121 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
21122 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
21123 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
21124 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
21125 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
21126 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
21127 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
21128 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
21129
21130 #define SAI_xFRCR_FSALL_Pos (8U)
21131 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
21132 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
21133 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
21134 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
21135 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
21136 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
21137 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
21138 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
21139 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
21140
21141 #define SAI_xFRCR_FSDEF_Pos (16U)
21142 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
21143 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
21144 #define SAI_xFRCR_FSPOL_Pos (17U)
21145 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
21146 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
21147 #define SAI_xFRCR_FSOFF_Pos (18U)
21148 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
21149 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
21150
21151 /* Legacy define */
21152 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
21153
21154 /****************** Bit definition for SAI_xSLOTR register *******************/
21155 #define SAI_xSLOTR_FBOFF_Pos (0U)
21156 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
21157 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
21158 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
21159 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
21160 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
21161 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
21162 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
21163
21164 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
21165 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
21166 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
21167 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
21168 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
21169
21170 #define SAI_xSLOTR_NBSLOT_Pos (8U)
21171 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
21172 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
21173 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
21174 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
21175 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
21176 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
21177
21178 #define SAI_xSLOTR_SLOTEN_Pos (16U)
21179 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
21180 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
21181
21182 /******************* Bit definition for SAI_xIMR register *******************/
21183 #define SAI_xIMR_OVRUDRIE_Pos (0U)
21184 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
21185 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
21186 #define SAI_xIMR_MUTEDETIE_Pos (1U)
21187 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
21188 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
21189 #define SAI_xIMR_WCKCFGIE_Pos (2U)
21190 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
21191 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
21192 #define SAI_xIMR_FREQIE_Pos (3U)
21193 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
21194 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
21195 #define SAI_xIMR_CNRDYIE_Pos (4U)
21196 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
21197 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
21198 #define SAI_xIMR_AFSDETIE_Pos (5U)
21199 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
21200 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
21201 #define SAI_xIMR_LFSDETIE_Pos (6U)
21202 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
21203 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
21204
21205 /******************** Bit definition for SAI_xSR register *******************/
21206 #define SAI_xSR_OVRUDR_Pos (0U)
21207 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
21208 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
21209 #define SAI_xSR_MUTEDET_Pos (1U)
21210 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
21211 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
21212 #define SAI_xSR_WCKCFG_Pos (2U)
21213 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
21214 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
21215 #define SAI_xSR_FREQ_Pos (3U)
21216 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
21217 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
21218 #define SAI_xSR_CNRDY_Pos (4U)
21219 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
21220 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
21221 #define SAI_xSR_AFSDET_Pos (5U)
21222 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
21223 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
21224 #define SAI_xSR_LFSDET_Pos (6U)
21225 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
21226 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
21227
21228 #define SAI_xSR_FLVL_Pos (16U)
21229 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
21230 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
21231 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
21232 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
21233 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
21234
21235 /****************** Bit definition for SAI_xCLRFR register ******************/
21236 #define SAI_xCLRFR_COVRUDR_Pos (0U)
21237 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
21238 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
21239 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
21240 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
21241 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
21242 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
21243 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
21244 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
21245 #define SAI_xCLRFR_CFREQ_Pos (3U)
21246 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
21247 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
21248 #define SAI_xCLRFR_CCNRDY_Pos (4U)
21249 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
21250 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
21251 #define SAI_xCLRFR_CAFSDET_Pos (5U)
21252 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
21253 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
21254 #define SAI_xCLRFR_CLFSDET_Pos (6U)
21255 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
21256 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
21257
21258 /****************** Bit definition for SAI_xDR register *********************/
21259 #define SAI_xDR_DATA_Pos (0U)
21260 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
21261 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
21262
21263 /******************* Bit definition for SAI_PDMCR register ******************/
21264 #define SAI_PDMCR_PDMEN_Pos (0U)
21265 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
21266 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
21267
21268 #define SAI_PDMCR_MICNBR_Pos (4U)
21269 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
21270 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
21271 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
21272 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
21273
21274 #define SAI_PDMCR_CKEN1_Pos (8U)
21275 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
21276 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
21277 #define SAI_PDMCR_CKEN2_Pos (9U)
21278 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
21279 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
21280 #define SAI_PDMCR_CKEN3_Pos (10U)
21281 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
21282 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
21283 #define SAI_PDMCR_CKEN4_Pos (11U)
21284 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
21285 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
21286
21287 /****************** Bit definition for SAI_PDMDLY register ******************/
21288 #define SAI_PDMDLY_DLYM1L_Pos (0U)
21289 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
21290 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
21291 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
21292 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
21293 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
21294
21295 #define SAI_PDMDLY_DLYM1R_Pos (4U)
21296 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
21297 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
21298 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
21299 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
21300 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
21301
21302 #define SAI_PDMDLY_DLYM2L_Pos (8U)
21303 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
21304 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
21305 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
21306 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
21307 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
21308
21309 #define SAI_PDMDLY_DLYM2R_Pos (12U)
21310 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
21311 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
21312 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
21313 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
21314 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
21315
21316 #define SAI_PDMDLY_DLYM3L_Pos (16U)
21317 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
21318 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
21319 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
21320 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
21321 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
21322
21323 #define SAI_PDMDLY_DLYM3R_Pos (20U)
21324 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
21325 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
21326 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
21327 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
21328 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
21329
21330 #define SAI_PDMDLY_DLYM4L_Pos (24U)
21331 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
21332 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
21333 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
21334 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
21335 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
21336
21337 #define SAI_PDMDLY_DLYM4R_Pos (28U)
21338 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
21339 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
21340 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
21341 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
21342 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
21343
21344 /******************************************************************************/
21345 /* */
21346 /* SDMMC Interface */
21347 /* */
21348 /******************************************************************************/
21349 /****************** Bit definition for SDMMC_POWER register ******************/
21350 #define SDMMC_POWER_PWRCTRL_Pos (0U)
21351 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
21352 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
21353 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
21354 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
21355 #define SDMMC_POWER_VSWITCH_Pos (2U)
21356 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
21357 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
21358 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
21359 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
21360 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
21361 #define SDMMC_POWER_DIRPOL_Pos (4U)
21362 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
21363 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
21364
21365 /****************** Bit definition for SDMMC_CLKCR register ******************/
21366 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
21367 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
21368 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
21369 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
21370 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
21371 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
21372
21373 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
21374 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
21375 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
21376 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
21377 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
21378
21379 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
21380 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
21381 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
21382 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
21383 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
21384 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
21385 #define SDMMC_CLKCR_DDR_Pos (18U)
21386 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
21387 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
21388 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
21389 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
21390 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
21391 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
21392 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
21393 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
21394 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
21395 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
21396
21397 /******************* Bit definition for SDMMC_ARG register *******************/
21398 #define SDMMC_ARG_CMDARG_Pos (0U)
21399 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
21400 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
21401
21402 /******************* Bit definition for SDMMC_CMD register *******************/
21403 #define SDMMC_CMD_CMDINDEX_Pos (0U)
21404 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
21405 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
21406 #define SDMMC_CMD_CMDTRANS_Pos (6U)
21407 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
21408 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
21409 #define SDMMC_CMD_CMDSTOP_Pos (7U)
21410 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
21411 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
21412
21413 #define SDMMC_CMD_WAITRESP_Pos (8U)
21414 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
21415 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
21416 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
21417 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
21418
21419 #define SDMMC_CMD_WAITINT_Pos (10U)
21420 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
21421 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
21422 #define SDMMC_CMD_WAITPEND_Pos (11U)
21423 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
21424 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
21425 #define SDMMC_CMD_CPSMEN_Pos (12U)
21426 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
21427 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
21428 #define SDMMC_CMD_DTHOLD_Pos (13U)
21429 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
21430 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
21431 #define SDMMC_CMD_BOOTMODE_Pos (14U)
21432 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
21433 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
21434 #define SDMMC_CMD_BOOTEN_Pos (15U)
21435 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
21436 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
21437 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
21438 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
21439 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
21440
21441 /***************** Bit definition for SDMMC_RESPCMD register *****************/
21442 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
21443 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
21444 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
21445
21446 /****************** Bit definition for SDMMC_RESP0 register ******************/
21447 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
21448 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
21449 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
21450
21451 /****************** Bit definition for SDMMC_RESP1 register ******************/
21452 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
21453 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
21454 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
21455
21456 /****************** Bit definition for SDMMC_RESP2 register ******************/
21457 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
21458 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
21459 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
21460
21461 /****************** Bit definition for SDMMC_RESP3 register ******************/
21462 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
21463 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
21464 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
21465
21466 /****************** Bit definition for SDMMC_RESP4 register ******************/
21467 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
21468 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
21469 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
21470
21471 /****************** Bit definition for SDMMC_DTIMER register *****************/
21472 #define SDMMC_DTIMER_DATATIME_Pos (0U)
21473 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
21474 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
21475
21476 /****************** Bit definition for SDMMC_DLEN register *******************/
21477 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
21478 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
21479 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
21480
21481 /****************** Bit definition for SDMMC_DCTRL register ******************/
21482 #define SDMMC_DCTRL_DTEN_Pos (0U)
21483 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
21484 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
21485 #define SDMMC_DCTRL_DTDIR_Pos (1U)
21486 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
21487 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
21488 #define SDMMC_DCTRL_DTMODE_Pos (2U)
21489 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
21490 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
21491 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
21492 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
21493
21494 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
21495 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
21496 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
21497 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
21498 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
21499 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
21500 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
21501
21502 #define SDMMC_DCTRL_RWSTART_Pos (8U)
21503 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
21504 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
21505 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
21506 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
21507 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
21508 #define SDMMC_DCTRL_RWMOD_Pos (10U)
21509 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
21510 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
21511 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
21512 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
21513 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
21514 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
21515 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
21516 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
21517 #define SDMMC_DCTRL_FIFORST_Pos (13U)
21518 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
21519 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
21520
21521 /****************** Bit definition for SDMMC_DCOUNT register *****************/
21522 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
21523 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
21524 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
21525
21526 /****************** Bit definition for SDMMC_STA register ********************/
21527 #define SDMMC_STA_CCRCFAIL_Pos (0U)
21528 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
21529 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
21530 #define SDMMC_STA_DCRCFAIL_Pos (1U)
21531 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
21532 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
21533 #define SDMMC_STA_CTIMEOUT_Pos (2U)
21534 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
21535 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
21536 #define SDMMC_STA_DTIMEOUT_Pos (3U)
21537 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
21538 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
21539 #define SDMMC_STA_TXUNDERR_Pos (4U)
21540 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
21541 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
21542 #define SDMMC_STA_RXOVERR_Pos (5U)
21543 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
21544 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
21545 #define SDMMC_STA_CMDREND_Pos (6U)
21546 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
21547 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
21548 #define SDMMC_STA_CMDSENT_Pos (7U)
21549 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
21550 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
21551 #define SDMMC_STA_DATAEND_Pos (8U)
21552 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
21553 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
21554 #define SDMMC_STA_DHOLD_Pos (9U)
21555 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
21556 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
21557 #define SDMMC_STA_DBCKEND_Pos (10U)
21558 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
21559 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
21560 #define SDMMC_STA_DABORT_Pos (11U)
21561 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
21562 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
21563 #define SDMMC_STA_DPSMACT_Pos (12U)
21564 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
21565 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
21566 #define SDMMC_STA_CPSMACT_Pos (13U)
21567 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
21568 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
21569 #define SDMMC_STA_TXFIFOHE_Pos (14U)
21570 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
21571 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
21572 #define SDMMC_STA_RXFIFOHF_Pos (15U)
21573 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
21574 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
21575 #define SDMMC_STA_TXFIFOF_Pos (16U)
21576 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
21577 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
21578 #define SDMMC_STA_RXFIFOF_Pos (17U)
21579 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
21580 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
21581 #define SDMMC_STA_TXFIFOE_Pos (18U)
21582 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
21583 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
21584 #define SDMMC_STA_RXFIFOE_Pos (19U)
21585 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
21586 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
21587 #define SDMMC_STA_BUSYD0_Pos (20U)
21588 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
21589 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
21590 #define SDMMC_STA_BUSYD0END_Pos (21U)
21591 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
21592 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
21593 #define SDMMC_STA_SDIOIT_Pos (22U)
21594 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
21595 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
21596 #define SDMMC_STA_ACKFAIL_Pos (23U)
21597 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
21598 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
21599 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
21600 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
21601 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
21602 #define SDMMC_STA_VSWEND_Pos (25U)
21603 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
21604 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
21605 #define SDMMC_STA_CKSTOP_Pos (26U)
21606 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
21607 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
21608 #define SDMMC_STA_IDMATE_Pos (27U)
21609 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
21610 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
21611 #define SDMMC_STA_IDMABTC_Pos (28U)
21612 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
21613 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
21614
21615 /******************* Bit definition for SDMMC_ICR register *******************/
21616 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
21617 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
21618 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
21619 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
21620 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
21621 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
21622 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
21623 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
21624 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
21625 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
21626 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
21627 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
21628 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
21629 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
21630 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
21631 #define SDMMC_ICR_RXOVERRC_Pos (5U)
21632 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
21633 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
21634 #define SDMMC_ICR_CMDRENDC_Pos (6U)
21635 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
21636 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
21637 #define SDMMC_ICR_CMDSENTC_Pos (7U)
21638 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
21639 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
21640 #define SDMMC_ICR_DATAENDC_Pos (8U)
21641 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
21642 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
21643 #define SDMMC_ICR_DHOLDC_Pos (9U)
21644 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
21645 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
21646 #define SDMMC_ICR_DBCKENDC_Pos (10U)
21647 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
21648 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
21649 #define SDMMC_ICR_DABORTC_Pos (11U)
21650 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
21651 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
21652 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
21653 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
21654 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
21655 #define SDMMC_ICR_SDIOITC_Pos (22U)
21656 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
21657 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
21658 #define SDMMC_ICR_ACKFAILC_Pos (23U)
21659 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
21660 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
21661 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
21662 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
21663 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
21664 #define SDMMC_ICR_VSWENDC_Pos (25U)
21665 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
21666 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
21667 #define SDMMC_ICR_CKSTOPC_Pos (26U)
21668 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
21669 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
21670 #define SDMMC_ICR_IDMATEC_Pos (27U)
21671 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
21672 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
21673 #define SDMMC_ICR_IDMABTCC_Pos (28U)
21674 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
21675 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
21676
21677 /****************** Bit definition for SDMMC_MASK register *******************/
21678 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
21679 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
21680 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
21681 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
21682 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
21683 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
21684 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
21685 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
21686 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
21687 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
21688 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
21689 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
21690 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
21691 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
21692 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
21693 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
21694 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
21695 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
21696 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
21697 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
21698 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
21699 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
21700 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
21701 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
21702 #define SDMMC_MASK_DATAENDIE_Pos (8U)
21703 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
21704 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
21705 #define SDMMC_MASK_DHOLDIE_Pos (9U)
21706 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
21707 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
21708 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
21709 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
21710 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
21711 #define SDMMC_MASK_DABORTIE_Pos (11U)
21712 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
21713 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
21714
21715 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
21716 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
21717 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
21718 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
21719 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
21720 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
21721
21722 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
21723 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
21724 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
21725 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
21726 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
21727 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
21728
21729 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
21730 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
21731 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
21732 #define SDMMC_MASK_SDIOITIE_Pos (22U)
21733 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
21734 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
21735 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
21736 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
21737 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
21738 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
21739 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
21740 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
21741 #define SDMMC_MASK_VSWENDIE_Pos (25U)
21742 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
21743 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
21744 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
21745 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
21746 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
21747 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
21748 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
21749 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
21750
21751 /***************** Bit definition for SDMMC_ACKTIME register *****************/
21752 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
21753 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
21754 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
21755
21756 /****************** Bit definition for SDMMC_FIFO register *******************/
21757 #define SDMMC_FIFO_FIFODATA_Pos (0U)
21758 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
21759 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
21760
21761 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
21762 #define SDMMC_IDMA_IDMAEN_Pos (0U)
21763 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
21764 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
21765 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
21766 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
21767 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
21768 #define SDMMC_IDMA_IDMABACT_Pos (2U)
21769 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
21770 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
21771
21772 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
21773 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
21774 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
21775 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
21776
21777 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
21778 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
21779
21780 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
21781 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
21782
21783 /******************************************************************************/
21784 /* */
21785 /* Delay Block Interface (DLYB) */
21786 /* */
21787 /******************************************************************************/
21788 /******************* Bit definition for DLYB_CR register ********************/
21789 #define DLYB_CR_DEN_Pos (0U)
21790 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
21791 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
21792 #define DLYB_CR_SEN_Pos (1U)
21793 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
21794 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
21795
21796
21797 /******************* Bit definition for DLYB_CFGR register ********************/
21798 #define DLYB_CFGR_SEL_Pos (0U)
21799 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
21800 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
21801 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
21802 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
21803 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
21804 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
21805
21806 #define DLYB_CFGR_UNIT_Pos (8U)
21807 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
21808 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
21809 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
21810 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
21811 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
21812 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
21813 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
21814 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
21815 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
21816
21817 #define DLYB_CFGR_LNG_Pos (16U)
21818 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
21819 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
21820 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
21821 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
21822 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
21823 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
21824 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
21825 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
21826 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
21827 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
21828 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
21829 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
21830 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
21831 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
21832
21833 #define DLYB_CFGR_LNGF_Pos (31U)
21834 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
21835 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
21836
21837 /******************************************************************************/
21838 /* */
21839 /* Serial Peripheral Interface (SPI/I2S) */
21840 /* */
21841 /******************************************************************************/
21842 /******************* Bit definition for SPI_CR1 register ********************/
21843 #define SPI_CR1_SPE_Pos (0U)
21844 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
21845 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
21846 #define SPI_CR1_MASRX_Pos (8U)
21847 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
21848 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
21849 #define SPI_CR1_CSTART_Pos (9U)
21850 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
21851 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
21852 #define SPI_CR1_CSUSP_Pos (10U)
21853 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
21854 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
21855 #define SPI_CR1_HDDIR_Pos (11U)
21856 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
21857 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
21858 #define SPI_CR1_SSI_Pos (12U)
21859 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
21860 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
21861 #define SPI_CR1_CRC33_17_Pos (13U)
21862 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
21863 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
21864 #define SPI_CR1_RCRCINI_Pos (14U)
21865 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
21866 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
21867 #define SPI_CR1_TCRCINI_Pos (15U)
21868 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
21869 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
21870 #define SPI_CR1_IOLOCK_Pos (16U)
21871 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
21872 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
21873
21874 /******************* Bit definition for SPI_CR2 register ********************/
21875 #define SPI_CR2_TSER_Pos (16U)
21876 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
21877 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
21878 #define SPI_CR2_TSIZE_Pos (0U)
21879 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
21880 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
21881
21882 /******************* Bit definition for SPI_CFG1 register ********************/
21883 #define SPI_CFG1_DSIZE_Pos (0U)
21884 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
21885 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
21886 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
21887 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
21888 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
21889 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
21890 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
21891
21892 #define SPI_CFG1_FTHLV_Pos (5U)
21893 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
21894 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
21895 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
21896 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
21897 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
21898 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
21899
21900 #define SPI_CFG1_UDRCFG_Pos (9U)
21901 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
21902 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
21903 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
21904 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
21905
21906
21907 #define SPI_CFG1_UDRDET_Pos (11U)
21908 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
21909 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
21910 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
21911 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
21912
21913 #define SPI_CFG1_RXDMAEN_Pos (14U)
21914 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
21915 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
21916 #define SPI_CFG1_TXDMAEN_Pos (15U)
21917 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
21918 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
21919
21920 #define SPI_CFG1_CRCSIZE_Pos (16U)
21921 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
21922 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
21923 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
21924 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
21925 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
21926 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
21927 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
21928
21929 #define SPI_CFG1_CRCEN_Pos (22U)
21930 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
21931 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
21932
21933 #define SPI_CFG1_MBR_Pos (28U)
21934 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
21935 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
21936 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
21937 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
21938 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
21939
21940 /******************* Bit definition for SPI_CFG2 register ********************/
21941 #define SPI_CFG2_MSSI_Pos (0U)
21942 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
21943 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
21944 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
21945 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
21946 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
21947 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
21948
21949 #define SPI_CFG2_MIDI_Pos (4U)
21950 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
21951 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
21952 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
21953 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
21954 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
21955 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
21956
21957 #define SPI_CFG2_IOSWP_Pos (15U)
21958 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
21959 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
21960
21961 #define SPI_CFG2_COMM_Pos (17U)
21962 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
21963 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
21964 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
21965 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
21966
21967 #define SPI_CFG2_SP_Pos (19U)
21968 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
21969 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
21970 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
21971 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
21972 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
21973
21974 #define SPI_CFG2_MASTER_Pos (22U)
21975 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
21976 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
21977 #define SPI_CFG2_LSBFRST_Pos (23U)
21978 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
21979 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
21980 #define SPI_CFG2_CPHA_Pos (24U)
21981 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
21982 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
21983 #define SPI_CFG2_CPOL_Pos (25U)
21984 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
21985 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
21986 #define SPI_CFG2_SSM_Pos (26U)
21987 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
21988 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
21989
21990 #define SPI_CFG2_SSIOP_Pos (28U)
21991 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
21992 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
21993 #define SPI_CFG2_SSOE_Pos (29U)
21994 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
21995 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
21996 #define SPI_CFG2_SSOM_Pos (30U)
21997 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
21998 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
21999
22000 #define SPI_CFG2_AFCNTR_Pos (31U)
22001 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
22002 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
22003
22004 /******************* Bit definition for SPI_IER register ********************/
22005 #define SPI_IER_RXPIE_Pos (0U)
22006 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
22007 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
22008 #define SPI_IER_TXPIE_Pos (1U)
22009 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
22010 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
22011 #define SPI_IER_DXPIE_Pos (2U)
22012 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
22013 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
22014 #define SPI_IER_EOTIE_Pos (3U)
22015 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
22016 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
22017 #define SPI_IER_TXTFIE_Pos (4U)
22018 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
22019 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
22020 #define SPI_IER_UDRIE_Pos (5U)
22021 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
22022 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
22023 #define SPI_IER_OVRIE_Pos (6U)
22024 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
22025 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
22026 #define SPI_IER_CRCEIE_Pos (7U)
22027 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
22028 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
22029 #define SPI_IER_TIFREIE_Pos (8U)
22030 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
22031 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
22032 #define SPI_IER_MODFIE_Pos (9U)
22033 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
22034 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
22035 #define SPI_IER_TSERFIE_Pos (10U)
22036 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
22037 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
22038
22039 /******************* Bit definition for SPI_SR register ********************/
22040 #define SPI_SR_RXP_Pos (0U)
22041 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
22042 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
22043 #define SPI_SR_TXP_Pos (1U)
22044 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
22045 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
22046 #define SPI_SR_DXP_Pos (2U)
22047 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
22048 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
22049 #define SPI_SR_EOT_Pos (3U)
22050 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
22051 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
22052 #define SPI_SR_TXTF_Pos (4U)
22053 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
22054 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
22055 #define SPI_SR_UDR_Pos (5U)
22056 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
22057 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
22058 #define SPI_SR_OVR_Pos (6U)
22059 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
22060 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
22061 #define SPI_SR_CRCE_Pos (7U)
22062 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
22063 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
22064 #define SPI_SR_TIFRE_Pos (8U)
22065 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
22066 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
22067 #define SPI_SR_MODF_Pos (9U)
22068 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
22069 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
22070 #define SPI_SR_TSERF_Pos (10U)
22071 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
22072 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
22073 #define SPI_SR_SUSP_Pos (11U)
22074 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
22075 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
22076 #define SPI_SR_TXC_Pos (12U)
22077 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
22078 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
22079 #define SPI_SR_RXPLVL_Pos (13U)
22080 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
22081 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
22082 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
22083 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
22084 #define SPI_SR_RXWNE_Pos (15U)
22085 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
22086 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
22087 #define SPI_SR_CTSIZE_Pos (16U)
22088 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
22089 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
22090
22091 /******************* Bit definition for SPI_IFCR register ********************/
22092 #define SPI_IFCR_EOTC_Pos (3U)
22093 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
22094 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
22095 #define SPI_IFCR_TXTFC_Pos (4U)
22096 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
22097 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
22098 #define SPI_IFCR_UDRC_Pos (5U)
22099 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
22100 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
22101 #define SPI_IFCR_OVRC_Pos (6U)
22102 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
22103 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
22104 #define SPI_IFCR_CRCEC_Pos (7U)
22105 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
22106 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
22107 #define SPI_IFCR_TIFREC_Pos (8U)
22108 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
22109 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
22110 #define SPI_IFCR_MODFC_Pos (9U)
22111 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
22112 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
22113 #define SPI_IFCR_TSERFC_Pos (10U)
22114 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
22115 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
22116 #define SPI_IFCR_SUSPC_Pos (11U)
22117 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
22118 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
22119
22120 /******************* Bit definition for SPI_TXDR register ********************/
22121 #define SPI_TXDR_TXDR_Pos (0U)
22122 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
22123 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
22124
22125 /******************* Bit definition for SPI_RXDR register ********************/
22126 #define SPI_RXDR_RXDR_Pos (0U)
22127 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
22128 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
22129
22130 /******************* Bit definition for SPI_CRCPOLY register ********************/
22131 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
22132 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
22133 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
22134
22135 /******************* Bit definition for SPI_TXCRC register ********************/
22136 #define SPI_TXCRC_TXCRC_Pos (0U)
22137 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
22138 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
22139
22140 /******************* Bit definition for SPI_RXCRC register ********************/
22141 #define SPI_RXCRC_RXCRC_Pos (0U)
22142 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
22143 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
22144
22145 /******************* Bit definition for SPI_UDRDR register ********************/
22146 #define SPI_UDRDR_UDRDR_Pos (0U)
22147 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
22148 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
22149
22150 /****************** Bit definition for SPI_I2SCFGR register *****************/
22151 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
22152 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
22153 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
22154 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
22155 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
22156 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
22157 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
22158 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
22159 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
22160 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
22161 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
22162 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
22163 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
22164 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
22165 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
22166 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
22167 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
22168 #define SPI_I2SCFGR_DATLEN_Pos (8U)
22169 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
22170 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
22171 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
22172 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
22173 #define SPI_I2SCFGR_CHLEN_Pos (10U)
22174 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
22175 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
22176 #define SPI_I2SCFGR_CKPOL_Pos (11U)
22177 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
22178 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
22179 #define SPI_I2SCFGR_FIXCH_Pos (12U)
22180 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
22181 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
22182 #define SPI_I2SCFGR_WSINV_Pos (13U)
22183 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
22184 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
22185 #define SPI_I2SCFGR_DATFMT_Pos (14U)
22186 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
22187 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
22188 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
22189 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
22190 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
22191 #define SPI_I2SCFGR_ODD_Pos (24U)
22192 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
22193 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
22194 #define SPI_I2SCFGR_MCKOE_Pos (25U)
22195 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
22196 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
22197
22198
22199 /******************************************************************************/
22200 /* */
22201 /* QUADSPI */
22202 /* */
22203 /******************************************************************************/
22204 /***************** Bit definition for QUADSPI_CR register *******************/
22205 #define QUADSPI_CR_EN_Pos (0U)
22206 #define QUADSPI_CR_EN_Msk (0x1UL << QUADSPI_CR_EN_Pos) /*!< 0x00000001 */
22207 #define QUADSPI_CR_EN QUADSPI_CR_EN_Msk /*!< Enable */
22208 #define QUADSPI_CR_ABORT_Pos (1U)
22209 #define QUADSPI_CR_ABORT_Msk (0x1UL << QUADSPI_CR_ABORT_Pos) /*!< 0x00000002 */
22210 #define QUADSPI_CR_ABORT QUADSPI_CR_ABORT_Msk /*!< Abort request */
22211 #define QUADSPI_CR_DMAEN_Pos (2U)
22212 #define QUADSPI_CR_DMAEN_Msk (0x1UL << QUADSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
22213 #define QUADSPI_CR_DMAEN QUADSPI_CR_DMAEN_Msk /*!< DMA Enable */
22214 #define QUADSPI_CR_TCEN_Pos (3U)
22215 #define QUADSPI_CR_TCEN_Msk (0x1UL << QUADSPI_CR_TCEN_Pos) /*!< 0x00000008 */
22216 #define QUADSPI_CR_TCEN QUADSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
22217 #define QUADSPI_CR_SSHIFT_Pos (4U)
22218 #define QUADSPI_CR_SSHIFT_Msk (0x1UL << QUADSPI_CR_SSHIFT_Pos) /*!< 0x00000010 */
22219 #define QUADSPI_CR_SSHIFT QUADSPI_CR_SSHIFT_Msk /*!< SSHIFT Sample Shift */
22220 #define QUADSPI_CR_DFM_Pos (6U)
22221 #define QUADSPI_CR_DFM_Msk (0x1UL << QUADSPI_CR_DFM_Pos) /*!< 0x00000040 */
22222 #define QUADSPI_CR_DFM QUADSPI_CR_DFM_Msk /*!< Dual Flash Mode */
22223 #define QUADSPI_CR_FSEL_Pos (7U)
22224 #define QUADSPI_CR_FSEL_Msk (0x1UL << QUADSPI_CR_FSEL_Pos) /*!< 0x00000080 */
22225 #define QUADSPI_CR_FSEL QUADSPI_CR_FSEL_Msk /*!< Flash Select */
22226 #define QUADSPI_CR_FTHRES_Pos (8U)
22227 #define QUADSPI_CR_FTHRES_Msk (0xFUL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000F00 */
22228 #define QUADSPI_CR_FTHRES QUADSPI_CR_FTHRES_Msk /*!< FTHRES[3:0] FIFO Level */
22229 #define QUADSPI_CR_FTHRES_0 (0x1UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000100 */
22230 #define QUADSPI_CR_FTHRES_1 (0x2UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000200 */
22231 #define QUADSPI_CR_FTHRES_2 (0x4UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000400 */
22232 #define QUADSPI_CR_FTHRES_3 (0x8UL << QUADSPI_CR_FTHRES_Pos) /*!< 0x00000800 */
22233 #define QUADSPI_CR_TEIE_Pos (16U)
22234 #define QUADSPI_CR_TEIE_Msk (0x1UL << QUADSPI_CR_TEIE_Pos) /*!< 0x00010000 */
22235 #define QUADSPI_CR_TEIE QUADSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
22236 #define QUADSPI_CR_TCIE_Pos (17U)
22237 #define QUADSPI_CR_TCIE_Msk (0x1UL << QUADSPI_CR_TCIE_Pos) /*!< 0x00020000 */
22238 #define QUADSPI_CR_TCIE QUADSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
22239 #define QUADSPI_CR_FTIE_Pos (18U)
22240 #define QUADSPI_CR_FTIE_Msk (0x1UL << QUADSPI_CR_FTIE_Pos) /*!< 0x00040000 */
22241 #define QUADSPI_CR_FTIE QUADSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
22242 #define QUADSPI_CR_SMIE_Pos (19U)
22243 #define QUADSPI_CR_SMIE_Msk (0x1UL << QUADSPI_CR_SMIE_Pos) /*!< 0x00080000 */
22244 #define QUADSPI_CR_SMIE QUADSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
22245 #define QUADSPI_CR_TOIE_Pos (20U)
22246 #define QUADSPI_CR_TOIE_Msk (0x1UL << QUADSPI_CR_TOIE_Pos) /*!< 0x00100000 */
22247 #define QUADSPI_CR_TOIE QUADSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
22248 #define QUADSPI_CR_APMS_Pos (22U)
22249 #define QUADSPI_CR_APMS_Msk (0x1UL << QUADSPI_CR_APMS_Pos) /*!< 0x00400000 */
22250 #define QUADSPI_CR_APMS QUADSPI_CR_APMS_Msk /*!< Bit 1 */
22251 #define QUADSPI_CR_PMM_Pos (23U)
22252 #define QUADSPI_CR_PMM_Msk (0x1UL << QUADSPI_CR_PMM_Pos) /*!< 0x00800000 */
22253 #define QUADSPI_CR_PMM QUADSPI_CR_PMM_Msk /*!< Polling Match Mode */
22254 #define QUADSPI_CR_PRESCALER_Pos (24U)
22255 #define QUADSPI_CR_PRESCALER_Msk (0xFFUL << QUADSPI_CR_PRESCALER_Pos) /*!< 0xFF000000 */
22256 #define QUADSPI_CR_PRESCALER QUADSPI_CR_PRESCALER_Msk /*!< PRESCALER[7:0] Clock prescaler */
22257 #define QUADSPI_CR_PRESCALER_0 (0x01UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x01000000 */
22258 #define QUADSPI_CR_PRESCALER_1 (0x02UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x02000000 */
22259 #define QUADSPI_CR_PRESCALER_2 (0x04UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x04000000 */
22260 #define QUADSPI_CR_PRESCALER_3 (0x08UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x08000000 */
22261 #define QUADSPI_CR_PRESCALER_4 (0x10UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x10000000 */
22262 #define QUADSPI_CR_PRESCALER_5 (0x20UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x20000000 */
22263 #define QUADSPI_CR_PRESCALER_6 (0x40UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x40000000 */
22264 #define QUADSPI_CR_PRESCALER_7 (0x80UL << QUADSPI_CR_PRESCALER_Pos) /*!< 0x80000000 */
22265
22266 /***************** Bit definition for QUADSPI_DCR register ******************/
22267 #define QUADSPI_DCR_CKMODE_Pos (0U)
22268 #define QUADSPI_DCR_CKMODE_Msk (0x1UL << QUADSPI_DCR_CKMODE_Pos) /*!< 0x00000001 */
22269 #define QUADSPI_DCR_CKMODE QUADSPI_DCR_CKMODE_Msk /*!< Mode 0 / Mode 3 */
22270 #define QUADSPI_DCR_CSHT_Pos (8U)
22271 #define QUADSPI_DCR_CSHT_Msk (0x7UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000700 */
22272 #define QUADSPI_DCR_CSHT QUADSPI_DCR_CSHT_Msk /*!< CSHT[2:0]: ChipSelect High Time */
22273 #define QUADSPI_DCR_CSHT_0 (0x1UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000100 */
22274 #define QUADSPI_DCR_CSHT_1 (0x2UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000200 */
22275 #define QUADSPI_DCR_CSHT_2 (0x4UL << QUADSPI_DCR_CSHT_Pos) /*!< 0x00000400 */
22276 #define QUADSPI_DCR_FSIZE_Pos (16U)
22277 #define QUADSPI_DCR_FSIZE_Msk (0x1FUL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x001F0000 */
22278 #define QUADSPI_DCR_FSIZE QUADSPI_DCR_FSIZE_Msk /*!< FSIZE[4:0]: Flash Size */
22279 #define QUADSPI_DCR_FSIZE_0 (0x01UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00010000 */
22280 #define QUADSPI_DCR_FSIZE_1 (0x02UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00020000 */
22281 #define QUADSPI_DCR_FSIZE_2 (0x04UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00040000 */
22282 #define QUADSPI_DCR_FSIZE_3 (0x08UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00080000 */
22283 #define QUADSPI_DCR_FSIZE_4 (0x10UL << QUADSPI_DCR_FSIZE_Pos) /*!< 0x00100000 */
22284
22285 /****************** Bit definition for QUADSPI_SR register *******************/
22286 #define QUADSPI_SR_TEF_Pos (0U)
22287 #define QUADSPI_SR_TEF_Msk (0x1UL << QUADSPI_SR_TEF_Pos) /*!< 0x00000001 */
22288 #define QUADSPI_SR_TEF QUADSPI_SR_TEF_Msk /*!< Transfer Error Flag */
22289 #define QUADSPI_SR_TCF_Pos (1U)
22290 #define QUADSPI_SR_TCF_Msk (0x1UL << QUADSPI_SR_TCF_Pos) /*!< 0x00000002 */
22291 #define QUADSPI_SR_TCF QUADSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
22292 #define QUADSPI_SR_FTF_Pos (2U)
22293 #define QUADSPI_SR_FTF_Msk (0x1UL << QUADSPI_SR_FTF_Pos) /*!< 0x00000004 */
22294 #define QUADSPI_SR_FTF QUADSPI_SR_FTF_Msk /*!< FIFO Threshlod Flag */
22295 #define QUADSPI_SR_SMF_Pos (3U)
22296 #define QUADSPI_SR_SMF_Msk (0x1UL << QUADSPI_SR_SMF_Pos) /*!< 0x00000008 */
22297 #define QUADSPI_SR_SMF QUADSPI_SR_SMF_Msk /*!< Status Match Flag */
22298 #define QUADSPI_SR_TOF_Pos (4U)
22299 #define QUADSPI_SR_TOF_Msk (0x1UL << QUADSPI_SR_TOF_Pos) /*!< 0x00000010 */
22300 #define QUADSPI_SR_TOF QUADSPI_SR_TOF_Msk /*!< Timeout Flag */
22301 #define QUADSPI_SR_BUSY_Pos (5U)
22302 #define QUADSPI_SR_BUSY_Msk (0x1UL << QUADSPI_SR_BUSY_Pos) /*!< 0x00000020 */
22303 #define QUADSPI_SR_BUSY QUADSPI_SR_BUSY_Msk /*!< Busy */
22304 #define QUADSPI_SR_FLEVEL_Pos (8U)
22305 #define QUADSPI_SR_FLEVEL_Msk (0x3FUL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
22306 #define QUADSPI_SR_FLEVEL QUADSPI_SR_FLEVEL_Msk /*!< FIFO Threshlod Flag */
22307 #define QUADSPI_SR_FLEVEL_0 (0x01UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000100 */
22308 #define QUADSPI_SR_FLEVEL_1 (0x02UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000200 */
22309 #define QUADSPI_SR_FLEVEL_2 (0x04UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000400 */
22310 #define QUADSPI_SR_FLEVEL_3 (0x08UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00000800 */
22311 #define QUADSPI_SR_FLEVEL_4 (0x10UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00001000 */
22312 #define QUADSPI_SR_FLEVEL_5 (0x20UL << QUADSPI_SR_FLEVEL_Pos) /*!< 0x00002000 */
22313
22314 /****************** Bit definition for QUADSPI_FCR register ******************/
22315 #define QUADSPI_FCR_CTEF_Pos (0U)
22316 #define QUADSPI_FCR_CTEF_Msk (0x1UL << QUADSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
22317 #define QUADSPI_FCR_CTEF QUADSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
22318 #define QUADSPI_FCR_CTCF_Pos (1U)
22319 #define QUADSPI_FCR_CTCF_Msk (0x1UL << QUADSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
22320 #define QUADSPI_FCR_CTCF QUADSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
22321 #define QUADSPI_FCR_CSMF_Pos (3U)
22322 #define QUADSPI_FCR_CSMF_Msk (0x1UL << QUADSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
22323 #define QUADSPI_FCR_CSMF QUADSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
22324 #define QUADSPI_FCR_CTOF_Pos (4U)
22325 #define QUADSPI_FCR_CTOF_Msk (0x1UL << QUADSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
22326 #define QUADSPI_FCR_CTOF QUADSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
22327
22328 /****************** Bit definition for QUADSPI_DLR register ******************/
22329 #define QUADSPI_DLR_DL_Pos (0U)
22330 #define QUADSPI_DLR_DL_Msk (0xFFFFFFFFUL << QUADSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
22331 #define QUADSPI_DLR_DL QUADSPI_DLR_DL_Msk /*!< DL[31:0]: Data Length */
22332
22333 /****************** Bit definition for QUADSPI_CCR register ******************/
22334 #define QUADSPI_CCR_INSTRUCTION_Pos (0U)
22335 #define QUADSPI_CCR_INSTRUCTION_Msk (0xFFUL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x000000FF */
22336 #define QUADSPI_CCR_INSTRUCTION QUADSPI_CCR_INSTRUCTION_Msk /*!< INSTRUCTION[7:0]: Instruction */
22337 #define QUADSPI_CCR_INSTRUCTION_0 (0x01UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000001 */
22338 #define QUADSPI_CCR_INSTRUCTION_1 (0x02UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000002 */
22339 #define QUADSPI_CCR_INSTRUCTION_2 (0x04UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000004 */
22340 #define QUADSPI_CCR_INSTRUCTION_3 (0x08UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000008 */
22341 #define QUADSPI_CCR_INSTRUCTION_4 (0x10UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000010 */
22342 #define QUADSPI_CCR_INSTRUCTION_5 (0x20UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000020 */
22343 #define QUADSPI_CCR_INSTRUCTION_6 (0x40UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000040 */
22344 #define QUADSPI_CCR_INSTRUCTION_7 (0x80UL << QUADSPI_CCR_INSTRUCTION_Pos) /*!< 0x00000080 */
22345 #define QUADSPI_CCR_IMODE_Pos (8U)
22346 #define QUADSPI_CCR_IMODE_Msk (0x3UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000300 */
22347 #define QUADSPI_CCR_IMODE QUADSPI_CCR_IMODE_Msk /*!< IMODE[1:0]: Instruction Mode */
22348 #define QUADSPI_CCR_IMODE_0 (0x1UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000100 */
22349 #define QUADSPI_CCR_IMODE_1 (0x2UL << QUADSPI_CCR_IMODE_Pos) /*!< 0x00000200 */
22350 #define QUADSPI_CCR_ADMODE_Pos (10U)
22351 #define QUADSPI_CCR_ADMODE_Msk (0x3UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000C00 */
22352 #define QUADSPI_CCR_ADMODE QUADSPI_CCR_ADMODE_Msk /*!< ADMODE[1:0]: Address Mode */
22353 #define QUADSPI_CCR_ADMODE_0 (0x1UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
22354 #define QUADSPI_CCR_ADMODE_1 (0x2UL << QUADSPI_CCR_ADMODE_Pos) /*!< 0x00000800 */
22355 #define QUADSPI_CCR_ADSIZE_Pos (12U)
22356 #define QUADSPI_CCR_ADSIZE_Msk (0x3UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
22357 #define QUADSPI_CCR_ADSIZE QUADSPI_CCR_ADSIZE_Msk /*!< ADSIZE[1:0]: Address Size */
22358 #define QUADSPI_CCR_ADSIZE_0 (0x1UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
22359 #define QUADSPI_CCR_ADSIZE_1 (0x2UL << QUADSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
22360 #define QUADSPI_CCR_ABMODE_Pos (14U)
22361 #define QUADSPI_CCR_ABMODE_Msk (0x3UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x0000C000 */
22362 #define QUADSPI_CCR_ABMODE QUADSPI_CCR_ABMODE_Msk /*!< ABMODE[1:0]: Alternate Bytes Mode */
22363 #define QUADSPI_CCR_ABMODE_0 (0x1UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00004000 */
22364 #define QUADSPI_CCR_ABMODE_1 (0x2UL << QUADSPI_CCR_ABMODE_Pos) /*!< 0x00008000 */
22365 #define QUADSPI_CCR_ABSIZE_Pos (16U)
22366 #define QUADSPI_CCR_ABSIZE_Msk (0x3UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00030000 */
22367 #define QUADSPI_CCR_ABSIZE QUADSPI_CCR_ABSIZE_Msk /*!< ABSIZE[1:0]: Instruction Mode */
22368 #define QUADSPI_CCR_ABSIZE_0 (0x1UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00010000 */
22369 #define QUADSPI_CCR_ABSIZE_1 (0x2UL << QUADSPI_CCR_ABSIZE_Pos) /*!< 0x00020000 */
22370 #define QUADSPI_CCR_DCYC_Pos (18U)
22371 #define QUADSPI_CCR_DCYC_Msk (0x1FUL << QUADSPI_CCR_DCYC_Pos) /*!< 0x007C0000 */
22372 #define QUADSPI_CCR_DCYC QUADSPI_CCR_DCYC_Msk /*!< DCYC[4:0]: Dummy Cycles */
22373 #define QUADSPI_CCR_DCYC_0 (0x01UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00040000 */
22374 #define QUADSPI_CCR_DCYC_1 (0x02UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00080000 */
22375 #define QUADSPI_CCR_DCYC_2 (0x04UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00100000 */
22376 #define QUADSPI_CCR_DCYC_3 (0x08UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00200000 */
22377 #define QUADSPI_CCR_DCYC_4 (0x10UL << QUADSPI_CCR_DCYC_Pos) /*!< 0x00400000 */
22378 #define QUADSPI_CCR_DMODE_Pos (24U)
22379 #define QUADSPI_CCR_DMODE_Msk (0x3UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x03000000 */
22380 #define QUADSPI_CCR_DMODE QUADSPI_CCR_DMODE_Msk /*!< DMODE[1:0]: Data Mode */
22381 #define QUADSPI_CCR_DMODE_0 (0x1UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
22382 #define QUADSPI_CCR_DMODE_1 (0x2UL << QUADSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
22383 #define QUADSPI_CCR_FMODE_Pos (26U)
22384 #define QUADSPI_CCR_FMODE_Msk (0x3UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x0C000000 */
22385 #define QUADSPI_CCR_FMODE QUADSPI_CCR_FMODE_Msk /*!< FMODE[1:0]: Functional Mode */
22386 #define QUADSPI_CCR_FMODE_0 (0x1UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x04000000 */
22387 #define QUADSPI_CCR_FMODE_1 (0x2UL << QUADSPI_CCR_FMODE_Pos) /*!< 0x08000000 */
22388 #define QUADSPI_CCR_SIOO_Pos (28U)
22389 #define QUADSPI_CCR_SIOO_Msk (0x1UL << QUADSPI_CCR_SIOO_Pos) /*!< 0x10000000 */
22390 #define QUADSPI_CCR_SIOO QUADSPI_CCR_SIOO_Msk /*!< SIOO: Send Instruction Only Once Mode */
22391 #define QUADSPI_CCR_DHHC_Pos (30U)
22392 #define QUADSPI_CCR_DHHC_Msk (0x1UL << QUADSPI_CCR_DHHC_Pos) /*!< 0x40000000 */
22393 #define QUADSPI_CCR_DHHC QUADSPI_CCR_DHHC_Msk /*!< DHHC: DDR hold half cycle */
22394 #define QUADSPI_CCR_DDRM_Pos (31U)
22395 #define QUADSPI_CCR_DDRM_Msk (0x1UL << QUADSPI_CCR_DDRM_Pos) /*!< 0x80000000 */
22396 #define QUADSPI_CCR_DDRM QUADSPI_CCR_DDRM_Msk /*!< DDRM: Double Data Rate Mode */
22397
22398 /****************** Bit definition for QUADSPI_AR register *******************/
22399 #define QUADSPI_AR_ADDRESS_Pos (0U)
22400 #define QUADSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << QUADSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
22401 #define QUADSPI_AR_ADDRESS QUADSPI_AR_ADDRESS_Msk /*!< ADDRESS[31:0]: Address */
22402
22403 /****************** Bit definition for QUADSPI_ABR register ******************/
22404 #define QUADSPI_ABR_ALTERNATE_Pos (0U)
22405 #define QUADSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << QUADSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
22406 #define QUADSPI_ABR_ALTERNATE QUADSPI_ABR_ALTERNATE_Msk /*!< ALTERNATE[31:0]: Alternate Bytes */
22407
22408 /****************** Bit definition for QUADSPI_DR register *******************/
22409 #define QUADSPI_DR_DATA_Pos (0U)
22410 #define QUADSPI_DR_DATA_Msk (0xFFFFFFFFUL << QUADSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
22411 #define QUADSPI_DR_DATA QUADSPI_DR_DATA_Msk /*!< DATA[31:0]: Data */
22412
22413 /****************** Bit definition for QUADSPI_PSMKR register ****************/
22414 #define QUADSPI_PSMKR_MASK_Pos (0U)
22415 #define QUADSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << QUADSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
22416 #define QUADSPI_PSMKR_MASK QUADSPI_PSMKR_MASK_Msk /*!< MASK[31:0]: Status Mask */
22417
22418 /****************** Bit definition for QUADSPI_PSMAR register ****************/
22419 #define QUADSPI_PSMAR_MATCH_Pos (0U)
22420 #define QUADSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << QUADSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
22421 #define QUADSPI_PSMAR_MATCH QUADSPI_PSMAR_MATCH_Msk /*!< MATCH[31:0]: Status Match */
22422
22423 /****************** Bit definition for QUADSPI_PIR register *****************/
22424 #define QUADSPI_PIR_INTERVAL_Pos (0U)
22425 #define QUADSPI_PIR_INTERVAL_Msk (0xFFFFUL << QUADSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
22426 #define QUADSPI_PIR_INTERVAL QUADSPI_PIR_INTERVAL_Msk /*!< INTERVAL[15:0]: Polling Interval */
22427
22428 /****************** Bit definition for QUADSPI_LPTR register *****************/
22429 #define QUADSPI_LPTR_TIMEOUT_Pos (0U)
22430 #define QUADSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << QUADSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
22431 #define QUADSPI_LPTR_TIMEOUT QUADSPI_LPTR_TIMEOUT_Msk /*!< TIMEOUT[15:0]: Timeout period */
22432
22433 /******************************************************************************/
22434 /* */
22435 /* SYSCFG */
22436 /* */
22437 /******************************************************************************/
22438
22439 /****************** Bit definition for SYSCFG_PMCR register ******************/
22440 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
22441 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
22442 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
22443 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
22444 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
22445 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
22446 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
22447 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
22448 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
22449 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
22450 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
22451 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
22452 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
22453 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
22454 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
22455 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
22456 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
22457 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
22458 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
22459 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
22460 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
22461 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
22462 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
22463 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
22464 #define SYSCFG_PMCR_BOOSTEN_Pos (8U)
22465 #define SYSCFG_PMCR_BOOSTEN_Msk (0x1UL << SYSCFG_PMCR_BOOSTEN_Pos) /*!< 0x00000100 */
22466 #define SYSCFG_PMCR_BOOSTEN SYSCFG_PMCR_BOOSTEN_Msk /*!< I/O analog switch voltage booster enable */
22467
22468 #define SYSCFG_PMCR_BOOSTVDDSEL_Pos (9U)
22469 #define SYSCFG_PMCR_BOOSTVDDSEL_Msk (0x1UL << SYSCFG_PMCR_BOOSTVDDSEL_Pos) /*!< 0x00000200 */
22470 #define SYSCFG_PMCR_BOOSTVDDSEL SYSCFG_PMCR_BOOSTVDDSEL_Msk /*!< Analog switch supply source selection : VDD/VDDA */
22471
22472 #define SYSCFG_PMCR_EPIS_SEL_Pos (21U)
22473 #define SYSCFG_PMCR_EPIS_SEL_Msk (0x7UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00E00000 */
22474 #define SYSCFG_PMCR_EPIS_SEL SYSCFG_PMCR_EPIS_SEL_Msk /*!< Ethernet PHY Interface Selection */
22475 #define SYSCFG_PMCR_EPIS_SEL_0 (0x1UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00200000 */
22476 #define SYSCFG_PMCR_EPIS_SEL_1 (0x2UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00400000 */
22477 #define SYSCFG_PMCR_EPIS_SEL_2 (0x4UL << SYSCFG_PMCR_EPIS_SEL_Pos) /*!< 0x00800000 */
22478 #define SYSCFG_PMCR_PA0SO_Pos (24U)
22479 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
22480 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
22481 #define SYSCFG_PMCR_PA1SO_Pos (25U)
22482 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
22483 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
22484 #define SYSCFG_PMCR_PC2SO_Pos (26U)
22485 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
22486 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
22487 #define SYSCFG_PMCR_PC3SO_Pos (27U)
22488 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
22489 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
22490
22491 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
22492 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
22493 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
22494 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
22495 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
22496 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
22497 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
22498 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
22499 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
22500 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
22501 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
22502 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
22503 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
22504 /**
22505 * @brief EXTI0 configuration
22506 */
22507 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
22508 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
22509 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
22510 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
22511 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
22512 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
22513 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
22514 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
22515 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
22516 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
22517 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
22518
22519 /**
22520 * @brief EXTI1 configuration
22521 */
22522 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
22523 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
22524 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
22525 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
22526 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
22527 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
22528 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
22529 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
22530 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
22531 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
22532 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
22533 /**
22534 * @brief EXTI2 configuration
22535 */
22536 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
22537 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
22538 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
22539 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
22540 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
22541 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
22542 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
22543 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
22544 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
22545 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
22546 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
22547
22548 /**
22549 * @brief EXTI3 configuration
22550 */
22551 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
22552 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
22553 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
22554 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
22555 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
22556 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
22557 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
22558 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
22559 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
22560 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
22561 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
22562
22563 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
22564 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
22565 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
22566 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
22567 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
22568 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
22569 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
22570 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
22571 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
22572 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
22573 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
22574 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
22575 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
22576 /**
22577 * @brief EXTI4 configuration
22578 */
22579 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
22580 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
22581 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
22582 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
22583 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
22584 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
22585 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
22586 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
22587 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
22588 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
22589 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
22590 /**
22591 * @brief EXTI5 configuration
22592 */
22593 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
22594 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
22595 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
22596 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
22597 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
22598 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
22599 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
22600 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
22601 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
22602 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
22603 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
22604 /**
22605 * @brief EXTI6 configuration
22606 */
22607 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
22608 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
22609 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
22610 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
22611 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
22612 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
22613 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
22614 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
22615 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
22616 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
22617 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
22618
22619 /**
22620 * @brief EXTI7 configuration
22621 */
22622 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
22623 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
22624 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
22625 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
22626 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
22627 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
22628 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
22629 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
22630 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
22631 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
22632 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
22633
22634 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
22635 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
22636 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
22637 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
22638 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
22639 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
22640 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
22641 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
22642 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
22643 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
22644 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
22645 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
22646 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
22647
22648 /**
22649 * @brief EXTI8 configuration
22650 */
22651 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
22652 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
22653 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
22654 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
22655 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
22656 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
22657 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
22658 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
22659 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
22660 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
22661 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
22662
22663 /**
22664 * @brief EXTI9 configuration
22665 */
22666 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
22667 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
22668 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
22669 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
22670 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
22671 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
22672 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
22673 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
22674 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
22675 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
22676 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
22677
22678 /**
22679 * @brief EXTI10 configuration
22680 */
22681 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
22682 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
22683 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
22684 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
22685 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
22686 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
22687 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
22688 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
22689 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
22690 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
22691 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
22692
22693 /**
22694 * @brief EXTI11 configuration
22695 */
22696 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
22697 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
22698 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
22699 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
22700 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
22701 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
22702 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
22703 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
22704 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
22705 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
22706 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
22707
22708 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
22709 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
22710 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
22711 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
22712 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
22713 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
22714 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
22715 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
22716 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
22717 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
22718 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
22719 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
22720 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
22721 /**
22722 * @brief EXTI12 configuration
22723 */
22724 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
22725 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
22726 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
22727 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
22728 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
22729 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
22730 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
22731 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
22732 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
22733 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
22734 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
22735 /**
22736 * @brief EXTI13 configuration
22737 */
22738 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
22739 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
22740 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
22741 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
22742 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
22743 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
22744 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
22745 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
22746 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
22747 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
22748 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
22749 /**
22750 * @brief EXTI14 configuration
22751 */
22752 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
22753 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
22754 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
22755 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
22756 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
22757 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
22758 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
22759 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
22760 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
22761 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
22762 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
22763 /**
22764 * @brief EXTI15 configuration
22765 */
22766 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
22767 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
22768 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
22769 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
22770 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
22771 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
22772 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
22773 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
22774 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
22775 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
22776 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
22777
22778 /****************** Bit definition for SYSCFG_CFGR register ******************/
22779 #define SYSCFG_CFGR_CM4L_Pos (0U)
22780 #define SYSCFG_CFGR_CM4L_Msk (0x1UL << SYSCFG_CFGR_CM4L_Pos) /*!< 0x00000001 */
22781 #define SYSCFG_CFGR_CM4L SYSCFG_CFGR_CM4L_Msk /*!<Cortex-M4 LOCKUP (Hardfault) output enable bit */
22782 #define SYSCFG_CFGR_PVDL_Pos (2U)
22783 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
22784 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
22785 #define SYSCFG_CFGR_FLASHL_Pos (3U)
22786 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
22787 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
22788 #define SYSCFG_CFGR_CM7L_Pos (6U)
22789 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
22790 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
22791 #define SYSCFG_CFGR_BKRAML_Pos (7U)
22792 #define SYSCFG_CFGR_BKRAML_Msk (0x1UL << SYSCFG_CFGR_BKRAML_Pos) /*!< 0x00000080 */
22793 #define SYSCFG_CFGR_BKRAML SYSCFG_CFGR_BKRAML_Msk /*!<Backup SRAM double ECC error lock bit */
22794 #define SYSCFG_CFGR_SRAM4L_Pos (9U)
22795 #define SYSCFG_CFGR_SRAM4L_Msk (0x1UL << SYSCFG_CFGR_SRAM4L_Pos) /*!< 0x00000200 */
22796 #define SYSCFG_CFGR_SRAM4L SYSCFG_CFGR_SRAM4L_Msk /*!<SRAM4 double ECC error lock bit */
22797 #define SYSCFG_CFGR_SRAM3L_Pos (10U)
22798 #define SYSCFG_CFGR_SRAM3L_Msk (0x1UL << SYSCFG_CFGR_SRAM3L_Pos) /*!< 0x00000400 */
22799 #define SYSCFG_CFGR_SRAM3L SYSCFG_CFGR_SRAM3L_Msk /*!<SRAM3 double ECC error lock bit */
22800 #define SYSCFG_CFGR_SRAM2L_Pos (11U)
22801 #define SYSCFG_CFGR_SRAM2L_Msk (0x1UL << SYSCFG_CFGR_SRAM2L_Pos) /*!< 0x00000800 */
22802 #define SYSCFG_CFGR_SRAM2L SYSCFG_CFGR_SRAM2L_Msk /*!<SRAM2 double ECC error lock bit */
22803 #define SYSCFG_CFGR_SRAM1L_Pos (12U)
22804 #define SYSCFG_CFGR_SRAM1L_Msk (0x1UL << SYSCFG_CFGR_SRAM1L_Pos) /*!< 0x00001000 */
22805 #define SYSCFG_CFGR_SRAM1L SYSCFG_CFGR_SRAM1L_Msk /*!<SRAM1 double ECC error lock bit */
22806 #define SYSCFG_CFGR_DTCML_Pos (13U)
22807 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
22808 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
22809 #define SYSCFG_CFGR_ITCML_Pos (14U)
22810 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
22811 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
22812 #define SYSCFG_CFGR_AXISRAML_Pos (15U)
22813 #define SYSCFG_CFGR_AXISRAML_Msk (0x1UL << SYSCFG_CFGR_AXISRAML_Pos) /*!< 0x00008000 */
22814 #define SYSCFG_CFGR_AXISRAML SYSCFG_CFGR_AXISRAML_Msk /*!<AXISRAM double ECC error lock bit */
22815
22816 /****************** Bit definition for SYSCFG_CCCSR register ******************/
22817 #define SYSCFG_CCCSR_EN_Pos (0U)
22818 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
22819 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
22820 #define SYSCFG_CCCSR_CS_Pos (1U)
22821 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
22822 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
22823 #define SYSCFG_CCCSR_READY_Pos (8U)
22824 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
22825 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
22826 #define SYSCFG_CCCSR_HSLV_Pos (16U)
22827 #define SYSCFG_CCCSR_HSLV_Msk (0x1UL << SYSCFG_CCCSR_HSLV_Pos) /*!< 0x00010000 */
22828 #define SYSCFG_CCCSR_HSLV SYSCFG_CCCSR_HSLV_Msk /*!< High-speed at low-voltage */
22829
22830 /****************** Bit definition for SYSCFG_CCVR register *******************/
22831 #define SYSCFG_CCVR_NCV_Pos (0U)
22832 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
22833 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
22834 #define SYSCFG_CCVR_PCV_Pos (4U)
22835 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
22836 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
22837
22838 /****************** Bit definition for SYSCFG_CCCR register *******************/
22839 #define SYSCFG_CCCR_NCC_Pos (0U)
22840 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
22841 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
22842 #define SYSCFG_CCCR_PCC_Pos (4U)
22843 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
22844 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
22845 /****************** Bit definition for SYSCFG_PWRCR register *******************/
22846 #define SYSCFG_PWRCR_ODEN_Pos (0U)
22847 #define SYSCFG_PWRCR_ODEN_Msk (0x1UL << SYSCFG_PWRCR_ODEN_Pos) /*!< 0x00000001 */
22848 #define SYSCFG_PWRCR_ODEN SYSCFG_PWRCR_ODEN_Msk /*!< PWR overdrive enable */
22849
22850 /****************** Bit definition for SYSCFG_PKGR register *******************/
22851 #define SYSCFG_PKGR_PKG_Pos (0U)
22852 #define SYSCFG_PKGR_PKG_Msk (0xFUL << SYSCFG_PKGR_PKG_Pos) /*!< 0x0000000F */
22853 #define SYSCFG_PKGR_PKG SYSCFG_PKGR_PKG_Msk /*!< Package type */
22854
22855 /****************** Bit definition for SYSCFG_UR0 register *******************/
22856 #define SYSCFG_UR0_BKS_Pos (0U)
22857 #define SYSCFG_UR0_BKS_Msk (0x1UL << SYSCFG_UR0_BKS_Pos) /*!< 0x00000001 */
22858 #define SYSCFG_UR0_BKS SYSCFG_UR0_BKS_Msk /*!< Bank Swap */
22859 #define SYSCFG_UR0_RDP_Pos (16U)
22860 #define SYSCFG_UR0_RDP_Msk (0xFFUL << SYSCFG_UR0_RDP_Pos) /*!< 0x00FF0000 */
22861 #define SYSCFG_UR0_RDP SYSCFG_UR0_RDP_Msk /*!< Readout protection */
22862
22863 /****************** Bit definition for SYSCFG_UR1 register *******************/
22864 #define SYSCFG_UR1_BCM4_Pos (0U)
22865 #define SYSCFG_UR1_BCM4_Msk (0x1UL << SYSCFG_UR1_BCM4_Pos) /*!< 0x00000001 */
22866 #define SYSCFG_UR1_BCM4 SYSCFG_UR1_BCM4_Msk /*!< Boot Cortex-M4 */
22867 #define SYSCFG_UR1_BCM7_Pos (16U)
22868 #define SYSCFG_UR1_BCM7_Msk (0x1UL << SYSCFG_UR1_BCM7_Pos) /*!< 0x00010000 */
22869 #define SYSCFG_UR1_BCM7 SYSCFG_UR1_BCM7_Msk /*!< Boot Cortex-M7 */
22870 /****************** Bit definition for SYSCFG_UR2 register *******************/
22871 #define SYSCFG_UR2_BORH_Pos (0U)
22872 #define SYSCFG_UR2_BORH_Msk (0x3UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000003 */
22873 #define SYSCFG_UR2_BORH SYSCFG_UR2_BORH_Msk /*!< Brown Out Reset High level */
22874 #define SYSCFG_UR2_BORH_0 (0x1UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000001 */
22875 #define SYSCFG_UR2_BORH_1 (0x2UL << SYSCFG_UR2_BORH_Pos) /*!< 0x00000002 */
22876 #define SYSCFG_UR2_BCM7_ADD0_Pos (16U)
22877 #define SYSCFG_UR2_BCM7_ADD0_Msk (0xFFFFUL << SYSCFG_UR2_BCM7_ADD0_Pos) /*!< 0xFFFF0000 */
22878 #define SYSCFG_UR2_BCM7_ADD0 SYSCFG_UR2_BCM7_ADD0_Msk /*!< Boot Cortex-M7 Address 0 */
22879 /****************** Bit definition for SYSCFG_UR3 register *******************/
22880 #define SYSCFG_UR3_BCM7_ADD1_Pos (0U)
22881 #define SYSCFG_UR3_BCM7_ADD1_Msk (0xFFFFUL << SYSCFG_UR3_BCM7_ADD1_Pos) /*!< 0x0000FFFF */
22882 #define SYSCFG_UR3_BCM7_ADD1 SYSCFG_UR3_BCM7_ADD1_Msk /*!< Boot Cortex-M7 Address 1 */
22883
22884 #define SYSCFG_UR3_BCM4_ADD0_Pos (16U)
22885 #define SYSCFG_UR3_BCM4_ADD0_Msk (0xFFFFUL << SYSCFG_UR3_BCM4_ADD0_Pos) /*!< 0xFFFF0000 */
22886 #define SYSCFG_UR3_BCM4_ADD0 SYSCFG_UR3_BCM4_ADD0_Msk /*!< Boot Cortex-M4 Address 0 */
22887
22888 /****************** Bit definition for SYSCFG_UR4 register *******************/
22889
22890 #define SYSCFG_UR4_BCM4_ADD1_Pos (0U)
22891 #define SYSCFG_UR4_BCM4_ADD1_Msk (0xFFFFUL << SYSCFG_UR4_BCM4_ADD1_Pos) /*!< 0x0000FFFF */
22892 #define SYSCFG_UR4_BCM4_ADD1 SYSCFG_UR4_BCM4_ADD1_Msk /*!< Boot Cortex-M4 Address 1 */
22893
22894 #define SYSCFG_UR4_MEPAD_BANK1_Pos (16U)
22895 #define SYSCFG_UR4_MEPAD_BANK1_Msk (0x1UL << SYSCFG_UR4_MEPAD_BANK1_Pos) /*!< 0x00010000 */
22896 #define SYSCFG_UR4_MEPAD_BANK1 SYSCFG_UR4_MEPAD_BANK1_Msk /*!< Mass Erase Protected Area Disabled for bank 1 */
22897
22898 /****************** Bit definition for SYSCFG_UR5 register *******************/
22899 #define SYSCFG_UR5_MESAD_BANK1_Pos (0U)
22900 #define SYSCFG_UR5_MESAD_BANK1_Msk (0x1UL << SYSCFG_UR5_MESAD_BANK1_Pos) /*!< 0x00000001 */
22901 #define SYSCFG_UR5_MESAD_BANK1 SYSCFG_UR5_MESAD_BANK1_Msk /*!< Mass erase secured area disabled for bank 1 */
22902 #define SYSCFG_UR5_WRPN_BANK1_Pos (16U)
22903 #define SYSCFG_UR5_WRPN_BANK1_Msk (0xFFUL << SYSCFG_UR5_WRPN_BANK1_Pos) /*!< 0x00FF0000 */
22904 #define SYSCFG_UR5_WRPN_BANK1 SYSCFG_UR5_WRPN_BANK1_Msk /*!< Write protection for flash bank 1 */
22905
22906 /****************** Bit definition for SYSCFG_UR6 register *******************/
22907 #define SYSCFG_UR6_PABEG_BANK1_Pos (0U)
22908 #define SYSCFG_UR6_PABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PABEG_BANK1_Pos) /*!< 0x00000FFF */
22909 #define SYSCFG_UR6_PABEG_BANK1 SYSCFG_UR6_PABEG_BANK1_Msk /*!< Protected area start address for bank 1 */
22910 #define SYSCFG_UR6_PAEND_BANK1_Pos (16U)
22911 #define SYSCFG_UR6_PAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR6_PAEND_BANK1_Pos) /*!< 0x0FFF0000 */
22912 #define SYSCFG_UR6_PAEND_BANK1 SYSCFG_UR6_PAEND_BANK1_Msk /*!< Protected area end address for bank 1 */
22913
22914 /****************** Bit definition for SYSCFG_UR7 register *******************/
22915 #define SYSCFG_UR7_SABEG_BANK1_Pos (0U)
22916 #define SYSCFG_UR7_SABEG_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SABEG_BANK1_Pos) /*!< 0x00000FFF */
22917 #define SYSCFG_UR7_SABEG_BANK1 SYSCFG_UR7_SABEG_BANK1_Msk /*!< Secured area start address for bank 1 */
22918 #define SYSCFG_UR7_SAEND_BANK1_Pos (16U)
22919 #define SYSCFG_UR7_SAEND_BANK1_Msk (0xFFFUL << SYSCFG_UR7_SAEND_BANK1_Pos) /*!< 0x0FFF0000 */
22920 #define SYSCFG_UR7_SAEND_BANK1 SYSCFG_UR7_SAEND_BANK1_Msk /*!< Secured area end address for bank 1 */
22921
22922 /****************** Bit definition for SYSCFG_UR8 register *******************/
22923 #define SYSCFG_UR8_MEPAD_BANK2_Pos (0U)
22924 #define SYSCFG_UR8_MEPAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MEPAD_BANK2_Pos) /*!< 0x00000001 */
22925 #define SYSCFG_UR8_MEPAD_BANK2 SYSCFG_UR8_MEPAD_BANK2_Msk /*!< Mass erase Protected area disabled for bank 2 */
22926 #define SYSCFG_UR8_MESAD_BANK2_Pos (16U)
22927 #define SYSCFG_UR8_MESAD_BANK2_Msk (0x1UL << SYSCFG_UR8_MESAD_BANK2_Pos) /*!< 0x00010000 */
22928 #define SYSCFG_UR8_MESAD_BANK2 SYSCFG_UR8_MESAD_BANK2_Msk /*!< Mass Erase Secured Area Disabled for bank 2 */
22929
22930 /****************** Bit definition for SYSCFG_UR9 register *******************/
22931 #define SYSCFG_UR9_WRPN_BANK2_Pos (0U)
22932 #define SYSCFG_UR9_WRPN_BANK2_Msk (0xFFUL << SYSCFG_UR9_WRPN_BANK2_Pos) /*!< 0x000000FF */
22933 #define SYSCFG_UR9_WRPN_BANK2 SYSCFG_UR9_WRPN_BANK2_Msk /*!< Write protection for flash bank 2 */
22934 #define SYSCFG_UR9_PABEG_BANK2_Pos (16U)
22935 #define SYSCFG_UR9_PABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR9_PABEG_BANK2_Pos) /*!< 0x0FFF0000 */
22936 #define SYSCFG_UR9_PABEG_BANK2 SYSCFG_UR9_PABEG_BANK2_Msk /*!< Protected area start address for bank 2 */
22937
22938 /****************** Bit definition for SYSCFG_UR10 register *******************/
22939 #define SYSCFG_UR10_PAEND_BANK2_Pos (0U)
22940 #define SYSCFG_UR10_PAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR10_PAEND_BANK2_Pos) /*!< 0x00000FFF */
22941 #define SYSCFG_UR10_PAEND_BANK2 SYSCFG_UR10_PAEND_BANK2_Msk /*!< Protected area end address for bank 2 */
22942 #define SYSCFG_UR10_SABEG_BANK2_Pos (16U)
22943 #define SYSCFG_UR10_SABEG_BANK2_Msk (0xFFFUL << SYSCFG_UR10_SABEG_BANK2_Pos) /*!< 0x0FFF0000 */
22944 #define SYSCFG_UR10_SABEG_BANK2 SYSCFG_UR10_SABEG_BANK2_Msk /*!< Secured area start address for bank 2 */
22945
22946 /****************** Bit definition for SYSCFG_UR11 register *******************/
22947 #define SYSCFG_UR11_SAEND_BANK2_Pos (0U)
22948 #define SYSCFG_UR11_SAEND_BANK2_Msk (0xFFFUL << SYSCFG_UR11_SAEND_BANK2_Pos) /*!< 0x00000FFF */
22949 #define SYSCFG_UR11_SAEND_BANK2 SYSCFG_UR11_SAEND_BANK2_Msk /*!< Secured area end address for bank 2 */
22950 #define SYSCFG_UR11_IWDG1M_Pos (16U)
22951 #define SYSCFG_UR11_IWDG1M_Msk (0x1UL << SYSCFG_UR11_IWDG1M_Pos) /*!< 0x00010000 */
22952 #define SYSCFG_UR11_IWDG1M SYSCFG_UR11_IWDG1M_Msk /*!< Independent Watchdog 1 mode (SW or HW) */
22953
22954 /****************** Bit definition for SYSCFG_UR12 register *******************/
22955 #define SYSCFG_UR12_IWDG2M_Pos (0U)
22956 #define SYSCFG_UR12_IWDG2M_Msk (0x1UL << SYSCFG_UR12_IWDG2M_Pos) /*!< 0x00000001 */
22957 #define SYSCFG_UR12_IWDG2M SYSCFG_UR12_IWDG2M_Msk /*!< Independent Watchdog 2 mode (SW or HW) */
22958
22959 #define SYSCFG_UR12_SECURE_Pos (16U)
22960 #define SYSCFG_UR12_SECURE_Msk (0x1UL << SYSCFG_UR12_SECURE_Pos) /*!< 0x00010000 */
22961 #define SYSCFG_UR12_SECURE SYSCFG_UR12_SECURE_Msk /*!< Secure mode status */
22962
22963 /****************** Bit definition for SYSCFG_UR13 register *******************/
22964 #define SYSCFG_UR13_SDRS_Pos (0U)
22965 #define SYSCFG_UR13_SDRS_Msk (0x3UL << SYSCFG_UR13_SDRS_Pos) /*!< 0x00000003 */
22966 #define SYSCFG_UR13_SDRS SYSCFG_UR13_SDRS_Msk /*!< Secured DTCM RAM Size */
22967 #define SYSCFG_UR13_D1SBRST_Pos (16U)
22968 #define SYSCFG_UR13_D1SBRST_Msk (0x1UL << SYSCFG_UR13_D1SBRST_Pos) /*!< 0x00010000 */
22969 #define SYSCFG_UR13_D1SBRST SYSCFG_UR13_D1SBRST_Msk /*!< D1 Standby reset */
22970
22971 /****************** Bit definition for SYSCFG_UR14 register *******************/
22972 #define SYSCFG_UR14_D1STPRST_Pos (0U)
22973 #define SYSCFG_UR14_D1STPRST_Msk (0x1UL << SYSCFG_UR14_D1STPRST_Pos) /*!< 0x00000001 */
22974 #define SYSCFG_UR14_D1STPRST SYSCFG_UR14_D1STPRST_Msk /*!< D1 Stop Reset */
22975 #define SYSCFG_UR14_D2SBRST_Pos (16U)
22976 #define SYSCFG_UR14_D2SBRST_Msk (0x1UL << SYSCFG_UR14_D2SBRST_Pos) /*!< 0x00010000 */
22977 #define SYSCFG_UR14_D2SBRST SYSCFG_UR14_D2SBRST_Msk /*!< D2 Standby Reset */
22978
22979 /****************** Bit definition for SYSCFG_UR15 register *******************/
22980 #define SYSCFG_UR15_D2STPRST_Pos (0U)
22981 #define SYSCFG_UR15_D2STPRST_Msk (0x1UL << SYSCFG_UR15_D2STPRST_Pos) /*!< 0x00000001 */
22982 #define SYSCFG_UR15_D2STPRST SYSCFG_UR15_D2STPRST_Msk /*!< D2 Stop Reset */
22983 #define SYSCFG_UR15_FZIWDGSTB_Pos (16U)
22984 #define SYSCFG_UR15_FZIWDGSTB_Msk (0x1UL << SYSCFG_UR15_FZIWDGSTB_Pos) /*!< 0x00010000 */
22985 #define SYSCFG_UR15_FZIWDGSTB SYSCFG_UR15_FZIWDGSTB_Msk /*!< Freeze independent watchdogs in Standby mode */
22986
22987 /****************** Bit definition for SYSCFG_UR16 register *******************/
22988 #define SYSCFG_UR16_FZIWDGSTP_Pos (0U)
22989 #define SYSCFG_UR16_FZIWDGSTP_Msk (0x1UL << SYSCFG_UR16_FZIWDGSTP_Pos) /*!< 0x00000001 */
22990 #define SYSCFG_UR16_FZIWDGSTP SYSCFG_UR16_FZIWDGSTP_Msk /*!< Freeze independent watchdogs in Stop mode */
22991 #define SYSCFG_UR16_PKP_Pos (16U)
22992 #define SYSCFG_UR16_PKP_Msk (0x1UL << SYSCFG_UR16_PKP_Pos) /*!< 0x00010000 */
22993 #define SYSCFG_UR16_PKP SYSCFG_UR16_PKP_Msk /*!< Private key programmed */
22994
22995 /****************** Bit definition for SYSCFG_UR17 register *******************/
22996 #define SYSCFG_UR17_IOHSLV_Pos (0U)
22997 #define SYSCFG_UR17_IOHSLV_Msk (0x1UL << SYSCFG_UR17_IOHSLV_Pos) /*!< 0x00000001 */
22998 #define SYSCFG_UR17_IOHSLV SYSCFG_UR17_IOHSLV_Msk /*!< I/O high speed / low voltage */
22999
23000
23001 /******************************************************************************/
23002 /* */
23003 /* TIM */
23004 /* */
23005 /******************************************************************************/
23006 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
23007
23008 /******************* Bit definition for TIM_CR1 register ********************/
23009 #define TIM_CR1_CEN_Pos (0U)
23010 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
23011 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
23012 #define TIM_CR1_UDIS_Pos (1U)
23013 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
23014 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
23015 #define TIM_CR1_URS_Pos (2U)
23016 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
23017 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
23018 #define TIM_CR1_OPM_Pos (3U)
23019 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
23020 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
23021 #define TIM_CR1_DIR_Pos (4U)
23022 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
23023 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
23024
23025 #define TIM_CR1_CMS_Pos (5U)
23026 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
23027 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
23028 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
23029 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
23030
23031 #define TIM_CR1_ARPE_Pos (7U)
23032 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
23033 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
23034
23035 #define TIM_CR1_CKD_Pos (8U)
23036 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
23037 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
23038 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
23039 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
23040
23041 #define TIM_CR1_UIFREMAP_Pos (11U)
23042 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
23043 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
23044
23045 /******************* Bit definition for TIM_CR2 register ********************/
23046 #define TIM_CR2_CCPC_Pos (0U)
23047 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
23048 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
23049 #define TIM_CR2_CCUS_Pos (2U)
23050 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
23051 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
23052 #define TIM_CR2_CCDS_Pos (3U)
23053 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
23054 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
23055
23056 #define TIM_CR2_MMS_Pos (4U)
23057 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
23058 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
23059 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
23060 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
23061 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
23062
23063 #define TIM_CR2_TI1S_Pos (7U)
23064 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
23065 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
23066 #define TIM_CR2_OIS1_Pos (8U)
23067 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
23068 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
23069 #define TIM_CR2_OIS1N_Pos (9U)
23070 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
23071 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
23072 #define TIM_CR2_OIS2_Pos (10U)
23073 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
23074 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
23075 #define TIM_CR2_OIS2N_Pos (11U)
23076 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
23077 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
23078 #define TIM_CR2_OIS3_Pos (12U)
23079 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
23080 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
23081 #define TIM_CR2_OIS3N_Pos (13U)
23082 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
23083 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
23084 #define TIM_CR2_OIS4_Pos (14U)
23085 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
23086 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
23087 #define TIM_CR2_OIS5_Pos (16U)
23088 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
23089 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
23090 #define TIM_CR2_OIS6_Pos (17U)
23091 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
23092 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
23093
23094 #define TIM_CR2_MMS2_Pos (20U)
23095 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
23096 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
23097 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
23098 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
23099 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
23100 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
23101
23102 /******************* Bit definition for TIM_SMCR register *******************/
23103 #define TIM_SMCR_SMS_Pos (0U)
23104 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
23105 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
23106 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
23107 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
23108 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
23109 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
23110
23111 #define TIM_SMCR_TS_Pos (4U)
23112 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
23113 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
23114 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
23115 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
23116 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
23117 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
23118 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
23119
23120 #define TIM_SMCR_MSM_Pos (7U)
23121 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
23122 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
23123
23124 #define TIM_SMCR_ETF_Pos (8U)
23125 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
23126 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
23127 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
23128 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
23129 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
23130 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
23131
23132 #define TIM_SMCR_ETPS_Pos (12U)
23133 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
23134 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
23135 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
23136 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
23137
23138 #define TIM_SMCR_ECE_Pos (14U)
23139 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
23140 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
23141 #define TIM_SMCR_ETP_Pos (15U)
23142 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
23143 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
23144
23145 /******************* Bit definition for TIM_DIER register *******************/
23146 #define TIM_DIER_UIE_Pos (0U)
23147 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
23148 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
23149 #define TIM_DIER_CC1IE_Pos (1U)
23150 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
23151 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
23152 #define TIM_DIER_CC2IE_Pos (2U)
23153 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
23154 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
23155 #define TIM_DIER_CC3IE_Pos (3U)
23156 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
23157 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
23158 #define TIM_DIER_CC4IE_Pos (4U)
23159 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
23160 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
23161 #define TIM_DIER_COMIE_Pos (5U)
23162 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
23163 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
23164 #define TIM_DIER_TIE_Pos (6U)
23165 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
23166 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
23167 #define TIM_DIER_BIE_Pos (7U)
23168 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
23169 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
23170 #define TIM_DIER_UDE_Pos (8U)
23171 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
23172 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
23173 #define TIM_DIER_CC1DE_Pos (9U)
23174 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
23175 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
23176 #define TIM_DIER_CC2DE_Pos (10U)
23177 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
23178 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
23179 #define TIM_DIER_CC3DE_Pos (11U)
23180 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
23181 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
23182 #define TIM_DIER_CC4DE_Pos (12U)
23183 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
23184 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
23185 #define TIM_DIER_COMDE_Pos (13U)
23186 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
23187 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
23188 #define TIM_DIER_TDE_Pos (14U)
23189 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
23190 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
23191
23192 /******************** Bit definition for TIM_SR register ********************/
23193 #define TIM_SR_UIF_Pos (0U)
23194 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
23195 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
23196 #define TIM_SR_CC1IF_Pos (1U)
23197 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
23198 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
23199 #define TIM_SR_CC2IF_Pos (2U)
23200 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
23201 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
23202 #define TIM_SR_CC3IF_Pos (3U)
23203 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
23204 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
23205 #define TIM_SR_CC4IF_Pos (4U)
23206 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
23207 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
23208 #define TIM_SR_COMIF_Pos (5U)
23209 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
23210 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
23211 #define TIM_SR_TIF_Pos (6U)
23212 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
23213 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
23214 #define TIM_SR_BIF_Pos (7U)
23215 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
23216 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
23217 #define TIM_SR_B2IF_Pos (8U)
23218 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
23219 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
23220 #define TIM_SR_CC1OF_Pos (9U)
23221 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
23222 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
23223 #define TIM_SR_CC2OF_Pos (10U)
23224 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
23225 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
23226 #define TIM_SR_CC3OF_Pos (11U)
23227 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
23228 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
23229 #define TIM_SR_CC4OF_Pos (12U)
23230 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
23231 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
23232 #define TIM_SR_CC5IF_Pos (16U)
23233 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
23234 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
23235 #define TIM_SR_CC6IF_Pos (17U)
23236 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
23237 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
23238 #define TIM_SR_SBIF_Pos (13U)
23239 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
23240 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
23241
23242 /******************* Bit definition for TIM_EGR register ********************/
23243 #define TIM_EGR_UG_Pos (0U)
23244 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
23245 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
23246 #define TIM_EGR_CC1G_Pos (1U)
23247 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
23248 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
23249 #define TIM_EGR_CC2G_Pos (2U)
23250 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
23251 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
23252 #define TIM_EGR_CC3G_Pos (3U)
23253 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
23254 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
23255 #define TIM_EGR_CC4G_Pos (4U)
23256 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
23257 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
23258 #define TIM_EGR_COMG_Pos (5U)
23259 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
23260 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
23261 #define TIM_EGR_TG_Pos (6U)
23262 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
23263 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
23264 #define TIM_EGR_BG_Pos (7U)
23265 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
23266 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
23267 #define TIM_EGR_B2G_Pos (8U)
23268 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
23269 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
23270
23271
23272 /****************** Bit definition for TIM_CCMR1 register *******************/
23273 #define TIM_CCMR1_CC1S_Pos (0U)
23274 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
23275 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
23276 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
23277 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
23278
23279 #define TIM_CCMR1_OC1FE_Pos (2U)
23280 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
23281 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
23282 #define TIM_CCMR1_OC1PE_Pos (3U)
23283 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
23284 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
23285
23286 #define TIM_CCMR1_OC1M_Pos (4U)
23287 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
23288 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
23289 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
23290 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
23291 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
23292 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
23293
23294 #define TIM_CCMR1_OC1CE_Pos (7U)
23295 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
23296 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
23297
23298 #define TIM_CCMR1_CC2S_Pos (8U)
23299 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
23300 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
23301 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
23302 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
23303
23304 #define TIM_CCMR1_OC2FE_Pos (10U)
23305 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
23306 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
23307 #define TIM_CCMR1_OC2PE_Pos (11U)
23308 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
23309 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
23310
23311 #define TIM_CCMR1_OC2M_Pos (12U)
23312 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
23313 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
23314 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
23315 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
23316 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
23317 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
23318
23319 #define TIM_CCMR1_OC2CE_Pos (15U)
23320 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
23321 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
23322
23323 /*----------------------------------------------------------------------------*/
23324
23325 #define TIM_CCMR1_IC1PSC_Pos (2U)
23326 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
23327 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
23328 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
23329 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
23330
23331 #define TIM_CCMR1_IC1F_Pos (4U)
23332 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
23333 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
23334 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
23335 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
23336 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
23337 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
23338
23339 #define TIM_CCMR1_IC2PSC_Pos (10U)
23340 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
23341 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
23342 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
23343 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
23344
23345 #define TIM_CCMR1_IC2F_Pos (12U)
23346 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
23347 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
23348 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
23349 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
23350 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
23351 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
23352
23353 /****************** Bit definition for TIM_CCMR2 register *******************/
23354 #define TIM_CCMR2_CC3S_Pos (0U)
23355 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
23356 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
23357 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
23358 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
23359
23360 #define TIM_CCMR2_OC3FE_Pos (2U)
23361 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
23362 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
23363 #define TIM_CCMR2_OC3PE_Pos (3U)
23364 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
23365 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
23366
23367 #define TIM_CCMR2_OC3M_Pos (4U)
23368 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
23369 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
23370 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
23371 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
23372 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
23373 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
23374
23375 #define TIM_CCMR2_OC3CE_Pos (7U)
23376 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
23377 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
23378
23379 #define TIM_CCMR2_CC4S_Pos (8U)
23380 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
23381 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
23382 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
23383 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
23384
23385 #define TIM_CCMR2_OC4FE_Pos (10U)
23386 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
23387 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
23388 #define TIM_CCMR2_OC4PE_Pos (11U)
23389 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
23390 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
23391
23392 #define TIM_CCMR2_OC4M_Pos (12U)
23393 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
23394 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
23395 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
23396 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
23397 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
23398 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
23399
23400 #define TIM_CCMR2_OC4CE_Pos (15U)
23401 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
23402 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
23403
23404 /*----------------------------------------------------------------------------*/
23405
23406 #define TIM_CCMR2_IC3PSC_Pos (2U)
23407 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
23408 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
23409 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
23410 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
23411
23412 #define TIM_CCMR2_IC3F_Pos (4U)
23413 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
23414 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
23415 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
23416 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
23417 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
23418 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
23419
23420 #define TIM_CCMR2_IC4PSC_Pos (10U)
23421 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
23422 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
23423 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
23424 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
23425
23426 #define TIM_CCMR2_IC4F_Pos (12U)
23427 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
23428 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
23429 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
23430 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
23431 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
23432 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
23433
23434 /******************* Bit definition for TIM_CCER register *******************/
23435 #define TIM_CCER_CC1E_Pos (0U)
23436 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
23437 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
23438 #define TIM_CCER_CC1P_Pos (1U)
23439 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
23440 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
23441 #define TIM_CCER_CC1NE_Pos (2U)
23442 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
23443 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
23444 #define TIM_CCER_CC1NP_Pos (3U)
23445 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
23446 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
23447 #define TIM_CCER_CC2E_Pos (4U)
23448 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
23449 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
23450 #define TIM_CCER_CC2P_Pos (5U)
23451 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
23452 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
23453 #define TIM_CCER_CC2NE_Pos (6U)
23454 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
23455 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
23456 #define TIM_CCER_CC2NP_Pos (7U)
23457 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
23458 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
23459 #define TIM_CCER_CC3E_Pos (8U)
23460 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
23461 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
23462 #define TIM_CCER_CC3P_Pos (9U)
23463 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
23464 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
23465 #define TIM_CCER_CC3NE_Pos (10U)
23466 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
23467 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
23468 #define TIM_CCER_CC3NP_Pos (11U)
23469 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
23470 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
23471 #define TIM_CCER_CC4E_Pos (12U)
23472 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
23473 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
23474 #define TIM_CCER_CC4P_Pos (13U)
23475 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
23476 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
23477 #define TIM_CCER_CC4NP_Pos (15U)
23478 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
23479 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
23480 #define TIM_CCER_CC5E_Pos (16U)
23481 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
23482 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
23483 #define TIM_CCER_CC5P_Pos (17U)
23484 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
23485 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
23486 #define TIM_CCER_CC6E_Pos (20U)
23487 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
23488 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
23489 #define TIM_CCER_CC6P_Pos (21U)
23490 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
23491 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
23492 /******************* Bit definition for TIM_CNT register ********************/
23493 #define TIM_CNT_CNT_Pos (0U)
23494 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
23495 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
23496 #define TIM_CNT_UIFCPY_Pos (31U)
23497 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
23498 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
23499 /******************* Bit definition for TIM_PSC register ********************/
23500 #define TIM_PSC_PSC_Pos (0U)
23501 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
23502 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
23503
23504 /******************* Bit definition for TIM_ARR register ********************/
23505 #define TIM_ARR_ARR_Pos (0U)
23506 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
23507 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
23508
23509 /******************* Bit definition for TIM_RCR register ********************/
23510 #define TIM_RCR_REP_Pos (0U)
23511 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
23512 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
23513
23514 /******************* Bit definition for TIM_CCR1 register *******************/
23515 #define TIM_CCR1_CCR1_Pos (0U)
23516 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
23517 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
23518
23519 /******************* Bit definition for TIM_CCR2 register *******************/
23520 #define TIM_CCR2_CCR2_Pos (0U)
23521 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
23522 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
23523
23524 /******************* Bit definition for TIM_CCR3 register *******************/
23525 #define TIM_CCR3_CCR3_Pos (0U)
23526 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
23527 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
23528
23529 /******************* Bit definition for TIM_CCR4 register *******************/
23530 #define TIM_CCR4_CCR4_Pos (0U)
23531 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
23532 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
23533
23534 /******************* Bit definition for TIM_CCR5 register *******************/
23535 #define TIM_CCR5_CCR5_Pos (0U)
23536 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
23537 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
23538 #define TIM_CCR5_GC5C1_Pos (29U)
23539 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
23540 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
23541 #define TIM_CCR5_GC5C2_Pos (30U)
23542 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
23543 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
23544 #define TIM_CCR5_GC5C3_Pos (31U)
23545 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
23546 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
23547
23548 /******************* Bit definition for TIM_CCR6 register *******************/
23549 #define TIM_CCR6_CCR6_Pos (0U)
23550 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
23551 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
23552
23553 /******************* Bit definition for TIM_BDTR register *******************/
23554 #define TIM_BDTR_DTG_Pos (0U)
23555 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
23556 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
23557 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
23558 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
23559 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
23560 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
23561 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
23562 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
23563 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
23564 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
23565
23566 #define TIM_BDTR_LOCK_Pos (8U)
23567 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
23568 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
23569 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
23570 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
23571
23572 #define TIM_BDTR_OSSI_Pos (10U)
23573 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
23574 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
23575 #define TIM_BDTR_OSSR_Pos (11U)
23576 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
23577 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
23578 #define TIM_BDTR_BKE_Pos (12U)
23579 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
23580 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
23581 #define TIM_BDTR_BKP_Pos (13U)
23582 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
23583 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
23584 #define TIM_BDTR_AOE_Pos (14U)
23585 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
23586 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
23587 #define TIM_BDTR_MOE_Pos (15U)
23588 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
23589 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
23590
23591 #define TIM_BDTR_BKF_Pos (16U)
23592 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
23593 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
23594 #define TIM_BDTR_BK2F_Pos (20U)
23595 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
23596 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
23597
23598 #define TIM_BDTR_BK2E_Pos (24U)
23599 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
23600 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
23601 #define TIM_BDTR_BK2P_Pos (25U)
23602 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
23603 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
23604
23605 /******************* Bit definition for TIM_DCR register ********************/
23606 #define TIM_DCR_DBA_Pos (0U)
23607 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
23608 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
23609 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
23610 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
23611 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
23612 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
23613 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
23614
23615 #define TIM_DCR_DBL_Pos (8U)
23616 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
23617 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
23618 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
23619 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
23620 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
23621 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
23622 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
23623
23624 /******************* Bit definition for TIM_DMAR register *******************/
23625 #define TIM_DMAR_DMAB_Pos (0U)
23626 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
23627 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
23628
23629 /****************** Bit definition for TIM_CCMR3 register *******************/
23630 #define TIM_CCMR3_OC5FE_Pos (2U)
23631 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
23632 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
23633 #define TIM_CCMR3_OC5PE_Pos (3U)
23634 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
23635 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
23636
23637 #define TIM_CCMR3_OC5M_Pos (4U)
23638 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
23639 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
23640 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
23641 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
23642 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
23643 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
23644
23645 #define TIM_CCMR3_OC5CE_Pos (7U)
23646 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
23647 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
23648
23649 #define TIM_CCMR3_OC6FE_Pos (10U)
23650 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
23651 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
23652 #define TIM_CCMR3_OC6PE_Pos (11U)
23653 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
23654 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
23655
23656 #define TIM_CCMR3_OC6M_Pos (12U)
23657 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
23658 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
23659 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
23660 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
23661 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
23662 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
23663
23664 #define TIM_CCMR3_OC6CE_Pos (15U)
23665 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
23666 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
23667 /******************* Bit definition for TIM1_AF1 register *********************/
23668 #define TIM1_AF1_BKINE_Pos (0U)
23669 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
23670 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
23671 #define TIM1_AF1_BKCMP1E_Pos (1U)
23672 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
23673 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
23674 #define TIM1_AF1_BKCMP2E_Pos (2U)
23675 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
23676 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
23677 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
23678 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
23679 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
23680 #define TIM1_AF1_BKINP_Pos (9U)
23681 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
23682 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
23683 #define TIM1_AF1_BKCMP1P_Pos (10U)
23684 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
23685 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
23686 #define TIM1_AF1_BKCMP2P_Pos (11U)
23687 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
23688 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
23689
23690 #define TIM1_AF1_ETRSEL_Pos (14U)
23691 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
23692 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
23693 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
23694 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
23695 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
23696 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
23697
23698 /******************* Bit definition for TIM1_AF2 register *********************/
23699 #define TIM1_AF2_BK2INE_Pos (0U)
23700 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
23701 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
23702 #define TIM1_AF2_BK2CMP1E_Pos (1U)
23703 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
23704 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
23705 #define TIM1_AF2_BK2CMP2E_Pos (2U)
23706 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
23707 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
23708 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
23709 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
23710 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
23711 #define TIM1_AF2_BK2INP_Pos (9U)
23712 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
23713 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
23714 #define TIM1_AF2_BK2CMP1P_Pos (10U)
23715 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
23716 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
23717 #define TIM1_AF2_BK2CMP2P_Pos (11U)
23718 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
23719 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
23720
23721 /******************* Bit definition for TIM_TISEL register *********************/
23722 #define TIM_TISEL_TI1SEL_Pos (0U)
23723 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
23724 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
23725 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
23726 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
23727 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
23728 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
23729
23730 #define TIM_TISEL_TI2SEL_Pos (8U)
23731 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
23732 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
23733 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
23734 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
23735 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
23736 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
23737
23738 #define TIM_TISEL_TI3SEL_Pos (16U)
23739 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
23740 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
23741 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
23742 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
23743 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
23744 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
23745
23746 #define TIM_TISEL_TI4SEL_Pos (24U)
23747 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
23748 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
23749 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
23750 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
23751 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
23752 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
23753
23754 /******************* Bit definition for TIM8_AF1 register *********************/
23755 #define TIM8_AF1_BKINE_Pos (0U)
23756 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
23757 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
23758 #define TIM8_AF1_BKCMP1E_Pos (1U)
23759 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
23760 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
23761 #define TIM8_AF1_BKCMP2E_Pos (2U)
23762 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
23763 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
23764 #define TIM8_AF1_BKDFBK2E_Pos (8U)
23765 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
23766 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
23767 #define TIM8_AF1_BKINP_Pos (9U)
23768 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
23769 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
23770 #define TIM8_AF1_BKCMP1P_Pos (10U)
23771 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
23772 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
23773 #define TIM8_AF1_BKCMP2P_Pos (11U)
23774 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
23775 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
23776
23777 #define TIM8_AF1_ETRSEL_Pos (14U)
23778 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
23779 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
23780 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
23781 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
23782 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
23783 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
23784 /******************* Bit definition for TIM8_AF2 register *********************/
23785 #define TIM8_AF2_BK2INE_Pos (0U)
23786 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
23787 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
23788 #define TIM8_AF2_BK2CMP1E_Pos (1U)
23789 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
23790 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
23791 #define TIM8_AF2_BK2CMP2E_Pos (2U)
23792 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
23793 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
23794 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
23795 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
23796 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
23797 #define TIM8_AF2_BK2INP_Pos (9U)
23798 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
23799 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
23800 #define TIM8_AF2_BK2CMP1P_Pos (10U)
23801 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
23802 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
23803 #define TIM8_AF2_BK2CMP2P_Pos (11U)
23804 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
23805 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
23806
23807 /******************* Bit definition for TIM2_AF1 register *********************/
23808 #define TIM2_AF1_ETRSEL_Pos (14U)
23809 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
23810 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
23811 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
23812 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
23813 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
23814 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
23815
23816 /******************* Bit definition for TIM3_AF1 register *********************/
23817 #define TIM3_AF1_ETRSEL_Pos (14U)
23818 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
23819 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
23820 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
23821 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
23822 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
23823 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
23824
23825 /******************* Bit definition for TIM5_AF1 register *********************/
23826 #define TIM5_AF1_ETRSEL_Pos (14U)
23827 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
23828 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
23829 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
23830 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
23831 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
23832 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
23833
23834 /******************* Bit definition for TIM15_AF1 register *********************/
23835 #define TIM15_AF1_BKINE_Pos (0U)
23836 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
23837 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
23838 #define TIM15_AF1_BKCMP1E_Pos (1U)
23839 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
23840 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
23841 #define TIM15_AF1_BKCMP2E_Pos (2U)
23842 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
23843 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
23844 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
23845 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
23846 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
23847 #define TIM15_AF1_BKINP_Pos (9U)
23848 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
23849 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
23850 #define TIM15_AF1_BKCMP1P_Pos (10U)
23851 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
23852 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
23853 #define TIM15_AF1_BKCMP2P_Pos (11U)
23854 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
23855 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
23856
23857 /******************* Bit definition for TIM16_ register *********************/
23858 #define TIM16_AF1_BKINE_Pos (0U)
23859 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
23860 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
23861 #define TIM16_AF1_BKCMP1E_Pos (1U)
23862 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
23863 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
23864 #define TIM16_AF1_BKCMP2E_Pos (2U)
23865 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
23866 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
23867 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
23868 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
23869 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
23870 #define TIM16_AF1_BKINP_Pos (9U)
23871 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
23872 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
23873 #define TIM16_AF1_BKCMP1P_Pos (10U)
23874 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
23875 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
23876 #define TIM16_AF1_BKCMP2P_Pos (11U)
23877 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
23878 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
23879
23880 /******************* Bit definition for TIM17_AF1 register *********************/
23881 #define TIM17_AF1_BKINE_Pos (0U)
23882 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
23883 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
23884 #define TIM17_AF1_BKCMP1E_Pos (1U)
23885 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
23886 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
23887 #define TIM17_AF1_BKCMP2E_Pos (2U)
23888 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
23889 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
23890 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
23891 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
23892 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
23893 #define TIM17_AF1_BKINP_Pos (9U)
23894 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
23895 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
23896 #define TIM17_AF1_BKCMP1P_Pos (10U)
23897 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
23898 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
23899 #define TIM17_AF1_BKCMP2P_Pos (11U)
23900 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
23901 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
23902
23903 /******************************************************************************/
23904 /* */
23905 /* Low Power Timer (LPTTIM) */
23906 /* */
23907 /******************************************************************************/
23908 /****************** Bit definition for LPTIM_ISR register *******************/
23909 #define LPTIM_ISR_CMPM_Pos (0U)
23910 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
23911 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
23912 #define LPTIM_ISR_ARRM_Pos (1U)
23913 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
23914 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
23915 #define LPTIM_ISR_EXTTRIG_Pos (2U)
23916 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
23917 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
23918 #define LPTIM_ISR_CMPOK_Pos (3U)
23919 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
23920 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
23921 #define LPTIM_ISR_ARROK_Pos (4U)
23922 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
23923 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
23924 #define LPTIM_ISR_UP_Pos (5U)
23925 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
23926 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
23927 #define LPTIM_ISR_DOWN_Pos (6U)
23928 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
23929 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
23930
23931 /****************** Bit definition for LPTIM_ICR register *******************/
23932 #define LPTIM_ICR_CMPMCF_Pos (0U)
23933 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
23934 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
23935 #define LPTIM_ICR_ARRMCF_Pos (1U)
23936 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
23937 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
23938 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
23939 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
23940 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
23941 #define LPTIM_ICR_CMPOKCF_Pos (3U)
23942 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
23943 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
23944 #define LPTIM_ICR_ARROKCF_Pos (4U)
23945 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
23946 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
23947 #define LPTIM_ICR_UPCF_Pos (5U)
23948 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
23949 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
23950 #define LPTIM_ICR_DOWNCF_Pos (6U)
23951 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
23952 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
23953
23954 /****************** Bit definition for LPTIM_IER register ********************/
23955 #define LPTIM_IER_CMPMIE_Pos (0U)
23956 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
23957 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
23958 #define LPTIM_IER_ARRMIE_Pos (1U)
23959 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
23960 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
23961 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
23962 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
23963 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
23964 #define LPTIM_IER_CMPOKIE_Pos (3U)
23965 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
23966 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
23967 #define LPTIM_IER_ARROKIE_Pos (4U)
23968 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
23969 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
23970 #define LPTIM_IER_UPIE_Pos (5U)
23971 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
23972 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
23973 #define LPTIM_IER_DOWNIE_Pos (6U)
23974 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
23975 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
23976
23977 /****************** Bit definition for LPTIM_CFGR register *******************/
23978 #define LPTIM_CFGR_CKSEL_Pos (0U)
23979 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
23980 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
23981
23982 #define LPTIM_CFGR_CKPOL_Pos (1U)
23983 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
23984 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
23985 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
23986 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
23987
23988 #define LPTIM_CFGR_CKFLT_Pos (3U)
23989 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
23990 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
23991 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
23992 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
23993
23994 #define LPTIM_CFGR_TRGFLT_Pos (6U)
23995 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
23996 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
23997 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
23998 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
23999
24000 #define LPTIM_CFGR_PRESC_Pos (9U)
24001 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
24002 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
24003 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
24004 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
24005 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
24006
24007 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
24008 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
24009 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
24010 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
24011 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
24012 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
24013
24014 #define LPTIM_CFGR_TRIGEN_Pos (17U)
24015 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
24016 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
24017 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
24018 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
24019
24020 #define LPTIM_CFGR_TIMOUT_Pos (19U)
24021 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
24022 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
24023 #define LPTIM_CFGR_WAVE_Pos (20U)
24024 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
24025 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
24026 #define LPTIM_CFGR_WAVPOL_Pos (21U)
24027 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
24028 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
24029 #define LPTIM_CFGR_PRELOAD_Pos (22U)
24030 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
24031 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
24032 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
24033 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
24034 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
24035 #define LPTIM_CFGR_ENC_Pos (24U)
24036 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
24037 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
24038
24039 /****************** Bit definition for LPTIM_CR register ********************/
24040 #define LPTIM_CR_ENABLE_Pos (0U)
24041 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
24042 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
24043 #define LPTIM_CR_SNGSTRT_Pos (1U)
24044 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
24045 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
24046 #define LPTIM_CR_CNTSTRT_Pos (2U)
24047 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
24048 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
24049 #define LPTIM_CR_COUNTRST_Pos (3U)
24050 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
24051 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
24052 #define LPTIM_CR_RSTARE_Pos (4U)
24053 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
24054 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
24055
24056
24057 /****************** Bit definition for LPTIM_CMP register *******************/
24058 #define LPTIM_CMP_CMP_Pos (0U)
24059 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
24060 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
24061
24062 /****************** Bit definition for LPTIM_ARR register *******************/
24063 #define LPTIM_ARR_ARR_Pos (0U)
24064 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
24065 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
24066
24067 /****************** Bit definition for LPTIM_CNT register *******************/
24068 #define LPTIM_CNT_CNT_Pos (0U)
24069 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
24070 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
24071
24072 /****************** Bit definition for LPTIM_CFGR2 register *****************/
24073 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
24074 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
24075 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
24076 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
24077 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
24078 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
24079 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
24080 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
24081 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
24082 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
24083
24084 /******************************************************************************/
24085 /* */
24086 /* Analog Comparators (COMP) */
24087 /* */
24088 /******************************************************************************/
24089
24090 /******************* Bit definition for COMP_SR register ********************/
24091 #define COMP_SR_C1VAL_Pos (0U)
24092 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
24093 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
24094 #define COMP_SR_C2VAL_Pos (1U)
24095 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
24096 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
24097 #define COMP_SR_C1IF_Pos (16U)
24098 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
24099 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
24100 #define COMP_SR_C2IF_Pos (17U)
24101 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
24102 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
24103 /******************* Bit definition for COMP_ICFR register ********************/
24104 #define COMP_ICFR_C1IF_Pos (16U)
24105 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
24106 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
24107 #define COMP_ICFR_C2IF_Pos (17U)
24108 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
24109 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
24110 /******************* Bit definition for COMP_OR register ********************/
24111 #define COMP_OR_AFOPA6_Pos (0U)
24112 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
24113 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
24114 #define COMP_OR_AFOPA8_Pos (1U)
24115 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
24116 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
24117 #define COMP_OR_AFOPB12_Pos (2U)
24118 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
24119 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
24120 #define COMP_OR_AFOPE6_Pos (3U)
24121 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
24122 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
24123 #define COMP_OR_AFOPE15_Pos (4U)
24124 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
24125 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
24126 #define COMP_OR_AFOPG2_Pos (5U)
24127 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
24128 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
24129 #define COMP_OR_AFOPG3_Pos (6U)
24130 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
24131 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
24132 #define COMP_OR_AFOPG4_Pos (7U)
24133 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
24134 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
24135 #define COMP_OR_AFOPI1_Pos (8U)
24136 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
24137 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
24138 #define COMP_OR_AFOPI4_Pos (9U)
24139 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
24140 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
24141 #define COMP_OR_AFOPK2_Pos (10U)
24142 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
24143 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
24144
24145 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
24146 #define COMP_CFGRx_EN_Pos (0U)
24147 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
24148 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
24149 #define COMP_CFGRx_BRGEN_Pos (1U)
24150 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
24151 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
24152 #define COMP_CFGRx_SCALEN_Pos (2U)
24153 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
24154 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
24155 #define COMP_CFGRx_POLARITY_Pos (3U)
24156 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
24157 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
24158 #define COMP_CFGRx_WINMODE_Pos (4U)
24159 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
24160 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
24161 #define COMP_CFGRx_ITEN_Pos (6U)
24162 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
24163 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
24164 #define COMP_CFGRx_HYST_Pos (8U)
24165 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
24166 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
24167 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
24168 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
24169 #define COMP_CFGRx_PWRMODE_Pos (12U)
24170 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
24171 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
24172 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
24173 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
24174 #define COMP_CFGRx_INMSEL_Pos (16U)
24175 #define COMP_CFGRx_INMSEL_Msk (0x7UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00070000 */
24176 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
24177 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
24178 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
24179 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
24180 #define COMP_CFGRx_INPSEL_Pos (20U)
24181 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
24182 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
24183 #define COMP_CFGRx_BLANKING_Pos (24U)
24184 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
24185 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
24186 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
24187 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
24188 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
24189 #define COMP_CFGRx_LOCK_Pos (31U)
24190 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
24191 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
24192
24193
24194 /******************************************************************************/
24195 /* */
24196 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
24197 /* */
24198 /******************************************************************************/
24199 /****************** Bit definition for USART_CR1 register *******************/
24200 #define USART_CR1_UE_Pos (0U)
24201 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
24202 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
24203 #define USART_CR1_UESM_Pos (1U)
24204 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
24205 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
24206 #define USART_CR1_RE_Pos (2U)
24207 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
24208 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
24209 #define USART_CR1_TE_Pos (3U)
24210 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
24211 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
24212 #define USART_CR1_IDLEIE_Pos (4U)
24213 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
24214 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
24215 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
24216 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
24217 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
24218 #define USART_CR1_TCIE_Pos (6U)
24219 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
24220 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
24221 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
24222 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
24223 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
24224 #define USART_CR1_PEIE_Pos (8U)
24225 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
24226 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
24227 #define USART_CR1_PS_Pos (9U)
24228 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
24229 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
24230 #define USART_CR1_PCE_Pos (10U)
24231 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
24232 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
24233 #define USART_CR1_WAKE_Pos (11U)
24234 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
24235 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
24236 #define USART_CR1_M_Pos (12U)
24237 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
24238 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
24239 #define USART_CR1_M0_Pos (12U)
24240 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
24241 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
24242 #define USART_CR1_MME_Pos (13U)
24243 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
24244 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
24245 #define USART_CR1_CMIE_Pos (14U)
24246 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
24247 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
24248 #define USART_CR1_OVER8_Pos (15U)
24249 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
24250 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
24251 #define USART_CR1_DEDT_Pos (16U)
24252 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
24253 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
24254 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
24255 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
24256 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
24257 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
24258 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
24259 #define USART_CR1_DEAT_Pos (21U)
24260 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
24261 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
24262 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
24263 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
24264 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
24265 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
24266 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
24267 #define USART_CR1_RTOIE_Pos (26U)
24268 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
24269 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
24270 #define USART_CR1_EOBIE_Pos (27U)
24271 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
24272 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
24273 #define USART_CR1_M1_Pos (28U)
24274 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
24275 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
24276 #define USART_CR1_FIFOEN_Pos (29U)
24277 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
24278 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
24279 #define USART_CR1_TXFEIE_Pos (30U)
24280 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
24281 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
24282 #define USART_CR1_RXFFIE_Pos (31U)
24283 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
24284 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
24285
24286 /* Legacy define */
24287 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
24288 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
24289
24290 /****************** Bit definition for USART_CR2 register *******************/
24291 #define USART_CR2_SLVEN_Pos (0U)
24292 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
24293 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
24294 #define USART_CR2_DIS_NSS_Pos (3U)
24295 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
24296 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
24297 #define USART_CR2_ADDM7_Pos (4U)
24298 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
24299 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
24300 #define USART_CR2_LBDL_Pos (5U)
24301 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
24302 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
24303 #define USART_CR2_LBDIE_Pos (6U)
24304 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
24305 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
24306 #define USART_CR2_LBCL_Pos (8U)
24307 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
24308 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
24309 #define USART_CR2_CPHA_Pos (9U)
24310 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
24311 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
24312 #define USART_CR2_CPOL_Pos (10U)
24313 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
24314 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
24315 #define USART_CR2_CLKEN_Pos (11U)
24316 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
24317 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
24318 #define USART_CR2_STOP_Pos (12U)
24319 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
24320 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
24321 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
24322 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
24323 #define USART_CR2_LINEN_Pos (14U)
24324 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
24325 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
24326 #define USART_CR2_SWAP_Pos (15U)
24327 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
24328 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
24329 #define USART_CR2_RXINV_Pos (16U)
24330 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
24331 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
24332 #define USART_CR2_TXINV_Pos (17U)
24333 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
24334 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
24335 #define USART_CR2_DATAINV_Pos (18U)
24336 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
24337 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
24338 #define USART_CR2_MSBFIRST_Pos (19U)
24339 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
24340 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
24341 #define USART_CR2_ABREN_Pos (20U)
24342 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
24343 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
24344 #define USART_CR2_ABRMODE_Pos (21U)
24345 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
24346 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
24347 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
24348 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
24349 #define USART_CR2_RTOEN_Pos (23U)
24350 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
24351 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
24352 #define USART_CR2_ADD_Pos (24U)
24353 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
24354 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
24355
24356 /****************** Bit definition for USART_CR3 register *******************/
24357 #define USART_CR3_EIE_Pos (0U)
24358 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
24359 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
24360 #define USART_CR3_IREN_Pos (1U)
24361 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
24362 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
24363 #define USART_CR3_IRLP_Pos (2U)
24364 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
24365 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
24366 #define USART_CR3_HDSEL_Pos (3U)
24367 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
24368 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
24369 #define USART_CR3_NACK_Pos (4U)
24370 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
24371 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
24372 #define USART_CR3_SCEN_Pos (5U)
24373 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
24374 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
24375 #define USART_CR3_DMAR_Pos (6U)
24376 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
24377 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
24378 #define USART_CR3_DMAT_Pos (7U)
24379 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
24380 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
24381 #define USART_CR3_RTSE_Pos (8U)
24382 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
24383 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
24384 #define USART_CR3_CTSE_Pos (9U)
24385 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
24386 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
24387 #define USART_CR3_CTSIE_Pos (10U)
24388 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
24389 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
24390 #define USART_CR3_ONEBIT_Pos (11U)
24391 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
24392 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
24393 #define USART_CR3_OVRDIS_Pos (12U)
24394 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
24395 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
24396 #define USART_CR3_DDRE_Pos (13U)
24397 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
24398 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
24399 #define USART_CR3_DEM_Pos (14U)
24400 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
24401 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
24402 #define USART_CR3_DEP_Pos (15U)
24403 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
24404 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
24405 #define USART_CR3_SCARCNT_Pos (17U)
24406 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
24407 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
24408 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
24409 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
24410 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
24411 #define USART_CR3_WUS_Pos (20U)
24412 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
24413 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
24414 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
24415 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
24416 #define USART_CR3_WUFIE_Pos (22U)
24417 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
24418 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
24419 #define USART_CR3_TXFTIE_Pos (23U)
24420 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
24421 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
24422 #define USART_CR3_TCBGTIE_Pos (24U)
24423 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
24424 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
24425 #define USART_CR3_RXFTCFG_Pos (25U)
24426 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
24427 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
24428 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
24429 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
24430 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
24431 #define USART_CR3_RXFTIE_Pos (28U)
24432 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
24433 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
24434 #define USART_CR3_TXFTCFG_Pos (29U)
24435 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
24436 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
24437 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
24438 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
24439 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
24440
24441 /****************** Bit definition for USART_BRR register *******************/
24442 #define USART_BRR_DIV_FRACTION_Pos (0U)
24443 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
24444 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
24445 #define USART_BRR_DIV_MANTISSA_Pos (4U)
24446 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
24447 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
24448
24449 /****************** Bit definition for USART_GTPR register ******************/
24450 #define USART_GTPR_PSC_Pos (0U)
24451 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
24452 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
24453 #define USART_GTPR_GT_Pos (8U)
24454 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
24455 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
24456
24457 /******************* Bit definition for USART_RTOR register *****************/
24458 #define USART_RTOR_RTO_Pos (0U)
24459 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
24460 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
24461 #define USART_RTOR_BLEN_Pos (24U)
24462 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
24463 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
24464
24465 /******************* Bit definition for USART_RQR register ******************/
24466 #define USART_RQR_ABRRQ_Pos (0U)
24467 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
24468 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
24469 #define USART_RQR_SBKRQ_Pos (1U)
24470 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
24471 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
24472 #define USART_RQR_MMRQ_Pos (2U)
24473 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
24474 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
24475 #define USART_RQR_RXFRQ_Pos (3U)
24476 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
24477 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
24478 #define USART_RQR_TXFRQ_Pos (4U)
24479 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
24480 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
24481
24482 /******************* Bit definition for USART_ISR register ******************/
24483 #define USART_ISR_PE_Pos (0U)
24484 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
24485 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
24486 #define USART_ISR_FE_Pos (1U)
24487 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
24488 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
24489 #define USART_ISR_NE_Pos (2U)
24490 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
24491 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
24492 #define USART_ISR_ORE_Pos (3U)
24493 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
24494 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
24495 #define USART_ISR_IDLE_Pos (4U)
24496 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
24497 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
24498 #define USART_ISR_RXNE_RXFNE_Pos (5U)
24499 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
24500 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
24501 #define USART_ISR_TC_Pos (6U)
24502 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
24503 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
24504 #define USART_ISR_TXE_TXFNF_Pos (7U)
24505 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
24506 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
24507 #define USART_ISR_LBDF_Pos (8U)
24508 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
24509 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
24510 #define USART_ISR_CTSIF_Pos (9U)
24511 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
24512 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
24513 #define USART_ISR_CTS_Pos (10U)
24514 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
24515 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
24516 #define USART_ISR_RTOF_Pos (11U)
24517 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
24518 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
24519 #define USART_ISR_EOBF_Pos (12U)
24520 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
24521 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
24522 #define USART_ISR_UDR_Pos (13U)
24523 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
24524 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
24525 #define USART_ISR_ABRE_Pos (14U)
24526 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
24527 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
24528 #define USART_ISR_ABRF_Pos (15U)
24529 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
24530 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
24531 #define USART_ISR_BUSY_Pos (16U)
24532 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
24533 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
24534 #define USART_ISR_CMF_Pos (17U)
24535 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
24536 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
24537 #define USART_ISR_SBKF_Pos (18U)
24538 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
24539 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
24540 #define USART_ISR_RWU_Pos (19U)
24541 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
24542 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
24543 #define USART_ISR_WUF_Pos (20U)
24544 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
24545 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
24546 #define USART_ISR_TEACK_Pos (21U)
24547 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
24548 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
24549 #define USART_ISR_REACK_Pos (22U)
24550 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
24551 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
24552 #define USART_ISR_TXFE_Pos (23U)
24553 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
24554 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
24555 #define USART_ISR_RXFF_Pos (24U)
24556 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
24557 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
24558 #define USART_ISR_TCBGT_Pos (25U)
24559 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
24560 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
24561 #define USART_ISR_RXFT_Pos (26U)
24562 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
24563 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
24564 #define USART_ISR_TXFT_Pos (27U)
24565 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
24566 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
24567
24568 /******************* Bit definition for USART_ICR register ******************/
24569 #define USART_ICR_PECF_Pos (0U)
24570 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
24571 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
24572 #define USART_ICR_FECF_Pos (1U)
24573 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
24574 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
24575 #define USART_ICR_NECF_Pos (2U)
24576 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
24577 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
24578 #define USART_ICR_ORECF_Pos (3U)
24579 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
24580 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
24581 #define USART_ICR_IDLECF_Pos (4U)
24582 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
24583 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
24584 #define USART_ICR_TXFECF_Pos (5U)
24585 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
24586 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
24587 #define USART_ICR_TCCF_Pos (6U)
24588 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
24589 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
24590 #define USART_ICR_TCBGTCF_Pos (7U)
24591 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
24592 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
24593 #define USART_ICR_LBDCF_Pos (8U)
24594 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
24595 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
24596 #define USART_ICR_CTSCF_Pos (9U)
24597 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
24598 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
24599 #define USART_ICR_RTOCF_Pos (11U)
24600 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
24601 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
24602 #define USART_ICR_EOBCF_Pos (12U)
24603 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
24604 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
24605 #define USART_ICR_UDRCF_Pos (13U)
24606 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
24607 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
24608 #define USART_ICR_CMCF_Pos (17U)
24609 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
24610 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
24611 #define USART_ICR_WUCF_Pos (20U)
24612 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
24613 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
24614
24615 /******************* Bit definition for USART_RDR register ******************/
24616 #define USART_RDR_RDR_Pos (0U)
24617 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
24618 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
24619
24620 /******************* Bit definition for USART_TDR register ******************/
24621 #define USART_TDR_TDR_Pos (0U)
24622 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
24623 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
24624
24625 /******************* Bit definition for USART_PRESC register ******************/
24626 #define USART_PRESC_PRESCALER_Pos (0U)
24627 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
24628 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
24629 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
24630 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
24631 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
24632 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
24633
24634 /******************************************************************************/
24635 /* */
24636 /* Single Wire Protocol Master Interface (SWPMI) */
24637 /* */
24638 /******************************************************************************/
24639
24640 /******************* Bit definition for SWPMI_CR register ********************/
24641 #define SWPMI_CR_RXDMA_Pos (0U)
24642 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
24643 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
24644 #define SWPMI_CR_TXDMA_Pos (1U)
24645 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
24646 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
24647 #define SWPMI_CR_RXMODE_Pos (2U)
24648 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
24649 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
24650 #define SWPMI_CR_TXMODE_Pos (3U)
24651 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
24652 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
24653 #define SWPMI_CR_LPBK_Pos (4U)
24654 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
24655 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
24656 #define SWPMI_CR_SWPACT_Pos (5U)
24657 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
24658 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
24659 #define SWPMI_CR_DEACT_Pos (10U)
24660 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
24661 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
24662 #define SWPMI_CR_SWPEN_Pos (11U)
24663 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
24664 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
24665
24666 /******************* Bit definition for SWPMI_BRR register ********************/
24667 #define SWPMI_BRR_BR_Pos (0U)
24668 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
24669 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
24670
24671 /******************* Bit definition for SWPMI_ISR register ********************/
24672 #define SWPMI_ISR_RXBFF_Pos (0U)
24673 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
24674 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
24675 #define SWPMI_ISR_TXBEF_Pos (1U)
24676 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
24677 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
24678 #define SWPMI_ISR_RXBERF_Pos (2U)
24679 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
24680 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
24681 #define SWPMI_ISR_RXOVRF_Pos (3U)
24682 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
24683 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
24684 #define SWPMI_ISR_TXUNRF_Pos (4U)
24685 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
24686 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
24687 #define SWPMI_ISR_RXNE_Pos (5U)
24688 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
24689 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
24690 #define SWPMI_ISR_TXE_Pos (6U)
24691 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
24692 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
24693 #define SWPMI_ISR_TCF_Pos (7U)
24694 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
24695 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
24696 #define SWPMI_ISR_SRF_Pos (8U)
24697 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
24698 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
24699 #define SWPMI_ISR_SUSP_Pos (9U)
24700 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
24701 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
24702 #define SWPMI_ISR_DEACTF_Pos (10U)
24703 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
24704 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
24705 #define SWPMI_ISR_RDYF_Pos (11U)
24706 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
24707 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
24708
24709 /******************* Bit definition for SWPMI_ICR register ********************/
24710 #define SWPMI_ICR_CRXBFF_Pos (0U)
24711 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
24712 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
24713 #define SWPMI_ICR_CTXBEF_Pos (1U)
24714 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
24715 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
24716 #define SWPMI_ICR_CRXBERF_Pos (2U)
24717 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
24718 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
24719 #define SWPMI_ICR_CRXOVRF_Pos (3U)
24720 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
24721 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
24722 #define SWPMI_ICR_CTXUNRF_Pos (4U)
24723 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
24724 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
24725 #define SWPMI_ICR_CTCF_Pos (7U)
24726 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
24727 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
24728 #define SWPMI_ICR_CSRF_Pos (8U)
24729 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
24730 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
24731 #define SWPMI_ICR_CRDYF_Pos (11U)
24732 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
24733 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
24734
24735 /******************* Bit definition for SWPMI_IER register ********************/
24736 #define SWPMI_IER_RXBFIE_Pos (0U)
24737 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
24738 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
24739 #define SWPMI_IER_TXBEIE_Pos (1U)
24740 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
24741 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
24742 #define SWPMI_IER_RXBERIE_Pos (2U)
24743 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
24744 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
24745 #define SWPMI_IER_RXOVRIE_Pos (3U)
24746 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
24747 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
24748 #define SWPMI_IER_TXUNRIE_Pos (4U)
24749 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
24750 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
24751 #define SWPMI_IER_RIE_Pos (5U)
24752 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
24753 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
24754 #define SWPMI_IER_TIE_Pos (6U)
24755 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
24756 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
24757 #define SWPMI_IER_TCIE_Pos (7U)
24758 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
24759 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
24760 #define SWPMI_IER_SRIE_Pos (8U)
24761 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
24762 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
24763 #define SWPMI_IER_RDYIE_Pos (11U)
24764 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
24765 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
24766
24767 /******************* Bit definition for SWPMI_RFL register ********************/
24768 #define SWPMI_RFL_RFL_Pos (0U)
24769 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
24770 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
24771 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
24772
24773 /******************* Bit definition for SWPMI_TDR register ********************/
24774 #define SWPMI_TDR_TD_Pos (0U)
24775 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
24776 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
24777
24778 /******************* Bit definition for SWPMI_RDR register ********************/
24779 #define SWPMI_RDR_RD_Pos (0U)
24780 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
24781 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
24782
24783
24784 /******************* Bit definition for SWPMI_OR register ********************/
24785 #define SWPMI_OR_TBYP_Pos (0U)
24786 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
24787 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
24788 #define SWPMI_OR_CLASS_Pos (1U)
24789 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
24790 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
24791
24792 /******************************************************************************/
24793 /* */
24794 /* Window WATCHDOG */
24795 /* */
24796 /******************************************************************************/
24797 /******************* Bit definition for WWDG_CR register ********************/
24798 #define WWDG_CR_T_Pos (0U)
24799 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
24800 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
24801 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
24802 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
24803 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
24804 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
24805 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
24806 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
24807 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
24808
24809 #define WWDG_CR_WDGA_Pos (7U)
24810 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
24811 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
24812
24813 /******************* Bit definition for WWDG_CFR register *******************/
24814 #define WWDG_CFR_W_Pos (0U)
24815 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
24816 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
24817 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
24818 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
24819 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
24820 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
24821 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
24822 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
24823 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
24824
24825 #define WWDG_CFR_EWI_Pos (9U)
24826 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
24827 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
24828
24829 #define WWDG_CFR_WDGTB_Pos (11U)
24830 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
24831 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
24832 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
24833 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
24834 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
24835
24836 /******************* Bit definition for WWDG_SR register ********************/
24837 #define WWDG_SR_EWIF_Pos (0U)
24838 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
24839 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
24840
24841
24842 /******************************************************************************/
24843 /* */
24844 /* DBG */
24845 /* */
24846 /******************************************************************************/
24847
24848 /******************** Bit definition for DBGMCU_IDCODE register *************/
24849 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
24850 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
24851 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
24852 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
24853 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
24854 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
24855
24856 /******************** Bit definition for DBGMCU_CR register *****************/
24857 #define DBGMCU_CR_DBG_SLEEPD1_Pos (0U)
24858 #define DBGMCU_CR_DBG_SLEEPD1_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD1_Pos) /*!< 0x00000001 */
24859 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPD1_Msk
24860 #define DBGMCU_CR_DBG_STOPD1_Pos (1U)
24861 #define DBGMCU_CR_DBG_STOPD1_Msk (0x1UL << DBGMCU_CR_DBG_STOPD1_Pos) /*!< 0x00000002 */
24862 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPD1_Msk
24863 #define DBGMCU_CR_DBG_STANDBYD1_Pos (2U)
24864 #define DBGMCU_CR_DBG_STANDBYD1_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD1_Pos) /*!< 0x00000004 */
24865 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYD1_Msk
24866 #define DBGMCU_CR_DBG_SLEEPD2_Pos (3U)
24867 #define DBGMCU_CR_DBG_SLEEPD2_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPD2_Pos) /*!< 0x00000008 */
24868 #define DBGMCU_CR_DBG_SLEEPD2 DBGMCU_CR_DBG_SLEEPD2_Msk
24869 #define DBGMCU_CR_DBG_STOPD2_Pos (4U)
24870 #define DBGMCU_CR_DBG_STOPD2_Msk (0x1UL << DBGMCU_CR_DBG_STOPD2_Pos) /*!< 0x00000010 */
24871 #define DBGMCU_CR_DBG_STOPD2 DBGMCU_CR_DBG_STOPD2_Msk
24872 #define DBGMCU_CR_DBG_STANDBYD2_Pos (5U)
24873 #define DBGMCU_CR_DBG_STANDBYD2_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD2_Pos) /*!< 0x00000020 */
24874 #define DBGMCU_CR_DBG_STANDBYD2 DBGMCU_CR_DBG_STANDBYD2_Msk
24875 #define DBGMCU_CR_DBG_STOPD3_Pos (7U)
24876 #define DBGMCU_CR_DBG_STOPD3_Msk (0x1UL << DBGMCU_CR_DBG_STOPD3_Pos) /*!< 0x00000080 */
24877 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPD3_Msk
24878 #define DBGMCU_CR_DBG_STANDBYD3_Pos (8U)
24879 #define DBGMCU_CR_DBG_STANDBYD3_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYD3_Pos) /*!< 0x00000100 */
24880 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYD3_Msk
24881 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
24882 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
24883 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
24884 #define DBGMCU_CR_DBG_CKD1EN_Pos (21U)
24885 #define DBGMCU_CR_DBG_CKD1EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD1EN_Pos) /*!< 0x00200000 */
24886 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKD1EN_Msk
24887 #define DBGMCU_CR_DBG_CKD3EN_Pos (22U)
24888 #define DBGMCU_CR_DBG_CKD3EN_Msk (0x1UL << DBGMCU_CR_DBG_CKD3EN_Pos) /*!< 0x00400000 */
24889 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKD3EN_Msk
24890 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
24891 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
24892 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
24893
24894 /******************** Bit definition for APB3FZ1 register ************/
24895 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
24896 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
24897 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
24898 /******************** Bit definition for APB3FZ2 register ************/
24899 #define DBGMCU_APB3FZ2_DBG_WWDG1_Pos (6U)
24900 #define DBGMCU_APB3FZ2_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ2_DBG_WWDG1_Pos) /*!< 0x00000040 */
24901 #define DBGMCU_APB3FZ2_DBG_WWDG1 DBGMCU_APB3FZ2_DBG_WWDG1_Msk
24902 /******************** Bit definition for APB1LFZ1 register ************/
24903 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
24904 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
24905 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
24906 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
24907 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
24908 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
24909 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
24910 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
24911 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
24912 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
24913 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
24914 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
24915 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
24916 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
24917 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
24918 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
24919 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
24920 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
24921 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
24922 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
24923 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
24924 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
24925 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
24926 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
24927 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
24928 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
24929 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
24930 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
24931 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
24932 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
24933 #define DBGMCU_APB1LFZ1_DBG_WWDG2_Pos (11U)
24934 #define DBGMCU_APB1LFZ1_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_WWDG2_Pos) /*!< 0x00000800 */
24935 #define DBGMCU_APB1LFZ1_DBG_WWDG2 DBGMCU_APB1LFZ1_DBG_WWDG2_Msk
24936 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
24937 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
24938 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
24939 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
24940 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
24941 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
24942 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
24943 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
24944 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
24945
24946 /******************** Bit definition for APB1LFZ2 register ************/
24947 #define DBGMCU_APB1LFZ2_DBG_TIM2_Pos (0U)
24948 #define DBGMCU_APB1LFZ2_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM2_Pos) /*!< 0x00000001 */
24949 #define DBGMCU_APB1LFZ2_DBG_TIM2 DBGMCU_APB1LFZ2_DBG_TIM2_Msk
24950 #define DBGMCU_APB1LFZ2_DBG_TIM3_Pos (1U)
24951 #define DBGMCU_APB1LFZ2_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM3_Pos) /*!< 0x00000002 */
24952 #define DBGMCU_APB1LFZ2_DBG_TIM3 DBGMCU_APB1LFZ2_DBG_TIM3_Msk
24953 #define DBGMCU_APB1LFZ2_DBG_TIM4_Pos (2U)
24954 #define DBGMCU_APB1LFZ2_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM4_Pos) /*!< 0x00000004 */
24955 #define DBGMCU_APB1LFZ2_DBG_TIM4 DBGMCU_APB1LFZ2_DBG_TIM4_Msk
24956 #define DBGMCU_APB1LFZ2_DBG_TIM5_Pos (3U)
24957 #define DBGMCU_APB1LFZ2_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM5_Pos) /*!< 0x00000008 */
24958 #define DBGMCU_APB1LFZ2_DBG_TIM5 DBGMCU_APB1LFZ2_DBG_TIM5_Msk
24959 #define DBGMCU_APB1LFZ2_DBG_TIM6_Pos (4U)
24960 #define DBGMCU_APB1LFZ2_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM6_Pos) /*!< 0x00000010 */
24961 #define DBGMCU_APB1LFZ2_DBG_TIM6 DBGMCU_APB1LFZ2_DBG_TIM6_Msk
24962 #define DBGMCU_APB1LFZ2_DBG_TIM7_Pos (5U)
24963 #define DBGMCU_APB1LFZ2_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM7_Pos) /*!< 0x00000020 */
24964 #define DBGMCU_APB1LFZ2_DBG_TIM7 DBGMCU_APB1LFZ2_DBG_TIM7_Msk
24965 #define DBGMCU_APB1LFZ2_DBG_TIM12_Pos (6U)
24966 #define DBGMCU_APB1LFZ2_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM12_Pos) /*!< 0x00000040 */
24967 #define DBGMCU_APB1LFZ2_DBG_TIM12 DBGMCU_APB1LFZ2_DBG_TIM12_Msk
24968 #define DBGMCU_APB1LFZ2_DBG_TIM13_Pos (7U)
24969 #define DBGMCU_APB1LFZ2_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM13_Pos) /*!< 0x00000080 */
24970 #define DBGMCU_APB1LFZ2_DBG_TIM13 DBGMCU_APB1LFZ2_DBG_TIM13_Msk
24971 #define DBGMCU_APB1LFZ2_DBG_TIM14_Pos (8U)
24972 #define DBGMCU_APB1LFZ2_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_TIM14_Pos) /*!< 0x00000100 */
24973 #define DBGMCU_APB1LFZ2_DBG_TIM14 DBGMCU_APB1LFZ2_DBG_TIM14_Msk
24974 #define DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos (9U)
24975 #define DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_LPTIM1_Pos) /*!< 0x00000200 */
24976 #define DBGMCU_APB1LFZ2_DBG_LPTIM1 DBGMCU_APB1LFZ2_DBG_LPTIM1_Msk
24977 #define DBGMCU_APB1LFZ2_DBG_WWDG2_Pos (11U)
24978 #define DBGMCU_APB1LFZ2_DBG_WWDG2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_WWDG2_Pos) /*!< 0x00000800 */
24979 #define DBGMCU_APB1LFZ2_DBG_WWDG2 DBGMCU_APB1LFZ2_DBG_WWDG2_Msk
24980 #define DBGMCU_APB1LFZ2_DBG_I2C1_Pos (21U)
24981 #define DBGMCU_APB1LFZ2_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C1_Pos) /*!< 0x00200000 */
24982 #define DBGMCU_APB1LFZ2_DBG_I2C1 DBGMCU_APB1LFZ2_DBG_I2C1_Msk
24983 #define DBGMCU_APB1LFZ2_DBG_I2C2_Pos (22U)
24984 #define DBGMCU_APB1LFZ2_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C2_Pos) /*!< 0x00400000 */
24985 #define DBGMCU_APB1LFZ2_DBG_I2C2 DBGMCU_APB1LFZ2_DBG_I2C2_Msk
24986 #define DBGMCU_APB1LFZ2_DBG_I2C3_Pos (23U)
24987 #define DBGMCU_APB1LFZ2_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ2_DBG_I2C3_Pos) /*!< 0x00800000 */
24988 #define DBGMCU_APB1LFZ2_DBG_I2C3 DBGMCU_APB1LFZ2_DBG_I2C3_Msk
24989 /******************** Bit definition for APB1HFZ1 register ************/
24990 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Pos (8U)
24991 #define DBGMCU_APB1HFZ1_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ1_DBG_FDCAN_Pos) /*!< 0x00000100 */
24992 #define DBGMCU_APB1HFZ1_DBG_FDCAN DBGMCU_APB1HFZ1_DBG_FDCAN_Msk
24993 /******************** Bit definition for APB1HFZ2 register ************/
24994 #define DBGMCU_APB1HFZ2_DBG_FDCAN_Pos (8U)
24995 #define DBGMCU_APB1HFZ2_DBG_FDCAN_Msk (0x1UL << DBGMCU_APB1HFZ2_DBG_FDCAN_Pos) /*!< 0x00000100 */
24996 #define DBGMCU_APB1HFZ2_DBG_FDCAN DBGMCU_APB1HFZ2_DBG_FDCAN_Msk
24997
24998 /******************** Bit definition for APB2FZ1 register ************/
24999 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
25000 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
25001 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
25002 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
25003 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
25004 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
25005 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
25006 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
25007 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
25008 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
25009 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
25010 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
25011 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
25012 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
25013 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
25014 #define DBGMCU_APB2FZ1_DBG_HRTIM_Pos (29U)
25015 #define DBGMCU_APB2FZ1_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_HRTIM_Pos) /*!< 0x20000000 */
25016 #define DBGMCU_APB2FZ1_DBG_HRTIM DBGMCU_APB2FZ1_DBG_HRTIM_Msk
25017
25018 /******************** Bit definition for APB2FZ2 register ************/
25019 #define DBGMCU_APB2FZ2_DBG_TIM1_Pos (0U)
25020 #define DBGMCU_APB2FZ2_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM1_Pos) /*!< 0x00000001 */
25021 #define DBGMCU_APB2FZ2_DBG_TIM1 DBGMCU_APB2FZ2_DBG_TIM1_Msk
25022 #define DBGMCU_APB2FZ2_DBG_TIM8_Pos (1U)
25023 #define DBGMCU_APB2FZ2_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM8_Pos) /*!< 0x00000002 */
25024 #define DBGMCU_APB2FZ2_DBG_TIM8 DBGMCU_APB2FZ2_DBG_TIM8_Msk
25025 #define DBGMCU_APB2FZ2_DBG_TIM15_Pos (16U)
25026 #define DBGMCU_APB2FZ2_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM15_Pos) /*!< 0x00010000 */
25027 #define DBGMCU_APB2FZ2_DBG_TIM15 DBGMCU_APB2FZ2_DBG_TIM15_Msk
25028 #define DBGMCU_APB2FZ2_DBG_TIM16_Pos (17U)
25029 #define DBGMCU_APB2FZ2_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM16_Pos) /*!< 0x00020000 */
25030 #define DBGMCU_APB2FZ2_DBG_TIM16 DBGMCU_APB2FZ2_DBG_TIM16_Msk
25031 #define DBGMCU_APB2FZ2_DBG_TIM17_Pos (18U)
25032 #define DBGMCU_APB2FZ2_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_TIM17_Pos) /*!< 0x00040000 */
25033 #define DBGMCU_APB2FZ2_DBG_TIM17 DBGMCU_APB2FZ2_DBG_TIM17_Msk
25034 #define DBGMCU_APB2FZ2_DBG_HRTIM_Pos (29U)
25035 #define DBGMCU_APB2FZ2_DBG_HRTIM_Msk (0x1UL << DBGMCU_APB2FZ2_DBG_HRTIM_Pos) /*!< 0x20000000 */
25036 #define DBGMCU_APB2FZ2_DBG_HRTIM DBGMCU_APB2FZ2_DBG_HRTIM_Msk
25037 /******************** Bit definition for APB4FZ1 register ************/
25038 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
25039 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
25040 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
25041 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
25042 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
25043 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
25044 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
25045 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
25046 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
25047 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Pos (11U)
25048 #define DBGMCU_APB4FZ1_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM4_Pos) /*!< 0x00000800 */
25049 #define DBGMCU_APB4FZ1_DBG_LPTIM4 DBGMCU_APB4FZ1_DBG_LPTIM4_Msk
25050 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Pos (12U)
25051 #define DBGMCU_APB4FZ1_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM5_Pos) /*!< 0x00001000 */
25052 #define DBGMCU_APB4FZ1_DBG_LPTIM5 DBGMCU_APB4FZ1_DBG_LPTIM5_Msk
25053 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
25054 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
25055 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
25056 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
25057 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
25058 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
25059 #define DBGMCU_APB4FZ1_DBG_IWDG2_Pos (19U)
25060 #define DBGMCU_APB4FZ1_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG2_Pos) /*!< 0x00080000 */
25061 #define DBGMCU_APB4FZ1_DBG_IWDG2 DBGMCU_APB4FZ1_DBG_IWDG2_Msk
25062 /******************** Bit definition for APB4FZ2 register ************/
25063 #define DBGMCU_APB4FZ2_DBG_I2C4_Pos (7U)
25064 #define DBGMCU_APB4FZ2_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_I2C4_Pos) /*!< 0x00000080 */
25065 #define DBGMCU_APB4FZ2_DBG_I2C4 DBGMCU_APB4FZ2_DBG_I2C4_Msk
25066 #define DBGMCU_APB4FZ2_DBG_LPTIM2_Pos (9U)
25067 #define DBGMCU_APB4FZ2_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM2_Pos) /*!< 0x00000200 */
25068 #define DBGMCU_APB4FZ2_DBG_LPTIM2 DBGMCU_APB4FZ2_DBG_LPTIM2_Msk
25069 #define DBGMCU_APB4FZ2_DBG_LPTIM3_Pos (10U)
25070 #define DBGMCU_APB4FZ2_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM3_Pos) /*!< 0x00000400 */
25071 #define DBGMCU_APB4FZ2_DBG_LPTIM3 DBGMCU_APB4FZ2_DBG_LPTIM3_Msk
25072 #define DBGMCU_APB4FZ2_DBG_LPTIM4_Pos (11U)
25073 #define DBGMCU_APB4FZ2_DBG_LPTIM4_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM4_Pos) /*!< 0x00000800 */
25074 #define DBGMCU_APB4FZ2_DBG_LPTIM4 DBGMCU_APB4FZ2_DBG_LPTIM4_Msk
25075 #define DBGMCU_APB4FZ2_DBG_LPTIM5_Pos (12U)
25076 #define DBGMCU_APB4FZ2_DBG_LPTIM5_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_LPTIM5_Pos) /*!< 0x00001000 */
25077 #define DBGMCU_APB4FZ2_DBG_LPTIM5 DBGMCU_APB4FZ2_DBG_LPTIM5_Msk
25078 #define DBGMCU_APB4FZ2_DBG_RTC_Pos (16U)
25079 #define DBGMCU_APB4FZ2_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_RTC_Pos) /*!< 0x00010000 */
25080 #define DBGMCU_APB4FZ2_DBG_RTC DBGMCU_APB4FZ2_DBG_RTC_Msk
25081 #define DBGMCU_APB4FZ2_DBG_IWDG1_Pos (18U)
25082 #define DBGMCU_APB4FZ2_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG1_Pos) /*!< 0x00040000 */
25083 #define DBGMCU_APB4FZ2_DBG_IWDG1 DBGMCU_APB4FZ2_DBG_IWDG1_Msk
25084 #define DBGMCU_APB4FZ2_DBG_IWDG2_Pos (19U)
25085 #define DBGMCU_APB4FZ2_DBG_IWDG2_Msk (0x1UL << DBGMCU_APB4FZ2_DBG_IWDG2_Pos) /*!< 0x00080000 */
25086 #define DBGMCU_APB4FZ2_DBG_IWDG2 DBGMCU_APB4FZ2_DBG_IWDG2_Msk
25087 /******************************************************************************/
25088 /* */
25089 /* High Resolution Timer (HRTIM) */
25090 /* */
25091 /******************************************************************************/
25092 /******************** Master Timer control register ***************************/
25093 #define HRTIM_MCR_CK_PSC_Pos (0U)
25094 #define HRTIM_MCR_CK_PSC_Msk (0x7UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000007 */
25095 #define HRTIM_MCR_CK_PSC HRTIM_MCR_CK_PSC_Msk /*!< Prescaler mask */
25096 #define HRTIM_MCR_CK_PSC_0 (0x1UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000001 */
25097 #define HRTIM_MCR_CK_PSC_1 (0x2UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000002 */
25098 #define HRTIM_MCR_CK_PSC_2 (0x4UL << HRTIM_MCR_CK_PSC_Pos) /*!< 0x00000004 */
25099
25100 #define HRTIM_MCR_CONT_Pos (3U)
25101 #define HRTIM_MCR_CONT_Msk (0x1UL << HRTIM_MCR_CONT_Pos) /*!< 0x00000008 */
25102 #define HRTIM_MCR_CONT HRTIM_MCR_CONT_Msk /*!< Continuous mode */
25103 #define HRTIM_MCR_RETRIG_Pos (4U)
25104 #define HRTIM_MCR_RETRIG_Msk (0x1UL << HRTIM_MCR_RETRIG_Pos) /*!< 0x00000010 */
25105 #define HRTIM_MCR_RETRIG HRTIM_MCR_RETRIG_Msk /*!< Rettrigreable mode */
25106 #define HRTIM_MCR_HALF_Pos (5U)
25107 #define HRTIM_MCR_HALF_Msk (0x1UL << HRTIM_MCR_HALF_Pos) /*!< 0x00000020 */
25108 #define HRTIM_MCR_HALF HRTIM_MCR_HALF_Msk /*!< Half mode */
25109
25110 #define HRTIM_MCR_SYNC_IN_Pos (8U)
25111 #define HRTIM_MCR_SYNC_IN_Msk (0x3UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000300 */
25112 #define HRTIM_MCR_SYNC_IN HRTIM_MCR_SYNC_IN_Msk /*!< Synchronization input master */
25113 #define HRTIM_MCR_SYNC_IN_0 (0x1UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000100 */
25114 #define HRTIM_MCR_SYNC_IN_1 (0x2UL << HRTIM_MCR_SYNC_IN_Pos) /*!< 0x00000200 */
25115 #define HRTIM_MCR_SYNCRSTM_Pos (10U)
25116 #define HRTIM_MCR_SYNCRSTM_Msk (0x1UL << HRTIM_MCR_SYNCRSTM_Pos) /*!< 0x00000400 */
25117 #define HRTIM_MCR_SYNCRSTM HRTIM_MCR_SYNCRSTM_Msk /*!< Synchronization reset master */
25118 #define HRTIM_MCR_SYNCSTRTM_Pos (11U)
25119 #define HRTIM_MCR_SYNCSTRTM_Msk (0x1UL << HRTIM_MCR_SYNCSTRTM_Pos) /*!< 0x00000800 */
25120 #define HRTIM_MCR_SYNCSTRTM HRTIM_MCR_SYNCSTRTM_Msk /*!< Synchronization start master */
25121 #define HRTIM_MCR_SYNC_OUT_Pos (12U)
25122 #define HRTIM_MCR_SYNC_OUT_Msk (0x3UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00003000 */
25123 #define HRTIM_MCR_SYNC_OUT HRTIM_MCR_SYNC_OUT_Msk /*!< Synchronization output master */
25124 #define HRTIM_MCR_SYNC_OUT_0 (0x1UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00001000 */
25125 #define HRTIM_MCR_SYNC_OUT_1 (0x2UL << HRTIM_MCR_SYNC_OUT_Pos) /*!< 0x00002000 */
25126 #define HRTIM_MCR_SYNC_SRC_Pos (14U)
25127 #define HRTIM_MCR_SYNC_SRC_Msk (0x3UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x0000C000 */
25128 #define HRTIM_MCR_SYNC_SRC HRTIM_MCR_SYNC_SRC_Msk /*!< Synchronization source */
25129 #define HRTIM_MCR_SYNC_SRC_0 (0x1UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00004000 */
25130 #define HRTIM_MCR_SYNC_SRC_1 (0x2UL << HRTIM_MCR_SYNC_SRC_Pos) /*!< 0x00008000 */
25131
25132 #define HRTIM_MCR_MCEN_Pos (16U)
25133 #define HRTIM_MCR_MCEN_Msk (0x1UL << HRTIM_MCR_MCEN_Pos) /*!< 0x00010000 */
25134 #define HRTIM_MCR_MCEN HRTIM_MCR_MCEN_Msk /*!< Master counter enable */
25135 #define HRTIM_MCR_TACEN_Pos (17U)
25136 #define HRTIM_MCR_TACEN_Msk (0x1UL << HRTIM_MCR_TACEN_Pos) /*!< 0x00020000 */
25137 #define HRTIM_MCR_TACEN HRTIM_MCR_TACEN_Msk /*!< Timer A counter enable */
25138 #define HRTIM_MCR_TBCEN_Pos (18U)
25139 #define HRTIM_MCR_TBCEN_Msk (0x1UL << HRTIM_MCR_TBCEN_Pos) /*!< 0x00040000 */
25140 #define HRTIM_MCR_TBCEN HRTIM_MCR_TBCEN_Msk /*!< Timer B counter enable */
25141 #define HRTIM_MCR_TCCEN_Pos (19U)
25142 #define HRTIM_MCR_TCCEN_Msk (0x1UL << HRTIM_MCR_TCCEN_Pos) /*!< 0x00080000 */
25143 #define HRTIM_MCR_TCCEN HRTIM_MCR_TCCEN_Msk /*!< Timer C counter enable */
25144 #define HRTIM_MCR_TDCEN_Pos (20U)
25145 #define HRTIM_MCR_TDCEN_Msk (0x1UL << HRTIM_MCR_TDCEN_Pos) /*!< 0x00100000 */
25146 #define HRTIM_MCR_TDCEN HRTIM_MCR_TDCEN_Msk /*!< Timer D counter enable */
25147 #define HRTIM_MCR_TECEN_Pos (21U)
25148 #define HRTIM_MCR_TECEN_Msk (0x1UL << HRTIM_MCR_TECEN_Pos) /*!< 0x00200000 */
25149 #define HRTIM_MCR_TECEN HRTIM_MCR_TECEN_Msk /*!< Timer E counter enable */
25150
25151 #define HRTIM_MCR_DACSYNC_Pos (25U)
25152 #define HRTIM_MCR_DACSYNC_Msk (0x3UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x06000000 */
25153 #define HRTIM_MCR_DACSYNC HRTIM_MCR_DACSYNC_Msk /*!< DAC sychronization mask */
25154 #define HRTIM_MCR_DACSYNC_0 (0x1UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x02000000 */
25155 #define HRTIM_MCR_DACSYNC_1 (0x2UL << HRTIM_MCR_DACSYNC_Pos) /*!< 0x04000000 */
25156
25157 #define HRTIM_MCR_PREEN_Pos (27U)
25158 #define HRTIM_MCR_PREEN_Msk (0x1UL << HRTIM_MCR_PREEN_Pos) /*!< 0x08000000 */
25159 #define HRTIM_MCR_PREEN HRTIM_MCR_PREEN_Msk /*!< Master preload enable */
25160 #define HRTIM_MCR_MREPU_Pos (29U)
25161 #define HRTIM_MCR_MREPU_Msk (0x1UL << HRTIM_MCR_MREPU_Pos) /*!< 0x20000000 */
25162 #define HRTIM_MCR_MREPU HRTIM_MCR_MREPU_Msk /*!< Master repetition update */
25163
25164 #define HRTIM_MCR_BRSTDMA_Pos (30U)
25165 #define HRTIM_MCR_BRSTDMA_Msk (0x3UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0xC0000000 */
25166 #define HRTIM_MCR_BRSTDMA HRTIM_MCR_BRSTDMA_Msk /*!< Burst DMA update */
25167 #define HRTIM_MCR_BRSTDMA_0 (0x1UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x40000000 */
25168 #define HRTIM_MCR_BRSTDMA_1 (0x2UL << HRTIM_MCR_BRSTDMA_Pos) /*!< 0x80000000 */
25169
25170 /******************** Master Timer Interrupt status register ******************/
25171 #define HRTIM_MISR_MCMP1_Pos (0U)
25172 #define HRTIM_MISR_MCMP1_Msk (0x1UL << HRTIM_MISR_MCMP1_Pos) /*!< 0x00000001 */
25173 #define HRTIM_MISR_MCMP1 HRTIM_MISR_MCMP1_Msk /*!< Master compare 1 interrupt flag */
25174 #define HRTIM_MISR_MCMP2_Pos (1U)
25175 #define HRTIM_MISR_MCMP2_Msk (0x1UL << HRTIM_MISR_MCMP2_Pos) /*!< 0x00000002 */
25176 #define HRTIM_MISR_MCMP2 HRTIM_MISR_MCMP2_Msk /*!< Master compare 2 interrupt flag */
25177 #define HRTIM_MISR_MCMP3_Pos (2U)
25178 #define HRTIM_MISR_MCMP3_Msk (0x1UL << HRTIM_MISR_MCMP3_Pos) /*!< 0x00000004 */
25179 #define HRTIM_MISR_MCMP3 HRTIM_MISR_MCMP3_Msk /*!< Master compare 3 interrupt flag */
25180 #define HRTIM_MISR_MCMP4_Pos (3U)
25181 #define HRTIM_MISR_MCMP4_Msk (0x1UL << HRTIM_MISR_MCMP4_Pos) /*!< 0x00000008 */
25182 #define HRTIM_MISR_MCMP4 HRTIM_MISR_MCMP4_Msk /*!< Master compare 4 interrupt flag */
25183 #define HRTIM_MISR_MREP_Pos (4U)
25184 #define HRTIM_MISR_MREP_Msk (0x1UL << HRTIM_MISR_MREP_Pos) /*!< 0x00000010 */
25185 #define HRTIM_MISR_MREP HRTIM_MISR_MREP_Msk /*!< Master Repetition interrupt flag */
25186 #define HRTIM_MISR_SYNC_Pos (5U)
25187 #define HRTIM_MISR_SYNC_Msk (0x1UL << HRTIM_MISR_SYNC_Pos) /*!< 0x00000020 */
25188 #define HRTIM_MISR_SYNC HRTIM_MISR_SYNC_Msk /*!< Synchronization input interrupt flag */
25189 #define HRTIM_MISR_MUPD_Pos (6U)
25190 #define HRTIM_MISR_MUPD_Msk (0x1UL << HRTIM_MISR_MUPD_Pos) /*!< 0x00000040 */
25191 #define HRTIM_MISR_MUPD HRTIM_MISR_MUPD_Msk /*!< Master update interrupt flag */
25192
25193 /******************** Master Timer Interrupt clear register *******************/
25194 #define HRTIM_MICR_MCMP1_Pos (0U)
25195 #define HRTIM_MICR_MCMP1_Msk (0x1UL << HRTIM_MICR_MCMP1_Pos) /*!< 0x00000001 */
25196 #define HRTIM_MICR_MCMP1 HRTIM_MICR_MCMP1_Msk /*!< Master compare 1 interrupt flag clear */
25197 #define HRTIM_MICR_MCMP2_Pos (1U)
25198 #define HRTIM_MICR_MCMP2_Msk (0x1UL << HRTIM_MICR_MCMP2_Pos) /*!< 0x00000002 */
25199 #define HRTIM_MICR_MCMP2 HRTIM_MICR_MCMP2_Msk /*!< Master compare 2 interrupt flag clear */
25200 #define HRTIM_MICR_MCMP3_Pos (2U)
25201 #define HRTIM_MICR_MCMP3_Msk (0x1UL << HRTIM_MICR_MCMP3_Pos) /*!< 0x00000004 */
25202 #define HRTIM_MICR_MCMP3 HRTIM_MICR_MCMP3_Msk /*!< Master compare 3 interrupt flag clear */
25203 #define HRTIM_MICR_MCMP4_Pos (3U)
25204 #define HRTIM_MICR_MCMP4_Msk (0x1UL << HRTIM_MICR_MCMP4_Pos) /*!< 0x00000008 */
25205 #define HRTIM_MICR_MCMP4 HRTIM_MICR_MCMP4_Msk /*!< Master compare 4 interrupt flag clear */
25206 #define HRTIM_MICR_MREP_Pos (4U)
25207 #define HRTIM_MICR_MREP_Msk (0x1UL << HRTIM_MICR_MREP_Pos) /*!< 0x00000010 */
25208 #define HRTIM_MICR_MREP HRTIM_MICR_MREP_Msk /*!< Master Repetition interrupt flag clear */
25209 #define HRTIM_MICR_SYNC_Pos (5U)
25210 #define HRTIM_MICR_SYNC_Msk (0x1UL << HRTIM_MICR_SYNC_Pos) /*!< 0x00000020 */
25211 #define HRTIM_MICR_SYNC HRTIM_MICR_SYNC_Msk /*!< Synchronization input interrupt flag clear */
25212 #define HRTIM_MICR_MUPD_Pos (6U)
25213 #define HRTIM_MICR_MUPD_Msk (0x1UL << HRTIM_MICR_MUPD_Pos) /*!< 0x00000040 */
25214 #define HRTIM_MICR_MUPD HRTIM_MICR_MUPD_Msk /*!< Master update interrupt flag clear */
25215
25216 /******************** Master Timer DMA/Interrupt enable register **************/
25217 #define HRTIM_MDIER_MCMP1IE_Pos (0U)
25218 #define HRTIM_MDIER_MCMP1IE_Msk (0x1UL << HRTIM_MDIER_MCMP1IE_Pos) /*!< 0x00000001 */
25219 #define HRTIM_MDIER_MCMP1IE HRTIM_MDIER_MCMP1IE_Msk /*!< Master compare 1 interrupt enable */
25220 #define HRTIM_MDIER_MCMP2IE_Pos (1U)
25221 #define HRTIM_MDIER_MCMP2IE_Msk (0x1UL << HRTIM_MDIER_MCMP2IE_Pos) /*!< 0x00000002 */
25222 #define HRTIM_MDIER_MCMP2IE HRTIM_MDIER_MCMP2IE_Msk /*!< Master compare 2 interrupt enable */
25223 #define HRTIM_MDIER_MCMP3IE_Pos (2U)
25224 #define HRTIM_MDIER_MCMP3IE_Msk (0x1UL << HRTIM_MDIER_MCMP3IE_Pos) /*!< 0x00000004 */
25225 #define HRTIM_MDIER_MCMP3IE HRTIM_MDIER_MCMP3IE_Msk /*!< Master compare 3 interrupt enable */
25226 #define HRTIM_MDIER_MCMP4IE_Pos (3U)
25227 #define HRTIM_MDIER_MCMP4IE_Msk (0x1UL << HRTIM_MDIER_MCMP4IE_Pos) /*!< 0x00000008 */
25228 #define HRTIM_MDIER_MCMP4IE HRTIM_MDIER_MCMP4IE_Msk /*!< Master compare 4 interrupt enable */
25229 #define HRTIM_MDIER_MREPIE_Pos (4U)
25230 #define HRTIM_MDIER_MREPIE_Msk (0x1UL << HRTIM_MDIER_MREPIE_Pos) /*!< 0x00000010 */
25231 #define HRTIM_MDIER_MREPIE HRTIM_MDIER_MREPIE_Msk /*!< Master Repetition interrupt enable */
25232 #define HRTIM_MDIER_SYNCIE_Pos (5U)
25233 #define HRTIM_MDIER_SYNCIE_Msk (0x1UL << HRTIM_MDIER_SYNCIE_Pos) /*!< 0x00000020 */
25234 #define HRTIM_MDIER_SYNCIE HRTIM_MDIER_SYNCIE_Msk /*!< Synchronization input interrupt enable */
25235 #define HRTIM_MDIER_MUPDIE_Pos (6U)
25236 #define HRTIM_MDIER_MUPDIE_Msk (0x1UL << HRTIM_MDIER_MUPDIE_Pos) /*!< 0x00000040 */
25237 #define HRTIM_MDIER_MUPDIE HRTIM_MDIER_MUPDIE_Msk /*!< Master update interrupt enable */
25238
25239 #define HRTIM_MDIER_MCMP1DE_Pos (16U)
25240 #define HRTIM_MDIER_MCMP1DE_Msk (0x1UL << HRTIM_MDIER_MCMP1DE_Pos) /*!< 0x00010000 */
25241 #define HRTIM_MDIER_MCMP1DE HRTIM_MDIER_MCMP1DE_Msk /*!< Master compare 1 DMA enable */
25242 #define HRTIM_MDIER_MCMP2DE_Pos (17U)
25243 #define HRTIM_MDIER_MCMP2DE_Msk (0x1UL << HRTIM_MDIER_MCMP2DE_Pos) /*!< 0x00020000 */
25244 #define HRTIM_MDIER_MCMP2DE HRTIM_MDIER_MCMP2DE_Msk /*!< Master compare 2 DMA enable */
25245 #define HRTIM_MDIER_MCMP3DE_Pos (18U)
25246 #define HRTIM_MDIER_MCMP3DE_Msk (0x1UL << HRTIM_MDIER_MCMP3DE_Pos) /*!< 0x00040000 */
25247 #define HRTIM_MDIER_MCMP3DE HRTIM_MDIER_MCMP3DE_Msk /*!< Master compare 3 DMA enable */
25248 #define HRTIM_MDIER_MCMP4DE_Pos (19U)
25249 #define HRTIM_MDIER_MCMP4DE_Msk (0x1UL << HRTIM_MDIER_MCMP4DE_Pos) /*!< 0x00080000 */
25250 #define HRTIM_MDIER_MCMP4DE HRTIM_MDIER_MCMP4DE_Msk /*!< Master compare 4 DMA enable */
25251 #define HRTIM_MDIER_MREPDE_Pos (20U)
25252 #define HRTIM_MDIER_MREPDE_Msk (0x1UL << HRTIM_MDIER_MREPDE_Pos) /*!< 0x00100000 */
25253 #define HRTIM_MDIER_MREPDE HRTIM_MDIER_MREPDE_Msk /*!< Master Repetition DMA enable */
25254 #define HRTIM_MDIER_SYNCDE_Pos (21U)
25255 #define HRTIM_MDIER_SYNCDE_Msk (0x1UL << HRTIM_MDIER_SYNCDE_Pos) /*!< 0x00200000 */
25256 #define HRTIM_MDIER_SYNCDE HRTIM_MDIER_SYNCDE_Msk /*!< Synchronization input DMA enable */
25257 #define HRTIM_MDIER_MUPDDE_Pos (22U)
25258 #define HRTIM_MDIER_MUPDDE_Msk (0x1UL << HRTIM_MDIER_MUPDDE_Pos) /*!< 0x00400000 */
25259 #define HRTIM_MDIER_MUPDDE HRTIM_MDIER_MUPDDE_Msk /*!< Master update DMA enable */
25260
25261 /******************* Bit definition for HRTIM_MCNTR register ****************/
25262 #define HRTIM_MCNTR_MCNTR_Pos (0U)
25263 #define HRTIM_MCNTR_MCNTR_Msk (0xFFFFUL << HRTIM_MCNTR_MCNTR_Pos) /*!< 0x0000FFFF */
25264 #define HRTIM_MCNTR_MCNTR HRTIM_MCNTR_MCNTR_Msk /*!<Counter Value */
25265
25266 /******************* Bit definition for HRTIM_MPER register *****************/
25267 #define HRTIM_MPER_MPER_Pos (0U)
25268 #define HRTIM_MPER_MPER_Msk (0xFFFFUL << HRTIM_MPER_MPER_Pos) /*!< 0x0000FFFF */
25269 #define HRTIM_MPER_MPER HRTIM_MPER_MPER_Msk /*!< Period Value */
25270
25271 /******************* Bit definition for HRTIM_MREP register *****************/
25272 #define HRTIM_MREP_MREP_Pos (0U)
25273 #define HRTIM_MREP_MREP_Msk (0xFFUL << HRTIM_MREP_MREP_Pos) /*!< 0x000000FF */
25274 #define HRTIM_MREP_MREP HRTIM_MREP_MREP_Msk /*!<Repetition Value */
25275
25276 /******************* Bit definition for HRTIM_MCMP1R register *****************/
25277 #define HRTIM_MCMP1R_MCMP1R_Pos (0U)
25278 #define HRTIM_MCMP1R_MCMP1R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP1R_Pos) /*!< 0x0000FFFF */
25279 #define HRTIM_MCMP1R_MCMP1R HRTIM_MCMP1R_MCMP1R_Msk /*!<Compare Value */
25280
25281 /******************* Bit definition for HRTIM_MCMP2R register *****************/
25282 #define HRTIM_MCMP1R_MCMP2R_Pos (0U)
25283 #define HRTIM_MCMP1R_MCMP2R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP2R_Pos) /*!< 0x0000FFFF */
25284 #define HRTIM_MCMP1R_MCMP2R HRTIM_MCMP1R_MCMP2R_Msk /*!<Compare Value */
25285
25286 /******************* Bit definition for HRTIM_MCMP3R register *****************/
25287 #define HRTIM_MCMP1R_MCMP3R_Pos (0U)
25288 #define HRTIM_MCMP1R_MCMP3R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP3R_Pos) /*!< 0x0000FFFF */
25289 #define HRTIM_MCMP1R_MCMP3R HRTIM_MCMP1R_MCMP3R_Msk /*!<Compare Value */
25290
25291 /******************* Bit definition for HRTIM_MCMP4R register *****************/
25292 #define HRTIM_MCMP1R_MCMP4R_Pos (0U)
25293 #define HRTIM_MCMP1R_MCMP4R_Msk (0xFFFFUL << HRTIM_MCMP1R_MCMP4R_Pos) /*!< 0x0000FFFF */
25294 #define HRTIM_MCMP1R_MCMP4R HRTIM_MCMP1R_MCMP4R_Msk /*!<Compare Value */
25295
25296 /******************** Slave control register **********************************/
25297 #define HRTIM_TIMCR_CK_PSC_Pos (0U)
25298 #define HRTIM_TIMCR_CK_PSC_Msk (0x7UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000007 */
25299 #define HRTIM_TIMCR_CK_PSC HRTIM_TIMCR_CK_PSC_Msk /*!< Slave prescaler mask*/
25300 #define HRTIM_TIMCR_CK_PSC_0 (0x1UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000001 */
25301 #define HRTIM_TIMCR_CK_PSC_1 (0x2UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000002 */
25302 #define HRTIM_TIMCR_CK_PSC_2 (0x4UL << HRTIM_TIMCR_CK_PSC_Pos) /*!< 0x00000004 */
25303
25304 #define HRTIM_TIMCR_CONT_Pos (3U)
25305 #define HRTIM_TIMCR_CONT_Msk (0x1UL << HRTIM_TIMCR_CONT_Pos) /*!< 0x00000008 */
25306 #define HRTIM_TIMCR_CONT HRTIM_TIMCR_CONT_Msk /*!< Slave continuous mode */
25307 #define HRTIM_TIMCR_RETRIG_Pos (4U)
25308 #define HRTIM_TIMCR_RETRIG_Msk (0x1UL << HRTIM_TIMCR_RETRIG_Pos) /*!< 0x00000010 */
25309 #define HRTIM_TIMCR_RETRIG HRTIM_TIMCR_RETRIG_Msk /*!< Slave Retrigreable mode */
25310 #define HRTIM_TIMCR_HALF_Pos (5U)
25311 #define HRTIM_TIMCR_HALF_Msk (0x1UL << HRTIM_TIMCR_HALF_Pos) /*!< 0x00000020 */
25312 #define HRTIM_TIMCR_HALF HRTIM_TIMCR_HALF_Msk /*!< Slave Half mode */
25313 #define HRTIM_TIMCR_PSHPLL_Pos (6U)
25314 #define HRTIM_TIMCR_PSHPLL_Msk (0x1UL << HRTIM_TIMCR_PSHPLL_Pos) /*!< 0x00000040 */
25315 #define HRTIM_TIMCR_PSHPLL HRTIM_TIMCR_PSHPLL_Msk /*!< Slave push-pull mode */
25316
25317 #define HRTIM_TIMCR_SYNCRST_Pos (10U)
25318 #define HRTIM_TIMCR_SYNCRST_Msk (0x1UL << HRTIM_TIMCR_SYNCRST_Pos) /*!< 0x00000400 */
25319 #define HRTIM_TIMCR_SYNCRST HRTIM_TIMCR_SYNCRST_Msk /*!< Slave synchronization resets */
25320 #define HRTIM_TIMCR_SYNCSTRT_Pos (11U)
25321 #define HRTIM_TIMCR_SYNCSTRT_Msk (0x1UL << HRTIM_TIMCR_SYNCSTRT_Pos) /*!< 0x00000800 */
25322 #define HRTIM_TIMCR_SYNCSTRT HRTIM_TIMCR_SYNCSTRT_Msk /*!< Slave synchronization starts */
25323
25324 #define HRTIM_TIMCR_DELCMP2_Pos (12U)
25325 #define HRTIM_TIMCR_DELCMP2_Msk (0x3UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00003000 */
25326 #define HRTIM_TIMCR_DELCMP2 HRTIM_TIMCR_DELCMP2_Msk /*!< Slave delayed compartor 2 mode mask */
25327 #define HRTIM_TIMCR_DELCMP2_0 (0x1UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00001000 */
25328 #define HRTIM_TIMCR_DELCMP2_1 (0x2UL << HRTIM_TIMCR_DELCMP2_Pos) /*!< 0x00002000 */
25329 #define HRTIM_TIMCR_DELCMP4_Pos (14U)
25330 #define HRTIM_TIMCR_DELCMP4_Msk (0x3UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x0000C000 */
25331 #define HRTIM_TIMCR_DELCMP4 HRTIM_TIMCR_DELCMP4_Msk /*!< Slave delayed compartor 4 mode mask */
25332 #define HRTIM_TIMCR_DELCMP4_0 (0x1UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00004000 */
25333 #define HRTIM_TIMCR_DELCMP4_1 (0x2UL << HRTIM_TIMCR_DELCMP4_Pos) /*!< 0x00008000 */
25334
25335 #define HRTIM_TIMCR_TREPU_Pos (17U)
25336 #define HRTIM_TIMCR_TREPU_Msk (0x1UL << HRTIM_TIMCR_TREPU_Pos) /*!< 0x00020000 */
25337 #define HRTIM_TIMCR_TREPU HRTIM_TIMCR_TREPU_Msk /*!< Slave repetition update */
25338 #define HRTIM_TIMCR_TRSTU_Pos (18U)
25339 #define HRTIM_TIMCR_TRSTU_Msk (0x1UL << HRTIM_TIMCR_TRSTU_Pos) /*!< 0x00040000 */
25340 #define HRTIM_TIMCR_TRSTU HRTIM_TIMCR_TRSTU_Msk /*!< Slave reset update */
25341 #define HRTIM_TIMCR_TAU_Pos (19U)
25342 #define HRTIM_TIMCR_TAU_Msk (0x1UL << HRTIM_TIMCR_TAU_Pos) /*!< 0x00080000 */
25343 #define HRTIM_TIMCR_TAU HRTIM_TIMCR_TAU_Msk /*!< Slave Timer A update reserved for TIM A */
25344 #define HRTIM_TIMCR_TBU_Pos (20U)
25345 #define HRTIM_TIMCR_TBU_Msk (0x1UL << HRTIM_TIMCR_TBU_Pos) /*!< 0x00100000 */
25346 #define HRTIM_TIMCR_TBU HRTIM_TIMCR_TBU_Msk /*!< Slave Timer B update reserved for TIM B */
25347 #define HRTIM_TIMCR_TCU_Pos (21U)
25348 #define HRTIM_TIMCR_TCU_Msk (0x1UL << HRTIM_TIMCR_TCU_Pos) /*!< 0x00200000 */
25349 #define HRTIM_TIMCR_TCU HRTIM_TIMCR_TCU_Msk /*!< Slave Timer C update reserved for TIM C */
25350 #define HRTIM_TIMCR_TDU_Pos (22U)
25351 #define HRTIM_TIMCR_TDU_Msk (0x1UL << HRTIM_TIMCR_TDU_Pos) /*!< 0x00400000 */
25352 #define HRTIM_TIMCR_TDU HRTIM_TIMCR_TDU_Msk /*!< Slave Timer D update reserved for TIM D */
25353 #define HRTIM_TIMCR_TEU_Pos (23U)
25354 #define HRTIM_TIMCR_TEU_Msk (0x1UL << HRTIM_TIMCR_TEU_Pos) /*!< 0x00800000 */
25355 #define HRTIM_TIMCR_TEU HRTIM_TIMCR_TEU_Msk /*!< Slave Timer E update reserved for TIM E */
25356 #define HRTIM_TIMCR_MSTU_Pos (24U)
25357 #define HRTIM_TIMCR_MSTU_Msk (0x1UL << HRTIM_TIMCR_MSTU_Pos) /*!< 0x01000000 */
25358 #define HRTIM_TIMCR_MSTU HRTIM_TIMCR_MSTU_Msk /*!< Master Update */
25359
25360 #define HRTIM_TIMCR_DACSYNC_Pos (25U)
25361 #define HRTIM_TIMCR_DACSYNC_Msk (0x3UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x06000000 */
25362 #define HRTIM_TIMCR_DACSYNC HRTIM_TIMCR_DACSYNC_Msk /*!< DAC sychronization mask */
25363 #define HRTIM_TIMCR_DACSYNC_0 (0x1UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x02000000 */
25364 #define HRTIM_TIMCR_DACSYNC_1 (0x2UL << HRTIM_TIMCR_DACSYNC_Pos) /*!< 0x04000000 */
25365 #define HRTIM_TIMCR_PREEN_Pos (27U)
25366 #define HRTIM_TIMCR_PREEN_Msk (0x1UL << HRTIM_TIMCR_PREEN_Pos) /*!< 0x08000000 */
25367 #define HRTIM_TIMCR_PREEN HRTIM_TIMCR_PREEN_Msk /*!< Slave preload enable */
25368
25369 #define HRTIM_TIMCR_UPDGAT_Pos (28U)
25370 #define HRTIM_TIMCR_UPDGAT_Msk (0xFUL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0xF0000000 */
25371 #define HRTIM_TIMCR_UPDGAT HRTIM_TIMCR_UPDGAT_Msk /*!< Slave update gating mask */
25372 #define HRTIM_TIMCR_UPDGAT_0 (0x1UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x10000000 */
25373 #define HRTIM_TIMCR_UPDGAT_1 (0x2UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x20000000 */
25374 #define HRTIM_TIMCR_UPDGAT_2 (0x4UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x40000000 */
25375 #define HRTIM_TIMCR_UPDGAT_3 (0x8UL << HRTIM_TIMCR_UPDGAT_Pos) /*!< 0x80000000 */
25376
25377 /******************** Slave Interrupt status register **************************/
25378 #define HRTIM_TIMISR_CMP1_Pos (0U)
25379 #define HRTIM_TIMISR_CMP1_Msk (0x1UL << HRTIM_TIMISR_CMP1_Pos) /*!< 0x00000001 */
25380 #define HRTIM_TIMISR_CMP1 HRTIM_TIMISR_CMP1_Msk /*!< Slave compare 1 interrupt flag */
25381 #define HRTIM_TIMISR_CMP2_Pos (1U)
25382 #define HRTIM_TIMISR_CMP2_Msk (0x1UL << HRTIM_TIMISR_CMP2_Pos) /*!< 0x00000002 */
25383 #define HRTIM_TIMISR_CMP2 HRTIM_TIMISR_CMP2_Msk /*!< Slave compare 2 interrupt flag */
25384 #define HRTIM_TIMISR_CMP3_Pos (2U)
25385 #define HRTIM_TIMISR_CMP3_Msk (0x1UL << HRTIM_TIMISR_CMP3_Pos) /*!< 0x00000004 */
25386 #define HRTIM_TIMISR_CMP3 HRTIM_TIMISR_CMP3_Msk /*!< Slave compare 3 interrupt flag */
25387 #define HRTIM_TIMISR_CMP4_Pos (3U)
25388 #define HRTIM_TIMISR_CMP4_Msk (0x1UL << HRTIM_TIMISR_CMP4_Pos) /*!< 0x00000008 */
25389 #define HRTIM_TIMISR_CMP4 HRTIM_TIMISR_CMP4_Msk /*!< Slave compare 4 interrupt flag */
25390 #define HRTIM_TIMISR_REP_Pos (4U)
25391 #define HRTIM_TIMISR_REP_Msk (0x1UL << HRTIM_TIMISR_REP_Pos) /*!< 0x00000010 */
25392 #define HRTIM_TIMISR_REP HRTIM_TIMISR_REP_Msk /*!< Slave repetition interrupt flag */
25393 #define HRTIM_TIMISR_UPD_Pos (6U)
25394 #define HRTIM_TIMISR_UPD_Msk (0x1UL << HRTIM_TIMISR_UPD_Pos) /*!< 0x00000040 */
25395 #define HRTIM_TIMISR_UPD HRTIM_TIMISR_UPD_Msk /*!< Slave update interrupt flag */
25396 #define HRTIM_TIMISR_CPT1_Pos (7U)
25397 #define HRTIM_TIMISR_CPT1_Msk (0x1UL << HRTIM_TIMISR_CPT1_Pos) /*!< 0x00000080 */
25398 #define HRTIM_TIMISR_CPT1 HRTIM_TIMISR_CPT1_Msk /*!< Slave capture 1 interrupt flag */
25399 #define HRTIM_TIMISR_CPT2_Pos (8U)
25400 #define HRTIM_TIMISR_CPT2_Msk (0x1UL << HRTIM_TIMISR_CPT2_Pos) /*!< 0x00000100 */
25401 #define HRTIM_TIMISR_CPT2 HRTIM_TIMISR_CPT2_Msk /*!< Slave capture 2 interrupt flag */
25402 #define HRTIM_TIMISR_SET1_Pos (9U)
25403 #define HRTIM_TIMISR_SET1_Msk (0x1UL << HRTIM_TIMISR_SET1_Pos) /*!< 0x00000200 */
25404 #define HRTIM_TIMISR_SET1 HRTIM_TIMISR_SET1_Msk /*!< Slave output 1 set interrupt flag */
25405 #define HRTIM_TIMISR_RST1_Pos (10U)
25406 #define HRTIM_TIMISR_RST1_Msk (0x1UL << HRTIM_TIMISR_RST1_Pos) /*!< 0x00000400 */
25407 #define HRTIM_TIMISR_RST1 HRTIM_TIMISR_RST1_Msk /*!< Slave output 1 reset interrupt flag */
25408 #define HRTIM_TIMISR_SET2_Pos (11U)
25409 #define HRTIM_TIMISR_SET2_Msk (0x1UL << HRTIM_TIMISR_SET2_Pos) /*!< 0x00000800 */
25410 #define HRTIM_TIMISR_SET2 HRTIM_TIMISR_SET2_Msk /*!< Slave output 2 set interrupt flag */
25411 #define HRTIM_TIMISR_RST2_Pos (12U)
25412 #define HRTIM_TIMISR_RST2_Msk (0x1UL << HRTIM_TIMISR_RST2_Pos) /*!< 0x00001000 */
25413 #define HRTIM_TIMISR_RST2 HRTIM_TIMISR_RST2_Msk /*!< Slave output 2 reset interrupt flag */
25414 #define HRTIM_TIMISR_RST_Pos (13U)
25415 #define HRTIM_TIMISR_RST_Msk (0x1UL << HRTIM_TIMISR_RST_Pos) /*!< 0x00002000 */
25416 #define HRTIM_TIMISR_RST HRTIM_TIMISR_RST_Msk /*!< Slave reset interrupt flag */
25417 #define HRTIM_TIMISR_DLYPRT_Pos (14U)
25418 #define HRTIM_TIMISR_DLYPRT_Msk (0x1UL << HRTIM_TIMISR_DLYPRT_Pos) /*!< 0x00004000 */
25419 #define HRTIM_TIMISR_DLYPRT HRTIM_TIMISR_DLYPRT_Msk /*!< Slave output 1 delay protection interrupt flag */
25420 #define HRTIM_TIMISR_CPPSTAT_Pos (16U)
25421 #define HRTIM_TIMISR_CPPSTAT_Msk (0x1UL << HRTIM_TIMISR_CPPSTAT_Pos) /*!< 0x00010000 */
25422 #define HRTIM_TIMISR_CPPSTAT HRTIM_TIMISR_CPPSTAT_Msk /*!< Slave current push-pull flag */
25423 #define HRTIM_TIMISR_IPPSTAT_Pos (17U)
25424 #define HRTIM_TIMISR_IPPSTAT_Msk (0x1UL << HRTIM_TIMISR_IPPSTAT_Pos) /*!< 0x00020000 */
25425 #define HRTIM_TIMISR_IPPSTAT HRTIM_TIMISR_IPPSTAT_Msk /*!< Slave idle push-pull flag */
25426 #define HRTIM_TIMISR_O1STAT_Pos (18U)
25427 #define HRTIM_TIMISR_O1STAT_Msk (0x1UL << HRTIM_TIMISR_O1STAT_Pos) /*!< 0x00040000 */
25428 #define HRTIM_TIMISR_O1STAT HRTIM_TIMISR_O1STAT_Msk /*!< Slave output 1 state flag */
25429 #define HRTIM_TIMISR_O2STAT_Pos (19U)
25430 #define HRTIM_TIMISR_O2STAT_Msk (0x1UL << HRTIM_TIMISR_O2STAT_Pos) /*!< 0x00080000 */
25431 #define HRTIM_TIMISR_O2STAT HRTIM_TIMISR_O2STAT_Msk /*!< Slave output 2 state flag */
25432 #define HRTIM_TIMISR_O1CPY_Pos (20U)
25433 #define HRTIM_TIMISR_O1CPY_Msk (0x1UL << HRTIM_TIMISR_O1CPY_Pos) /*!< 0x00100000 */
25434 #define HRTIM_TIMISR_O1CPY HRTIM_TIMISR_O1CPY_Msk /*!< Slave output 1 copy flag */
25435 #define HRTIM_TIMISR_O2CPY_Pos (21U)
25436 #define HRTIM_TIMISR_O2CPY_Msk (0x1UL << HRTIM_TIMISR_O2CPY_Pos) /*!< 0x00200000 */
25437 #define HRTIM_TIMISR_O2CPY HRTIM_TIMISR_O2CPY_Msk /*!< Slave output 2 copy flag */
25438
25439 /******************** Slave Interrupt clear register **************************/
25440 #define HRTIM_TIMICR_CMP1C_Pos (0U)
25441 #define HRTIM_TIMICR_CMP1C_Msk (0x1UL << HRTIM_TIMICR_CMP1C_Pos) /*!< 0x00000001 */
25442 #define HRTIM_TIMICR_CMP1C HRTIM_TIMICR_CMP1C_Msk /*!< Slave compare 1 clear flag */
25443 #define HRTIM_TIMICR_CMP2C_Pos (1U)
25444 #define HRTIM_TIMICR_CMP2C_Msk (0x1UL << HRTIM_TIMICR_CMP2C_Pos) /*!< 0x00000002 */
25445 #define HRTIM_TIMICR_CMP2C HRTIM_TIMICR_CMP2C_Msk /*!< Slave compare 2 clear flag */
25446 #define HRTIM_TIMICR_CMP3C_Pos (2U)
25447 #define HRTIM_TIMICR_CMP3C_Msk (0x1UL << HRTIM_TIMICR_CMP3C_Pos) /*!< 0x00000004 */
25448 #define HRTIM_TIMICR_CMP3C HRTIM_TIMICR_CMP3C_Msk /*!< Slave compare 3 clear flag */
25449 #define HRTIM_TIMICR_CMP4C_Pos (3U)
25450 #define HRTIM_TIMICR_CMP4C_Msk (0x1UL << HRTIM_TIMICR_CMP4C_Pos) /*!< 0x00000008 */
25451 #define HRTIM_TIMICR_CMP4C HRTIM_TIMICR_CMP4C_Msk /*!< Slave compare 4 clear flag */
25452 #define HRTIM_TIMICR_REPC_Pos (4U)
25453 #define HRTIM_TIMICR_REPC_Msk (0x1UL << HRTIM_TIMICR_REPC_Pos) /*!< 0x00000010 */
25454 #define HRTIM_TIMICR_REPC HRTIM_TIMICR_REPC_Msk /*!< Slave repetition clear flag */
25455 #define HRTIM_TIMICR_UPDC_Pos (6U)
25456 #define HRTIM_TIMICR_UPDC_Msk (0x1UL << HRTIM_TIMICR_UPDC_Pos) /*!< 0x00000040 */
25457 #define HRTIM_TIMICR_UPDC HRTIM_TIMICR_UPDC_Msk /*!< Slave update clear flag */
25458 #define HRTIM_TIMICR_CPT1C_Pos (7U)
25459 #define HRTIM_TIMICR_CPT1C_Msk (0x1UL << HRTIM_TIMICR_CPT1C_Pos) /*!< 0x00000080 */
25460 #define HRTIM_TIMICR_CPT1C HRTIM_TIMICR_CPT1C_Msk /*!< Slave capture 1 clear flag */
25461 #define HRTIM_TIMICR_CPT2C_Pos (8U)
25462 #define HRTIM_TIMICR_CPT2C_Msk (0x1UL << HRTIM_TIMICR_CPT2C_Pos) /*!< 0x00000100 */
25463 #define HRTIM_TIMICR_CPT2C HRTIM_TIMICR_CPT2C_Msk /*!< Slave capture 2 clear flag */
25464 #define HRTIM_TIMICR_SET1C_Pos (9U)
25465 #define HRTIM_TIMICR_SET1C_Msk (0x1UL << HRTIM_TIMICR_SET1C_Pos) /*!< 0x00000200 */
25466 #define HRTIM_TIMICR_SET1C HRTIM_TIMICR_SET1C_Msk /*!< Slave output 1 set clear flag */
25467 #define HRTIM_TIMICR_RST1C_Pos (10U)
25468 #define HRTIM_TIMICR_RST1C_Msk (0x1UL << HRTIM_TIMICR_RST1C_Pos) /*!< 0x00000400 */
25469 #define HRTIM_TIMICR_RST1C HRTIM_TIMICR_RST1C_Msk /*!< Slave output 1 reset clear flag */
25470 #define HRTIM_TIMICR_SET2C_Pos (11U)
25471 #define HRTIM_TIMICR_SET2C_Msk (0x1UL << HRTIM_TIMICR_SET2C_Pos) /*!< 0x00000800 */
25472 #define HRTIM_TIMICR_SET2C HRTIM_TIMICR_SET2C_Msk /*!< Slave output 2 set clear flag */
25473 #define HRTIM_TIMICR_RST2C_Pos (12U)
25474 #define HRTIM_TIMICR_RST2C_Msk (0x1UL << HRTIM_TIMICR_RST2C_Pos) /*!< 0x00001000 */
25475 #define HRTIM_TIMICR_RST2C HRTIM_TIMICR_RST2C_Msk /*!< Slave output 2 reset clear flag */
25476 #define HRTIM_TIMICR_RSTC_Pos (13U)
25477 #define HRTIM_TIMICR_RSTC_Msk (0x1UL << HRTIM_TIMICR_RSTC_Pos) /*!< 0x00002000 */
25478 #define HRTIM_TIMICR_RSTC HRTIM_TIMICR_RSTC_Msk /*!< Slave reset clear flag */
25479 #define HRTIM_TIMICR_DLYPRTC_Pos (14U)
25480 #define HRTIM_TIMICR_DLYPRTC_Msk (0x1UL << HRTIM_TIMICR_DLYPRTC_Pos) /*!< 0x00004000 */
25481 #define HRTIM_TIMICR_DLYPRTC HRTIM_TIMICR_DLYPRTC_Msk /*!< Slave output 1 delay protection clear flag */
25482
25483 /******************** Slave DMA/Interrupt enable register *********************/
25484 #define HRTIM_TIMDIER_CMP1IE_Pos (0U)
25485 #define HRTIM_TIMDIER_CMP1IE_Msk (0x1UL << HRTIM_TIMDIER_CMP1IE_Pos) /*!< 0x00000001 */
25486 #define HRTIM_TIMDIER_CMP1IE HRTIM_TIMDIER_CMP1IE_Msk /*!< Slave compare 1 interrupt enable */
25487 #define HRTIM_TIMDIER_CMP2IE_Pos (1U)
25488 #define HRTIM_TIMDIER_CMP2IE_Msk (0x1UL << HRTIM_TIMDIER_CMP2IE_Pos) /*!< 0x00000002 */
25489 #define HRTIM_TIMDIER_CMP2IE HRTIM_TIMDIER_CMP2IE_Msk /*!< Slave compare 2 interrupt enable */
25490 #define HRTIM_TIMDIER_CMP3IE_Pos (2U)
25491 #define HRTIM_TIMDIER_CMP3IE_Msk (0x1UL << HRTIM_TIMDIER_CMP3IE_Pos) /*!< 0x00000004 */
25492 #define HRTIM_TIMDIER_CMP3IE HRTIM_TIMDIER_CMP3IE_Msk /*!< Slave compare 3 interrupt enable */
25493 #define HRTIM_TIMDIER_CMP4IE_Pos (3U)
25494 #define HRTIM_TIMDIER_CMP4IE_Msk (0x1UL << HRTIM_TIMDIER_CMP4IE_Pos) /*!< 0x00000008 */
25495 #define HRTIM_TIMDIER_CMP4IE HRTIM_TIMDIER_CMP4IE_Msk /*!< Slave compare 4 interrupt enable */
25496 #define HRTIM_TIMDIER_REPIE_Pos (4U)
25497 #define HRTIM_TIMDIER_REPIE_Msk (0x1UL << HRTIM_TIMDIER_REPIE_Pos) /*!< 0x00000010 */
25498 #define HRTIM_TIMDIER_REPIE HRTIM_TIMDIER_REPIE_Msk /*!< Slave repetition interrupt enable */
25499 #define HRTIM_TIMDIER_UPDIE_Pos (6U)
25500 #define HRTIM_TIMDIER_UPDIE_Msk (0x1UL << HRTIM_TIMDIER_UPDIE_Pos) /*!< 0x00000040 */
25501 #define HRTIM_TIMDIER_UPDIE HRTIM_TIMDIER_UPDIE_Msk /*!< Slave update interrupt enable */
25502 #define HRTIM_TIMDIER_CPT1IE_Pos (7U)
25503 #define HRTIM_TIMDIER_CPT1IE_Msk (0x1UL << HRTIM_TIMDIER_CPT1IE_Pos) /*!< 0x00000080 */
25504 #define HRTIM_TIMDIER_CPT1IE HRTIM_TIMDIER_CPT1IE_Msk /*!< Slave capture 1 interrupt enable */
25505 #define HRTIM_TIMDIER_CPT2IE_Pos (8U)
25506 #define HRTIM_TIMDIER_CPT2IE_Msk (0x1UL << HRTIM_TIMDIER_CPT2IE_Pos) /*!< 0x00000100 */
25507 #define HRTIM_TIMDIER_CPT2IE HRTIM_TIMDIER_CPT2IE_Msk /*!< Slave capture 2 interrupt enable */
25508 #define HRTIM_TIMDIER_SET1IE_Pos (9U)
25509 #define HRTIM_TIMDIER_SET1IE_Msk (0x1UL << HRTIM_TIMDIER_SET1IE_Pos) /*!< 0x00000200 */
25510 #define HRTIM_TIMDIER_SET1IE HRTIM_TIMDIER_SET1IE_Msk /*!< Slave output 1 set interrupt enable */
25511 #define HRTIM_TIMDIER_RST1IE_Pos (10U)
25512 #define HRTIM_TIMDIER_RST1IE_Msk (0x1UL << HRTIM_TIMDIER_RST1IE_Pos) /*!< 0x00000400 */
25513 #define HRTIM_TIMDIER_RST1IE HRTIM_TIMDIER_RST1IE_Msk /*!< Slave output 1 reset interrupt enable */
25514 #define HRTIM_TIMDIER_SET2IE_Pos (11U)
25515 #define HRTIM_TIMDIER_SET2IE_Msk (0x1UL << HRTIM_TIMDIER_SET2IE_Pos) /*!< 0x00000800 */
25516 #define HRTIM_TIMDIER_SET2IE HRTIM_TIMDIER_SET2IE_Msk /*!< Slave output 2 set interrupt enable */
25517 #define HRTIM_TIMDIER_RST2IE_Pos (12U)
25518 #define HRTIM_TIMDIER_RST2IE_Msk (0x1UL << HRTIM_TIMDIER_RST2IE_Pos) /*!< 0x00001000 */
25519 #define HRTIM_TIMDIER_RST2IE HRTIM_TIMDIER_RST2IE_Msk /*!< Slave output 2 reset interrupt enable */
25520 #define HRTIM_TIMDIER_RSTIE_Pos (13U)
25521 #define HRTIM_TIMDIER_RSTIE_Msk (0x1UL << HRTIM_TIMDIER_RSTIE_Pos) /*!< 0x00002000 */
25522 #define HRTIM_TIMDIER_RSTIE HRTIM_TIMDIER_RSTIE_Msk /*!< Slave reset interrupt enable */
25523 #define HRTIM_TIMDIER_DLYPRTIE_Pos (14U)
25524 #define HRTIM_TIMDIER_DLYPRTIE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTIE_Pos) /*!< 0x00004000 */
25525 #define HRTIM_TIMDIER_DLYPRTIE HRTIM_TIMDIER_DLYPRTIE_Msk /*!< Slave delay protection interrupt enable */
25526
25527 #define HRTIM_TIMDIER_CMP1DE_Pos (16U)
25528 #define HRTIM_TIMDIER_CMP1DE_Msk (0x1UL << HRTIM_TIMDIER_CMP1DE_Pos) /*!< 0x00010000 */
25529 #define HRTIM_TIMDIER_CMP1DE HRTIM_TIMDIER_CMP1DE_Msk /*!< Slave compare 1 request enable */
25530 #define HRTIM_TIMDIER_CMP2DE_Pos (17U)
25531 #define HRTIM_TIMDIER_CMP2DE_Msk (0x1UL << HRTIM_TIMDIER_CMP2DE_Pos) /*!< 0x00020000 */
25532 #define HRTIM_TIMDIER_CMP2DE HRTIM_TIMDIER_CMP2DE_Msk /*!< Slave compare 2 request enable */
25533 #define HRTIM_TIMDIER_CMP3DE_Pos (18U)
25534 #define HRTIM_TIMDIER_CMP3DE_Msk (0x1UL << HRTIM_TIMDIER_CMP3DE_Pos) /*!< 0x00040000 */
25535 #define HRTIM_TIMDIER_CMP3DE HRTIM_TIMDIER_CMP3DE_Msk /*!< Slave compare 3 request enable */
25536 #define HRTIM_TIMDIER_CMP4DE_Pos (19U)
25537 #define HRTIM_TIMDIER_CMP4DE_Msk (0x1UL << HRTIM_TIMDIER_CMP4DE_Pos) /*!< 0x00080000 */
25538 #define HRTIM_TIMDIER_CMP4DE HRTIM_TIMDIER_CMP4DE_Msk /*!< Slave compare 4 request enable */
25539 #define HRTIM_TIMDIER_REPDE_Pos (20U)
25540 #define HRTIM_TIMDIER_REPDE_Msk (0x1UL << HRTIM_TIMDIER_REPDE_Pos) /*!< 0x00100000 */
25541 #define HRTIM_TIMDIER_REPDE HRTIM_TIMDIER_REPDE_Msk /*!< Slave repetition request enable */
25542 #define HRTIM_TIMDIER_UPDDE_Pos (22U)
25543 #define HRTIM_TIMDIER_UPDDE_Msk (0x1UL << HRTIM_TIMDIER_UPDDE_Pos) /*!< 0x00400000 */
25544 #define HRTIM_TIMDIER_UPDDE HRTIM_TIMDIER_UPDDE_Msk /*!< Slave update request enable */
25545 #define HRTIM_TIMDIER_CPT1DE_Pos (23U)
25546 #define HRTIM_TIMDIER_CPT1DE_Msk (0x1UL << HRTIM_TIMDIER_CPT1DE_Pos) /*!< 0x00800000 */
25547 #define HRTIM_TIMDIER_CPT1DE HRTIM_TIMDIER_CPT1DE_Msk /*!< Slave capture 1 request enable */
25548 #define HRTIM_TIMDIER_CPT2DE_Pos (24U)
25549 #define HRTIM_TIMDIER_CPT2DE_Msk (0x1UL << HRTIM_TIMDIER_CPT2DE_Pos) /*!< 0x01000000 */
25550 #define HRTIM_TIMDIER_CPT2DE HRTIM_TIMDIER_CPT2DE_Msk /*!< Slave capture 2 request enable */
25551 #define HRTIM_TIMDIER_SET1DE_Pos (25U)
25552 #define HRTIM_TIMDIER_SET1DE_Msk (0x1UL << HRTIM_TIMDIER_SET1DE_Pos) /*!< 0x02000000 */
25553 #define HRTIM_TIMDIER_SET1DE HRTIM_TIMDIER_SET1DE_Msk /*!< Slave output 1 set request enable */
25554 #define HRTIM_TIMDIER_RST1DE_Pos (26U)
25555 #define HRTIM_TIMDIER_RST1DE_Msk (0x1UL << HRTIM_TIMDIER_RST1DE_Pos) /*!< 0x04000000 */
25556 #define HRTIM_TIMDIER_RST1DE HRTIM_TIMDIER_RST1DE_Msk /*!< Slave output 1 reset request enable */
25557 #define HRTIM_TIMDIER_SET2DE_Pos (27U)
25558 #define HRTIM_TIMDIER_SET2DE_Msk (0x1UL << HRTIM_TIMDIER_SET2DE_Pos) /*!< 0x08000000 */
25559 #define HRTIM_TIMDIER_SET2DE HRTIM_TIMDIER_SET2DE_Msk /*!< Slave output 2 set request enable */
25560 #define HRTIM_TIMDIER_RST2DE_Pos (28U)
25561 #define HRTIM_TIMDIER_RST2DE_Msk (0x1UL << HRTIM_TIMDIER_RST2DE_Pos) /*!< 0x10000000 */
25562 #define HRTIM_TIMDIER_RST2DE HRTIM_TIMDIER_RST2DE_Msk /*!< Slave output 2 reset request enable */
25563 #define HRTIM_TIMDIER_RSTDE_Pos (29U)
25564 #define HRTIM_TIMDIER_RSTDE_Msk (0x1UL << HRTIM_TIMDIER_RSTDE_Pos) /*!< 0x20000000 */
25565 #define HRTIM_TIMDIER_RSTDE HRTIM_TIMDIER_RSTDE_Msk /*!< Slave reset request enable */
25566 #define HRTIM_TIMDIER_DLYPRTDE_Pos (30U)
25567 #define HRTIM_TIMDIER_DLYPRTDE_Msk (0x1UL << HRTIM_TIMDIER_DLYPRTDE_Pos) /*!< 0x40000000 */
25568 #define HRTIM_TIMDIER_DLYPRTDE HRTIM_TIMDIER_DLYPRTDE_Msk /*!< Slavedelay protection request enable */
25569
25570 /****************** Bit definition for HRTIM_CNTR register ****************/
25571 #define HRTIM_CNTR_CNTR_Pos (0U)
25572 #define HRTIM_CNTR_CNTR_Msk (0xFFFFUL << HRTIM_CNTR_CNTR_Pos) /*!< 0x0000FFFF */
25573 #define HRTIM_CNTR_CNTR HRTIM_CNTR_CNTR_Msk /*!< Counter Value */
25574
25575 /******************* Bit definition for HRTIM_PER register *****************/
25576 #define HRTIM_PER_PER_Pos (0U)
25577 #define HRTIM_PER_PER_Msk (0xFFFFUL << HRTIM_PER_PER_Pos) /*!< 0x0000FFFF */
25578 #define HRTIM_PER_PER HRTIM_PER_PER_Msk /*!< Period Value */
25579
25580 /******************* Bit definition for HRTIM_REP register *****************/
25581 #define HRTIM_REP_REP_Pos (0U)
25582 #define HRTIM_REP_REP_Msk (0xFFUL << HRTIM_REP_REP_Pos) /*!< 0x000000FF */
25583 #define HRTIM_REP_REP HRTIM_REP_REP_Msk /*!< Repetition Value */
25584
25585 /******************* Bit definition for HRTIM_CMP1R register *****************/
25586 #define HRTIM_CMP1R_CMP1R_Pos (0U)
25587 #define HRTIM_CMP1R_CMP1R_Msk (0xFFFFUL << HRTIM_CMP1R_CMP1R_Pos) /*!< 0x0000FFFF */
25588 #define HRTIM_CMP1R_CMP1R HRTIM_CMP1R_CMP1R_Msk /*!< Compare Value */
25589
25590 /******************* Bit definition for HRTIM_CMP1CR register *****************/
25591 #define HRTIM_CMP1CR_CMP1CR_Pos (0U)
25592 #define HRTIM_CMP1CR_CMP1CR_Msk (0xFFFFFFFFUL << HRTIM_CMP1CR_CMP1CR_Pos) /*!< 0xFFFFFFFF */
25593 #define HRTIM_CMP1CR_CMP1CR HRTIM_CMP1CR_CMP1CR_Msk /*!< Compare Value */
25594
25595 /******************* Bit definition for HRTIM_CMP2R register *****************/
25596 #define HRTIM_CMP2R_CMP2R_Pos (0U)
25597 #define HRTIM_CMP2R_CMP2R_Msk (0xFFFFUL << HRTIM_CMP2R_CMP2R_Pos) /*!< 0x0000FFFF */
25598 #define HRTIM_CMP2R_CMP2R HRTIM_CMP2R_CMP2R_Msk /*!< Compare Value */
25599
25600 /******************* Bit definition for HRTIM_CMP3R register *****************/
25601 #define HRTIM_CMP3R_CMP3R_Pos (0U)
25602 #define HRTIM_CMP3R_CMP3R_Msk (0xFFFFUL << HRTIM_CMP3R_CMP3R_Pos) /*!< 0x0000FFFF */
25603 #define HRTIM_CMP3R_CMP3R HRTIM_CMP3R_CMP3R_Msk /*!< Compare Value */
25604
25605 /******************* Bit definition for HRTIM_CMP4R register *****************/
25606 #define HRTIM_CMP4R_CMP4R_Pos (0U)
25607 #define HRTIM_CMP4R_CMP4R_Msk (0xFFFFUL << HRTIM_CMP4R_CMP4R_Pos) /*!< 0x0000FFFF */
25608 #define HRTIM_CMP4R_CMP4R HRTIM_CMP4R_CMP4R_Msk /*!< Compare Value */
25609
25610 /******************* Bit definition for HRTIM_CPT1R register ****************/
25611 #define HRTIM_CPT1R_CPT1R_Pos (0U)
25612 #define HRTIM_CPT1R_CPT1R_Msk (0xFFFFUL << HRTIM_CPT1R_CPT1R_Pos) /*!< 0x0000FFFF */
25613 #define HRTIM_CPT1R_CPT1R HRTIM_CPT1R_CPT1R_Msk /*!< Capture Value */
25614
25615 /******************* Bit definition for HRTIM_CPT2R register ****************/
25616 #define HRTIM_CPT2R_CPT2R_Pos (0U)
25617 #define HRTIM_CPT2R_CPT2R_Msk (0xFFFFUL << HRTIM_CPT2R_CPT2R_Pos) /*!< 0x0000FFFF */
25618 #define HRTIM_CPT2R_CPT2R HRTIM_CPT2R_CPT2R_Msk /*!< Capture Value */
25619
25620 /******************** Bit definition for Slave Deadtime register **************/
25621 #define HRTIM_DTR_DTR_Pos (0U)
25622 #define HRTIM_DTR_DTR_Msk (0x1FFUL << HRTIM_DTR_DTR_Pos) /*!< 0x000001FF */
25623 #define HRTIM_DTR_DTR HRTIM_DTR_DTR_Msk /*!< Dead time rising value */
25624 #define HRTIM_DTR_DTR_0 (0x001UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000001 */
25625 #define HRTIM_DTR_DTR_1 (0x002UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000002 */
25626 #define HRTIM_DTR_DTR_2 (0x004UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000004 */
25627 #define HRTIM_DTR_DTR_3 (0x008UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000008 */
25628 #define HRTIM_DTR_DTR_4 (0x010UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000010 */
25629 #define HRTIM_DTR_DTR_5 (0x020UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000020 */
25630 #define HRTIM_DTR_DTR_6 (0x040UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000040 */
25631 #define HRTIM_DTR_DTR_7 (0x080UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000080 */
25632 #define HRTIM_DTR_DTR_8 (0x100UL << HRTIM_DTR_DTR_Pos) /*!< 0x00000100 */
25633 #define HRTIM_DTR_SDTR_Pos (9U)
25634 #define HRTIM_DTR_SDTR_Msk (0x1UL << HRTIM_DTR_SDTR_Pos) /*!< 0x00000200 */
25635 #define HRTIM_DTR_SDTR HRTIM_DTR_SDTR_Msk /*!< Sign dead time rising value */
25636 #define HRTIM_DTR_DTPRSC_Pos (10U)
25637 #define HRTIM_DTR_DTPRSC_Msk (0x7UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001C00 */
25638 #define HRTIM_DTR_DTPRSC HRTIM_DTR_DTPRSC_Msk /*!< Dead time prescaler */
25639 #define HRTIM_DTR_DTPRSC_0 (0x1UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000400 */
25640 #define HRTIM_DTR_DTPRSC_1 (0x2UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00000800 */
25641 #define HRTIM_DTR_DTPRSC_2 (0x4UL << HRTIM_DTR_DTPRSC_Pos) /*!< 0x00001000 */
25642 #define HRTIM_DTR_DTRSLK_Pos (14U)
25643 #define HRTIM_DTR_DTRSLK_Msk (0x1UL << HRTIM_DTR_DTRSLK_Pos) /*!< 0x00004000 */
25644 #define HRTIM_DTR_DTRSLK HRTIM_DTR_DTRSLK_Msk /*!< Dead time rising sign lock */
25645 #define HRTIM_DTR_DTRLK_Pos (15U)
25646 #define HRTIM_DTR_DTRLK_Msk (0x1UL << HRTIM_DTR_DTRLK_Pos) /*!< 0x00008000 */
25647 #define HRTIM_DTR_DTRLK HRTIM_DTR_DTRLK_Msk /*!< Dead time rising lock */
25648 #define HRTIM_DTR_DTF_Pos (16U)
25649 #define HRTIM_DTR_DTF_Msk (0x1FFUL << HRTIM_DTR_DTF_Pos) /*!< 0x01FF0000 */
25650 #define HRTIM_DTR_DTF HRTIM_DTR_DTF_Msk /*!< Dead time falling value */
25651 #define HRTIM_DTR_DTF_0 (0x001UL << HRTIM_DTR_DTF_Pos) /*!< 0x00010000 */
25652 #define HRTIM_DTR_DTF_1 (0x002UL << HRTIM_DTR_DTF_Pos) /*!< 0x00020000 */
25653 #define HRTIM_DTR_DTF_2 (0x004UL << HRTIM_DTR_DTF_Pos) /*!< 0x00040000 */
25654 #define HRTIM_DTR_DTF_3 (0x008UL << HRTIM_DTR_DTF_Pos) /*!< 0x00080000 */
25655 #define HRTIM_DTR_DTF_4 (0x010UL << HRTIM_DTR_DTF_Pos) /*!< 0x00100000 */
25656 #define HRTIM_DTR_DTF_5 (0x020UL << HRTIM_DTR_DTF_Pos) /*!< 0x00200000 */
25657 #define HRTIM_DTR_DTF_6 (0x040UL << HRTIM_DTR_DTF_Pos) /*!< 0x00400000 */
25658 #define HRTIM_DTR_DTF_7 (0x080UL << HRTIM_DTR_DTF_Pos) /*!< 0x00800000 */
25659 #define HRTIM_DTR_DTF_8 (0x100UL << HRTIM_DTR_DTF_Pos) /*!< 0x01000000 */
25660 #define HRTIM_DTR_SDTF_Pos (25U)
25661 #define HRTIM_DTR_SDTF_Msk (0x1UL << HRTIM_DTR_SDTF_Pos) /*!< 0x02000000 */
25662 #define HRTIM_DTR_SDTF HRTIM_DTR_SDTF_Msk /*!< Sign dead time falling value */
25663 #define HRTIM_DTR_DTFSLK_Pos (30U)
25664 #define HRTIM_DTR_DTFSLK_Msk (0x1UL << HRTIM_DTR_DTFSLK_Pos) /*!< 0x40000000 */
25665 #define HRTIM_DTR_DTFSLK HRTIM_DTR_DTFSLK_Msk /*!< Dead time falling sign lock */
25666 #define HRTIM_DTR_DTFLK_Pos (31U)
25667 #define HRTIM_DTR_DTFLK_Msk (0x1UL << HRTIM_DTR_DTFLK_Pos) /*!< 0x80000000 */
25668 #define HRTIM_DTR_DTFLK HRTIM_DTR_DTFLK_Msk /*!< Dead time falling lock */
25669
25670 /**** Bit definition for Slave Output 1 set register **************************/
25671 #define HRTIM_SET1R_SST_Pos (0U)
25672 #define HRTIM_SET1R_SST_Msk (0x1UL << HRTIM_SET1R_SST_Pos) /*!< 0x00000001 */
25673 #define HRTIM_SET1R_SST HRTIM_SET1R_SST_Msk /*!< software set trigger */
25674 #define HRTIM_SET1R_RESYNC_Pos (1U)
25675 #define HRTIM_SET1R_RESYNC_Msk (0x1UL << HRTIM_SET1R_RESYNC_Pos) /*!< 0x00000002 */
25676 #define HRTIM_SET1R_RESYNC HRTIM_SET1R_RESYNC_Msk /*!< Timer A resynchronization */
25677 #define HRTIM_SET1R_PER_Pos (2U)
25678 #define HRTIM_SET1R_PER_Msk (0x1UL << HRTIM_SET1R_PER_Pos) /*!< 0x00000004 */
25679 #define HRTIM_SET1R_PER HRTIM_SET1R_PER_Msk /*!< Timer A period */
25680 #define HRTIM_SET1R_CMP1_Pos (3U)
25681 #define HRTIM_SET1R_CMP1_Msk (0x1UL << HRTIM_SET1R_CMP1_Pos) /*!< 0x00000008 */
25682 #define HRTIM_SET1R_CMP1 HRTIM_SET1R_CMP1_Msk /*!< Timer A compare 1 */
25683 #define HRTIM_SET1R_CMP2_Pos (4U)
25684 #define HRTIM_SET1R_CMP2_Msk (0x1UL << HRTIM_SET1R_CMP2_Pos) /*!< 0x00000010 */
25685 #define HRTIM_SET1R_CMP2 HRTIM_SET1R_CMP2_Msk /*!< Timer A compare 2 */
25686 #define HRTIM_SET1R_CMP3_Pos (5U)
25687 #define HRTIM_SET1R_CMP3_Msk (0x1UL << HRTIM_SET1R_CMP3_Pos) /*!< 0x00000020 */
25688 #define HRTIM_SET1R_CMP3 HRTIM_SET1R_CMP3_Msk /*!< Timer A compare 3 */
25689 #define HRTIM_SET1R_CMP4_Pos (6U)
25690 #define HRTIM_SET1R_CMP4_Msk (0x1UL << HRTIM_SET1R_CMP4_Pos) /*!< 0x00000040 */
25691 #define HRTIM_SET1R_CMP4 HRTIM_SET1R_CMP4_Msk /*!< Timer A compare 4 */
25692
25693 #define HRTIM_SET1R_MSTPER_Pos (7U)
25694 #define HRTIM_SET1R_MSTPER_Msk (0x1UL << HRTIM_SET1R_MSTPER_Pos) /*!< 0x00000080 */
25695 #define HRTIM_SET1R_MSTPER HRTIM_SET1R_MSTPER_Msk /*!< Master period */
25696 #define HRTIM_SET1R_MSTCMP1_Pos (8U)
25697 #define HRTIM_SET1R_MSTCMP1_Msk (0x1UL << HRTIM_SET1R_MSTCMP1_Pos) /*!< 0x00000100 */
25698 #define HRTIM_SET1R_MSTCMP1 HRTIM_SET1R_MSTCMP1_Msk /*!< Master compare 1 */
25699 #define HRTIM_SET1R_MSTCMP2_Pos (9U)
25700 #define HRTIM_SET1R_MSTCMP2_Msk (0x1UL << HRTIM_SET1R_MSTCMP2_Pos) /*!< 0x00000200 */
25701 #define HRTIM_SET1R_MSTCMP2 HRTIM_SET1R_MSTCMP2_Msk /*!< Master compare 2 */
25702 #define HRTIM_SET1R_MSTCMP3_Pos (10U)
25703 #define HRTIM_SET1R_MSTCMP3_Msk (0x1UL << HRTIM_SET1R_MSTCMP3_Pos) /*!< 0x00000400 */
25704 #define HRTIM_SET1R_MSTCMP3 HRTIM_SET1R_MSTCMP3_Msk /*!< Master compare 3 */
25705 #define HRTIM_SET1R_MSTCMP4_Pos (11U)
25706 #define HRTIM_SET1R_MSTCMP4_Msk (0x1UL << HRTIM_SET1R_MSTCMP4_Pos) /*!< 0x00000800 */
25707 #define HRTIM_SET1R_MSTCMP4 HRTIM_SET1R_MSTCMP4_Msk /*!< Master compare 4 */
25708
25709 #define HRTIM_SET1R_TIMEVNT1_Pos (12U)
25710 #define HRTIM_SET1R_TIMEVNT1_Msk (0x1UL << HRTIM_SET1R_TIMEVNT1_Pos) /*!< 0x00001000 */
25711 #define HRTIM_SET1R_TIMEVNT1 HRTIM_SET1R_TIMEVNT1_Msk /*!< Timer event 1 */
25712 #define HRTIM_SET1R_TIMEVNT2_Pos (13U)
25713 #define HRTIM_SET1R_TIMEVNT2_Msk (0x1UL << HRTIM_SET1R_TIMEVNT2_Pos) /*!< 0x00002000 */
25714 #define HRTIM_SET1R_TIMEVNT2 HRTIM_SET1R_TIMEVNT2_Msk /*!< Timer event 2 */
25715 #define HRTIM_SET1R_TIMEVNT3_Pos (14U)
25716 #define HRTIM_SET1R_TIMEVNT3_Msk (0x1UL << HRTIM_SET1R_TIMEVNT3_Pos) /*!< 0x00004000 */
25717 #define HRTIM_SET1R_TIMEVNT3 HRTIM_SET1R_TIMEVNT3_Msk /*!< Timer event 3 */
25718 #define HRTIM_SET1R_TIMEVNT4_Pos (15U)
25719 #define HRTIM_SET1R_TIMEVNT4_Msk (0x1UL << HRTIM_SET1R_TIMEVNT4_Pos) /*!< 0x00008000 */
25720 #define HRTIM_SET1R_TIMEVNT4 HRTIM_SET1R_TIMEVNT4_Msk /*!< Timer event 4 */
25721 #define HRTIM_SET1R_TIMEVNT5_Pos (16U)
25722 #define HRTIM_SET1R_TIMEVNT5_Msk (0x1UL << HRTIM_SET1R_TIMEVNT5_Pos) /*!< 0x00010000 */
25723 #define HRTIM_SET1R_TIMEVNT5 HRTIM_SET1R_TIMEVNT5_Msk /*!< Timer event 5 */
25724 #define HRTIM_SET1R_TIMEVNT6_Pos (17U)
25725 #define HRTIM_SET1R_TIMEVNT6_Msk (0x1UL << HRTIM_SET1R_TIMEVNT6_Pos) /*!< 0x00020000 */
25726 #define HRTIM_SET1R_TIMEVNT6 HRTIM_SET1R_TIMEVNT6_Msk /*!< Timer event 6 */
25727 #define HRTIM_SET1R_TIMEVNT7_Pos (18U)
25728 #define HRTIM_SET1R_TIMEVNT7_Msk (0x1UL << HRTIM_SET1R_TIMEVNT7_Pos) /*!< 0x00040000 */
25729 #define HRTIM_SET1R_TIMEVNT7 HRTIM_SET1R_TIMEVNT7_Msk /*!< Timer event 7 */
25730 #define HRTIM_SET1R_TIMEVNT8_Pos (19U)
25731 #define HRTIM_SET1R_TIMEVNT8_Msk (0x1UL << HRTIM_SET1R_TIMEVNT8_Pos) /*!< 0x00080000 */
25732 #define HRTIM_SET1R_TIMEVNT8 HRTIM_SET1R_TIMEVNT8_Msk /*!< Timer event 8 */
25733 #define HRTIM_SET1R_TIMEVNT9_Pos (20U)
25734 #define HRTIM_SET1R_TIMEVNT9_Msk (0x1UL << HRTIM_SET1R_TIMEVNT9_Pos) /*!< 0x00100000 */
25735 #define HRTIM_SET1R_TIMEVNT9 HRTIM_SET1R_TIMEVNT9_Msk /*!< Timer event 9 */
25736
25737 #define HRTIM_SET1R_EXTVNT1_Pos (21U)
25738 #define HRTIM_SET1R_EXTVNT1_Msk (0x1UL << HRTIM_SET1R_EXTVNT1_Pos) /*!< 0x00200000 */
25739 #define HRTIM_SET1R_EXTVNT1 HRTIM_SET1R_EXTVNT1_Msk /*!< External event 1 */
25740 #define HRTIM_SET1R_EXTVNT2_Pos (22U)
25741 #define HRTIM_SET1R_EXTVNT2_Msk (0x1UL << HRTIM_SET1R_EXTVNT2_Pos) /*!< 0x00400000 */
25742 #define HRTIM_SET1R_EXTVNT2 HRTIM_SET1R_EXTVNT2_Msk /*!< External event 2 */
25743 #define HRTIM_SET1R_EXTVNT3_Pos (23U)
25744 #define HRTIM_SET1R_EXTVNT3_Msk (0x1UL << HRTIM_SET1R_EXTVNT3_Pos) /*!< 0x00800000 */
25745 #define HRTIM_SET1R_EXTVNT3 HRTIM_SET1R_EXTVNT3_Msk /*!< External event 3 */
25746 #define HRTIM_SET1R_EXTVNT4_Pos (24U)
25747 #define HRTIM_SET1R_EXTVNT4_Msk (0x1UL << HRTIM_SET1R_EXTVNT4_Pos) /*!< 0x01000000 */
25748 #define HRTIM_SET1R_EXTVNT4 HRTIM_SET1R_EXTVNT4_Msk /*!< External event 4 */
25749 #define HRTIM_SET1R_EXTVNT5_Pos (25U)
25750 #define HRTIM_SET1R_EXTVNT5_Msk (0x1UL << HRTIM_SET1R_EXTVNT5_Pos) /*!< 0x02000000 */
25751 #define HRTIM_SET1R_EXTVNT5 HRTIM_SET1R_EXTVNT5_Msk /*!< External event 5 */
25752 #define HRTIM_SET1R_EXTVNT6_Pos (26U)
25753 #define HRTIM_SET1R_EXTVNT6_Msk (0x1UL << HRTIM_SET1R_EXTVNT6_Pos) /*!< 0x04000000 */
25754 #define HRTIM_SET1R_EXTVNT6 HRTIM_SET1R_EXTVNT6_Msk /*!< External event 6 */
25755 #define HRTIM_SET1R_EXTVNT7_Pos (27U)
25756 #define HRTIM_SET1R_EXTVNT7_Msk (0x1UL << HRTIM_SET1R_EXTVNT7_Pos) /*!< 0x08000000 */
25757 #define HRTIM_SET1R_EXTVNT7 HRTIM_SET1R_EXTVNT7_Msk /*!< External event 7 */
25758 #define HRTIM_SET1R_EXTVNT8_Pos (28U)
25759 #define HRTIM_SET1R_EXTVNT8_Msk (0x1UL << HRTIM_SET1R_EXTVNT8_Pos) /*!< 0x10000000 */
25760 #define HRTIM_SET1R_EXTVNT8 HRTIM_SET1R_EXTVNT8_Msk /*!< External event 8 */
25761 #define HRTIM_SET1R_EXTVNT9_Pos (29U)
25762 #define HRTIM_SET1R_EXTVNT9_Msk (0x1UL << HRTIM_SET1R_EXTVNT9_Pos) /*!< 0x20000000 */
25763 #define HRTIM_SET1R_EXTVNT9 HRTIM_SET1R_EXTVNT9_Msk /*!< External event 9 */
25764 #define HRTIM_SET1R_EXTVNT10_Pos (30U)
25765 #define HRTIM_SET1R_EXTVNT10_Msk (0x1UL << HRTIM_SET1R_EXTVNT10_Pos) /*!< 0x40000000 */
25766 #define HRTIM_SET1R_EXTVNT10 HRTIM_SET1R_EXTVNT10_Msk /*!< External event 10 */
25767
25768 #define HRTIM_SET1R_UPDATE_Pos (31U)
25769 #define HRTIM_SET1R_UPDATE_Msk (0x1UL << HRTIM_SET1R_UPDATE_Pos) /*!< 0x80000000 */
25770 #define HRTIM_SET1R_UPDATE HRTIM_SET1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
25771
25772 /**** Bit definition for Slave Output 1 reset register ************************/
25773 #define HRTIM_RST1R_SRT_Pos (0U)
25774 #define HRTIM_RST1R_SRT_Msk (0x1UL << HRTIM_RST1R_SRT_Pos) /*!< 0x00000001 */
25775 #define HRTIM_RST1R_SRT HRTIM_RST1R_SRT_Msk /*!< software reset trigger */
25776 #define HRTIM_RST1R_RESYNC_Pos (1U)
25777 #define HRTIM_RST1R_RESYNC_Msk (0x1UL << HRTIM_RST1R_RESYNC_Pos) /*!< 0x00000002 */
25778 #define HRTIM_RST1R_RESYNC HRTIM_RST1R_RESYNC_Msk /*!< Timer A resynchronization */
25779 #define HRTIM_RST1R_PER_Pos (2U)
25780 #define HRTIM_RST1R_PER_Msk (0x1UL << HRTIM_RST1R_PER_Pos) /*!< 0x00000004 */
25781 #define HRTIM_RST1R_PER HRTIM_RST1R_PER_Msk /*!< Timer A period */
25782 #define HRTIM_RST1R_CMP1_Pos (3U)
25783 #define HRTIM_RST1R_CMP1_Msk (0x1UL << HRTIM_RST1R_CMP1_Pos) /*!< 0x00000008 */
25784 #define HRTIM_RST1R_CMP1 HRTIM_RST1R_CMP1_Msk /*!< Timer A compare 1 */
25785 #define HRTIM_RST1R_CMP2_Pos (4U)
25786 #define HRTIM_RST1R_CMP2_Msk (0x1UL << HRTIM_RST1R_CMP2_Pos) /*!< 0x00000010 */
25787 #define HRTIM_RST1R_CMP2 HRTIM_RST1R_CMP2_Msk /*!< Timer A compare 2 */
25788 #define HRTIM_RST1R_CMP3_Pos (5U)
25789 #define HRTIM_RST1R_CMP3_Msk (0x1UL << HRTIM_RST1R_CMP3_Pos) /*!< 0x00000020 */
25790 #define HRTIM_RST1R_CMP3 HRTIM_RST1R_CMP3_Msk /*!< Timer A compare 3 */
25791 #define HRTIM_RST1R_CMP4_Pos (6U)
25792 #define HRTIM_RST1R_CMP4_Msk (0x1UL << HRTIM_RST1R_CMP4_Pos) /*!< 0x00000040 */
25793 #define HRTIM_RST1R_CMP4 HRTIM_RST1R_CMP4_Msk /*!< Timer A compare 4 */
25794
25795 #define HRTIM_RST1R_MSTPER_Pos (7U)
25796 #define HRTIM_RST1R_MSTPER_Msk (0x1UL << HRTIM_RST1R_MSTPER_Pos) /*!< 0x00000080 */
25797 #define HRTIM_RST1R_MSTPER HRTIM_RST1R_MSTPER_Msk /*!< Master period */
25798 #define HRTIM_RST1R_MSTCMP1_Pos (8U)
25799 #define HRTIM_RST1R_MSTCMP1_Msk (0x1UL << HRTIM_RST1R_MSTCMP1_Pos) /*!< 0x00000100 */
25800 #define HRTIM_RST1R_MSTCMP1 HRTIM_RST1R_MSTCMP1_Msk /*!< Master compare 1 */
25801 #define HRTIM_RST1R_MSTCMP2_Pos (9U)
25802 #define HRTIM_RST1R_MSTCMP2_Msk (0x1UL << HRTIM_RST1R_MSTCMP2_Pos) /*!< 0x00000200 */
25803 #define HRTIM_RST1R_MSTCMP2 HRTIM_RST1R_MSTCMP2_Msk /*!< Master compare 2 */
25804 #define HRTIM_RST1R_MSTCMP3_Pos (10U)
25805 #define HRTIM_RST1R_MSTCMP3_Msk (0x1UL << HRTIM_RST1R_MSTCMP3_Pos) /*!< 0x00000400 */
25806 #define HRTIM_RST1R_MSTCMP3 HRTIM_RST1R_MSTCMP3_Msk /*!< Master compare 3 */
25807 #define HRTIM_RST1R_MSTCMP4_Pos (11U)
25808 #define HRTIM_RST1R_MSTCMP4_Msk (0x1UL << HRTIM_RST1R_MSTCMP4_Pos) /*!< 0x00000800 */
25809 #define HRTIM_RST1R_MSTCMP4 HRTIM_RST1R_MSTCMP4_Msk /*!< Master compare 4 */
25810
25811 #define HRTIM_RST1R_TIMEVNT1_Pos (12U)
25812 #define HRTIM_RST1R_TIMEVNT1_Msk (0x1UL << HRTIM_RST1R_TIMEVNT1_Pos) /*!< 0x00001000 */
25813 #define HRTIM_RST1R_TIMEVNT1 HRTIM_RST1R_TIMEVNT1_Msk /*!< Timer event 1 */
25814 #define HRTIM_RST1R_TIMEVNT2_Pos (13U)
25815 #define HRTIM_RST1R_TIMEVNT2_Msk (0x1UL << HRTIM_RST1R_TIMEVNT2_Pos) /*!< 0x00002000 */
25816 #define HRTIM_RST1R_TIMEVNT2 HRTIM_RST1R_TIMEVNT2_Msk /*!< Timer event 2 */
25817 #define HRTIM_RST1R_TIMEVNT3_Pos (14U)
25818 #define HRTIM_RST1R_TIMEVNT3_Msk (0x1UL << HRTIM_RST1R_TIMEVNT3_Pos) /*!< 0x00004000 */
25819 #define HRTIM_RST1R_TIMEVNT3 HRTIM_RST1R_TIMEVNT3_Msk /*!< Timer event 3 */
25820 #define HRTIM_RST1R_TIMEVNT4_Pos (15U)
25821 #define HRTIM_RST1R_TIMEVNT4_Msk (0x1UL << HRTIM_RST1R_TIMEVNT4_Pos) /*!< 0x00008000 */
25822 #define HRTIM_RST1R_TIMEVNT4 HRTIM_RST1R_TIMEVNT4_Msk /*!< Timer event 4 */
25823 #define HRTIM_RST1R_TIMEVNT5_Pos (16U)
25824 #define HRTIM_RST1R_TIMEVNT5_Msk (0x1UL << HRTIM_RST1R_TIMEVNT5_Pos) /*!< 0x00010000 */
25825 #define HRTIM_RST1R_TIMEVNT5 HRTIM_RST1R_TIMEVNT5_Msk /*!< Timer event 5 */
25826 #define HRTIM_RST1R_TIMEVNT6_Pos (17U)
25827 #define HRTIM_RST1R_TIMEVNT6_Msk (0x1UL << HRTIM_RST1R_TIMEVNT6_Pos) /*!< 0x00020000 */
25828 #define HRTIM_RST1R_TIMEVNT6 HRTIM_RST1R_TIMEVNT6_Msk /*!< Timer event 6 */
25829 #define HRTIM_RST1R_TIMEVNT7_Pos (18U)
25830 #define HRTIM_RST1R_TIMEVNT7_Msk (0x1UL << HRTIM_RST1R_TIMEVNT7_Pos) /*!< 0x00040000 */
25831 #define HRTIM_RST1R_TIMEVNT7 HRTIM_RST1R_TIMEVNT7_Msk /*!< Timer event 7 */
25832 #define HRTIM_RST1R_TIMEVNT8_Pos (19U)
25833 #define HRTIM_RST1R_TIMEVNT8_Msk (0x1UL << HRTIM_RST1R_TIMEVNT8_Pos) /*!< 0x00080000 */
25834 #define HRTIM_RST1R_TIMEVNT8 HRTIM_RST1R_TIMEVNT8_Msk /*!< Timer event 8 */
25835 #define HRTIM_RST1R_TIMEVNT9_Pos (20U)
25836 #define HRTIM_RST1R_TIMEVNT9_Msk (0x1UL << HRTIM_RST1R_TIMEVNT9_Pos) /*!< 0x00100000 */
25837 #define HRTIM_RST1R_TIMEVNT9 HRTIM_RST1R_TIMEVNT9_Msk /*!< Timer event 9 */
25838
25839 #define HRTIM_RST1R_EXTVNT1_Pos (21U)
25840 #define HRTIM_RST1R_EXTVNT1_Msk (0x1UL << HRTIM_RST1R_EXTVNT1_Pos) /*!< 0x00200000 */
25841 #define HRTIM_RST1R_EXTVNT1 HRTIM_RST1R_EXTVNT1_Msk /*!< External event 1 */
25842 #define HRTIM_RST1R_EXTVNT2_Pos (22U)
25843 #define HRTIM_RST1R_EXTVNT2_Msk (0x1UL << HRTIM_RST1R_EXTVNT2_Pos) /*!< 0x00400000 */
25844 #define HRTIM_RST1R_EXTVNT2 HRTIM_RST1R_EXTVNT2_Msk /*!< External event 2 */
25845 #define HRTIM_RST1R_EXTVNT3_Pos (23U)
25846 #define HRTIM_RST1R_EXTVNT3_Msk (0x1UL << HRTIM_RST1R_EXTVNT3_Pos) /*!< 0x00800000 */
25847 #define HRTIM_RST1R_EXTVNT3 HRTIM_RST1R_EXTVNT3_Msk /*!< External event 3 */
25848 #define HRTIM_RST1R_EXTVNT4_Pos (24U)
25849 #define HRTIM_RST1R_EXTVNT4_Msk (0x1UL << HRTIM_RST1R_EXTVNT4_Pos) /*!< 0x01000000 */
25850 #define HRTIM_RST1R_EXTVNT4 HRTIM_RST1R_EXTVNT4_Msk /*!< External event 4 */
25851 #define HRTIM_RST1R_EXTVNT5_Pos (25U)
25852 #define HRTIM_RST1R_EXTVNT5_Msk (0x1UL << HRTIM_RST1R_EXTVNT5_Pos) /*!< 0x02000000 */
25853 #define HRTIM_RST1R_EXTVNT5 HRTIM_RST1R_EXTVNT5_Msk /*!< External event 5 */
25854 #define HRTIM_RST1R_EXTVNT6_Pos (26U)
25855 #define HRTIM_RST1R_EXTVNT6_Msk (0x1UL << HRTIM_RST1R_EXTVNT6_Pos) /*!< 0x04000000 */
25856 #define HRTIM_RST1R_EXTVNT6 HRTIM_RST1R_EXTVNT6_Msk /*!< External event 6 */
25857 #define HRTIM_RST1R_EXTVNT7_Pos (27U)
25858 #define HRTIM_RST1R_EXTVNT7_Msk (0x1UL << HRTIM_RST1R_EXTVNT7_Pos) /*!< 0x08000000 */
25859 #define HRTIM_RST1R_EXTVNT7 HRTIM_RST1R_EXTVNT7_Msk /*!< External event 7 */
25860 #define HRTIM_RST1R_EXTVNT8_Pos (28U)
25861 #define HRTIM_RST1R_EXTVNT8_Msk (0x1UL << HRTIM_RST1R_EXTVNT8_Pos) /*!< 0x10000000 */
25862 #define HRTIM_RST1R_EXTVNT8 HRTIM_RST1R_EXTVNT8_Msk /*!< External event 8 */
25863 #define HRTIM_RST1R_EXTVNT9_Pos (29U)
25864 #define HRTIM_RST1R_EXTVNT9_Msk (0x1UL << HRTIM_RST1R_EXTVNT9_Pos) /*!< 0x20000000 */
25865 #define HRTIM_RST1R_EXTVNT9 HRTIM_RST1R_EXTVNT9_Msk /*!< External event 9 */
25866 #define HRTIM_RST1R_EXTVNT10_Pos (30U)
25867 #define HRTIM_RST1R_EXTVNT10_Msk (0x1UL << HRTIM_RST1R_EXTVNT10_Pos) /*!< 0x40000000 */
25868 #define HRTIM_RST1R_EXTVNT10 HRTIM_RST1R_EXTVNT10_Msk /*!< External event 10 */
25869
25870 #define HRTIM_RST1R_UPDATE_Pos (31U)
25871 #define HRTIM_RST1R_UPDATE_Msk (0x1UL << HRTIM_RST1R_UPDATE_Pos) /*!< 0x80000000 */
25872 #define HRTIM_RST1R_UPDATE HRTIM_RST1R_UPDATE_Msk /*!< Register update (transfer preload to active) */
25873
25874
25875 /**** Bit definition for Slave Output 2 set register **************************/
25876 #define HRTIM_SET2R_SST_Pos (0U)
25877 #define HRTIM_SET2R_SST_Msk (0x1UL << HRTIM_SET2R_SST_Pos) /*!< 0x00000001 */
25878 #define HRTIM_SET2R_SST HRTIM_SET2R_SST_Msk /*!< software set trigger */
25879 #define HRTIM_SET2R_RESYNC_Pos (1U)
25880 #define HRTIM_SET2R_RESYNC_Msk (0x1UL << HRTIM_SET2R_RESYNC_Pos) /*!< 0x00000002 */
25881 #define HRTIM_SET2R_RESYNC HRTIM_SET2R_RESYNC_Msk /*!< Timer A resynchronization */
25882 #define HRTIM_SET2R_PER_Pos (2U)
25883 #define HRTIM_SET2R_PER_Msk (0x1UL << HRTIM_SET2R_PER_Pos) /*!< 0x00000004 */
25884 #define HRTIM_SET2R_PER HRTIM_SET2R_PER_Msk /*!< Timer A period */
25885 #define HRTIM_SET2R_CMP1_Pos (3U)
25886 #define HRTIM_SET2R_CMP1_Msk (0x1UL << HRTIM_SET2R_CMP1_Pos) /*!< 0x00000008 */
25887 #define HRTIM_SET2R_CMP1 HRTIM_SET2R_CMP1_Msk /*!< Timer A compare 1 */
25888 #define HRTIM_SET2R_CMP2_Pos (4U)
25889 #define HRTIM_SET2R_CMP2_Msk (0x1UL << HRTIM_SET2R_CMP2_Pos) /*!< 0x00000010 */
25890 #define HRTIM_SET2R_CMP2 HRTIM_SET2R_CMP2_Msk /*!< Timer A compare 2 */
25891 #define HRTIM_SET2R_CMP3_Pos (5U)
25892 #define HRTIM_SET2R_CMP3_Msk (0x1UL << HRTIM_SET2R_CMP3_Pos) /*!< 0x00000020 */
25893 #define HRTIM_SET2R_CMP3 HRTIM_SET2R_CMP3_Msk /*!< Timer A compare 3 */
25894 #define HRTIM_SET2R_CMP4_Pos (6U)
25895 #define HRTIM_SET2R_CMP4_Msk (0x1UL << HRTIM_SET2R_CMP4_Pos) /*!< 0x00000040 */
25896 #define HRTIM_SET2R_CMP4 HRTIM_SET2R_CMP4_Msk /*!< Timer A compare 4 */
25897
25898 #define HRTIM_SET2R_MSTPER_Pos (7U)
25899 #define HRTIM_SET2R_MSTPER_Msk (0x1UL << HRTIM_SET2R_MSTPER_Pos) /*!< 0x00000080 */
25900 #define HRTIM_SET2R_MSTPER HRTIM_SET2R_MSTPER_Msk /*!< Master period */
25901 #define HRTIM_SET2R_MSTCMP1_Pos (8U)
25902 #define HRTIM_SET2R_MSTCMP1_Msk (0x1UL << HRTIM_SET2R_MSTCMP1_Pos) /*!< 0x00000100 */
25903 #define HRTIM_SET2R_MSTCMP1 HRTIM_SET2R_MSTCMP1_Msk /*!< Master compare 1 */
25904 #define HRTIM_SET2R_MSTCMP2_Pos (9U)
25905 #define HRTIM_SET2R_MSTCMP2_Msk (0x1UL << HRTIM_SET2R_MSTCMP2_Pos) /*!< 0x00000200 */
25906 #define HRTIM_SET2R_MSTCMP2 HRTIM_SET2R_MSTCMP2_Msk /*!< Master compare 2 */
25907 #define HRTIM_SET2R_MSTCMP3_Pos (10U)
25908 #define HRTIM_SET2R_MSTCMP3_Msk (0x1UL << HRTIM_SET2R_MSTCMP3_Pos) /*!< 0x00000400 */
25909 #define HRTIM_SET2R_MSTCMP3 HRTIM_SET2R_MSTCMP3_Msk /*!< Master compare 3 */
25910 #define HRTIM_SET2R_MSTCMP4_Pos (11U)
25911 #define HRTIM_SET2R_MSTCMP4_Msk (0x1UL << HRTIM_SET2R_MSTCMP4_Pos) /*!< 0x00000800 */
25912 #define HRTIM_SET2R_MSTCMP4 HRTIM_SET2R_MSTCMP4_Msk /*!< Master compare 4 */
25913
25914 #define HRTIM_SET2R_TIMEVNT1_Pos (12U)
25915 #define HRTIM_SET2R_TIMEVNT1_Msk (0x1UL << HRTIM_SET2R_TIMEVNT1_Pos) /*!< 0x00001000 */
25916 #define HRTIM_SET2R_TIMEVNT1 HRTIM_SET2R_TIMEVNT1_Msk /*!< Timer event 1 */
25917 #define HRTIM_SET2R_TIMEVNT2_Pos (13U)
25918 #define HRTIM_SET2R_TIMEVNT2_Msk (0x1UL << HRTIM_SET2R_TIMEVNT2_Pos) /*!< 0x00002000 */
25919 #define HRTIM_SET2R_TIMEVNT2 HRTIM_SET2R_TIMEVNT2_Msk /*!< Timer event 2 */
25920 #define HRTIM_SET2R_TIMEVNT3_Pos (14U)
25921 #define HRTIM_SET2R_TIMEVNT3_Msk (0x1UL << HRTIM_SET2R_TIMEVNT3_Pos) /*!< 0x00004000 */
25922 #define HRTIM_SET2R_TIMEVNT3 HRTIM_SET2R_TIMEVNT3_Msk /*!< Timer event 3 */
25923 #define HRTIM_SET2R_TIMEVNT4_Pos (15U)
25924 #define HRTIM_SET2R_TIMEVNT4_Msk (0x1UL << HRTIM_SET2R_TIMEVNT4_Pos) /*!< 0x00008000 */
25925 #define HRTIM_SET2R_TIMEVNT4 HRTIM_SET2R_TIMEVNT4_Msk /*!< Timer event 4 */
25926 #define HRTIM_SET2R_TIMEVNT5_Pos (16U)
25927 #define HRTIM_SET2R_TIMEVNT5_Msk (0x1UL << HRTIM_SET2R_TIMEVNT5_Pos) /*!< 0x00010000 */
25928 #define HRTIM_SET2R_TIMEVNT5 HRTIM_SET2R_TIMEVNT5_Msk /*!< Timer event 5 */
25929 #define HRTIM_SET2R_TIMEVNT6_Pos (17U)
25930 #define HRTIM_SET2R_TIMEVNT6_Msk (0x1UL << HRTIM_SET2R_TIMEVNT6_Pos) /*!< 0x00020000 */
25931 #define HRTIM_SET2R_TIMEVNT6 HRTIM_SET2R_TIMEVNT6_Msk /*!< Timer event 6 */
25932 #define HRTIM_SET2R_TIMEVNT7_Pos (18U)
25933 #define HRTIM_SET2R_TIMEVNT7_Msk (0x1UL << HRTIM_SET2R_TIMEVNT7_Pos) /*!< 0x00040000 */
25934 #define HRTIM_SET2R_TIMEVNT7 HRTIM_SET2R_TIMEVNT7_Msk /*!< Timer event 7 */
25935 #define HRTIM_SET2R_TIMEVNT8_Pos (19U)
25936 #define HRTIM_SET2R_TIMEVNT8_Msk (0x1UL << HRTIM_SET2R_TIMEVNT8_Pos) /*!< 0x00080000 */
25937 #define HRTIM_SET2R_TIMEVNT8 HRTIM_SET2R_TIMEVNT8_Msk /*!< Timer event 8 */
25938 #define HRTIM_SET2R_TIMEVNT9_Pos (20U)
25939 #define HRTIM_SET2R_TIMEVNT9_Msk (0x1UL << HRTIM_SET2R_TIMEVNT9_Pos) /*!< 0x00100000 */
25940 #define HRTIM_SET2R_TIMEVNT9 HRTIM_SET2R_TIMEVNT9_Msk /*!< Timer event 9 */
25941
25942 #define HRTIM_SET2R_EXTVNT1_Pos (21U)
25943 #define HRTIM_SET2R_EXTVNT1_Msk (0x1UL << HRTIM_SET2R_EXTVNT1_Pos) /*!< 0x00200000 */
25944 #define HRTIM_SET2R_EXTVNT1 HRTIM_SET2R_EXTVNT1_Msk /*!< External event 1 */
25945 #define HRTIM_SET2R_EXTVNT2_Pos (22U)
25946 #define HRTIM_SET2R_EXTVNT2_Msk (0x1UL << HRTIM_SET2R_EXTVNT2_Pos) /*!< 0x00400000 */
25947 #define HRTIM_SET2R_EXTVNT2 HRTIM_SET2R_EXTVNT2_Msk /*!< External event 2 */
25948 #define HRTIM_SET2R_EXTVNT3_Pos (23U)
25949 #define HRTIM_SET2R_EXTVNT3_Msk (0x1UL << HRTIM_SET2R_EXTVNT3_Pos) /*!< 0x00800000 */
25950 #define HRTIM_SET2R_EXTVNT3 HRTIM_SET2R_EXTVNT3_Msk /*!< External event 3 */
25951 #define HRTIM_SET2R_EXTVNT4_Pos (24U)
25952 #define HRTIM_SET2R_EXTVNT4_Msk (0x1UL << HRTIM_SET2R_EXTVNT4_Pos) /*!< 0x01000000 */
25953 #define HRTIM_SET2R_EXTVNT4 HRTIM_SET2R_EXTVNT4_Msk /*!< External event 4 */
25954 #define HRTIM_SET2R_EXTVNT5_Pos (25U)
25955 #define HRTIM_SET2R_EXTVNT5_Msk (0x1UL << HRTIM_SET2R_EXTVNT5_Pos) /*!< 0x02000000 */
25956 #define HRTIM_SET2R_EXTVNT5 HRTIM_SET2R_EXTVNT5_Msk /*!< External event 5 */
25957 #define HRTIM_SET2R_EXTVNT6_Pos (26U)
25958 #define HRTIM_SET2R_EXTVNT6_Msk (0x1UL << HRTIM_SET2R_EXTVNT6_Pos) /*!< 0x04000000 */
25959 #define HRTIM_SET2R_EXTVNT6 HRTIM_SET2R_EXTVNT6_Msk /*!< External event 6 */
25960 #define HRTIM_SET2R_EXTVNT7_Pos (27U)
25961 #define HRTIM_SET2R_EXTVNT7_Msk (0x1UL << HRTIM_SET2R_EXTVNT7_Pos) /*!< 0x08000000 */
25962 #define HRTIM_SET2R_EXTVNT7 HRTIM_SET2R_EXTVNT7_Msk /*!< External event 7 */
25963 #define HRTIM_SET2R_EXTVNT8_Pos (28U)
25964 #define HRTIM_SET2R_EXTVNT8_Msk (0x1UL << HRTIM_SET2R_EXTVNT8_Pos) /*!< 0x10000000 */
25965 #define HRTIM_SET2R_EXTVNT8 HRTIM_SET2R_EXTVNT8_Msk /*!< External event 8 */
25966 #define HRTIM_SET2R_EXTVNT9_Pos (29U)
25967 #define HRTIM_SET2R_EXTVNT9_Msk (0x1UL << HRTIM_SET2R_EXTVNT9_Pos) /*!< 0x20000000 */
25968 #define HRTIM_SET2R_EXTVNT9 HRTIM_SET2R_EXTVNT9_Msk /*!< External event 9 */
25969 #define HRTIM_SET2R_EXTVNT10_Pos (30U)
25970 #define HRTIM_SET2R_EXTVNT10_Msk (0x1UL << HRTIM_SET2R_EXTVNT10_Pos) /*!< 0x40000000 */
25971 #define HRTIM_SET2R_EXTVNT10 HRTIM_SET2R_EXTVNT10_Msk /*!< External event 10 */
25972
25973 #define HRTIM_SET2R_UPDATE_Pos (31U)
25974 #define HRTIM_SET2R_UPDATE_Msk (0x1UL << HRTIM_SET2R_UPDATE_Pos) /*!< 0x80000000 */
25975 #define HRTIM_SET2R_UPDATE HRTIM_SET2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
25976
25977 /**** Bit definition for Slave Output 2 reset register ************************/
25978 #define HRTIM_RST2R_SRT_Pos (0U)
25979 #define HRTIM_RST2R_SRT_Msk (0x1UL << HRTIM_RST2R_SRT_Pos) /*!< 0x00000001 */
25980 #define HRTIM_RST2R_SRT HRTIM_RST2R_SRT_Msk /*!< software reset trigger */
25981 #define HRTIM_RST2R_RESYNC_Pos (1U)
25982 #define HRTIM_RST2R_RESYNC_Msk (0x1UL << HRTIM_RST2R_RESYNC_Pos) /*!< 0x00000002 */
25983 #define HRTIM_RST2R_RESYNC HRTIM_RST2R_RESYNC_Msk /*!< Timer A resynchronization */
25984 #define HRTIM_RST2R_PER_Pos (2U)
25985 #define HRTIM_RST2R_PER_Msk (0x1UL << HRTIM_RST2R_PER_Pos) /*!< 0x00000004 */
25986 #define HRTIM_RST2R_PER HRTIM_RST2R_PER_Msk /*!< Timer A period */
25987 #define HRTIM_RST2R_CMP1_Pos (3U)
25988 #define HRTIM_RST2R_CMP1_Msk (0x1UL << HRTIM_RST2R_CMP1_Pos) /*!< 0x00000008 */
25989 #define HRTIM_RST2R_CMP1 HRTIM_RST2R_CMP1_Msk /*!< Timer A compare 1 */
25990 #define HRTIM_RST2R_CMP2_Pos (4U)
25991 #define HRTIM_RST2R_CMP2_Msk (0x1UL << HRTIM_RST2R_CMP2_Pos) /*!< 0x00000010 */
25992 #define HRTIM_RST2R_CMP2 HRTIM_RST2R_CMP2_Msk /*!< Timer A compare 2 */
25993 #define HRTIM_RST2R_CMP3_Pos (5U)
25994 #define HRTIM_RST2R_CMP3_Msk (0x1UL << HRTIM_RST2R_CMP3_Pos) /*!< 0x00000020 */
25995 #define HRTIM_RST2R_CMP3 HRTIM_RST2R_CMP3_Msk /*!< Timer A compare 3 */
25996 #define HRTIM_RST2R_CMP4_Pos (6U)
25997 #define HRTIM_RST2R_CMP4_Msk (0x1UL << HRTIM_RST2R_CMP4_Pos) /*!< 0x00000040 */
25998 #define HRTIM_RST2R_CMP4 HRTIM_RST2R_CMP4_Msk /*!< Timer A compare 4 */
25999
26000 #define HRTIM_RST2R_MSTPER_Pos (7U)
26001 #define HRTIM_RST2R_MSTPER_Msk (0x1UL << HRTIM_RST2R_MSTPER_Pos) /*!< 0x00000080 */
26002 #define HRTIM_RST2R_MSTPER HRTIM_RST2R_MSTPER_Msk /*!< Master period */
26003 #define HRTIM_RST2R_MSTCMP1_Pos (8U)
26004 #define HRTIM_RST2R_MSTCMP1_Msk (0x1UL << HRTIM_RST2R_MSTCMP1_Pos) /*!< 0x00000100 */
26005 #define HRTIM_RST2R_MSTCMP1 HRTIM_RST2R_MSTCMP1_Msk /*!< Master compare 1 */
26006 #define HRTIM_RST2R_MSTCMP2_Pos (9U)
26007 #define HRTIM_RST2R_MSTCMP2_Msk (0x1UL << HRTIM_RST2R_MSTCMP2_Pos) /*!< 0x00000200 */
26008 #define HRTIM_RST2R_MSTCMP2 HRTIM_RST2R_MSTCMP2_Msk /*!< Master compare 2 */
26009 #define HRTIM_RST2R_MSTCMP3_Pos (10U)
26010 #define HRTIM_RST2R_MSTCMP3_Msk (0x1UL << HRTIM_RST2R_MSTCMP3_Pos) /*!< 0x00000400 */
26011 #define HRTIM_RST2R_MSTCMP3 HRTIM_RST2R_MSTCMP3_Msk /*!< Master compare 3 */
26012 #define HRTIM_RST2R_MSTCMP4_Pos (11U)
26013 #define HRTIM_RST2R_MSTCMP4_Msk (0x1UL << HRTIM_RST2R_MSTCMP4_Pos) /*!< 0x00000800 */
26014 #define HRTIM_RST2R_MSTCMP4 HRTIM_RST2R_MSTCMP4_Msk /*!< Master compare 4 */
26015
26016 #define HRTIM_RST2R_TIMEVNT1_Pos (12U)
26017 #define HRTIM_RST2R_TIMEVNT1_Msk (0x1UL << HRTIM_RST2R_TIMEVNT1_Pos) /*!< 0x00001000 */
26018 #define HRTIM_RST2R_TIMEVNT1 HRTIM_RST2R_TIMEVNT1_Msk /*!< Timer event 1 */
26019 #define HRTIM_RST2R_TIMEVNT2_Pos (13U)
26020 #define HRTIM_RST2R_TIMEVNT2_Msk (0x1UL << HRTIM_RST2R_TIMEVNT2_Pos) /*!< 0x00002000 */
26021 #define HRTIM_RST2R_TIMEVNT2 HRTIM_RST2R_TIMEVNT2_Msk /*!< Timer event 2 */
26022 #define HRTIM_RST2R_TIMEVNT3_Pos (14U)
26023 #define HRTIM_RST2R_TIMEVNT3_Msk (0x1UL << HRTIM_RST2R_TIMEVNT3_Pos) /*!< 0x00004000 */
26024 #define HRTIM_RST2R_TIMEVNT3 HRTIM_RST2R_TIMEVNT3_Msk /*!< Timer event 3 */
26025 #define HRTIM_RST2R_TIMEVNT4_Pos (15U)
26026 #define HRTIM_RST2R_TIMEVNT4_Msk (0x1UL << HRTIM_RST2R_TIMEVNT4_Pos) /*!< 0x00008000 */
26027 #define HRTIM_RST2R_TIMEVNT4 HRTIM_RST2R_TIMEVNT4_Msk /*!< Timer event 4 */
26028 #define HRTIM_RST2R_TIMEVNT5_Pos (16U)
26029 #define HRTIM_RST2R_TIMEVNT5_Msk (0x1UL << HRTIM_RST2R_TIMEVNT5_Pos) /*!< 0x00010000 */
26030 #define HRTIM_RST2R_TIMEVNT5 HRTIM_RST2R_TIMEVNT5_Msk /*!< Timer event 5 */
26031 #define HRTIM_RST2R_TIMEVNT6_Pos (17U)
26032 #define HRTIM_RST2R_TIMEVNT6_Msk (0x1UL << HRTIM_RST2R_TIMEVNT6_Pos) /*!< 0x00020000 */
26033 #define HRTIM_RST2R_TIMEVNT6 HRTIM_RST2R_TIMEVNT6_Msk /*!< Timer event 6 */
26034 #define HRTIM_RST2R_TIMEVNT7_Pos (18U)
26035 #define HRTIM_RST2R_TIMEVNT7_Msk (0x1UL << HRTIM_RST2R_TIMEVNT7_Pos) /*!< 0x00040000 */
26036 #define HRTIM_RST2R_TIMEVNT7 HRTIM_RST2R_TIMEVNT7_Msk /*!< Timer event 7 */
26037 #define HRTIM_RST2R_TIMEVNT8_Pos (19U)
26038 #define HRTIM_RST2R_TIMEVNT8_Msk (0x1UL << HRTIM_RST2R_TIMEVNT8_Pos) /*!< 0x00080000 */
26039 #define HRTIM_RST2R_TIMEVNT8 HRTIM_RST2R_TIMEVNT8_Msk /*!< Timer event 8 */
26040 #define HRTIM_RST2R_TIMEVNT9_Pos (20U)
26041 #define HRTIM_RST2R_TIMEVNT9_Msk (0x1UL << HRTIM_RST2R_TIMEVNT9_Pos) /*!< 0x00100000 */
26042 #define HRTIM_RST2R_TIMEVNT9 HRTIM_RST2R_TIMEVNT9_Msk /*!< Timer event 9 */
26043
26044 #define HRTIM_RST2R_EXTVNT1_Pos (21U)
26045 #define HRTIM_RST2R_EXTVNT1_Msk (0x1UL << HRTIM_RST2R_EXTVNT1_Pos) /*!< 0x00200000 */
26046 #define HRTIM_RST2R_EXTVNT1 HRTIM_RST2R_EXTVNT1_Msk /*!< External event 1 */
26047 #define HRTIM_RST2R_EXTVNT2_Pos (22U)
26048 #define HRTIM_RST2R_EXTVNT2_Msk (0x1UL << HRTIM_RST2R_EXTVNT2_Pos) /*!< 0x00400000 */
26049 #define HRTIM_RST2R_EXTVNT2 HRTIM_RST2R_EXTVNT2_Msk /*!< External event 2 */
26050 #define HRTIM_RST2R_EXTVNT3_Pos (23U)
26051 #define HRTIM_RST2R_EXTVNT3_Msk (0x1UL << HRTIM_RST2R_EXTVNT3_Pos) /*!< 0x00800000 */
26052 #define HRTIM_RST2R_EXTVNT3 HRTIM_RST2R_EXTVNT3_Msk /*!< External event 3 */
26053 #define HRTIM_RST2R_EXTVNT4_Pos (24U)
26054 #define HRTIM_RST2R_EXTVNT4_Msk (0x1UL << HRTIM_RST2R_EXTVNT4_Pos) /*!< 0x01000000 */
26055 #define HRTIM_RST2R_EXTVNT4 HRTIM_RST2R_EXTVNT4_Msk /*!< External event 4 */
26056 #define HRTIM_RST2R_EXTVNT5_Pos (25U)
26057 #define HRTIM_RST2R_EXTVNT5_Msk (0x1UL << HRTIM_RST2R_EXTVNT5_Pos) /*!< 0x02000000 */
26058 #define HRTIM_RST2R_EXTVNT5 HRTIM_RST2R_EXTVNT5_Msk /*!< External event 5 */
26059 #define HRTIM_RST2R_EXTVNT6_Pos (26U)
26060 #define HRTIM_RST2R_EXTVNT6_Msk (0x1UL << HRTIM_RST2R_EXTVNT6_Pos) /*!< 0x04000000 */
26061 #define HRTIM_RST2R_EXTVNT6 HRTIM_RST2R_EXTVNT6_Msk /*!< External event 6 */
26062 #define HRTIM_RST2R_EXTVNT7_Pos (27U)
26063 #define HRTIM_RST2R_EXTVNT7_Msk (0x1UL << HRTIM_RST2R_EXTVNT7_Pos) /*!< 0x08000000 */
26064 #define HRTIM_RST2R_EXTVNT7 HRTIM_RST2R_EXTVNT7_Msk /*!< External event 7 */
26065 #define HRTIM_RST2R_EXTVNT8_Pos (28U)
26066 #define HRTIM_RST2R_EXTVNT8_Msk (0x1UL << HRTIM_RST2R_EXTVNT8_Pos) /*!< 0x10000000 */
26067 #define HRTIM_RST2R_EXTVNT8 HRTIM_RST2R_EXTVNT8_Msk /*!< External event 8 */
26068 #define HRTIM_RST2R_EXTVNT9_Pos (29U)
26069 #define HRTIM_RST2R_EXTVNT9_Msk (0x1UL << HRTIM_RST2R_EXTVNT9_Pos) /*!< 0x20000000 */
26070 #define HRTIM_RST2R_EXTVNT9 HRTIM_RST2R_EXTVNT9_Msk /*!< External event 9 */
26071 #define HRTIM_RST2R_EXTVNT10_Pos (30U)
26072 #define HRTIM_RST2R_EXTVNT10_Msk (0x1UL << HRTIM_RST2R_EXTVNT10_Pos) /*!< 0x40000000 */
26073 #define HRTIM_RST2R_EXTVNT10 HRTIM_RST2R_EXTVNT10_Msk /*!< External event 10 */
26074
26075 #define HRTIM_RST2R_UPDATE_Pos (31U)
26076 #define HRTIM_RST2R_UPDATE_Msk (0x1UL << HRTIM_RST2R_UPDATE_Pos) /*!< 0x80000000 */
26077 #define HRTIM_RST2R_UPDATE HRTIM_RST2R_UPDATE_Msk /*!< Register update (transfer preload to active) */
26078
26079 /**** Bit definition for Slave external event filtering register 1 ***********/
26080 #define HRTIM_EEFR1_EE1LTCH_Pos (0U)
26081 #define HRTIM_EEFR1_EE1LTCH_Msk (0x1UL << HRTIM_EEFR1_EE1LTCH_Pos) /*!< 0x00000001 */
26082 #define HRTIM_EEFR1_EE1LTCH HRTIM_EEFR1_EE1LTCH_Msk /*!< External Event 1 latch */
26083 #define HRTIM_EEFR1_EE1FLTR_Pos (1U)
26084 #define HRTIM_EEFR1_EE1FLTR_Msk (0xFUL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x0000001E */
26085 #define HRTIM_EEFR1_EE1FLTR HRTIM_EEFR1_EE1FLTR_Msk /*!< External Event 1 filter mask */
26086 #define HRTIM_EEFR1_EE1FLTR_0 (0x1UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000002 */
26087 #define HRTIM_EEFR1_EE1FLTR_1 (0x2UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000004 */
26088 #define HRTIM_EEFR1_EE1FLTR_2 (0x4UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000008 */
26089 #define HRTIM_EEFR1_EE1FLTR_3 (0x8UL << HRTIM_EEFR1_EE1FLTR_Pos) /*!< 0x00000010 */
26090
26091 #define HRTIM_EEFR1_EE2LTCH_Pos (6U)
26092 #define HRTIM_EEFR1_EE2LTCH_Msk (0x1UL << HRTIM_EEFR1_EE2LTCH_Pos) /*!< 0x00000040 */
26093 #define HRTIM_EEFR1_EE2LTCH HRTIM_EEFR1_EE2LTCH_Msk /*!< External Event 2 latch */
26094 #define HRTIM_EEFR1_EE2FLTR_Pos (7U)
26095 #define HRTIM_EEFR1_EE2FLTR_Msk (0xFUL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000780 */
26096 #define HRTIM_EEFR1_EE2FLTR HRTIM_EEFR1_EE2FLTR_Msk /*!< External Event 2 filter mask */
26097 #define HRTIM_EEFR1_EE2FLTR_0 (0x1UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000080 */
26098 #define HRTIM_EEFR1_EE2FLTR_1 (0x2UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000100 */
26099 #define HRTIM_EEFR1_EE2FLTR_2 (0x4UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000200 */
26100 #define HRTIM_EEFR1_EE2FLTR_3 (0x8UL << HRTIM_EEFR1_EE2FLTR_Pos) /*!< 0x00000400 */
26101
26102 #define HRTIM_EEFR1_EE3LTCH_Pos (12U)
26103 #define HRTIM_EEFR1_EE3LTCH_Msk (0x1UL << HRTIM_EEFR1_EE3LTCH_Pos) /*!< 0x00001000 */
26104 #define HRTIM_EEFR1_EE3LTCH HRTIM_EEFR1_EE3LTCH_Msk /*!< External Event 3 latch */
26105 #define HRTIM_EEFR1_EE3FLTR_Pos (13U)
26106 #define HRTIM_EEFR1_EE3FLTR_Msk (0xFUL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x0001E000 */
26107 #define HRTIM_EEFR1_EE3FLTR HRTIM_EEFR1_EE3FLTR_Msk /*!< External Event 3 filter mask */
26108 #define HRTIM_EEFR1_EE3FLTR_0 (0x1UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00002000 */
26109 #define HRTIM_EEFR1_EE3FLTR_1 (0x2UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00004000 */
26110 #define HRTIM_EEFR1_EE3FLTR_2 (0x4UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00008000 */
26111 #define HRTIM_EEFR1_EE3FLTR_3 (0x8UL << HRTIM_EEFR1_EE3FLTR_Pos) /*!< 0x00010000 */
26112
26113 #define HRTIM_EEFR1_EE4LTCH_Pos (18U)
26114 #define HRTIM_EEFR1_EE4LTCH_Msk (0x1UL << HRTIM_EEFR1_EE4LTCH_Pos) /*!< 0x00040000 */
26115 #define HRTIM_EEFR1_EE4LTCH HRTIM_EEFR1_EE4LTCH_Msk /*!< External Event 4 latch */
26116 #define HRTIM_EEFR1_EE4FLTR_Pos (19U)
26117 #define HRTIM_EEFR1_EE4FLTR_Msk (0xFUL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00780000 */
26118 #define HRTIM_EEFR1_EE4FLTR HRTIM_EEFR1_EE4FLTR_Msk /*!< External Event 4 filter mask */
26119 #define HRTIM_EEFR1_EE4FLTR_0 (0x1UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00080000 */
26120 #define HRTIM_EEFR1_EE4FLTR_1 (0x2UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00100000 */
26121 #define HRTIM_EEFR1_EE4FLTR_2 (0x4UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00200000 */
26122 #define HRTIM_EEFR1_EE4FLTR_3 (0x8UL << HRTIM_EEFR1_EE4FLTR_Pos) /*!< 0x00400000 */
26123
26124 #define HRTIM_EEFR1_EE5LTCH_Pos (24U)
26125 #define HRTIM_EEFR1_EE5LTCH_Msk (0x1UL << HRTIM_EEFR1_EE5LTCH_Pos) /*!< 0x01000000 */
26126 #define HRTIM_EEFR1_EE5LTCH HRTIM_EEFR1_EE5LTCH_Msk /*!< External Event 5 latch */
26127 #define HRTIM_EEFR1_EE5FLTR_Pos (25U)
26128 #define HRTIM_EEFR1_EE5FLTR_Msk (0xFUL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x1E000000 */
26129 #define HRTIM_EEFR1_EE5FLTR HRTIM_EEFR1_EE5FLTR_Msk /*!< External Event 5 filter mask */
26130 #define HRTIM_EEFR1_EE5FLTR_0 (0x1UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x02000000 */
26131 #define HRTIM_EEFR1_EE5FLTR_1 (0x2UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x04000000 */
26132 #define HRTIM_EEFR1_EE5FLTR_2 (0x4UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x08000000 */
26133 #define HRTIM_EEFR1_EE5FLTR_3 (0x8UL << HRTIM_EEFR1_EE5FLTR_Pos) /*!< 0x10000000 */
26134
26135 /**** Bit definition for Slave external event filtering register 2 ***********/
26136 #define HRTIM_EEFR2_EE6LTCH_Pos (0U)
26137 #define HRTIM_EEFR2_EE6LTCH_Msk (0x1UL << HRTIM_EEFR2_EE6LTCH_Pos) /*!< 0x00000001 */
26138 #define HRTIM_EEFR2_EE6LTCH HRTIM_EEFR2_EE6LTCH_Msk /*!< External Event 6 latch */
26139 #define HRTIM_EEFR2_EE6FLTR_Pos (1U)
26140 #define HRTIM_EEFR2_EE6FLTR_Msk (0xFUL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x0000001E */
26141 #define HRTIM_EEFR2_EE6FLTR HRTIM_EEFR2_EE6FLTR_Msk /*!< External Event 6 filter mask */
26142 #define HRTIM_EEFR2_EE6FLTR_0 (0x1UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000002 */
26143 #define HRTIM_EEFR2_EE6FLTR_1 (0x2UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000004 */
26144 #define HRTIM_EEFR2_EE6FLTR_2 (0x4UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000008 */
26145 #define HRTIM_EEFR2_EE6FLTR_3 (0x8UL << HRTIM_EEFR2_EE6FLTR_Pos) /*!< 0x00000010 */
26146
26147 #define HRTIM_EEFR2_EE7LTCH_Pos (6U)
26148 #define HRTIM_EEFR2_EE7LTCH_Msk (0x1UL << HRTIM_EEFR2_EE7LTCH_Pos) /*!< 0x00000040 */
26149 #define HRTIM_EEFR2_EE7LTCH HRTIM_EEFR2_EE7LTCH_Msk /*!< External Event 7 latch */
26150 #define HRTIM_EEFR2_EE7FLTR_Pos (7U)
26151 #define HRTIM_EEFR2_EE7FLTR_Msk (0xFUL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000780 */
26152 #define HRTIM_EEFR2_EE7FLTR HRTIM_EEFR2_EE7FLTR_Msk /*!< External Event 7 filter mask */
26153 #define HRTIM_EEFR2_EE7FLTR_0 (0x1UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000080 */
26154 #define HRTIM_EEFR2_EE7FLTR_1 (0x2UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000100 */
26155 #define HRTIM_EEFR2_EE7FLTR_2 (0x4UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000200 */
26156 #define HRTIM_EEFR2_EE7FLTR_3 (0x8UL << HRTIM_EEFR2_EE7FLTR_Pos) /*!< 0x00000400 */
26157
26158 #define HRTIM_EEFR2_EE8LTCH_Pos (12U)
26159 #define HRTIM_EEFR2_EE8LTCH_Msk (0x1UL << HRTIM_EEFR2_EE8LTCH_Pos) /*!< 0x00001000 */
26160 #define HRTIM_EEFR2_EE8LTCH HRTIM_EEFR2_EE8LTCH_Msk /*!< External Event 8 latch */
26161 #define HRTIM_EEFR2_EE8FLTR_Pos (13U)
26162 #define HRTIM_EEFR2_EE8FLTR_Msk (0xFUL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x0001E000 */
26163 #define HRTIM_EEFR2_EE8FLTR HRTIM_EEFR2_EE8FLTR_Msk /*!< External Event 8 filter mask */
26164 #define HRTIM_EEFR2_EE8FLTR_0 (0x1UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00002000 */
26165 #define HRTIM_EEFR2_EE8FLTR_1 (0x2UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00004000 */
26166 #define HRTIM_EEFR2_EE8FLTR_2 (0x4UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00008000 */
26167 #define HRTIM_EEFR2_EE8FLTR_3 (0x8UL << HRTIM_EEFR2_EE8FLTR_Pos) /*!< 0x00010000 */
26168
26169 #define HRTIM_EEFR2_EE9LTCH_Pos (18U)
26170 #define HRTIM_EEFR2_EE9LTCH_Msk (0x1UL << HRTIM_EEFR2_EE9LTCH_Pos) /*!< 0x00040000 */
26171 #define HRTIM_EEFR2_EE9LTCH HRTIM_EEFR2_EE9LTCH_Msk /*!< External Event 9 latch */
26172 #define HRTIM_EEFR2_EE9FLTR_Pos (19U)
26173 #define HRTIM_EEFR2_EE9FLTR_Msk (0xFUL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00780000 */
26174 #define HRTIM_EEFR2_EE9FLTR HRTIM_EEFR2_EE9FLTR_Msk /*!< External Event 9 filter mask */
26175 #define HRTIM_EEFR2_EE9FLTR_0 (0x1UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00080000 */
26176 #define HRTIM_EEFR2_EE9FLTR_1 (0x2UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00100000 */
26177 #define HRTIM_EEFR2_EE9FLTR_2 (0x4UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00200000 */
26178 #define HRTIM_EEFR2_EE9FLTR_3 (0x8UL << HRTIM_EEFR2_EE9FLTR_Pos) /*!< 0x00400000 */
26179
26180 #define HRTIM_EEFR2_EE10LTCH_Pos (24U)
26181 #define HRTIM_EEFR2_EE10LTCH_Msk (0x1UL << HRTIM_EEFR2_EE10LTCH_Pos) /*!< 0x01000000 */
26182 #define HRTIM_EEFR2_EE10LTCH HRTIM_EEFR2_EE10LTCH_Msk /*!< External Event 10 latch */
26183 #define HRTIM_EEFR2_EE10FLTR_Pos (25U)
26184 #define HRTIM_EEFR2_EE10FLTR_Msk (0xFUL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x1E000000 */
26185 #define HRTIM_EEFR2_EE10FLTR HRTIM_EEFR2_EE10FLTR_Msk /*!< External Event 10 filter mask */
26186 #define HRTIM_EEFR2_EE10FLTR_0 (0x1UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x02000000 */
26187 #define HRTIM_EEFR2_EE10FLTR_1 (0x2UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x04000000 */
26188 #define HRTIM_EEFR2_EE10FLTR_2 (0x4UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x08000000 */
26189 #define HRTIM_EEFR2_EE10FLTR_3 (0x8UL << HRTIM_EEFR2_EE10FLTR_Pos) /*!< 0x10000000 */
26190
26191 /**** Bit definition for Slave Timer reset register ***************************/
26192 #define HRTIM_RSTR_UPDATE_Pos (1U)
26193 #define HRTIM_RSTR_UPDATE_Msk (0x1UL << HRTIM_RSTR_UPDATE_Pos) /*!< 0x00000002 */
26194 #define HRTIM_RSTR_UPDATE HRTIM_RSTR_UPDATE_Msk /*!< Timer update */
26195 #define HRTIM_RSTR_CMP2_Pos (2U)
26196 #define HRTIM_RSTR_CMP2_Msk (0x1UL << HRTIM_RSTR_CMP2_Pos) /*!< 0x00000004 */
26197 #define HRTIM_RSTR_CMP2 HRTIM_RSTR_CMP2_Msk /*!< Timer compare2 */
26198 #define HRTIM_RSTR_CMP4_Pos (3U)
26199 #define HRTIM_RSTR_CMP4_Msk (0x1UL << HRTIM_RSTR_CMP4_Pos) /*!< 0x00000008 */
26200 #define HRTIM_RSTR_CMP4 HRTIM_RSTR_CMP4_Msk /*!< Timer compare4 */
26201
26202 #define HRTIM_RSTR_MSTPER_Pos (4U)
26203 #define HRTIM_RSTR_MSTPER_Msk (0x1UL << HRTIM_RSTR_MSTPER_Pos) /*!< 0x00000010 */
26204 #define HRTIM_RSTR_MSTPER HRTIM_RSTR_MSTPER_Msk /*!< Master period */
26205 #define HRTIM_RSTR_MSTCMP1_Pos (5U)
26206 #define HRTIM_RSTR_MSTCMP1_Msk (0x1UL << HRTIM_RSTR_MSTCMP1_Pos) /*!< 0x00000020 */
26207 #define HRTIM_RSTR_MSTCMP1 HRTIM_RSTR_MSTCMP1_Msk /*!< Master compare1 */
26208 #define HRTIM_RSTR_MSTCMP2_Pos (6U)
26209 #define HRTIM_RSTR_MSTCMP2_Msk (0x1UL << HRTIM_RSTR_MSTCMP2_Pos) /*!< 0x00000040 */
26210 #define HRTIM_RSTR_MSTCMP2 HRTIM_RSTR_MSTCMP2_Msk /*!< Master compare2 */
26211 #define HRTIM_RSTR_MSTCMP3_Pos (7U)
26212 #define HRTIM_RSTR_MSTCMP3_Msk (0x1UL << HRTIM_RSTR_MSTCMP3_Pos) /*!< 0x00000080 */
26213 #define HRTIM_RSTR_MSTCMP3 HRTIM_RSTR_MSTCMP3_Msk /*!< Master compare3 */
26214 #define HRTIM_RSTR_MSTCMP4_Pos (8U)
26215 #define HRTIM_RSTR_MSTCMP4_Msk (0x1UL << HRTIM_RSTR_MSTCMP4_Pos) /*!< 0x00000100 */
26216 #define HRTIM_RSTR_MSTCMP4 HRTIM_RSTR_MSTCMP4_Msk /*!< Master compare4 */
26217
26218 #define HRTIM_RSTR_EXTEVNT1_Pos (9U)
26219 #define HRTIM_RSTR_EXTEVNT1_Msk (0x1UL << HRTIM_RSTR_EXTEVNT1_Pos) /*!< 0x00000200 */
26220 #define HRTIM_RSTR_EXTEVNT1 HRTIM_RSTR_EXTEVNT1_Msk /*!< External event 1 */
26221 #define HRTIM_RSTR_EXTEVNT2_Pos (10U)
26222 #define HRTIM_RSTR_EXTEVNT2_Msk (0x1UL << HRTIM_RSTR_EXTEVNT2_Pos) /*!< 0x00000400 */
26223 #define HRTIM_RSTR_EXTEVNT2 HRTIM_RSTR_EXTEVNT2_Msk /*!< External event 2 */
26224 #define HRTIM_RSTR_EXTEVNT3_Pos (11U)
26225 #define HRTIM_RSTR_EXTEVNT3_Msk (0x1UL << HRTIM_RSTR_EXTEVNT3_Pos) /*!< 0x00000800 */
26226 #define HRTIM_RSTR_EXTEVNT3 HRTIM_RSTR_EXTEVNT3_Msk /*!< External event 3 */
26227 #define HRTIM_RSTR_EXTEVNT4_Pos (12U)
26228 #define HRTIM_RSTR_EXTEVNT4_Msk (0x1UL << HRTIM_RSTR_EXTEVNT4_Pos) /*!< 0x00001000 */
26229 #define HRTIM_RSTR_EXTEVNT4 HRTIM_RSTR_EXTEVNT4_Msk /*!< External event 4 */
26230 #define HRTIM_RSTR_EXTEVNT5_Pos (13U)
26231 #define HRTIM_RSTR_EXTEVNT5_Msk (0x1UL << HRTIM_RSTR_EXTEVNT5_Pos) /*!< 0x00002000 */
26232 #define HRTIM_RSTR_EXTEVNT5 HRTIM_RSTR_EXTEVNT5_Msk /*!< External event 5 */
26233 #define HRTIM_RSTR_EXTEVNT6_Pos (14U)
26234 #define HRTIM_RSTR_EXTEVNT6_Msk (0x1UL << HRTIM_RSTR_EXTEVNT6_Pos) /*!< 0x00004000 */
26235 #define HRTIM_RSTR_EXTEVNT6 HRTIM_RSTR_EXTEVNT6_Msk /*!< External event 6 */
26236 #define HRTIM_RSTR_EXTEVNT7_Pos (15U)
26237 #define HRTIM_RSTR_EXTEVNT7_Msk (0x1UL << HRTIM_RSTR_EXTEVNT7_Pos) /*!< 0x00008000 */
26238 #define HRTIM_RSTR_EXTEVNT7 HRTIM_RSTR_EXTEVNT7_Msk /*!< External event 7 */
26239 #define HRTIM_RSTR_EXTEVNT8_Pos (16U)
26240 #define HRTIM_RSTR_EXTEVNT8_Msk (0x1UL << HRTIM_RSTR_EXTEVNT8_Pos) /*!< 0x00010000 */
26241 #define HRTIM_RSTR_EXTEVNT8 HRTIM_RSTR_EXTEVNT8_Msk /*!< External event 8 */
26242 #define HRTIM_RSTR_EXTEVNT9_Pos (17U)
26243 #define HRTIM_RSTR_EXTEVNT9_Msk (0x1UL << HRTIM_RSTR_EXTEVNT9_Pos) /*!< 0x00020000 */
26244 #define HRTIM_RSTR_EXTEVNT9 HRTIM_RSTR_EXTEVNT9_Msk /*!< External event 9 */
26245 #define HRTIM_RSTR_EXTEVNT10_Pos (18U)
26246 #define HRTIM_RSTR_EXTEVNT10_Msk (0x1UL << HRTIM_RSTR_EXTEVNT10_Pos) /*!< 0x00040000 */
26247 #define HRTIM_RSTR_EXTEVNT10 HRTIM_RSTR_EXTEVNT10_Msk /*!< External event 10 */
26248
26249 #define HRTIM_RSTR_TIMBCMP1_Pos (19U)
26250 #define HRTIM_RSTR_TIMBCMP1_Msk (0x1UL << HRTIM_RSTR_TIMBCMP1_Pos) /*!< 0x00080000 */
26251 #define HRTIM_RSTR_TIMBCMP1 HRTIM_RSTR_TIMBCMP1_Msk /*!< Timer B compare 1 */
26252 #define HRTIM_RSTR_TIMBCMP2_Pos (20U)
26253 #define HRTIM_RSTR_TIMBCMP2_Msk (0x1UL << HRTIM_RSTR_TIMBCMP2_Pos) /*!< 0x00100000 */
26254 #define HRTIM_RSTR_TIMBCMP2 HRTIM_RSTR_TIMBCMP2_Msk /*!< Timer B compare 2 */
26255 #define HRTIM_RSTR_TIMBCMP4_Pos (21U)
26256 #define HRTIM_RSTR_TIMBCMP4_Msk (0x1UL << HRTIM_RSTR_TIMBCMP4_Pos) /*!< 0x00200000 */
26257 #define HRTIM_RSTR_TIMBCMP4 HRTIM_RSTR_TIMBCMP4_Msk /*!< Timer B compare 4 */
26258
26259 #define HRTIM_RSTR_TIMCCMP1_Pos (22U)
26260 #define HRTIM_RSTR_TIMCCMP1_Msk (0x1UL << HRTIM_RSTR_TIMCCMP1_Pos) /*!< 0x00400000 */
26261 #define HRTIM_RSTR_TIMCCMP1 HRTIM_RSTR_TIMCCMP1_Msk /*!< Timer C compare 1 */
26262 #define HRTIM_RSTR_TIMCCMP2_Pos (23U)
26263 #define HRTIM_RSTR_TIMCCMP2_Msk (0x1UL << HRTIM_RSTR_TIMCCMP2_Pos) /*!< 0x00800000 */
26264 #define HRTIM_RSTR_TIMCCMP2 HRTIM_RSTR_TIMCCMP2_Msk /*!< Timer C compare 2 */
26265 #define HRTIM_RSTR_TIMCCMP4_Pos (24U)
26266 #define HRTIM_RSTR_TIMCCMP4_Msk (0x1UL << HRTIM_RSTR_TIMCCMP4_Pos) /*!< 0x01000000 */
26267 #define HRTIM_RSTR_TIMCCMP4 HRTIM_RSTR_TIMCCMP4_Msk /*!< Timer C compare 4 */
26268
26269 #define HRTIM_RSTR_TIMDCMP1_Pos (25U)
26270 #define HRTIM_RSTR_TIMDCMP1_Msk (0x1UL << HRTIM_RSTR_TIMDCMP1_Pos) /*!< 0x02000000 */
26271 #define HRTIM_RSTR_TIMDCMP1 HRTIM_RSTR_TIMDCMP1_Msk /*!< Timer D compare 1 */
26272 #define HRTIM_RSTR_TIMDCMP2_Pos (26U)
26273 #define HRTIM_RSTR_TIMDCMP2_Msk (0x1UL << HRTIM_RSTR_TIMDCMP2_Pos) /*!< 0x04000000 */
26274 #define HRTIM_RSTR_TIMDCMP2 HRTIM_RSTR_TIMDCMP2_Msk /*!< Timer D compare 2 */
26275 #define HRTIM_RSTR_TIMDCMP4_Pos (27U)
26276 #define HRTIM_RSTR_TIMDCMP4_Msk (0x1UL << HRTIM_RSTR_TIMDCMP4_Pos) /*!< 0x08000000 */
26277 #define HRTIM_RSTR_TIMDCMP4 HRTIM_RSTR_TIMDCMP4_Msk /*!< Timer D compare 4 */
26278
26279 #define HRTIM_RSTR_TIMECMP1_Pos (28U)
26280 #define HRTIM_RSTR_TIMECMP1_Msk (0x1UL << HRTIM_RSTR_TIMECMP1_Pos) /*!< 0x10000000 */
26281 #define HRTIM_RSTR_TIMECMP1 HRTIM_RSTR_TIMECMP1_Msk /*!< Timer E compare 1 */
26282 #define HRTIM_RSTR_TIMECMP2_Pos (29U)
26283 #define HRTIM_RSTR_TIMECMP2_Msk (0x1UL << HRTIM_RSTR_TIMECMP2_Pos) /*!< 0x20000000 */
26284 #define HRTIM_RSTR_TIMECMP2 HRTIM_RSTR_TIMECMP2_Msk /*!< Timer E compare 2 */
26285 #define HRTIM_RSTR_TIMECMP4_Pos (30U)
26286 #define HRTIM_RSTR_TIMECMP4_Msk (0x1UL << HRTIM_RSTR_TIMECMP4_Pos) /*!< 0x40000000 */
26287 #define HRTIM_RSTR_TIMECMP4 HRTIM_RSTR_TIMECMP4_Msk /*!< Timer E compare 4 */
26288
26289 /**** Bit definition for Slave Timer Chopper register *************************/
26290 #define HRTIM_CHPR_CARFRQ_Pos (0U)
26291 #define HRTIM_CHPR_CARFRQ_Msk (0xFUL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x0000000F */
26292 #define HRTIM_CHPR_CARFRQ HRTIM_CHPR_CARFRQ_Msk /*!< Timer carrier frequency value */
26293 #define HRTIM_CHPR_CARFRQ_0 (0x1UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000001 */
26294 #define HRTIM_CHPR_CARFRQ_1 (0x2UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000002 */
26295 #define HRTIM_CHPR_CARFRQ_2 (0x4UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000004 */
26296 #define HRTIM_CHPR_CARFRQ_3 (0x8UL << HRTIM_CHPR_CARFRQ_Pos) /*!< 0x00000008 */
26297
26298 #define HRTIM_CHPR_CARDTY_Pos (4U)
26299 #define HRTIM_CHPR_CARDTY_Msk (0x7UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000070 */
26300 #define HRTIM_CHPR_CARDTY HRTIM_CHPR_CARDTY_Msk /*!< Timer chopper duty cycle value */
26301 #define HRTIM_CHPR_CARDTY_0 (0x1UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000010 */
26302 #define HRTIM_CHPR_CARDTY_1 (0x2UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000020 */
26303 #define HRTIM_CHPR_CARDTY_2 (0x4UL << HRTIM_CHPR_CARDTY_Pos) /*!< 0x00000040 */
26304
26305 #define HRTIM_CHPR_STRPW_Pos (7U)
26306 #define HRTIM_CHPR_STRPW_Msk (0xFUL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000780 */
26307 #define HRTIM_CHPR_STRPW HRTIM_CHPR_STRPW_Msk /*!< Timer start pulse width value */
26308 #define HRTIM_CHPR_STRPW_0 (0x1UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000080 */
26309 #define HRTIM_CHPR_STRPW_1 (0x2UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000100 */
26310 #define HRTIM_CHPR_STRPW_2 (0x4UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000200 */
26311 #define HRTIM_CHPR_STRPW_3 (0x8UL << HRTIM_CHPR_STRPW_Pos) /*!< 0x00000400 */
26312
26313 /**** Bit definition for Slave Timer Capture 1 control register ***************/
26314 #define HRTIM_CPT1CR_SWCPT_Pos (0U)
26315 #define HRTIM_CPT1CR_SWCPT_Msk (0x1UL << HRTIM_CPT1CR_SWCPT_Pos) /*!< 0x00000001 */
26316 #define HRTIM_CPT1CR_SWCPT HRTIM_CPT1CR_SWCPT_Msk /*!< Software capture */
26317 #define HRTIM_CPT1CR_UPDCPT_Pos (1U)
26318 #define HRTIM_CPT1CR_UPDCPT_Msk (0x1UL << HRTIM_CPT1CR_UPDCPT_Pos) /*!< 0x00000002 */
26319 #define HRTIM_CPT1CR_UPDCPT HRTIM_CPT1CR_UPDCPT_Msk /*!< Update capture */
26320 #define HRTIM_CPT1CR_EXEV1CPT_Pos (2U)
26321 #define HRTIM_CPT1CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV1CPT_Pos) /*!< 0x00000004 */
26322 #define HRTIM_CPT1CR_EXEV1CPT HRTIM_CPT1CR_EXEV1CPT_Msk /*!< External event 1 capture */
26323 #define HRTIM_CPT1CR_EXEV2CPT_Pos (3U)
26324 #define HRTIM_CPT1CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV2CPT_Pos) /*!< 0x00000008 */
26325 #define HRTIM_CPT1CR_EXEV2CPT HRTIM_CPT1CR_EXEV2CPT_Msk /*!< External event 2 capture */
26326 #define HRTIM_CPT1CR_EXEV3CPT_Pos (4U)
26327 #define HRTIM_CPT1CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV3CPT_Pos) /*!< 0x00000010 */
26328 #define HRTIM_CPT1CR_EXEV3CPT HRTIM_CPT1CR_EXEV3CPT_Msk /*!< External event 3 capture */
26329 #define HRTIM_CPT1CR_EXEV4CPT_Pos (5U)
26330 #define HRTIM_CPT1CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV4CPT_Pos) /*!< 0x00000020 */
26331 #define HRTIM_CPT1CR_EXEV4CPT HRTIM_CPT1CR_EXEV4CPT_Msk /*!< External event 4 capture */
26332 #define HRTIM_CPT1CR_EXEV5CPT_Pos (6U)
26333 #define HRTIM_CPT1CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV5CPT_Pos) /*!< 0x00000040 */
26334 #define HRTIM_CPT1CR_EXEV5CPT HRTIM_CPT1CR_EXEV5CPT_Msk /*!< External event 5 capture */
26335 #define HRTIM_CPT1CR_EXEV6CPT_Pos (7U)
26336 #define HRTIM_CPT1CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV6CPT_Pos) /*!< 0x00000080 */
26337 #define HRTIM_CPT1CR_EXEV6CPT HRTIM_CPT1CR_EXEV6CPT_Msk /*!< External event 6 capture */
26338 #define HRTIM_CPT1CR_EXEV7CPT_Pos (8U)
26339 #define HRTIM_CPT1CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV7CPT_Pos) /*!< 0x00000100 */
26340 #define HRTIM_CPT1CR_EXEV7CPT HRTIM_CPT1CR_EXEV7CPT_Msk /*!< External event 7 capture */
26341 #define HRTIM_CPT1CR_EXEV8CPT_Pos (9U)
26342 #define HRTIM_CPT1CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV8CPT_Pos) /*!< 0x00000200 */
26343 #define HRTIM_CPT1CR_EXEV8CPT HRTIM_CPT1CR_EXEV8CPT_Msk /*!< External event 8 capture */
26344 #define HRTIM_CPT1CR_EXEV9CPT_Pos (10U)
26345 #define HRTIM_CPT1CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV9CPT_Pos) /*!< 0x00000400 */
26346 #define HRTIM_CPT1CR_EXEV9CPT HRTIM_CPT1CR_EXEV9CPT_Msk /*!< External event 9 capture */
26347 #define HRTIM_CPT1CR_EXEV10CPT_Pos (11U)
26348 #define HRTIM_CPT1CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT1CR_EXEV10CPT_Pos) /*!< 0x00000800 */
26349 #define HRTIM_CPT1CR_EXEV10CPT HRTIM_CPT1CR_EXEV10CPT_Msk /*!< External event 10 capture */
26350
26351 #define HRTIM_CPT1CR_TA1SET_Pos (12U)
26352 #define HRTIM_CPT1CR_TA1SET_Msk (0x1UL << HRTIM_CPT1CR_TA1SET_Pos) /*!< 0x00001000 */
26353 #define HRTIM_CPT1CR_TA1SET HRTIM_CPT1CR_TA1SET_Msk /*!< Timer A output 1 set */
26354 #define HRTIM_CPT1CR_TA1RST_Pos (13U)
26355 #define HRTIM_CPT1CR_TA1RST_Msk (0x1UL << HRTIM_CPT1CR_TA1RST_Pos) /*!< 0x00002000 */
26356 #define HRTIM_CPT1CR_TA1RST HRTIM_CPT1CR_TA1RST_Msk /*!< Timer A output 1 reset */
26357 #define HRTIM_CPT1CR_TIMACMP1_Pos (14U)
26358 #define HRTIM_CPT1CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP1_Pos) /*!< 0x00004000 */
26359 #define HRTIM_CPT1CR_TIMACMP1 HRTIM_CPT1CR_TIMACMP1_Msk /*!< Timer A compare 1 */
26360 #define HRTIM_CPT1CR_TIMACMP2_Pos (15U)
26361 #define HRTIM_CPT1CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMACMP2_Pos) /*!< 0x00008000 */
26362 #define HRTIM_CPT1CR_TIMACMP2 HRTIM_CPT1CR_TIMACMP2_Msk /*!< Timer A compare 2 */
26363
26364 #define HRTIM_CPT1CR_TB1SET_Pos (16U)
26365 #define HRTIM_CPT1CR_TB1SET_Msk (0x1UL << HRTIM_CPT1CR_TB1SET_Pos) /*!< 0x00010000 */
26366 #define HRTIM_CPT1CR_TB1SET HRTIM_CPT1CR_TB1SET_Msk /*!< Timer B output 1 set */
26367 #define HRTIM_CPT1CR_TB1RST_Pos (17U)
26368 #define HRTIM_CPT1CR_TB1RST_Msk (0x1UL << HRTIM_CPT1CR_TB1RST_Pos) /*!< 0x00020000 */
26369 #define HRTIM_CPT1CR_TB1RST HRTIM_CPT1CR_TB1RST_Msk /*!< Timer B output 1 reset */
26370 #define HRTIM_CPT1CR_TIMBCMP1_Pos (18U)
26371 #define HRTIM_CPT1CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP1_Pos) /*!< 0x00040000 */
26372 #define HRTIM_CPT1CR_TIMBCMP1 HRTIM_CPT1CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
26373 #define HRTIM_CPT1CR_TIMBCMP2_Pos (19U)
26374 #define HRTIM_CPT1CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMBCMP2_Pos) /*!< 0x00080000 */
26375 #define HRTIM_CPT1CR_TIMBCMP2 HRTIM_CPT1CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
26376
26377 #define HRTIM_CPT1CR_TC1SET_Pos (20U)
26378 #define HRTIM_CPT1CR_TC1SET_Msk (0x1UL << HRTIM_CPT1CR_TC1SET_Pos) /*!< 0x00100000 */
26379 #define HRTIM_CPT1CR_TC1SET HRTIM_CPT1CR_TC1SET_Msk /*!< Timer C output 1 set */
26380 #define HRTIM_CPT1CR_TC1RST_Pos (21U)
26381 #define HRTIM_CPT1CR_TC1RST_Msk (0x1UL << HRTIM_CPT1CR_TC1RST_Pos) /*!< 0x00200000 */
26382 #define HRTIM_CPT1CR_TC1RST HRTIM_CPT1CR_TC1RST_Msk /*!< Timer C output 1 reset */
26383 #define HRTIM_CPT1CR_TIMCCMP1_Pos (22U)
26384 #define HRTIM_CPT1CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP1_Pos) /*!< 0x00400000 */
26385 #define HRTIM_CPT1CR_TIMCCMP1 HRTIM_CPT1CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
26386 #define HRTIM_CPT1CR_TIMCCMP2_Pos (23U)
26387 #define HRTIM_CPT1CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMCCMP2_Pos) /*!< 0x00800000 */
26388 #define HRTIM_CPT1CR_TIMCCMP2 HRTIM_CPT1CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
26389
26390 #define HRTIM_CPT1CR_TD1SET_Pos (24U)
26391 #define HRTIM_CPT1CR_TD1SET_Msk (0x1UL << HRTIM_CPT1CR_TD1SET_Pos) /*!< 0x01000000 */
26392 #define HRTIM_CPT1CR_TD1SET HRTIM_CPT1CR_TD1SET_Msk /*!< Timer D output 1 set */
26393 #define HRTIM_CPT1CR_TD1RST_Pos (25U)
26394 #define HRTIM_CPT1CR_TD1RST_Msk (0x1UL << HRTIM_CPT1CR_TD1RST_Pos) /*!< 0x02000000 */
26395 #define HRTIM_CPT1CR_TD1RST HRTIM_CPT1CR_TD1RST_Msk /*!< Timer D output 1 reset */
26396 #define HRTIM_CPT1CR_TIMDCMP1_Pos (26U)
26397 #define HRTIM_CPT1CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP1_Pos) /*!< 0x04000000 */
26398 #define HRTIM_CPT1CR_TIMDCMP1 HRTIM_CPT1CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
26399 #define HRTIM_CPT1CR_TIMDCMP2_Pos (27U)
26400 #define HRTIM_CPT1CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMDCMP2_Pos) /*!< 0x08000000 */
26401 #define HRTIM_CPT1CR_TIMDCMP2 HRTIM_CPT1CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
26402
26403 #define HRTIM_CPT1CR_TE1SET_Pos (28U)
26404 #define HRTIM_CPT1CR_TE1SET_Msk (0x1UL << HRTIM_CPT1CR_TE1SET_Pos) /*!< 0x10000000 */
26405 #define HRTIM_CPT1CR_TE1SET HRTIM_CPT1CR_TE1SET_Msk /*!< Timer E output 1 set */
26406 #define HRTIM_CPT1CR_TE1RST_Pos (29U)
26407 #define HRTIM_CPT1CR_TE1RST_Msk (0x1UL << HRTIM_CPT1CR_TE1RST_Pos) /*!< 0x20000000 */
26408 #define HRTIM_CPT1CR_TE1RST HRTIM_CPT1CR_TE1RST_Msk /*!< Timer E output 1 reset */
26409 #define HRTIM_CPT1CR_TIMECMP1_Pos (30U)
26410 #define HRTIM_CPT1CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP1_Pos) /*!< 0x40000000 */
26411 #define HRTIM_CPT1CR_TIMECMP1 HRTIM_CPT1CR_TIMECMP1_Msk /*!< Timer E compare 1 */
26412 #define HRTIM_CPT1CR_TIMECMP2_Pos (31U)
26413 #define HRTIM_CPT1CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT1CR_TIMECMP2_Pos) /*!< 0x80000000 */
26414 #define HRTIM_CPT1CR_TIMECMP2 HRTIM_CPT1CR_TIMECMP2_Msk /*!< Timer E compare 2 */
26415
26416 /**** Bit definition for Slave Timer Capture 2 control register ***************/
26417 #define HRTIM_CPT2CR_SWCPT_Pos (0U)
26418 #define HRTIM_CPT2CR_SWCPT_Msk (0x1UL << HRTIM_CPT2CR_SWCPT_Pos) /*!< 0x00000001 */
26419 #define HRTIM_CPT2CR_SWCPT HRTIM_CPT2CR_SWCPT_Msk /*!< Software capture */
26420 #define HRTIM_CPT2CR_UPDCPT_Pos (1U)
26421 #define HRTIM_CPT2CR_UPDCPT_Msk (0x1UL << HRTIM_CPT2CR_UPDCPT_Pos) /*!< 0x00000002 */
26422 #define HRTIM_CPT2CR_UPDCPT HRTIM_CPT2CR_UPDCPT_Msk /*!< Update capture */
26423 #define HRTIM_CPT2CR_EXEV1CPT_Pos (2U)
26424 #define HRTIM_CPT2CR_EXEV1CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV1CPT_Pos) /*!< 0x00000004 */
26425 #define HRTIM_CPT2CR_EXEV1CPT HRTIM_CPT2CR_EXEV1CPT_Msk /*!< External event 1 capture */
26426 #define HRTIM_CPT2CR_EXEV2CPT_Pos (3U)
26427 #define HRTIM_CPT2CR_EXEV2CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV2CPT_Pos) /*!< 0x00000008 */
26428 #define HRTIM_CPT2CR_EXEV2CPT HRTIM_CPT2CR_EXEV2CPT_Msk /*!< External event 2 capture */
26429 #define HRTIM_CPT2CR_EXEV3CPT_Pos (4U)
26430 #define HRTIM_CPT2CR_EXEV3CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV3CPT_Pos) /*!< 0x00000010 */
26431 #define HRTIM_CPT2CR_EXEV3CPT HRTIM_CPT2CR_EXEV3CPT_Msk /*!< External event 3 capture */
26432 #define HRTIM_CPT2CR_EXEV4CPT_Pos (5U)
26433 #define HRTIM_CPT2CR_EXEV4CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV4CPT_Pos) /*!< 0x00000020 */
26434 #define HRTIM_CPT2CR_EXEV4CPT HRTIM_CPT2CR_EXEV4CPT_Msk /*!< External event 4 capture */
26435 #define HRTIM_CPT2CR_EXEV5CPT_Pos (6U)
26436 #define HRTIM_CPT2CR_EXEV5CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV5CPT_Pos) /*!< 0x00000040 */
26437 #define HRTIM_CPT2CR_EXEV5CPT HRTIM_CPT2CR_EXEV5CPT_Msk /*!< External event 5 capture */
26438 #define HRTIM_CPT2CR_EXEV6CPT_Pos (7U)
26439 #define HRTIM_CPT2CR_EXEV6CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV6CPT_Pos) /*!< 0x00000080 */
26440 #define HRTIM_CPT2CR_EXEV6CPT HRTIM_CPT2CR_EXEV6CPT_Msk /*!< External event 6 capture */
26441 #define HRTIM_CPT2CR_EXEV7CPT_Pos (8U)
26442 #define HRTIM_CPT2CR_EXEV7CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV7CPT_Pos) /*!< 0x00000100 */
26443 #define HRTIM_CPT2CR_EXEV7CPT HRTIM_CPT2CR_EXEV7CPT_Msk /*!< External event 7 capture */
26444 #define HRTIM_CPT2CR_EXEV8CPT_Pos (9U)
26445 #define HRTIM_CPT2CR_EXEV8CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV8CPT_Pos) /*!< 0x00000200 */
26446 #define HRTIM_CPT2CR_EXEV8CPT HRTIM_CPT2CR_EXEV8CPT_Msk /*!< External event 8 capture */
26447 #define HRTIM_CPT2CR_EXEV9CPT_Pos (10U)
26448 #define HRTIM_CPT2CR_EXEV9CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV9CPT_Pos) /*!< 0x00000400 */
26449 #define HRTIM_CPT2CR_EXEV9CPT HRTIM_CPT2CR_EXEV9CPT_Msk /*!< External event 9 capture */
26450 #define HRTIM_CPT2CR_EXEV10CPT_Pos (11U)
26451 #define HRTIM_CPT2CR_EXEV10CPT_Msk (0x1UL << HRTIM_CPT2CR_EXEV10CPT_Pos) /*!< 0x00000800 */
26452 #define HRTIM_CPT2CR_EXEV10CPT HRTIM_CPT2CR_EXEV10CPT_Msk /*!< External event 10 capture */
26453
26454 #define HRTIM_CPT2CR_TA1SET_Pos (12U)
26455 #define HRTIM_CPT2CR_TA1SET_Msk (0x1UL << HRTIM_CPT2CR_TA1SET_Pos) /*!< 0x00001000 */
26456 #define HRTIM_CPT2CR_TA1SET HRTIM_CPT2CR_TA1SET_Msk /*!< Timer A output 1 set */
26457 #define HRTIM_CPT2CR_TA1RST_Pos (13U)
26458 #define HRTIM_CPT2CR_TA1RST_Msk (0x1UL << HRTIM_CPT2CR_TA1RST_Pos) /*!< 0x00002000 */
26459 #define HRTIM_CPT2CR_TA1RST HRTIM_CPT2CR_TA1RST_Msk /*!< Timer A output 1 reset */
26460 #define HRTIM_CPT2CR_TIMACMP1_Pos (14U)
26461 #define HRTIM_CPT2CR_TIMACMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP1_Pos) /*!< 0x00004000 */
26462 #define HRTIM_CPT2CR_TIMACMP1 HRTIM_CPT2CR_TIMACMP1_Msk /*!< Timer A compare 1 */
26463 #define HRTIM_CPT2CR_TIMACMP2_Pos (15U)
26464 #define HRTIM_CPT2CR_TIMACMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMACMP2_Pos) /*!< 0x00008000 */
26465 #define HRTIM_CPT2CR_TIMACMP2 HRTIM_CPT2CR_TIMACMP2_Msk /*!< Timer A compare 2 */
26466
26467 #define HRTIM_CPT2CR_TB1SET_Pos (16U)
26468 #define HRTIM_CPT2CR_TB1SET_Msk (0x1UL << HRTIM_CPT2CR_TB1SET_Pos) /*!< 0x00010000 */
26469 #define HRTIM_CPT2CR_TB1SET HRTIM_CPT2CR_TB1SET_Msk /*!< Timer B output 1 set */
26470 #define HRTIM_CPT2CR_TB1RST_Pos (17U)
26471 #define HRTIM_CPT2CR_TB1RST_Msk (0x1UL << HRTIM_CPT2CR_TB1RST_Pos) /*!< 0x00020000 */
26472 #define HRTIM_CPT2CR_TB1RST HRTIM_CPT2CR_TB1RST_Msk /*!< Timer B output 1 reset */
26473 #define HRTIM_CPT2CR_TIMBCMP1_Pos (18U)
26474 #define HRTIM_CPT2CR_TIMBCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP1_Pos) /*!< 0x00040000 */
26475 #define HRTIM_CPT2CR_TIMBCMP1 HRTIM_CPT2CR_TIMBCMP1_Msk /*!< Timer B compare 1 */
26476 #define HRTIM_CPT2CR_TIMBCMP2_Pos (19U)
26477 #define HRTIM_CPT2CR_TIMBCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMBCMP2_Pos) /*!< 0x00080000 */
26478 #define HRTIM_CPT2CR_TIMBCMP2 HRTIM_CPT2CR_TIMBCMP2_Msk /*!< Timer B compare 2 */
26479
26480 #define HRTIM_CPT2CR_TC1SET_Pos (20U)
26481 #define HRTIM_CPT2CR_TC1SET_Msk (0x1UL << HRTIM_CPT2CR_TC1SET_Pos) /*!< 0x00100000 */
26482 #define HRTIM_CPT2CR_TC1SET HRTIM_CPT2CR_TC1SET_Msk /*!< Timer C output 1 set */
26483 #define HRTIM_CPT2CR_TC1RST_Pos (21U)
26484 #define HRTIM_CPT2CR_TC1RST_Msk (0x1UL << HRTIM_CPT2CR_TC1RST_Pos) /*!< 0x00200000 */
26485 #define HRTIM_CPT2CR_TC1RST HRTIM_CPT2CR_TC1RST_Msk /*!< Timer C output 1 reset */
26486 #define HRTIM_CPT2CR_TIMCCMP1_Pos (22U)
26487 #define HRTIM_CPT2CR_TIMCCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP1_Pos) /*!< 0x00400000 */
26488 #define HRTIM_CPT2CR_TIMCCMP1 HRTIM_CPT2CR_TIMCCMP1_Msk /*!< Timer C compare 1 */
26489 #define HRTIM_CPT2CR_TIMCCMP2_Pos (23U)
26490 #define HRTIM_CPT2CR_TIMCCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMCCMP2_Pos) /*!< 0x00800000 */
26491 #define HRTIM_CPT2CR_TIMCCMP2 HRTIM_CPT2CR_TIMCCMP2_Msk /*!< Timer C compare 2 */
26492
26493 #define HRTIM_CPT2CR_TD1SET_Pos (24U)
26494 #define HRTIM_CPT2CR_TD1SET_Msk (0x1UL << HRTIM_CPT2CR_TD1SET_Pos) /*!< 0x01000000 */
26495 #define HRTIM_CPT2CR_TD1SET HRTIM_CPT2CR_TD1SET_Msk /*!< Timer D output 1 set */
26496 #define HRTIM_CPT2CR_TD1RST_Pos (25U)
26497 #define HRTIM_CPT2CR_TD1RST_Msk (0x1UL << HRTIM_CPT2CR_TD1RST_Pos) /*!< 0x02000000 */
26498 #define HRTIM_CPT2CR_TD1RST HRTIM_CPT2CR_TD1RST_Msk /*!< Timer D output 1 reset */
26499 #define HRTIM_CPT2CR_TIMDCMP1_Pos (26U)
26500 #define HRTIM_CPT2CR_TIMDCMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP1_Pos) /*!< 0x04000000 */
26501 #define HRTIM_CPT2CR_TIMDCMP1 HRTIM_CPT2CR_TIMDCMP1_Msk /*!< Timer D compare 1 */
26502 #define HRTIM_CPT2CR_TIMDCMP2_Pos (27U)
26503 #define HRTIM_CPT2CR_TIMDCMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMDCMP2_Pos) /*!< 0x08000000 */
26504 #define HRTIM_CPT2CR_TIMDCMP2 HRTIM_CPT2CR_TIMDCMP2_Msk /*!< Timer D compare 2 */
26505
26506 #define HRTIM_CPT2CR_TE1SET_Pos (28U)
26507 #define HRTIM_CPT2CR_TE1SET_Msk (0x1UL << HRTIM_CPT2CR_TE1SET_Pos) /*!< 0x10000000 */
26508 #define HRTIM_CPT2CR_TE1SET HRTIM_CPT2CR_TE1SET_Msk /*!< Timer E output 1 set */
26509 #define HRTIM_CPT2CR_TE1RST_Pos (29U)
26510 #define HRTIM_CPT2CR_TE1RST_Msk (0x1UL << HRTIM_CPT2CR_TE1RST_Pos) /*!< 0x20000000 */
26511 #define HRTIM_CPT2CR_TE1RST HRTIM_CPT2CR_TE1RST_Msk /*!< Timer E output 1 reset */
26512 #define HRTIM_CPT2CR_TIMECMP1_Pos (30U)
26513 #define HRTIM_CPT2CR_TIMECMP1_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP1_Pos) /*!< 0x40000000 */
26514 #define HRTIM_CPT2CR_TIMECMP1 HRTIM_CPT2CR_TIMECMP1_Msk /*!< Timer E compare 1 */
26515 #define HRTIM_CPT2CR_TIMECMP2_Pos (31U)
26516 #define HRTIM_CPT2CR_TIMECMP2_Msk (0x1UL << HRTIM_CPT2CR_TIMECMP2_Pos) /*!< 0x80000000 */
26517 #define HRTIM_CPT2CR_TIMECMP2 HRTIM_CPT2CR_TIMECMP2_Msk /*!< Timer E compare 2 */
26518
26519 /**** Bit definition for Slave Timer Output register **************************/
26520 #define HRTIM_OUTR_POL1_Pos (1U)
26521 #define HRTIM_OUTR_POL1_Msk (0x1UL << HRTIM_OUTR_POL1_Pos) /*!< 0x00000002 */
26522 #define HRTIM_OUTR_POL1 HRTIM_OUTR_POL1_Msk /*!< Slave output 1 polarity */
26523 #define HRTIM_OUTR_IDLM1_Pos (2U)
26524 #define HRTIM_OUTR_IDLM1_Msk (0x1UL << HRTIM_OUTR_IDLM1_Pos) /*!< 0x00000004 */
26525 #define HRTIM_OUTR_IDLM1 HRTIM_OUTR_IDLM1_Msk /*!< Slave output 1 idle mode */
26526 #define HRTIM_OUTR_IDLES1_Pos (3U)
26527 #define HRTIM_OUTR_IDLES1_Msk (0x1UL << HRTIM_OUTR_IDLES1_Pos) /*!< 0x00000008 */
26528 #define HRTIM_OUTR_IDLES1 HRTIM_OUTR_IDLES1_Msk /*!< Slave output 1 idle state */
26529 #define HRTIM_OUTR_FAULT1_Pos (4U)
26530 #define HRTIM_OUTR_FAULT1_Msk (0x3UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000030 */
26531 #define HRTIM_OUTR_FAULT1 HRTIM_OUTR_FAULT1_Msk /*!< Slave output 1 fault state */
26532 #define HRTIM_OUTR_FAULT1_0 (0x1UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000010 */
26533 #define HRTIM_OUTR_FAULT1_1 (0x2UL << HRTIM_OUTR_FAULT1_Pos) /*!< 0x00000020 */
26534 #define HRTIM_OUTR_CHP1_Pos (6U)
26535 #define HRTIM_OUTR_CHP1_Msk (0x1UL << HRTIM_OUTR_CHP1_Pos) /*!< 0x00000040 */
26536 #define HRTIM_OUTR_CHP1 HRTIM_OUTR_CHP1_Msk /*!< Slave output 1 chopper enable */
26537 #define HRTIM_OUTR_DIDL1_Pos (7U)
26538 #define HRTIM_OUTR_DIDL1_Msk (0x1UL << HRTIM_OUTR_DIDL1_Pos) /*!< 0x00000080 */
26539 #define HRTIM_OUTR_DIDL1 HRTIM_OUTR_DIDL1_Msk /*!< Slave output 1 dead time idle */
26540
26541 #define HRTIM_OUTR_DTEN_Pos (8U)
26542 #define HRTIM_OUTR_DTEN_Msk (0x1UL << HRTIM_OUTR_DTEN_Pos) /*!< 0x00000100 */
26543 #define HRTIM_OUTR_DTEN HRTIM_OUTR_DTEN_Msk /*!< Slave output deadtime enable */
26544 #define HRTIM_OUTR_DLYPRTEN_Pos (9U)
26545 #define HRTIM_OUTR_DLYPRTEN_Msk (0x1UL << HRTIM_OUTR_DLYPRTEN_Pos) /*!< 0x00000200 */
26546 #define HRTIM_OUTR_DLYPRTEN HRTIM_OUTR_DLYPRTEN_Msk /*!< Slave output delay protection enable */
26547 #define HRTIM_OUTR_DLYPRT_Pos (10U)
26548 #define HRTIM_OUTR_DLYPRT_Msk (0x7UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001C00 */
26549 #define HRTIM_OUTR_DLYPRT HRTIM_OUTR_DLYPRT_Msk /*!< Slave output delay protection */
26550 #define HRTIM_OUTR_DLYPRT_0 (0x1UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000400 */
26551 #define HRTIM_OUTR_DLYPRT_1 (0x2UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00000800 */
26552 #define HRTIM_OUTR_DLYPRT_2 (0x4UL << HRTIM_OUTR_DLYPRT_Pos) /*!< 0x00001000 */
26553
26554 #define HRTIM_OUTR_POL2_Pos (17U)
26555 #define HRTIM_OUTR_POL2_Msk (0x1UL << HRTIM_OUTR_POL2_Pos) /*!< 0x00020000 */
26556 #define HRTIM_OUTR_POL2 HRTIM_OUTR_POL2_Msk /*!< Slave output 2 polarity */
26557 #define HRTIM_OUTR_IDLM2_Pos (18U)
26558 #define HRTIM_OUTR_IDLM2_Msk (0x1UL << HRTIM_OUTR_IDLM2_Pos) /*!< 0x00040000 */
26559 #define HRTIM_OUTR_IDLM2 HRTIM_OUTR_IDLM2_Msk /*!< Slave output 2 idle mode */
26560 #define HRTIM_OUTR_IDLES2_Pos (19U)
26561 #define HRTIM_OUTR_IDLES2_Msk (0x1UL << HRTIM_OUTR_IDLES2_Pos) /*!< 0x00080000 */
26562 #define HRTIM_OUTR_IDLES2 HRTIM_OUTR_IDLES2_Msk /*!< Slave output 2 idle state */
26563 #define HRTIM_OUTR_FAULT2_Pos (20U)
26564 #define HRTIM_OUTR_FAULT2_Msk (0x3UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00300000 */
26565 #define HRTIM_OUTR_FAULT2 HRTIM_OUTR_FAULT2_Msk /*!< Slave output 2 fault state */
26566 #define HRTIM_OUTR_FAULT2_0 (0x1UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00100000 */
26567 #define HRTIM_OUTR_FAULT2_1 (0x2UL << HRTIM_OUTR_FAULT2_Pos) /*!< 0x00200000 */
26568 #define HRTIM_OUTR_CHP2_Pos (22U)
26569 #define HRTIM_OUTR_CHP2_Msk (0x1UL << HRTIM_OUTR_CHP2_Pos) /*!< 0x00400000 */
26570 #define HRTIM_OUTR_CHP2 HRTIM_OUTR_CHP2_Msk /*!< Slave output 2 chopper enable */
26571 #define HRTIM_OUTR_DIDL2_Pos (23U)
26572 #define HRTIM_OUTR_DIDL2_Msk (0x1UL << HRTIM_OUTR_DIDL2_Pos) /*!< 0x00800000 */
26573 #define HRTIM_OUTR_DIDL2 HRTIM_OUTR_DIDL2_Msk /*!< Slave output 2 dead time idle */
26574
26575 /**** Bit definition for Slave Timer Fault register ***************************/
26576 #define HRTIM_FLTR_FLT1EN_Pos (0U)
26577 #define HRTIM_FLTR_FLT1EN_Msk (0x1UL << HRTIM_FLTR_FLT1EN_Pos) /*!< 0x00000001 */
26578 #define HRTIM_FLTR_FLT1EN HRTIM_FLTR_FLT1EN_Msk /*!< Fault 1 enable */
26579 #define HRTIM_FLTR_FLT2EN_Pos (1U)
26580 #define HRTIM_FLTR_FLT2EN_Msk (0x1UL << HRTIM_FLTR_FLT2EN_Pos) /*!< 0x00000002 */
26581 #define HRTIM_FLTR_FLT2EN HRTIM_FLTR_FLT2EN_Msk /*!< Fault 2 enable */
26582 #define HRTIM_FLTR_FLT3EN_Pos (2U)
26583 #define HRTIM_FLTR_FLT3EN_Msk (0x1UL << HRTIM_FLTR_FLT3EN_Pos) /*!< 0x00000004 */
26584 #define HRTIM_FLTR_FLT3EN HRTIM_FLTR_FLT3EN_Msk /*!< Fault 3 enable */
26585 #define HRTIM_FLTR_FLT4EN_Pos (3U)
26586 #define HRTIM_FLTR_FLT4EN_Msk (0x1UL << HRTIM_FLTR_FLT4EN_Pos) /*!< 0x00000008 */
26587 #define HRTIM_FLTR_FLT4EN HRTIM_FLTR_FLT4EN_Msk /*!< Fault 4 enable */
26588 #define HRTIM_FLTR_FLT5EN_Pos (4U)
26589 #define HRTIM_FLTR_FLT5EN_Msk (0x1UL << HRTIM_FLTR_FLT5EN_Pos) /*!< 0x00000010 */
26590 #define HRTIM_FLTR_FLT5EN HRTIM_FLTR_FLT5EN_Msk /*!< Fault 5 enable */
26591 #define HRTIM_FLTR_FLTLCK_Pos (31U)
26592 #define HRTIM_FLTR_FLTLCK_Msk (0x1UL << HRTIM_FLTR_FLTLCK_Pos) /*!< 0x80000000 */
26593 #define HRTIM_FLTR_FLTLCK HRTIM_FLTR_FLTLCK_Msk /*!< Fault sources lock */
26594
26595 /**** Bit definition for Common HRTIM Timer control register 1 ****************/
26596 #define HRTIM_CR1_MUDIS_Pos (0U)
26597 #define HRTIM_CR1_MUDIS_Msk (0x1UL << HRTIM_CR1_MUDIS_Pos) /*!< 0x00000001 */
26598 #define HRTIM_CR1_MUDIS HRTIM_CR1_MUDIS_Msk /*!< Master update disable*/
26599 #define HRTIM_CR1_TAUDIS_Pos (1U)
26600 #define HRTIM_CR1_TAUDIS_Msk (0x1UL << HRTIM_CR1_TAUDIS_Pos) /*!< 0x00000002 */
26601 #define HRTIM_CR1_TAUDIS HRTIM_CR1_TAUDIS_Msk /*!< Timer A update disable*/
26602 #define HRTIM_CR1_TBUDIS_Pos (2U)
26603 #define HRTIM_CR1_TBUDIS_Msk (0x1UL << HRTIM_CR1_TBUDIS_Pos) /*!< 0x00000004 */
26604 #define HRTIM_CR1_TBUDIS HRTIM_CR1_TBUDIS_Msk /*!< Timer B update disable*/
26605 #define HRTIM_CR1_TCUDIS_Pos (3U)
26606 #define HRTIM_CR1_TCUDIS_Msk (0x1UL << HRTIM_CR1_TCUDIS_Pos) /*!< 0x00000008 */
26607 #define HRTIM_CR1_TCUDIS HRTIM_CR1_TCUDIS_Msk /*!< Timer C update disable*/
26608 #define HRTIM_CR1_TDUDIS_Pos (4U)
26609 #define HRTIM_CR1_TDUDIS_Msk (0x1UL << HRTIM_CR1_TDUDIS_Pos) /*!< 0x00000010 */
26610 #define HRTIM_CR1_TDUDIS HRTIM_CR1_TDUDIS_Msk /*!< Timer D update disable*/
26611 #define HRTIM_CR1_TEUDIS_Pos (5U)
26612 #define HRTIM_CR1_TEUDIS_Msk (0x1UL << HRTIM_CR1_TEUDIS_Pos) /*!< 0x00000020 */
26613 #define HRTIM_CR1_TEUDIS HRTIM_CR1_TEUDIS_Msk /*!< Timer E update disable*/
26614 #define HRTIM_CR1_ADC1USRC_Pos (16U)
26615 #define HRTIM_CR1_ADC1USRC_Msk (0x7UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00070000 */
26616 #define HRTIM_CR1_ADC1USRC HRTIM_CR1_ADC1USRC_Msk /*!< ADC Trigger 1 update source */
26617 #define HRTIM_CR1_ADC1USRC_0 (0x1UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00010000 */
26618 #define HRTIM_CR1_ADC1USRC_1 (0x2UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00020000 */
26619 #define HRTIM_CR1_ADC1USRC_2 (0x4UL << HRTIM_CR1_ADC1USRC_Pos) /*!< 0x00040000 */
26620 #define HRTIM_CR1_ADC2USRC_Pos (19U)
26621 #define HRTIM_CR1_ADC2USRC_Msk (0x7UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00380000 */
26622 #define HRTIM_CR1_ADC2USRC HRTIM_CR1_ADC2USRC_Msk /*!< ADC Trigger 2 update source */
26623 #define HRTIM_CR1_ADC2USRC_0 (0x1UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00080000 */
26624 #define HRTIM_CR1_ADC2USRC_1 (0x2UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00100000 */
26625 #define HRTIM_CR1_ADC2USRC_2 (0x4UL << HRTIM_CR1_ADC2USRC_Pos) /*!< 0x00200000 */
26626 #define HRTIM_CR1_ADC3USRC_Pos (22U)
26627 #define HRTIM_CR1_ADC3USRC_Msk (0x7UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01C00000 */
26628 #define HRTIM_CR1_ADC3USRC HRTIM_CR1_ADC3USRC_Msk /*!< ADC Trigger 3 update source */
26629 #define HRTIM_CR1_ADC3USRC_0 (0x1UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00400000 */
26630 #define HRTIM_CR1_ADC3USRC_1 (0x2UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x00800000 */
26631 #define HRTIM_CR1_ADC3USRC_2 (0x4UL << HRTIM_CR1_ADC3USRC_Pos) /*!< 0x01000000 */
26632 #define HRTIM_CR1_ADC4USRC_Pos (25U)
26633 #define HRTIM_CR1_ADC4USRC_Msk (0x7UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0E000000 */
26634 #define HRTIM_CR1_ADC4USRC HRTIM_CR1_ADC4USRC_Msk /*!< ADC Trigger 4 update source */
26635 #define HRTIM_CR1_ADC4USRC_0 (0x1UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x02000000 */
26636 #define HRTIM_CR1_ADC4USRC_1 (0x2UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x04000000 */
26637 #define HRTIM_CR1_ADC4USRC_2 (0x0UL << HRTIM_CR1_ADC4USRC_Pos) /*!< 0x0800000 */
26638
26639 /**** Bit definition for Common HRTIM Timer control register 2 ****************/
26640 #define HRTIM_CR2_MSWU_Pos (0U)
26641 #define HRTIM_CR2_MSWU_Msk (0x1UL << HRTIM_CR2_MSWU_Pos) /*!< 0x00000001 */
26642 #define HRTIM_CR2_MSWU HRTIM_CR2_MSWU_Msk /*!< Master software update */
26643 #define HRTIM_CR2_TASWU_Pos (1U)
26644 #define HRTIM_CR2_TASWU_Msk (0x1UL << HRTIM_CR2_TASWU_Pos) /*!< 0x00000002 */
26645 #define HRTIM_CR2_TASWU HRTIM_CR2_TASWU_Msk /*!< Timer A software update */
26646 #define HRTIM_CR2_TBSWU_Pos (2U)
26647 #define HRTIM_CR2_TBSWU_Msk (0x1UL << HRTIM_CR2_TBSWU_Pos) /*!< 0x00000004 */
26648 #define HRTIM_CR2_TBSWU HRTIM_CR2_TBSWU_Msk /*!< Timer B software update */
26649 #define HRTIM_CR2_TCSWU_Pos (3U)
26650 #define HRTIM_CR2_TCSWU_Msk (0x1UL << HRTIM_CR2_TCSWU_Pos) /*!< 0x00000008 */
26651 #define HRTIM_CR2_TCSWU HRTIM_CR2_TCSWU_Msk /*!< Timer C software update */
26652 #define HRTIM_CR2_TDSWU_Pos (4U)
26653 #define HRTIM_CR2_TDSWU_Msk (0x1UL << HRTIM_CR2_TDSWU_Pos) /*!< 0x00000010 */
26654 #define HRTIM_CR2_TDSWU HRTIM_CR2_TDSWU_Msk /*!< Timer D software update */
26655 #define HRTIM_CR2_TESWU_Pos (5U)
26656 #define HRTIM_CR2_TESWU_Msk (0x1UL << HRTIM_CR2_TESWU_Pos) /*!< 0x00000020 */
26657 #define HRTIM_CR2_TESWU HRTIM_CR2_TESWU_Msk /*!< Timer E software update */
26658 #define HRTIM_CR2_MRST_Pos (8U)
26659 #define HRTIM_CR2_MRST_Msk (0x1UL << HRTIM_CR2_MRST_Pos) /*!< 0x00000100 */
26660 #define HRTIM_CR2_MRST HRTIM_CR2_MRST_Msk /*!< Master count software reset */
26661 #define HRTIM_CR2_TARST_Pos (9U)
26662 #define HRTIM_CR2_TARST_Msk (0x1UL << HRTIM_CR2_TARST_Pos) /*!< 0x00000200 */
26663 #define HRTIM_CR2_TARST HRTIM_CR2_TARST_Msk /*!< Timer A count software reset */
26664 #define HRTIM_CR2_TBRST_Pos (10U)
26665 #define HRTIM_CR2_TBRST_Msk (0x1UL << HRTIM_CR2_TBRST_Pos) /*!< 0x00000400 */
26666 #define HRTIM_CR2_TBRST HRTIM_CR2_TBRST_Msk /*!< Timer B count software reset */
26667 #define HRTIM_CR2_TCRST_Pos (11U)
26668 #define HRTIM_CR2_TCRST_Msk (0x1UL << HRTIM_CR2_TCRST_Pos) /*!< 0x00000800 */
26669 #define HRTIM_CR2_TCRST HRTIM_CR2_TCRST_Msk /*!< Timer C count software reset */
26670 #define HRTIM_CR2_TDRST_Pos (12U)
26671 #define HRTIM_CR2_TDRST_Msk (0x1UL << HRTIM_CR2_TDRST_Pos) /*!< 0x00001000 */
26672 #define HRTIM_CR2_TDRST HRTIM_CR2_TDRST_Msk /*!< Timer D count software reset */
26673 #define HRTIM_CR2_TERST_Pos (13U)
26674 #define HRTIM_CR2_TERST_Msk (0x1UL << HRTIM_CR2_TERST_Pos) /*!< 0x00002000 */
26675 #define HRTIM_CR2_TERST HRTIM_CR2_TERST_Msk /*!< Timer E count software reset */
26676
26677 /**** Bit definition for Common HRTIM Timer interrupt status register *********/
26678 #define HRTIM_ISR_FLT1_Pos (0U)
26679 #define HRTIM_ISR_FLT1_Msk (0x1UL << HRTIM_ISR_FLT1_Pos) /*!< 0x00000001 */
26680 #define HRTIM_ISR_FLT1 HRTIM_ISR_FLT1_Msk /*!< Fault 1 interrupt flag */
26681 #define HRTIM_ISR_FLT2_Pos (1U)
26682 #define HRTIM_ISR_FLT2_Msk (0x1UL << HRTIM_ISR_FLT2_Pos) /*!< 0x00000002 */
26683 #define HRTIM_ISR_FLT2 HRTIM_ISR_FLT2_Msk /*!< Fault 2 interrupt flag */
26684 #define HRTIM_ISR_FLT3_Pos (2U)
26685 #define HRTIM_ISR_FLT3_Msk (0x1UL << HRTIM_ISR_FLT3_Pos) /*!< 0x00000004 */
26686 #define HRTIM_ISR_FLT3 HRTIM_ISR_FLT3_Msk /*!< Fault 3 interrupt flag */
26687 #define HRTIM_ISR_FLT4_Pos (3U)
26688 #define HRTIM_ISR_FLT4_Msk (0x1UL << HRTIM_ISR_FLT4_Pos) /*!< 0x00000008 */
26689 #define HRTIM_ISR_FLT4 HRTIM_ISR_FLT4_Msk /*!< Fault 4 interrupt flag */
26690 #define HRTIM_ISR_FLT5_Pos (4U)
26691 #define HRTIM_ISR_FLT5_Msk (0x1UL << HRTIM_ISR_FLT5_Pos) /*!< 0x00000010 */
26692 #define HRTIM_ISR_FLT5 HRTIM_ISR_FLT5_Msk /*!< Fault 5 interrupt flag */
26693 #define HRTIM_ISR_SYSFLT_Pos (5U)
26694 #define HRTIM_ISR_SYSFLT_Msk (0x1UL << HRTIM_ISR_SYSFLT_Pos) /*!< 0x00000020 */
26695 #define HRTIM_ISR_SYSFLT HRTIM_ISR_SYSFLT_Msk /*!< System Fault interrupt flag */
26696 #define HRTIM_ISR_BMPER_Pos (17U)
26697 #define HRTIM_ISR_BMPER_Msk (0x1UL << HRTIM_ISR_BMPER_Pos) /*!< 0x00020000 */
26698 #define HRTIM_ISR_BMPER HRTIM_ISR_BMPER_Msk /*!< Burst mode period interrupt flag */
26699
26700 /**** Bit definition for Common HRTIM Timer interrupt clear register **********/
26701 #define HRTIM_ICR_FLT1C_Pos (0U)
26702 #define HRTIM_ICR_FLT1C_Msk (0x1UL << HRTIM_ICR_FLT1C_Pos) /*!< 0x00000001 */
26703 #define HRTIM_ICR_FLT1C HRTIM_ICR_FLT1C_Msk /*!< Fault 1 interrupt flag clear */
26704 #define HRTIM_ICR_FLT2C_Pos (1U)
26705 #define HRTIM_ICR_FLT2C_Msk (0x1UL << HRTIM_ICR_FLT2C_Pos) /*!< 0x00000002 */
26706 #define HRTIM_ICR_FLT2C HRTIM_ICR_FLT2C_Msk /*!< Fault 2 interrupt flag clear */
26707 #define HRTIM_ICR_FLT3C_Pos (2U)
26708 #define HRTIM_ICR_FLT3C_Msk (0x1UL << HRTIM_ICR_FLT3C_Pos) /*!< 0x00000004 */
26709 #define HRTIM_ICR_FLT3C HRTIM_ICR_FLT3C_Msk /*!< Fault 3 interrupt flag clear */
26710 #define HRTIM_ICR_FLT4C_Pos (3U)
26711 #define HRTIM_ICR_FLT4C_Msk (0x1UL << HRTIM_ICR_FLT4C_Pos) /*!< 0x00000008 */
26712 #define HRTIM_ICR_FLT4C HRTIM_ICR_FLT4C_Msk /*!< Fault 4 interrupt flag clear */
26713 #define HRTIM_ICR_FLT5C_Pos (4U)
26714 #define HRTIM_ICR_FLT5C_Msk (0x1UL << HRTIM_ICR_FLT5C_Pos) /*!< 0x00000010 */
26715 #define HRTIM_ICR_FLT5C HRTIM_ICR_FLT5C_Msk /*!< Fault 5 interrupt flag clear */
26716 #define HRTIM_ICR_SYSFLTC_Pos (5U)
26717 #define HRTIM_ICR_SYSFLTC_Msk (0x1UL << HRTIM_ICR_SYSFLTC_Pos) /*!< 0x00000020 */
26718 #define HRTIM_ICR_SYSFLTC HRTIM_ICR_SYSFLTC_Msk /*!< System Fault interrupt flag clear */
26719 #define HRTIM_ICR_BMPERC_Pos (17U)
26720 #define HRTIM_ICR_BMPERC_Msk (0x1UL << HRTIM_ICR_BMPERC_Pos) /*!< 0x00020000 */
26721 #define HRTIM_ICR_BMPERC HRTIM_ICR_BMPERC_Msk /*!< Burst mode period interrupt flag clear */
26722
26723 /**** Bit definition for Common HRTIM Timer interrupt enable register *********/
26724 #define HRTIM_IER_FLT1_Pos (0U)
26725 #define HRTIM_IER_FLT1_Msk (0x1UL << HRTIM_IER_FLT1_Pos) /*!< 0x00000001 */
26726 #define HRTIM_IER_FLT1 HRTIM_IER_FLT1_Msk /*!< Fault 1 interrupt enable */
26727 #define HRTIM_IER_FLT2_Pos (1U)
26728 #define HRTIM_IER_FLT2_Msk (0x1UL << HRTIM_IER_FLT2_Pos) /*!< 0x00000002 */
26729 #define HRTIM_IER_FLT2 HRTIM_IER_FLT2_Msk /*!< Fault 2 interrupt enable */
26730 #define HRTIM_IER_FLT3_Pos (2U)
26731 #define HRTIM_IER_FLT3_Msk (0x1UL << HRTIM_IER_FLT3_Pos) /*!< 0x00000004 */
26732 #define HRTIM_IER_FLT3 HRTIM_IER_FLT3_Msk /*!< Fault 3 interrupt enable */
26733 #define HRTIM_IER_FLT4_Pos (3U)
26734 #define HRTIM_IER_FLT4_Msk (0x1UL << HRTIM_IER_FLT4_Pos) /*!< 0x00000008 */
26735 #define HRTIM_IER_FLT4 HRTIM_IER_FLT4_Msk /*!< Fault 4 interrupt enable */
26736 #define HRTIM_IER_FLT5_Pos (4U)
26737 #define HRTIM_IER_FLT5_Msk (0x1UL << HRTIM_IER_FLT5_Pos) /*!< 0x00000010 */
26738 #define HRTIM_IER_FLT5 HRTIM_IER_FLT5_Msk /*!< Fault 5 interrupt enable */
26739 #define HRTIM_IER_SYSFLT_Pos (5U)
26740 #define HRTIM_IER_SYSFLT_Msk (0x1UL << HRTIM_IER_SYSFLT_Pos) /*!< 0x00000020 */
26741 #define HRTIM_IER_SYSFLT HRTIM_IER_SYSFLT_Msk /*!< System Fault interrupt enable */
26742 #define HRTIM_IER_BMPER_Pos (17U)
26743 #define HRTIM_IER_BMPER_Msk (0x1UL << HRTIM_IER_BMPER_Pos) /*!< 0x00020000 */
26744 #define HRTIM_IER_BMPER HRTIM_IER_BMPER_Msk /*!< Burst mode period interrupt enable */
26745
26746 /**** Bit definition for Common HRTIM Timer output enable register ************/
26747 #define HRTIM_OENR_TA1OEN_Pos (0U)
26748 #define HRTIM_OENR_TA1OEN_Msk (0x1UL << HRTIM_OENR_TA1OEN_Pos) /*!< 0x00000001 */
26749 #define HRTIM_OENR_TA1OEN HRTIM_OENR_TA1OEN_Msk /*!< Timer A Output 1 enable */
26750 #define HRTIM_OENR_TA2OEN_Pos (1U)
26751 #define HRTIM_OENR_TA2OEN_Msk (0x1UL << HRTIM_OENR_TA2OEN_Pos) /*!< 0x00000002 */
26752 #define HRTIM_OENR_TA2OEN HRTIM_OENR_TA2OEN_Msk /*!< Timer A Output 2 enable */
26753 #define HRTIM_OENR_TB1OEN_Pos (2U)
26754 #define HRTIM_OENR_TB1OEN_Msk (0x1UL << HRTIM_OENR_TB1OEN_Pos) /*!< 0x00000004 */
26755 #define HRTIM_OENR_TB1OEN HRTIM_OENR_TB1OEN_Msk /*!< Timer B Output 1 enable */
26756 #define HRTIM_OENR_TB2OEN_Pos (3U)
26757 #define HRTIM_OENR_TB2OEN_Msk (0x1UL << HRTIM_OENR_TB2OEN_Pos) /*!< 0x00000008 */
26758 #define HRTIM_OENR_TB2OEN HRTIM_OENR_TB2OEN_Msk /*!< Timer B Output 2 enable */
26759 #define HRTIM_OENR_TC1OEN_Pos (4U)
26760 #define HRTIM_OENR_TC1OEN_Msk (0x1UL << HRTIM_OENR_TC1OEN_Pos) /*!< 0x00000010 */
26761 #define HRTIM_OENR_TC1OEN HRTIM_OENR_TC1OEN_Msk /*!< Timer C Output 1 enable */
26762 #define HRTIM_OENR_TC2OEN_Pos (5U)
26763 #define HRTIM_OENR_TC2OEN_Msk (0x1UL << HRTIM_OENR_TC2OEN_Pos) /*!< 0x00000020 */
26764 #define HRTIM_OENR_TC2OEN HRTIM_OENR_TC2OEN_Msk /*!< Timer C Output 2 enable */
26765 #define HRTIM_OENR_TD1OEN_Pos (6U)
26766 #define HRTIM_OENR_TD1OEN_Msk (0x1UL << HRTIM_OENR_TD1OEN_Pos) /*!< 0x00000040 */
26767 #define HRTIM_OENR_TD1OEN HRTIM_OENR_TD1OEN_Msk /*!< Timer D Output 1 enable */
26768 #define HRTIM_OENR_TD2OEN_Pos (7U)
26769 #define HRTIM_OENR_TD2OEN_Msk (0x1UL << HRTIM_OENR_TD2OEN_Pos) /*!< 0x00000080 */
26770 #define HRTIM_OENR_TD2OEN HRTIM_OENR_TD2OEN_Msk /*!< Timer D Output 2 enable */
26771 #define HRTIM_OENR_TE1OEN_Pos (8U)
26772 #define HRTIM_OENR_TE1OEN_Msk (0x1UL << HRTIM_OENR_TE1OEN_Pos) /*!< 0x00000100 */
26773 #define HRTIM_OENR_TE1OEN HRTIM_OENR_TE1OEN_Msk /*!< Timer E Output 1 enable */
26774 #define HRTIM_OENR_TE2OEN_Pos (9U)
26775 #define HRTIM_OENR_TE2OEN_Msk (0x1UL << HRTIM_OENR_TE2OEN_Pos) /*!< 0x00000200 */
26776 #define HRTIM_OENR_TE2OEN HRTIM_OENR_TE2OEN_Msk /*!< Timer E Output 2 enable */
26777
26778 /**** Bit definition for Common HRTIM Timer output disable register ***********/
26779 #define HRTIM_ODISR_TA1ODIS_Pos (0U)
26780 #define HRTIM_ODISR_TA1ODIS_Msk (0x1UL << HRTIM_ODISR_TA1ODIS_Pos) /*!< 0x00000001 */
26781 #define HRTIM_ODISR_TA1ODIS HRTIM_ODISR_TA1ODIS_Msk /*!< Timer A Output 1 disable */
26782 #define HRTIM_ODISR_TA2ODIS_Pos (1U)
26783 #define HRTIM_ODISR_TA2ODIS_Msk (0x1UL << HRTIM_ODISR_TA2ODIS_Pos) /*!< 0x00000002 */
26784 #define HRTIM_ODISR_TA2ODIS HRTIM_ODISR_TA2ODIS_Msk /*!< Timer A Output 2 disable */
26785 #define HRTIM_ODISR_TB1ODIS_Pos (2U)
26786 #define HRTIM_ODISR_TB1ODIS_Msk (0x1UL << HRTIM_ODISR_TB1ODIS_Pos) /*!< 0x00000004 */
26787 #define HRTIM_ODISR_TB1ODIS HRTIM_ODISR_TB1ODIS_Msk /*!< Timer B Output 1 disable */
26788 #define HRTIM_ODISR_TB2ODIS_Pos (3U)
26789 #define HRTIM_ODISR_TB2ODIS_Msk (0x1UL << HRTIM_ODISR_TB2ODIS_Pos) /*!< 0x00000008 */
26790 #define HRTIM_ODISR_TB2ODIS HRTIM_ODISR_TB2ODIS_Msk /*!< Timer B Output 2 disable */
26791 #define HRTIM_ODISR_TC1ODIS_Pos (4U)
26792 #define HRTIM_ODISR_TC1ODIS_Msk (0x1UL << HRTIM_ODISR_TC1ODIS_Pos) /*!< 0x00000010 */
26793 #define HRTIM_ODISR_TC1ODIS HRTIM_ODISR_TC1ODIS_Msk /*!< Timer C Output 1 disable */
26794 #define HRTIM_ODISR_TC2ODIS_Pos (5U)
26795 #define HRTIM_ODISR_TC2ODIS_Msk (0x1UL << HRTIM_ODISR_TC2ODIS_Pos) /*!< 0x00000020 */
26796 #define HRTIM_ODISR_TC2ODIS HRTIM_ODISR_TC2ODIS_Msk /*!< Timer C Output 2 disable */
26797 #define HRTIM_ODISR_TD1ODIS_Pos (6U)
26798 #define HRTIM_ODISR_TD1ODIS_Msk (0x1UL << HRTIM_ODISR_TD1ODIS_Pos) /*!< 0x00000040 */
26799 #define HRTIM_ODISR_TD1ODIS HRTIM_ODISR_TD1ODIS_Msk /*!< Timer D Output 1 disable */
26800 #define HRTIM_ODISR_TD2ODIS_Pos (7U)
26801 #define HRTIM_ODISR_TD2ODIS_Msk (0x1UL << HRTIM_ODISR_TD2ODIS_Pos) /*!< 0x00000080 */
26802 #define HRTIM_ODISR_TD2ODIS HRTIM_ODISR_TD2ODIS_Msk /*!< Timer D Output 2 disable */
26803 #define HRTIM_ODISR_TE1ODIS_Pos (8U)
26804 #define HRTIM_ODISR_TE1ODIS_Msk (0x1UL << HRTIM_ODISR_TE1ODIS_Pos) /*!< 0x00000100 */
26805 #define HRTIM_ODISR_TE1ODIS HRTIM_ODISR_TE1ODIS_Msk /*!< Timer E Output 1 disable */
26806 #define HRTIM_ODISR_TE2ODIS_Pos (9U)
26807 #define HRTIM_ODISR_TE2ODIS_Msk (0x1UL << HRTIM_ODISR_TE2ODIS_Pos) /*!< 0x00000200 */
26808 #define HRTIM_ODISR_TE2ODIS HRTIM_ODISR_TE2ODIS_Msk /*!< Timer E Output 2 disable */
26809
26810 /**** Bit definition for Common HRTIM Timer output disable status register *****/
26811 #define HRTIM_ODSR_TA1ODS_Pos (0U)
26812 #define HRTIM_ODSR_TA1ODS_Msk (0x1UL << HRTIM_ODSR_TA1ODS_Pos) /*!< 0x00000001 */
26813 #define HRTIM_ODSR_TA1ODS HRTIM_ODSR_TA1ODS_Msk /*!< Timer A Output 1 disable status */
26814 #define HRTIM_ODSR_TA2ODS_Pos (1U)
26815 #define HRTIM_ODSR_TA2ODS_Msk (0x1UL << HRTIM_ODSR_TA2ODS_Pos) /*!< 0x00000002 */
26816 #define HRTIM_ODSR_TA2ODS HRTIM_ODSR_TA2ODS_Msk /*!< Timer A Output 2 disable status */
26817 #define HRTIM_ODSR_TB1ODS_Pos (2U)
26818 #define HRTIM_ODSR_TB1ODS_Msk (0x1UL << HRTIM_ODSR_TB1ODS_Pos) /*!< 0x00000004 */
26819 #define HRTIM_ODSR_TB1ODS HRTIM_ODSR_TB1ODS_Msk /*!< Timer B Output 1 disable status */
26820 #define HRTIM_ODSR_TB2ODS_Pos (3U)
26821 #define HRTIM_ODSR_TB2ODS_Msk (0x1UL << HRTIM_ODSR_TB2ODS_Pos) /*!< 0x00000008 */
26822 #define HRTIM_ODSR_TB2ODS HRTIM_ODSR_TB2ODS_Msk /*!< Timer B Output 2 disable status */
26823 #define HRTIM_ODSR_TC1ODS_Pos (4U)
26824 #define HRTIM_ODSR_TC1ODS_Msk (0x1UL << HRTIM_ODSR_TC1ODS_Pos) /*!< 0x00000010 */
26825 #define HRTIM_ODSR_TC1ODS HRTIM_ODSR_TC1ODS_Msk /*!< Timer C Output 1 disable status */
26826 #define HRTIM_ODSR_TC2ODS_Pos (5U)
26827 #define HRTIM_ODSR_TC2ODS_Msk (0x1UL << HRTIM_ODSR_TC2ODS_Pos) /*!< 0x00000020 */
26828 #define HRTIM_ODSR_TC2ODS HRTIM_ODSR_TC2ODS_Msk /*!< Timer C Output 2 disable status */
26829 #define HRTIM_ODSR_TD1ODS_Pos (6U)
26830 #define HRTIM_ODSR_TD1ODS_Msk (0x1UL << HRTIM_ODSR_TD1ODS_Pos) /*!< 0x00000040 */
26831 #define HRTIM_ODSR_TD1ODS HRTIM_ODSR_TD1ODS_Msk /*!< Timer D Output 1 disable status */
26832 #define HRTIM_ODSR_TD2ODS_Pos (7U)
26833 #define HRTIM_ODSR_TD2ODS_Msk (0x1UL << HRTIM_ODSR_TD2ODS_Pos) /*!< 0x00000080 */
26834 #define HRTIM_ODSR_TD2ODS HRTIM_ODSR_TD2ODS_Msk /*!< Timer D Output 2 disable status */
26835 #define HRTIM_ODSR_TE1ODS_Pos (8U)
26836 #define HRTIM_ODSR_TE1ODS_Msk (0x1UL << HRTIM_ODSR_TE1ODS_Pos) /*!< 0x00000100 */
26837 #define HRTIM_ODSR_TE1ODS HRTIM_ODSR_TE1ODS_Msk /*!< Timer E Output 1 disable status */
26838 #define HRTIM_ODSR_TE2ODS_Pos (9U)
26839 #define HRTIM_ODSR_TE2ODS_Msk (0x1UL << HRTIM_ODSR_TE2ODS_Pos) /*!< 0x00000200 */
26840 #define HRTIM_ODSR_TE2ODS HRTIM_ODSR_TE2ODS_Msk /*!< Timer E Output 2 disable status */
26841
26842 /**** Bit definition for Common HRTIM Timer Burst mode control register ********/
26843 #define HRTIM_BMCR_BME_Pos (0U)
26844 #define HRTIM_BMCR_BME_Msk (0x1UL << HRTIM_BMCR_BME_Pos) /*!< 0x00000001 */
26845 #define HRTIM_BMCR_BME HRTIM_BMCR_BME_Msk /*!< Burst mode enbale */
26846 #define HRTIM_BMCR_BMOM_Pos (1U)
26847 #define HRTIM_BMCR_BMOM_Msk (0x1UL << HRTIM_BMCR_BMOM_Pos) /*!< 0x00000002 */
26848 #define HRTIM_BMCR_BMOM HRTIM_BMCR_BMOM_Msk /*!< Burst mode operating mode */
26849 #define HRTIM_BMCR_BMCLK_Pos (2U)
26850 #define HRTIM_BMCR_BMCLK_Msk (0xFUL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x0000003C */
26851 #define HRTIM_BMCR_BMCLK HRTIM_BMCR_BMCLK_Msk /*!< Burst mode clock source */
26852 #define HRTIM_BMCR_BMCLK_0 (0x1UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000004 */
26853 #define HRTIM_BMCR_BMCLK_1 (0x2UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000008 */
26854 #define HRTIM_BMCR_BMCLK_2 (0x4UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000010 */
26855 #define HRTIM_BMCR_BMCLK_3 (0x8UL << HRTIM_BMCR_BMCLK_Pos) /*!< 0x00000020 */
26856 #define HRTIM_BMCR_BMPRSC_Pos (6U)
26857 #define HRTIM_BMCR_BMPRSC_Msk (0xFUL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x000003C0 */
26858 #define HRTIM_BMCR_BMPRSC HRTIM_BMCR_BMPRSC_Msk /*!< Burst mode prescaler */
26859 #define HRTIM_BMCR_BMPRSC_0 (0x1UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000040 */
26860 #define HRTIM_BMCR_BMPRSC_1 (0x2UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000080 */
26861 #define HRTIM_BMCR_BMPRSC_2 (0x4UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000100 */
26862 #define HRTIM_BMCR_BMPRSC_3 (0x8UL << HRTIM_BMCR_BMPRSC_Pos) /*!< 0x00000200 */
26863 #define HRTIM_BMCR_BMPREN_Pos (10U)
26864 #define HRTIM_BMCR_BMPREN_Msk (0x1UL << HRTIM_BMCR_BMPREN_Pos) /*!< 0x00000400 */
26865 #define HRTIM_BMCR_BMPREN HRTIM_BMCR_BMPREN_Msk /*!< Burst mode Preload bit */
26866 #define HRTIM_BMCR_MTBM_Pos (16U)
26867 #define HRTIM_BMCR_MTBM_Msk (0x1UL << HRTIM_BMCR_MTBM_Pos) /*!< 0x00010000 */
26868 #define HRTIM_BMCR_MTBM HRTIM_BMCR_MTBM_Msk /*!< Master Timer Burst mode */
26869 #define HRTIM_BMCR_TABM_Pos (17U)
26870 #define HRTIM_BMCR_TABM_Msk (0x1UL << HRTIM_BMCR_TABM_Pos) /*!< 0x00020000 */
26871 #define HRTIM_BMCR_TABM HRTIM_BMCR_TABM_Msk /*!< Timer A Burst mode */
26872 #define HRTIM_BMCR_TBBM_Pos (18U)
26873 #define HRTIM_BMCR_TBBM_Msk (0x1UL << HRTIM_BMCR_TBBM_Pos) /*!< 0x00040000 */
26874 #define HRTIM_BMCR_TBBM HRTIM_BMCR_TBBM_Msk /*!< Timer B Burst mode */
26875 #define HRTIM_BMCR_TCBM_Pos (19U)
26876 #define HRTIM_BMCR_TCBM_Msk (0x1UL << HRTIM_BMCR_TCBM_Pos) /*!< 0x00080000 */
26877 #define HRTIM_BMCR_TCBM HRTIM_BMCR_TCBM_Msk /*!< Timer C Burst mode */
26878 #define HRTIM_BMCR_TDBM_Pos (20U)
26879 #define HRTIM_BMCR_TDBM_Msk (0x1UL << HRTIM_BMCR_TDBM_Pos) /*!< 0x00100000 */
26880 #define HRTIM_BMCR_TDBM HRTIM_BMCR_TDBM_Msk /*!< Timer D Burst mode */
26881 #define HRTIM_BMCR_TEBM_Pos (21U)
26882 #define HRTIM_BMCR_TEBM_Msk (0x1UL << HRTIM_BMCR_TEBM_Pos) /*!< 0x00200000 */
26883 #define HRTIM_BMCR_TEBM HRTIM_BMCR_TEBM_Msk /*!< Timer E Burst mode */
26884 #define HRTIM_BMCR_BMSTAT_Pos (31U)
26885 #define HRTIM_BMCR_BMSTAT_Msk (0x1UL << HRTIM_BMCR_BMSTAT_Pos) /*!< 0x80000000 */
26886 #define HRTIM_BMCR_BMSTAT HRTIM_BMCR_BMSTAT_Msk /*!< Burst mode status */
26887
26888 /**** Bit definition for Common HRTIM Timer Burst mode Trigger register *******/
26889 #define HRTIM_BMTRGR_SW_Pos (0U)
26890 #define HRTIM_BMTRGR_SW_Msk (0x1UL << HRTIM_BMTRGR_SW_Pos) /*!< 0x00000001 */
26891 #define HRTIM_BMTRGR_SW HRTIM_BMTRGR_SW_Msk /*!< Software start */
26892 #define HRTIM_BMTRGR_MSTRST_Pos (1U)
26893 #define HRTIM_BMTRGR_MSTRST_Msk (0x1UL << HRTIM_BMTRGR_MSTRST_Pos) /*!< 0x00000002 */
26894 #define HRTIM_BMTRGR_MSTRST HRTIM_BMTRGR_MSTRST_Msk /*!< Master reset */
26895 #define HRTIM_BMTRGR_MSTREP_Pos (2U)
26896 #define HRTIM_BMTRGR_MSTREP_Msk (0x1UL << HRTIM_BMTRGR_MSTREP_Pos) /*!< 0x00000004 */
26897 #define HRTIM_BMTRGR_MSTREP HRTIM_BMTRGR_MSTREP_Msk /*!< Master repetition */
26898 #define HRTIM_BMTRGR_MSTCMP1_Pos (3U)
26899 #define HRTIM_BMTRGR_MSTCMP1_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP1_Pos) /*!< 0x00000008 */
26900 #define HRTIM_BMTRGR_MSTCMP1 HRTIM_BMTRGR_MSTCMP1_Msk /*!< Master compare 1 */
26901 #define HRTIM_BMTRGR_MSTCMP2_Pos (4U)
26902 #define HRTIM_BMTRGR_MSTCMP2_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP2_Pos) /*!< 0x00000010 */
26903 #define HRTIM_BMTRGR_MSTCMP2 HRTIM_BMTRGR_MSTCMP2_Msk /*!< Master compare 2 */
26904 #define HRTIM_BMTRGR_MSTCMP3_Pos (5U)
26905 #define HRTIM_BMTRGR_MSTCMP3_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP3_Pos) /*!< 0x00000020 */
26906 #define HRTIM_BMTRGR_MSTCMP3 HRTIM_BMTRGR_MSTCMP3_Msk /*!< Master compare 3 */
26907 #define HRTIM_BMTRGR_MSTCMP4_Pos (6U)
26908 #define HRTIM_BMTRGR_MSTCMP4_Msk (0x1UL << HRTIM_BMTRGR_MSTCMP4_Pos) /*!< 0x00000040 */
26909 #define HRTIM_BMTRGR_MSTCMP4 HRTIM_BMTRGR_MSTCMP4_Msk /*!< Master compare 4 */
26910 #define HRTIM_BMTRGR_TARST_Pos (7U)
26911 #define HRTIM_BMTRGR_TARST_Msk (0x1UL << HRTIM_BMTRGR_TARST_Pos) /*!< 0x00000080 */
26912 #define HRTIM_BMTRGR_TARST HRTIM_BMTRGR_TARST_Msk /*!< Timer A reset */
26913 #define HRTIM_BMTRGR_TAREP_Pos (8U)
26914 #define HRTIM_BMTRGR_TAREP_Msk (0x1UL << HRTIM_BMTRGR_TAREP_Pos) /*!< 0x00000100 */
26915 #define HRTIM_BMTRGR_TAREP HRTIM_BMTRGR_TAREP_Msk /*!< Timer A repetition */
26916 #define HRTIM_BMTRGR_TACMP1_Pos (9U)
26917 #define HRTIM_BMTRGR_TACMP1_Msk (0x1UL << HRTIM_BMTRGR_TACMP1_Pos) /*!< 0x00000200 */
26918 #define HRTIM_BMTRGR_TACMP1 HRTIM_BMTRGR_TACMP1_Msk /*!< Timer A compare 1 */
26919 #define HRTIM_BMTRGR_TACMP2_Pos (10U)
26920 #define HRTIM_BMTRGR_TACMP2_Msk (0x1UL << HRTIM_BMTRGR_TACMP2_Pos) /*!< 0x00000400 */
26921 #define HRTIM_BMTRGR_TACMP2 HRTIM_BMTRGR_TACMP2_Msk /*!< Timer A compare 2 */
26922 #define HRTIM_BMTRGR_TBRST_Pos (11U)
26923 #define HRTIM_BMTRGR_TBRST_Msk (0x1UL << HRTIM_BMTRGR_TBRST_Pos) /*!< 0x00000800 */
26924 #define HRTIM_BMTRGR_TBRST HRTIM_BMTRGR_TBRST_Msk /*!< Timer B reset */
26925 #define HRTIM_BMTRGR_TBREP_Pos (12U)
26926 #define HRTIM_BMTRGR_TBREP_Msk (0x1UL << HRTIM_BMTRGR_TBREP_Pos) /*!< 0x00001000 */
26927 #define HRTIM_BMTRGR_TBREP HRTIM_BMTRGR_TBREP_Msk /*!< Timer B repetition */
26928 #define HRTIM_BMTRGR_TBCMP1_Pos (13U)
26929 #define HRTIM_BMTRGR_TBCMP1_Msk (0x1UL << HRTIM_BMTRGR_TBCMP1_Pos) /*!< 0x00002000 */
26930 #define HRTIM_BMTRGR_TBCMP1 HRTIM_BMTRGR_TBCMP1_Msk /*!< Timer B compare 1 */
26931 #define HRTIM_BMTRGR_TBCMP2_Pos (14U)
26932 #define HRTIM_BMTRGR_TBCMP2_Msk (0x1UL << HRTIM_BMTRGR_TBCMP2_Pos) /*!< 0x00004000 */
26933 #define HRTIM_BMTRGR_TBCMP2 HRTIM_BMTRGR_TBCMP2_Msk /*!< Timer B compare 2 */
26934 #define HRTIM_BMTRGR_TCRST_Pos (15U)
26935 #define HRTIM_BMTRGR_TCRST_Msk (0x1UL << HRTIM_BMTRGR_TCRST_Pos) /*!< 0x00008000 */
26936 #define HRTIM_BMTRGR_TCRST HRTIM_BMTRGR_TCRST_Msk /*!< Timer C reset */
26937 #define HRTIM_BMTRGR_TCREP_Pos (16U)
26938 #define HRTIM_BMTRGR_TCREP_Msk (0x1UL << HRTIM_BMTRGR_TCREP_Pos) /*!< 0x00010000 */
26939 #define HRTIM_BMTRGR_TCREP HRTIM_BMTRGR_TCREP_Msk /*!< Timer C repetition */
26940 #define HRTIM_BMTRGR_TCCMP1_Pos (17U)
26941 #define HRTIM_BMTRGR_TCCMP1_Msk (0x1UL << HRTIM_BMTRGR_TCCMP1_Pos) /*!< 0x00020000 */
26942 #define HRTIM_BMTRGR_TCCMP1 HRTIM_BMTRGR_TCCMP1_Msk /*!< Timer C compare 1 */
26943 #define HRTIM_BMTRGR_TCCMP2_Pos (18U)
26944 #define HRTIM_BMTRGR_TCCMP2_Msk (0x1UL << HRTIM_BMTRGR_TCCMP2_Pos) /*!< 0x00040000 */
26945 #define HRTIM_BMTRGR_TCCMP2 HRTIM_BMTRGR_TCCMP2_Msk /*!< Timer C compare 2 */
26946 #define HRTIM_BMTRGR_TDRST_Pos (19U)
26947 #define HRTIM_BMTRGR_TDRST_Msk (0x1UL << HRTIM_BMTRGR_TDRST_Pos) /*!< 0x00080000 */
26948 #define HRTIM_BMTRGR_TDRST HRTIM_BMTRGR_TDRST_Msk /*!< Timer D reset */
26949 #define HRTIM_BMTRGR_TDREP_Pos (20U)
26950 #define HRTIM_BMTRGR_TDREP_Msk (0x1UL << HRTIM_BMTRGR_TDREP_Pos) /*!< 0x00100000 */
26951 #define HRTIM_BMTRGR_TDREP HRTIM_BMTRGR_TDREP_Msk /*!< Timer D repetition */
26952 #define HRTIM_BMTRGR_TDCMP1_Pos (21U)
26953 #define HRTIM_BMTRGR_TDCMP1_Msk (0x1UL << HRTIM_BMTRGR_TDCMP1_Pos) /*!< 0x00200000 */
26954 #define HRTIM_BMTRGR_TDCMP1 HRTIM_BMTRGR_TDCMP1_Msk /*!< Timer D compare 1 */
26955 #define HRTIM_BMTRGR_TDCMP2_Pos (22U)
26956 #define HRTIM_BMTRGR_TDCMP2_Msk (0x1UL << HRTIM_BMTRGR_TDCMP2_Pos) /*!< 0x00400000 */
26957 #define HRTIM_BMTRGR_TDCMP2 HRTIM_BMTRGR_TDCMP2_Msk /*!< Timer D compare 2 */
26958 #define HRTIM_BMTRGR_TERST_Pos (23U)
26959 #define HRTIM_BMTRGR_TERST_Msk (0x1UL << HRTIM_BMTRGR_TERST_Pos) /*!< 0x00800000 */
26960 #define HRTIM_BMTRGR_TERST HRTIM_BMTRGR_TERST_Msk /*!< Timer E reset */
26961 #define HRTIM_BMTRGR_TEREP_Pos (24U)
26962 #define HRTIM_BMTRGR_TEREP_Msk (0x1UL << HRTIM_BMTRGR_TEREP_Pos) /*!< 0x01000000 */
26963 #define HRTIM_BMTRGR_TEREP HRTIM_BMTRGR_TEREP_Msk /*!< Timer E repetition */
26964 #define HRTIM_BMTRGR_TECMP1_Pos (25U)
26965 #define HRTIM_BMTRGR_TECMP1_Msk (0x1UL << HRTIM_BMTRGR_TECMP1_Pos) /*!< 0x02000000 */
26966 #define HRTIM_BMTRGR_TECMP1 HRTIM_BMTRGR_TECMP1_Msk /*!< Timer E compare 1 */
26967 #define HRTIM_BMTRGR_TECMP2_Pos (26U)
26968 #define HRTIM_BMTRGR_TECMP2_Msk (0x1UL << HRTIM_BMTRGR_TECMP2_Pos) /*!< 0x04000000 */
26969 #define HRTIM_BMTRGR_TECMP2 HRTIM_BMTRGR_TECMP2_Msk /*!< Timer E compare 2 */
26970 #define HRTIM_BMTRGR_TAEEV7_Pos (27U)
26971 #define HRTIM_BMTRGR_TAEEV7_Msk (0x1UL << HRTIM_BMTRGR_TAEEV7_Pos) /*!< 0x08000000 */
26972 #define HRTIM_BMTRGR_TAEEV7 HRTIM_BMTRGR_TAEEV7_Msk /*!< Timer A period following External Event7 */
26973 #define HRTIM_BMTRGR_TDEEV8_Pos (28U)
26974 #define HRTIM_BMTRGR_TDEEV8_Msk (0x1UL << HRTIM_BMTRGR_TDEEV8_Pos) /*!< 0x10000000 */
26975 #define HRTIM_BMTRGR_TDEEV8 HRTIM_BMTRGR_TDEEV8_Msk /*!< Timer D period following External Event8 */
26976 #define HRTIM_BMTRGR_EEV7_Pos (29U)
26977 #define HRTIM_BMTRGR_EEV7_Msk (0x1UL << HRTIM_BMTRGR_EEV7_Pos) /*!< 0x20000000 */
26978 #define HRTIM_BMTRGR_EEV7 HRTIM_BMTRGR_EEV7_Msk /*!< External Event 7 */
26979 #define HRTIM_BMTRGR_EEV8_Pos (30U)
26980 #define HRTIM_BMTRGR_EEV8_Msk (0x1UL << HRTIM_BMTRGR_EEV8_Pos) /*!< 0x40000000 */
26981 #define HRTIM_BMTRGR_EEV8 HRTIM_BMTRGR_EEV8_Msk /*!< External Event 8 */
26982 #define HRTIM_BMTRGR_OCHPEV_Pos (31U)
26983 #define HRTIM_BMTRGR_OCHPEV_Msk (0x1UL << HRTIM_BMTRGR_OCHPEV_Pos) /*!< 0x80000000 */
26984 #define HRTIM_BMTRGR_OCHPEV HRTIM_BMTRGR_OCHPEV_Msk /*!< on-chip Event */
26985
26986 /******************* Bit definition for HRTIM_BMCMPR register ***************/
26987 #define HRTIM_BMCMPR_BMCMPR_Pos (0U)
26988 #define HRTIM_BMCMPR_BMCMPR_Msk (0xFFFFUL << HRTIM_BMCMPR_BMCMPR_Pos) /*!< 0x0000FFFF */
26989 #define HRTIM_BMCMPR_BMCMPR HRTIM_BMCMPR_BMCMPR_Msk /*!<!<Burst Compare Value */
26990
26991 /******************* Bit definition for HRTIM_BMPER register ****************/
26992 #define HRTIM_BMPER_BMPER_Pos (0U)
26993 #define HRTIM_BMPER_BMPER_Msk (0xFFFFUL << HRTIM_BMPER_BMPER_Pos) /*!< 0x0000FFFF */
26994 #define HRTIM_BMPER_BMPER HRTIM_BMPER_BMPER_Msk /*!<!<Burst period Value */
26995
26996 /******************* Bit definition for HRTIM_EECR1 register ****************/
26997 #define HRTIM_EECR1_EE1SRC_Pos (0U)
26998 #define HRTIM_EECR1_EE1SRC_Msk (0x3UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000003 */
26999 #define HRTIM_EECR1_EE1SRC HRTIM_EECR1_EE1SRC_Msk /*!< External event 1 source */
27000 #define HRTIM_EECR1_EE1SRC_0 (0x1UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000001 */
27001 #define HRTIM_EECR1_EE1SRC_1 (0x2UL << HRTIM_EECR1_EE1SRC_Pos) /*!< 0x00000002 */
27002 #define HRTIM_EECR1_EE1POL_Pos (2U)
27003 #define HRTIM_EECR1_EE1POL_Msk (0x1UL << HRTIM_EECR1_EE1POL_Pos) /*!< 0x00000004 */
27004 #define HRTIM_EECR1_EE1POL HRTIM_EECR1_EE1POL_Msk /*!< External event 1 Polarity */
27005 #define HRTIM_EECR1_EE1SNS_Pos (3U)
27006 #define HRTIM_EECR1_EE1SNS_Msk (0x3UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000018 */
27007 #define HRTIM_EECR1_EE1SNS HRTIM_EECR1_EE1SNS_Msk /*!< External event 1 sensitivity */
27008 #define HRTIM_EECR1_EE1SNS_0 (0x1UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000008 */
27009 #define HRTIM_EECR1_EE1SNS_1 (0x2UL << HRTIM_EECR1_EE1SNS_Pos) /*!< 0x00000010 */
27010 #define HRTIM_EECR1_EE1FAST_Pos (5U)
27011 #define HRTIM_EECR1_EE1FAST_Msk (0x1UL << HRTIM_EECR1_EE1FAST_Pos) /*!< 0x00000020 */
27012 #define HRTIM_EECR1_EE1FAST HRTIM_EECR1_EE1FAST_Msk /*!< External event 1 Fast mode */
27013
27014 #define HRTIM_EECR1_EE2SRC_Pos (6U)
27015 #define HRTIM_EECR1_EE2SRC_Msk (0x3UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x000000C0 */
27016 #define HRTIM_EECR1_EE2SRC HRTIM_EECR1_EE2SRC_Msk /*!< External event 2 source */
27017 #define HRTIM_EECR1_EE2SRC_0 (0x1UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000040 */
27018 #define HRTIM_EECR1_EE2SRC_1 (0x2UL << HRTIM_EECR1_EE2SRC_Pos) /*!< 0x00000080 */
27019 #define HRTIM_EECR1_EE2POL_Pos (8U)
27020 #define HRTIM_EECR1_EE2POL_Msk (0x1UL << HRTIM_EECR1_EE2POL_Pos) /*!< 0x00000100 */
27021 #define HRTIM_EECR1_EE2POL HRTIM_EECR1_EE2POL_Msk /*!< External event 2 Polarity */
27022 #define HRTIM_EECR1_EE2SNS_Pos (9U)
27023 #define HRTIM_EECR1_EE2SNS_Msk (0x3UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000600 */
27024 #define HRTIM_EECR1_EE2SNS HRTIM_EECR1_EE2SNS_Msk /*!< External event 2 sensitivity */
27025 #define HRTIM_EECR1_EE2SNS_0 (0x1UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000200 */
27026 #define HRTIM_EECR1_EE2SNS_1 (0x2UL << HRTIM_EECR1_EE2SNS_Pos) /*!< 0x00000400 */
27027 #define HRTIM_EECR1_EE2FAST_Pos (11U)
27028 #define HRTIM_EECR1_EE2FAST_Msk (0x1UL << HRTIM_EECR1_EE2FAST_Pos) /*!< 0x00000800 */
27029 #define HRTIM_EECR1_EE2FAST HRTIM_EECR1_EE2FAST_Msk /*!< External event 2 Fast mode */
27030
27031 #define HRTIM_EECR1_EE3SRC_Pos (12U)
27032 #define HRTIM_EECR1_EE3SRC_Msk (0x3UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00003000 */
27033 #define HRTIM_EECR1_EE3SRC HRTIM_EECR1_EE3SRC_Msk /*!< External event 3 source */
27034 #define HRTIM_EECR1_EE3SRC_0 (0x1UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00001000 */
27035 #define HRTIM_EECR1_EE3SRC_1 (0x2UL << HRTIM_EECR1_EE3SRC_Pos) /*!< 0x00002000 */
27036 #define HRTIM_EECR1_EE3POL_Pos (14U)
27037 #define HRTIM_EECR1_EE3POL_Msk (0x1UL << HRTIM_EECR1_EE3POL_Pos) /*!< 0x00004000 */
27038 #define HRTIM_EECR1_EE3POL HRTIM_EECR1_EE3POL_Msk /*!< External event 3 Polarity */
27039 #define HRTIM_EECR1_EE3SNS_Pos (15U)
27040 #define HRTIM_EECR1_EE3SNS_Msk (0x3UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00018000 */
27041 #define HRTIM_EECR1_EE3SNS HRTIM_EECR1_EE3SNS_Msk /*!< External event 3 sensitivity */
27042 #define HRTIM_EECR1_EE3SNS_0 (0x1UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00008000 */
27043 #define HRTIM_EECR1_EE3SNS_1 (0x2UL << HRTIM_EECR1_EE3SNS_Pos) /*!< 0x00010000 */
27044 #define HRTIM_EECR1_EE3FAST_Pos (17U)
27045 #define HRTIM_EECR1_EE3FAST_Msk (0x1UL << HRTIM_EECR1_EE3FAST_Pos) /*!< 0x00020000 */
27046 #define HRTIM_EECR1_EE3FAST HRTIM_EECR1_EE3FAST_Msk /*!< External event 3 Fast mode */
27047
27048 #define HRTIM_EECR1_EE4SRC_Pos (18U)
27049 #define HRTIM_EECR1_EE4SRC_Msk (0x3UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x000C0000 */
27050 #define HRTIM_EECR1_EE4SRC HRTIM_EECR1_EE4SRC_Msk /*!< External event 4 source */
27051 #define HRTIM_EECR1_EE4SRC_0 (0x1UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00040000 */
27052 #define HRTIM_EECR1_EE4SRC_1 (0x2UL << HRTIM_EECR1_EE4SRC_Pos) /*!< 0x00080000 */
27053 #define HRTIM_EECR1_EE4POL_Pos (20U)
27054 #define HRTIM_EECR1_EE4POL_Msk (0x1UL << HRTIM_EECR1_EE4POL_Pos) /*!< 0x00100000 */
27055 #define HRTIM_EECR1_EE4POL HRTIM_EECR1_EE4POL_Msk /*!< External event 4 Polarity */
27056 #define HRTIM_EECR1_EE4SNS_Pos (21U)
27057 #define HRTIM_EECR1_EE4SNS_Msk (0x3UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00600000 */
27058 #define HRTIM_EECR1_EE4SNS HRTIM_EECR1_EE4SNS_Msk /*!< External event 4 sensitivity */
27059 #define HRTIM_EECR1_EE4SNS_0 (0x1UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00200000 */
27060 #define HRTIM_EECR1_EE4SNS_1 (0x2UL << HRTIM_EECR1_EE4SNS_Pos) /*!< 0x00400000 */
27061 #define HRTIM_EECR1_EE4FAST_Pos (23U)
27062 #define HRTIM_EECR1_EE4FAST_Msk (0x1UL << HRTIM_EECR1_EE4FAST_Pos) /*!< 0x00800000 */
27063 #define HRTIM_EECR1_EE4FAST HRTIM_EECR1_EE4FAST_Msk /*!< External event 4 Fast mode */
27064
27065 #define HRTIM_EECR1_EE5SRC_Pos (24U)
27066 #define HRTIM_EECR1_EE5SRC_Msk (0x3UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x03000000 */
27067 #define HRTIM_EECR1_EE5SRC HRTIM_EECR1_EE5SRC_Msk /*!< External event 5 source */
27068 #define HRTIM_EECR1_EE5SRC_0 (0x1UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x01000000 */
27069 #define HRTIM_EECR1_EE5SRC_1 (0x2UL << HRTIM_EECR1_EE5SRC_Pos) /*!< 0x02000000 */
27070 #define HRTIM_EECR1_EE5POL_Pos (26U)
27071 #define HRTIM_EECR1_EE5POL_Msk (0x1UL << HRTIM_EECR1_EE5POL_Pos) /*!< 0x04000000 */
27072 #define HRTIM_EECR1_EE5POL HRTIM_EECR1_EE5POL_Msk /*!< External event 5 Polarity */
27073 #define HRTIM_EECR1_EE5SNS_Pos (27U)
27074 #define HRTIM_EECR1_EE5SNS_Msk (0x3UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x18000000 */
27075 #define HRTIM_EECR1_EE5SNS HRTIM_EECR1_EE5SNS_Msk /*!< External event 5 sensitivity */
27076 #define HRTIM_EECR1_EE5SNS_0 (0x1UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x08000000 */
27077 #define HRTIM_EECR1_EE5SNS_1 (0x2UL << HRTIM_EECR1_EE5SNS_Pos) /*!< 0x10000000 */
27078 #define HRTIM_EECR1_EE5FAST_Pos (29U)
27079 #define HRTIM_EECR1_EE5FAST_Msk (0x1UL << HRTIM_EECR1_EE5FAST_Pos) /*!< 0x20000000 */
27080 #define HRTIM_EECR1_EE5FAST HRTIM_EECR1_EE5FAST_Msk /*!< External event 5 Fast mode */
27081
27082 /******************* Bit definition for HRTIM_EECR2 register ****************/
27083 #define HRTIM_EECR2_EE6SRC_Pos (0U)
27084 #define HRTIM_EECR2_EE6SRC_Msk (0x3UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000003 */
27085 #define HRTIM_EECR2_EE6SRC HRTIM_EECR2_EE6SRC_Msk /*!< External event 6 source */
27086 #define HRTIM_EECR2_EE6SRC_0 (0x1UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000001 */
27087 #define HRTIM_EECR2_EE6SRC_1 (0x2UL << HRTIM_EECR2_EE6SRC_Pos) /*!< 0x00000002 */
27088 #define HRTIM_EECR2_EE6POL_Pos (2U)
27089 #define HRTIM_EECR2_EE6POL_Msk (0x1UL << HRTIM_EECR2_EE6POL_Pos) /*!< 0x00000004 */
27090 #define HRTIM_EECR2_EE6POL HRTIM_EECR2_EE6POL_Msk /*!< External event 6 Polarity */
27091 #define HRTIM_EECR2_EE6SNS_Pos (3U)
27092 #define HRTIM_EECR2_EE6SNS_Msk (0x3UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000018 */
27093 #define HRTIM_EECR2_EE6SNS HRTIM_EECR2_EE6SNS_Msk /*!< External event 6 sensitivity */
27094 #define HRTIM_EECR2_EE6SNS_0 (0x1UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000008 */
27095 #define HRTIM_EECR2_EE6SNS_1 (0x2UL << HRTIM_EECR2_EE6SNS_Pos) /*!< 0x00000010 */
27096
27097 #define HRTIM_EECR2_EE7SRC_Pos (6U)
27098 #define HRTIM_EECR2_EE7SRC_Msk (0x3UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x000000C0 */
27099 #define HRTIM_EECR2_EE7SRC HRTIM_EECR2_EE7SRC_Msk /*!< External event 7 source */
27100 #define HRTIM_EECR2_EE7SRC_0 (0x1UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000040 */
27101 #define HRTIM_EECR2_EE7SRC_1 (0x2UL << HRTIM_EECR2_EE7SRC_Pos) /*!< 0x00000080 */
27102 #define HRTIM_EECR2_EE7POL_Pos (8U)
27103 #define HRTIM_EECR2_EE7POL_Msk (0x1UL << HRTIM_EECR2_EE7POL_Pos) /*!< 0x00000100 */
27104 #define HRTIM_EECR2_EE7POL HRTIM_EECR2_EE7POL_Msk /*!< External event 7 Polarity */
27105 #define HRTIM_EECR2_EE7SNS_Pos (9U)
27106 #define HRTIM_EECR2_EE7SNS_Msk (0x3UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000600 */
27107 #define HRTIM_EECR2_EE7SNS HRTIM_EECR2_EE7SNS_Msk /*!< External event 7 sensitivity */
27108 #define HRTIM_EECR2_EE7SNS_0 (0x1UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000200 */
27109 #define HRTIM_EECR2_EE7SNS_1 (0x2UL << HRTIM_EECR2_EE7SNS_Pos) /*!< 0x00000400 */
27110
27111 #define HRTIM_EECR2_EE8SRC_Pos (12U)
27112 #define HRTIM_EECR2_EE8SRC_Msk (0x3UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00003000 */
27113 #define HRTIM_EECR2_EE8SRC HRTIM_EECR2_EE8SRC_Msk /*!< External event 8 source */
27114 #define HRTIM_EECR2_EE8SRC_0 (0x1UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00001000 */
27115 #define HRTIM_EECR2_EE8SRC_1 (0x2UL << HRTIM_EECR2_EE8SRC_Pos) /*!< 0x00002000 */
27116 #define HRTIM_EECR2_EE8POL_Pos (14U)
27117 #define HRTIM_EECR2_EE8POL_Msk (0x1UL << HRTIM_EECR2_EE8POL_Pos) /*!< 0x00004000 */
27118 #define HRTIM_EECR2_EE8POL HRTIM_EECR2_EE8POL_Msk /*!< External event 8 Polarity */
27119 #define HRTIM_EECR2_EE8SNS_Pos (15U)
27120 #define HRTIM_EECR2_EE8SNS_Msk (0x3UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00018000 */
27121 #define HRTIM_EECR2_EE8SNS HRTIM_EECR2_EE8SNS_Msk /*!< External event 8 sensitivity */
27122 #define HRTIM_EECR2_EE8SNS_0 (0x1UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00008000 */
27123 #define HRTIM_EECR2_EE8SNS_1 (0x2UL << HRTIM_EECR2_EE8SNS_Pos) /*!< 0x00010000 */
27124
27125 #define HRTIM_EECR2_EE9SRC_Pos (18U)
27126 #define HRTIM_EECR2_EE9SRC_Msk (0x3UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x000C0000 */
27127 #define HRTIM_EECR2_EE9SRC HRTIM_EECR2_EE9SRC_Msk /*!< External event 9 source */
27128 #define HRTIM_EECR2_EE9SRC_0 (0x1UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00040000 */
27129 #define HRTIM_EECR2_EE9SRC_1 (0x2UL << HRTIM_EECR2_EE9SRC_Pos) /*!< 0x00080000 */
27130 #define HRTIM_EECR2_EE9POL_Pos (20U)
27131 #define HRTIM_EECR2_EE9POL_Msk (0x1UL << HRTIM_EECR2_EE9POL_Pos) /*!< 0x00100000 */
27132 #define HRTIM_EECR2_EE9POL HRTIM_EECR2_EE9POL_Msk /*!< External event 9 Polarity */
27133 #define HRTIM_EECR2_EE9SNS_Pos (21U)
27134 #define HRTIM_EECR2_EE9SNS_Msk (0x3UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00600000 */
27135 #define HRTIM_EECR2_EE9SNS HRTIM_EECR2_EE9SNS_Msk /*!< External event 9 sensitivity */
27136 #define HRTIM_EECR2_EE9SNS_0 (0x1UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00200000 */
27137 #define HRTIM_EECR2_EE9SNS_1 (0x2UL << HRTIM_EECR2_EE9SNS_Pos) /*!< 0x00400000 */
27138
27139 #define HRTIM_EECR2_EE10SRC_Pos (24U)
27140 #define HRTIM_EECR2_EE10SRC_Msk (0x3UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x03000000 */
27141 #define HRTIM_EECR2_EE10SRC HRTIM_EECR2_EE10SRC_Msk /*!< External event 10 source */
27142 #define HRTIM_EECR2_EE10SRC_0 (0x1UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x01000000 */
27143 #define HRTIM_EECR2_EE10SRC_1 (0x2UL << HRTIM_EECR2_EE10SRC_Pos) /*!< 0x02000000 */
27144 #define HRTIM_EECR2_EE10POL_Pos (26U)
27145 #define HRTIM_EECR2_EE10POL_Msk (0x1UL << HRTIM_EECR2_EE10POL_Pos) /*!< 0x04000000 */
27146 #define HRTIM_EECR2_EE10POL HRTIM_EECR2_EE10POL_Msk /*!< External event 10 Polarity */
27147 #define HRTIM_EECR2_EE10SNS_Pos (27U)
27148 #define HRTIM_EECR2_EE10SNS_Msk (0x3UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x18000000 */
27149 #define HRTIM_EECR2_EE10SNS HRTIM_EECR2_EE10SNS_Msk /*!< External event 10 sensitivity */
27150 #define HRTIM_EECR2_EE10SNS_0 (0x1UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x08000000 */
27151 #define HRTIM_EECR2_EE10SNS_1 (0x2UL << HRTIM_EECR2_EE10SNS_Pos) /*!< 0x10000000 */
27152
27153 /******************* Bit definition for HRTIM_EECR3 register ****************/
27154 #define HRTIM_EECR3_EE6F_Pos (0U)
27155 #define HRTIM_EECR3_EE6F_Msk (0xFUL << HRTIM_EECR3_EE6F_Pos) /*!< 0x0000000F */
27156 #define HRTIM_EECR3_EE6F HRTIM_EECR3_EE6F_Msk /*!< External event 6 filter */
27157 #define HRTIM_EECR3_EE6F_0 (0x1UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000001 */
27158 #define HRTIM_EECR3_EE6F_1 (0x2UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000002 */
27159 #define HRTIM_EECR3_EE6F_2 (0x4UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000004 */
27160 #define HRTIM_EECR3_EE6F_3 (0x8UL << HRTIM_EECR3_EE6F_Pos) /*!< 0x00000008 */
27161 #define HRTIM_EECR3_EE7F_Pos (6U)
27162 #define HRTIM_EECR3_EE7F_Msk (0xFUL << HRTIM_EECR3_EE7F_Pos) /*!< 0x000003C0 */
27163 #define HRTIM_EECR3_EE7F HRTIM_EECR3_EE7F_Msk /*!< External event 7 filter */
27164 #define HRTIM_EECR3_EE7F_0 (0x1UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000040 */
27165 #define HRTIM_EECR3_EE7F_1 (0x2UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000080 */
27166 #define HRTIM_EECR3_EE7F_2 (0x4UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000100 */
27167 #define HRTIM_EECR3_EE7F_3 (0x8UL << HRTIM_EECR3_EE7F_Pos) /*!< 0x00000200 */
27168 #define HRTIM_EECR3_EE8F_Pos (12U)
27169 #define HRTIM_EECR3_EE8F_Msk (0xFUL << HRTIM_EECR3_EE8F_Pos) /*!< 0x0000F000 */
27170 #define HRTIM_EECR3_EE8F HRTIM_EECR3_EE8F_Msk /*!< External event 8 filter */
27171 #define HRTIM_EECR3_EE8F_0 (0x1UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00001000 */
27172 #define HRTIM_EECR3_EE8F_1 (0x2UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00002000 */
27173 #define HRTIM_EECR3_EE8F_2 (0x4UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00004000 */
27174 #define HRTIM_EECR3_EE8F_3 (0x8UL << HRTIM_EECR3_EE8F_Pos) /*!< 0x00008000 */
27175 #define HRTIM_EECR3_EE9F_Pos (18U)
27176 #define HRTIM_EECR3_EE9F_Msk (0xFUL << HRTIM_EECR3_EE9F_Pos) /*!< 0x003C0000 */
27177 #define HRTIM_EECR3_EE9F HRTIM_EECR3_EE9F_Msk /*!< External event 9 filter */
27178 #define HRTIM_EECR3_EE9F_0 (0x1UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00040000 */
27179 #define HRTIM_EECR3_EE9F_1 (0x2UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00080000 */
27180 #define HRTIM_EECR3_EE9F_2 (0x4UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00100000 */
27181 #define HRTIM_EECR3_EE9F_3 (0x8UL << HRTIM_EECR3_EE9F_Pos) /*!< 0x00200000 */
27182 #define HRTIM_EECR3_EE10F_Pos (24U)
27183 #define HRTIM_EECR3_EE10F_Msk (0xFUL << HRTIM_EECR3_EE10F_Pos) /*!< 0x0F000000 */
27184 #define HRTIM_EECR3_EE10F HRTIM_EECR3_EE10F_Msk /*!< External event 10 filter */
27185 #define HRTIM_EECR3_EE10F_0 (0x1UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x01000000 */
27186 #define HRTIM_EECR3_EE10F_1 (0x2UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x02000000 */
27187 #define HRTIM_EECR3_EE10F_2 (0x4UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x04000000 */
27188 #define HRTIM_EECR3_EE10F_3 (0x8UL << HRTIM_EECR3_EE10F_Pos) /*!< 0x08000000 */
27189 #define HRTIM_EECR3_EEVSD_Pos (30U)
27190 #define HRTIM_EECR3_EEVSD_Msk (0x3UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0xC0000000 */
27191 #define HRTIM_EECR3_EEVSD HRTIM_EECR3_EEVSD_Msk /*!< External event sampling clock division */
27192 #define HRTIM_EECR3_EEVSD_0 (0x1UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x40000000 */
27193 #define HRTIM_EECR3_EEVSD_1 (0x2UL << HRTIM_EECR3_EEVSD_Pos) /*!< 0x80000000 */
27194
27195 /******************* Bit definition for HRTIM_ADC1R register ****************/
27196 #define HRTIM_ADC1R_AD1MC1_Pos (0U)
27197 #define HRTIM_ADC1R_AD1MC1_Msk (0x1UL << HRTIM_ADC1R_AD1MC1_Pos) /*!< 0x00000001 */
27198 #define HRTIM_ADC1R_AD1MC1 HRTIM_ADC1R_AD1MC1_Msk /*!< ADC Trigger 1 on master compare 1 */
27199 #define HRTIM_ADC1R_AD1MC2_Pos (1U)
27200 #define HRTIM_ADC1R_AD1MC2_Msk (0x1UL << HRTIM_ADC1R_AD1MC2_Pos) /*!< 0x00000002 */
27201 #define HRTIM_ADC1R_AD1MC2 HRTIM_ADC1R_AD1MC2_Msk /*!< ADC Trigger 1 on master compare 2 */
27202 #define HRTIM_ADC1R_AD1MC3_Pos (2U)
27203 #define HRTIM_ADC1R_AD1MC3_Msk (0x1UL << HRTIM_ADC1R_AD1MC3_Pos) /*!< 0x00000004 */
27204 #define HRTIM_ADC1R_AD1MC3 HRTIM_ADC1R_AD1MC3_Msk /*!< ADC Trigger 1 on master compare 3 */
27205 #define HRTIM_ADC1R_AD1MC4_Pos (3U)
27206 #define HRTIM_ADC1R_AD1MC4_Msk (0x1UL << HRTIM_ADC1R_AD1MC4_Pos) /*!< 0x00000008 */
27207 #define HRTIM_ADC1R_AD1MC4 HRTIM_ADC1R_AD1MC4_Msk /*!< ADC Trigger 1 on master compare 4 */
27208 #define HRTIM_ADC1R_AD1MPER_Pos (4U)
27209 #define HRTIM_ADC1R_AD1MPER_Msk (0x1UL << HRTIM_ADC1R_AD1MPER_Pos) /*!< 0x00000010 */
27210 #define HRTIM_ADC1R_AD1MPER HRTIM_ADC1R_AD1MPER_Msk /*!< ADC Trigger 1 on master period */
27211 #define HRTIM_ADC1R_AD1EEV1_Pos (5U)
27212 #define HRTIM_ADC1R_AD1EEV1_Msk (0x1UL << HRTIM_ADC1R_AD1EEV1_Pos) /*!< 0x00000020 */
27213 #define HRTIM_ADC1R_AD1EEV1 HRTIM_ADC1R_AD1EEV1_Msk /*!< ADC Trigger 1 on external event 1 */
27214 #define HRTIM_ADC1R_AD1EEV2_Pos (6U)
27215 #define HRTIM_ADC1R_AD1EEV2_Msk (0x1UL << HRTIM_ADC1R_AD1EEV2_Pos) /*!< 0x00000040 */
27216 #define HRTIM_ADC1R_AD1EEV2 HRTIM_ADC1R_AD1EEV2_Msk /*!< ADC Trigger 1 on external event 2 */
27217 #define HRTIM_ADC1R_AD1EEV3_Pos (7U)
27218 #define HRTIM_ADC1R_AD1EEV3_Msk (0x1UL << HRTIM_ADC1R_AD1EEV3_Pos) /*!< 0x00000080 */
27219 #define HRTIM_ADC1R_AD1EEV3 HRTIM_ADC1R_AD1EEV3_Msk /*!< ADC Trigger 1 on external event 3 */
27220 #define HRTIM_ADC1R_AD1EEV4_Pos (8U)
27221 #define HRTIM_ADC1R_AD1EEV4_Msk (0x1UL << HRTIM_ADC1R_AD1EEV4_Pos) /*!< 0x00000100 */
27222 #define HRTIM_ADC1R_AD1EEV4 HRTIM_ADC1R_AD1EEV4_Msk /*!< ADC Trigger 1 on external event 4 */
27223 #define HRTIM_ADC1R_AD1EEV5_Pos (9U)
27224 #define HRTIM_ADC1R_AD1EEV5_Msk (0x1UL << HRTIM_ADC1R_AD1EEV5_Pos) /*!< 0x00000200 */
27225 #define HRTIM_ADC1R_AD1EEV5 HRTIM_ADC1R_AD1EEV5_Msk /*!< ADC Trigger 1 on external event 5 */
27226 #define HRTIM_ADC1R_AD1TAC2_Pos (10U)
27227 #define HRTIM_ADC1R_AD1TAC2_Msk (0x1UL << HRTIM_ADC1R_AD1TAC2_Pos) /*!< 0x00000400 */
27228 #define HRTIM_ADC1R_AD1TAC2 HRTIM_ADC1R_AD1TAC2_Msk /*!< ADC Trigger 1 on Timer A compare 2 */
27229 #define HRTIM_ADC1R_AD1TAC3_Pos (11U)
27230 #define HRTIM_ADC1R_AD1TAC3_Msk (0x1UL << HRTIM_ADC1R_AD1TAC3_Pos) /*!< 0x00000800 */
27231 #define HRTIM_ADC1R_AD1TAC3 HRTIM_ADC1R_AD1TAC3_Msk /*!< ADC Trigger 1 on Timer A compare 3 */
27232 #define HRTIM_ADC1R_AD1TAC4_Pos (12U)
27233 #define HRTIM_ADC1R_AD1TAC4_Msk (0x1UL << HRTIM_ADC1R_AD1TAC4_Pos) /*!< 0x00001000 */
27234 #define HRTIM_ADC1R_AD1TAC4 HRTIM_ADC1R_AD1TAC4_Msk /*!< ADC Trigger 1 on Timer A compare 4 */
27235 #define HRTIM_ADC1R_AD1TAPER_Pos (13U)
27236 #define HRTIM_ADC1R_AD1TAPER_Msk (0x1UL << HRTIM_ADC1R_AD1TAPER_Pos) /*!< 0x00002000 */
27237 #define HRTIM_ADC1R_AD1TAPER HRTIM_ADC1R_AD1TAPER_Msk /*!< ADC Trigger 1 on Timer A period */
27238 #define HRTIM_ADC1R_AD1TARST_Pos (14U)
27239 #define HRTIM_ADC1R_AD1TARST_Msk (0x1UL << HRTIM_ADC1R_AD1TARST_Pos) /*!< 0x00004000 */
27240 #define HRTIM_ADC1R_AD1TARST HRTIM_ADC1R_AD1TARST_Msk /*!< ADC Trigger 1 on Timer A reset */
27241 #define HRTIM_ADC1R_AD1TBC2_Pos (15U)
27242 #define HRTIM_ADC1R_AD1TBC2_Msk (0x1UL << HRTIM_ADC1R_AD1TBC2_Pos) /*!< 0x00008000 */
27243 #define HRTIM_ADC1R_AD1TBC2 HRTIM_ADC1R_AD1TBC2_Msk /*!< ADC Trigger 1 on Timer B compare 2 */
27244 #define HRTIM_ADC1R_AD1TBC3_Pos (16U)
27245 #define HRTIM_ADC1R_AD1TBC3_Msk (0x1UL << HRTIM_ADC1R_AD1TBC3_Pos) /*!< 0x00010000 */
27246 #define HRTIM_ADC1R_AD1TBC3 HRTIM_ADC1R_AD1TBC3_Msk /*!< ADC Trigger 1 on Timer B compare 3 */
27247 #define HRTIM_ADC1R_AD1TBC4_Pos (17U)
27248 #define HRTIM_ADC1R_AD1TBC4_Msk (0x1UL << HRTIM_ADC1R_AD1TBC4_Pos) /*!< 0x00020000 */
27249 #define HRTIM_ADC1R_AD1TBC4 HRTIM_ADC1R_AD1TBC4_Msk /*!< ADC Trigger 1 on Timer B compare 4 */
27250 #define HRTIM_ADC1R_AD1TBPER_Pos (18U)
27251 #define HRTIM_ADC1R_AD1TBPER_Msk (0x1UL << HRTIM_ADC1R_AD1TBPER_Pos) /*!< 0x00040000 */
27252 #define HRTIM_ADC1R_AD1TBPER HRTIM_ADC1R_AD1TBPER_Msk /*!< ADC Trigger 1 on Timer B period */
27253 #define HRTIM_ADC1R_AD1TBRST_Pos (19U)
27254 #define HRTIM_ADC1R_AD1TBRST_Msk (0x1UL << HRTIM_ADC1R_AD1TBRST_Pos) /*!< 0x00080000 */
27255 #define HRTIM_ADC1R_AD1TBRST HRTIM_ADC1R_AD1TBRST_Msk /*!< ADC Trigger 1 on Timer B reset */
27256 #define HRTIM_ADC1R_AD1TCC2_Pos (20U)
27257 #define HRTIM_ADC1R_AD1TCC2_Msk (0x1UL << HRTIM_ADC1R_AD1TCC2_Pos) /*!< 0x00100000 */
27258 #define HRTIM_ADC1R_AD1TCC2 HRTIM_ADC1R_AD1TCC2_Msk /*!< ADC Trigger 1 on Timer C compare 2 */
27259 #define HRTIM_ADC1R_AD1TCC3_Pos (21U)
27260 #define HRTIM_ADC1R_AD1TCC3_Msk (0x1UL << HRTIM_ADC1R_AD1TCC3_Pos) /*!< 0x00200000 */
27261 #define HRTIM_ADC1R_AD1TCC3 HRTIM_ADC1R_AD1TCC3_Msk /*!< ADC Trigger 1 on Timer C compare 3 */
27262 #define HRTIM_ADC1R_AD1TCC4_Pos (22U)
27263 #define HRTIM_ADC1R_AD1TCC4_Msk (0x1UL << HRTIM_ADC1R_AD1TCC4_Pos) /*!< 0x00400000 */
27264 #define HRTIM_ADC1R_AD1TCC4 HRTIM_ADC1R_AD1TCC4_Msk /*!< ADC Trigger 1 on Timer C compare 4 */
27265 #define HRTIM_ADC1R_AD1TCPER_Pos (23U)
27266 #define HRTIM_ADC1R_AD1TCPER_Msk (0x1UL << HRTIM_ADC1R_AD1TCPER_Pos) /*!< 0x00800000 */
27267 #define HRTIM_ADC1R_AD1TCPER HRTIM_ADC1R_AD1TCPER_Msk /*!< ADC Trigger 1 on Timer C period */
27268 #define HRTIM_ADC1R_AD1TDC2_Pos (24U)
27269 #define HRTIM_ADC1R_AD1TDC2_Msk (0x1UL << HRTIM_ADC1R_AD1TDC2_Pos) /*!< 0x01000000 */
27270 #define HRTIM_ADC1R_AD1TDC2 HRTIM_ADC1R_AD1TDC2_Msk /*!< ADC Trigger 1 on Timer D compare 2 */
27271 #define HRTIM_ADC1R_AD1TDC3_Pos (25U)
27272 #define HRTIM_ADC1R_AD1TDC3_Msk (0x1UL << HRTIM_ADC1R_AD1TDC3_Pos) /*!< 0x02000000 */
27273 #define HRTIM_ADC1R_AD1TDC3 HRTIM_ADC1R_AD1TDC3_Msk /*!< ADC Trigger 1 on Timer D compare 3 */
27274 #define HRTIM_ADC1R_AD1TDC4_Pos (26U)
27275 #define HRTIM_ADC1R_AD1TDC4_Msk (0x1UL << HRTIM_ADC1R_AD1TDC4_Pos) /*!< 0x04000000 */
27276 #define HRTIM_ADC1R_AD1TDC4 HRTIM_ADC1R_AD1TDC4_Msk /*!< ADC Trigger 1 on Timer D compare 4 */
27277 #define HRTIM_ADC1R_AD1TDPER_Pos (27U)
27278 #define HRTIM_ADC1R_AD1TDPER_Msk (0x1UL << HRTIM_ADC1R_AD1TDPER_Pos) /*!< 0x08000000 */
27279 #define HRTIM_ADC1R_AD1TDPER HRTIM_ADC1R_AD1TDPER_Msk /*!< ADC Trigger 1 on Timer D period */
27280 #define HRTIM_ADC1R_AD1TEC2_Pos (28U)
27281 #define HRTIM_ADC1R_AD1TEC2_Msk (0x1UL << HRTIM_ADC1R_AD1TEC2_Pos) /*!< 0x10000000 */
27282 #define HRTIM_ADC1R_AD1TEC2 HRTIM_ADC1R_AD1TEC2_Msk /*!< ADC Trigger 1 on Timer E compare 2 */
27283 #define HRTIM_ADC1R_AD1TEC3_Pos (29U)
27284 #define HRTIM_ADC1R_AD1TEC3_Msk (0x1UL << HRTIM_ADC1R_AD1TEC3_Pos) /*!< 0x20000000 */
27285 #define HRTIM_ADC1R_AD1TEC3 HRTIM_ADC1R_AD1TEC3_Msk /*!< ADC Trigger 1 on Timer E compare 3 */
27286 #define HRTIM_ADC1R_AD1TEC4_Pos (30U)
27287 #define HRTIM_ADC1R_AD1TEC4_Msk (0x1UL << HRTIM_ADC1R_AD1TEC4_Pos) /*!< 0x40000000 */
27288 #define HRTIM_ADC1R_AD1TEC4 HRTIM_ADC1R_AD1TEC4_Msk /*!< ADC Trigger 1 on Timer E compare 4 */
27289 #define HRTIM_ADC1R_AD1TEPER_Pos (31U)
27290 #define HRTIM_ADC1R_AD1TEPER_Msk (0x1UL << HRTIM_ADC1R_AD1TEPER_Pos) /*!< 0x80000000 */
27291 #define HRTIM_ADC1R_AD1TEPER HRTIM_ADC1R_AD1TEPER_Msk /*!< ADC Trigger 1 on Timer E period */
27292
27293 /******************* Bit definition for HRTIM_ADC2R register ****************/
27294 #define HRTIM_ADC2R_AD2MC1_Pos (0U)
27295 #define HRTIM_ADC2R_AD2MC1_Msk (0x1UL << HRTIM_ADC2R_AD2MC1_Pos) /*!< 0x00000001 */
27296 #define HRTIM_ADC2R_AD2MC1 HRTIM_ADC2R_AD2MC1_Msk /*!< ADC Trigger 2 on master compare 1 */
27297 #define HRTIM_ADC2R_AD2MC2_Pos (1U)
27298 #define HRTIM_ADC2R_AD2MC2_Msk (0x1UL << HRTIM_ADC2R_AD2MC2_Pos) /*!< 0x00000002 */
27299 #define HRTIM_ADC2R_AD2MC2 HRTIM_ADC2R_AD2MC2_Msk /*!< ADC Trigger 2 on master compare 2 */
27300 #define HRTIM_ADC2R_AD2MC3_Pos (2U)
27301 #define HRTIM_ADC2R_AD2MC3_Msk (0x1UL << HRTIM_ADC2R_AD2MC3_Pos) /*!< 0x00000004 */
27302 #define HRTIM_ADC2R_AD2MC3 HRTIM_ADC2R_AD2MC3_Msk /*!< ADC Trigger 2 on master compare 3 */
27303 #define HRTIM_ADC2R_AD2MC4_Pos (3U)
27304 #define HRTIM_ADC2R_AD2MC4_Msk (0x1UL << HRTIM_ADC2R_AD2MC4_Pos) /*!< 0x00000008 */
27305 #define HRTIM_ADC2R_AD2MC4 HRTIM_ADC2R_AD2MC4_Msk /*!< ADC Trigger 2 on master compare 4 */
27306 #define HRTIM_ADC2R_AD2MPER_Pos (4U)
27307 #define HRTIM_ADC2R_AD2MPER_Msk (0x1UL << HRTIM_ADC2R_AD2MPER_Pos) /*!< 0x00000010 */
27308 #define HRTIM_ADC2R_AD2MPER HRTIM_ADC2R_AD2MPER_Msk /*!< ADC Trigger 2 on master period */
27309 #define HRTIM_ADC2R_AD2EEV6_Pos (5U)
27310 #define HRTIM_ADC2R_AD2EEV6_Msk (0x1UL << HRTIM_ADC2R_AD2EEV6_Pos) /*!< 0x00000020 */
27311 #define HRTIM_ADC2R_AD2EEV6 HRTIM_ADC2R_AD2EEV6_Msk /*!< ADC Trigger 2 on external event 6 */
27312 #define HRTIM_ADC2R_AD2EEV7_Pos (6U)
27313 #define HRTIM_ADC2R_AD2EEV7_Msk (0x1UL << HRTIM_ADC2R_AD2EEV7_Pos) /*!< 0x00000040 */
27314 #define HRTIM_ADC2R_AD2EEV7 HRTIM_ADC2R_AD2EEV7_Msk /*!< ADC Trigger 2 on external event 7 */
27315 #define HRTIM_ADC2R_AD2EEV8_Pos (7U)
27316 #define HRTIM_ADC2R_AD2EEV8_Msk (0x1UL << HRTIM_ADC2R_AD2EEV8_Pos) /*!< 0x00000080 */
27317 #define HRTIM_ADC2R_AD2EEV8 HRTIM_ADC2R_AD2EEV8_Msk /*!< ADC Trigger 2 on external event 8 */
27318 #define HRTIM_ADC2R_AD2EEV9_Pos (8U)
27319 #define HRTIM_ADC2R_AD2EEV9_Msk (0x1UL << HRTIM_ADC2R_AD2EEV9_Pos) /*!< 0x00000100 */
27320 #define HRTIM_ADC2R_AD2EEV9 HRTIM_ADC2R_AD2EEV9_Msk /*!< ADC Trigger 2 on external event 9 */
27321 #define HRTIM_ADC2R_AD2EEV10_Pos (9U)
27322 #define HRTIM_ADC2R_AD2EEV10_Msk (0x1UL << HRTIM_ADC2R_AD2EEV10_Pos) /*!< 0x00000200 */
27323 #define HRTIM_ADC2R_AD2EEV10 HRTIM_ADC2R_AD2EEV10_Msk /*!< ADC Trigger 2 on external event 10 */
27324 #define HRTIM_ADC2R_AD2TAC2_Pos (10U)
27325 #define HRTIM_ADC2R_AD2TAC2_Msk (0x1UL << HRTIM_ADC2R_AD2TAC2_Pos) /*!< 0x00000400 */
27326 #define HRTIM_ADC2R_AD2TAC2 HRTIM_ADC2R_AD2TAC2_Msk /*!< ADC Trigger 2 on Timer A compare 2 */
27327 #define HRTIM_ADC2R_AD2TAC3_Pos (11U)
27328 #define HRTIM_ADC2R_AD2TAC3_Msk (0x1UL << HRTIM_ADC2R_AD2TAC3_Pos) /*!< 0x00000800 */
27329 #define HRTIM_ADC2R_AD2TAC3 HRTIM_ADC2R_AD2TAC3_Msk /*!< ADC Trigger 2 on Timer A compare 3 */
27330 #define HRTIM_ADC2R_AD2TAC4_Pos (12U)
27331 #define HRTIM_ADC2R_AD2TAC4_Msk (0x1UL << HRTIM_ADC2R_AD2TAC4_Pos) /*!< 0x00001000 */
27332 #define HRTIM_ADC2R_AD2TAC4 HRTIM_ADC2R_AD2TAC4_Msk /*!< ADC Trigger 2 on Timer A compare 4*/
27333 #define HRTIM_ADC2R_AD2TAPER_Pos (13U)
27334 #define HRTIM_ADC2R_AD2TAPER_Msk (0x1UL << HRTIM_ADC2R_AD2TAPER_Pos) /*!< 0x00002000 */
27335 #define HRTIM_ADC2R_AD2TAPER HRTIM_ADC2R_AD2TAPER_Msk /*!< ADC Trigger 2 on Timer A period */
27336 #define HRTIM_ADC2R_AD2TBC2_Pos (14U)
27337 #define HRTIM_ADC2R_AD2TBC2_Msk (0x1UL << HRTIM_ADC2R_AD2TBC2_Pos) /*!< 0x00004000 */
27338 #define HRTIM_ADC2R_AD2TBC2 HRTIM_ADC2R_AD2TBC2_Msk /*!< ADC Trigger 2 on Timer B compare 2 */
27339 #define HRTIM_ADC2R_AD2TBC3_Pos (15U)
27340 #define HRTIM_ADC2R_AD2TBC3_Msk (0x1UL << HRTIM_ADC2R_AD2TBC3_Pos) /*!< 0x00008000 */
27341 #define HRTIM_ADC2R_AD2TBC3 HRTIM_ADC2R_AD2TBC3_Msk /*!< ADC Trigger 2 on Timer B compare 3 */
27342 #define HRTIM_ADC2R_AD2TBC4_Pos (16U)
27343 #define HRTIM_ADC2R_AD2TBC4_Msk (0x1UL << HRTIM_ADC2R_AD2TBC4_Pos) /*!< 0x00010000 */
27344 #define HRTIM_ADC2R_AD2TBC4 HRTIM_ADC2R_AD2TBC4_Msk /*!< ADC Trigger 2 on Timer B compare 4 */
27345 #define HRTIM_ADC2R_AD2TBPER_Pos (17U)
27346 #define HRTIM_ADC2R_AD2TBPER_Msk (0x1UL << HRTIM_ADC2R_AD2TBPER_Pos) /*!< 0x00020000 */
27347 #define HRTIM_ADC2R_AD2TBPER HRTIM_ADC2R_AD2TBPER_Msk /*!< ADC Trigger 2 on Timer B period */
27348 #define HRTIM_ADC2R_AD2TCC2_Pos (18U)
27349 #define HRTIM_ADC2R_AD2TCC2_Msk (0x1UL << HRTIM_ADC2R_AD2TCC2_Pos) /*!< 0x00040000 */
27350 #define HRTIM_ADC2R_AD2TCC2 HRTIM_ADC2R_AD2TCC2_Msk /*!< ADC Trigger 2 on Timer C compare 2 */
27351 #define HRTIM_ADC2R_AD2TCC3_Pos (19U)
27352 #define HRTIM_ADC2R_AD2TCC3_Msk (0x1UL << HRTIM_ADC2R_AD2TCC3_Pos) /*!< 0x00080000 */
27353 #define HRTIM_ADC2R_AD2TCC3 HRTIM_ADC2R_AD2TCC3_Msk /*!< ADC Trigger 2 on Timer C compare 3 */
27354 #define HRTIM_ADC2R_AD2TCC4_Pos (20U)
27355 #define HRTIM_ADC2R_AD2TCC4_Msk (0x1UL << HRTIM_ADC2R_AD2TCC4_Pos) /*!< 0x00100000 */
27356 #define HRTIM_ADC2R_AD2TCC4 HRTIM_ADC2R_AD2TCC4_Msk /*!< ADC Trigger 2 on Timer C compare 4 */
27357 #define HRTIM_ADC2R_AD2TCPER_Pos (21U)
27358 #define HRTIM_ADC2R_AD2TCPER_Msk (0x1UL << HRTIM_ADC2R_AD2TCPER_Pos) /*!< 0x00200000 */
27359 #define HRTIM_ADC2R_AD2TCPER HRTIM_ADC2R_AD2TCPER_Msk /*!< ADC Trigger 2 on Timer C period */
27360 #define HRTIM_ADC2R_AD2TCRST_Pos (22U)
27361 #define HRTIM_ADC2R_AD2TCRST_Msk (0x1UL << HRTIM_ADC2R_AD2TCRST_Pos) /*!< 0x00400000 */
27362 #define HRTIM_ADC2R_AD2TCRST HRTIM_ADC2R_AD2TCRST_Msk /*!< ADC Trigger 2 on Timer C reset */
27363 #define HRTIM_ADC2R_AD2TDC2_Pos (23U)
27364 #define HRTIM_ADC2R_AD2TDC2_Msk (0x1UL << HRTIM_ADC2R_AD2TDC2_Pos) /*!< 0x00800000 */
27365 #define HRTIM_ADC2R_AD2TDC2 HRTIM_ADC2R_AD2TDC2_Msk /*!< ADC Trigger 2 on Timer D compare 2 */
27366 #define HRTIM_ADC2R_AD2TDC3_Pos (24U)
27367 #define HRTIM_ADC2R_AD2TDC3_Msk (0x1UL << HRTIM_ADC2R_AD2TDC3_Pos) /*!< 0x01000000 */
27368 #define HRTIM_ADC2R_AD2TDC3 HRTIM_ADC2R_AD2TDC3_Msk /*!< ADC Trigger 2 on Timer D compare 3 */
27369 #define HRTIM_ADC2R_AD2TDC4_Pos (25U)
27370 #define HRTIM_ADC2R_AD2TDC4_Msk (0x1UL << HRTIM_ADC2R_AD2TDC4_Pos) /*!< 0x02000000 */
27371 #define HRTIM_ADC2R_AD2TDC4 HRTIM_ADC2R_AD2TDC4_Msk /*!< ADC Trigger 2 on Timer D compare 4*/
27372 #define HRTIM_ADC2R_AD2TDPER_Pos (26U)
27373 #define HRTIM_ADC2R_AD2TDPER_Msk (0x1UL << HRTIM_ADC2R_AD2TDPER_Pos) /*!< 0x04000000 */
27374 #define HRTIM_ADC2R_AD2TDPER HRTIM_ADC2R_AD2TDPER_Msk /*!< ADC Trigger 2 on Timer D period */
27375 #define HRTIM_ADC2R_AD2TDRST_Pos (27U)
27376 #define HRTIM_ADC2R_AD2TDRST_Msk (0x1UL << HRTIM_ADC2R_AD2TDRST_Pos) /*!< 0x08000000 */
27377 #define HRTIM_ADC2R_AD2TDRST HRTIM_ADC2R_AD2TDRST_Msk /*!< ADC Trigger 2 on Timer D reset */
27378 #define HRTIM_ADC2R_AD2TEC2_Pos (28U)
27379 #define HRTIM_ADC2R_AD2TEC2_Msk (0x1UL << HRTIM_ADC2R_AD2TEC2_Pos) /*!< 0x10000000 */
27380 #define HRTIM_ADC2R_AD2TEC2 HRTIM_ADC2R_AD2TEC2_Msk /*!< ADC Trigger 2 on Timer E compare 2 */
27381 #define HRTIM_ADC2R_AD2TEC3_Pos (29U)
27382 #define HRTIM_ADC2R_AD2TEC3_Msk (0x1UL << HRTIM_ADC2R_AD2TEC3_Pos) /*!< 0x20000000 */
27383 #define HRTIM_ADC2R_AD2TEC3 HRTIM_ADC2R_AD2TEC3_Msk /*!< ADC Trigger 2 on Timer E compare 3 */
27384 #define HRTIM_ADC2R_AD2TEC4_Pos (30U)
27385 #define HRTIM_ADC2R_AD2TEC4_Msk (0x1UL << HRTIM_ADC2R_AD2TEC4_Pos) /*!< 0x40000000 */
27386 #define HRTIM_ADC2R_AD2TEC4 HRTIM_ADC2R_AD2TEC4_Msk /*!< ADC Trigger 2 on Timer E compare 4 */
27387 #define HRTIM_ADC2R_AD2TERST_Pos (31U)
27388 #define HRTIM_ADC2R_AD2TERST_Msk (0x1UL << HRTIM_ADC2R_AD2TERST_Pos) /*!< 0x80000000 */
27389 #define HRTIM_ADC2R_AD2TERST HRTIM_ADC2R_AD2TERST_Msk /*!< ADC Trigger 2 on Timer E reset */
27390
27391 /******************* Bit definition for HRTIM_ADC3R register ****************/
27392 #define HRTIM_ADC3R_AD3MC1_Pos (0U)
27393 #define HRTIM_ADC3R_AD3MC1_Msk (0x1UL << HRTIM_ADC3R_AD3MC1_Pos) /*!< 0x00000001 */
27394 #define HRTIM_ADC3R_AD3MC1 HRTIM_ADC3R_AD3MC1_Msk /*!< ADC Trigger 3 on master compare 1 */
27395 #define HRTIM_ADC3R_AD3MC2_Pos (1U)
27396 #define HRTIM_ADC3R_AD3MC2_Msk (0x1UL << HRTIM_ADC3R_AD3MC2_Pos) /*!< 0x00000002 */
27397 #define HRTIM_ADC3R_AD3MC2 HRTIM_ADC3R_AD3MC2_Msk /*!< ADC Trigger 3 on master compare 2 */
27398 #define HRTIM_ADC3R_AD3MC3_Pos (2U)
27399 #define HRTIM_ADC3R_AD3MC3_Msk (0x1UL << HRTIM_ADC3R_AD3MC3_Pos) /*!< 0x00000004 */
27400 #define HRTIM_ADC3R_AD3MC3 HRTIM_ADC3R_AD3MC3_Msk /*!< ADC Trigger 3 on master compare 3 */
27401 #define HRTIM_ADC3R_AD3MC4_Pos (3U)
27402 #define HRTIM_ADC3R_AD3MC4_Msk (0x1UL << HRTIM_ADC3R_AD3MC4_Pos) /*!< 0x00000008 */
27403 #define HRTIM_ADC3R_AD3MC4 HRTIM_ADC3R_AD3MC4_Msk /*!< ADC Trigger 3 on master compare 4 */
27404 #define HRTIM_ADC3R_AD3MPER_Pos (4U)
27405 #define HRTIM_ADC3R_AD3MPER_Msk (0x1UL << HRTIM_ADC3R_AD3MPER_Pos) /*!< 0x00000010 */
27406 #define HRTIM_ADC3R_AD3MPER HRTIM_ADC3R_AD3MPER_Msk /*!< ADC Trigger 3 on master period */
27407 #define HRTIM_ADC3R_AD3EEV1_Pos (5U)
27408 #define HRTIM_ADC3R_AD3EEV1_Msk (0x1UL << HRTIM_ADC3R_AD3EEV1_Pos) /*!< 0x00000020 */
27409 #define HRTIM_ADC3R_AD3EEV1 HRTIM_ADC3R_AD3EEV1_Msk /*!< ADC Trigger 3 on external event 1 */
27410 #define HRTIM_ADC3R_AD3EEV2_Pos (6U)
27411 #define HRTIM_ADC3R_AD3EEV2_Msk (0x1UL << HRTIM_ADC3R_AD3EEV2_Pos) /*!< 0x00000040 */
27412 #define HRTIM_ADC3R_AD3EEV2 HRTIM_ADC3R_AD3EEV2_Msk /*!< ADC Trigger 3 on external event 2 */
27413 #define HRTIM_ADC3R_AD3EEV3_Pos (7U)
27414 #define HRTIM_ADC3R_AD3EEV3_Msk (0x1UL << HRTIM_ADC3R_AD3EEV3_Pos) /*!< 0x00000080 */
27415 #define HRTIM_ADC3R_AD3EEV3 HRTIM_ADC3R_AD3EEV3_Msk /*!< ADC Trigger 3 on external event 3 */
27416 #define HRTIM_ADC3R_AD3EEV4_Pos (8U)
27417 #define HRTIM_ADC3R_AD3EEV4_Msk (0x1UL << HRTIM_ADC3R_AD3EEV4_Pos) /*!< 0x00000100 */
27418 #define HRTIM_ADC3R_AD3EEV4 HRTIM_ADC3R_AD3EEV4_Msk /*!< ADC Trigger 3 on external event 4 */
27419 #define HRTIM_ADC3R_AD3EEV5_Pos (9U)
27420 #define HRTIM_ADC3R_AD3EEV5_Msk (0x1UL << HRTIM_ADC3R_AD3EEV5_Pos) /*!< 0x00000200 */
27421 #define HRTIM_ADC3R_AD3EEV5 HRTIM_ADC3R_AD3EEV5_Msk /*!< ADC Trigger 3 on external event 5 */
27422 #define HRTIM_ADC3R_AD3TAC2_Pos (10U)
27423 #define HRTIM_ADC3R_AD3TAC2_Msk (0x1UL << HRTIM_ADC3R_AD3TAC2_Pos) /*!< 0x00000400 */
27424 #define HRTIM_ADC3R_AD3TAC2 HRTIM_ADC3R_AD3TAC2_Msk /*!< ADC Trigger 3 on Timer A compare 2 */
27425 #define HRTIM_ADC3R_AD3TAC3_Pos (11U)
27426 #define HRTIM_ADC3R_AD3TAC3_Msk (0x1UL << HRTIM_ADC3R_AD3TAC3_Pos) /*!< 0x00000800 */
27427 #define HRTIM_ADC3R_AD3TAC3 HRTIM_ADC3R_AD3TAC3_Msk /*!< ADC Trigger 3 on Timer A compare 3 */
27428 #define HRTIM_ADC3R_AD3TAC4_Pos (12U)
27429 #define HRTIM_ADC3R_AD3TAC4_Msk (0x1UL << HRTIM_ADC3R_AD3TAC4_Pos) /*!< 0x00001000 */
27430 #define HRTIM_ADC3R_AD3TAC4 HRTIM_ADC3R_AD3TAC4_Msk /*!< ADC Trigger 3 on Timer A compare 4 */
27431 #define HRTIM_ADC3R_AD3TAPER_Pos (13U)
27432 #define HRTIM_ADC3R_AD3TAPER_Msk (0x1UL << HRTIM_ADC3R_AD3TAPER_Pos) /*!< 0x00002000 */
27433 #define HRTIM_ADC3R_AD3TAPER HRTIM_ADC3R_AD3TAPER_Msk /*!< ADC Trigger 3 on Timer A period */
27434 #define HRTIM_ADC3R_AD3TARST_Pos (14U)
27435 #define HRTIM_ADC3R_AD3TARST_Msk (0x1UL << HRTIM_ADC3R_AD3TARST_Pos) /*!< 0x00004000 */
27436 #define HRTIM_ADC3R_AD3TARST HRTIM_ADC3R_AD3TARST_Msk /*!< ADC Trigger 3 on Timer A reset */
27437 #define HRTIM_ADC3R_AD3TBC2_Pos (15U)
27438 #define HRTIM_ADC3R_AD3TBC2_Msk (0x1UL << HRTIM_ADC3R_AD3TBC2_Pos) /*!< 0x00008000 */
27439 #define HRTIM_ADC3R_AD3TBC2 HRTIM_ADC3R_AD3TBC2_Msk /*!< ADC Trigger 3 on Timer B compare 2 */
27440 #define HRTIM_ADC3R_AD3TBC3_Pos (16U)
27441 #define HRTIM_ADC3R_AD3TBC3_Msk (0x1UL << HRTIM_ADC3R_AD3TBC3_Pos) /*!< 0x00010000 */
27442 #define HRTIM_ADC3R_AD3TBC3 HRTIM_ADC3R_AD3TBC3_Msk /*!< ADC Trigger 3 on Timer B compare 3 */
27443 #define HRTIM_ADC3R_AD3TBC4_Pos (17U)
27444 #define HRTIM_ADC3R_AD3TBC4_Msk (0x1UL << HRTIM_ADC3R_AD3TBC4_Pos) /*!< 0x00020000 */
27445 #define HRTIM_ADC3R_AD3TBC4 HRTIM_ADC3R_AD3TBC4_Msk /*!< ADC Trigger 3 on Timer B compare 4 */
27446 #define HRTIM_ADC3R_AD3TBPER_Pos (18U)
27447 #define HRTIM_ADC3R_AD3TBPER_Msk (0x1UL << HRTIM_ADC3R_AD3TBPER_Pos) /*!< 0x00040000 */
27448 #define HRTIM_ADC3R_AD3TBPER HRTIM_ADC3R_AD3TBPER_Msk /*!< ADC Trigger 3 on Timer B period */
27449 #define HRTIM_ADC3R_AD3TBRST_Pos (19U)
27450 #define HRTIM_ADC3R_AD3TBRST_Msk (0x1UL << HRTIM_ADC3R_AD3TBRST_Pos) /*!< 0x00080000 */
27451 #define HRTIM_ADC3R_AD3TBRST HRTIM_ADC3R_AD3TBRST_Msk /*!< ADC Trigger 3 on Timer B reset */
27452 #define HRTIM_ADC3R_AD3TCC2_Pos (20U)
27453 #define HRTIM_ADC3R_AD3TCC2_Msk (0x1UL << HRTIM_ADC3R_AD3TCC2_Pos) /*!< 0x00100000 */
27454 #define HRTIM_ADC3R_AD3TCC2 HRTIM_ADC3R_AD3TCC2_Msk /*!< ADC Trigger 3 on Timer C compare 2 */
27455 #define HRTIM_ADC3R_AD3TCC3_Pos (21U)
27456 #define HRTIM_ADC3R_AD3TCC3_Msk (0x1UL << HRTIM_ADC3R_AD3TCC3_Pos) /*!< 0x00200000 */
27457 #define HRTIM_ADC3R_AD3TCC3 HRTIM_ADC3R_AD3TCC3_Msk /*!< ADC Trigger 3 on Timer C compare 3 */
27458 #define HRTIM_ADC3R_AD3TCC4_Pos (22U)
27459 #define HRTIM_ADC3R_AD3TCC4_Msk (0x1UL << HRTIM_ADC3R_AD3TCC4_Pos) /*!< 0x00400000 */
27460 #define HRTIM_ADC3R_AD3TCC4 HRTIM_ADC3R_AD3TCC4_Msk /*!< ADC Trigger 3 on Timer C compare 4 */
27461 #define HRTIM_ADC3R_AD3TCPER_Pos (23U)
27462 #define HRTIM_ADC3R_AD3TCPER_Msk (0x1UL << HRTIM_ADC3R_AD3TCPER_Pos) /*!< 0x00800000 */
27463 #define HRTIM_ADC3R_AD3TCPER HRTIM_ADC3R_AD3TCPER_Msk /*!< ADC Trigger 3 on Timer C period */
27464 #define HRTIM_ADC3R_AD3TDC2_Pos (24U)
27465 #define HRTIM_ADC3R_AD3TDC2_Msk (0x1UL << HRTIM_ADC3R_AD3TDC2_Pos) /*!< 0x01000000 */
27466 #define HRTIM_ADC3R_AD3TDC2 HRTIM_ADC3R_AD3TDC2_Msk /*!< ADC Trigger 3 on Timer D compare 2 */
27467 #define HRTIM_ADC3R_AD3TDC3_Pos (25U)
27468 #define HRTIM_ADC3R_AD3TDC3_Msk (0x1UL << HRTIM_ADC3R_AD3TDC3_Pos) /*!< 0x02000000 */
27469 #define HRTIM_ADC3R_AD3TDC3 HRTIM_ADC3R_AD3TDC3_Msk /*!< ADC Trigger 3 on Timer D compare 3 */
27470 #define HRTIM_ADC3R_AD3TDC4_Pos (26U)
27471 #define HRTIM_ADC3R_AD3TDC4_Msk (0x1UL << HRTIM_ADC3R_AD3TDC4_Pos) /*!< 0x04000000 */
27472 #define HRTIM_ADC3R_AD3TDC4 HRTIM_ADC3R_AD3TDC4_Msk /*!< ADC Trigger 3 on Timer D compare 4 */
27473 #define HRTIM_ADC3R_AD3TDPER_Pos (27U)
27474 #define HRTIM_ADC3R_AD3TDPER_Msk (0x1UL << HRTIM_ADC3R_AD3TDPER_Pos) /*!< 0x08000000 */
27475 #define HRTIM_ADC3R_AD3TDPER HRTIM_ADC3R_AD3TDPER_Msk /*!< ADC Trigger 3 on Timer D period */
27476 #define HRTIM_ADC3R_AD3TEC2_Pos (28U)
27477 #define HRTIM_ADC3R_AD3TEC2_Msk (0x1UL << HRTIM_ADC3R_AD3TEC2_Pos) /*!< 0x10000000 */
27478 #define HRTIM_ADC3R_AD3TEC2 HRTIM_ADC3R_AD3TEC2_Msk /*!< ADC Trigger 3 on Timer E compare 2 */
27479 #define HRTIM_ADC3R_AD3TEC3_Pos (29U)
27480 #define HRTIM_ADC3R_AD3TEC3_Msk (0x1UL << HRTIM_ADC3R_AD3TEC3_Pos) /*!< 0x20000000 */
27481 #define HRTIM_ADC3R_AD3TEC3 HRTIM_ADC3R_AD3TEC3_Msk /*!< ADC Trigger 3 on Timer E compare 3 */
27482 #define HRTIM_ADC3R_AD3TEC4_Pos (30U)
27483 #define HRTIM_ADC3R_AD3TEC4_Msk (0x1UL << HRTIM_ADC3R_AD3TEC4_Pos) /*!< 0x40000000 */
27484 #define HRTIM_ADC3R_AD3TEC4 HRTIM_ADC3R_AD3TEC4_Msk /*!< ADC Trigger 3 on Timer E compare 4 */
27485 #define HRTIM_ADC3R_AD3TEPER_Pos (31U)
27486 #define HRTIM_ADC3R_AD3TEPER_Msk (0x1UL << HRTIM_ADC3R_AD3TEPER_Pos) /*!< 0x80000000 */
27487 #define HRTIM_ADC3R_AD3TEPER HRTIM_ADC3R_AD3TEPER_Msk /*!< ADC Trigger 3 on Timer E period */
27488
27489 /******************* Bit definition for HRTIM_ADC4R register ****************/
27490 #define HRTIM_ADC4R_AD4MC1_Pos (0U)
27491 #define HRTIM_ADC4R_AD4MC1_Msk (0x1UL << HRTIM_ADC4R_AD4MC1_Pos) /*!< 0x00000001 */
27492 #define HRTIM_ADC4R_AD4MC1 HRTIM_ADC4R_AD4MC1_Msk /*!< ADC Trigger 4 on master compare 1 */
27493 #define HRTIM_ADC4R_AD4MC2_Pos (1U)
27494 #define HRTIM_ADC4R_AD4MC2_Msk (0x1UL << HRTIM_ADC4R_AD4MC2_Pos) /*!< 0x00000002 */
27495 #define HRTIM_ADC4R_AD4MC2 HRTIM_ADC4R_AD4MC2_Msk /*!< ADC Trigger 4 on master compare 2 */
27496 #define HRTIM_ADC4R_AD4MC3_Pos (2U)
27497 #define HRTIM_ADC4R_AD4MC3_Msk (0x1UL << HRTIM_ADC4R_AD4MC3_Pos) /*!< 0x00000004 */
27498 #define HRTIM_ADC4R_AD4MC3 HRTIM_ADC4R_AD4MC3_Msk /*!< ADC Trigger 4 on master compare 3 */
27499 #define HRTIM_ADC4R_AD4MC4_Pos (3U)
27500 #define HRTIM_ADC4R_AD4MC4_Msk (0x1UL << HRTIM_ADC4R_AD4MC4_Pos) /*!< 0x00000008 */
27501 #define HRTIM_ADC4R_AD4MC4 HRTIM_ADC4R_AD4MC4_Msk /*!< ADC Trigger 4 on master compare 4 */
27502 #define HRTIM_ADC4R_AD4MPER_Pos (4U)
27503 #define HRTIM_ADC4R_AD4MPER_Msk (0x1UL << HRTIM_ADC4R_AD4MPER_Pos) /*!< 0x00000010 */
27504 #define HRTIM_ADC4R_AD4MPER HRTIM_ADC4R_AD4MPER_Msk /*!< ADC Trigger 4 on master period */
27505 #define HRTIM_ADC4R_AD4EEV6_Pos (5U)
27506 #define HRTIM_ADC4R_AD4EEV6_Msk (0x1UL << HRTIM_ADC4R_AD4EEV6_Pos) /*!< 0x00000020 */
27507 #define HRTIM_ADC4R_AD4EEV6 HRTIM_ADC4R_AD4EEV6_Msk /*!< ADC Trigger 4 on external event 6 */
27508 #define HRTIM_ADC4R_AD4EEV7_Pos (6U)
27509 #define HRTIM_ADC4R_AD4EEV7_Msk (0x1UL << HRTIM_ADC4R_AD4EEV7_Pos) /*!< 0x00000040 */
27510 #define HRTIM_ADC4R_AD4EEV7 HRTIM_ADC4R_AD4EEV7_Msk /*!< ADC Trigger 4 on external event 7 */
27511 #define HRTIM_ADC4R_AD4EEV8_Pos (7U)
27512 #define HRTIM_ADC4R_AD4EEV8_Msk (0x1UL << HRTIM_ADC4R_AD4EEV8_Pos) /*!< 0x00000080 */
27513 #define HRTIM_ADC4R_AD4EEV8 HRTIM_ADC4R_AD4EEV8_Msk /*!< ADC Trigger 4 on external event 8 */
27514 #define HRTIM_ADC4R_AD4EEV9_Pos (8U)
27515 #define HRTIM_ADC4R_AD4EEV9_Msk (0x1UL << HRTIM_ADC4R_AD4EEV9_Pos) /*!< 0x00000100 */
27516 #define HRTIM_ADC4R_AD4EEV9 HRTIM_ADC4R_AD4EEV9_Msk /*!< ADC Trigger 4 on external event 9 */
27517 #define HRTIM_ADC4R_AD4EEV10_Pos (9U)
27518 #define HRTIM_ADC4R_AD4EEV10_Msk (0x1UL << HRTIM_ADC4R_AD4EEV10_Pos) /*!< 0x00000200 */
27519 #define HRTIM_ADC4R_AD4EEV10 HRTIM_ADC4R_AD4EEV10_Msk /*!< ADC Trigger 4 on external event 10 */
27520 #define HRTIM_ADC4R_AD4TAC2_Pos (10U)
27521 #define HRTIM_ADC4R_AD4TAC2_Msk (0x1UL << HRTIM_ADC4R_AD4TAC2_Pos) /*!< 0x00000400 */
27522 #define HRTIM_ADC4R_AD4TAC2 HRTIM_ADC4R_AD4TAC2_Msk /*!< ADC Trigger 4 on Timer A compare 2 */
27523 #define HRTIM_ADC4R_AD4TAC3_Pos (11U)
27524 #define HRTIM_ADC4R_AD4TAC3_Msk (0x1UL << HRTIM_ADC4R_AD4TAC3_Pos) /*!< 0x00000800 */
27525 #define HRTIM_ADC4R_AD4TAC3 HRTIM_ADC4R_AD4TAC3_Msk /*!< ADC Trigger 4 on Timer A compare 3 */
27526 #define HRTIM_ADC4R_AD4TAC4_Pos (12U)
27527 #define HRTIM_ADC4R_AD4TAC4_Msk (0x1UL << HRTIM_ADC4R_AD4TAC4_Pos) /*!< 0x00001000 */
27528 #define HRTIM_ADC4R_AD4TAC4 HRTIM_ADC4R_AD4TAC4_Msk /*!< ADC Trigger 4 on Timer A compare 4*/
27529 #define HRTIM_ADC4R_AD4TAPER_Pos (13U)
27530 #define HRTIM_ADC4R_AD4TAPER_Msk (0x1UL << HRTIM_ADC4R_AD4TAPER_Pos) /*!< 0x00002000 */
27531 #define HRTIM_ADC4R_AD4TAPER HRTIM_ADC4R_AD4TAPER_Msk /*!< ADC Trigger 4 on Timer A period */
27532 #define HRTIM_ADC4R_AD4TBC2_Pos (14U)
27533 #define HRTIM_ADC4R_AD4TBC2_Msk (0x1UL << HRTIM_ADC4R_AD4TBC2_Pos) /*!< 0x00004000 */
27534 #define HRTIM_ADC4R_AD4TBC2 HRTIM_ADC4R_AD4TBC2_Msk /*!< ADC Trigger 4 on Timer B compare 2 */
27535 #define HRTIM_ADC4R_AD4TBC3_Pos (15U)
27536 #define HRTIM_ADC4R_AD4TBC3_Msk (0x1UL << HRTIM_ADC4R_AD4TBC3_Pos) /*!< 0x00008000 */
27537 #define HRTIM_ADC4R_AD4TBC3 HRTIM_ADC4R_AD4TBC3_Msk /*!< ADC Trigger 4 on Timer B compare 3 */
27538 #define HRTIM_ADC4R_AD4TBC4_Pos (16U)
27539 #define HRTIM_ADC4R_AD4TBC4_Msk (0x1UL << HRTIM_ADC4R_AD4TBC4_Pos) /*!< 0x00010000 */
27540 #define HRTIM_ADC4R_AD4TBC4 HRTIM_ADC4R_AD4TBC4_Msk /*!< ADC Trigger 4 on Timer B compare 4 */
27541 #define HRTIM_ADC4R_AD4TBPER_Pos (17U)
27542 #define HRTIM_ADC4R_AD4TBPER_Msk (0x1UL << HRTIM_ADC4R_AD4TBPER_Pos) /*!< 0x00020000 */
27543 #define HRTIM_ADC4R_AD4TBPER HRTIM_ADC4R_AD4TBPER_Msk /*!< ADC Trigger 4 on Timer B period */
27544 #define HRTIM_ADC4R_AD4TCC2_Pos (18U)
27545 #define HRTIM_ADC4R_AD4TCC2_Msk (0x1UL << HRTIM_ADC4R_AD4TCC2_Pos) /*!< 0x00040000 */
27546 #define HRTIM_ADC4R_AD4TCC2 HRTIM_ADC4R_AD4TCC2_Msk /*!< ADC Trigger 4 on Timer C compare 2 */
27547 #define HRTIM_ADC4R_AD4TCC3_Pos (19U)
27548 #define HRTIM_ADC4R_AD4TCC3_Msk (0x1UL << HRTIM_ADC4R_AD4TCC3_Pos) /*!< 0x00080000 */
27549 #define HRTIM_ADC4R_AD4TCC3 HRTIM_ADC4R_AD4TCC3_Msk /*!< ADC Trigger 4 on Timer C compare 3 */
27550 #define HRTIM_ADC4R_AD4TCC4_Pos (20U)
27551 #define HRTIM_ADC4R_AD4TCC4_Msk (0x1UL << HRTIM_ADC4R_AD4TCC4_Pos) /*!< 0x00100000 */
27552 #define HRTIM_ADC4R_AD4TCC4 HRTIM_ADC4R_AD4TCC4_Msk /*!< ADC Trigger 4 on Timer C compare 4 */
27553 #define HRTIM_ADC4R_AD4TCPER_Pos (21U)
27554 #define HRTIM_ADC4R_AD4TCPER_Msk (0x1UL << HRTIM_ADC4R_AD4TCPER_Pos) /*!< 0x00200000 */
27555 #define HRTIM_ADC4R_AD4TCPER HRTIM_ADC4R_AD4TCPER_Msk /*!< ADC Trigger 4 on Timer C period */
27556 #define HRTIM_ADC4R_AD4TCRST_Pos (22U)
27557 #define HRTIM_ADC4R_AD4TCRST_Msk (0x1UL << HRTIM_ADC4R_AD4TCRST_Pos) /*!< 0x00400000 */
27558 #define HRTIM_ADC4R_AD4TCRST HRTIM_ADC4R_AD4TCRST_Msk /*!< ADC Trigger 4 on Timer C reset */
27559 #define HRTIM_ADC4R_AD4TDC2_Pos (23U)
27560 #define HRTIM_ADC4R_AD4TDC2_Msk (0x1UL << HRTIM_ADC4R_AD4TDC2_Pos) /*!< 0x00800000 */
27561 #define HRTIM_ADC4R_AD4TDC2 HRTIM_ADC4R_AD4TDC2_Msk /*!< ADC Trigger 4 on Timer D compare 2 */
27562 #define HRTIM_ADC4R_AD4TDC3_Pos (24U)
27563 #define HRTIM_ADC4R_AD4TDC3_Msk (0x1UL << HRTIM_ADC4R_AD4TDC3_Pos) /*!< 0x01000000 */
27564 #define HRTIM_ADC4R_AD4TDC3 HRTIM_ADC4R_AD4TDC3_Msk /*!< ADC Trigger 4 on Timer D compare 3 */
27565 #define HRTIM_ADC4R_AD4TDC4_Pos (25U)
27566 #define HRTIM_ADC4R_AD4TDC4_Msk (0x1UL << HRTIM_ADC4R_AD4TDC4_Pos) /*!< 0x02000000 */
27567 #define HRTIM_ADC4R_AD4TDC4 HRTIM_ADC4R_AD4TDC4_Msk /*!< ADC Trigger 4 on Timer D compare 4*/
27568 #define HRTIM_ADC4R_AD4TDPER_Pos (26U)
27569 #define HRTIM_ADC4R_AD4TDPER_Msk (0x1UL << HRTIM_ADC4R_AD4TDPER_Pos) /*!< 0x04000000 */
27570 #define HRTIM_ADC4R_AD4TDPER HRTIM_ADC4R_AD4TDPER_Msk /*!< ADC Trigger 4 on Timer D period */
27571 #define HRTIM_ADC4R_AD4TDRST_Pos (27U)
27572 #define HRTIM_ADC4R_AD4TDRST_Msk (0x1UL << HRTIM_ADC4R_AD4TDRST_Pos) /*!< 0x08000000 */
27573 #define HRTIM_ADC4R_AD4TDRST HRTIM_ADC4R_AD4TDRST_Msk /*!< ADC Trigger 4 on Timer D reset */
27574 #define HRTIM_ADC4R_AD4TEC2_Pos (28U)
27575 #define HRTIM_ADC4R_AD4TEC2_Msk (0x1UL << HRTIM_ADC4R_AD4TEC2_Pos) /*!< 0x10000000 */
27576 #define HRTIM_ADC4R_AD4TEC2 HRTIM_ADC4R_AD4TEC2_Msk /*!< ADC Trigger 4 on Timer E compare 2 */
27577 #define HRTIM_ADC4R_AD4TEC3_Pos (29U)
27578 #define HRTIM_ADC4R_AD4TEC3_Msk (0x1UL << HRTIM_ADC4R_AD4TEC3_Pos) /*!< 0x20000000 */
27579 #define HRTIM_ADC4R_AD4TEC3 HRTIM_ADC4R_AD4TEC3_Msk /*!< ADC Trigger 4 on Timer E compare 3 */
27580 #define HRTIM_ADC4R_AD4TEC4_Pos (30U)
27581 #define HRTIM_ADC4R_AD4TEC4_Msk (0x1UL << HRTIM_ADC4R_AD4TEC4_Pos) /*!< 0x40000000 */
27582 #define HRTIM_ADC4R_AD4TEC4 HRTIM_ADC4R_AD4TEC4_Msk /*!< ADC Trigger 4 on Timer E compare 4 */
27583 #define HRTIM_ADC4R_AD4TERST_Pos (31U)
27584 #define HRTIM_ADC4R_AD4TERST_Msk (0x1UL << HRTIM_ADC4R_AD4TERST_Pos) /*!< 0x80000000 */
27585 #define HRTIM_ADC4R_AD4TERST HRTIM_ADC4R_AD4TERST_Msk /*!< ADC Trigger 4 on Timer E reset */
27586
27587 /******************* Bit definition for HRTIM_FLTINR1 register ***************/
27588 #define HRTIM_FLTINR1_FLT1E_Pos (0U)
27589 #define HRTIM_FLTINR1_FLT1E_Msk (0x1UL << HRTIM_FLTINR1_FLT1E_Pos) /*!< 0x00000001 */
27590 #define HRTIM_FLTINR1_FLT1E HRTIM_FLTINR1_FLT1E_Msk /*!< Fault 1 enable */
27591 #define HRTIM_FLTINR1_FLT1P_Pos (1U)
27592 #define HRTIM_FLTINR1_FLT1P_Msk (0x1UL << HRTIM_FLTINR1_FLT1P_Pos) /*!< 0x00000002 */
27593 #define HRTIM_FLTINR1_FLT1P HRTIM_FLTINR1_FLT1P_Msk /*!< Fault 1 polarity */
27594 #define HRTIM_FLTINR1_FLT1SRC_Pos (2U)
27595 #define HRTIM_FLTINR1_FLT1SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT1SRC_Pos) /*!< 0x00000004 */
27596 #define HRTIM_FLTINR1_FLT1SRC HRTIM_FLTINR1_FLT1SRC_Msk /*!< Fault 1 source */
27597 #define HRTIM_FLTINR1_FLT1F_Pos (3U)
27598 #define HRTIM_FLTINR1_FLT1F_Msk (0xFUL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000078 */
27599 #define HRTIM_FLTINR1_FLT1F HRTIM_FLTINR1_FLT1F_Msk /*!< Fault 1 filter */
27600 #define HRTIM_FLTINR1_FLT1F_0 (0x1UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000008 */
27601 #define HRTIM_FLTINR1_FLT1F_1 (0x2UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000010 */
27602 #define HRTIM_FLTINR1_FLT1F_2 (0x4UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000020 */
27603 #define HRTIM_FLTINR1_FLT1F_3 (0x8UL << HRTIM_FLTINR1_FLT1F_Pos) /*!< 0x00000040 */
27604 #define HRTIM_FLTINR1_FLT1LCK_Pos (7U)
27605 #define HRTIM_FLTINR1_FLT1LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT1LCK_Pos) /*!< 0x00000080 */
27606 #define HRTIM_FLTINR1_FLT1LCK HRTIM_FLTINR1_FLT1LCK_Msk /*!< Fault 1 lock */
27607
27608 #define HRTIM_FLTINR1_FLT2E_Pos (8U)
27609 #define HRTIM_FLTINR1_FLT2E_Msk (0x1UL << HRTIM_FLTINR1_FLT2E_Pos) /*!< 0x00000100 */
27610 #define HRTIM_FLTINR1_FLT2E HRTIM_FLTINR1_FLT2E_Msk /*!< Fault 2 enable */
27611 #define HRTIM_FLTINR1_FLT2P_Pos (9U)
27612 #define HRTIM_FLTINR1_FLT2P_Msk (0x1UL << HRTIM_FLTINR1_FLT2P_Pos) /*!< 0x00000200 */
27613 #define HRTIM_FLTINR1_FLT2P HRTIM_FLTINR1_FLT2P_Msk /*!< Fault 2 polarity */
27614 #define HRTIM_FLTINR1_FLT2SRC_Pos (10U)
27615 #define HRTIM_FLTINR1_FLT2SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT2SRC_Pos) /*!< 0x00000400 */
27616 #define HRTIM_FLTINR1_FLT2SRC HRTIM_FLTINR1_FLT2SRC_Msk /*!< Fault 2 source */
27617 #define HRTIM_FLTINR1_FLT2F_Pos (11U)
27618 #define HRTIM_FLTINR1_FLT2F_Msk (0xFUL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00007800 */
27619 #define HRTIM_FLTINR1_FLT2F HRTIM_FLTINR1_FLT2F_Msk /*!< Fault 2 filter */
27620 #define HRTIM_FLTINR1_FLT2F_0 (0x1UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00000800 */
27621 #define HRTIM_FLTINR1_FLT2F_1 (0x2UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00001000 */
27622 #define HRTIM_FLTINR1_FLT2F_2 (0x4UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00002000 */
27623 #define HRTIM_FLTINR1_FLT2F_3 (0x8UL << HRTIM_FLTINR1_FLT2F_Pos) /*!< 0x00004000 */
27624 #define HRTIM_FLTINR1_FLT2LCK_Pos (15U)
27625 #define HRTIM_FLTINR1_FLT2LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT2LCK_Pos) /*!< 0x00008000 */
27626 #define HRTIM_FLTINR1_FLT2LCK HRTIM_FLTINR1_FLT2LCK_Msk /*!< Fault 2 lock */
27627
27628 #define HRTIM_FLTINR1_FLT3E_Pos (16U)
27629 #define HRTIM_FLTINR1_FLT3E_Msk (0x1UL << HRTIM_FLTINR1_FLT3E_Pos) /*!< 0x00010000 */
27630 #define HRTIM_FLTINR1_FLT3E HRTIM_FLTINR1_FLT3E_Msk /*!< Fault 3 enable */
27631 #define HRTIM_FLTINR1_FLT3P_Pos (17U)
27632 #define HRTIM_FLTINR1_FLT3P_Msk (0x1UL << HRTIM_FLTINR1_FLT3P_Pos) /*!< 0x00020000 */
27633 #define HRTIM_FLTINR1_FLT3P HRTIM_FLTINR1_FLT3P_Msk /*!< Fault 3 polarity */
27634 #define HRTIM_FLTINR1_FLT3SRC_Pos (18U)
27635 #define HRTIM_FLTINR1_FLT3SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT3SRC_Pos) /*!< 0x00040000 */
27636 #define HRTIM_FLTINR1_FLT3SRC HRTIM_FLTINR1_FLT3SRC_Msk /*!< Fault 3 source */
27637 #define HRTIM_FLTINR1_FLT3F_Pos (19U)
27638 #define HRTIM_FLTINR1_FLT3F_Msk (0xFUL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00780000 */
27639 #define HRTIM_FLTINR1_FLT3F HRTIM_FLTINR1_FLT3F_Msk /*!< Fault 3 filter */
27640 #define HRTIM_FLTINR1_FLT3F_0 (0x1UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00080000 */
27641 #define HRTIM_FLTINR1_FLT3F_1 (0x2UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00100000 */
27642 #define HRTIM_FLTINR1_FLT3F_2 (0x4UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00200000 */
27643 #define HRTIM_FLTINR1_FLT3F_3 (0x8UL << HRTIM_FLTINR1_FLT3F_Pos) /*!< 0x00400000 */
27644 #define HRTIM_FLTINR1_FLT3LCK_Pos (23U)
27645 #define HRTIM_FLTINR1_FLT3LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT3LCK_Pos) /*!< 0x00800000 */
27646 #define HRTIM_FLTINR1_FLT3LCK HRTIM_FLTINR1_FLT3LCK_Msk /*!< Fault 3 lock */
27647
27648 #define HRTIM_FLTINR1_FLT4E_Pos (24U)
27649 #define HRTIM_FLTINR1_FLT4E_Msk (0x1UL << HRTIM_FLTINR1_FLT4E_Pos) /*!< 0x01000000 */
27650 #define HRTIM_FLTINR1_FLT4E HRTIM_FLTINR1_FLT4E_Msk /*!< Fault 4 enable */
27651 #define HRTIM_FLTINR1_FLT4P_Pos (25U)
27652 #define HRTIM_FLTINR1_FLT4P_Msk (0x1UL << HRTIM_FLTINR1_FLT4P_Pos) /*!< 0x02000000 */
27653 #define HRTIM_FLTINR1_FLT4P HRTIM_FLTINR1_FLT4P_Msk /*!< Fault 4 polarity */
27654 #define HRTIM_FLTINR1_FLT4SRC_Pos (26U)
27655 #define HRTIM_FLTINR1_FLT4SRC_Msk (0x1UL << HRTIM_FLTINR1_FLT4SRC_Pos) /*!< 0x04000000 */
27656 #define HRTIM_FLTINR1_FLT4SRC HRTIM_FLTINR1_FLT4SRC_Msk /*!< Fault 4 source */
27657 #define HRTIM_FLTINR1_FLT4F_Pos (27U)
27658 #define HRTIM_FLTINR1_FLT4F_Msk (0xFUL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x78000000 */
27659 #define HRTIM_FLTINR1_FLT4F HRTIM_FLTINR1_FLT4F_Msk /*!< Fault 4 filter */
27660 #define HRTIM_FLTINR1_FLT4F_0 (0x1UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x08000000 */
27661 #define HRTIM_FLTINR1_FLT4F_1 (0x2UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x10000000 */
27662 #define HRTIM_FLTINR1_FLT4F_2 (0x4UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x20000000 */
27663 #define HRTIM_FLTINR1_FLT4F_3 (0x8UL << HRTIM_FLTINR1_FLT4F_Pos) /*!< 0x40000000 */
27664 #define HRTIM_FLTINR1_FLT4LCK_Pos (31U)
27665 #define HRTIM_FLTINR1_FLT4LCK_Msk (0x1UL << HRTIM_FLTINR1_FLT4LCK_Pos) /*!< 0x80000000 */
27666 #define HRTIM_FLTINR1_FLT4LCK HRTIM_FLTINR1_FLT4LCK_Msk /*!< Fault 4 lock */
27667
27668 /******************* Bit definition for HRTIM_FLTINR2 register ***************/
27669 #define HRTIM_FLTINR2_FLT5E_Pos (0U)
27670 #define HRTIM_FLTINR2_FLT5E_Msk (0x1UL << HRTIM_FLTINR2_FLT5E_Pos) /*!< 0x00000001 */
27671 #define HRTIM_FLTINR2_FLT5E HRTIM_FLTINR2_FLT5E_Msk /*!< Fault 5 enable */
27672 #define HRTIM_FLTINR2_FLT5P_Pos (1U)
27673 #define HRTIM_FLTINR2_FLT5P_Msk (0x1UL << HRTIM_FLTINR2_FLT5P_Pos) /*!< 0x00000002 */
27674 #define HRTIM_FLTINR2_FLT5P HRTIM_FLTINR2_FLT5P_Msk /*!< Fault 5 polarity */
27675 #define HRTIM_FLTINR2_FLT5SRC_Pos (2U)
27676 #define HRTIM_FLTINR2_FLT5SRC_Msk (0x1UL << HRTIM_FLTINR2_FLT5SRC_Pos) /*!< 0x00000004 */
27677 #define HRTIM_FLTINR2_FLT5SRC HRTIM_FLTINR2_FLT5SRC_Msk /*!< Fault 5 source */
27678 #define HRTIM_FLTINR2_FLT5F_Pos (3U)
27679 #define HRTIM_FLTINR2_FLT5F_Msk (0xFUL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000078 */
27680 #define HRTIM_FLTINR2_FLT5F HRTIM_FLTINR2_FLT5F_Msk /*!< Fault 5 filter */
27681 #define HRTIM_FLTINR2_FLT5F_0 (0x1UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000008 */
27682 #define HRTIM_FLTINR2_FLT5F_1 (0x2UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000010 */
27683 #define HRTIM_FLTINR2_FLT5F_2 (0x4UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000020 */
27684 #define HRTIM_FLTINR2_FLT5F_3 (0x8UL << HRTIM_FLTINR2_FLT5F_Pos) /*!< 0x00000040 */
27685 #define HRTIM_FLTINR2_FLT5LCK_Pos (7U)
27686 #define HRTIM_FLTINR2_FLT5LCK_Msk (0x1UL << HRTIM_FLTINR2_FLT5LCK_Pos) /*!< 0x00000080 */
27687 #define HRTIM_FLTINR2_FLT5LCK HRTIM_FLTINR2_FLT5LCK_Msk /*!< Fault 5 lock */
27688 #define HRTIM_FLTINR2_FLTSD_Pos (24U)
27689 #define HRTIM_FLTINR2_FLTSD_Msk (0x3UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x03000000 */
27690 #define HRTIM_FLTINR2_FLTSD HRTIM_FLTINR2_FLTSD_Msk /*!< Fault sampling clock division */
27691 #define HRTIM_FLTINR2_FLTSD_0 (0x1UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x01000000 */
27692 #define HRTIM_FLTINR2_FLTSD_1 (0x2UL << HRTIM_FLTINR2_FLTSD_Pos) /*!< 0x02000000 */
27693
27694 /******************* Bit definition for HRTIM_BDMUPR register ***************/
27695 #define HRTIM_BDMUPR_MCR_Pos (0U)
27696 #define HRTIM_BDMUPR_MCR_Msk (0x1UL << HRTIM_BDMUPR_MCR_Pos) /*!< 0x00000001 */
27697 #define HRTIM_BDMUPR_MCR HRTIM_BDMUPR_MCR_Msk /*!< MCR register update enable */
27698 #define HRTIM_BDMUPR_MICR_Pos (1U)
27699 #define HRTIM_BDMUPR_MICR_Msk (0x1UL << HRTIM_BDMUPR_MICR_Pos) /*!< 0x00000002 */
27700 #define HRTIM_BDMUPR_MICR HRTIM_BDMUPR_MICR_Msk /*!< MICR register update enable */
27701 #define HRTIM_BDMUPR_MDIER_Pos (2U)
27702 #define HRTIM_BDMUPR_MDIER_Msk (0x1UL << HRTIM_BDMUPR_MDIER_Pos) /*!< 0x00000004 */
27703 #define HRTIM_BDMUPR_MDIER HRTIM_BDMUPR_MDIER_Msk /*!< MDIER register update enable */
27704 #define HRTIM_BDMUPR_MCNT_Pos (3U)
27705 #define HRTIM_BDMUPR_MCNT_Msk (0x1UL << HRTIM_BDMUPR_MCNT_Pos) /*!< 0x00000008 */
27706 #define HRTIM_BDMUPR_MCNT HRTIM_BDMUPR_MCNT_Msk /*!< MCNT register update enable */
27707 #define HRTIM_BDMUPR_MPER_Pos (4U)
27708 #define HRTIM_BDMUPR_MPER_Msk (0x1UL << HRTIM_BDMUPR_MPER_Pos) /*!< 0x00000010 */
27709 #define HRTIM_BDMUPR_MPER HRTIM_BDMUPR_MPER_Msk /*!< MPER register update enable */
27710 #define HRTIM_BDMUPR_MREP_Pos (5U)
27711 #define HRTIM_BDMUPR_MREP_Msk (0x1UL << HRTIM_BDMUPR_MREP_Pos) /*!< 0x00000020 */
27712 #define HRTIM_BDMUPR_MREP HRTIM_BDMUPR_MREP_Msk /*!< MREP register update enable */
27713 #define HRTIM_BDMUPR_MCMP1_Pos (6U)
27714 #define HRTIM_BDMUPR_MCMP1_Msk (0x1UL << HRTIM_BDMUPR_MCMP1_Pos) /*!< 0x00000040 */
27715 #define HRTIM_BDMUPR_MCMP1 HRTIM_BDMUPR_MCMP1_Msk /*!< MCMP1 register update enable */
27716 #define HRTIM_BDMUPR_MCMP2_Pos (7U)
27717 #define HRTIM_BDMUPR_MCMP2_Msk (0x1UL << HRTIM_BDMUPR_MCMP2_Pos) /*!< 0x00000080 */
27718 #define HRTIM_BDMUPR_MCMP2 HRTIM_BDMUPR_MCMP2_Msk /*!< MCMP2 register update enable */
27719 #define HRTIM_BDMUPR_MCMP3_Pos (8U)
27720 #define HRTIM_BDMUPR_MCMP3_Msk (0x1UL << HRTIM_BDMUPR_MCMP3_Pos) /*!< 0x00000100 */
27721 #define HRTIM_BDMUPR_MCMP3 HRTIM_BDMUPR_MCMP3_Msk /*!< MCMP3 register update enable */
27722 #define HRTIM_BDMUPR_MCMP4_Pos (9U)
27723 #define HRTIM_BDMUPR_MCMP4_Msk (0x1UL << HRTIM_BDMUPR_MCMP4_Pos) /*!< 0x00000200 */
27724 #define HRTIM_BDMUPR_MCMP4 HRTIM_BDMUPR_MCMP4_Msk /*!< MPCMP4 register update enable */
27725
27726 /******************* Bit definition for HRTIM_BDTUPR register ***************/
27727 #define HRTIM_BDTUPR_TIMCR_Pos (0U)
27728 #define HRTIM_BDTUPR_TIMCR_Msk (0x1UL << HRTIM_BDTUPR_TIMCR_Pos) /*!< 0x00000001 */
27729 #define HRTIM_BDTUPR_TIMCR HRTIM_BDTUPR_TIMCR_Msk /*!< TIMCR register update enable */
27730 #define HRTIM_BDTUPR_TIMICR_Pos (1U)
27731 #define HRTIM_BDTUPR_TIMICR_Msk (0x1UL << HRTIM_BDTUPR_TIMICR_Pos) /*!< 0x00000002 */
27732 #define HRTIM_BDTUPR_TIMICR HRTIM_BDTUPR_TIMICR_Msk /*!< TIMICR register update enable */
27733 #define HRTIM_BDTUPR_TIMDIER_Pos (2U)
27734 #define HRTIM_BDTUPR_TIMDIER_Msk (0x1UL << HRTIM_BDTUPR_TIMDIER_Pos) /*!< 0x00000004 */
27735 #define HRTIM_BDTUPR_TIMDIER HRTIM_BDTUPR_TIMDIER_Msk /*!< TIMDIER register update enable */
27736 #define HRTIM_BDTUPR_TIMCNT_Pos (3U)
27737 #define HRTIM_BDTUPR_TIMCNT_Msk (0x1UL << HRTIM_BDTUPR_TIMCNT_Pos) /*!< 0x00000008 */
27738 #define HRTIM_BDTUPR_TIMCNT HRTIM_BDTUPR_TIMCNT_Msk /*!< TIMCNT register update enable */
27739 #define HRTIM_BDTUPR_TIMPER_Pos (4U)
27740 #define HRTIM_BDTUPR_TIMPER_Msk (0x1UL << HRTIM_BDTUPR_TIMPER_Pos) /*!< 0x00000010 */
27741 #define HRTIM_BDTUPR_TIMPER HRTIM_BDTUPR_TIMPER_Msk /*!< TIMPER register update enable */
27742 #define HRTIM_BDTUPR_TIMREP_Pos (5U)
27743 #define HRTIM_BDTUPR_TIMREP_Msk (0x1UL << HRTIM_BDTUPR_TIMREP_Pos) /*!< 0x00000020 */
27744 #define HRTIM_BDTUPR_TIMREP HRTIM_BDTUPR_TIMREP_Msk /*!< TIMREP register update enable */
27745 #define HRTIM_BDTUPR_TIMCMP1_Pos (6U)
27746 #define HRTIM_BDTUPR_TIMCMP1_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP1_Pos) /*!< 0x00000040 */
27747 #define HRTIM_BDTUPR_TIMCMP1 HRTIM_BDTUPR_TIMCMP1_Msk /*!< TIMCMP1 register update enable */
27748 #define HRTIM_BDTUPR_TIMCMP2_Pos (7U)
27749 #define HRTIM_BDTUPR_TIMCMP2_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP2_Pos) /*!< 0x00000080 */
27750 #define HRTIM_BDTUPR_TIMCMP2 HRTIM_BDTUPR_TIMCMP2_Msk /*!< TIMCMP2 register update enable */
27751 #define HRTIM_BDTUPR_TIMCMP3_Pos (8U)
27752 #define HRTIM_BDTUPR_TIMCMP3_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP3_Pos) /*!< 0x00000100 */
27753 #define HRTIM_BDTUPR_TIMCMP3 HRTIM_BDTUPR_TIMCMP3_Msk /*!< TIMCMP3 register update enable */
27754 #define HRTIM_BDTUPR_TIMCMP4_Pos (9U)
27755 #define HRTIM_BDTUPR_TIMCMP4_Msk (0x1UL << HRTIM_BDTUPR_TIMCMP4_Pos) /*!< 0x00000200 */
27756 #define HRTIM_BDTUPR_TIMCMP4 HRTIM_BDTUPR_TIMCMP4_Msk /*!< TIMCMP4 register update enable */
27757 #define HRTIM_BDTUPR_TIMDTR_Pos (10U)
27758 #define HRTIM_BDTUPR_TIMDTR_Msk (0x1UL << HRTIM_BDTUPR_TIMDTR_Pos) /*!< 0x00000400 */
27759 #define HRTIM_BDTUPR_TIMDTR HRTIM_BDTUPR_TIMDTR_Msk /*!< TIMDTR register update enable */
27760 #define HRTIM_BDTUPR_TIMSET1R_Pos (11U)
27761 #define HRTIM_BDTUPR_TIMSET1R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET1R_Pos) /*!< 0x00000800 */
27762 #define HRTIM_BDTUPR_TIMSET1R HRTIM_BDTUPR_TIMSET1R_Msk /*!< TIMSET1R register update enable */
27763 #define HRTIM_BDTUPR_TIMRST1R_Pos (12U)
27764 #define HRTIM_BDTUPR_TIMRST1R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST1R_Pos) /*!< 0x00001000 */
27765 #define HRTIM_BDTUPR_TIMRST1R HRTIM_BDTUPR_TIMRST1R_Msk /*!< TIMRST1R register update enable */
27766 #define HRTIM_BDTUPR_TIMSET2R_Pos (13U)
27767 #define HRTIM_BDTUPR_TIMSET2R_Msk (0x1UL << HRTIM_BDTUPR_TIMSET2R_Pos) /*!< 0x00002000 */
27768 #define HRTIM_BDTUPR_TIMSET2R HRTIM_BDTUPR_TIMSET2R_Msk /*!< TIMSET2R register update enable */
27769 #define HRTIM_BDTUPR_TIMRST2R_Pos (14U)
27770 #define HRTIM_BDTUPR_TIMRST2R_Msk (0x1UL << HRTIM_BDTUPR_TIMRST2R_Pos) /*!< 0x00004000 */
27771 #define HRTIM_BDTUPR_TIMRST2R HRTIM_BDTUPR_TIMRST2R_Msk /*!< TIMRST2R register update enable */
27772 #define HRTIM_BDTUPR_TIMEEFR1_Pos (15U)
27773 #define HRTIM_BDTUPR_TIMEEFR1_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR1_Pos) /*!< 0x00008000 */
27774 #define HRTIM_BDTUPR_TIMEEFR1 HRTIM_BDTUPR_TIMEEFR1_Msk /*!< TIMEEFR1 register update enable */
27775 #define HRTIM_BDTUPR_TIMEEFR2_Pos (16U)
27776 #define HRTIM_BDTUPR_TIMEEFR2_Msk (0x1UL << HRTIM_BDTUPR_TIMEEFR2_Pos) /*!< 0x00010000 */
27777 #define HRTIM_BDTUPR_TIMEEFR2 HRTIM_BDTUPR_TIMEEFR2_Msk /*!< TIMEEFR2 register update enable */
27778 #define HRTIM_BDTUPR_TIMRSTR_Pos (17U)
27779 #define HRTIM_BDTUPR_TIMRSTR_Msk (0x1UL << HRTIM_BDTUPR_TIMRSTR_Pos) /*!< 0x00020000 */
27780 #define HRTIM_BDTUPR_TIMRSTR HRTIM_BDTUPR_TIMRSTR_Msk /*!< TIMRSTR register update enable */
27781 #define HRTIM_BDTUPR_TIMCHPR_Pos (18U)
27782 #define HRTIM_BDTUPR_TIMCHPR_Msk (0x1UL << HRTIM_BDTUPR_TIMCHPR_Pos) /*!< 0x00040000 */
27783 #define HRTIM_BDTUPR_TIMCHPR HRTIM_BDTUPR_TIMCHPR_Msk /*!< TIMCHPR register update enable */
27784 #define HRTIM_BDTUPR_TIMOUTR_Pos (19U)
27785 #define HRTIM_BDTUPR_TIMOUTR_Msk (0x1UL << HRTIM_BDTUPR_TIMOUTR_Pos) /*!< 0x00080000 */
27786 #define HRTIM_BDTUPR_TIMOUTR HRTIM_BDTUPR_TIMOUTR_Msk /*!< TIMOUTR register update enable */
27787 #define HRTIM_BDTUPR_TIMFLTR_Pos (20U)
27788 #define HRTIM_BDTUPR_TIMFLTR_Msk (0x1UL << HRTIM_BDTUPR_TIMFLTR_Pos) /*!< 0x00100000 */
27789 #define HRTIM_BDTUPR_TIMFLTR HRTIM_BDTUPR_TIMFLTR_Msk /*!< TIMFLTR register update enable */
27790
27791 /******************* Bit definition for HRTIM_BDMADR register ***************/
27792 #define HRTIM_BDMADR_BDMADR_Pos (0U)
27793 #define HRTIM_BDMADR_BDMADR_Msk (0xFFFFFFFFUL << HRTIM_BDMADR_BDMADR_Pos) /*!< 0xFFFFFFFF */
27794 #define HRTIM_BDMADR_BDMADR HRTIM_BDMADR_BDMADR_Msk /*!< Burst DMA Data register */
27795
27796 /******************************************************************************/
27797 /* */
27798 /* RAM ECC monitoring */
27799 /* */
27800 /******************************************************************************/
27801 /****************** Bit definition for RAMECC_IER register ******************/
27802 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
27803 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
27804 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
27805 #define RAMECC_IER_GECCDEIE_Pos (2U)
27806 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
27807 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
27808 #define RAMECC_IER_GECCSEIE_Pos (1U)
27809 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
27810 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
27811 #define RAMECC_IER_GIE_Pos (0U)
27812 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
27813 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
27814
27815 /******************* Bit definition for RAMECC_CR register ******************/
27816 #define RAMECC_CR_ECCELEN_Pos (5U)
27817 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
27818 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
27819 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
27820 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
27821 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
27822 #define RAMECC_CR_ECCDEIE_Pos (3U)
27823 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
27824 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
27825 #define RAMECC_CR_ECCSEIE_Pos (2U)
27826 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
27827 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
27828
27829 /******************* Bit definition for RAMECC_SR register ******************/
27830 #define RAMECC_SR_DEBWDF_Pos (2U)
27831 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
27832 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
27833 #define RAMECC_SR_DEDF_Pos (1U)
27834 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
27835 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
27836 #define RAMECC_SR_SEDCF_Pos (0U)
27837 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
27838 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
27839
27840 /****************** Bit definition for RAMECC_FAR register ******************/
27841 #define RAMECC_FAR_FADD_Pos (0U)
27842 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
27843 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
27844
27845 /****************** Bit definition for RAMECC_FDRL register *****************/
27846 #define RAMECC_FAR_FDATAL_Pos (0U)
27847 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
27848 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
27849
27850 /****************** Bit definition for RAMECC_FDRH register *****************/
27851 #define RAMECC_FAR_FDATAH_Pos (0U)
27852 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
27853 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
27854
27855 /***************** Bit definition for RAMECC_FECR register ******************/
27856 #define RAMECC_FECR_FEC_Pos (0U)
27857 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
27858 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
27859
27860 /******************************************************************************/
27861 /* */
27862 /* MDIOS */
27863 /* */
27864 /******************************************************************************/
27865 /******************** Bit definition for MDIOS_CR register *******************/
27866 #define MDIOS_CR_EN_Pos (0U)
27867 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
27868 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
27869 #define MDIOS_CR_WRIE_Pos (1U)
27870 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
27871 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
27872 #define MDIOS_CR_RDIE_Pos (2U)
27873 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
27874 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
27875 #define MDIOS_CR_EIE_Pos (3U)
27876 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
27877 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
27878 #define MDIOS_CR_DPC_Pos (7U)
27879 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
27880 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
27881 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
27882 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
27883 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
27884 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
27885 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
27886 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
27887 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
27888 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
27889
27890 /******************** Bit definition for MDIOS_SR register *******************/
27891 #define MDIOS_SR_PERF_Pos (0U)
27892 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
27893 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
27894 #define MDIOS_SR_SERF_Pos (1U)
27895 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
27896 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
27897 #define MDIOS_SR_TERF_Pos (2U)
27898 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
27899 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
27900
27901 /******************** Bit definition for MDIOS_CLRFR register *******************/
27902 #define MDIOS_SR_CPERF_Pos (0U)
27903 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
27904 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
27905 #define MDIOS_SR_CSERF_Pos (1U)
27906 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
27907 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
27908 #define MDIOS_SR_CTERF_Pos (2U)
27909 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
27910 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
27911
27912 /******************************************************************************/
27913 /* */
27914 /* USB_OTG */
27915 /* */
27916 /******************************************************************************/
27917 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
27918 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
27919 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
27920 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
27921 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
27922 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
27923 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
27924 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
27925 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
27926 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
27927 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
27928 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
27929 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
27930 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
27931 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
27932 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
27933 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
27934 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
27935 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
27936 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
27937 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
27938 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
27939 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
27940 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
27941 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
27942 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
27943 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
27944 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
27945 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
27946 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
27947 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
27948 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
27949 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
27950 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
27951 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
27952 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
27953 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
27954 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
27955 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
27956 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
27957 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
27958 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
27959 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
27960 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
27961 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
27962 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
27963 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
27964 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
27965 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
27966 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
27967 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
27968 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
27969 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
27970 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
27971 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
27972
27973 /******************** Bit definition forUSB_OTG_HCFG register ********************/
27974
27975 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
27976 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
27977 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
27978 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
27979 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
27980 #define USB_OTG_HCFG_FSLSS_Pos (2U)
27981 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
27982 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
27983
27984 /******************** Bit definition forUSB_OTG_DCFG register ********************/
27985
27986 #define USB_OTG_DCFG_DSPD_Pos (0U)
27987 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
27988 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
27989 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
27990 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
27991 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
27992 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
27993 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
27994
27995 #define USB_OTG_DCFG_DAD_Pos (4U)
27996 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
27997 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
27998 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
27999 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
28000 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
28001 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
28002 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
28003 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
28004 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
28005
28006 #define USB_OTG_DCFG_PFIVL_Pos (11U)
28007 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
28008 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
28009 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
28010 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
28011
28012 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
28013 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
28014 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
28015 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
28016 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
28017
28018 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
28019 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
28020 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
28021 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
28022 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
28023 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
28024 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
28025 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
28026 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
28027 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
28028
28029 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
28030 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
28031 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
28032 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
28033 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
28034 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
28035 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
28036 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
28037 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
28038 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
28039 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
28040 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
28041 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
28042 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
28043 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
28044 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
28045 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
28046 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
28047 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
28048
28049 /******************** Bit definition forUSB_OTG_DCTL register ********************/
28050 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
28051 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
28052 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
28053 #define USB_OTG_DCTL_SDIS_Pos (1U)
28054 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
28055 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
28056 #define USB_OTG_DCTL_GINSTS_Pos (2U)
28057 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
28058 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
28059 #define USB_OTG_DCTL_GONSTS_Pos (3U)
28060 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
28061 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
28062
28063 #define USB_OTG_DCTL_TCTL_Pos (4U)
28064 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
28065 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
28066 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
28067 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
28068 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
28069 #define USB_OTG_DCTL_SGINAK_Pos (7U)
28070 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
28071 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
28072 #define USB_OTG_DCTL_CGINAK_Pos (8U)
28073 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
28074 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
28075 #define USB_OTG_DCTL_SGONAK_Pos (9U)
28076 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
28077 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
28078 #define USB_OTG_DCTL_CGONAK_Pos (10U)
28079 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
28080 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
28081 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
28082 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
28083 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
28084
28085 /******************** Bit definition forUSB_OTG_HFIR register ********************/
28086 #define USB_OTG_HFIR_FRIVL_Pos (0U)
28087 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
28088 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
28089
28090 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
28091 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
28092 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
28093 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
28094 #define USB_OTG_HFNUM_FTREM_Pos (16U)
28095 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
28096 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
28097
28098 /******************** Bit definition forUSB_OTG_DSTS register ********************/
28099 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
28100 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
28101 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
28102
28103 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
28104 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
28105 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
28106 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
28107 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
28108 #define USB_OTG_DSTS_EERR_Pos (3U)
28109 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
28110 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
28111 #define USB_OTG_DSTS_FNSOF_Pos (8U)
28112 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
28113 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
28114
28115 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
28116 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
28117 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
28118 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
28119
28120 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
28121 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
28122 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
28123 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
28124 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
28125 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
28126 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
28127 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
28128 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
28129 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
28130 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
28131 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
28132 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
28133 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
28134 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
28135 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
28136 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
28137
28138 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
28139
28140 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
28141 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
28142 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
28143 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
28144 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
28145 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
28146 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
28147 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
28148 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
28149 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
28150 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
28151 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
28152 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
28153 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
28154 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
28155
28156 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
28157 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
28158 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
28159 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
28160 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
28161 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
28162 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
28163 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
28164 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
28165 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
28166 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
28167 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
28168 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
28169 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
28170 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
28171 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
28172 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
28173 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
28174 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
28175 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
28176 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
28177 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
28178 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
28179 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
28180 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
28181 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
28182 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
28183 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
28184 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
28185 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
28186 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
28187 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
28188 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
28189 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
28190 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
28191 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
28192 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
28193 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
28194 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
28195 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
28196 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
28197 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
28198 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
28199 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
28200 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
28201 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
28202
28203 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
28204 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
28205 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
28206 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
28207 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
28208 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
28209 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
28210 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
28211 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
28212 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
28213 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
28214 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
28215 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
28216 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
28217 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
28218 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
28219
28220 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
28221 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
28222 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
28223 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
28224 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
28225 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
28226 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
28227 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
28228 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
28229 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
28230 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
28231 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
28232 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
28233 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
28234
28235 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
28236 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
28237 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
28238 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
28239 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
28240 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
28241 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
28242 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
28243 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
28244 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
28245 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
28246 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
28247 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
28248 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
28249 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
28250 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
28251 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
28252 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
28253 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
28254 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
28255 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
28256 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
28257 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
28258 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
28259 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
28260
28261 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
28262 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
28263 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
28264 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
28265
28266 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
28267 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
28268 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
28269 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
28270 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
28271 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
28272 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
28273 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
28274 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
28275 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
28276 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
28277
28278 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
28279 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
28280 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
28281 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
28282 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
28283 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
28284 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
28285 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
28286 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
28287 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
28288 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
28289
28290 /******************** Bit definition forUSB_OTG_HAINT register ********************/
28291 #define USB_OTG_HAINT_HAINT_Pos (0U)
28292 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
28293 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
28294
28295 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
28296 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
28297 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
28298 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
28299 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
28300 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
28301 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
28302 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
28303 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
28304 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
28305 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
28306 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
28307 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
28308 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
28309 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
28310 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
28311 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
28312 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
28313 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
28314 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
28315 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
28316 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
28317 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
28318 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
28319 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
28320 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
28321 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
28322 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
28323 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
28324 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
28325 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
28326 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
28327 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
28328 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
28329 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
28330 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
28331 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
28332
28333 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
28334 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
28335 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
28336 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
28337 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
28338 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
28339 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
28340 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
28341 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
28342 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
28343 #define USB_OTG_GINTSTS_SOF_Pos (3U)
28344 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
28345 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
28346 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
28347 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
28348 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
28349 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
28350 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
28351 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
28352 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
28353 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
28354 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
28355 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
28356 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
28357 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
28358 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
28359 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
28360 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
28361 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
28362 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
28363 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
28364 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
28365 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
28366 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
28367 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
28368 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
28369 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
28370 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
28371 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
28372 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
28373 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
28374 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
28375 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
28376 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
28377 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
28378 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
28379 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
28380 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
28381 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
28382 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
28383 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
28384 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
28385 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
28386 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
28387 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
28388 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
28389 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
28390 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
28391 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
28392 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
28393 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
28394 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
28395 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
28396 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
28397 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
28398 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
28399 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
28400 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
28401 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
28402 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
28403 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
28404 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
28405 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
28406 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
28407 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
28408 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
28409 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
28410 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
28411 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
28412 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
28413 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
28414 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
28415 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
28416 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
28417 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
28418
28419 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
28420 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
28421 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
28422 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
28423 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
28424 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
28425 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
28426 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
28427 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
28428 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
28429 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
28430 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
28431 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
28432 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
28433 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
28434 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
28435 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
28436 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
28437 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
28438 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
28439 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
28440 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
28441 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
28442 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
28443 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
28444 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
28445 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
28446 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
28447 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
28448 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
28449 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
28450 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
28451 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
28452 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
28453 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
28454 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
28455 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
28456 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
28457 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
28458 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
28459 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
28460 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
28461 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
28462 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
28463 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
28464 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
28465 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
28466 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
28467 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
28468 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
28469 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
28470 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
28471 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
28472 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
28473 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
28474 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
28475 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
28476 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
28477 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
28478 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
28479 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
28480 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
28481 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
28482 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
28483 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
28484 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
28485 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
28486 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
28487 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
28488 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
28489 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
28490 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
28491 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
28492 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
28493 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
28494 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
28495 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
28496 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
28497 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
28498 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
28499 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
28500 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
28501 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
28502 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
28503 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
28504
28505 /******************** Bit definition forUSB_OTG_DAINT register ********************/
28506 #define USB_OTG_DAINT_IEPINT_Pos (0U)
28507 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
28508 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
28509 #define USB_OTG_DAINT_OEPINT_Pos (16U)
28510 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
28511 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
28512
28513 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
28514 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
28515 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
28516 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
28517
28518 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
28519 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
28520 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
28521 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
28522 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
28523 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
28524 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
28525 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
28526 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
28527 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
28528 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
28529 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
28530 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
28531
28532 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
28533 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
28534 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
28535 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
28536 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
28537 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
28538 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
28539
28540 /******************** Bit definition for OTG register ********************/
28541
28542 #define USB_OTG_CHNUM_Pos (0U)
28543 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
28544 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
28545 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
28546 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
28547 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
28548 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
28549 #define USB_OTG_BCNT_Pos (4U)
28550 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
28551 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
28552
28553 #define USB_OTG_DPID_Pos (15U)
28554 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
28555 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
28556 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
28557 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
28558
28559 #define USB_OTG_PKTSTS_Pos (17U)
28560 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
28561 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
28562 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
28563 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
28564 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
28565 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
28566
28567 #define USB_OTG_EPNUM_Pos (0U)
28568 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
28569 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
28570 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
28571 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
28572 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
28573 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
28574
28575 #define USB_OTG_FRMNUM_Pos (21U)
28576 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
28577 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
28578 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
28579 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
28580 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
28581 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
28582
28583 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
28584 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
28585 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
28586 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
28587
28588 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
28589 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
28590 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
28591 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
28592
28593 /******************** Bit definition for OTG register ********************/
28594 #define USB_OTG_NPTXFSA_Pos (0U)
28595 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
28596 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
28597 #define USB_OTG_NPTXFD_Pos (16U)
28598 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
28599 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
28600 #define USB_OTG_TX0FSA_Pos (0U)
28601 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
28602 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
28603 #define USB_OTG_TX0FD_Pos (16U)
28604 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
28605 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
28606
28607 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
28608 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
28609 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
28610 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
28611
28612 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
28613 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
28614 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
28615 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
28616
28617 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
28618 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
28619 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
28620 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
28621 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
28622 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
28623 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
28624 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
28625 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
28626 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
28627 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
28628
28629 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
28630 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
28631 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
28632 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
28633 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
28634 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
28635 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
28636 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
28637 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
28638 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
28639
28640 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
28641 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
28642 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
28643 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
28644 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
28645 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
28646 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
28647
28648 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
28649 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
28650 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
28651 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
28652 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
28653 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
28654 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
28655 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
28656 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
28657 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
28658 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
28659 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
28660 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
28661 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
28662 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
28663
28664 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
28665 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
28666 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
28667 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
28668 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
28669 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
28670 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
28671 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
28672 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
28673 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
28674 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
28675 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
28676 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
28677 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
28678 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
28679
28680 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
28681 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
28682 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
28683 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
28684
28685 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
28686 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
28687 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
28688 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
28689 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
28690 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
28691 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
28692
28693 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
28694 #define USB_OTG_GCCFG_DCDET_Pos (0U)
28695 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
28696 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
28697 #define USB_OTG_GCCFG_PDET_Pos (1U)
28698 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
28699 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
28700 #define USB_OTG_GCCFG_SDET_Pos (2U)
28701 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
28702 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
28703 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
28704 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
28705 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
28706 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
28707 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
28708 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
28709 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
28710 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
28711 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
28712 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
28713 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
28714 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
28715 #define USB_OTG_GCCFG_PDEN_Pos (19U)
28716 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
28717 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
28718 #define USB_OTG_GCCFG_SDEN_Pos (20U)
28719 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
28720 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
28721 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
28722 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
28723 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
28724
28725 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
28726 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
28727 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
28728 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
28729 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
28730 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
28731 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
28732
28733 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
28734 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
28735 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
28736 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
28737 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
28738 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
28739 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
28740
28741 /******************** Bit definition forUSB_OTG_CID register ********************/
28742 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
28743 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
28744 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
28745
28746 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
28747 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
28748 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
28749 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
28750 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
28751 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
28752 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
28753 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
28754 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
28755 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
28756 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
28757 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
28758 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
28759 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
28760 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
28761 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
28762 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
28763 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
28764 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
28765 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
28766 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
28767 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
28768 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
28769 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
28770 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
28771 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
28772 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
28773 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
28774 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
28775 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
28776 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
28777 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
28778 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
28779 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
28780 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
28781 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
28782 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
28783 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
28784 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
28785 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
28786 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
28787 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
28788 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
28789 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
28790 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
28791 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
28792
28793 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
28794 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
28795 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
28796 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
28797 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
28798 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
28799 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
28800 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
28801 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
28802 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
28803 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
28804 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
28805 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
28806 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
28807 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
28808 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
28809 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
28810 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
28811 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
28812 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
28813 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
28814 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
28815 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
28816 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
28817 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
28818 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
28819 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
28820 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
28821
28822 /******************** Bit definition forUSB_OTG_HPRT register ********************/
28823 #define USB_OTG_HPRT_PCSTS_Pos (0U)
28824 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
28825 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
28826 #define USB_OTG_HPRT_PCDET_Pos (1U)
28827 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
28828 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
28829 #define USB_OTG_HPRT_PENA_Pos (2U)
28830 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
28831 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
28832 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
28833 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
28834 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
28835 #define USB_OTG_HPRT_POCA_Pos (4U)
28836 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
28837 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
28838 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
28839 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
28840 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
28841 #define USB_OTG_HPRT_PRES_Pos (6U)
28842 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
28843 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
28844 #define USB_OTG_HPRT_PSUSP_Pos (7U)
28845 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
28846 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
28847 #define USB_OTG_HPRT_PRST_Pos (8U)
28848 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
28849 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
28850
28851 #define USB_OTG_HPRT_PLSTS_Pos (10U)
28852 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
28853 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
28854 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
28855 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
28856 #define USB_OTG_HPRT_PPWR_Pos (12U)
28857 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
28858 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
28859
28860 #define USB_OTG_HPRT_PTCTL_Pos (13U)
28861 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
28862 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
28863 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
28864 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
28865 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
28866 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
28867
28868 #define USB_OTG_HPRT_PSPD_Pos (17U)
28869 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
28870 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
28871 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
28872 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
28873
28874 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
28875 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
28876 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
28877 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
28878 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
28879 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
28880 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
28881 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
28882 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
28883 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
28884 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
28885 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
28886 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
28887 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
28888 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
28889 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
28890 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
28891 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
28892 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
28893 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
28894 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
28895 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
28896 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
28897 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
28898 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
28899 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
28900 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
28901 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
28902 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
28903 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
28904 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
28905 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
28906 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
28907 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
28908
28909 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
28910 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
28911 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
28912 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
28913 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
28914 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
28915 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
28916
28917 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
28918 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
28919 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
28920 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
28921 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
28922 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
28923 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
28924 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
28925 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
28926 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
28927 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
28928 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
28929 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
28930
28931 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
28932 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
28933 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
28934 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
28935 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
28936 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
28937 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
28938 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
28939
28940 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
28941 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
28942 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
28943 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
28944 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
28945 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
28946 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
28947 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
28948 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
28949 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
28950 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
28951 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
28952 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
28953 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
28954 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
28955 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
28956 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
28957 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
28958 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
28959 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
28960 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
28961 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
28962 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
28963 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
28964 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
28965
28966 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
28967 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
28968 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
28969 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
28970
28971 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
28972 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
28973 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
28974 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
28975 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
28976 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
28977 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
28978 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
28979 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
28980 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
28981 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
28982 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
28983 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
28984
28985 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
28986 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
28987 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
28988 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
28989 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
28990
28991 #define USB_OTG_HCCHAR_MC_Pos (20U)
28992 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
28993 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
28994 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
28995 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
28996
28997 #define USB_OTG_HCCHAR_DAD_Pos (22U)
28998 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
28999 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
29000 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
29001 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
29002 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
29003 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
29004 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
29005 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
29006 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
29007 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
29008 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
29009 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
29010 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
29011 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
29012 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
29013 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
29014 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
29015 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
29016
29017 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
29018
29019 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
29020 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
29021 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
29022 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
29023 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
29024 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
29025 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
29026 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
29027 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
29028 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
29029
29030 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
29031 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
29032 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
29033 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
29034 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
29035 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
29036 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
29037 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
29038 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
29039 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
29040
29041 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
29042 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
29043 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
29044 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
29045 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
29046 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
29047 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
29048 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
29049 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
29050 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
29051 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
29052
29053 /******************** Bit definition forUSB_OTG_HCINT register ********************/
29054 #define USB_OTG_HCINT_XFRC_Pos (0U)
29055 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
29056 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
29057 #define USB_OTG_HCINT_CHH_Pos (1U)
29058 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
29059 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
29060 #define USB_OTG_HCINT_AHBERR_Pos (2U)
29061 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
29062 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
29063 #define USB_OTG_HCINT_STALL_Pos (3U)
29064 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
29065 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
29066 #define USB_OTG_HCINT_NAK_Pos (4U)
29067 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
29068 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
29069 #define USB_OTG_HCINT_ACK_Pos (5U)
29070 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
29071 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
29072 #define USB_OTG_HCINT_NYET_Pos (6U)
29073 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
29074 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
29075 #define USB_OTG_HCINT_TXERR_Pos (7U)
29076 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
29077 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
29078 #define USB_OTG_HCINT_BBERR_Pos (8U)
29079 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
29080 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
29081 #define USB_OTG_HCINT_FRMOR_Pos (9U)
29082 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
29083 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
29084 #define USB_OTG_HCINT_DTERR_Pos (10U)
29085 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
29086 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
29087
29088 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
29089 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
29090 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
29091 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
29092 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
29093 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
29094 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
29095 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
29096 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
29097 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
29098 #define USB_OTG_DIEPINT_TOC_Pos (3U)
29099 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
29100 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
29101 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
29102 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
29103 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
29104 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
29105 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
29106 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
29107 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
29108 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
29109 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
29110 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
29111 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
29112 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
29113 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
29114 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
29115 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
29116 #define USB_OTG_DIEPINT_BNA_Pos (9U)
29117 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
29118 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
29119 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
29120 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
29121 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
29122 #define USB_OTG_DIEPINT_BERR_Pos (12U)
29123 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
29124 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
29125 #define USB_OTG_DIEPINT_NAK_Pos (13U)
29126 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
29127 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
29128
29129 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
29130 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
29131 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
29132 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
29133 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
29134 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
29135 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
29136 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
29137 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
29138 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
29139 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
29140 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
29141 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
29142 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
29143 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
29144 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
29145 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
29146 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
29147 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
29148 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
29149 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
29150 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
29151 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
29152 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
29153 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
29154 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
29155 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
29156 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
29157 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
29158 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
29159 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
29160 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
29161 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
29162 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
29163
29164 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
29165
29166 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
29167 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
29168 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
29169 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
29170 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
29171 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
29172 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
29173 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
29174 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
29175 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
29176 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
29177 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
29178 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
29179 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
29180 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
29181 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
29182 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
29183 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
29184 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
29185 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
29186 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
29187 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
29188 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
29189 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
29190
29191 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
29192 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
29193 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
29194 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
29195
29196 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
29197 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
29198 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
29199 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
29200
29201 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
29202 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
29203 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
29204 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
29205
29206 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
29207 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
29208 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
29209 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
29210 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
29211 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
29212 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
29213
29214 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
29215
29216 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
29217 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
29218 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
29219 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
29220 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
29221 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
29222 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
29223 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
29224 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
29225 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
29226 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
29227 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
29228 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
29229 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
29230 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
29231 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
29232 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
29233 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
29234 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
29235 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
29236 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
29237 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
29238 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
29239 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
29240 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
29241 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
29242 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
29243 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
29244 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
29245 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
29246 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
29247 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
29248 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
29249 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
29250 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
29251 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
29252 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
29253 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
29254
29255 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
29256 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
29257 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
29258 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
29259 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
29260 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
29261 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
29262 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
29263 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
29264 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
29265 #define USB_OTG_DOEPINT_STUP_Pos (3U)
29266 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
29267 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
29268 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
29269 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
29270 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
29271 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
29272 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
29273 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
29274 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
29275 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
29276 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
29277 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
29278 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
29279 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
29280 #define USB_OTG_DOEPINT_BERR_Pos (12U)
29281 #define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
29282 #define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
29283 #define USB_OTG_DOEPINT_NAK_Pos (13U)
29284 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
29285 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
29286 #define USB_OTG_DOEPINT_NYET_Pos (14U)
29287 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
29288 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
29289 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
29290 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
29291 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
29292
29293 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
29294
29295 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
29296 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
29297 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
29298 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
29299 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
29300 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
29301
29302 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
29303 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
29304 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
29305 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
29306 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
29307
29308 /******************** Bit definition for PCGCCTL register ********************/
29309 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
29310 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
29311 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
29312 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
29313 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
29314 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
29315 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
29316 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
29317 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
29318
29319 /**
29320 * @}
29321 */
29322
29323 /**
29324 * @}
29325 */
29326
29327 /** @addtogroup Exported_macros
29328 * @{
29329 */
29330
29331 /******************************* ADC Instances ********************************/
29332 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
29333 ((INSTANCE) == ADC2) || \
29334 ((INSTANCE) == ADC3))
29335
29336 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
29337
29338 #define IS_ADC_COMMON_INSTANCE(INSTANCE) (((INSTANCE) == ADC12_COMMON) ||\
29339 ((INSTANCE) == ADC3_COMMON))
29340
29341 /******************************** COMP Instances ******************************/
29342 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
29343 ((INSTANCE) == COMP2))
29344
29345 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
29346 /******************** COMP Instances with window mode capability **************/
29347 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
29348
29349
29350 /******************************* CRC Instances ********************************/
29351 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
29352
29353 /******************************* DAC Instances ********************************/
29354 #define IS_DAC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DAC1)
29355 /******************************* DCMI Instances *******************************/
29356 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
29357
29358 /******************************* DELAYBLOCK Instances *******************************/
29359 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
29360 ((INSTANCE) == DLYB_SDMMC2) || \
29361 ((INSTANCE) == DLYB_QUADSPI))
29362 /****************************** DFSDM Instances *******************************/
29363 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
29364 ((INSTANCE) == DFSDM1_Filter1) || \
29365 ((INSTANCE) == DFSDM1_Filter2) || \
29366 ((INSTANCE) == DFSDM1_Filter3))
29367
29368 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
29369 ((INSTANCE) == DFSDM1_Channel1) || \
29370 ((INSTANCE) == DFSDM1_Channel2) || \
29371 ((INSTANCE) == DFSDM1_Channel3) || \
29372 ((INSTANCE) == DFSDM1_Channel4) || \
29373 ((INSTANCE) == DFSDM1_Channel5) || \
29374 ((INSTANCE) == DFSDM1_Channel6) || \
29375 ((INSTANCE) == DFSDM1_Channel7))
29376 /****************************** RAMECC Instances ******************************/
29377 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC1_Monitor1) || \
29378 ((INSTANCE) == RAMECC1_Monitor2) || \
29379 ((INSTANCE) == RAMECC1_Monitor3) || \
29380 ((INSTANCE) == RAMECC1_Monitor4) || \
29381 ((INSTANCE) == RAMECC1_Monitor5) || \
29382 ((INSTANCE) == RAMECC2_Monitor1) || \
29383 ((INSTANCE) == RAMECC2_Monitor2) || \
29384 ((INSTANCE) == RAMECC2_Monitor3) || \
29385 ((INSTANCE) == RAMECC2_Monitor4) || \
29386 ((INSTANCE) == RAMECC2_Monitor5) || \
29387 ((INSTANCE) == RAMECC3_Monitor1) || \
29388 ((INSTANCE) == RAMECC3_Monitor2))
29389
29390 /******************************** DMA Instances *******************************/
29391 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29392 ((INSTANCE) == DMA1_Stream1) || \
29393 ((INSTANCE) == DMA1_Stream2) || \
29394 ((INSTANCE) == DMA1_Stream3) || \
29395 ((INSTANCE) == DMA1_Stream4) || \
29396 ((INSTANCE) == DMA1_Stream5) || \
29397 ((INSTANCE) == DMA1_Stream6) || \
29398 ((INSTANCE) == DMA1_Stream7) || \
29399 ((INSTANCE) == DMA2_Stream0) || \
29400 ((INSTANCE) == DMA2_Stream1) || \
29401 ((INSTANCE) == DMA2_Stream2) || \
29402 ((INSTANCE) == DMA2_Stream3) || \
29403 ((INSTANCE) == DMA2_Stream4) || \
29404 ((INSTANCE) == DMA2_Stream5) || \
29405 ((INSTANCE) == DMA2_Stream6) || \
29406 ((INSTANCE) == DMA2_Stream7) || \
29407 ((INSTANCE) == BDMA_Channel0) || \
29408 ((INSTANCE) == BDMA_Channel1) || \
29409 ((INSTANCE) == BDMA_Channel2) || \
29410 ((INSTANCE) == BDMA_Channel3) || \
29411 ((INSTANCE) == BDMA_Channel4) || \
29412 ((INSTANCE) == BDMA_Channel5) || \
29413 ((INSTANCE) == BDMA_Channel6) || \
29414 ((INSTANCE) == BDMA_Channel7))
29415
29416 /****************************** BDMA CHANNEL Instances ***************************/
29417 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
29418 ((INSTANCE) == BDMA_Channel1) || \
29419 ((INSTANCE) == BDMA_Channel2) || \
29420 ((INSTANCE) == BDMA_Channel3) || \
29421 ((INSTANCE) == BDMA_Channel4) || \
29422 ((INSTANCE) == BDMA_Channel5) || \
29423 ((INSTANCE) == BDMA_Channel6) || \
29424 ((INSTANCE) == BDMA_Channel7))
29425
29426 /****************************** DMA DMAMUX ALL Instances ***************************/
29427 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29428 ((INSTANCE) == DMA1_Stream1) || \
29429 ((INSTANCE) == DMA1_Stream2) || \
29430 ((INSTANCE) == DMA1_Stream3) || \
29431 ((INSTANCE) == DMA1_Stream4) || \
29432 ((INSTANCE) == DMA1_Stream5) || \
29433 ((INSTANCE) == DMA1_Stream6) || \
29434 ((INSTANCE) == DMA1_Stream7) || \
29435 ((INSTANCE) == DMA2_Stream0) || \
29436 ((INSTANCE) == DMA2_Stream1) || \
29437 ((INSTANCE) == DMA2_Stream2) || \
29438 ((INSTANCE) == DMA2_Stream3) || \
29439 ((INSTANCE) == DMA2_Stream4) || \
29440 ((INSTANCE) == DMA2_Stream5) || \
29441 ((INSTANCE) == DMA2_Stream6) || \
29442 ((INSTANCE) == DMA2_Stream7) || \
29443 ((INSTANCE) == BDMA_Channel0) || \
29444 ((INSTANCE) == BDMA_Channel1) || \
29445 ((INSTANCE) == BDMA_Channel2) || \
29446 ((INSTANCE) == BDMA_Channel3) || \
29447 ((INSTANCE) == BDMA_Channel4) || \
29448 ((INSTANCE) == BDMA_Channel5) || \
29449 ((INSTANCE) == BDMA_Channel6) || \
29450 ((INSTANCE) == BDMA_Channel7))
29451
29452 /****************************** BDMA DMAMUX Instances ***************************/
29453 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA_Channel0) || \
29454 ((INSTANCE) == BDMA_Channel1) || \
29455 ((INSTANCE) == BDMA_Channel2) || \
29456 ((INSTANCE) == BDMA_Channel3) || \
29457 ((INSTANCE) == BDMA_Channel4) || \
29458 ((INSTANCE) == BDMA_Channel5) || \
29459 ((INSTANCE) == BDMA_Channel6) || \
29460 ((INSTANCE) == BDMA_Channel7))
29461
29462 /****************************** DMA STREAM Instances ***************************/
29463 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29464 ((INSTANCE) == DMA1_Stream1) || \
29465 ((INSTANCE) == DMA1_Stream2) || \
29466 ((INSTANCE) == DMA1_Stream3) || \
29467 ((INSTANCE) == DMA1_Stream4) || \
29468 ((INSTANCE) == DMA1_Stream5) || \
29469 ((INSTANCE) == DMA1_Stream6) || \
29470 ((INSTANCE) == DMA1_Stream7) || \
29471 ((INSTANCE) == DMA2_Stream0) || \
29472 ((INSTANCE) == DMA2_Stream1) || \
29473 ((INSTANCE) == DMA2_Stream2) || \
29474 ((INSTANCE) == DMA2_Stream3) || \
29475 ((INSTANCE) == DMA2_Stream4) || \
29476 ((INSTANCE) == DMA2_Stream5) || \
29477 ((INSTANCE) == DMA2_Stream6) || \
29478 ((INSTANCE) == DMA2_Stream7))
29479
29480 /****************************** DMA DMAMUX Instances ***************************/
29481 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
29482 ((INSTANCE) == DMA1_Stream1) || \
29483 ((INSTANCE) == DMA1_Stream2) || \
29484 ((INSTANCE) == DMA1_Stream3) || \
29485 ((INSTANCE) == DMA1_Stream4) || \
29486 ((INSTANCE) == DMA1_Stream5) || \
29487 ((INSTANCE) == DMA1_Stream6) || \
29488 ((INSTANCE) == DMA1_Stream7) || \
29489 ((INSTANCE) == DMA2_Stream0) || \
29490 ((INSTANCE) == DMA2_Stream1) || \
29491 ((INSTANCE) == DMA2_Stream2) || \
29492 ((INSTANCE) == DMA2_Stream3) || \
29493 ((INSTANCE) == DMA2_Stream4) || \
29494 ((INSTANCE) == DMA2_Stream5) || \
29495 ((INSTANCE) == DMA2_Stream6) || \
29496 ((INSTANCE) == DMA2_Stream7))
29497
29498 /******************************** DMA Request Generator Instances **************/
29499 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
29500 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
29501 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
29502 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
29503 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
29504 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
29505 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
29506 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
29507 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
29508 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
29509 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
29510 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
29511 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
29512 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
29513 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
29514 ((INSTANCE) == DMAMUX2_RequestGenerator7))
29515
29516 /******************************* DMA2D Instances *******************************/
29517 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
29518
29519 /******************************** MDMA Request Generator Instances **************/
29520 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
29521 ((INSTANCE) == MDMA_Channel1) || \
29522 ((INSTANCE) == MDMA_Channel2) || \
29523 ((INSTANCE) == MDMA_Channel3) || \
29524 ((INSTANCE) == MDMA_Channel4) || \
29525 ((INSTANCE) == MDMA_Channel5) || \
29526 ((INSTANCE) == MDMA_Channel6) || \
29527 ((INSTANCE) == MDMA_Channel7) || \
29528 ((INSTANCE) == MDMA_Channel8) || \
29529 ((INSTANCE) == MDMA_Channel9) || \
29530 ((INSTANCE) == MDMA_Channel10) || \
29531 ((INSTANCE) == MDMA_Channel11) || \
29532 ((INSTANCE) == MDMA_Channel12) || \
29533 ((INSTANCE) == MDMA_Channel13) || \
29534 ((INSTANCE) == MDMA_Channel14) || \
29535 ((INSTANCE) == MDMA_Channel15))
29536
29537 /******************************* QUADSPI Instances *******************************/
29538 #define IS_QSPI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == QUADSPI)
29539
29540 /******************************* FDCAN Instances ******************************/
29541 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
29542 ((__INSTANCE__) == FDCAN2))
29543
29544 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
29545
29546 /******************************* GPIO Instances *******************************/
29547 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
29548 ((INSTANCE) == GPIOB) || \
29549 ((INSTANCE) == GPIOC) || \
29550 ((INSTANCE) == GPIOD) || \
29551 ((INSTANCE) == GPIOE) || \
29552 ((INSTANCE) == GPIOF) || \
29553 ((INSTANCE) == GPIOG) || \
29554 ((INSTANCE) == GPIOH) || \
29555 ((INSTANCE) == GPIOI) || \
29556 ((INSTANCE) == GPIOJ) || \
29557 ((INSTANCE) == GPIOK))
29558
29559 /******************************* GPIO AF Instances ****************************/
29560 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
29561
29562 /**************************** GPIO Lock Instances *****************************/
29563 /* On H7, all GPIO Bank support the Lock mechanism */
29564 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
29565
29566 /******************************** HSEM Instances *******************************/
29567 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
29568 /******************** Bit definition for HSEM_CR register *****************/
29569 #define HSEM_CPU1_COREID (0x00000003U) /* Semaphore Core CM7 ID */
29570 #define HSEM_CPU2_COREID (0x00000001U) /* Semaphore Core CM4 ID */
29571 #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
29572 #define HSEM_CR_COREID_CPU2 (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
29573 #if defined(CORE_CM4)
29574 #define HSEM_CR_COREID_CURRENT (HSEM_CPU2_COREID << HSEM_CR_COREID_Pos)
29575 #else /* CORE_CM7 */
29576 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
29577 #endif /* CORE_CM4 */
29578
29579 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
29580 #define HSEM_SEMID_MAX (31U) /* HSEM ID Max */
29581
29582 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
29583 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
29584
29585 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
29586 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
29587
29588 /******************************** I2C Instances *******************************/
29589 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
29590 ((INSTANCE) == I2C2) || \
29591 ((INSTANCE) == I2C3) || \
29592 ((INSTANCE) == I2C4))
29593 /************** I2C Instances : wakeup capability from stop modes *************/
29594 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
29595
29596 /****************************** SMBUS Instances *******************************/
29597 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
29598 ((INSTANCE) == I2C2) || \
29599 ((INSTANCE) == I2C3) || \
29600 ((INSTANCE) == I2C4))
29601 /******************************** I2S Instances *******************************/
29602 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29603 ((INSTANCE) == SPI2) || \
29604 ((INSTANCE) == SPI3))
29605
29606 /****************************** LTDC Instances ********************************/
29607 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
29608
29609 /******************************* RNG Instances ********************************/
29610 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
29611
29612 /****************************** RTC Instances *********************************/
29613 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
29614
29615 /****************************** SDMMC Instances *********************************/
29616 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
29617 ((_INSTANCE_) == SDMMC2))
29618
29619 /******************************** SMBUS Instances *****************************/
29620 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
29621
29622 /******************************** SPI Instances *******************************/
29623 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29624 ((INSTANCE) == SPI2) || \
29625 ((INSTANCE) == SPI3) || \
29626 ((INSTANCE) == SPI4) || \
29627 ((INSTANCE) == SPI5) || \
29628 ((INSTANCE) == SPI6))
29629
29630 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
29631 ((INSTANCE) == SPI2) || \
29632 ((INSTANCE) == SPI3))
29633
29634 /******************************** SWPMI Instances *****************************/
29635 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
29636
29637 /****************** LPTIM Instances : All supported instances *****************/
29638 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
29639 ((INSTANCE) == LPTIM2) || \
29640 ((INSTANCE) == LPTIM3) || \
29641 ((INSTANCE) == LPTIM4) || \
29642 ((INSTANCE) == LPTIM5))
29643
29644 /****************** LPTIM Instances : supporting encoder interface **************/
29645 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
29646 ((INSTANCE) == LPTIM2))
29647
29648 /****************** TIM Instances : All supported instances *******************/
29649 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29650 ((INSTANCE) == TIM2) || \
29651 ((INSTANCE) == TIM3) || \
29652 ((INSTANCE) == TIM4) || \
29653 ((INSTANCE) == TIM5) || \
29654 ((INSTANCE) == TIM6) || \
29655 ((INSTANCE) == TIM7) || \
29656 ((INSTANCE) == TIM8) || \
29657 ((INSTANCE) == TIM12) || \
29658 ((INSTANCE) == TIM13) || \
29659 ((INSTANCE) == TIM14) || \
29660 ((INSTANCE) == TIM15) || \
29661 ((INSTANCE) == TIM16) || \
29662 ((INSTANCE) == TIM17))
29663
29664 /************* TIM Instances : at least 1 capture/compare channel *************/
29665 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29666 ((INSTANCE) == TIM2) || \
29667 ((INSTANCE) == TIM3) || \
29668 ((INSTANCE) == TIM4) || \
29669 ((INSTANCE) == TIM5) || \
29670 ((INSTANCE) == TIM8) || \
29671 ((INSTANCE) == TIM12) || \
29672 ((INSTANCE) == TIM13) || \
29673 ((INSTANCE) == TIM14) || \
29674 ((INSTANCE) == TIM15) || \
29675 ((INSTANCE) == TIM16) || \
29676 ((INSTANCE) == TIM17))
29677
29678 /************ TIM Instances : at least 2 capture/compare channels *************/
29679 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29680 ((INSTANCE) == TIM2) || \
29681 ((INSTANCE) == TIM3) || \
29682 ((INSTANCE) == TIM4) || \
29683 ((INSTANCE) == TIM5) || \
29684 ((INSTANCE) == TIM8) || \
29685 ((INSTANCE) == TIM12) || \
29686 ((INSTANCE) == TIM15))
29687
29688 /************ TIM Instances : at least 3 capture/compare channels *************/
29689 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29690 ((INSTANCE) == TIM2) || \
29691 ((INSTANCE) == TIM3) || \
29692 ((INSTANCE) == TIM4) || \
29693 ((INSTANCE) == TIM5) || \
29694 ((INSTANCE) == TIM8))
29695
29696 /************ TIM Instances : at least 4 capture/compare channels *************/
29697 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29698 ((INSTANCE) == TIM2) || \
29699 ((INSTANCE) == TIM3) || \
29700 ((INSTANCE) == TIM4) || \
29701 ((INSTANCE) == TIM5) || \
29702 ((INSTANCE) == TIM8))
29703
29704 /************ TIM Instances : at least 5 capture/compare channels *************/
29705 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29706 ((INSTANCE) == TIM8))
29707 /************ TIM Instances : at least 6 capture/compare channels *************/
29708 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29709 ((INSTANCE) == TIM8))
29710
29711 /******************** TIM Instances : Advanced-control timers *****************/
29712 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
29713 ((__INSTANCE__) == TIM8))
29714
29715 /******************** TIM Instances : Advanced-control timers *****************/
29716
29717 /******************* TIM Instances : Timer input XOR function *****************/
29718 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29719 ((INSTANCE) == TIM2) || \
29720 ((INSTANCE) == TIM3) || \
29721 ((INSTANCE) == TIM4) || \
29722 ((INSTANCE) == TIM5) || \
29723 ((INSTANCE) == TIM8) || \
29724 ((INSTANCE) == TIM15))
29725
29726 /****************** TIM Instances : DMA requests generation (UDE) *************/
29727 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29728 ((INSTANCE) == TIM2) || \
29729 ((INSTANCE) == TIM3) || \
29730 ((INSTANCE) == TIM4) || \
29731 ((INSTANCE) == TIM5) || \
29732 ((INSTANCE) == TIM6) || \
29733 ((INSTANCE) == TIM7) || \
29734 ((INSTANCE) == TIM8) || \
29735 ((INSTANCE) == TIM15) || \
29736 ((INSTANCE) == TIM16) || \
29737 ((INSTANCE) == TIM17))
29738
29739 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
29740 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29741 ((INSTANCE) == TIM2) || \
29742 ((INSTANCE) == TIM3) || \
29743 ((INSTANCE) == TIM4) || \
29744 ((INSTANCE) == TIM5) || \
29745 ((INSTANCE) == TIM8) || \
29746 ((INSTANCE) == TIM15) || \
29747 ((INSTANCE) == TIM16) || \
29748 ((INSTANCE) == TIM17))
29749
29750 /************ TIM Instances : DMA requests generation (COMDE) *****************/
29751 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29752 ((INSTANCE) == TIM2) || \
29753 ((INSTANCE) == TIM3) || \
29754 ((INSTANCE) == TIM4) || \
29755 ((INSTANCE) == TIM5) || \
29756 ((INSTANCE) == TIM8) || \
29757 ((INSTANCE) == TIM15))
29758
29759 /******************** TIM Instances : DMA burst feature ***********************/
29760 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29761 ((INSTANCE) == TIM2) || \
29762 ((INSTANCE) == TIM3) || \
29763 ((INSTANCE) == TIM4) || \
29764 ((INSTANCE) == TIM5) || \
29765 ((INSTANCE) == TIM8))
29766
29767 /*************** TIM Instances : external trigger reamp input available *******/
29768 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29769 ((INSTANCE) == TIM2) || \
29770 ((INSTANCE) == TIM3) || \
29771 ((INSTANCE) == TIM4) || \
29772 ((INSTANCE) == TIM5) || \
29773 ((INSTANCE) == TIM8))
29774
29775 /****************** TIM Instances : remapping capability **********************/
29776 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29777 ((INSTANCE) == TIM2) || \
29778 ((INSTANCE) == TIM3) || \
29779 ((INSTANCE) == TIM5) || \
29780 ((INSTANCE) == TIM8) || \
29781 ((INSTANCE) == TIM16) || \
29782 ((INSTANCE) == TIM17))
29783
29784 /*************** TIM Instances : external trigger reamp input available *******/
29785 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29786 ((INSTANCE) == TIM2) || \
29787 ((INSTANCE) == TIM3) || \
29788 ((INSTANCE) == TIM5) || \
29789 ((INSTANCE) == TIM8))
29790
29791 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
29792 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29793 ((INSTANCE) == TIM2) || \
29794 ((INSTANCE) == TIM3) || \
29795 ((INSTANCE) == TIM4) || \
29796 ((INSTANCE) == TIM5) || \
29797 ((INSTANCE) == TIM6) || \
29798 ((INSTANCE) == TIM7) || \
29799 ((INSTANCE) == TIM8) || \
29800 ((INSTANCE) == TIM15))
29801
29802 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
29803 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29804 ((INSTANCE) == TIM2) || \
29805 ((INSTANCE) == TIM3) || \
29806 ((INSTANCE) == TIM4) || \
29807 ((INSTANCE) == TIM5) || \
29808 ((INSTANCE) == TIM8) || \
29809 ((INSTANCE) == TIM12))
29810
29811 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
29812 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29813 ((INSTANCE) == TIM8))
29814
29815 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
29816 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29817 ((INSTANCE) == TIM2) || \
29818 ((INSTANCE) == TIM3) || \
29819 ((INSTANCE) == TIM4) || \
29820 ((INSTANCE) == TIM5) || \
29821 ((INSTANCE) == TIM8) || \
29822 ((INSTANCE) == TIM15) || \
29823 ((INSTANCE) == TIM16) || \
29824 ((INSTANCE) == TIM17))
29825
29826 /****************** TIM Instances : supporting commutation event *************/
29827 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29828 ((INSTANCE) == TIM8) || \
29829 ((INSTANCE) == TIM15) || \
29830 ((INSTANCE) == TIM16) || \
29831 ((INSTANCE) == TIM17))
29832
29833 /****************** TIM Instances : supporting encoder interface **************/
29834 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
29835 ((__INSTANCE__) == TIM2) || \
29836 ((__INSTANCE__) == TIM3) || \
29837 ((__INSTANCE__) == TIM4) || \
29838 ((__INSTANCE__) == TIM5) || \
29839 ((__INSTANCE__) == TIM8))
29840
29841 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
29842 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29843 ((INSTANCE) == TIM8))
29844 /******************* TIM Instances : output(s) available **********************/
29845 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
29846 ((((INSTANCE) == TIM1) && \
29847 (((CHANNEL) == TIM_CHANNEL_1) || \
29848 ((CHANNEL) == TIM_CHANNEL_2) || \
29849 ((CHANNEL) == TIM_CHANNEL_3) || \
29850 ((CHANNEL) == TIM_CHANNEL_4) || \
29851 ((CHANNEL) == TIM_CHANNEL_5) || \
29852 ((CHANNEL) == TIM_CHANNEL_6))) \
29853 || \
29854 (((INSTANCE) == TIM2) && \
29855 (((CHANNEL) == TIM_CHANNEL_1) || \
29856 ((CHANNEL) == TIM_CHANNEL_2) || \
29857 ((CHANNEL) == TIM_CHANNEL_3) || \
29858 ((CHANNEL) == TIM_CHANNEL_4))) \
29859 || \
29860 (((INSTANCE) == TIM3) && \
29861 (((CHANNEL) == TIM_CHANNEL_1)|| \
29862 ((CHANNEL) == TIM_CHANNEL_2) || \
29863 ((CHANNEL) == TIM_CHANNEL_3) || \
29864 ((CHANNEL) == TIM_CHANNEL_4))) \
29865 || \
29866 (((INSTANCE) == TIM4) && \
29867 (((CHANNEL) == TIM_CHANNEL_1) || \
29868 ((CHANNEL) == TIM_CHANNEL_2) || \
29869 ((CHANNEL) == TIM_CHANNEL_3) || \
29870 ((CHANNEL) == TIM_CHANNEL_4))) \
29871 || \
29872 (((INSTANCE) == TIM5) && \
29873 (((CHANNEL) == TIM_CHANNEL_1) || \
29874 ((CHANNEL) == TIM_CHANNEL_2) || \
29875 ((CHANNEL) == TIM_CHANNEL_3) || \
29876 ((CHANNEL) == TIM_CHANNEL_4))) \
29877 || \
29878 (((INSTANCE) == TIM8) && \
29879 (((CHANNEL) == TIM_CHANNEL_1) || \
29880 ((CHANNEL) == TIM_CHANNEL_2) || \
29881 ((CHANNEL) == TIM_CHANNEL_3) || \
29882 ((CHANNEL) == TIM_CHANNEL_4) || \
29883 ((CHANNEL) == TIM_CHANNEL_5) || \
29884 ((CHANNEL) == TIM_CHANNEL_6))) \
29885 || \
29886 (((INSTANCE) == TIM12) && \
29887 (((CHANNEL) == TIM_CHANNEL_1) || \
29888 ((CHANNEL) == TIM_CHANNEL_2))) \
29889 || \
29890 (((INSTANCE) == TIM13) && \
29891 (((CHANNEL) == TIM_CHANNEL_1))) \
29892 || \
29893 (((INSTANCE) == TIM14) && \
29894 (((CHANNEL) == TIM_CHANNEL_1))) \
29895 || \
29896 (((INSTANCE) == TIM15) && \
29897 (((CHANNEL) == TIM_CHANNEL_1) || \
29898 ((CHANNEL) == TIM_CHANNEL_2))) \
29899 || \
29900 (((INSTANCE) == TIM16) && \
29901 (((CHANNEL) == TIM_CHANNEL_1))) \
29902 || \
29903 (((INSTANCE) == TIM17) && \
29904 (((CHANNEL) == TIM_CHANNEL_1))))
29905
29906 /****************** TIM Instances : supporting the break function *************/
29907 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
29908 (((INSTANCE) == TIM1) || \
29909 ((INSTANCE) == TIM8) || \
29910 ((INSTANCE) == TIM15) || \
29911 ((INSTANCE) == TIM16) || \
29912 ((INSTANCE) == TIM17))
29913
29914 /************** TIM Instances : supporting Break source selection *************/
29915 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
29916 ((INSTANCE) == TIM8))
29917
29918 /****************** TIM Instances : supporting complementary output(s) ********/
29919 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
29920 ((((INSTANCE) == TIM1) && \
29921 (((CHANNEL) == TIM_CHANNEL_1) || \
29922 ((CHANNEL) == TIM_CHANNEL_2) || \
29923 ((CHANNEL) == TIM_CHANNEL_3))) \
29924 || \
29925 (((INSTANCE) == TIM8) && \
29926 (((CHANNEL) == TIM_CHANNEL_1) || \
29927 ((CHANNEL) == TIM_CHANNEL_2) || \
29928 ((CHANNEL) == TIM_CHANNEL_3))) \
29929 || \
29930 (((INSTANCE) == TIM15) && \
29931 ((CHANNEL) == TIM_CHANNEL_1)) \
29932 || \
29933 (((INSTANCE) == TIM16) && \
29934 ((CHANNEL) == TIM_CHANNEL_1)) \
29935 || \
29936 (((INSTANCE) == TIM17) && \
29937 ((CHANNEL) == TIM_CHANNEL_1)))
29938
29939 /****************** TIM Instances : supporting counting mode selection ********/
29940 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
29941 (((INSTANCE) == TIM1) || \
29942 ((INSTANCE) == TIM2) || \
29943 ((INSTANCE) == TIM3) || \
29944 ((INSTANCE) == TIM4) || \
29945 ((INSTANCE) == TIM5) || \
29946 ((INSTANCE) == TIM8))
29947
29948 /****************** TIM Instances : supporting repetition counter *************/
29949 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
29950 (((INSTANCE) == TIM1) || \
29951 ((INSTANCE) == TIM8) || \
29952 ((INSTANCE) == TIM15) || \
29953 ((INSTANCE) == TIM16) || \
29954 ((INSTANCE) == TIM17))
29955
29956 /****************** TIM Instances : supporting synchronization ****************/
29957 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
29958 (((__INSTANCE__) == TIM1) || \
29959 ((__INSTANCE__) == TIM2) || \
29960 ((__INSTANCE__) == TIM3) || \
29961 ((__INSTANCE__) == TIM4) || \
29962 ((__INSTANCE__) == TIM5) || \
29963 ((__INSTANCE__) == TIM6) || \
29964 ((__INSTANCE__) == TIM8) || \
29965 ((__INSTANCE__) == TIM12) || \
29966 ((__INSTANCE__) == TIM15))
29967
29968 /****************** TIM Instances : supporting clock division *****************/
29969 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
29970 (((INSTANCE) == TIM1) || \
29971 ((INSTANCE) == TIM2) || \
29972 ((INSTANCE) == TIM3) || \
29973 ((INSTANCE) == TIM4) || \
29974 ((INSTANCE) == TIM5) || \
29975 ((INSTANCE) == TIM8) || \
29976 ((INSTANCE) == TIM15) || \
29977 ((INSTANCE) == TIM16) || \
29978 ((INSTANCE) == TIM17))
29979
29980 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
29981 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
29982 (((INSTANCE) == TIM1) || \
29983 ((INSTANCE) == TIM2) || \
29984 ((INSTANCE) == TIM3) || \
29985 ((INSTANCE) == TIM4) || \
29986 ((INSTANCE) == TIM5) || \
29987 ((INSTANCE) == TIM8))
29988
29989 /****************** TIM Instances : supporting external clock mode 2 **********/
29990 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
29991 (((INSTANCE) == TIM1) || \
29992 ((INSTANCE) == TIM2) || \
29993 ((INSTANCE) == TIM3) || \
29994 ((INSTANCE) == TIM4) || \
29995 ((INSTANCE) == TIM5) || \
29996 ((INSTANCE) == TIM8))
29997
29998 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
29999 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
30000 (((INSTANCE) == TIM1) || \
30001 ((INSTANCE) == TIM2) || \
30002 ((INSTANCE) == TIM3) || \
30003 ((INSTANCE) == TIM4) || \
30004 ((INSTANCE) == TIM5) || \
30005 ((INSTANCE) == TIM8) || \
30006 ((INSTANCE) == TIM15))
30007
30008 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
30009 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
30010 (((INSTANCE) == TIM1) || \
30011 ((INSTANCE) == TIM2) || \
30012 ((INSTANCE) == TIM3) || \
30013 ((INSTANCE) == TIM4) || \
30014 ((INSTANCE) == TIM5) || \
30015 ((INSTANCE) == TIM8) || \
30016 ((INSTANCE) == TIM15))
30017
30018 /****************** TIM Instances : supporting OCxREF clear *******************/
30019 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
30020 (((INSTANCE) == TIM1) || \
30021 ((INSTANCE) == TIM2) || \
30022 ((INSTANCE) == TIM3))
30023
30024 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
30025 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
30026 (((INSTANCE) == TIM2) || \
30027 ((INSTANCE) == TIM5))
30028
30029 /****************** TIM Instances : TIM_BKIN2 ***************************/
30030 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
30031 (((INSTANCE) == TIM1) || \
30032 ((INSTANCE) == TIM8))
30033
30034 /****************** TIM Instances : supporting Hall sensor interface **********/
30035 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
30036 ((__INSTANCE__) == TIM2) || \
30037 ((__INSTANCE__) == TIM3) || \
30038 ((__INSTANCE__) == TIM4) || \
30039 ((__INSTANCE__) == TIM5) || \
30040 ((__INSTANCE__) == TIM15) || \
30041 ((__INSTANCE__) == TIM8))
30042
30043 /****************************** HRTIM Instances *******************************/
30044 #define IS_HRTIM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == HRTIM1))
30045
30046 /******************** USART Instances : Synchronous mode **********************/
30047 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30048 ((INSTANCE) == USART2) || \
30049 ((INSTANCE) == USART3) || \
30050 ((INSTANCE) == USART6))
30051
30052 /******************** USART Instances : SPI slave mode ************************/
30053 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30054 ((INSTANCE) == USART2) || \
30055 ((INSTANCE) == USART3) || \
30056 ((INSTANCE) == USART6))
30057
30058 /******************** UART Instances : Asynchronous mode **********************/
30059 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30060 ((INSTANCE) == USART2) || \
30061 ((INSTANCE) == USART3) || \
30062 ((INSTANCE) == UART4) || \
30063 ((INSTANCE) == UART5) || \
30064 ((INSTANCE) == USART6) || \
30065 ((INSTANCE) == UART7) || \
30066 ((INSTANCE) == UART8))
30067
30068 /******************** UART Instances : FIFO mode.******************************/
30069 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30070 ((INSTANCE) == USART2) || \
30071 ((INSTANCE) == USART3) || \
30072 ((INSTANCE) == UART4) || \
30073 ((INSTANCE) == UART5) || \
30074 ((INSTANCE) == USART6) || \
30075 ((INSTANCE) == UART7) || \
30076 ((INSTANCE) == UART8))
30077
30078 /****************** UART Instances : Auto Baud Rate detection *****************/
30079 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30080 ((INSTANCE) == USART2) || \
30081 ((INSTANCE) == USART3) || \
30082 ((INSTANCE) == UART4) || \
30083 ((INSTANCE) == UART5) || \
30084 ((INSTANCE) == USART6) || \
30085 ((INSTANCE) == UART7) || \
30086 ((INSTANCE) == UART8))
30087
30088 /*********************** UART Instances : Driver Enable ***********************/
30089 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30090 ((INSTANCE) == USART2) || \
30091 ((INSTANCE) == USART3) || \
30092 ((INSTANCE) == UART4) || \
30093 ((INSTANCE) == UART5) || \
30094 ((INSTANCE) == USART6) || \
30095 ((INSTANCE) == UART7) || \
30096 ((INSTANCE) == UART8) || \
30097 ((INSTANCE) == LPUART1))
30098
30099 /********************* UART Instances : Half-Duplex mode **********************/
30100 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30101 ((INSTANCE) == USART2) || \
30102 ((INSTANCE) == USART3) || \
30103 ((INSTANCE) == UART4) || \
30104 ((INSTANCE) == UART5) || \
30105 ((INSTANCE) == USART6) || \
30106 ((INSTANCE) == UART7) || \
30107 ((INSTANCE) == UART8) || \
30108 ((INSTANCE) == LPUART1))
30109
30110 /******************* UART Instances : Hardware Flow control *******************/
30111 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30112 ((INSTANCE) == USART2) || \
30113 ((INSTANCE) == USART3) || \
30114 ((INSTANCE) == UART4) || \
30115 ((INSTANCE) == UART5) || \
30116 ((INSTANCE) == USART6) || \
30117 ((INSTANCE) == UART7) || \
30118 ((INSTANCE) == UART8) || \
30119 ((INSTANCE) == LPUART1))
30120
30121 /************************* UART Instances : LIN mode **************************/
30122 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30123 ((INSTANCE) == USART2) || \
30124 ((INSTANCE) == USART3) || \
30125 ((INSTANCE) == UART4) || \
30126 ((INSTANCE) == UART5) || \
30127 ((INSTANCE) == USART6) || \
30128 ((INSTANCE) == UART7) || \
30129 ((INSTANCE) == UART8))
30130
30131 /****************** UART Instances : Wake-up from Stop mode *******************/
30132 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30133 ((INSTANCE) == USART2) || \
30134 ((INSTANCE) == USART3) || \
30135 ((INSTANCE) == UART4) || \
30136 ((INSTANCE) == UART5) || \
30137 ((INSTANCE) == USART6) || \
30138 ((INSTANCE) == UART7) || \
30139 ((INSTANCE) == UART8) || \
30140 ((INSTANCE) == LPUART1))
30141
30142 /************************* UART Instances : IRDA mode *************************/
30143 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30144 ((INSTANCE) == USART2) || \
30145 ((INSTANCE) == USART3) || \
30146 ((INSTANCE) == UART4) || \
30147 ((INSTANCE) == UART5) || \
30148 ((INSTANCE) == USART6) || \
30149 ((INSTANCE) == UART7) || \
30150 ((INSTANCE) == UART8))
30151
30152 /********************* USART Instances : Smard card mode **********************/
30153 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
30154 ((INSTANCE) == USART2) || \
30155 ((INSTANCE) == USART3) || \
30156 ((INSTANCE) == USART6))
30157
30158 /****************************** LPUART Instance *******************************/
30159 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
30160
30161 /****************************** IWDG Instances ********************************/
30162 #define IS_IWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == IWDG1) || ((INSTANCE) == IWDG2))
30163 /****************************** USB Instances ********************************/
30164 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
30165
30166 /****************************** WWDG Instances ********************************/
30167 #define IS_WWDG_ALL_INSTANCE(INSTANCE) (((INSTANCE) == WWDG1) || \
30168 ((INSTANCE) == WWDG2))
30169 /****************************** MDIOS Instances ********************************/
30170 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
30171
30172 /****************************** CEC Instances *********************************/
30173 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
30174
30175 /****************************** SAI Instances ********************************/
30176 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
30177 ((INSTANCE) == SAI1_Block_B) || \
30178 ((INSTANCE) == SAI2_Block_A) || \
30179 ((INSTANCE) == SAI2_Block_B) || \
30180 ((INSTANCE) == SAI3_Block_A) || \
30181 ((INSTANCE) == SAI3_Block_B) || \
30182 ((INSTANCE) == SAI4_Block_A) || \
30183 ((INSTANCE) == SAI4_Block_B))
30184
30185 /****************************** SPDIFRX Instances ********************************/
30186 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
30187
30188 /****************************** OPAMP Instances *******************************/
30189 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
30190 ((INSTANCE) == OPAMP2))
30191
30192 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
30193
30194 /*********************** USB OTG PCD Instances ********************************/
30195 #define IS_PCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
30196 ((INSTANCE) == USB_OTG_HS))
30197
30198 /*********************** USB OTG HCD Instances ********************************/
30199 #define IS_HCD_ALL_INSTANCE(INSTANCE) (((INSTANCE) == USB_OTG_FS) || \
30200 ((INSTANCE) == USB_OTG_HS))
30201
30202 /******************************************************************************/
30203 /* For a painless codes migration between the STM32H7xx device product */
30204 /* lines, or with STM32F7xx devices the aliases defined below are put */
30205 /* in place to overcome the differences in the interrupt handlers and IRQn */
30206 /* definitions. No need to update developed interrupt code when moving */
30207 /* across product lines within the same STM32H7 Family */
30208 /******************************************************************************/
30209
30210 /* Aliases for __IRQn */
30211 #define HASH_RNG_IRQn RNG_IRQn
30212 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
30213 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
30214 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
30215 #define PVD_IRQn PVD_AVD_IRQn
30216
30217
30218
30219 /* Aliases for __IRQHandler */
30220 #define HASH_RNG_IRQHandler RNG_IRQHandler
30221 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
30222 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
30223 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
30224 #define PVD_IRQHandler PVD_AVD_IRQHandler
30225
30226 /* Aliases for COMP __IRQHandler */
30227 #define COMP_IRQHandler COMP1_IRQHandler
30228
30229 /**
30230 * @}
30231 */
30232
30233 /**
30234 * @}
30235 */
30236
30237 /**
30238 * @}
30239 */
30240
30241 #ifdef __cplusplus
30242 }
30243 #endif /* __cplusplus */
30244
30245 #endif /* STM32H747xx_H */
30246
30247 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software