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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / CMSIS / Device / ST / STM32H7xx / Include / stm32h7a3xxq.h
blob1b428ccdac10ca31b9d6cf3aee94fb6b38f04468
1 /**
2 ******************************************************************************
3 * @file stm32h7a3xxq.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H7A3xxQ Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32h7a3xxq
31 * @{
32 */
33
34 #ifndef STM32H7A3xxQ_H
35 #define STM32H7A3xxQ_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45 /**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49 typedef enum
50 {
51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */
64 RTC_TAMP_STAMP_CSS_LSE_IRQn = 2, /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 DFSDM2_IRQn = 42, /*!< DFSDM2 global Interrupt */
105 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
106 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
107 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
108 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
109 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
110 FMC_IRQn = 48, /*!< FMC global Interrupt */
111 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
112 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
113 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
114 UART4_IRQn = 52, /*!< UART4 global Interrupt */
115 UART5_IRQn = 53, /*!< UART5 global Interrupt */
116 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
117 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
118 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
119 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
120 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
121 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
122 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
123 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
124 DFSDM1_FLT4_IRQn = 64, /*!< DFSDM Filter4 Interrupt */
125 DFSDM1_FLT5_IRQn = 65, /*!< DFSDM Filter5 Interrupt */
126 DFSDM1_FLT6_IRQn = 66, /*!< DFSDM Filter6 Interrupt */
127 DFSDM1_FLT7_IRQn = 67, /*!< DFSDM Filter7 Interrupt */
128 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
129 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
130 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
131 USART6_IRQn = 71, /*!< USART6 global interrupt */
132 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
133 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
134 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
135 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
136 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
137 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
138 DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */
139 RNG_IRQn = 80, /*!< RNG global interrupt */
140 FPU_IRQn = 81, /*!< FPU global interrupt */
141 UART7_IRQn = 82, /*!< UART7 global interrupt */
142 UART8_IRQn = 83, /*!< UART8 global interrupt */
143 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
144 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
145 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
146 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
147 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
148 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
149 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
150 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
151 OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */
152 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
153 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
154 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
155 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
156 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
157 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
158 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
159 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
160 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
161 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
162 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
163 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
164 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
165 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
166 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
167 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
168 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
169 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
170 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
171 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
172 DAC2_IRQn = 127, /*!< DAC2 global Interrupt */
173 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
174 BDMA2_Channel0_IRQn = 129, /*!< BDMA2 Channel 0 global Interrupt */
175 BDMA2_Channel1_IRQn = 130, /*!< BDMA2 Channel 1 global Interrupt */
176 BDMA2_Channel2_IRQn = 131, /*!< BDMA2 Channel 2 global Interrupt */
177 BDMA2_Channel3_IRQn = 132, /*!< BDMA2 Channel 3 global Interrupt */
178 BDMA2_Channel4_IRQn = 133, /*!< BDMA2 Channel 4 global Interrupt */
179 BDMA2_Channel5_IRQn = 134, /*!< BDMA2 Channel 5 global Interrupt */
180 BDMA2_Channel6_IRQn = 135, /*!< BDMA2 Channel 6 global Interrupt */
181 BDMA2_Channel7_IRQn = 136, /*!< BDMA2 Channel 7 global Interrupt */
182 COMP_IRQn = 137 , /*!< COMP global Interrupt */
183 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
184 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
185 UART9_IRQn = 140, /*!< UART9 global interrupt */
186 USART10_IRQn = 141, /*!< USART10 global interrupt */
187 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
188 WWDG_RST_IRQn = 143, /*!<Window Watchdog Event interrupt */
189 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
190 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
191 DTS_IRQn = 147, /*!< Digital Temperature Sensor Global Interrupt */
192 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
193 OCTOSPI2_IRQn = 150, /*!< OctoSPI2 global interrupt */
194 GFXMMU_IRQn = 153, /*!< GFXMMU global interrupt */
195 BDMA1_IRQn = 154, /*!< BDMA1 for DFSM global interrupt */
196 } IRQn_Type;
197
198 /**
199 * @}
200 */
201
202 /** @addtogroup Configuration_section_for_CMSIS
203 * @{
204 */
205
206 #define SMPS /*!< Switched mode power supply feature */
207
208
209
210 /**
211 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
212 */
213 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
214 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
215 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
216 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
217 #define __FPU_PRESENT 1 /*!< FPU present */
218 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
219 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
220 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
221
222 /**
223 * @}
224 */
225
226
227
228
229 #include "system_stm32h7xx.h"
230 #include <stdint.h>
231
232 /** @addtogroup Peripheral_registers_structures
233 * @{
234 */
235
236 /**
237 * @brief Analog to Digital Converter
238 */
239
240 typedef struct
241 {
242 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
243 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
244 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
245 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
246 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
247 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
248 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
249 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
250 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
251 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
252 uint32_t RESERVED1; /*!< Reserved, 0x028 */
253 uint32_t RESERVED2; /*!< Reserved, 0x02C */
254 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
255 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
256 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
257 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
258 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
259 uint32_t RESERVED3; /*!< Reserved, 0x044 */
260 uint32_t RESERVED4; /*!< Reserved, 0x048 */
261 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
262 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
263 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
264 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
265 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
266 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
267 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
268 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
269 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
270 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
271 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
272 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
273 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
274 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
275 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
276 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
277 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
278 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
279 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
280 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
281 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
282 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
283 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
284 } ADC_TypeDef;
285
286
287 typedef struct
288 {
289 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
290 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
291 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
292 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
293 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
294
295 } ADC_Common_TypeDef;
296
297
298 /**
299 * @brief VREFBUF
300 */
301
302 typedef struct
303 {
304 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
305 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
306 } VREFBUF_TypeDef;
307
308
309 /**
310 * @brief FD Controller Area Network
311 */
312
313 typedef struct
314 {
315 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
316 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
317 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
318 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
319 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
320 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
321 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
322 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
323 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
324 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
325 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
326 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
327 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
328 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
329 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
330 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
331 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
332 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
333 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
334 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
335 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
336 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
337 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
338 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
339 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
340 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
341 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
342 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
343 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
344 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
345 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
346 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
347 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
348 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
349 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
350 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
351 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
352 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
353 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
354 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
355 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
356 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
357 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
358 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
359 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
360 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
361 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
362 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
363 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
364 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
365 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
366 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
367 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
368 } FDCAN_GlobalTypeDef;
369
370 /**
371 * @brief TTFD Controller Area Network
372 */
373
374 typedef struct
375 {
376 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
377 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
378 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
379 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
380 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
381 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
382 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
383 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
384 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
385 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
386 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
387 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
388 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
389 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
390 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
391 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
392 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
393 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
394 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
395 } TTCAN_TypeDef;
396
397 /**
398 * @brief FD Controller Area Network
399 */
400
401 typedef struct
402 {
403 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
404 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
405 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
406 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
407 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
408 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
409 } FDCAN_ClockCalibrationUnit_TypeDef;
410
411
412 /**
413 * @brief Consumer Electronics Control
414 */
415
416 typedef struct
417 {
418 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
419 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
420 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
421 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
422 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
423 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
424 }CEC_TypeDef;
425
426 /**
427 * @brief CRC calculation unit
428 */
429
430 typedef struct
431 {
432 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
433 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
434 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
435 uint32_t RESERVED2; /*!< Reserved, 0x0C */
436 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
437 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
438 } CRC_TypeDef;
439
440
441 /**
442 * @brief Clock Recovery System
443 */
444 typedef struct
445 {
446 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
447 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
448 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
449 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
450 } CRS_TypeDef;
451
452
453 /**
454 * @brief Digital to Analog Converter
455 */
456
457 typedef struct
458 {
459 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
460 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
461 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
462 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
463 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
464 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
465 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
466 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
467 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
468 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
469 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
470 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
471 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
472 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
473 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
474 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
475 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
476 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
477 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
478 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
479 } DAC_TypeDef;
480
481 /**
482 * @brief DFSDM module registers
483 */
484 typedef struct
485 {
486 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
487 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
488 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
489 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
490 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
491 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
492 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
493 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
494 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
495 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
496 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
497 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
498 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
499 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
500 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
501 } DFSDM_Filter_TypeDef;
502
503 /**
504 * @brief DFSDM channel configuration registers
505 */
506 typedef struct
507 {
508 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
509 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
510 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
511 short circuit detector register, Address offset: 0x08 */
512 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
513 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
514 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
515 } DFSDM_Channel_TypeDef;
516
517 /**
518 * @brief Debug MCU
519 */
520 typedef struct
521 {
522 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
523 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
524 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
525 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
526 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
527 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
528 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
529 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
530 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
531 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
532 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
533 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
534 }DBGMCU_TypeDef;
535 /**
536 * @brief DCMI
537 */
538
539 typedef struct
540 {
541 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
542 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
543 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
544 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
545 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
546 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
547 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
548 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
549 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
550 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
551 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
552 } DCMI_TypeDef;
553
554 /**
555 * @brief PSSI
556 */
557
558 typedef struct
559 {
560 __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */
561 __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
562 __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
563 __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
564 __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
565 __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
566 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
567 __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
568 __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */
569 __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */
570 __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */
571 __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */
572 __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */
573 } PSSI_TypeDef;
574
575 /**
576 * @brief DMA Controller
577 */
578
579 typedef struct
580 {
581 __IO uint32_t CR; /*!< DMA stream x configuration register */
582 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
583 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
584 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
585 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
586 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
587 } DMA_Stream_TypeDef;
588
589 typedef struct
590 {
591 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
592 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
593 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
594 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
595 } DMA_TypeDef;
596
597 typedef struct
598 {
599 __IO uint32_t CCR; /*!< DMA channel x configuration register */
600 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
601 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
602 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
603 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
604 } BDMA_Channel_TypeDef;
605
606 typedef struct
607 {
608 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
609 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
610 } BDMA_TypeDef;
611
612 typedef struct
613 {
614 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
615 }DMAMUX_Channel_TypeDef;
616
617 typedef struct
618 {
619 __IO uint32_t CSR; /*!< DMA Channel Status Register */
620 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
621 }DMAMUX_ChannelStatus_TypeDef;
622
623 typedef struct
624 {
625 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
626 }DMAMUX_RequestGen_TypeDef;
627
628 typedef struct
629 {
630 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
631 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
632 }DMAMUX_RequestGenStatus_TypeDef;
633
634 /**
635 * @brief MDMA Controller
636 */
637 typedef struct
638 {
639 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
640 }MDMA_TypeDef;
641
642 typedef struct
643 {
644 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
645 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
646 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
647 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
648 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
649 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
650 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
651 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
652 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
653 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
654 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
655 uint32_t RESERVED0; /*!< Reserved, 0x68 */
656 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
657 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
658 }MDMA_Channel_TypeDef;
659
660 /**
661 * @brief DMA2D Controller
662 */
663
664 typedef struct
665 {
666 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
667 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
668 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
669 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
670 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
671 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
672 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
673 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
674 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
675 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
676 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
677 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
678 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
679 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
680 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
681 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
682 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
683 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
684 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
685 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
686 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
687 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
688 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
689 } DMA2D_TypeDef;
690
691
692 /**
693 * @brief External Interrupt/Event Controller
694 */
695
696 typedef struct
697 {
698 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
699 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
700 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
701 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
702 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
703 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
704 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
705 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
706 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
707 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
708 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
709 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
710 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
711 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
712 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
713 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
714 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
715 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
716 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
717 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
718 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
719 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
720 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
721 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
722 uint32_t RESERVED4; /*!< Reserved, 0x8C */
723 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
724 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
725 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
726 uint32_t RESERVED5; /*!< Reserved, 0x9C */
727 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
728 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
729 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
730 }EXTI_TypeDef;
731
732 typedef struct
733 {
734 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
735 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
736 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
737 uint32_t RESERVED1; /*!< Reserved, 0x0C */
738 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
739 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
740 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
741 uint32_t RESERVED2; /*!< Reserved, 0x1C */
742 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
743 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
744 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
745 }EXTI_Core_TypeDef;
746
747
748 /**
749 * @brief FLASH Registers
750 */
751
752 typedef struct
753 {
754 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
755 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
756 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
757 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
758 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
759 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
760 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
761 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
762 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
763 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
764 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
765 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
766 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
767 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
768 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
769 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
770 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
771 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
772 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
773 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
774 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
775 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
776 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
777 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
778 uint32_t RESERVED; /*!< Reserved, 0x64 */
779 __IO uint32_t OTPBL_CUR; /*!< Flash Current OTP Block Lock Register, Address offset: 0x68 */
780 __IO uint32_t OTPBL_PRG; /*!< Flash OTP Block Lock to Program Register, Address offset: 0x6C */
781 uint32_t RESERVED1[37]; /*!< Reserved, 0x70 to 0x100 */
782 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
783 uint32_t RESERVED2; /*!< Reserved, 0x108 */
784 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
785 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
786 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
787 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
788 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
789 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
790 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
791 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
792 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
793 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
794 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
795 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
796 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
797 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
798 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
799 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
800 } FLASH_TypeDef;
801
802 /**
803 * @brief Flexible Memory Controller
804 */
805
806 typedef struct
807 {
808 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
809 } FMC_Bank1_TypeDef;
810
811 /**
812 * @brief Flexible Memory Controller Bank1E
813 */
814
815 typedef struct
816 {
817 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
818 } FMC_Bank1E_TypeDef;
819
820 /**
821 * @brief Flexible Memory Controller Bank2
822 */
823
824 typedef struct
825 {
826 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
827 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
828 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
829 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
830 uint32_t RESERVED0; /*!< Reserved, 0x70 */
831 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
832 } FMC_Bank2_TypeDef;
833
834 /**
835 * @brief Flexible Memory Controller Bank3
836 */
837
838 typedef struct
839 {
840 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
841 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
842 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
843 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
844 uint32_t RESERVED; /*!< Reserved, 0x90 */
845 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
846 } FMC_Bank3_TypeDef;
847
848 /**
849 * @brief Flexible Memory Controller Bank5 and 6
850 */
851
852
853 typedef struct
854 {
855 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
856 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
857 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
858 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
859 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
860 } FMC_Bank5_6_TypeDef;
861
862 /**
863 * @brief GFXMMU registers
864 */
865
866 typedef struct
867 {
868 __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
869 __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
870 __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
871 __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */
872 __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
873 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
874 __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
875 __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
876 __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
877 __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
878 uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
879 __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
880 __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
881 __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
882 __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
883 __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
884 For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
885 } GFXMMU_TypeDef;
886 /**
887 * @brief General Purpose I/O
888 */
889
890 typedef struct
891 {
892 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
893 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
894 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
895 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
896 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
897 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
898 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
899 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
900 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
901 } GPIO_TypeDef;
902
903 /**
904 * @brief Operational Amplifier (OPAMP)
905 */
906
907 typedef struct
908 {
909 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
910 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
911 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
912 } OPAMP_TypeDef;
913
914 /**
915 * @brief System configuration controller
916 */
917
918 typedef struct
919 {
920 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
921 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
922 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
923 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
924 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
925 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
926 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
927 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
928
929 } SYSCFG_TypeDef;
930
931 /**
932 * @brief Inter-integrated Circuit Interface
933 */
934
935 typedef struct
936 {
937 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
938 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
939 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
940 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
941 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
942 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
943 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
944 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
945 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
946 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
947 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
948 } I2C_TypeDef;
949
950 /**
951 * @brief Independent WATCHDOG
952 */
953
954 typedef struct
955 {
956 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
957 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
958 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
959 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
960 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
961 } IWDG_TypeDef;
962
963
964 /**
965 * @brief JPEG Codec
966 */
967 typedef struct
968 {
969 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
970 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
971 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
972 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
973 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
974 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
975 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
976 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
977 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
978 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
979 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
980 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
981 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
982 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
983 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
984 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
985 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
986 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
987 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
988 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
989 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
990 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
991 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
992 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
993 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
994 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
995 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
996 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
997 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
998
999 } JPEG_TypeDef;
1000
1001 /**
1002 * @brief LCD-TFT Display Controller
1003 */
1004
1005 typedef struct
1006 {
1007 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1008 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1009 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1010 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1011 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1012 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1013 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1014 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1015 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1016 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1017 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1018 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1019 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1020 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1021 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1022 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1023 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1024 } LTDC_TypeDef;
1025
1026 /**
1027 * @brief LCD-TFT Display layer x Controller
1028 */
1029
1030 typedef struct
1031 {
1032 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1033 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1034 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1035 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1036 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1037 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1038 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1039 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1040 uint32_t RESERVED0[2]; /*!< Reserved */
1041 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1042 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1043 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1044 uint32_t RESERVED1[3]; /*!< Reserved */
1045 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1046
1047 } LTDC_Layer_TypeDef;
1048
1049 /**
1050 * @brief Power Control
1051 */
1052
1053 typedef struct
1054 {
1055 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1056 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1057 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1058 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1059 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1060 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1061 __IO uint32_t SRDCR; /*!< PWR SRD domain control register, Address offset: 0x18 */
1062 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1063 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1064 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1065 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1066 } PWR_TypeDef;
1067
1068 /**
1069 * @brief Reset and Clock Control
1070 */
1071
1072 typedef struct
1073 {
1074 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1075 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1076 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1077 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1078 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1079 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1080 __IO uint32_t CDCFGR1; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1081 __IO uint32_t CDCFGR2; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1082 __IO uint32_t SRDCFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1083 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1084 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1085 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1086 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1087 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1088 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1089 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1090 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1091 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1092 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1093 __IO uint32_t CDCCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1094 __IO uint32_t CDCCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1095 __IO uint32_t CDCCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1096 __IO uint32_t SRDCCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1097 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1098 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1099 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1100 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1101 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1102 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1103 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1104 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1105 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1106 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1107 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1108 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1109 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1110 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1111 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1112 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1113 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1114 uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA0 */
1115 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1116 __IO uint32_t SRDAMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1117 uint32_t RESERVED9; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1118 __IO uint32_t CKGAENR; /*!< AXI Clocks Gating Enable Register, Address offset: 0xB0 */
1119 uint32_t RESERVED10[31]; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1120 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1121 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1122 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1123 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1124 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1125 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1126 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1127 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1128 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1129 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1130 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1131 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1132 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1133 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1134 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1135 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1136 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1137 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1138 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1139 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1140 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1141
1142 } RCC_TypeDef;
1143
1144
1145 /**
1146 * @brief Real-Time Clock
1147 */
1148 typedef struct
1149 {
1150 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1151 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1152 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
1153 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
1154 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1155 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1156 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
1157 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */
1158 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */
1159 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1160 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
1161 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1162 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1163 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1164 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1165 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */
1166 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
1167 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1168 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
1169 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
1170 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
1171 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
1172 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */
1173 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
1174 __IO uint32_t CFGR; /*!< RTC configuration register, Address offset: 0x60 */
1175 } RTC_TypeDef;
1176
1177 /**
1178 * @brief Tamper and backup registers
1179 */
1180 typedef struct
1181 {
1182 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
1183 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
1184 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */
1185 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
1186 __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
1187 __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
1188 __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
1189 uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1C -- 0x28 */
1190 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
1191 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
1192 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
1193 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */
1194 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
1195 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1196 uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x44 -- 0x4C */
1197 __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1198 uint32_t RESERVED4[43]; /*!< Reserved, Address offset: 0x54 -- 0xFC */
1199 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
1200 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
1201 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
1202 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
1203 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
1204 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
1205 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
1206 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
1207 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
1208 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
1209 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
1210 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
1211 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
1212 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
1213 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
1214 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
1215 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
1216 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
1217 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
1218 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
1219 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
1220 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
1221 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
1222 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
1223 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
1224 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
1225 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
1226 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
1227 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
1228 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
1229 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
1230 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
1231 } TAMP_TypeDef;
1232
1233 /**
1234 * @brief Serial Audio Interface
1235 */
1236
1237 typedef struct
1238 {
1239 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1240 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1241 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1242 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1243 } SAI_TypeDef;
1244
1245 typedef struct
1246 {
1247 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1248 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1249 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1250 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1251 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1252 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1253 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1254 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1255 } SAI_Block_TypeDef;
1256
1257 /**
1258 * @brief SPDIF-RX Interface
1259 */
1260
1261 typedef struct
1262 {
1263 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1264 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1265 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1266 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1267 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1268 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1269 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1270 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1271 } SPDIFRX_TypeDef;
1272
1273
1274 /**
1275 * @brief Secure digital input/output Interface
1276 */
1277
1278 typedef struct
1279 {
1280 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1281 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1282 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1283 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1284 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1285 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1286 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1287 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1288 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1289 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1290 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1291 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1292 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1293 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1294 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1295 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1296 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1297 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1298 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1299 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1300 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1301 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1302 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1303 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1304 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1305 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1306 } SDMMC_TypeDef;
1307
1308
1309 /**
1310 * @brief Delay Block DLYB
1311 */
1312
1313 typedef struct
1314 {
1315 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1316 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1317 } DLYB_TypeDef;
1318
1319 /**
1320 * @brief HW Semaphore HSEM
1321 */
1322
1323 typedef struct
1324 {
1325 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1326 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1327 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1328 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1329 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1330 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1331 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1332 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1333 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1334
1335 } HSEM_TypeDef;
1336
1337 typedef struct
1338 {
1339 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1340 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1341 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1342 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1343 } HSEM_Common_TypeDef;
1344
1345 /**
1346 * @brief Serial Peripheral Interface
1347 */
1348
1349 typedef struct
1350 {
1351 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1352 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1353 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1354 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1355 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1356 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1357 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1358 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1359 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1360 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1361 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1362 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1363 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1364 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1365 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1366 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1367 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1368
1369 } SPI_TypeDef;
1370
1371 /**
1372 * @brief DTS
1373 */
1374 typedef struct
1375 {
1376 __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */
1377 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
1378 __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */
1379 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
1380 __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */
1381 __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */
1382 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
1383 __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */
1384 __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */
1385 __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */
1386 __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */
1387 __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */
1388 }
1389 DTS_TypeDef;
1390
1391 /**
1392 * @brief TIM
1393 */
1394
1395 typedef struct
1396 {
1397 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1398 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1399 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1400 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1401 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1402 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1403 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1404 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1405 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1406 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1407 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1408 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1409 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1410 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1411 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1412 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1413 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1414 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1415 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1416 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1417 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1418 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1419 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1420 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1421 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1422 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1423 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1424 } TIM_TypeDef;
1425
1426 /**
1427 * @brief LPTIMIMER
1428 */
1429 typedef struct
1430 {
1431 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1432 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1433 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1434 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1435 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1436 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1437 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1438 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1439 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1440 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1441 } LPTIM_TypeDef;
1442
1443 /**
1444 * @brief Comparator
1445 */
1446 typedef struct
1447 {
1448 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1449 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1450 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1451 } COMPOPT_TypeDef;
1452
1453 typedef struct
1454 {
1455 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1456 } COMP_TypeDef;
1457
1458 typedef struct
1459 {
1460 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1461 } COMP_Common_TypeDef;
1462 /**
1463 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1464 */
1465
1466 typedef struct
1467 {
1468 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1469 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1470 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1471 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1472 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1473 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1474 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1475 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1476 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1477 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1478 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1479 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1480 } USART_TypeDef;
1481
1482 /**
1483 * @brief Single Wire Protocol Master Interface SPWMI
1484 */
1485 typedef struct
1486 {
1487 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1488 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1489 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1490 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1491 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1492 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1493 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1494 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1495 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1496 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1497 } SWPMI_TypeDef;
1498
1499 /**
1500 * @brief Window WATCHDOG
1501 */
1502
1503 typedef struct
1504 {
1505 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1506 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1507 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1508 } WWDG_TypeDef;
1509
1510
1511 /**
1512 * @brief RAM_ECC_Specific_Registers
1513 */
1514 typedef struct
1515 {
1516 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1517 __IO uint32_t SR; /*!< RAMECC monitor status register */
1518 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1519 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1520 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1521 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1522 } RAMECC_MonitorTypeDef;
1523
1524 typedef struct
1525 {
1526 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1527 } RAMECC_TypeDef;
1528 /**
1529 * @}
1530 */
1531
1532
1533
1534 /**
1535 * @brief RNG
1536 */
1537
1538 typedef struct
1539 {
1540 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1541 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1542 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1543 uint32_t RESERVED;
1544 __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
1545 } RNG_TypeDef;
1546
1547 /**
1548 * @brief MDIOS
1549 */
1550
1551 typedef struct
1552 {
1553 __IO uint32_t CR;
1554 __IO uint32_t WRFR;
1555 __IO uint32_t CWRFR;
1556 __IO uint32_t RDFR;
1557 __IO uint32_t CRDFR;
1558 __IO uint32_t SR;
1559 __IO uint32_t CLRFR;
1560 uint32_t RESERVED[57];
1561 __IO uint32_t DINR0;
1562 __IO uint32_t DINR1;
1563 __IO uint32_t DINR2;
1564 __IO uint32_t DINR3;
1565 __IO uint32_t DINR4;
1566 __IO uint32_t DINR5;
1567 __IO uint32_t DINR6;
1568 __IO uint32_t DINR7;
1569 __IO uint32_t DINR8;
1570 __IO uint32_t DINR9;
1571 __IO uint32_t DINR10;
1572 __IO uint32_t DINR11;
1573 __IO uint32_t DINR12;
1574 __IO uint32_t DINR13;
1575 __IO uint32_t DINR14;
1576 __IO uint32_t DINR15;
1577 __IO uint32_t DINR16;
1578 __IO uint32_t DINR17;
1579 __IO uint32_t DINR18;
1580 __IO uint32_t DINR19;
1581 __IO uint32_t DINR20;
1582 __IO uint32_t DINR21;
1583 __IO uint32_t DINR22;
1584 __IO uint32_t DINR23;
1585 __IO uint32_t DINR24;
1586 __IO uint32_t DINR25;
1587 __IO uint32_t DINR26;
1588 __IO uint32_t DINR27;
1589 __IO uint32_t DINR28;
1590 __IO uint32_t DINR29;
1591 __IO uint32_t DINR30;
1592 __IO uint32_t DINR31;
1593 __IO uint32_t DOUTR0;
1594 __IO uint32_t DOUTR1;
1595 __IO uint32_t DOUTR2;
1596 __IO uint32_t DOUTR3;
1597 __IO uint32_t DOUTR4;
1598 __IO uint32_t DOUTR5;
1599 __IO uint32_t DOUTR6;
1600 __IO uint32_t DOUTR7;
1601 __IO uint32_t DOUTR8;
1602 __IO uint32_t DOUTR9;
1603 __IO uint32_t DOUTR10;
1604 __IO uint32_t DOUTR11;
1605 __IO uint32_t DOUTR12;
1606 __IO uint32_t DOUTR13;
1607 __IO uint32_t DOUTR14;
1608 __IO uint32_t DOUTR15;
1609 __IO uint32_t DOUTR16;
1610 __IO uint32_t DOUTR17;
1611 __IO uint32_t DOUTR18;
1612 __IO uint32_t DOUTR19;
1613 __IO uint32_t DOUTR20;
1614 __IO uint32_t DOUTR21;
1615 __IO uint32_t DOUTR22;
1616 __IO uint32_t DOUTR23;
1617 __IO uint32_t DOUTR24;
1618 __IO uint32_t DOUTR25;
1619 __IO uint32_t DOUTR26;
1620 __IO uint32_t DOUTR27;
1621 __IO uint32_t DOUTR28;
1622 __IO uint32_t DOUTR29;
1623 __IO uint32_t DOUTR30;
1624 __IO uint32_t DOUTR31;
1625 } MDIOS_TypeDef;
1626
1627
1628 /**
1629 * @brief USB_OTG_Core_Registers
1630 */
1631 typedef struct
1632 {
1633 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1634 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1635 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1636 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1637 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1638 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1639 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1640 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1641 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1642 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1643 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1644 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1645 uint32_t Reserved30[2]; /*!< Reserved 030h */
1646 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1647 __IO uint32_t CID; /*!< User ID Register 03Ch */
1648 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1649 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1650 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1651 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1652 uint32_t Reserved6; /*!< Reserved 050h */
1653 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1654 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1655 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1656 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1657 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1658 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1659 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1660 } USB_OTG_GlobalTypeDef;
1661
1662
1663 /**
1664 * @brief USB_OTG_device_Registers
1665 */
1666 typedef struct
1667 {
1668 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1669 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1670 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1671 uint32_t Reserved0C; /*!< Reserved 80Ch */
1672 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1673 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1674 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1675 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1676 uint32_t Reserved20; /*!< Reserved 820h */
1677 uint32_t Reserved9; /*!< Reserved 824h */
1678 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1679 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1680 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1681 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1682 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1683 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1684 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1685 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1686 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1687 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1688 } USB_OTG_DeviceTypeDef;
1689
1690
1691 /**
1692 * @brief USB_OTG_IN_Endpoint-Specific_Register
1693 */
1694 typedef struct
1695 {
1696 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1697 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1698 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1699 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1700 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1701 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1702 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1703 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1704 } USB_OTG_INEndpointTypeDef;
1705
1706
1707 /**
1708 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1709 */
1710 typedef struct
1711 {
1712 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1713 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1714 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1715 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1716 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1717 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1718 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1719 } USB_OTG_OUTEndpointTypeDef;
1720
1721
1722 /**
1723 * @brief USB_OTG_Host_Mode_Register_Structures
1724 */
1725 typedef struct
1726 {
1727 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1728 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1729 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1730 uint32_t Reserved40C; /*!< Reserved 40Ch */
1731 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1732 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1733 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1734 } USB_OTG_HostTypeDef;
1735
1736 /**
1737 * @brief USB_OTG_Host_Channel_Specific_Registers
1738 */
1739 typedef struct
1740 {
1741 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1742 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1743 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1744 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1745 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1746 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1747 uint32_t Reserved[2]; /*!< Reserved */
1748 } USB_OTG_HostChannelTypeDef;
1749 /**
1750 * @}
1751 */
1752
1753 /**
1754 * @brief OCTO Serial Peripheral Interface
1755 */
1756
1757 typedef struct
1758 {
1759 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
1760 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
1761 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
1762 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
1763 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
1764 __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
1765 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1766 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
1767 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
1768 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1769 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
1770 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
1771 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
1772 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
1773 __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */
1774 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1775 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
1776 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
1777 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
1778 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
1779 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
1780 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1781 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
1782 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
1783 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
1784 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
1785 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
1786 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1787 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
1788 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1789 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
1790 uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1791 __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
1792 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
1793 __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
1794 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
1795 __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
1796 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
1797 __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
1798 uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
1799 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
1800 uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
1801 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
1802 uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
1803 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
1804 uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
1805 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
1806 uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
1807 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
1808 uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */
1809 __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */
1810 __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
1811 __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */
1812 __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */
1813 } OCTOSPI_TypeDef;
1814
1815 /**
1816 * @}
1817 */
1818 /**
1819 * @brief OCTO Serial Peripheral Interface IO Manager
1820 */
1821
1822 typedef struct
1823 {
1824 __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
1825 __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
1826 } OCTOSPIM_TypeDef;
1827
1828 /**
1829 * @}
1830 */
1831
1832 /** @addtogroup Peripheral_memory_map
1833 * @{
1834 */
1835 #define CD_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1836 #define CD_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM */
1837 #define CD_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1838
1839 #define CD_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI */
1840 #define CD_AXISRAM2_BASE (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI */
1841 #define CD_AXISRAM3_BASE (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI */
1842 #define CD_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge */
1843 #define CD_AHBSRAM2_BASE (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge */
1844
1845 #define SRD_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1846 #define SRD_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge */
1847
1848 #define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */
1849 #define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */
1850
1851 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 1 MB) Flash Bank1 accessible over AXI */
1852 #define FLASH_BANK2_BASE (0x08100000UL) /*!< Base address of : (up to 1 MB) Flash Bank2 accessible over AXI */
1853 #define FLASH_END (0x081FFFFFUL) /*!< FLASH end address */
1854
1855 /* Legacy define */
1856 #define FLASH_BASE FLASH_BANK1_BASE
1857 #define D1_AXISRAM_BASE CD_AXISRAM1_BASE
1858
1859 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1860 #define FLASH_OTP_END (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1861
1862
1863 /*!< Device electronic signature memory map */
1864 #define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
1865 #define FLASHSIZE_BASE (0x08FFF80CUL) /*!< FLASH Size register base address */
1866 #define PACKAGE_BASE (0x08FFF80EUL) /*!< Package Data register base address */
1867
1868 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals */
1869 /*!< Peripheral memory map */
1870 #define CD_APB1PERIPH_BASE PERIPH_BASE /*!< D2_APB1PERIPH_BASE PERIPH_BASE */
1871 #define CD_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) /*!< D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) */
1872 #define CD_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) /*!< D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) */
1873 #define CD_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) /*!< D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) */
1874
1875 #define CD_APB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) /*!< D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) */
1876 #define CD_AHB3PERIPH_BASE (PERIPH_BASE + 0x12000000UL) /*!< D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) */
1877
1878 #define SRD_APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) /*!< D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) */
1879 #define SRD_AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) /*!< D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) */
1880
1881 /*!< Legacy Peripheral memory map */
1882 #define APB1PERIPH_BASE PERIPH_BASE
1883 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1884 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1885 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
1886
1887 /*!< CD_AHB3PERIPH peripherals */
1888 #define MDMA_BASE (CD_AHB3PERIPH_BASE + 0x0000UL)
1889 #define DMA2D_BASE (CD_AHB3PERIPH_BASE + 0x1000UL)
1890 #define FLASH_R_BASE (CD_AHB3PERIPH_BASE + 0x2000UL)
1891 #define JPGDEC_BASE (CD_AHB3PERIPH_BASE + 0x3000UL)
1892 #define FMC_R_BASE (CD_AHB3PERIPH_BASE + 0x4000UL)
1893 #define OCTOSPI1_R_BASE (CD_AHB3PERIPH_BASE + 0x5000UL)
1894 #define DLYB_OCTOSPI1_BASE (CD_AHB3PERIPH_BASE + 0x6000UL)
1895 #define SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x7000UL)
1896 #define DLYB_SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x8000UL)
1897 #define RAMECC_BASE (CD_AHB3PERIPH_BASE + 0x9000UL)
1898 #define OCTOSPI2_R_BASE (CD_AHB3PERIPH_BASE + 0xA000UL)
1899 #define DLYB_OCTOSPI2_BASE (CD_AHB3PERIPH_BASE + 0xB000UL)
1900 #define OCTOSPIM_BASE (CD_AHB3PERIPH_BASE + 0xB400UL)
1901
1902 /*!< CD_AHB1PERIPH peripherals */
1903
1904 #define DMA1_BASE (CD_AHB1PERIPH_BASE + 0x0000UL)
1905 #define DMA2_BASE (CD_AHB1PERIPH_BASE + 0x0400UL)
1906 #define DMAMUX1_BASE (CD_AHB1PERIPH_BASE + 0x0800UL)
1907 #define ADC1_BASE (CD_AHB1PERIPH_BASE + 0x2000UL)
1908 #define ADC2_BASE (CD_AHB1PERIPH_BASE + 0x2100UL)
1909 #define ADC12_COMMON_BASE (CD_AHB1PERIPH_BASE + 0x2300UL)
1910 #define CRC_BASE (CD_AHB1PERIPH_BASE + 0x3000UL)
1911
1912 /*!< USB registers base address */
1913 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
1914 #define USB_OTG_GLOBAL_BASE (0x000UL)
1915 #define USB_OTG_DEVICE_BASE (0x800UL)
1916 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
1917 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
1918 #define USB_OTG_EP_REG_SIZE (0x20UL)
1919 #define USB_OTG_HOST_BASE (0x400UL)
1920 #define USB_OTG_HOST_PORT_BASE (0x440UL)
1921 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
1922 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
1923 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
1924 #define USB_OTG_FIFO_BASE (0x1000UL)
1925 #define USB_OTG_FIFO_SIZE (0x1000UL)
1926
1927 /*!< CD_AHB2PERIPH peripherals */
1928
1929 #define DCMI_BASE (CD_AHB2PERIPH_BASE + 0x0000UL)
1930 #define PSSI_BASE (CD_AHB2PERIPH_BASE + 0x0400UL)
1931 #define HSEM_BASE (CD_AHB2PERIPH_BASE + 0x0800UL)
1932 #define RNG_BASE (CD_AHB2PERIPH_BASE + 0x1800UL)
1933 #define SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2400UL)
1934 #define DLYB_SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2800UL)
1935 #define BDMA1_BASE (CD_AHB2PERIPH_BASE + 0x2C00UL)
1936
1937 /*!< SRD_AHB4PERIPH peripherals */
1938 #define GPIOA_BASE (SRD_AHB4PERIPH_BASE + 0x0000UL)
1939 #define GPIOB_BASE (SRD_AHB4PERIPH_BASE + 0x0400UL)
1940 #define GPIOC_BASE (SRD_AHB4PERIPH_BASE + 0x0800UL)
1941 #define GPIOD_BASE (SRD_AHB4PERIPH_BASE + 0x0C00UL)
1942 #define GPIOE_BASE (SRD_AHB4PERIPH_BASE + 0x1000UL)
1943 #define GPIOF_BASE (SRD_AHB4PERIPH_BASE + 0x1400UL)
1944 #define GPIOG_BASE (SRD_AHB4PERIPH_BASE + 0x1800UL)
1945 #define GPIOH_BASE (SRD_AHB4PERIPH_BASE + 0x1C00UL)
1946 #define GPIOI_BASE (SRD_AHB4PERIPH_BASE + 0x2000UL)
1947 #define GPIOJ_BASE (SRD_AHB4PERIPH_BASE + 0x2400UL)
1948 #define GPIOK_BASE (SRD_AHB4PERIPH_BASE + 0x2800UL)
1949 #define RCC_BASE (SRD_AHB4PERIPH_BASE + 0x4400UL)
1950 #define PWR_BASE (SRD_AHB4PERIPH_BASE + 0x4800UL)
1951 #define BDMA2_BASE (SRD_AHB4PERIPH_BASE + 0x5400UL)
1952 #define DMAMUX2_BASE (SRD_AHB4PERIPH_BASE + 0x5800UL)
1953
1954 /*!< CD_APB3PERIPH peripherals */
1955 #define LTDC_BASE (CD_APB3PERIPH_BASE + 0x1000UL)
1956 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
1957 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
1958 #define WWDG1_BASE (CD_APB3PERIPH_BASE + 0x3000UL)
1959
1960 /*!< CD_APB1PERIPH peripherals */
1961 #define TIM2_BASE (CD_APB1PERIPH_BASE + 0x0000UL)
1962 #define TIM3_BASE (CD_APB1PERIPH_BASE + 0x0400UL)
1963 #define TIM4_BASE (CD_APB1PERIPH_BASE + 0x0800UL)
1964 #define TIM5_BASE (CD_APB1PERIPH_BASE + 0x0C00UL)
1965 #define TIM6_BASE (CD_APB1PERIPH_BASE + 0x1000UL)
1966 #define TIM7_BASE (CD_APB1PERIPH_BASE + 0x1400UL)
1967 #define TIM12_BASE (CD_APB1PERIPH_BASE + 0x1800UL)
1968 #define TIM13_BASE (CD_APB1PERIPH_BASE + 0x1C00UL)
1969 #define TIM14_BASE (CD_APB1PERIPH_BASE + 0x2000UL)
1970 #define LPTIM1_BASE (CD_APB1PERIPH_BASE + 0x2400UL)
1971
1972 #define SPI2_BASE (CD_APB1PERIPH_BASE + 0x3800UL)
1973 #define SPI3_BASE (CD_APB1PERIPH_BASE + 0x3C00UL)
1974 #define SPDIFRX_BASE (CD_APB1PERIPH_BASE + 0x4000UL)
1975 #define USART2_BASE (CD_APB1PERIPH_BASE + 0x4400UL)
1976 #define USART3_BASE (CD_APB1PERIPH_BASE + 0x4800UL)
1977 #define UART4_BASE (CD_APB1PERIPH_BASE + 0x4C00UL)
1978 #define UART5_BASE (CD_APB1PERIPH_BASE + 0x5000UL)
1979 #define I2C1_BASE (CD_APB1PERIPH_BASE + 0x5400UL)
1980 #define I2C2_BASE (CD_APB1PERIPH_BASE + 0x5800UL)
1981 #define I2C3_BASE (CD_APB1PERIPH_BASE + 0x5C00UL)
1982 #define CEC_BASE (CD_APB1PERIPH_BASE + 0x6C00UL)
1983 #define DAC1_BASE (CD_APB1PERIPH_BASE + 0x7400UL)
1984 #define UART7_BASE (CD_APB1PERIPH_BASE + 0x7800UL)
1985 #define UART8_BASE (CD_APB1PERIPH_BASE + 0x7C00UL)
1986 #define CRS_BASE (CD_APB1PERIPH_BASE + 0x8400UL)
1987 #define SWPMI1_BASE (CD_APB1PERIPH_BASE + 0x8800UL)
1988 #define OPAMP_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
1989 #define OPAMP1_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
1990 #define OPAMP2_BASE (CD_APB1PERIPH_BASE + 0x9010UL)
1991 #define MDIOS_BASE (CD_APB1PERIPH_BASE + 0x9400UL)
1992 #define FDCAN1_BASE (CD_APB1PERIPH_BASE + 0xA000UL)
1993 #define FDCAN2_BASE (CD_APB1PERIPH_BASE + 0xA400UL)
1994 #define FDCAN_CCU_BASE (CD_APB1PERIPH_BASE + 0xA800UL)
1995 #define SRAMCAN_BASE (CD_APB1PERIPH_BASE + 0xAC00UL)
1996
1997 /*!< CD_APB2PERIPH peripherals */
1998
1999 #define TIM1_BASE (CD_APB2PERIPH_BASE + 0x0000UL)
2000 #define TIM8_BASE (CD_APB2PERIPH_BASE + 0x0400UL)
2001 #define USART1_BASE (CD_APB2PERIPH_BASE + 0x1000UL)
2002 #define USART6_BASE (CD_APB2PERIPH_BASE + 0x1400UL)
2003 #define UART9_BASE (CD_APB2PERIPH_BASE + 0x1800UL)
2004 #define USART10_BASE (CD_APB2PERIPH_BASE + 0x1C00UL)
2005 #define SPI1_BASE (CD_APB2PERIPH_BASE + 0x3000UL)
2006 #define SPI4_BASE (CD_APB2PERIPH_BASE + 0x3400UL)
2007 #define TIM15_BASE (CD_APB2PERIPH_BASE + 0x4000UL)
2008 #define TIM16_BASE (CD_APB2PERIPH_BASE + 0x4400UL)
2009 #define TIM17_BASE (CD_APB2PERIPH_BASE + 0x4800UL)
2010 #define SPI5_BASE (CD_APB2PERIPH_BASE + 0x5000UL)
2011 #define SAI1_BASE (CD_APB2PERIPH_BASE + 0x5800UL)
2012 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2013 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2014 #define SAI2_BASE (CD_APB2PERIPH_BASE + 0x5C00UL)
2015 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2016 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2017 #define DFSDM1_BASE (CD_APB2PERIPH_BASE + 0x7800UL)
2018 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2019 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2020 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2021 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2022 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2023 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2024 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2025 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2026 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2027 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2028 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2029 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2030 #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300UL)
2031 #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380UL)
2032 #define DFSDM1_Filter6_BASE (DFSDM1_BASE + 0x400UL)
2033 #define DFSDM1_Filter7_BASE (DFSDM1_BASE + 0x480UL)
2034 /*!< SRD_APB4PERIPH peripherals */
2035 #define EXTI_BASE (SRD_APB4PERIPH_BASE + 0x0000UL)
2036 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2037 #define SYSCFG_BASE (SRD_APB4PERIPH_BASE + 0x0400UL)
2038 #define LPUART1_BASE (SRD_APB4PERIPH_BASE + 0x0C00UL)
2039 #define SPI6_BASE (SRD_APB4PERIPH_BASE + 0x1400UL)
2040 #define I2C4_BASE (SRD_APB4PERIPH_BASE + 0x1C00UL)
2041 #define LPTIM2_BASE (SRD_APB4PERIPH_BASE + 0x2400UL)
2042 #define LPTIM3_BASE (SRD_APB4PERIPH_BASE + 0x2800UL)
2043 #define DAC2_BASE (SRD_APB4PERIPH_BASE + 0x3400UL)
2044 #define COMP12_BASE (SRD_APB4PERIPH_BASE + 0x3800UL)
2045 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
2046 #define COMP2_BASE (COMP12_BASE + 0x10UL)
2047 #define VREFBUF_BASE (SRD_APB4PERIPH_BASE + 0x3C00UL)
2048 #define RTC_BASE (SRD_APB4PERIPH_BASE + 0x4000UL)
2049 #define TAMP_BASE (SRD_APB4PERIPH_BASE + 0x4400UL)
2050 #define IWDG1_BASE (SRD_APB4PERIPH_BASE + 0x4800UL)
2051
2052 #define DTS_BASE (SRD_APB4PERIPH_BASE + 0x6800UL)
2053
2054 #define DFSDM2_BASE (SRD_APB4PERIPH_BASE + 0x6C00UL)
2055 #define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
2056 #define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
2057 #define DFSDM2_FLT0_BASE (DFSDM2_BASE + 0x100UL)
2058
2059 /*!< CD_AHB3PERIPH peripherals */
2060 #define GFXMMU_BASE (CD_AHB3PERIPH_BASE + 0xC000UL)
2061
2062 #define BDMA1_Channel0_BASE (BDMA1_BASE + 0x0008UL)
2063 #define BDMA1_Channel1_BASE (BDMA1_BASE + 0x001CUL)
2064 #define BDMA1_Channel2_BASE (BDMA1_BASE + 0x0030UL)
2065 #define BDMA1_Channel3_BASE (BDMA1_BASE + 0x0044UL)
2066 #define BDMA1_Channel4_BASE (BDMA1_BASE + 0x0058UL)
2067 #define BDMA1_Channel5_BASE (BDMA1_BASE + 0x006CUL)
2068 #define BDMA1_Channel6_BASE (BDMA1_BASE + 0x0080UL)
2069 #define BDMA1_Channel7_BASE (BDMA1_BASE + 0x0094UL)
2070
2071 #define BDMA2_Channel0_BASE (BDMA2_BASE + 0x0008UL)
2072 #define BDMA2_Channel1_BASE (BDMA2_BASE + 0x001CUL)
2073 #define BDMA2_Channel2_BASE (BDMA2_BASE + 0x0030UL)
2074 #define BDMA2_Channel3_BASE (BDMA2_BASE + 0x0044UL)
2075 #define BDMA2_Channel4_BASE (BDMA2_BASE + 0x0058UL)
2076 #define BDMA2_Channel5_BASE (BDMA2_BASE + 0x006CUL)
2077 #define BDMA2_Channel6_BASE (BDMA2_BASE + 0x0080UL)
2078 #define BDMA2_Channel7_BASE (BDMA2_BASE + 0x0094UL)
2079
2080
2081 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2082 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2083 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2084 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2085 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2086 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2087 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2088 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2089
2090 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2091 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2092 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2093 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2094 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2095 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2096 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2097 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2098
2099 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2100 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2101
2102 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2103 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2104 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2105 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2106 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2107 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2108 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2109 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2110
2111 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2112 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2113 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2114 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2115 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2116 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2117 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2118 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2119
2120
2121 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2122 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2123 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2124 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2125 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2126 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2127 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2128 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2129 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2130 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2131 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2132 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2133 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2134 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2135 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2136 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2137
2138 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2139 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2140 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2141 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2142 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2143 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2144 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2145 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2146
2147 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2148 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2149
2150 /*!< FMC Banks registers base address */
2151 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2152 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2153 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2154 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2155 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2156
2157 /* Debug MCU registers base address */
2158 #define DBGMCU_BASE (0x5C001000UL)
2159
2160 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2161 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2162 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2163 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2164 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2165 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2166 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2167 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2168 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2169 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2170 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2171 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2172 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2173 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2174 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2175 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2176 #define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
2177
2178 /* GFXMMU virtual buffers base address */
2179 #define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
2180 #define GFXMMU_VIRTUAL_BUFFER0_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE)
2181 #define GFXMMU_VIRTUAL_BUFFER1_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2182 #define GFXMMU_VIRTUAL_BUFFER2_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2183 #define GFXMMU_VIRTUAL_BUFFER3_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2184
2185 #define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2186 #define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2187 #define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2188
2189 /**
2190 * @}
2191 */
2192
2193 /** @addtogroup Peripheral_declaration
2194 * @{
2195 */
2196 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2197 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2198 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2199 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2200 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2201 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2202 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2203 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2204 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2205 #define RTC ((RTC_TypeDef *) RTC_BASE)
2206 #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
2207 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2208
2209
2210 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2211 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2212 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2213 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2214 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2215 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2216 #define USART2 ((USART_TypeDef *) USART2_BASE)
2217 #define USART3 ((USART_TypeDef *) USART3_BASE)
2218 #define USART6 ((USART_TypeDef *) USART6_BASE)
2219 #define USART10 ((USART_TypeDef *) USART10_BASE)
2220 #define UART7 ((USART_TypeDef *) UART7_BASE)
2221 #define UART8 ((USART_TypeDef *) UART8_BASE)
2222 #define UART9 ((USART_TypeDef *) UART9_BASE)
2223 #define CRS ((CRS_TypeDef *) CRS_BASE)
2224 #define UART4 ((USART_TypeDef *) UART4_BASE)
2225 #define UART5 ((USART_TypeDef *) UART5_BASE)
2226 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2227 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2228 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2229 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2230 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2231 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2232 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2233 #define CEC ((CEC_TypeDef *) CEC_BASE)
2234 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2235 #define PWR ((PWR_TypeDef *) PWR_BASE)
2236 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2237 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2238 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2239 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2240 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2241 #define DTS ((DTS_TypeDef *) DTS_BASE)
2242
2243 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2244 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2245 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2246 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2247 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2248 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2249 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2250 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2251
2252
2253 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2254 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2255 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2256 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2257 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2258 #define USART1 ((USART_TypeDef *) USART1_BASE)
2259 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2260 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2261 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2262 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2263 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2264 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2265 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2266 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2267 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2268 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2269
2270 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2271 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2272 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2273 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2274 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2275 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2276 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2277 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2278 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2279 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2280 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2281 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2282 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2283 #define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2284 #define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2285 #define DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2286 #define DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2287 #define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2288 #define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2289 #define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2290 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2291 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2292 #define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2293 #define RCC ((RCC_TypeDef *) RCC_BASE)
2294 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2295 #define CRC ((CRC_TypeDef *) CRC_BASE)
2296
2297 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2298 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2299 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2300 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2301 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2302 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2303 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2304 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2305 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2306 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2307 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2308
2309 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2310 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2311 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2312
2313 #define RNG ((RNG_TypeDef *) RNG_BASE)
2314 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2315 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2316
2317 #define BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)
2318 #define BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2319 #define BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2320 #define BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2321 #define BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2322 #define BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2323 #define BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2324 #define BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2325 #define BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2326
2327 #define BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)
2328 #define BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2329 #define BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2330 #define BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2331 #define BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2332 #define BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2333 #define BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2334 #define BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2335 #define BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2336
2337 #define RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)
2338 #define RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2339 #define RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2340 #define RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2341
2342 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2343 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2344 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2345 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2346 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2347 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2348 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2349 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2350 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2351
2352
2353 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2354 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2355 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2356 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2357 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2358 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2359 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2360 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2361
2362 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2363 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2364
2365 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2366 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2367 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2368 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2369 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2370 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2371 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2372 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2373 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2374
2375 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2376 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2377 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2378 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2379 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2380 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2381 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2382 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2383 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2384
2385
2386 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2387 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2388 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2389 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2390 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2391 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2392 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2393 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2394 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2395 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2396 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2397 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2398 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2399 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2400 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2401 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2402 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2403
2404 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2405 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2406 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2407 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2408 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2409 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2410 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2411 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2412
2413 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2414 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2415
2416
2417 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2418 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2419 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2420 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2421 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2422
2423 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
2424 #define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2425 #define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2426 #define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2427 #define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2428 #define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2429 #define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
2430
2431 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2432 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2433
2434 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2435
2436 #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2437 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2438 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2439
2440 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2441 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2442 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2443
2444 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2445
2446 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2447 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2448 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2449 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2450 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2451 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2452 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2453 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2454 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2455 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2456 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2457 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2458 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2459 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2460 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2461 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2462 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2463
2464
2465 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2466
2467 /* Legacy defines */
2468 #define USB_OTG_HS USB1_OTG_HS
2469 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2470
2471 /**
2472 * @}
2473 */
2474
2475 /** @addtogroup Exported_constants
2476 * @{
2477 */
2478
2479 /** @addtogroup Peripheral_Registers_Bits_Definition
2480 * @{
2481 */
2482
2483 /******************************************************************************/
2484 /* Peripheral Registers_Bits_Definition */
2485 /******************************************************************************/
2486
2487 /******************************************************************************/
2488 /* */
2489 /* Analog to Digital Converter */
2490 /* */
2491 /******************************************************************************/
2492 /******************************* ADC VERSION ********************************/
2493 #define ADC_VER_V5_3
2494 /******************** Bit definition for ADC_ISR register ********************/
2495 #define ADC_ISR_ADRDY_Pos (0U)
2496 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2497 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2498 #define ADC_ISR_EOSMP_Pos (1U)
2499 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2500 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2501 #define ADC_ISR_EOC_Pos (2U)
2502 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2503 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2504 #define ADC_ISR_EOS_Pos (3U)
2505 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2506 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2507 #define ADC_ISR_OVR_Pos (4U)
2508 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2509 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2510 #define ADC_ISR_JEOC_Pos (5U)
2511 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2512 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2513 #define ADC_ISR_JEOS_Pos (6U)
2514 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2515 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2516 #define ADC_ISR_AWD1_Pos (7U)
2517 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2518 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2519 #define ADC_ISR_AWD2_Pos (8U)
2520 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2521 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2522 #define ADC_ISR_AWD3_Pos (9U)
2523 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2524 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2525 #define ADC_ISR_JQOVF_Pos (10U)
2526 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2527 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2528
2529 /******************** Bit definition for ADC_IER register ********************/
2530 #define ADC_IER_ADRDYIE_Pos (0U)
2531 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2532 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2533 #define ADC_IER_EOSMPIE_Pos (1U)
2534 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2535 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2536 #define ADC_IER_EOCIE_Pos (2U)
2537 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2538 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2539 #define ADC_IER_EOSIE_Pos (3U)
2540 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2541 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2542 #define ADC_IER_OVRIE_Pos (4U)
2543 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2544 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2545 #define ADC_IER_JEOCIE_Pos (5U)
2546 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2547 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2548 #define ADC_IER_JEOSIE_Pos (6U)
2549 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2550 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2551 #define ADC_IER_AWD1IE_Pos (7U)
2552 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2553 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2554 #define ADC_IER_AWD2IE_Pos (8U)
2555 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2556 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2557 #define ADC_IER_AWD3IE_Pos (9U)
2558 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2559 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2560 #define ADC_IER_JQOVFIE_Pos (10U)
2561 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2562 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2563
2564 /******************** Bit definition for ADC_CR register ********************/
2565 #define ADC_CR_ADEN_Pos (0U)
2566 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2567 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2568 #define ADC_CR_ADDIS_Pos (1U)
2569 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2570 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2571 #define ADC_CR_ADSTART_Pos (2U)
2572 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2573 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2574 #define ADC_CR_JADSTART_Pos (3U)
2575 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2576 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2577 #define ADC_CR_ADSTP_Pos (4U)
2578 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2579 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2580 #define ADC_CR_JADSTP_Pos (5U)
2581 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2582 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2583 #define ADC_CR_BOOST_Pos (8U)
2584 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2585 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2586 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2587 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2588 #define ADC_CR_ADCALLIN_Pos (16U)
2589 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2590 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2591 #define ADC_CR_LINCALRDYW1_Pos (22U)
2592 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2593 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2594 #define ADC_CR_LINCALRDYW2_Pos (23U)
2595 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2596 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2597 #define ADC_CR_LINCALRDYW3_Pos (24U)
2598 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2599 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2600 #define ADC_CR_LINCALRDYW4_Pos (25U)
2601 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2602 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2603 #define ADC_CR_LINCALRDYW5_Pos (26U)
2604 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2605 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2606 #define ADC_CR_LINCALRDYW6_Pos (27U)
2607 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2608 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2609 #define ADC_CR_ADVREGEN_Pos (28U)
2610 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2611 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2612 #define ADC_CR_DEEPPWD_Pos (29U)
2613 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2614 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2615 #define ADC_CR_ADCALDIF_Pos (30U)
2616 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2617 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2618 #define ADC_CR_ADCAL_Pos (31U)
2619 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2620 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2621
2622 /******************** Bit definition for ADC_CFGR register ********************/
2623 #define ADC_CFGR_DMNGT_Pos (0U)
2624 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2625 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2626 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2627 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2628
2629 #define ADC_CFGR_RES_Pos (2U)
2630 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2631 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2632 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2633 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2634 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2635
2636 #define ADC_CFGR_EXTSEL_Pos (5U)
2637 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2638 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2639 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2640 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2641 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2642 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2643 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2644
2645 #define ADC_CFGR_EXTEN_Pos (10U)
2646 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2647 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2648 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2649 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2650
2651 #define ADC_CFGR_OVRMOD_Pos (12U)
2652 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2653 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2654 #define ADC_CFGR_CONT_Pos (13U)
2655 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2656 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2657 #define ADC_CFGR_AUTDLY_Pos (14U)
2658 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2659 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2660
2661 #define ADC_CFGR_DISCEN_Pos (16U)
2662 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2663 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2664
2665 #define ADC_CFGR_DISCNUM_Pos (17U)
2666 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2667 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2668 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2669 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2670 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2671
2672 #define ADC_CFGR_JDISCEN_Pos (20U)
2673 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2674 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2675 #define ADC_CFGR_JQM_Pos (21U)
2676 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2677 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2678 #define ADC_CFGR_AWD1SGL_Pos (22U)
2679 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2680 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2681 #define ADC_CFGR_AWD1EN_Pos (23U)
2682 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2683 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2684 #define ADC_CFGR_JAWD1EN_Pos (24U)
2685 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2686 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2687 #define ADC_CFGR_JAUTO_Pos (25U)
2688 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2689 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2690
2691 #define ADC_CFGR_AWD1CH_Pos (26U)
2692 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2693 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2694 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2695 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2696 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2697 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2698 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2699
2700 #define ADC_CFGR_JQDIS_Pos (31U)
2701 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2702 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2703
2704 /******************** Bit definition for ADC_CFGR2 register ********************/
2705 #define ADC_CFGR2_ROVSE_Pos (0U)
2706 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2707 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2708 #define ADC_CFGR2_JOVSE_Pos (1U)
2709 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2710 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2711
2712 #define ADC_CFGR2_OVSS_Pos (5U)
2713 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2714 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2715 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2716 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2717 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2718 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2719
2720 #define ADC_CFGR2_TROVS_Pos (9U)
2721 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2722 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2723 #define ADC_CFGR2_ROVSM_Pos (10U)
2724 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2725 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2726
2727 #define ADC_CFGR2_RSHIFT1_Pos (11U)
2728 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2729 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2730 #define ADC_CFGR2_RSHIFT2_Pos (12U)
2731 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2732 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2733 #define ADC_CFGR2_RSHIFT3_Pos (13U)
2734 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2735 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2736 #define ADC_CFGR2_RSHIFT4_Pos (14U)
2737 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2738 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2739
2740 #define ADC_CFGR2_OVSR_Pos (16U)
2741 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2742 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2743 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2744 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2745 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2746 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2747 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2748 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2749 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2750 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2751 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2752 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2753
2754 #define ADC_CFGR2_LSHIFT_Pos (28U)
2755 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2756 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2757 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2758 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2759 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2760 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2761
2762 /******************** Bit definition for ADC_SMPR1 register ********************/
2763 #define ADC_SMPR1_SMP0_Pos (0U)
2764 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2765 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2766 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2767 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2768 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2769
2770 #define ADC_SMPR1_SMP1_Pos (3U)
2771 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2772 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2773 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2774 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2775 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2776
2777 #define ADC_SMPR1_SMP2_Pos (6U)
2778 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2779 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2780 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2781 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2782 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2783
2784 #define ADC_SMPR1_SMP3_Pos (9U)
2785 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2786 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2787 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2788 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2789 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2790
2791 #define ADC_SMPR1_SMP4_Pos (12U)
2792 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2793 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2794 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2795 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2796 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2797
2798 #define ADC_SMPR1_SMP5_Pos (15U)
2799 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2800 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2801 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2802 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2803 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2804
2805 #define ADC_SMPR1_SMP6_Pos (18U)
2806 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2807 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2808 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2809 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2810 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2811
2812 #define ADC_SMPR1_SMP7_Pos (21U)
2813 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2814 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2815 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2816 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2817 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2818
2819 #define ADC_SMPR1_SMP8_Pos (24U)
2820 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2821 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2822 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2823 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2824 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2825
2826 #define ADC_SMPR1_SMP9_Pos (27U)
2827 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2828 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2829 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2830 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2831 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2832
2833 /******************** Bit definition for ADC_SMPR2 register ********************/
2834 #define ADC_SMPR2_SMP10_Pos (0U)
2835 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2836 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2837 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2838 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2839 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2840
2841 #define ADC_SMPR2_SMP11_Pos (3U)
2842 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2843 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2844 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2845 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2846 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2847
2848 #define ADC_SMPR2_SMP12_Pos (6U)
2849 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2850 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2851 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2852 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2853 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2854
2855 #define ADC_SMPR2_SMP13_Pos (9U)
2856 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2857 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2858 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2859 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2860 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2861
2862 #define ADC_SMPR2_SMP14_Pos (12U)
2863 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2864 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
2865 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
2866 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
2867 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
2868
2869 #define ADC_SMPR2_SMP15_Pos (15U)
2870 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
2871 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
2872 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
2873 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
2874 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
2875
2876 #define ADC_SMPR2_SMP16_Pos (18U)
2877 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
2878 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
2879 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
2880 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
2881 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
2882
2883 #define ADC_SMPR2_SMP17_Pos (21U)
2884 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
2885 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
2886 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
2887 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
2888 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
2889
2890 #define ADC_SMPR2_SMP18_Pos (24U)
2891 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
2892 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
2893 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
2894 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
2895 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
2896
2897 #define ADC_SMPR2_SMP19_Pos (27U)
2898 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
2899 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
2900 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
2901 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
2902 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
2903
2904 /******************** Bit definition for ADC_PCSEL register ********************/
2905 #define ADC_PCSEL_PCSEL_Pos (0U)
2906 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
2907 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
2908 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
2909 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
2910 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
2911 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
2912 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
2913 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
2914 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
2915 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
2916 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
2917 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
2918 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
2919 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
2920 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
2921 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
2922 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
2923 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
2924 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
2925 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
2926 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
2927 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
2928
2929 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
2930 #define ADC_LTR_LT_Pos (0U)
2931 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
2932 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
2933
2934 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
2935 #define ADC_HTR_HT_Pos (0U)
2936 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
2937 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
2938
2939
2940 /******************** Bit definition for ADC_SQR1 register ********************/
2941 #define ADC_SQR1_L_Pos (0U)
2942 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
2943 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
2944 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
2945 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
2946 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
2947 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
2948
2949 #define ADC_SQR1_SQ1_Pos (6U)
2950 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
2951 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
2952 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
2953 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
2954 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
2955 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
2956 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
2957
2958 #define ADC_SQR1_SQ2_Pos (12U)
2959 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
2960 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
2961 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
2962 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
2963 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
2964 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
2965 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
2966
2967 #define ADC_SQR1_SQ3_Pos (18U)
2968 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
2969 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
2970 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
2971 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
2972 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
2973 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
2974 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
2975
2976 #define ADC_SQR1_SQ4_Pos (24U)
2977 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
2978 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
2979 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
2980 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
2981 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
2982 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
2983 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
2984
2985 /******************** Bit definition for ADC_SQR2 register ********************/
2986 #define ADC_SQR2_SQ5_Pos (0U)
2987 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
2988 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
2989 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
2990 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
2991 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
2992 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
2993 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
2994
2995 #define ADC_SQR2_SQ6_Pos (6U)
2996 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
2997 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
2998 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
2999 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3000 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3001 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3002 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3003
3004 #define ADC_SQR2_SQ7_Pos (12U)
3005 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3006 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3007 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3008 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3009 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3010 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3011 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3012
3013 #define ADC_SQR2_SQ8_Pos (18U)
3014 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3015 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3016 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3017 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3018 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3019 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3020 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3021
3022 #define ADC_SQR2_SQ9_Pos (24U)
3023 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3024 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3025 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3026 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3027 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3028 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3029 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3030
3031 /******************** Bit definition for ADC_SQR3 register ********************/
3032 #define ADC_SQR3_SQ10_Pos (0U)
3033 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3034 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3035 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3036 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3037 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3038 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3039 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3040
3041 #define ADC_SQR3_SQ11_Pos (6U)
3042 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3043 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3044 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3045 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3046 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3047 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3048 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3049
3050 #define ADC_SQR3_SQ12_Pos (12U)
3051 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3052 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3053 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3054 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3055 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3056 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3057 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3058
3059 #define ADC_SQR3_SQ13_Pos (18U)
3060 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3061 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3062 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3063 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3064 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3065 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3066 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3067
3068 #define ADC_SQR3_SQ14_Pos (24U)
3069 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3070 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3071 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3072 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3073 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3074 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3075 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3076
3077 /******************** Bit definition for ADC_SQR4 register ********************/
3078 #define ADC_SQR4_SQ15_Pos (0U)
3079 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3080 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3081 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3082 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3083 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3084 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3085 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3086
3087 #define ADC_SQR4_SQ16_Pos (6U)
3088 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3089 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3090 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3091 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3092 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3093 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3094 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3095 /******************** Bit definition for ADC_DR register ********************/
3096 #define ADC_DR_RDATA_Pos (0U)
3097 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3098 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3099
3100 /******************** Bit definition for ADC_JSQR register ********************/
3101 #define ADC_JSQR_JL_Pos (0U)
3102 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3103 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3104 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3105 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3106
3107 #define ADC_JSQR_JEXTSEL_Pos (2U)
3108 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3109 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3110 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3111 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3112 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3113 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3114 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3115
3116 #define ADC_JSQR_JEXTEN_Pos (7U)
3117 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3118 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3119 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3120 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3121
3122 #define ADC_JSQR_JSQ1_Pos (9U)
3123 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3124 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3125 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3126 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3127 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3128 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3129 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3130
3131 #define ADC_JSQR_JSQ2_Pos (15U)
3132 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3133 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3134 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3135 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3136 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3137 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3138 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3139
3140 #define ADC_JSQR_JSQ3_Pos (21U)
3141 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3142 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3143 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3144 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3145 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3146 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3147 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3148
3149 #define ADC_JSQR_JSQ4_Pos (27U)
3150 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3151 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3152 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3153 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3154 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3155 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3156 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3157
3158 /******************** Bit definition for ADC_OFR1 register ********************/
3159 #define ADC_OFR1_OFFSET1_Pos (0U)
3160 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3161 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3162 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3163 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3164 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3165 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3166 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3167 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3168 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3169 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3170 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3171 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3172 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3173 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3174 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3175 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3176 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3177 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3178 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3179 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3180 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3181 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3182 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3183 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3184 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3185 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3186 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3187 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3188
3189 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
3190 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3191 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3192 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3193 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3194 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3195 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3196 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3197
3198 #define ADC_OFR1_SSATE_Pos (31U)
3199 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3200 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3201
3202
3203 /******************** Bit definition for ADC_OFR2 register ********************/
3204 #define ADC_OFR2_OFFSET2_Pos (0U)
3205 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3206 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3207 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3208 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3209 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3210 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3211 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3212 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3213 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3214 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3215 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3216 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3217 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3218 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3219 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3220 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3221 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3222 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3223 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3224 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3225 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3226 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3227 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3228 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3229 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3230 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3231 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3232 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3233
3234 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
3235 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3236 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3237 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3238 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3239 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3240 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3241 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3242
3243 #define ADC_OFR2_SSATE_Pos (31U)
3244 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3245 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3246
3247
3248 /******************** Bit definition for ADC_OFR3 register ********************/
3249 #define ADC_OFR3_OFFSET3_Pos (0U)
3250 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3251 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3252 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3253 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3254 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3255 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3256 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3257 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3258 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3259 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3260 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3261 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3262 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3263 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3264 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3265 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3266 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3267 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3268 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3269 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3270 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3271 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3272 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3273 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3274 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3275 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3276 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3277 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3278
3279 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
3280 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3281 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3282 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3283 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3284 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3285 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3286 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3287
3288 #define ADC_OFR3_SSATE_Pos (31U)
3289 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3290 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3291
3292
3293 /******************** Bit definition for ADC_OFR4 register ********************/
3294 #define ADC_OFR4_OFFSET4_Pos (0U)
3295 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3296 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3297 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3298 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3299 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3300 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3301 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3302 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3303 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3304 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3305 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3306 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3307 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3308 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3309 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3310 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3311 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3312 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3313 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3314 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3315 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3316 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3317 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3318 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3319 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3320 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3321 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3322 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3323
3324 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
3325 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3326 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3327 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3328 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3329 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3330 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3331 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3332
3333 #define ADC_OFR4_SSATE_Pos (31U)
3334 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3335 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3336
3337
3338 /******************** Bit definition for ADC_JDR1 register ********************/
3339 #define ADC_JDR1_JDATA_Pos (0U)
3340 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3341 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3342 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3343 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3344 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3345 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3346 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3347 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3348 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3349 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3350 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3351 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3352 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3353 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3354 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3355 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3356 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3357 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3358 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3359 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3360 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3361 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3362 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3363 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3364 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3365 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3366 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3367 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3368 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3369 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3370 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3371 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3372 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3373 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3374
3375 /******************** Bit definition for ADC_JDR2 register ********************/
3376 #define ADC_JDR2_JDATA_Pos (0U)
3377 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3378 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3379 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3380 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3381 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3382 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3383 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3384 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3385 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3386 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3387 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3388 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3389 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3390 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3391 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3392 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3393 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3394 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3395 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3396 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3397 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3398 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3399 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3400 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3401 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3402 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3403 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3404 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3405 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3406 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3407 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3408 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3409 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3410 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3411
3412 /******************** Bit definition for ADC_JDR3 register ********************/
3413 #define ADC_JDR3_JDATA_Pos (0U)
3414 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3415 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3416 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3417 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3418 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3419 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3420 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3421 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3422 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3423 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3424 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3425 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3426 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3427 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3428 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3429 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3430 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3431 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3432 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3433 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3434 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3435 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3436 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3437 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3438 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3439 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3440 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3441 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3442 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3443 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3444 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3445 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3446 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3447 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3448
3449 /******************** Bit definition for ADC_JDR4 register ********************/
3450 #define ADC_JDR4_JDATA_Pos (0U)
3451 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3452 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3453 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3454 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3455 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3456 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3457 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3458 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3459 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3460 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3461 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3462 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3463 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3464 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3465 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3466 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3467 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3468 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3469 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3470 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3471 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3472 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3473 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3474 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3475 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3476 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3477 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3478 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3479 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3480 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3481 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3482 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3483 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3484 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3485
3486 /******************** Bit definition for ADC_AWD2CR register ********************/
3487 #define ADC_AWD2CR_AWD2CH_Pos (0U)
3488 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3489 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3490 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3491 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3492 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3493 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3494 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3495 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3496 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3497 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3498 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3499 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3500 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3501 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3502 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3503 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3504 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3505 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3506 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3507 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3508 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3509 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3510
3511 /******************** Bit definition for ADC_AWD3CR register ********************/
3512 #define ADC_AWD3CR_AWD3CH_Pos (0U)
3513 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3514 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3515 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3516 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3517 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3518 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3519 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3520 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3521 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3522 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3523 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3524 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3525 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3526 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3527 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3528 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3529 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3530 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3531 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3532 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3533 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3534 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3535
3536 /******************** Bit definition for ADC_DIFSEL register ********************/
3537 #define ADC_DIFSEL_DIFSEL_Pos (0U)
3538 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3539 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3540 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3541 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3542 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3543 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3544 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3545 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3546 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3547 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3548 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3549 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3550 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3551 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3552 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3553 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3554 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3555 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3556 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3557 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3558 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3559 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3560
3561 /******************** Bit definition for ADC_CALFACT register ********************/
3562 #define ADC_CALFACT_CALFACT_S_Pos (0U)
3563 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3564 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3565 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3566 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3567 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3568 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3569 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3570 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3571 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3572 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3573 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3574 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3575 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3576 #define ADC_CALFACT_CALFACT_D_Pos (16U)
3577 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3578 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3579 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3580 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3581 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3582 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3583 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3584 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3585 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3586 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3587 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3588 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3589 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3590
3591 /******************** Bit definition for ADC_CALFACT2 register ********************/
3592 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
3593 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3594 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3595 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3596 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3597 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3598 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3599 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3600 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3601 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3602 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3603 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3604 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3605 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3606 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3607 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3608 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3609 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3610 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3611 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3612 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3613 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3614 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3615 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3616 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3617 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3618 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3619 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3620 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3621 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3622 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3623 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3624 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3625
3626 /************************* ADC Common registers *****************************/
3627 /******************** Bit definition for ADC_CSR register ********************/
3628 #define ADC_CSR_ADRDY_MST_Pos (0U)
3629 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3630 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3631 #define ADC_CSR_EOSMP_MST_Pos (1U)
3632 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3633 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3634 #define ADC_CSR_EOC_MST_Pos (2U)
3635 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3636 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3637 #define ADC_CSR_EOS_MST_Pos (3U)
3638 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3639 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3640 #define ADC_CSR_OVR_MST_Pos (4U)
3641 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3642 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3643 #define ADC_CSR_JEOC_MST_Pos (5U)
3644 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3645 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3646 #define ADC_CSR_JEOS_MST_Pos (6U)
3647 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3648 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3649 #define ADC_CSR_AWD1_MST_Pos (7U)
3650 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3651 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3652 #define ADC_CSR_AWD2_MST_Pos (8U)
3653 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3654 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3655 #define ADC_CSR_AWD3_MST_Pos (9U)
3656 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3657 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3658 #define ADC_CSR_JQOVF_MST_Pos (10U)
3659 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3660 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3661 #define ADC_CSR_ADRDY_SLV_Pos (16U)
3662 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3663 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3664 #define ADC_CSR_EOSMP_SLV_Pos (17U)
3665 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3666 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3667 #define ADC_CSR_EOC_SLV_Pos (18U)
3668 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3669 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3670 #define ADC_CSR_EOS_SLV_Pos (19U)
3671 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3672 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3673 #define ADC_CSR_OVR_SLV_Pos (20U)
3674 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3675 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3676 #define ADC_CSR_JEOC_SLV_Pos (21U)
3677 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3678 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3679 #define ADC_CSR_JEOS_SLV_Pos (22U)
3680 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3681 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3682 #define ADC_CSR_AWD1_SLV_Pos (23U)
3683 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3684 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3685 #define ADC_CSR_AWD2_SLV_Pos (24U)
3686 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3687 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3688 #define ADC_CSR_AWD3_SLV_Pos (25U)
3689 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3690 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3691 #define ADC_CSR_JQOVF_SLV_Pos (26U)
3692 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3693 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3694
3695 /******************** Bit definition for ADC_CCR register ********************/
3696 #define ADC_CCR_DUAL_Pos (0U)
3697 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3698 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3699 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3700 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3701 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3702 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3703 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3704
3705 #define ADC_CCR_DELAY_Pos (8U)
3706 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3707 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3708 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3709 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3710 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3711 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3712
3713
3714 #define ADC_CCR_DAMDF_Pos (14U)
3715 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3716 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3717 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3718 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3719
3720 #define ADC_CCR_CKMODE_Pos (16U)
3721 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3722 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3723 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3724 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3725
3726 #define ADC_CCR_PRESC_Pos (18U)
3727 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3728 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3729 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3730 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3731 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3732 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3733
3734 #define ADC_CCR_VREFEN_Pos (22U)
3735 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3736 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3737 #define ADC_CCR_TSEN_Pos (23U)
3738 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3739 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3740 #define ADC_CCR_VBATEN_Pos (24U)
3741 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3742 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3743
3744 /******************** Bit definition for ADC_CDR register *******************/
3745 #define ADC_CDR_RDATA_MST_Pos (0U)
3746 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3747 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3748
3749 #define ADC_CDR_RDATA_SLV_Pos (16U)
3750 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3751 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3752
3753 /******************** Bit definition for ADC_CDR2 register ******************/
3754 #define ADC_CDR2_RDATA_ALT_Pos (0U)
3755 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3756 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3757
3758
3759 /******************************************************************************/
3760 /* */
3761 /* VREFBUF */
3762 /* */
3763 /******************************************************************************/
3764 /******************* Bit definition for VREFBUF_CSR register ****************/
3765 #define VREFBUF_CSR_ENVR_Pos (0U)
3766 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3767 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3768 #define VREFBUF_CSR_HIZ_Pos (1U)
3769 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3770 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3771 #define VREFBUF_CSR_VRR_Pos (3U)
3772 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3773 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3774 #define VREFBUF_CSR_VRS_Pos (4U)
3775 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3776 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3777
3778 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3779 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3780 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3781 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3782 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3783 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3784 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
3785 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3786 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
3787 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
3788
3789 /******************* Bit definition for VREFBUF_CCR register ****************/
3790 #define VREFBUF_CCR_TRIM_Pos (0U)
3791 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
3792 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
3793
3794 /******************************************************************************/
3795 /* */
3796 /* Flexible Datarate Controller Area Network */
3797 /* */
3798 /******************************************************************************/
3799 /*!<FDCAN control and status registers */
3800 /***************** Bit definition for FDCAN_CREL register *******************/
3801 #define FDCAN_CREL_DAY_Pos (0U)
3802 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
3803 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
3804 #define FDCAN_CREL_MON_Pos (8U)
3805 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
3806 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
3807 #define FDCAN_CREL_YEAR_Pos (16U)
3808 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
3809 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
3810 #define FDCAN_CREL_SUBSTEP_Pos (20U)
3811 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
3812 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
3813 #define FDCAN_CREL_STEP_Pos (24U)
3814 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
3815 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
3816 #define FDCAN_CREL_REL_Pos (28U)
3817 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
3818 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
3819
3820 /***************** Bit definition for FDCAN_ENDN register *******************/
3821 #define FDCAN_ENDN_ETV_Pos (0U)
3822 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
3823 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
3824
3825 /***************** Bit definition for FDCAN_DBTP register *******************/
3826 #define FDCAN_DBTP_DSJW_Pos (0U)
3827 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
3828 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
3829 #define FDCAN_DBTP_DTSEG2_Pos (4U)
3830 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
3831 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
3832 #define FDCAN_DBTP_DTSEG1_Pos (8U)
3833 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
3834 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
3835 #define FDCAN_DBTP_DBRP_Pos (16U)
3836 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
3837 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
3838 #define FDCAN_DBTP_TDC_Pos (23U)
3839 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
3840 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
3841
3842 /***************** Bit definition for FDCAN_TEST register *******************/
3843 #define FDCAN_TEST_LBCK_Pos (4U)
3844 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
3845 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
3846 #define FDCAN_TEST_TX_Pos (5U)
3847 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
3848 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
3849 #define FDCAN_TEST_RX_Pos (7U)
3850 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
3851 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
3852
3853 /***************** Bit definition for FDCAN_RWD register ********************/
3854 #define FDCAN_RWD_WDC_Pos (0U)
3855 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
3856 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
3857 #define FDCAN_RWD_WDV_Pos (8U)
3858 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
3859 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
3860
3861 /***************** Bit definition for FDCAN_CCCR register ********************/
3862 #define FDCAN_CCCR_INIT_Pos (0U)
3863 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
3864 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
3865 #define FDCAN_CCCR_CCE_Pos (1U)
3866 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
3867 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
3868 #define FDCAN_CCCR_ASM_Pos (2U)
3869 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
3870 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
3871 #define FDCAN_CCCR_CSA_Pos (3U)
3872 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
3873 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
3874 #define FDCAN_CCCR_CSR_Pos (4U)
3875 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
3876 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
3877 #define FDCAN_CCCR_MON_Pos (5U)
3878 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
3879 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
3880 #define FDCAN_CCCR_DAR_Pos (6U)
3881 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
3882 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
3883 #define FDCAN_CCCR_TEST_Pos (7U)
3884 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
3885 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
3886 #define FDCAN_CCCR_FDOE_Pos (8U)
3887 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
3888 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
3889 #define FDCAN_CCCR_BRSE_Pos (9U)
3890 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
3891 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
3892 #define FDCAN_CCCR_PXHD_Pos (12U)
3893 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
3894 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
3895 #define FDCAN_CCCR_EFBI_Pos (13U)
3896 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
3897 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
3898 #define FDCAN_CCCR_TXP_Pos (14U)
3899 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
3900 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
3901 #define FDCAN_CCCR_NISO_Pos (15U)
3902 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
3903 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
3904
3905 /***************** Bit definition for FDCAN_NBTP register ********************/
3906 #define FDCAN_NBTP_NTSEG2_Pos (0U)
3907 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
3908 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
3909 #define FDCAN_NBTP_NTSEG1_Pos (8U)
3910 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
3911 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
3912 #define FDCAN_NBTP_NBRP_Pos (16U)
3913 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
3914 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
3915 #define FDCAN_NBTP_NSJW_Pos (25U)
3916 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
3917 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
3918
3919 /***************** Bit definition for FDCAN_TSCC register ********************/
3920 #define FDCAN_TSCC_TSS_Pos (0U)
3921 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
3922 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
3923 #define FDCAN_TSCC_TCP_Pos (16U)
3924 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
3925 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
3926
3927 /***************** Bit definition for FDCAN_TSCV register ********************/
3928 #define FDCAN_TSCV_TSC_Pos (0U)
3929 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
3930 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
3931
3932 /***************** Bit definition for FDCAN_TOCC register ********************/
3933 #define FDCAN_TOCC_ETOC_Pos (0U)
3934 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
3935 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
3936 #define FDCAN_TOCC_TOS_Pos (1U)
3937 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
3938 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
3939 #define FDCAN_TOCC_TOP_Pos (16U)
3940 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
3941 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
3942
3943 /***************** Bit definition for FDCAN_TOCV register ********************/
3944 #define FDCAN_TOCV_TOC_Pos (0U)
3945 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
3946 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
3947
3948 /***************** Bit definition for FDCAN_ECR register *********************/
3949 #define FDCAN_ECR_TEC_Pos (0U)
3950 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
3951 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
3952 #define FDCAN_ECR_REC_Pos (8U)
3953 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
3954 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
3955 #define FDCAN_ECR_RP_Pos (15U)
3956 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
3957 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
3958 #define FDCAN_ECR_CEL_Pos (16U)
3959 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
3960 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
3961
3962 /***************** Bit definition for FDCAN_PSR register *********************/
3963 #define FDCAN_PSR_LEC_Pos (0U)
3964 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
3965 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
3966 #define FDCAN_PSR_ACT_Pos (3U)
3967 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
3968 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
3969 #define FDCAN_PSR_EP_Pos (5U)
3970 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
3971 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
3972 #define FDCAN_PSR_EW_Pos (6U)
3973 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
3974 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
3975 #define FDCAN_PSR_BO_Pos (7U)
3976 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
3977 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
3978 #define FDCAN_PSR_DLEC_Pos (8U)
3979 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
3980 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
3981 #define FDCAN_PSR_RESI_Pos (11U)
3982 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
3983 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
3984 #define FDCAN_PSR_RBRS_Pos (12U)
3985 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
3986 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
3987 #define FDCAN_PSR_REDL_Pos (13U)
3988 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
3989 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
3990 #define FDCAN_PSR_PXE_Pos (14U)
3991 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
3992 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
3993 #define FDCAN_PSR_TDCV_Pos (16U)
3994 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
3995 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
3996
3997 /***************** Bit definition for FDCAN_TDCR register ********************/
3998 #define FDCAN_TDCR_TDCF_Pos (0U)
3999 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4000 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4001 #define FDCAN_TDCR_TDCO_Pos (8U)
4002 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4003 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4004
4005 /***************** Bit definition for FDCAN_IR register **********************/
4006 #define FDCAN_IR_RF0N_Pos (0U)
4007 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4008 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4009 #define FDCAN_IR_RF0W_Pos (1U)
4010 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4011 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4012 #define FDCAN_IR_RF0F_Pos (2U)
4013 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4014 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4015 #define FDCAN_IR_RF0L_Pos (3U)
4016 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4017 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4018 #define FDCAN_IR_RF1N_Pos (4U)
4019 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4020 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4021 #define FDCAN_IR_RF1W_Pos (5U)
4022 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4023 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4024 #define FDCAN_IR_RF1F_Pos (6U)
4025 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4026 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4027 #define FDCAN_IR_RF1L_Pos (7U)
4028 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4029 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4030 #define FDCAN_IR_HPM_Pos (8U)
4031 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4032 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4033 #define FDCAN_IR_TC_Pos (9U)
4034 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4035 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4036 #define FDCAN_IR_TCF_Pos (10U)
4037 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4038 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4039 #define FDCAN_IR_TFE_Pos (11U)
4040 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4041 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4042 #define FDCAN_IR_TEFN_Pos (12U)
4043 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4044 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4045 #define FDCAN_IR_TEFW_Pos (13U)
4046 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4047 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4048 #define FDCAN_IR_TEFF_Pos (14U)
4049 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4050 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4051 #define FDCAN_IR_TEFL_Pos (15U)
4052 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4053 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4054 #define FDCAN_IR_TSW_Pos (16U)
4055 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4056 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4057 #define FDCAN_IR_MRAF_Pos (17U)
4058 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4059 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4060 #define FDCAN_IR_TOO_Pos (18U)
4061 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4062 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4063 #define FDCAN_IR_DRX_Pos (19U)
4064 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4065 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4066 #define FDCAN_IR_ELO_Pos (22U)
4067 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4068 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4069 #define FDCAN_IR_EP_Pos (23U)
4070 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4071 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4072 #define FDCAN_IR_EW_Pos (24U)
4073 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4074 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4075 #define FDCAN_IR_BO_Pos (25U)
4076 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4077 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4078 #define FDCAN_IR_WDI_Pos (26U)
4079 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4080 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4081 #define FDCAN_IR_PEA_Pos (27U)
4082 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4083 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4084 #define FDCAN_IR_PED_Pos (28U)
4085 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4086 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4087 #define FDCAN_IR_ARA_Pos (29U)
4088 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4089 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4090
4091 /***************** Bit definition for FDCAN_IE register **********************/
4092 #define FDCAN_IE_RF0NE_Pos (0U)
4093 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4094 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4095 #define FDCAN_IE_RF0WE_Pos (1U)
4096 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4097 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4098 #define FDCAN_IE_RF0FE_Pos (2U)
4099 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4100 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4101 #define FDCAN_IE_RF0LE_Pos (3U)
4102 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4103 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4104 #define FDCAN_IE_RF1NE_Pos (4U)
4105 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4106 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4107 #define FDCAN_IE_RF1WE_Pos (5U)
4108 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4109 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4110 #define FDCAN_IE_RF1FE_Pos (6U)
4111 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4112 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4113 #define FDCAN_IE_RF1LE_Pos (7U)
4114 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4115 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4116 #define FDCAN_IE_HPME_Pos (8U)
4117 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4118 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4119 #define FDCAN_IE_TCE_Pos (9U)
4120 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4121 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4122 #define FDCAN_IE_TCFE_Pos (10U)
4123 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4124 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4125 #define FDCAN_IE_TFEE_Pos (11U)
4126 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4127 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4128 #define FDCAN_IE_TEFNE_Pos (12U)
4129 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4130 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4131 #define FDCAN_IE_TEFWE_Pos (13U)
4132 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4133 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4134 #define FDCAN_IE_TEFFE_Pos (14U)
4135 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4136 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4137 #define FDCAN_IE_TEFLE_Pos (15U)
4138 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4139 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4140 #define FDCAN_IE_TSWE_Pos (16U)
4141 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4142 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4143 #define FDCAN_IE_MRAFE_Pos (17U)
4144 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4145 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4146 #define FDCAN_IE_TOOE_Pos (18U)
4147 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4148 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4149 #define FDCAN_IE_DRXE_Pos (19U)
4150 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4151 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4152 #define FDCAN_IE_BECE_Pos (20U)
4153 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4154 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4155 #define FDCAN_IE_BEUE_Pos (21U)
4156 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4157 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4158 #define FDCAN_IE_ELOE_Pos (22U)
4159 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4160 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4161 #define FDCAN_IE_EPE_Pos (23U)
4162 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4163 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4164 #define FDCAN_IE_EWE_Pos (24U)
4165 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4166 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4167 #define FDCAN_IE_BOE_Pos (25U)
4168 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4169 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4170 #define FDCAN_IE_WDIE_Pos (26U)
4171 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4172 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4173 #define FDCAN_IE_PEAE_Pos (27U)
4174 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4175 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4176 #define FDCAN_IE_PEDE_Pos (28U)
4177 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4178 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4179 #define FDCAN_IE_ARAE_Pos (29U)
4180 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4181 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4182
4183 /***************** Bit definition for FDCAN_ILS register **********************/
4184 #define FDCAN_ILS_RF0NL_Pos (0U)
4185 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4186 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4187 #define FDCAN_ILS_RF0WL_Pos (1U)
4188 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4189 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4190 #define FDCAN_ILS_RF0FL_Pos (2U)
4191 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4192 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4193 #define FDCAN_ILS_RF0LL_Pos (3U)
4194 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4195 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4196 #define FDCAN_ILS_RF1NL_Pos (4U)
4197 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4198 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4199 #define FDCAN_ILS_RF1WL_Pos (5U)
4200 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4201 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4202 #define FDCAN_ILS_RF1FL_Pos (6U)
4203 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4204 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4205 #define FDCAN_ILS_RF1LL_Pos (7U)
4206 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4207 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4208 #define FDCAN_ILS_HPML_Pos (8U)
4209 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4210 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4211 #define FDCAN_ILS_TCL_Pos (9U)
4212 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4213 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4214 #define FDCAN_ILS_TCFL_Pos (10U)
4215 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4216 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4217 #define FDCAN_ILS_TFEL_Pos (11U)
4218 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4219 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4220 #define FDCAN_ILS_TEFNL_Pos (12U)
4221 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4222 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4223 #define FDCAN_ILS_TEFWL_Pos (13U)
4224 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4225 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4226 #define FDCAN_ILS_TEFFL_Pos (14U)
4227 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4228 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4229 #define FDCAN_ILS_TEFLL_Pos (15U)
4230 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4231 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4232 #define FDCAN_ILS_TSWL_Pos (16U)
4233 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4234 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4235 #define FDCAN_ILS_MRAFE_Pos (17U)
4236 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4237 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4238 #define FDCAN_ILS_TOOE_Pos (18U)
4239 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4240 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4241 #define FDCAN_ILS_DRXE_Pos (19U)
4242 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4243 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4244 #define FDCAN_ILS_BECE_Pos (20U)
4245 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4246 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4247 #define FDCAN_ILS_BEUE_Pos (21U)
4248 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4249 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4250 #define FDCAN_ILS_ELOE_Pos (22U)
4251 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4252 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4253 #define FDCAN_ILS_EPE_Pos (23U)
4254 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4255 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4256 #define FDCAN_ILS_EWE_Pos (24U)
4257 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4258 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4259 #define FDCAN_ILS_BOE_Pos (25U)
4260 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4261 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4262 #define FDCAN_ILS_WDIE_Pos (26U)
4263 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4264 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4265 #define FDCAN_ILS_PEAE_Pos (27U)
4266 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4267 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4268 #define FDCAN_ILS_PEDE_Pos (28U)
4269 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4270 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4271 #define FDCAN_ILS_ARAE_Pos (29U)
4272 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4273 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4274
4275 /***************** Bit definition for FDCAN_ILE register **********************/
4276 #define FDCAN_ILE_EINT0_Pos (0U)
4277 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4278 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4279 #define FDCAN_ILE_EINT1_Pos (1U)
4280 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4281 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4282
4283 /***************** Bit definition for FDCAN_GFC register **********************/
4284 #define FDCAN_GFC_RRFE_Pos (0U)
4285 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4286 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4287 #define FDCAN_GFC_RRFS_Pos (1U)
4288 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4289 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4290 #define FDCAN_GFC_ANFE_Pos (2U)
4291 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4292 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4293 #define FDCAN_GFC_ANFS_Pos (4U)
4294 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4295 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4296
4297 /***************** Bit definition for FDCAN_SIDFC register ********************/
4298 #define FDCAN_SIDFC_FLSSA_Pos (2U)
4299 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4300 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4301 #define FDCAN_SIDFC_LSS_Pos (16U)
4302 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4303 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4304
4305 /***************** Bit definition for FDCAN_XIDFC register ********************/
4306 #define FDCAN_XIDFC_FLESA_Pos (2U)
4307 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4308 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4309 #define FDCAN_XIDFC_LSE_Pos (16U)
4310 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4311 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4312
4313 /***************** Bit definition for FDCAN_XIDAM register ********************/
4314 #define FDCAN_XIDAM_EIDM_Pos (0U)
4315 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4316 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4317
4318 /***************** Bit definition for FDCAN_HPMS register *********************/
4319 #define FDCAN_HPMS_BIDX_Pos (0U)
4320 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4321 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4322 #define FDCAN_HPMS_MSI_Pos (6U)
4323 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4324 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4325 #define FDCAN_HPMS_FIDX_Pos (8U)
4326 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4327 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4328 #define FDCAN_HPMS_FLST_Pos (15U)
4329 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4330 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4331
4332 /***************** Bit definition for FDCAN_NDAT1 register ********************/
4333 #define FDCAN_NDAT1_ND0_Pos (0U)
4334 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4335 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4336 #define FDCAN_NDAT1_ND1_Pos (1U)
4337 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4338 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4339 #define FDCAN_NDAT1_ND2_Pos (2U)
4340 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4341 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4342 #define FDCAN_NDAT1_ND3_Pos (3U)
4343 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4344 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4345 #define FDCAN_NDAT1_ND4_Pos (4U)
4346 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4347 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4348 #define FDCAN_NDAT1_ND5_Pos (5U)
4349 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4350 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4351 #define FDCAN_NDAT1_ND6_Pos (6U)
4352 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4353 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4354 #define FDCAN_NDAT1_ND7_Pos (7U)
4355 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4356 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4357 #define FDCAN_NDAT1_ND8_Pos (8U)
4358 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4359 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4360 #define FDCAN_NDAT1_ND9_Pos (9U)
4361 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4362 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4363 #define FDCAN_NDAT1_ND10_Pos (10U)
4364 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4365 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4366 #define FDCAN_NDAT1_ND11_Pos (11U)
4367 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4368 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4369 #define FDCAN_NDAT1_ND12_Pos (12U)
4370 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4371 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4372 #define FDCAN_NDAT1_ND13_Pos (13U)
4373 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4374 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4375 #define FDCAN_NDAT1_ND14_Pos (14U)
4376 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4377 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4378 #define FDCAN_NDAT1_ND15_Pos (15U)
4379 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4380 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4381 #define FDCAN_NDAT1_ND16_Pos (16U)
4382 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4383 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4384 #define FDCAN_NDAT1_ND17_Pos (17U)
4385 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4386 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4387 #define FDCAN_NDAT1_ND18_Pos (18U)
4388 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4389 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4390 #define FDCAN_NDAT1_ND19_Pos (19U)
4391 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4392 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4393 #define FDCAN_NDAT1_ND20_Pos (20U)
4394 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4395 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4396 #define FDCAN_NDAT1_ND21_Pos (21U)
4397 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4398 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4399 #define FDCAN_NDAT1_ND22_Pos (22U)
4400 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4401 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4402 #define FDCAN_NDAT1_ND23_Pos (23U)
4403 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4404 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4405 #define FDCAN_NDAT1_ND24_Pos (24U)
4406 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4407 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4408 #define FDCAN_NDAT1_ND25_Pos (25U)
4409 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4410 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4411 #define FDCAN_NDAT1_ND26_Pos (26U)
4412 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4413 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4414 #define FDCAN_NDAT1_ND27_Pos (27U)
4415 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4416 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4417 #define FDCAN_NDAT1_ND28_Pos (28U)
4418 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4419 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4420 #define FDCAN_NDAT1_ND29_Pos (29U)
4421 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4422 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4423 #define FDCAN_NDAT1_ND30_Pos (30U)
4424 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4425 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4426 #define FDCAN_NDAT1_ND31_Pos (31U)
4427 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4428 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4429
4430 /***************** Bit definition for FDCAN_NDAT2 register ********************/
4431 #define FDCAN_NDAT2_ND32_Pos (0U)
4432 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4433 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4434 #define FDCAN_NDAT2_ND33_Pos (1U)
4435 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4436 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4437 #define FDCAN_NDAT2_ND34_Pos (2U)
4438 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4439 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4440 #define FDCAN_NDAT2_ND35_Pos (3U)
4441 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4442 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4443 #define FDCAN_NDAT2_ND36_Pos (4U)
4444 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4445 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4446 #define FDCAN_NDAT2_ND37_Pos (5U)
4447 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4448 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4449 #define FDCAN_NDAT2_ND38_Pos (6U)
4450 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4451 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4452 #define FDCAN_NDAT2_ND39_Pos (7U)
4453 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4454 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4455 #define FDCAN_NDAT2_ND40_Pos (8U)
4456 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4457 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4458 #define FDCAN_NDAT2_ND41_Pos (9U)
4459 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4460 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4461 #define FDCAN_NDAT2_ND42_Pos (10U)
4462 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4463 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4464 #define FDCAN_NDAT2_ND43_Pos (11U)
4465 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4466 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4467 #define FDCAN_NDAT2_ND44_Pos (12U)
4468 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4469 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4470 #define FDCAN_NDAT2_ND45_Pos (13U)
4471 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4472 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4473 #define FDCAN_NDAT2_ND46_Pos (14U)
4474 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4475 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4476 #define FDCAN_NDAT2_ND47_Pos (15U)
4477 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4478 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4479 #define FDCAN_NDAT2_ND48_Pos (16U)
4480 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4481 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4482 #define FDCAN_NDAT2_ND49_Pos (17U)
4483 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4484 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4485 #define FDCAN_NDAT2_ND50_Pos (18U)
4486 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4487 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4488 #define FDCAN_NDAT2_ND51_Pos (19U)
4489 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4490 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4491 #define FDCAN_NDAT2_ND52_Pos (20U)
4492 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4493 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4494 #define FDCAN_NDAT2_ND53_Pos (21U)
4495 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4496 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4497 #define FDCAN_NDAT2_ND54_Pos (22U)
4498 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4499 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4500 #define FDCAN_NDAT2_ND55_Pos (23U)
4501 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4502 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4503 #define FDCAN_NDAT2_ND56_Pos (24U)
4504 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4505 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4506 #define FDCAN_NDAT2_ND57_Pos (25U)
4507 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4508 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4509 #define FDCAN_NDAT2_ND58_Pos (26U)
4510 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4511 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4512 #define FDCAN_NDAT2_ND59_Pos (27U)
4513 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4514 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4515 #define FDCAN_NDAT2_ND60_Pos (28U)
4516 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4517 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4518 #define FDCAN_NDAT2_ND61_Pos (29U)
4519 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4520 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4521 #define FDCAN_NDAT2_ND62_Pos (30U)
4522 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4523 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4524 #define FDCAN_NDAT2_ND63_Pos (31U)
4525 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4526 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4527
4528 /***************** Bit definition for FDCAN_RXF0C register ********************/
4529 #define FDCAN_RXF0C_F0SA_Pos (2U)
4530 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4531 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4532 #define FDCAN_RXF0C_F0S_Pos (16U)
4533 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4534 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4535 #define FDCAN_RXF0C_F0WM_Pos (24U)
4536 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4537 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4538 #define FDCAN_RXF0C_F0OM_Pos (31U)
4539 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4540 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4541
4542 /***************** Bit definition for FDCAN_RXF0S register ********************/
4543 #define FDCAN_RXF0S_F0FL_Pos (0U)
4544 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4545 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4546 #define FDCAN_RXF0S_F0GI_Pos (8U)
4547 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4548 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4549 #define FDCAN_RXF0S_F0PI_Pos (16U)
4550 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4551 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4552 #define FDCAN_RXF0S_F0F_Pos (24U)
4553 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4554 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4555 #define FDCAN_RXF0S_RF0L_Pos (25U)
4556 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4557 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4558
4559 /***************** Bit definition for FDCAN_RXF0A register ********************/
4560 #define FDCAN_RXF0A_F0AI_Pos (0U)
4561 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4562 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4563
4564 /***************** Bit definition for FDCAN_RXBC register ********************/
4565 #define FDCAN_RXBC_RBSA_Pos (2U)
4566 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4567 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4568
4569 /***************** Bit definition for FDCAN_RXF1C register ********************/
4570 #define FDCAN_RXF1C_F1SA_Pos (2U)
4571 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4572 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4573 #define FDCAN_RXF1C_F1S_Pos (16U)
4574 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4575 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4576 #define FDCAN_RXF1C_F1WM_Pos (24U)
4577 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4578 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4579 #define FDCAN_RXF1C_F1OM_Pos (31U)
4580 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4581 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4582
4583 /***************** Bit definition for FDCAN_RXF1S register ********************/
4584 #define FDCAN_RXF1S_F1FL_Pos (0U)
4585 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4586 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4587 #define FDCAN_RXF1S_F1GI_Pos (8U)
4588 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4589 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4590 #define FDCAN_RXF1S_F1PI_Pos (16U)
4591 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4592 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4593 #define FDCAN_RXF1S_F1F_Pos (24U)
4594 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4595 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4596 #define FDCAN_RXF1S_RF1L_Pos (25U)
4597 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4598 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4599
4600 /***************** Bit definition for FDCAN_RXF1A register ********************/
4601 #define FDCAN_RXF1A_F1AI_Pos (0U)
4602 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4603 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4604
4605 /***************** Bit definition for FDCAN_RXESC register ********************/
4606 #define FDCAN_RXESC_F0DS_Pos (0U)
4607 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4608 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4609 #define FDCAN_RXESC_F1DS_Pos (4U)
4610 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4611 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4612 #define FDCAN_RXESC_RBDS_Pos (8U)
4613 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4614 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4615
4616 /***************** Bit definition for FDCAN_TXBC register *********************/
4617 #define FDCAN_TXBC_TBSA_Pos (2U)
4618 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4619 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4620 #define FDCAN_TXBC_NDTB_Pos (16U)
4621 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4622 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4623 #define FDCAN_TXBC_TFQS_Pos (24U)
4624 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4625 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4626 #define FDCAN_TXBC_TFQM_Pos (30U)
4627 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4628 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4629
4630 /***************** Bit definition for FDCAN_TXFQS register *********************/
4631 #define FDCAN_TXFQS_TFFL_Pos (0U)
4632 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4633 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4634 #define FDCAN_TXFQS_TFGI_Pos (8U)
4635 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4636 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4637 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4638 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4639 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4640 #define FDCAN_TXFQS_TFQF_Pos (21U)
4641 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4642 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4643
4644 /***************** Bit definition for FDCAN_TXESC register *********************/
4645 #define FDCAN_TXESC_TBDS_Pos (0U)
4646 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4647 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4648
4649 /***************** Bit definition for FDCAN_TXBRP register *********************/
4650 #define FDCAN_TXBRP_TRP_Pos (0U)
4651 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4652 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4653
4654 /***************** Bit definition for FDCAN_TXBAR register *********************/
4655 #define FDCAN_TXBAR_AR_Pos (0U)
4656 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4657 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4658
4659 /***************** Bit definition for FDCAN_TXBCR register *********************/
4660 #define FDCAN_TXBCR_CR_Pos (0U)
4661 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4662 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4663
4664 /***************** Bit definition for FDCAN_TXBTO register *********************/
4665 #define FDCAN_TXBTO_TO_Pos (0U)
4666 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4667 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4668
4669 /***************** Bit definition for FDCAN_TXBCF register *********************/
4670 #define FDCAN_TXBCF_CF_Pos (0U)
4671 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4672 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4673
4674 /***************** Bit definition for FDCAN_TXBTIE register ********************/
4675 #define FDCAN_TXBTIE_TIE_Pos (0U)
4676 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4677 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4678
4679 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
4680 #define FDCAN_TXBCIE_CFIE_Pos (0U)
4681 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4682 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4683
4684 /***************** Bit definition for FDCAN_TXEFC register *********************/
4685 #define FDCAN_TXEFC_EFSA_Pos (2U)
4686 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4687 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4688 #define FDCAN_TXEFC_EFS_Pos (16U)
4689 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4690 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4691 #define FDCAN_TXEFC_EFWM_Pos (24U)
4692 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4693 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4694
4695 /***************** Bit definition for FDCAN_TXEFS register *********************/
4696 #define FDCAN_TXEFS_EFFL_Pos (0U)
4697 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4698 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4699 #define FDCAN_TXEFS_EFGI_Pos (8U)
4700 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4701 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4702 #define FDCAN_TXEFS_EFPI_Pos (16U)
4703 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4704 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4705 #define FDCAN_TXEFS_EFF_Pos (24U)
4706 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4707 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4708 #define FDCAN_TXEFS_TEFL_Pos (25U)
4709 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4710 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4711
4712 /***************** Bit definition for FDCAN_TXEFA register *********************/
4713 #define FDCAN_TXEFA_EFAI_Pos (0U)
4714 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4715 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4716
4717 /***************** Bit definition for FDCAN_TTTMC register *********************/
4718 #define FDCAN_TTTMC_TMSA_Pos (2U)
4719 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4720 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4721 #define FDCAN_TTTMC_TME_Pos (16U)
4722 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4723 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4724
4725 /***************** Bit definition for FDCAN_TTRMC register *********************/
4726 #define FDCAN_TTRMC_RID_Pos (0U)
4727 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4728 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4729 #define FDCAN_TTRMC_XTD_Pos (30U)
4730 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4731 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4732 #define FDCAN_TTRMC_RMPS_Pos (31U)
4733 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4734 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4735
4736 /***************** Bit definition for FDCAN_TTOCF register *********************/
4737 #define FDCAN_TTOCF_OM_Pos (0U)
4738 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4739 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4740 #define FDCAN_TTOCF_GEN_Pos (3U)
4741 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4742 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4743 #define FDCAN_TTOCF_TM_Pos (4U)
4744 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4745 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4746 #define FDCAN_TTOCF_LDSDL_Pos (5U)
4747 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4748 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4749 #define FDCAN_TTOCF_IRTO_Pos (8U)
4750 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4751 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4752 #define FDCAN_TTOCF_EECS_Pos (15U)
4753 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4754 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4755 #define FDCAN_TTOCF_AWL_Pos (16U)
4756 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4757 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4758 #define FDCAN_TTOCF_EGTF_Pos (24U)
4759 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4760 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4761 #define FDCAN_TTOCF_ECC_Pos (25U)
4762 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4763 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4764 #define FDCAN_TTOCF_EVTP_Pos (26U)
4765 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4766 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4767
4768 /***************** Bit definition for FDCAN_TTMLM register *********************/
4769 #define FDCAN_TTMLM_CCM_Pos (0U)
4770 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4771 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4772 #define FDCAN_TTMLM_CSS_Pos (6U)
4773 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4774 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4775 #define FDCAN_TTMLM_TXEW_Pos (8U)
4776 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4777 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4778 #define FDCAN_TTMLM_ENTT_Pos (16U)
4779 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4780 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4781
4782 /***************** Bit definition for FDCAN_TURCF register *********************/
4783 #define FDCAN_TURCF_NCL_Pos (0U)
4784 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
4785 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
4786 #define FDCAN_TURCF_DC_Pos (16U)
4787 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
4788 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
4789 #define FDCAN_TURCF_ELT_Pos (31U)
4790 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
4791 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
4792
4793 /***************** Bit definition for FDCAN_TTOCN register ********************/
4794 #define FDCAN_TTOCN_SGT_Pos (0U)
4795 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
4796 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
4797 #define FDCAN_TTOCN_ECS_Pos (1U)
4798 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
4799 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
4800 #define FDCAN_TTOCN_SWP_Pos (2U)
4801 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
4802 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
4803 #define FDCAN_TTOCN_SWS_Pos (3U)
4804 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
4805 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
4806 #define FDCAN_TTOCN_RTIE_Pos (5U)
4807 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
4808 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
4809 #define FDCAN_TTOCN_TMC_Pos (6U)
4810 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
4811 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
4812 #define FDCAN_TTOCN_TTIE_Pos (8U)
4813 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
4814 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
4815 #define FDCAN_TTOCN_GCS_Pos (9U)
4816 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
4817 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
4818 #define FDCAN_TTOCN_FGP_Pos (10U)
4819 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
4820 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
4821 #define FDCAN_TTOCN_TMG_Pos (11U)
4822 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
4823 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
4824 #define FDCAN_TTOCN_NIG_Pos (12U)
4825 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
4826 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
4827 #define FDCAN_TTOCN_ESCN_Pos (13U)
4828 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
4829 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
4830 #define FDCAN_TTOCN_LCKC_Pos (15U)
4831 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
4832 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
4833
4834 /***************** Bit definition for FDCAN_TTGTP register ********************/
4835 #define FDCAN_TTGTP_TP_Pos (0U)
4836 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
4837 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
4838 #define FDCAN_TTGTP_CTP_Pos (16U)
4839 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
4840 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
4841
4842 /***************** Bit definition for FDCAN_TTTMK register ********************/
4843 #define FDCAN_TTTMK_TM_Pos (0U)
4844 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
4845 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
4846 #define FDCAN_TTTMK_TICC_Pos (16U)
4847 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
4848 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
4849 #define FDCAN_TTTMK_LCKM_Pos (31U)
4850 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
4851 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
4852
4853 /***************** Bit definition for FDCAN_TTIR register ********************/
4854 #define FDCAN_TTIR_SBC_Pos (0U)
4855 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
4856 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
4857 #define FDCAN_TTIR_SMC_Pos (1U)
4858 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
4859 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
4860 #define FDCAN_TTIR_CSM_Pos (2U)
4861 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
4862 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
4863 #define FDCAN_TTIR_SOG_Pos (3U)
4864 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
4865 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
4866 #define FDCAN_TTIR_RTMI_Pos (4U)
4867 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
4868 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
4869 #define FDCAN_TTIR_TTMI_Pos (5U)
4870 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
4871 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
4872 #define FDCAN_TTIR_SWE_Pos (6U)
4873 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
4874 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
4875 #define FDCAN_TTIR_GTW_Pos (7U)
4876 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
4877 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
4878 #define FDCAN_TTIR_GTD_Pos (8U)
4879 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
4880 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
4881 #define FDCAN_TTIR_GTE_Pos (9U)
4882 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
4883 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
4884 #define FDCAN_TTIR_TXU_Pos (10U)
4885 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
4886 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
4887 #define FDCAN_TTIR_TXO_Pos (11U)
4888 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
4889 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
4890 #define FDCAN_TTIR_SE1_Pos (12U)
4891 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
4892 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
4893 #define FDCAN_TTIR_SE2_Pos (13U)
4894 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
4895 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
4896 #define FDCAN_TTIR_ELC_Pos (14U)
4897 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
4898 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
4899 #define FDCAN_TTIR_IWT_Pos (15U)
4900 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
4901 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
4902 #define FDCAN_TTIR_WT_Pos (16U)
4903 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
4904 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
4905 #define FDCAN_TTIR_AW_Pos (17U)
4906 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
4907 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
4908 #define FDCAN_TTIR_CER_Pos (18U)
4909 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
4910 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
4911
4912 /***************** Bit definition for FDCAN_TTIE register ********************/
4913 #define FDCAN_TTIE_SBCE_Pos (0U)
4914 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
4915 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
4916 #define FDCAN_TTIE_SMCE_Pos (1U)
4917 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
4918 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
4919 #define FDCAN_TTIE_CSME_Pos (2U)
4920 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
4921 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
4922 #define FDCAN_TTIE_SOGE_Pos (3U)
4923 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
4924 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
4925 #define FDCAN_TTIE_RTMIE_Pos (4U)
4926 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
4927 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
4928 #define FDCAN_TTIE_TTMIE_Pos (5U)
4929 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
4930 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
4931 #define FDCAN_TTIE_SWEE_Pos (6U)
4932 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
4933 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
4934 #define FDCAN_TTIE_GTWE_Pos (7U)
4935 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
4936 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
4937 #define FDCAN_TTIE_GTDE_Pos (8U)
4938 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
4939 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
4940 #define FDCAN_TTIE_GTEE_Pos (9U)
4941 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
4942 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
4943 #define FDCAN_TTIE_TXUE_Pos (10U)
4944 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
4945 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
4946 #define FDCAN_TTIE_TXOE_Pos (11U)
4947 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
4948 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
4949 #define FDCAN_TTIE_SE1E_Pos (12U)
4950 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
4951 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
4952 #define FDCAN_TTIE_SE2E_Pos (13U)
4953 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
4954 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
4955 #define FDCAN_TTIE_ELCE_Pos (14U)
4956 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
4957 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
4958 #define FDCAN_TTIE_IWTE_Pos (15U)
4959 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
4960 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
4961 #define FDCAN_TTIE_WTE_Pos (16U)
4962 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
4963 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
4964 #define FDCAN_TTIE_AWE_Pos (17U)
4965 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
4966 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
4967 #define FDCAN_TTIE_CERE_Pos (18U)
4968 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
4969 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
4970
4971 /***************** Bit definition for FDCAN_TTILS register ********************/
4972 #define FDCAN_TTILS_SBCS_Pos (0U)
4973 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
4974 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
4975 #define FDCAN_TTILS_SMCS_Pos (1U)
4976 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
4977 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
4978 #define FDCAN_TTILS_CSMS_Pos (2U)
4979 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
4980 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
4981 #define FDCAN_TTILS_SOGS_Pos (3U)
4982 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
4983 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
4984 #define FDCAN_TTILS_RTMIS_Pos (4U)
4985 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
4986 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
4987 #define FDCAN_TTILS_TTMIS_Pos (5U)
4988 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
4989 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
4990 #define FDCAN_TTILS_SWES_Pos (6U)
4991 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
4992 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
4993 #define FDCAN_TTILS_GTWS_Pos (7U)
4994 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
4995 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
4996 #define FDCAN_TTILS_GTDS_Pos (8U)
4997 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
4998 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
4999 #define FDCAN_TTILS_GTES_Pos (9U)
5000 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5001 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5002 #define FDCAN_TTILS_TXUS_Pos (10U)
5003 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5004 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5005 #define FDCAN_TTILS_TXOS_Pos (11U)
5006 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5007 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5008 #define FDCAN_TTILS_SE1S_Pos (12U)
5009 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5010 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5011 #define FDCAN_TTILS_SE2S_Pos (13U)
5012 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5013 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5014 #define FDCAN_TTILS_ELCS_Pos (14U)
5015 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5016 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5017 #define FDCAN_TTILS_IWTS_Pos (15U)
5018 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5019 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5020 #define FDCAN_TTILS_WTS_Pos (16U)
5021 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5022 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5023 #define FDCAN_TTILS_AWS_Pos (17U)
5024 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5025 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5026 #define FDCAN_TTILS_CERS_Pos (18U)
5027 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5028 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5029
5030 /***************** Bit definition for FDCAN_TTOST register ********************/
5031 #define FDCAN_TTOST_EL_Pos (0U)
5032 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5033 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5034 #define FDCAN_TTOST_MS_Pos (2U)
5035 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5036 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5037 #define FDCAN_TTOST_SYS_Pos (4U)
5038 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5039 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5040 #define FDCAN_TTOST_QGTP_Pos (6U)
5041 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5042 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5043 #define FDCAN_TTOST_QCS_Pos (7U)
5044 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5045 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5046 #define FDCAN_TTOST_RTO_Pos (8U)
5047 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5048 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5049 #define FDCAN_TTOST_WGTD_Pos (22U)
5050 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5051 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5052 #define FDCAN_TTOST_GFI_Pos (23U)
5053 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5054 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5055 #define FDCAN_TTOST_TMP_Pos (24U)
5056 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5057 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5058 #define FDCAN_TTOST_GSI_Pos (27U)
5059 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5060 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5061 #define FDCAN_TTOST_WFE_Pos (28U)
5062 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5063 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5064 #define FDCAN_TTOST_AWE_Pos (29U)
5065 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5066 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5067 #define FDCAN_TTOST_WECS_Pos (30U)
5068 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5069 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5070 #define FDCAN_TTOST_SPL_Pos (31U)
5071 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5072 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5073
5074 /***************** Bit definition for FDCAN_TURNA register ********************/
5075 #define FDCAN_TURNA_NAV_Pos (0U)
5076 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5077 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5078
5079 /***************** Bit definition for FDCAN_TTLGT register ********************/
5080 #define FDCAN_TTLGT_LT_Pos (0U)
5081 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5082 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5083 #define FDCAN_TTLGT_GT_Pos (16U)
5084 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5085 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5086
5087 /***************** Bit definition for FDCAN_TTCTC register ********************/
5088 #define FDCAN_TTCTC_CT_Pos (0U)
5089 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5090 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5091 #define FDCAN_TTCTC_CC_Pos (16U)
5092 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5093 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5094
5095 /***************** Bit definition for FDCAN_TTCPT register ********************/
5096 #define FDCAN_TTCPT_CCV_Pos (0U)
5097 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5098 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5099 #define FDCAN_TTCPT_SWV_Pos (16U)
5100 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5101 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5102
5103 /***************** Bit definition for FDCAN_TTCSM register ********************/
5104 #define FDCAN_TTCSM_CSM_Pos (0U)
5105 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5106 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5107
5108 /***************** Bit definition for FDCAN_TTTS register *********************/
5109 #define FDCAN_TTTS_SWTSEL_Pos (0U)
5110 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5111 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5112 #define FDCAN_TTTS_EVTSEL_Pos (4U)
5113 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5114 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5115
5116 /********************************************************************************/
5117 /* */
5118 /* FDCANCCU (Clock Calibration unit) */
5119 /* */
5120 /********************************************************************************/
5121
5122 /***************** Bit definition for FDCANCCU_CREL register ******************/
5123 #define FDCANCCU_CREL_DAY_Pos (0U)
5124 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5125 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5126 #define FDCANCCU_CREL_MON_Pos (8U)
5127 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5128 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5129 #define FDCANCCU_CREL_YEAR_Pos (16U)
5130 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5131 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5132 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5133 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5134 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5135 #define FDCANCCU_CREL_STEP_Pos (24U)
5136 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5137 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5138 #define FDCANCCU_CREL_REL_Pos (28U)
5139 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5140 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5141
5142 /***************** Bit definition for FDCANCCU_CCFG register ******************/
5143 #define FDCANCCU_CCFG_TQBT_Pos (0U)
5144 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5145 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5146 #define FDCANCCU_CCFG_BCC_Pos (6U)
5147 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5148 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5149 #define FDCANCCU_CCFG_CFL_Pos (7U)
5150 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5151 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5152 #define FDCANCCU_CCFG_OCPM_Pos (8U)
5153 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5154 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5155 #define FDCANCCU_CCFG_CDIV_Pos (16U)
5156 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5157 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5158 #define FDCANCCU_CCFG_SWR_Pos (31U)
5159 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5160 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5161
5162 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
5163 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
5164 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5165 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5166 #define FDCANCCU_CSTAT_TQC_Pos (18U)
5167 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5168 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5169 #define FDCANCCU_CSTAT_CALS_Pos (30U)
5170 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5171 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5172
5173 /****************** Bit definition for FDCANCCU_CWD register ******************/
5174 #define FDCANCCU_CWD_WDC_Pos (0U)
5175 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5176 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5177 #define FDCANCCU_CWD_WDV_Pos (16U)
5178 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5179 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5180
5181 /****************** Bit definition for FDCANCCU_IR register *******************/
5182 #define FDCANCCU_IR_CWE_Pos (0U)
5183 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5184 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5185 #define FDCANCCU_IR_CSC_Pos (1U)
5186 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5187 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5188
5189 /****************** Bit definition for FDCANCCU_IE register *******************/
5190 #define FDCANCCU_IE_CWEE_Pos (0U)
5191 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5192 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5193 #define FDCANCCU_IE_CSCE_Pos (1U)
5194 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5195 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5196
5197 /******************************************************************************/
5198 /* */
5199 /* HDMI-CEC (CEC) */
5200 /* */
5201 /******************************************************************************/
5202
5203 /******************* Bit definition for CEC_CR register *********************/
5204 #define CEC_CR_CECEN_Pos (0U)
5205 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5206 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5207 #define CEC_CR_TXSOM_Pos (1U)
5208 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5209 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5210 #define CEC_CR_TXEOM_Pos (2U)
5211 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5212 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5213
5214 /******************* Bit definition for CEC_CFGR register *******************/
5215 #define CEC_CFGR_SFT_Pos (0U)
5216 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5217 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5218 #define CEC_CFGR_RXTOL_Pos (3U)
5219 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5220 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5221 #define CEC_CFGR_BRESTP_Pos (4U)
5222 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5223 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5224 #define CEC_CFGR_BREGEN_Pos (5U)
5225 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5226 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5227 #define CEC_CFGR_LBPEGEN_Pos (6U)
5228 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5229 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5230 #define CEC_CFGR_SFTOPT_Pos (8U)
5231 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5232 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5233 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5234 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5235 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5236 #define CEC_CFGR_OAR_Pos (16U)
5237 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5238 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5239 #define CEC_CFGR_LSTN_Pos (31U)
5240 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5241 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5242
5243 /******************* Bit definition for CEC_TXDR register *******************/
5244 #define CEC_TXDR_TXD_Pos (0U)
5245 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5246 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5247
5248 /******************* Bit definition for CEC_RXDR register *******************/
5249 #define CEC_RXDR_RXD_Pos (0U)
5250 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5251 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5252
5253 /******************* Bit definition for CEC_ISR register ********************/
5254 #define CEC_ISR_RXBR_Pos (0U)
5255 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5256 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5257 #define CEC_ISR_RXEND_Pos (1U)
5258 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5259 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5260 #define CEC_ISR_RXOVR_Pos (2U)
5261 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5262 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5263 #define CEC_ISR_BRE_Pos (3U)
5264 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5265 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5266 #define CEC_ISR_SBPE_Pos (4U)
5267 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5268 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5269 #define CEC_ISR_LBPE_Pos (5U)
5270 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5271 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5272 #define CEC_ISR_RXACKE_Pos (6U)
5273 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5274 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5275 #define CEC_ISR_ARBLST_Pos (7U)
5276 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5277 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5278 #define CEC_ISR_TXBR_Pos (8U)
5279 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5280 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5281 #define CEC_ISR_TXEND_Pos (9U)
5282 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5283 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5284 #define CEC_ISR_TXUDR_Pos (10U)
5285 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5286 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5287 #define CEC_ISR_TXERR_Pos (11U)
5288 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5289 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5290 #define CEC_ISR_TXACKE_Pos (12U)
5291 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5292 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5293
5294 /******************* Bit definition for CEC_IER register ********************/
5295 #define CEC_IER_RXBRIE_Pos (0U)
5296 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5297 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5298 #define CEC_IER_RXENDIE_Pos (1U)
5299 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5300 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5301 #define CEC_IER_RXOVRIE_Pos (2U)
5302 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5303 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5304 #define CEC_IER_BREIE_Pos (3U)
5305 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5306 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5307 #define CEC_IER_SBPEIE_Pos (4U)
5308 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5309 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5310 #define CEC_IER_LBPEIE_Pos (5U)
5311 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5312 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5313 #define CEC_IER_RXACKEIE_Pos (6U)
5314 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5315 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5316 #define CEC_IER_ARBLSTIE_Pos (7U)
5317 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5318 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5319 #define CEC_IER_TXBRIE_Pos (8U)
5320 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5321 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5322 #define CEC_IER_TXENDIE_Pos (9U)
5323 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5324 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5325 #define CEC_IER_TXUDRIE_Pos (10U)
5326 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5327 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5328 #define CEC_IER_TXERRIE_Pos (11U)
5329 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5330 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5331 #define CEC_IER_TXACKEIE_Pos (12U)
5332 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5333 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5334
5335 /******************************************************************************/
5336 /* */
5337 /* CRC calculation unit */
5338 /* */
5339 /******************************************************************************/
5340 /******************* Bit definition for CRC_DR register *********************/
5341 #define CRC_DR_DR_Pos (0U)
5342 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5343 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5344
5345 /******************* Bit definition for CRC_IDR register ********************/
5346 #define CRC_IDR_IDR_Pos (0U)
5347 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5348 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5349
5350 /******************** Bit definition for CRC_CR register ********************/
5351 #define CRC_CR_RESET_Pos (0U)
5352 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5353 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5354 #define CRC_CR_POLYSIZE_Pos (3U)
5355 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5356 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5357 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5358 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5359 #define CRC_CR_REV_IN_Pos (5U)
5360 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5361 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5362 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5363 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5364 #define CRC_CR_REV_OUT_Pos (7U)
5365 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5366 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5367
5368 /******************* Bit definition for CRC_INIT register *******************/
5369 #define CRC_INIT_INIT_Pos (0U)
5370 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5371 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5372
5373 /******************* Bit definition for CRC_POL register ********************/
5374 #define CRC_POL_POL_Pos (0U)
5375 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5376 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5377
5378 /******************************************************************************/
5379 /* */
5380 /* CRS Clock Recovery System */
5381 /******************************************************************************/
5382
5383 /******************* Bit definition for CRS_CR register *********************/
5384 #define CRS_CR_SYNCOKIE_Pos (0U)
5385 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5386 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5387 #define CRS_CR_SYNCWARNIE_Pos (1U)
5388 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5389 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5390 #define CRS_CR_ERRIE_Pos (2U)
5391 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5392 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5393 #define CRS_CR_ESYNCIE_Pos (3U)
5394 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5395 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5396 #define CRS_CR_CEN_Pos (5U)
5397 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5398 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5399 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5400 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5401 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5402 #define CRS_CR_SWSYNC_Pos (7U)
5403 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5404 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5405 #define CRS_CR_TRIM_Pos (8U)
5406 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5407 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5408
5409 /******************* Bit definition for CRS_CFGR register *********************/
5410 #define CRS_CFGR_RELOAD_Pos (0U)
5411 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5412 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5413 #define CRS_CFGR_FELIM_Pos (16U)
5414 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5415 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5416
5417 #define CRS_CFGR_SYNCDIV_Pos (24U)
5418 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5419 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5420 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5421 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5422 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5423
5424 #define CRS_CFGR_SYNCSRC_Pos (28U)
5425 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5426 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5427 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5428 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5429
5430 #define CRS_CFGR_SYNCPOL_Pos (31U)
5431 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5432 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5433
5434 /******************* Bit definition for CRS_ISR register *********************/
5435 #define CRS_ISR_SYNCOKF_Pos (0U)
5436 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5437 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5438 #define CRS_ISR_SYNCWARNF_Pos (1U)
5439 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5440 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5441 #define CRS_ISR_ERRF_Pos (2U)
5442 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5443 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5444 #define CRS_ISR_ESYNCF_Pos (3U)
5445 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5446 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5447 #define CRS_ISR_SYNCERR_Pos (8U)
5448 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5449 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5450 #define CRS_ISR_SYNCMISS_Pos (9U)
5451 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5452 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5453 #define CRS_ISR_TRIMOVF_Pos (10U)
5454 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5455 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5456 #define CRS_ISR_FEDIR_Pos (15U)
5457 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5458 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5459 #define CRS_ISR_FECAP_Pos (16U)
5460 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5461 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5462
5463 /******************* Bit definition for CRS_ICR register *********************/
5464 #define CRS_ICR_SYNCOKC_Pos (0U)
5465 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5466 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5467 #define CRS_ICR_SYNCWARNC_Pos (1U)
5468 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5469 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5470 #define CRS_ICR_ERRC_Pos (2U)
5471 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5472 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5473 #define CRS_ICR_ESYNCC_Pos (3U)
5474 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5475 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5476
5477 /******************************************************************************/
5478 /* */
5479 /* Digital to Analog Converter */
5480 /* */
5481 /******************************************************************************/
5482 /******************** Bit definition for DAC_CR register ********************/
5483 #define DAC_CR_EN1_Pos (0U)
5484 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5485 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5486 #define DAC_CR_TEN1_Pos (1U)
5487 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5488 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5489
5490 #define DAC_CR_TSEL1_Pos (2U)
5491 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5492 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5493 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5494 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5495 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5496 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5497
5498
5499 #define DAC_CR_WAVE1_Pos (6U)
5500 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5501 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5502 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5503 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5504
5505 #define DAC_CR_MAMP1_Pos (8U)
5506 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5507 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5508 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5509 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5510 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5511 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5512
5513 #define DAC_CR_DMAEN1_Pos (12U)
5514 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5515 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5516 #define DAC_CR_DMAUDRIE1_Pos (13U)
5517 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5518 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5519 #define DAC_CR_CEN1_Pos (14U)
5520 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5521 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5522
5523 #define DAC_CR_EN2_Pos (16U)
5524 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5525 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5526 #define DAC_CR_TEN2_Pos (17U)
5527 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5528 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5529
5530 #define DAC_CR_TSEL2_Pos (18U)
5531 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5532 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5533 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5534 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5535 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5536 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5537
5538
5539 #define DAC_CR_WAVE2_Pos (22U)
5540 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5541 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5542 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5543 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5544
5545 #define DAC_CR_MAMP2_Pos (24U)
5546 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5547 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5548 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5549 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5550 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5551 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5552
5553 #define DAC_CR_DMAEN2_Pos (28U)
5554 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5555 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5556 #define DAC_CR_DMAUDRIE2_Pos (29U)
5557 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5558 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5559 #define DAC_CR_CEN2_Pos (30U)
5560 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5561 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5562
5563 /***************** Bit definition for DAC_SWTRIGR register ******************/
5564 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5565 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5566 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5567 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5568 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5569 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5570
5571 /***************** Bit definition for DAC_DHR12R1 register ******************/
5572 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5573 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5574 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5575
5576 /***************** Bit definition for DAC_DHR12L1 register ******************/
5577 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5578 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5579 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5580
5581 /****************** Bit definition for DAC_DHR8R1 register ******************/
5582 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5583 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5584 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5585
5586 /***************** Bit definition for DAC_DHR12R2 register ******************/
5587 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5588 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5589 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5590
5591 /***************** Bit definition for DAC_DHR12L2 register ******************/
5592 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5593 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5594 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5595
5596 /****************** Bit definition for DAC_DHR8R2 register ******************/
5597 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5598 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5599 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5600
5601 /***************** Bit definition for DAC_DHR12RD register ******************/
5602 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5603 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5604 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5605 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5606 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5607 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5608
5609 /***************** Bit definition for DAC_DHR12LD register ******************/
5610 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5611 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5612 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5613 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5614 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5615 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5616
5617 /****************** Bit definition for DAC_DHR8RD register ******************/
5618 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5619 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5620 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5621 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5622 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5623 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5624
5625 /******************* Bit definition for DAC_DOR1 register *******************/
5626 #define DAC_DOR1_DACC1DOR_Pos (0U)
5627 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5628 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5629
5630 /******************* Bit definition for DAC_DOR2 register *******************/
5631 #define DAC_DOR2_DACC2DOR_Pos (0U)
5632 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5633 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5634
5635 /******************** Bit definition for DAC_SR register ********************/
5636 #define DAC_SR_DMAUDR1_Pos (13U)
5637 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5638 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5639 #define DAC_SR_CAL_FLAG1_Pos (14U)
5640 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5641 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5642 #define DAC_SR_BWST1_Pos (15U)
5643 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5644 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5645
5646 #define DAC_SR_DMAUDR2_Pos (29U)
5647 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5648 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5649 #define DAC_SR_CAL_FLAG2_Pos (30U)
5650 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5651 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5652 #define DAC_SR_BWST2_Pos (31U)
5653 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5654 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5655
5656 /******************* Bit definition for DAC_CCR register ********************/
5657 #define DAC_CCR_OTRIM1_Pos (0U)
5658 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5659 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5660 #define DAC_CCR_OTRIM2_Pos (16U)
5661 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5662 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5663
5664 /******************* Bit definition for DAC_MCR register *******************/
5665 #define DAC_MCR_MODE1_Pos (0U)
5666 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5667 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5668 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5669 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5670 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5671
5672 #define DAC_MCR_MODE2_Pos (16U)
5673 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5674 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5675 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5676 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5677 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5678
5679 /****************** Bit definition for DAC_SHSR1 register ******************/
5680 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
5681 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5682 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5683
5684 /****************** Bit definition for DAC_SHSR2 register ******************/
5685 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
5686 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
5687 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
5688
5689 /****************** Bit definition for DAC_SHHR register ******************/
5690 #define DAC_SHHR_THOLD1_Pos (0U)
5691 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
5692 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
5693 #define DAC_SHHR_THOLD2_Pos (16U)
5694 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
5695 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
5696
5697 /****************** Bit definition for DAC_SHRR register ******************/
5698 #define DAC_SHRR_TREFRESH1_Pos (0U)
5699 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
5700 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
5701 #define DAC_SHRR_TREFRESH2_Pos (16U)
5702 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
5703 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
5704
5705 /******************************************************************************/
5706 /* */
5707 /* DCMI */
5708 /* */
5709 /******************************************************************************/
5710 /******************** Bits definition for DCMI_CR register ******************/
5711 #define DCMI_CR_CAPTURE_Pos (0U)
5712 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5713 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5714 #define DCMI_CR_CM_Pos (1U)
5715 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5716 #define DCMI_CR_CM DCMI_CR_CM_Msk
5717 #define DCMI_CR_CROP_Pos (2U)
5718 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5719 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5720 #define DCMI_CR_JPEG_Pos (3U)
5721 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5722 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5723 #define DCMI_CR_ESS_Pos (4U)
5724 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5725 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5726 #define DCMI_CR_PCKPOL_Pos (5U)
5727 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5728 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5729 #define DCMI_CR_HSPOL_Pos (6U)
5730 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5731 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5732 #define DCMI_CR_VSPOL_Pos (7U)
5733 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5734 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5735 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
5736 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
5737 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
5738 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
5739 #define DCMI_CR_CRE_Pos (12U)
5740 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5741 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5742 #define DCMI_CR_ENABLE_Pos (14U)
5743 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5744 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5745 #define DCMI_CR_BSM_Pos (16U)
5746 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
5747 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
5748 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
5749 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
5750 #define DCMI_CR_OEBS_Pos (18U)
5751 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
5752 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
5753 #define DCMI_CR_LSM_Pos (19U)
5754 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
5755 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
5756 #define DCMI_CR_OELS_Pos (20U)
5757 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
5758 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
5759
5760 /******************** Bits definition for DCMI_SR register ******************/
5761 #define DCMI_SR_HSYNC_Pos (0U)
5762 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
5763 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
5764 #define DCMI_SR_VSYNC_Pos (1U)
5765 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
5766 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
5767 #define DCMI_SR_FNE_Pos (2U)
5768 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
5769 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
5770
5771 /******************** Bits definition for DCMI_RIS register ****************/
5772 #define DCMI_RIS_FRAME_RIS_Pos (0U)
5773 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
5774 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
5775 #define DCMI_RIS_OVR_RIS_Pos (1U)
5776 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
5777 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
5778 #define DCMI_RIS_ERR_RIS_Pos (2U)
5779 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
5780 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
5781 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
5782 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
5783 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
5784 #define DCMI_RIS_LINE_RIS_Pos (4U)
5785 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
5786 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
5787
5788 /******************** Bits definition for DCMI_IER register *****************/
5789 #define DCMI_IER_FRAME_IE_Pos (0U)
5790 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
5791 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
5792 #define DCMI_IER_OVR_IE_Pos (1U)
5793 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
5794 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
5795 #define DCMI_IER_ERR_IE_Pos (2U)
5796 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
5797 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
5798 #define DCMI_IER_VSYNC_IE_Pos (3U)
5799 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
5800 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
5801 #define DCMI_IER_LINE_IE_Pos (4U)
5802 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
5803 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
5804
5805
5806 /******************** Bits definition for DCMI_MIS register *****************/
5807 #define DCMI_MIS_FRAME_MIS_Pos (0U)
5808 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
5809 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
5810 #define DCMI_MIS_OVR_MIS_Pos (1U)
5811 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
5812 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
5813 #define DCMI_MIS_ERR_MIS_Pos (2U)
5814 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
5815 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
5816 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
5817 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
5818 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
5819 #define DCMI_MIS_LINE_MIS_Pos (4U)
5820 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
5821 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
5822
5823
5824 /******************** Bits definition for DCMI_ICR register *****************/
5825 #define DCMI_ICR_FRAME_ISC_Pos (0U)
5826 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
5827 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
5828 #define DCMI_ICR_OVR_ISC_Pos (1U)
5829 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
5830 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
5831 #define DCMI_ICR_ERR_ISC_Pos (2U)
5832 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
5833 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
5834 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
5835 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
5836 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
5837 #define DCMI_ICR_LINE_ISC_Pos (4U)
5838 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
5839 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
5840
5841
5842 /******************** Bits definition for DCMI_ESCR register ******************/
5843 #define DCMI_ESCR_FSC_Pos (0U)
5844 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
5845 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
5846 #define DCMI_ESCR_LSC_Pos (8U)
5847 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
5848 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
5849 #define DCMI_ESCR_LEC_Pos (16U)
5850 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
5851 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
5852 #define DCMI_ESCR_FEC_Pos (24U)
5853 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
5854 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
5855
5856 /******************** Bits definition for DCMI_ESUR register ******************/
5857 #define DCMI_ESUR_FSU_Pos (0U)
5858 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
5859 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
5860 #define DCMI_ESUR_LSU_Pos (8U)
5861 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
5862 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
5863 #define DCMI_ESUR_LEU_Pos (16U)
5864 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
5865 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
5866 #define DCMI_ESUR_FEU_Pos (24U)
5867 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
5868 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
5869
5870 /******************** Bits definition for DCMI_CWSTRT register ******************/
5871 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
5872 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
5873 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
5874 #define DCMI_CWSTRT_VST_Pos (16U)
5875 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
5876 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
5877
5878 /******************** Bits definition for DCMI_CWSIZE register ******************/
5879 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
5880 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
5881 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
5882 #define DCMI_CWSIZE_VLINE_Pos (16U)
5883 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
5884 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
5885
5886 /******************** Bits definition for DCMI_DR register ******************/
5887 #define DCMI_DR_BYTE0_Pos (0U)
5888 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
5889 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
5890 #define DCMI_DR_BYTE1_Pos (8U)
5891 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
5892 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
5893 #define DCMI_DR_BYTE2_Pos (16U)
5894 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
5895 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
5896 #define DCMI_DR_BYTE3_Pos (24U)
5897 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
5898 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
5899
5900 /******************************************************************************/
5901 /* */
5902 /* Digital Filter for Sigma Delta Modulators */
5903 /* */
5904 /******************************************************************************/
5905
5906 /**************** DFSDM channel configuration registers ********************/
5907
5908 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
5909 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
5910 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
5911 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
5912 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
5913 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
5914 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
5915 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
5916 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
5917 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
5918 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
5919 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
5920 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
5921 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
5922 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
5923 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
5924 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
5925 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
5926 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
5927 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
5928 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
5929 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
5930 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
5931 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
5932 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
5933 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
5934 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
5935 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
5936 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
5937 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
5938 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
5939 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
5940 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
5941 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
5942 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
5943 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
5944 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
5945 #define DFSDM_CHCFGR1_SITP_Pos (0U)
5946 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
5947 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
5948 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
5949 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
5950
5951 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
5952 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
5953 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
5954 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
5955 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
5956 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
5957 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
5958
5959 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
5960 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
5961 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
5962 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
5963 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
5964 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
5965 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
5966 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
5967 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
5968 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
5969 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
5970 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
5971 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
5972 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
5973 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
5974
5975 /**************** Bit definition for DFSDM_CHWDATR register *******************/
5976 #define DFSDM_CHWDATR_WDATA_Pos (0U)
5977 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
5978 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
5979
5980 /**************** Bit definition for DFSDM_CHDATINR register *****************/
5981 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
5982 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
5983 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
5984 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
5985 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
5986 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
5987
5988 /**************** Bit definition for DFSDM_CHDLYR register *****************/
5989 #define DFSDM_CHDLYR_PLSSKP_Pos (0U)
5990 #define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F*/
5991 #define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk
5992 /************************ DFSDM module registers ****************************/
5993
5994 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
5995 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
5996 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
5997 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
5998 #define DFSDM_FLTCR1_FAST_Pos (29U)
5999 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6000 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6001 #define DFSDM_FLTCR1_RCH_Pos (24U)
6002 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6003 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6004 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6005 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6006 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6007 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6008 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6009 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6010 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6011 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6012 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6013 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6014 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6015 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6016 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6017 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6018 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6019 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6020 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6021 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6022 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6023 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6024 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6025 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6026 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6027 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6028 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6029
6030 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6031 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6032 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6033 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6034 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6035 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6036 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6037 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6038 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6039 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6040 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6041 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6042 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6043 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6044 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6045
6046 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6047 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6048 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6049 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6050 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6051 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6052 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6053 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6054 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6055 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6056 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6057 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6058 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6059 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6060 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6061 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6062 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6063 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6064 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6065 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6066 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6067 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6068 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6069 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6070 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6071 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6072 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6073 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6074
6075 /******************** Bit definition for DFSDM_FLTISR register *******************/
6076 #define DFSDM_FLTISR_SCDF_Pos (24U)
6077 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6078 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6079 #define DFSDM_FLTISR_CKABF_Pos (16U)
6080 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6081 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6082 #define DFSDM_FLTISR_RCIP_Pos (14U)
6083 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6084 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6085 #define DFSDM_FLTISR_JCIP_Pos (13U)
6086 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6087 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6088 #define DFSDM_FLTISR_AWDF_Pos (4U)
6089 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6090 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6091 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6092 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6093 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6094 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6095 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6096 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6097 #define DFSDM_FLTISR_REOCF_Pos (1U)
6098 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6099 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6100 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6101 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6102 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6103
6104 /******************** Bit definition for DFSDM_FLTICR register *******************/
6105 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6106 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6107 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6108 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6109 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6110 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6111 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6112 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6113 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6114 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6115 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6116 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6117
6118 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6119 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6120 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6121 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6122
6123 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6124 #define DFSDM_FLTFCR_FORD_Pos (29U)
6125 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6126 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6127 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6128 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6129 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6130 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6131 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6132 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6133 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6134 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6135 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6136
6137 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6138 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6139 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6140 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6141 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6142 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6143 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6144
6145 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6146 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6147 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6148 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6149 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6150 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6151 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6152 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6153 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6154 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6155
6156 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6157 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6158 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6159 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6160 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6161 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6162 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6163
6164 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6165 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6166 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6167 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6168 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6169 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6170 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6171
6172 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6173 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6174 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6175 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6176 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6177 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6178 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6179
6180 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6181 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6182 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6183 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6184 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6185 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6186 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6187
6188 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6189 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6190 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6191 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6192 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6193 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6194 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6195
6196 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6197 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6198 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6199 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6200 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6201 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6202 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6203
6204 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6205 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6206 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6207 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6208
6209 /******************************************************************************/
6210 /* */
6211 /* BDMA Controller */
6212 /* */
6213 /******************************************************************************/
6214
6215 /******************* Bit definition for BDMA_ISR register ********************/
6216 #define BDMA_ISR_GIF0_Pos (0U)
6217 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6218 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6219 #define BDMA_ISR_TCIF0_Pos (1U)
6220 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6221 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6222 #define BDMA_ISR_HTIF0_Pos (2U)
6223 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6224 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6225 #define BDMA_ISR_TEIF0_Pos (3U)
6226 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6227 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6228 #define BDMA_ISR_GIF1_Pos (4U)
6229 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6230 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6231 #define BDMA_ISR_TCIF1_Pos (5U)
6232 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6233 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6234 #define BDMA_ISR_HTIF1_Pos (6U)
6235 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6236 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6237 #define BDMA_ISR_TEIF1_Pos (7U)
6238 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6239 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6240 #define BDMA_ISR_GIF2_Pos (8U)
6241 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6242 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6243 #define BDMA_ISR_TCIF2_Pos (9U)
6244 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6245 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6246 #define BDMA_ISR_HTIF2_Pos (10U)
6247 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6248 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6249 #define BDMA_ISR_TEIF2_Pos (11U)
6250 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6251 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6252 #define BDMA_ISR_GIF3_Pos (12U)
6253 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6254 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6255 #define BDMA_ISR_TCIF3_Pos (13U)
6256 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6257 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6258 #define BDMA_ISR_HTIF3_Pos (14U)
6259 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6260 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6261 #define BDMA_ISR_TEIF3_Pos (15U)
6262 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6263 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6264 #define BDMA_ISR_GIF4_Pos (16U)
6265 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6266 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6267 #define BDMA_ISR_TCIF4_Pos (17U)
6268 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6269 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6270 #define BDMA_ISR_HTIF4_Pos (18U)
6271 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6272 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6273 #define BDMA_ISR_TEIF4_Pos (19U)
6274 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6275 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6276 #define BDMA_ISR_GIF5_Pos (20U)
6277 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6278 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6279 #define BDMA_ISR_TCIF5_Pos (21U)
6280 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6281 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6282 #define BDMA_ISR_HTIF5_Pos (22U)
6283 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6284 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6285 #define BDMA_ISR_TEIF5_Pos (23U)
6286 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6287 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6288 #define BDMA_ISR_GIF6_Pos (24U)
6289 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6290 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6291 #define BDMA_ISR_TCIF6_Pos (25U)
6292 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6293 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6294 #define BDMA_ISR_HTIF6_Pos (26U)
6295 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6296 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6297 #define BDMA_ISR_TEIF6_Pos (27U)
6298 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6299 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6300 #define BDMA_ISR_GIF7_Pos (28U)
6301 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6302 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6303 #define BDMA_ISR_TCIF7_Pos (29U)
6304 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6305 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6306 #define BDMA_ISR_HTIF7_Pos (30U)
6307 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6308 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6309 #define BDMA_ISR_TEIF7_Pos (31U)
6310 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6311 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6312
6313 /******************* Bit definition for BDMA_IFCR register *******************/
6314 #define BDMA_IFCR_CGIF0_Pos (0U)
6315 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6316 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6317 #define BDMA_IFCR_CTCIF0_Pos (1U)
6318 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6319 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6320 #define BDMA_IFCR_CHTIF0_Pos (2U)
6321 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6322 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6323 #define BDMA_IFCR_CTEIF0_Pos (3U)
6324 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6325 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6326 #define BDMA_IFCR_CGIF1_Pos (4U)
6327 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6328 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6329 #define BDMA_IFCR_CTCIF1_Pos (5U)
6330 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6331 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6332 #define BDMA_IFCR_CHTIF1_Pos (6U)
6333 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6334 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6335 #define BDMA_IFCR_CTEIF1_Pos (7U)
6336 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6337 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6338 #define BDMA_IFCR_CGIF2_Pos (8U)
6339 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6340 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6341 #define BDMA_IFCR_CTCIF2_Pos (9U)
6342 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6343 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6344 #define BDMA_IFCR_CHTIF2_Pos (10U)
6345 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6346 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6347 #define BDMA_IFCR_CTEIF2_Pos (11U)
6348 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6349 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6350 #define BDMA_IFCR_CGIF3_Pos (12U)
6351 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6352 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6353 #define BDMA_IFCR_CTCIF3_Pos (13U)
6354 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6355 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6356 #define BDMA_IFCR_CHTIF3_Pos (14U)
6357 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6358 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6359 #define BDMA_IFCR_CTEIF3_Pos (15U)
6360 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6361 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6362 #define BDMA_IFCR_CGIF4_Pos (16U)
6363 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6364 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6365 #define BDMA_IFCR_CTCIF4_Pos (17U)
6366 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6367 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6368 #define BDMA_IFCR_CHTIF4_Pos (18U)
6369 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6370 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6371 #define BDMA_IFCR_CTEIF4_Pos (19U)
6372 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6373 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6374 #define BDMA_IFCR_CGIF5_Pos (20U)
6375 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6376 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6377 #define BDMA_IFCR_CTCIF5_Pos (21U)
6378 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6379 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6380 #define BDMA_IFCR_CHTIF5_Pos (22U)
6381 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6382 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6383 #define BDMA_IFCR_CTEIF5_Pos (23U)
6384 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6385 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6386 #define BDMA_IFCR_CGIF6_Pos (24U)
6387 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6388 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6389 #define BDMA_IFCR_CTCIF6_Pos (25U)
6390 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6391 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6392 #define BDMA_IFCR_CHTIF6_Pos (26U)
6393 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6394 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6395 #define BDMA_IFCR_CTEIF6_Pos (27U)
6396 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6397 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6398 #define BDMA_IFCR_CGIF7_Pos (28U)
6399 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6400 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6401 #define BDMA_IFCR_CTCIF7_Pos (29U)
6402 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6403 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6404 #define BDMA_IFCR_CHTIF7_Pos (30U)
6405 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6406 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6407 #define BDMA_IFCR_CTEIF7_Pos (31U)
6408 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6409 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6410
6411 /******************* Bit definition for BDMA_CCR register ********************/
6412 #define BDMA_CCR_EN_Pos (0U)
6413 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6414 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6415 #define BDMA_CCR_TCIE_Pos (1U)
6416 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6417 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6418 #define BDMA_CCR_HTIE_Pos (2U)
6419 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6420 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6421 #define BDMA_CCR_TEIE_Pos (3U)
6422 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6423 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6424 #define BDMA_CCR_DIR_Pos (4U)
6425 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6426 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6427 #define BDMA_CCR_CIRC_Pos (5U)
6428 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6429 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6430 #define BDMA_CCR_PINC_Pos (6U)
6431 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6432 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6433 #define BDMA_CCR_MINC_Pos (7U)
6434 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6435 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6436
6437 #define BDMA_CCR_PSIZE_Pos (8U)
6438 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6439 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6440 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6441 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6442
6443 #define BDMA_CCR_MSIZE_Pos (10U)
6444 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6445 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6446 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6447 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6448
6449 #define BDMA_CCR_PL_Pos (12U)
6450 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6451 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6452 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6453 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6454
6455 #define BDMA_CCR_MEM2MEM_Pos (14U)
6456 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6457 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6458 #define BDMA_CCR_DBM_Pos (15U)
6459 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6460 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6461 #define BDMA_CCR_CT_Pos (16U)
6462 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6463 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6464
6465 /****************** Bit definition for BDMA_CNDTR register *******************/
6466 #define BDMA_CNDTR_NDT_Pos (0U)
6467 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6468 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6469
6470 /****************** Bit definition for BDMA_CPAR register ********************/
6471 #define BDMA_CPAR_PA_Pos (0U)
6472 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6473 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6474
6475 /****************** Bit definition for BDMA_CM0AR register ********************/
6476 #define BDMA_CM0AR_MA_Pos (0U)
6477 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6478 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6479
6480 /****************** Bit definition for BDMA_CM1AR register ********************/
6481 #define BDMA_CM1AR_MA_Pos (0U)
6482 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6483 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6484
6485 /******************************************************************************/
6486 /* */
6487 /* DMA Controller */
6488 /* */
6489 /******************************************************************************/
6490 /******************** Bits definition for DMA_SxCR register *****************/
6491 #define DMA_SxCR_MBURST_Pos (23U)
6492 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6493 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
6494 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6495 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6496 #define DMA_SxCR_PBURST_Pos (21U)
6497 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6498 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
6499 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6500 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6501 #define DMA_SxCR_CT_Pos (19U)
6502 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6503 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
6504 #define DMA_SxCR_DBM_Pos (18U)
6505 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6506 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
6507 #define DMA_SxCR_PL_Pos (16U)
6508 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6509 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
6510 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6511 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6512 #define DMA_SxCR_PINCOS_Pos (15U)
6513 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6514 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
6515 #define DMA_SxCR_MSIZE_Pos (13U)
6516 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6517 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
6518 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6519 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6520 #define DMA_SxCR_PSIZE_Pos (11U)
6521 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6522 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
6523 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6524 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6525 #define DMA_SxCR_MINC_Pos (10U)
6526 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6527 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
6528 #define DMA_SxCR_PINC_Pos (9U)
6529 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6530 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
6531 #define DMA_SxCR_CIRC_Pos (8U)
6532 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6533 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
6534 #define DMA_SxCR_DIR_Pos (6U)
6535 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6536 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
6537 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6538 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6539 #define DMA_SxCR_PFCTRL_Pos (5U)
6540 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6541 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
6542 #define DMA_SxCR_TCIE_Pos (4U)
6543 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6544 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6545 #define DMA_SxCR_HTIE_Pos (3U)
6546 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6547 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
6548 #define DMA_SxCR_TEIE_Pos (2U)
6549 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6550 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
6551 #define DMA_SxCR_DMEIE_Pos (1U)
6552 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6553 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
6554 #define DMA_SxCR_EN_Pos (0U)
6555 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6556 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
6557
6558 /******************** Bits definition for DMA_SxCNDTR register **************/
6559 #define DMA_SxNDT_Pos (0U)
6560 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6561 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
6562 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
6563 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
6564 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
6565 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
6566 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
6567 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
6568 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
6569 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
6570 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
6571 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
6572 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
6573 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
6574 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
6575 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
6576 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
6577 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
6578
6579 /******************** Bits definition for DMA_SxFCR register ****************/
6580 #define DMA_SxFCR_FEIE_Pos (7U)
6581 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6582 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
6583 #define DMA_SxFCR_FS_Pos (3U)
6584 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6585 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
6586 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6587 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6588 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6589 #define DMA_SxFCR_DMDIS_Pos (2U)
6590 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6591 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
6592 #define DMA_SxFCR_FTH_Pos (0U)
6593 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6594 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
6595 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6596 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6597
6598 /******************** Bits definition for DMA_LISR register *****************/
6599 #define DMA_LISR_TCIF3_Pos (27U)
6600 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6601 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
6602 #define DMA_LISR_HTIF3_Pos (26U)
6603 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6604 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
6605 #define DMA_LISR_TEIF3_Pos (25U)
6606 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6607 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
6608 #define DMA_LISR_DMEIF3_Pos (24U)
6609 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6610 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
6611 #define DMA_LISR_FEIF3_Pos (22U)
6612 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6613 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
6614 #define DMA_LISR_TCIF2_Pos (21U)
6615 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6616 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
6617 #define DMA_LISR_HTIF2_Pos (20U)
6618 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6619 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
6620 #define DMA_LISR_TEIF2_Pos (19U)
6621 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6622 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
6623 #define DMA_LISR_DMEIF2_Pos (18U)
6624 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6625 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
6626 #define DMA_LISR_FEIF2_Pos (16U)
6627 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6628 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
6629 #define DMA_LISR_TCIF1_Pos (11U)
6630 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6631 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
6632 #define DMA_LISR_HTIF1_Pos (10U)
6633 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6634 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
6635 #define DMA_LISR_TEIF1_Pos (9U)
6636 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6637 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
6638 #define DMA_LISR_DMEIF1_Pos (8U)
6639 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6640 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
6641 #define DMA_LISR_FEIF1_Pos (6U)
6642 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6643 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
6644 #define DMA_LISR_TCIF0_Pos (5U)
6645 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6646 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
6647 #define DMA_LISR_HTIF0_Pos (4U)
6648 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6649 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
6650 #define DMA_LISR_TEIF0_Pos (3U)
6651 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6652 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
6653 #define DMA_LISR_DMEIF0_Pos (2U)
6654 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6655 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
6656 #define DMA_LISR_FEIF0_Pos (0U)
6657 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6658 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
6659
6660 /******************** Bits definition for DMA_HISR register *****************/
6661 #define DMA_HISR_TCIF7_Pos (27U)
6662 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6663 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
6664 #define DMA_HISR_HTIF7_Pos (26U)
6665 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6666 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
6667 #define DMA_HISR_TEIF7_Pos (25U)
6668 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6669 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
6670 #define DMA_HISR_DMEIF7_Pos (24U)
6671 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6672 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
6673 #define DMA_HISR_FEIF7_Pos (22U)
6674 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6675 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
6676 #define DMA_HISR_TCIF6_Pos (21U)
6677 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6678 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
6679 #define DMA_HISR_HTIF6_Pos (20U)
6680 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6681 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
6682 #define DMA_HISR_TEIF6_Pos (19U)
6683 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6684 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
6685 #define DMA_HISR_DMEIF6_Pos (18U)
6686 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6687 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
6688 #define DMA_HISR_FEIF6_Pos (16U)
6689 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6690 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
6691 #define DMA_HISR_TCIF5_Pos (11U)
6692 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6693 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
6694 #define DMA_HISR_HTIF5_Pos (10U)
6695 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6696 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
6697 #define DMA_HISR_TEIF5_Pos (9U)
6698 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6699 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
6700 #define DMA_HISR_DMEIF5_Pos (8U)
6701 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6702 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
6703 #define DMA_HISR_FEIF5_Pos (6U)
6704 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6705 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
6706 #define DMA_HISR_TCIF4_Pos (5U)
6707 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6708 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
6709 #define DMA_HISR_HTIF4_Pos (4U)
6710 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6711 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
6712 #define DMA_HISR_TEIF4_Pos (3U)
6713 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6714 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
6715 #define DMA_HISR_DMEIF4_Pos (2U)
6716 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6717 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
6718 #define DMA_HISR_FEIF4_Pos (0U)
6719 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6720 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
6721
6722 /******************** Bits definition for DMA_LIFCR register ****************/
6723 #define DMA_LIFCR_CTCIF3_Pos (27U)
6724 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6725 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
6726 #define DMA_LIFCR_CHTIF3_Pos (26U)
6727 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6728 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
6729 #define DMA_LIFCR_CTEIF3_Pos (25U)
6730 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6731 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
6732 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6733 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6734 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
6735 #define DMA_LIFCR_CFEIF3_Pos (22U)
6736 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6737 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
6738 #define DMA_LIFCR_CTCIF2_Pos (21U)
6739 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6740 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
6741 #define DMA_LIFCR_CHTIF2_Pos (20U)
6742 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6743 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
6744 #define DMA_LIFCR_CTEIF2_Pos (19U)
6745 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
6746 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
6747 #define DMA_LIFCR_CDMEIF2_Pos (18U)
6748 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
6749 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
6750 #define DMA_LIFCR_CFEIF2_Pos (16U)
6751 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
6752 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
6753 #define DMA_LIFCR_CTCIF1_Pos (11U)
6754 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
6755 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
6756 #define DMA_LIFCR_CHTIF1_Pos (10U)
6757 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
6758 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
6759 #define DMA_LIFCR_CTEIF1_Pos (9U)
6760 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
6761 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
6762 #define DMA_LIFCR_CDMEIF1_Pos (8U)
6763 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
6764 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
6765 #define DMA_LIFCR_CFEIF1_Pos (6U)
6766 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
6767 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
6768 #define DMA_LIFCR_CTCIF0_Pos (5U)
6769 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
6770 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
6771 #define DMA_LIFCR_CHTIF0_Pos (4U)
6772 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
6773 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
6774 #define DMA_LIFCR_CTEIF0_Pos (3U)
6775 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
6776 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
6777 #define DMA_LIFCR_CDMEIF0_Pos (2U)
6778 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
6779 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
6780 #define DMA_LIFCR_CFEIF0_Pos (0U)
6781 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
6782 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
6783
6784 /******************** Bits definition for DMA_HIFCR register ****************/
6785 #define DMA_HIFCR_CTCIF7_Pos (27U)
6786 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
6787 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
6788 #define DMA_HIFCR_CHTIF7_Pos (26U)
6789 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
6790 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
6791 #define DMA_HIFCR_CTEIF7_Pos (25U)
6792 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
6793 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
6794 #define DMA_HIFCR_CDMEIF7_Pos (24U)
6795 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
6796 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
6797 #define DMA_HIFCR_CFEIF7_Pos (22U)
6798 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
6799 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
6800 #define DMA_HIFCR_CTCIF6_Pos (21U)
6801 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
6802 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
6803 #define DMA_HIFCR_CHTIF6_Pos (20U)
6804 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
6805 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
6806 #define DMA_HIFCR_CTEIF6_Pos (19U)
6807 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
6808 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
6809 #define DMA_HIFCR_CDMEIF6_Pos (18U)
6810 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
6811 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
6812 #define DMA_HIFCR_CFEIF6_Pos (16U)
6813 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
6814 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
6815 #define DMA_HIFCR_CTCIF5_Pos (11U)
6816 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
6817 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
6818 #define DMA_HIFCR_CHTIF5_Pos (10U)
6819 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
6820 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
6821 #define DMA_HIFCR_CTEIF5_Pos (9U)
6822 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
6823 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
6824 #define DMA_HIFCR_CDMEIF5_Pos (8U)
6825 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
6826 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
6827 #define DMA_HIFCR_CFEIF5_Pos (6U)
6828 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
6829 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
6830 #define DMA_HIFCR_CTCIF4_Pos (5U)
6831 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
6832 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
6833 #define DMA_HIFCR_CHTIF4_Pos (4U)
6834 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
6835 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
6836 #define DMA_HIFCR_CTEIF4_Pos (3U)
6837 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
6838 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
6839 #define DMA_HIFCR_CDMEIF4_Pos (2U)
6840 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
6841 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
6842 #define DMA_HIFCR_CFEIF4_Pos (0U)
6843 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
6844 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
6845
6846 /****************** Bit definition for DMA_SxPAR register ********************/
6847 #define DMA_SxPAR_PA_Pos (0U)
6848 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
6849 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
6850
6851 /****************** Bit definition for DMA_SxM0AR register ********************/
6852 #define DMA_SxM0AR_M0A_Pos (0U)
6853 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
6854 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
6855
6856 /****************** Bit definition for DMA_SxM1AR register ********************/
6857 #define DMA_SxM1AR_M1A_Pos (0U)
6858 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
6859 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
6860
6861 /******************************************************************************/
6862 /* */
6863 /* DMAMUX Controller */
6864 /* */
6865 /******************************************************************************/
6866 /******************** Bits definition for DMAMUX_CxCR register **************/
6867 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
6868 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
6869 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
6870 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
6871 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
6872 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
6873 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
6874 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
6875 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
6876 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
6877 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
6878 #define DMAMUX_CxCR_SOIE_Pos (8U)
6879 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
6880 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
6881 #define DMAMUX_CxCR_EGE_Pos (9U)
6882 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
6883 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
6884 #define DMAMUX_CxCR_SE_Pos (16U)
6885 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
6886 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
6887 #define DMAMUX_CxCR_SPOL_Pos (17U)
6888 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
6889 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
6890 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
6891 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
6892 #define DMAMUX_CxCR_NBREQ_Pos (19U)
6893 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
6894 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
6895 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
6896 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
6897 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
6898 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
6899 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
6900 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
6901 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
6902 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
6903 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
6904 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
6905 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
6906 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
6907 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
6908
6909 /******************** Bits definition for DMAMUX_CSR register **************/
6910 #define DMAMUX_CSR_SOF0_Pos (0U)
6911 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
6912 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
6913 #define DMAMUX_CSR_SOF1_Pos (1U)
6914 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
6915 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
6916 #define DMAMUX_CSR_SOF2_Pos (2U)
6917 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
6918 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
6919 #define DMAMUX_CSR_SOF3_Pos (3U)
6920 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
6921 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
6922 #define DMAMUX_CSR_SOF4_Pos (4U)
6923 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
6924 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
6925 #define DMAMUX_CSR_SOF5_Pos (5U)
6926 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
6927 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
6928 #define DMAMUX_CSR_SOF6_Pos (6U)
6929 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
6930 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
6931 #define DMAMUX_CSR_SOF7_Pos (7U)
6932 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
6933 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
6934 #define DMAMUX_CSR_SOF8_Pos (8U)
6935 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
6936 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
6937 #define DMAMUX_CSR_SOF9_Pos (9U)
6938 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
6939 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
6940 #define DMAMUX_CSR_SOF10_Pos (10U)
6941 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
6942 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
6943 #define DMAMUX_CSR_SOF11_Pos (11U)
6944 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
6945 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
6946 #define DMAMUX_CSR_SOF12_Pos (12U)
6947 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
6948 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
6949 #define DMAMUX_CSR_SOF13_Pos (13U)
6950 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
6951 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
6952 #define DMAMUX_CSR_SOF14_Pos (14U)
6953 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
6954 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
6955 #define DMAMUX_CSR_SOF15_Pos (15U)
6956 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
6957 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
6958
6959 /******************** Bits definition for DMAMUX_CFR register **************/
6960 #define DMAMUX_CFR_CSOF0_Pos (0U)
6961 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
6962 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
6963 #define DMAMUX_CFR_CSOF1_Pos (1U)
6964 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
6965 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
6966 #define DMAMUX_CFR_CSOF2_Pos (2U)
6967 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
6968 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
6969 #define DMAMUX_CFR_CSOF3_Pos (3U)
6970 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
6971 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
6972 #define DMAMUX_CFR_CSOF4_Pos (4U)
6973 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
6974 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
6975 #define DMAMUX_CFR_CSOF5_Pos (5U)
6976 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
6977 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
6978 #define DMAMUX_CFR_CSOF6_Pos (6U)
6979 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
6980 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
6981 #define DMAMUX_CFR_CSOF7_Pos (7U)
6982 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
6983 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
6984 #define DMAMUX_CFR_CSOF8_Pos (8U)
6985 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
6986 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
6987 #define DMAMUX_CFR_CSOF9_Pos (9U)
6988 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
6989 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
6990 #define DMAMUX_CFR_CSOF10_Pos (10U)
6991 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
6992 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
6993 #define DMAMUX_CFR_CSOF11_Pos (11U)
6994 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
6995 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
6996 #define DMAMUX_CFR_CSOF12_Pos (12U)
6997 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
6998 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
6999 #define DMAMUX_CFR_CSOF13_Pos (13U)
7000 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
7001 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
7002 #define DMAMUX_CFR_CSOF14_Pos (14U)
7003 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
7004 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
7005 #define DMAMUX_CFR_CSOF15_Pos (15U)
7006 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
7007 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
7008
7009 /******************** Bits definition for DMAMUX_RGxCR register ************/
7010 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
7011 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
7012 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
7013 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
7014 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
7015 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
7016 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
7017 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
7018 #define DMAMUX_RGxCR_OIE_Pos (8U)
7019 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
7020 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
7021 #define DMAMUX_RGxCR_GE_Pos (16U)
7022 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
7023 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
7024 #define DMAMUX_RGxCR_GPOL_Pos (17U)
7025 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
7026 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
7027 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
7028 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
7029 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
7030 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
7031 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
7032 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
7033 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
7034 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
7035 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
7036 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
7037
7038 /******************** Bits definition for DMAMUX_RGSR register **************/
7039 #define DMAMUX_RGSR_OF0_Pos (0U)
7040 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
7041 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
7042 #define DMAMUX_RGSR_OF1_Pos (1U)
7043 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
7044 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
7045 #define DMAMUX_RGSR_OF2_Pos (2U)
7046 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
7047 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
7048 #define DMAMUX_RGSR_OF3_Pos (3U)
7049 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
7050 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
7051 #define DMAMUX_RGSR_OF4_Pos (4U)
7052 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
7053 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
7054 #define DMAMUX_RGSR_OF5_Pos (5U)
7055 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
7056 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
7057 #define DMAMUX_RGSR_OF6_Pos (6U)
7058 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
7059 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
7060 #define DMAMUX_RGSR_OF7_Pos (7U)
7061 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
7062 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
7063
7064 /******************** Bits definition for DMAMUX_RGCFR register **************/
7065 #define DMAMUX_RGCFR_COF0_Pos (0U)
7066 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
7067 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
7068 #define DMAMUX_RGCFR_COF1_Pos (1U)
7069 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
7070 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
7071 #define DMAMUX_RGCFR_COF2_Pos (2U)
7072 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
7073 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
7074 #define DMAMUX_RGCFR_COF3_Pos (3U)
7075 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
7076 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
7077 #define DMAMUX_RGCFR_COF4_Pos (4U)
7078 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
7079 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
7080 #define DMAMUX_RGCFR_COF5_Pos (5U)
7081 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
7082 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
7083 #define DMAMUX_RGCFR_COF6_Pos (6U)
7084 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
7085 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
7086 #define DMAMUX_RGCFR_COF7_Pos (7U)
7087 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
7088 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
7089
7090 /******************************************************************************/
7091 /* */
7092 /* AHB Master DMA2D Controller (DMA2D) */
7093 /* */
7094 /******************************************************************************/
7095
7096 /******************** Bit definition for DMA2D_CR register ******************/
7097
7098 #define DMA2D_CR_START_Pos (0U)
7099 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
7100 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
7101 #define DMA2D_CR_SUSP_Pos (1U)
7102 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
7103 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
7104 #define DMA2D_CR_ABORT_Pos (2U)
7105 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
7106 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
7107 #define DMA2D_CR_LOM_Pos (6U)
7108 #define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
7109 #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
7110 #define DMA2D_CR_TEIE_Pos (8U)
7111 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
7112 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
7113 #define DMA2D_CR_TCIE_Pos (9U)
7114 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
7115 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
7116 #define DMA2D_CR_TWIE_Pos (10U)
7117 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
7118 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
7119 #define DMA2D_CR_CAEIE_Pos (11U)
7120 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
7121 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
7122 #define DMA2D_CR_CTCIE_Pos (12U)
7123 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
7124 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
7125 #define DMA2D_CR_CEIE_Pos (13U)
7126 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
7127 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
7128 #define DMA2D_CR_MODE_Pos (16U)
7129 #define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
7130 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
7131 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
7132 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
7133 #define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
7134
7135 /******************** Bit definition for DMA2D_ISR register *****************/
7136
7137 #define DMA2D_ISR_TEIF_Pos (0U)
7138 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
7139 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
7140 #define DMA2D_ISR_TCIF_Pos (1U)
7141 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
7142 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
7143 #define DMA2D_ISR_TWIF_Pos (2U)
7144 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
7145 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
7146 #define DMA2D_ISR_CAEIF_Pos (3U)
7147 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
7148 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
7149 #define DMA2D_ISR_CTCIF_Pos (4U)
7150 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
7151 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
7152 #define DMA2D_ISR_CEIF_Pos (5U)
7153 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
7154 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
7155
7156 /******************** Bit definition for DMA2D_IFCR register ****************/
7157
7158 #define DMA2D_IFCR_CTEIF_Pos (0U)
7159 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
7160 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
7161 #define DMA2D_IFCR_CTCIF_Pos (1U)
7162 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
7163 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7164 #define DMA2D_IFCR_CTWIF_Pos (2U)
7165 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7166 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7167 #define DMA2D_IFCR_CAECIF_Pos (3U)
7168 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7169 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7170 #define DMA2D_IFCR_CCTCIF_Pos (4U)
7171 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7172 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7173 #define DMA2D_IFCR_CCEIF_Pos (5U)
7174 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7175 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7176
7177 /******************** Bit definition for DMA2D_FGMAR register ***************/
7178
7179 #define DMA2D_FGMAR_MA_Pos (0U)
7180 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7181 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
7182
7183 /******************** Bit definition for DMA2D_FGOR register ****************/
7184
7185 #define DMA2D_FGOR_LO_Pos (0U)
7186 #define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
7187 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7188
7189 /******************** Bit definition for DMA2D_BGMAR register ***************/
7190
7191 #define DMA2D_BGMAR_MA_Pos (0U)
7192 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7193 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
7194
7195 /******************** Bit definition for DMA2D_BGOR register ****************/
7196
7197 #define DMA2D_BGOR_LO_Pos (0U)
7198 #define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
7199 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7200
7201 /******************** Bit definition for DMA2D_FGPFCCR register *************/
7202
7203 #define DMA2D_FGPFCCR_CM_Pos (0U)
7204 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7205 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7206 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7207 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7208 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7209 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7210 #define DMA2D_FGPFCCR_CCM_Pos (4U)
7211 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7212 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7213 #define DMA2D_FGPFCCR_START_Pos (5U)
7214 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7215 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7216 #define DMA2D_FGPFCCR_CS_Pos (8U)
7217 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7218 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7219 #define DMA2D_FGPFCCR_AM_Pos (16U)
7220 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
7221 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7222 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
7223 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
7224 #define DMA2D_FGPFCCR_CSS_Pos (18U)
7225 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
7226 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
7227 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
7228 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
7229 #define DMA2D_FGPFCCR_AI_Pos (20U)
7230 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
7231 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
7232 #define DMA2D_FGPFCCR_RBS_Pos (21U)
7233 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
7234 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
7235 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7236 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7237 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
7238
7239 /******************** Bit definition for DMA2D_FGCOLR register **************/
7240
7241 #define DMA2D_FGCOLR_BLUE_Pos (0U)
7242 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
7243 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
7244 #define DMA2D_FGCOLR_GREEN_Pos (8U)
7245 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7246 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
7247 #define DMA2D_FGCOLR_RED_Pos (16U)
7248 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
7249 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
7250
7251 /******************** Bit definition for DMA2D_BGPFCCR register *************/
7252
7253 #define DMA2D_BGPFCCR_CM_Pos (0U)
7254 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
7255 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7256 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
7257 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
7258 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
7259 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
7260 #define DMA2D_BGPFCCR_CCM_Pos (4U)
7261 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
7262 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
7263 #define DMA2D_BGPFCCR_START_Pos (5U)
7264 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
7265 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
7266 #define DMA2D_BGPFCCR_CS_Pos (8U)
7267 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7268 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
7269 #define DMA2D_BGPFCCR_AM_Pos (16U)
7270 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
7271 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7272 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
7273 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
7274 #define DMA2D_BGPFCCR_AI_Pos (20U)
7275 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
7276 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
7277 #define DMA2D_BGPFCCR_RBS_Pos (21U)
7278 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
7279 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
7280 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7281 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7282 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
7283
7284 /******************** Bit definition for DMA2D_BGCOLR register **************/
7285
7286 #define DMA2D_BGCOLR_BLUE_Pos (0U)
7287 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
7288 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
7289 #define DMA2D_BGCOLR_GREEN_Pos (8U)
7290 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7291 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
7292 #define DMA2D_BGCOLR_RED_Pos (16U)
7293 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
7294 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
7295
7296 /******************** Bit definition for DMA2D_FGCMAR register **************/
7297
7298 #define DMA2D_FGCMAR_MA_Pos (0U)
7299 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7300 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
7301
7302 /******************** Bit definition for DMA2D_BGCMAR register **************/
7303
7304 #define DMA2D_BGCMAR_MA_Pos (0U)
7305 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7306 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
7307
7308 /******************** Bit definition for DMA2D_OPFCCR register **************/
7309
7310 #define DMA2D_OPFCCR_CM_Pos (0U)
7311 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
7312 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
7313 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
7314 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
7315 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
7316 #define DMA2D_OPFCCR_SB_Pos (8U)
7317 #define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
7318 #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
7319 #define DMA2D_OPFCCR_AI_Pos (20U)
7320 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
7321 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
7322 #define DMA2D_OPFCCR_RBS_Pos (21U)
7323 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
7324 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
7325
7326 /******************** Bit definition for DMA2D_OCOLR register ***************/
7327
7328 /*!<Mode_ARGB8888/RGB888 */
7329
7330 #define DMA2D_OCOLR_BLUE_1_Pos (0U)
7331 #define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
7332 #define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
7333 #define DMA2D_OCOLR_GREEN_1_Pos (8U)
7334 #define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
7335 #define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
7336 #define DMA2D_OCOLR_RED_1_Pos (16U)
7337 #define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
7338 #define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
7339 #define DMA2D_OCOLR_ALPHA_1_Pos (24U)
7340 #define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
7341 #define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
7342
7343 /*!<Mode_RGB565 */
7344 #define DMA2D_OCOLR_BLUE_2_Pos (0U)
7345 #define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
7346 #define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
7347 #define DMA2D_OCOLR_GREEN_2_Pos (5U)
7348 #define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
7349 #define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
7350 #define DMA2D_OCOLR_RED_2_Pos (11U)
7351 #define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
7352 #define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
7353
7354 /*!<Mode_ARGB1555 */
7355 #define DMA2D_OCOLR_BLUE_3_Pos (0U)
7356 #define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
7357 #define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
7358 #define DMA2D_OCOLR_GREEN_3_Pos (5U)
7359 #define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
7360 #define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
7361 #define DMA2D_OCOLR_RED_3_Pos (10U)
7362 #define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
7363 #define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
7364 #define DMA2D_OCOLR_ALPHA_3_Pos (15U)
7365 #define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
7366 #define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
7367
7368 /*!<Mode_ARGB4444 */
7369 #define DMA2D_OCOLR_BLUE_4_Pos (0U)
7370 #define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
7371 #define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
7372 #define DMA2D_OCOLR_GREEN_4_Pos (4U)
7373 #define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
7374 #define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
7375 #define DMA2D_OCOLR_RED_4_Pos (8U)
7376 #define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
7377 #define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
7378 #define DMA2D_OCOLR_ALPHA_4_Pos (12U)
7379 #define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
7380 #define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
7381
7382 /******************** Bit definition for DMA2D_OMAR register ****************/
7383
7384 #define DMA2D_OMAR_MA_Pos (0U)
7385 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
7386 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
7387
7388 /******************** Bit definition for DMA2D_OOR register *****************/
7389
7390 #define DMA2D_OOR_LO_Pos (0U)
7391 #define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
7392 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
7393
7394 /******************** Bit definition for DMA2D_NLR register *****************/
7395
7396 #define DMA2D_NLR_NL_Pos (0U)
7397 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
7398 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
7399 #define DMA2D_NLR_PL_Pos (16U)
7400 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
7401 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
7402
7403 /******************** Bit definition for DMA2D_LWR register *****************/
7404
7405 #define DMA2D_LWR_LW_Pos (0U)
7406 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
7407 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
7408
7409 /******************** Bit definition for DMA2D_AMTCR register ***************/
7410
7411 #define DMA2D_AMTCR_EN_Pos (0U)
7412 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
7413 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
7414 #define DMA2D_AMTCR_DT_Pos (8U)
7415 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
7416 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
7417
7418
7419 /******************** Bit definition for DMA2D_FGCLUT register **************/
7420
7421 /******************** Bit definition for DMA2D_BGCLUT register **************/
7422
7423
7424 /******************************************************************************/
7425 /* */
7426 /* External Interrupt/Event Controller */
7427 /* */
7428 /******************************************************************************/
7429 /****************** Bit definition for EXTI_RTSR1 register *******************/
7430 #define EXTI_RTSR1_TR_Pos (0U)
7431 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
7432 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
7433 #define EXTI_RTSR1_TR0_Pos (0U)
7434 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
7435 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7436 #define EXTI_RTSR1_TR1_Pos (1U)
7437 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
7438 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7439 #define EXTI_RTSR1_TR2_Pos (2U)
7440 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
7441 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7442 #define EXTI_RTSR1_TR3_Pos (3U)
7443 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
7444 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7445 #define EXTI_RTSR1_TR4_Pos (4U)
7446 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
7447 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7448 #define EXTI_RTSR1_TR5_Pos (5U)
7449 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
7450 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7451 #define EXTI_RTSR1_TR6_Pos (6U)
7452 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
7453 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7454 #define EXTI_RTSR1_TR7_Pos (7U)
7455 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
7456 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7457 #define EXTI_RTSR1_TR8_Pos (8U)
7458 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
7459 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7460 #define EXTI_RTSR1_TR9_Pos (9U)
7461 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
7462 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7463 #define EXTI_RTSR1_TR10_Pos (10U)
7464 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
7465 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7466 #define EXTI_RTSR1_TR11_Pos (11U)
7467 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
7468 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7469 #define EXTI_RTSR1_TR12_Pos (12U)
7470 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
7471 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7472 #define EXTI_RTSR1_TR13_Pos (13U)
7473 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
7474 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7475 #define EXTI_RTSR1_TR14_Pos (14U)
7476 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
7477 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7478 #define EXTI_RTSR1_TR15_Pos (15U)
7479 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
7480 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7481 #define EXTI_RTSR1_TR16_Pos (16U)
7482 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
7483 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7484 #define EXTI_RTSR1_TR17_Pos (17U)
7485 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
7486 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7487 #define EXTI_RTSR1_TR18_Pos (18U)
7488 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
7489 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7490 #define EXTI_RTSR1_TR19_Pos (19U)
7491 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
7492 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7493 #define EXTI_RTSR1_TR20_Pos (20U)
7494 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
7495 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7496 #define EXTI_RTSR1_TR21_Pos (21U)
7497 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
7498 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7499
7500 /****************** Bit definition for EXTI_FTSR1 register *******************/
7501 #define EXTI_FTSR1_TR_Pos (0U)
7502 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
7503 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
7504 #define EXTI_FTSR1_TR0_Pos (0U)
7505 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
7506 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7507 #define EXTI_FTSR1_TR1_Pos (1U)
7508 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
7509 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7510 #define EXTI_FTSR1_TR2_Pos (2U)
7511 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
7512 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7513 #define EXTI_FTSR1_TR3_Pos (3U)
7514 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
7515 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7516 #define EXTI_FTSR1_TR4_Pos (4U)
7517 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
7518 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7519 #define EXTI_FTSR1_TR5_Pos (5U)
7520 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
7521 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7522 #define EXTI_FTSR1_TR6_Pos (6U)
7523 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
7524 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7525 #define EXTI_FTSR1_TR7_Pos (7U)
7526 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
7527 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7528 #define EXTI_FTSR1_TR8_Pos (8U)
7529 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
7530 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7531 #define EXTI_FTSR1_TR9_Pos (9U)
7532 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
7533 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7534 #define EXTI_FTSR1_TR10_Pos (10U)
7535 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
7536 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7537 #define EXTI_FTSR1_TR11_Pos (11U)
7538 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
7539 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7540 #define EXTI_FTSR1_TR12_Pos (12U)
7541 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
7542 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7543 #define EXTI_FTSR1_TR13_Pos (13U)
7544 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
7545 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7546 #define EXTI_FTSR1_TR14_Pos (14U)
7547 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
7548 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7549 #define EXTI_FTSR1_TR15_Pos (15U)
7550 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
7551 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7552 #define EXTI_FTSR1_TR16_Pos (16U)
7553 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
7554 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7555 #define EXTI_FTSR1_TR17_Pos (17U)
7556 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
7557 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7558 #define EXTI_FTSR1_TR18_Pos (18U)
7559 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
7560 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7561 #define EXTI_FTSR1_TR19_Pos (19U)
7562 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
7563 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7564 #define EXTI_FTSR1_TR20_Pos (20U)
7565 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
7566 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7567 #define EXTI_FTSR1_TR21_Pos (21U)
7568 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
7569 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7570
7571 /****************** Bit definition for EXTI_SWIER1 register ******************/
7572 #define EXTI_SWIER1_SWIER0_Pos (0U)
7573 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
7574 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
7575 #define EXTI_SWIER1_SWIER1_Pos (1U)
7576 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
7577 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
7578 #define EXTI_SWIER1_SWIER2_Pos (2U)
7579 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
7580 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
7581 #define EXTI_SWIER1_SWIER3_Pos (3U)
7582 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
7583 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
7584 #define EXTI_SWIER1_SWIER4_Pos (4U)
7585 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
7586 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
7587 #define EXTI_SWIER1_SWIER5_Pos (5U)
7588 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
7589 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
7590 #define EXTI_SWIER1_SWIER6_Pos (6U)
7591 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
7592 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
7593 #define EXTI_SWIER1_SWIER7_Pos (7U)
7594 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
7595 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
7596 #define EXTI_SWIER1_SWIER8_Pos (8U)
7597 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
7598 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
7599 #define EXTI_SWIER1_SWIER9_Pos (9U)
7600 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
7601 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
7602 #define EXTI_SWIER1_SWIER10_Pos (10U)
7603 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
7604 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
7605 #define EXTI_SWIER1_SWIER11_Pos (11U)
7606 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
7607 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
7608 #define EXTI_SWIER1_SWIER12_Pos (12U)
7609 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
7610 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
7611 #define EXTI_SWIER1_SWIER13_Pos (13U)
7612 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
7613 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
7614 #define EXTI_SWIER1_SWIER14_Pos (14U)
7615 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
7616 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
7617 #define EXTI_SWIER1_SWIER15_Pos (15U)
7618 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
7619 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
7620 #define EXTI_SWIER1_SWIER16_Pos (16U)
7621 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
7622 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
7623 #define EXTI_SWIER1_SWIER17_Pos (17U)
7624 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
7625 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
7626 #define EXTI_SWIER1_SWIER18_Pos (18U)
7627 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
7628 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
7629 #define EXTI_SWIER1_SWIER19_Pos (19U)
7630 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
7631 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
7632 #define EXTI_SWIER1_SWIER20_Pos (20U)
7633 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
7634 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
7635 #define EXTI_SWIER1_SWIER21_Pos (21U)
7636 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
7637 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
7638
7639 /****************** Bit definition for EXTI_D3PMR1 register ******************/
7640 #define EXTI_D3PMR1_MR0_Pos (0U)
7641 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
7642 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
7643 #define EXTI_D3PMR1_MR1_Pos (1U)
7644 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
7645 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
7646 #define EXTI_D3PMR1_MR2_Pos (2U)
7647 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
7648 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
7649 #define EXTI_D3PMR1_MR3_Pos (3U)
7650 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
7651 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
7652 #define EXTI_D3PMR1_MR4_Pos (4U)
7653 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
7654 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
7655 #define EXTI_D3PMR1_MR5_Pos (5U)
7656 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
7657 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
7658 #define EXTI_D3PMR1_MR6_Pos (6U)
7659 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
7660 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
7661 #define EXTI_D3PMR1_MR7_Pos (7U)
7662 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
7663 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
7664 #define EXTI_D3PMR1_MR8_Pos (8U)
7665 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
7666 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
7667 #define EXTI_D3PMR1_MR9_Pos (9U)
7668 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
7669 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
7670 #define EXTI_D3PMR1_MR10_Pos (10U)
7671 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
7672 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
7673 #define EXTI_D3PMR1_MR11_Pos (11U)
7674 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
7675 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
7676 #define EXTI_D3PMR1_MR12_Pos (12U)
7677 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
7678 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
7679 #define EXTI_D3PMR1_MR13_Pos (13U)
7680 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
7681 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
7682 #define EXTI_D3PMR1_MR14_Pos (14U)
7683 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
7684 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
7685 #define EXTI_D3PMR1_MR15_Pos (15U)
7686 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
7687 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
7688 #define EXTI_D3PMR1_MR19_Pos (19U)
7689 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
7690 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
7691 #define EXTI_D3PMR1_MR20_Pos (20U)
7692 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
7693 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
7694 #define EXTI_D3PMR1_MR21_Pos (21U)
7695 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
7696 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
7697 #define EXTI_D3PMR1_MR25_Pos (24U)
7698 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
7699 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
7700
7701 /******************* Bit definition for EXTI_D3PCR1L register ****************/
7702 #define EXTI_D3PCR1L_PCS0_Pos (0U)
7703 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
7704 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
7705 #define EXTI_D3PCR1L_PCS1_Pos (2U)
7706 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
7707 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
7708 #define EXTI_D3PCR1L_PCS2_Pos (4U)
7709 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
7710 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
7711 #define EXTI_D3PCR1L_PCS3_Pos (6U)
7712 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
7713 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
7714 #define EXTI_D3PCR1L_PCS4_Pos (8U)
7715 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
7716 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
7717 #define EXTI_D3PCR1L_PCS5_Pos (10U)
7718 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
7719 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
7720 #define EXTI_D3PCR1L_PCS6_Pos (12U)
7721 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
7722 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
7723 #define EXTI_D3PCR1L_PCS7_Pos (14U)
7724 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
7725 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
7726 #define EXTI_D3PCR1L_PCS8_Pos (16U)
7727 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
7728 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
7729 #define EXTI_D3PCR1L_PCS9_Pos (18U)
7730 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
7731 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
7732 #define EXTI_D3PCR1L_PCS10_Pos (20U)
7733 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
7734 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
7735 #define EXTI_D3PCR1L_PCS11_Pos (22U)
7736 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
7737 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
7738 #define EXTI_D3PCR1L_PCS12_Pos (24U)
7739 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
7740 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
7741 #define EXTI_D3PCR1L_PCS13_Pos (26U)
7742 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
7743 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
7744 #define EXTI_D3PCR1L_PCS14_Pos (28U)
7745 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
7746 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
7747 #define EXTI_D3PCR1L_PCS15_Pos (30U)
7748 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
7749 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
7750
7751 /******************* Bit definition for EXTI_D3PCR1H register ****************/
7752 #define EXTI_D3PCR1H_PCS19_Pos (6U)
7753 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
7754 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
7755 #define EXTI_D3PCR1H_PCS20_Pos (8U)
7756 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
7757 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
7758 #define EXTI_D3PCR1H_PCS21_Pos (10U)
7759 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
7760 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
7761 #define EXTI_D3PCR1H_PCS25_Pos (18U)
7762 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
7763 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
7764
7765 /****************** Bit definition for EXTI_RTSR2 register *******************/
7766 #define EXTI_RTSR2_TR_Pos (17U)
7767 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
7768 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
7769 #define EXTI_RTSR2_TR49_Pos (17U)
7770 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
7771 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
7772 #define EXTI_RTSR2_TR51_Pos (19U)
7773 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
7774 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
7775
7776 /****************** Bit definition for EXTI_FTSR2 register *******************/
7777 #define EXTI_FTSR2_TR_Pos (17U)
7778 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
7779 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
7780 #define EXTI_FTSR2_TR49_Pos (17U)
7781 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
7782 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
7783 #define EXTI_FTSR2_TR51_Pos (19U)
7784 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
7785 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
7786
7787 /****************** Bit definition for EXTI_SWIER2 register ******************/
7788 #define EXTI_SWIER2_SWIER49_Pos (17U)
7789 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
7790 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
7791 #define EXTI_SWIER2_SWIER51_Pos (19U)
7792 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
7793 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
7794
7795 /****************** Bit definition for EXTI_D3PMR2 register ******************/
7796 #define EXTI_D3PMR2_MR34_Pos (2U)
7797 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
7798 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
7799 #define EXTI_D3PMR2_MR35_Pos (3U)
7800 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
7801 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
7802 #define EXTI_D3PMR2_MR41_Pos (9U)
7803 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
7804 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
7805 #define EXTI_D3PMR2_MR48_Pos (16U)
7806 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
7807 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
7808 #define EXTI_D3PMR2_MR49_Pos (17U)
7809 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
7810 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
7811 #define EXTI_D3PMR2_MR50_Pos (18U)
7812 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
7813 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
7814 #define EXTI_D3PMR2_MR51_Pos (19U)
7815 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
7816 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
7817 /******************* Bit definition for EXTI_D3PCR2L register ****************/
7818 #define EXTI_D3PCR2L_PCS34_Pos (4U)
7819 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
7820 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
7821 #define EXTI_D3PCR2L_PCS35_Pos (6U)
7822 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
7823 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
7824 #define EXTI_D3PCR2L_PCS41_Pos (18U)
7825 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
7826 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
7827
7828
7829 /******************* Bit definition for EXTI_D3PCR2H register ****************/
7830 #define EXTI_D3PCR2H_PCS48_Pos (0U)
7831 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
7832 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
7833 #define EXTI_D3PCR2H_PCS49_Pos (2U)
7834 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
7835 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
7836 #define EXTI_D3PCR2H_PCS50_Pos (4U)
7837 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
7838 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
7839 #define EXTI_D3PCR2H_PCS51_Pos (6U)
7840 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
7841 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
7842 /****************** Bit definition for EXTI_RTSR3 register *******************/
7843 #define EXTI_RTSR3_TR_Pos (18U)
7844 #define EXTI_RTSR3_TR_Msk (0x9UL << EXTI_RTSR3_TR_Pos) /*!< 0x00240000 */
7845 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
7846 #define EXTI_RTSR3_TR82_Pos (18U)
7847 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
7848 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
7849 #define EXTI_RTSR3_TR85_Pos (21U)
7850 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
7851 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
7852
7853 /****************** Bit definition for EXTI_FTSR3 register *******************/
7854 #define EXTI_FTSR3_TR_Pos (18U)
7855 #define EXTI_FTSR3_TR_Msk (0x9UL << EXTI_FTSR3_TR_Pos) /*!< 0x00240000 */
7856 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
7857 #define EXTI_FTSR3_TR82_Pos (18U)
7858 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
7859 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
7860 #define EXTI_FTSR3_TR85_Pos (21U)
7861 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
7862 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
7863
7864 /****************** Bit definition for EXTI_SWIER3 register ******************/
7865 #define EXTI_SWIER3_SWI_Pos (18U)
7866 #define EXTI_SWIER3_SWI_Msk (0x9UL << EXTI_SWIER3_SWI_Pos) /*!< 0x00240000 */
7867 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
7868 #define EXTI_SWIER3_SWIER82_Pos (18U)
7869 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
7870 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
7871 #define EXTI_SWIER3_SWIER85_Pos (21U)
7872 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
7873 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
7874
7875 /****************** Bit definition for EXTI_D3PMR3 register ******************/
7876 #define EXTI_D3PMR3_MR88_Pos (24U)
7877 #define EXTI_D3PMR3_MR88_Msk (0x1UL << EXTI_D3PMR3_MR88_Pos) /*!< 0x01000000 */
7878 #define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk /*!< Pending Mask Event for line 88 */
7879
7880 /******************* Bit definition for EXTI_D3PCR3H register ****************/
7881 #define EXTI_D3PCR3H_PCS88_Pos (16U)
7882 #define EXTI_D3PCR3H_PCS88_Msk (0x3UL << EXTI_D3PCR3H_PCS88_Pos) /*!< 0x00030000 */
7883 #define EXTI_D3PCR3H_PCS88 EXTI_D3PCR3H_PCS88_Msk /*!< D3 Pending request clear input signal selection on line 88 */
7884
7885 /******************* Bit definition for EXTI_IMR1 register *******************/
7886 #define EXTI_IMR1_IM_Pos (0U)
7887 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
7888 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
7889 #define EXTI_IMR1_IM0_Pos (0U)
7890 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
7891 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
7892 #define EXTI_IMR1_IM1_Pos (1U)
7893 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
7894 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
7895 #define EXTI_IMR1_IM2_Pos (2U)
7896 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
7897 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
7898 #define EXTI_IMR1_IM3_Pos (3U)
7899 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
7900 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
7901 #define EXTI_IMR1_IM4_Pos (4U)
7902 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
7903 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
7904 #define EXTI_IMR1_IM5_Pos (5U)
7905 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
7906 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
7907 #define EXTI_IMR1_IM6_Pos (6U)
7908 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
7909 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
7910 #define EXTI_IMR1_IM7_Pos (7U)
7911 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
7912 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
7913 #define EXTI_IMR1_IM8_Pos (8U)
7914 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
7915 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
7916 #define EXTI_IMR1_IM9_Pos (9U)
7917 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
7918 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
7919 #define EXTI_IMR1_IM10_Pos (10U)
7920 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
7921 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
7922 #define EXTI_IMR1_IM11_Pos (11U)
7923 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
7924 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
7925 #define EXTI_IMR1_IM12_Pos (12U)
7926 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
7927 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
7928 #define EXTI_IMR1_IM13_Pos (13U)
7929 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
7930 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
7931 #define EXTI_IMR1_IM14_Pos (14U)
7932 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
7933 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
7934 #define EXTI_IMR1_IM15_Pos (15U)
7935 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
7936 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
7937 #define EXTI_IMR1_IM16_Pos (16U)
7938 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
7939 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
7940 #define EXTI_IMR1_IM17_Pos (17U)
7941 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
7942 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
7943 #define EXTI_IMR1_IM18_Pos (18U)
7944 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
7945 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
7946 #define EXTI_IMR1_IM19_Pos (19U)
7947 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
7948 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
7949 #define EXTI_IMR1_IM20_Pos (20U)
7950 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
7951 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
7952 #define EXTI_IMR1_IM21_Pos (21U)
7953 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
7954 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
7955 #define EXTI_IMR1_IM22_Pos (22U)
7956 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
7957 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
7958 #define EXTI_IMR1_IM23_Pos (23U)
7959 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
7960 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
7961 #define EXTI_IMR1_IM24_Pos (24U)
7962 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
7963 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
7964 #define EXTI_IMR1_IM25_Pos (25U)
7965 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
7966 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
7967 #define EXTI_IMR1_IM26_Pos (26U)
7968 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
7969 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
7970 #define EXTI_IMR1_IM27_Pos (27U)
7971 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
7972 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
7973 #define EXTI_IMR1_IM28_Pos (28U)
7974 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
7975 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
7976 #define EXTI_IMR1_IM29_Pos (29U)
7977 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
7978 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
7979 #define EXTI_IMR1_IM30_Pos (30U)
7980 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
7981 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
7982 #define EXTI_IMR1_IM31_Pos (31U)
7983 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
7984 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
7985
7986 /******************* Bit definition for EXTI_EMR1 register *******************/
7987 #define EXTI_EMR1_EM_Pos (0U)
7988 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
7989 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
7990 #define EXTI_EMR1_EM0_Pos (0U)
7991 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
7992 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
7993 #define EXTI_EMR1_EM1_Pos (1U)
7994 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
7995 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
7996 #define EXTI_EMR1_EM2_Pos (2U)
7997 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
7998 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
7999 #define EXTI_EMR1_EM3_Pos (3U)
8000 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
8001 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
8002 #define EXTI_EMR1_EM4_Pos (4U)
8003 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
8004 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
8005 #define EXTI_EMR1_EM5_Pos (5U)
8006 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
8007 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
8008 #define EXTI_EMR1_EM6_Pos (6U)
8009 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
8010 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
8011 #define EXTI_EMR1_EM7_Pos (7U)
8012 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
8013 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
8014 #define EXTI_EMR1_EM8_Pos (8U)
8015 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
8016 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
8017 #define EXTI_EMR1_EM9_Pos (9U)
8018 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
8019 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
8020 #define EXTI_EMR1_EM10_Pos (10U)
8021 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
8022 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
8023 #define EXTI_EMR1_EM11_Pos (11U)
8024 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
8025 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
8026 #define EXTI_EMR1_EM12_Pos (12U)
8027 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
8028 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
8029 #define EXTI_EMR1_EM13_Pos (13U)
8030 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
8031 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
8032 #define EXTI_EMR1_EM14_Pos (14U)
8033 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
8034 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
8035 #define EXTI_EMR1_EM15_Pos (15U)
8036 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
8037 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
8038 #define EXTI_EMR1_EM16_Pos (16U)
8039 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
8040 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
8041 #define EXTI_EMR1_EM17_Pos (17U)
8042 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
8043 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
8044 #define EXTI_EMR1_EM18_Pos (18U)
8045 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
8046 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
8047 #define EXTI_EMR1_EM20_Pos (20U)
8048 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
8049 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
8050 #define EXTI_EMR1_EM21_Pos (21U)
8051 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
8052 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
8053 #define EXTI_EMR1_EM22_Pos (22U)
8054 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
8055 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
8056 #define EXTI_EMR1_EM23_Pos (23U)
8057 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
8058 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
8059 #define EXTI_EMR1_EM24_Pos (24U)
8060 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
8061 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
8062 #define EXTI_EMR1_EM25_Pos (25U)
8063 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
8064 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
8065 #define EXTI_EMR1_EM26_Pos (26U)
8066 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
8067 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
8068 #define EXTI_EMR1_EM27_Pos (27U)
8069 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
8070 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
8071 #define EXTI_EMR1_EM28_Pos (28U)
8072 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
8073 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
8074 #define EXTI_EMR1_EM29_Pos (29U)
8075 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
8076 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
8077 #define EXTI_EMR1_EM30_Pos (30U)
8078 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
8079 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
8080 #define EXTI_EMR1_EM31_Pos (31U)
8081 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
8082 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
8083
8084 /******************* Bit definition for EXTI_PR1 register ********************/
8085 #define EXTI_PR1_PR_Pos (0U)
8086 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
8087 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
8088 #define EXTI_PR1_PR0_Pos (0U)
8089 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
8090 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
8091 #define EXTI_PR1_PR1_Pos (1U)
8092 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
8093 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
8094 #define EXTI_PR1_PR2_Pos (2U)
8095 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
8096 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
8097 #define EXTI_PR1_PR3_Pos (3U)
8098 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
8099 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
8100 #define EXTI_PR1_PR4_Pos (4U)
8101 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
8102 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
8103 #define EXTI_PR1_PR5_Pos (5U)
8104 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
8105 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
8106 #define EXTI_PR1_PR6_Pos (6U)
8107 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
8108 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
8109 #define EXTI_PR1_PR7_Pos (7U)
8110 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
8111 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
8112 #define EXTI_PR1_PR8_Pos (8U)
8113 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
8114 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
8115 #define EXTI_PR1_PR9_Pos (9U)
8116 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
8117 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
8118 #define EXTI_PR1_PR10_Pos (10U)
8119 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
8120 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
8121 #define EXTI_PR1_PR11_Pos (11U)
8122 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
8123 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
8124 #define EXTI_PR1_PR12_Pos (12U)
8125 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
8126 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
8127 #define EXTI_PR1_PR13_Pos (13U)
8128 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
8129 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
8130 #define EXTI_PR1_PR14_Pos (14U)
8131 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
8132 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
8133 #define EXTI_PR1_PR15_Pos (15U)
8134 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
8135 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
8136 #define EXTI_PR1_PR16_Pos (16U)
8137 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
8138 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
8139 #define EXTI_PR1_PR17_Pos (17U)
8140 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
8141 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
8142 #define EXTI_PR1_PR18_Pos (18U)
8143 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
8144 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
8145 #define EXTI_PR1_PR19_Pos (19U)
8146 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
8147 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
8148 #define EXTI_PR1_PR20_Pos (20U)
8149 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
8150 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
8151 #define EXTI_PR1_PR21_Pos (21U)
8152 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
8153 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
8154
8155 /******************* Bit definition for EXTI_IMR2 register *******************/
8156 #define EXTI_IMR2_IM_Pos (0U)
8157 #define EXTI_IMR2_IM_Msk (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFF8FFF */
8158 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
8159 #define EXTI_IMR2_IM32_Pos (0U)
8160 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
8161 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
8162 #define EXTI_IMR2_IM33_Pos (1U)
8163 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
8164 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
8165 #define EXTI_IMR2_IM34_Pos (2U)
8166 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
8167 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
8168 #define EXTI_IMR2_IM35_Pos (3U)
8169 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
8170 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
8171 #define EXTI_IMR2_IM36_Pos (4U)
8172 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
8173 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
8174 #define EXTI_IMR2_IM37_Pos (5U)
8175 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
8176 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
8177 #define EXTI_IMR2_IM38_Pos (6U)
8178 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
8179 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
8180 #define EXTI_IMR2_IM39_Pos (7U)
8181 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
8182 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
8183 #define EXTI_IMR2_IM40_Pos (8U)
8184 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
8185 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
8186 #define EXTI_IMR2_IM41_Pos (9U)
8187 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
8188 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
8189 #define EXTI_IMR2_IM42_Pos (10U)
8190 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
8191 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
8192 #define EXTI_IMR2_IM43_Pos (11U)
8193 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
8194 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
8195 #define EXTI_IMR2_IM47_Pos (15U)
8196 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
8197 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
8198 #define EXTI_IMR2_IM48_Pos (16U)
8199 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
8200 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
8201 #define EXTI_IMR2_IM49_Pos (17U)
8202 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
8203 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
8204 #define EXTI_IMR2_IM50_Pos (18U)
8205 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
8206 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
8207 #define EXTI_IMR2_IM51_Pos (19U)
8208 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
8209 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
8210 #define EXTI_IMR2_IM52_Pos (20U)
8211 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
8212 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
8213 #define EXTI_IMR2_IM53_Pos (21U)
8214 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
8215 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
8216 #define EXTI_IMR2_IM54_Pos (22U)
8217 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
8218 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
8219 #define EXTI_IMR2_IM55_Pos (23U)
8220 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
8221 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
8222 #define EXTI_IMR2_IM56_Pos (24U)
8223 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
8224 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
8225 #define EXTI_IMR2_IM57_Pos (25U)
8226 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
8227 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
8228 #define EXTI_IMR2_IM58_Pos (26U)
8229 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
8230 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
8231 #define EXTI_IMR2_IM59_Pos (27U)
8232 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
8233 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
8234 #define EXTI_IMR2_IM60_Pos (28U)
8235 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
8236 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
8237 #define EXTI_IMR2_IM61_Pos (29U)
8238 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
8239 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
8240 #define EXTI_IMR2_IM62_Pos (30U)
8241 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
8242 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
8243 #define EXTI_IMR2_IM63_Pos (31U)
8244 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
8245 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
8246
8247 /******************* Bit definition for EXTI_EMR2 register *******************/
8248 #define EXTI_EMR2_EM_Pos (0U)
8249 #define EXTI_EMR2_EM_Msk (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFF8FFF */
8250 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
8251 #define EXTI_EMR2_EM32_Pos (0U)
8252 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
8253 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
8254 #define EXTI_EMR2_EM33_Pos (1U)
8255 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
8256 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
8257 #define EXTI_EMR2_EM34_Pos (2U)
8258 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
8259 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
8260 #define EXTI_EMR2_EM35_Pos (3U)
8261 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
8262 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
8263 #define EXTI_EMR2_EM36_Pos (4U)
8264 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
8265 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
8266 #define EXTI_EMR2_EM37_Pos (5U)
8267 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
8268 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
8269 #define EXTI_EMR2_EM38_Pos (6U)
8270 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
8271 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
8272 #define EXTI_EMR2_EM39_Pos (7U)
8273 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
8274 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
8275 #define EXTI_EMR2_EM40_Pos (8U)
8276 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
8277 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
8278 #define EXTI_EMR2_EM41_Pos (9U)
8279 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
8280 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
8281 #define EXTI_EMR2_EM42_Pos (10U)
8282 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
8283 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
8284 #define EXTI_EMR2_EM43_Pos (11U)
8285 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
8286 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
8287 #define EXTI_EMR2_EM47_Pos (15U)
8288 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
8289 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
8290 #define EXTI_EMR2_EM48_Pos (16U)
8291 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
8292 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
8293 #define EXTI_EMR2_EM49_Pos (17U)
8294 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
8295 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
8296 #define EXTI_EMR2_EM50_Pos (18U)
8297 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
8298 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
8299 #define EXTI_EMR2_EM51_Pos (19U)
8300 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
8301 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
8302 #define EXTI_EMR2_EM52_Pos (20U)
8303 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
8304 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
8305 #define EXTI_EMR2_EM53_Pos (21U)
8306 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
8307 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
8308 #define EXTI_EMR2_EM54_Pos (22U)
8309 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
8310 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
8311 #define EXTI_EMR2_EM55_Pos (23U)
8312 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
8313 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
8314 #define EXTI_EMR2_EM56_Pos (24U)
8315 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
8316 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
8317 #define EXTI_EMR2_EM57_Pos (25U)
8318 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
8319 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
8320 #define EXTI_EMR2_EM58_Pos (26U)
8321 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
8322 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
8323 #define EXTI_EMR2_EM59_Pos (27U)
8324 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
8325 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
8326 #define EXTI_EMR2_EM60_Pos (28U)
8327 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
8328 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
8329 #define EXTI_EMR2_EM61_Pos (29U)
8330 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
8331 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
8332 #define EXTI_EMR2_EM62_Pos (30U)
8333 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
8334 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
8335 #define EXTI_EMR2_EM63_Pos (31U)
8336 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
8337 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
8338
8339 /******************* Bit definition for EXTI_PR2 register ********************/
8340 #define EXTI_PR2_PR_Pos (17U)
8341 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
8342 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
8343 #define EXTI_PR2_PR49_Pos (17U)
8344 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
8345 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
8346 #define EXTI_PR2_PR51_Pos (19U)
8347 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
8348 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
8349
8350 /******************* Bit definition for EXTI_IMR3 register *******************/
8351 #define EXTI_IMR3_IM_Pos (0U)
8352 #define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
8353 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
8354 #define EXTI_IMR3_IM64_Pos (0U)
8355 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
8356 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
8357 #define EXTI_IMR3_IM65_Pos (1U)
8358 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
8359 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
8360 #define EXTI_IMR3_IM66_Pos (2U)
8361 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
8362 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
8363 #define EXTI_IMR3_IM67_Pos (3U)
8364 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
8365 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
8366 #define EXTI_IMR3_IM68_Pos (4U)
8367 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
8368 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
8369 #define EXTI_IMR3_IM69_Pos (5U)
8370 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
8371 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
8372 #define EXTI_IMR3_IM70_Pos (6U)
8373 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
8374 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
8375 #define EXTI_IMR3_IM71_Pos (7U)
8376 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
8377 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
8378 #define EXTI_IMR3_IM72_Pos (8U)
8379 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
8380 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
8381 #define EXTI_IMR3_IM73_Pos (9U)
8382 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
8383 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
8384 #define EXTI_IMR3_IM74_Pos (10U)
8385 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
8386 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
8387 #define EXTI_IMR3_IM77_Pos (13U)
8388 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
8389 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
8390 #define EXTI_IMR3_IM80_Pos (16U)
8391 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
8392 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
8393 #define EXTI_IMR3_IM82_Pos (18U)
8394 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
8395 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
8396 #define EXTI_IMR3_IM85_Pos (21U)
8397 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
8398 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
8399 #define EXTI_IMR3_IM87_Pos (23U)
8400 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
8401 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
8402
8403
8404 #define EXTI_IMR3_IM88_Pos (24U)
8405 #define EXTI_IMR3_IM88_Msk (0x1UL << EXTI_IMR3_IM88_Pos) /*!< 0x01000000 */
8406 #define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk /*!< Interrupt Mask on line 88 */
8407
8408 /******************* Bit definition for EXTI_EMR3 register *******************/
8409 #define EXTI_EMR3_EM_Pos (0U)
8410 #define EXTI_EMR3_EM_Msk (0x01A527FFUL << EXTI_EMR3_EM_Pos) /*!< 0x01A527FF */
8411 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
8412 #define EXTI_EMR3_EM64_Pos (0U)
8413 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
8414 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
8415 #define EXTI_EMR3_EM65_Pos (1U)
8416 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
8417 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
8418 #define EXTI_EMR3_EM66_Pos (2U)
8419 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
8420 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
8421 #define EXTI_EMR3_EM67_Pos (3U)
8422 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
8423 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
8424 #define EXTI_EMR3_EM68_Pos (4U)
8425 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
8426 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
8427 #define EXTI_EMR3_EM69_Pos (5U)
8428 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
8429 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
8430 #define EXTI_EMR3_EM70_Pos (6U)
8431 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
8432 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
8433 #define EXTI_EMR3_EM71_Pos (7U)
8434 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
8435 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
8436 #define EXTI_EMR3_EM72_Pos (8U)
8437 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
8438 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
8439 #define EXTI_EMR3_EM73_Pos (9U)
8440 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
8441 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
8442 #define EXTI_EMR3_EM74_Pos (10U)
8443 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
8444 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
8445 #define EXTI_EMR3_EM77_Pos (13U)
8446 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
8447 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
8448 #define EXTI_EMR3_EM80_Pos (16U)
8449 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
8450 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
8451 #define EXTI_EMR3_EM81_Pos (17U)
8452 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
8453 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
8454 #define EXTI_EMR3_EM82_Pos (18U)
8455 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
8456 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
8457 #define EXTI_EMR3_EM85_Pos (21U)
8458 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
8459 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
8460 #define EXTI_EMR3_EM87_Pos (23U)
8461 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
8462 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
8463
8464 #define EXTI_EMR3_EM88_Pos (24U)
8465 #define EXTI_EMR3_EM88_Msk (0x1UL << EXTI_EMR3_EM88_Pos) /*!< 0x01000000 */
8466 #define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk /*!< Event Mask on line 88 */
8467
8468 /******************* Bit definition for EXTI_PR3 register ********************/
8469 #define EXTI_PR3_PR_Pos (18U)
8470 #define EXTI_PR3_PR_Msk (0x9UL << EXTI_PR3_PR_Pos) /*!< 0x00240000 */
8471 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
8472 #define EXTI_PR3_PR82_Pos (18U)
8473 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
8474 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
8475 #define EXTI_PR3_PR85_Pos (21U)
8476 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
8477 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
8478 /******************************************************************************/
8479 /* */
8480 /* FLASH */
8481 /* */
8482 /******************************************************************************/
8483 /*
8484 * @brief FLASH Global Defines
8485 */
8486 #define FLASH_SECTOR_TOTAL 128U /* 128 sectors */
8487 #define FLASH_SIZE 0x200000UL /* 2 MB */
8488 #define FLASH_BANK_SIZE (FLASH_SIZE >> 1) /* 1 MB */
8489 #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
8490 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
8491 #define FLASH_NB_32BITWORD_IN_FLASHWORD 4U /* 128 bits */
8492 #define DUAL_BANK /* Dual-bank Flash */
8493
8494 /******************* Bits definition for FLASH_ACR register **********************/
8495 #define FLASH_ACR_LATENCY_Pos (0U)
8496 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
8497 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
8498 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
8499 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
8500 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
8501 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
8502 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
8503 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
8504 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
8505 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
8506 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
8507 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
8508 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
8509 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
8510 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
8511 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
8512 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
8513 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
8514 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
8515 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
8516 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
8517 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
8518 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
8519
8520 /******************* Bits definition for FLASH_CR register ***********************/
8521 #define FLASH_CR_LOCK_Pos (0U)
8522 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
8523 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
8524 #define FLASH_CR_PG_Pos (1U)
8525 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
8526 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
8527 #define FLASH_CR_SER_Pos (2U)
8528 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
8529 #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
8530 #define FLASH_CR_BER_Pos (3U)
8531 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
8532 #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
8533 #define FLASH_CR_FW_Pos (4U)
8534 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */
8535 #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
8536 #define FLASH_CR_START_Pos (5U)
8537 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */
8538 #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
8539 #define FLASH_CR_SNB_Pos (6U)
8540 #define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */
8541 #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
8542 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
8543 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
8544 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
8545 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
8546 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
8547 #define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */
8548 #define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */
8549 #define FLASH_CR_CRC_EN_Pos (15U)
8550 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
8551 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
8552 #define FLASH_CR_EOPIE_Pos (16U)
8553 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
8554 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
8555 #define FLASH_CR_WRPERRIE_Pos (17U)
8556 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
8557 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
8558 #define FLASH_CR_PGSERRIE_Pos (18U)
8559 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
8560 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
8561 #define FLASH_CR_STRBERRIE_Pos (19U)
8562 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
8563 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
8564 #define FLASH_CR_INCERRIE_Pos (21U)
8565 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
8566 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
8567 #define FLASH_CR_RDPERRIE_Pos (23U)
8568 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
8569 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
8570 #define FLASH_CR_RDSERRIE_Pos (24U)
8571 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
8572 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
8573 #define FLASH_CR_SNECCERRIE_Pos (25U)
8574 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
8575 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
8576 #define FLASH_CR_DBECCERRIE_Pos (26U)
8577 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
8578 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
8579 #define FLASH_CR_CRCENDIE_Pos (27U)
8580 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
8581 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
8582 #define FLASH_CR_CRCRDERRIE_Pos (28U)
8583 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
8584 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
8585
8586 /******************* Bits definition for FLASH_SR register ***********************/
8587 #define FLASH_SR_BSY_Pos (0U)
8588 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
8589 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
8590 #define FLASH_SR_WBNE_Pos (1U)
8591 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
8592 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
8593 #define FLASH_SR_QW_Pos (2U)
8594 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
8595 #define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
8596 #define FLASH_SR_CRC_BUSY_Pos (3U)
8597 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
8598 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
8599 #define FLASH_SR_EOP_Pos (16U)
8600 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
8601 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
8602 #define FLASH_SR_WRPERR_Pos (17U)
8603 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
8604 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
8605 #define FLASH_SR_PGSERR_Pos (18U)
8606 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
8607 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
8608 #define FLASH_SR_STRBERR_Pos (19U)
8609 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
8610 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
8611 #define FLASH_SR_INCERR_Pos (21U)
8612 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
8613 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
8614 #define FLASH_SR_RDPERR_Pos (23U)
8615 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
8616 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
8617 #define FLASH_SR_RDSERR_Pos (24U)
8618 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
8619 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
8620 #define FLASH_SR_SNECCERR_Pos (25U)
8621 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
8622 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
8623 #define FLASH_SR_DBECCERR_Pos (26U)
8624 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
8625 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
8626 #define FLASH_SR_CRCEND_Pos (27U)
8627 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
8628 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
8629 #define FLASH_SR_CRCRDERR_Pos (28U)
8630 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
8631 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
8632
8633 /******************* Bits definition for FLASH_CCR register *******************/
8634 #define FLASH_CCR_CLR_EOP_Pos (16U)
8635 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
8636 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
8637 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
8638 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
8639 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
8640 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
8641 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
8642 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
8643 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
8644 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
8645 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
8646 #define FLASH_CCR_CLR_INCERR_Pos (21U)
8647 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
8648 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
8649 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
8650 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
8651 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
8652 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
8653 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
8654 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
8655 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
8656 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
8657 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
8658 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
8659 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
8660 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
8661 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
8662 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
8663 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
8664 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
8665 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
8666 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
8667
8668 /******************* Bits definition for FLASH_OPTCR register *******************/
8669 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
8670 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
8671 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
8672 #define FLASH_OPTCR_OPTSTART_Pos (1U)
8673 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
8674 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
8675 #define FLASH_OPTCR_MER_Pos (4U)
8676 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
8677 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
8678 #define FLASH_OPTCR_PG_OTP_Pos (5U)
8679 #define FLASH_OPTCR_PG_OTP_Msk (0x1UL << FLASH_OPTCR_PG_OTP_Pos) /*!< 0x00000020 */
8680 #define FLASH_OPTCR_PG_OTP FLASH_OPTCR_PG_OTP_Msk /*!< OTP program control bit */
8681 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
8682 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
8683 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
8684 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
8685 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
8686 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
8687
8688 /******************* Bits definition for FLASH_OPTSR register ***************/
8689 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
8690 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
8691 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
8692 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
8693 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
8694 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
8695 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
8696 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
8697 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
8698 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
8699 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
8700 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
8701 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
8702 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
8703 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
8704 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
8705 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
8706 #define FLASH_OPTSR_RDP_Pos (8U)
8707 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
8708 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
8709 #define FLASH_OPTSR_VDDMMC_HSLV_Pos (16U)
8710 #define FLASH_OPTSR_VDDMMC_HSLV_Msk (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */
8711 #define FLASH_OPTSR_VDDMMC_HSLV FLASH_OPTSR_VDDMMC_HSLV_Msk /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */
8712 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
8713 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
8714 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
8715 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
8716 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
8717 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
8718 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
8719 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
8720 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
8721 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
8722 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
8723 #define FLASH_OPTSR_SECURITY_Pos (21U)
8724 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
8725 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
8726 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
8727 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
8728 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
8729 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
8730 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
8731 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
8732 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
8733 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
8734 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
8735
8736 /******************* Bits definition for FLASH_OPTCCR register *******************/
8737 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
8738 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
8739 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
8740
8741 /******************* Bits definition for FLASH_PRAR register *********************/
8742 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
8743 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
8744 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
8745 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
8746 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
8747 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
8748 #define FLASH_PRAR_DMEP_Pos (31U)
8749 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
8750 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
8751
8752 /******************* Bits definition for FLASH_SCAR register *********************/
8753 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
8754 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
8755 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
8756 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
8757 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
8758 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
8759 #define FLASH_SCAR_DMES_Pos (31U)
8760 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
8761 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
8762
8763 /******************* Bits definition for FLASH_WPSN register *********************/
8764 #define FLASH_WPSN_WRPSN_Pos (0U)
8765 #define FLASH_WPSN_WRPSN_Msk (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0xFFFFFFFF */
8766 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
8767
8768 /******************* Bits definition for FLASH_BOOT_CUR register ****************/
8769 #define FLASH_BOOT_ADD0_Pos (0U)
8770 #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
8771 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
8772 #define FLASH_BOOT_ADD1_Pos (16U)
8773 #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
8774 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
8775
8776
8777 /******************* Bits definition for FLASH_CRCCR register ********************/
8778 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
8779 #define FLASH_CRCCR_CRC_SECT_Msk (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */
8780 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
8781 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
8782 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
8783 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
8784 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
8785 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
8786 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
8787 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
8788 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
8789 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
8790 #define FLASH_CRCCR_START_CRC_Pos (16U)
8791 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
8792 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
8793 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
8794 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
8795 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
8796 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
8797 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
8798 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
8799 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
8800 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
8801 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
8802 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
8803 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
8804
8805 /******************* Bits definition for FLASH_CRCSADD register ****************/
8806 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
8807 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
8808 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
8809
8810 /******************* Bits definition for FLASH_CRCEADD register ****************/
8811 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
8812 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
8813 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
8814
8815 /******************* Bits definition for FLASH_CRCDATA register ***************/
8816 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
8817 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
8818 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
8819
8820 /******************* Bits definition for FLASH_ECC_FA register *******************/
8821 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
8822 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */
8823 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
8824 #define FLASH_ECC_FA_OTP_FAIL_ECC_Pos (31U)
8825 #define FLASH_ECC_FA_OTP_FAIL_ECC_Msk (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */
8826 #define FLASH_ECC_FA_OTP_FAIL_ECC FLASH_ECC_FA_OTP_FAIL_ECC_Msk /*!< OTP ECC error bit */
8827
8828 /******************* Bits definition for FLASH_OTPBL register *******************/
8829 #define FLASH_OTPBL_LOCKBL_Pos (0U)
8830 #define FLASH_OTPBL_LOCKBL_Msk (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */
8831 #define FLASH_OTPBL_LOCKBL FLASH_OTPBL_LOCKBL_Msk /*!< OTP Block Lock */
8832
8833 /******************************************************************************/
8834 /* */
8835 /* Flexible Memory Controller */
8836 /* */
8837 /******************************************************************************/
8838 /****************** Bit definition for FMC_BCR1 register *******************/
8839 #define FMC_BCR1_CCLKEN_Pos (20U)
8840 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
8841 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
8842 #define FMC_BCR1_WFDIS_Pos (21U)
8843 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
8844 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
8845
8846 #define FMC_BCR1_BMAP_Pos (24U)
8847 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
8848 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
8849 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
8850 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
8851
8852 #define FMC_BCR1_FMCEN_Pos (31U)
8853 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
8854 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
8855 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
8856 #define FMC_BCRx_MBKEN_Pos (0U)
8857 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
8858 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
8859 #define FMC_BCRx_MUXEN_Pos (1U)
8860 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
8861 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
8862
8863 #define FMC_BCRx_MTYP_Pos (2U)
8864 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
8865 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
8866 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
8867 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
8868
8869 #define FMC_BCRx_MWID_Pos (4U)
8870 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
8871 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
8872 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
8873 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
8874
8875 #define FMC_BCRx_FACCEN_Pos (6U)
8876 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
8877 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
8878 #define FMC_BCRx_BURSTEN_Pos (8U)
8879 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
8880 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
8881 #define FMC_BCRx_WAITPOL_Pos (9U)
8882 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
8883 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
8884 #define FMC_BCRx_WAITCFG_Pos (11U)
8885 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
8886 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
8887 #define FMC_BCRx_WREN_Pos (12U)
8888 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
8889 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
8890 #define FMC_BCRx_WAITEN_Pos (13U)
8891 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
8892 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
8893 #define FMC_BCRx_EXTMOD_Pos (14U)
8894 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
8895 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
8896 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
8897 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
8898 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
8899
8900 #define FMC_BCRx_CPSIZE_Pos (16U)
8901 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
8902 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
8903 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
8904 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
8905 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
8906
8907 #define FMC_BCRx_CBURSTRW_Pos (19U)
8908 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
8909 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
8910
8911 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
8912 #define FMC_BTRx_ADDSET_Pos (0U)
8913 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
8914 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8915 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
8916 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
8917 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
8918 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
8919
8920 #define FMC_BTRx_ADDHLD_Pos (4U)
8921 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8922 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8923 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
8924 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
8925 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
8926 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
8927
8928 #define FMC_BTRx_DATAST_Pos (8U)
8929 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
8930 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8931 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
8932 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
8933 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
8934 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
8935 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
8936 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
8937 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
8938 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
8939
8940 #define FMC_BTRx_BUSTURN_Pos (16U)
8941 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
8942 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
8943 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
8944 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
8945 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
8946 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
8947
8948 #define FMC_BTRx_CLKDIV_Pos (20U)
8949 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
8950 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
8951 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
8952 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
8953 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
8954 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
8955
8956 #define FMC_BTRx_DATLAT_Pos (24U)
8957 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
8958 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
8959 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
8960 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
8961 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
8962 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
8963
8964 #define FMC_BTRx_ACCMOD_Pos (28U)
8965 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
8966 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
8967 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
8968 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
8969
8970 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
8971 #define FMC_BWTRx_ADDSET_Pos (0U)
8972 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
8973 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
8974 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
8975 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
8976 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
8977 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
8978
8979 #define FMC_BWTRx_ADDHLD_Pos (4U)
8980 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
8981 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
8982 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
8983 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
8984 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
8985 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
8986
8987 #define FMC_BWTRx_DATAST_Pos (8U)
8988 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
8989 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
8990 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
8991 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
8992 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
8993 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
8994 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
8995 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
8996 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
8997 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
8998
8999 #define FMC_BWTRx_BUSTURN_Pos (16U)
9000 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
9001 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9002 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
9003 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
9004 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
9005 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
9006
9007 #define FMC_BWTRx_ACCMOD_Pos (28U)
9008 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
9009 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9010 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
9011 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
9012
9013 /****************** Bit definition for FMC_PCR register *******************/
9014 #define FMC_PCR_PWAITEN_Pos (1U)
9015 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
9016 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
9017 #define FMC_PCR_PBKEN_Pos (2U)
9018 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
9019 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
9020
9021 #define FMC_PCR_PWID_Pos (4U)
9022 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
9023 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9024 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
9025 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
9026
9027 #define FMC_PCR_ECCEN_Pos (6U)
9028 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
9029 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
9030
9031 #define FMC_PCR_TCLR_Pos (9U)
9032 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
9033 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9034 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
9035 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
9036 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
9037 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
9038
9039 #define FMC_PCR_TAR_Pos (13U)
9040 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
9041 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9042 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
9043 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
9044 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
9045 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
9046
9047 #define FMC_PCR_ECCPS_Pos (17U)
9048 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
9049 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
9050 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
9051 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
9052 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
9053
9054 /******************* Bit definition for FMC_SR register *******************/
9055 #define FMC_SR_IRS_Pos (0U)
9056 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
9057 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
9058 #define FMC_SR_ILS_Pos (1U)
9059 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
9060 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
9061 #define FMC_SR_IFS_Pos (2U)
9062 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
9063 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
9064 #define FMC_SR_IREN_Pos (3U)
9065 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
9066 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9067 #define FMC_SR_ILEN_Pos (4U)
9068 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
9069 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9070 #define FMC_SR_IFEN_Pos (5U)
9071 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
9072 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9073 #define FMC_SR_FEMPT_Pos (6U)
9074 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
9075 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
9076
9077 /****************** Bit definition for FMC_PMEM register ******************/
9078 #define FMC_PMEM_MEMSET_Pos (0U)
9079 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
9080 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
9081 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
9082 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
9083 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
9084 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
9085 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
9086 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
9087 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
9088 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
9089
9090 #define FMC_PMEM_MEMWAIT_Pos (8U)
9091 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
9092 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
9093 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
9094 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
9095 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
9096 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
9097 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
9098 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
9099 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
9100 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
9101
9102 #define FMC_PMEM_MEMHOLD_Pos (16U)
9103 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
9104 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
9105 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
9106 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
9107 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
9108 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
9109 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
9110 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
9111 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
9112 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
9113
9114 #define FMC_PMEM_MEMHIZ_Pos (24U)
9115 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
9116 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
9117 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
9118 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
9119 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
9120 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
9121 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
9122 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
9123 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
9124 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
9125
9126 /****************** Bit definition for FMC_PATT register ******************/
9127 #define FMC_PATT_ATTSET_Pos (0U)
9128 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
9129 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
9130 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
9131 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
9132 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
9133 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
9134 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
9135 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
9136 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
9137 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
9138
9139 #define FMC_PATT_ATTWAIT_Pos (8U)
9140 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
9141 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
9142 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
9143 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
9144 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
9145 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
9146 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
9147 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
9148 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
9149 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
9150
9151 #define FMC_PATT_ATTHOLD_Pos (16U)
9152 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
9153 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
9154 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
9155 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
9156 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
9157 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
9158 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
9159 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
9160 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
9161 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
9162
9163 #define FMC_PATT_ATTHIZ_Pos (24U)
9164 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
9165 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
9166 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
9167 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
9168 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
9169 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
9170 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
9171 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
9172 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
9173 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
9174
9175 /****************** Bit definition for FMC_ECCR3 register ******************/
9176 #define FMC_ECCR3_ECC3_Pos (0U)
9177 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
9178 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
9179
9180 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
9181 #define FMC_SDCRx_NC_Pos (0U)
9182 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
9183 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
9184 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
9185 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
9186
9187 #define FMC_SDCRx_NR_Pos (2U)
9188 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
9189 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
9190 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
9191 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
9192
9193 #define FMC_SDCRx_MWID_Pos (4U)
9194 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
9195 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
9196 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
9197 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
9198
9199 #define FMC_SDCRx_NB_Pos (6U)
9200 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
9201 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
9202
9203 #define FMC_SDCRx_CAS_Pos (7U)
9204 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
9205 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
9206 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
9207 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
9208
9209 #define FMC_SDCRx_WP_Pos (9U)
9210 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
9211 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
9212
9213 #define FMC_SDCRx_SDCLK_Pos (10U)
9214 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
9215 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
9216 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
9217 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
9218
9219 #define FMC_SDCRx_RBURST_Pos (12U)
9220 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
9221 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
9222
9223 #define FMC_SDCRx_RPIPE_Pos (13U)
9224 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
9225 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
9226 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
9227 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
9228
9229 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
9230 #define FMC_SDTRx_TMRD_Pos (0U)
9231 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
9232 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
9233 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
9234 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
9235 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
9236 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
9237
9238 #define FMC_SDTRx_TXSR_Pos (4U)
9239 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
9240 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
9241 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
9242 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
9243 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
9244 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
9245
9246 #define FMC_SDTRx_TRAS_Pos (8U)
9247 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
9248 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
9249 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
9250 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
9251 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
9252 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
9253
9254 #define FMC_SDTRx_TRC_Pos (12U)
9255 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
9256 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
9257 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
9258 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
9259 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
9260
9261 #define FMC_SDTRx_TWR_Pos (16U)
9262 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
9263 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
9264 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
9265 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
9266 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
9267
9268 #define FMC_SDTRx_TRP_Pos (20U)
9269 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
9270 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
9271 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
9272 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
9273 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
9274
9275 #define FMC_SDTRx_TRCD_Pos (24U)
9276 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
9277 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
9278 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
9279 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
9280 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
9281
9282 /****************** Bit definition for FMC_SDCMR register ******************/
9283 #define FMC_SDCMR_MODE_Pos (0U)
9284 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
9285 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
9286 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
9287 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
9288 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
9289
9290 #define FMC_SDCMR_CTB2_Pos (3U)
9291 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
9292 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
9293
9294 #define FMC_SDCMR_CTB1_Pos (4U)
9295 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
9296 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
9297
9298 #define FMC_SDCMR_NRFS_Pos (5U)
9299 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
9300 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
9301 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
9302 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
9303 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
9304 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
9305
9306 #define FMC_SDCMR_MRD_Pos (9U)
9307 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
9308 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
9309
9310 /****************** Bit definition for FMC_SDRTR register ******************/
9311 #define FMC_SDRTR_CRE_Pos (0U)
9312 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
9313 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
9314
9315 #define FMC_SDRTR_COUNT_Pos (1U)
9316 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
9317 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
9318
9319 #define FMC_SDRTR_REIE_Pos (14U)
9320 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
9321 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
9322
9323 /****************** Bit definition for FMC_SDSR register ******************/
9324 #define FMC_SDSR_RE_Pos (0U)
9325 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
9326 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
9327
9328 #define FMC_SDSR_MODES1_Pos (1U)
9329 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
9330 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
9331 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
9332 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
9333
9334 #define FMC_SDSR_MODES2_Pos (3U)
9335 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
9336 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
9337 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
9338 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
9339
9340 /******************************************************************************/
9341 /* */
9342 /* Graphic MMU (GFXMMU) */
9343 /* */
9344 /******************************************************************************/
9345 /****************** Bits definition for GFXMMU_CR register ********************/
9346 #define GFXMMU_CR_B0OIE_Pos (0U)
9347 #define GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos) /*!< 0x00000001 */
9348 #define GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk /*!< Buffer 0 overflow interrupt enable */
9349 #define GFXMMU_CR_B1OIE_Pos (1U)
9350 #define GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos) /*!< 0x00000002 */
9351 #define GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk /*!< Buffer 1 overflow interrupt enable */
9352 #define GFXMMU_CR_B2OIE_Pos (2U)
9353 #define GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos) /*!< 0x00000004 */
9354 #define GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk /*!< Buffer 2 overflow interrupt enable */
9355 #define GFXMMU_CR_B3OIE_Pos (3U)
9356 #define GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos) /*!< 0x00000008 */
9357 #define GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk /*!< Buffer 3 overflow interrupt enable */
9358 #define GFXMMU_CR_AMEIE_Pos (4U)
9359 #define GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos) /*!< 0x00000010 */
9360 #define GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk /*!< AHB master error interrupt enable */
9361 #define GFXMMU_CR_192BM_Pos (6U)
9362 #define GFXMMU_CR_192BM_Msk (0x1UL << GFXMMU_CR_192BM_Pos) /*!< 0x00000040 */
9363 #define GFXMMU_CR_192BM GFXMMU_CR_192BM_Msk /*!< 192 block mode */
9364 #define GFXMMU_CR_CE_Pos (7U)
9365 #define GFXMMU_CR_CE_Msk (0x1UL << GFXMMU_CR_CE_Pos) /*!< 0x00000080 */
9366 #define GFXMMU_CR_CE GFXMMU_CR_CE_Msk /*!< Cache Enable */
9367 #define GFXMMU_CR_CL_Pos (8U)
9368 #define GFXMMU_CR_CL_Msk (0x1UL << GFXMMU_CR_CL_Pos) /*!< 0x00000100 */
9369 #define GFXMMU_CR_CL GFXMMU_CR_CL_Msk /*!< Cache Lock */
9370 #define GFXMMU_CR_CLB_Pos (9U)
9371 #define GFXMMU_CR_CLB_Msk (0x3UL << GFXMMU_CR_CLB_Pos) /*!< 0x00000600 */
9372 #define GFXMMU_CR_CLB GFXMMU_CR_CLB_Msk /*!< CLB[1:0]: Cache Lock Buffer */
9373 #define GFXMMU_CR_CLB_0 (0x1UL << GFXMMU_CR_CLB_Pos) /*!< Cache locked on buffer 1 */
9374 #define GFXMMU_CR_CLB_1 (0x2UL << GFXMMU_CR_CLB_Pos) /*!< Cache locked on buffer 2 */
9375 #define GFXMMU_CR_FC_Pos (11U)
9376 #define GFXMMU_CR_FC_Msk (0x1UL << GFXMMU_CR_FC_Pos) /*!< 0x00000800 */
9377 #define GFXMMU_CR_FC GFXMMU_CR_FC_Msk /*!< Force Caching */
9378 #define GFXMMU_CR_PD_Pos (12U)
9379 #define GFXMMU_CR_PD_Msk (0x1UL << GFXMMU_CR_PD_Pos) /*!< 0x00001000 */
9380 #define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
9381 #define GFXMMU_CR_OC_Pos (16U)
9382 #define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
9383 #define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
9384 #define GFXMMU_CR_OB_Pos (17U)
9385 #define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
9386 #define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
9387
9388 /****************** Bits definition for GFXMMU_SR register ********************/
9389 #define GFXMMU_SR_B0OF_Pos (0U)
9390 #define GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos) /*!< 0x00000001 */
9391 #define GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk /*!< Buffer 0 overflow flag */
9392 #define GFXMMU_SR_B1OF_Pos (1U)
9393 #define GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos) /*!< 0x00000002 */
9394 #define GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk /*!< Buffer 1 overflow flag */
9395 #define GFXMMU_SR_B2OF_Pos (2U)
9396 #define GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos) /*!< 0x00000004 */
9397 #define GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk /*!< Buffer 2 overflow flag */
9398 #define GFXMMU_SR_B3OF_Pos (3U)
9399 #define GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos) /*!< 0x00000008 */
9400 #define GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk /*!< Buffer 3 overflow flag */
9401 #define GFXMMU_SR_AMEF_Pos (4U)
9402 #define GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos) /*!< 0x00000010 */
9403 #define GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk /*!< AHB master error flag */
9404
9405 /****************** Bits definition for GFXMMU_FCR register *******************/
9406 #define GFXMMU_FCR_CB0OF_Pos (0U)
9407 #define GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos) /*!< 0x00000001 */
9408 #define GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk /*!< Clear buffer 0 overflow flag */
9409 #define GFXMMU_FCR_CB1OF_Pos (1U)
9410 #define GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos) /*!< 0x00000002 */
9411 #define GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk /*!< Clear buffer 1 overflow flag */
9412 #define GFXMMU_FCR_CB2OF_Pos (2U)
9413 #define GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos) /*!< 0x00000004 */
9414 #define GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk /*!< Clear buffer 2 overflow flag */
9415 #define GFXMMU_FCR_CB3OF_Pos (3U)
9416 #define GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos) /*!< 0x00000008 */
9417 #define GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk /*!< Clear buffer 3 overflow flag */
9418 #define GFXMMU_FCR_CAMEF_Pos (4U)
9419 #define GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos) /*!< 0x00000010 */
9420 #define GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk /*!< Clear AHB master error flag */
9421
9422 /****************** Bits definition for GFXMMU_CCR register *******************/
9423 #define GFXMMU_CCR_FF_Pos (0U)
9424 #define GFXMMU_CCR_FF_Msk (0x1UL << GFXMMU_CCR_FF_Pos) /*!< 0x00000001 */
9425 #define GFXMMU_CCR_FF GFXMMU_CCR_FF_Msk /*!< Clear buffer 0 overflow flag */
9426 #define GFXMMU_CCR_FI_Pos (1U)
9427 #define GFXMMU_CCR_FI_Msk (0x1UL << GFXMMU_CCR_FI_Pos) /*!< 0x00000002 */
9428 #define GFXMMU_CCR_FI GFXMMU_CCR_FI_Msk /*!< Clear buffer 1 overflow flag */
9429
9430 /****************** Bits definition for GFXMMU_DVR register *******************/
9431 #define GFXMMU_DVR_DV_Pos (0U)
9432 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
9433 #define GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk /*!< DV[31:0] bits (Default value) */
9434
9435 /****************** Bits definition for GFXMMU_B0CR register ******************/
9436 #define GFXMMU_B0CR_PBO_Pos (4U)
9437 #define GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos) /*!< 0x007FFFF0 */
9438 #define GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9439 #define GFXMMU_B0CR_PBBA_Pos (23U)
9440 #define GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos) /*!< 0xFF800000 */
9441 #define GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9442
9443 /****************** Bits definition for GFXMMU_B1CR register ******************/
9444 #define GFXMMU_B1CR_PBO_Pos (4U)
9445 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
9446 #define GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9447 #define GFXMMU_B1CR_PBBA_Pos (23U)
9448 #define GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos) /*!< 0xFF800000 */
9449 #define GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9450
9451 /****************** Bits definition for GFXMMU_B2CR register ******************/
9452 #define GFXMMU_B2CR_PBO_Pos (4U)
9453 #define GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos) /*!< 0x007FFFF0 */
9454 #define GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9455 #define GFXMMU_B2CR_PBBA_Pos (23U)
9456 #define GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos) /*!< 0xFF800000 */
9457 #define GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9458
9459 /****************** Bits definition for GFXMMU_B3CR register ******************/
9460 #define GFXMMU_B3CR_PBO_Pos (4U)
9461 #define GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos) /*!< 0x007FFFF0 */
9462 #define GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9463 #define GFXMMU_B3CR_PBBA_Pos (23U)
9464 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
9465 #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9466
9467 /****************** Bits definition for GFXMMU_HWCFGR register ****************/
9468 #define GFXMMU_HWCFGR_TBD_Pos (0U)
9469 #define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
9470 #define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
9471
9472 /****************** Bits definition for GFXMMU_VERR register ******************/
9473 #define GFXMMU_VERR_MINREV_Pos (0U)
9474 #define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
9475 #define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
9476 #define GFXMMU_VERR_MAJREV_Pos (4U)
9477 #define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
9478 #define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
9479
9480 /****************** Bits definition for GFXMMU_IPIDR register *****************/
9481 #define GFXMMU_IPIDR_ID_Pos (0U)
9482 #define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
9483 #define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
9484
9485 /****************** Bits definition for GFXMMU_SIDR register ******************/
9486 #define GFXMMU_SIDR_SID_Pos (0U)
9487 #define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
9488 #define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
9489
9490 /****************** Bits definition for GFXMMU_LUTxL register *****************/
9491 #define GFXMMU_LUTxL_EN_Pos (0U)
9492 #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
9493 #define GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk /*!< Enable */
9494 #define GFXMMU_LUTxL_FVB_Pos (8U)
9495 #define GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos) /*!< 0x0000FF00 */
9496 #define GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk /*!< FVB[7:0] bits (First visible block) */
9497 #define GFXMMU_LUTxL_LVB_Pos (16U)
9498 #define GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos) /*!< 0x00FF0000 */
9499 #define GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk /*!< LVB[7:0] bits (Last visible block) */
9500
9501 /****************** Bits definition for GFXMMU_LUTxH register *****************/
9502 #define GFXMMU_LUTxH_LO_Pos (4U)
9503 #define GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos) /*!< 0x003FFFF0 */
9504 #define GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk /*!< LO[21:4] bits (Line offset) */
9505
9506 /******************************************************************************/
9507 /* */
9508 /* General Purpose I/O */
9509 /* */
9510 /******************************************************************************/
9511 /****************** Bits definition for GPIO_MODER register *****************/
9512 #define GPIO_MODER_MODE0_Pos (0U)
9513 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
9514 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
9515 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
9516 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
9517
9518 #define GPIO_MODER_MODE1_Pos (2U)
9519 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
9520 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
9521 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
9522 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
9523
9524 #define GPIO_MODER_MODE2_Pos (4U)
9525 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
9526 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
9527 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
9528 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
9529
9530 #define GPIO_MODER_MODE3_Pos (6U)
9531 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
9532 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
9533 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
9534 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
9535
9536 #define GPIO_MODER_MODE4_Pos (8U)
9537 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
9538 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
9539 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
9540 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
9541
9542 #define GPIO_MODER_MODE5_Pos (10U)
9543 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
9544 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
9545 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
9546 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
9547
9548 #define GPIO_MODER_MODE6_Pos (12U)
9549 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
9550 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
9551 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
9552 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
9553
9554 #define GPIO_MODER_MODE7_Pos (14U)
9555 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
9556 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
9557 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
9558 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
9559
9560 #define GPIO_MODER_MODE8_Pos (16U)
9561 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
9562 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
9563 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
9564 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
9565
9566 #define GPIO_MODER_MODE9_Pos (18U)
9567 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
9568 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
9569 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
9570 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
9571
9572 #define GPIO_MODER_MODE10_Pos (20U)
9573 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
9574 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
9575 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
9576 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
9577
9578 #define GPIO_MODER_MODE11_Pos (22U)
9579 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
9580 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
9581 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
9582 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
9583
9584 #define GPIO_MODER_MODE12_Pos (24U)
9585 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
9586 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
9587 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
9588 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
9589
9590 #define GPIO_MODER_MODE13_Pos (26U)
9591 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
9592 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
9593 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
9594 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
9595
9596 #define GPIO_MODER_MODE14_Pos (28U)
9597 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
9598 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
9599 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
9600 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
9601
9602 #define GPIO_MODER_MODE15_Pos (30U)
9603 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
9604 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
9605 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
9606 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
9607
9608 /****************** Bits definition for GPIO_OTYPER register ****************/
9609 #define GPIO_OTYPER_OT0_Pos (0U)
9610 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
9611 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9612 #define GPIO_OTYPER_OT1_Pos (1U)
9613 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
9614 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9615 #define GPIO_OTYPER_OT2_Pos (2U)
9616 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
9617 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9618 #define GPIO_OTYPER_OT3_Pos (3U)
9619 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
9620 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9621 #define GPIO_OTYPER_OT4_Pos (4U)
9622 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
9623 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9624 #define GPIO_OTYPER_OT5_Pos (5U)
9625 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
9626 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9627 #define GPIO_OTYPER_OT6_Pos (6U)
9628 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
9629 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9630 #define GPIO_OTYPER_OT7_Pos (7U)
9631 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
9632 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9633 #define GPIO_OTYPER_OT8_Pos (8U)
9634 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
9635 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9636 #define GPIO_OTYPER_OT9_Pos (9U)
9637 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
9638 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9639 #define GPIO_OTYPER_OT10_Pos (10U)
9640 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
9641 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9642 #define GPIO_OTYPER_OT11_Pos (11U)
9643 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
9644 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9645 #define GPIO_OTYPER_OT12_Pos (12U)
9646 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
9647 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9648 #define GPIO_OTYPER_OT13_Pos (13U)
9649 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
9650 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9651 #define GPIO_OTYPER_OT14_Pos (14U)
9652 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
9653 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9654 #define GPIO_OTYPER_OT15_Pos (15U)
9655 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
9656 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9657
9658 /****************** Bits definition for GPIO_OSPEEDR register ***************/
9659 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9660 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
9661 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9662 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
9663 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
9664
9665 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9666 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
9667 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9668 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
9669 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
9670
9671 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9672 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
9673 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9674 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
9675 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
9676
9677 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9678 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
9679 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9680 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
9681 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
9682
9683 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9684 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
9685 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9686 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
9687 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
9688
9689 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9690 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
9691 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9692 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
9693 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
9694
9695 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9696 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
9697 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9698 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
9699 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
9700
9701 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9702 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
9703 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9704 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
9705 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
9706
9707 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9708 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
9709 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9710 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
9711 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
9712
9713 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9714 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
9715 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9716 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
9717 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
9718
9719 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9720 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
9721 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9722 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
9723 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
9724
9725 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9726 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
9727 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9728 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
9729 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
9730
9731 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9732 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
9733 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9734 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
9735 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
9736
9737 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9738 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
9739 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9740 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
9741 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
9742
9743 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9744 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
9745 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9746 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
9747 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
9748
9749 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
9750 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
9751 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
9752 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
9753 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
9754
9755 /****************** Bits definition for GPIO_PUPDR register *****************/
9756 #define GPIO_PUPDR_PUPD0_Pos (0U)
9757 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
9758 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
9759 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
9760 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
9761
9762 #define GPIO_PUPDR_PUPD1_Pos (2U)
9763 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
9764 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
9765 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
9766 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
9767
9768 #define GPIO_PUPDR_PUPD2_Pos (4U)
9769 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
9770 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
9771 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
9772 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
9773
9774 #define GPIO_PUPDR_PUPD3_Pos (6U)
9775 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
9776 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
9777 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
9778 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
9779
9780 #define GPIO_PUPDR_PUPD4_Pos (8U)
9781 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
9782 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
9783 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
9784 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
9785
9786 #define GPIO_PUPDR_PUPD5_Pos (10U)
9787 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
9788 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
9789 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
9790 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
9791
9792 #define GPIO_PUPDR_PUPD6_Pos (12U)
9793 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
9794 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
9795 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
9796 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
9797
9798 #define GPIO_PUPDR_PUPD7_Pos (14U)
9799 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
9800 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
9801 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
9802 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
9803
9804 #define GPIO_PUPDR_PUPD8_Pos (16U)
9805 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
9806 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
9807 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
9808 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
9809
9810 #define GPIO_PUPDR_PUPD9_Pos (18U)
9811 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
9812 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
9813 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
9814 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
9815
9816 #define GPIO_PUPDR_PUPD10_Pos (20U)
9817 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
9818 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
9819 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
9820 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
9821
9822 #define GPIO_PUPDR_PUPD11_Pos (22U)
9823 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
9824 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
9825 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
9826 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
9827
9828 #define GPIO_PUPDR_PUPD12_Pos (24U)
9829 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
9830 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
9831 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
9832 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
9833
9834 #define GPIO_PUPDR_PUPD13_Pos (26U)
9835 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
9836 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
9837 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
9838 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
9839
9840 #define GPIO_PUPDR_PUPD14_Pos (28U)
9841 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
9842 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
9843 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
9844 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
9845
9846 #define GPIO_PUPDR_PUPD15_Pos (30U)
9847 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
9848 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
9849 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
9850 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
9851
9852 /****************** Bits definition for GPIO_IDR register *******************/
9853 #define GPIO_IDR_ID0_Pos (0U)
9854 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
9855 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
9856 #define GPIO_IDR_ID1_Pos (1U)
9857 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
9858 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
9859 #define GPIO_IDR_ID2_Pos (2U)
9860 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
9861 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
9862 #define GPIO_IDR_ID3_Pos (3U)
9863 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
9864 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
9865 #define GPIO_IDR_ID4_Pos (4U)
9866 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
9867 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
9868 #define GPIO_IDR_ID5_Pos (5U)
9869 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
9870 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
9871 #define GPIO_IDR_ID6_Pos (6U)
9872 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
9873 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
9874 #define GPIO_IDR_ID7_Pos (7U)
9875 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
9876 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
9877 #define GPIO_IDR_ID8_Pos (8U)
9878 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
9879 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
9880 #define GPIO_IDR_ID9_Pos (9U)
9881 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
9882 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
9883 #define GPIO_IDR_ID10_Pos (10U)
9884 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
9885 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
9886 #define GPIO_IDR_ID11_Pos (11U)
9887 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
9888 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
9889 #define GPIO_IDR_ID12_Pos (12U)
9890 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
9891 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
9892 #define GPIO_IDR_ID13_Pos (13U)
9893 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
9894 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
9895 #define GPIO_IDR_ID14_Pos (14U)
9896 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
9897 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
9898 #define GPIO_IDR_ID15_Pos (15U)
9899 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
9900 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
9901
9902 /****************** Bits definition for GPIO_ODR register *******************/
9903 #define GPIO_ODR_OD0_Pos (0U)
9904 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
9905 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
9906 #define GPIO_ODR_OD1_Pos (1U)
9907 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
9908 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
9909 #define GPIO_ODR_OD2_Pos (2U)
9910 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
9911 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
9912 #define GPIO_ODR_OD3_Pos (3U)
9913 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
9914 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
9915 #define GPIO_ODR_OD4_Pos (4U)
9916 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
9917 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
9918 #define GPIO_ODR_OD5_Pos (5U)
9919 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
9920 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
9921 #define GPIO_ODR_OD6_Pos (6U)
9922 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
9923 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
9924 #define GPIO_ODR_OD7_Pos (7U)
9925 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
9926 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
9927 #define GPIO_ODR_OD8_Pos (8U)
9928 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
9929 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
9930 #define GPIO_ODR_OD9_Pos (9U)
9931 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
9932 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
9933 #define GPIO_ODR_OD10_Pos (10U)
9934 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
9935 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
9936 #define GPIO_ODR_OD11_Pos (11U)
9937 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
9938 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
9939 #define GPIO_ODR_OD12_Pos (12U)
9940 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
9941 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
9942 #define GPIO_ODR_OD13_Pos (13U)
9943 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
9944 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
9945 #define GPIO_ODR_OD14_Pos (14U)
9946 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
9947 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
9948 #define GPIO_ODR_OD15_Pos (15U)
9949 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
9950 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
9951
9952 /****************** Bits definition for GPIO_BSRR register ******************/
9953 #define GPIO_BSRR_BS0_Pos (0U)
9954 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
9955 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
9956 #define GPIO_BSRR_BS1_Pos (1U)
9957 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
9958 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
9959 #define GPIO_BSRR_BS2_Pos (2U)
9960 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
9961 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
9962 #define GPIO_BSRR_BS3_Pos (3U)
9963 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
9964 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
9965 #define GPIO_BSRR_BS4_Pos (4U)
9966 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
9967 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
9968 #define GPIO_BSRR_BS5_Pos (5U)
9969 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
9970 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
9971 #define GPIO_BSRR_BS6_Pos (6U)
9972 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
9973 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
9974 #define GPIO_BSRR_BS7_Pos (7U)
9975 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
9976 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
9977 #define GPIO_BSRR_BS8_Pos (8U)
9978 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
9979 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
9980 #define GPIO_BSRR_BS9_Pos (9U)
9981 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
9982 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
9983 #define GPIO_BSRR_BS10_Pos (10U)
9984 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
9985 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
9986 #define GPIO_BSRR_BS11_Pos (11U)
9987 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
9988 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
9989 #define GPIO_BSRR_BS12_Pos (12U)
9990 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
9991 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
9992 #define GPIO_BSRR_BS13_Pos (13U)
9993 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
9994 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
9995 #define GPIO_BSRR_BS14_Pos (14U)
9996 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
9997 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
9998 #define GPIO_BSRR_BS15_Pos (15U)
9999 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
10000 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
10001 #define GPIO_BSRR_BR0_Pos (16U)
10002 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
10003 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
10004 #define GPIO_BSRR_BR1_Pos (17U)
10005 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
10006 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
10007 #define GPIO_BSRR_BR2_Pos (18U)
10008 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
10009 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
10010 #define GPIO_BSRR_BR3_Pos (19U)
10011 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
10012 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
10013 #define GPIO_BSRR_BR4_Pos (20U)
10014 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
10015 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
10016 #define GPIO_BSRR_BR5_Pos (21U)
10017 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
10018 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
10019 #define GPIO_BSRR_BR6_Pos (22U)
10020 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
10021 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
10022 #define GPIO_BSRR_BR7_Pos (23U)
10023 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
10024 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
10025 #define GPIO_BSRR_BR8_Pos (24U)
10026 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
10027 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
10028 #define GPIO_BSRR_BR9_Pos (25U)
10029 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
10030 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
10031 #define GPIO_BSRR_BR10_Pos (26U)
10032 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
10033 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
10034 #define GPIO_BSRR_BR11_Pos (27U)
10035 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
10036 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
10037 #define GPIO_BSRR_BR12_Pos (28U)
10038 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
10039 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
10040 #define GPIO_BSRR_BR13_Pos (29U)
10041 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
10042 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
10043 #define GPIO_BSRR_BR14_Pos (30U)
10044 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
10045 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
10046 #define GPIO_BSRR_BR15_Pos (31U)
10047 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
10048 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
10049
10050 /****************** Bit definition for GPIO_LCKR register *********************/
10051 #define GPIO_LCKR_LCK0_Pos (0U)
10052 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
10053 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10054 #define GPIO_LCKR_LCK1_Pos (1U)
10055 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
10056 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10057 #define GPIO_LCKR_LCK2_Pos (2U)
10058 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
10059 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10060 #define GPIO_LCKR_LCK3_Pos (3U)
10061 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
10062 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10063 #define GPIO_LCKR_LCK4_Pos (4U)
10064 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
10065 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10066 #define GPIO_LCKR_LCK5_Pos (5U)
10067 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
10068 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10069 #define GPIO_LCKR_LCK6_Pos (6U)
10070 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
10071 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10072 #define GPIO_LCKR_LCK7_Pos (7U)
10073 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
10074 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10075 #define GPIO_LCKR_LCK8_Pos (8U)
10076 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
10077 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10078 #define GPIO_LCKR_LCK9_Pos (9U)
10079 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
10080 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10081 #define GPIO_LCKR_LCK10_Pos (10U)
10082 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
10083 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10084 #define GPIO_LCKR_LCK11_Pos (11U)
10085 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
10086 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10087 #define GPIO_LCKR_LCK12_Pos (12U)
10088 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
10089 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10090 #define GPIO_LCKR_LCK13_Pos (13U)
10091 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
10092 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10093 #define GPIO_LCKR_LCK14_Pos (14U)
10094 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
10095 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10096 #define GPIO_LCKR_LCK15_Pos (15U)
10097 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
10098 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10099 #define GPIO_LCKR_LCKK_Pos (16U)
10100 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
10101 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10102
10103 /****************** Bit definition for GPIO_AFRL register ********************/
10104 #define GPIO_AFRL_AFSEL0_Pos (0U)
10105 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
10106 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
10107 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
10108 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
10109 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
10110 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
10111 #define GPIO_AFRL_AFSEL1_Pos (4U)
10112 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
10113 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
10114 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
10115 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
10116 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
10117 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
10118 #define GPIO_AFRL_AFSEL2_Pos (8U)
10119 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
10120 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
10121 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
10122 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
10123 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
10124 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
10125 #define GPIO_AFRL_AFSEL3_Pos (12U)
10126 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
10127 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
10128 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
10129 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
10130 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
10131 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
10132 #define GPIO_AFRL_AFSEL4_Pos (16U)
10133 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
10134 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
10135 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
10136 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
10137 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
10138 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
10139 #define GPIO_AFRL_AFSEL5_Pos (20U)
10140 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
10141 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
10142 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
10143 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
10144 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
10145 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
10146 #define GPIO_AFRL_AFSEL6_Pos (24U)
10147 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
10148 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
10149 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
10150 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
10151 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
10152 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
10153 #define GPIO_AFRL_AFSEL7_Pos (28U)
10154 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
10155 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
10156 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
10157 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
10158 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
10159 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
10160
10161 /* Legacy defines */
10162 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
10163 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
10164 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
10165 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
10166 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
10167 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
10168 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
10169 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
10170
10171 /****************** Bit definition for GPIO_AFRH register ********************/
10172 #define GPIO_AFRH_AFSEL8_Pos (0U)
10173 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
10174 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
10175 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
10176 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
10177 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
10178 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
10179 #define GPIO_AFRH_AFSEL9_Pos (4U)
10180 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
10181 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
10182 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
10183 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
10184 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
10185 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
10186 #define GPIO_AFRH_AFSEL10_Pos (8U)
10187 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
10188 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
10189 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
10190 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
10191 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
10192 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
10193 #define GPIO_AFRH_AFSEL11_Pos (12U)
10194 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
10195 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
10196 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
10197 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
10198 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
10199 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
10200 #define GPIO_AFRH_AFSEL12_Pos (16U)
10201 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
10202 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
10203 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
10204 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
10205 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
10206 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
10207 #define GPIO_AFRH_AFSEL13_Pos (20U)
10208 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
10209 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
10210 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
10211 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
10212 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
10213 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
10214 #define GPIO_AFRH_AFSEL14_Pos (24U)
10215 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
10216 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
10217 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
10218 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
10219 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
10220 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
10221 #define GPIO_AFRH_AFSEL15_Pos (28U)
10222 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
10223 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
10224 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
10225 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
10226 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
10227 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
10228
10229 /* Legacy defines */
10230 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
10231 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
10232 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
10233 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
10234 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10235 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10236 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10237 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10238
10239 /******************************************************************************/
10240 /* */
10241 /* HSEM HW Semaphore */
10242 /* */
10243 /******************************************************************************/
10244 /******************** Bit definition for HSEM_R register ********************/
10245 #define HSEM_R_PROCID_Pos (0U)
10246 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
10247 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
10248 #define HSEM_R_COREID_Pos (8U)
10249 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
10250 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
10251 #define HSEM_R_LOCK_Pos (31U)
10252 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
10253 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
10254
10255 /******************** Bit definition for HSEM_RLR register ******************/
10256 #define HSEM_RLR_PROCID_Pos (0U)
10257 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
10258 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
10259 #define HSEM_RLR_COREID_Pos (8U)
10260 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
10261 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
10262 #define HSEM_RLR_LOCK_Pos (31U)
10263 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
10264 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
10265
10266 /******************** Bit definition for HSEM_C1IER register *****************/
10267 #define HSEM_C1IER_ISE0_Pos (0U)
10268 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
10269 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
10270 #define HSEM_C1IER_ISE1_Pos (1U)
10271 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
10272 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
10273 #define HSEM_C1IER_ISE2_Pos (2U)
10274 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
10275 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
10276 #define HSEM_C1IER_ISE3_Pos (3U)
10277 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
10278 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
10279 #define HSEM_C1IER_ISE4_Pos (4U)
10280 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
10281 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
10282 #define HSEM_C1IER_ISE5_Pos (5U)
10283 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
10284 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
10285 #define HSEM_C1IER_ISE6_Pos (6U)
10286 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
10287 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
10288 #define HSEM_C1IER_ISE7_Pos (7U)
10289 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
10290 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
10291 #define HSEM_C1IER_ISE8_Pos (8U)
10292 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
10293 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
10294 #define HSEM_C1IER_ISE9_Pos (9U)
10295 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
10296 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
10297 #define HSEM_C1IER_ISE10_Pos (10U)
10298 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
10299 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
10300 #define HSEM_C1IER_ISE11_Pos (11U)
10301 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
10302 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
10303 #define HSEM_C1IER_ISE12_Pos (12U)
10304 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
10305 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
10306 #define HSEM_C1IER_ISE13_Pos (13U)
10307 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
10308 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
10309 #define HSEM_C1IER_ISE14_Pos (14U)
10310 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
10311 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
10312 #define HSEM_C1IER_ISE15_Pos (15U)
10313 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
10314 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
10315 #define HSEM_C1IER_ISE16_Pos (16U)
10316 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
10317 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
10318 #define HSEM_C1IER_ISE17_Pos (17U)
10319 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
10320 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
10321 #define HSEM_C1IER_ISE18_Pos (18U)
10322 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
10323 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
10324 #define HSEM_C1IER_ISE19_Pos (19U)
10325 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
10326 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
10327 #define HSEM_C1IER_ISE20_Pos (20U)
10328 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
10329 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
10330 #define HSEM_C1IER_ISE21_Pos (21U)
10331 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
10332 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
10333 #define HSEM_C1IER_ISE22_Pos (22U)
10334 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
10335 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
10336 #define HSEM_C1IER_ISE23_Pos (23U)
10337 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
10338 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
10339 #define HSEM_C1IER_ISE24_Pos (24U)
10340 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
10341 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
10342 #define HSEM_C1IER_ISE25_Pos (25U)
10343 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
10344 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
10345 #define HSEM_C1IER_ISE26_Pos (26U)
10346 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
10347 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
10348 #define HSEM_C1IER_ISE27_Pos (27U)
10349 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
10350 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
10351 #define HSEM_C1IER_ISE28_Pos (28U)
10352 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
10353 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
10354 #define HSEM_C1IER_ISE29_Pos (29U)
10355 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
10356 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
10357 #define HSEM_C1IER_ISE30_Pos (30U)
10358 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
10359 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
10360 #define HSEM_C1IER_ISE31_Pos (31U)
10361 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
10362 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
10363
10364 /******************** Bit definition for HSEM_C1ICR register *****************/
10365 #define HSEM_C1ICR_ISC0_Pos (0U)
10366 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
10367 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
10368 #define HSEM_C1ICR_ISC1_Pos (1U)
10369 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
10370 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
10371 #define HSEM_C1ICR_ISC2_Pos (2U)
10372 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
10373 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
10374 #define HSEM_C1ICR_ISC3_Pos (3U)
10375 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
10376 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
10377 #define HSEM_C1ICR_ISC4_Pos (4U)
10378 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
10379 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
10380 #define HSEM_C1ICR_ISC5_Pos (5U)
10381 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
10382 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
10383 #define HSEM_C1ICR_ISC6_Pos (6U)
10384 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
10385 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
10386 #define HSEM_C1ICR_ISC7_Pos (7U)
10387 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
10388 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
10389 #define HSEM_C1ICR_ISC8_Pos (8U)
10390 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
10391 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
10392 #define HSEM_C1ICR_ISC9_Pos (9U)
10393 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
10394 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
10395 #define HSEM_C1ICR_ISC10_Pos (10U)
10396 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
10397 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
10398 #define HSEM_C1ICR_ISC11_Pos (11U)
10399 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
10400 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
10401 #define HSEM_C1ICR_ISC12_Pos (12U)
10402 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
10403 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
10404 #define HSEM_C1ICR_ISC13_Pos (13U)
10405 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
10406 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
10407 #define HSEM_C1ICR_ISC14_Pos (14U)
10408 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
10409 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
10410 #define HSEM_C1ICR_ISC15_Pos (15U)
10411 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
10412 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
10413 #define HSEM_C1ICR_ISC16_Pos (16U)
10414 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
10415 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
10416 #define HSEM_C1ICR_ISC17_Pos (17U)
10417 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
10418 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
10419 #define HSEM_C1ICR_ISC18_Pos (18U)
10420 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
10421 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
10422 #define HSEM_C1ICR_ISC19_Pos (19U)
10423 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
10424 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
10425 #define HSEM_C1ICR_ISC20_Pos (20U)
10426 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
10427 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
10428 #define HSEM_C1ICR_ISC21_Pos (21U)
10429 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
10430 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
10431 #define HSEM_C1ICR_ISC22_Pos (22U)
10432 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
10433 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
10434 #define HSEM_C1ICR_ISC23_Pos (23U)
10435 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
10436 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
10437 #define HSEM_C1ICR_ISC24_Pos (24U)
10438 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
10439 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
10440 #define HSEM_C1ICR_ISC25_Pos (25U)
10441 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
10442 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
10443 #define HSEM_C1ICR_ISC26_Pos (26U)
10444 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
10445 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
10446 #define HSEM_C1ICR_ISC27_Pos (27U)
10447 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
10448 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
10449 #define HSEM_C1ICR_ISC28_Pos (28U)
10450 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
10451 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
10452 #define HSEM_C1ICR_ISC29_Pos (29U)
10453 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
10454 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
10455 #define HSEM_C1ICR_ISC30_Pos (30U)
10456 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
10457 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
10458 #define HSEM_C1ICR_ISC31_Pos (31U)
10459 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
10460 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
10461
10462 /******************** Bit definition for HSEM_C1ISR register *****************/
10463 #define HSEM_C1ISR_ISF0_Pos (0U)
10464 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
10465 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
10466 #define HSEM_C1ISR_ISF1_Pos (1U)
10467 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
10468 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
10469 #define HSEM_C1ISR_ISF2_Pos (2U)
10470 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
10471 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
10472 #define HSEM_C1ISR_ISF3_Pos (3U)
10473 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
10474 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
10475 #define HSEM_C1ISR_ISF4_Pos (4U)
10476 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
10477 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
10478 #define HSEM_C1ISR_ISF5_Pos (5U)
10479 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
10480 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
10481 #define HSEM_C1ISR_ISF6_Pos (6U)
10482 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
10483 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
10484 #define HSEM_C1ISR_ISF7_Pos (7U)
10485 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
10486 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
10487 #define HSEM_C1ISR_ISF8_Pos (8U)
10488 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
10489 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
10490 #define HSEM_C1ISR_ISF9_Pos (9U)
10491 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
10492 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
10493 #define HSEM_C1ISR_ISF10_Pos (10U)
10494 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
10495 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
10496 #define HSEM_C1ISR_ISF11_Pos (11U)
10497 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
10498 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
10499 #define HSEM_C1ISR_ISF12_Pos (12U)
10500 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
10501 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
10502 #define HSEM_C1ISR_ISF13_Pos (13U)
10503 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
10504 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
10505 #define HSEM_C1ISR_ISF14_Pos (14U)
10506 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
10507 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
10508 #define HSEM_C1ISR_ISF15_Pos (15U)
10509 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
10510 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
10511 #define HSEM_C1ISR_ISF16_Pos (16U)
10512 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
10513 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
10514 #define HSEM_C1ISR_ISF17_Pos (17U)
10515 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
10516 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
10517 #define HSEM_C1ISR_ISF18_Pos (18U)
10518 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
10519 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
10520 #define HSEM_C1ISR_ISF19_Pos (19U)
10521 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
10522 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
10523 #define HSEM_C1ISR_ISF20_Pos (20U)
10524 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
10525 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
10526 #define HSEM_C1ISR_ISF21_Pos (21U)
10527 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
10528 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
10529 #define HSEM_C1ISR_ISF22_Pos (22U)
10530 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
10531 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
10532 #define HSEM_C1ISR_ISF23_Pos (23U)
10533 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
10534 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
10535 #define HSEM_C1ISR_ISF24_Pos (24U)
10536 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
10537 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
10538 #define HSEM_C1ISR_ISF25_Pos (25U)
10539 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
10540 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
10541 #define HSEM_C1ISR_ISF26_Pos (26U)
10542 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
10543 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
10544 #define HSEM_C1ISR_ISF27_Pos (27U)
10545 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
10546 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
10547 #define HSEM_C1ISR_ISF28_Pos (28U)
10548 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
10549 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
10550 #define HSEM_C1ISR_ISF29_Pos (29U)
10551 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
10552 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
10553 #define HSEM_C1ISR_ISF30_Pos (30U)
10554 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
10555 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
10556 #define HSEM_C1ISR_ISF31_Pos (31U)
10557 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
10558 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
10559
10560 /******************** Bit definition for HSEM_C1MISR register *****************/
10561 #define HSEM_C1MISR_MISF0_Pos (0U)
10562 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
10563 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
10564 #define HSEM_C1MISR_MISF1_Pos (1U)
10565 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
10566 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
10567 #define HSEM_C1MISR_MISF2_Pos (2U)
10568 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
10569 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
10570 #define HSEM_C1MISR_MISF3_Pos (3U)
10571 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
10572 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
10573 #define HSEM_C1MISR_MISF4_Pos (4U)
10574 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
10575 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
10576 #define HSEM_C1MISR_MISF5_Pos (5U)
10577 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
10578 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
10579 #define HSEM_C1MISR_MISF6_Pos (6U)
10580 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
10581 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
10582 #define HSEM_C1MISR_MISF7_Pos (7U)
10583 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
10584 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
10585 #define HSEM_C1MISR_MISF8_Pos (8U)
10586 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
10587 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
10588 #define HSEM_C1MISR_MISF9_Pos (9U)
10589 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
10590 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
10591 #define HSEM_C1MISR_MISF10_Pos (10U)
10592 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
10593 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
10594 #define HSEM_C1MISR_MISF11_Pos (11U)
10595 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
10596 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
10597 #define HSEM_C1MISR_MISF12_Pos (12U)
10598 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
10599 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
10600 #define HSEM_C1MISR_MISF13_Pos (13U)
10601 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
10602 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
10603 #define HSEM_C1MISR_MISF14_Pos (14U)
10604 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
10605 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
10606 #define HSEM_C1MISR_MISF15_Pos (15U)
10607 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
10608 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
10609 #define HSEM_C1MISR_MISF16_Pos (16U)
10610 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
10611 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
10612 #define HSEM_C1MISR_MISF17_Pos (17U)
10613 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
10614 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
10615 #define HSEM_C1MISR_MISF18_Pos (18U)
10616 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
10617 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
10618 #define HSEM_C1MISR_MISF19_Pos (19U)
10619 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
10620 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
10621 #define HSEM_C1MISR_MISF20_Pos (20U)
10622 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
10623 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
10624 #define HSEM_C1MISR_MISF21_Pos (21U)
10625 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
10626 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
10627 #define HSEM_C1MISR_MISF22_Pos (22U)
10628 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
10629 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
10630 #define HSEM_C1MISR_MISF23_Pos (23U)
10631 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
10632 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
10633 #define HSEM_C1MISR_MISF24_Pos (24U)
10634 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
10635 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
10636 #define HSEM_C1MISR_MISF25_Pos (25U)
10637 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
10638 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
10639 #define HSEM_C1MISR_MISF26_Pos (26U)
10640 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
10641 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
10642 #define HSEM_C1MISR_MISF27_Pos (27U)
10643 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
10644 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
10645 #define HSEM_C1MISR_MISF28_Pos (28U)
10646 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
10647 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
10648 #define HSEM_C1MISR_MISF29_Pos (29U)
10649 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
10650 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
10651 #define HSEM_C1MISR_MISF30_Pos (30U)
10652 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
10653 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
10654 #define HSEM_C1MISR_MISF31_Pos (31U)
10655 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
10656 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
10657
10658 /******************** Bit definition for HSEM_CR register *****************/
10659 #define HSEM_CR_COREID_Pos (8U)
10660 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
10661 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
10662 #define HSEM_CR_KEY_Pos (16U)
10663 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
10664 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
10665
10666 /******************** Bit definition for HSEM_KEYR register *****************/
10667 #define HSEM_KEYR_KEY_Pos (16U)
10668 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
10669 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
10670
10671 /******************************************************************************/
10672 /* */
10673 /* Inter-integrated Circuit Interface (I2C) */
10674 /* */
10675 /******************************************************************************/
10676 /******************* Bit definition for I2C_CR1 register *******************/
10677 #define I2C_CR1_PE_Pos (0U)
10678 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
10679 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
10680 #define I2C_CR1_TXIE_Pos (1U)
10681 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
10682 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
10683 #define I2C_CR1_RXIE_Pos (2U)
10684 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
10685 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
10686 #define I2C_CR1_ADDRIE_Pos (3U)
10687 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
10688 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
10689 #define I2C_CR1_NACKIE_Pos (4U)
10690 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
10691 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
10692 #define I2C_CR1_STOPIE_Pos (5U)
10693 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
10694 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
10695 #define I2C_CR1_TCIE_Pos (6U)
10696 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
10697 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
10698 #define I2C_CR1_ERRIE_Pos (7U)
10699 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
10700 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
10701 #define I2C_CR1_DNF_Pos (8U)
10702 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
10703 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
10704 #define I2C_CR1_ANFOFF_Pos (12U)
10705 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
10706 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
10707 #define I2C_CR1_TXDMAEN_Pos (14U)
10708 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
10709 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
10710 #define I2C_CR1_RXDMAEN_Pos (15U)
10711 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
10712 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
10713 #define I2C_CR1_SBC_Pos (16U)
10714 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
10715 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
10716 #define I2C_CR1_NOSTRETCH_Pos (17U)
10717 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
10718 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
10719 #define I2C_CR1_WUPEN_Pos (18U)
10720 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
10721 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
10722 #define I2C_CR1_GCEN_Pos (19U)
10723 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
10724 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
10725 #define I2C_CR1_SMBHEN_Pos (20U)
10726 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
10727 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
10728 #define I2C_CR1_SMBDEN_Pos (21U)
10729 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
10730 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
10731 #define I2C_CR1_ALERTEN_Pos (22U)
10732 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
10733 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
10734 #define I2C_CR1_PECEN_Pos (23U)
10735 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
10736 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
10737
10738 /****************** Bit definition for I2C_CR2 register ********************/
10739 #define I2C_CR2_SADD_Pos (0U)
10740 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
10741 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
10742 #define I2C_CR2_RD_WRN_Pos (10U)
10743 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
10744 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
10745 #define I2C_CR2_ADD10_Pos (11U)
10746 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
10747 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
10748 #define I2C_CR2_HEAD10R_Pos (12U)
10749 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
10750 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
10751 #define I2C_CR2_START_Pos (13U)
10752 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
10753 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
10754 #define I2C_CR2_STOP_Pos (14U)
10755 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
10756 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
10757 #define I2C_CR2_NACK_Pos (15U)
10758 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
10759 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
10760 #define I2C_CR2_NBYTES_Pos (16U)
10761 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
10762 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
10763 #define I2C_CR2_RELOAD_Pos (24U)
10764 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
10765 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
10766 #define I2C_CR2_AUTOEND_Pos (25U)
10767 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
10768 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
10769 #define I2C_CR2_PECBYTE_Pos (26U)
10770 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
10771 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
10772
10773 /******************* Bit definition for I2C_OAR1 register ******************/
10774 #define I2C_OAR1_OA1_Pos (0U)
10775 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
10776 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
10777 #define I2C_OAR1_OA1MODE_Pos (10U)
10778 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
10779 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
10780 #define I2C_OAR1_OA1EN_Pos (15U)
10781 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
10782 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
10783
10784 /******************* Bit definition for I2C_OAR2 register ******************/
10785 #define I2C_OAR2_OA2_Pos (1U)
10786 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
10787 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
10788 #define I2C_OAR2_OA2MSK_Pos (8U)
10789 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
10790 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
10791 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
10792 #define I2C_OAR2_OA2MASK01_Pos (8U)
10793 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
10794 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
10795 #define I2C_OAR2_OA2MASK02_Pos (9U)
10796 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
10797 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
10798 #define I2C_OAR2_OA2MASK03_Pos (8U)
10799 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
10800 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
10801 #define I2C_OAR2_OA2MASK04_Pos (10U)
10802 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
10803 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
10804 #define I2C_OAR2_OA2MASK05_Pos (8U)
10805 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
10806 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
10807 #define I2C_OAR2_OA2MASK06_Pos (9U)
10808 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
10809 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
10810 #define I2C_OAR2_OA2MASK07_Pos (8U)
10811 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
10812 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
10813 #define I2C_OAR2_OA2EN_Pos (15U)
10814 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
10815 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
10816
10817 /******************* Bit definition for I2C_TIMINGR register *******************/
10818 #define I2C_TIMINGR_SCLL_Pos (0U)
10819 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
10820 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
10821 #define I2C_TIMINGR_SCLH_Pos (8U)
10822 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
10823 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
10824 #define I2C_TIMINGR_SDADEL_Pos (16U)
10825 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
10826 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
10827 #define I2C_TIMINGR_SCLDEL_Pos (20U)
10828 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
10829 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
10830 #define I2C_TIMINGR_PRESC_Pos (28U)
10831 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
10832 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
10833
10834 /******************* Bit definition for I2C_TIMEOUTR register *******************/
10835 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
10836 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
10837 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
10838 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
10839 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
10840 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
10841 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
10842 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
10843 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
10844 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
10845 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
10846 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
10847 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
10848 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
10849 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
10850
10851 /****************** Bit definition for I2C_ISR register *********************/
10852 #define I2C_ISR_TXE_Pos (0U)
10853 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
10854 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
10855 #define I2C_ISR_TXIS_Pos (1U)
10856 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
10857 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
10858 #define I2C_ISR_RXNE_Pos (2U)
10859 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
10860 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
10861 #define I2C_ISR_ADDR_Pos (3U)
10862 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
10863 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
10864 #define I2C_ISR_NACKF_Pos (4U)
10865 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
10866 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
10867 #define I2C_ISR_STOPF_Pos (5U)
10868 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
10869 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
10870 #define I2C_ISR_TC_Pos (6U)
10871 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
10872 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
10873 #define I2C_ISR_TCR_Pos (7U)
10874 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
10875 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
10876 #define I2C_ISR_BERR_Pos (8U)
10877 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
10878 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
10879 #define I2C_ISR_ARLO_Pos (9U)
10880 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
10881 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
10882 #define I2C_ISR_OVR_Pos (10U)
10883 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
10884 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
10885 #define I2C_ISR_PECERR_Pos (11U)
10886 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
10887 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
10888 #define I2C_ISR_TIMEOUT_Pos (12U)
10889 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
10890 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
10891 #define I2C_ISR_ALERT_Pos (13U)
10892 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
10893 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
10894 #define I2C_ISR_BUSY_Pos (15U)
10895 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
10896 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
10897 #define I2C_ISR_DIR_Pos (16U)
10898 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
10899 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
10900 #define I2C_ISR_ADDCODE_Pos (17U)
10901 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
10902 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
10903
10904 /****************** Bit definition for I2C_ICR register *********************/
10905 #define I2C_ICR_ADDRCF_Pos (3U)
10906 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
10907 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
10908 #define I2C_ICR_NACKCF_Pos (4U)
10909 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
10910 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
10911 #define I2C_ICR_STOPCF_Pos (5U)
10912 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
10913 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
10914 #define I2C_ICR_BERRCF_Pos (8U)
10915 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
10916 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
10917 #define I2C_ICR_ARLOCF_Pos (9U)
10918 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
10919 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
10920 #define I2C_ICR_OVRCF_Pos (10U)
10921 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
10922 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
10923 #define I2C_ICR_PECCF_Pos (11U)
10924 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
10925 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
10926 #define I2C_ICR_TIMOUTCF_Pos (12U)
10927 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
10928 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
10929 #define I2C_ICR_ALERTCF_Pos (13U)
10930 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
10931 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
10932
10933 /****************** Bit definition for I2C_PECR register *********************/
10934 #define I2C_PECR_PEC_Pos (0U)
10935 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
10936 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
10937
10938 /****************** Bit definition for I2C_RXDR register *********************/
10939 #define I2C_RXDR_RXDATA_Pos (0U)
10940 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
10941 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
10942
10943 /****************** Bit definition for I2C_TXDR register *********************/
10944 #define I2C_TXDR_TXDATA_Pos (0U)
10945 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
10946 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
10947
10948 /******************************************************************************/
10949 /* */
10950 /* Independent WATCHDOG */
10951 /* */
10952 /******************************************************************************/
10953 /******************* Bit definition for IWDG_KR register ********************/
10954 #define IWDG_KR_KEY_Pos (0U)
10955 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
10956 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
10957
10958 /******************* Bit definition for IWDG_PR register ********************/
10959 #define IWDG_PR_PR_Pos (0U)
10960 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
10961 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
10962 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
10963 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
10964 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
10965
10966 /******************* Bit definition for IWDG_RLR register *******************/
10967 #define IWDG_RLR_RL_Pos (0U)
10968 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
10969 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
10970
10971 /******************* Bit definition for IWDG_SR register ********************/
10972 #define IWDG_SR_PVU_Pos (0U)
10973 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
10974 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
10975 #define IWDG_SR_RVU_Pos (1U)
10976 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
10977 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
10978 #define IWDG_SR_WVU_Pos (2U)
10979 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
10980 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
10981
10982 /******************* Bit definition for IWDG_KR register ********************/
10983 #define IWDG_WINR_WIN_Pos (0U)
10984 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
10985 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
10986
10987 /******************************************************************************/
10988 /* */
10989 /* JPEG Encoder/Decoder */
10990 /* */
10991 /******************************************************************************/
10992 /******************** Bit definition for CONFR0 register ********************/
10993 #define JPEG_CONFR0_START_Pos (0U)
10994 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
10995 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
10996
10997 /******************** Bit definition for CONFR1 register ********************/
10998 #define JPEG_CONFR1_NF_Pos (0U)
10999 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
11000 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
11001 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
11002 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
11003 #define JPEG_CONFR1_DE_Pos (3U)
11004 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
11005 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
11006 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
11007 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
11008 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
11009 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
11010 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
11011 #define JPEG_CONFR1_NS_Pos (6U)
11012 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
11013 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
11014 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
11015 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
11016 #define JPEG_CONFR1_HDR_Pos (8U)
11017 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
11018 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
11019 #define JPEG_CONFR1_YSIZE_Pos (16U)
11020 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
11021 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
11022
11023 /******************** Bit definition for CONFR2 register ********************/
11024 #define JPEG_CONFR2_NMCU_Pos (0U)
11025 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
11026 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
11027
11028 /******************** Bit definition for CONFR3 register ********************/
11029 #define JPEG_CONFR3_XSIZE_Pos (16U)
11030 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
11031 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
11032
11033 /******************** Bit definition for CONFR4 register ********************/
11034 #define JPEG_CONFR4_HD_Pos (0U)
11035 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
11036 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11037 #define JPEG_CONFR4_HA_Pos (1U)
11038 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
11039 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11040 #define JPEG_CONFR4_QT_Pos (2U)
11041 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
11042 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
11043 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
11044 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
11045 #define JPEG_CONFR4_NB_Pos (4U)
11046 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
11047 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11048 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
11049 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
11050 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
11051 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
11052 #define JPEG_CONFR4_VSF_Pos (8U)
11053 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
11054 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
11055 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
11056 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
11057 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
11058 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
11059 #define JPEG_CONFR4_HSF_Pos (12U)
11060 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
11061 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
11062 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
11063 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
11064 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
11065 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
11066
11067 /******************** Bit definition for CONFR5 register ********************/
11068 #define JPEG_CONFR5_HD_Pos (0U)
11069 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
11070 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11071 #define JPEG_CONFR5_HA_Pos (1U)
11072 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
11073 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11074 #define JPEG_CONFR5_QT_Pos (2U)
11075 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
11076 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
11077 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
11078 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
11079 #define JPEG_CONFR5_NB_Pos (4U)
11080 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
11081 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11082 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
11083 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
11084 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
11085 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
11086 #define JPEG_CONFR5_VSF_Pos (8U)
11087 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
11088 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
11089 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
11090 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
11091 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
11092 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
11093 #define JPEG_CONFR5_HSF_Pos (12U)
11094 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
11095 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11096 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
11097 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
11098 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
11099 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
11100
11101 /******************** Bit definition for CONFR6 register ********************/
11102 #define JPEG_CONFR6_HD_Pos (0U)
11103 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
11104 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11105 #define JPEG_CONFR6_HA_Pos (1U)
11106 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
11107 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11108 #define JPEG_CONFR6_QT_Pos (2U)
11109 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
11110 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
11111 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
11112 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
11113 #define JPEG_CONFR6_NB_Pos (4U)
11114 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
11115 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11116 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
11117 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
11118 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
11119 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
11120 #define JPEG_CONFR6_VSF_Pos (8U)
11121 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
11122 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
11123 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
11124 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
11125 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
11126 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
11127 #define JPEG_CONFR6_HSF_Pos (12U)
11128 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
11129 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11130 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
11131 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
11132 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
11133 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
11134
11135 /******************** Bit definition for CONFR7 register ********************/
11136 #define JPEG_CONFR7_HD_Pos (0U)
11137 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
11138 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11139 #define JPEG_CONFR7_HA_Pos (1U)
11140 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
11141 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11142 #define JPEG_CONFR7_QT_Pos (2U)
11143 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
11144 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
11145 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
11146 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
11147 #define JPEG_CONFR7_NB_Pos (4U)
11148 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
11149 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11150 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
11151 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
11152 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
11153 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
11154 #define JPEG_CONFR7_VSF_Pos (8U)
11155 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
11156 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
11157 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
11158 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
11159 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
11160 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
11161 #define JPEG_CONFR7_HSF_Pos (12U)
11162 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
11163 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11164 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
11165 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
11166 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
11167 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
11168
11169 /******************** Bit definition for CR register ********************/
11170 #define JPEG_CR_JCEN_Pos (0U)
11171 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
11172 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
11173 #define JPEG_CR_IFTIE_Pos (1U)
11174 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
11175 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
11176 #define JPEG_CR_IFNFIE_Pos (2U)
11177 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
11178 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
11179 #define JPEG_CR_OFTIE_Pos (3U)
11180 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
11181 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
11182 #define JPEG_CR_OFNEIE_Pos (4U)
11183 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
11184 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
11185 #define JPEG_CR_EOCIE_Pos (5U)
11186 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
11187 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
11188 #define JPEG_CR_HPDIE_Pos (6U)
11189 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
11190 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
11191 #define JPEG_CR_IFF_Pos (13U)
11192 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
11193 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
11194 #define JPEG_CR_OFF_Pos (14U)
11195 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
11196 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
11197
11198 /******************** Bit definition for SR register ********************/
11199 #define JPEG_SR_IFTF_Pos (1U)
11200 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
11201 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
11202 #define JPEG_SR_IFNFF_Pos (2U)
11203 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
11204 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
11205 #define JPEG_SR_OFTF_Pos (3U)
11206 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
11207 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
11208 #define JPEG_SR_OFNEF_Pos (4U)
11209 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
11210 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
11211 #define JPEG_SR_EOCF_Pos (5U)
11212 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
11213 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
11214 #define JPEG_SR_HPDF_Pos (6U)
11215 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
11216 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
11217 #define JPEG_SR_COF_Pos (7U)
11218 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
11219 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
11220
11221 /******************** Bit definition for CFR register ********************/
11222 #define JPEG_CFR_CEOCF_Pos (4U)
11223 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
11224 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
11225 #define JPEG_CFR_CHPDF_Pos (5U)
11226 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
11227 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
11228
11229 /******************** Bit definition for DIR register ********************/
11230 #define JPEG_DIR_DATAIN_Pos (0U)
11231 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
11232 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
11233
11234 /******************** Bit definition for DOR register ********************/
11235 #define JPEG_DOR_DATAOUT_Pos (0U)
11236 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
11237 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
11238
11239 /******************************************************************************/
11240 /* */
11241 /* LCD-TFT Display Controller (LTDC) */
11242 /* */
11243 /******************************************************************************/
11244
11245 /******************** Bit definition for LTDC_SSCR register *****************/
11246
11247 #define LTDC_SSCR_VSH_Pos (0U)
11248 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
11249 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
11250 #define LTDC_SSCR_HSW_Pos (16U)
11251 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
11252 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
11253
11254 /******************** Bit definition for LTDC_BPCR register *****************/
11255
11256 #define LTDC_BPCR_AVBP_Pos (0U)
11257 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
11258 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
11259 #define LTDC_BPCR_AHBP_Pos (16U)
11260 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
11261 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
11262
11263 /******************** Bit definition for LTDC_AWCR register *****************/
11264
11265 #define LTDC_AWCR_AAH_Pos (0U)
11266 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
11267 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
11268 #define LTDC_AWCR_AAW_Pos (16U)
11269 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
11270 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
11271
11272 /******************** Bit definition for LTDC_TWCR register *****************/
11273
11274 #define LTDC_TWCR_TOTALH_Pos (0U)
11275 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
11276 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
11277 #define LTDC_TWCR_TOTALW_Pos (16U)
11278 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
11279 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
11280
11281 /******************** Bit definition for LTDC_GCR register ******************/
11282
11283 #define LTDC_GCR_LTDCEN_Pos (0U)
11284 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
11285 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
11286 #define LTDC_GCR_DBW_Pos (4U)
11287 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
11288 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
11289 #define LTDC_GCR_DGW_Pos (8U)
11290 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
11291 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
11292 #define LTDC_GCR_DRW_Pos (12U)
11293 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
11294 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
11295 #define LTDC_GCR_DEN_Pos (16U)
11296 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
11297 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
11298 #define LTDC_GCR_PCPOL_Pos (28U)
11299 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
11300 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
11301 #define LTDC_GCR_DEPOL_Pos (29U)
11302 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
11303 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
11304 #define LTDC_GCR_VSPOL_Pos (30U)
11305 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
11306 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
11307 #define LTDC_GCR_HSPOL_Pos (31U)
11308 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
11309 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
11310
11311
11312 /******************** Bit definition for LTDC_SRCR register *****************/
11313
11314 #define LTDC_SRCR_IMR_Pos (0U)
11315 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
11316 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
11317 #define LTDC_SRCR_VBR_Pos (1U)
11318 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
11319 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
11320
11321 /******************** Bit definition for LTDC_BCCR register *****************/
11322
11323 #define LTDC_BCCR_BCBLUE_Pos (0U)
11324 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
11325 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
11326 #define LTDC_BCCR_BCGREEN_Pos (8U)
11327 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
11328 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
11329 #define LTDC_BCCR_BCRED_Pos (16U)
11330 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
11331 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
11332
11333 /******************** Bit definition for LTDC_IER register ******************/
11334
11335 #define LTDC_IER_LIE_Pos (0U)
11336 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
11337 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
11338 #define LTDC_IER_FUIE_Pos (1U)
11339 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
11340 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
11341 #define LTDC_IER_TERRIE_Pos (2U)
11342 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
11343 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
11344 #define LTDC_IER_RRIE_Pos (3U)
11345 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
11346 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
11347
11348 /******************** Bit definition for LTDC_ISR register ******************/
11349
11350 #define LTDC_ISR_LIF_Pos (0U)
11351 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
11352 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
11353 #define LTDC_ISR_FUIF_Pos (1U)
11354 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
11355 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
11356 #define LTDC_ISR_TERRIF_Pos (2U)
11357 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
11358 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
11359 #define LTDC_ISR_RRIF_Pos (3U)
11360 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
11361 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
11362
11363 /******************** Bit definition for LTDC_ICR register ******************/
11364
11365 #define LTDC_ICR_CLIF_Pos (0U)
11366 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
11367 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
11368 #define LTDC_ICR_CFUIF_Pos (1U)
11369 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
11370 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
11371 #define LTDC_ICR_CTERRIF_Pos (2U)
11372 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
11373 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
11374 #define LTDC_ICR_CRRIF_Pos (3U)
11375 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
11376 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
11377
11378 /******************** Bit definition for LTDC_LIPCR register ****************/
11379
11380 #define LTDC_LIPCR_LIPOS_Pos (0U)
11381 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
11382 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
11383
11384 /******************** Bit definition for LTDC_CPSR register *****************/
11385
11386 #define LTDC_CPSR_CYPOS_Pos (0U)
11387 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
11388 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
11389 #define LTDC_CPSR_CXPOS_Pos (16U)
11390 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
11391 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
11392
11393 /******************** Bit definition for LTDC_CDSR register *****************/
11394
11395 #define LTDC_CDSR_VDES_Pos (0U)
11396 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
11397 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
11398 #define LTDC_CDSR_HDES_Pos (1U)
11399 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
11400 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
11401 #define LTDC_CDSR_VSYNCS_Pos (2U)
11402 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
11403 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
11404 #define LTDC_CDSR_HSYNCS_Pos (3U)
11405 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
11406 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
11407
11408 /******************** Bit definition for LTDC_LxCR register *****************/
11409
11410 #define LTDC_LxCR_LEN_Pos (0U)
11411 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
11412 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
11413 #define LTDC_LxCR_COLKEN_Pos (1U)
11414 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
11415 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
11416 #define LTDC_LxCR_CLUTEN_Pos (4U)
11417 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
11418 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
11419
11420 /******************** Bit definition for LTDC_LxWHPCR register **************/
11421
11422 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
11423 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
11424 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
11425 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
11426 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
11427 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
11428
11429 /******************** Bit definition for LTDC_LxWVPCR register **************/
11430
11431 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
11432 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
11433 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
11434 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
11435 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
11436 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
11437
11438 /******************** Bit definition for LTDC_LxCKCR register ***************/
11439
11440 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
11441 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
11442 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
11443 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
11444 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
11445 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
11446 #define LTDC_LxCKCR_CKRED_Pos (16U)
11447 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
11448 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
11449
11450 /******************** Bit definition for LTDC_LxPFCR register ***************/
11451
11452 #define LTDC_LxPFCR_PF_Pos (0U)
11453 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
11454 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
11455
11456 /******************** Bit definition for LTDC_LxCACR register ***************/
11457
11458 #define LTDC_LxCACR_CONSTA_Pos (0U)
11459 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
11460 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
11461
11462 /******************** Bit definition for LTDC_LxDCCR register ***************/
11463
11464 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
11465 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
11466 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
11467 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
11468 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
11469 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
11470 #define LTDC_LxDCCR_DCRED_Pos (16U)
11471 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
11472 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
11473 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
11474 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
11475 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
11476
11477 /******************** Bit definition for LTDC_LxBFCR register ***************/
11478
11479 #define LTDC_LxBFCR_BF2_Pos (0U)
11480 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
11481 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
11482 #define LTDC_LxBFCR_BF1_Pos (8U)
11483 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
11484 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
11485
11486 /******************** Bit definition for LTDC_LxCFBAR register **************/
11487
11488 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
11489 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
11490 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
11491
11492 /******************** Bit definition for LTDC_LxCFBLR register **************/
11493
11494 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
11495 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
11496 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
11497 #define LTDC_LxCFBLR_CFBP_Pos (16U)
11498 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
11499 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
11500
11501 /******************** Bit definition for LTDC_LxCFBLNR register *************/
11502
11503 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
11504 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
11505 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
11506
11507 /******************** Bit definition for LTDC_LxCLUTWR register *************/
11508
11509 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
11510 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
11511 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
11512 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
11513 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
11514 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
11515 #define LTDC_LxCLUTWR_RED_Pos (16U)
11516 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
11517 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
11518 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
11519 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
11520 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
11521
11522 /******************************************************************************/
11523 /* */
11524 /* MDMA */
11525 /* */
11526 /******************************************************************************/
11527 /******************** Bit definition for MDMA_GISR0 register ****************/
11528 #define MDMA_GISR0_GIF0_Pos (0U)
11529 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
11530 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
11531 #define MDMA_GISR0_GIF1_Pos (1U)
11532 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
11533 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
11534 #define MDMA_GISR0_GIF2_Pos (2U)
11535 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
11536 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
11537 #define MDMA_GISR0_GIF3_Pos (3U)
11538 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
11539 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
11540 #define MDMA_GISR0_GIF4_Pos (4U)
11541 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
11542 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
11543 #define MDMA_GISR0_GIF5_Pos (5U)
11544 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
11545 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
11546 #define MDMA_GISR0_GIF6_Pos (6U)
11547 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
11548 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
11549 #define MDMA_GISR0_GIF7_Pos (7U)
11550 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
11551 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
11552 #define MDMA_GISR0_GIF8_Pos (8U)
11553 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
11554 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
11555 #define MDMA_GISR0_GIF9_Pos (9U)
11556 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
11557 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
11558 #define MDMA_GISR0_GIF10_Pos (10U)
11559 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
11560 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
11561 #define MDMA_GISR0_GIF11_Pos (11U)
11562 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
11563 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
11564 #define MDMA_GISR0_GIF12_Pos (12U)
11565 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
11566 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
11567 #define MDMA_GISR0_GIF13_Pos (13U)
11568 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
11569 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
11570 #define MDMA_GISR0_GIF14_Pos (14U)
11571 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
11572 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
11573 #define MDMA_GISR0_GIF15_Pos (15U)
11574 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
11575 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
11576
11577 /******************** Bit definition for MDMA_CxISR register ****************/
11578 #define MDMA_CISR_TEIF_Pos (0U)
11579 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
11580 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
11581 #define MDMA_CISR_CTCIF_Pos (1U)
11582 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
11583 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
11584 #define MDMA_CISR_BRTIF_Pos (2U)
11585 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
11586 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
11587 #define MDMA_CISR_BTIF_Pos (3U)
11588 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
11589 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
11590 #define MDMA_CISR_TCIF_Pos (4U)
11591 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
11592 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
11593 #define MDMA_CISR_CRQA_Pos (16U)
11594 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
11595 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
11596
11597 /******************** Bit definition for MDMA_CxIFCR register ****************/
11598 #define MDMA_CIFCR_CTEIF_Pos (0U)
11599 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
11600 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
11601 #define MDMA_CIFCR_CCTCIF_Pos (1U)
11602 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
11603 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
11604 #define MDMA_CIFCR_CBRTIF_Pos (2U)
11605 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
11606 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
11607 #define MDMA_CIFCR_CBTIF_Pos (3U)
11608 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
11609 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
11610 #define MDMA_CIFCR_CLTCIF_Pos (4U)
11611 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
11612 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
11613
11614 /******************** Bit definition for MDMA_CxESR register ****************/
11615 #define MDMA_CESR_TEA_Pos (0U)
11616 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
11617 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
11618 #define MDMA_CESR_TED_Pos (7U)
11619 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
11620 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
11621 #define MDMA_CESR_TELD_Pos (8U)
11622 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
11623 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
11624 #define MDMA_CESR_TEMD_Pos (9U)
11625 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
11626 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
11627 #define MDMA_CESR_ASE_Pos (10U)
11628 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
11629 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
11630 #define MDMA_CESR_BSE_Pos (11U)
11631 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
11632 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
11633
11634 /******************** Bit definition for MDMA_CxCR register ****************/
11635 #define MDMA_CCR_EN_Pos (0U)
11636 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
11637 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
11638 #define MDMA_CCR_TEIE_Pos (1U)
11639 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
11640 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
11641 #define MDMA_CCR_CTCIE_Pos (2U)
11642 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
11643 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
11644 #define MDMA_CCR_BRTIE_Pos (3U)
11645 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
11646 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
11647 #define MDMA_CCR_BTIE_Pos (4U)
11648 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
11649 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
11650 #define MDMA_CCR_TCIE_Pos (5U)
11651 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
11652 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
11653 #define MDMA_CCR_PL_Pos (6U)
11654 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
11655 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
11656 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
11657 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
11658 #define MDMA_CCR_BEX_Pos (12U)
11659 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
11660 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
11661 #define MDMA_CCR_HEX_Pos (13U)
11662 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
11663 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
11664 #define MDMA_CCR_WEX_Pos (14U)
11665 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
11666 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
11667 #define MDMA_CCR_SWRQ_Pos (16U)
11668 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
11669 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
11670
11671 /******************** Bit definition for MDMA_CxTCR register ****************/
11672 #define MDMA_CTCR_SINC_Pos (0U)
11673 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
11674 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
11675 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
11676 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
11677 #define MDMA_CTCR_DINC_Pos (2U)
11678 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
11679 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
11680 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
11681 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
11682 #define MDMA_CTCR_SSIZE_Pos (4U)
11683 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
11684 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
11685 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
11686 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
11687 #define MDMA_CTCR_DSIZE_Pos (6U)
11688 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
11689 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
11690 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
11691 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
11692 #define MDMA_CTCR_SINCOS_Pos (8U)
11693 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
11694 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
11695 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
11696 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
11697 #define MDMA_CTCR_DINCOS_Pos (10U)
11698 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
11699 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
11700 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
11701 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
11702 #define MDMA_CTCR_SBURST_Pos (12U)
11703 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
11704 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
11705 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
11706 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
11707 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
11708 #define MDMA_CTCR_DBURST_Pos (15U)
11709 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
11710 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
11711 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
11712 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
11713 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
11714 #define MDMA_CTCR_TLEN_Pos (18U)
11715 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
11716 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
11717 #define MDMA_CTCR_PKE_Pos (25U)
11718 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
11719 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
11720 #define MDMA_CTCR_PAM_Pos (26U)
11721 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
11722 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
11723 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
11724 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
11725 #define MDMA_CTCR_TRGM_Pos (28U)
11726 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
11727 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
11728 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
11729 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
11730 #define MDMA_CTCR_SWRM_Pos (30U)
11731 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
11732 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
11733 #define MDMA_CTCR_BWM_Pos (31U)
11734 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
11735 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
11736
11737 /******************** Bit definition for MDMA_CxBNDTR register ****************/
11738 #define MDMA_CBNDTR_BNDT_Pos (0U)
11739 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
11740 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
11741 #define MDMA_CBNDTR_BRSUM_Pos (18U)
11742 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
11743 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
11744 #define MDMA_CBNDTR_BRDUM_Pos (19U)
11745 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
11746 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
11747 #define MDMA_CBNDTR_BRC_Pos (20U)
11748 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
11749 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
11750
11751 /******************** Bit definition for MDMA_CxSAR register ****************/
11752 #define MDMA_CSAR_SAR_Pos (0U)
11753 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
11754 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
11755
11756 /******************** Bit definition for MDMA_CxDAR register ****************/
11757 #define MDMA_CDAR_DAR_Pos (0U)
11758 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
11759 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
11760
11761 /******************** Bit definition for MDMA_CxBRUR ************************/
11762 #define MDMA_CBRUR_SUV_Pos (0U)
11763 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
11764 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
11765 #define MDMA_CBRUR_DUV_Pos (16U)
11766 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
11767 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
11768
11769 /******************** Bit definition for MDMA_CxLAR *************************/
11770 #define MDMA_CLAR_LAR_Pos (0U)
11771 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
11772 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
11773
11774 /******************** Bit definition for MDMA_CxTBR) ************************/
11775 #define MDMA_CTBR_TSEL_Pos (0U)
11776 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
11777 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
11778 #define MDMA_CTBR_SBUS_Pos (16U)
11779 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
11780 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
11781 #define MDMA_CTBR_DBUS_Pos (17U)
11782 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
11783 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
11784
11785 /******************** Bit definition for MDMA_CxMAR) ************************/
11786 #define MDMA_CMAR_MAR_Pos (0U)
11787 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
11788 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
11789
11790 /******************** Bit definition for MDMA_CxMDR) ************************/
11791 #define MDMA_CMDR_MDR_Pos (0U)
11792 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
11793 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
11794
11795 /******************************************************************************/
11796 /* */
11797 /* Operational Amplifier (OPAMP) */
11798 /* */
11799 /******************************************************************************/
11800 /********************* Bit definition for OPAMPx_CSR register ***************/
11801 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
11802 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
11803 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
11804 #define OPAMP_CSR_FORCEVP_Pos (1U)
11805 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
11806 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
11807
11808 #define OPAMP_CSR_VPSEL_Pos (2U)
11809 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
11810 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
11811 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
11812 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
11813
11814 #define OPAMP_CSR_VMSEL_Pos (5U)
11815 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
11816 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
11817 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
11818 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
11819
11820 #define OPAMP_CSR_OPAHSM_Pos (8U)
11821 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
11822 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
11823 #define OPAMP_CSR_CALON_Pos (11U)
11824 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
11825 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
11826
11827 #define OPAMP_CSR_CALSEL_Pos (12U)
11828 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
11829 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
11830 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
11831 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
11832
11833 #define OPAMP_CSR_PGGAIN_Pos (14U)
11834 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
11835 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
11836 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
11837 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
11838 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
11839 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
11840
11841 #define OPAMP_CSR_USERTRIM_Pos (18U)
11842 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
11843 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
11844 #define OPAMP_CSR_TSTREF_Pos (29U)
11845 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
11846 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
11847 #define OPAMP_CSR_CALOUT_Pos (30U)
11848 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
11849 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
11850
11851 /********************* Bit definition for OPAMP1_CSR register ***************/
11852 #define OPAMP1_CSR_OPAEN_Pos (0U)
11853 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
11854 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
11855 #define OPAMP1_CSR_FORCEVP_Pos (1U)
11856 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
11857 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
11858
11859 #define OPAMP1_CSR_VPSEL_Pos (2U)
11860 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
11861 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
11862 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
11863 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
11864
11865 #define OPAMP1_CSR_VMSEL_Pos (5U)
11866 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
11867 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
11868 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
11869 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
11870
11871 #define OPAMP1_CSR_OPAHSM_Pos (8U)
11872 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
11873 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
11874 #define OPAMP1_CSR_CALON_Pos (11U)
11875 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
11876 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
11877
11878 #define OPAMP1_CSR_CALSEL_Pos (12U)
11879 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
11880 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
11881 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
11882 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
11883
11884 #define OPAMP1_CSR_PGGAIN_Pos (14U)
11885 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
11886 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
11887 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
11888 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
11889 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
11890 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
11891
11892 #define OPAMP1_CSR_USERTRIM_Pos (18U)
11893 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
11894 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
11895 #define OPAMP1_CSR_TSTREF_Pos (29U)
11896 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
11897 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
11898 #define OPAMP1_CSR_CALOUT_Pos (30U)
11899 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
11900 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
11901
11902 /********************* Bit definition for OPAMP2_CSR register ***************/
11903 #define OPAMP2_CSR_OPAEN_Pos (0U)
11904 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
11905 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
11906 #define OPAMP2_CSR_FORCEVP_Pos (1U)
11907 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
11908 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
11909
11910 #define OPAMP2_CSR_VPSEL_Pos (2U)
11911 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
11912 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
11913 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
11914 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
11915
11916 #define OPAMP2_CSR_VMSEL_Pos (5U)
11917 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
11918 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
11919 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
11920 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
11921
11922 #define OPAMP2_CSR_OPAHSM_Pos (8U)
11923 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
11924 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
11925 #define OPAMP2_CSR_CALON_Pos (11U)
11926 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
11927 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
11928
11929 #define OPAMP2_CSR_CALSEL_Pos (12U)
11930 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
11931 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
11932 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
11933 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
11934
11935 #define OPAMP2_CSR_PGGAIN_Pos (14U)
11936 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
11937 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
11938 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
11939 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
11940 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
11941 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
11942
11943 #define OPAMP2_CSR_USERTRIM_Pos (18U)
11944 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
11945 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
11946 #define OPAMP2_CSR_TSTREF_Pos (29U)
11947 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
11948 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
11949 #define OPAMP2_CSR_CALOUT_Pos (30U)
11950 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
11951 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
11952
11953 /******************* Bit definition for OPAMP_OTR register ******************/
11954 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
11955 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
11956 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11957 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
11958 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
11959 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
11960
11961 /******************* Bit definition for OPAMP1_OTR register ******************/
11962 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
11963 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
11964 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11965 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
11966 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
11967 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
11968
11969 /******************* Bit definition for OPAMP2_OTR register ******************/
11970 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
11971 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
11972 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11973 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
11974 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
11975 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
11976
11977 /******************* Bit definition for OPAMP_HSOTR register ****************/
11978 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
11979 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
11980 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11981 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
11982 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
11983 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
11984
11985 /******************* Bit definition for OPAMP1_HSOTR register ****************/
11986 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
11987 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
11988 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11989 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
11990 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
11991 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
11992
11993 /******************* Bit definition for OPAMP2_HSOTR register ****************/
11994 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
11995 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
11996 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
11997 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
11998 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
11999 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12000
12001 /******************************************************************************/
12002 /* */
12003 /* Parallel Synchronous Slave Interface (PSSI ) */
12004 /* */
12005 /******************************************************************************/
12006
12007 /******************** Bit definition for PSSI_CR register *******************/
12008 #define PSSI_CR_OUTEN_Pos (31U)
12009 #define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */
12010 #define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */
12011 #define PSSI_CR_DMAEN_Pos (30U)
12012 #define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */
12013 #define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */
12014 #define PSSI_CR_DERDYCFG_Pos (18U)
12015 #define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */
12016 #define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */
12017 #define PSSI_CR_ENABLE_Pos (14U)
12018 #define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */
12019 #define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */
12020 #define PSSI_CR_EDM_Pos (10U)
12021 #define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */
12022 #define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */
12023 #define PSSI_CR_RDYPOL_Pos (8U)
12024 #define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000C00 */
12025 #define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */
12026 #define PSSI_CR_DEPOL_Pos (6U)
12027 #define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000C00 */
12028 #define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */
12029 #define PSSI_CR_CKPOL_Pos (5U)
12030 #define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000C00 */
12031 #define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */
12032 /******************** Bit definition for PSSI_SR register *******************/
12033 #define PSSI_SR_RTT1B_Pos (3U)
12034 #define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */
12035 #define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */
12036 #define PSSI_SR_RTT4B_Pos (2U)
12037 #define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */
12038 #define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */
12039 /******************** Bit definition for PSSI_RIS register *******************/
12040 #define PSSI_RIS_OVR_RIS_Pos (1U)
12041 #define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
12042 #define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */
12043 /******************** Bit definition for PSSI_IER register *******************/
12044 #define PSSI_IER_OVR_IE_Pos (1U)
12045 #define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */
12046 #define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */
12047 /******************** Bit definition for PSSI_MIS register *******************/
12048 #define PSSI_MIS_OVR_MIS_Pos (1U)
12049 #define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
12050 #define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */
12051 /******************** Bit definition for PSSI_ICR register *******************/
12052 #define PSSI_ICR_OVR_ISC_Pos (1U)
12053 #define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
12054 #define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */
12055 /******************** Bit definition for PSSI_DR register *******************/
12056 #define PSSI_DR_DR_Pos (0U)
12057 #define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */
12058 #define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */
12059
12060 /******************************************************************************/
12061 /* */
12062 /* Power Control */
12063 /* */
12064 /******************************************************************************/
12065 /************************* NUMBER OF POWER DOMAINS **************************/
12066 #define POWER_DOMAINS_NUMBER 2U /*!< 2 Domains */
12067
12068 /******************** Bit definition for PWR_CR1 register *******************/
12069 #define PWR_CR1_SRDRAMSO_Pos (27U)
12070 #define PWR_CR1_SRDRAMSO_Msk (0x1UL << PWR_CR1_SRDRAMSO_Pos) /*!< 0x08000000 */
12071 #define PWR_CR1_SRDRAMSO PWR_CR1_SRDRAMSO_Msk /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */
12072 #define PWR_CR1_HSITFSO_Pos (26U)
12073 #define PWR_CR1_HSITFSO_Msk (0x1UL << PWR_CR1_HSITFSO_Pos) /*!< 0x04000000 */
12074 #define PWR_CR1_HSITFSO PWR_CR1_HSITFSO_Msk /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */
12075 #define PWR_CR1_GFXSO_Pos (25U)
12076 #define PWR_CR1_GFXSO_Msk (0x1UL << PWR_CR1_GFXSO_Pos) /*!< 0x02000000 */
12077 #define PWR_CR1_GFXSO PWR_CR1_GFXSO_Msk /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */
12078 #define PWR_CR1_ITCMSO_Pos (24U)
12079 #define PWR_CR1_ITCMSO_Msk (0x1UL << PWR_CR1_ITCMSO_Pos) /*!< 0x01000000 */
12080 #define PWR_CR1_ITCMSO PWR_CR1_ITCMSO_Msk /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */
12081 #define PWR_CR1_AHBRAM2SO_Pos (23U)
12082 #define PWR_CR1_AHBRAM2SO_Msk (0x1UL << PWR_CR1_AHBRAM2SO_Pos) /*!< 0x00800000 */
12083 #define PWR_CR1_AHBRAM2SO PWR_CR1_AHBRAM2SO_Msk /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */
12084 #define PWR_CR1_AHBRAM1SO_Pos (22U)
12085 #define PWR_CR1_AHBRAM1SO_Msk (0x1UL << PWR_CR1_AHBRAM1SO_Pos) /*!< 0x00400000 */
12086 #define PWR_CR1_AHBRAM1SO PWR_CR1_AHBRAM1SO_Msk /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */
12087 #define PWR_CR1_AXIRAM3SO_Pos (21U)
12088 #define PWR_CR1_AXIRAM3SO_Msk (0x1UL << PWR_CR1_AXIRAM3SO_Pos) /*!< 0x00200000 */
12089 #define PWR_CR1_AXIRAM3SO PWR_CR1_AXIRAM3SO_Msk /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */
12090 #define PWR_CR1_AXIRAM2SO_Pos (20U)
12091 #define PWR_CR1_AXIRAM2SO_Msk (0x1UL << PWR_CR1_AXIRAM2SO_Pos) /*!< 0x00100000 */
12092 #define PWR_CR1_AXIRAM2SO PWR_CR1_AXIRAM2SO_Msk /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */
12093 #define PWR_CR1_AXIRAM1SO_Pos (19U)
12094 #define PWR_CR1_AXIRAM1SO_Msk (0x1UL << PWR_CR1_AXIRAM1SO_Pos) /*!< 0x00080000 */
12095 #define PWR_CR1_AXIRAM1SO PWR_CR1_AXIRAM1SO_Msk /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */
12096 #define PWR_CR1_ALS_Pos (17U)
12097 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
12098 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
12099 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
12100 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
12101 #define PWR_CR1_AVDEN_Pos (16U)
12102 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
12103 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
12104 #define PWR_CR1_SVOS_Pos (14U)
12105 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
12106 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
12107 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
12108 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
12109 #define PWR_CR1_AVD_READY_Pos (13U)
12110 #define PWR_CR1_AVD_READY_Msk (0x1UL << PWR_CR1_AVD_READY_Pos) /*!< 0x00002000 */
12111 #define PWR_CR1_AVD_READY PWR_CR1_AVD_READY_Msk /*!< Analog Voltage Ready. */
12112 #define PWR_CR1_BOOSTE_Pos (12U)
12113 #define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00001000 */
12114 #define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control */
12115 #define PWR_CR1_FLPS_Pos (9U)
12116 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
12117 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
12118 #define PWR_CR1_DBP_Pos (8U)
12119 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
12120 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
12121 #define PWR_CR1_PLS_Pos (5U)
12122 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
12123 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
12124 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
12125 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
12126 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
12127 #define PWR_CR1_PVDEN_Pos (4U)
12128 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
12129 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
12130 #define PWR_CR1_LPDS_Pos (0U)
12131 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
12132 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
12133
12134 /*!< PVD level configuration */
12135 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
12136 #define PWR_CR1_PLS_LEV1_Pos (5U)
12137 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
12138 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
12139 #define PWR_CR1_PLS_LEV2_Pos (6U)
12140 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
12141 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
12142 #define PWR_CR1_PLS_LEV3_Pos (5U)
12143 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
12144 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
12145 #define PWR_CR1_PLS_LEV4_Pos (7U)
12146 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
12147 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
12148 #define PWR_CR1_PLS_LEV5_Pos (5U)
12149 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
12150 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
12151 #define PWR_CR1_PLS_LEV6_Pos (6U)
12152 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
12153 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
12154 #define PWR_CR1_PLS_LEV7_Pos (5U)
12155 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
12156 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
12157
12158 /*!< AVD level configuration */
12159 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
12160 #define PWR_CR1_ALS_LEV1_Pos (17U)
12161 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
12162 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
12163 #define PWR_CR1_ALS_LEV2_Pos (18U)
12164 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
12165 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
12166 #define PWR_CR1_ALS_LEV3_Pos (17U)
12167 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
12168 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
12169
12170 /******************** Bit definition for PWR_CSR1 register ******************/
12171 #define PWR_CSR1_MMCVDO_Pos (17U)
12172 #define PWR_CSR1_MMCVDO_Msk (0x1UL << PWR_CSR1_MMCVDO_Pos) /*!< 0x00020000 */
12173 #define PWR_CSR1_MMCVDO PWR_CSR1_MMCVDO_Msk /*!< voltage detector output on VDDMMC */
12174 #define PWR_CSR1_AVDO_Pos (16U)
12175 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
12176 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
12177 #define PWR_CSR1_ACTVOS_Pos (14U)
12178 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
12179 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
12180 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
12181 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
12182 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
12183 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
12184 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
12185 #define PWR_CSR1_PVDO_Pos (4U)
12186 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
12187 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
12188
12189 /******************** Bit definition for PWR_CR2 register *******************/
12190 #define PWR_CR2_TEMPH_Pos (23U)
12191 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
12192 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
12193 #define PWR_CR2_TEMPL_Pos (22U)
12194 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
12195 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
12196 #define PWR_CR2_VBATH_Pos (21U)
12197 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
12198 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
12199 #define PWR_CR2_VBATL_Pos (20U)
12200 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
12201 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
12202 #define PWR_CR2_BRRDY_Pos (16U)
12203 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
12204 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
12205 #define PWR_CR2_MONEN_Pos (4U)
12206 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
12207 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
12208 #define PWR_CR2_BREN_Pos (0U)
12209 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
12210 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
12211
12212 /******************** Bit definition for PWR_CR3 register *******************/
12213 #define PWR_CR3_USB33RDY_Pos (26U)
12214 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
12215 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
12216 #define PWR_CR3_USBREGEN_Pos (25U)
12217 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
12218 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
12219 #define PWR_CR3_USB33DEN_Pos (24U)
12220 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
12221 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
12222 #define PWR_CR3_SMPSEXTRDY_Pos (16U)
12223 #define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */
12224 #define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */
12225 #define PWR_CR3_VBRS_Pos (9U)
12226 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
12227 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
12228 #define PWR_CR3_VBE_Pos (8U)
12229 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
12230 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
12231 #define PWR_CR3_SMPSLEVEL_Pos (4U)
12232 #define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */
12233 #define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */
12234 #define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */
12235 #define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */
12236 #define PWR_CR3_SMPSEXTHP_Pos (3U)
12237 #define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */
12238 #define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */
12239 #define PWR_CR3_SMPSEN_Pos (2U)
12240 #define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */
12241 #define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */
12242 #define PWR_CR3_LDOEN_Pos (1U)
12243 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
12244 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
12245 #define PWR_CR3_BYPASS_Pos (0U)
12246 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
12247 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
12248
12249 /******************** Bit definition for PWR_CPUCR register *****************/
12250 #define PWR_CPUCR_RUN_SRD_Pos (11U)
12251 #define PWR_CPUCR_RUN_SRD_Msk (0x1UL << PWR_CPUCR_RUN_SRD_Pos) /*!< 0x00000800 */
12252 #define PWR_CPUCR_RUN_SRD PWR_CPUCR_RUN_SRD_Msk /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */
12253 #define PWR_CPUCR_CSSF_Pos (9U)
12254 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
12255 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
12256 #define PWR_CPUCR_SBF_Pos (6U)
12257 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
12258 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
12259 #define PWR_CPUCR_STOPF_Pos (5U)
12260 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
12261 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
12262 #define PWR_CPUCR_PDDS_SRD_Pos (2U)
12263 #define PWR_CPUCR_PDDS_SRD_Msk (0x1UL << PWR_CPUCR_PDDS_SRD_Pos) /*!< 0x00000004 */
12264 #define PWR_CPUCR_PDDS_SRD PWR_CPUCR_PDDS_SRD_Msk /*!< System SRD domain Power Down Deepsleep */
12265 #define PWR_CPUCR_RETDS_CD_Pos (0U)
12266 #define PWR_CPUCR_RETDS_CD_Msk (0x1UL << PWR_CPUCR_RETDS_CD_Pos) /*!< 0x00000001 */
12267 #define PWR_CPUCR_RETDS_CD PWR_CPUCR_RETDS_CD_Msk /*!< CD domain Power Down Deepsleep selection */
12268 /******************** Bit definition for PWR_SRDCR register *****************/
12269 #define PWR_SRDCR_VOS_Pos (14U)
12270 #define PWR_SRDCR_VOS_Msk (0x3UL << PWR_SRDCR_VOS_Pos) /*!< 0x0000C000 */
12271 #define PWR_SRDCR_VOS PWR_SRDCR_VOS_Msk /*!< Voltage Scaling selection according performance */
12272 #define PWR_SRDCR_VOS_0 (0x1UL << PWR_SRDCR_VOS_Pos) /*!< 0x00004000 */
12273 #define PWR_SRDCR_VOS_1 (0x2UL << PWR_SRDCR_VOS_Pos) /*!< 0x00008000 */
12274 #define PWR_SRDCR_VOSRDY_Pos (13U)
12275 #define PWR_SRDCR_VOSRDY_Msk (0x1UL << PWR_SRDCR_VOSRDY_Pos) /*!< 0x00002000 */
12276 #define PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
12277 /****************** Bit definition for PWR_WKUPCR register ******************/
12278 #define PWR_WKUPCR_WKUPC6_Pos (5U)
12279 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
12280 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
12281 #define PWR_WKUPCR_WKUPC5_Pos (4U)
12282 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
12283 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
12284 #define PWR_WKUPCR_WKUPC4_Pos (3U)
12285 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
12286 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
12287 #define PWR_WKUPCR_WKUPC3_Pos (2U)
12288 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
12289 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
12290 #define PWR_WKUPCR_WKUPC2_Pos (1U)
12291 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
12292 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
12293 #define PWR_WKUPCR_WKUPC1_Pos (0U)
12294 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
12295 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
12296
12297 /******************** Bit definition for PWR_WKUPFR register ****************/
12298 #define PWR_WKUPFR_WKUPF6_Pos (5U)
12299 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
12300 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
12301 #define PWR_WKUPFR_WKUPF5_Pos (4U)
12302 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
12303 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
12304 #define PWR_WKUPFR_WKUPF4_Pos (3U)
12305 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
12306 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
12307 #define PWR_WKUPFR_WKUPF3_Pos (2U)
12308 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
12309 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
12310 #define PWR_WKUPFR_WKUPF2_Pos (1U)
12311 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
12312 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
12313 #define PWR_WKUPFR_WKUPF1_Pos (0U)
12314 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
12315 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
12316
12317 /****************** Bit definition for PWR_WKUPEPR register *****************/
12318 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
12319 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
12320 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
12321 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
12322 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
12323 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
12324 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
12325 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
12326 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
12327 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
12328 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
12329 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
12330 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
12331 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
12332 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
12333 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
12334 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
12335 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
12336 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
12337 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
12338 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
12339 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
12340 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
12341 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
12342 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
12343 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
12344 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
12345 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
12346 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
12347 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
12348 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
12349 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
12350 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
12351 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
12352 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
12353 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
12354 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
12355 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
12356 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
12357 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
12358 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
12359 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
12360 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
12361 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
12362 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
12363 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
12364 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
12365 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
12366 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
12367 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
12368 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
12369 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
12370 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
12371 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
12372 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
12373 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
12374 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
12375 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
12376 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
12377 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
12378 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
12379 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
12380 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
12381 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
12382 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
12383 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
12384 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
12385 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
12386 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
12387
12388 /******************************************************************************/
12389 /* */
12390 /* Reset and Clock Control */
12391 /* */
12392 /******************************************************************************/
12393 /******************************* RCC VERSION ********************************/
12394 #define RCC_VER_2_0
12395
12396 /******************** Bit definition for RCC_CR register ********************/
12397 #define RCC_CR_HSION_Pos (0U)
12398 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
12399 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
12400 #define RCC_CR_HSIKERON_Pos (1U)
12401 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
12402 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
12403 #define RCC_CR_HSIRDY_Pos (2U)
12404 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
12405 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
12406 #define RCC_CR_HSIDIV_Pos (3U)
12407 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
12408 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
12409 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
12410 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
12411 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
12412 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
12413
12414 #define RCC_CR_HSIDIVF_Pos (5U)
12415 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
12416 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
12417 #define RCC_CR_CSION_Pos (7U)
12418 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
12419 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
12420 #define RCC_CR_CSIRDY_Pos (8U)
12421 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
12422 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
12423 #define RCC_CR_CSIKERON_Pos (9U)
12424 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
12425 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
12426 #define RCC_CR_HSI48ON_Pos (12U)
12427 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
12428 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
12429 #define RCC_CR_HSI48RDY_Pos (13U)
12430 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
12431 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
12432
12433 #define RCC_CR_CPUCKRDY_Pos (14U)
12434 #define RCC_CR_CPUCKRDY_Msk (0x1UL << RCC_CR_CPUCKRDY_Pos) /*!< 0x00004000 */
12435 #define RCC_CR_CPUCKRDY RCC_CR_CPUCKRDY_Msk /*!< CPU domain clocks ready flag */
12436 #define RCC_CR_CDCKRDY_Pos (15U)
12437 #define RCC_CR_CDCKRDY_Msk (0x1UL << RCC_CR_CDCKRDY_Pos) /*!< 0x00008000 */
12438 #define RCC_CR_CDCKRDY RCC_CR_CDCKRDY_Msk /*!< CD domain clocks ready flag */
12439
12440 #define RCC_CR_HSEON_Pos (16U)
12441 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
12442 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
12443 #define RCC_CR_HSERDY_Pos (17U)
12444 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
12445 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
12446 #define RCC_CR_HSEBYP_Pos (18U)
12447 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
12448 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
12449 #define RCC_CR_CSSHSEON_Pos (19U)
12450 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
12451 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
12452
12453 #define RCC_CR_HSEEXT_Pos (20U)
12454 #define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00080000 */
12455 #define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< HSE Clock security System enable */
12456
12457 #define RCC_CR_PLL1ON_Pos (24U)
12458 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
12459 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
12460 #define RCC_CR_PLL1RDY_Pos (25U)
12461 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
12462 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
12463 #define RCC_CR_PLL2ON_Pos (26U)
12464 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
12465 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
12466 #define RCC_CR_PLL2RDY_Pos (27U)
12467 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
12468 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
12469 #define RCC_CR_PLL3ON_Pos (28U)
12470 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
12471 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
12472 #define RCC_CR_PLL3RDY_Pos (29U)
12473 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
12474 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
12475
12476 /*Legacy */
12477 #define RCC_CR_PLLON_Pos (24U)
12478 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
12479 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
12480 #define RCC_CR_PLLRDY_Pos (25U)
12481 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
12482 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
12483
12484 /******************** Bit definition for RCC_HSICFGR register ***************/
12485 /*!< HSICAL configuration */
12486 #define RCC_HSICFGR_HSICAL_Pos (0U)
12487 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
12488 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
12489 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
12490 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
12491 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
12492 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
12493 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
12494 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
12495 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
12496 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
12497 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
12498 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
12499 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
12500 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
12501
12502 /*!< HSITRIM configuration */
12503 #define RCC_HSICFGR_HSITRIM_Pos (24U)
12504 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
12505 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
12506 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
12507 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
12508 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
12509 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
12510 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
12511 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
12512 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
12513
12514
12515 /******************** Bit definition for RCC_CRRCR register *****************/
12516
12517 /*!< HSI48CAL configuration */
12518 #define RCC_CRRCR_HSI48CAL_Pos (0U)
12519 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
12520 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
12521 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
12522 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
12523 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
12524 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
12525 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
12526 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
12527 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
12528 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
12529 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
12530 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
12531
12532
12533 /******************** Bit definition for RCC_CSICFGR register *****************/
12534 /*!< CSICAL configuration */
12535 #define RCC_CSICFGR_CSICAL_Pos (0U)
12536 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
12537 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
12538 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
12539 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
12540 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
12541 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
12542 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
12543 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
12544 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
12545 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
12546
12547 /*!< CSITRIM configuration */
12548 #define RCC_CSICFGR_CSITRIM_Pos (24U)
12549 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
12550 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
12551 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
12552 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
12553 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
12554 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
12555 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
12556 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
12557
12558 /******************** Bit definition for RCC_CFGR register ******************/
12559 /*!< SW configuration */
12560 #define RCC_CFGR_SW_Pos (0U)
12561 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
12562 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
12563 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
12564 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
12565 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
12566
12567 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
12568 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
12569 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
12570 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
12571
12572 /*!< SWS configuration */
12573 #define RCC_CFGR_SWS_Pos (3U)
12574 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
12575 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
12576 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
12577 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
12578 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
12579
12580 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
12581 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
12582 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
12583 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
12584
12585 #define RCC_CFGR_STOPWUCK_Pos (6U)
12586 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
12587 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
12588
12589 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
12590 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
12591 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
12592
12593 /*!< RTCPRE configuration */
12594 #define RCC_CFGR_RTCPRE_Pos (8U)
12595 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
12596 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
12597 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
12598 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
12599 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
12600 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
12601 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
12602 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
12603
12604
12605 /*!< TIMPRE configuration */
12606 #define RCC_CFGR_TIMPRE_Pos (15U)
12607 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
12608 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
12609
12610 /*!< MCO1 configuration */
12611 #define RCC_CFGR_MCO1_Pos (22U)
12612 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
12613 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
12614 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
12615 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
12616 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
12617
12618 #define RCC_CFGR_MCO1PRE_Pos (18U)
12619 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
12620 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
12621 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
12622 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
12623 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
12624 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
12625
12626 #define RCC_CFGR_MCO2PRE_Pos (25U)
12627 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
12628 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
12629 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
12630 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
12631 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
12632 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
12633
12634 #define RCC_CFGR_MCO2_Pos (29U)
12635 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
12636 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
12637 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
12638 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
12639 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
12640
12641 /******************** Bit definition for RCC_D1CFGR register ******************/
12642 /*!< D1HPRE configuration */
12643 #define RCC_CDCFGR1_HPRE_Pos (0U)
12644 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */
12645 #define RCC_CDCFGR1_HPRE RCC_CDCFGR1_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
12646 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */
12647 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */
12648 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
12649 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
12650
12651 #define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
12652 #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
12653 #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
12654 #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
12655 #define RCC_CDCFGR1_HPRE_DIV4_Pos (0U)
12656 #define RCC_CDCFGR1_HPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos) /*!< 0x00000009 */
12657 #define RCC_CDCFGR1_HPRE_DIV4 RCC_CDCFGR1_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
12658 #define RCC_CDCFGR1_HPRE_DIV8_Pos (1U)
12659 #define RCC_CDCFGR1_HPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos) /*!< 0x0000000A */
12660 #define RCC_CDCFGR1_HPRE_DIV8 RCC_CDCFGR1_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
12661 #define RCC_CDCFGR1_HPRE_DIV16_Pos (0U)
12662 #define RCC_CDCFGR1_HPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos) /*!< 0x0000000B */
12663 #define RCC_CDCFGR1_HPRE_DIV16 RCC_CDCFGR1_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
12664 #define RCC_CDCFGR1_HPRE_DIV64_Pos (2U)
12665 #define RCC_CDCFGR1_HPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos) /*!< 0x0000000C */
12666 #define RCC_CDCFGR1_HPRE_DIV64 RCC_CDCFGR1_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
12667 #define RCC_CDCFGR1_HPRE_DIV128_Pos (0U)
12668 #define RCC_CDCFGR1_HPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */
12669 #define RCC_CDCFGR1_HPRE_DIV128 RCC_CDCFGR1_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
12670 #define RCC_CDCFGR1_HPRE_DIV256_Pos (1U)
12671 #define RCC_CDCFGR1_HPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */
12672 #define RCC_CDCFGR1_HPRE_DIV256 RCC_CDCFGR1_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
12673 #define RCC_CDCFGR1_HPRE_DIV512_Pos (0U)
12674 #define RCC_CDCFGR1_HPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */
12675 #define RCC_CDCFGR1_HPRE_DIV512 RCC_CDCFGR1_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
12676
12677 /*!< D1PPRE configuration */
12678 #define RCC_CDCFGR1_CDPPRE_Pos (4U)
12679 #define RCC_CDCFGR1_CDPPRE_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000070 */
12680 #define RCC_CDCFGR1_CDPPRE RCC_CDCFGR1_CDPPRE_Msk /*!< CDPRE[2:0] bits (APB3 prescaler) */
12681 #define RCC_CDCFGR1_CDPPRE_0 (0x1UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000010 */
12682 #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
12683 #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
12684
12685 #define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
12686 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
12687 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
12688 #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
12689 #define RCC_CDCFGR1_CDPPRE_DIV4_Pos (4U)
12690 #define RCC_CDCFGR1_CDPPRE_DIV4_Msk (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */
12691 #define RCC_CDCFGR1_CDPPRE_DIV4 RCC_CDCFGR1_CDPPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
12692 #define RCC_CDCFGR1_CDPPRE_DIV8_Pos (5U)
12693 #define RCC_CDCFGR1_CDPPRE_DIV8_Msk (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */
12694 #define RCC_CDCFGR1_CDPPRE_DIV8 RCC_CDCFGR1_CDPPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
12695 #define RCC_CDCFGR1_CDPPRE_DIV16_Pos (4U)
12696 #define RCC_CDCFGR1_CDPPRE_DIV16_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */
12697 #define RCC_CDCFGR1_CDPPRE_DIV16 RCC_CDCFGR1_CDPPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
12698
12699 #define RCC_CDCFGR1_CDCPRE_Pos (8U)
12700 #define RCC_CDCFGR1_CDCPRE_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000F00 */
12701 #define RCC_CDCFGR1_CDCPRE RCC_CDCFGR1_CDCPRE_Msk /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */
12702 #define RCC_CDCFGR1_CDCPRE_0 (0x1UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000100 */
12703 #define RCC_CDCFGR1_CDCPRE_1 (0x2UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000200 */
12704 #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
12705 #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
12706
12707 #define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
12708 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
12709 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
12710 #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
12711 #define RCC_CDCFGR1_CDCPRE_DIV4_Pos (8U)
12712 #define RCC_CDCFGR1_CDCPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos) /*!< 0x00000900 */
12713 #define RCC_CDCFGR1_CDCPRE_DIV4 RCC_CDCFGR1_CDCPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
12714 #define RCC_CDCFGR1_CDCPRE_DIV8_Pos (9U)
12715 #define RCC_CDCFGR1_CDCPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos) /*!< 0x00000A00 */
12716 #define RCC_CDCFGR1_CDCPRE_DIV8 RCC_CDCFGR1_CDCPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
12717 #define RCC_CDCFGR1_CDCPRE_DIV16_Pos (8U)
12718 #define RCC_CDCFGR1_CDCPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */
12719 #define RCC_CDCFGR1_CDCPRE_DIV16 RCC_CDCFGR1_CDCPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
12720 #define RCC_CDCFGR1_CDCPRE_DIV64_Pos (10U)
12721 #define RCC_CDCFGR1_CDCPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */
12722 #define RCC_CDCFGR1_CDCPRE_DIV64 RCC_CDCFGR1_CDCPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
12723 #define RCC_CDCFGR1_CDCPRE_DIV128_Pos (8U)
12724 #define RCC_CDCFGR1_CDCPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */
12725 #define RCC_CDCFGR1_CDCPRE_DIV128 RCC_CDCFGR1_CDCPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
12726 #define RCC_CDCFGR1_CDCPRE_DIV256_Pos (9U)
12727 #define RCC_CDCFGR1_CDCPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */
12728 #define RCC_CDCFGR1_CDCPRE_DIV256 RCC_CDCFGR1_CDCPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
12729 #define RCC_CDCFGR1_CDCPRE_DIV512_Pos (8U)
12730 #define RCC_CDCFGR1_CDCPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */
12731 #define RCC_CDCFGR1_CDCPRE_DIV512 RCC_CDCFGR1_CDCPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
12732
12733 /******************** Bit definition for RCC_CDCFGR2 register ******************/
12734 /*!< CDPPRE1 configuration */
12735 #define RCC_CDCFGR2_CDPPRE1_Pos (4U)
12736 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */
12737 #define RCC_CDCFGR2_CDPPRE1 RCC_CDCFGR2_CDPPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
12738 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */
12739 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
12740 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
12741
12742 #define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
12743 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
12744 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
12745 #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
12746 #define RCC_CDCFGR2_CDPPRE1_DIV4_Pos (4U)
12747 #define RCC_CDCFGR2_CDPPRE1_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */
12748 #define RCC_CDCFGR2_CDPPRE1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
12749 #define RCC_CDCFGR2_CDPPRE1_DIV8_Pos (5U)
12750 #define RCC_CDCFGR2_CDPPRE1_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */
12751 #define RCC_CDCFGR2_CDPPRE1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
12752 #define RCC_CDCFGR2_CDPPRE1_DIV16_Pos (4U)
12753 #define RCC_CDCFGR2_CDPPRE1_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */
12754 #define RCC_CDCFGR2_CDPPRE1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
12755
12756 /*!< CDPPRE2 configuration */
12757 #define RCC_CDCFGR2_CDPPRE2_Pos (8U)
12758 #define RCC_CDCFGR2_CDPPRE2_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */
12759 #define RCC_CDCFGR2_CDPPRE2 RCC_CDCFGR2_CDPPRE2_Msk /*!< CDPPRE2[2:0] bits (APB2 prescaler) */
12760 #define RCC_CDCFGR2_CDPPRE2_0 (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */
12761 #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
12762 #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
12763
12764 #define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
12765 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
12766 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
12767 #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
12768 #define RCC_CDCFGR2_CDPPRE2_DIV4_Pos (8U)
12769 #define RCC_CDCFGR2_CDPPRE2_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */
12770 #define RCC_CDCFGR2_CDPPRE2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
12771 #define RCC_CDCFGR2_CDPPRE2_DIV8_Pos (9U)
12772 #define RCC_CDCFGR2_CDPPRE2_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */
12773 #define RCC_CDCFGR2_CDPPRE2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
12774 #define RCC_CDCFGR2_CDPPRE2_DIV16_Pos (8U)
12775 #define RCC_CDCFGR2_CDPPRE2_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */
12776 #define RCC_CDCFGR2_CDPPRE2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
12777
12778 /******************** Bit definition for RCC_SRDCFGR register ******************/
12779 /*!< SRDPPRE configuration */
12780 #define RCC_SRDCFGR_SRDPPRE_Pos (4U)
12781 #define RCC_SRDCFGR_SRDPPRE_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */
12782 #define RCC_SRDCFGR_SRDPPRE RCC_SRDCFGR_SRDPPRE_Msk /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */
12783 #define RCC_SRDCFGR_SRDPPRE_0 (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */
12784 #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
12785 #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
12786
12787 #define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
12788 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
12789 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
12790 #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
12791 #define RCC_SRDCFGR_SRDPPRE_DIV4_Pos (4U)
12792 #define RCC_SRDCFGR_SRDPPRE_DIV4_Msk (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */
12793 #define RCC_SRDCFGR_SRDPPRE_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
12794 #define RCC_SRDCFGR_SRDPPRE_DIV8_Pos (5U)
12795 #define RCC_SRDCFGR_SRDPPRE_DIV8_Msk (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */
12796 #define RCC_SRDCFGR_SRDPPRE_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
12797 #define RCC_SRDCFGR_SRDPPRE_DIV16_Pos (4U)
12798 #define RCC_SRDCFGR_SRDPPRE_DIV16_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */
12799 #define RCC_SRDCFGR_SRDPPRE_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
12800
12801 /******************** Bit definition for RCC_PLLCKSELR register *************/
12802
12803 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
12804 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
12805 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
12806
12807 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
12808 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
12809 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
12810 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
12811 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
12812 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
12813 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
12814 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
12815 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
12816 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
12817
12818 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
12819 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
12820 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
12821 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
12822 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
12823 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
12824 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
12825 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
12826 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
12827
12828 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
12829 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
12830 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
12831 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
12832 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
12833 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
12834 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
12835 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
12836 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
12837
12838 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
12839 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
12840 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
12841 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
12842 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
12843 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
12844 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
12845 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
12846 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
12847
12848 /******************** Bit definition for RCC_PLLCFGR register ***************/
12849
12850 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
12851 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
12852 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
12853 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
12854 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
12855 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
12856 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
12857 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
12858 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
12859 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
12860 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
12861 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
12862 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
12863
12864 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
12865 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
12866 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
12867 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
12868 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
12869 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
12870 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
12871 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
12872 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
12873 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
12874 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
12875 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
12876 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
12877
12878 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
12879 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
12880 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
12881 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
12882 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
12883 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
12884 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
12885 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
12886 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
12887 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
12888 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
12889 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
12890 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
12891
12892 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
12893 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
12894 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
12895 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
12896 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
12897 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
12898 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
12899 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
12900 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
12901
12902 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
12903 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
12904 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
12905 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
12906 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
12907 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
12908 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
12909 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
12910 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
12911
12912 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
12913 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
12914 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
12915 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
12916 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
12917 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
12918 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
12919 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
12920 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
12921
12922
12923 /******************** Bit definition for RCC_PLL1DIVR register ***************/
12924 #define RCC_PLL1DIVR_N1_Pos (0U)
12925 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
12926 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
12927 #define RCC_PLL1DIVR_P1_Pos (9U)
12928 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
12929 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
12930 #define RCC_PLL1DIVR_Q1_Pos (16U)
12931 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
12932 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
12933 #define RCC_PLL1DIVR_R1_Pos (24U)
12934 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
12935 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
12936
12937 /******************** Bit definition for RCC_PLL1FRACR register ***************/
12938 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
12939 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
12940 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
12941
12942 /******************** Bit definition for RCC_PLL2DIVR register ***************/
12943 #define RCC_PLL2DIVR_N2_Pos (0U)
12944 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
12945 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
12946 #define RCC_PLL2DIVR_P2_Pos (9U)
12947 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
12948 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
12949 #define RCC_PLL2DIVR_Q2_Pos (16U)
12950 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
12951 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
12952 #define RCC_PLL2DIVR_R2_Pos (24U)
12953 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
12954 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
12955
12956 /******************** Bit definition for RCC_PLL2FRACR register ***************/
12957 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
12958 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
12959 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
12960
12961 /******************** Bit definition for RCC_PLL3DIVR register ***************/
12962 #define RCC_PLL3DIVR_N3_Pos (0U)
12963 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
12964 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
12965 #define RCC_PLL3DIVR_P3_Pos (9U)
12966 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
12967 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
12968 #define RCC_PLL3DIVR_Q3_Pos (16U)
12969 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
12970 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
12971 #define RCC_PLL3DIVR_R3_Pos (24U)
12972 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
12973 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
12974
12975 /******************** Bit definition for RCC_PLL3FRACR register ***************/
12976 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
12977 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
12978 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
12979
12980 /******************** Bit definition for RCC_CDCCIPR register ***************/
12981 #define RCC_CDCCIPR_FMCSEL_Pos (0U)
12982 #define RCC_CDCCIPR_FMCSEL_Msk (0x3UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000003 */
12983 #define RCC_CDCCIPR_FMCSEL RCC_CDCCIPR_FMCSEL_Msk
12984 #define RCC_CDCCIPR_FMCSEL_0 (0x1UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000001 */
12985 #define RCC_CDCCIPR_FMCSEL_1 (0x2UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000002 */
12986 #define RCC_CDCCIPR_OCTOSPISEL_Pos (4U)
12987 #define RCC_CDCCIPR_OCTOSPISEL_Msk (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */
12988 #define RCC_CDCCIPR_OCTOSPISEL RCC_CDCCIPR_OCTOSPISEL_Msk
12989 #define RCC_CDCCIPR_OCTOSPISEL_0 (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */
12990 #define RCC_CDCCIPR_OCTOSPISEL_1 (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */
12991 #define RCC_CDCCIPR_SDMMCSEL_Pos (16U)
12992 #define RCC_CDCCIPR_SDMMCSEL_Msk (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
12993 #define RCC_CDCCIPR_SDMMCSEL RCC_CDCCIPR_SDMMCSEL_Msk
12994 #define RCC_CDCCIPR_CKPERSEL_Pos (28U)
12995 #define RCC_CDCCIPR_CKPERSEL_Msk (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
12996 #define RCC_CDCCIPR_CKPERSEL RCC_CDCCIPR_CKPERSEL_Msk
12997 #define RCC_CDCCIPR_CKPERSEL_0 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
12998 #define RCC_CDCCIPR_CKPERSEL_1 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
12999
13000 /******************** Bit definition for RCC_CDCCIP1R register ***************/
13001 #define RCC_CDCCIP1R_SAI1SEL_Pos (0U)
13002 #define RCC_CDCCIP1R_SAI1SEL_Msk (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
13003 #define RCC_CDCCIP1R_SAI1SEL RCC_CDCCIP1R_SAI1SEL_Msk
13004 #define RCC_CDCCIP1R_SAI1SEL_0 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
13005 #define RCC_CDCCIP1R_SAI1SEL_1 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
13006 #define RCC_CDCCIP1R_SAI1SEL_2 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
13007
13008 #define RCC_CDCCIP1R_SAI2ASEL_Pos (6U)
13009 #define RCC_CDCCIP1R_SAI2ASEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x000001C0 */
13010 #define RCC_CDCCIP1R_SAI2ASEL RCC_CDCCIP1R_SAI2ASEL_Msk
13011 #define RCC_CDCCIP1R_SAI2ASEL_0 (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000040 */
13012 #define RCC_CDCCIP1R_SAI2ASEL_1 (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000080 */
13013 #define RCC_CDCCIP1R_SAI2ASEL_2 (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000100 */
13014
13015 #define RCC_CDCCIP1R_SAI2BSEL_Pos (9U)
13016 #define RCC_CDCCIP1R_SAI2BSEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000E00 */
13017 #define RCC_CDCCIP1R_SAI2BSEL RCC_CDCCIP1R_SAI2BSEL_Msk
13018 #define RCC_CDCCIP1R_SAI2BSEL_0 (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000200 */
13019 #define RCC_CDCCIP1R_SAI2BSEL_1 (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000400 */
13020 #define RCC_CDCCIP1R_SAI2BSEL_2 (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000800 */
13021
13022 #define RCC_CDCCIP1R_SPI123SEL_Pos (12U)
13023 #define RCC_CDCCIP1R_SPI123SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
13024 #define RCC_CDCCIP1R_SPI123SEL RCC_CDCCIP1R_SPI123SEL_Msk
13025 #define RCC_CDCCIP1R_SPI123SEL_0 (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
13026 #define RCC_CDCCIP1R_SPI123SEL_1 (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
13027 #define RCC_CDCCIP1R_SPI123SEL_2 (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
13028
13029 #define RCC_CDCCIP1R_SPI45SEL_Pos (16U)
13030 #define RCC_CDCCIP1R_SPI45SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
13031 #define RCC_CDCCIP1R_SPI45SEL RCC_CDCCIP1R_SPI45SEL_Msk
13032 #define RCC_CDCCIP1R_SPI45SEL_0 (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
13033 #define RCC_CDCCIP1R_SPI45SEL_1 (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
13034 #define RCC_CDCCIP1R_SPI45SEL_2 (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
13035
13036 #define RCC_CDCCIP1R_SPDIFSEL_Pos (20U)
13037 #define RCC_CDCCIP1R_SPDIFSEL_Msk (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
13038 #define RCC_CDCCIP1R_SPDIFSEL RCC_CDCCIP1R_SPDIFSEL_Msk
13039 #define RCC_CDCCIP1R_SPDIFSEL_0 (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
13040 #define RCC_CDCCIP1R_SPDIFSEL_1 (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
13041
13042 #define RCC_CDCCIP1R_DFSDM1SEL_Pos (24U)
13043 #define RCC_CDCCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
13044 #define RCC_CDCCIP1R_DFSDM1SEL RCC_CDCCIP1R_DFSDM1SEL_Msk
13045
13046 #define RCC_CDCCIP1R_FDCANSEL_Pos (28U)
13047 #define RCC_CDCCIP1R_FDCANSEL_Msk (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
13048 #define RCC_CDCCIP1R_FDCANSEL RCC_CDCCIP1R_FDCANSEL_Msk
13049 #define RCC_CDCCIP1R_FDCANSEL_0 (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
13050 #define RCC_CDCCIP1R_FDCANSEL_1 (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
13051
13052 #define RCC_CDCCIP1R_SWPSEL_Pos (31U)
13053 #define RCC_CDCCIP1R_SWPSEL_Msk (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
13054 #define RCC_CDCCIP1R_SWPSEL RCC_CDCCIP1R_SWPSEL_Msk
13055
13056 /******************** Bit definition for RCC_CDCCIP2R register ***************/
13057 #define RCC_CDCCIP2R_USART234578SEL_Pos (0U)
13058 #define RCC_CDCCIP2R_USART234578SEL_Msk (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000007 */
13059 #define RCC_CDCCIP2R_USART234578SEL RCC_CDCCIP2R_USART234578SEL_Msk
13060 #define RCC_CDCCIP2R_USART234578SEL_0 (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000001 */
13061 #define RCC_CDCCIP2R_USART234578SEL_1 (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000002 */
13062 #define RCC_CDCCIP2R_USART234578SEL_2 (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000004 */
13063
13064 #define RCC_CDCCIP2R_USART16910SEL_Pos (3U)
13065 #define RCC_CDCCIP2R_USART16910SEL_Msk (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000038 */
13066 #define RCC_CDCCIP2R_USART16910SEL RCC_CDCCIP2R_USART16910SEL_Msk
13067 #define RCC_CDCCIP2R_USART16910SEL_0 (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000008 */
13068 #define RCC_CDCCIP2R_USART16910SEL_1 (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000010 */
13069 #define RCC_CDCCIP2R_USART16910SEL_2 (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000020 */
13070
13071 #define RCC_CDCCIP2R_RNGSEL_Pos (8U)
13072 #define RCC_CDCCIP2R_RNGSEL_Msk (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
13073 #define RCC_CDCCIP2R_RNGSEL RCC_CDCCIP2R_RNGSEL_Msk
13074 #define RCC_CDCCIP2R_RNGSEL_0 (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
13075 #define RCC_CDCCIP2R_RNGSEL_1 (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
13076
13077 #define RCC_CDCCIP2R_I2C123SEL_Pos (12U)
13078 #define RCC_CDCCIP2R_I2C123SEL_Msk (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
13079 #define RCC_CDCCIP2R_I2C123SEL RCC_CDCCIP2R_I2C123SEL_Msk
13080 #define RCC_CDCCIP2R_I2C123SEL_0 (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
13081 #define RCC_CDCCIP2R_I2C123SEL_1 (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
13082
13083 #define RCC_CDCCIP2R_USBSEL_Pos (20U)
13084 #define RCC_CDCCIP2R_USBSEL_Msk (0x3UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00300000 */
13085 #define RCC_CDCCIP2R_USBSEL RCC_CDCCIP2R_USBSEL_Msk
13086 #define RCC_CDCCIP2R_USBSEL_0 (0x1UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00100000 */
13087 #define RCC_CDCCIP2R_USBSEL_1 (0x2UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00200000 */
13088
13089 #define RCC_CDCCIP2R_CECSEL_Pos (22U)
13090 #define RCC_CDCCIP2R_CECSEL_Msk (0x3UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
13091 #define RCC_CDCCIP2R_CECSEL RCC_CDCCIP2R_CECSEL_Msk
13092 #define RCC_CDCCIP2R_CECSEL_0 (0x1UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00400000 */
13093 #define RCC_CDCCIP2R_CECSEL_1 (0x2UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00800000 */
13094
13095 #define RCC_CDCCIP2R_LPTIM1SEL_Pos (28U)
13096 #define RCC_CDCCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
13097 #define RCC_CDCCIP2R_LPTIM1SEL RCC_CDCCIP2R_LPTIM1SEL_Msk
13098 #define RCC_CDCCIP2R_LPTIM1SEL_0 (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
13099 #define RCC_CDCCIP2R_LPTIM1SEL_1 (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
13100 #define RCC_CDCCIP2R_LPTIM1SEL_2 (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
13101
13102 /******************** Bit definition for RCC_SRDCCIPR register ***************/
13103 #define RCC_SRDCCIPR_LPUART1SEL_Pos (0U)
13104 #define RCC_SRDCCIPR_LPUART1SEL_Msk (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
13105 #define RCC_SRDCCIPR_LPUART1SEL RCC_SRDCCIPR_LPUART1SEL_Msk
13106 #define RCC_SRDCCIPR_LPUART1SEL_0 (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
13107 #define RCC_SRDCCIPR_LPUART1SEL_1 (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
13108 #define RCC_SRDCCIPR_LPUART1SEL_2 (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
13109
13110 #define RCC_SRDCCIPR_I2C4SEL_Pos (8U)
13111 #define RCC_SRDCCIPR_I2C4SEL_Msk (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
13112 #define RCC_SRDCCIPR_I2C4SEL RCC_SRDCCIPR_I2C4SEL_Msk
13113 #define RCC_SRDCCIPR_I2C4SEL_0 (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
13114 #define RCC_SRDCCIPR_I2C4SEL_1 (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
13115
13116 #define RCC_SRDCCIPR_LPTIM2SEL_Pos (10U)
13117 #define RCC_SRDCCIPR_LPTIM2SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
13118 #define RCC_SRDCCIPR_LPTIM2SEL RCC_SRDCCIPR_LPTIM2SEL_Msk
13119 #define RCC_SRDCCIPR_LPTIM2SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
13120 #define RCC_SRDCCIPR_LPTIM2SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
13121 #define RCC_SRDCCIPR_LPTIM2SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
13122
13123 #define RCC_SRDCCIPR_LPTIM3SEL_Pos (13U)
13124 #define RCC_SRDCCIPR_LPTIM3SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x0000E000 */
13125 #define RCC_SRDCCIPR_LPTIM3SEL RCC_SRDCCIPR_LPTIM3SEL_Msk
13126 #define RCC_SRDCCIPR_LPTIM3SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00002000 */
13127 #define RCC_SRDCCIPR_LPTIM3SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00004000 */
13128 #define RCC_SRDCCIPR_LPTIM3SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00008000 */
13129
13130 #define RCC_SRDCCIPR_ADCSEL_Pos (16U)
13131 #define RCC_SRDCCIPR_ADCSEL_Msk (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00030000 */
13132 #define RCC_SRDCCIPR_ADCSEL RCC_SRDCCIPR_ADCSEL_Msk
13133 #define RCC_SRDCCIPR_ADCSEL_0 (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00010000 */
13134 #define RCC_SRDCCIPR_ADCSEL_1 (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00020000 */
13135
13136 #define RCC_SRDCCIPR_DFSDM2SEL_Pos (27U)
13137 #define RCC_SRDCCIPR_DFSDM2SEL_Msk (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos) /*!< 0x08000000 */
13138 #define RCC_SRDCCIPR_DFSDM2SEL RCC_SRDCCIPR_DFSDM2SEL_Msk
13139
13140 #define RCC_SRDCCIPR_SPI6SEL_Pos (28U)
13141 #define RCC_SRDCCIPR_SPI6SEL_Msk (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
13142 #define RCC_SRDCCIPR_SPI6SEL RCC_SRDCCIPR_SPI6SEL_Msk
13143 #define RCC_SRDCCIPR_SPI6SEL_0 (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
13144 #define RCC_SRDCCIPR_SPI6SEL_1 (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
13145 #define RCC_SRDCCIPR_SPI6SEL_2 (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
13146
13147 /******************** Bit definition for RCC_CIER register ******************/
13148 #define RCC_CIER_LSIRDYIE_Pos (0U)
13149 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
13150 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
13151 #define RCC_CIER_LSERDYIE_Pos (1U)
13152 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
13153 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
13154 #define RCC_CIER_HSIRDYIE_Pos (2U)
13155 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
13156 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
13157 #define RCC_CIER_HSERDYIE_Pos (3U)
13158 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
13159 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
13160 #define RCC_CIER_CSIRDYIE_Pos (4U)
13161 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
13162 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
13163 #define RCC_CIER_HSI48RDYIE_Pos (5U)
13164 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
13165 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
13166 #define RCC_CIER_PLL1RDYIE_Pos (6U)
13167 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
13168 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
13169 #define RCC_CIER_PLL2RDYIE_Pos (7U)
13170 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
13171 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
13172 #define RCC_CIER_PLL3RDYIE_Pos (8U)
13173 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
13174 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
13175 #define RCC_CIER_LSECSSIE_Pos (9U)
13176 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
13177 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
13178
13179 /******************** Bit definition for RCC_CIFR register ******************/
13180 #define RCC_CIFR_LSIRDYF_Pos (0U)
13181 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
13182 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
13183 #define RCC_CIFR_LSERDYF_Pos (1U)
13184 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
13185 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
13186 #define RCC_CIFR_HSIRDYF_Pos (2U)
13187 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
13188 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
13189 #define RCC_CIFR_HSERDYF_Pos (3U)
13190 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
13191 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
13192 #define RCC_CIFR_CSIRDYF_Pos (4U)
13193 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
13194 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
13195 #define RCC_CIFR_HSI48RDYF_Pos (5U)
13196 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
13197 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
13198 #define RCC_CIFR_PLLRDYF_Pos (6U)
13199 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
13200 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
13201 #define RCC_CIFR_PLL2RDYF_Pos (7U)
13202 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
13203 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
13204 #define RCC_CIFR_PLL3RDYF_Pos (8U)
13205 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
13206 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
13207 #define RCC_CIFR_LSECSSF_Pos (9U)
13208 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
13209 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
13210 #define RCC_CIFR_HSECSSF_Pos (10U)
13211 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
13212 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
13213
13214 /******************** Bit definition for RCC_CICR register ******************/
13215 #define RCC_CICR_LSIRDYC_Pos (0U)
13216 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
13217 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
13218 #define RCC_CICR_LSERDYC_Pos (1U)
13219 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
13220 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
13221 #define RCC_CICR_HSIRDYC_Pos (2U)
13222 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
13223 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
13224 #define RCC_CICR_HSERDYC_Pos (3U)
13225 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
13226 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
13227 #define RCC_CICR_CSIRDYC_Pos (4U)
13228 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
13229 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
13230 #define RCC_CICR_HSI48RDYC_Pos (5U)
13231 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
13232 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
13233 #define RCC_CICR_PLLRDYC_Pos (6U)
13234 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
13235 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
13236 #define RCC_CICR_PLL2RDYC_Pos (7U)
13237 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
13238 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
13239 #define RCC_CICR_PLL3RDYC_Pos (8U)
13240 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
13241 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
13242 #define RCC_CICR_LSECSSC_Pos (9U)
13243 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
13244 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
13245 #define RCC_CICR_HSECSSC_Pos (10U)
13246 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
13247 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
13248
13249 /******************** Bit definition for RCC_BDCR register ******************/
13250 #define RCC_BDCR_LSEON_Pos (0U)
13251 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
13252 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
13253 #define RCC_BDCR_LSERDY_Pos (1U)
13254 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
13255 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
13256 #define RCC_BDCR_LSEBYP_Pos (2U)
13257 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
13258 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
13259
13260 #define RCC_BDCR_LSEDRV_Pos (3U)
13261 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
13262 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
13263 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
13264 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
13265
13266 #define RCC_BDCR_LSECSSON_Pos (5U)
13267 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
13268 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
13269 #define RCC_BDCR_LSECSSD_Pos (6U)
13270 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
13271 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
13272 #define RCC_BDCR_LSEEXT_Pos (7U)
13273 #define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */
13274 #define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk
13275
13276 #define RCC_BDCR_RTCSEL_Pos (8U)
13277 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
13278 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
13279 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
13280 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
13281
13282 #define RCC_BDCR_RTCEN_Pos (15U)
13283 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
13284 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
13285 #define RCC_BDCR_VSWRST_Pos (16U)
13286 #define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */
13287 #define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk
13288 /* Legacy define */
13289 #define RCC_BDCR_BDRST_Pos RCC_BDCR_VSWRST_Pos
13290 #define RCC_BDCR_BDRST_Msk RCC_BDCR_VSWRST_Msk
13291 #define RCC_BDCR_BDRST RCC_BDCR_VSWRST
13292 /******************** Bit definition for RCC_CSR register *******************/
13293 #define RCC_CSR_LSION_Pos (0U)
13294 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
13295 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
13296 #define RCC_CSR_LSIRDY_Pos (1U)
13297 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
13298 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
13299
13300
13301 /******************** Bit definition for RCC_AHB3ENR register **************/
13302 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
13303 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
13304 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
13305 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
13306 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
13307 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
13308 #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
13309 #define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
13310 #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
13311 #define RCC_AHB3ENR_FMCEN_Pos (12U)
13312 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
13313 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
13314 #define RCC_AHB3ENR_OSPI1EN_Pos (14U)
13315 #define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos) /*!< 0x00004000 */
13316 #define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
13317 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
13318 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
13319 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
13320 #define RCC_AHB3ENR_OSPI2EN_Pos (19U)
13321 #define RCC_AHB3ENR_OSPI2EN_Msk (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos) /*!< 0x00040000 */
13322 #define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
13323 #define RCC_AHB3ENR_IOMNGREN_Pos (21U)
13324 #define RCC_AHB3ENR_IOMNGREN_Msk (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos) /*!< 0x00100000 */
13325 #define RCC_AHB3ENR_IOMNGREN RCC_AHB3ENR_IOMNGREN_Msk
13326 #define RCC_AHB3ENR_GFXMMUEN_Pos (24U)
13327 #define RCC_AHB3ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos) /*!< 0x00800000 */
13328 #define RCC_AHB3ENR_GFXMMUEN RCC_AHB3ENR_GFXMMUEN_Msk
13329
13330 /******************** Bit definition for RCC_AHB1ENR register ***************/
13331 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
13332 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
13333 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
13334 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
13335 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
13336 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
13337 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
13338 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
13339 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
13340 #define RCC_AHB1ENR_CRCEN_Pos (9U)
13341 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00000200 */
13342 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
13343 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
13344 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
13345 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
13346 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
13347 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
13348 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
13349
13350 /******************** Bit definition for RCC_AHB2ENR register ***************/
13351 #define RCC_AHB2ENR_DCMI_PSSIEN_Pos (0U)
13352 #define RCC_AHB2ENR_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos) /*!< 0x00000001 */
13353 #define RCC_AHB2ENR_DCMI_PSSIEN RCC_AHB2ENR_DCMI_PSSIEN_Msk
13354 #define RCC_AHB2ENR_HSEMEN_Pos (2U)
13355 #define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */
13356 #define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk
13357 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
13358 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
13359 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
13360 #define RCC_AHB2ENR_HASHEN_Pos (5U)
13361 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
13362 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
13363 #define RCC_AHB2ENR_RNGEN_Pos (6U)
13364 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
13365 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
13366 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
13367 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
13368 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
13369 #define RCC_AHB2ENR_BDMA1EN_Pos (11U)
13370 #define RCC_AHB2ENR_BDMA1EN_Msk (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos) /*!< 0x00000800 */
13371 #define RCC_AHB2ENR_BDMA1EN RCC_AHB2ENR_BDMA1EN_Msk
13372 #define RCC_AHB2ENR_AHBSRAM1EN_Pos (29U)
13373 #define RCC_AHB2ENR_AHBSRAM1EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos) /*!< 0x20000000 */
13374 #define RCC_AHB2ENR_AHBSRAM1EN RCC_AHB2ENR_AHBSRAM1EN_Msk
13375 #define RCC_AHB2ENR_AHBSRAM2EN_Pos (30U)
13376 #define RCC_AHB2ENR_AHBSRAM2EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos) /*!< 0x40000000 */
13377 #define RCC_AHB2ENR_AHBSRAM2EN RCC_AHB2ENR_AHBSRAM2EN_Msk
13378
13379 /* Legacy define */
13380 #define RCC_AHB2ENR_DCMIEN_Pos RCC_AHB2ENR_DCMI_PSSIEN_Pos
13381 #define RCC_AHB2ENR_DCMIEN_Msk RCC_AHB2ENR_DCMI_PSSIEN_Msk
13382 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMI_PSSIEN
13383
13384 /******************** Bit definition for RCC_AHB4ENR register ******************/
13385 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
13386 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
13387 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
13388 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
13389 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
13390 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
13391 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
13392 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
13393 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
13394 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
13395 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
13396 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
13397 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
13398 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
13399 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
13400 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
13401 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
13402 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
13403 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
13404 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
13405 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
13406 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
13407 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
13408 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
13409 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
13410 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
13411 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
13412 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
13413 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
13414 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
13415 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
13416 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
13417 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
13418 #define RCC_AHB4ENR_BDMA2EN_Pos (21U)
13419 #define RCC_AHB4ENR_BDMA2EN_Msk (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos) /*!< 0x00080000 */
13420 #define RCC_AHB4ENR_BDMA2EN RCC_AHB4ENR_BDMA2EN_Msk
13421 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
13422 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
13423 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
13424 #define RCC_AHB4ENR_SRDSRAMEN_Pos (29U)
13425 #define RCC_AHB4ENR_SRDSRAMEN_Msk (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos) /*!< 0x20000000 */
13426 #define RCC_AHB4ENR_SRDSRAMEN RCC_AHB4ENR_SRDSRAMEN_Msk
13427
13428 /******************** Bit definition for RCC_APB3ENR register ******************/
13429 #define RCC_APB3ENR_LTDCEN_Pos (3U)
13430 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
13431 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
13432 #define RCC_APB3ENR_WWDGEN_Pos (6U)
13433 #define RCC_APB3ENR_WWDGEN_Msk (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */
13434 #define RCC_APB3ENR_WWDGEN RCC_APB3ENR_WWDGEN_Msk
13435
13436 /* Legacy define */
13437 #define RCC_APB3ENR_WWDG1EN_Pos RCC_APB3ENR_WWDGEN_Pos
13438 #define RCC_APB3ENR_WWDG1EN_Msk RCC_APB3ENR_WWDGEN_Msk
13439 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDGEN
13440 /******************** Bit definition for RCC_APB1LENR register ******************/
13441
13442 #define RCC_APB1LENR_TIM2EN_Pos (0U)
13443 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
13444 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
13445 #define RCC_APB1LENR_TIM3EN_Pos (1U)
13446 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
13447 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
13448 #define RCC_APB1LENR_TIM4EN_Pos (2U)
13449 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
13450 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
13451 #define RCC_APB1LENR_TIM5EN_Pos (3U)
13452 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
13453 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
13454 #define RCC_APB1LENR_TIM6EN_Pos (4U)
13455 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
13456 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
13457 #define RCC_APB1LENR_TIM7EN_Pos (5U)
13458 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
13459 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
13460 #define RCC_APB1LENR_TIM12EN_Pos (6U)
13461 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
13462 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
13463 #define RCC_APB1LENR_TIM13EN_Pos (7U)
13464 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
13465 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
13466 #define RCC_APB1LENR_TIM14EN_Pos (8U)
13467 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
13468 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
13469 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
13470 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
13471 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
13472
13473
13474 #define RCC_APB1LENR_SPI2EN_Pos (14U)
13475 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
13476 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
13477 #define RCC_APB1LENR_SPI3EN_Pos (15U)
13478 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
13479 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
13480 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
13481 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
13482 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
13483 #define RCC_APB1LENR_USART2EN_Pos (17U)
13484 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
13485 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
13486 #define RCC_APB1LENR_USART3EN_Pos (18U)
13487 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
13488 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
13489 #define RCC_APB1LENR_UART4EN_Pos (19U)
13490 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
13491 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
13492 #define RCC_APB1LENR_UART5EN_Pos (20U)
13493 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
13494 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
13495 #define RCC_APB1LENR_I2C1EN_Pos (21U)
13496 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
13497 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
13498 #define RCC_APB1LENR_I2C2EN_Pos (22U)
13499 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
13500 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
13501 #define RCC_APB1LENR_I2C3EN_Pos (23U)
13502 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
13503 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
13504 #define RCC_APB1LENR_CECEN_Pos (27U)
13505 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
13506 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
13507 #define RCC_APB1LENR_DAC12EN_Pos (29U)
13508 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
13509 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
13510 #define RCC_APB1LENR_UART7EN_Pos (30U)
13511 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
13512 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
13513 #define RCC_APB1LENR_UART8EN_Pos (31U)
13514 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
13515 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
13516
13517 /* Legacy define */
13518 #define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
13519 #define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
13520 #define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
13521 /******************** Bit definition for RCC_APB1HENR register ******************/
13522 #define RCC_APB1HENR_CRSEN_Pos (1U)
13523 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
13524 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
13525 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
13526 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
13527 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
13528 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
13529 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
13530 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
13531 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
13532 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
13533 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
13534 #define RCC_APB1HENR_FDCANEN_Pos (8U)
13535 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
13536 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
13537
13538 /******************** Bit definition for RCC_APB2ENR register ******************/
13539 #define RCC_APB2ENR_TIM1EN_Pos (0U)
13540 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
13541 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
13542 #define RCC_APB2ENR_TIM8EN_Pos (1U)
13543 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
13544 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
13545 #define RCC_APB2ENR_USART1EN_Pos (4U)
13546 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
13547 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
13548 #define RCC_APB2ENR_USART6EN_Pos (5U)
13549 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
13550 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
13551 #define RCC_APB2ENR_UART9EN_Pos (6U)
13552 #define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
13553 #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
13554 #define RCC_APB2ENR_USART10EN_Pos (7U)
13555 #define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */
13556 #define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk
13557 #define RCC_APB2ENR_SPI1EN_Pos (12U)
13558 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
13559 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
13560 #define RCC_APB2ENR_SPI4EN_Pos (13U)
13561 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
13562 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
13563 #define RCC_APB2ENR_TIM15EN_Pos (16U)
13564 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
13565 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
13566 #define RCC_APB2ENR_TIM16EN_Pos (17U)
13567 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
13568 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
13569 #define RCC_APB2ENR_TIM17EN_Pos (18U)
13570 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
13571 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
13572 #define RCC_APB2ENR_SPI5EN_Pos (20U)
13573 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
13574 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
13575 #define RCC_APB2ENR_SAI1EN_Pos (22U)
13576 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
13577 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
13578 #define RCC_APB2ENR_SAI2EN_Pos (23U)
13579 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
13580 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
13581 #define RCC_APB2ENR_DFSDM1EN_Pos (30U)
13582 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */
13583 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
13584
13585 /******************** Bit definition for RCC_APB4ENR register ******************/
13586 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
13587 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
13588 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
13589 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
13590 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
13591 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
13592 #define RCC_APB4ENR_SPI6EN_Pos (5U)
13593 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
13594 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
13595 #define RCC_APB4ENR_I2C4EN_Pos (7U)
13596 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
13597 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
13598 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
13599 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
13600 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
13601 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
13602 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
13603 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
13604 #define RCC_APB4ENR_DAC2EN_Pos (13U)
13605 #define RCC_APB4ENR_DAC2EN_Msk (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */
13606 #define RCC_APB4ENR_DAC2EN RCC_APB4ENR_DAC2EN_Msk
13607 #define RCC_APB4ENR_COMP12EN_Pos (14U)
13608 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
13609 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
13610 #define RCC_APB4ENR_VREFEN_Pos (15U)
13611 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
13612 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
13613 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
13614 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
13615 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
13616
13617 #define RCC_APB4ENR_DTSEN_Pos (26U)
13618 #define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */
13619 #define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk
13620 #define RCC_APB4ENR_DFSDM2EN_Pos (27U)
13621 #define RCC_APB4ENR_DFSDM2EN_Msk (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */
13622 #define RCC_APB4ENR_DFSDM2EN RCC_APB4ENR_DFSDM2EN_Msk
13623
13624 /******************** Bit definition for RCC_AHB3RSTR register ***************/
13625 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
13626 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
13627 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
13628 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
13629 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
13630 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
13631 #define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
13632 #define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
13633 #define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
13634 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
13635 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
13636 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
13637 #define RCC_AHB3RSTR_OSPI1RST_Pos (14U)
13638 #define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos) /*!< 0x00004000 */
13639 #define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
13640 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
13641 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
13642 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
13643 #define RCC_AHB3RSTR_OSPI2RST_Pos (19U)
13644 #define RCC_AHB3RSTR_OSPI2RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos) /*!< 0x00008000 */
13645 #define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
13646 #define RCC_AHB3RSTR_IOMNGRRST_Pos (21U)
13647 #define RCC_AHB3RSTR_IOMNGRRST_Msk (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos) /*!< 0x00020000 */
13648 #define RCC_AHB3RSTR_IOMNGRRST RCC_AHB3RSTR_IOMNGRRST_Msk
13649 #define RCC_AHB3RSTR_GFXMMURST_Pos (24U)
13650 #define RCC_AHB3RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos) /*!< 0x00100000 */
13651 #define RCC_AHB3RSTR_GFXMMURST RCC_AHB3RSTR_GFXMMURST_Msk
13652
13653
13654 /******************** Bit definition for RCC_AHB1RSTR register ***************/
13655 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
13656 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
13657 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
13658 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
13659 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
13660 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
13661 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
13662 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
13663 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
13664 #define RCC_AHB1RSTR_CRCRST_Pos (9U)
13665 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00000200 */
13666 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
13667 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
13668 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
13669 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
13670
13671 /******************** Bit definition for RCC_AHB2RSTR register ***************/
13672 #define RCC_AHB2RSTR_DCMI_PSSIRST_Pos (0U)
13673 #define RCC_AHB2RSTR_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos) /*!< 0x00000001 */
13674 #define RCC_AHB2RSTR_DCMI_PSSIRST RCC_AHB2RSTR_DCMI_PSSIRST_Msk
13675 #define RCC_AHB2RSTR_HSEMRST_Pos (2U)
13676 #define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */
13677 #define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk
13678 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
13679 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
13680 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
13681 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
13682 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
13683 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
13684 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
13685 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
13686 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
13687 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
13688 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
13689 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
13690 #define RCC_AHB2RSTR_BDMA1RST_Pos (11U)
13691 #define RCC_AHB2RSTR_BDMA1RST_Msk (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos) /*!< 0x00000200 */
13692 #define RCC_AHB2RSTR_BDMA1RST RCC_AHB2RSTR_BDMA1RST_Msk
13693
13694 /* Legacy define */
13695 #define RCC_AHB2RSTR_DCMIRST_Pos RCC_AHB2RSTR_DCMI_PSSIRST_Pos
13696 #define RCC_AHB2RSTR_DCMIRST_Msk RCC_AHB2RSTR_DCMI_PSSIRST_Msk
13697 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMI_PSSIRST
13698 /******************** Bit definition for RCC_AHB4RSTR register ******************/
13699 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
13700 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
13701 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
13702 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
13703 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
13704 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
13705 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
13706 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
13707 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
13708 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
13709 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
13710 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
13711 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
13712 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
13713 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
13714 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
13715 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
13716 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
13717 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
13718 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
13719 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
13720 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
13721 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
13722 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
13723 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
13724 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
13725 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
13726 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
13727 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
13728 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
13729 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
13730 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
13731 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
13732 #define RCC_AHB4RSTR_BDMA2RST_Pos (21U)
13733 #define RCC_AHB4RSTR_BDMA2RST_Msk (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos) /*!< 0x00200000 */
13734 #define RCC_AHB4RSTR_BDMA2RST RCC_AHB4RSTR_BDMA2RST_Msk
13735
13736
13737 /******************** Bit definition for RCC_APB3RSTR register ******************/
13738 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
13739 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
13740 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
13741
13742 /******************** Bit definition for RCC_APB1LRSTR register ******************/
13743
13744 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
13745 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
13746 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
13747 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
13748 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
13749 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
13750 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
13751 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
13752 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
13753 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
13754 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
13755 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
13756 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
13757 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
13758 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
13759 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
13760 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
13761 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
13762 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
13763 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
13764 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
13765 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
13766 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
13767 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
13768 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
13769 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
13770 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
13771 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
13772 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
13773 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
13774 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
13775 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
13776 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
13777 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
13778 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
13779 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
13780 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
13781 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
13782 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
13783 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
13784 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
13785 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
13786 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
13787 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
13788 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
13789 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
13790 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
13791 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
13792 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
13793 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
13794 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
13795 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
13796 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
13797 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
13798 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
13799 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
13800 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
13801 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
13802 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
13803 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
13804 #define RCC_APB1LRSTR_CECRST_Pos (27U)
13805 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
13806 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
13807 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
13808 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
13809 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
13810 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
13811 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
13812 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
13813 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
13814 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
13815 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
13816
13817 /* Legacy define */
13818 #define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
13819 #define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
13820 #define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
13821 /******************** Bit definition for RCC_APB1HRSTR register ******************/
13822 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
13823 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
13824 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
13825 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
13826 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
13827 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
13828 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
13829 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
13830 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
13831 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
13832 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
13833 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
13834 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
13835 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
13836 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
13837
13838 /******************** Bit definition for RCC_APB2RSTR register ******************/
13839 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
13840 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
13841 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
13842 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
13843 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
13844 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
13845 #define RCC_APB2RSTR_USART1RST_Pos (4U)
13846 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
13847 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
13848 #define RCC_APB2RSTR_USART6RST_Pos (5U)
13849 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
13850 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
13851 #define RCC_APB2RSTR_UART9RST_Pos (6U)
13852 #define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
13853 #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
13854 #define RCC_APB2RSTR_USART10RST_Pos (7U)
13855 #define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */
13856 #define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk
13857 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
13858 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
13859 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
13860 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
13861 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
13862 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
13863 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
13864 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
13865 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
13866 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
13867 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
13868 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
13869 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
13870 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
13871 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
13872 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
13873 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
13874 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
13875 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
13876 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
13877 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
13878 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
13879 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
13880 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
13881 #define RCC_APB2RSTR_DFSDM1RST_Pos (30U)
13882 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
13883 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
13884
13885 /******************** Bit definition for RCC_APB4RSTR register ******************/
13886 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
13887 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
13888 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
13889 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
13890 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
13891 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
13892 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
13893 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
13894 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
13895 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
13896 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
13897 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
13898 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
13899 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
13900 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
13901 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
13902 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
13903 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
13904 #define RCC_APB4RSTR_DAC2RST_Pos (13U)
13905 #define RCC_APB4RSTR_DAC2RST_Msk (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */
13906 #define RCC_APB4RSTR_DAC2RST RCC_APB4RSTR_DAC2RST_Msk
13907 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
13908 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
13909 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
13910 #define RCC_APB4RSTR_VREFRST_Pos (15U)
13911 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
13912 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
13913
13914 #define RCC_APB4RSTR_DTSRST_Pos (26U)
13915 #define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */
13916 #define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk
13917 #define RCC_APB4RSTR_DFSDM2RST_Pos (27U)
13918 #define RCC_APB4RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */
13919 #define RCC_APB4RSTR_DFSDM2RST RCC_APB4RSTR_DFSDM2RST_Msk
13920
13921
13922 /******************** Bit definition for RCC_SRDAMR register ********************/
13923 #define RCC_SRDAMR_BDMA2AMEN_Pos (0U)
13924 #define RCC_SRDAMR_BDMA2AMEN_Msk (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */
13925 #define RCC_SRDAMR_BDMA2AMEN RCC_SRDAMR_BDMA2AMEN_Msk
13926 #define RCC_SRDAMR_GPIOAMEN_Pos (1U)
13927 #define RCC_SRDAMR_GPIOAMEN_Msk (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */
13928 #define RCC_SRDAMR_GPIOAMEN RCC_SRDAMR_GPIOAMEN_Msk
13929 #define RCC_SRDAMR_LPUART1AMEN_Pos (3U)
13930 #define RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
13931 #define RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk
13932 #define RCC_SRDAMR_SPI6AMEN_Pos (5U)
13933 #define RCC_SRDAMR_SPI6AMEN_Msk (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */
13934 #define RCC_SRDAMR_SPI6AMEN RCC_SRDAMR_SPI6AMEN_Msk
13935 #define RCC_SRDAMR_I2C4AMEN_Pos (7U)
13936 #define RCC_SRDAMR_I2C4AMEN_Msk (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */
13937 #define RCC_SRDAMR_I2C4AMEN RCC_SRDAMR_I2C4AMEN_Msk
13938 #define RCC_SRDAMR_LPTIM2AMEN_Pos (9U)
13939 #define RCC_SRDAMR_LPTIM2AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
13940 #define RCC_SRDAMR_LPTIM2AMEN RCC_SRDAMR_LPTIM2AMEN_Msk
13941 #define RCC_SRDAMR_LPTIM3AMEN_Pos (10U)
13942 #define RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
13943 #define RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk
13944 #define RCC_SRDAMR_DAC2AMEN_Pos (13U)
13945 #define RCC_SRDAMR_DAC2AMEN_Msk (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */
13946 #define RCC_SRDAMR_DAC2AMEN RCC_SRDAMR_DAC2AMEN_Msk
13947 #define RCC_SRDAMR_COMP12AMEN_Pos (14U)
13948 #define RCC_SRDAMR_COMP12AMEN_Msk (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */
13949 #define RCC_SRDAMR_COMP12AMEN RCC_SRDAMR_COMP12AMEN_Msk
13950 #define RCC_SRDAMR_VREFAMEN_Pos (15U)
13951 #define RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */
13952 #define RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk
13953 #define RCC_SRDAMR_RTCAMEN_Pos (16U)
13954 #define RCC_SRDAMR_RTCAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */
13955 #define RCC_SRDAMR_RTCAMEN RCC_SRDAMR_RTCAMEN_Msk
13956 #define RCC_SRDAMR_DTSAMEN_Pos (26U)
13957 #define RCC_SRDAMR_DTSAMEN_Msk (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */
13958 #define RCC_SRDAMR_DTSAMEN RCC_SRDAMR_DTSAMEN_Msk
13959 #define RCC_SRDAMR_DFSDM2AMEN_Pos (27U)
13960 #define RCC_SRDAMR_DFSDM2AMEN_Msk (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */
13961 #define RCC_SRDAMR_DFSDM2AMEN RCC_SRDAMR_DFSDM2AMEN_Msk
13962 #define RCC_SRDAMR_BKPRAMAMEN_Pos (28U)
13963 #define RCC_SRDAMR_BKPRAMAMEN_Msk (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
13964 #define RCC_SRDAMR_BKPRAMAMEN RCC_SRDAMR_BKPRAMAMEN_Msk
13965 #define RCC_SRDAMR_SRDSRAMAMEN_Pos (29U)
13966 #define RCC_SRDAMR_SRDSRAMAMEN_Msk (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */
13967 #define RCC_SRDAMR_SRDSRAMAMEN RCC_SRDAMR_SRDSRAMAMEN_Msk
13968 /******************** Bit definition for RCC_CKGAENR register ********************/
13969 #define RCC_CKGAENR_AXICKG_Pos (0U)
13970 #define RCC_CKGAENR_AXICKG_Msk (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */
13971 #define RCC_CKGAENR_AXICKG RCC_CKGAENR_AXICKG_Msk
13972 #define RCC_CKGAENR_AHBCKG_Pos (1U)
13973 #define RCC_CKGAENR_AHBCKG_Msk (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */
13974 #define RCC_CKGAENR_AHBCKG RCC_CKGAENR_AHBCKG_Msk
13975 #define RCC_CKGAENR_CPUCKG_Pos (2U)
13976 #define RCC_CKGAENR_CPUCKG_Msk (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */
13977 #define RCC_CKGAENR_CPUCKG RCC_CKGAENR_CPUCKG_Msk
13978 #define RCC_CKGAENR_SDMMCCKG_Pos (3U)
13979 #define RCC_CKGAENR_SDMMCCKG_Msk (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */
13980 #define RCC_CKGAENR_SDMMCCKG RCC_CKGAENR_SDMMCCKG_Msk
13981 #define RCC_CKGAENR_MDMACKG_Pos (4U)
13982 #define RCC_CKGAENR_MDMACKG_Msk (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */
13983 #define RCC_CKGAENR_MDMACKG RCC_CKGAENR_MDMACKG_Msk
13984 #define RCC_CKGAENR_DMA2DCKG_Pos (5U)
13985 #define RCC_CKGAENR_DMA2DCKG_Msk (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */
13986 #define RCC_CKGAENR_DMA2DCKG RCC_CKGAENR_DMA2DCKG_Msk
13987 #define RCC_CKGAENR_LTDCCKG_Pos (6U)
13988 #define RCC_CKGAENR_LTDCCKG_Msk (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */
13989 #define RCC_CKGAENR_LTDCCKG RCC_CKGAENR_LTDCCKG_Msk
13990 #define RCC_CKGAENR_GFXMMUMCKG_Pos (7U)
13991 #define RCC_CKGAENR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */
13992 #define RCC_CKGAENR_GFXMMUMCKG RCC_CKGAENR_GFXMMUMCKG_Msk
13993 #define RCC_CKGAENR_AHB12CKG_Pos (8U)
13994 #define RCC_CKGAENR_AHB12CKG_Msk (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */
13995 #define RCC_CKGAENR_AHB12CKG RCC_CKGAENR_AHB12CKG_Msk
13996 #define RCC_CKGAENR_AHB34CKG_Pos (9U)
13997 #define RCC_CKGAENR_AHB34CKG_Msk (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */
13998 #define RCC_CKGAENR_AHB34CKG RCC_CKGAENR_AHB34CKG_Msk
13999 #define RCC_CKGAENR_FLIFTCKG_Pos (10U)
14000 #define RCC_CKGAENR_FLIFTCKG_Msk (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */
14001 #define RCC_CKGAENR_FLIFTCKG RCC_CKGAENR_FLIFTCKG_Msk
14002 #define RCC_CKGAENR_OCTOSPI2CKG_Pos (11U)
14003 #define RCC_CKGAENR_OCTOSPI2CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */
14004 #define RCC_CKGAENR_OCTOSPI2CKG RCC_CKGAENR_OCTOSPI2CKG_Msk
14005 #define RCC_CKGAENR_FMCCKG_Pos (12U)
14006 #define RCC_CKGAENR_FMCCKG_Msk (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */
14007 #define RCC_CKGAENR_FMCCKG RCC_CKGAENR_FMCCKG_Msk
14008 #define RCC_CKGAENR_OCTOSPI1CKG_Pos (13U)
14009 #define RCC_CKGAENR_OCTOSPI1CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */
14010 #define RCC_CKGAENR_OCTOSPI1CKG RCC_CKGAENR_OCTOSPI1CKG_Msk
14011 #define RCC_CKGAENR_AXIRAM1CKG_Pos (14U)
14012 #define RCC_CKGAENR_AXIRAM1CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */
14013 #define RCC_CKGAENR_AXIRAM1CKG RCC_CKGAENR_AXIRAM1CKG_Msk
14014 #define RCC_CKGAENR_AXIRAM2CKG_Pos (15U)
14015 #define RCC_CKGAENR_AXIRAM2CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */
14016 #define RCC_CKGAENR_AXIRAM2CKG RCC_CKGAENR_AXIRAM2CKG_Msk
14017 #define RCC_CKGAENR_AXIRAM3CKG_Pos (16U)
14018 #define RCC_CKGAENR_AXIRAM3CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */
14019 #define RCC_CKGAENR_AXIRAM3CKG RCC_CKGAENR_AXIRAM3CKG_Msk
14020 #define RCC_CKGAENR_GFXMMUSCKG_Pos (17U)
14021 #define RCC_CKGAENR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */
14022 #define RCC_CKGAENR_GFXMMUSCKG RCC_CKGAENR_GFXMMUSCKG_Msk
14023 #define RCC_CKGAENR_ECCRAMCKG_Pos (29U)
14024 #define RCC_CKGAENR_ECCRAMCKG_Msk (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */
14025 #define RCC_CKGAENR_ECCRAMCKG RCC_CKGAENR_ECCRAMCKG_Msk
14026 #define RCC_CKGAENR_EXTICKG_Pos (30U)
14027 #define RCC_CKGAENR_EXTICKG_Msk (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */
14028 #define RCC_CKGAENR_EXTICKG RCC_CKGAENR_EXTICKG_Msk
14029 #define RCC_CKGAENR_JTAGCKG_Pos (31U)
14030 #define RCC_CKGAENR_JTAGCKG_Msk (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */
14031 #define RCC_CKGAENR_JTAGCKG RCC_CKGAENR_JTAGCKG_Msk
14032 /******************** Bit definition for RCC_AHB3LPENR register **************/
14033 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
14034 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
14035 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
14036 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
14037 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
14038 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
14039 #define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
14040 #define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
14041 #define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
14042 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
14043 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
14044 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
14045 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
14046 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
14047 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14048 #define RCC_AHB3LPENR_OSPI1LPEN_Pos (14U)
14049 #define RCC_AHB3LPENR_OSPI1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos) /*!< 0x00004000 */
14050 #define RCC_AHB3LPENR_OSPI1LPEN RCC_AHB3LPENR_OSPI1LPEN_Msk
14051 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
14052 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
14053 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
14054 #define RCC_AHB3LPENR_OSPI2LPEN_Pos (19U)
14055 #define RCC_AHB3LPENR_OSPI2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos) /*!< 0x00080000 */
14056 #define RCC_AHB3LPENR_OSPI2LPEN RCC_AHB3LPENR_OSPI2LPEN_Msk
14057 #define RCC_AHB3LPENR_IOMNGRLPEN_Pos (21U)
14058 #define RCC_AHB3LPENR_IOMNGRLPEN_Msk (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos) /*!< 0x00200000 */
14059 #define RCC_AHB3LPENR_IOMNGRLPEN RCC_AHB3LPENR_IOMNGRLPEN_Msk
14060 #define RCC_AHB3LPENR_GFXMMULPEN_Pos (24U)
14061 #define RCC_AHB3LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos) /*!< 0x01000000 */
14062 #define RCC_AHB3LPENR_GFXMMULPEN RCC_AHB3LPENR_GFXMMULPEN_Msk
14063 #define RCC_AHB3LPENR_AXISRAM2LPEN_Pos (26U)
14064 #define RCC_AHB3LPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos) /*!< 0x02000000 */
14065 #define RCC_AHB3LPENR_AXISRAM2LPEN RCC_AHB3LPENR_AXISRAM2LPEN_Msk
14066 #define RCC_AHB3LPENR_AXISRAM3LPEN_Pos (27U)
14067 #define RCC_AHB3LPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos) /*!< 0x04000000 */
14068 #define RCC_AHB3LPENR_AXISRAM3LPEN RCC_AHB3LPENR_AXISRAM3LPEN_Msk
14069 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
14070 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
14071 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
14072 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
14073 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
14074 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
14075 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
14076 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
14077 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
14078 #define RCC_AHB3LPENR_AXISRAM1LPEN_Pos (31U)
14079 #define RCC_AHB3LPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos) /*!< 0x80000000 */
14080 #define RCC_AHB3LPENR_AXISRAM1LPEN RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14081
14082
14083 /* Legacy define */
14084 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos RCC_AHB3LPENR_AXISRAM1LPEN_Pos
14085 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14086 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAM1LPEN
14087 /******************** Bit definition for RCC_AHB1LPENR register ***************/
14088 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
14089 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
14090 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14091 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
14092 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
14093 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14094 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
14095 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
14096 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
14097 #define RCC_AHB1LPENR_CRCLPEN_Pos (9U)
14098 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */
14099 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14100 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
14101 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
14102 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
14103 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
14104 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
14105 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
14106
14107 /******************** Bit definition for RCC_AHB2LPENR register ***************/
14108 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
14109 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */
14110 #define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14111 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14112 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
14113 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14114 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14115 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
14116 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14117 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14118 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14119 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14120 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
14121 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
14122 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
14123 #define RCC_AHB2LPENR_BDMA1LPEN_Pos (11U)
14124 #define RCC_AHB2LPENR_BDMA1LPEN_Msk (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos) /*!< 0x00000800 */
14125 #define RCC_AHB2LPENR_BDMA1LPEN RCC_AHB2LPENR_BDMA1LPEN_Msk
14126 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos (29U)
14127 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */
14128 #define RCC_AHB2LPENR_AHBSRAM1LPEN RCC_AHB2LPENR_AHBSRAM1LPEN_Msk
14129 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos (30U)
14130 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */
14131 #define RCC_AHB2LPENR_AHBSRAM2LPEN RCC_AHB2LPENR_AHBSRAM2LPEN_Msk
14132
14133 /* Legacy define */
14134 #define RCC_AHB2LPENR_DFSDMDMALPEN_Pos RCC_AHB2LPENR_BDMA1LPEN_Pos
14135 #define RCC_AHB2LPENR_DFSDMDMALPEN_Msk RCC_AHB2LPENR_BDMA1LPEN_Msk
14136 #define RCC_AHB2LPENR_DFSDMDMALPEN RCC_AHB2LPENR_BDMA1LPEN
14137 #define RCC_AHB2LPENR_DCMILPEN_Pos RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
14138 #define RCC_AHB2LPENR_DCMILPEN_Msk RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14139 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMI_PSSILPEN
14140
14141 /******************** Bit definition for RCC_AHB4LPENR register ******************/
14142 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
14143 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14144 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
14145 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
14146 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14147 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
14148 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
14149 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14150 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
14151 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
14152 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14153 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
14154 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
14155 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14156 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
14157 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
14158 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14159 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
14160 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
14161 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14162 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
14163 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
14164 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14165 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
14166 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
14167 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14168 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
14169 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
14170 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14171 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
14172 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
14173 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14174 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
14175 #define RCC_AHB4LPENR_BDMA2LPEN_Pos (21U)
14176 #define RCC_AHB4LPENR_BDMA2LPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */
14177 #define RCC_AHB4LPENR_BDMA2LPEN RCC_AHB4LPENR_BDMA2LPEN_Msk
14178 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
14179 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
14180 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
14181 #define RCC_AHB4LPENR_SRDSRAMLPEN_Pos (29U)
14182 #define RCC_AHB4LPENR_SRDSRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */
14183 #define RCC_AHB4LPENR_SRDSRAMLPEN RCC_AHB4LPENR_SRDSRAMLPEN_Msk
14184
14185 /******************** Bit definition for RCC_APB3LPENR register ******************/
14186 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
14187 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
14188 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
14189 #define RCC_APB3LPENR_WWDGLPEN_Pos (6U)
14190 #define RCC_APB3LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos) /*!< 0x00000040 */
14191 #define RCC_APB3LPENR_WWDGLPEN RCC_APB3LPENR_WWDGLPEN_Msk
14192
14193 /* Legacy define */
14194 #define RCC_APB3LPENR_WWDG1LPEN_Pos RCC_APB3LPENR_WWDGLPEN_Pos
14195 #define RCC_APB3LPENR_WWDG1LPEN_Msk RCC_APB3LPENR_WWDGLPEN_Msk
14196 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDGLPEN
14197 /******************** Bit definition for RCC_APB1LLPENR register ******************/
14198
14199 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
14200 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14201 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
14202 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
14203 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14204 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
14205 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
14206 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14207 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
14208 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
14209 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14210 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
14211 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
14212 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14213 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
14214 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
14215 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14216 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
14217 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
14218 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14219 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
14220 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
14221 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14222 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
14223 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
14224 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14225 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
14226 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
14227 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
14228 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
14229
14230
14231 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
14232 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14233 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
14234 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
14235 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14236 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
14237 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
14238 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
14239 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
14240 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
14241 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14242 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
14243 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
14244 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14245 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
14246 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
14247 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14248 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
14249 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
14250 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14251 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
14252 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
14253 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14254 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
14255 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
14256 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14257 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
14258 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
14259 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14260 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
14261 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
14262 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
14263 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
14264 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
14265 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
14266 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
14267 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
14268 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14269 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
14270 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
14271 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14272 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
14273
14274 /* Legacy define */
14275 #define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
14276 #define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
14277 #define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
14278 /******************** Bit definition for RCC_APB1HLPENR register ******************/
14279 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
14280 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
14281 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
14282 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
14283 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
14284 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
14285 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
14286 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
14287 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
14288 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
14289 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
14290 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
14291 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
14292 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
14293 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
14294
14295 /******************** Bit definition for RCC_APB2LPENR register ******************/
14296 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14297 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14298 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14299 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14300 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14301 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14302 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14303 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14304 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14305 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14306 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14307 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14308 #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
14309 #define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
14310 #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
14311 #define RCC_APB2LPENR_USART10LPEN_Pos (7U)
14312 #define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */
14313 #define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk
14314 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14315 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14316 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14317 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14318 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14319 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14320 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
14321 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
14322 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
14323 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
14324 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
14325 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
14326 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
14327 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
14328 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
14329 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14330 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14331 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14332 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14333 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14334 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14335 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
14336 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
14337 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
14338 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (30U)
14339 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */
14340 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
14341
14342 /******************** Bit definition for RCC_APB4LPENR register ******************/
14343 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
14344 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
14345 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
14346 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
14347 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
14348 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
14349 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
14350 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
14351 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
14352 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
14353 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
14354 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
14355 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
14356 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
14357 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
14358 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
14359 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
14360 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
14361 #define RCC_APB4LPENR_DAC2LPEN_Pos (13U)
14362 #define RCC_APB4LPENR_DAC2LPEN_Msk (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */
14363 #define RCC_APB4LPENR_DAC2LPEN RCC_APB4LPENR_DAC2LPEN_Msk
14364 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
14365 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
14366 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
14367 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
14368 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
14369 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
14370 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
14371 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
14372 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
14373
14374 #define RCC_APB4LPENR_DTSLPEN_Pos (26U)
14375 #define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */
14376 #define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk
14377 #define RCC_APB4LPENR_DFSDM2LPEN_Pos (27U)
14378 #define RCC_APB4LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */
14379 #define RCC_APB4LPENR_DFSDM2LPEN RCC_APB4LPENR_DFSDM2LPEN_Msk
14380
14381 /******************** Bit definition for RCC_RSR register *******************/
14382 #define RCC_RSR_RMVF_Pos (16U)
14383 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
14384 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
14385 #define RCC_RSR_CDRSTF_Pos (19U)
14386 #define RCC_RSR_CDRSTF_Msk (0x1UL << RCC_RSR_CDRSTF_Pos) /*!< 0x00080000 */
14387 #define RCC_RSR_CDRSTF RCC_RSR_CDRSTF_Msk
14388 #define RCC_RSR_BORRSTF_Pos (21U)
14389 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
14390 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
14391 #define RCC_RSR_PINRSTF_Pos (22U)
14392 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
14393 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
14394 #define RCC_RSR_PORRSTF_Pos (23U)
14395 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
14396 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
14397 #define RCC_RSR_SFTRSTF_Pos (24U)
14398 #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
14399 #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
14400 #define RCC_RSR_IWDGRSTF_Pos (26U)
14401 #define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */
14402 #define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk
14403 #define RCC_RSR_WWDGRSTF_Pos (28U)
14404 #define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */
14405 #define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk
14406
14407 #define RCC_RSR_LPWRRSTF_Pos (30U)
14408 #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
14409 #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
14410
14411
14412 /* Legacy define */
14413 #define RCC_RSR_IWDG1RSTF_Pos RCC_RSR_IWDGRSTF_Pos
14414 #define RCC_RSR_IWDG1RSTF_Msk RCC_RSR_IWDGRSTF_Msk
14415 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDGRSTF
14416 #define RCC_RSR_WWDG1RSTF_Pos RCC_RSR_WWDGRSTF_Pos
14417 #define RCC_RSR_WWDG1RSTF_Msk RCC_RSR_WWDGRSTF_Msk
14418 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDGRSTF
14419 /******************************************************************************/
14420 /* */
14421 /* RNG */
14422 /* */
14423 /******************************************************************************/
14424 /*************************** RNG VER **************************************/
14425 #define RNG_VER_3_1
14426 /******************** Bits definition for RNG_CR register *******************/
14427 #define RNG_CR_RNGEN_Pos (2U)
14428 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
14429 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14430 #define RNG_CR_IE_Pos (3U)
14431 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
14432 #define RNG_CR_IE RNG_CR_IE_Msk
14433 #define RNG_CR_CED_Pos (5U)
14434 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
14435 #define RNG_CR_CED RNG_CR_CED_Msk
14436 #define RNG_CR_RNG_CONFIG3_Pos (8U)
14437 #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
14438 #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
14439 #define RNG_CR_NISTC_Pos (12U)
14440 #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
14441 #define RNG_CR_NISTC RNG_CR_NISTC_Msk
14442 #define RNG_CR_RNG_CONFIG2_Pos (13U)
14443 #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
14444 #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
14445 #define RNG_CR_CLKDIV_Pos (16U)
14446 #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
14447 #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
14448 #define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
14449 #define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
14450 #define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
14451 #define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
14452 #define RNG_CR_RNG_CONFIG1_Pos (20U)
14453 #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
14454 #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
14455 #define RNG_CR_CONDRST_Pos (30U)
14456 #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
14457 #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
14458 #define RNG_CR_CONFIGLOCK_Pos (31U)
14459 #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
14460 #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
14461
14462 /******************** Bits definition for RNG_SR register *******************/
14463 #define RNG_SR_DRDY_Pos (0U)
14464 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
14465 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
14466 #define RNG_SR_CECS_Pos (1U)
14467 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
14468 #define RNG_SR_CECS RNG_SR_CECS_Msk
14469 #define RNG_SR_SECS_Pos (2U)
14470 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
14471 #define RNG_SR_SECS RNG_SR_SECS_Msk
14472 #define RNG_SR_CEIS_Pos (5U)
14473 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
14474 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
14475 #define RNG_SR_SEIS_Pos (6U)
14476 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
14477 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
14478
14479 /******************************************************************************/
14480 /* */
14481 /* Real-Time Clock (RTC) */
14482 /* */
14483 /******************************************************************************/
14484 /******************** Bits definition for RTC_TR register *******************/
14485 #define RTC_TR_PM_Pos (22U)
14486 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
14487 #define RTC_TR_PM RTC_TR_PM_Msk
14488 #define RTC_TR_HT_Pos (20U)
14489 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
14490 #define RTC_TR_HT RTC_TR_HT_Msk
14491 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
14492 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
14493 #define RTC_TR_HU_Pos (16U)
14494 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
14495 #define RTC_TR_HU RTC_TR_HU_Msk
14496 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
14497 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
14498 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
14499 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
14500 #define RTC_TR_MNT_Pos (12U)
14501 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
14502 #define RTC_TR_MNT RTC_TR_MNT_Msk
14503 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
14504 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
14505 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
14506 #define RTC_TR_MNU_Pos (8U)
14507 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
14508 #define RTC_TR_MNU RTC_TR_MNU_Msk
14509 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
14510 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
14511 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
14512 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
14513 #define RTC_TR_ST_Pos (4U)
14514 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
14515 #define RTC_TR_ST RTC_TR_ST_Msk
14516 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
14517 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
14518 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
14519 #define RTC_TR_SU_Pos (0U)
14520 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
14521 #define RTC_TR_SU RTC_TR_SU_Msk
14522 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
14523 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
14524 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
14525 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
14526
14527 /******************** Bits definition for RTC_DR register *******************/
14528 #define RTC_DR_YT_Pos (20U)
14529 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
14530 #define RTC_DR_YT RTC_DR_YT_Msk
14531 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
14532 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
14533 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
14534 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
14535 #define RTC_DR_YU_Pos (16U)
14536 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
14537 #define RTC_DR_YU RTC_DR_YU_Msk
14538 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
14539 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
14540 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
14541 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
14542 #define RTC_DR_WDU_Pos (13U)
14543 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
14544 #define RTC_DR_WDU RTC_DR_WDU_Msk
14545 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
14546 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
14547 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
14548 #define RTC_DR_MT_Pos (12U)
14549 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
14550 #define RTC_DR_MT RTC_DR_MT_Msk
14551 #define RTC_DR_MU_Pos (8U)
14552 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
14553 #define RTC_DR_MU RTC_DR_MU_Msk
14554 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
14555 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
14556 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
14557 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
14558 #define RTC_DR_DT_Pos (4U)
14559 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
14560 #define RTC_DR_DT RTC_DR_DT_Msk
14561 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
14562 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
14563 #define RTC_DR_DU_Pos (0U)
14564 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
14565 #define RTC_DR_DU RTC_DR_DU_Msk
14566 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
14567 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
14568 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
14569 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
14570
14571 /******************** Bits definition for RTC_CR register *******************/
14572 #define RTC_CR_OUT2EN_Pos (31U)
14573 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
14574 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
14575 #define RTC_CR_TAMPALRM_TYPE_Pos (30U)
14576 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
14577 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
14578 #define RTC_CR_TAMPALRM_PU_Pos (29U)
14579 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
14580 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
14581 #define RTC_CR_TAMPOE_Pos (26U)
14582 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
14583 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
14584 #define RTC_CR_TAMPTS_Pos (25U)
14585 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
14586 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
14587 #define RTC_CR_ITSE_Pos (24U)
14588 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
14589 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
14590 #define RTC_CR_COE_Pos (23U)
14591 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
14592 #define RTC_CR_COE RTC_CR_COE_Msk
14593 #define RTC_CR_OSEL_Pos (21U)
14594 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
14595 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
14596 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
14597 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
14598 #define RTC_CR_POL_Pos (20U)
14599 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
14600 #define RTC_CR_POL RTC_CR_POL_Msk
14601 #define RTC_CR_COSEL_Pos (19U)
14602 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
14603 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
14604 #define RTC_CR_BKP_Pos (18U)
14605 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
14606 #define RTC_CR_BKP RTC_CR_BKP_Msk
14607 #define RTC_CR_SUB1H_Pos (17U)
14608 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
14609 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
14610 #define RTC_CR_ADD1H_Pos (16U)
14611 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
14612 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
14613 #define RTC_CR_TSIE_Pos (15U)
14614 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
14615 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
14616 #define RTC_CR_WUTIE_Pos (14U)
14617 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
14618 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
14619 #define RTC_CR_ALRBIE_Pos (13U)
14620 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
14621 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
14622 #define RTC_CR_ALRAIE_Pos (12U)
14623 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
14624 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
14625 #define RTC_CR_TSE_Pos (11U)
14626 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
14627 #define RTC_CR_TSE RTC_CR_TSE_Msk
14628 #define RTC_CR_WUTE_Pos (10U)
14629 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
14630 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
14631 #define RTC_CR_ALRBE_Pos (9U)
14632 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
14633 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
14634 #define RTC_CR_ALRAE_Pos (8U)
14635 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
14636 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
14637 #define RTC_CR_FMT_Pos (6U)
14638 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
14639 #define RTC_CR_FMT RTC_CR_FMT_Msk
14640 #define RTC_CR_BYPSHAD_Pos (5U)
14641 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
14642 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
14643 #define RTC_CR_REFCKON_Pos (4U)
14644 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
14645 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
14646 #define RTC_CR_TSEDGE_Pos (3U)
14647 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
14648 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
14649 #define RTC_CR_WUCKSEL_Pos (0U)
14650 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
14651 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
14652 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
14653 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
14654 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
14655
14656 /******************** Bits definition for RTC_ICSR register ******************/
14657 #define RTC_ICSR_RECALPF_Pos (16U)
14658 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
14659 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
14660 #define RTC_ICSR_INIT_Pos (7U)
14661 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
14662 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
14663 #define RTC_ICSR_INITF_Pos (6U)
14664 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
14665 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
14666 #define RTC_ICSR_RSF_Pos (5U)
14667 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
14668 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
14669 #define RTC_ICSR_INITS_Pos (4U)
14670 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
14671 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
14672 #define RTC_ICSR_SHPF_Pos (3U)
14673 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
14674 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
14675 #define RTC_ICSR_WUTWF_Pos (2U)
14676 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
14677 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
14678 #define RTC_ICSR_ALRBWF_Pos (1U)
14679 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
14680 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
14681 #define RTC_ICSR_ALRAWF_Pos (0U)
14682 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
14683 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
14684
14685 /******************** Bits definition for RTC_PRER register *****************/
14686 #define RTC_PRER_PREDIV_A_Pos (16U)
14687 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
14688 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
14689 #define RTC_PRER_PREDIV_S_Pos (0U)
14690 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
14691 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
14692
14693 /******************** Bits definition for RTC_WUTR register *****************/
14694 #define RTC_WUTR_WUT_Pos (0U)
14695 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
14696 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
14697
14698 /******************** Bits definition for RTC_ALRMAR register ***************/
14699 #define RTC_ALRMAR_MSK4_Pos (31U)
14700 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
14701 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
14702 #define RTC_ALRMAR_WDSEL_Pos (30U)
14703 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
14704 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
14705 #define RTC_ALRMAR_DT_Pos (28U)
14706 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
14707 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
14708 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
14709 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
14710 #define RTC_ALRMAR_DU_Pos (24U)
14711 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
14712 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
14713 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
14714 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
14715 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
14716 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
14717 #define RTC_ALRMAR_MSK3_Pos (23U)
14718 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
14719 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
14720 #define RTC_ALRMAR_PM_Pos (22U)
14721 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
14722 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
14723 #define RTC_ALRMAR_HT_Pos (20U)
14724 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
14725 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
14726 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
14727 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
14728 #define RTC_ALRMAR_HU_Pos (16U)
14729 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
14730 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
14731 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
14732 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
14733 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
14734 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
14735 #define RTC_ALRMAR_MSK2_Pos (15U)
14736 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
14737 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
14738 #define RTC_ALRMAR_MNT_Pos (12U)
14739 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
14740 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
14741 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
14742 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
14743 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
14744 #define RTC_ALRMAR_MNU_Pos (8U)
14745 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
14746 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
14747 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
14748 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
14749 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
14750 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
14751 #define RTC_ALRMAR_MSK1_Pos (7U)
14752 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
14753 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
14754 #define RTC_ALRMAR_ST_Pos (4U)
14755 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
14756 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
14757 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
14758 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
14759 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
14760 #define RTC_ALRMAR_SU_Pos (0U)
14761 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
14762 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
14763 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
14764 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
14765 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
14766 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
14767
14768 /******************** Bits definition for RTC_ALRMBR register ***************/
14769 #define RTC_ALRMBR_MSK4_Pos (31U)
14770 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
14771 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
14772 #define RTC_ALRMBR_WDSEL_Pos (30U)
14773 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
14774 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
14775 #define RTC_ALRMBR_DT_Pos (28U)
14776 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
14777 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
14778 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
14779 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
14780 #define RTC_ALRMBR_DU_Pos (24U)
14781 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
14782 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
14783 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
14784 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
14785 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
14786 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
14787 #define RTC_ALRMBR_MSK3_Pos (23U)
14788 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
14789 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
14790 #define RTC_ALRMBR_PM_Pos (22U)
14791 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
14792 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
14793 #define RTC_ALRMBR_HT_Pos (20U)
14794 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
14795 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
14796 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
14797 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
14798 #define RTC_ALRMBR_HU_Pos (16U)
14799 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
14800 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
14801 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
14802 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
14803 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
14804 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
14805 #define RTC_ALRMBR_MSK2_Pos (15U)
14806 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
14807 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
14808 #define RTC_ALRMBR_MNT_Pos (12U)
14809 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
14810 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
14811 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
14812 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
14813 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
14814 #define RTC_ALRMBR_MNU_Pos (8U)
14815 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
14816 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
14817 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
14818 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
14819 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
14820 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
14821 #define RTC_ALRMBR_MSK1_Pos (7U)
14822 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
14823 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
14824 #define RTC_ALRMBR_ST_Pos (4U)
14825 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
14826 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
14827 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
14828 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
14829 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
14830 #define RTC_ALRMBR_SU_Pos (0U)
14831 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
14832 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
14833 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
14834 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
14835 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
14836 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
14837
14838 /******************** Bits definition for RTC_WPR register ******************/
14839 #define RTC_WPR_KEY_Pos (0U)
14840 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
14841 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
14842
14843 /******************** Bits definition for RTC_SSR register ******************/
14844 #define RTC_SSR_SS_Pos (0U)
14845 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
14846 #define RTC_SSR_SS RTC_SSR_SS_Msk
14847
14848 /******************** Bits definition for RTC_SHIFTR register ***************/
14849 #define RTC_SHIFTR_SUBFS_Pos (0U)
14850 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
14851 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
14852 #define RTC_SHIFTR_ADD1S_Pos (31U)
14853 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
14854 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
14855
14856 /******************** Bits definition for RTC_TSTR register *****************/
14857 #define RTC_TSTR_PM_Pos (22U)
14858 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
14859 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
14860 #define RTC_TSTR_HT_Pos (20U)
14861 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
14862 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
14863 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
14864 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
14865 #define RTC_TSTR_HU_Pos (16U)
14866 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
14867 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
14868 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
14869 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
14870 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
14871 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
14872 #define RTC_TSTR_MNT_Pos (12U)
14873 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
14874 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
14875 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
14876 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
14877 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
14878 #define RTC_TSTR_MNU_Pos (8U)
14879 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
14880 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
14881 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
14882 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
14883 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
14884 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
14885 #define RTC_TSTR_ST_Pos (4U)
14886 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
14887 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
14888 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
14889 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
14890 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
14891 #define RTC_TSTR_SU_Pos (0U)
14892 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
14893 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
14894 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
14895 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
14896 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
14897 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
14898
14899 /******************** Bits definition for RTC_TSDR register *****************/
14900 #define RTC_TSDR_WDU_Pos (13U)
14901 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
14902 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
14903 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
14904 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
14905 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
14906 #define RTC_TSDR_MT_Pos (12U)
14907 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
14908 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
14909 #define RTC_TSDR_MU_Pos (8U)
14910 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
14911 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
14912 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
14913 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
14914 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
14915 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
14916 #define RTC_TSDR_DT_Pos (4U)
14917 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
14918 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
14919 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
14920 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
14921 #define RTC_TSDR_DU_Pos (0U)
14922 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
14923 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
14924 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
14925 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
14926 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
14927 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
14928
14929 /******************** Bits definition for RTC_TSSSR register ****************/
14930 #define RTC_TSSSR_SS_Pos (0U)
14931 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
14932 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
14933
14934 /******************** Bits definition for RTC_CALR register *****************/
14935 #define RTC_CALR_CALP_Pos (15U)
14936 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
14937 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
14938 #define RTC_CALR_CALW8_Pos (14U)
14939 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
14940 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
14941 #define RTC_CALR_CALW16_Pos (13U)
14942 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
14943 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
14944 #define RTC_CALR_CALM_Pos (0U)
14945 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
14946 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
14947 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
14948 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
14949 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
14950 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
14951 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
14952 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
14953 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
14954 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
14955 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
14956
14957
14958 /******************** Bits definition for RTC_ALRMASSR register *************/
14959 #define RTC_ALRMASSR_MASKSS_Pos (24U)
14960 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
14961 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
14962 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
14963 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
14964 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
14965 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
14966 #define RTC_ALRMASSR_SS_Pos (0U)
14967 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
14968 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
14969
14970 /******************** Bits definition for RTC_ALRMBSSR register *************/
14971 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
14972 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
14973 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
14974 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
14975 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
14976 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
14977 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
14978 #define RTC_ALRMBSSR_SS_Pos (0U)
14979 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
14980 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
14981
14982
14983 /******************** Bits definition for RTC_SR register *******************/
14984 #define RTC_SR_ITSF_Pos (5U)
14985 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
14986 #define RTC_SR_ITSF RTC_SR_ITSF_Msk
14987 #define RTC_SR_TSOVF_Pos (4U)
14988 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
14989 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
14990 #define RTC_SR_TSF_Pos (3U)
14991 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
14992 #define RTC_SR_TSF RTC_SR_TSF_Msk
14993 #define RTC_SR_WUTF_Pos (2U)
14994 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
14995 #define RTC_SR_WUTF RTC_SR_WUTF_Msk
14996 #define RTC_SR_ALRBF_Pos (1U)
14997 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
14998 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
14999 #define RTC_SR_ALRAF_Pos (0U)
15000 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
15001 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
15002
15003 /******************** Bits definition for RTC_MISR register *****************/
15004 #define RTC_MISR_ITSMF_Pos (5U)
15005 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
15006 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
15007 #define RTC_MISR_TSOVMF_Pos (4U)
15008 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
15009 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
15010 #define RTC_MISR_TSMF_Pos (3U)
15011 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
15012 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
15013 #define RTC_MISR_WUTMF_Pos (2U)
15014 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
15015 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
15016 #define RTC_MISR_ALRBMF_Pos (1U)
15017 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
15018 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
15019 #define RTC_MISR_ALRAMF_Pos (0U)
15020 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
15021 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
15022
15023 /******************** Bits definition for RTC_SCR register ******************/
15024 #define RTC_SCR_CITSF_Pos (5U)
15025 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
15026 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
15027 #define RTC_SCR_CTSOVF_Pos (4U)
15028 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
15029 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
15030 #define RTC_SCR_CTSF_Pos (3U)
15031 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
15032 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
15033 #define RTC_SCR_CWUTF_Pos (2U)
15034 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
15035 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
15036 #define RTC_SCR_CALRBF_Pos (1U)
15037 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
15038 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
15039 #define RTC_SCR_CALRAF_Pos (0U)
15040 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
15041 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
15042
15043 /******************************************************************************/
15044 /* */
15045 /* Tamper and backup register (TAMP) */
15046 /* */
15047 /******************************************************************************/
15048 /******************** Bits definition for TAMP_CR1 register *****************/
15049 #define TAMP_CR1_TAMP1E_Pos (0U)
15050 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
15051 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
15052 #define TAMP_CR1_TAMP2E_Pos (1U)
15053 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
15054 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
15055 #define TAMP_CR1_TAMP3E_Pos (2U)
15056 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
15057 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
15058 #define TAMP_CR1_ITAMP1E_Pos (16U)
15059 #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
15060 #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
15061 #define TAMP_CR1_ITAMP2E_Pos (17U)
15062 #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */
15063 #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
15064 #define TAMP_CR1_ITAMP3E_Pos (18U)
15065 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
15066 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
15067 #define TAMP_CR1_ITAMP4E_Pos (19U)
15068 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
15069 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
15070 #define TAMP_CR1_ITAMP5E_Pos (20U)
15071 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
15072 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
15073 #define TAMP_CR1_ITAMP6E_Pos (21U)
15074 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
15075 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
15076 #define TAMP_CR1_ITAMP8E_Pos (23U)
15077 #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
15078 #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
15079
15080 /******************** Bits definition for TAMP_CR2 register *****************/
15081 #define TAMP_CR2_TAMP1NOERASE_Pos (0U)
15082 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
15083 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
15084 #define TAMP_CR2_TAMP2NOERASE_Pos (1U)
15085 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
15086 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
15087 #define TAMP_CR2_TAMP3NOERASE_Pos (2U)
15088 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
15089 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
15090 #define TAMP_CR2_TAMP1MSK_Pos (16U)
15091 #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
15092 #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
15093 #define TAMP_CR2_TAMP2MSK_Pos (17U)
15094 #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
15095 #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
15096 #define TAMP_CR2_TAMP3MSK_Pos (18U)
15097 #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
15098 #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
15099 #define TAMP_CR2_TAMP1TRG_Pos (24U)
15100 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
15101 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
15102 #define TAMP_CR2_TAMP2TRG_Pos (25U)
15103 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
15104 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
15105 #define TAMP_CR2_TAMP3TRG_Pos (26U)
15106 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
15107 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
15108
15109 /******************** Bits definition for TAMP_FLTCR register ***************/
15110 #define TAMP_FLTCR_TAMPFREQ_Pos (0U)
15111 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
15112 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
15113 #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
15114 #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
15115 #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
15116 #define TAMP_FLTCR_TAMPFLT_Pos (3U)
15117 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
15118 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
15119 #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
15120 #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
15121 #define TAMP_FLTCR_TAMPPRCH_Pos (5U)
15122 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
15123 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
15124 #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
15125 #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
15126 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
15127 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
15128 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
15129
15130 /******************* Bits definition for TAMP_ATCR1 register ****************/
15131 #define TAMP_ATCR1_TAMP1AM_Pos (0U)
15132 #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
15133 #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
15134 #define TAMP_ATCR1_TAMP2AM_Pos (1U)
15135 #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
15136 #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
15137 #define TAMP_ATCR1_TAMP3AM_Pos (2U)
15138 #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
15139 #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
15140 #define TAMP_ATCR1_ATOSEL1_Pos (8U)
15141 #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
15142 #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
15143 #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
15144 #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
15145 #define TAMP_ATCR1_ATOSEL2_Pos (10U)
15146 #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
15147 #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
15148 #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
15149 #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
15150 #define TAMP_ATCR1_ATOSEL3_Pos (12U)
15151 #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
15152 #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
15153 #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
15154 #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
15155 #define TAMP_ATCR1_ATOSEL4_Pos (14U)
15156 #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
15157 #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
15158 #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
15159 #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
15160 #define TAMP_ATCR1_ATCKSEL_Pos (16U)
15161 #define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
15162 #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
15163 #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
15164 #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
15165 #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
15166 #define TAMP_ATCR1_ATPER_Pos (24U)
15167 #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
15168 #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
15169 #define TAMP_ATCR1_ATOSHARE_Pos (30U)
15170 #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
15171 #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
15172 #define TAMP_ATCR1_FLTEN_Pos (31U)
15173 #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
15174 #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
15175
15176 /******************** Bits definition for TAMP_ATSEEDR register *************/
15177 #define TAMP_ATSEEDR_SEED_Pos (0U)
15178 #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
15179 #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
15180
15181 /******************** Bits definition for TAMP_ATOR register ****************/
15182 #define TAMP_ATOR_PRNG_Pos (0U)
15183 #define TAMP_ATOR_PRNG_Msk (0x000000FFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
15184 #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
15185 #define TAMP_ATOR_SEEDF_Pos (14U)
15186 #define TAMP_ATOR_SEEDF_Msk (0x01UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
15187 #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
15188 #define TAMP_ATOR_INITS_Pos (15U)
15189 #define TAMP_ATOR_INITS_Msk (0x01UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
15190 #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
15191
15192 /******************** Bits definition for TAMP_IER register *****************/
15193 #define TAMP_IER_TAMP1IE_Pos (0U)
15194 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
15195 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
15196 #define TAMP_IER_TAMP2IE_Pos (1U)
15197 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
15198 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
15199 #define TAMP_IER_TAMP3IE_Pos (2U)
15200 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
15201 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
15202 #define TAMP_IER_ITAMP1IE_Pos (16U)
15203 #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
15204 #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
15205 #define TAMP_IER_ITAMP2IE_Pos (17U)
15206 #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
15207 #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
15208 #define TAMP_IER_ITAMP3IE_Pos (18U)
15209 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
15210 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
15211 #define TAMP_IER_ITAMP4IE_Pos (19U)
15212 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
15213 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
15214 #define TAMP_IER_ITAMP5IE_Pos (20U)
15215 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
15216 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
15217 #define TAMP_IER_ITAMP6IE_Pos (21U)
15218 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
15219 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
15220 #define TAMP_IER_ITAMP8IE_Pos (23U)
15221 #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */
15222 #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
15223
15224 /******************** Bits definition for TAMP_SR register *****************/
15225 #define TAMP_SR_TAMP1F_Pos (0U)
15226 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
15227 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
15228 #define TAMP_SR_TAMP2F_Pos (1U)
15229 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
15230 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
15231 #define TAMP_SR_TAMP3F_Pos (2U)
15232 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
15233 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
15234 #define TAMP_SR_ITAMP1F_Pos (16U)
15235 #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
15236 #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
15237 #define TAMP_SR_ITAMP2F_Pos (17U)
15238 #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */
15239 #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
15240 #define TAMP_SR_ITAMP3F_Pos (18U)
15241 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
15242 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
15243 #define TAMP_SR_ITAMP4F_Pos (19U)
15244 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
15245 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
15246 #define TAMP_SR_ITAMP5F_Pos (20U)
15247 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
15248 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
15249 #define TAMP_SR_ITAMP6F_Pos (21U)
15250 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
15251 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
15252 #define TAMP_SR_ITAMP8F_Pos (23U)
15253 #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */
15254 #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
15255
15256 /******************** Bits definition for TAMP_MISR register ************ *****/
15257 #define TAMP_MISR_TAMP1MF_Pos (0U)
15258 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
15259 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
15260 #define TAMP_MISR_TAMP2MF_Pos (1U)
15261 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
15262 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
15263 #define TAMP_MISR_TAMP3MF_Pos (2U)
15264 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
15265 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
15266 #define TAMP_MISR_ITAMP1MF_Pos (16U)
15267 #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
15268 #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
15269 #define TAMP_MISR_ITAMP2MF_Pos (17U)
15270 #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */
15271 #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
15272 #define TAMP_MISR_ITAMP3MF_Pos (18U)
15273 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
15274 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
15275 #define TAMP_MISR_ITAMP4MF_Pos (19U)
15276 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
15277 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
15278 #define TAMP_MISR_ITAMP5MF_Pos (20U)
15279 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
15280 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
15281 #define TAMP_MISR_ITAMP6MF_Pos (21U)
15282 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
15283 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
15284 #define TAMP_MISR_ITAMP8MF_Pos (23U)
15285 #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */
15286 #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
15287
15288 /******************** Bits definition for TAMP_SCR register *****************/
15289 #define TAMP_SCR_CTAMP1F_Pos (0U)
15290 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
15291 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
15292 #define TAMP_SCR_CTAMP2F_Pos (1U)
15293 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
15294 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
15295 #define TAMP_SCR_CTAMP3F_Pos (2U)
15296 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
15297 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
15298 #define TAMP_SCR_CITAMP1F_Pos (16U)
15299 #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
15300 #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
15301 #define TAMP_SCR_CITAMP2F_Pos (17U)
15302 #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */
15303 #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
15304 #define TAMP_SCR_CITAMP3F_Pos (18U)
15305 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
15306 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
15307 #define TAMP_SCR_CITAMP4F_Pos (19U)
15308 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
15309 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
15310 #define TAMP_SCR_CITAMP5F_Pos (20U)
15311 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
15312 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
15313 #define TAMP_SCR_CITAMP6F_Pos (21U)
15314 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
15315 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
15316 #define TAMP_SCR_CITAMP8F_Pos (23U)
15317 #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */
15318 #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
15319
15320 /******************** Bits definition for TAMP_COUNTR register **************/
15321 #define TAMP_COUNTR_Pos (16U)
15322 #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
15323 #define TAMP_COUNTR TAMP_COUNTR_Msk
15324
15325 /******************** Bits definition for TAMP_OR register ******************/
15326 #define TAMP_OR_OUT3_RMP_Pos (0U)
15327 #define TAMP_OR_OUT3_RMP_Msk (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000001 */
15328 #define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk
15329
15330 /******************** Bits definition for TAMP_BKP0R register ***************/
15331 #define TAMP_BKP0R_Pos (0U)
15332 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
15333 #define TAMP_BKP0R TAMP_BKP0R_Msk
15334
15335 /******************** Bits definition for TAMP_BKP1R register ****************/
15336 #define TAMP_BKP1R_Pos (0U)
15337 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
15338 #define TAMP_BKP1R TAMP_BKP1R_Msk
15339
15340 /******************** Bits definition for TAMP_BKP2R register ****************/
15341 #define TAMP_BKP2R_Pos (0U)
15342 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
15343 #define TAMP_BKP2R TAMP_BKP2R_Msk
15344
15345 /******************** Bits definition for TAMP_BKP3R register ****************/
15346 #define TAMP_BKP3R_Pos (0U)
15347 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
15348 #define TAMP_BKP3R TAMP_BKP3R_Msk
15349
15350 /******************** Bits definition for TAMP_BKP4R register ****************/
15351 #define TAMP_BKP4R_Pos (0U)
15352 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
15353 #define TAMP_BKP4R TAMP_BKP4R_Msk
15354
15355 /******************** Bits definition for TAMP_BKP5R register ****************/
15356 #define TAMP_BKP5R_Pos (0U)
15357 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
15358 #define TAMP_BKP5R TAMP_BKP5R_Msk
15359
15360 /******************** Bits definition for TAMP_BKP6R register ****************/
15361 #define TAMP_BKP6R_Pos (0U)
15362 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
15363 #define TAMP_BKP6R TAMP_BKP6R_Msk
15364
15365 /******************** Bits definition for TAMP_BKP7R register ****************/
15366 #define TAMP_BKP7R_Pos (0U)
15367 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
15368 #define TAMP_BKP7R TAMP_BKP7R_Msk
15369
15370 /******************** Bits definition for TAMP_BKP8R register ****************/
15371 #define TAMP_BKP8R_Pos (0U)
15372 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
15373 #define TAMP_BKP8R TAMP_BKP8R_Msk
15374
15375 /******************** Bits definition for TAMP_BKP9R register ****************/
15376 #define TAMP_BKP9R_Pos (0U)
15377 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
15378 #define TAMP_BKP9R TAMP_BKP9R_Msk
15379
15380 /******************** Bits definition for TAMP_BKP10R register ***************/
15381 #define TAMP_BKP10R_Pos (0U)
15382 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
15383 #define TAMP_BKP10R TAMP_BKP10R_Msk
15384
15385 /******************** Bits definition for TAMP_BKP11R register ***************/
15386 #define TAMP_BKP11R_Pos (0U)
15387 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
15388 #define TAMP_BKP11R TAMP_BKP11R_Msk
15389
15390 /******************** Bits definition for TAMP_BKP12R register ***************/
15391 #define TAMP_BKP12R_Pos (0U)
15392 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
15393 #define TAMP_BKP12R TAMP_BKP12R_Msk
15394
15395 /******************** Bits definition for TAMP_BKP13R register ***************/
15396 #define TAMP_BKP13R_Pos (0U)
15397 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
15398 #define TAMP_BKP13R TAMP_BKP13R_Msk
15399
15400 /******************** Bits definition for TAMP_BKP14R register ***************/
15401 #define TAMP_BKP14R_Pos (0U)
15402 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
15403 #define TAMP_BKP14R TAMP_BKP14R_Msk
15404
15405 /******************** Bits definition for TAMP_BKP15R register ***************/
15406 #define TAMP_BKP15R_Pos (0U)
15407 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
15408 #define TAMP_BKP15R TAMP_BKP15R_Msk
15409
15410 /******************** Bits definition for TAMP_BKP16R register ***************/
15411 #define TAMP_BKP16R_Pos (0U)
15412 #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
15413 #define TAMP_BKP16R TAMP_BKP16R_Msk
15414
15415 /******************** Bits definition for TAMP_BKP17R register ***************/
15416 #define TAMP_BKP17R_Pos (0U)
15417 #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
15418 #define TAMP_BKP17R TAMP_BKP17R_Msk
15419
15420 /******************** Bits definition for TAMP_BKP18R register ***************/
15421 #define TAMP_BKP18R_Pos (0U)
15422 #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
15423 #define TAMP_BKP18R TAMP_BKP18R_Msk
15424
15425 /******************** Bits definition for TAMP_BKP19R register ***************/
15426 #define TAMP_BKP19R_Pos (0U)
15427 #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
15428 #define TAMP_BKP19R TAMP_BKP19R_Msk
15429
15430 /******************** Bits definition for TAMP_BKP20R register ***************/
15431 #define TAMP_BKP20R_Pos (0U)
15432 #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
15433 #define TAMP_BKP20R TAMP_BKP20R_Msk
15434
15435 /******************** Bits definition for TAMP_BKP21R register ***************/
15436 #define TAMP_BKP21R_Pos (0U)
15437 #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
15438 #define TAMP_BKP21R TAMP_BKP21R_Msk
15439
15440 /******************** Bits definition for TAMP_BKP22R register ***************/
15441 #define TAMP_BKP22R_Pos (0U)
15442 #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
15443 #define TAMP_BKP22R TAMP_BKP22R_Msk
15444
15445 /******************** Bits definition for TAMP_BKP23R register ***************/
15446 #define TAMP_BKP23R_Pos (0U)
15447 #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
15448 #define TAMP_BKP23R TAMP_BKP23R_Msk
15449
15450 /******************** Bits definition for TAMP_BKP24R register ***************/
15451 #define TAMP_BKP24R_Pos (0U)
15452 #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
15453 #define TAMP_BKP24R TAMP_BKP24R_Msk
15454
15455 /******************** Bits definition for TAMP_BKP25R register ***************/
15456 #define TAMP_BKP25R_Pos (0U)
15457 #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
15458 #define TAMP_BKP25R TAMP_BKP25R_Msk
15459
15460 /******************** Bits definition for TAMP_BKP26R register ***************/
15461 #define TAMP_BKP26R_Pos (0U)
15462 #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
15463 #define TAMP_BKP26R TAMP_BKP26R_Msk
15464
15465 /******************** Bits definition for TAMP_BKP27R register ***************/
15466 #define TAMP_BKP27R_Pos (0U)
15467 #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
15468 #define TAMP_BKP27R TAMP_BKP27R_Msk
15469
15470 /******************** Bits definition for TAMP_BKP28R register ***************/
15471 #define TAMP_BKP28R_Pos (0U)
15472 #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
15473 #define TAMP_BKP28R TAMP_BKP28R_Msk
15474
15475 /******************** Bits definition for TAMP_BKP29R register ***************/
15476 #define TAMP_BKP29R_Pos (0U)
15477 #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
15478 #define TAMP_BKP29R TAMP_BKP29R_Msk
15479
15480 /******************** Bits definition for TAMP_BKP30R register ***************/
15481 #define TAMP_BKP30R_Pos (0U)
15482 #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
15483 #define TAMP_BKP30R TAMP_BKP30R_Msk
15484
15485 /******************** Bits definition for TAMP_BKP31R register ***************/
15486 #define TAMP_BKP31R_Pos (0U)
15487 #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
15488 #define TAMP_BKP31R TAMP_BKP31R_Msk
15489
15490 /******************** Number of backup registers ******************************/
15491 #define TAMP_BKP_NUMBER_Pos (5U)
15492 #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */
15493 #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 32 BKPREG */
15494
15495 /******************************************************************************/
15496 /* */
15497 /* SPDIF-RX Interface */
15498 /* */
15499 /******************************************************************************/
15500 /******************** Bit definition for SPDIF_CR register ******************/
15501 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
15502 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
15503 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
15504 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
15505 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
15506 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
15507 #define SPDIFRX_CR_RXSTEO_Pos (3U)
15508 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
15509 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
15510 #define SPDIFRX_CR_DRFMT_Pos (4U)
15511 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
15512 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
15513 #define SPDIFRX_CR_PMSK_Pos (6U)
15514 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
15515 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
15516 #define SPDIFRX_CR_VMSK_Pos (7U)
15517 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
15518 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
15519 #define SPDIFRX_CR_CUMSK_Pos (8U)
15520 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
15521 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
15522 #define SPDIFRX_CR_PTMSK_Pos (9U)
15523 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
15524 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
15525 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
15526 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
15527 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
15528 #define SPDIFRX_CR_CHSEL_Pos (11U)
15529 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
15530 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
15531 #define SPDIFRX_CR_NBTR_Pos (12U)
15532 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
15533 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
15534 #define SPDIFRX_CR_WFA_Pos (14U)
15535 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
15536 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
15537 #define SPDIFRX_CR_INSEL_Pos (16U)
15538 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
15539 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
15540 #define SPDIFRX_CR_CKSEN_Pos (20U)
15541 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
15542 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
15543 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
15544 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
15545 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
15546
15547 /******************* Bit definition for SPDIFRX_IMR register *******************/
15548 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
15549 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
15550 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
15551 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
15552 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
15553 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
15554 #define SPDIFRX_IMR_PERRIE_Pos (2U)
15555 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
15556 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
15557 #define SPDIFRX_IMR_OVRIE_Pos (3U)
15558 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
15559 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
15560 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
15561 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
15562 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
15563 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
15564 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
15565 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
15566 #define SPDIFRX_IMR_IFEIE_Pos (6U)
15567 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
15568 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
15569
15570 /******************* Bit definition for SPDIFRX_SR register *******************/
15571 #define SPDIFRX_SR_RXNE_Pos (0U)
15572 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
15573 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
15574 #define SPDIFRX_SR_CSRNE_Pos (1U)
15575 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
15576 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
15577 #define SPDIFRX_SR_PERR_Pos (2U)
15578 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
15579 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
15580 #define SPDIFRX_SR_OVR_Pos (3U)
15581 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
15582 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
15583 #define SPDIFRX_SR_SBD_Pos (4U)
15584 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
15585 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
15586 #define SPDIFRX_SR_SYNCD_Pos (5U)
15587 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
15588 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
15589 #define SPDIFRX_SR_FERR_Pos (6U)
15590 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
15591 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
15592 #define SPDIFRX_SR_SERR_Pos (7U)
15593 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
15594 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
15595 #define SPDIFRX_SR_TERR_Pos (8U)
15596 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
15597 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
15598 #define SPDIFRX_SR_WIDTH5_Pos (16U)
15599 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
15600 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
15601
15602 /******************* Bit definition for SPDIFRX_IFCR register *******************/
15603 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
15604 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
15605 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
15606 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
15607 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
15608 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
15609 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
15610 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
15611 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
15612 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
15613 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
15614 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
15615
15616 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
15617 #define SPDIFRX_DR0_DR_Pos (0U)
15618 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
15619 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
15620 #define SPDIFRX_DR0_PE_Pos (24U)
15621 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
15622 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
15623 #define SPDIFRX_DR0_V_Pos (25U)
15624 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
15625 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
15626 #define SPDIFRX_DR0_U_Pos (26U)
15627 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
15628 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
15629 #define SPDIFRX_DR0_C_Pos (27U)
15630 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
15631 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
15632 #define SPDIFRX_DR0_PT_Pos (28U)
15633 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
15634 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
15635
15636 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
15637 #define SPDIFRX_DR1_DR_Pos (8U)
15638 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
15639 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
15640 #define SPDIFRX_DR1_PT_Pos (4U)
15641 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
15642 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
15643 #define SPDIFRX_DR1_C_Pos (3U)
15644 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
15645 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
15646 #define SPDIFRX_DR1_U_Pos (2U)
15647 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
15648 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
15649 #define SPDIFRX_DR1_V_Pos (1U)
15650 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
15651 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
15652 #define SPDIFRX_DR1_PE_Pos (0U)
15653 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
15654 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
15655
15656 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
15657 #define SPDIFRX_DR1_DRNL1_Pos (16U)
15658 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
15659 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
15660 #define SPDIFRX_DR1_DRNL2_Pos (0U)
15661 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
15662 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
15663
15664 /******************* Bit definition for SPDIFRX_CSR register *******************/
15665 #define SPDIFRX_CSR_USR_Pos (0U)
15666 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
15667 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
15668 #define SPDIFRX_CSR_CS_Pos (16U)
15669 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
15670 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
15671 #define SPDIFRX_CSR_SOB_Pos (24U)
15672 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
15673 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
15674
15675 /******************* Bit definition for SPDIFRX_DIR register *******************/
15676 #define SPDIFRX_DIR_THI_Pos (0U)
15677 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
15678 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
15679 #define SPDIFRX_DIR_TLO_Pos (16U)
15680 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
15681 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
15682
15683 /******************* Bit definition for SPDIFRX_VERR register *******************/
15684 #define SPDIFRX_VERR_MINREV_Pos (0U)
15685 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
15686 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
15687 #define SPDIFRX_VERR_MAJREV_Pos (4U)
15688 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
15689 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
15690
15691 /******************* Bit definition for SPDIFRX_IDR register *******************/
15692 #define SPDIFRX_IDR_ID_Pos (0U)
15693 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
15694 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
15695
15696 /******************* Bit definition for SPDIFRX_SIDR register *******************/
15697 #define SPDIFRX_SIDR_SID_Pos (0U)
15698 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
15699 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
15700
15701 /******************************************************************************/
15702 /* */
15703 /* Serial Audio Interface */
15704 /* */
15705 /******************************************************************************/
15706 /******************************* SAI VERSION ********************************/
15707 #define SAI_VER_V2_1
15708
15709 /******************** Bit definition for SAI_GCR register *******************/
15710 #define SAI_GCR_SYNCIN_Pos (0U)
15711 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
15712 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
15713 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
15714 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
15715
15716 #define SAI_GCR_SYNCOUT_Pos (4U)
15717 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
15718 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
15719 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
15720 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
15721
15722 /******************* Bit definition for SAI_xCR1 register *******************/
15723 #define SAI_xCR1_MODE_Pos (0U)
15724 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
15725 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
15726 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
15727 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
15728
15729 #define SAI_xCR1_PRTCFG_Pos (2U)
15730 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
15731 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
15732 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
15733 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
15734
15735 #define SAI_xCR1_DS_Pos (5U)
15736 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
15737 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
15738 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
15739 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
15740 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
15741
15742 #define SAI_xCR1_LSBFIRST_Pos (8U)
15743 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
15744 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
15745 #define SAI_xCR1_CKSTR_Pos (9U)
15746 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
15747 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
15748
15749 #define SAI_xCR1_SYNCEN_Pos (10U)
15750 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
15751 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
15752 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
15753 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
15754
15755 #define SAI_xCR1_MONO_Pos (12U)
15756 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
15757 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
15758 #define SAI_xCR1_OUTDRIV_Pos (13U)
15759 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
15760 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
15761 #define SAI_xCR1_SAIEN_Pos (16U)
15762 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
15763 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
15764 #define SAI_xCR1_DMAEN_Pos (17U)
15765 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
15766 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
15767 #define SAI_xCR1_NODIV_Pos (19U)
15768 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
15769 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
15770
15771 #define SAI_xCR1_MCKDIV_Pos (20U)
15772 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
15773 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
15774 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
15775 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
15776 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
15777 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
15778 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
15779 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
15780
15781 #define SAI_xCR1_MCKEN_Pos (27U)
15782 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
15783 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
15784
15785 #define SAI_xCR1_OSR_Pos (26U)
15786 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
15787 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
15788
15789 /* Legacy define */
15790 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
15791
15792 /******************* Bit definition for SAI_xCR2 register *******************/
15793 #define SAI_xCR2_FTH_Pos (0U)
15794 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
15795 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
15796 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
15797 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
15798 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
15799
15800 #define SAI_xCR2_FFLUSH_Pos (3U)
15801 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
15802 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
15803 #define SAI_xCR2_TRIS_Pos (4U)
15804 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
15805 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
15806 #define SAI_xCR2_MUTE_Pos (5U)
15807 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
15808 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
15809 #define SAI_xCR2_MUTEVAL_Pos (6U)
15810 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
15811 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
15812
15813 #define SAI_xCR2_MUTECNT_Pos (7U)
15814 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
15815 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
15816 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
15817 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
15818 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
15819 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
15820 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
15821 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
15822
15823 #define SAI_xCR2_CPL_Pos (13U)
15824 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
15825 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
15826
15827 #define SAI_xCR2_COMP_Pos (14U)
15828 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
15829 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
15830 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
15831 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
15832
15833 /****************** Bit definition for SAI_xFRCR register *******************/
15834 #define SAI_xFRCR_FRL_Pos (0U)
15835 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
15836 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
15837 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
15838 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
15839 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
15840 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
15841 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
15842 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
15843 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
15844 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
15845
15846 #define SAI_xFRCR_FSALL_Pos (8U)
15847 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
15848 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
15849 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
15850 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
15851 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
15852 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
15853 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
15854 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
15855 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
15856
15857 #define SAI_xFRCR_FSDEF_Pos (16U)
15858 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
15859 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
15860 #define SAI_xFRCR_FSPOL_Pos (17U)
15861 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
15862 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
15863 #define SAI_xFRCR_FSOFF_Pos (18U)
15864 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
15865 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
15866
15867 /* Legacy define */
15868 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
15869
15870 /****************** Bit definition for SAI_xSLOTR register *******************/
15871 #define SAI_xSLOTR_FBOFF_Pos (0U)
15872 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
15873 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
15874 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
15875 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
15876 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
15877 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
15878 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
15879
15880 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
15881 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
15882 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
15883 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
15884 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
15885
15886 #define SAI_xSLOTR_NBSLOT_Pos (8U)
15887 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
15888 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
15889 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
15890 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
15891 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
15892 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
15893
15894 #define SAI_xSLOTR_SLOTEN_Pos (16U)
15895 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
15896 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
15897
15898 /******************* Bit definition for SAI_xIMR register *******************/
15899 #define SAI_xIMR_OVRUDRIE_Pos (0U)
15900 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
15901 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
15902 #define SAI_xIMR_MUTEDETIE_Pos (1U)
15903 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
15904 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
15905 #define SAI_xIMR_WCKCFGIE_Pos (2U)
15906 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
15907 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
15908 #define SAI_xIMR_FREQIE_Pos (3U)
15909 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
15910 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
15911 #define SAI_xIMR_CNRDYIE_Pos (4U)
15912 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
15913 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
15914 #define SAI_xIMR_AFSDETIE_Pos (5U)
15915 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
15916 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
15917 #define SAI_xIMR_LFSDETIE_Pos (6U)
15918 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
15919 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
15920
15921 /******************** Bit definition for SAI_xSR register *******************/
15922 #define SAI_xSR_OVRUDR_Pos (0U)
15923 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
15924 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
15925 #define SAI_xSR_MUTEDET_Pos (1U)
15926 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
15927 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
15928 #define SAI_xSR_WCKCFG_Pos (2U)
15929 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
15930 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
15931 #define SAI_xSR_FREQ_Pos (3U)
15932 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
15933 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
15934 #define SAI_xSR_CNRDY_Pos (4U)
15935 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
15936 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
15937 #define SAI_xSR_AFSDET_Pos (5U)
15938 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
15939 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
15940 #define SAI_xSR_LFSDET_Pos (6U)
15941 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
15942 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
15943
15944 #define SAI_xSR_FLVL_Pos (16U)
15945 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
15946 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
15947 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
15948 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
15949 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
15950
15951 /****************** Bit definition for SAI_xCLRFR register ******************/
15952 #define SAI_xCLRFR_COVRUDR_Pos (0U)
15953 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
15954 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
15955 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
15956 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
15957 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
15958 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
15959 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
15960 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
15961 #define SAI_xCLRFR_CFREQ_Pos (3U)
15962 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
15963 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
15964 #define SAI_xCLRFR_CCNRDY_Pos (4U)
15965 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
15966 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
15967 #define SAI_xCLRFR_CAFSDET_Pos (5U)
15968 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
15969 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
15970 #define SAI_xCLRFR_CLFSDET_Pos (6U)
15971 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
15972 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
15973
15974 /****************** Bit definition for SAI_xDR register *********************/
15975 #define SAI_xDR_DATA_Pos (0U)
15976 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
15977 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
15978
15979 /******************* Bit definition for SAI_PDMCR register ******************/
15980 #define SAI_PDMCR_PDMEN_Pos (0U)
15981 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
15982 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
15983
15984 #define SAI_PDMCR_MICNBR_Pos (4U)
15985 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
15986 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
15987 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
15988 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
15989
15990 #define SAI_PDMCR_CKEN1_Pos (8U)
15991 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
15992 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
15993 #define SAI_PDMCR_CKEN2_Pos (9U)
15994 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
15995 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
15996 #define SAI_PDMCR_CKEN3_Pos (10U)
15997 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
15998 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
15999 #define SAI_PDMCR_CKEN4_Pos (11U)
16000 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
16001 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
16002
16003 /****************** Bit definition for SAI_PDMDLY register ******************/
16004 #define SAI_PDMDLY_DLYM1L_Pos (0U)
16005 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
16006 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
16007 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
16008 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
16009 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
16010
16011 #define SAI_PDMDLY_DLYM1R_Pos (4U)
16012 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
16013 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
16014 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
16015 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
16016 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
16017
16018 #define SAI_PDMDLY_DLYM2L_Pos (8U)
16019 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
16020 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
16021 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
16022 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
16023 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
16024
16025 #define SAI_PDMDLY_DLYM2R_Pos (12U)
16026 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
16027 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
16028 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
16029 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
16030 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
16031
16032 #define SAI_PDMDLY_DLYM3L_Pos (16U)
16033 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
16034 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
16035 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
16036 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
16037 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
16038
16039 #define SAI_PDMDLY_DLYM3R_Pos (20U)
16040 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
16041 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
16042 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
16043 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
16044 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
16045
16046 #define SAI_PDMDLY_DLYM4L_Pos (24U)
16047 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
16048 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
16049 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
16050 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
16051 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
16052
16053 #define SAI_PDMDLY_DLYM4R_Pos (28U)
16054 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
16055 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
16056 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
16057 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
16058 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
16059
16060 /******************************************************************************/
16061 /* */
16062 /* SDMMC Interface */
16063 /* */
16064 /******************************************************************************/
16065 /****************** Bit definition for SDMMC_POWER register ******************/
16066 #define SDMMC_POWER_PWRCTRL_Pos (0U)
16067 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
16068 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
16069 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
16070 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
16071 #define SDMMC_POWER_VSWITCH_Pos (2U)
16072 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
16073 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
16074 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
16075 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
16076 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
16077 #define SDMMC_POWER_DIRPOL_Pos (4U)
16078 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
16079 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
16080
16081 /****************** Bit definition for SDMMC_CLKCR register ******************/
16082 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
16083 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
16084 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
16085 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
16086 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
16087 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
16088
16089 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
16090 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
16091 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
16092 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
16093 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
16094
16095 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
16096 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
16097 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
16098 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
16099 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
16100 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
16101 #define SDMMC_CLKCR_DDR_Pos (18U)
16102 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
16103 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
16104 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
16105 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
16106 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
16107 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
16108 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
16109 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
16110 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
16111 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
16112
16113 /******************* Bit definition for SDMMC_ARG register *******************/
16114 #define SDMMC_ARG_CMDARG_Pos (0U)
16115 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
16116 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
16117
16118 /******************* Bit definition for SDMMC_CMD register *******************/
16119 #define SDMMC_CMD_CMDINDEX_Pos (0U)
16120 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
16121 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
16122 #define SDMMC_CMD_CMDTRANS_Pos (6U)
16123 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
16124 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
16125 #define SDMMC_CMD_CMDSTOP_Pos (7U)
16126 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
16127 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
16128
16129 #define SDMMC_CMD_WAITRESP_Pos (8U)
16130 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
16131 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
16132 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
16133 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
16134
16135 #define SDMMC_CMD_WAITINT_Pos (10U)
16136 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
16137 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
16138 #define SDMMC_CMD_WAITPEND_Pos (11U)
16139 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
16140 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
16141 #define SDMMC_CMD_CPSMEN_Pos (12U)
16142 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
16143 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
16144 #define SDMMC_CMD_DTHOLD_Pos (13U)
16145 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
16146 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
16147 #define SDMMC_CMD_BOOTMODE_Pos (14U)
16148 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
16149 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
16150 #define SDMMC_CMD_BOOTEN_Pos (15U)
16151 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
16152 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
16153 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
16154 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
16155 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
16156
16157 /***************** Bit definition for SDMMC_RESPCMD register *****************/
16158 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
16159 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
16160 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
16161
16162 /****************** Bit definition for SDMMC_RESP0 register ******************/
16163 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
16164 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
16165 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
16166
16167 /****************** Bit definition for SDMMC_RESP1 register ******************/
16168 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
16169 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
16170 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
16171
16172 /****************** Bit definition for SDMMC_RESP2 register ******************/
16173 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
16174 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
16175 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
16176
16177 /****************** Bit definition for SDMMC_RESP3 register ******************/
16178 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
16179 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
16180 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
16181
16182 /****************** Bit definition for SDMMC_RESP4 register ******************/
16183 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
16184 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
16185 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
16186
16187 /****************** Bit definition for SDMMC_DTIMER register *****************/
16188 #define SDMMC_DTIMER_DATATIME_Pos (0U)
16189 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
16190 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
16191
16192 /****************** Bit definition for SDMMC_DLEN register *******************/
16193 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
16194 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
16195 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
16196
16197 /****************** Bit definition for SDMMC_DCTRL register ******************/
16198 #define SDMMC_DCTRL_DTEN_Pos (0U)
16199 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
16200 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
16201 #define SDMMC_DCTRL_DTDIR_Pos (1U)
16202 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
16203 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
16204 #define SDMMC_DCTRL_DTMODE_Pos (2U)
16205 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
16206 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
16207 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
16208 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
16209
16210 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
16211 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
16212 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
16213 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
16214 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
16215 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
16216 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
16217
16218 #define SDMMC_DCTRL_RWSTART_Pos (8U)
16219 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
16220 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
16221 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
16222 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
16223 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
16224 #define SDMMC_DCTRL_RWMOD_Pos (10U)
16225 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
16226 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
16227 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
16228 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
16229 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
16230 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
16231 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
16232 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
16233 #define SDMMC_DCTRL_FIFORST_Pos (13U)
16234 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
16235 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
16236
16237 /****************** Bit definition for SDMMC_DCOUNT register *****************/
16238 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
16239 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
16240 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
16241
16242 /****************** Bit definition for SDMMC_STA register ********************/
16243 #define SDMMC_STA_CCRCFAIL_Pos (0U)
16244 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
16245 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
16246 #define SDMMC_STA_DCRCFAIL_Pos (1U)
16247 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
16248 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
16249 #define SDMMC_STA_CTIMEOUT_Pos (2U)
16250 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
16251 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
16252 #define SDMMC_STA_DTIMEOUT_Pos (3U)
16253 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
16254 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
16255 #define SDMMC_STA_TXUNDERR_Pos (4U)
16256 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
16257 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
16258 #define SDMMC_STA_RXOVERR_Pos (5U)
16259 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
16260 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
16261 #define SDMMC_STA_CMDREND_Pos (6U)
16262 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
16263 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
16264 #define SDMMC_STA_CMDSENT_Pos (7U)
16265 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
16266 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
16267 #define SDMMC_STA_DATAEND_Pos (8U)
16268 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
16269 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
16270 #define SDMMC_STA_DHOLD_Pos (9U)
16271 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
16272 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
16273 #define SDMMC_STA_DBCKEND_Pos (10U)
16274 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
16275 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
16276 #define SDMMC_STA_DABORT_Pos (11U)
16277 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
16278 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
16279 #define SDMMC_STA_DPSMACT_Pos (12U)
16280 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
16281 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
16282 #define SDMMC_STA_CPSMACT_Pos (13U)
16283 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
16284 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
16285 #define SDMMC_STA_TXFIFOHE_Pos (14U)
16286 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
16287 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
16288 #define SDMMC_STA_RXFIFOHF_Pos (15U)
16289 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
16290 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
16291 #define SDMMC_STA_TXFIFOF_Pos (16U)
16292 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
16293 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
16294 #define SDMMC_STA_RXFIFOF_Pos (17U)
16295 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
16296 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
16297 #define SDMMC_STA_TXFIFOE_Pos (18U)
16298 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
16299 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
16300 #define SDMMC_STA_RXFIFOE_Pos (19U)
16301 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
16302 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
16303 #define SDMMC_STA_BUSYD0_Pos (20U)
16304 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
16305 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
16306 #define SDMMC_STA_BUSYD0END_Pos (21U)
16307 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
16308 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
16309 #define SDMMC_STA_SDIOIT_Pos (22U)
16310 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
16311 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
16312 #define SDMMC_STA_ACKFAIL_Pos (23U)
16313 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
16314 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
16315 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
16316 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
16317 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
16318 #define SDMMC_STA_VSWEND_Pos (25U)
16319 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
16320 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
16321 #define SDMMC_STA_CKSTOP_Pos (26U)
16322 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
16323 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
16324 #define SDMMC_STA_IDMATE_Pos (27U)
16325 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
16326 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
16327 #define SDMMC_STA_IDMABTC_Pos (28U)
16328 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
16329 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
16330
16331 /******************* Bit definition for SDMMC_ICR register *******************/
16332 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
16333 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
16334 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
16335 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
16336 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
16337 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
16338 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
16339 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
16340 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
16341 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
16342 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
16343 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
16344 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
16345 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
16346 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
16347 #define SDMMC_ICR_RXOVERRC_Pos (5U)
16348 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
16349 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
16350 #define SDMMC_ICR_CMDRENDC_Pos (6U)
16351 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
16352 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
16353 #define SDMMC_ICR_CMDSENTC_Pos (7U)
16354 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
16355 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
16356 #define SDMMC_ICR_DATAENDC_Pos (8U)
16357 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
16358 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
16359 #define SDMMC_ICR_DHOLDC_Pos (9U)
16360 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
16361 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
16362 #define SDMMC_ICR_DBCKENDC_Pos (10U)
16363 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
16364 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
16365 #define SDMMC_ICR_DABORTC_Pos (11U)
16366 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
16367 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
16368 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
16369 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
16370 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
16371 #define SDMMC_ICR_SDIOITC_Pos (22U)
16372 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
16373 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
16374 #define SDMMC_ICR_ACKFAILC_Pos (23U)
16375 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
16376 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
16377 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
16378 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
16379 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
16380 #define SDMMC_ICR_VSWENDC_Pos (25U)
16381 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
16382 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
16383 #define SDMMC_ICR_CKSTOPC_Pos (26U)
16384 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
16385 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
16386 #define SDMMC_ICR_IDMATEC_Pos (27U)
16387 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
16388 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
16389 #define SDMMC_ICR_IDMABTCC_Pos (28U)
16390 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
16391 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
16392
16393 /****************** Bit definition for SDMMC_MASK register *******************/
16394 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
16395 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
16396 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
16397 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
16398 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
16399 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
16400 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
16401 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
16402 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
16403 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
16404 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
16405 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
16406 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
16407 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
16408 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
16409 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
16410 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
16411 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
16412 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
16413 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
16414 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
16415 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
16416 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
16417 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
16418 #define SDMMC_MASK_DATAENDIE_Pos (8U)
16419 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
16420 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
16421 #define SDMMC_MASK_DHOLDIE_Pos (9U)
16422 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
16423 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
16424 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
16425 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
16426 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
16427 #define SDMMC_MASK_DABORTIE_Pos (11U)
16428 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
16429 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
16430
16431 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
16432 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
16433 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
16434 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
16435 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
16436 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
16437
16438 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
16439 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
16440 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
16441 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
16442 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
16443 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
16444
16445 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
16446 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
16447 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
16448 #define SDMMC_MASK_SDIOITIE_Pos (22U)
16449 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
16450 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
16451 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
16452 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
16453 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
16454 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
16455 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
16456 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
16457 #define SDMMC_MASK_VSWENDIE_Pos (25U)
16458 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
16459 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
16460 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
16461 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
16462 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
16463 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
16464 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
16465 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
16466
16467 /***************** Bit definition for SDMMC_ACKTIME register *****************/
16468 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
16469 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
16470 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
16471
16472 /****************** Bit definition for SDMMC_FIFO register *******************/
16473 #define SDMMC_FIFO_FIFODATA_Pos (0U)
16474 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
16475 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
16476
16477 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
16478 #define SDMMC_IDMA_IDMAEN_Pos (0U)
16479 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
16480 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
16481 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
16482 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
16483 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
16484 #define SDMMC_IDMA_IDMABACT_Pos (2U)
16485 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
16486 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
16487
16488 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
16489 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
16490 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
16491 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
16492
16493 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
16494 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
16495
16496 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
16497 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
16498
16499 /******************************************************************************/
16500 /* */
16501 /* Delay Block Interface (DLYB) */
16502 /* */
16503 /******************************************************************************/
16504 /******************* Bit definition for DLYB_CR register ********************/
16505 #define DLYB_CR_DEN_Pos (0U)
16506 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
16507 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
16508 #define DLYB_CR_SEN_Pos (1U)
16509 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
16510 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
16511
16512
16513 /******************* Bit definition for DLYB_CFGR register ********************/
16514 #define DLYB_CFGR_SEL_Pos (0U)
16515 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
16516 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
16517 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
16518 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
16519 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
16520 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
16521
16522 #define DLYB_CFGR_UNIT_Pos (8U)
16523 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
16524 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
16525 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
16526 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
16527 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
16528 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
16529 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
16530 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
16531 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
16532
16533 #define DLYB_CFGR_LNG_Pos (16U)
16534 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
16535 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
16536 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
16537 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
16538 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
16539 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
16540 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
16541 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
16542 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
16543 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
16544 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
16545 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
16546 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
16547 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
16548
16549 #define DLYB_CFGR_LNGF_Pos (31U)
16550 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
16551 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
16552
16553 /******************************************************************************/
16554 /* */
16555 /* Serial Peripheral Interface (SPI/I2S) */
16556 /* */
16557 /******************************************************************************/
16558 #define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
16559 /******************* Bit definition for SPI_CR1 register ********************/
16560 #define SPI_CR1_SPE_Pos (0U)
16561 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
16562 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
16563 #define SPI_CR1_MASRX_Pos (8U)
16564 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
16565 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
16566 #define SPI_CR1_CSTART_Pos (9U)
16567 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
16568 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
16569 #define SPI_CR1_CSUSP_Pos (10U)
16570 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
16571 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
16572 #define SPI_CR1_HDDIR_Pos (11U)
16573 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
16574 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
16575 #define SPI_CR1_SSI_Pos (12U)
16576 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
16577 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
16578 #define SPI_CR1_CRC33_17_Pos (13U)
16579 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
16580 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
16581 #define SPI_CR1_RCRCINI_Pos (14U)
16582 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
16583 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
16584 #define SPI_CR1_TCRCINI_Pos (15U)
16585 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
16586 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
16587 #define SPI_CR1_IOLOCK_Pos (16U)
16588 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
16589 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
16590
16591 /******************* Bit definition for SPI_CR2 register ********************/
16592 #define SPI_CR2_TSER_Pos (16U)
16593 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
16594 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
16595 #define SPI_CR2_TSIZE_Pos (0U)
16596 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
16597 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
16598
16599 /******************* Bit definition for SPI_CFG1 register ********************/
16600 #define SPI_CFG1_DSIZE_Pos (0U)
16601 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
16602 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
16603 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
16604 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
16605 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
16606 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
16607 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
16608
16609 #define SPI_CFG1_FTHLV_Pos (5U)
16610 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
16611 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
16612 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
16613 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
16614 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
16615 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
16616
16617 #define SPI_CFG1_UDRCFG_Pos (9U)
16618 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
16619 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
16620 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
16621 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
16622
16623
16624 #define SPI_CFG1_UDRDET_Pos (11U)
16625 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
16626 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
16627 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
16628 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
16629
16630 #define SPI_CFG1_RXDMAEN_Pos (14U)
16631 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
16632 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
16633 #define SPI_CFG1_TXDMAEN_Pos (15U)
16634 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
16635 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
16636
16637 #define SPI_CFG1_CRCSIZE_Pos (16U)
16638 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
16639 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
16640 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
16641 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
16642 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
16643 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
16644 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
16645
16646 #define SPI_CFG1_CRCEN_Pos (22U)
16647 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
16648 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
16649
16650 #define SPI_CFG1_MBR_Pos (28U)
16651 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
16652 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
16653 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
16654 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
16655 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
16656
16657 /******************* Bit definition for SPI_CFG2 register ********************/
16658 #define SPI_CFG2_MSSI_Pos (0U)
16659 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
16660 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
16661 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
16662 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
16663 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
16664 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
16665
16666 #define SPI_CFG2_MIDI_Pos (4U)
16667 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
16668 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
16669 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
16670 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
16671 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
16672 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
16673
16674 #define SPI_CFG2_IOSWP_Pos (15U)
16675 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
16676 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
16677
16678 #define SPI_CFG2_COMM_Pos (17U)
16679 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
16680 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
16681 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
16682 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
16683
16684 #define SPI_CFG2_SP_Pos (19U)
16685 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
16686 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
16687 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
16688 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
16689 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
16690
16691 #define SPI_CFG2_MASTER_Pos (22U)
16692 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
16693 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
16694 #define SPI_CFG2_LSBFRST_Pos (23U)
16695 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
16696 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
16697 #define SPI_CFG2_CPHA_Pos (24U)
16698 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
16699 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
16700 #define SPI_CFG2_CPOL_Pos (25U)
16701 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
16702 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
16703 #define SPI_CFG2_SSM_Pos (26U)
16704 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
16705 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
16706
16707 #define SPI_CFG2_SSIOP_Pos (28U)
16708 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
16709 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
16710 #define SPI_CFG2_SSOE_Pos (29U)
16711 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
16712 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
16713 #define SPI_CFG2_SSOM_Pos (30U)
16714 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
16715 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
16716
16717 #define SPI_CFG2_AFCNTR_Pos (31U)
16718 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
16719 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
16720
16721 /******************* Bit definition for SPI_IER register ********************/
16722 #define SPI_IER_RXPIE_Pos (0U)
16723 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
16724 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
16725 #define SPI_IER_TXPIE_Pos (1U)
16726 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
16727 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
16728 #define SPI_IER_DXPIE_Pos (2U)
16729 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
16730 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
16731 #define SPI_IER_EOTIE_Pos (3U)
16732 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
16733 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
16734 #define SPI_IER_TXTFIE_Pos (4U)
16735 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
16736 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
16737 #define SPI_IER_UDRIE_Pos (5U)
16738 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
16739 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
16740 #define SPI_IER_OVRIE_Pos (6U)
16741 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
16742 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
16743 #define SPI_IER_CRCEIE_Pos (7U)
16744 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
16745 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
16746 #define SPI_IER_TIFREIE_Pos (8U)
16747 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
16748 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
16749 #define SPI_IER_MODFIE_Pos (9U)
16750 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
16751 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
16752 #define SPI_IER_TSERFIE_Pos (10U)
16753 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
16754 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
16755
16756 /******************* Bit definition for SPI_SR register ********************/
16757 #define SPI_SR_RXP_Pos (0U)
16758 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
16759 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
16760 #define SPI_SR_TXP_Pos (1U)
16761 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
16762 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
16763 #define SPI_SR_DXP_Pos (2U)
16764 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
16765 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
16766 #define SPI_SR_EOT_Pos (3U)
16767 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
16768 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
16769 #define SPI_SR_TXTF_Pos (4U)
16770 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
16771 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
16772 #define SPI_SR_UDR_Pos (5U)
16773 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
16774 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
16775 #define SPI_SR_OVR_Pos (6U)
16776 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
16777 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
16778 #define SPI_SR_CRCE_Pos (7U)
16779 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
16780 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
16781 #define SPI_SR_TIFRE_Pos (8U)
16782 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
16783 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
16784 #define SPI_SR_MODF_Pos (9U)
16785 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
16786 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
16787 #define SPI_SR_TSERF_Pos (10U)
16788 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
16789 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
16790 #define SPI_SR_SUSP_Pos (11U)
16791 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
16792 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
16793 #define SPI_SR_TXC_Pos (12U)
16794 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
16795 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
16796 #define SPI_SR_RXPLVL_Pos (13U)
16797 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
16798 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
16799 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
16800 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
16801 #define SPI_SR_RXWNE_Pos (15U)
16802 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
16803 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
16804 #define SPI_SR_CTSIZE_Pos (16U)
16805 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
16806 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
16807
16808 /******************* Bit definition for SPI_IFCR register ********************/
16809 #define SPI_IFCR_EOTC_Pos (3U)
16810 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
16811 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
16812 #define SPI_IFCR_TXTFC_Pos (4U)
16813 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
16814 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
16815 #define SPI_IFCR_UDRC_Pos (5U)
16816 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
16817 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
16818 #define SPI_IFCR_OVRC_Pos (6U)
16819 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
16820 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
16821 #define SPI_IFCR_CRCEC_Pos (7U)
16822 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
16823 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
16824 #define SPI_IFCR_TIFREC_Pos (8U)
16825 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
16826 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
16827 #define SPI_IFCR_MODFC_Pos (9U)
16828 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
16829 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
16830 #define SPI_IFCR_TSERFC_Pos (10U)
16831 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
16832 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
16833 #define SPI_IFCR_SUSPC_Pos (11U)
16834 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
16835 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
16836
16837 /******************* Bit definition for SPI_TXDR register ********************/
16838 #define SPI_TXDR_TXDR_Pos (0U)
16839 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
16840 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
16841
16842 /******************* Bit definition for SPI_RXDR register ********************/
16843 #define SPI_RXDR_RXDR_Pos (0U)
16844 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
16845 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
16846
16847 /******************* Bit definition for SPI_CRCPOLY register ********************/
16848 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
16849 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
16850 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
16851
16852 /******************* Bit definition for SPI_TXCRC register ********************/
16853 #define SPI_TXCRC_TXCRC_Pos (0U)
16854 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
16855 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
16856
16857 /******************* Bit definition for SPI_RXCRC register ********************/
16858 #define SPI_RXCRC_RXCRC_Pos (0U)
16859 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
16860 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
16861
16862 /******************* Bit definition for SPI_UDRDR register ********************/
16863 #define SPI_UDRDR_UDRDR_Pos (0U)
16864 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
16865 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
16866
16867 /****************** Bit definition for SPI_I2SCFGR register *****************/
16868 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
16869 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
16870 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
16871 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
16872 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
16873 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
16874 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
16875 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
16876 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
16877 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
16878 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
16879 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
16880 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
16881 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
16882 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
16883 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
16884 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
16885 #define SPI_I2SCFGR_DATLEN_Pos (8U)
16886 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
16887 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
16888 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
16889 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
16890 #define SPI_I2SCFGR_CHLEN_Pos (10U)
16891 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
16892 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
16893 #define SPI_I2SCFGR_CKPOL_Pos (11U)
16894 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
16895 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
16896 #define SPI_I2SCFGR_FIXCH_Pos (12U)
16897 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
16898 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
16899 #define SPI_I2SCFGR_WSINV_Pos (13U)
16900 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
16901 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
16902 #define SPI_I2SCFGR_DATFMT_Pos (14U)
16903 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
16904 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
16905 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
16906 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
16907 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
16908 #define SPI_I2SCFGR_ODD_Pos (24U)
16909 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
16910 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
16911 #define SPI_I2SCFGR_MCKOE_Pos (25U)
16912 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
16913 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
16914
16915
16916
16917 /******************************************************************************/
16918 /* */
16919 /* SYSCFG */
16920 /* */
16921 /******************************************************************************/
16922
16923 /****************** Bit definition for SYSCFG_PMCR register ******************/
16924 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
16925 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
16926 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
16927 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
16928 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
16929 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
16930 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
16931 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
16932 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
16933 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
16934 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
16935 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
16936 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
16937 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
16938 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
16939 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
16940 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
16941 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
16942 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
16943 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
16944 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
16945 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
16946 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
16947 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
16948 #define SYSCFG_PMCR_PA0SO_Pos (24U)
16949 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
16950 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
16951 #define SYSCFG_PMCR_PA1SO_Pos (25U)
16952 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
16953 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
16954 #define SYSCFG_PMCR_PC2SO_Pos (26U)
16955 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
16956 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
16957 #define SYSCFG_PMCR_PC3SO_Pos (27U)
16958 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
16959 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
16960
16961 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
16962 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
16963 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
16964 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
16965 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
16966 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
16967 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
16968 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
16969 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
16970 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
16971 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
16972 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
16973 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
16974 /**
16975 * @brief EXTI0 configuration
16976 */
16977 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
16978 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
16979 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
16980 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
16981 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
16982 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
16983 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
16984 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
16985 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
16986 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
16987 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
16988
16989 /**
16990 * @brief EXTI1 configuration
16991 */
16992 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
16993 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
16994 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
16995 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
16996 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
16997 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
16998 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
16999 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
17000 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
17001 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
17002 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
17003 /**
17004 * @brief EXTI2 configuration
17005 */
17006 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
17007 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
17008 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
17009 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
17010 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
17011 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
17012 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
17013 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
17014 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
17015 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
17016 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
17017
17018 /**
17019 * @brief EXTI3 configuration
17020 */
17021 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
17022 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
17023 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
17024 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
17025 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
17026 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
17027 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
17028 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
17029 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
17030 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
17031 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
17032
17033 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
17034 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
17035 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
17036 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
17037 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
17038 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
17039 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
17040 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
17041 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
17042 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
17043 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
17044 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
17045 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
17046 /**
17047 * @brief EXTI4 configuration
17048 */
17049 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
17050 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
17051 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
17052 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
17053 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
17054 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
17055 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
17056 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
17057 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
17058 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
17059 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
17060 /**
17061 * @brief EXTI5 configuration
17062 */
17063 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
17064 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
17065 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
17066 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
17067 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
17068 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
17069 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
17070 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
17071 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
17072 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
17073 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
17074 /**
17075 * @brief EXTI6 configuration
17076 */
17077 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
17078 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
17079 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
17080 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
17081 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
17082 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
17083 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
17084 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
17085 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
17086 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
17087 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
17088
17089 /**
17090 * @brief EXTI7 configuration
17091 */
17092 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
17093 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
17094 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
17095 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
17096 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
17097 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
17098 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
17099 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
17100 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
17101 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
17102 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
17103
17104 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
17105 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
17106 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
17107 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
17108 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
17109 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
17110 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
17111 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
17112 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
17113 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
17114 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
17115 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
17116 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
17117
17118 /**
17119 * @brief EXTI8 configuration
17120 */
17121 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
17122 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
17123 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
17124 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
17125 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
17126 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
17127 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
17128 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
17129 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
17130 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
17131 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
17132
17133 /**
17134 * @brief EXTI9 configuration
17135 */
17136 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
17137 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
17138 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
17139 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
17140 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
17141 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
17142 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
17143 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
17144 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
17145 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
17146 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
17147
17148 /**
17149 * @brief EXTI10 configuration
17150 */
17151 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
17152 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
17153 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
17154 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
17155 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
17156 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
17157 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
17158 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
17159 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
17160 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
17161 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
17162
17163 /**
17164 * @brief EXTI11 configuration
17165 */
17166 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
17167 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
17168 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
17169 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
17170 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
17171 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
17172 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
17173 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
17174 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
17175 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
17176 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
17177
17178 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
17179 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
17180 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
17181 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
17182 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
17183 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
17184 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
17185 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
17186 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
17187 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
17188 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
17189 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
17190 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
17191 /**
17192 * @brief EXTI12 configuration
17193 */
17194 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
17195 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
17196 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
17197 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
17198 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
17199 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
17200 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
17201 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
17202 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
17203 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
17204 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
17205 /**
17206 * @brief EXTI13 configuration
17207 */
17208 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
17209 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
17210 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
17211 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
17212 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
17213 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
17214 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
17215 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
17216 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
17217 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
17218 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
17219 /**
17220 * @brief EXTI14 configuration
17221 */
17222 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
17223 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
17224 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
17225 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
17226 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
17227 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
17228 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
17229 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
17230 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
17231 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
17232 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
17233 /**
17234 * @brief EXTI15 configuration
17235 */
17236 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
17237 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
17238 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
17239 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
17240 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
17241 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
17242 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
17243 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
17244 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
17245 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
17246 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
17247
17248 /****************** Bit definition for SYSCFG_CFGR register ******************/
17249 #define SYSCFG_CFGR_PVDL_Pos (2U)
17250 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
17251 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
17252 #define SYSCFG_CFGR_FLASHL_Pos (3U)
17253 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
17254 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
17255 #define SYSCFG_CFGR_CM7L_Pos (6U)
17256 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
17257 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
17258 #define SYSCFG_CFGR_DTCML_Pos (13U)
17259 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
17260 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
17261 #define SYSCFG_CFGR_ITCML_Pos (14U)
17262 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
17263 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
17264 /****************** Bit definition for SYSCFG_CCCSR register ******************/
17265 #define SYSCFG_CCCSR_EN_Pos (0U)
17266 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
17267 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
17268 #define SYSCFG_CCCSR_CS_Pos (1U)
17269 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
17270 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
17271 #define SYSCFG_CCCSR_CS_MMC_Pos (3U)
17272 #define SYSCFG_CCCSR_CS_MMC_Msk (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos) /*!< 0x00000004 */
17273 #define SYSCFG_CCCSR_CS_MMC SYSCFG_CCCSR_CS_MMC_Msk /*!< I/O compensation cell code selection */
17274 #define SYSCFG_CCCSR_READY_Pos (8U)
17275 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
17276 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
17277 #define SYSCFG_CCCSR_HSLV0_Pos (16U)
17278 #define SYSCFG_CCCSR_HSLV0_Msk (0x1UL << SYSCFG_CCCSR_HSLV0_Pos) /*!< 0x00010000 */
17279 #define SYSCFG_CCCSR_HSLV0 SYSCFG_CCCSR_HSLV0_Msk /*!< High-speed at low-voltage */
17280 #define SYSCFG_CCCSR_HSLV1_Pos (17U)
17281 #define SYSCFG_CCCSR_HSLV1_Msk (0x1UL << SYSCFG_CCCSR_HSLV1_Pos) /*!< 0x00020000 */
17282 #define SYSCFG_CCCSR_HSLV1 SYSCFG_CCCSR_HSLV1_Msk /*!< High-speed at low-voltage */
17283 #define SYSCFG_CCCSR_HSLV2_Pos (18U)
17284 #define SYSCFG_CCCSR_HSLV2_Msk (0x1UL << SYSCFG_CCCSR_HSLV2_Pos) /*!< 0x00040000 */
17285 #define SYSCFG_CCCSR_HSLV2 SYSCFG_CCCSR_HSLV2_Msk /*!< High-speed at low-voltage */
17286 #define SYSCFG_CCCSR_HSLV3_Pos (19U)
17287 #define SYSCFG_CCCSR_HSLV3_Msk (0x1UL << SYSCFG_CCCSR_HSLV3_Pos) /*!< 0x00080000 */
17288 #define SYSCFG_CCCSR_HSLV3 SYSCFG_CCCSR_HSLV3_Msk /*!< High-speed at low-voltage */
17289 /****************** Bit definition for SYSCFG_CCVR register *******************/
17290 #define SYSCFG_CCVR_NCV_Pos (0U)
17291 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
17292 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
17293 #define SYSCFG_CCVR_PCV_Pos (4U)
17294 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
17295 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
17296
17297 /****************** Bit definition for SYSCFG_CCCR register *******************/
17298 #define SYSCFG_CCCR_NCC_Pos (0U)
17299 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
17300 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
17301 #define SYSCFG_CCCR_PCC_Pos (4U)
17302 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
17303 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
17304 #define SYSCFG_CCCR_NCC_MMC_Pos (8U)
17305 #define SYSCFG_CCCR_NCC_MMC_Msk (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos) /*!< 0x00000F00 */
17306 #define SYSCFG_CCCR_NCC_MMC SYSCFG_CCCR_NCC_MMC_Msk /*!< NMOS compensation code */
17307 #define SYSCFG_CCCR_PCC_MMC_Pos (12U)
17308 #define SYSCFG_CCCR_PCC_MMC_Msk (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos) /*!< 0x0000F000 */
17309 #define SYSCFG_CCCR_PCC_MMC SYSCFG_CCCR_PCC_MMC_Msk /*!< PMOS compensation code */
17310 /******************************************************************************/
17311 /* */
17312 /* Digital Temperature Sensor (DTS) */
17313 /* */
17314 /******************************************************************************/
17315
17316 /****************** Bit definition for DTS_CFGR1 register ******************/
17317 #define DTS_CFGR1_TS1_EN_Pos (0U)
17318 #define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
17319 #define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS Enable */
17320 #define DTS_CFGR1_TS1_START_Pos (4U)
17321 #define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
17322 #define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS */
17323 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
17324 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
17325 #define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
17326 #define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
17327 #define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
17328 #define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
17329 #define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
17330 #define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
17331 #define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
17332 #define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS */
17333 #define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
17334 #define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
17335 #define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
17336 #define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
17337 #define DTS_CFGR1_REFCLK_SEL_Pos (20U)
17338 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
17339 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */
17340 #define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
17341 #define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
17342 #define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */
17343 #define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
17344 #define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
17345 #define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
17346
17347 /****************** Bit definition for DTS_T0VALR1 register ******************/
17348 #define DTS_T0VALR1_TS1_FMT0_Pos (0U)
17349 #define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
17350 #define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS */
17351 #define DTS_T0VALR1_TS1_T0_Pos (16U)
17352 #define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
17353 #define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS */
17354
17355 /****************** Bit definition for DTS_RAMPVALR register ******************/
17356 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
17357 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
17358 #define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
17359
17360 /****************** Bit definition for DTS_ITR1 register ******************/
17361 #define DTS_ITR1_TS1_LITTHD_Pos (0U)
17362 #define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
17363 #define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS */
17364 #define DTS_ITR1_TS1_HITTHD_Pos (16U)
17365 #define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
17366 #define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS */
17367
17368 /****************** Bit definition for DTS_DR register ******************/
17369 #define DTS_DR_TS1_MFREQ_Pos (0U)
17370 #define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
17371 #define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS */
17372
17373 /****************** Bit definition for DTS_SR register ******************/
17374 #define DTS_SR_TS1_ITEF_Pos (0U)
17375 #define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
17376 #define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS */
17377 #define DTS_SR_TS1_ITLF_Pos (1U)
17378 #define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
17379 #define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS */
17380 #define DTS_SR_TS1_ITHF_Pos (2U)
17381 #define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
17382 #define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS */
17383 #define DTS_SR_TS1_AITEF_Pos (4U)
17384 #define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
17385 #define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS */
17386 #define DTS_SR_TS1_AITLF_Pos (5U)
17387 #define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
17388 #define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS */
17389 #define DTS_SR_TS1_AITHF_Pos (6U)
17390 #define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
17391 #define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS */
17392 #define DTS_SR_TS1_RDY_Pos (15U)
17393 #define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
17394 #define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS ready flag */
17395
17396 /****************** Bit definition for DTS_ITENR register ******************/
17397 #define DTS_ITENR_TS1_ITEEN_Pos (0U)
17398 #define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
17399 #define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS */
17400 #define DTS_ITENR_TS1_ITLEN_Pos (1U)
17401 #define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
17402 #define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS */
17403 #define DTS_ITENR_TS1_ITHEN_Pos (2U)
17404 #define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
17405 #define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS */
17406 #define DTS_ITENR_TS1_AITEEN_Pos (4U)
17407 #define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
17408 #define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS */
17409 #define DTS_ITENR_TS1_AITLEN_Pos (5U)
17410 #define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
17411 #define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS */
17412 #define DTS_ITENR_TS1_AITHEN_Pos (6U)
17413 #define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
17414 #define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS */
17415
17416 /****************** Bit definition for DTS_ICIFR register ******************/
17417 #define DTS_ICIFR_TS1_CITEF_Pos (0U)
17418 #define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
17419 #define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS */
17420 #define DTS_ICIFR_TS1_CITLF_Pos (1U)
17421 #define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
17422 #define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS */
17423 #define DTS_ICIFR_TS1_CITHF_Pos (2U)
17424 #define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
17425 #define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS */
17426 #define DTS_ICIFR_TS1_CAITEF_Pos (4U)
17427 #define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
17428 #define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
17429 #define DTS_ICIFR_TS1_CAITLF_Pos (5U)
17430 #define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
17431 #define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS */
17432 #define DTS_ICIFR_TS1_CAITHF_Pos (6U)
17433 #define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
17434 #define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS */
17435
17436
17437 /******************************************************************************/
17438 /* */
17439 /* TIM */
17440 /* */
17441 /******************************************************************************/
17442 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
17443
17444 /******************* Bit definition for TIM_CR1 register ********************/
17445 #define TIM_CR1_CEN_Pos (0U)
17446 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
17447 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
17448 #define TIM_CR1_UDIS_Pos (1U)
17449 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
17450 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
17451 #define TIM_CR1_URS_Pos (2U)
17452 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
17453 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
17454 #define TIM_CR1_OPM_Pos (3U)
17455 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
17456 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
17457 #define TIM_CR1_DIR_Pos (4U)
17458 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
17459 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
17460
17461 #define TIM_CR1_CMS_Pos (5U)
17462 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
17463 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
17464 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
17465 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
17466
17467 #define TIM_CR1_ARPE_Pos (7U)
17468 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
17469 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
17470
17471 #define TIM_CR1_CKD_Pos (8U)
17472 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
17473 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
17474 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
17475 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
17476
17477 #define TIM_CR1_UIFREMAP_Pos (11U)
17478 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
17479 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
17480
17481 /******************* Bit definition for TIM_CR2 register ********************/
17482 #define TIM_CR2_CCPC_Pos (0U)
17483 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
17484 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
17485 #define TIM_CR2_CCUS_Pos (2U)
17486 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
17487 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
17488 #define TIM_CR2_CCDS_Pos (3U)
17489 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
17490 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
17491
17492 #define TIM_CR2_MMS_Pos (4U)
17493 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
17494 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
17495 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
17496 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
17497 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
17498
17499 #define TIM_CR2_TI1S_Pos (7U)
17500 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
17501 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
17502 #define TIM_CR2_OIS1_Pos (8U)
17503 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
17504 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
17505 #define TIM_CR2_OIS1N_Pos (9U)
17506 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
17507 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
17508 #define TIM_CR2_OIS2_Pos (10U)
17509 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
17510 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
17511 #define TIM_CR2_OIS2N_Pos (11U)
17512 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
17513 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
17514 #define TIM_CR2_OIS3_Pos (12U)
17515 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
17516 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
17517 #define TIM_CR2_OIS3N_Pos (13U)
17518 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
17519 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
17520 #define TIM_CR2_OIS4_Pos (14U)
17521 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
17522 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
17523 #define TIM_CR2_OIS5_Pos (16U)
17524 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
17525 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
17526 #define TIM_CR2_OIS6_Pos (17U)
17527 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
17528 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
17529
17530 #define TIM_CR2_MMS2_Pos (20U)
17531 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
17532 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
17533 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
17534 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
17535 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
17536 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
17537
17538 /******************* Bit definition for TIM_SMCR register *******************/
17539 #define TIM_SMCR_SMS_Pos (0U)
17540 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
17541 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
17542 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
17543 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
17544 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
17545 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
17546
17547 #define TIM_SMCR_TS_Pos (4U)
17548 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
17549 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
17550 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
17551 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
17552 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
17553 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
17554 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
17555
17556 #define TIM_SMCR_MSM_Pos (7U)
17557 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
17558 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
17559
17560 #define TIM_SMCR_ETF_Pos (8U)
17561 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
17562 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
17563 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
17564 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
17565 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
17566 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
17567
17568 #define TIM_SMCR_ETPS_Pos (12U)
17569 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
17570 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
17571 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
17572 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
17573
17574 #define TIM_SMCR_ECE_Pos (14U)
17575 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
17576 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
17577 #define TIM_SMCR_ETP_Pos (15U)
17578 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
17579 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
17580
17581 /******************* Bit definition for TIM_DIER register *******************/
17582 #define TIM_DIER_UIE_Pos (0U)
17583 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
17584 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
17585 #define TIM_DIER_CC1IE_Pos (1U)
17586 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
17587 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
17588 #define TIM_DIER_CC2IE_Pos (2U)
17589 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
17590 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
17591 #define TIM_DIER_CC3IE_Pos (3U)
17592 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
17593 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
17594 #define TIM_DIER_CC4IE_Pos (4U)
17595 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
17596 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
17597 #define TIM_DIER_COMIE_Pos (5U)
17598 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
17599 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
17600 #define TIM_DIER_TIE_Pos (6U)
17601 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
17602 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
17603 #define TIM_DIER_BIE_Pos (7U)
17604 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
17605 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
17606 #define TIM_DIER_UDE_Pos (8U)
17607 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
17608 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
17609 #define TIM_DIER_CC1DE_Pos (9U)
17610 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
17611 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
17612 #define TIM_DIER_CC2DE_Pos (10U)
17613 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
17614 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
17615 #define TIM_DIER_CC3DE_Pos (11U)
17616 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
17617 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
17618 #define TIM_DIER_CC4DE_Pos (12U)
17619 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
17620 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
17621 #define TIM_DIER_COMDE_Pos (13U)
17622 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
17623 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
17624 #define TIM_DIER_TDE_Pos (14U)
17625 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
17626 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
17627
17628 /******************** Bit definition for TIM_SR register ********************/
17629 #define TIM_SR_UIF_Pos (0U)
17630 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
17631 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
17632 #define TIM_SR_CC1IF_Pos (1U)
17633 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
17634 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
17635 #define TIM_SR_CC2IF_Pos (2U)
17636 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
17637 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
17638 #define TIM_SR_CC3IF_Pos (3U)
17639 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
17640 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
17641 #define TIM_SR_CC4IF_Pos (4U)
17642 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
17643 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
17644 #define TIM_SR_COMIF_Pos (5U)
17645 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
17646 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
17647 #define TIM_SR_TIF_Pos (6U)
17648 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
17649 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
17650 #define TIM_SR_BIF_Pos (7U)
17651 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
17652 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
17653 #define TIM_SR_B2IF_Pos (8U)
17654 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
17655 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
17656 #define TIM_SR_CC1OF_Pos (9U)
17657 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
17658 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
17659 #define TIM_SR_CC2OF_Pos (10U)
17660 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
17661 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
17662 #define TIM_SR_CC3OF_Pos (11U)
17663 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
17664 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
17665 #define TIM_SR_CC4OF_Pos (12U)
17666 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
17667 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
17668 #define TIM_SR_CC5IF_Pos (16U)
17669 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
17670 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
17671 #define TIM_SR_CC6IF_Pos (17U)
17672 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
17673 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
17674 #define TIM_SR_SBIF_Pos (13U)
17675 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
17676 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
17677
17678 /******************* Bit definition for TIM_EGR register ********************/
17679 #define TIM_EGR_UG_Pos (0U)
17680 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
17681 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
17682 #define TIM_EGR_CC1G_Pos (1U)
17683 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
17684 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
17685 #define TIM_EGR_CC2G_Pos (2U)
17686 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
17687 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
17688 #define TIM_EGR_CC3G_Pos (3U)
17689 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
17690 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
17691 #define TIM_EGR_CC4G_Pos (4U)
17692 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
17693 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
17694 #define TIM_EGR_COMG_Pos (5U)
17695 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
17696 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
17697 #define TIM_EGR_TG_Pos (6U)
17698 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
17699 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
17700 #define TIM_EGR_BG_Pos (7U)
17701 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
17702 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
17703 #define TIM_EGR_B2G_Pos (8U)
17704 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
17705 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
17706
17707
17708 /****************** Bit definition for TIM_CCMR1 register *******************/
17709 #define TIM_CCMR1_CC1S_Pos (0U)
17710 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
17711 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
17712 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
17713 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
17714
17715 #define TIM_CCMR1_OC1FE_Pos (2U)
17716 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
17717 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
17718 #define TIM_CCMR1_OC1PE_Pos (3U)
17719 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
17720 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
17721
17722 #define TIM_CCMR1_OC1M_Pos (4U)
17723 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
17724 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
17725 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
17726 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
17727 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
17728 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
17729
17730 #define TIM_CCMR1_OC1CE_Pos (7U)
17731 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
17732 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
17733
17734 #define TIM_CCMR1_CC2S_Pos (8U)
17735 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
17736 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
17737 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
17738 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
17739
17740 #define TIM_CCMR1_OC2FE_Pos (10U)
17741 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
17742 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
17743 #define TIM_CCMR1_OC2PE_Pos (11U)
17744 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
17745 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
17746
17747 #define TIM_CCMR1_OC2M_Pos (12U)
17748 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
17749 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
17750 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
17751 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
17752 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
17753 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
17754
17755 #define TIM_CCMR1_OC2CE_Pos (15U)
17756 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
17757 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
17758
17759 /*----------------------------------------------------------------------------*/
17760
17761 #define TIM_CCMR1_IC1PSC_Pos (2U)
17762 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
17763 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
17764 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
17765 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
17766
17767 #define TIM_CCMR1_IC1F_Pos (4U)
17768 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
17769 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
17770 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
17771 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
17772 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
17773 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
17774
17775 #define TIM_CCMR1_IC2PSC_Pos (10U)
17776 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
17777 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
17778 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
17779 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
17780
17781 #define TIM_CCMR1_IC2F_Pos (12U)
17782 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
17783 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
17784 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
17785 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
17786 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
17787 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
17788
17789 /****************** Bit definition for TIM_CCMR2 register *******************/
17790 #define TIM_CCMR2_CC3S_Pos (0U)
17791 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
17792 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
17793 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
17794 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
17795
17796 #define TIM_CCMR2_OC3FE_Pos (2U)
17797 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
17798 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
17799 #define TIM_CCMR2_OC3PE_Pos (3U)
17800 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
17801 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
17802
17803 #define TIM_CCMR2_OC3M_Pos (4U)
17804 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
17805 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
17806 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
17807 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
17808 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
17809 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
17810
17811 #define TIM_CCMR2_OC3CE_Pos (7U)
17812 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
17813 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
17814
17815 #define TIM_CCMR2_CC4S_Pos (8U)
17816 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
17817 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
17818 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
17819 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
17820
17821 #define TIM_CCMR2_OC4FE_Pos (10U)
17822 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
17823 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
17824 #define TIM_CCMR2_OC4PE_Pos (11U)
17825 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
17826 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
17827
17828 #define TIM_CCMR2_OC4M_Pos (12U)
17829 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
17830 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
17831 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
17832 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
17833 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
17834 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
17835
17836 #define TIM_CCMR2_OC4CE_Pos (15U)
17837 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
17838 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
17839
17840 /*----------------------------------------------------------------------------*/
17841
17842 #define TIM_CCMR2_IC3PSC_Pos (2U)
17843 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
17844 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
17845 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
17846 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
17847
17848 #define TIM_CCMR2_IC3F_Pos (4U)
17849 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
17850 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
17851 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
17852 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
17853 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
17854 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
17855
17856 #define TIM_CCMR2_IC4PSC_Pos (10U)
17857 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
17858 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
17859 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
17860 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
17861
17862 #define TIM_CCMR2_IC4F_Pos (12U)
17863 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
17864 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
17865 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
17866 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
17867 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
17868 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
17869
17870 /******************* Bit definition for TIM_CCER register *******************/
17871 #define TIM_CCER_CC1E_Pos (0U)
17872 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
17873 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
17874 #define TIM_CCER_CC1P_Pos (1U)
17875 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
17876 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
17877 #define TIM_CCER_CC1NE_Pos (2U)
17878 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
17879 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
17880 #define TIM_CCER_CC1NP_Pos (3U)
17881 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
17882 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
17883 #define TIM_CCER_CC2E_Pos (4U)
17884 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
17885 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
17886 #define TIM_CCER_CC2P_Pos (5U)
17887 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
17888 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
17889 #define TIM_CCER_CC2NE_Pos (6U)
17890 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
17891 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
17892 #define TIM_CCER_CC2NP_Pos (7U)
17893 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
17894 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
17895 #define TIM_CCER_CC3E_Pos (8U)
17896 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
17897 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
17898 #define TIM_CCER_CC3P_Pos (9U)
17899 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
17900 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
17901 #define TIM_CCER_CC3NE_Pos (10U)
17902 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
17903 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
17904 #define TIM_CCER_CC3NP_Pos (11U)
17905 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
17906 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
17907 #define TIM_CCER_CC4E_Pos (12U)
17908 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
17909 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
17910 #define TIM_CCER_CC4P_Pos (13U)
17911 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
17912 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
17913 #define TIM_CCER_CC4NP_Pos (15U)
17914 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
17915 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
17916 #define TIM_CCER_CC5E_Pos (16U)
17917 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
17918 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
17919 #define TIM_CCER_CC5P_Pos (17U)
17920 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
17921 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
17922 #define TIM_CCER_CC6E_Pos (20U)
17923 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
17924 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
17925 #define TIM_CCER_CC6P_Pos (21U)
17926 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
17927 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
17928 /******************* Bit definition for TIM_CNT register ********************/
17929 #define TIM_CNT_CNT_Pos (0U)
17930 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
17931 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
17932 #define TIM_CNT_UIFCPY_Pos (31U)
17933 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
17934 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
17935 /******************* Bit definition for TIM_PSC register ********************/
17936 #define TIM_PSC_PSC_Pos (0U)
17937 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
17938 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
17939
17940 /******************* Bit definition for TIM_ARR register ********************/
17941 #define TIM_ARR_ARR_Pos (0U)
17942 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
17943 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
17944
17945 /******************* Bit definition for TIM_RCR register ********************/
17946 #define TIM_RCR_REP_Pos (0U)
17947 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
17948 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
17949
17950 /******************* Bit definition for TIM_CCR1 register *******************/
17951 #define TIM_CCR1_CCR1_Pos (0U)
17952 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
17953 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
17954
17955 /******************* Bit definition for TIM_CCR2 register *******************/
17956 #define TIM_CCR2_CCR2_Pos (0U)
17957 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
17958 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
17959
17960 /******************* Bit definition for TIM_CCR3 register *******************/
17961 #define TIM_CCR3_CCR3_Pos (0U)
17962 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
17963 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
17964
17965 /******************* Bit definition for TIM_CCR4 register *******************/
17966 #define TIM_CCR4_CCR4_Pos (0U)
17967 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
17968 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
17969
17970 /******************* Bit definition for TIM_CCR5 register *******************/
17971 #define TIM_CCR5_CCR5_Pos (0U)
17972 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
17973 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
17974 #define TIM_CCR5_GC5C1_Pos (29U)
17975 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
17976 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
17977 #define TIM_CCR5_GC5C2_Pos (30U)
17978 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
17979 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
17980 #define TIM_CCR5_GC5C3_Pos (31U)
17981 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
17982 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
17983
17984 /******************* Bit definition for TIM_CCR6 register *******************/
17985 #define TIM_CCR6_CCR6_Pos (0U)
17986 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
17987 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
17988
17989 /******************* Bit definition for TIM_BDTR register *******************/
17990 #define TIM_BDTR_DTG_Pos (0U)
17991 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
17992 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
17993 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
17994 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
17995 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
17996 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
17997 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
17998 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
17999 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
18000 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
18001
18002 #define TIM_BDTR_LOCK_Pos (8U)
18003 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
18004 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
18005 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
18006 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
18007
18008 #define TIM_BDTR_OSSI_Pos (10U)
18009 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
18010 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
18011 #define TIM_BDTR_OSSR_Pos (11U)
18012 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
18013 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
18014 #define TIM_BDTR_BKE_Pos (12U)
18015 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
18016 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
18017 #define TIM_BDTR_BKP_Pos (13U)
18018 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
18019 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
18020 #define TIM_BDTR_AOE_Pos (14U)
18021 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
18022 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
18023 #define TIM_BDTR_MOE_Pos (15U)
18024 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
18025 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
18026
18027 #define TIM_BDTR_BKF_Pos (16U)
18028 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
18029 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
18030 #define TIM_BDTR_BK2F_Pos (20U)
18031 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
18032 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
18033
18034 #define TIM_BDTR_BK2E_Pos (24U)
18035 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
18036 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
18037 #define TIM_BDTR_BK2P_Pos (25U)
18038 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
18039 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
18040
18041 /******************* Bit definition for TIM_DCR register ********************/
18042 #define TIM_DCR_DBA_Pos (0U)
18043 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
18044 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
18045 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
18046 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
18047 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
18048 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
18049 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
18050
18051 #define TIM_DCR_DBL_Pos (8U)
18052 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
18053 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
18054 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
18055 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
18056 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
18057 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
18058 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
18059
18060 /******************* Bit definition for TIM_DMAR register *******************/
18061 #define TIM_DMAR_DMAB_Pos (0U)
18062 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
18063 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
18064
18065 /****************** Bit definition for TIM_CCMR3 register *******************/
18066 #define TIM_CCMR3_OC5FE_Pos (2U)
18067 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
18068 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
18069 #define TIM_CCMR3_OC5PE_Pos (3U)
18070 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
18071 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
18072
18073 #define TIM_CCMR3_OC5M_Pos (4U)
18074 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
18075 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
18076 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
18077 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
18078 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
18079 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
18080
18081 #define TIM_CCMR3_OC5CE_Pos (7U)
18082 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
18083 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
18084
18085 #define TIM_CCMR3_OC6FE_Pos (10U)
18086 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
18087 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
18088 #define TIM_CCMR3_OC6PE_Pos (11U)
18089 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
18090 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
18091
18092 #define TIM_CCMR3_OC6M_Pos (12U)
18093 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
18094 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
18095 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
18096 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
18097 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
18098 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
18099
18100 #define TIM_CCMR3_OC6CE_Pos (15U)
18101 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
18102 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
18103 /******************* Bit definition for TIM1_AF1 register *********************/
18104 #define TIM1_AF1_BKINE_Pos (0U)
18105 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
18106 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18107 #define TIM1_AF1_BKCMP1E_Pos (1U)
18108 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18109 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18110 #define TIM1_AF1_BKCMP2E_Pos (2U)
18111 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18112 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18113 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
18114 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
18115 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
18116 #define TIM1_AF1_BKINP_Pos (9U)
18117 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
18118 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18119 #define TIM1_AF1_BKCMP1P_Pos (10U)
18120 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18121 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18122 #define TIM1_AF1_BKCMP2P_Pos (11U)
18123 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18124 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18125
18126 #define TIM1_AF1_ETRSEL_Pos (14U)
18127 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18128 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
18129 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18130 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18131 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18132 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18133
18134 /******************* Bit definition for TIM1_AF2 register *********************/
18135 #define TIM1_AF2_BK2INE_Pos (0U)
18136 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
18137 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
18138 #define TIM1_AF2_BK2CMP1E_Pos (1U)
18139 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
18140 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
18141 #define TIM1_AF2_BK2CMP2E_Pos (2U)
18142 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
18143 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
18144 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
18145 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
18146 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
18147 #define TIM1_AF2_BK2INP_Pos (9U)
18148 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
18149 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
18150 #define TIM1_AF2_BK2CMP1P_Pos (10U)
18151 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
18152 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
18153 #define TIM1_AF2_BK2CMP2P_Pos (11U)
18154 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
18155 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
18156
18157 /******************* Bit definition for TIM_TISEL register *********************/
18158 #define TIM_TISEL_TI1SEL_Pos (0U)
18159 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
18160 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
18161 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
18162 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
18163 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
18164 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
18165
18166 #define TIM_TISEL_TI2SEL_Pos (8U)
18167 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
18168 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
18169 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
18170 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
18171 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
18172 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
18173
18174 #define TIM_TISEL_TI3SEL_Pos (16U)
18175 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
18176 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
18177 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
18178 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
18179 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
18180 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
18181
18182 #define TIM_TISEL_TI4SEL_Pos (24U)
18183 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
18184 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
18185 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
18186 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
18187 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
18188 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
18189
18190 /******************* Bit definition for TIM8_AF1 register *********************/
18191 #define TIM8_AF1_BKINE_Pos (0U)
18192 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
18193 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18194 #define TIM8_AF1_BKCMP1E_Pos (1U)
18195 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18196 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18197 #define TIM8_AF1_BKCMP2E_Pos (2U)
18198 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18199 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18200 #define TIM8_AF1_BKDFBK2E_Pos (8U)
18201 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
18202 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
18203 #define TIM8_AF1_BKINP_Pos (9U)
18204 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
18205 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18206 #define TIM8_AF1_BKCMP1P_Pos (10U)
18207 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18208 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18209 #define TIM8_AF1_BKCMP2P_Pos (11U)
18210 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18211 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18212
18213 #define TIM8_AF1_ETRSEL_Pos (14U)
18214 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18215 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
18216 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18217 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18218 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18219 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18220 /******************* Bit definition for TIM8_AF2 register *********************/
18221 #define TIM8_AF2_BK2INE_Pos (0U)
18222 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
18223 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
18224 #define TIM8_AF2_BK2CMP1E_Pos (1U)
18225 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
18226 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
18227 #define TIM8_AF2_BK2CMP2E_Pos (2U)
18228 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
18229 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
18230 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
18231 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
18232 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
18233 #define TIM8_AF2_BK2INP_Pos (9U)
18234 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
18235 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
18236 #define TIM8_AF2_BK2CMP1P_Pos (10U)
18237 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
18238 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
18239 #define TIM8_AF2_BK2CMP2P_Pos (11U)
18240 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
18241 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
18242
18243 /******************* Bit definition for TIM2_AF1 register *********************/
18244 #define TIM2_AF1_ETRSEL_Pos (14U)
18245 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18246 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
18247 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18248 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18249 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18250 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18251
18252 /******************* Bit definition for TIM3_AF1 register *********************/
18253 #define TIM3_AF1_ETRSEL_Pos (14U)
18254 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18255 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
18256 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18257 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18258 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18259 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18260
18261 /******************* Bit definition for TIM5_AF1 register *********************/
18262 #define TIM5_AF1_ETRSEL_Pos (14U)
18263 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18264 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
18265 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18266 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18267 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18268 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18269
18270 /******************* Bit definition for TIM15_AF1 register *********************/
18271 #define TIM15_AF1_BKINE_Pos (0U)
18272 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
18273 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18274 #define TIM15_AF1_BKCMP1E_Pos (1U)
18275 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18276 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18277 #define TIM15_AF1_BKCMP2E_Pos (2U)
18278 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18279 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18280 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
18281 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18282 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
18283 #define TIM15_AF1_BKINP_Pos (9U)
18284 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
18285 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18286 #define TIM15_AF1_BKCMP1P_Pos (10U)
18287 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18288 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18289 #define TIM15_AF1_BKCMP2P_Pos (11U)
18290 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18291 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18292
18293 /******************* Bit definition for TIM16_ register *********************/
18294 #define TIM16_AF1_BKINE_Pos (0U)
18295 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
18296 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18297 #define TIM16_AF1_BKCMP1E_Pos (1U)
18298 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18299 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18300 #define TIM16_AF1_BKCMP2E_Pos (2U)
18301 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18302 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18303 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
18304 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18305 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
18306 #define TIM16_AF1_BKINP_Pos (9U)
18307 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
18308 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18309 #define TIM16_AF1_BKCMP1P_Pos (10U)
18310 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18311 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18312 #define TIM16_AF1_BKCMP2P_Pos (11U)
18313 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18314 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18315
18316 /******************* Bit definition for TIM17_AF1 register *********************/
18317 #define TIM17_AF1_BKINE_Pos (0U)
18318 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
18319 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18320 #define TIM17_AF1_BKCMP1E_Pos (1U)
18321 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18322 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18323 #define TIM17_AF1_BKCMP2E_Pos (2U)
18324 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18325 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18326 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
18327 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18328 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
18329 #define TIM17_AF1_BKINP_Pos (9U)
18330 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
18331 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18332 #define TIM17_AF1_BKCMP1P_Pos (10U)
18333 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18334 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18335 #define TIM17_AF1_BKCMP2P_Pos (11U)
18336 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18337 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18338
18339 /******************************************************************************/
18340 /* */
18341 /* Low Power Timer (LPTTIM) */
18342 /* */
18343 /******************************************************************************/
18344 /****************** Bit definition for LPTIM_ISR register *******************/
18345 #define LPTIM_ISR_CMPM_Pos (0U)
18346 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
18347 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
18348 #define LPTIM_ISR_ARRM_Pos (1U)
18349 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
18350 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
18351 #define LPTIM_ISR_EXTTRIG_Pos (2U)
18352 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
18353 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
18354 #define LPTIM_ISR_CMPOK_Pos (3U)
18355 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
18356 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
18357 #define LPTIM_ISR_ARROK_Pos (4U)
18358 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
18359 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
18360 #define LPTIM_ISR_UP_Pos (5U)
18361 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
18362 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
18363 #define LPTIM_ISR_DOWN_Pos (6U)
18364 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
18365 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
18366
18367 /****************** Bit definition for LPTIM_ICR register *******************/
18368 #define LPTIM_ICR_CMPMCF_Pos (0U)
18369 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
18370 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
18371 #define LPTIM_ICR_ARRMCF_Pos (1U)
18372 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
18373 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
18374 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
18375 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
18376 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
18377 #define LPTIM_ICR_CMPOKCF_Pos (3U)
18378 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
18379 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
18380 #define LPTIM_ICR_ARROKCF_Pos (4U)
18381 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
18382 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
18383 #define LPTIM_ICR_UPCF_Pos (5U)
18384 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
18385 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
18386 #define LPTIM_ICR_DOWNCF_Pos (6U)
18387 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
18388 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
18389
18390 /****************** Bit definition for LPTIM_IER register ********************/
18391 #define LPTIM_IER_CMPMIE_Pos (0U)
18392 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
18393 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
18394 #define LPTIM_IER_ARRMIE_Pos (1U)
18395 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
18396 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
18397 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
18398 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
18399 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
18400 #define LPTIM_IER_CMPOKIE_Pos (3U)
18401 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
18402 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
18403 #define LPTIM_IER_ARROKIE_Pos (4U)
18404 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
18405 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
18406 #define LPTIM_IER_UPIE_Pos (5U)
18407 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
18408 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
18409 #define LPTIM_IER_DOWNIE_Pos (6U)
18410 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
18411 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
18412
18413 /****************** Bit definition for LPTIM_CFGR register *******************/
18414 #define LPTIM_CFGR_CKSEL_Pos (0U)
18415 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
18416 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
18417
18418 #define LPTIM_CFGR_CKPOL_Pos (1U)
18419 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
18420 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
18421 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
18422 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
18423
18424 #define LPTIM_CFGR_CKFLT_Pos (3U)
18425 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
18426 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
18427 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
18428 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
18429
18430 #define LPTIM_CFGR_TRGFLT_Pos (6U)
18431 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
18432 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
18433 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
18434 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
18435
18436 #define LPTIM_CFGR_PRESC_Pos (9U)
18437 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
18438 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
18439 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
18440 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
18441 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
18442
18443 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
18444 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
18445 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
18446 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
18447 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
18448 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
18449
18450 #define LPTIM_CFGR_TRIGEN_Pos (17U)
18451 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
18452 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
18453 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
18454 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
18455
18456 #define LPTIM_CFGR_TIMOUT_Pos (19U)
18457 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
18458 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
18459 #define LPTIM_CFGR_WAVE_Pos (20U)
18460 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
18461 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
18462 #define LPTIM_CFGR_WAVPOL_Pos (21U)
18463 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
18464 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
18465 #define LPTIM_CFGR_PRELOAD_Pos (22U)
18466 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
18467 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
18468 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
18469 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
18470 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
18471 #define LPTIM_CFGR_ENC_Pos (24U)
18472 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
18473 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
18474
18475 /****************** Bit definition for LPTIM_CR register ********************/
18476 #define LPTIM_CR_ENABLE_Pos (0U)
18477 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
18478 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
18479 #define LPTIM_CR_SNGSTRT_Pos (1U)
18480 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
18481 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
18482 #define LPTIM_CR_CNTSTRT_Pos (2U)
18483 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
18484 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
18485 #define LPTIM_CR_COUNTRST_Pos (3U)
18486 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
18487 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
18488 #define LPTIM_CR_RSTARE_Pos (4U)
18489 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
18490 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
18491
18492
18493 /****************** Bit definition for LPTIM_CMP register *******************/
18494 #define LPTIM_CMP_CMP_Pos (0U)
18495 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
18496 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
18497
18498 /****************** Bit definition for LPTIM_ARR register *******************/
18499 #define LPTIM_ARR_ARR_Pos (0U)
18500 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
18501 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
18502
18503 /****************** Bit definition for LPTIM_CNT register *******************/
18504 #define LPTIM_CNT_CNT_Pos (0U)
18505 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
18506 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
18507
18508 /****************** Bit definition for LPTIM_CFGR2 register *****************/
18509 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
18510 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
18511 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
18512 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
18513 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
18514 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
18515 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
18516 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
18517 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
18518 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
18519
18520 /******************************************************************************/
18521 /* */
18522 /* OCTOSPI */
18523 /* */
18524 /******************************************************************************/
18525 /***************** Bit definition for OCTOSPI_CR register *******************/
18526 #define OCTOSPI_CR_EN_Pos (0U)
18527 #define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
18528 #define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
18529 #define OCTOSPI_CR_ABORT_Pos (1U)
18530 #define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
18531 #define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
18532 #define OCTOSPI_CR_DMAEN_Pos (2U)
18533 #define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
18534 #define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
18535 #define OCTOSPI_CR_TCEN_Pos (3U)
18536 #define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
18537 #define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
18538 #define OCTOSPI_CR_DQM_Pos (6U)
18539 #define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
18540 #define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
18541 #define OCTOSPI_CR_FSEL_Pos (7U)
18542 #define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
18543 #define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
18544 #define OCTOSPI_CR_FTHRES_Pos (8U)
18545 #define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
18546 #define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
18547 #define OCTOSPI_CR_TEIE_Pos (16U)
18548 #define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
18549 #define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
18550 #define OCTOSPI_CR_TCIE_Pos (17U)
18551 #define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
18552 #define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
18553 #define OCTOSPI_CR_FTIE_Pos (18U)
18554 #define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
18555 #define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
18556 #define OCTOSPI_CR_SMIE_Pos (19U)
18557 #define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
18558 #define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
18559 #define OCTOSPI_CR_TOIE_Pos (20U)
18560 #define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
18561 #define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
18562 #define OCTOSPI_CR_APMS_Pos (22U)
18563 #define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
18564 #define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
18565 #define OCTOSPI_CR_PMM_Pos (23U)
18566 #define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
18567 #define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
18568 #define OCTOSPI_CR_FMODE_Pos (28U)
18569 #define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
18570 #define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
18571 #define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
18572 #define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
18573
18574 /**************** Bit definition for OCTOSPI_DCR1 register ******************/
18575 #define OCTOSPI_DCR1_CKMODE_Pos (0U)
18576 #define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
18577 #define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
18578 #define OCTOSPI_DCR1_FRCK_Pos (1U)
18579 #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
18580 #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
18581 #define OCTOSPI_DCR1_DLYBYP_Pos (3U)
18582 #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
18583 #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
18584 #define OCTOSPI_DCR1_CKCSHT_Pos (4U)
18585 #define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
18586 #define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
18587 #define OCTOSPI_DCR1_CSHT_Pos (8U)
18588 #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
18589 #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
18590 #define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
18591 #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
18592 #define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
18593 #define OCTOSPI_DCR1_MTYP_Pos (24U)
18594 #define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
18595 #define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
18596 #define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
18597 #define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
18598 #define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
18599
18600 /**************** Bit definition for OCTOSPI_DCR2 register ******************/
18601 #define OCTOSPI_DCR2_PRESCALER_Pos (0U)
18602 #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
18603 #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
18604 #define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
18605 #define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
18606 #define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
18607 #define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
18608 #define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
18609 #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
18610
18611 /**************** Bit definition for OCTOSPI_DCR3 register ******************/
18612 #define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
18613 #define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
18614 #define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */
18615 #define OCTOSPI_DCR3_CSBOUND_Pos (16U)
18616 #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
18617 #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */
18618
18619 /**************** Bit definition for OCTOSPI_DCR4 register ******************/
18620 #define OCTOSPI_DCR4_REFRESH_Pos (0U)
18621 #define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
18622 #define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
18623
18624 /***************** Bit definition for OCTOSPI_SR register *******************/
18625 #define OCTOSPI_SR_TEF_Pos (0U)
18626 #define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
18627 #define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
18628 #define OCTOSPI_SR_TCF_Pos (1U)
18629 #define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
18630 #define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
18631 #define OCTOSPI_SR_FTF_Pos (2U)
18632 #define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
18633 #define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
18634 #define OCTOSPI_SR_SMF_Pos (3U)
18635 #define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
18636 #define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
18637 #define OCTOSPI_SR_TOF_Pos (4U)
18638 #define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
18639 #define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
18640 #define OCTOSPI_SR_BUSY_Pos (5U)
18641 #define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
18642 #define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
18643 #define OCTOSPI_SR_FLEVEL_Pos (8U)
18644 #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
18645 #define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
18646
18647 /**************** Bit definition for OCTOSPI_FCR register *******************/
18648 #define OCTOSPI_FCR_CTEF_Pos (0U)
18649 #define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
18650 #define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
18651 #define OCTOSPI_FCR_CTCF_Pos (1U)
18652 #define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
18653 #define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
18654 #define OCTOSPI_FCR_CSMF_Pos (3U)
18655 #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
18656 #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
18657 #define OCTOSPI_FCR_CTOF_Pos (4U)
18658 #define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
18659 #define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
18660
18661 /**************** Bit definition for OCTOSPI_DLR register *******************/
18662 #define OCTOSPI_DLR_DL_Pos (0U)
18663 #define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
18664 #define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
18665
18666 /***************** Bit definition for OCTOSPI_AR register *******************/
18667 #define OCTOSPI_AR_ADDRESS_Pos (0U)
18668 #define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
18669 #define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
18670
18671 /***************** Bit definition for OCTOSPI_DR register *******************/
18672 #define OCTOSPI_DR_DATA_Pos (0U)
18673 #define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
18674 #define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
18675
18676 /*************** Bit definition for OCTOSPI_PSMKR register ******************/
18677 #define OCTOSPI_PSMKR_MASK_Pos (0U)
18678 #define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
18679 #define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
18680
18681 /*************** Bit definition for OCTOSPI_PSMAR register ******************/
18682 #define OCTOSPI_PSMAR_MATCH_Pos (0U)
18683 #define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
18684 #define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
18685
18686 /**************** Bit definition for OCTOSPI_PIR register *******************/
18687 #define OCTOSPI_PIR_INTERVAL_Pos (0U)
18688 #define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
18689 #define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
18690
18691 /**************** Bit definition for OCTOSPI_CCR register *******************/
18692 #define OCTOSPI_CCR_IMODE_Pos (0U)
18693 #define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
18694 #define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
18695 #define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
18696 #define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
18697 #define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
18698 #define OCTOSPI_CCR_IDTR_Pos (3U)
18699 #define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
18700 #define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
18701 #define OCTOSPI_CCR_ISIZE_Pos (4U)
18702 #define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
18703 #define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
18704 #define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
18705 #define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
18706 #define OCTOSPI_CCR_ADMODE_Pos (8U)
18707 #define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
18708 #define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
18709 #define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
18710 #define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
18711 #define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
18712 #define OCTOSPI_CCR_ADDTR_Pos (11U)
18713 #define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
18714 #define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
18715 #define OCTOSPI_CCR_ADSIZE_Pos (12U)
18716 #define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
18717 #define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
18718 #define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
18719 #define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
18720 #define OCTOSPI_CCR_ABMODE_Pos (16U)
18721 #define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
18722 #define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
18723 #define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
18724 #define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
18725 #define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
18726 #define OCTOSPI_CCR_ABDTR_Pos (19U)
18727 #define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
18728 #define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
18729 #define OCTOSPI_CCR_ABSIZE_Pos (20U)
18730 #define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
18731 #define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
18732 #define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
18733 #define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
18734 #define OCTOSPI_CCR_DMODE_Pos (24U)
18735 #define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
18736 #define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
18737 #define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
18738 #define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
18739 #define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
18740 #define OCTOSPI_CCR_DDTR_Pos (27U)
18741 #define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
18742 #define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
18743 #define OCTOSPI_CCR_DQSE_Pos (29U)
18744 #define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
18745 #define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
18746 #define OCTOSPI_CCR_SIOO_Pos (31U)
18747 #define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
18748 #define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
18749
18750 /**************** Bit definition for OCTOSPI_TCR register *******************/
18751 #define OCTOSPI_TCR_DCYC_Pos (0U)
18752 #define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
18753 #define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
18754 #define OCTOSPI_TCR_DHQC_Pos (28U)
18755 #define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
18756 #define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
18757 #define OCTOSPI_TCR_SSHIFT_Pos (30U)
18758 #define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
18759 #define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
18760
18761 /***************** Bit definition for OCTOSPI_IR register *******************/
18762 #define OCTOSPI_IR_INSTRUCTION_Pos (0U)
18763 #define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
18764 #define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
18765
18766 /**************** Bit definition for OCTOSPI_ABR register *******************/
18767 #define OCTOSPI_ABR_ALTERNATE_Pos (0U)
18768 #define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
18769 #define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
18770
18771 /**************** Bit definition for OCTOSPI_LPTR register ******************/
18772 #define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
18773 #define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
18774 #define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
18775
18776 /**************** Bit definition for OCTOSPI_WPCCR register *******************/
18777 #define OCTOSPI_WPCCR_IMODE_Pos (0U)
18778 #define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
18779 #define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
18780 #define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
18781 #define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
18782 #define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
18783 #define OCTOSPI_WPCCR_IDTR_Pos (3U)
18784 #define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
18785 #define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
18786 #define OCTOSPI_WPCCR_ISIZE_Pos (4U)
18787 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
18788 #define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
18789 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
18790 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
18791 #define OCTOSPI_WPCCR_ADMODE_Pos (8U)
18792 #define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
18793 #define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
18794 #define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
18795 #define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
18796 #define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
18797 #define OCTOSPI_WPCCR_ADDTR_Pos (11U)
18798 #define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
18799 #define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
18800 #define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
18801 #define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
18802 #define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
18803 #define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
18804 #define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
18805 #define OCTOSPI_WPCCR_ABMODE_Pos (16U)
18806 #define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
18807 #define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
18808 #define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
18809 #define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
18810 #define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
18811 #define OCTOSPI_WPCCR_ABDTR_Pos (19U)
18812 #define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
18813 #define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
18814 #define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
18815 #define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
18816 #define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
18817 #define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
18818 #define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
18819 #define OCTOSPI_WPCCR_DMODE_Pos (24U)
18820 #define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
18821 #define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk /*!< Data Mode */
18822 #define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
18823 #define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
18824 #define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
18825 #define OCTOSPI_WPCCR_DDTR_Pos (27U)
18826 #define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
18827 #define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
18828 #define OCTOSPI_WPCCR_DQSE_Pos (29U)
18829 #define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
18830 #define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
18831 #define OCTOSPI_WPCCR_SIOO_Pos (31U)
18832 #define OCTOSPI_WPCCR_SIOO_Msk (0x1UL << OCTOSPI_WPCCR_SIOO_Pos) /*!< 0x80000000 */
18833 #define OCTOSPI_WPCCR_SIOO OCTOSPI_WPCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
18834
18835 /**************** Bit definition for OCTOSPI_WPTCR register *******************/
18836 #define OCTOSPI_WPTCR_DCYC_Pos (0U)
18837 #define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
18838 #define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
18839 #define OCTOSPI_WPTCR_DHQC_Pos (28U)
18840 #define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
18841 #define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
18842 #define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
18843 #define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
18844 #define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
18845
18846 /***************** Bit definition for OCTOSPI_WPIR register *******************/
18847 #define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
18848 #define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
18849 #define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
18850
18851 /**************** Bit definition for OCTOSPI_WPABR register *******************/
18852 #define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
18853 #define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
18854 #define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
18855
18856 /**************** Bit definition for OCTOSPI_WCCR register ******************/
18857 #define OCTOSPI_WCCR_IMODE_Pos (0U)
18858 #define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
18859 #define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
18860 #define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
18861 #define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
18862 #define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
18863 #define OCTOSPI_WCCR_IDTR_Pos (3U)
18864 #define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
18865 #define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
18866 #define OCTOSPI_WCCR_ISIZE_Pos (4U)
18867 #define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
18868 #define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
18869 #define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
18870 #define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
18871 #define OCTOSPI_WCCR_ADMODE_Pos (8U)
18872 #define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
18873 #define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
18874 #define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
18875 #define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
18876 #define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
18877 #define OCTOSPI_WCCR_ADDTR_Pos (11U)
18878 #define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
18879 #define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
18880 #define OCTOSPI_WCCR_ADSIZE_Pos (12U)
18881 #define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
18882 #define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
18883 #define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
18884 #define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
18885 #define OCTOSPI_WCCR_ABMODE_Pos (16U)
18886 #define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
18887 #define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
18888 #define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
18889 #define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
18890 #define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
18891 #define OCTOSPI_WCCR_ABDTR_Pos (19U)
18892 #define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
18893 #define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
18894 #define OCTOSPI_WCCR_ABSIZE_Pos (20U)
18895 #define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
18896 #define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
18897 #define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
18898 #define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
18899 #define OCTOSPI_WCCR_DMODE_Pos (24U)
18900 #define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
18901 #define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
18902 #define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
18903 #define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
18904 #define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
18905 #define OCTOSPI_WCCR_DDTR_Pos (27U)
18906 #define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
18907 #define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
18908 #define OCTOSPI_WCCR_DQSE_Pos (29U)
18909 #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
18910 #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
18911 #define OCTOSPI_WCCR_SIOO_Pos (31U)
18912 #define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */
18913 #define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
18914
18915 /**************** Bit definition for OCTOSPI_WTCR register ******************/
18916 #define OCTOSPI_WTCR_DCYC_Pos (0U)
18917 #define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
18918 #define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
18919
18920 /**************** Bit definition for OCTOSPI_WIR register *******************/
18921 #define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
18922 #define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
18923 #define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
18924
18925 /**************** Bit definition for OCTOSPI_WABR register ******************/
18926 #define OCTOSPI_WABR_ALTERNATE_Pos (0U)
18927 #define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
18928 #define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
18929
18930 /**************** Bit definition for OCTOSPI_HLCR register ******************/
18931 #define OCTOSPI_HLCR_LM_Pos (0U)
18932 #define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
18933 #define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
18934 #define OCTOSPI_HLCR_WZL_Pos (1U)
18935 #define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
18936 #define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
18937 #define OCTOSPI_HLCR_TACC_Pos (8U)
18938 #define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
18939 #define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
18940 #define OCTOSPI_HLCR_TRWR_Pos (16U)
18941 #define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
18942 #define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
18943
18944 /**************** Bit definition for OCTOSPI_VER register *******************/
18945 #define OCTOSPI_VER_VER_Pos (0U)
18946 #define OCTOSPI_VER_VER_Msk (0xFFUL << OCTOSPI_VER_VER_Pos) /*!< 0x000000FF */
18947 #define OCTOSPI_VER_VER OCTOSPI_VER_VER_Msk /*!< Version */
18948
18949 /***************** Bit definition for OCTOSPI_ID register *******************/
18950 #define OCTOSPI_ID_ID_Pos (0U)
18951 #define OCTOSPI_ID_ID_Msk (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos) /*!< 0xFFFFFFFF */
18952 #define OCTOSPI_ID_ID OCTOSPI_ID_ID_Msk /*!< Identification */
18953
18954 /**************** Bit definition for OCTOSPI_MID register *******************/
18955 #define OCTOSPI_MID_MID_Pos (0U)
18956 #define OCTOSPI_MID_MID_Msk (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos) /*!< 0xFFFFFFFF */
18957 #define OCTOSPI_MID_MID OCTOSPI_MID_MID_Msk /*!< Magic ID */
18958
18959 /******************************************************************************/
18960 /* */
18961 /* OCTOSPIM */
18962 /* */
18963 /******************************************************************************/
18964 /*************** Bit definition for OCTOSPIM_PCR register *******************/
18965 #define OCTOSPIM_PCR_CLKEN_Pos (0U)
18966 #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
18967 #define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
18968 #define OCTOSPIM_PCR_CLKSRC_Pos (1U)
18969 #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
18970 #define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
18971 #define OCTOSPIM_PCR_DQSEN_Pos (4U)
18972 #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
18973 #define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
18974 #define OCTOSPIM_PCR_DQSSRC_Pos (5U)
18975 #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
18976 #define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
18977 #define OCTOSPIM_PCR_NCSEN_Pos (8U)
18978 #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
18979 #define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
18980 #define OCTOSPIM_PCR_NCSSRC_Pos (9U)
18981 #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
18982 #define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
18983 #define OCTOSPIM_PCR_IOLEN_Pos (16U)
18984 #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
18985 #define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
18986 #define OCTOSPIM_PCR_IOLSRC_Pos (17U)
18987 #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
18988 #define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
18989 #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
18990 #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
18991 #define OCTOSPIM_PCR_IOHEN_Pos (24U)
18992 #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
18993 #define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
18994 #define OCTOSPIM_PCR_IOHSRC_Pos (25U)
18995 #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
18996 #define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
18997 #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
18998 #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
18999 /******************************************************************************/
19000 /* */
19001 /* Analog Comparators (COMP) */
19002 /* */
19003 /******************************************************************************/
19004
19005 /******************* Bit definition for COMP_SR register ********************/
19006 #define COMP_SR_C1VAL_Pos (0U)
19007 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
19008 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
19009 #define COMP_SR_C2VAL_Pos (1U)
19010 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
19011 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
19012 #define COMP_SR_C1IF_Pos (16U)
19013 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
19014 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
19015 #define COMP_SR_C2IF_Pos (17U)
19016 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
19017 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
19018 /******************* Bit definition for COMP_ICFR register ********************/
19019 #define COMP_ICFR_C1IF_Pos (16U)
19020 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
19021 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
19022 #define COMP_ICFR_C2IF_Pos (17U)
19023 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
19024 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
19025 /******************* Bit definition for COMP_OR register ********************/
19026 #define COMP_OR_AFOPA6_Pos (0U)
19027 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
19028 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
19029 #define COMP_OR_AFOPA8_Pos (1U)
19030 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
19031 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
19032 #define COMP_OR_AFOPB12_Pos (2U)
19033 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
19034 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
19035 #define COMP_OR_AFOPE6_Pos (3U)
19036 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
19037 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
19038 #define COMP_OR_AFOPE15_Pos (4U)
19039 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
19040 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
19041 #define COMP_OR_AFOPG2_Pos (5U)
19042 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
19043 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
19044 #define COMP_OR_AFOPG3_Pos (6U)
19045 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
19046 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
19047 #define COMP_OR_AFOPG4_Pos (7U)
19048 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
19049 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
19050 #define COMP_OR_AFOPI1_Pos (8U)
19051 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
19052 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
19053 #define COMP_OR_AFOPI4_Pos (9U)
19054 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
19055 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
19056 #define COMP_OR_AFOPK2_Pos (10U)
19057 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
19058 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
19059
19060 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
19061 #define COMP_CFGRx_EN_Pos (0U)
19062 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
19063 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
19064 #define COMP_CFGRx_BRGEN_Pos (1U)
19065 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
19066 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
19067 #define COMP_CFGRx_SCALEN_Pos (2U)
19068 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
19069 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
19070 #define COMP_CFGRx_POLARITY_Pos (3U)
19071 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
19072 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
19073 #define COMP_CFGRx_WINMODE_Pos (4U)
19074 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
19075 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
19076 #define COMP_CFGRx_ITEN_Pos (6U)
19077 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
19078 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
19079 #define COMP_CFGRx_HYST_Pos (8U)
19080 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
19081 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
19082 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
19083 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
19084 #define COMP_CFGRx_PWRMODE_Pos (12U)
19085 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
19086 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
19087 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
19088 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
19089 #define COMP_CFGRx_INMSEL_Pos (16U)
19090 #define COMP_CFGRx_INMSEL_Msk (0xFUL << COMP_CFGRx_INMSEL_Pos) /*!< 0x000F0000 */
19091 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
19092 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
19093 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
19094 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
19095 #define COMP_CFGRx_INMSEL_3 (0x8UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00080000 */
19096 #define COMP_CFGRx_INPSEL_Pos (20U)
19097 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
19098 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
19099 #define COMP_CFGRx_INP2SEL_Pos (22U)
19100 #define COMP_CFGRx_INP2SEL_Msk (0x1UL << COMP_CFGRx_INP2SEL_Pos) /*!< 0x00400000 */
19101 #define COMP_CFGRx_INP2SEL COMP_CFGRx_INP2SEL_Msk /*!< COMPx input plus 2 selection bit */
19102 #define COMP_CFGRx_BLANKING_Pos (24U)
19103 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
19104 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
19105 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
19106 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
19107 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
19108 #define COMP_CFGRx_LOCK_Pos (31U)
19109 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
19110 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
19111
19112
19113 /******************************************************************************/
19114 /* */
19115 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
19116 /* */
19117 /******************************************************************************/
19118 /****************** Bit definition for USART_CR1 register *******************/
19119 #define USART_CR1_UE_Pos (0U)
19120 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
19121 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
19122 #define USART_CR1_UESM_Pos (1U)
19123 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
19124 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
19125 #define USART_CR1_RE_Pos (2U)
19126 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
19127 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
19128 #define USART_CR1_TE_Pos (3U)
19129 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
19130 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
19131 #define USART_CR1_IDLEIE_Pos (4U)
19132 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
19133 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
19134 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
19135 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
19136 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
19137 #define USART_CR1_TCIE_Pos (6U)
19138 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
19139 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
19140 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
19141 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
19142 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
19143 #define USART_CR1_PEIE_Pos (8U)
19144 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
19145 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
19146 #define USART_CR1_PS_Pos (9U)
19147 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
19148 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
19149 #define USART_CR1_PCE_Pos (10U)
19150 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
19151 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
19152 #define USART_CR1_WAKE_Pos (11U)
19153 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
19154 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
19155 #define USART_CR1_M_Pos (12U)
19156 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
19157 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
19158 #define USART_CR1_M0_Pos (12U)
19159 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
19160 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
19161 #define USART_CR1_MME_Pos (13U)
19162 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
19163 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
19164 #define USART_CR1_CMIE_Pos (14U)
19165 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
19166 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
19167 #define USART_CR1_OVER8_Pos (15U)
19168 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
19169 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
19170 #define USART_CR1_DEDT_Pos (16U)
19171 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
19172 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
19173 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
19174 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
19175 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
19176 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
19177 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
19178 #define USART_CR1_DEAT_Pos (21U)
19179 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
19180 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
19181 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
19182 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
19183 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
19184 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
19185 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
19186 #define USART_CR1_RTOIE_Pos (26U)
19187 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
19188 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
19189 #define USART_CR1_EOBIE_Pos (27U)
19190 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
19191 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
19192 #define USART_CR1_M1_Pos (28U)
19193 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
19194 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
19195 #define USART_CR1_FIFOEN_Pos (29U)
19196 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
19197 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
19198 #define USART_CR1_TXFEIE_Pos (30U)
19199 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
19200 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
19201 #define USART_CR1_RXFFIE_Pos (31U)
19202 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
19203 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
19204
19205 /* Legacy define */
19206 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
19207 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
19208
19209 /****************** Bit definition for USART_CR2 register *******************/
19210 #define USART_CR2_SLVEN_Pos (0U)
19211 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
19212 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
19213 #define USART_CR2_DIS_NSS_Pos (3U)
19214 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
19215 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
19216 #define USART_CR2_ADDM7_Pos (4U)
19217 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
19218 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
19219 #define USART_CR2_LBDL_Pos (5U)
19220 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
19221 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
19222 #define USART_CR2_LBDIE_Pos (6U)
19223 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
19224 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
19225 #define USART_CR2_LBCL_Pos (8U)
19226 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
19227 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
19228 #define USART_CR2_CPHA_Pos (9U)
19229 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
19230 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
19231 #define USART_CR2_CPOL_Pos (10U)
19232 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
19233 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
19234 #define USART_CR2_CLKEN_Pos (11U)
19235 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
19236 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
19237 #define USART_CR2_STOP_Pos (12U)
19238 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
19239 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
19240 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
19241 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
19242 #define USART_CR2_LINEN_Pos (14U)
19243 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
19244 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
19245 #define USART_CR2_SWAP_Pos (15U)
19246 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
19247 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
19248 #define USART_CR2_RXINV_Pos (16U)
19249 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
19250 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
19251 #define USART_CR2_TXINV_Pos (17U)
19252 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
19253 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
19254 #define USART_CR2_DATAINV_Pos (18U)
19255 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
19256 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
19257 #define USART_CR2_MSBFIRST_Pos (19U)
19258 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
19259 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
19260 #define USART_CR2_ABREN_Pos (20U)
19261 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
19262 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
19263 #define USART_CR2_ABRMODE_Pos (21U)
19264 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
19265 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
19266 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
19267 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
19268 #define USART_CR2_RTOEN_Pos (23U)
19269 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
19270 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
19271 #define USART_CR2_ADD_Pos (24U)
19272 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
19273 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
19274
19275 /****************** Bit definition for USART_CR3 register *******************/
19276 #define USART_CR3_EIE_Pos (0U)
19277 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
19278 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
19279 #define USART_CR3_IREN_Pos (1U)
19280 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
19281 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
19282 #define USART_CR3_IRLP_Pos (2U)
19283 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
19284 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
19285 #define USART_CR3_HDSEL_Pos (3U)
19286 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
19287 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
19288 #define USART_CR3_NACK_Pos (4U)
19289 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
19290 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
19291 #define USART_CR3_SCEN_Pos (5U)
19292 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
19293 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
19294 #define USART_CR3_DMAR_Pos (6U)
19295 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
19296 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
19297 #define USART_CR3_DMAT_Pos (7U)
19298 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
19299 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
19300 #define USART_CR3_RTSE_Pos (8U)
19301 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
19302 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
19303 #define USART_CR3_CTSE_Pos (9U)
19304 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
19305 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
19306 #define USART_CR3_CTSIE_Pos (10U)
19307 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
19308 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
19309 #define USART_CR3_ONEBIT_Pos (11U)
19310 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
19311 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
19312 #define USART_CR3_OVRDIS_Pos (12U)
19313 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
19314 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
19315 #define USART_CR3_DDRE_Pos (13U)
19316 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
19317 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
19318 #define USART_CR3_DEM_Pos (14U)
19319 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
19320 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
19321 #define USART_CR3_DEP_Pos (15U)
19322 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
19323 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
19324 #define USART_CR3_SCARCNT_Pos (17U)
19325 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
19326 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
19327 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
19328 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
19329 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
19330 #define USART_CR3_WUS_Pos (20U)
19331 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
19332 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
19333 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
19334 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
19335 #define USART_CR3_WUFIE_Pos (22U)
19336 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
19337 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
19338 #define USART_CR3_TXFTIE_Pos (23U)
19339 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
19340 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
19341 #define USART_CR3_TCBGTIE_Pos (24U)
19342 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
19343 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
19344 #define USART_CR3_RXFTCFG_Pos (25U)
19345 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
19346 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
19347 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
19348 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
19349 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
19350 #define USART_CR3_RXFTIE_Pos (28U)
19351 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
19352 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
19353 #define USART_CR3_TXFTCFG_Pos (29U)
19354 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
19355 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
19356 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
19357 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
19358 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
19359
19360 /****************** Bit definition for USART_BRR register *******************/
19361 #define USART_BRR_DIV_FRACTION_Pos (0U)
19362 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
19363 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
19364 #define USART_BRR_DIV_MANTISSA_Pos (4U)
19365 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
19366 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
19367
19368 /****************** Bit definition for USART_GTPR register ******************/
19369 #define USART_GTPR_PSC_Pos (0U)
19370 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
19371 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
19372 #define USART_GTPR_GT_Pos (8U)
19373 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
19374 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
19375
19376 /******************* Bit definition for USART_RTOR register *****************/
19377 #define USART_RTOR_RTO_Pos (0U)
19378 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
19379 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
19380 #define USART_RTOR_BLEN_Pos (24U)
19381 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
19382 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
19383
19384 /******************* Bit definition for USART_RQR register ******************/
19385 #define USART_RQR_ABRRQ_Pos (0U)
19386 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
19387 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
19388 #define USART_RQR_SBKRQ_Pos (1U)
19389 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
19390 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
19391 #define USART_RQR_MMRQ_Pos (2U)
19392 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
19393 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
19394 #define USART_RQR_RXFRQ_Pos (3U)
19395 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
19396 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
19397 #define USART_RQR_TXFRQ_Pos (4U)
19398 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
19399 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
19400
19401 /******************* Bit definition for USART_ISR register ******************/
19402 #define USART_ISR_PE_Pos (0U)
19403 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
19404 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
19405 #define USART_ISR_FE_Pos (1U)
19406 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
19407 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
19408 #define USART_ISR_NE_Pos (2U)
19409 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
19410 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
19411 #define USART_ISR_ORE_Pos (3U)
19412 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
19413 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
19414 #define USART_ISR_IDLE_Pos (4U)
19415 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
19416 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
19417 #define USART_ISR_RXNE_RXFNE_Pos (5U)
19418 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
19419 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
19420 #define USART_ISR_TC_Pos (6U)
19421 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
19422 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
19423 #define USART_ISR_TXE_TXFNF_Pos (7U)
19424 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
19425 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
19426 #define USART_ISR_LBDF_Pos (8U)
19427 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
19428 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
19429 #define USART_ISR_CTSIF_Pos (9U)
19430 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
19431 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
19432 #define USART_ISR_CTS_Pos (10U)
19433 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
19434 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
19435 #define USART_ISR_RTOF_Pos (11U)
19436 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
19437 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
19438 #define USART_ISR_EOBF_Pos (12U)
19439 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
19440 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
19441 #define USART_ISR_UDR_Pos (13U)
19442 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
19443 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
19444 #define USART_ISR_ABRE_Pos (14U)
19445 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
19446 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
19447 #define USART_ISR_ABRF_Pos (15U)
19448 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
19449 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
19450 #define USART_ISR_BUSY_Pos (16U)
19451 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
19452 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
19453 #define USART_ISR_CMF_Pos (17U)
19454 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
19455 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
19456 #define USART_ISR_SBKF_Pos (18U)
19457 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
19458 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
19459 #define USART_ISR_RWU_Pos (19U)
19460 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
19461 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
19462 #define USART_ISR_WUF_Pos (20U)
19463 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
19464 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
19465 #define USART_ISR_TEACK_Pos (21U)
19466 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
19467 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
19468 #define USART_ISR_REACK_Pos (22U)
19469 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
19470 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
19471 #define USART_ISR_TXFE_Pos (23U)
19472 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
19473 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
19474 #define USART_ISR_RXFF_Pos (24U)
19475 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
19476 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
19477 #define USART_ISR_TCBGT_Pos (25U)
19478 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
19479 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
19480 #define USART_ISR_RXFT_Pos (26U)
19481 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
19482 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
19483 #define USART_ISR_TXFT_Pos (27U)
19484 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
19485 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
19486
19487 /******************* Bit definition for USART_ICR register ******************/
19488 #define USART_ICR_PECF_Pos (0U)
19489 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
19490 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
19491 #define USART_ICR_FECF_Pos (1U)
19492 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
19493 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
19494 #define USART_ICR_NECF_Pos (2U)
19495 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
19496 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
19497 #define USART_ICR_ORECF_Pos (3U)
19498 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
19499 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
19500 #define USART_ICR_IDLECF_Pos (4U)
19501 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
19502 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
19503 #define USART_ICR_TXFECF_Pos (5U)
19504 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
19505 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
19506 #define USART_ICR_TCCF_Pos (6U)
19507 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
19508 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
19509 #define USART_ICR_TCBGTCF_Pos (7U)
19510 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
19511 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
19512 #define USART_ICR_LBDCF_Pos (8U)
19513 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
19514 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
19515 #define USART_ICR_CTSCF_Pos (9U)
19516 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
19517 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
19518 #define USART_ICR_RTOCF_Pos (11U)
19519 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
19520 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
19521 #define USART_ICR_EOBCF_Pos (12U)
19522 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
19523 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
19524 #define USART_ICR_UDRCF_Pos (13U)
19525 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
19526 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
19527 #define USART_ICR_CMCF_Pos (17U)
19528 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
19529 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
19530 #define USART_ICR_WUCF_Pos (20U)
19531 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
19532 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
19533
19534 /******************* Bit definition for USART_RDR register ******************/
19535 #define USART_RDR_RDR_Pos (0U)
19536 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
19537 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
19538
19539 /******************* Bit definition for USART_TDR register ******************/
19540 #define USART_TDR_TDR_Pos (0U)
19541 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
19542 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
19543
19544 /******************* Bit definition for USART_PRESC register ******************/
19545 #define USART_PRESC_PRESCALER_Pos (0U)
19546 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
19547 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
19548 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
19549 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
19550 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
19551 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
19552
19553 /******************************************************************************/
19554 /* */
19555 /* Single Wire Protocol Master Interface (SWPMI) */
19556 /* */
19557 /******************************************************************************/
19558
19559 /******************* Bit definition for SWPMI_CR register ********************/
19560 #define SWPMI_CR_RXDMA_Pos (0U)
19561 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
19562 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
19563 #define SWPMI_CR_TXDMA_Pos (1U)
19564 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
19565 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
19566 #define SWPMI_CR_RXMODE_Pos (2U)
19567 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
19568 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
19569 #define SWPMI_CR_TXMODE_Pos (3U)
19570 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
19571 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
19572 #define SWPMI_CR_LPBK_Pos (4U)
19573 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
19574 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
19575 #define SWPMI_CR_SWPACT_Pos (5U)
19576 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
19577 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
19578 #define SWPMI_CR_DEACT_Pos (10U)
19579 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
19580 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
19581 #define SWPMI_CR_SWPEN_Pos (11U)
19582 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
19583 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
19584
19585 /******************* Bit definition for SWPMI_BRR register ********************/
19586 #define SWPMI_BRR_BR_Pos (0U)
19587 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
19588 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
19589
19590 /******************* Bit definition for SWPMI_ISR register ********************/
19591 #define SWPMI_ISR_RXBFF_Pos (0U)
19592 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
19593 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
19594 #define SWPMI_ISR_TXBEF_Pos (1U)
19595 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
19596 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
19597 #define SWPMI_ISR_RXBERF_Pos (2U)
19598 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
19599 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
19600 #define SWPMI_ISR_RXOVRF_Pos (3U)
19601 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
19602 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
19603 #define SWPMI_ISR_TXUNRF_Pos (4U)
19604 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
19605 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
19606 #define SWPMI_ISR_RXNE_Pos (5U)
19607 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
19608 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
19609 #define SWPMI_ISR_TXE_Pos (6U)
19610 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
19611 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
19612 #define SWPMI_ISR_TCF_Pos (7U)
19613 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
19614 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
19615 #define SWPMI_ISR_SRF_Pos (8U)
19616 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
19617 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
19618 #define SWPMI_ISR_SUSP_Pos (9U)
19619 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
19620 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
19621 #define SWPMI_ISR_DEACTF_Pos (10U)
19622 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
19623 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
19624 #define SWPMI_ISR_RDYF_Pos (11U)
19625 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
19626 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
19627
19628 /******************* Bit definition for SWPMI_ICR register ********************/
19629 #define SWPMI_ICR_CRXBFF_Pos (0U)
19630 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
19631 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
19632 #define SWPMI_ICR_CTXBEF_Pos (1U)
19633 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
19634 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
19635 #define SWPMI_ICR_CRXBERF_Pos (2U)
19636 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
19637 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
19638 #define SWPMI_ICR_CRXOVRF_Pos (3U)
19639 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
19640 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
19641 #define SWPMI_ICR_CTXUNRF_Pos (4U)
19642 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
19643 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
19644 #define SWPMI_ICR_CTCF_Pos (7U)
19645 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
19646 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
19647 #define SWPMI_ICR_CSRF_Pos (8U)
19648 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
19649 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
19650 #define SWPMI_ICR_CRDYF_Pos (11U)
19651 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
19652 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
19653
19654 /******************* Bit definition for SWPMI_IER register ********************/
19655 #define SWPMI_IER_RXBFIE_Pos (0U)
19656 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
19657 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
19658 #define SWPMI_IER_TXBEIE_Pos (1U)
19659 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
19660 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
19661 #define SWPMI_IER_RXBERIE_Pos (2U)
19662 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
19663 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
19664 #define SWPMI_IER_RXOVRIE_Pos (3U)
19665 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
19666 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
19667 #define SWPMI_IER_TXUNRIE_Pos (4U)
19668 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
19669 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
19670 #define SWPMI_IER_RIE_Pos (5U)
19671 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
19672 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
19673 #define SWPMI_IER_TIE_Pos (6U)
19674 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
19675 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
19676 #define SWPMI_IER_TCIE_Pos (7U)
19677 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
19678 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
19679 #define SWPMI_IER_SRIE_Pos (8U)
19680 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
19681 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
19682 #define SWPMI_IER_RDYIE_Pos (11U)
19683 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
19684 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
19685
19686 /******************* Bit definition for SWPMI_RFL register ********************/
19687 #define SWPMI_RFL_RFL_Pos (0U)
19688 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
19689 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
19690 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
19691
19692 /******************* Bit definition for SWPMI_TDR register ********************/
19693 #define SWPMI_TDR_TD_Pos (0U)
19694 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
19695 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
19696
19697 /******************* Bit definition for SWPMI_RDR register ********************/
19698 #define SWPMI_RDR_RD_Pos (0U)
19699 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
19700 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
19701
19702
19703 /******************* Bit definition for SWPMI_OR register ********************/
19704 #define SWPMI_OR_TBYP_Pos (0U)
19705 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
19706 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
19707 #define SWPMI_OR_CLASS_Pos (1U)
19708 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
19709 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
19710
19711 /******************************************************************************/
19712 /* */
19713 /* Window WATCHDOG */
19714 /* */
19715 /******************************************************************************/
19716 /******************* Bit definition for WWDG_CR register ********************/
19717 #define WWDG_CR_T_Pos (0U)
19718 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
19719 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
19720 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
19721 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
19722 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
19723 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
19724 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
19725 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
19726 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
19727
19728 #define WWDG_CR_WDGA_Pos (7U)
19729 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
19730 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
19731
19732 /******************* Bit definition for WWDG_CFR register *******************/
19733 #define WWDG_CFR_W_Pos (0U)
19734 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
19735 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
19736 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
19737 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
19738 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
19739 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
19740 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
19741 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
19742 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
19743
19744 #define WWDG_CFR_EWI_Pos (9U)
19745 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
19746 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
19747
19748 #define WWDG_CFR_WDGTB_Pos (11U)
19749 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
19750 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
19751 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
19752 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
19753 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
19754
19755 /******************* Bit definition for WWDG_SR register ********************/
19756 #define WWDG_SR_EWIF_Pos (0U)
19757 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
19758 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
19759
19760
19761 /******************************************************************************/
19762 /* */
19763 /* DBG */
19764 /* */
19765 /******************************************************************************/
19766
19767 /******************** Bit definition for DBGMCU_IDCODE register *************/
19768 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
19769 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
19770 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
19771 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
19772 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
19773 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
19774
19775 /******************** Bit definition for DBGMCU_CR register *****************/
19776 #define DBGMCU_CR_DBG_SLEEPCD_Pos (0U)
19777 #define DBGMCU_CR_DBG_SLEEPCD_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */
19778 #define DBGMCU_CR_DBG_SLEEPCD DBGMCU_CR_DBG_SLEEPCD_Msk
19779 #define DBGMCU_CR_DBG_STOPCD_Pos (1U)
19780 #define DBGMCU_CR_DBG_STOPCD_Msk (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos) /*!< 0x00000002 */
19781 #define DBGMCU_CR_DBG_STOPCD DBGMCU_CR_DBG_STOPCD_Msk
19782 #define DBGMCU_CR_DBG_STANDBYCD_Pos (2U)
19783 #define DBGMCU_CR_DBG_STANDBYCD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */
19784 #define DBGMCU_CR_DBG_STANDBYCD DBGMCU_CR_DBG_STANDBYCD_Msk
19785
19786 /* Legacy defines */
19787 #define DBGMCU_CR_DBG_SLEEPD1_Pos DBGMCU_CR_DBG_SLEEPCD_Pos
19788 #define DBGMCU_CR_DBG_SLEEPD1_Msk DBGMCU_CR_DBG_SLEEPCD_Msk
19789 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPCD
19790 #define DBGMCU_CR_DBG_STOPD1_Pos DBGMCU_CR_DBG_STOPCD_Pos
19791 #define DBGMCU_CR_DBG_STOPD1_Msk DBGMCU_CR_DBG_STOPCD_Msk
19792 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPCD
19793 #define DBGMCU_CR_DBG_STANDBYD1_Pos DBGMCU_CR_DBG_STANDBYCD_Pos
19794 #define DBGMCU_CR_DBG_STANDBYD1_Msk DBGMCU_CR_DBG_STANDBYCD_Msk
19795 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYCD
19796 #define DBGMCU_CR_DBG_STOPSRD_Pos (7U)
19797 #define DBGMCU_CR_DBG_STOPSRD_Msk (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos) /*!< 0x00000080 */
19798 #define DBGMCU_CR_DBG_STOPSRD DBGMCU_CR_DBG_STOPSRD_Msk
19799 #define DBGMCU_CR_DBG_STANDBYSRD_Pos (8U)
19800 #define DBGMCU_CR_DBG_STANDBYSRD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */
19801 #define DBGMCU_CR_DBG_STANDBYSRD DBGMCU_CR_DBG_STANDBYSRD_Msk
19802
19803 /* Legacy defines */
19804 #define DBGMCU_CR_DBG_STOPD3_Pos DBGMCU_CR_DBG_STOPSRD_Pos
19805 #define DBGMCU_CR_DBG_STOPD3_Msk DBGMCU_CR_DBG_STOPSRD_Msk
19806 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPSRD
19807 #define DBGMCU_CR_DBG_STANDBYD3_Pos DBGMCU_CR_DBG_STANDBYSRD_Pos
19808 #define DBGMCU_CR_DBG_STANDBYD3_Msk DBGMCU_CR_DBG_STANDBYSRD_Msk
19809 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYSRD
19810
19811 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
19812 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
19813 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
19814 #define DBGMCU_CR_DBG_CKCDEN_Pos (21U)
19815 #define DBGMCU_CR_DBG_CKCDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos) /*!< 0x00200000 */
19816 #define DBGMCU_CR_DBG_CKCDEN DBGMCU_CR_DBG_CKCDEN_Msk
19817 #define DBGMCU_CR_DBG_CKSRDEN_Pos (22U)
19818 #define DBGMCU_CR_DBG_CKSRDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos) /*!< 0x00400000 */
19819 #define DBGMCU_CR_DBG_CKSRDEN DBGMCU_CR_DBG_CKSRDEN_Msk
19820
19821 /* Legacy defines */
19822 #define DBGMCU_CR_DBG_CKD1EN_Pos DBGMCU_CR_DBG_CKCDEN_Pos
19823 #define DBGMCU_CR_DBG_CKD1EN_Msk DBGMCU_CR_DBG_CKCDEN_Msk
19824 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKCDEN
19825 #define DBGMCU_CR_DBG_CKD3EN_Pos DBGMCU_CR_DBG_CKSRDEN_Pos
19826 #define DBGMCU_CR_DBG_CKD3EN_Msk DBGMCU_CR_DBG_CKSRDEN_Msk
19827 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKSRDEN
19828
19829 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
19830 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
19831 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
19832
19833 /******************** Bit definition for APB3FZ1 register ************/
19834 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
19835 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
19836 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
19837 /******************** Bit definition for APB1LFZ1 register ************/
19838 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
19839 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
19840 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
19841 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
19842 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
19843 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
19844 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
19845 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
19846 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
19847 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
19848 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
19849 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
19850 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
19851 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
19852 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
19853 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
19854 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
19855 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
19856 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
19857 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
19858 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
19859 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
19860 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
19861 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
19862 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
19863 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
19864 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
19865 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
19866 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
19867 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
19868 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
19869 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
19870 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
19871 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
19872 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
19873 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
19874 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
19875 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
19876 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
19877
19878 /******************** Bit definition for APB2FZ1 register ************/
19879 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
19880 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
19881 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
19882 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
19883 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
19884 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
19885 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
19886 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
19887 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
19888 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
19889 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
19890 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
19891 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
19892 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
19893 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
19894 /******************** Bit definition for APB4FZ1 register ************/
19895 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
19896 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
19897 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
19898 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
19899 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
19900 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
19901 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
19902 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
19903 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
19904 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
19905 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
19906 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
19907 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
19908 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
19909 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
19910 /******************************************************************************/
19911 /* */
19912 /* RAM ECC monitoring */
19913 /* */
19914 /******************************************************************************/
19915 /****************** Bit definition for RAMECC_IER register ******************/
19916 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
19917 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
19918 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
19919 #define RAMECC_IER_GECCDEIE_Pos (2U)
19920 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
19921 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
19922 #define RAMECC_IER_GECCSEIE_Pos (1U)
19923 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
19924 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
19925 #define RAMECC_IER_GIE_Pos (0U)
19926 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
19927 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
19928
19929 /******************* Bit definition for RAMECC_CR register ******************/
19930 #define RAMECC_CR_ECCELEN_Pos (5U)
19931 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
19932 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
19933 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
19934 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
19935 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
19936 #define RAMECC_CR_ECCDEIE_Pos (3U)
19937 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
19938 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
19939 #define RAMECC_CR_ECCSEIE_Pos (2U)
19940 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
19941 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
19942
19943 /******************* Bit definition for RAMECC_SR register ******************/
19944 #define RAMECC_SR_DEBWDF_Pos (2U)
19945 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
19946 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
19947 #define RAMECC_SR_DEDF_Pos (1U)
19948 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
19949 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
19950 #define RAMECC_SR_SEDCF_Pos (0U)
19951 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
19952 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
19953
19954 /****************** Bit definition for RAMECC_FAR register ******************/
19955 #define RAMECC_FAR_FADD_Pos (0U)
19956 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
19957 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
19958
19959 /****************** Bit definition for RAMECC_FDRL register *****************/
19960 #define RAMECC_FAR_FDATAL_Pos (0U)
19961 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
19962 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
19963
19964 /****************** Bit definition for RAMECC_FDRH register *****************/
19965 #define RAMECC_FAR_FDATAH_Pos (0U)
19966 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
19967 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
19968
19969 /***************** Bit definition for RAMECC_FECR register ******************/
19970 #define RAMECC_FECR_FEC_Pos (0U)
19971 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
19972 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
19973
19974 /******************************************************************************/
19975 /* */
19976 /* MDIOS */
19977 /* */
19978 /******************************************************************************/
19979 /******************** Bit definition for MDIOS_CR register *******************/
19980 #define MDIOS_CR_EN_Pos (0U)
19981 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
19982 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
19983 #define MDIOS_CR_WRIE_Pos (1U)
19984 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
19985 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
19986 #define MDIOS_CR_RDIE_Pos (2U)
19987 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
19988 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
19989 #define MDIOS_CR_EIE_Pos (3U)
19990 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
19991 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
19992 #define MDIOS_CR_DPC_Pos (7U)
19993 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
19994 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
19995 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
19996 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
19997 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
19998 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
19999 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
20000 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
20001 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
20002 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
20003
20004 /******************** Bit definition for MDIOS_SR register *******************/
20005 #define MDIOS_SR_PERF_Pos (0U)
20006 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
20007 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
20008 #define MDIOS_SR_SERF_Pos (1U)
20009 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
20010 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
20011 #define MDIOS_SR_TERF_Pos (2U)
20012 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
20013 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
20014
20015 /******************** Bit definition for MDIOS_CLRFR register *******************/
20016 #define MDIOS_SR_CPERF_Pos (0U)
20017 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
20018 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
20019 #define MDIOS_SR_CSERF_Pos (1U)
20020 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
20021 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
20022 #define MDIOS_SR_CTERF_Pos (2U)
20023 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
20024 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
20025
20026 /******************************************************************************/
20027 /* */
20028 /* USB_OTG */
20029 /* */
20030 /******************************************************************************/
20031 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
20032 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
20033 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
20034 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
20035 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
20036 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
20037 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
20038 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
20039 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
20040 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
20041 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
20042 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
20043 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
20044 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
20045 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
20046 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
20047 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
20048 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
20049 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
20050 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
20051 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
20052 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
20053 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
20054 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
20055 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
20056 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
20057 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
20058 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
20059 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
20060 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
20061 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
20062 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
20063 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
20064 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
20065 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
20066 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
20067 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
20068 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
20069 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
20070 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
20071 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
20072 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
20073 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
20074 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
20075 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
20076 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
20077 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
20078 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
20079 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
20080 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
20081 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
20082 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
20083 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
20084 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
20085 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
20086
20087 /******************** Bit definition forUSB_OTG_HCFG register ********************/
20088
20089 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
20090 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
20091 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
20092 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
20093 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
20094 #define USB_OTG_HCFG_FSLSS_Pos (2U)
20095 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
20096 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
20097
20098 /******************** Bit definition forUSB_OTG_DCFG register ********************/
20099
20100 #define USB_OTG_DCFG_DSPD_Pos (0U)
20101 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
20102 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
20103 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
20104 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
20105 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
20106 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
20107 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
20108
20109 #define USB_OTG_DCFG_DAD_Pos (4U)
20110 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
20111 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
20112 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
20113 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
20114 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
20115 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
20116 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
20117 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
20118 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
20119
20120 #define USB_OTG_DCFG_PFIVL_Pos (11U)
20121 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
20122 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
20123 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
20124 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
20125
20126 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
20127 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
20128 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
20129 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
20130 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
20131
20132 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
20133 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
20134 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
20135 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
20136 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
20137 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
20138 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
20139 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
20140 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
20141 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
20142
20143 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
20144 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
20145 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
20146 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
20147 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
20148 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
20149 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
20150 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
20151 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
20152 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
20153 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
20154 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
20155 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
20156 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
20157 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
20158 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
20159 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
20160 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
20161 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
20162
20163 /******************** Bit definition forUSB_OTG_DCTL register ********************/
20164 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
20165 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
20166 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
20167 #define USB_OTG_DCTL_SDIS_Pos (1U)
20168 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
20169 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
20170 #define USB_OTG_DCTL_GINSTS_Pos (2U)
20171 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
20172 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
20173 #define USB_OTG_DCTL_GONSTS_Pos (3U)
20174 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
20175 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
20176
20177 #define USB_OTG_DCTL_TCTL_Pos (4U)
20178 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
20179 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
20180 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
20181 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
20182 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
20183 #define USB_OTG_DCTL_SGINAK_Pos (7U)
20184 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
20185 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
20186 #define USB_OTG_DCTL_CGINAK_Pos (8U)
20187 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
20188 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
20189 #define USB_OTG_DCTL_SGONAK_Pos (9U)
20190 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
20191 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
20192 #define USB_OTG_DCTL_CGONAK_Pos (10U)
20193 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
20194 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
20195 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
20196 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
20197 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
20198
20199 /******************** Bit definition forUSB_OTG_HFIR register ********************/
20200 #define USB_OTG_HFIR_FRIVL_Pos (0U)
20201 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
20202 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
20203
20204 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
20205 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
20206 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
20207 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
20208 #define USB_OTG_HFNUM_FTREM_Pos (16U)
20209 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
20210 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
20211
20212 /******************** Bit definition forUSB_OTG_DSTS register ********************/
20213 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
20214 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
20215 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
20216
20217 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
20218 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
20219 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
20220 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
20221 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
20222 #define USB_OTG_DSTS_EERR_Pos (3U)
20223 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
20224 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
20225 #define USB_OTG_DSTS_FNSOF_Pos (8U)
20226 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
20227 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
20228
20229 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
20230 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
20231 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
20232 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
20233
20234 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
20235 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
20236 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
20237 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
20238 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
20239 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
20240 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
20241 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
20242 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
20243 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
20244 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
20245 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
20246 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
20247 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
20248 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
20249 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
20250 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
20251
20252 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
20253
20254 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
20255 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
20256 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
20257 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
20258 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
20259 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
20260 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
20261 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
20262 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
20263 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
20264 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
20265 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
20266 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
20267 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
20268 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
20269
20270 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
20271 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
20272 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
20273 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
20274 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
20275 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
20276 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
20277 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
20278 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
20279 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
20280 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
20281 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
20282 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
20283 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
20284 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
20285 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
20286 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
20287 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
20288 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
20289 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
20290 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
20291 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
20292 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
20293 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
20294 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
20295 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
20296 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
20297 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
20298 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
20299 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
20300 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
20301 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
20302 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
20303 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
20304 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
20305 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
20306 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
20307 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
20308 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
20309 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
20310 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
20311 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
20312 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
20313 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
20314 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
20315 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
20316
20317 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
20318 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
20319 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
20320 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
20321 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
20322 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
20323 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
20324 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
20325 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
20326 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
20327 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
20328 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
20329 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
20330 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
20331 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
20332 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
20333
20334 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
20335 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
20336 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
20337 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
20338 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
20339 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
20340 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
20341 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
20342 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
20343 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
20344 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
20345 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
20346 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
20347 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
20348
20349 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
20350 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
20351 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
20352 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
20353 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
20354 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
20355 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20356 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
20357 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
20358 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
20359 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
20360 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
20361 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
20362 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
20363 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
20364 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
20365 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
20366 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
20367 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
20368 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
20369 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
20370 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
20371 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
20372 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
20373 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
20374
20375 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
20376 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
20377 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
20378 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
20379
20380 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
20381 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
20382 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
20383 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
20384 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
20385 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
20386 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
20387 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
20388 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
20389 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
20390 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
20391
20392 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
20393 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
20394 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
20395 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
20396 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
20397 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
20398 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
20399 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
20400 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
20401 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
20402 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
20403
20404 /******************** Bit definition forUSB_OTG_HAINT register ********************/
20405 #define USB_OTG_HAINT_HAINT_Pos (0U)
20406 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
20407 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
20408
20409 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
20410 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
20411 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
20412 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
20413 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
20414 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
20415 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20416 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
20417 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
20418 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
20419 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
20420 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
20421 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
20422 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
20423 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
20424 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
20425 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
20426 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
20427 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
20428 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
20429 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
20430 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
20431 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
20432 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
20433 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
20434 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
20435 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
20436 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
20437 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
20438 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
20439 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
20440 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
20441 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
20442 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
20443 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
20444 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
20445 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
20446
20447 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
20448 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
20449 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
20450 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
20451 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
20452 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
20453 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
20454 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
20455 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
20456 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
20457 #define USB_OTG_GINTSTS_SOF_Pos (3U)
20458 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
20459 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
20460 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
20461 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
20462 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
20463 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
20464 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
20465 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
20466 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
20467 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
20468 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
20469 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
20470 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
20471 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
20472 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
20473 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
20474 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
20475 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
20476 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
20477 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
20478 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
20479 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
20480 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
20481 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
20482 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
20483 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
20484 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
20485 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
20486 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
20487 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
20488 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
20489 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
20490 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
20491 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
20492 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
20493 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
20494 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
20495 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
20496 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
20497 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
20498 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
20499 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
20500 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
20501 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
20502 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
20503 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
20504 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
20505 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
20506 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
20507 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
20508 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
20509 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
20510 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
20511 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
20512 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
20513 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
20514 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
20515 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
20516 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
20517 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
20518 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
20519 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
20520 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
20521 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
20522 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
20523 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
20524 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
20525 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
20526 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
20527 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
20528 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
20529 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
20530 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
20531 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
20532
20533 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
20534 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
20535 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
20536 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
20537 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
20538 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
20539 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
20540 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
20541 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
20542 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
20543 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
20544 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
20545 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
20546 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
20547 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
20548 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
20549 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
20550 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
20551 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
20552 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
20553 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
20554 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
20555 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
20556 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
20557 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
20558 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
20559 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
20560 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
20561 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
20562 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
20563 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
20564 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
20565 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
20566 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
20567 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
20568 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
20569 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
20570 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
20571 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
20572 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
20573 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
20574 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
20575 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
20576 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
20577 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
20578 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
20579 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
20580 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
20581 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
20582 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
20583 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
20584 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
20585 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
20586 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
20587 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
20588 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
20589 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
20590 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
20591 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
20592 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
20593 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
20594 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
20595 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
20596 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
20597 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
20598 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
20599 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
20600 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
20601 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
20602 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
20603 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
20604 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
20605 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
20606 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
20607 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
20608 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
20609 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
20610 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
20611 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
20612 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
20613 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
20614 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
20615 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
20616 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
20617 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
20618
20619 /******************** Bit definition forUSB_OTG_DAINT register ********************/
20620 #define USB_OTG_DAINT_IEPINT_Pos (0U)
20621 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
20622 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
20623 #define USB_OTG_DAINT_OEPINT_Pos (16U)
20624 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
20625 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
20626
20627 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
20628 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
20629 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
20630 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
20631
20632 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
20633 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
20634 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
20635 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
20636 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
20637 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
20638 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
20639 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
20640 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
20641 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
20642 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
20643 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
20644 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
20645
20646 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
20647 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
20648 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
20649 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
20650 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
20651 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
20652 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
20653
20654 /******************** Bit definition for OTG register ********************/
20655
20656 #define USB_OTG_CHNUM_Pos (0U)
20657 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
20658 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
20659 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
20660 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
20661 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
20662 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
20663 #define USB_OTG_BCNT_Pos (4U)
20664 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
20665 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
20666
20667 #define USB_OTG_DPID_Pos (15U)
20668 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
20669 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
20670 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
20671 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
20672
20673 #define USB_OTG_PKTSTS_Pos (17U)
20674 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
20675 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
20676 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
20677 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
20678 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
20679 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
20680
20681 #define USB_OTG_EPNUM_Pos (0U)
20682 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
20683 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
20684 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
20685 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
20686 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
20687 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
20688
20689 #define USB_OTG_FRMNUM_Pos (21U)
20690 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
20691 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
20692 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
20693 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
20694 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
20695 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
20696
20697 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
20698 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
20699 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
20700 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
20701
20702 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
20703 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
20704 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
20705 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
20706
20707 /******************** Bit definition for OTG register ********************/
20708 #define USB_OTG_NPTXFSA_Pos (0U)
20709 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
20710 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
20711 #define USB_OTG_NPTXFD_Pos (16U)
20712 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
20713 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
20714 #define USB_OTG_TX0FSA_Pos (0U)
20715 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
20716 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
20717 #define USB_OTG_TX0FD_Pos (16U)
20718 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
20719 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
20720
20721 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
20722 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
20723 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
20724 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
20725
20726 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
20727 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
20728 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
20729 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
20730
20731 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
20732 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
20733 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
20734 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
20735 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
20736 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
20737 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
20738 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
20739 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
20740 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
20741 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
20742
20743 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
20744 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
20745 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
20746 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
20747 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
20748 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
20749 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
20750 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
20751 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
20752 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
20753
20754 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
20755 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
20756 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
20757 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
20758 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
20759 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
20760 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
20761
20762 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
20763 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
20764 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
20765 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
20766 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
20767 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
20768 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
20769 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
20770 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
20771 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
20772 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
20773 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
20774 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
20775 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
20776 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
20777
20778 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
20779 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
20780 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
20781 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
20782 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
20783 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
20784 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
20785 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
20786 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
20787 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
20788 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
20789 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
20790 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
20791 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
20792 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
20793
20794 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
20795 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
20796 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
20797 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
20798
20799 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
20800 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
20801 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
20802 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
20803 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
20804 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
20805 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
20806
20807 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
20808 #define USB_OTG_GCCFG_DCDET_Pos (0U)
20809 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
20810 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
20811 #define USB_OTG_GCCFG_PDET_Pos (1U)
20812 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
20813 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
20814 #define USB_OTG_GCCFG_SDET_Pos (2U)
20815 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
20816 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
20817 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
20818 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
20819 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
20820 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
20821 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
20822 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
20823 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
20824 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
20825 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
20826 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
20827 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
20828 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
20829 #define USB_OTG_GCCFG_PDEN_Pos (19U)
20830 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
20831 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
20832 #define USB_OTG_GCCFG_SDEN_Pos (20U)
20833 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
20834 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
20835 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
20836 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
20837 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
20838
20839 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
20840 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
20841 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
20842 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
20843 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
20844 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
20845 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
20846
20847 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
20848 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
20849 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
20850 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
20851 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
20852 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
20853 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
20854
20855 /******************** Bit definition forUSB_OTG_CID register ********************/
20856 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
20857 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
20858 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
20859
20860 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
20861 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
20862 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
20863 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
20864 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
20865 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
20866 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
20867 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
20868 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
20869 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
20870 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
20871 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
20872 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
20873 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
20874 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
20875 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
20876 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
20877 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
20878 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
20879 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
20880 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
20881 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
20882 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
20883 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
20884 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
20885 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
20886 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
20887 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
20888 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
20889 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
20890 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
20891 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
20892 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
20893 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
20894 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
20895 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
20896 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
20897 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
20898 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
20899 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
20900 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
20901 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
20902 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
20903 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
20904 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
20905 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
20906
20907 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
20908 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
20909 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
20910 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
20911 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
20912 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
20913 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20914 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
20915 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
20916 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
20917 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
20918 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
20919 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
20920 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
20921 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
20922 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
20923 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
20924 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
20925 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
20926 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
20927 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
20928 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
20929 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
20930 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
20931 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
20932 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
20933 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
20934 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
20935
20936 /******************** Bit definition forUSB_OTG_HPRT register ********************/
20937 #define USB_OTG_HPRT_PCSTS_Pos (0U)
20938 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
20939 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
20940 #define USB_OTG_HPRT_PCDET_Pos (1U)
20941 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
20942 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
20943 #define USB_OTG_HPRT_PENA_Pos (2U)
20944 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
20945 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
20946 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
20947 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
20948 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
20949 #define USB_OTG_HPRT_POCA_Pos (4U)
20950 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
20951 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
20952 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
20953 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
20954 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
20955 #define USB_OTG_HPRT_PRES_Pos (6U)
20956 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
20957 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
20958 #define USB_OTG_HPRT_PSUSP_Pos (7U)
20959 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
20960 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
20961 #define USB_OTG_HPRT_PRST_Pos (8U)
20962 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
20963 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
20964
20965 #define USB_OTG_HPRT_PLSTS_Pos (10U)
20966 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
20967 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
20968 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
20969 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
20970 #define USB_OTG_HPRT_PPWR_Pos (12U)
20971 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
20972 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
20973
20974 #define USB_OTG_HPRT_PTCTL_Pos (13U)
20975 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
20976 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
20977 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
20978 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
20979 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
20980 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
20981
20982 #define USB_OTG_HPRT_PSPD_Pos (17U)
20983 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
20984 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
20985 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
20986 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
20987
20988 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
20989 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
20990 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
20991 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
20992 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
20993 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
20994 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20995 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
20996 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
20997 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
20998 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
20999 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
21000 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
21001 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
21002 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
21003 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
21004 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
21005 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
21006 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
21007 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
21008 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
21009 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
21010 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
21011 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
21012 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
21013 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
21014 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
21015 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
21016 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
21017 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
21018 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
21019 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
21020 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
21021 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
21022
21023 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
21024 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
21025 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
21026 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
21027 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
21028 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
21029 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
21030
21031 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
21032 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
21033 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
21034 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
21035 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
21036 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
21037 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
21038 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
21039 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
21040 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
21041 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
21042 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
21043 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
21044
21045 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
21046 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
21047 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
21048 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
21049 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
21050 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
21051 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
21052 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
21053
21054 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
21055 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
21056 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
21057 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
21058 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
21059 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
21060 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
21061 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
21062 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
21063 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
21064 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
21065 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
21066 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
21067 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
21068 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
21069 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
21070 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
21071 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
21072 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
21073 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
21074 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
21075 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
21076 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
21077 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
21078 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
21079
21080 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
21081 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
21082 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
21083 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
21084
21085 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
21086 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
21087 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
21088 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
21089 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
21090 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
21091 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
21092 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
21093 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
21094 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
21095 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
21096 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
21097 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
21098
21099 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
21100 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
21101 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
21102 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
21103 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
21104
21105 #define USB_OTG_HCCHAR_MC_Pos (20U)
21106 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
21107 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
21108 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
21109 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
21110
21111 #define USB_OTG_HCCHAR_DAD_Pos (22U)
21112 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
21113 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
21114 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
21115 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
21116 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
21117 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
21118 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
21119 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
21120 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
21121 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
21122 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
21123 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
21124 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
21125 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
21126 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
21127 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
21128 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
21129 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
21130
21131 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
21132
21133 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
21134 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
21135 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
21136 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
21137 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
21138 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
21139 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
21140 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
21141 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
21142 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
21143
21144 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
21145 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
21146 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
21147 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
21148 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
21149 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
21150 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
21151 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
21152 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
21153 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
21154
21155 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
21156 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
21157 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
21158 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
21159 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
21160 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
21161 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
21162 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
21163 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
21164 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
21165 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
21166
21167 /******************** Bit definition forUSB_OTG_HCINT register ********************/
21168 #define USB_OTG_HCINT_XFRC_Pos (0U)
21169 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
21170 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
21171 #define USB_OTG_HCINT_CHH_Pos (1U)
21172 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
21173 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
21174 #define USB_OTG_HCINT_AHBERR_Pos (2U)
21175 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
21176 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
21177 #define USB_OTG_HCINT_STALL_Pos (3U)
21178 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
21179 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
21180 #define USB_OTG_HCINT_NAK_Pos (4U)
21181 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
21182 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
21183 #define USB_OTG_HCINT_ACK_Pos (5U)
21184 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
21185 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
21186 #define USB_OTG_HCINT_NYET_Pos (6U)
21187 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
21188 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
21189 #define USB_OTG_HCINT_TXERR_Pos (7U)
21190 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
21191 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
21192 #define USB_OTG_HCINT_BBERR_Pos (8U)
21193 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
21194 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
21195 #define USB_OTG_HCINT_FRMOR_Pos (9U)
21196 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
21197 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
21198 #define USB_OTG_HCINT_DTERR_Pos (10U)
21199 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
21200 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
21201
21202 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
21203 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
21204 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
21205 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
21206 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
21207 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
21208 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
21209 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
21210 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
21211 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
21212 #define USB_OTG_DIEPINT_TOC_Pos (3U)
21213 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
21214 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
21215 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
21216 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
21217 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
21218 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
21219 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
21220 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
21221 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
21222 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
21223 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
21224 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
21225 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
21226 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
21227 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
21228 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
21229 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
21230 #define USB_OTG_DIEPINT_BNA_Pos (9U)
21231 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
21232 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
21233 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
21234 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
21235 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
21236 #define USB_OTG_DIEPINT_BERR_Pos (12U)
21237 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
21238 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
21239 #define USB_OTG_DIEPINT_NAK_Pos (13U)
21240 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
21241 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
21242
21243 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
21244 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
21245 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
21246 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
21247 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
21248 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
21249 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
21250 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
21251 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
21252 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
21253 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
21254 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
21255 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
21256 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
21257 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
21258 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
21259 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
21260 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
21261 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
21262 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
21263 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
21264 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
21265 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
21266 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
21267 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
21268 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
21269 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
21270 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
21271 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
21272 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
21273 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
21274 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
21275 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
21276 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
21277
21278 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
21279
21280 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
21281 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21282 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
21283 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
21284 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21285 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
21286 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
21287 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
21288 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
21289 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
21290 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
21291 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21292 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
21293 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
21294 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21295 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
21296 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
21297 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
21298 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
21299 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
21300 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
21301 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
21302 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
21303 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
21304
21305 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
21306 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
21307 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
21308 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
21309
21310 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
21311 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
21312 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
21313 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
21314
21315 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
21316 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
21317 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
21318 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
21319
21320 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
21321 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
21322 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
21323 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
21324 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
21325 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
21326 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
21327
21328 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
21329
21330 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
21331 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
21332 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
21333 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
21334 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
21335 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
21336 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
21337 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
21338 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
21339 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
21340 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
21341 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
21342 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
21343 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
21344 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
21345 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
21346 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
21347 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
21348 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
21349 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
21350 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
21351 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
21352 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
21353 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
21354 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
21355 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
21356 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
21357 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
21358 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
21359 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
21360 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
21361 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
21362 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
21363 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
21364 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
21365 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
21366 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
21367 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
21368
21369 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
21370 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
21371 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
21372 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
21373 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
21374 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
21375 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
21376 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
21377 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
21378 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
21379 #define USB_OTG_DOEPINT_STUP_Pos (3U)
21380 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
21381 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
21382 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
21383 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
21384 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
21385 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
21386 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
21387 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
21388 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
21389 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
21390 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
21391 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
21392 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
21393 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
21394 #define USB_OTG_DOEPINT_BNA_Pos (9U)
21395 #define USB_OTG_DOEPINT_BNA_Msk (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */
21396 #define USB_OTG_DOEPINT_BNA USB_OTG_DOEPINT_BNA_Msk /*!< Buffer not available interrupt */
21397 #define USB_OTG_DOEPINT_BERR_Pos (12U)
21398 #define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
21399 #define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
21400 #define USB_OTG_DOEPINT_NAK_Pos (13U)
21401 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
21402 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
21403 #define USB_OTG_DOEPINT_NYET_Pos (14U)
21404 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
21405 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
21406 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
21407 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
21408 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
21409
21410 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
21411
21412 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
21413 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21414 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
21415 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
21416 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21417 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
21418
21419 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
21420 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
21421 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
21422 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
21423 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
21424
21425 /******************** Bit definition for PCGCCTL register ********************/
21426 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
21427 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
21428 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
21429 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
21430 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
21431 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
21432 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
21433 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
21434 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
21435
21436 /**
21437 * @}
21438 */
21439
21440 /**
21441 * @}
21442 */
21443
21444 /** @addtogroup Exported_macros
21445 * @{
21446 */
21447
21448 /******************************* ADC Instances ********************************/
21449 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
21450 ((INSTANCE) == ADC2))
21451
21452 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
21453
21454 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
21455
21456 /******************************** COMP Instances ******************************/
21457 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
21458 ((INSTANCE) == COMP2))
21459
21460 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
21461 /******************** COMP Instances with window mode capability **************/
21462 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
21463
21464 /******************************** DTS Instances ******************************/
21465 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
21466
21467 /******************************* CRC Instances ********************************/
21468 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
21469
21470 /******************************* DAC Instances ********************************/
21471 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \
21472 ((INSTANCE) == DAC2))
21473 /******************************* DCMI Instances *******************************/
21474 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
21475
21476 /******************************* DELAYBLOCK Instances *******************************/
21477 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
21478 ((INSTANCE) == DLYB_SDMMC2) || \
21479 ((INSTANCE) == DLYB_OCTOSPI1) || \
21480 ((INSTANCE) == DLYB_OCTOSPI2) )
21481 /****************************** DFSDM Instances *******************************/
21482 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
21483 ((INSTANCE) == DFSDM1_Filter1) || \
21484 ((INSTANCE) == DFSDM1_Filter2) || \
21485 ((INSTANCE) == DFSDM1_Filter3) || \
21486 ((INSTANCE) == DFSDM1_Filter4) || \
21487 ((INSTANCE) == DFSDM1_Filter5) || \
21488 ((INSTANCE) == DFSDM1_Filter6) || \
21489 ((INSTANCE) == DFSDM1_Filter7) || \
21490 ((INSTANCE) == DFSDM2_Filter0))
21491 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
21492 ((INSTANCE) == DFSDM1_Channel1) || \
21493 ((INSTANCE) == DFSDM1_Channel2) || \
21494 ((INSTANCE) == DFSDM1_Channel3) || \
21495 ((INSTANCE) == DFSDM1_Channel4) || \
21496 ((INSTANCE) == DFSDM1_Channel5) || \
21497 ((INSTANCE) == DFSDM1_Channel6) || \
21498 ((INSTANCE) == DFSDM1_Channel7) || \
21499 ((INSTANCE) == DFSDM2_Channel0) || \
21500 ((INSTANCE) == DFSDM2_Channel1))
21501 /****************************** RAMECC Instances ******************************/
21502 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1) || \
21503 ((INSTANCE) == RAMECC_Monitor2) || \
21504 ((INSTANCE) == RAMECC_Monitor3))
21505
21506 /******************************** DMA Instances *******************************/
21507 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
21508 ((INSTANCE) == DMA1_Stream1) || \
21509 ((INSTANCE) == DMA1_Stream2) || \
21510 ((INSTANCE) == DMA1_Stream3) || \
21511 ((INSTANCE) == DMA1_Stream4) || \
21512 ((INSTANCE) == DMA1_Stream5) || \
21513 ((INSTANCE) == DMA1_Stream6) || \
21514 ((INSTANCE) == DMA1_Stream7) || \
21515 ((INSTANCE) == DMA2_Stream0) || \
21516 ((INSTANCE) == DMA2_Stream1) || \
21517 ((INSTANCE) == DMA2_Stream2) || \
21518 ((INSTANCE) == DMA2_Stream3) || \
21519 ((INSTANCE) == DMA2_Stream4) || \
21520 ((INSTANCE) == DMA2_Stream5) || \
21521 ((INSTANCE) == DMA2_Stream6) || \
21522 ((INSTANCE) == DMA2_Stream7) || \
21523 ((INSTANCE) == BDMA1_Channel0) || \
21524 ((INSTANCE) == BDMA1_Channel1) || \
21525 ((INSTANCE) == BDMA1_Channel2) || \
21526 ((INSTANCE) == BDMA1_Channel3) || \
21527 ((INSTANCE) == BDMA1_Channel4) || \
21528 ((INSTANCE) == BDMA1_Channel5) || \
21529 ((INSTANCE) == BDMA1_Channel6) || \
21530 ((INSTANCE) == BDMA1_Channel7) || \
21531 ((INSTANCE) == BDMA2_Channel0) || \
21532 ((INSTANCE) == BDMA2_Channel1) || \
21533 ((INSTANCE) == BDMA2_Channel2) || \
21534 ((INSTANCE) == BDMA2_Channel3) || \
21535 ((INSTANCE) == BDMA2_Channel4) || \
21536 ((INSTANCE) == BDMA2_Channel5) || \
21537 ((INSTANCE) == BDMA2_Channel6) || \
21538 ((INSTANCE) == BDMA2_Channel7))
21539
21540 /****************************** BDMA CHANNEL Instances ***************************/
21541 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \
21542 ((INSTANCE) == BDMA1_Channel1) || \
21543 ((INSTANCE) == BDMA1_Channel2) || \
21544 ((INSTANCE) == BDMA1_Channel3) || \
21545 ((INSTANCE) == BDMA1_Channel4) || \
21546 ((INSTANCE) == BDMA1_Channel5) || \
21547 ((INSTANCE) == BDMA1_Channel6) || \
21548 ((INSTANCE) == BDMA1_Channel7) || \
21549 ((INSTANCE) == BDMA2_Channel0) || \
21550 ((INSTANCE) == BDMA2_Channel1) || \
21551 ((INSTANCE) == BDMA2_Channel2) || \
21552 ((INSTANCE) == BDMA2_Channel3) || \
21553 ((INSTANCE) == BDMA2_Channel4) || \
21554 ((INSTANCE) == BDMA2_Channel5) || \
21555 ((INSTANCE) == BDMA2_Channel6) || \
21556 ((INSTANCE) == BDMA2_Channel7))
21557
21558 /****************************** DMA DMAMUX ALL Instances ***************************/
21559 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
21560 ((INSTANCE) == DMA1_Stream1) || \
21561 ((INSTANCE) == DMA1_Stream2) || \
21562 ((INSTANCE) == DMA1_Stream3) || \
21563 ((INSTANCE) == DMA1_Stream4) || \
21564 ((INSTANCE) == DMA1_Stream5) || \
21565 ((INSTANCE) == DMA1_Stream6) || \
21566 ((INSTANCE) == DMA1_Stream7) || \
21567 ((INSTANCE) == DMA2_Stream0) || \
21568 ((INSTANCE) == DMA2_Stream1) || \
21569 ((INSTANCE) == DMA2_Stream2) || \
21570 ((INSTANCE) == DMA2_Stream3) || \
21571 ((INSTANCE) == DMA2_Stream4) || \
21572 ((INSTANCE) == DMA2_Stream5) || \
21573 ((INSTANCE) == DMA2_Stream6) || \
21574 ((INSTANCE) == DMA2_Stream7) || \
21575 ((INSTANCE) == BDMA2_Channel0) || \
21576 ((INSTANCE) == BDMA2_Channel1) || \
21577 ((INSTANCE) == BDMA2_Channel2) || \
21578 ((INSTANCE) == BDMA2_Channel3) || \
21579 ((INSTANCE) == BDMA2_Channel4) || \
21580 ((INSTANCE) == BDMA2_Channel5) || \
21581 ((INSTANCE) == BDMA2_Channel6) || \
21582 ((INSTANCE) == BDMA2_Channel7))
21583
21584 /****************************** BDMA DMAMUX Instances ***************************/
21585 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA2_Channel0) || \
21586 ((INSTANCE) == BDMA2_Channel1) || \
21587 ((INSTANCE) == BDMA2_Channel2) || \
21588 ((INSTANCE) == BDMA2_Channel3) || \
21589 ((INSTANCE) == BDMA2_Channel4) || \
21590 ((INSTANCE) == BDMA2_Channel5) || \
21591 ((INSTANCE) == BDMA2_Channel6) || \
21592 ((INSTANCE) == BDMA2_Channel7))
21593
21594 /****************************** DMA STREAM Instances ***************************/
21595 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
21596 ((INSTANCE) == DMA1_Stream1) || \
21597 ((INSTANCE) == DMA1_Stream2) || \
21598 ((INSTANCE) == DMA1_Stream3) || \
21599 ((INSTANCE) == DMA1_Stream4) || \
21600 ((INSTANCE) == DMA1_Stream5) || \
21601 ((INSTANCE) == DMA1_Stream6) || \
21602 ((INSTANCE) == DMA1_Stream7) || \
21603 ((INSTANCE) == DMA2_Stream0) || \
21604 ((INSTANCE) == DMA2_Stream1) || \
21605 ((INSTANCE) == DMA2_Stream2) || \
21606 ((INSTANCE) == DMA2_Stream3) || \
21607 ((INSTANCE) == DMA2_Stream4) || \
21608 ((INSTANCE) == DMA2_Stream5) || \
21609 ((INSTANCE) == DMA2_Stream6) || \
21610 ((INSTANCE) == DMA2_Stream7))
21611
21612 /****************************** DMA DMAMUX Instances ***************************/
21613 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
21614 ((INSTANCE) == DMA1_Stream1) || \
21615 ((INSTANCE) == DMA1_Stream2) || \
21616 ((INSTANCE) == DMA1_Stream3) || \
21617 ((INSTANCE) == DMA1_Stream4) || \
21618 ((INSTANCE) == DMA1_Stream5) || \
21619 ((INSTANCE) == DMA1_Stream6) || \
21620 ((INSTANCE) == DMA1_Stream7) || \
21621 ((INSTANCE) == DMA2_Stream0) || \
21622 ((INSTANCE) == DMA2_Stream1) || \
21623 ((INSTANCE) == DMA2_Stream2) || \
21624 ((INSTANCE) == DMA2_Stream3) || \
21625 ((INSTANCE) == DMA2_Stream4) || \
21626 ((INSTANCE) == DMA2_Stream5) || \
21627 ((INSTANCE) == DMA2_Stream6) || \
21628 ((INSTANCE) == DMA2_Stream7))
21629
21630 /******************************** DMA Request Generator Instances **************/
21631 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
21632 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
21633 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
21634 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
21635 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
21636 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
21637 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
21638 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
21639 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
21640 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
21641 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
21642 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
21643 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
21644 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
21645 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
21646 ((INSTANCE) == DMAMUX2_RequestGenerator7))
21647
21648 /******************************* DMA2D Instances *******************************/
21649 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
21650
21651 /****************************** PSSI Instance *********************************/
21652 #define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
21653
21654 /******************************** MDMA Request Generator Instances **************/
21655 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
21656 ((INSTANCE) == MDMA_Channel1) || \
21657 ((INSTANCE) == MDMA_Channel2) || \
21658 ((INSTANCE) == MDMA_Channel3) || \
21659 ((INSTANCE) == MDMA_Channel4) || \
21660 ((INSTANCE) == MDMA_Channel5) || \
21661 ((INSTANCE) == MDMA_Channel6) || \
21662 ((INSTANCE) == MDMA_Channel7) || \
21663 ((INSTANCE) == MDMA_Channel8) || \
21664 ((INSTANCE) == MDMA_Channel9) || \
21665 ((INSTANCE) == MDMA_Channel10) || \
21666 ((INSTANCE) == MDMA_Channel11) || \
21667 ((INSTANCE) == MDMA_Channel12) || \
21668 ((INSTANCE) == MDMA_Channel13) || \
21669 ((INSTANCE) == MDMA_Channel14) || \
21670 ((INSTANCE) == MDMA_Channel15))
21671
21672
21673 /******************************* FDCAN Instances ******************************/
21674 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
21675 ((__INSTANCE__) == FDCAN2))
21676
21677 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
21678
21679 /******************************* GFXMMU Instances *******************************/
21680 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)
21681
21682 /******************************* GPIO Instances *******************************/
21683 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
21684 ((INSTANCE) == GPIOB) || \
21685 ((INSTANCE) == GPIOC) || \
21686 ((INSTANCE) == GPIOD) || \
21687 ((INSTANCE) == GPIOE) || \
21688 ((INSTANCE) == GPIOF) || \
21689 ((INSTANCE) == GPIOG) || \
21690 ((INSTANCE) == GPIOH) || \
21691 ((INSTANCE) == GPIOI) || \
21692 ((INSTANCE) == GPIOJ) || \
21693 ((INSTANCE) == GPIOK))
21694
21695 /******************************* GPIO AF Instances ****************************/
21696 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
21697
21698 /**************************** GPIO Lock Instances *****************************/
21699 /* On H7, all GPIO Bank support the Lock mechanism */
21700 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
21701
21702 /******************************** HSEM Instances *******************************/
21703 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
21704 #define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */
21705 #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
21706 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
21707
21708 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
21709 #define HSEM_SEMID_MAX (15U) /* HSEM ID Max */
21710
21711 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
21712 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
21713
21714 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
21715 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
21716
21717 /******************************** I2C Instances *******************************/
21718 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
21719 ((INSTANCE) == I2C2) || \
21720 ((INSTANCE) == I2C3) || \
21721 ((INSTANCE) == I2C4))
21722 /************** I2C Instances : wakeup capability from stop modes *************/
21723 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
21724
21725 /****************************** SMBUS Instances *******************************/
21726 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
21727 ((INSTANCE) == I2C2) || \
21728 ((INSTANCE) == I2C3) || \
21729 ((INSTANCE) == I2C4))
21730 /******************************** I2S Instances *******************************/
21731 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
21732 ((INSTANCE) == SPI2) || \
21733 ((INSTANCE) == SPI3) || \
21734 ((INSTANCE) == SPI6))
21735
21736 /****************************** LTDC Instances ********************************/
21737 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
21738
21739 /******************************* RNG Instances ********************************/
21740 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
21741
21742 /****************************** RTC Instances *********************************/
21743 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
21744
21745 /****************************** SDMMC Instances *********************************/
21746 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
21747 ((_INSTANCE_) == SDMMC2))
21748
21749 /******************************** SMBUS Instances *****************************/
21750 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
21751
21752 /******************************** SPI Instances *******************************/
21753 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
21754 ((INSTANCE) == SPI2) || \
21755 ((INSTANCE) == SPI3) || \
21756 ((INSTANCE) == SPI4) || \
21757 ((INSTANCE) == SPI5) || \
21758 ((INSTANCE) == SPI6))
21759
21760 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
21761 ((INSTANCE) == SPI2) || \
21762 ((INSTANCE) == SPI3))
21763
21764 /******************************** SWPMI Instances *****************************/
21765 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
21766
21767 /****************** LPTIM Instances : All supported instances *****************/
21768 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
21769 ((INSTANCE) == LPTIM2) || \
21770 ((INSTANCE) == LPTIM3))
21771
21772 /****************** LPTIM Instances : supporting encoder interface **************/
21773 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
21774 ((INSTANCE) == LPTIM2))
21775
21776 /****************** TIM Instances : All supported instances *******************/
21777 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21778 ((INSTANCE) == TIM2) || \
21779 ((INSTANCE) == TIM3) || \
21780 ((INSTANCE) == TIM4) || \
21781 ((INSTANCE) == TIM5) || \
21782 ((INSTANCE) == TIM6) || \
21783 ((INSTANCE) == TIM7) || \
21784 ((INSTANCE) == TIM8) || \
21785 ((INSTANCE) == TIM12) || \
21786 ((INSTANCE) == TIM13) || \
21787 ((INSTANCE) == TIM14) || \
21788 ((INSTANCE) == TIM15) || \
21789 ((INSTANCE) == TIM16) || \
21790 ((INSTANCE) == TIM17))
21791
21792 /************* TIM Instances : at least 1 capture/compare channel *************/
21793 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21794 ((INSTANCE) == TIM2) || \
21795 ((INSTANCE) == TIM3) || \
21796 ((INSTANCE) == TIM4) || \
21797 ((INSTANCE) == TIM5) || \
21798 ((INSTANCE) == TIM8) || \
21799 ((INSTANCE) == TIM12) || \
21800 ((INSTANCE) == TIM13) || \
21801 ((INSTANCE) == TIM14) || \
21802 ((INSTANCE) == TIM15) || \
21803 ((INSTANCE) == TIM16) || \
21804 ((INSTANCE) == TIM17))
21805
21806 /************ TIM Instances : at least 2 capture/compare channels *************/
21807 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21808 ((INSTANCE) == TIM2) || \
21809 ((INSTANCE) == TIM3) || \
21810 ((INSTANCE) == TIM4) || \
21811 ((INSTANCE) == TIM5) || \
21812 ((INSTANCE) == TIM8) || \
21813 ((INSTANCE) == TIM12) || \
21814 ((INSTANCE) == TIM15))
21815
21816 /************ TIM Instances : at least 3 capture/compare channels *************/
21817 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21818 ((INSTANCE) == TIM2) || \
21819 ((INSTANCE) == TIM3) || \
21820 ((INSTANCE) == TIM4) || \
21821 ((INSTANCE) == TIM5) || \
21822 ((INSTANCE) == TIM8))
21823
21824 /************ TIM Instances : at least 4 capture/compare channels *************/
21825 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21826 ((INSTANCE) == TIM2) || \
21827 ((INSTANCE) == TIM3) || \
21828 ((INSTANCE) == TIM4) || \
21829 ((INSTANCE) == TIM5) || \
21830 ((INSTANCE) == TIM8))
21831
21832 /************ TIM Instances : at least 5 capture/compare channels *************/
21833 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21834 ((INSTANCE) == TIM8))
21835 /************ TIM Instances : at least 6 capture/compare channels *************/
21836 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21837 ((INSTANCE) == TIM8))
21838
21839 /******************** TIM Instances : Advanced-control timers *****************/
21840 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21841 ((__INSTANCE__) == TIM8))
21842
21843 /******************** TIM Instances : Advanced-control timers *****************/
21844
21845 /******************* TIM Instances : Timer input XOR function *****************/
21846 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21847 ((INSTANCE) == TIM2) || \
21848 ((INSTANCE) == TIM3) || \
21849 ((INSTANCE) == TIM4) || \
21850 ((INSTANCE) == TIM5) || \
21851 ((INSTANCE) == TIM8) || \
21852 ((INSTANCE) == TIM15))
21853
21854 /****************** TIM Instances : DMA requests generation (UDE) *************/
21855 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21856 ((INSTANCE) == TIM2) || \
21857 ((INSTANCE) == TIM3) || \
21858 ((INSTANCE) == TIM4) || \
21859 ((INSTANCE) == TIM5) || \
21860 ((INSTANCE) == TIM6) || \
21861 ((INSTANCE) == TIM7) || \
21862 ((INSTANCE) == TIM8) || \
21863 ((INSTANCE) == TIM15) || \
21864 ((INSTANCE) == TIM16) || \
21865 ((INSTANCE) == TIM17))
21866
21867 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
21868 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21869 ((INSTANCE) == TIM2) || \
21870 ((INSTANCE) == TIM3) || \
21871 ((INSTANCE) == TIM4) || \
21872 ((INSTANCE) == TIM5) || \
21873 ((INSTANCE) == TIM8) || \
21874 ((INSTANCE) == TIM15) || \
21875 ((INSTANCE) == TIM16) || \
21876 ((INSTANCE) == TIM17))
21877
21878 /************ TIM Instances : DMA requests generation (COMDE) *****************/
21879 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21880 ((INSTANCE) == TIM2) || \
21881 ((INSTANCE) == TIM3) || \
21882 ((INSTANCE) == TIM4) || \
21883 ((INSTANCE) == TIM5) || \
21884 ((INSTANCE) == TIM8) || \
21885 ((INSTANCE) == TIM15))
21886
21887 /******************** TIM Instances : DMA burst feature ***********************/
21888 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21889 ((INSTANCE) == TIM2) || \
21890 ((INSTANCE) == TIM3) || \
21891 ((INSTANCE) == TIM4) || \
21892 ((INSTANCE) == TIM5) || \
21893 ((INSTANCE) == TIM8))
21894
21895 /*************** TIM Instances : external trigger reamp input available *******/
21896 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21897 ((INSTANCE) == TIM2) || \
21898 ((INSTANCE) == TIM3) || \
21899 ((INSTANCE) == TIM4) || \
21900 ((INSTANCE) == TIM5) || \
21901 ((INSTANCE) == TIM8))
21902
21903 /****************** TIM Instances : remapping capability **********************/
21904 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21905 ((INSTANCE) == TIM2) || \
21906 ((INSTANCE) == TIM3) || \
21907 ((INSTANCE) == TIM5) || \
21908 ((INSTANCE) == TIM8) || \
21909 ((INSTANCE) == TIM16) || \
21910 ((INSTANCE) == TIM17))
21911
21912 /*************** TIM Instances : external trigger reamp input available *******/
21913 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21914 ((INSTANCE) == TIM2) || \
21915 ((INSTANCE) == TIM3) || \
21916 ((INSTANCE) == TIM5) || \
21917 ((INSTANCE) == TIM8))
21918
21919 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
21920 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21921 ((INSTANCE) == TIM2) || \
21922 ((INSTANCE) == TIM3) || \
21923 ((INSTANCE) == TIM4) || \
21924 ((INSTANCE) == TIM5) || \
21925 ((INSTANCE) == TIM6) || \
21926 ((INSTANCE) == TIM7) || \
21927 ((INSTANCE) == TIM8) || \
21928 ((INSTANCE) == TIM15))
21929
21930 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
21931 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21932 ((INSTANCE) == TIM2) || \
21933 ((INSTANCE) == TIM3) || \
21934 ((INSTANCE) == TIM4) || \
21935 ((INSTANCE) == TIM5) || \
21936 ((INSTANCE) == TIM8) || \
21937 ((INSTANCE) == TIM12))
21938
21939 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
21940 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21941 ((INSTANCE) == TIM8))
21942
21943 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
21944 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21945 ((INSTANCE) == TIM2) || \
21946 ((INSTANCE) == TIM3) || \
21947 ((INSTANCE) == TIM4) || \
21948 ((INSTANCE) == TIM5) || \
21949 ((INSTANCE) == TIM8) || \
21950 ((INSTANCE) == TIM15) || \
21951 ((INSTANCE) == TIM16) || \
21952 ((INSTANCE) == TIM17))
21953
21954 /****************** TIM Instances : supporting commutation event *************/
21955 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21956 ((INSTANCE) == TIM8) || \
21957 ((INSTANCE) == TIM15) || \
21958 ((INSTANCE) == TIM16) || \
21959 ((INSTANCE) == TIM17))
21960
21961 /****************** TIM Instances : supporting encoder interface **************/
21962 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
21963 ((__INSTANCE__) == TIM2) || \
21964 ((__INSTANCE__) == TIM3) || \
21965 ((__INSTANCE__) == TIM4) || \
21966 ((__INSTANCE__) == TIM5) || \
21967 ((__INSTANCE__) == TIM8))
21968
21969 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
21970 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
21971 ((INSTANCE) == TIM8))
21972 /******************* TIM Instances : output(s) available **********************/
21973 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
21974 ((((INSTANCE) == TIM1) && \
21975 (((CHANNEL) == TIM_CHANNEL_1) || \
21976 ((CHANNEL) == TIM_CHANNEL_2) || \
21977 ((CHANNEL) == TIM_CHANNEL_3) || \
21978 ((CHANNEL) == TIM_CHANNEL_4) || \
21979 ((CHANNEL) == TIM_CHANNEL_5) || \
21980 ((CHANNEL) == TIM_CHANNEL_6))) \
21981 || \
21982 (((INSTANCE) == TIM2) && \
21983 (((CHANNEL) == TIM_CHANNEL_1) || \
21984 ((CHANNEL) == TIM_CHANNEL_2) || \
21985 ((CHANNEL) == TIM_CHANNEL_3) || \
21986 ((CHANNEL) == TIM_CHANNEL_4))) \
21987 || \
21988 (((INSTANCE) == TIM3) && \
21989 (((CHANNEL) == TIM_CHANNEL_1)|| \
21990 ((CHANNEL) == TIM_CHANNEL_2) || \
21991 ((CHANNEL) == TIM_CHANNEL_3) || \
21992 ((CHANNEL) == TIM_CHANNEL_4))) \
21993 || \
21994 (((INSTANCE) == TIM4) && \
21995 (((CHANNEL) == TIM_CHANNEL_1) || \
21996 ((CHANNEL) == TIM_CHANNEL_2) || \
21997 ((CHANNEL) == TIM_CHANNEL_3) || \
21998 ((CHANNEL) == TIM_CHANNEL_4))) \
21999 || \
22000 (((INSTANCE) == TIM5) && \
22001 (((CHANNEL) == TIM_CHANNEL_1) || \
22002 ((CHANNEL) == TIM_CHANNEL_2) || \
22003 ((CHANNEL) == TIM_CHANNEL_3) || \
22004 ((CHANNEL) == TIM_CHANNEL_4))) \
22005 || \
22006 (((INSTANCE) == TIM8) && \
22007 (((CHANNEL) == TIM_CHANNEL_1) || \
22008 ((CHANNEL) == TIM_CHANNEL_2) || \
22009 ((CHANNEL) == TIM_CHANNEL_3) || \
22010 ((CHANNEL) == TIM_CHANNEL_4) || \
22011 ((CHANNEL) == TIM_CHANNEL_5) || \
22012 ((CHANNEL) == TIM_CHANNEL_6))) \
22013 || \
22014 (((INSTANCE) == TIM12) && \
22015 (((CHANNEL) == TIM_CHANNEL_1) || \
22016 ((CHANNEL) == TIM_CHANNEL_2))) \
22017 || \
22018 (((INSTANCE) == TIM13) && \
22019 (((CHANNEL) == TIM_CHANNEL_1))) \
22020 || \
22021 (((INSTANCE) == TIM14) && \
22022 (((CHANNEL) == TIM_CHANNEL_1))) \
22023 || \
22024 (((INSTANCE) == TIM15) && \
22025 (((CHANNEL) == TIM_CHANNEL_1) || \
22026 ((CHANNEL) == TIM_CHANNEL_2))) \
22027 || \
22028 (((INSTANCE) == TIM16) && \
22029 (((CHANNEL) == TIM_CHANNEL_1))) \
22030 || \
22031 (((INSTANCE) == TIM17) && \
22032 (((CHANNEL) == TIM_CHANNEL_1))))
22033
22034 /****************** TIM Instances : supporting the break function *************/
22035 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
22036 (((INSTANCE) == TIM1) || \
22037 ((INSTANCE) == TIM8) || \
22038 ((INSTANCE) == TIM15) || \
22039 ((INSTANCE) == TIM16) || \
22040 ((INSTANCE) == TIM17))
22041
22042 /************** TIM Instances : supporting Break source selection *************/
22043 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22044 ((INSTANCE) == TIM8))
22045
22046 /****************** TIM Instances : supporting complementary output(s) ********/
22047 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
22048 ((((INSTANCE) == TIM1) && \
22049 (((CHANNEL) == TIM_CHANNEL_1) || \
22050 ((CHANNEL) == TIM_CHANNEL_2) || \
22051 ((CHANNEL) == TIM_CHANNEL_3))) \
22052 || \
22053 (((INSTANCE) == TIM8) && \
22054 (((CHANNEL) == TIM_CHANNEL_1) || \
22055 ((CHANNEL) == TIM_CHANNEL_2) || \
22056 ((CHANNEL) == TIM_CHANNEL_3))) \
22057 || \
22058 (((INSTANCE) == TIM15) && \
22059 ((CHANNEL) == TIM_CHANNEL_1)) \
22060 || \
22061 (((INSTANCE) == TIM16) && \
22062 ((CHANNEL) == TIM_CHANNEL_1)) \
22063 || \
22064 (((INSTANCE) == TIM17) && \
22065 ((CHANNEL) == TIM_CHANNEL_1)))
22066
22067 /****************** TIM Instances : supporting counting mode selection ********/
22068 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
22069 (((INSTANCE) == TIM1) || \
22070 ((INSTANCE) == TIM2) || \
22071 ((INSTANCE) == TIM3) || \
22072 ((INSTANCE) == TIM4) || \
22073 ((INSTANCE) == TIM5) || \
22074 ((INSTANCE) == TIM8))
22075
22076 /****************** TIM Instances : supporting repetition counter *************/
22077 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
22078 (((INSTANCE) == TIM1) || \
22079 ((INSTANCE) == TIM8) || \
22080 ((INSTANCE) == TIM15) || \
22081 ((INSTANCE) == TIM16) || \
22082 ((INSTANCE) == TIM17))
22083
22084 /****************** TIM Instances : supporting synchronization ****************/
22085 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
22086 (((__INSTANCE__) == TIM1) || \
22087 ((__INSTANCE__) == TIM2) || \
22088 ((__INSTANCE__) == TIM3) || \
22089 ((__INSTANCE__) == TIM4) || \
22090 ((__INSTANCE__) == TIM5) || \
22091 ((__INSTANCE__) == TIM6) || \
22092 ((__INSTANCE__) == TIM8) || \
22093 ((__INSTANCE__) == TIM12) || \
22094 ((__INSTANCE__) == TIM15))
22095
22096 /****************** TIM Instances : supporting clock division *****************/
22097 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
22098 (((INSTANCE) == TIM1) || \
22099 ((INSTANCE) == TIM2) || \
22100 ((INSTANCE) == TIM3) || \
22101 ((INSTANCE) == TIM4) || \
22102 ((INSTANCE) == TIM5) || \
22103 ((INSTANCE) == TIM8) || \
22104 ((INSTANCE) == TIM15) || \
22105 ((INSTANCE) == TIM16) || \
22106 ((INSTANCE) == TIM17))
22107
22108 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
22109 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
22110 (((INSTANCE) == TIM1) || \
22111 ((INSTANCE) == TIM2) || \
22112 ((INSTANCE) == TIM3) || \
22113 ((INSTANCE) == TIM4) || \
22114 ((INSTANCE) == TIM5) || \
22115 ((INSTANCE) == TIM8))
22116
22117 /****************** TIM Instances : supporting external clock mode 2 **********/
22118 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
22119 (((INSTANCE) == TIM1) || \
22120 ((INSTANCE) == TIM2) || \
22121 ((INSTANCE) == TIM3) || \
22122 ((INSTANCE) == TIM4) || \
22123 ((INSTANCE) == TIM5) || \
22124 ((INSTANCE) == TIM8))
22125
22126 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
22127 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
22128 (((INSTANCE) == TIM1) || \
22129 ((INSTANCE) == TIM2) || \
22130 ((INSTANCE) == TIM3) || \
22131 ((INSTANCE) == TIM4) || \
22132 ((INSTANCE) == TIM5) || \
22133 ((INSTANCE) == TIM8) || \
22134 ((INSTANCE) == TIM15))
22135
22136 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
22137 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
22138 (((INSTANCE) == TIM1) || \
22139 ((INSTANCE) == TIM2) || \
22140 ((INSTANCE) == TIM3) || \
22141 ((INSTANCE) == TIM4) || \
22142 ((INSTANCE) == TIM5) || \
22143 ((INSTANCE) == TIM8) || \
22144 ((INSTANCE) == TIM15))
22145
22146 /****************** TIM Instances : supporting OCxREF clear *******************/
22147 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
22148 (((INSTANCE) == TIM1) || \
22149 ((INSTANCE) == TIM2) || \
22150 ((INSTANCE) == TIM3))
22151
22152 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
22153 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
22154 (((INSTANCE) == TIM2) || \
22155 ((INSTANCE) == TIM5))
22156
22157 /****************** TIM Instances : TIM_BKIN2 ***************************/
22158 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
22159 (((INSTANCE) == TIM1) || \
22160 ((INSTANCE) == TIM8))
22161
22162 /****************** TIM Instances : supporting Hall sensor interface **********/
22163 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22164 ((__INSTANCE__) == TIM2) || \
22165 ((__INSTANCE__) == TIM3) || \
22166 ((__INSTANCE__) == TIM4) || \
22167 ((__INSTANCE__) == TIM5) || \
22168 ((__INSTANCE__) == TIM15) || \
22169 ((__INSTANCE__) == TIM8))
22170
22171 /******************** USART Instances : Synchronous mode **********************/
22172 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22173 ((INSTANCE) == USART2) || \
22174 ((INSTANCE) == USART3) || \
22175 ((INSTANCE) == USART6) || \
22176 ((INSTANCE) == USART10))
22177
22178 /******************** USART Instances : SPI slave mode ************************/
22179 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22180 ((INSTANCE) == USART2) || \
22181 ((INSTANCE) == USART3) || \
22182 ((INSTANCE) == USART6) || \
22183 ((INSTANCE) == USART10))
22184
22185 /******************** UART Instances : Asynchronous mode **********************/
22186 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22187 ((INSTANCE) == USART2) || \
22188 ((INSTANCE) == USART3) || \
22189 ((INSTANCE) == UART4) || \
22190 ((INSTANCE) == UART5) || \
22191 ((INSTANCE) == USART6) || \
22192 ((INSTANCE) == UART7) || \
22193 ((INSTANCE) == UART8) || \
22194 ((INSTANCE) == UART9) || \
22195 ((INSTANCE) == USART10))
22196
22197 /******************** UART Instances : FIFO mode.******************************/
22198 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22199 ((INSTANCE) == USART2) || \
22200 ((INSTANCE) == USART3) || \
22201 ((INSTANCE) == UART4) || \
22202 ((INSTANCE) == UART5) || \
22203 ((INSTANCE) == USART6) || \
22204 ((INSTANCE) == UART7) || \
22205 ((INSTANCE) == UART8) || \
22206 ((INSTANCE) == UART9) || \
22207 ((INSTANCE) == USART10)|| \
22208 ((INSTANCE) == LPUART1))
22209
22210 /****************** UART Instances : Auto Baud Rate detection *****************/
22211 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22212 ((INSTANCE) == USART2) || \
22213 ((INSTANCE) == USART3) || \
22214 ((INSTANCE) == UART4) || \
22215 ((INSTANCE) == UART5) || \
22216 ((INSTANCE) == USART6) || \
22217 ((INSTANCE) == UART7) || \
22218 ((INSTANCE) == UART8) || \
22219 ((INSTANCE) == UART9) || \
22220 ((INSTANCE) == USART10))
22221
22222 /*********************** UART Instances : Driver Enable ***********************/
22223 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22224 ((INSTANCE) == USART2) || \
22225 ((INSTANCE) == USART3) || \
22226 ((INSTANCE) == UART4) || \
22227 ((INSTANCE) == UART5) || \
22228 ((INSTANCE) == USART6) || \
22229 ((INSTANCE) == UART7) || \
22230 ((INSTANCE) == UART8) || \
22231 ((INSTANCE) == UART9) || \
22232 ((INSTANCE) == USART10)|| \
22233 ((INSTANCE) == LPUART1))
22234
22235 /********************* UART Instances : Half-Duplex mode **********************/
22236 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22237 ((INSTANCE) == USART2) || \
22238 ((INSTANCE) == USART3) || \
22239 ((INSTANCE) == UART4) || \
22240 ((INSTANCE) == UART5) || \
22241 ((INSTANCE) == USART6) || \
22242 ((INSTANCE) == UART7) || \
22243 ((INSTANCE) == UART8) || \
22244 ((INSTANCE) == UART9) || \
22245 ((INSTANCE) == USART10)|| \
22246 ((INSTANCE) == LPUART1))
22247
22248 /******************* UART Instances : Hardware Flow control *******************/
22249 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22250 ((INSTANCE) == USART2) || \
22251 ((INSTANCE) == USART3) || \
22252 ((INSTANCE) == UART4) || \
22253 ((INSTANCE) == UART5) || \
22254 ((INSTANCE) == USART6) || \
22255 ((INSTANCE) == UART7) || \
22256 ((INSTANCE) == UART8) || \
22257 ((INSTANCE) == UART9) || \
22258 ((INSTANCE) == USART10)|| \
22259 ((INSTANCE) == LPUART1))
22260
22261 /************************* UART Instances : LIN mode **************************/
22262 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22263 ((INSTANCE) == USART2) || \
22264 ((INSTANCE) == USART3) || \
22265 ((INSTANCE) == UART4) || \
22266 ((INSTANCE) == UART5) || \
22267 ((INSTANCE) == USART6) || \
22268 ((INSTANCE) == UART7) || \
22269 ((INSTANCE) == UART8) || \
22270 ((INSTANCE) == UART9) || \
22271 ((INSTANCE) == USART10))
22272
22273 /****************** UART Instances : Wake-up from Stop mode *******************/
22274 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22275 ((INSTANCE) == USART2) || \
22276 ((INSTANCE) == USART3) || \
22277 ((INSTANCE) == UART4) || \
22278 ((INSTANCE) == UART5) || \
22279 ((INSTANCE) == USART6) || \
22280 ((INSTANCE) == UART7) || \
22281 ((INSTANCE) == UART8) || \
22282 ((INSTANCE) == UART9) || \
22283 ((INSTANCE) == USART10)|| \
22284 ((INSTANCE) == LPUART1))
22285
22286 /************************* UART Instances : IRDA mode *************************/
22287 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22288 ((INSTANCE) == USART2) || \
22289 ((INSTANCE) == USART3) || \
22290 ((INSTANCE) == UART4) || \
22291 ((INSTANCE) == UART5) || \
22292 ((INSTANCE) == USART6) || \
22293 ((INSTANCE) == UART7) || \
22294 ((INSTANCE) == UART8) || \
22295 ((INSTANCE) == UART9) || \
22296 ((INSTANCE) == USART10))
22297
22298 /********************* USART Instances : Smard card mode **********************/
22299 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22300 ((INSTANCE) == USART2) || \
22301 ((INSTANCE) == USART3) || \
22302 ((INSTANCE) == USART6) ||\
22303 ((INSTANCE) == USART10))
22304
22305 /****************************** LPUART Instance *******************************/
22306 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
22307
22308 /****************************** IWDG Instances ********************************/
22309 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
22310 /****************************** USB Instances ********************************/
22311 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
22312
22313 /****************************** WWDG Instances ********************************/
22314 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
22315 /****************************** MDIOS Instances ********************************/
22316 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
22317
22318 /****************************** CEC Instances *********************************/
22319 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
22320
22321 /****************************** SAI Instances ********************************/
22322 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
22323 ((INSTANCE) == SAI1_Block_B) || \
22324 ((INSTANCE) == SAI2_Block_A) || \
22325 ((INSTANCE) == SAI2_Block_B))
22326
22327 /****************************** SPDIFRX Instances ********************************/
22328 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
22329
22330 /****************************** OPAMP Instances *******************************/
22331 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
22332 ((INSTANCE) == OPAMP2))
22333
22334 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
22335
22336 /*********************** USB OTG PCD Instances ********************************/
22337 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22338
22339 /*********************** USB OTG HCD Instances ********************************/
22340 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22341
22342 /******************************************************************************/
22343 /* For a painless codes migration between the STM32H7xx device product */
22344 /* lines, or with STM32F7xx devices the aliases defined below are put */
22345 /* in place to overcome the differences in the interrupt handlers and IRQn */
22346 /* definitions. No need to update developed interrupt code when moving */
22347 /* across product lines within the same STM32H7 Family */
22348 /******************************************************************************/
22349
22350 /* Aliases for __IRQn */
22351 #define HASH_RNG_IRQn RNG_IRQn
22352 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
22353 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
22354 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
22355 #define PVD_IRQn PVD_AVD_IRQn
22356
22357 /* Aliases for BDMA __IRQn */
22358 #define BDMA_Channel0_IRQn BDMA2_Channel0_IRQn
22359 #define BDMA_Channel1_IRQn BDMA2_Channel1_IRQn
22360 #define BDMA_Channel2_IRQn BDMA2_Channel2_IRQn
22361 #define BDMA_Channel3_IRQn BDMA2_Channel3_IRQn
22362 #define BDMA_Channel4_IRQn BDMA2_Channel4_IRQn
22363 #define BDMA_Channel5_IRQn BDMA2_Channel5_IRQn
22364 #define BDMA_Channel6_IRQn BDMA2_Channel6_IRQn
22365 #define BDMA_Channel7_IRQn BDMA2_Channel7_IRQn
22366
22367 /* Aliases for PWR __IRQn */
22368 #define PVD_AVD_IRQn PVD_PVM_IRQn
22369
22370 /* Aliases for DCMI/PSSI __IRQn */
22371 #define DCMI_IRQn DCMI_PSSI_IRQn
22372
22373 /* Aliases for __IRQHandler */
22374 #define HASH_RNG_IRQHandler RNG_IRQHandler
22375 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
22376 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
22377 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
22378 #define PVD_IRQHandler PVD_AVD_IRQHandler
22379
22380
22381 /* Aliases for BDMA __IRQHandler */
22382 #define BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler
22383 #define BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler
22384 #define BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler
22385 #define BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler
22386 #define BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler
22387 #define BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler
22388 #define BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler
22389 #define BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler
22390
22391 /* Aliases for PWR __IRQHandler */
22392 #define PVD_AVD_IRQHandler PVD_PVM_IRQHandler
22393
22394 /* Aliases for DCMI/PSSI __IRQHandler */
22395 #define DCMI_IRQHandler DCMI_PSSI_IRQHandler
22396
22397 /* Alias for BDMA defines */
22398 #define BDMA_BASE BDMA2_BASE
22399 #define BDMA_Channel0_BASE BDMA2_Channel0_BASE
22400 #define BDMA_Channel1_BASE BDMA2_Channel1_BASE
22401 #define BDMA_Channel2_BASE BDMA2_Channel2_BASE
22402 #define BDMA_Channel3_BASE BDMA2_Channel3_BASE
22403 #define BDMA_Channel4_BASE BDMA2_Channel4_BASE
22404 #define BDMA_Channel5_BASE BDMA2_Channel5_BASE
22405 #define BDMA_Channel6_BASE BDMA2_Channel6_BASE
22406 #define BDMA_Channel7_BASE BDMA2_Channel7_BASE
22407
22408 #define BDMA BDMA2
22409 #define BDMA_Channel0 BDMA2_Channel0
22410 #define BDMA_Channel1 BDMA2_Channel1
22411 #define BDMA_Channel2 BDMA2_Channel2
22412 #define BDMA_Channel3 BDMA2_Channel3
22413 #define BDMA_Channel4 BDMA2_Channel4
22414 #define BDMA_Channel5 BDMA2_Channel5
22415 #define BDMA_Channel6 BDMA2_Channel6
22416 #define BDMA_Channel7 BDMA2_Channel7
22417
22418 /* Alias for PWR defines */
22419 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD
22420 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD
22421 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD
22422
22423 #define PWR_D3CR_VOS PWR_SRDCR_VOS
22424
22425 #define PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0
22426 #define PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1
22427 #define PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY
22428
22429 /**
22430 * @}
22431 */
22432
22433 /**
22434 * @}
22435 */
22436
22437 /**
22438 * @}
22439 */
22440
22441 #ifdef __cplusplus
22442 }
22443 #endif /* __cplusplus */
22444
22445 #endif /* STM32H7A3xxQ_H */
22446
22447 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software