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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / CMSIS / Device / ST / STM32H7xx / Include / stm32h7b0xxq.h
blob056f02fe5ba38c733e51c892be861fce9efc6bb9
1 /**
2 ******************************************************************************
3 * @file stm32h7b0xxQ.h
4 * @author MCD Application Team
5 * @brief CMSIS STM32H7B0xxQ Device Peripheral Access Layer Header File.
6 *
7 * This file contains:
8 * - Data structures and the address mapping for all peripherals
9 * - Peripheral's registers declarations and bits definition
10 * - Macros to access peripheral's registers hardware
11 *
12 ******************************************************************************
13 * @attention
14 *
15 * <h2><center>&copy; Copyright (c) 2019 STMicroelectronics.
16 * All rights reserved.</center></h2>
17 *
18 * This software component is licensed by ST under BSD 3-Clause license,
19 * the "License"; You may not use this file except in compliance with the
20 * License. You may obtain a copy of the License at:
21 * opensource.org/licenses/BSD-3-Clause
22 *
23 ******************************************************************************
24 */
25
26 /** @addtogroup CMSIS_Device
27 * @{
28 */
29
30 /** @addtogroup stm32h7b0xxQ
31 * @{
32 */
33
34 #ifndef STM32H7B0xxQ_H
35 #define STM32H7B0xxQ_H
36
37 #ifdef __cplusplus
38 extern "C" {
39 #endif /* __cplusplus */
40
41 /** @addtogroup Peripheral_interrupt_number_definition
42 * @{
43 */
44
45 /**
46 * @brief STM32H7XX Interrupt Number Definition, according to the selected device
47 * in @ref Library_configuration_section
48 */
49 typedef enum
50 {
51 /****** Cortex-M Processor Exceptions Numbers *****************************************************************/
52 NonMaskableInt_IRQn = -14, /*!< 2 Non Maskable Interrupt */
53 HardFault_IRQn = -13, /*!< 4 Cortex-M Memory Management Interrupt */
54 MemoryManagement_IRQn = -12, /*!< 4 Cortex-M Memory Management Interrupt */
55 BusFault_IRQn = -11, /*!< 5 Cortex-M Bus Fault Interrupt */
56 UsageFault_IRQn = -10, /*!< 6 Cortex-M Usage Fault Interrupt */
57 SVCall_IRQn = -5, /*!< 11 Cortex-M SV Call Interrupt */
58 DebugMonitor_IRQn = -4, /*!< 12 Cortex-M Debug Monitor Interrupt */
59 PendSV_IRQn = -2, /*!< 14 Cortex-M Pend SV Interrupt */
60 SysTick_IRQn = -1, /*!< 15 Cortex-M System Tick Interrupt */
61 /****** STM32 specific Interrupt Numbers **********************************************************************/
62 WWDG_IRQn = 0, /*!< Window WatchDog Interrupt ( wwdg1_it, wwdg2_it) */
63 PVD_PVM_IRQn = 1, /*!< PVD/PVM through EXTI Line detection Interrupt */
64 RTC_TAMP_STAMP_CSS_LSE_IRQn = 2, /*!< Tamper, TimeStamp, CSS and LSE interrupts through the EXTI line */
65 RTC_WKUP_IRQn = 3, /*!< RTC Wakeup interrupt through the EXTI line */
66 FLASH_IRQn = 4, /*!< FLASH global Interrupt */
67 RCC_IRQn = 5, /*!< RCC global Interrupt */
68 EXTI0_IRQn = 6, /*!< EXTI Line0 Interrupt */
69 EXTI1_IRQn = 7, /*!< EXTI Line1 Interrupt */
70 EXTI2_IRQn = 8, /*!< EXTI Line2 Interrupt */
71 EXTI3_IRQn = 9, /*!< EXTI Line3 Interrupt */
72 EXTI4_IRQn = 10, /*!< EXTI Line4 Interrupt */
73 DMA1_Stream0_IRQn = 11, /*!< DMA1 Stream 0 global Interrupt */
74 DMA1_Stream1_IRQn = 12, /*!< DMA1 Stream 1 global Interrupt */
75 DMA1_Stream2_IRQn = 13, /*!< DMA1 Stream 2 global Interrupt */
76 DMA1_Stream3_IRQn = 14, /*!< DMA1 Stream 3 global Interrupt */
77 DMA1_Stream4_IRQn = 15, /*!< DMA1 Stream 4 global Interrupt */
78 DMA1_Stream5_IRQn = 16, /*!< DMA1 Stream 5 global Interrupt */
79 DMA1_Stream6_IRQn = 17, /*!< DMA1 Stream 6 global Interrupt */
80 ADC_IRQn = 18, /*!< ADC1 and ADC2 global Interrupts */
81 FDCAN1_IT0_IRQn = 19, /*!< FDCAN1 Interrupt line 0 */
82 FDCAN2_IT0_IRQn = 20, /*!< FDCAN2 Interrupt line 0 */
83 FDCAN1_IT1_IRQn = 21, /*!< FDCAN1 Interrupt line 1 */
84 FDCAN2_IT1_IRQn = 22, /*!< FDCAN2 Interrupt line 1 */
85 EXTI9_5_IRQn = 23, /*!< External Line[9:5] Interrupts */
86 TIM1_BRK_IRQn = 24, /*!< TIM1 Break Interrupt */
87 TIM1_UP_IRQn = 25, /*!< TIM1 Update Interrupt */
88 TIM1_TRG_COM_IRQn = 26, /*!< TIM1 Trigger and Commutation Interrupt */
89 TIM1_CC_IRQn = 27, /*!< TIM1 Capture Compare Interrupt */
90 TIM2_IRQn = 28, /*!< TIM2 global Interrupt */
91 TIM3_IRQn = 29, /*!< TIM3 global Interrupt */
92 TIM4_IRQn = 30, /*!< TIM4 global Interrupt */
93 I2C1_EV_IRQn = 31, /*!< I2C1 Event Interrupt */
94 I2C1_ER_IRQn = 32, /*!< I2C1 Error Interrupt */
95 I2C2_EV_IRQn = 33, /*!< I2C2 Event Interrupt */
96 I2C2_ER_IRQn = 34, /*!< I2C2 Error Interrupt */
97 SPI1_IRQn = 35, /*!< SPI1 global Interrupt */
98 SPI2_IRQn = 36, /*!< SPI2 global Interrupt */
99 USART1_IRQn = 37, /*!< USART1 global Interrupt */
100 USART2_IRQn = 38, /*!< USART2 global Interrupt */
101 USART3_IRQn = 39, /*!< USART3 global Interrupt */
102 EXTI15_10_IRQn = 40, /*!< External Line[15:10] Interrupts */
103 RTC_Alarm_IRQn = 41, /*!< RTC Alarm (A and B) through EXTI Line Interrupt */
104 DFSDM2_IRQn = 42, /*!< DFSDM2 global Interrupt */
105 TIM8_BRK_TIM12_IRQn = 43, /*!< TIM8 Break Interrupt and TIM12 global interrupt */
106 TIM8_UP_TIM13_IRQn = 44, /*!< TIM8 Update Interrupt and TIM13 global interrupt */
107 TIM8_TRG_COM_TIM14_IRQn = 45, /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
108 TIM8_CC_IRQn = 46, /*!< TIM8 Capture Compare Interrupt */
109 DMA1_Stream7_IRQn = 47, /*!< DMA1 Stream7 Interrupt */
110 FMC_IRQn = 48, /*!< FMC global Interrupt */
111 SDMMC1_IRQn = 49, /*!< SDMMC1 global Interrupt */
112 TIM5_IRQn = 50, /*!< TIM5 global Interrupt */
113 SPI3_IRQn = 51, /*!< SPI3 global Interrupt */
114 UART4_IRQn = 52, /*!< UART4 global Interrupt */
115 UART5_IRQn = 53, /*!< UART5 global Interrupt */
116 TIM6_DAC_IRQn = 54, /*!< TIM6 global and DAC1&2 underrun error interrupts */
117 TIM7_IRQn = 55, /*!< TIM7 global interrupt */
118 DMA2_Stream0_IRQn = 56, /*!< DMA2 Stream 0 global Interrupt */
119 DMA2_Stream1_IRQn = 57, /*!< DMA2 Stream 1 global Interrupt */
120 DMA2_Stream2_IRQn = 58, /*!< DMA2 Stream 2 global Interrupt */
121 DMA2_Stream3_IRQn = 59, /*!< DMA2 Stream 3 global Interrupt */
122 DMA2_Stream4_IRQn = 60, /*!< DMA2 Stream 4 global Interrupt */
123 FDCAN_CAL_IRQn = 63, /*!< FDCAN Calibration unit Interrupt */
124 DFSDM1_FLT4_IRQn = 64, /*!< DFSDM Filter4 Interrupt */
125 DFSDM1_FLT5_IRQn = 65, /*!< DFSDM Filter5 Interrupt */
126 DFSDM1_FLT6_IRQn = 66, /*!< DFSDM Filter6 Interrupt */
127 DFSDM1_FLT7_IRQn = 67, /*!< DFSDM Filter7 Interrupt */
128 DMA2_Stream5_IRQn = 68, /*!< DMA2 Stream 5 global interrupt */
129 DMA2_Stream6_IRQn = 69, /*!< DMA2 Stream 6 global interrupt */
130 DMA2_Stream7_IRQn = 70, /*!< DMA2 Stream 7 global interrupt */
131 USART6_IRQn = 71, /*!< USART6 global interrupt */
132 I2C3_EV_IRQn = 72, /*!< I2C3 event interrupt */
133 I2C3_ER_IRQn = 73, /*!< I2C3 error interrupt */
134 OTG_HS_EP1_OUT_IRQn = 74, /*!< USB OTG HS End Point 1 Out global interrupt */
135 OTG_HS_EP1_IN_IRQn = 75, /*!< USB OTG HS End Point 1 In global interrupt */
136 OTG_HS_WKUP_IRQn = 76, /*!< USB OTG HS Wakeup through EXTI interrupt */
137 OTG_HS_IRQn = 77, /*!< USB OTG HS global interrupt */
138 DCMI_PSSI_IRQn = 78, /*!< DCMI and PSSI global interrupt */
139 CRYP_IRQn = 79, /*!< CRYP crypto global interrupt */
140 HASH_RNG_IRQn = 80, /*!< HASH and RNG global interrupt */
141 FPU_IRQn = 81, /*!< FPU global interrupt */
142 UART7_IRQn = 82, /*!< UART7 global interrupt */
143 UART8_IRQn = 83, /*!< UART8 global interrupt */
144 SPI4_IRQn = 84, /*!< SPI4 global Interrupt */
145 SPI5_IRQn = 85, /*!< SPI5 global Interrupt */
146 SPI6_IRQn = 86, /*!< SPI6 global Interrupt */
147 SAI1_IRQn = 87, /*!< SAI1 global Interrupt */
148 LTDC_IRQn = 88, /*!< LTDC global Interrupt */
149 LTDC_ER_IRQn = 89, /*!< LTDC Error global Interrupt */
150 DMA2D_IRQn = 90, /*!< DMA2D global Interrupt */
151 SAI2_IRQn = 91, /*!< SAI2 global Interrupt */
152 OCTOSPI1_IRQn = 92, /*!< OCTOSPI1 global interrupt */
153 LPTIM1_IRQn = 93, /*!< LP TIM1 interrupt */
154 CEC_IRQn = 94, /*!< HDMI-CEC global Interrupt */
155 I2C4_EV_IRQn = 95, /*!< I2C4 Event Interrupt */
156 I2C4_ER_IRQn = 96, /*!< I2C4 Error Interrupt */
157 SPDIF_RX_IRQn = 97, /*!< SPDIF-RX global Interrupt */
158 DMAMUX1_OVR_IRQn = 102, /*!<DMAMUX1 Overrun interrupt */
159 DFSDM1_FLT0_IRQn = 110, /*!<DFSDM Filter1 Interrupt */
160 DFSDM1_FLT1_IRQn = 111, /*!<DFSDM Filter2 Interrupt */
161 DFSDM1_FLT2_IRQn = 112, /*!<DFSDM Filter3 Interrupt */
162 DFSDM1_FLT3_IRQn = 113, /*!<DFSDM Filter4 Interrupt */
163 SWPMI1_IRQn = 115, /*!< Serial Wire Interface 1 global interrupt */
164 TIM15_IRQn = 116, /*!< TIM15 global Interrupt */
165 TIM16_IRQn = 117, /*!< TIM16 global Interrupt */
166 TIM17_IRQn = 118, /*!< TIM17 global Interrupt */
167 MDIOS_WKUP_IRQn = 119, /*!< MDIOS Wakeup Interrupt */
168 MDIOS_IRQn = 120, /*!< MDIOS global Interrupt */
169 JPEG_IRQn = 121, /*!< JPEG global Interrupt */
170 MDMA_IRQn = 122, /*!< MDMA global Interrupt */
171 SDMMC2_IRQn = 124, /*!< SDMMC2 global Interrupt */
172 HSEM1_IRQn = 125, /*!< HSEM1 global Interrupt */
173 DAC2_IRQn = 127, /*!< DAC2 global Interrupt */
174 DMAMUX2_OVR_IRQn = 128, /*!<DMAMUX2 Overrun interrupt */
175 BDMA2_Channel0_IRQn = 129, /*!< BDMA2 Channel 0 global Interrupt */
176 BDMA2_Channel1_IRQn = 130, /*!< BDMA2 Channel 1 global Interrupt */
177 BDMA2_Channel2_IRQn = 131, /*!< BDMA2 Channel 2 global Interrupt */
178 BDMA2_Channel3_IRQn = 132, /*!< BDMA2 Channel 3 global Interrupt */
179 BDMA2_Channel4_IRQn = 133, /*!< BDMA2 Channel 4 global Interrupt */
180 BDMA2_Channel5_IRQn = 134, /*!< BDMA2 Channel 5 global Interrupt */
181 BDMA2_Channel6_IRQn = 135, /*!< BDMA2 Channel 6 global Interrupt */
182 BDMA2_Channel7_IRQn = 136, /*!< BDMA2 Channel 7 global Interrupt */
183 COMP_IRQn = 137 , /*!< COMP global Interrupt */
184 LPTIM2_IRQn = 138, /*!< LP TIM2 global interrupt */
185 LPTIM3_IRQn = 139, /*!< LP TIM3 global interrupt */
186 UART9_IRQn = 140, /*!< UART9 global interrupt */
187 USART10_IRQn = 141, /*!< USART10 global interrupt */
188 LPUART1_IRQn = 142, /*!< LP UART1 interrupt */
189 WWDG_RST_IRQn = 143, /*!<Window Watchdog Event interrupt */
190 CRS_IRQn = 144, /*!< Clock Recovery Global Interrupt */
191 ECC_IRQn = 145, /*!< ECC diagnostic Global Interrupt */
192 DTS_IRQn = 147, /*!< Digital Temperature Sensor Global Interrupt */
193 WAKEUP_PIN_IRQn = 149, /*!< Interrupt for all 6 wake-up pins */
194 OCTOSPI2_IRQn = 150, /*!< OctoSPI2 global interrupt */
195 OTFDEC1_IRQn = 151, /*!< OTFDEC1 global interrupt */
196 OTFDEC2_IRQn = 152, /*!< OTFDEC2 global interrupt */
197 GFXMMU_IRQn = 153, /*!< GFXMMU global interrupt */
198 BDMA1_IRQn = 154, /*!< BDMA1 for DFSM global interrupt */
199 } IRQn_Type;
200
201 /**
202 * @}
203 */
204
205 /** @addtogroup Configuration_section_for_CMSIS
206 * @{
207 */
208
209 #define SMPS /*!< Switched mode power supply feature */
210
211
212
213 /**
214 * @brief Configuration of the Cortex-M7 Processor and Core Peripherals
215 */
216 #define __CM7_REV 0x0100U /*!< Cortex-M7 revision r1p0 */
217 #define __MPU_PRESENT 1 /*!< CM7 provides an MPU */
218 #define __NVIC_PRIO_BITS 4 /*!< CM7 uses 4 Bits for the Priority Levels */
219 #define __Vendor_SysTickConfig 0 /*!< Set to 1 if different SysTick Config is used */
220 #define __FPU_PRESENT 1 /*!< FPU present */
221 #define __ICACHE_PRESENT 1 /*!< CM7 instruction cache present */
222 #define __DCACHE_PRESENT 1 /*!< CM7 data cache present */
223 #include "core_cm7.h" /*!< Cortex-M7 processor and core peripherals */
224
225 /**
226 * @}
227 */
228
229
230
231
232 #include "system_stm32h7xx.h"
233 #include <stdint.h>
234
235 /** @addtogroup Peripheral_registers_structures
236 * @{
237 */
238
239 /**
240 * @brief Analog to Digital Converter
241 */
242
243 typedef struct
244 {
245 __IO uint32_t ISR; /*!< ADC Interrupt and Status Register, Address offset: 0x00 */
246 __IO uint32_t IER; /*!< ADC Interrupt Enable Register, Address offset: 0x04 */
247 __IO uint32_t CR; /*!< ADC control register, Address offset: 0x08 */
248 __IO uint32_t CFGR; /*!< ADC Configuration register, Address offset: 0x0C */
249 __IO uint32_t CFGR2; /*!< ADC Configuration register 2, Address offset: 0x10 */
250 __IO uint32_t SMPR1; /*!< ADC sample time register 1, Address offset: 0x14 */
251 __IO uint32_t SMPR2; /*!< ADC sample time register 2, Address offset: 0x18 */
252 __IO uint32_t PCSEL; /*!< ADC pre-channel selection, Address offset: 0x1C */
253 __IO uint32_t LTR1; /*!< ADC watchdog Lower threshold register 1, Address offset: 0x20 */
254 __IO uint32_t HTR1; /*!< ADC watchdog higher threshold register 1, Address offset: 0x24 */
255 uint32_t RESERVED1; /*!< Reserved, 0x028 */
256 uint32_t RESERVED2; /*!< Reserved, 0x02C */
257 __IO uint32_t SQR1; /*!< ADC regular sequence register 1, Address offset: 0x30 */
258 __IO uint32_t SQR2; /*!< ADC regular sequence register 2, Address offset: 0x34 */
259 __IO uint32_t SQR3; /*!< ADC regular sequence register 3, Address offset: 0x38 */
260 __IO uint32_t SQR4; /*!< ADC regular sequence register 4, Address offset: 0x3C */
261 __IO uint32_t DR; /*!< ADC regular data register, Address offset: 0x40 */
262 uint32_t RESERVED3; /*!< Reserved, 0x044 */
263 uint32_t RESERVED4; /*!< Reserved, 0x048 */
264 __IO uint32_t JSQR; /*!< ADC injected sequence register, Address offset: 0x4C */
265 uint32_t RESERVED5[4]; /*!< Reserved, 0x050 - 0x05C */
266 __IO uint32_t OFR1; /*!< ADC offset register 1, Address offset: 0x60 */
267 __IO uint32_t OFR2; /*!< ADC offset register 2, Address offset: 0x64 */
268 __IO uint32_t OFR3; /*!< ADC offset register 3, Address offset: 0x68 */
269 __IO uint32_t OFR4; /*!< ADC offset register 4, Address offset: 0x6C */
270 uint32_t RESERVED6[4]; /*!< Reserved, 0x070 - 0x07C */
271 __IO uint32_t JDR1; /*!< ADC injected data register 1, Address offset: 0x80 */
272 __IO uint32_t JDR2; /*!< ADC injected data register 2, Address offset: 0x84 */
273 __IO uint32_t JDR3; /*!< ADC injected data register 3, Address offset: 0x88 */
274 __IO uint32_t JDR4; /*!< ADC injected data register 4, Address offset: 0x8C */
275 uint32_t RESERVED7[4]; /*!< Reserved, 0x090 - 0x09C */
276 __IO uint32_t AWD2CR; /*!< ADC Analog Watchdog 2 Configuration Register, Address offset: 0xA0 */
277 __IO uint32_t AWD3CR; /*!< ADC Analog Watchdog 3 Configuration Register, Address offset: 0xA4 */
278 uint32_t RESERVED8; /*!< Reserved, 0x0A8 */
279 uint32_t RESERVED9; /*!< Reserved, 0x0AC */
280 __IO uint32_t LTR2; /*!< ADC watchdog Lower threshold register 2, Address offset: 0xB0 */
281 __IO uint32_t HTR2; /*!< ADC watchdog Higher threshold register 2, Address offset: 0xB4 */
282 __IO uint32_t LTR3; /*!< ADC watchdog Lower threshold register 3, Address offset: 0xB8 */
283 __IO uint32_t HTR3; /*!< ADC watchdog Higher threshold register 3, Address offset: 0xBC */
284 __IO uint32_t DIFSEL; /*!< ADC Differential Mode Selection Register, Address offset: 0xC0 */
285 __IO uint32_t CALFACT; /*!< ADC Calibration Factors, Address offset: 0xC4 */
286 __IO uint32_t CALFACT2; /*!< ADC Linearity Calibration Factors, Address offset: 0xC8 */
287 } ADC_TypeDef;
288
289
290 typedef struct
291 {
292 __IO uint32_t CSR; /*!< ADC Common status register, Address offset: ADC1/3 base address + 0x300 */
293 uint32_t RESERVED; /*!< Reserved, ADC1/3 base address + 0x304 */
294 __IO uint32_t CCR; /*!< ADC common control register, Address offset: ADC1/3 base address + 0x308 */
295 __IO uint32_t CDR; /*!< ADC common regular data register for dual Address offset: ADC1/3 base address + 0x30C */
296 __IO uint32_t CDR2; /*!< ADC common regular data register for 32-bit dual mode Address offset: ADC1/3 base address + 0x310 */
297
298 } ADC_Common_TypeDef;
299
300
301 /**
302 * @brief VREFBUF
303 */
304
305 typedef struct
306 {
307 __IO uint32_t CSR; /*!< VREFBUF control and status register, Address offset: 0x00 */
308 __IO uint32_t CCR; /*!< VREFBUF calibration and control register, Address offset: 0x04 */
309 } VREFBUF_TypeDef;
310
311
312 /**
313 * @brief FD Controller Area Network
314 */
315
316 typedef struct
317 {
318 __IO uint32_t CREL; /*!< FDCAN Core Release register, Address offset: 0x000 */
319 __IO uint32_t ENDN; /*!< FDCAN Endian register, Address offset: 0x004 */
320 __IO uint32_t RESERVED1; /*!< Reserved, 0x008 */
321 __IO uint32_t DBTP; /*!< FDCAN Data Bit Timing & Prescaler register, Address offset: 0x00C */
322 __IO uint32_t TEST; /*!< FDCAN Test register, Address offset: 0x010 */
323 __IO uint32_t RWD; /*!< FDCAN RAM Watchdog register, Address offset: 0x014 */
324 __IO uint32_t CCCR; /*!< FDCAN CC Control register, Address offset: 0x018 */
325 __IO uint32_t NBTP; /*!< FDCAN Nominal Bit Timing & Prescaler register, Address offset: 0x01C */
326 __IO uint32_t TSCC; /*!< FDCAN Timestamp Counter Configuration register, Address offset: 0x020 */
327 __IO uint32_t TSCV; /*!< FDCAN Timestamp Counter Value register, Address offset: 0x024 */
328 __IO uint32_t TOCC; /*!< FDCAN Timeout Counter Configuration register, Address offset: 0x028 */
329 __IO uint32_t TOCV; /*!< FDCAN Timeout Counter Value register, Address offset: 0x02C */
330 __IO uint32_t RESERVED2[4]; /*!< Reserved, 0x030 - 0x03C */
331 __IO uint32_t ECR; /*!< FDCAN Error Counter register, Address offset: 0x040 */
332 __IO uint32_t PSR; /*!< FDCAN Protocol Status register, Address offset: 0x044 */
333 __IO uint32_t TDCR; /*!< FDCAN Transmitter Delay Compensation register, Address offset: 0x048 */
334 __IO uint32_t RESERVED3; /*!< Reserved, 0x04C */
335 __IO uint32_t IR; /*!< FDCAN Interrupt register, Address offset: 0x050 */
336 __IO uint32_t IE; /*!< FDCAN Interrupt Enable register, Address offset: 0x054 */
337 __IO uint32_t ILS; /*!< FDCAN Interrupt Line Select register, Address offset: 0x058 */
338 __IO uint32_t ILE; /*!< FDCAN Interrupt Line Enable register, Address offset: 0x05C */
339 __IO uint32_t RESERVED4[8]; /*!< Reserved, 0x060 - 0x07C */
340 __IO uint32_t GFC; /*!< FDCAN Global Filter Configuration register, Address offset: 0x080 */
341 __IO uint32_t SIDFC; /*!< FDCAN Standard ID Filter Configuration register, Address offset: 0x084 */
342 __IO uint32_t XIDFC; /*!< FDCAN Extended ID Filter Configuration register, Address offset: 0x088 */
343 __IO uint32_t RESERVED5; /*!< Reserved, 0x08C */
344 __IO uint32_t XIDAM; /*!< FDCAN Extended ID AND Mask register, Address offset: 0x090 */
345 __IO uint32_t HPMS; /*!< FDCAN High Priority Message Status register, Address offset: 0x094 */
346 __IO uint32_t NDAT1; /*!< FDCAN New Data 1 register, Address offset: 0x098 */
347 __IO uint32_t NDAT2; /*!< FDCAN New Data 2 register, Address offset: 0x09C */
348 __IO uint32_t RXF0C; /*!< FDCAN Rx FIFO 0 Configuration register, Address offset: 0x0A0 */
349 __IO uint32_t RXF0S; /*!< FDCAN Rx FIFO 0 Status register, Address offset: 0x0A4 */
350 __IO uint32_t RXF0A; /*!< FDCAN Rx FIFO 0 Acknowledge register, Address offset: 0x0A8 */
351 __IO uint32_t RXBC; /*!< FDCAN Rx Buffer Configuration register, Address offset: 0x0AC */
352 __IO uint32_t RXF1C; /*!< FDCAN Rx FIFO 1 Configuration register, Address offset: 0x0B0 */
353 __IO uint32_t RXF1S; /*!< FDCAN Rx FIFO 1 Status register, Address offset: 0x0B4 */
354 __IO uint32_t RXF1A; /*!< FDCAN Rx FIFO 1 Acknowledge register, Address offset: 0x0B8 */
355 __IO uint32_t RXESC; /*!< FDCAN Rx Buffer/FIFO Element Size Configuration register, Address offset: 0x0BC */
356 __IO uint32_t TXBC; /*!< FDCAN Tx Buffer Configuration register, Address offset: 0x0C0 */
357 __IO uint32_t TXFQS; /*!< FDCAN Tx FIFO/Queue Status register, Address offset: 0x0C4 */
358 __IO uint32_t TXESC; /*!< FDCAN Tx Buffer Element Size Configuration register, Address offset: 0x0C8 */
359 __IO uint32_t TXBRP; /*!< FDCAN Tx Buffer Request Pending register, Address offset: 0x0CC */
360 __IO uint32_t TXBAR; /*!< FDCAN Tx Buffer Add Request register, Address offset: 0x0D0 */
361 __IO uint32_t TXBCR; /*!< FDCAN Tx Buffer Cancellation Request register, Address offset: 0x0D4 */
362 __IO uint32_t TXBTO; /*!< FDCAN Tx Buffer Transmission Occurred register, Address offset: 0x0D8 */
363 __IO uint32_t TXBCF; /*!< FDCAN Tx Buffer Cancellation Finished register, Address offset: 0x0DC */
364 __IO uint32_t TXBTIE; /*!< FDCAN Tx Buffer Transmission Interrupt Enable register, Address offset: 0x0E0 */
365 __IO uint32_t TXBCIE; /*!< FDCAN Tx Buffer Cancellation Finished Interrupt Enable register, Address offset: 0x0E4 */
366 __IO uint32_t RESERVED6[2]; /*!< Reserved, 0x0E8 - 0x0EC */
367 __IO uint32_t TXEFC; /*!< FDCAN Tx Event FIFO Configuration register, Address offset: 0x0F0 */
368 __IO uint32_t TXEFS; /*!< FDCAN Tx Event FIFO Status register, Address offset: 0x0F4 */
369 __IO uint32_t TXEFA; /*!< FDCAN Tx Event FIFO Acknowledge register, Address offset: 0x0F8 */
370 __IO uint32_t RESERVED7; /*!< Reserved, 0x0FC */
371 } FDCAN_GlobalTypeDef;
372
373 /**
374 * @brief TTFD Controller Area Network
375 */
376
377 typedef struct
378 {
379 __IO uint32_t TTTMC; /*!< TT Trigger Memory Configuration register, Address offset: 0x100 */
380 __IO uint32_t TTRMC; /*!< TT Reference Message Configuration register, Address offset: 0x104 */
381 __IO uint32_t TTOCF; /*!< TT Operation Configuration register, Address offset: 0x108 */
382 __IO uint32_t TTMLM; /*!< TT Matrix Limits register, Address offset: 0x10C */
383 __IO uint32_t TURCF; /*!< TUR Configuration register, Address offset: 0x110 */
384 __IO uint32_t TTOCN; /*!< TT Operation Control register, Address offset: 0x114 */
385 __IO uint32_t TTGTP; /*!< TT Global Time Preset register, Address offset: 0x118 */
386 __IO uint32_t TTTMK; /*!< TT Time Mark register, Address offset: 0x11C */
387 __IO uint32_t TTIR; /*!< TT Interrupt register, Address offset: 0x120 */
388 __IO uint32_t TTIE; /*!< TT Interrupt Enable register, Address offset: 0x124 */
389 __IO uint32_t TTILS; /*!< TT Interrupt Line Select register, Address offset: 0x128 */
390 __IO uint32_t TTOST; /*!< TT Operation Status register, Address offset: 0x12C */
391 __IO uint32_t TURNA; /*!< TT TUR Numerator Actual register, Address offset: 0x130 */
392 __IO uint32_t TTLGT; /*!< TT Local and Global Time register, Address offset: 0x134 */
393 __IO uint32_t TTCTC; /*!< TT Cycle Time and Count register, Address offset: 0x138 */
394 __IO uint32_t TTCPT; /*!< TT Capture Time register, Address offset: 0x13C */
395 __IO uint32_t TTCSM; /*!< TT Cycle Sync Mark register, Address offset: 0x140 */
396 __IO uint32_t RESERVED1[111]; /*!< Reserved, 0x144 - 0x2FC */
397 __IO uint32_t TTTS; /*!< TT Trigger Select register, Address offset: 0x300 */
398 } TTCAN_TypeDef;
399
400 /**
401 * @brief FD Controller Area Network
402 */
403
404 typedef struct
405 {
406 __IO uint32_t CREL; /*!< Clock Calibration Unit Core Release register, Address offset: 0x00 */
407 __IO uint32_t CCFG; /*!< Calibration Configuration register, Address offset: 0x04 */
408 __IO uint32_t CSTAT; /*!< Calibration Status register, Address offset: 0x08 */
409 __IO uint32_t CWD; /*!< Calibration Watchdog register, Address offset: 0x0C */
410 __IO uint32_t IR; /*!< CCU Interrupt register, Address offset: 0x10 */
411 __IO uint32_t IE; /*!< CCU Interrupt Enable register, Address offset: 0x14 */
412 } FDCAN_ClockCalibrationUnit_TypeDef;
413
414
415 /**
416 * @brief Consumer Electronics Control
417 */
418
419 typedef struct
420 {
421 __IO uint32_t CR; /*!< CEC control register, Address offset:0x00 */
422 __IO uint32_t CFGR; /*!< CEC configuration register, Address offset:0x04 */
423 __IO uint32_t TXDR; /*!< CEC Tx data register , Address offset:0x08 */
424 __IO uint32_t RXDR; /*!< CEC Rx Data Register, Address offset:0x0C */
425 __IO uint32_t ISR; /*!< CEC Interrupt and Status Register, Address offset:0x10 */
426 __IO uint32_t IER; /*!< CEC interrupt enable register, Address offset:0x14 */
427 }CEC_TypeDef;
428
429 /**
430 * @brief CRC calculation unit
431 */
432
433 typedef struct
434 {
435 __IO uint32_t DR; /*!< CRC Data register, Address offset: 0x00 */
436 __IO uint32_t IDR; /*!< CRC Independent data register, Address offset: 0x04 */
437 __IO uint32_t CR; /*!< CRC Control register, Address offset: 0x08 */
438 uint32_t RESERVED2; /*!< Reserved, 0x0C */
439 __IO uint32_t INIT; /*!< Initial CRC value register, Address offset: 0x10 */
440 __IO uint32_t POL; /*!< CRC polynomial register, Address offset: 0x14 */
441 } CRC_TypeDef;
442
443
444 /**
445 * @brief Clock Recovery System
446 */
447 typedef struct
448 {
449 __IO uint32_t CR; /*!< CRS ccontrol register, Address offset: 0x00 */
450 __IO uint32_t CFGR; /*!< CRS configuration register, Address offset: 0x04 */
451 __IO uint32_t ISR; /*!< CRS interrupt and status register, Address offset: 0x08 */
452 __IO uint32_t ICR; /*!< CRS interrupt flag clear register, Address offset: 0x0C */
453 } CRS_TypeDef;
454
455
456 /**
457 * @brief Digital to Analog Converter
458 */
459
460 typedef struct
461 {
462 __IO uint32_t CR; /*!< DAC control register, Address offset: 0x00 */
463 __IO uint32_t SWTRIGR; /*!< DAC software trigger register, Address offset: 0x04 */
464 __IO uint32_t DHR12R1; /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
465 __IO uint32_t DHR12L1; /*!< DAC channel1 12-bit left aligned data holding register, Address offset: 0x0C */
466 __IO uint32_t DHR8R1; /*!< DAC channel1 8-bit right aligned data holding register, Address offset: 0x10 */
467 __IO uint32_t DHR12R2; /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
468 __IO uint32_t DHR12L2; /*!< DAC channel2 12-bit left aligned data holding register, Address offset: 0x18 */
469 __IO uint32_t DHR8R2; /*!< DAC channel2 8-bit right-aligned data holding register, Address offset: 0x1C */
470 __IO uint32_t DHR12RD; /*!< Dual DAC 12-bit right-aligned data holding register, Address offset: 0x20 */
471 __IO uint32_t DHR12LD; /*!< DUAL DAC 12-bit left aligned data holding register, Address offset: 0x24 */
472 __IO uint32_t DHR8RD; /*!< DUAL DAC 8-bit right aligned data holding register, Address offset: 0x28 */
473 __IO uint32_t DOR1; /*!< DAC channel1 data output register, Address offset: 0x2C */
474 __IO uint32_t DOR2; /*!< DAC channel2 data output register, Address offset: 0x30 */
475 __IO uint32_t SR; /*!< DAC status register, Address offset: 0x34 */
476 __IO uint32_t CCR; /*!< DAC calibration control register, Address offset: 0x38 */
477 __IO uint32_t MCR; /*!< DAC mode control register, Address offset: 0x3C */
478 __IO uint32_t SHSR1; /*!< DAC Sample and Hold sample time register 1, Address offset: 0x40 */
479 __IO uint32_t SHSR2; /*!< DAC Sample and Hold sample time register 2, Address offset: 0x44 */
480 __IO uint32_t SHHR; /*!< DAC Sample and Hold hold time register, Address offset: 0x48 */
481 __IO uint32_t SHRR; /*!< DAC Sample and Hold refresh time register, Address offset: 0x4C */
482 } DAC_TypeDef;
483
484 /**
485 * @brief DFSDM module registers
486 */
487 typedef struct
488 {
489 __IO uint32_t FLTCR1; /*!< DFSDM control register1, Address offset: 0x100 */
490 __IO uint32_t FLTCR2; /*!< DFSDM control register2, Address offset: 0x104 */
491 __IO uint32_t FLTISR; /*!< DFSDM interrupt and status register, Address offset: 0x108 */
492 __IO uint32_t FLTICR; /*!< DFSDM interrupt flag clear register, Address offset: 0x10C */
493 __IO uint32_t FLTJCHGR; /*!< DFSDM injected channel group selection register, Address offset: 0x110 */
494 __IO uint32_t FLTFCR; /*!< DFSDM filter control register, Address offset: 0x114 */
495 __IO uint32_t FLTJDATAR; /*!< DFSDM data register for injected group, Address offset: 0x118 */
496 __IO uint32_t FLTRDATAR; /*!< DFSDM data register for regular group, Address offset: 0x11C */
497 __IO uint32_t FLTAWHTR; /*!< DFSDM analog watchdog high threshold register, Address offset: 0x120 */
498 __IO uint32_t FLTAWLTR; /*!< DFSDM analog watchdog low threshold register, Address offset: 0x124 */
499 __IO uint32_t FLTAWSR; /*!< DFSDM analog watchdog status register Address offset: 0x128 */
500 __IO uint32_t FLTAWCFR; /*!< DFSDM analog watchdog clear flag register Address offset: 0x12C */
501 __IO uint32_t FLTEXMAX; /*!< DFSDM extreme detector maximum register, Address offset: 0x130 */
502 __IO uint32_t FLTEXMIN; /*!< DFSDM extreme detector minimum register Address offset: 0x134 */
503 __IO uint32_t FLTCNVTIMR; /*!< DFSDM conversion timer, Address offset: 0x138 */
504 } DFSDM_Filter_TypeDef;
505
506 /**
507 * @brief DFSDM channel configuration registers
508 */
509 typedef struct
510 {
511 __IO uint32_t CHCFGR1; /*!< DFSDM channel configuration register1, Address offset: 0x00 */
512 __IO uint32_t CHCFGR2; /*!< DFSDM channel configuration register2, Address offset: 0x04 */
513 __IO uint32_t CHAWSCDR; /*!< DFSDM channel analog watchdog and
514 short circuit detector register, Address offset: 0x08 */
515 __IO uint32_t CHWDATAR; /*!< DFSDM channel watchdog filter data register, Address offset: 0x0C */
516 __IO uint32_t CHDATINR; /*!< DFSDM channel data input register, Address offset: 0x10 */
517 __IO uint32_t CHDLYR; /*!< DFSDM channel delay register, Address offset: 0x14 */
518 } DFSDM_Channel_TypeDef;
519
520 /**
521 * @brief Debug MCU
522 */
523 typedef struct
524 {
525 __IO uint32_t IDCODE; /*!< MCU device ID code, Address offset: 0x00 */
526 __IO uint32_t CR; /*!< Debug MCU configuration register, Address offset: 0x04 */
527 uint32_t RESERVED4[11]; /*!< Reserved, Address offset: 0x08 */
528 __IO uint32_t APB3FZ1; /*!< Debug MCU APB3FZ1 freeze register, Address offset: 0x34 */
529 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x38 */
530 __IO uint32_t APB1LFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x3C */
531 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x40 */
532 __IO uint32_t APB1HFZ1; /*!< Debug MCU APB1LFZ1 freeze register, Address offset: 0x44 */
533 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x48 */
534 __IO uint32_t APB2FZ1; /*!< Debug MCU APB2FZ1 freeze register, Address offset: 0x4C */
535 uint32_t RESERVED8; /*!< Reserved, Address offset: 0x50 */
536 __IO uint32_t APB4FZ1; /*!< Debug MCU APB4FZ1 freeze register, Address offset: 0x54 */
537 }DBGMCU_TypeDef;
538 /**
539 * @brief DCMI
540 */
541
542 typedef struct
543 {
544 __IO uint32_t CR; /*!< DCMI control register 1, Address offset: 0x00 */
545 __IO uint32_t SR; /*!< DCMI status register, Address offset: 0x04 */
546 __IO uint32_t RISR; /*!< DCMI raw interrupt status register, Address offset: 0x08 */
547 __IO uint32_t IER; /*!< DCMI interrupt enable register, Address offset: 0x0C */
548 __IO uint32_t MISR; /*!< DCMI masked interrupt status register, Address offset: 0x10 */
549 __IO uint32_t ICR; /*!< DCMI interrupt clear register, Address offset: 0x14 */
550 __IO uint32_t ESCR; /*!< DCMI embedded synchronization code register, Address offset: 0x18 */
551 __IO uint32_t ESUR; /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
552 __IO uint32_t CWSTRTR; /*!< DCMI crop window start, Address offset: 0x20 */
553 __IO uint32_t CWSIZER; /*!< DCMI crop window size, Address offset: 0x24 */
554 __IO uint32_t DR; /*!< DCMI data register, Address offset: 0x28 */
555 } DCMI_TypeDef;
556
557 /**
558 * @brief PSSI
559 */
560
561 typedef struct
562 {
563 __IO uint32_t CR; /*!< PSSI control register 1, Address offset: 0x000 */
564 __IO uint32_t SR; /*!< PSSI status register, Address offset: 0x004 */
565 __IO uint32_t RIS; /*!< PSSI raw interrupt status register, Address offset: 0x008 */
566 __IO uint32_t IER; /*!< PSSI interrupt enable register, Address offset: 0x00C */
567 __IO uint32_t MIS; /*!< PSSI masked interrupt status register, Address offset: 0x010 */
568 __IO uint32_t ICR; /*!< PSSI interrupt clear register, Address offset: 0x014 */
569 __IO uint32_t RESERVED1[4]; /*!< Reserved, 0x018 - 0x024 */
570 __IO uint32_t DR; /*!< PSSI data register, Address offset: 0x028 */
571 __IO uint32_t RESERVED2[241]; /*!< Reserved, 0x02C - 0x3EC */
572 __IO uint32_t HWCFGR; /*!< PSSI IP HW configuration register, Address offset: 0x3F0 */
573 __IO uint32_t VERR; /*!< PSSI IP version register, Address offset: 0x3F4 */
574 __IO uint32_t IPIDR; /*!< PSSI IP ID register, Address offset: 0x3F8 */
575 __IO uint32_t SIDR; /*!< PSSI SIZE ID register, Address offset: 0x3FC */
576 } PSSI_TypeDef;
577
578 /**
579 * @brief DMA Controller
580 */
581
582 typedef struct
583 {
584 __IO uint32_t CR; /*!< DMA stream x configuration register */
585 __IO uint32_t NDTR; /*!< DMA stream x number of data register */
586 __IO uint32_t PAR; /*!< DMA stream x peripheral address register */
587 __IO uint32_t M0AR; /*!< DMA stream x memory 0 address register */
588 __IO uint32_t M1AR; /*!< DMA stream x memory 1 address register */
589 __IO uint32_t FCR; /*!< DMA stream x FIFO control register */
590 } DMA_Stream_TypeDef;
591
592 typedef struct
593 {
594 __IO uint32_t LISR; /*!< DMA low interrupt status register, Address offset: 0x00 */
595 __IO uint32_t HISR; /*!< DMA high interrupt status register, Address offset: 0x04 */
596 __IO uint32_t LIFCR; /*!< DMA low interrupt flag clear register, Address offset: 0x08 */
597 __IO uint32_t HIFCR; /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
598 } DMA_TypeDef;
599
600 typedef struct
601 {
602 __IO uint32_t CCR; /*!< DMA channel x configuration register */
603 __IO uint32_t CNDTR; /*!< DMA channel x number of data register */
604 __IO uint32_t CPAR; /*!< DMA channel x peripheral address register */
605 __IO uint32_t CM0AR; /*!< DMA channel x memory 0 address register */
606 __IO uint32_t CM1AR; /*!< DMA channel x memory 1 address register */
607 } BDMA_Channel_TypeDef;
608
609 typedef struct
610 {
611 __IO uint32_t ISR; /*!< DMA interrupt status register, Address offset: 0x00 */
612 __IO uint32_t IFCR; /*!< DMA interrupt flag clear register, Address offset: 0x04 */
613 } BDMA_TypeDef;
614
615 typedef struct
616 {
617 __IO uint32_t CCR; /*!< DMA Multiplexer Channel x Control Register */
618 }DMAMUX_Channel_TypeDef;
619
620 typedef struct
621 {
622 __IO uint32_t CSR; /*!< DMA Channel Status Register */
623 __IO uint32_t CFR; /*!< DMA Channel Clear Flag Register */
624 }DMAMUX_ChannelStatus_TypeDef;
625
626 typedef struct
627 {
628 __IO uint32_t RGCR; /*!< DMA Request Generator x Control Register */
629 }DMAMUX_RequestGen_TypeDef;
630
631 typedef struct
632 {
633 __IO uint32_t RGSR; /*!< DMA Request Generator Status Register */
634 __IO uint32_t RGCFR; /*!< DMA Request Generator Clear Flag Register */
635 }DMAMUX_RequestGenStatus_TypeDef;
636
637 /**
638 * @brief MDMA Controller
639 */
640 typedef struct
641 {
642 __IO uint32_t GISR0; /*!< MDMA Global Interrupt/Status Register 0, Address offset: 0x00 */
643 }MDMA_TypeDef;
644
645 typedef struct
646 {
647 __IO uint32_t CISR; /*!< MDMA channel x interrupt/status register, Address offset: 0x40 */
648 __IO uint32_t CIFCR; /*!< MDMA channel x interrupt flag clear register, Address offset: 0x44 */
649 __IO uint32_t CESR; /*!< MDMA Channel x error status register, Address offset: 0x48 */
650 __IO uint32_t CCR; /*!< MDMA channel x control register, Address offset: 0x4C */
651 __IO uint32_t CTCR; /*!< MDMA channel x Transfer Configuration register, Address offset: 0x50 */
652 __IO uint32_t CBNDTR; /*!< MDMA Channel x block number of data register, Address offset: 0x54 */
653 __IO uint32_t CSAR; /*!< MDMA channel x source address register, Address offset: 0x58 */
654 __IO uint32_t CDAR; /*!< MDMA channel x destination address register, Address offset: 0x5C */
655 __IO uint32_t CBRUR; /*!< MDMA channel x Block Repeat address Update register, Address offset: 0x60 */
656 __IO uint32_t CLAR; /*!< MDMA channel x Link Address register, Address offset: 0x64 */
657 __IO uint32_t CTBR; /*!< MDMA channel x Trigger and Bus selection Register, Address offset: 0x68 */
658 uint32_t RESERVED0; /*!< Reserved, 0x68 */
659 __IO uint32_t CMAR; /*!< MDMA channel x Mask address register, Address offset: 0x70 */
660 __IO uint32_t CMDR; /*!< MDMA channel x Mask Data register, Address offset: 0x74 */
661 }MDMA_Channel_TypeDef;
662
663 /**
664 * @brief DMA2D Controller
665 */
666
667 typedef struct
668 {
669 __IO uint32_t CR; /*!< DMA2D Control Register, Address offset: 0x00 */
670 __IO uint32_t ISR; /*!< DMA2D Interrupt Status Register, Address offset: 0x04 */
671 __IO uint32_t IFCR; /*!< DMA2D Interrupt Flag Clear Register, Address offset: 0x08 */
672 __IO uint32_t FGMAR; /*!< DMA2D Foreground Memory Address Register, Address offset: 0x0C */
673 __IO uint32_t FGOR; /*!< DMA2D Foreground Offset Register, Address offset: 0x10 */
674 __IO uint32_t BGMAR; /*!< DMA2D Background Memory Address Register, Address offset: 0x14 */
675 __IO uint32_t BGOR; /*!< DMA2D Background Offset Register, Address offset: 0x18 */
676 __IO uint32_t FGPFCCR; /*!< DMA2D Foreground PFC Control Register, Address offset: 0x1C */
677 __IO uint32_t FGCOLR; /*!< DMA2D Foreground Color Register, Address offset: 0x20 */
678 __IO uint32_t BGPFCCR; /*!< DMA2D Background PFC Control Register, Address offset: 0x24 */
679 __IO uint32_t BGCOLR; /*!< DMA2D Background Color Register, Address offset: 0x28 */
680 __IO uint32_t FGCMAR; /*!< DMA2D Foreground CLUT Memory Address Register, Address offset: 0x2C */
681 __IO uint32_t BGCMAR; /*!< DMA2D Background CLUT Memory Address Register, Address offset: 0x30 */
682 __IO uint32_t OPFCCR; /*!< DMA2D Output PFC Control Register, Address offset: 0x34 */
683 __IO uint32_t OCOLR; /*!< DMA2D Output Color Register, Address offset: 0x38 */
684 __IO uint32_t OMAR; /*!< DMA2D Output Memory Address Register, Address offset: 0x3C */
685 __IO uint32_t OOR; /*!< DMA2D Output Offset Register, Address offset: 0x40 */
686 __IO uint32_t NLR; /*!< DMA2D Number of Line Register, Address offset: 0x44 */
687 __IO uint32_t LWR; /*!< DMA2D Line Watermark Register, Address offset: 0x48 */
688 __IO uint32_t AMTCR; /*!< DMA2D AHB Master Timer Configuration Register, Address offset: 0x4C */
689 uint32_t RESERVED[236]; /*!< Reserved, 0x50-0x3FF */
690 __IO uint32_t FGCLUT[256]; /*!< DMA2D Foreground CLUT, Address offset:400-7FF */
691 __IO uint32_t BGCLUT[256]; /*!< DMA2D Background CLUT, Address offset:800-BFF */
692 } DMA2D_TypeDef;
693
694
695 /**
696 * @brief External Interrupt/Event Controller
697 */
698
699 typedef struct
700 {
701 __IO uint32_t RTSR1; /*!< EXTI Rising trigger selection register, Address offset: 0x00 */
702 __IO uint32_t FTSR1; /*!< EXTI Falling trigger selection register, Address offset: 0x04 */
703 __IO uint32_t SWIER1; /*!< EXTI Software interrupt event register, Address offset: 0x08 */
704 __IO uint32_t D3PMR1; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR1) Address offset: 0x0C */
705 __IO uint32_t D3PCR1L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR1L) Address offset: 0x10 */
706 __IO uint32_t D3PCR1H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR1H) Address offset: 0x14 */
707 uint32_t RESERVED1[2]; /*!< Reserved, 0x18 to 0x1C */
708 __IO uint32_t RTSR2; /*!< EXTI Rising trigger selection register, Address offset: 0x20 */
709 __IO uint32_t FTSR2; /*!< EXTI Falling trigger selection register, Address offset: 0x24 */
710 __IO uint32_t SWIER2; /*!< EXTI Software interrupt event register, Address offset: 0x28 */
711 __IO uint32_t D3PMR2; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR2) Address offset: 0x2C */
712 __IO uint32_t D3PCR2L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR2L) Address offset: 0x30 */
713 __IO uint32_t D3PCR2H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR2H) Address offset: 0x34 */
714 uint32_t RESERVED2[2]; /*!< Reserved, 0x38 to 0x3C */
715 __IO uint32_t RTSR3; /*!< EXTI Rising trigger selection register, Address offset: 0x40 */
716 __IO uint32_t FTSR3; /*!< EXTI Falling trigger selection register, Address offset: 0x44 */
717 __IO uint32_t SWIER3; /*!< EXTI Software interrupt event register, Address offset: 0x48 */
718 __IO uint32_t D3PMR3; /*!< EXTI D3 Pending mask register, (same register as to SRDPMR3) Address offset: 0x4C */
719 __IO uint32_t D3PCR3L; /*!< EXTI D3 Pending clear selection register low, (same register as to SRDPCR3L) Address offset: 0x50 */
720 __IO uint32_t D3PCR3H; /*!< EXTI D3 Pending clear selection register High, (same register as to SRDPCR3H) Address offset: 0x54 */
721 uint32_t RESERVED3[10]; /*!< Reserved, 0x58 to 0x7C */
722 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x80 */
723 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x84 */
724 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x88 */
725 uint32_t RESERVED4; /*!< Reserved, 0x8C */
726 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x90 */
727 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x94 */
728 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x98 */
729 uint32_t RESERVED5; /*!< Reserved, 0x9C */
730 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0xA0 */
731 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0xA4 */
732 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0xA8 */
733 }EXTI_TypeDef;
734
735 typedef struct
736 {
737 __IO uint32_t IMR1; /*!< EXTI Interrupt mask register, Address offset: 0x00 */
738 __IO uint32_t EMR1; /*!< EXTI Event mask register, Address offset: 0x04 */
739 __IO uint32_t PR1; /*!< EXTI Pending register, Address offset: 0x08 */
740 uint32_t RESERVED1; /*!< Reserved, 0x0C */
741 __IO uint32_t IMR2; /*!< EXTI Interrupt mask register, Address offset: 0x10 */
742 __IO uint32_t EMR2; /*!< EXTI Event mask register, Address offset: 0x14 */
743 __IO uint32_t PR2; /*!< EXTI Pending register, Address offset: 0x18 */
744 uint32_t RESERVED2; /*!< Reserved, 0x1C */
745 __IO uint32_t IMR3; /*!< EXTI Interrupt mask register, Address offset: 0x20 */
746 __IO uint32_t EMR3; /*!< EXTI Event mask register, Address offset: 0x24 */
747 __IO uint32_t PR3; /*!< EXTI Pending register, Address offset: 0x28 */
748 }EXTI_Core_TypeDef;
749
750
751 /**
752 * @brief FLASH Registers
753 */
754
755 typedef struct
756 {
757 __IO uint32_t ACR; /*!< FLASH access control register, Address offset: 0x00 */
758 __IO uint32_t KEYR1; /*!< Flash Key Register for bank1, Address offset: 0x04 */
759 __IO uint32_t OPTKEYR; /*!< Flash Option Key Register, Address offset: 0x08 */
760 __IO uint32_t CR1; /*!< Flash Control Register for bank1, Address offset: 0x0C */
761 __IO uint32_t SR1; /*!< Flash Status Register for bank1, Address offset: 0x10 */
762 __IO uint32_t CCR1; /*!< Flash Control Register for bank1, Address offset: 0x14 */
763 __IO uint32_t OPTCR; /*!< Flash Option Control Register, Address offset: 0x18 */
764 __IO uint32_t OPTSR_CUR; /*!< Flash Option Status Current Register, Address offset: 0x1C */
765 __IO uint32_t OPTSR_PRG; /*!< Flash Option Status to Program Register, Address offset: 0x20 */
766 __IO uint32_t OPTCCR; /*!< Flash Option Clear Control Register, Address offset: 0x24 */
767 __IO uint32_t PRAR_CUR1; /*!< Flash Current Protection Address Register for bank1, Address offset: 0x28 */
768 __IO uint32_t PRAR_PRG1; /*!< Flash Protection Address to Program Register for bank1, Address offset: 0x2C */
769 __IO uint32_t SCAR_CUR1; /*!< Flash Current Secure Address Register for bank1, Address offset: 0x30 */
770 __IO uint32_t SCAR_PRG1; /*!< Flash Secure Address to Program Register for bank1, Address offset: 0x34 */
771 __IO uint32_t WPSN_CUR1; /*!< Flash Current Write Protection Register on bank1, Address offset: 0x38 */
772 __IO uint32_t WPSN_PRG1; /*!< Flash Write Protection to Program Register on bank1, Address offset: 0x3C */
773 __IO uint32_t BOOT_CUR; /*!< Flash Current Boot Address for Pelican Core Register, Address offset: 0x40 */
774 __IO uint32_t BOOT_PRG; /*!< Flash Boot Address to Program for Pelican Core Register, Address offset: 0x44 */
775 uint32_t RESERVED0[2]; /*!< Reserved, 0x48 to 0x4C */
776 __IO uint32_t CRCCR1; /*!< Flash CRC Control register For Bank1 Register , Address offset: 0x50 */
777 __IO uint32_t CRCSADD1; /*!< Flash CRC Start Address Register for Bank1 , Address offset: 0x54 */
778 __IO uint32_t CRCEADD1; /*!< Flash CRC End Address Register for Bank1 , Address offset: 0x58 */
779 __IO uint32_t CRCDATA; /*!< Flash CRC Data Register for Bank1 , Address offset: 0x5C */
780 __IO uint32_t ECC_FA1; /*!< Flash ECC Fail Address For Bank1 Register , Address offset: 0x60 */
781 uint32_t RESERVED; /*!< Reserved, 0x64 */
782 __IO uint32_t OTPBL_CUR; /*!< Flash Current OTP Block Lock Register, Address offset: 0x68 */
783 __IO uint32_t OTPBL_PRG; /*!< Flash OTP Block Lock to Program Register, Address offset: 0x6C */
784 uint32_t RESERVED1[37]; /*!< Reserved, 0x70 to 0x100 */
785 __IO uint32_t KEYR2; /*!< Flash Key Register for bank2, Address offset: 0x104 */
786 uint32_t RESERVED2; /*!< Reserved, 0x108 */
787 __IO uint32_t CR2; /*!< Flash Control Register for bank2, Address offset: 0x10C */
788 __IO uint32_t SR2; /*!< Flash Status Register for bank2, Address offset: 0x110 */
789 __IO uint32_t CCR2; /*!< Flash Status Register for bank2, Address offset: 0x114 */
790 uint32_t RESERVED3[4]; /*!< Reserved, 0x118 to 0x124 */
791 __IO uint32_t PRAR_CUR2; /*!< Flash Current Protection Address Register for bank2, Address offset: 0x128 */
792 __IO uint32_t PRAR_PRG2; /*!< Flash Protection Address to Program Register for bank2, Address offset: 0x12C */
793 __IO uint32_t SCAR_CUR2; /*!< Flash Current Secure Address Register for bank2, Address offset: 0x130 */
794 __IO uint32_t SCAR_PRG2; /*!< Flash Secure Address Register for bank2, Address offset: 0x134 */
795 __IO uint32_t WPSN_CUR2; /*!< Flash Current Write Protection Register on bank2, Address offset: 0x138 */
796 __IO uint32_t WPSN_PRG2; /*!< Flash Write Protection to Program Register on bank2, Address offset: 0x13C */
797 uint32_t RESERVED4[4]; /*!< Reserved, 0x140 to 0x14C */
798 __IO uint32_t CRCCR2; /*!< Flash CRC Control register For Bank2 Register , Address offset: 0x150 */
799 __IO uint32_t CRCSADD2; /*!< Flash CRC Start Address Register for Bank2 , Address offset: 0x154 */
800 __IO uint32_t CRCEADD2; /*!< Flash CRC End Address Register for Bank2 , Address offset: 0x158 */
801 __IO uint32_t CRCDATA2; /*!< Flash CRC Data Register for Bank2 , Address offset: 0x15C */
802 __IO uint32_t ECC_FA2; /*!< Flash ECC Fail Address For Bank2 Register , Address offset: 0x160 */
803 } FLASH_TypeDef;
804
805 /**
806 * @brief Flexible Memory Controller
807 */
808
809 typedef struct
810 {
811 __IO uint32_t BTCR[8]; /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */
812 } FMC_Bank1_TypeDef;
813
814 /**
815 * @brief Flexible Memory Controller Bank1E
816 */
817
818 typedef struct
819 {
820 __IO uint32_t BWTR[7]; /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
821 } FMC_Bank1E_TypeDef;
822
823 /**
824 * @brief Flexible Memory Controller Bank2
825 */
826
827 typedef struct
828 {
829 __IO uint32_t PCR2; /*!< NAND Flash control register 2, Address offset: 0x60 */
830 __IO uint32_t SR2; /*!< NAND Flash FIFO status and interrupt register 2, Address offset: 0x64 */
831 __IO uint32_t PMEM2; /*!< NAND Flash Common memory space timing register 2, Address offset: 0x68 */
832 __IO uint32_t PATT2; /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
833 uint32_t RESERVED0; /*!< Reserved, 0x70 */
834 __IO uint32_t ECCR2; /*!< NAND Flash ECC result registers 2, Address offset: 0x74 */
835 } FMC_Bank2_TypeDef;
836
837 /**
838 * @brief Flexible Memory Controller Bank3
839 */
840
841 typedef struct
842 {
843 __IO uint32_t PCR; /*!< NAND Flash control register 3, Address offset: 0x80 */
844 __IO uint32_t SR; /*!< NAND Flash FIFO status and interrupt register 3, Address offset: 0x84 */
845 __IO uint32_t PMEM; /*!< NAND Flash Common memory space timing register 3, Address offset: 0x88 */
846 __IO uint32_t PATT; /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
847 uint32_t RESERVED; /*!< Reserved, 0x90 */
848 __IO uint32_t ECCR; /*!< NAND Flash ECC result registers 3, Address offset: 0x94 */
849 } FMC_Bank3_TypeDef;
850
851 /**
852 * @brief Flexible Memory Controller Bank5 and 6
853 */
854
855
856 typedef struct
857 {
858 __IO uint32_t SDCR[2]; /*!< SDRAM Control registers , Address offset: 0x140-0x144 */
859 __IO uint32_t SDTR[2]; /*!< SDRAM Timing registers , Address offset: 0x148-0x14C */
860 __IO uint32_t SDCMR; /*!< SDRAM Command Mode register, Address offset: 0x150 */
861 __IO uint32_t SDRTR; /*!< SDRAM Refresh Timer register, Address offset: 0x154 */
862 __IO uint32_t SDSR; /*!< SDRAM Status register, Address offset: 0x158 */
863 } FMC_Bank5_6_TypeDef;
864
865 /**
866 * @brief GFXMMU registers
867 */
868
869 typedef struct
870 {
871 __IO uint32_t CR; /*!< GFXMMU configuration register, Address offset: 0x00 */
872 __IO uint32_t SR; /*!< GFXMMU status register, Address offset: 0x04 */
873 __IO uint32_t FCR; /*!< GFXMMU flag clear register, Address offset: 0x08 */
874 __IO uint32_t CCR; /*!< GFXMMU Cache Control Register, Address offset: 0x0C */
875 __IO uint32_t DVR; /*!< GFXMMU default value register, Address offset: 0x10 */
876 uint32_t RESERVED1[3]; /*!< Reserved1, Address offset: 0x14 to 0x1C */
877 __IO uint32_t B0CR; /*!< GFXMMU buffer 0 configuration register, Address offset: 0x20 */
878 __IO uint32_t B1CR; /*!< GFXMMU buffer 1 configuration register, Address offset: 0x24 */
879 __IO uint32_t B2CR; /*!< GFXMMU buffer 2 configuration register, Address offset: 0x28 */
880 __IO uint32_t B3CR; /*!< GFXMMU buffer 3 configuration register, Address offset: 0x2C */
881 uint32_t RESERVED2[1008]; /*!< Reserved2, Address offset: 0x30 to 0xFEC */
882 __IO uint32_t HWCFGR; /*!< GFXMMU hardware configuration register, Address offset: 0xFF0 */
883 __IO uint32_t VERR; /*!< GFXMMU version register, Address offset: 0xFF4 */
884 __IO uint32_t IPIDR; /*!< GFXMMU identification register, Address offset: 0xFF8 */
885 __IO uint32_t SIDR; /*!< GFXMMU size identification register, Address offset: 0xFFC */
886 __IO uint32_t LUT[2048]; /*!< GFXMMU LUT registers, Address offset: 0x1000 to 0x2FFC
887 For LUT line i, LUTiL = LUT[2*i] and LUTiH = LUT[(2*i)+1] */
888 } GFXMMU_TypeDef;
889 /**
890 * @brief General Purpose I/O
891 */
892
893 typedef struct
894 {
895 __IO uint32_t MODER; /*!< GPIO port mode register, Address offset: 0x00 */
896 __IO uint32_t OTYPER; /*!< GPIO port output type register, Address offset: 0x04 */
897 __IO uint32_t OSPEEDR; /*!< GPIO port output speed register, Address offset: 0x08 */
898 __IO uint32_t PUPDR; /*!< GPIO port pull-up/pull-down register, Address offset: 0x0C */
899 __IO uint32_t IDR; /*!< GPIO port input data register, Address offset: 0x10 */
900 __IO uint32_t ODR; /*!< GPIO port output data register, Address offset: 0x14 */
901 __IO uint32_t BSRR; /*!< GPIO port bit set/reset, Address offset: 0x18 */
902 __IO uint32_t LCKR; /*!< GPIO port configuration lock register, Address offset: 0x1C */
903 __IO uint32_t AFR[2]; /*!< GPIO alternate function registers, Address offset: 0x20-0x24 */
904 } GPIO_TypeDef;
905
906 /**
907 * @brief Operational Amplifier (OPAMP)
908 */
909
910 typedef struct
911 {
912 __IO uint32_t CSR; /*!< OPAMP control/status register, Address offset: 0x00 */
913 __IO uint32_t OTR; /*!< OPAMP offset trimming register for normal mode, Address offset: 0x04 */
914 __IO uint32_t HSOTR; /*!< OPAMP offset trimming register for high speed mode, Address offset: 0x08 */
915 } OPAMP_TypeDef;
916
917 /**
918 * @brief System configuration controller
919 */
920
921 typedef struct
922 {
923 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x00 */
924 __IO uint32_t PMCR; /*!< SYSCFG peripheral mode configuration register, Address offset: 0x04 */
925 __IO uint32_t EXTICR[4]; /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
926 __IO uint32_t CFGR; /*!< SYSCFG configuration registers, Address offset: 0x18 */
927 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x1C */
928 __IO uint32_t CCCSR; /*!< SYSCFG compensation cell control/status register, Address offset: 0x20 */
929 __IO uint32_t CCVR; /*!< SYSCFG compensation cell value register, Address offset: 0x24 */
930 __IO uint32_t CCCR; /*!< SYSCFG compensation cell code register, Address offset: 0x28 */
931
932 } SYSCFG_TypeDef;
933
934 /**
935 * @brief Inter-integrated Circuit Interface
936 */
937
938 typedef struct
939 {
940 __IO uint32_t CR1; /*!< I2C Control register 1, Address offset: 0x00 */
941 __IO uint32_t CR2; /*!< I2C Control register 2, Address offset: 0x04 */
942 __IO uint32_t OAR1; /*!< I2C Own address 1 register, Address offset: 0x08 */
943 __IO uint32_t OAR2; /*!< I2C Own address 2 register, Address offset: 0x0C */
944 __IO uint32_t TIMINGR; /*!< I2C Timing register, Address offset: 0x10 */
945 __IO uint32_t TIMEOUTR; /*!< I2C Timeout register, Address offset: 0x14 */
946 __IO uint32_t ISR; /*!< I2C Interrupt and status register, Address offset: 0x18 */
947 __IO uint32_t ICR; /*!< I2C Interrupt clear register, Address offset: 0x1C */
948 __IO uint32_t PECR; /*!< I2C PEC register, Address offset: 0x20 */
949 __IO uint32_t RXDR; /*!< I2C Receive data register, Address offset: 0x24 */
950 __IO uint32_t TXDR; /*!< I2C Transmit data register, Address offset: 0x28 */
951 } I2C_TypeDef;
952
953 /**
954 * @brief Independent WATCHDOG
955 */
956
957 typedef struct
958 {
959 __IO uint32_t KR; /*!< IWDG Key register, Address offset: 0x00 */
960 __IO uint32_t PR; /*!< IWDG Prescaler register, Address offset: 0x04 */
961 __IO uint32_t RLR; /*!< IWDG Reload register, Address offset: 0x08 */
962 __IO uint32_t SR; /*!< IWDG Status register, Address offset: 0x0C */
963 __IO uint32_t WINR; /*!< IWDG Window register, Address offset: 0x10 */
964 } IWDG_TypeDef;
965
966
967 /**
968 * @brief JPEG Codec
969 */
970 typedef struct
971 {
972 __IO uint32_t CONFR0; /*!< JPEG Codec Control Register (JPEG_CONFR0), Address offset: 00h */
973 __IO uint32_t CONFR1; /*!< JPEG Codec Control Register (JPEG_CONFR1), Address offset: 04h */
974 __IO uint32_t CONFR2; /*!< JPEG Codec Control Register (JPEG_CONFR2), Address offset: 08h */
975 __IO uint32_t CONFR3; /*!< JPEG Codec Control Register (JPEG_CONFR3), Address offset: 0Ch */
976 __IO uint32_t CONFR4; /*!< JPEG Codec Control Register (JPEG_CONFR4), Address offset: 10h */
977 __IO uint32_t CONFR5; /*!< JPEG Codec Control Register (JPEG_CONFR5), Address offset: 14h */
978 __IO uint32_t CONFR6; /*!< JPEG Codec Control Register (JPEG_CONFR6), Address offset: 18h */
979 __IO uint32_t CONFR7; /*!< JPEG Codec Control Register (JPEG_CONFR7), Address offset: 1Ch */
980 uint32_t Reserved20[4]; /* Reserved Address offset: 20h-2Ch */
981 __IO uint32_t CR; /*!< JPEG Control Register (JPEG_CR), Address offset: 30h */
982 __IO uint32_t SR; /*!< JPEG Status Register (JPEG_SR), Address offset: 34h */
983 __IO uint32_t CFR; /*!< JPEG Clear Flag Register (JPEG_CFR), Address offset: 38h */
984 uint32_t Reserved3c; /* Reserved Address offset: 3Ch */
985 __IO uint32_t DIR; /*!< JPEG Data Input Register (JPEG_DIR), Address offset: 40h */
986 __IO uint32_t DOR; /*!< JPEG Data Output Register (JPEG_DOR), Address offset: 44h */
987 uint32_t Reserved48[2]; /* Reserved Address offset: 48h-4Ch */
988 __IO uint32_t QMEM0[16]; /*!< JPEG quantization tables 0, Address offset: 50h-8Ch */
989 __IO uint32_t QMEM1[16]; /*!< JPEG quantization tables 1, Address offset: 90h-CCh */
990 __IO uint32_t QMEM2[16]; /*!< JPEG quantization tables 2, Address offset: D0h-10Ch */
991 __IO uint32_t QMEM3[16]; /*!< JPEG quantization tables 3, Address offset: 110h-14Ch */
992 __IO uint32_t HUFFMIN[16]; /*!< JPEG HuffMin tables, Address offset: 150h-18Ch */
993 __IO uint32_t HUFFBASE[32]; /*!< JPEG HuffSymb tables, Address offset: 190h-20Ch */
994 __IO uint32_t HUFFSYMB[84]; /*!< JPEG HUFFSYMB tables, Address offset: 210h-35Ch */
995 __IO uint32_t DHTMEM[103]; /*!< JPEG DHTMem tables, Address offset: 360h-4F8h */
996 uint32_t Reserved4FC; /* Reserved Address offset: 4FCh */
997 __IO uint32_t HUFFENC_AC0[88]; /*!< JPEG encodor, AC Huffman table 0, Address offset: 500h-65Ch */
998 __IO uint32_t HUFFENC_AC1[88]; /*!< JPEG encodor, AC Huffman table 1, Address offset: 660h-7BCh */
999 __IO uint32_t HUFFENC_DC0[8]; /*!< JPEG encodor, DC Huffman table 0, Address offset: 7C0h-7DCh */
1000 __IO uint32_t HUFFENC_DC1[8]; /*!< JPEG encodor, DC Huffman table 1, Address offset: 7E0h-7FCh */
1001
1002 } JPEG_TypeDef;
1003
1004 /**
1005 * @brief LCD-TFT Display Controller
1006 */
1007
1008 typedef struct
1009 {
1010 uint32_t RESERVED0[2]; /*!< Reserved, 0x00-0x04 */
1011 __IO uint32_t SSCR; /*!< LTDC Synchronization Size Configuration Register, Address offset: 0x08 */
1012 __IO uint32_t BPCR; /*!< LTDC Back Porch Configuration Register, Address offset: 0x0C */
1013 __IO uint32_t AWCR; /*!< LTDC Active Width Configuration Register, Address offset: 0x10 */
1014 __IO uint32_t TWCR; /*!< LTDC Total Width Configuration Register, Address offset: 0x14 */
1015 __IO uint32_t GCR; /*!< LTDC Global Control Register, Address offset: 0x18 */
1016 uint32_t RESERVED1[2]; /*!< Reserved, 0x1C-0x20 */
1017 __IO uint32_t SRCR; /*!< LTDC Shadow Reload Configuration Register, Address offset: 0x24 */
1018 uint32_t RESERVED2[1]; /*!< Reserved, 0x28 */
1019 __IO uint32_t BCCR; /*!< LTDC Background Color Configuration Register, Address offset: 0x2C */
1020 uint32_t RESERVED3[1]; /*!< Reserved, 0x30 */
1021 __IO uint32_t IER; /*!< LTDC Interrupt Enable Register, Address offset: 0x34 */
1022 __IO uint32_t ISR; /*!< LTDC Interrupt Status Register, Address offset: 0x38 */
1023 __IO uint32_t ICR; /*!< LTDC Interrupt Clear Register, Address offset: 0x3C */
1024 __IO uint32_t LIPCR; /*!< LTDC Line Interrupt Position Configuration Register, Address offset: 0x40 */
1025 __IO uint32_t CPSR; /*!< LTDC Current Position Status Register, Address offset: 0x44 */
1026 __IO uint32_t CDSR; /*!< LTDC Current Display Status Register, Address offset: 0x48 */
1027 } LTDC_TypeDef;
1028
1029 /**
1030 * @brief LCD-TFT Display layer x Controller
1031 */
1032
1033 typedef struct
1034 {
1035 __IO uint32_t CR; /*!< LTDC Layerx Control Register Address offset: 0x84 */
1036 __IO uint32_t WHPCR; /*!< LTDC Layerx Window Horizontal Position Configuration Register Address offset: 0x88 */
1037 __IO uint32_t WVPCR; /*!< LTDC Layerx Window Vertical Position Configuration Register Address offset: 0x8C */
1038 __IO uint32_t CKCR; /*!< LTDC Layerx Color Keying Configuration Register Address offset: 0x90 */
1039 __IO uint32_t PFCR; /*!< LTDC Layerx Pixel Format Configuration Register Address offset: 0x94 */
1040 __IO uint32_t CACR; /*!< LTDC Layerx Constant Alpha Configuration Register Address offset: 0x98 */
1041 __IO uint32_t DCCR; /*!< LTDC Layerx Default Color Configuration Register Address offset: 0x9C */
1042 __IO uint32_t BFCR; /*!< LTDC Layerx Blending Factors Configuration Register Address offset: 0xA0 */
1043 uint32_t RESERVED0[2]; /*!< Reserved */
1044 __IO uint32_t CFBAR; /*!< LTDC Layerx Color Frame Buffer Address Register Address offset: 0xAC */
1045 __IO uint32_t CFBLR; /*!< LTDC Layerx Color Frame Buffer Length Register Address offset: 0xB0 */
1046 __IO uint32_t CFBLNR; /*!< LTDC Layerx ColorFrame Buffer Line Number Register Address offset: 0xB4 */
1047 uint32_t RESERVED1[3]; /*!< Reserved */
1048 __IO uint32_t CLUTWR; /*!< LTDC Layerx CLUT Write Register Address offset: 0x144 */
1049
1050 } LTDC_Layer_TypeDef;
1051
1052 /**
1053 * @brief Power Control
1054 */
1055
1056 typedef struct
1057 {
1058 __IO uint32_t CR1; /*!< PWR power control register 1, Address offset: 0x00 */
1059 __IO uint32_t CSR1; /*!< PWR power control status register 1, Address offset: 0x04 */
1060 __IO uint32_t CR2; /*!< PWR power control register 2, Address offset: 0x08 */
1061 __IO uint32_t CR3; /*!< PWR power control register 3, Address offset: 0x0C */
1062 __IO uint32_t CPUCR; /*!< PWR CPU control register, Address offset: 0x10 */
1063 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x14 */
1064 __IO uint32_t SRDCR; /*!< PWR SRD domain control register, Address offset: 0x18 */
1065 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x1C */
1066 __IO uint32_t WKUPCR; /*!< PWR wakeup clear register, Address offset: 0x20 */
1067 __IO uint32_t WKUPFR; /*!< PWR wakeup flag register, Address offset: 0x24 */
1068 __IO uint32_t WKUPEPR; /*!< PWR wakeup enable and polarity register, Address offset: 0x28 */
1069 } PWR_TypeDef;
1070
1071 /**
1072 * @brief Reset and Clock Control
1073 */
1074
1075 typedef struct
1076 {
1077 __IO uint32_t CR; /*!< RCC clock control register, Address offset: 0x00 */
1078 __IO uint32_t HSICFGR; /*!< HSI Clock Calibration Register, Address offset: 0x04 */
1079 __IO uint32_t CRRCR; /*!< Clock Recovery RC Register, Address offset: 0x08 */
1080 __IO uint32_t CSICFGR; /*!< CSI Clock Calibration Register, Address offset: 0x0C */
1081 __IO uint32_t CFGR; /*!< RCC clock configuration register, Address offset: 0x10 */
1082 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x14 */
1083 __IO uint32_t CDCFGR1; /*!< RCC Domain 1 configuration register, Address offset: 0x18 */
1084 __IO uint32_t CDCFGR2; /*!< RCC Domain 2 configuration register, Address offset: 0x1C */
1085 __IO uint32_t SRDCFGR; /*!< RCC Domain 3 configuration register, Address offset: 0x20 */
1086 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x24 */
1087 __IO uint32_t PLLCKSELR; /*!< RCC PLLs Clock Source Selection Register, Address offset: 0x28 */
1088 __IO uint32_t PLLCFGR; /*!< RCC PLLs Configuration Register, Address offset: 0x2C */
1089 __IO uint32_t PLL1DIVR; /*!< RCC PLL1 Dividers Configuration Register, Address offset: 0x30 */
1090 __IO uint32_t PLL1FRACR; /*!< RCC PLL1 Fractional Divider Configuration Register, Address offset: 0x34 */
1091 __IO uint32_t PLL2DIVR; /*!< RCC PLL2 Dividers Configuration Register, Address offset: 0x38 */
1092 __IO uint32_t PLL2FRACR; /*!< RCC PLL2 Fractional Divider Configuration Register, Address offset: 0x3C */
1093 __IO uint32_t PLL3DIVR; /*!< RCC PLL3 Dividers Configuration Register, Address offset: 0x40 */
1094 __IO uint32_t PLL3FRACR; /*!< RCC PLL3 Fractional Divider Configuration Register, Address offset: 0x44 */
1095 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x48 */
1096 __IO uint32_t CDCCIPR; /*!< RCC Domain 1 Kernel Clock Configuration Register Address offset: 0x4C */
1097 __IO uint32_t CDCCIP1R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x50 */
1098 __IO uint32_t CDCCIP2R; /*!< RCC Domain 2 Kernel Clock Configuration Register Address offset: 0x54 */
1099 __IO uint32_t SRDCCIPR; /*!< RCC Domain 3 Kernel Clock Configuration Register Address offset: 0x58 */
1100 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x5C */
1101 __IO uint32_t CIER; /*!< RCC Clock Source Interrupt Enable Register Address offset: 0x60 */
1102 __IO uint32_t CIFR; /*!< RCC Clock Source Interrupt Flag Register Address offset: 0x64 */
1103 __IO uint32_t CICR; /*!< RCC Clock Source Interrupt Clear Register Address offset: 0x68 */
1104 uint32_t RESERVED5; /*!< Reserved, Address offset: 0x6C */
1105 __IO uint32_t BDCR; /*!< RCC Vswitch Backup Domain Control Register, Address offset: 0x70 */
1106 __IO uint32_t CSR; /*!< RCC clock control & status register, Address offset: 0x74 */
1107 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x78 */
1108 __IO uint32_t AHB3RSTR; /*!< RCC AHB3 peripheral reset register, Address offset: 0x7C */
1109 __IO uint32_t AHB1RSTR; /*!< RCC AHB1 peripheral reset register, Address offset: 0x80 */
1110 __IO uint32_t AHB2RSTR; /*!< RCC AHB2 peripheral reset register, Address offset: 0x84 */
1111 __IO uint32_t AHB4RSTR; /*!< RCC AHB4 peripheral reset register, Address offset: 0x88 */
1112 __IO uint32_t APB3RSTR; /*!< RCC APB3 peripheral reset register, Address offset: 0x8C */
1113 __IO uint32_t APB1LRSTR; /*!< RCC APB1 peripheral reset Low Word register, Address offset: 0x90 */
1114 __IO uint32_t APB1HRSTR; /*!< RCC APB1 peripheral reset High Word register, Address offset: 0x94 */
1115 __IO uint32_t APB2RSTR; /*!< RCC APB2 peripheral reset register, Address offset: 0x98 */
1116 __IO uint32_t APB4RSTR; /*!< RCC APB4 peripheral reset register, Address offset: 0x9C */
1117 uint32_t RESERVED7; /*!< Reserved, Address offset: 0xA0 */
1118 uint32_t RESERVED8; /*!< Reserved, Address offset: 0xA4 */
1119 __IO uint32_t SRDAMR; /*!< RCC Domain 3 Autonomous Mode Register, Address offset: 0xA8 */
1120 uint32_t RESERVED9; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1121 __IO uint32_t CKGAENR; /*!< AXI Clocks Gating Enable Register, Address offset: 0xB0 */
1122 uint32_t RESERVED10[31]; /*!< Reserved, 0xAC-0xAF Address offset: 0xAC */
1123 __IO uint32_t RSR; /*!< RCC Reset status register, Address offset: 0xD0 */
1124 __IO uint32_t AHB3ENR; /*!< RCC AHB3 peripheral clock register, Address offset: 0xD4 */
1125 __IO uint32_t AHB1ENR; /*!< RCC AHB1 peripheral clock register, Address offset: 0xD8 */
1126 __IO uint32_t AHB2ENR; /*!< RCC AHB2 peripheral clock register, Address offset: 0xDC */
1127 __IO uint32_t AHB4ENR; /*!< RCC AHB4 peripheral clock register, Address offset: 0xE0 */
1128 __IO uint32_t APB3ENR; /*!< RCC APB3 peripheral clock register, Address offset: 0xE4 */
1129 __IO uint32_t APB1LENR; /*!< RCC APB1 peripheral clock Low Word register, Address offset: 0xE8 */
1130 __IO uint32_t APB1HENR; /*!< RCC APB1 peripheral clock High Word register, Address offset: 0xEC */
1131 __IO uint32_t APB2ENR; /*!< RCC APB2 peripheral clock register, Address offset: 0xF0 */
1132 __IO uint32_t APB4ENR; /*!< RCC APB4 peripheral clock register, Address offset: 0xF4 */
1133 uint32_t RESERVED12; /*!< Reserved, Address offset: 0xF8 */
1134 __IO uint32_t AHB3LPENR; /*!< RCC AHB3 peripheral sleep clock register, Address offset: 0xFC */
1135 __IO uint32_t AHB1LPENR; /*!< RCC AHB1 peripheral sleep clock register, Address offset: 0x100 */
1136 __IO uint32_t AHB2LPENR; /*!< RCC AHB2 peripheral sleep clock register, Address offset: 0x104 */
1137 __IO uint32_t AHB4LPENR; /*!< RCC AHB4 peripheral sleep clock register, Address offset: 0x108 */
1138 __IO uint32_t APB3LPENR; /*!< RCC APB3 peripheral sleep clock register, Address offset: 0x10C */
1139 __IO uint32_t APB1LLPENR; /*!< RCC APB1 peripheral sleep clock Low Word register, Address offset: 0x110 */
1140 __IO uint32_t APB1HLPENR; /*!< RCC APB1 peripheral sleep clock High Word register, Address offset: 0x114 */
1141 __IO uint32_t APB2LPENR; /*!< RCC APB2 peripheral sleep clock register, Address offset: 0x118 */
1142 __IO uint32_t APB4LPENR; /*!< RCC APB4 peripheral sleep clock register, Address offset: 0x11C */
1143 uint32_t RESERVED13[4]; /*!< Reserved, 0x120-0x12C Address offset: 0x120 */
1144
1145 } RCC_TypeDef;
1146
1147
1148 /**
1149 * @brief Real-Time Clock
1150 */
1151 typedef struct
1152 {
1153 __IO uint32_t TR; /*!< RTC time register, Address offset: 0x00 */
1154 __IO uint32_t DR; /*!< RTC date register, Address offset: 0x04 */
1155 __IO uint32_t SSR; /*!< RTC sub second register, Address offset: 0x08 */
1156 __IO uint32_t ICSR; /*!< RTC initialization control and status register, Address offset: 0x0C */
1157 __IO uint32_t PRER; /*!< RTC prescaler register, Address offset: 0x10 */
1158 __IO uint32_t WUTR; /*!< RTC wakeup timer register, Address offset: 0x14 */
1159 __IO uint32_t CR; /*!< RTC control register, Address offset: 0x18 */
1160 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x1C */
1161 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x20 */
1162 __IO uint32_t WPR; /*!< RTC write protection register, Address offset: 0x24 */
1163 __IO uint32_t CALR; /*!< RTC calibration register, Address offset: 0x28 */
1164 __IO uint32_t SHIFTR; /*!< RTC shift control register, Address offset: 0x2C */
1165 __IO uint32_t TSTR; /*!< RTC time stamp time register, Address offset: 0x30 */
1166 __IO uint32_t TSDR; /*!< RTC time stamp date register, Address offset: 0x34 */
1167 __IO uint32_t TSSSR; /*!< RTC time-stamp sub second register, Address offset: 0x38 */
1168 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x3C */
1169 __IO uint32_t ALRMAR; /*!< RTC alarm A register, Address offset: 0x40 */
1170 __IO uint32_t ALRMASSR; /*!< RTC alarm A sub second register, Address offset: 0x44 */
1171 __IO uint32_t ALRMBR; /*!< RTC alarm B register, Address offset: 0x48 */
1172 __IO uint32_t ALRMBSSR; /*!< RTC alarm B sub second register, Address offset: 0x4C */
1173 __IO uint32_t SR; /*!< RTC Status register, Address offset: 0x50 */
1174 __IO uint32_t MISR; /*!< RTC masked interrupt status register, Address offset: 0x54 */
1175 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x58 */
1176 __IO uint32_t SCR; /*!< RTC status Clear register, Address offset: 0x5C */
1177 __IO uint32_t CFGR; /*!< RTC configuration register, Address offset: 0x60 */
1178 } RTC_TypeDef;
1179
1180 /**
1181 * @brief Tamper and backup registers
1182 */
1183 typedef struct
1184 {
1185 __IO uint32_t CR1; /*!< TAMP configuration register 1, Address offset: 0x00 */
1186 __IO uint32_t CR2; /*!< TAMP configuration register 2, Address offset: 0x04 */
1187 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x08 */
1188 __IO uint32_t FLTCR; /*!< TAMP filter control register, Address offset: 0x0C */
1189 __IO uint32_t ATCR1; /*!< TAMP active tamper control register, Address offset: 0x10 */
1190 __IO uint32_t ATSEEDR; /*!< TAMP active tamper seed register, Address offset: 0x14 */
1191 __IO uint32_t ATOR; /*!< TAMP active tamper output register, Address offset: 0x18 */
1192 uint32_t RESERVED1[4]; /*!< Reserved, Address offset: 0x1C -- 0x28 */
1193 __IO uint32_t IER; /*!< TAMP interrupt enable register, Address offset: 0x2C */
1194 __IO uint32_t SR; /*!< TAMP status register, Address offset: 0x30 */
1195 __IO uint32_t MISR; /*!< TAMP masked interrupt status register, Address offset: 0x34 */
1196 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x38 */
1197 __IO uint32_t SCR; /*!< TAMP status clear register, Address offset: 0x3C */
1198 __IO uint32_t COUNTR; /*!< TAMP monotonic counter register, Address offset: 0x40 */
1199 uint32_t RESERVED3[3]; /*!< Reserved, Address offset: 0x44 -- 0x4C */
1200 __IO uint32_t CFGR; /*!< TAMP configuration register, Address offset: 0x50 */
1201 uint32_t RESERVED4[43]; /*!< Reserved, Address offset: 0x54 -- 0xFC */
1202 __IO uint32_t BKP0R; /*!< TAMP backup register 0, Address offset: 0x100 */
1203 __IO uint32_t BKP1R; /*!< TAMP backup register 1, Address offset: 0x104 */
1204 __IO uint32_t BKP2R; /*!< TAMP backup register 2, Address offset: 0x108 */
1205 __IO uint32_t BKP3R; /*!< TAMP backup register 3, Address offset: 0x10C */
1206 __IO uint32_t BKP4R; /*!< TAMP backup register 4, Address offset: 0x110 */
1207 __IO uint32_t BKP5R; /*!< TAMP backup register 5, Address offset: 0x114 */
1208 __IO uint32_t BKP6R; /*!< TAMP backup register 6, Address offset: 0x118 */
1209 __IO uint32_t BKP7R; /*!< TAMP backup register 7, Address offset: 0x11C */
1210 __IO uint32_t BKP8R; /*!< TAMP backup register 8, Address offset: 0x120 */
1211 __IO uint32_t BKP9R; /*!< TAMP backup register 9, Address offset: 0x124 */
1212 __IO uint32_t BKP10R; /*!< TAMP backup register 10, Address offset: 0x128 */
1213 __IO uint32_t BKP11R; /*!< TAMP backup register 11, Address offset: 0x12C */
1214 __IO uint32_t BKP12R; /*!< TAMP backup register 12, Address offset: 0x130 */
1215 __IO uint32_t BKP13R; /*!< TAMP backup register 13, Address offset: 0x134 */
1216 __IO uint32_t BKP14R; /*!< TAMP backup register 14, Address offset: 0x138 */
1217 __IO uint32_t BKP15R; /*!< TAMP backup register 15, Address offset: 0x13C */
1218 __IO uint32_t BKP16R; /*!< TAMP backup register 16, Address offset: 0x140 */
1219 __IO uint32_t BKP17R; /*!< TAMP backup register 17, Address offset: 0x144 */
1220 __IO uint32_t BKP18R; /*!< TAMP backup register 18, Address offset: 0x148 */
1221 __IO uint32_t BKP19R; /*!< TAMP backup register 19, Address offset: 0x14C */
1222 __IO uint32_t BKP20R; /*!< TAMP backup register 20, Address offset: 0x150 */
1223 __IO uint32_t BKP21R; /*!< TAMP backup register 21, Address offset: 0x154 */
1224 __IO uint32_t BKP22R; /*!< TAMP backup register 22, Address offset: 0x158 */
1225 __IO uint32_t BKP23R; /*!< TAMP backup register 23, Address offset: 0x15C */
1226 __IO uint32_t BKP24R; /*!< TAMP backup register 24, Address offset: 0x160 */
1227 __IO uint32_t BKP25R; /*!< TAMP backup register 25, Address offset: 0x164 */
1228 __IO uint32_t BKP26R; /*!< TAMP backup register 26, Address offset: 0x168 */
1229 __IO uint32_t BKP27R; /*!< TAMP backup register 27, Address offset: 0x16C */
1230 __IO uint32_t BKP28R; /*!< TAMP backup register 28, Address offset: 0x170 */
1231 __IO uint32_t BKP29R; /*!< TAMP backup register 29, Address offset: 0x174 */
1232 __IO uint32_t BKP30R; /*!< TAMP backup register 30, Address offset: 0x178 */
1233 __IO uint32_t BKP31R; /*!< TAMP backup register 31, Address offset: 0x17C */
1234 } TAMP_TypeDef;
1235
1236 /**
1237 * @brief Serial Audio Interface
1238 */
1239
1240 typedef struct
1241 {
1242 __IO uint32_t GCR; /*!< SAI global configuration register, Address offset: 0x00 */
1243 uint32_t RESERVED0[16]; /*!< Reserved, 0x04 - 0x43 */
1244 __IO uint32_t PDMCR; /*!< SAI PDM control register, Address offset: 0x44 */
1245 __IO uint32_t PDMDLY; /*!< SAI PDM delay register, Address offset: 0x48 */
1246 } SAI_TypeDef;
1247
1248 typedef struct
1249 {
1250 __IO uint32_t CR1; /*!< SAI block x configuration register 1, Address offset: 0x04 */
1251 __IO uint32_t CR2; /*!< SAI block x configuration register 2, Address offset: 0x08 */
1252 __IO uint32_t FRCR; /*!< SAI block x frame configuration register, Address offset: 0x0C */
1253 __IO uint32_t SLOTR; /*!< SAI block x slot register, Address offset: 0x10 */
1254 __IO uint32_t IMR; /*!< SAI block x interrupt mask register, Address offset: 0x14 */
1255 __IO uint32_t SR; /*!< SAI block x status register, Address offset: 0x18 */
1256 __IO uint32_t CLRFR; /*!< SAI block x clear flag register, Address offset: 0x1C */
1257 __IO uint32_t DR; /*!< SAI block x data register, Address offset: 0x20 */
1258 } SAI_Block_TypeDef;
1259
1260 /**
1261 * @brief SPDIF-RX Interface
1262 */
1263
1264 typedef struct
1265 {
1266 __IO uint32_t CR; /*!< Control register, Address offset: 0x00 */
1267 __IO uint32_t IMR; /*!< Interrupt mask register, Address offset: 0x04 */
1268 __IO uint32_t SR; /*!< Status register, Address offset: 0x08 */
1269 __IO uint32_t IFCR; /*!< Interrupt Flag Clear register, Address offset: 0x0C */
1270 __IO uint32_t DR; /*!< Data input register, Address offset: 0x10 */
1271 __IO uint32_t CSR; /*!< Channel Status register, Address offset: 0x14 */
1272 __IO uint32_t DIR; /*!< Debug Information register, Address offset: 0x18 */
1273 uint32_t RESERVED2; /*!< Reserved, 0x1A */
1274 } SPDIFRX_TypeDef;
1275
1276
1277 /**
1278 * @brief Secure digital input/output Interface
1279 */
1280
1281 typedef struct
1282 {
1283 __IO uint32_t POWER; /*!< SDMMC power control register, Address offset: 0x00 */
1284 __IO uint32_t CLKCR; /*!< SDMMC clock control register, Address offset: 0x04 */
1285 __IO uint32_t ARG; /*!< SDMMC argument register, Address offset: 0x08 */
1286 __IO uint32_t CMD; /*!< SDMMC command register, Address offset: 0x0C */
1287 __I uint32_t RESPCMD; /*!< SDMMC command response register, Address offset: 0x10 */
1288 __I uint32_t RESP1; /*!< SDMMC response 1 register, Address offset: 0x14 */
1289 __I uint32_t RESP2; /*!< SDMMC response 2 register, Address offset: 0x18 */
1290 __I uint32_t RESP3; /*!< SDMMC response 3 register, Address offset: 0x1C */
1291 __I uint32_t RESP4; /*!< SDMMC response 4 register, Address offset: 0x20 */
1292 __IO uint32_t DTIMER; /*!< SDMMC data timer register, Address offset: 0x24 */
1293 __IO uint32_t DLEN; /*!< SDMMC data length register, Address offset: 0x28 */
1294 __IO uint32_t DCTRL; /*!< SDMMC data control register, Address offset: 0x2C */
1295 __I uint32_t DCOUNT; /*!< SDMMC data counter register, Address offset: 0x30 */
1296 __I uint32_t STA; /*!< SDMMC status register, Address offset: 0x34 */
1297 __IO uint32_t ICR; /*!< SDMMC interrupt clear register, Address offset: 0x38 */
1298 __IO uint32_t MASK; /*!< SDMMC mask register, Address offset: 0x3C */
1299 __IO uint32_t ACKTIME; /*!< SDMMC Acknowledgement timer register, Address offset: 0x40 */
1300 uint32_t RESERVED0[3]; /*!< Reserved, 0x44 - 0x4C - 0x4C */
1301 __IO uint32_t IDMACTRL; /*!< SDMMC DMA control register, Address offset: 0x50 */
1302 __IO uint32_t IDMABSIZE; /*!< SDMMC DMA buffer size register, Address offset: 0x54 */
1303 __IO uint32_t IDMABASE0; /*!< SDMMC DMA buffer 0 base address register, Address offset: 0x58 */
1304 __IO uint32_t IDMABASE1; /*!< SDMMC DMA buffer 1 base address register, Address offset: 0x5C */
1305 uint32_t RESERVED1[8]; /*!< Reserved, 0x60-0x7C */
1306 __IO uint32_t FIFO; /*!< SDMMC data FIFO register, Address offset: 0x80 */
1307 uint32_t RESERVED2[222]; /*!< Reserved, 0x84-0x3F8 */
1308 __IO uint32_t IPVR; /*!< SDMMC data FIFO register, Address offset: 0x3FC */
1309 } SDMMC_TypeDef;
1310
1311
1312 /**
1313 * @brief Delay Block DLYB
1314 */
1315
1316 typedef struct
1317 {
1318 __IO uint32_t CR; /*!< DELAY BLOCK control register, Address offset: 0x00 */
1319 __IO uint32_t CFGR; /*!< DELAY BLOCK configuration register, Address offset: 0x04 */
1320 } DLYB_TypeDef;
1321
1322 /**
1323 * @brief HW Semaphore HSEM
1324 */
1325
1326 typedef struct
1327 {
1328 __IO uint32_t R[32]; /*!< 2-step write lock and read back registers, Address offset: 00h-7Ch */
1329 __IO uint32_t RLR[32]; /*!< 1-step read lock registers, Address offset: 80h-FCh */
1330 __IO uint32_t C1IER; /*!< HSEM Interrupt enable register , Address offset: 100h */
1331 __IO uint32_t C1ICR; /*!< HSEM Interrupt clear register , Address offset: 104h */
1332 __IO uint32_t C1ISR; /*!< HSEM Interrupt Status register , Address offset: 108h */
1333 __IO uint32_t C1MISR; /*!< HSEM Interrupt Masked Status register , Address offset: 10Ch */
1334 uint32_t Reserved[12]; /* Reserved Address offset: 110h-13Ch */
1335 __IO uint32_t CR; /*!< HSEM Semaphore clear register , Address offset: 140h */
1336 __IO uint32_t KEYR; /*!< HSEM Semaphore clear key register , Address offset: 144h */
1337
1338 } HSEM_TypeDef;
1339
1340 typedef struct
1341 {
1342 __IO uint32_t IER; /*!< HSEM interrupt enable register , Address offset: 0h */
1343 __IO uint32_t ICR; /*!< HSEM interrupt clear register , Address offset: 4h */
1344 __IO uint32_t ISR; /*!< HSEM interrupt status register , Address offset: 8h */
1345 __IO uint32_t MISR; /*!< HSEM masked interrupt status register , Address offset: Ch */
1346 } HSEM_Common_TypeDef;
1347
1348 /**
1349 * @brief Serial Peripheral Interface
1350 */
1351
1352 typedef struct
1353 {
1354 __IO uint32_t CR1; /*!< SPI/I2S Control register 1, Address offset: 0x00 */
1355 __IO uint32_t CR2; /*!< SPI Control register 2, Address offset: 0x04 */
1356 __IO uint32_t CFG1; /*!< SPI Configuration register 1, Address offset: 0x08 */
1357 __IO uint32_t CFG2; /*!< SPI Configuration register 2, Address offset: 0x0C */
1358 __IO uint32_t IER; /*!< SPI/I2S Interrupt Enable register, Address offset: 0x10 */
1359 __IO uint32_t SR; /*!< SPI/I2S Status register, Address offset: 0x14 */
1360 __IO uint32_t IFCR; /*!< SPI/I2S Interrupt/Status flags clear register, Address offset: 0x18 */
1361 uint32_t RESERVED0; /*!< Reserved, 0x1C */
1362 __IO uint32_t TXDR; /*!< SPI/I2S Transmit data register, Address offset: 0x20 */
1363 uint32_t RESERVED1[3]; /*!< Reserved, 0x24-0x2C */
1364 __IO uint32_t RXDR; /*!< SPI/I2S Receive data register, Address offset: 0x30 */
1365 uint32_t RESERVED2[3]; /*!< Reserved, 0x34-0x3C */
1366 __IO uint32_t CRCPOLY; /*!< SPI CRC Polynomial register, Address offset: 0x40 */
1367 __IO uint32_t TXCRC; /*!< SPI Transmitter CRC register, Address offset: 0x44 */
1368 __IO uint32_t RXCRC; /*!< SPI Receiver CRC register, Address offset: 0x48 */
1369 __IO uint32_t UDRDR; /*!< SPI Underrun data register, Address offset: 0x4C */
1370 __IO uint32_t I2SCFGR; /*!< I2S Configuration register, Address offset: 0x50 */
1371
1372 } SPI_TypeDef;
1373
1374 /**
1375 * @brief DTS
1376 */
1377 typedef struct
1378 {
1379 __IO uint32_t CFGR1; /*!< DTS configuration register, Address offset: 0x00 */
1380 uint32_t RESERVED0; /*!< Reserved, Address offset: 0x04 */
1381 __IO uint32_t T0VALR1; /*!< DTS T0 Value register, Address offset: 0x08 */
1382 uint32_t RESERVED1; /*!< Reserved, Address offset: 0x0C */
1383 __IO uint32_t RAMPVALR; /*!< DTS Ramp value register, Address offset: 0x10 */
1384 __IO uint32_t ITR1; /*!< DTS Interrupt threshold register, Address offset: 0x14 */
1385 uint32_t RESERVED2; /*!< Reserved, Address offset: 0x18 */
1386 __IO uint32_t DR; /*!< DTS data register, Address offset: 0x1C */
1387 __IO uint32_t SR; /*!< DTS status register Address offset: 0x20 */
1388 __IO uint32_t ITENR; /*!< DTS Interrupt enable register, Address offset: 0x24 */
1389 __IO uint32_t ICIFR; /*!< DTS Clear Interrupt flag register, Address offset: 0x28 */
1390 __IO uint32_t OR; /*!< DTS option register 1, Address offset: 0x2C */
1391 }
1392 DTS_TypeDef;
1393
1394 /**
1395 * @brief TIM
1396 */
1397
1398 typedef struct
1399 {
1400 __IO uint32_t CR1; /*!< TIM control register 1, Address offset: 0x00 */
1401 __IO uint32_t CR2; /*!< TIM control register 2, Address offset: 0x04 */
1402 __IO uint32_t SMCR; /*!< TIM slave mode control register, Address offset: 0x08 */
1403 __IO uint32_t DIER; /*!< TIM DMA/interrupt enable register, Address offset: 0x0C */
1404 __IO uint32_t SR; /*!< TIM status register, Address offset: 0x10 */
1405 __IO uint32_t EGR; /*!< TIM event generation register, Address offset: 0x14 */
1406 __IO uint32_t CCMR1; /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
1407 __IO uint32_t CCMR2; /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
1408 __IO uint32_t CCER; /*!< TIM capture/compare enable register, Address offset: 0x20 */
1409 __IO uint32_t CNT; /*!< TIM counter register, Address offset: 0x24 */
1410 __IO uint32_t PSC; /*!< TIM prescaler, Address offset: 0x28 */
1411 __IO uint32_t ARR; /*!< TIM auto-reload register, Address offset: 0x2C */
1412 __IO uint32_t RCR; /*!< TIM repetition counter register, Address offset: 0x30 */
1413 __IO uint32_t CCR1; /*!< TIM capture/compare register 1, Address offset: 0x34 */
1414 __IO uint32_t CCR2; /*!< TIM capture/compare register 2, Address offset: 0x38 */
1415 __IO uint32_t CCR3; /*!< TIM capture/compare register 3, Address offset: 0x3C */
1416 __IO uint32_t CCR4; /*!< TIM capture/compare register 4, Address offset: 0x40 */
1417 __IO uint32_t BDTR; /*!< TIM break and dead-time register, Address offset: 0x44 */
1418 __IO uint32_t DCR; /*!< TIM DMA control register, Address offset: 0x48 */
1419 __IO uint32_t DMAR; /*!< TIM DMA address for full transfer, Address offset: 0x4C */
1420 uint32_t RESERVED1; /*!< Reserved, 0x50 */
1421 __IO uint32_t CCMR3; /*!< TIM capture/compare mode register 3, Address offset: 0x54 */
1422 __IO uint32_t CCR5; /*!< TIM capture/compare register5, Address offset: 0x58 */
1423 __IO uint32_t CCR6; /*!< TIM capture/compare register6, Address offset: 0x5C */
1424 __IO uint32_t AF1; /*!< TIM alternate function option register 1, Address offset: 0x60 */
1425 __IO uint32_t AF2; /*!< TIM alternate function option register 2, Address offset: 0x64 */
1426 __IO uint32_t TISEL; /*!< TIM Input Selection register, Address offset: 0x68 */
1427 } TIM_TypeDef;
1428
1429 /**
1430 * @brief LPTIMIMER
1431 */
1432 typedef struct
1433 {
1434 __IO uint32_t ISR; /*!< LPTIM Interrupt and Status register, Address offset: 0x00 */
1435 __IO uint32_t ICR; /*!< LPTIM Interrupt Clear register, Address offset: 0x04 */
1436 __IO uint32_t IER; /*!< LPTIM Interrupt Enable register, Address offset: 0x08 */
1437 __IO uint32_t CFGR; /*!< LPTIM Configuration register, Address offset: 0x0C */
1438 __IO uint32_t CR; /*!< LPTIM Control register, Address offset: 0x10 */
1439 __IO uint32_t CMP; /*!< LPTIM Compare register, Address offset: 0x14 */
1440 __IO uint32_t ARR; /*!< LPTIM Autoreload register, Address offset: 0x18 */
1441 __IO uint32_t CNT; /*!< LPTIM Counter register, Address offset: 0x1C */
1442 uint32_t RESERVED1; /*!< Reserved, 0x20 */
1443 __IO uint32_t CFGR2; /*!< LPTIM Configuration register, Address offset: 0x24 */
1444 } LPTIM_TypeDef;
1445
1446 /**
1447 * @brief Comparator
1448 */
1449 typedef struct
1450 {
1451 __IO uint32_t SR; /*!< Comparator status register, Address offset: 0x00 */
1452 __IO uint32_t ICFR; /*!< Comparator interrupt clear flag register, Address offset: 0x04 */
1453 __IO uint32_t OR; /*!< Comparator option register, Address offset: 0x08 */
1454 } COMPOPT_TypeDef;
1455
1456 typedef struct
1457 {
1458 __IO uint32_t CFGR; /*!< Comparator configuration register , Address offset: 0x00 */
1459 } COMP_TypeDef;
1460
1461 typedef struct
1462 {
1463 __IO uint32_t CFGR; /*!< COMP control and status register, used for bits common to several COMP instances, Address offset: 0x00 */
1464 } COMP_Common_TypeDef;
1465 /**
1466 * @brief Universal Synchronous Asynchronous Receiver Transmitter
1467 */
1468
1469 typedef struct
1470 {
1471 __IO uint32_t CR1; /*!< USART Control register 1, Address offset: 0x00 */
1472 __IO uint32_t CR2; /*!< USART Control register 2, Address offset: 0x04 */
1473 __IO uint32_t CR3; /*!< USART Control register 3, Address offset: 0x08 */
1474 __IO uint32_t BRR; /*!< USART Baud rate register, Address offset: 0x0C */
1475 __IO uint32_t GTPR; /*!< USART Guard time and prescaler register, Address offset: 0x10 */
1476 __IO uint32_t RTOR; /*!< USART Receiver Time Out register, Address offset: 0x14 */
1477 __IO uint32_t RQR; /*!< USART Request register, Address offset: 0x18 */
1478 __IO uint32_t ISR; /*!< USART Interrupt and status register, Address offset: 0x1C */
1479 __IO uint32_t ICR; /*!< USART Interrupt flag Clear register, Address offset: 0x20 */
1480 __IO uint32_t RDR; /*!< USART Receive Data register, Address offset: 0x24 */
1481 __IO uint32_t TDR; /*!< USART Transmit Data register, Address offset: 0x28 */
1482 __IO uint32_t PRESC; /*!< USART clock Prescaler register, Address offset: 0x2C */
1483 } USART_TypeDef;
1484
1485 /**
1486 * @brief Single Wire Protocol Master Interface SPWMI
1487 */
1488 typedef struct
1489 {
1490 __IO uint32_t CR; /*!< SWPMI Configuration/Control register, Address offset: 0x00 */
1491 __IO uint32_t BRR; /*!< SWPMI bitrate register, Address offset: 0x04 */
1492 uint32_t RESERVED1; /*!< Reserved, 0x08 */
1493 __IO uint32_t ISR; /*!< SWPMI Interrupt and Status register, Address offset: 0x0C */
1494 __IO uint32_t ICR; /*!< SWPMI Interrupt Flag Clear register, Address offset: 0x10 */
1495 __IO uint32_t IER; /*!< SWPMI Interrupt Enable register, Address offset: 0x14 */
1496 __IO uint32_t RFL; /*!< SWPMI Receive Frame Length register, Address offset: 0x18 */
1497 __IO uint32_t TDR; /*!< SWPMI Transmit data register, Address offset: 0x1C */
1498 __IO uint32_t RDR; /*!< SWPMI Receive data register, Address offset: 0x20 */
1499 __IO uint32_t OR; /*!< SWPMI Option register, Address offset: 0x24 */
1500 } SWPMI_TypeDef;
1501
1502 /**
1503 * @brief Window WATCHDOG
1504 */
1505
1506 typedef struct
1507 {
1508 __IO uint32_t CR; /*!< WWDG Control register, Address offset: 0x00 */
1509 __IO uint32_t CFR; /*!< WWDG Configuration register, Address offset: 0x04 */
1510 __IO uint32_t SR; /*!< WWDG Status register, Address offset: 0x08 */
1511 } WWDG_TypeDef;
1512
1513
1514 /**
1515 * @brief RAM_ECC_Specific_Registers
1516 */
1517 typedef struct
1518 {
1519 __IO uint32_t CR; /*!< RAMECC monitor configuration register */
1520 __IO uint32_t SR; /*!< RAMECC monitor status register */
1521 __IO uint32_t FAR; /*!< RAMECC monitor failing address register */
1522 __IO uint32_t FDRL; /*!< RAMECC monitor failing data low register */
1523 __IO uint32_t FDRH; /*!< RAMECC monitor failing data high register */
1524 __IO uint32_t FECR; /*!< RAMECC monitor failing ECC error code register */
1525 } RAMECC_MonitorTypeDef;
1526
1527 typedef struct
1528 {
1529 __IO uint32_t IER; /*!< RAMECC interrupt enable register */
1530 } RAMECC_TypeDef;
1531 /**
1532 * @}
1533 */
1534
1535
1536 /**
1537 * @brief Crypto Processor
1538 */
1539
1540 typedef struct
1541 {
1542 __IO uint32_t CR; /*!< CRYP control register, Address offset: 0x00 */
1543 __IO uint32_t SR; /*!< CRYP status register, Address offset: 0x04 */
1544 __IO uint32_t DIN; /*!< CRYP data input register, Address offset: 0x08 */
1545 __IO uint32_t DOUT; /*!< CRYP data output register, Address offset: 0x0C */
1546 __IO uint32_t DMACR; /*!< CRYP DMA control register, Address offset: 0x10 */
1547 __IO uint32_t IMSCR; /*!< CRYP interrupt mask set/clear register, Address offset: 0x14 */
1548 __IO uint32_t RISR; /*!< CRYP raw interrupt status register, Address offset: 0x18 */
1549 __IO uint32_t MISR; /*!< CRYP masked interrupt status register, Address offset: 0x1C */
1550 __IO uint32_t K0LR; /*!< CRYP key left register 0, Address offset: 0x20 */
1551 __IO uint32_t K0RR; /*!< CRYP key right register 0, Address offset: 0x24 */
1552 __IO uint32_t K1LR; /*!< CRYP key left register 1, Address offset: 0x28 */
1553 __IO uint32_t K1RR; /*!< CRYP key right register 1, Address offset: 0x2C */
1554 __IO uint32_t K2LR; /*!< CRYP key left register 2, Address offset: 0x30 */
1555 __IO uint32_t K2RR; /*!< CRYP key right register 2, Address offset: 0x34 */
1556 __IO uint32_t K3LR; /*!< CRYP key left register 3, Address offset: 0x38 */
1557 __IO uint32_t K3RR; /*!< CRYP key right register 3, Address offset: 0x3C */
1558 __IO uint32_t IV0LR; /*!< CRYP initialization vector left-word register 0, Address offset: 0x40 */
1559 __IO uint32_t IV0RR; /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
1560 __IO uint32_t IV1LR; /*!< CRYP initialization vector left-word register 1, Address offset: 0x48 */
1561 __IO uint32_t IV1RR; /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
1562 __IO uint32_t CSGCMCCM0R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 0, Address offset: 0x50 */
1563 __IO uint32_t CSGCMCCM1R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 1, Address offset: 0x54 */
1564 __IO uint32_t CSGCMCCM2R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 2, Address offset: 0x58 */
1565 __IO uint32_t CSGCMCCM3R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 3, Address offset: 0x5C */
1566 __IO uint32_t CSGCMCCM4R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 4, Address offset: 0x60 */
1567 __IO uint32_t CSGCMCCM5R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 5, Address offset: 0x64 */
1568 __IO uint32_t CSGCMCCM6R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 6, Address offset: 0x68 */
1569 __IO uint32_t CSGCMCCM7R; /*!< CRYP GCM/GMAC or CCM/CMAC context swap register 7, Address offset: 0x6C */
1570 __IO uint32_t CSGCM0R; /*!< CRYP GCM/GMAC context swap register 0, Address offset: 0x70 */
1571 __IO uint32_t CSGCM1R; /*!< CRYP GCM/GMAC context swap register 1, Address offset: 0x74 */
1572 __IO uint32_t CSGCM2R; /*!< CRYP GCM/GMAC context swap register 2, Address offset: 0x78 */
1573 __IO uint32_t CSGCM3R; /*!< CRYP GCM/GMAC context swap register 3, Address offset: 0x7C */
1574 __IO uint32_t CSGCM4R; /*!< CRYP GCM/GMAC context swap register 4, Address offset: 0x80 */
1575 __IO uint32_t CSGCM5R; /*!< CRYP GCM/GMAC context swap register 5, Address offset: 0x84 */
1576 __IO uint32_t CSGCM6R; /*!< CRYP GCM/GMAC context swap register 6, Address offset: 0x88 */
1577 __IO uint32_t CSGCM7R; /*!< CRYP GCM/GMAC context swap register 7, Address offset: 0x8C */
1578 } CRYP_TypeDef;
1579
1580 /**
1581 * @brief HASH
1582 */
1583
1584 typedef struct
1585 {
1586 __IO uint32_t CR; /*!< HASH control register, Address offset: 0x00 */
1587 __IO uint32_t DIN; /*!< HASH data input register, Address offset: 0x04 */
1588 __IO uint32_t STR; /*!< HASH start register, Address offset: 0x08 */
1589 __IO uint32_t HR[5]; /*!< HASH digest registers, Address offset: 0x0C-0x1C */
1590 __IO uint32_t IMR; /*!< HASH interrupt enable register, Address offset: 0x20 */
1591 __IO uint32_t SR; /*!< HASH status register, Address offset: 0x24 */
1592 uint32_t RESERVED[52]; /*!< Reserved, 0x28-0xF4 */
1593 __IO uint32_t CSR[54]; /*!< HASH context swap registers, Address offset: 0x0F8-0x1CC */
1594 } HASH_TypeDef;
1595
1596 /**
1597 * @brief HASH_DIGEST
1598 */
1599
1600 typedef struct
1601 {
1602 __IO uint32_t HR[8]; /*!< HASH digest registers, Address offset: 0x310-0x32C */
1603 } HASH_DIGEST_TypeDef;
1604
1605
1606 /**
1607 * @brief RNG
1608 */
1609
1610 typedef struct
1611 {
1612 __IO uint32_t CR; /*!< RNG control register, Address offset: 0x00 */
1613 __IO uint32_t SR; /*!< RNG status register, Address offset: 0x04 */
1614 __IO uint32_t DR; /*!< RNG data register, Address offset: 0x08 */
1615 uint32_t RESERVED;
1616 __IO uint32_t HTCR; /*!< RNG health test configuration register, Address offset: 0x10 */
1617 } RNG_TypeDef;
1618
1619 /**
1620 * @brief MDIOS
1621 */
1622
1623 typedef struct
1624 {
1625 __IO uint32_t CR;
1626 __IO uint32_t WRFR;
1627 __IO uint32_t CWRFR;
1628 __IO uint32_t RDFR;
1629 __IO uint32_t CRDFR;
1630 __IO uint32_t SR;
1631 __IO uint32_t CLRFR;
1632 uint32_t RESERVED[57];
1633 __IO uint32_t DINR0;
1634 __IO uint32_t DINR1;
1635 __IO uint32_t DINR2;
1636 __IO uint32_t DINR3;
1637 __IO uint32_t DINR4;
1638 __IO uint32_t DINR5;
1639 __IO uint32_t DINR6;
1640 __IO uint32_t DINR7;
1641 __IO uint32_t DINR8;
1642 __IO uint32_t DINR9;
1643 __IO uint32_t DINR10;
1644 __IO uint32_t DINR11;
1645 __IO uint32_t DINR12;
1646 __IO uint32_t DINR13;
1647 __IO uint32_t DINR14;
1648 __IO uint32_t DINR15;
1649 __IO uint32_t DINR16;
1650 __IO uint32_t DINR17;
1651 __IO uint32_t DINR18;
1652 __IO uint32_t DINR19;
1653 __IO uint32_t DINR20;
1654 __IO uint32_t DINR21;
1655 __IO uint32_t DINR22;
1656 __IO uint32_t DINR23;
1657 __IO uint32_t DINR24;
1658 __IO uint32_t DINR25;
1659 __IO uint32_t DINR26;
1660 __IO uint32_t DINR27;
1661 __IO uint32_t DINR28;
1662 __IO uint32_t DINR29;
1663 __IO uint32_t DINR30;
1664 __IO uint32_t DINR31;
1665 __IO uint32_t DOUTR0;
1666 __IO uint32_t DOUTR1;
1667 __IO uint32_t DOUTR2;
1668 __IO uint32_t DOUTR3;
1669 __IO uint32_t DOUTR4;
1670 __IO uint32_t DOUTR5;
1671 __IO uint32_t DOUTR6;
1672 __IO uint32_t DOUTR7;
1673 __IO uint32_t DOUTR8;
1674 __IO uint32_t DOUTR9;
1675 __IO uint32_t DOUTR10;
1676 __IO uint32_t DOUTR11;
1677 __IO uint32_t DOUTR12;
1678 __IO uint32_t DOUTR13;
1679 __IO uint32_t DOUTR14;
1680 __IO uint32_t DOUTR15;
1681 __IO uint32_t DOUTR16;
1682 __IO uint32_t DOUTR17;
1683 __IO uint32_t DOUTR18;
1684 __IO uint32_t DOUTR19;
1685 __IO uint32_t DOUTR20;
1686 __IO uint32_t DOUTR21;
1687 __IO uint32_t DOUTR22;
1688 __IO uint32_t DOUTR23;
1689 __IO uint32_t DOUTR24;
1690 __IO uint32_t DOUTR25;
1691 __IO uint32_t DOUTR26;
1692 __IO uint32_t DOUTR27;
1693 __IO uint32_t DOUTR28;
1694 __IO uint32_t DOUTR29;
1695 __IO uint32_t DOUTR30;
1696 __IO uint32_t DOUTR31;
1697 } MDIOS_TypeDef;
1698
1699
1700 /**
1701 * @brief USB_OTG_Core_Registers
1702 */
1703 typedef struct
1704 {
1705 __IO uint32_t GOTGCTL; /*!< USB_OTG Control and Status Register 000h */
1706 __IO uint32_t GOTGINT; /*!< USB_OTG Interrupt Register 004h */
1707 __IO uint32_t GAHBCFG; /*!< Core AHB Configuration Register 008h */
1708 __IO uint32_t GUSBCFG; /*!< Core USB Configuration Register 00Ch */
1709 __IO uint32_t GRSTCTL; /*!< Core Reset Register 010h */
1710 __IO uint32_t GINTSTS; /*!< Core Interrupt Register 014h */
1711 __IO uint32_t GINTMSK; /*!< Core Interrupt Mask Register 018h */
1712 __IO uint32_t GRXSTSR; /*!< Receive Sts Q Read Register 01Ch */
1713 __IO uint32_t GRXSTSP; /*!< Receive Sts Q Read & POP Register 020h */
1714 __IO uint32_t GRXFSIZ; /*!< Receive FIFO Size Register 024h */
1715 __IO uint32_t DIEPTXF0_HNPTXFSIZ; /*!< EP0 / Non Periodic Tx FIFO Size Register 028h */
1716 __IO uint32_t HNPTXSTS; /*!< Non Periodic Tx FIFO/Queue Sts reg 02Ch */
1717 uint32_t Reserved30[2]; /*!< Reserved 030h */
1718 __IO uint32_t GCCFG; /*!< General Purpose IO Register 038h */
1719 __IO uint32_t CID; /*!< User ID Register 03Ch */
1720 __IO uint32_t GSNPSID; /* USB_OTG core ID 040h*/
1721 __IO uint32_t GHWCFG1; /* User HW config1 044h*/
1722 __IO uint32_t GHWCFG2; /* User HW config2 048h*/
1723 __IO uint32_t GHWCFG3; /*!< User HW config3 04Ch */
1724 uint32_t Reserved6; /*!< Reserved 050h */
1725 __IO uint32_t GLPMCFG; /*!< LPM Register 054h */
1726 __IO uint32_t GPWRDN; /*!< Power Down Register 058h */
1727 __IO uint32_t GDFIFOCFG; /*!< DFIFO Software Config Register 05Ch */
1728 __IO uint32_t GADPCTL; /*!< ADP Timer, Control and Status Register 60Ch */
1729 uint32_t Reserved43[39]; /*!< Reserved 058h-0FFh */
1730 __IO uint32_t HPTXFSIZ; /*!< Host Periodic Tx FIFO Size Reg 100h */
1731 __IO uint32_t DIEPTXF[0x0F]; /*!< dev Periodic Transmit FIFO */
1732 } USB_OTG_GlobalTypeDef;
1733
1734
1735 /**
1736 * @brief USB_OTG_device_Registers
1737 */
1738 typedef struct
1739 {
1740 __IO uint32_t DCFG; /*!< dev Configuration Register 800h */
1741 __IO uint32_t DCTL; /*!< dev Control Register 804h */
1742 __IO uint32_t DSTS; /*!< dev Status Register (RO) 808h */
1743 uint32_t Reserved0C; /*!< Reserved 80Ch */
1744 __IO uint32_t DIEPMSK; /*!< dev IN Endpoint Mask 810h */
1745 __IO uint32_t DOEPMSK; /*!< dev OUT Endpoint Mask 814h */
1746 __IO uint32_t DAINT; /*!< dev All Endpoints Itr Reg 818h */
1747 __IO uint32_t DAINTMSK; /*!< dev All Endpoints Itr Mask 81Ch */
1748 uint32_t Reserved20; /*!< Reserved 820h */
1749 uint32_t Reserved9; /*!< Reserved 824h */
1750 __IO uint32_t DVBUSDIS; /*!< dev VBUS discharge Register 828h */
1751 __IO uint32_t DVBUSPULSE; /*!< dev VBUS Pulse Register 82Ch */
1752 __IO uint32_t DTHRCTL; /*!< dev threshold 830h */
1753 __IO uint32_t DIEPEMPMSK; /*!< dev empty msk 834h */
1754 __IO uint32_t DEACHINT; /*!< dedicated EP interrupt 838h */
1755 __IO uint32_t DEACHMSK; /*!< dedicated EP msk 83Ch */
1756 uint32_t Reserved40; /*!< dedicated EP mask 840h */
1757 __IO uint32_t DINEP1MSK; /*!< dedicated EP mask 844h */
1758 uint32_t Reserved44[15]; /*!< Reserved 844-87Ch */
1759 __IO uint32_t DOUTEP1MSK; /*!< dedicated EP msk 884h */
1760 } USB_OTG_DeviceTypeDef;
1761
1762
1763 /**
1764 * @brief USB_OTG_IN_Endpoint-Specific_Register
1765 */
1766 typedef struct
1767 {
1768 __IO uint32_t DIEPCTL; /*!< dev IN Endpoint Control Reg 900h + (ep_num * 20h) + 00h */
1769 uint32_t Reserved04; /*!< Reserved 900h + (ep_num * 20h) + 04h */
1770 __IO uint32_t DIEPINT; /*!< dev IN Endpoint Itr Reg 900h + (ep_num * 20h) + 08h */
1771 uint32_t Reserved0C; /*!< Reserved 900h + (ep_num * 20h) + 0Ch */
1772 __IO uint32_t DIEPTSIZ; /*!< IN Endpoint Txfer Size 900h + (ep_num * 20h) + 10h */
1773 __IO uint32_t DIEPDMA; /*!< IN Endpoint DMA Address Reg 900h + (ep_num * 20h) + 14h */
1774 __IO uint32_t DTXFSTS; /*!< IN Endpoint Tx FIFO Status Reg 900h + (ep_num * 20h) + 18h */
1775 uint32_t Reserved18; /*!< Reserved 900h+(ep_num*20h)+1Ch-900h+ (ep_num * 20h) + 1Ch */
1776 } USB_OTG_INEndpointTypeDef;
1777
1778
1779 /**
1780 * @brief USB_OTG_OUT_Endpoint-Specific_Registers
1781 */
1782 typedef struct
1783 {
1784 __IO uint32_t DOEPCTL; /*!< dev OUT Endpoint Control Reg B00h + (ep_num * 20h) + 00h */
1785 uint32_t Reserved04; /*!< Reserved B00h + (ep_num * 20h) + 04h */
1786 __IO uint32_t DOEPINT; /*!< dev OUT Endpoint Itr Reg B00h + (ep_num * 20h) + 08h */
1787 uint32_t Reserved0C; /*!< Reserved B00h + (ep_num * 20h) + 0Ch */
1788 __IO uint32_t DOEPTSIZ; /*!< dev OUT Endpoint Txfer Size B00h + (ep_num * 20h) + 10h */
1789 __IO uint32_t DOEPDMA; /*!< dev OUT Endpoint DMA Address B00h + (ep_num * 20h) + 14h */
1790 uint32_t Reserved18[2]; /*!< Reserved B00h + (ep_num * 20h) + 18h - B00h + (ep_num * 20h) + 1Ch */
1791 } USB_OTG_OUTEndpointTypeDef;
1792
1793
1794 /**
1795 * @brief USB_OTG_Host_Mode_Register_Structures
1796 */
1797 typedef struct
1798 {
1799 __IO uint32_t HCFG; /*!< Host Configuration Register 400h */
1800 __IO uint32_t HFIR; /*!< Host Frame Interval Register 404h */
1801 __IO uint32_t HFNUM; /*!< Host Frame Nbr/Frame Remaining 408h */
1802 uint32_t Reserved40C; /*!< Reserved 40Ch */
1803 __IO uint32_t HPTXSTS; /*!< Host Periodic Tx FIFO/ Queue Status 410h */
1804 __IO uint32_t HAINT; /*!< Host All Channels Interrupt Register 414h */
1805 __IO uint32_t HAINTMSK; /*!< Host All Channels Interrupt Mask 418h */
1806 } USB_OTG_HostTypeDef;
1807
1808 /**
1809 * @brief USB_OTG_Host_Channel_Specific_Registers
1810 */
1811 typedef struct
1812 {
1813 __IO uint32_t HCCHAR; /*!< Host Channel Characteristics Register 500h */
1814 __IO uint32_t HCSPLT; /*!< Host Channel Split Control Register 504h */
1815 __IO uint32_t HCINT; /*!< Host Channel Interrupt Register 508h */
1816 __IO uint32_t HCINTMSK; /*!< Host Channel Interrupt Mask Register 50Ch */
1817 __IO uint32_t HCTSIZ; /*!< Host Channel Transfer Size Register 510h */
1818 __IO uint32_t HCDMA; /*!< Host Channel DMA Address Register 514h */
1819 uint32_t Reserved[2]; /*!< Reserved */
1820 } USB_OTG_HostChannelTypeDef;
1821 /**
1822 * @}
1823 */
1824
1825 /**
1826 * @brief OCTO Serial Peripheral Interface
1827 */
1828
1829 typedef struct
1830 {
1831 __IO uint32_t CR; /*!< OCTOSPI Control register, Address offset: 0x000 */
1832 uint32_t RESERVED; /*!< Reserved, Address offset: 0x004 */
1833 __IO uint32_t DCR1; /*!< OCTOSPI Device Configuration register 1, Address offset: 0x008 */
1834 __IO uint32_t DCR2; /*!< OCTOSPI Device Configuration register 2, Address offset: 0x00C */
1835 __IO uint32_t DCR3; /*!< OCTOSPI Device Configuration register 3, Address offset: 0x010 */
1836 __IO uint32_t DCR4; /*!< OCTOSPI Device Configuration register 4, Address offset: 0x014 */
1837 uint32_t RESERVED1[2]; /*!< Reserved, Address offset: 0x018-0x01C */
1838 __IO uint32_t SR; /*!< OCTOSPI Status register, Address offset: 0x020 */
1839 __IO uint32_t FCR; /*!< OCTOSPI Flag Clear register, Address offset: 0x024 */
1840 uint32_t RESERVED2[6]; /*!< Reserved, Address offset: 0x028-0x03C */
1841 __IO uint32_t DLR; /*!< OCTOSPI Data Length register, Address offset: 0x040 */
1842 uint32_t RESERVED3; /*!< Reserved, Address offset: 0x044 */
1843 __IO uint32_t AR; /*!< OCTOSPI Address register, Address offset: 0x048 */
1844 uint32_t RESERVED4; /*!< Reserved, Address offset: 0x04C */
1845 __IO uint32_t DR; /*!< OCTOSPI Data register, Address offset: 0x050 */
1846 uint32_t RESERVED5[11]; /*!< Reserved, Address offset: 0x054-0x07C */
1847 __IO uint32_t PSMKR; /*!< OCTOSPI Polling Status Mask register, Address offset: 0x080 */
1848 uint32_t RESERVED6; /*!< Reserved, Address offset: 0x084 */
1849 __IO uint32_t PSMAR; /*!< OCTOSPI Polling Status Match register, Address offset: 0x088 */
1850 uint32_t RESERVED7; /*!< Reserved, Address offset: 0x08C */
1851 __IO uint32_t PIR; /*!< OCTOSPI Polling Interval register, Address offset: 0x090 */
1852 uint32_t RESERVED8[27]; /*!< Reserved, Address offset: 0x094-0x0FC */
1853 __IO uint32_t CCR; /*!< OCTOSPI Communication Configuration register, Address offset: 0x100 */
1854 uint32_t RESERVED9; /*!< Reserved, Address offset: 0x104 */
1855 __IO uint32_t TCR; /*!< OCTOSPI Timing Configuration register, Address offset: 0x108 */
1856 uint32_t RESERVED10; /*!< Reserved, Address offset: 0x10C */
1857 __IO uint32_t IR; /*!< OCTOSPI Instruction register, Address offset: 0x110 */
1858 uint32_t RESERVED11[3]; /*!< Reserved, Address offset: 0x114-0x11C */
1859 __IO uint32_t ABR; /*!< OCTOSPI Alternate Bytes register, Address offset: 0x120 */
1860 uint32_t RESERVED12[3]; /*!< Reserved, Address offset: 0x124-0x12C */
1861 __IO uint32_t LPTR; /*!< OCTOSPI Low Power Timeout register, Address offset: 0x130 */
1862 uint32_t RESERVED13[3]; /*!< Reserved, Address offset: 0x134-0x13C */
1863 __IO uint32_t WPCCR; /*!< OCTOSPI Wrap Communication Configuration register, Address offset: 0x140 */
1864 uint32_t RESERVED14; /*!< Reserved, Address offset: 0x144 */
1865 __IO uint32_t WPTCR; /*!< OCTOSPI Wrap Timing Configuration register, Address offset: 0x148 */
1866 uint32_t RESERVED15; /*!< Reserved, Address offset: 0x14C */
1867 __IO uint32_t WPIR; /*!< OCTOSPI Wrap Instruction register, Address offset: 0x150 */
1868 uint32_t RESERVED16[3]; /*!< Reserved, Address offset: 0x154-0x15C */
1869 __IO uint32_t WPABR; /*!< OCTOSPI Wrap Alternate Bytes register, Address offset: 0x160 */
1870 uint32_t RESERVED17[7]; /*!< Reserved, Address offset: 0x164-0x17C */
1871 __IO uint32_t WCCR; /*!< OCTOSPI Write Communication Configuration register, Address offset: 0x180 */
1872 uint32_t RESERVED18; /*!< Reserved, Address offset: 0x184 */
1873 __IO uint32_t WTCR; /*!< OCTOSPI Write Timing Configuration register, Address offset: 0x188 */
1874 uint32_t RESERVED19; /*!< Reserved, Address offset: 0x18C */
1875 __IO uint32_t WIR; /*!< OCTOSPI Write Instruction register, Address offset: 0x190 */
1876 uint32_t RESERVED20[3]; /*!< Reserved, Address offset: 0x194-0x19C */
1877 __IO uint32_t WABR; /*!< OCTOSPI Write Alternate Bytes register, Address offset: 0x1A0 */
1878 uint32_t RESERVED21[23]; /*!< Reserved, Address offset: 0x1A4-0x1FC */
1879 __IO uint32_t HLCR; /*!< OCTOSPI Hyperbus Latency Configuration register, Address offset: 0x200 */
1880 uint32_t RESERVED22[122]; /*!< Reserved, Address offset: 0x204-0x3EC */
1881 __IO uint32_t HWCFGR; /*!< OCTOSPI HW Configuration register, Address offset: 0x3F0 */
1882 __IO uint32_t VER; /*!< OCTOSPI Version register, Address offset: 0x3F4 */
1883 __IO uint32_t ID; /*!< OCTOSPI Identification register, Address offset: 0x3F8 */
1884 __IO uint32_t MID; /*!< OCTOPSI HW Magic ID register, Address offset: 0x3FC */
1885 } OCTOSPI_TypeDef;
1886
1887 /**
1888 * @}
1889 */
1890 /**
1891 * @brief OCTO Serial Peripheral Interface IO Manager
1892 */
1893
1894 typedef struct
1895 {
1896 __IO uint32_t CR; /*!< OCTOSPI IO Manager Control register, Address offset: 0x00 */
1897 __IO uint32_t PCR[8]; /*!< OCTOSPI IO Manager Port[1:8] Configuration register, Address offset: 0x04-0x20 */
1898 } OCTOSPIM_TypeDef;
1899
1900 /**
1901 * @}
1902 */
1903
1904 /**
1905 * @brief OTFD register
1906 */
1907 typedef struct
1908 {
1909 __IO uint32_t REG_CONFIGR;
1910 __IO uint32_t REG_START_ADDR;
1911 __IO uint32_t REG_END_ADDR;
1912 __IO uint32_t REG_NONCER0;
1913 __IO uint32_t REG_NONCER1;
1914 __IO uint32_t REG_KEYR0;
1915 __IO uint32_t REG_KEYR1;
1916 __IO uint32_t REG_KEYR2;
1917 __IO uint32_t REG_KEYR3;
1918 } OTFDEC_Region_TypeDef;
1919
1920 typedef struct
1921 {
1922 __IO uint32_t CR;
1923 uint32_t RESERVED1[191];
1924 __IO uint32_t ISR;
1925 __IO uint32_t ICR;
1926 __IO uint32_t IER;
1927 uint32_t RESERVED2[56];
1928 __IO uint32_t HWCFGR2;
1929 __IO uint32_t HWCFGR1;
1930 __IO uint32_t VERR;
1931 __IO uint32_t IPIDR;
1932 __IO uint32_t SIDR;
1933 } OTFDEC_TypeDef;
1934 /**
1935 * @}
1936 */
1937
1938 /** @addtogroup Peripheral_memory_map
1939 * @{
1940 */
1941 #define CD_ITCMRAM_BASE (0x00000000UL) /*!< Base address of : 64KB RAM reserved for CPU execution/instruction accessible over ITCM */
1942 #define CD_DTCMRAM_BASE (0x20000000UL) /*!< Base address of : 128KB (2x64KB) system data RAM accessible over DTCM */
1943 #define CD_AXIFLASH_BASE (0x08000000UL) /*!< Base address of : (up to 2 MB) embedded FLASH memory accessible over AXI */
1944
1945 #define CD_AXISRAM1_BASE (0x24000000UL) /*!< Base address of : (up to 256KB) system data RAM1 accessible over over AXI */
1946 #define CD_AXISRAM2_BASE (0x24040000UL) /*!< Base address of : (up to 384KB) system data RAM2 accessible over over AXI */
1947 #define CD_AXISRAM3_BASE (0x240A0000UL) /*!< Base address of : (up to 384KB) system data RAM3 accessible over over AXI */
1948 #define CD_AHBSRAM1_BASE (0x30000000UL) /*!< Base address of : (up to 64KB) system data RAM1 accessible over over AXI->AHB Bridge */
1949 #define CD_AHBSRAM2_BASE (0x30010000UL) /*!< Base address of : (up to 64KB) system data RAM2 accessible over over AXI->AHB Bridge */
1950
1951 #define SRD_BKPSRAM_BASE (0x38800000UL) /*!< Base address of : Backup SRAM(4 KB) over AXI->AHB Bridge */
1952 #define SRD_SRAM_BASE (0x38000000UL) /*!< Base address of : Backup SRAM(32 KB) over AXI->AHB Bridge */
1953
1954 #define OCTOSPI1_BASE (0x90000000UL) /*!< Base address of : OCTOSPI1 memories accessible over AXI */
1955 #define OCTOSPI2_BASE (0x70000000UL) /*!< Base address of : OCTOSPI2 memories accessible over AXI */
1956
1957 #define FLASH_BANK1_BASE (0x08000000UL) /*!< Base address of : (up to 128 KB) Flash Bank1 accessible over AXI */
1958 #define FLASH_BANK2_BASE (0x08100000UL) /*!< For legacy only , Flash bank 2 not available on STM32H7B0xx value line */
1959 #define FLASH_END (0x0801FFFFUL) /*!< FLASH end address */
1960
1961 /* Legacy define */
1962 #define FLASH_BASE FLASH_BANK1_BASE
1963 #define D1_AXISRAM_BASE CD_AXISRAM1_BASE
1964
1965 #define FLASH_OTP_BASE (0x08FFF000UL) /*!< Base address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1966 #define FLASH_OTP_END (0x08FFF3FFUL) /*!< End address of : (up to 1KB) embedded FLASH Bank1 OTP Area */
1967
1968
1969 /*!< Device electronic signature memory map */
1970 #define UID_BASE (0x08FFF800UL) /*!< Unique device ID register base address */
1971 #define FLASHSIZE_BASE (0x08FFF80CUL) /*!< FLASH Size register base address */
1972 #define PACKAGE_BASE (0x08FFF80EUL) /*!< Package Data register base address */
1973
1974 #define PERIPH_BASE (0x40000000UL) /*!< Base address of : AHB/ABP Peripherals */
1975 /*!< Peripheral memory map */
1976 #define CD_APB1PERIPH_BASE PERIPH_BASE /*!< D2_APB1PERIPH_BASE PERIPH_BASE */
1977 #define CD_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) /*!< D2_APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL) */
1978 #define CD_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) /*!< D2_AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL) */
1979 #define CD_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) /*!< D2_AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL) */
1980
1981 #define CD_APB3PERIPH_BASE (PERIPH_BASE + 0x10000000UL) /*!< D1_APB1PERIPH_BASE (PERIPH_BASE + 0x10000000UL) */
1982 #define CD_AHB3PERIPH_BASE (PERIPH_BASE + 0x12000000UL) /*!< D1_AHB1PERIPH_BASE (PERIPH_BASE + 0x12000000UL) */
1983
1984 #define SRD_APB4PERIPH_BASE (PERIPH_BASE + 0x18000000UL) /*!< D3_APB1PERIPH_BASE (PERIPH_BASE + 0x18000000UL) */
1985 #define SRD_AHB4PERIPH_BASE (PERIPH_BASE + 0x18020000UL) /*!< D3_AHB1PERIPH_BASE (PERIPH_BASE + 0x18020000UL) */
1986
1987 /*!< Legacy Peripheral memory map */
1988 #define APB1PERIPH_BASE PERIPH_BASE
1989 #define APB2PERIPH_BASE (PERIPH_BASE + 0x00010000UL)
1990 #define AHB1PERIPH_BASE (PERIPH_BASE + 0x00020000UL)
1991 #define AHB2PERIPH_BASE (PERIPH_BASE + 0x08020000UL)
1992
1993 /*!< CD_AHB3PERIPH peripherals */
1994 #define MDMA_BASE (CD_AHB3PERIPH_BASE + 0x0000UL)
1995 #define DMA2D_BASE (CD_AHB3PERIPH_BASE + 0x1000UL)
1996 #define FLASH_R_BASE (CD_AHB3PERIPH_BASE + 0x2000UL)
1997 #define JPGDEC_BASE (CD_AHB3PERIPH_BASE + 0x3000UL)
1998 #define FMC_R_BASE (CD_AHB3PERIPH_BASE + 0x4000UL)
1999 #define OCTOSPI1_R_BASE (CD_AHB3PERIPH_BASE + 0x5000UL)
2000 #define DLYB_OCTOSPI1_BASE (CD_AHB3PERIPH_BASE + 0x6000UL)
2001 #define SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x7000UL)
2002 #define DLYB_SDMMC1_BASE (CD_AHB3PERIPH_BASE + 0x8000UL)
2003 #define RAMECC_BASE (CD_AHB3PERIPH_BASE + 0x9000UL)
2004 #define OCTOSPI2_R_BASE (CD_AHB3PERIPH_BASE + 0xA000UL)
2005 #define DLYB_OCTOSPI2_BASE (CD_AHB3PERIPH_BASE + 0xB000UL)
2006 #define OCTOSPIM_BASE (CD_AHB3PERIPH_BASE + 0xB400UL)
2007
2008 /*!< CD_AHB1PERIPH peripherals */
2009
2010 #define DMA1_BASE (CD_AHB1PERIPH_BASE + 0x0000UL)
2011 #define DMA2_BASE (CD_AHB1PERIPH_BASE + 0x0400UL)
2012 #define DMAMUX1_BASE (CD_AHB1PERIPH_BASE + 0x0800UL)
2013 #define ADC1_BASE (CD_AHB1PERIPH_BASE + 0x2000UL)
2014 #define ADC2_BASE (CD_AHB1PERIPH_BASE + 0x2100UL)
2015 #define ADC12_COMMON_BASE (CD_AHB1PERIPH_BASE + 0x2300UL)
2016 #define CRC_BASE (CD_AHB1PERIPH_BASE + 0x3000UL)
2017
2018 /*!< USB registers base address */
2019 #define USB1_OTG_HS_PERIPH_BASE (0x40040000UL)
2020 #define USB_OTG_GLOBAL_BASE (0x000UL)
2021 #define USB_OTG_DEVICE_BASE (0x800UL)
2022 #define USB_OTG_IN_ENDPOINT_BASE (0x900UL)
2023 #define USB_OTG_OUT_ENDPOINT_BASE (0xB00UL)
2024 #define USB_OTG_EP_REG_SIZE (0x20UL)
2025 #define USB_OTG_HOST_BASE (0x400UL)
2026 #define USB_OTG_HOST_PORT_BASE (0x440UL)
2027 #define USB_OTG_HOST_CHANNEL_BASE (0x500UL)
2028 #define USB_OTG_HOST_CHANNEL_SIZE (0x20UL)
2029 #define USB_OTG_PCGCCTL_BASE (0xE00UL)
2030 #define USB_OTG_FIFO_BASE (0x1000UL)
2031 #define USB_OTG_FIFO_SIZE (0x1000UL)
2032
2033 /*!< CD_AHB2PERIPH peripherals */
2034
2035 #define DCMI_BASE (CD_AHB2PERIPH_BASE + 0x0000UL)
2036 #define PSSI_BASE (CD_AHB2PERIPH_BASE + 0x0400UL)
2037 #define HSEM_BASE (CD_AHB2PERIPH_BASE + 0x0800UL)
2038 #define CRYP_BASE (CD_AHB2PERIPH_BASE + 0x1000UL)
2039 #define HASH_BASE (CD_AHB2PERIPH_BASE + 0x1400UL)
2040 #define HASH_DIGEST_BASE (CD_AHB2PERIPH_BASE + 0x1710UL)
2041 #define RNG_BASE (CD_AHB2PERIPH_BASE + 0x1800UL)
2042 #define SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2400UL)
2043 #define DLYB_SDMMC2_BASE (CD_AHB2PERIPH_BASE + 0x2800UL)
2044 #define BDMA1_BASE (CD_AHB2PERIPH_BASE + 0x2C00UL)
2045
2046 /*!< SRD_AHB4PERIPH peripherals */
2047 #define GPIOA_BASE (SRD_AHB4PERIPH_BASE + 0x0000UL)
2048 #define GPIOB_BASE (SRD_AHB4PERIPH_BASE + 0x0400UL)
2049 #define GPIOC_BASE (SRD_AHB4PERIPH_BASE + 0x0800UL)
2050 #define GPIOD_BASE (SRD_AHB4PERIPH_BASE + 0x0C00UL)
2051 #define GPIOE_BASE (SRD_AHB4PERIPH_BASE + 0x1000UL)
2052 #define GPIOF_BASE (SRD_AHB4PERIPH_BASE + 0x1400UL)
2053 #define GPIOG_BASE (SRD_AHB4PERIPH_BASE + 0x1800UL)
2054 #define GPIOH_BASE (SRD_AHB4PERIPH_BASE + 0x1C00UL)
2055 #define GPIOI_BASE (SRD_AHB4PERIPH_BASE + 0x2000UL)
2056 #define GPIOJ_BASE (SRD_AHB4PERIPH_BASE + 0x2400UL)
2057 #define GPIOK_BASE (SRD_AHB4PERIPH_BASE + 0x2800UL)
2058 #define RCC_BASE (SRD_AHB4PERIPH_BASE + 0x4400UL)
2059 #define PWR_BASE (SRD_AHB4PERIPH_BASE + 0x4800UL)
2060 #define BDMA2_BASE (SRD_AHB4PERIPH_BASE + 0x5400UL)
2061 #define DMAMUX2_BASE (SRD_AHB4PERIPH_BASE + 0x5800UL)
2062
2063 /*!< CD_APB3PERIPH peripherals */
2064 #define LTDC_BASE (CD_APB3PERIPH_BASE + 0x1000UL)
2065 #define LTDC_Layer1_BASE (LTDC_BASE + 0x84UL)
2066 #define LTDC_Layer2_BASE (LTDC_BASE + 0x104UL)
2067 #define WWDG1_BASE (CD_APB3PERIPH_BASE + 0x3000UL)
2068
2069 /*!< CD_APB1PERIPH peripherals */
2070 #define TIM2_BASE (CD_APB1PERIPH_BASE + 0x0000UL)
2071 #define TIM3_BASE (CD_APB1PERIPH_BASE + 0x0400UL)
2072 #define TIM4_BASE (CD_APB1PERIPH_BASE + 0x0800UL)
2073 #define TIM5_BASE (CD_APB1PERIPH_BASE + 0x0C00UL)
2074 #define TIM6_BASE (CD_APB1PERIPH_BASE + 0x1000UL)
2075 #define TIM7_BASE (CD_APB1PERIPH_BASE + 0x1400UL)
2076 #define TIM12_BASE (CD_APB1PERIPH_BASE + 0x1800UL)
2077 #define TIM13_BASE (CD_APB1PERIPH_BASE + 0x1C00UL)
2078 #define TIM14_BASE (CD_APB1PERIPH_BASE + 0x2000UL)
2079 #define LPTIM1_BASE (CD_APB1PERIPH_BASE + 0x2400UL)
2080
2081 #define SPI2_BASE (CD_APB1PERIPH_BASE + 0x3800UL)
2082 #define SPI3_BASE (CD_APB1PERIPH_BASE + 0x3C00UL)
2083 #define SPDIFRX_BASE (CD_APB1PERIPH_BASE + 0x4000UL)
2084 #define USART2_BASE (CD_APB1PERIPH_BASE + 0x4400UL)
2085 #define USART3_BASE (CD_APB1PERIPH_BASE + 0x4800UL)
2086 #define UART4_BASE (CD_APB1PERIPH_BASE + 0x4C00UL)
2087 #define UART5_BASE (CD_APB1PERIPH_BASE + 0x5000UL)
2088 #define I2C1_BASE (CD_APB1PERIPH_BASE + 0x5400UL)
2089 #define I2C2_BASE (CD_APB1PERIPH_BASE + 0x5800UL)
2090 #define I2C3_BASE (CD_APB1PERIPH_BASE + 0x5C00UL)
2091 #define CEC_BASE (CD_APB1PERIPH_BASE + 0x6C00UL)
2092 #define DAC1_BASE (CD_APB1PERIPH_BASE + 0x7400UL)
2093 #define UART7_BASE (CD_APB1PERIPH_BASE + 0x7800UL)
2094 #define UART8_BASE (CD_APB1PERIPH_BASE + 0x7C00UL)
2095 #define CRS_BASE (CD_APB1PERIPH_BASE + 0x8400UL)
2096 #define SWPMI1_BASE (CD_APB1PERIPH_BASE + 0x8800UL)
2097 #define OPAMP_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2098 #define OPAMP1_BASE (CD_APB1PERIPH_BASE + 0x9000UL)
2099 #define OPAMP2_BASE (CD_APB1PERIPH_BASE + 0x9010UL)
2100 #define MDIOS_BASE (CD_APB1PERIPH_BASE + 0x9400UL)
2101 #define FDCAN1_BASE (CD_APB1PERIPH_BASE + 0xA000UL)
2102 #define FDCAN2_BASE (CD_APB1PERIPH_BASE + 0xA400UL)
2103 #define FDCAN_CCU_BASE (CD_APB1PERIPH_BASE + 0xA800UL)
2104 #define SRAMCAN_BASE (CD_APB1PERIPH_BASE + 0xAC00UL)
2105
2106 /*!< CD_APB2PERIPH peripherals */
2107
2108 #define TIM1_BASE (CD_APB2PERIPH_BASE + 0x0000UL)
2109 #define TIM8_BASE (CD_APB2PERIPH_BASE + 0x0400UL)
2110 #define USART1_BASE (CD_APB2PERIPH_BASE + 0x1000UL)
2111 #define USART6_BASE (CD_APB2PERIPH_BASE + 0x1400UL)
2112 #define UART9_BASE (CD_APB2PERIPH_BASE + 0x1800UL)
2113 #define USART10_BASE (CD_APB2PERIPH_BASE + 0x1C00UL)
2114 #define SPI1_BASE (CD_APB2PERIPH_BASE + 0x3000UL)
2115 #define SPI4_BASE (CD_APB2PERIPH_BASE + 0x3400UL)
2116 #define TIM15_BASE (CD_APB2PERIPH_BASE + 0x4000UL)
2117 #define TIM16_BASE (CD_APB2PERIPH_BASE + 0x4400UL)
2118 #define TIM17_BASE (CD_APB2PERIPH_BASE + 0x4800UL)
2119 #define SPI5_BASE (CD_APB2PERIPH_BASE + 0x5000UL)
2120 #define SAI1_BASE (CD_APB2PERIPH_BASE + 0x5800UL)
2121 #define SAI1_Block_A_BASE (SAI1_BASE + 0x004UL)
2122 #define SAI1_Block_B_BASE (SAI1_BASE + 0x024UL)
2123 #define SAI2_BASE (CD_APB2PERIPH_BASE + 0x5C00UL)
2124 #define SAI2_Block_A_BASE (SAI2_BASE + 0x004UL)
2125 #define SAI2_Block_B_BASE (SAI2_BASE + 0x024UL)
2126 #define DFSDM1_BASE (CD_APB2PERIPH_BASE + 0x7800UL)
2127 #define DFSDM1_Channel0_BASE (DFSDM1_BASE + 0x00UL)
2128 #define DFSDM1_Channel1_BASE (DFSDM1_BASE + 0x20UL)
2129 #define DFSDM1_Channel2_BASE (DFSDM1_BASE + 0x40UL)
2130 #define DFSDM1_Channel3_BASE (DFSDM1_BASE + 0x60UL)
2131 #define DFSDM1_Channel4_BASE (DFSDM1_BASE + 0x80UL)
2132 #define DFSDM1_Channel5_BASE (DFSDM1_BASE + 0xA0UL)
2133 #define DFSDM1_Channel6_BASE (DFSDM1_BASE + 0xC0UL)
2134 #define DFSDM1_Channel7_BASE (DFSDM1_BASE + 0xE0UL)
2135 #define DFSDM1_Filter0_BASE (DFSDM1_BASE + 0x100UL)
2136 #define DFSDM1_Filter1_BASE (DFSDM1_BASE + 0x180UL)
2137 #define DFSDM1_Filter2_BASE (DFSDM1_BASE + 0x200UL)
2138 #define DFSDM1_Filter3_BASE (DFSDM1_BASE + 0x280UL)
2139 #define DFSDM1_Filter4_BASE (DFSDM1_BASE + 0x300UL)
2140 #define DFSDM1_Filter5_BASE (DFSDM1_BASE + 0x380UL)
2141 #define DFSDM1_Filter6_BASE (DFSDM1_BASE + 0x400UL)
2142 #define DFSDM1_Filter7_BASE (DFSDM1_BASE + 0x480UL)
2143 /*!< SRD_APB4PERIPH peripherals */
2144 #define EXTI_BASE (SRD_APB4PERIPH_BASE + 0x0000UL)
2145 #define EXTI_D1_BASE (EXTI_BASE + 0x0080UL)
2146 #define SYSCFG_BASE (SRD_APB4PERIPH_BASE + 0x0400UL)
2147 #define LPUART1_BASE (SRD_APB4PERIPH_BASE + 0x0C00UL)
2148 #define SPI6_BASE (SRD_APB4PERIPH_BASE + 0x1400UL)
2149 #define I2C4_BASE (SRD_APB4PERIPH_BASE + 0x1C00UL)
2150 #define LPTIM2_BASE (SRD_APB4PERIPH_BASE + 0x2400UL)
2151 #define LPTIM3_BASE (SRD_APB4PERIPH_BASE + 0x2800UL)
2152 #define DAC2_BASE (SRD_APB4PERIPH_BASE + 0x3400UL)
2153 #define COMP12_BASE (SRD_APB4PERIPH_BASE + 0x3800UL)
2154 #define COMP1_BASE (COMP12_BASE + 0x0CUL)
2155 #define COMP2_BASE (COMP12_BASE + 0x10UL)
2156 #define VREFBUF_BASE (SRD_APB4PERIPH_BASE + 0x3C00UL)
2157 #define RTC_BASE (SRD_APB4PERIPH_BASE + 0x4000UL)
2158 #define TAMP_BASE (SRD_APB4PERIPH_BASE + 0x4400UL)
2159 #define IWDG1_BASE (SRD_APB4PERIPH_BASE + 0x4800UL)
2160
2161 #define DTS_BASE (SRD_APB4PERIPH_BASE + 0x6800UL)
2162
2163 #define DFSDM2_BASE (SRD_APB4PERIPH_BASE + 0x6C00UL)
2164 #define DFSDM2_Channel0_BASE (DFSDM2_BASE + 0x00UL)
2165 #define DFSDM2_Channel1_BASE (DFSDM2_BASE + 0x20UL)
2166 #define DFSDM2_FLT0_BASE (DFSDM2_BASE + 0x100UL)
2167
2168 /*!< CD_AHB3PERIPH peripherals */
2169
2170 #define OTFDEC1_BASE (CD_AHB3PERIPH_BASE + 0xB800UL)
2171 #define OTFDEC1_REGION1_BASE (OTFDEC1_BASE + 0x20UL)
2172 #define OTFDEC1_REGION2_BASE (OTFDEC1_BASE + 0x50UL)
2173 #define OTFDEC1_REGION3_BASE (OTFDEC1_BASE + 0x80UL)
2174 #define OTFDEC1_REGION4_BASE (OTFDEC1_BASE + 0xB0UL)
2175 #define OTFDEC2_BASE (CD_AHB3PERIPH_BASE + 0xBC00UL)
2176 #define OTFDEC2_REGION1_BASE (OTFDEC2_BASE + 0x20UL)
2177 #define OTFDEC2_REGION2_BASE (OTFDEC2_BASE + 0x50UL)
2178 #define OTFDEC2_REGION3_BASE (OTFDEC2_BASE + 0x80UL)
2179 #define OTFDEC2_REGION4_BASE (OTFDEC2_BASE + 0xB0UL)
2180 #define GFXMMU_BASE (CD_AHB3PERIPH_BASE + 0xC000UL)
2181
2182 #define BDMA1_Channel0_BASE (BDMA1_BASE + 0x0008UL)
2183 #define BDMA1_Channel1_BASE (BDMA1_BASE + 0x001CUL)
2184 #define BDMA1_Channel2_BASE (BDMA1_BASE + 0x0030UL)
2185 #define BDMA1_Channel3_BASE (BDMA1_BASE + 0x0044UL)
2186 #define BDMA1_Channel4_BASE (BDMA1_BASE + 0x0058UL)
2187 #define BDMA1_Channel5_BASE (BDMA1_BASE + 0x006CUL)
2188 #define BDMA1_Channel6_BASE (BDMA1_BASE + 0x0080UL)
2189 #define BDMA1_Channel7_BASE (BDMA1_BASE + 0x0094UL)
2190
2191 #define BDMA2_Channel0_BASE (BDMA2_BASE + 0x0008UL)
2192 #define BDMA2_Channel1_BASE (BDMA2_BASE + 0x001CUL)
2193 #define BDMA2_Channel2_BASE (BDMA2_BASE + 0x0030UL)
2194 #define BDMA2_Channel3_BASE (BDMA2_BASE + 0x0044UL)
2195 #define BDMA2_Channel4_BASE (BDMA2_BASE + 0x0058UL)
2196 #define BDMA2_Channel5_BASE (BDMA2_BASE + 0x006CUL)
2197 #define BDMA2_Channel6_BASE (BDMA2_BASE + 0x0080UL)
2198 #define BDMA2_Channel7_BASE (BDMA2_BASE + 0x0094UL)
2199
2200
2201 #define DMAMUX2_Channel0_BASE (DMAMUX2_BASE)
2202 #define DMAMUX2_Channel1_BASE (DMAMUX2_BASE + 0x0004UL)
2203 #define DMAMUX2_Channel2_BASE (DMAMUX2_BASE + 0x0008UL)
2204 #define DMAMUX2_Channel3_BASE (DMAMUX2_BASE + 0x000CUL)
2205 #define DMAMUX2_Channel4_BASE (DMAMUX2_BASE + 0x0010UL)
2206 #define DMAMUX2_Channel5_BASE (DMAMUX2_BASE + 0x0014UL)
2207 #define DMAMUX2_Channel6_BASE (DMAMUX2_BASE + 0x0018UL)
2208 #define DMAMUX2_Channel7_BASE (DMAMUX2_BASE + 0x001CUL)
2209
2210 #define DMAMUX2_RequestGenerator0_BASE (DMAMUX2_BASE + 0x0100UL)
2211 #define DMAMUX2_RequestGenerator1_BASE (DMAMUX2_BASE + 0x0104UL)
2212 #define DMAMUX2_RequestGenerator2_BASE (DMAMUX2_BASE + 0x0108UL)
2213 #define DMAMUX2_RequestGenerator3_BASE (DMAMUX2_BASE + 0x010CUL)
2214 #define DMAMUX2_RequestGenerator4_BASE (DMAMUX2_BASE + 0x0110UL)
2215 #define DMAMUX2_RequestGenerator5_BASE (DMAMUX2_BASE + 0x0114UL)
2216 #define DMAMUX2_RequestGenerator6_BASE (DMAMUX2_BASE + 0x0118UL)
2217 #define DMAMUX2_RequestGenerator7_BASE (DMAMUX2_BASE + 0x011CUL)
2218
2219 #define DMAMUX2_ChannelStatus_BASE (DMAMUX2_BASE + 0x0080UL)
2220 #define DMAMUX2_RequestGenStatus_BASE (DMAMUX2_BASE + 0x0140UL)
2221
2222 #define DMA1_Stream0_BASE (DMA1_BASE + 0x010UL)
2223 #define DMA1_Stream1_BASE (DMA1_BASE + 0x028UL)
2224 #define DMA1_Stream2_BASE (DMA1_BASE + 0x040UL)
2225 #define DMA1_Stream3_BASE (DMA1_BASE + 0x058UL)
2226 #define DMA1_Stream4_BASE (DMA1_BASE + 0x070UL)
2227 #define DMA1_Stream5_BASE (DMA1_BASE + 0x088UL)
2228 #define DMA1_Stream6_BASE (DMA1_BASE + 0x0A0UL)
2229 #define DMA1_Stream7_BASE (DMA1_BASE + 0x0B8UL)
2230
2231 #define DMA2_Stream0_BASE (DMA2_BASE + 0x010UL)
2232 #define DMA2_Stream1_BASE (DMA2_BASE + 0x028UL)
2233 #define DMA2_Stream2_BASE (DMA2_BASE + 0x040UL)
2234 #define DMA2_Stream3_BASE (DMA2_BASE + 0x058UL)
2235 #define DMA2_Stream4_BASE (DMA2_BASE + 0x070UL)
2236 #define DMA2_Stream5_BASE (DMA2_BASE + 0x088UL)
2237 #define DMA2_Stream6_BASE (DMA2_BASE + 0x0A0UL)
2238 #define DMA2_Stream7_BASE (DMA2_BASE + 0x0B8UL)
2239
2240
2241 #define DMAMUX1_Channel0_BASE (DMAMUX1_BASE)
2242 #define DMAMUX1_Channel1_BASE (DMAMUX1_BASE + 0x0004UL)
2243 #define DMAMUX1_Channel2_BASE (DMAMUX1_BASE + 0x0008UL)
2244 #define DMAMUX1_Channel3_BASE (DMAMUX1_BASE + 0x000CUL)
2245 #define DMAMUX1_Channel4_BASE (DMAMUX1_BASE + 0x0010UL)
2246 #define DMAMUX1_Channel5_BASE (DMAMUX1_BASE + 0x0014UL)
2247 #define DMAMUX1_Channel6_BASE (DMAMUX1_BASE + 0x0018UL)
2248 #define DMAMUX1_Channel7_BASE (DMAMUX1_BASE + 0x001CUL)
2249 #define DMAMUX1_Channel8_BASE (DMAMUX1_BASE + 0x0020UL)
2250 #define DMAMUX1_Channel9_BASE (DMAMUX1_BASE + 0x0024UL)
2251 #define DMAMUX1_Channel10_BASE (DMAMUX1_BASE + 0x0028UL)
2252 #define DMAMUX1_Channel11_BASE (DMAMUX1_BASE + 0x002CUL)
2253 #define DMAMUX1_Channel12_BASE (DMAMUX1_BASE + 0x0030UL)
2254 #define DMAMUX1_Channel13_BASE (DMAMUX1_BASE + 0x0034UL)
2255 #define DMAMUX1_Channel14_BASE (DMAMUX1_BASE + 0x0038UL)
2256 #define DMAMUX1_Channel15_BASE (DMAMUX1_BASE + 0x003CUL)
2257
2258 #define DMAMUX1_RequestGenerator0_BASE (DMAMUX1_BASE + 0x0100UL)
2259 #define DMAMUX1_RequestGenerator1_BASE (DMAMUX1_BASE + 0x0104UL)
2260 #define DMAMUX1_RequestGenerator2_BASE (DMAMUX1_BASE + 0x0108UL)
2261 #define DMAMUX1_RequestGenerator3_BASE (DMAMUX1_BASE + 0x010CUL)
2262 #define DMAMUX1_RequestGenerator4_BASE (DMAMUX1_BASE + 0x0110UL)
2263 #define DMAMUX1_RequestGenerator5_BASE (DMAMUX1_BASE + 0x0114UL)
2264 #define DMAMUX1_RequestGenerator6_BASE (DMAMUX1_BASE + 0x0118UL)
2265 #define DMAMUX1_RequestGenerator7_BASE (DMAMUX1_BASE + 0x011CUL)
2266
2267 #define DMAMUX1_ChannelStatus_BASE (DMAMUX1_BASE + 0x0080UL)
2268 #define DMAMUX1_RequestGenStatus_BASE (DMAMUX1_BASE + 0x0140UL)
2269
2270 /*!< FMC Banks registers base address */
2271 #define FMC_Bank1_R_BASE (FMC_R_BASE + 0x0000UL)
2272 #define FMC_Bank1E_R_BASE (FMC_R_BASE + 0x0104UL)
2273 #define FMC_Bank2_R_BASE (FMC_R_BASE + 0x0060UL)
2274 #define FMC_Bank3_R_BASE (FMC_R_BASE + 0x0080UL)
2275 #define FMC_Bank5_6_R_BASE (FMC_R_BASE + 0x0140UL)
2276
2277 /* Debug MCU registers base address */
2278 #define DBGMCU_BASE (0x5C001000UL)
2279
2280 #define MDMA_Channel0_BASE (MDMA_BASE + 0x00000040UL)
2281 #define MDMA_Channel1_BASE (MDMA_BASE + 0x00000080UL)
2282 #define MDMA_Channel2_BASE (MDMA_BASE + 0x000000C0UL)
2283 #define MDMA_Channel3_BASE (MDMA_BASE + 0x00000100UL)
2284 #define MDMA_Channel4_BASE (MDMA_BASE + 0x00000140UL)
2285 #define MDMA_Channel5_BASE (MDMA_BASE + 0x00000180UL)
2286 #define MDMA_Channel6_BASE (MDMA_BASE + 0x000001C0UL)
2287 #define MDMA_Channel7_BASE (MDMA_BASE + 0x00000200UL)
2288 #define MDMA_Channel8_BASE (MDMA_BASE + 0x00000240UL)
2289 #define MDMA_Channel9_BASE (MDMA_BASE + 0x00000280UL)
2290 #define MDMA_Channel10_BASE (MDMA_BASE + 0x000002C0UL)
2291 #define MDMA_Channel11_BASE (MDMA_BASE + 0x00000300UL)
2292 #define MDMA_Channel12_BASE (MDMA_BASE + 0x00000340UL)
2293 #define MDMA_Channel13_BASE (MDMA_BASE + 0x00000380UL)
2294 #define MDMA_Channel14_BASE (MDMA_BASE + 0x000003C0UL)
2295 #define MDMA_Channel15_BASE (MDMA_BASE + 0x00000400UL)
2296 #define MDMA_Channel16_BASE (MDMA_BASE + 0x00000440UL)
2297
2298 /* GFXMMU virtual buffers base address */
2299 #define GFXMMU_VIRTUAL_BUFFERS_BASE (0x25000000UL)
2300 #define GFXMMU_VIRTUAL_BUFFER0_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE)
2301 #define GFXMMU_VIRTUAL_BUFFER1_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x400000UL)
2302 #define GFXMMU_VIRTUAL_BUFFER2_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0x800000UL)
2303 #define GFXMMU_VIRTUAL_BUFFER3_BASE (GFXMMU_VIRTUAL_BUFFERS_BASE + 0xC00000UL)
2304
2305 #define RAMECC_Monitor1_BASE (RAMECC_BASE + 0x20UL)
2306 #define RAMECC_Monitor2_BASE (RAMECC_BASE + 0x40UL)
2307 #define RAMECC_Monitor3_BASE (RAMECC_BASE + 0x60UL)
2308
2309 /**
2310 * @}
2311 */
2312
2313 /** @addtogroup Peripheral_declaration
2314 * @{
2315 */
2316 #define TIM2 ((TIM_TypeDef *) TIM2_BASE)
2317 #define TIM3 ((TIM_TypeDef *) TIM3_BASE)
2318 #define TIM4 ((TIM_TypeDef *) TIM4_BASE)
2319 #define TIM5 ((TIM_TypeDef *) TIM5_BASE)
2320 #define TIM6 ((TIM_TypeDef *) TIM6_BASE)
2321 #define TIM7 ((TIM_TypeDef *) TIM7_BASE)
2322 #define TIM13 ((TIM_TypeDef *) TIM13_BASE)
2323 #define TIM14 ((TIM_TypeDef *) TIM14_BASE)
2324 #define VREFBUF ((VREFBUF_TypeDef *) VREFBUF_BASE)
2325 #define RTC ((RTC_TypeDef *) RTC_BASE)
2326 #define TAMP ((TAMP_TypeDef *) TAMP_BASE)
2327 #define WWDG1 ((WWDG_TypeDef *) WWDG1_BASE)
2328
2329
2330 #define IWDG1 ((IWDG_TypeDef *) IWDG1_BASE)
2331 #define SPI2 ((SPI_TypeDef *) SPI2_BASE)
2332 #define SPI3 ((SPI_TypeDef *) SPI3_BASE)
2333 #define SPI4 ((SPI_TypeDef *) SPI4_BASE)
2334 #define SPI5 ((SPI_TypeDef *) SPI5_BASE)
2335 #define SPI6 ((SPI_TypeDef *) SPI6_BASE)
2336 #define USART2 ((USART_TypeDef *) USART2_BASE)
2337 #define USART3 ((USART_TypeDef *) USART3_BASE)
2338 #define USART6 ((USART_TypeDef *) USART6_BASE)
2339 #define USART10 ((USART_TypeDef *) USART10_BASE)
2340 #define UART7 ((USART_TypeDef *) UART7_BASE)
2341 #define UART8 ((USART_TypeDef *) UART8_BASE)
2342 #define UART9 ((USART_TypeDef *) UART9_BASE)
2343 #define CRS ((CRS_TypeDef *) CRS_BASE)
2344 #define UART4 ((USART_TypeDef *) UART4_BASE)
2345 #define UART5 ((USART_TypeDef *) UART5_BASE)
2346 #define I2C1 ((I2C_TypeDef *) I2C1_BASE)
2347 #define I2C2 ((I2C_TypeDef *) I2C2_BASE)
2348 #define I2C3 ((I2C_TypeDef *) I2C3_BASE)
2349 #define I2C4 ((I2C_TypeDef *) I2C4_BASE)
2350 #define FDCAN1 ((FDCAN_GlobalTypeDef *) FDCAN1_BASE)
2351 #define FDCAN2 ((FDCAN_GlobalTypeDef *) FDCAN2_BASE)
2352 #define FDCAN_CCU ((FDCAN_ClockCalibrationUnit_TypeDef *) FDCAN_CCU_BASE)
2353 #define CEC ((CEC_TypeDef *) CEC_BASE)
2354 #define LPTIM1 ((LPTIM_TypeDef *) LPTIM1_BASE)
2355 #define PWR ((PWR_TypeDef *) PWR_BASE)
2356 #define DAC1 ((DAC_TypeDef *) DAC1_BASE)
2357 #define LPUART1 ((USART_TypeDef *) LPUART1_BASE)
2358 #define SWPMI1 ((SWPMI_TypeDef *) SWPMI1_BASE)
2359 #define LPTIM2 ((LPTIM_TypeDef *) LPTIM2_BASE)
2360 #define LPTIM3 ((LPTIM_TypeDef *) LPTIM3_BASE)
2361 #define DTS ((DTS_TypeDef *) DTS_BASE)
2362
2363 #define SYSCFG ((SYSCFG_TypeDef *) SYSCFG_BASE)
2364 #define COMP12 ((COMPOPT_TypeDef *) COMP12_BASE)
2365 #define COMP1 ((COMP_TypeDef *) COMP1_BASE)
2366 #define COMP2 ((COMP_TypeDef *) COMP2_BASE)
2367 #define COMP12_COMMON ((COMP_Common_TypeDef *) COMP2_BASE)
2368 #define OPAMP ((OPAMP_TypeDef *) OPAMP_BASE)
2369 #define OPAMP1 ((OPAMP_TypeDef *) OPAMP1_BASE)
2370 #define OPAMP2 ((OPAMP_TypeDef *) OPAMP2_BASE)
2371
2372
2373 #define EXTI ((EXTI_TypeDef *) EXTI_BASE)
2374 #define EXTI_D1 ((EXTI_Core_TypeDef *) EXTI_D1_BASE)
2375 #define TIM1 ((TIM_TypeDef *) TIM1_BASE)
2376 #define SPI1 ((SPI_TypeDef *) SPI1_BASE)
2377 #define TIM8 ((TIM_TypeDef *) TIM8_BASE)
2378 #define USART1 ((USART_TypeDef *) USART1_BASE)
2379 #define TIM12 ((TIM_TypeDef *) TIM12_BASE)
2380 #define TIM15 ((TIM_TypeDef *) TIM15_BASE)
2381 #define TIM16 ((TIM_TypeDef *) TIM16_BASE)
2382 #define TIM17 ((TIM_TypeDef *) TIM17_BASE)
2383 #define SAI1 ((SAI_TypeDef *) SAI1_BASE)
2384 #define SAI1_Block_A ((SAI_Block_TypeDef *)SAI1_Block_A_BASE)
2385 #define SAI1_Block_B ((SAI_Block_TypeDef *)SAI1_Block_B_BASE)
2386 #define SAI2 ((SAI_TypeDef *) SAI2_BASE)
2387 #define SAI2_Block_A ((SAI_Block_TypeDef *)SAI2_Block_A_BASE)
2388 #define SAI2_Block_B ((SAI_Block_TypeDef *)SAI2_Block_B_BASE)
2389
2390 #define SPDIFRX ((SPDIFRX_TypeDef *) SPDIFRX_BASE)
2391 #define DFSDM1_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel0_BASE)
2392 #define DFSDM1_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel1_BASE)
2393 #define DFSDM1_Channel2 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel2_BASE)
2394 #define DFSDM1_Channel3 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel3_BASE)
2395 #define DFSDM1_Channel4 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel4_BASE)
2396 #define DFSDM1_Channel5 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel5_BASE)
2397 #define DFSDM1_Channel6 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel6_BASE)
2398 #define DFSDM1_Channel7 ((DFSDM_Channel_TypeDef *) DFSDM1_Channel7_BASE)
2399 #define DFSDM1_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter0_BASE)
2400 #define DFSDM1_Filter1 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter1_BASE)
2401 #define DFSDM1_Filter2 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter2_BASE)
2402 #define DFSDM1_Filter3 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter3_BASE)
2403 #define DFSDM1_Filter4 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter4_BASE)
2404 #define DFSDM1_Filter5 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter5_BASE)
2405 #define DFSDM1_Filter6 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter6_BASE)
2406 #define DFSDM1_Filter7 ((DFSDM_Filter_TypeDef *) DFSDM1_Filter7_BASE)
2407 #define DFSDM2_Channel0 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel0_BASE)
2408 #define DFSDM2_Channel1 ((DFSDM_Channel_TypeDef *) DFSDM2_Channel1_BASE)
2409 #define DFSDM2_Filter0 ((DFSDM_Filter_TypeDef *) DFSDM2_FLT0_BASE)
2410 #define DMA2D ((DMA2D_TypeDef *) DMA2D_BASE)
2411 #define DCMI ((DCMI_TypeDef *) DCMI_BASE)
2412 #define PSSI ((PSSI_TypeDef *) PSSI_BASE)
2413 #define RCC ((RCC_TypeDef *) RCC_BASE)
2414 #define FLASH ((FLASH_TypeDef *) FLASH_R_BASE)
2415 #define CRC ((CRC_TypeDef *) CRC_BASE)
2416
2417 #define GPIOA ((GPIO_TypeDef *) GPIOA_BASE)
2418 #define GPIOB ((GPIO_TypeDef *) GPIOB_BASE)
2419 #define GPIOC ((GPIO_TypeDef *) GPIOC_BASE)
2420 #define GPIOD ((GPIO_TypeDef *) GPIOD_BASE)
2421 #define GPIOE ((GPIO_TypeDef *) GPIOE_BASE)
2422 #define GPIOF ((GPIO_TypeDef *) GPIOF_BASE)
2423 #define GPIOG ((GPIO_TypeDef *) GPIOG_BASE)
2424 #define GPIOH ((GPIO_TypeDef *) GPIOH_BASE)
2425 #define GPIOI ((GPIO_TypeDef *) GPIOI_BASE)
2426 #define GPIOJ ((GPIO_TypeDef *) GPIOJ_BASE)
2427 #define GPIOK ((GPIO_TypeDef *) GPIOK_BASE)
2428
2429 #define ADC1 ((ADC_TypeDef *) ADC1_BASE)
2430 #define ADC2 ((ADC_TypeDef *) ADC2_BASE)
2431 #define ADC12_COMMON ((ADC_Common_TypeDef *) ADC12_COMMON_BASE)
2432
2433 #define CRYP ((CRYP_TypeDef *) CRYP_BASE)
2434 #define HASH ((HASH_TypeDef *) HASH_BASE)
2435 #define HASH_DIGEST ((HASH_DIGEST_TypeDef *) HASH_DIGEST_BASE)
2436 #define RNG ((RNG_TypeDef *) RNG_BASE)
2437 #define SDMMC2 ((SDMMC_TypeDef *) SDMMC2_BASE)
2438 #define DLYB_SDMMC2 ((DLYB_TypeDef *) DLYB_SDMMC2_BASE)
2439
2440 #define BDMA1 ((BDMA_TypeDef *) BDMA1_BASE)
2441 #define BDMA1_Channel0 ((BDMA_Channel_TypeDef *) BDMA1_Channel0_BASE)
2442 #define BDMA1_Channel1 ((BDMA_Channel_TypeDef *) BDMA1_Channel1_BASE)
2443 #define BDMA1_Channel2 ((BDMA_Channel_TypeDef *) BDMA1_Channel2_BASE)
2444 #define BDMA1_Channel3 ((BDMA_Channel_TypeDef *) BDMA1_Channel3_BASE)
2445 #define BDMA1_Channel4 ((BDMA_Channel_TypeDef *) BDMA1_Channel4_BASE)
2446 #define BDMA1_Channel5 ((BDMA_Channel_TypeDef *) BDMA1_Channel5_BASE)
2447 #define BDMA1_Channel6 ((BDMA_Channel_TypeDef *) BDMA1_Channel6_BASE)
2448 #define BDMA1_Channel7 ((BDMA_Channel_TypeDef *) BDMA1_Channel7_BASE)
2449
2450 #define BDMA2 ((BDMA_TypeDef *) BDMA2_BASE)
2451 #define BDMA2_Channel0 ((BDMA_Channel_TypeDef *) BDMA2_Channel0_BASE)
2452 #define BDMA2_Channel1 ((BDMA_Channel_TypeDef *) BDMA2_Channel1_BASE)
2453 #define BDMA2_Channel2 ((BDMA_Channel_TypeDef *) BDMA2_Channel2_BASE)
2454 #define BDMA2_Channel3 ((BDMA_Channel_TypeDef *) BDMA2_Channel3_BASE)
2455 #define BDMA2_Channel4 ((BDMA_Channel_TypeDef *) BDMA2_Channel4_BASE)
2456 #define BDMA2_Channel5 ((BDMA_Channel_TypeDef *) BDMA2_Channel5_BASE)
2457 #define BDMA2_Channel6 ((BDMA_Channel_TypeDef *) BDMA2_Channel6_BASE)
2458 #define BDMA2_Channel7 ((BDMA_Channel_TypeDef *) BDMA2_Channel7_BASE)
2459
2460 #define RAMECC ((RAMECC_TypeDef *)RAMECC_BASE)
2461 #define RAMECC_Monitor1 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor1_BASE)
2462 #define RAMECC_Monitor2 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor2_BASE)
2463 #define RAMECC_Monitor3 ((RAMECC_MonitorTypeDef *)RAMECC_Monitor3_BASE)
2464
2465 #define DMAMUX2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_BASE)
2466 #define DMAMUX2_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel0_BASE)
2467 #define DMAMUX2_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel1_BASE)
2468 #define DMAMUX2_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel2_BASE)
2469 #define DMAMUX2_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel3_BASE)
2470 #define DMAMUX2_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel4_BASE)
2471 #define DMAMUX2_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel5_BASE)
2472 #define DMAMUX2_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel6_BASE)
2473 #define DMAMUX2_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX2_Channel7_BASE)
2474
2475
2476 #define DMAMUX2_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator0_BASE)
2477 #define DMAMUX2_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator1_BASE)
2478 #define DMAMUX2_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator2_BASE)
2479 #define DMAMUX2_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator3_BASE)
2480 #define DMAMUX2_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator4_BASE)
2481 #define DMAMUX2_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator5_BASE)
2482 #define DMAMUX2_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator6_BASE)
2483 #define DMAMUX2_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX2_RequestGenerator7_BASE)
2484
2485 #define DMAMUX2_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX2_ChannelStatus_BASE)
2486 #define DMAMUX2_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX2_RequestGenStatus_BASE)
2487
2488 #define DMA2 ((DMA_TypeDef *) DMA2_BASE)
2489 #define DMA2_Stream0 ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
2490 #define DMA2_Stream1 ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
2491 #define DMA2_Stream2 ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
2492 #define DMA2_Stream3 ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
2493 #define DMA2_Stream4 ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
2494 #define DMA2_Stream5 ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
2495 #define DMA2_Stream6 ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
2496 #define DMA2_Stream7 ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
2497
2498 #define DMA1 ((DMA_TypeDef *) DMA1_BASE)
2499 #define DMA1_Stream0 ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
2500 #define DMA1_Stream1 ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
2501 #define DMA1_Stream2 ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
2502 #define DMA1_Stream3 ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
2503 #define DMA1_Stream4 ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
2504 #define DMA1_Stream5 ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
2505 #define DMA1_Stream6 ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
2506 #define DMA1_Stream7 ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
2507
2508
2509 #define DMAMUX1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_BASE)
2510 #define DMAMUX1_Channel0 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel0_BASE)
2511 #define DMAMUX1_Channel1 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel1_BASE)
2512 #define DMAMUX1_Channel2 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel2_BASE)
2513 #define DMAMUX1_Channel3 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel3_BASE)
2514 #define DMAMUX1_Channel4 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel4_BASE)
2515 #define DMAMUX1_Channel5 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel5_BASE)
2516 #define DMAMUX1_Channel6 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel6_BASE)
2517 #define DMAMUX1_Channel7 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel7_BASE)
2518 #define DMAMUX1_Channel8 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel8_BASE)
2519 #define DMAMUX1_Channel9 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel9_BASE)
2520 #define DMAMUX1_Channel10 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel10_BASE)
2521 #define DMAMUX1_Channel11 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel11_BASE)
2522 #define DMAMUX1_Channel12 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel12_BASE)
2523 #define DMAMUX1_Channel13 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel13_BASE)
2524 #define DMAMUX1_Channel14 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel14_BASE)
2525 #define DMAMUX1_Channel15 ((DMAMUX_Channel_TypeDef *) DMAMUX1_Channel15_BASE)
2526
2527 #define DMAMUX1_RequestGenerator0 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator0_BASE)
2528 #define DMAMUX1_RequestGenerator1 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator1_BASE)
2529 #define DMAMUX1_RequestGenerator2 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator2_BASE)
2530 #define DMAMUX1_RequestGenerator3 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator3_BASE)
2531 #define DMAMUX1_RequestGenerator4 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator4_BASE)
2532 #define DMAMUX1_RequestGenerator5 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator5_BASE)
2533 #define DMAMUX1_RequestGenerator6 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator6_BASE)
2534 #define DMAMUX1_RequestGenerator7 ((DMAMUX_RequestGen_TypeDef *) DMAMUX1_RequestGenerator7_BASE)
2535
2536 #define DMAMUX1_ChannelStatus ((DMAMUX_ChannelStatus_TypeDef *) DMAMUX1_ChannelStatus_BASE)
2537 #define DMAMUX1_RequestGenStatus ((DMAMUX_RequestGenStatus_TypeDef *) DMAMUX1_RequestGenStatus_BASE)
2538
2539
2540 #define FMC_Bank1_R ((FMC_Bank1_TypeDef *) FMC_Bank1_R_BASE)
2541 #define FMC_Bank1E_R ((FMC_Bank1E_TypeDef *) FMC_Bank1E_R_BASE)
2542 #define FMC_Bank2_R ((FMC_Bank2_TypeDef *) FMC_Bank2_R_BASE)
2543 #define FMC_Bank3_R ((FMC_Bank3_TypeDef *) FMC_Bank3_R_BASE)
2544 #define FMC_Bank5_6_R ((FMC_Bank5_6_TypeDef *) FMC_Bank5_6_R_BASE)
2545
2546 #define DAC2 ((DAC_TypeDef *) DAC2_BASE)
2547 #define OCTOSPI1 ((OCTOSPI_TypeDef *) OCTOSPI1_R_BASE)
2548 #define DLYB_OCTOSPI1 ((DLYB_TypeDef *) DLYB_OCTOSPI1_BASE)
2549 #define OCTOSPI2 ((OCTOSPI_TypeDef *) OCTOSPI2_R_BASE)
2550 #define DLYB_OCTOSPI2 ((DLYB_TypeDef *) DLYB_OCTOSPI2_BASE)
2551 #define OCTOSPIM ((OCTOSPIM_TypeDef *) OCTOSPIM_BASE)
2552
2553 #define OTFDEC1 ((OTFDEC_TypeDef *) OTFDEC1_BASE)
2554 #define OTFDEC1_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION1_BASE)
2555 #define OTFDEC1_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION2_BASE)
2556 #define OTFDEC1_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION3_BASE)
2557 #define OTFDEC1_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC1_REGION4_BASE)
2558
2559 #define OTFDEC2 ((OTFDEC_TypeDef *) OTFDEC2_BASE)
2560 #define OTFDEC2_REGION1 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION1_BASE)
2561 #define OTFDEC2_REGION2 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION2_BASE)
2562 #define OTFDEC2_REGION3 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION3_BASE)
2563 #define OTFDEC2_REGION4 ((OTFDEC_Region_TypeDef *) OTFDEC2_REGION4_BASE)
2564 #define GFXMMU ((GFXMMU_TypeDef *) GFXMMU_BASE)
2565
2566 #define SDMMC1 ((SDMMC_TypeDef *) SDMMC1_BASE)
2567 #define DLYB_SDMMC1 ((DLYB_TypeDef *) DLYB_SDMMC1_BASE)
2568
2569 #define DBGMCU ((DBGMCU_TypeDef *) DBGMCU_BASE)
2570
2571 #define JPEG ((JPEG_TypeDef *) JPGDEC_BASE)
2572 #define HSEM ((HSEM_TypeDef *) HSEM_BASE)
2573 #define HSEM_COMMON ((HSEM_Common_TypeDef *) (HSEM_BASE + 0x100UL))
2574
2575 #define LTDC ((LTDC_TypeDef *)LTDC_BASE)
2576 #define LTDC_Layer1 ((LTDC_Layer_TypeDef *)LTDC_Layer1_BASE)
2577 #define LTDC_Layer2 ((LTDC_Layer_TypeDef *)LTDC_Layer2_BASE)
2578
2579 #define MDIOS ((MDIOS_TypeDef *) MDIOS_BASE)
2580
2581 #define MDMA ((MDMA_TypeDef *)MDMA_BASE)
2582 #define MDMA_Channel0 ((MDMA_Channel_TypeDef *)MDMA_Channel0_BASE)
2583 #define MDMA_Channel1 ((MDMA_Channel_TypeDef *)MDMA_Channel1_BASE)
2584 #define MDMA_Channel2 ((MDMA_Channel_TypeDef *)MDMA_Channel2_BASE)
2585 #define MDMA_Channel3 ((MDMA_Channel_TypeDef *)MDMA_Channel3_BASE)
2586 #define MDMA_Channel4 ((MDMA_Channel_TypeDef *)MDMA_Channel4_BASE)
2587 #define MDMA_Channel5 ((MDMA_Channel_TypeDef *)MDMA_Channel5_BASE)
2588 #define MDMA_Channel6 ((MDMA_Channel_TypeDef *)MDMA_Channel6_BASE)
2589 #define MDMA_Channel7 ((MDMA_Channel_TypeDef *)MDMA_Channel7_BASE)
2590 #define MDMA_Channel8 ((MDMA_Channel_TypeDef *)MDMA_Channel8_BASE)
2591 #define MDMA_Channel9 ((MDMA_Channel_TypeDef *)MDMA_Channel9_BASE)
2592 #define MDMA_Channel10 ((MDMA_Channel_TypeDef *)MDMA_Channel10_BASE)
2593 #define MDMA_Channel11 ((MDMA_Channel_TypeDef *)MDMA_Channel11_BASE)
2594 #define MDMA_Channel12 ((MDMA_Channel_TypeDef *)MDMA_Channel12_BASE)
2595 #define MDMA_Channel13 ((MDMA_Channel_TypeDef *)MDMA_Channel13_BASE)
2596 #define MDMA_Channel14 ((MDMA_Channel_TypeDef *)MDMA_Channel14_BASE)
2597 #define MDMA_Channel15 ((MDMA_Channel_TypeDef *)MDMA_Channel15_BASE)
2598
2599
2600 #define USB1_OTG_HS ((USB_OTG_GlobalTypeDef *) USB1_OTG_HS_PERIPH_BASE)
2601
2602 /* Legacy defines */
2603 #define USB_OTG_HS USB1_OTG_HS
2604 #define USB_OTG_HS_PERIPH_BASE USB1_OTG_HS_PERIPH_BASE
2605
2606 /**
2607 * @}
2608 */
2609
2610 /** @addtogroup Exported_constants
2611 * @{
2612 */
2613
2614 /** @addtogroup Peripheral_Registers_Bits_Definition
2615 * @{
2616 */
2617
2618 /******************************************************************************/
2619 /* Peripheral Registers_Bits_Definition */
2620 /******************************************************************************/
2621
2622 /******************************************************************************/
2623 /* */
2624 /* Analog to Digital Converter */
2625 /* */
2626 /******************************************************************************/
2627 /******************************* ADC VERSION ********************************/
2628 #define ADC_VER_V5_3
2629 /******************** Bit definition for ADC_ISR register ********************/
2630 #define ADC_ISR_ADRDY_Pos (0U)
2631 #define ADC_ISR_ADRDY_Msk (0x1UL << ADC_ISR_ADRDY_Pos) /*!< 0x00000001 */
2632 #define ADC_ISR_ADRDY ADC_ISR_ADRDY_Msk /*!< ADC Ready (ADRDY) flag */
2633 #define ADC_ISR_EOSMP_Pos (1U)
2634 #define ADC_ISR_EOSMP_Msk (0x1UL << ADC_ISR_EOSMP_Pos) /*!< 0x00000002 */
2635 #define ADC_ISR_EOSMP ADC_ISR_EOSMP_Msk /*!< ADC End of Sampling flag */
2636 #define ADC_ISR_EOC_Pos (2U)
2637 #define ADC_ISR_EOC_Msk (0x1UL << ADC_ISR_EOC_Pos) /*!< 0x00000004 */
2638 #define ADC_ISR_EOC ADC_ISR_EOC_Msk /*!< ADC End of Regular Conversion flag */
2639 #define ADC_ISR_EOS_Pos (3U)
2640 #define ADC_ISR_EOS_Msk (0x1UL << ADC_ISR_EOS_Pos) /*!< 0x00000008 */
2641 #define ADC_ISR_EOS ADC_ISR_EOS_Msk /*!< ADC End of Regular sequence of Conversions flag */
2642 #define ADC_ISR_OVR_Pos (4U)
2643 #define ADC_ISR_OVR_Msk (0x1UL << ADC_ISR_OVR_Pos) /*!< 0x00000010 */
2644 #define ADC_ISR_OVR ADC_ISR_OVR_Msk /*!< ADC overrun flag */
2645 #define ADC_ISR_JEOC_Pos (5U)
2646 #define ADC_ISR_JEOC_Msk (0x1UL << ADC_ISR_JEOC_Pos) /*!< 0x00000020 */
2647 #define ADC_ISR_JEOC ADC_ISR_JEOC_Msk /*!< ADC End of Injected Conversion flag */
2648 #define ADC_ISR_JEOS_Pos (6U)
2649 #define ADC_ISR_JEOS_Msk (0x1UL << ADC_ISR_JEOS_Pos) /*!< 0x00000040 */
2650 #define ADC_ISR_JEOS ADC_ISR_JEOS_Msk /*!< ADC End of Injected sequence of Conversions flag */
2651 #define ADC_ISR_AWD1_Pos (7U)
2652 #define ADC_ISR_AWD1_Msk (0x1UL << ADC_ISR_AWD1_Pos) /*!< 0x00000080 */
2653 #define ADC_ISR_AWD1 ADC_ISR_AWD1_Msk /*!< ADC Analog watchdog 1 flag */
2654 #define ADC_ISR_AWD2_Pos (8U)
2655 #define ADC_ISR_AWD2_Msk (0x1UL << ADC_ISR_AWD2_Pos) /*!< 0x00000100 */
2656 #define ADC_ISR_AWD2 ADC_ISR_AWD2_Msk /*!< ADC Analog watchdog 2 flag */
2657 #define ADC_ISR_AWD3_Pos (9U)
2658 #define ADC_ISR_AWD3_Msk (0x1UL << ADC_ISR_AWD3_Pos) /*!< 0x00000200 */
2659 #define ADC_ISR_AWD3 ADC_ISR_AWD3_Msk /*!< ADC Analog watchdog 3 flag */
2660 #define ADC_ISR_JQOVF_Pos (10U)
2661 #define ADC_ISR_JQOVF_Msk (0x1UL << ADC_ISR_JQOVF_Pos) /*!< 0x00000400 */
2662 #define ADC_ISR_JQOVF ADC_ISR_JQOVF_Msk /*!< ADC Injected Context Queue Overflow flag */
2663
2664 /******************** Bit definition for ADC_IER register ********************/
2665 #define ADC_IER_ADRDYIE_Pos (0U)
2666 #define ADC_IER_ADRDYIE_Msk (0x1UL << ADC_IER_ADRDYIE_Pos) /*!< 0x00000001 */
2667 #define ADC_IER_ADRDYIE ADC_IER_ADRDYIE_Msk /*!< ADC Ready (ADRDY) interrupt source */
2668 #define ADC_IER_EOSMPIE_Pos (1U)
2669 #define ADC_IER_EOSMPIE_Msk (0x1UL << ADC_IER_EOSMPIE_Pos) /*!< 0x00000002 */
2670 #define ADC_IER_EOSMPIE ADC_IER_EOSMPIE_Msk /*!< ADC End of Sampling interrupt source */
2671 #define ADC_IER_EOCIE_Pos (2U)
2672 #define ADC_IER_EOCIE_Msk (0x1UL << ADC_IER_EOCIE_Pos) /*!< 0x00000004 */
2673 #define ADC_IER_EOCIE ADC_IER_EOCIE_Msk /*!< ADC End of Regular Conversion interrupt source */
2674 #define ADC_IER_EOSIE_Pos (3U)
2675 #define ADC_IER_EOSIE_Msk (0x1UL << ADC_IER_EOSIE_Pos) /*!< 0x00000008 */
2676 #define ADC_IER_EOSIE ADC_IER_EOSIE_Msk /*!< ADC End of Regular sequence of Conversions interrupt source */
2677 #define ADC_IER_OVRIE_Pos (4U)
2678 #define ADC_IER_OVRIE_Msk (0x1UL << ADC_IER_OVRIE_Pos) /*!< 0x00000010 */
2679 #define ADC_IER_OVRIE ADC_IER_OVRIE_Msk /*!< ADC overrun interrupt source */
2680 #define ADC_IER_JEOCIE_Pos (5U)
2681 #define ADC_IER_JEOCIE_Msk (0x1UL << ADC_IER_JEOCIE_Pos) /*!< 0x00000020 */
2682 #define ADC_IER_JEOCIE ADC_IER_JEOCIE_Msk /*!< ADC End of Injected Conversion interrupt source */
2683 #define ADC_IER_JEOSIE_Pos (6U)
2684 #define ADC_IER_JEOSIE_Msk (0x1UL << ADC_IER_JEOSIE_Pos) /*!< 0x00000040 */
2685 #define ADC_IER_JEOSIE ADC_IER_JEOSIE_Msk /*!< ADC End of Injected sequence of Conversions interrupt source */
2686 #define ADC_IER_AWD1IE_Pos (7U)
2687 #define ADC_IER_AWD1IE_Msk (0x1UL << ADC_IER_AWD1IE_Pos) /*!< 0x00000080 */
2688 #define ADC_IER_AWD1IE ADC_IER_AWD1IE_Msk /*!< ADC Analog watchdog 1 interrupt source */
2689 #define ADC_IER_AWD2IE_Pos (8U)
2690 #define ADC_IER_AWD2IE_Msk (0x1UL << ADC_IER_AWD2IE_Pos) /*!< 0x00000100 */
2691 #define ADC_IER_AWD2IE ADC_IER_AWD2IE_Msk /*!< ADC Analog watchdog 2 interrupt source */
2692 #define ADC_IER_AWD3IE_Pos (9U)
2693 #define ADC_IER_AWD3IE_Msk (0x1UL << ADC_IER_AWD3IE_Pos) /*!< 0x00000200 */
2694 #define ADC_IER_AWD3IE ADC_IER_AWD3IE_Msk /*!< ADC Analog watchdog 3 interrupt source */
2695 #define ADC_IER_JQOVFIE_Pos (10U)
2696 #define ADC_IER_JQOVFIE_Msk (0x1UL << ADC_IER_JQOVFIE_Pos) /*!< 0x00000400 */
2697 #define ADC_IER_JQOVFIE ADC_IER_JQOVFIE_Msk /*!< ADC Injected Context Queue Overflow interrupt source */
2698
2699 /******************** Bit definition for ADC_CR register ********************/
2700 #define ADC_CR_ADEN_Pos (0U)
2701 #define ADC_CR_ADEN_Msk (0x1UL << ADC_CR_ADEN_Pos) /*!< 0x00000001 */
2702 #define ADC_CR_ADEN ADC_CR_ADEN_Msk /*!< ADC Enable control */
2703 #define ADC_CR_ADDIS_Pos (1U)
2704 #define ADC_CR_ADDIS_Msk (0x1UL << ADC_CR_ADDIS_Pos) /*!< 0x00000002 */
2705 #define ADC_CR_ADDIS ADC_CR_ADDIS_Msk /*!< ADC Disable command */
2706 #define ADC_CR_ADSTART_Pos (2U)
2707 #define ADC_CR_ADSTART_Msk (0x1UL << ADC_CR_ADSTART_Pos) /*!< 0x00000004 */
2708 #define ADC_CR_ADSTART ADC_CR_ADSTART_Msk /*!< ADC Start of Regular conversion */
2709 #define ADC_CR_JADSTART_Pos (3U)
2710 #define ADC_CR_JADSTART_Msk (0x1UL << ADC_CR_JADSTART_Pos) /*!< 0x00000008 */
2711 #define ADC_CR_JADSTART ADC_CR_JADSTART_Msk /*!< ADC Start of injected conversion */
2712 #define ADC_CR_ADSTP_Pos (4U)
2713 #define ADC_CR_ADSTP_Msk (0x1UL << ADC_CR_ADSTP_Pos) /*!< 0x00000010 */
2714 #define ADC_CR_ADSTP ADC_CR_ADSTP_Msk /*!< ADC Stop of Regular conversion */
2715 #define ADC_CR_JADSTP_Pos (5U)
2716 #define ADC_CR_JADSTP_Msk (0x1UL << ADC_CR_JADSTP_Pos) /*!< 0x00000020 */
2717 #define ADC_CR_JADSTP ADC_CR_JADSTP_Msk /*!< ADC Stop of injected conversion */
2718 #define ADC_CR_BOOST_Pos (8U)
2719 #define ADC_CR_BOOST_Msk (0x3UL << ADC_CR_BOOST_Pos) /*!< 0x00000300 */
2720 #define ADC_CR_BOOST ADC_CR_BOOST_Msk /*!< ADC Boost Mode configuration */
2721 #define ADC_CR_BOOST_0 (0x1UL << ADC_CR_BOOST_Pos) /*!< 0x00000100 */
2722 #define ADC_CR_BOOST_1 (0x2UL << ADC_CR_BOOST_Pos) /*!< 0x00000200 */
2723 #define ADC_CR_ADCALLIN_Pos (16U)
2724 #define ADC_CR_ADCALLIN_Msk (0x1UL << ADC_CR_ADCALLIN_Pos) /*!< 0x00010000 */
2725 #define ADC_CR_ADCALLIN ADC_CR_ADCALLIN_Msk /*!< ADC Linearity calibration */
2726 #define ADC_CR_LINCALRDYW1_Pos (22U)
2727 #define ADC_CR_LINCALRDYW1_Msk (0x1UL << ADC_CR_LINCALRDYW1_Pos) /*!< 0x00400000 */
2728 #define ADC_CR_LINCALRDYW1 ADC_CR_LINCALRDYW1_Msk /*!< ADC Linearity calibration ready Word 1 */
2729 #define ADC_CR_LINCALRDYW2_Pos (23U)
2730 #define ADC_CR_LINCALRDYW2_Msk (0x1UL << ADC_CR_LINCALRDYW2_Pos) /*!< 0x00800000 */
2731 #define ADC_CR_LINCALRDYW2 ADC_CR_LINCALRDYW2_Msk /*!< ADC Linearity calibration ready Word 2 */
2732 #define ADC_CR_LINCALRDYW3_Pos (24U)
2733 #define ADC_CR_LINCALRDYW3_Msk (0x1UL << ADC_CR_LINCALRDYW3_Pos) /*!< 0x01000000 */
2734 #define ADC_CR_LINCALRDYW3 ADC_CR_LINCALRDYW3_Msk /*!< ADC Linearity calibration ready Word 3 */
2735 #define ADC_CR_LINCALRDYW4_Pos (25U)
2736 #define ADC_CR_LINCALRDYW4_Msk (0x1UL << ADC_CR_LINCALRDYW4_Pos) /*!< 0x02000000 */
2737 #define ADC_CR_LINCALRDYW4 ADC_CR_LINCALRDYW4_Msk /*!< ADC Linearity calibration ready Word 4 */
2738 #define ADC_CR_LINCALRDYW5_Pos (26U)
2739 #define ADC_CR_LINCALRDYW5_Msk (0x1UL << ADC_CR_LINCALRDYW5_Pos) /*!< 0x04000000 */
2740 #define ADC_CR_LINCALRDYW5 ADC_CR_LINCALRDYW5_Msk /*!< ADC Linearity calibration ready Word 5 */
2741 #define ADC_CR_LINCALRDYW6_Pos (27U)
2742 #define ADC_CR_LINCALRDYW6_Msk (0x1UL << ADC_CR_LINCALRDYW6_Pos) /*!< 0x08000000 */
2743 #define ADC_CR_LINCALRDYW6 ADC_CR_LINCALRDYW6_Msk /*!< ADC Linearity calibration ready Word 6 */
2744 #define ADC_CR_ADVREGEN_Pos (28U)
2745 #define ADC_CR_ADVREGEN_Msk (0x1UL << ADC_CR_ADVREGEN_Pos) /*!< 0x10000000 */
2746 #define ADC_CR_ADVREGEN ADC_CR_ADVREGEN_Msk /*!< ADC Voltage regulator Enable */
2747 #define ADC_CR_DEEPPWD_Pos (29U)
2748 #define ADC_CR_DEEPPWD_Msk (0x1UL << ADC_CR_DEEPPWD_Pos) /*!< 0x20000000 */
2749 #define ADC_CR_DEEPPWD ADC_CR_DEEPPWD_Msk /*!< ADC Deep power down Enable */
2750 #define ADC_CR_ADCALDIF_Pos (30U)
2751 #define ADC_CR_ADCALDIF_Msk (0x1UL << ADC_CR_ADCALDIF_Pos) /*!< 0x40000000 */
2752 #define ADC_CR_ADCALDIF ADC_CR_ADCALDIF_Msk /*!< ADC Differential Mode for calibration */
2753 #define ADC_CR_ADCAL_Pos (31U)
2754 #define ADC_CR_ADCAL_Msk (0x1UL << ADC_CR_ADCAL_Pos) /*!< 0x80000000 */
2755 #define ADC_CR_ADCAL ADC_CR_ADCAL_Msk /*!< ADC Calibration */
2756
2757 /******************** Bit definition for ADC_CFGR register ********************/
2758 #define ADC_CFGR_DMNGT_Pos (0U)
2759 #define ADC_CFGR_DMNGT_Msk (0x3UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000003 */
2760 #define ADC_CFGR_DMNGT ADC_CFGR_DMNGT_Msk /*!< ADC Data Management configuration */
2761 #define ADC_CFGR_DMNGT_0 (0x1UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000001 */
2762 #define ADC_CFGR_DMNGT_1 (0x2UL << ADC_CFGR_DMNGT_Pos) /*!< 0x00000002 */
2763
2764 #define ADC_CFGR_RES_Pos (2U)
2765 #define ADC_CFGR_RES_Msk (0x7UL << ADC_CFGR_RES_Pos) /*!< 0x0000001C */
2766 #define ADC_CFGR_RES ADC_CFGR_RES_Msk /*!< ADC Data resolution */
2767 #define ADC_CFGR_RES_0 (0x1UL << ADC_CFGR_RES_Pos) /*!< 0x00000004 */
2768 #define ADC_CFGR_RES_1 (0x2UL << ADC_CFGR_RES_Pos) /*!< 0x00000008 */
2769 #define ADC_CFGR_RES_2 (0x4UL << ADC_CFGR_RES_Pos) /*!< 0x00000010 */
2770
2771 #define ADC_CFGR_EXTSEL_Pos (5U)
2772 #define ADC_CFGR_EXTSEL_Msk (0x1FUL << ADC_CFGR_EXTSEL_Pos) /*!< 0x000003E0 */
2773 #define ADC_CFGR_EXTSEL ADC_CFGR_EXTSEL_Msk /*!< ADC External trigger selection for regular group */
2774 #define ADC_CFGR_EXTSEL_0 (0x01UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000020 */
2775 #define ADC_CFGR_EXTSEL_1 (0x02UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000040 */
2776 #define ADC_CFGR_EXTSEL_2 (0x04UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000080 */
2777 #define ADC_CFGR_EXTSEL_3 (0x08UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000100 */
2778 #define ADC_CFGR_EXTSEL_4 (0x10UL << ADC_CFGR_EXTSEL_Pos) /*!< 0x00000200 */
2779
2780 #define ADC_CFGR_EXTEN_Pos (10U)
2781 #define ADC_CFGR_EXTEN_Msk (0x3UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000C00 */
2782 #define ADC_CFGR_EXTEN ADC_CFGR_EXTEN_Msk /*!< ADC External trigger enable and polarity selection for regular channels */
2783 #define ADC_CFGR_EXTEN_0 (0x1UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000400 */
2784 #define ADC_CFGR_EXTEN_1 (0x2UL << ADC_CFGR_EXTEN_Pos) /*!< 0x00000800 */
2785
2786 #define ADC_CFGR_OVRMOD_Pos (12U)
2787 #define ADC_CFGR_OVRMOD_Msk (0x1UL << ADC_CFGR_OVRMOD_Pos) /*!< 0x00001000 */
2788 #define ADC_CFGR_OVRMOD ADC_CFGR_OVRMOD_Msk /*!< ADC overrun mode */
2789 #define ADC_CFGR_CONT_Pos (13U)
2790 #define ADC_CFGR_CONT_Msk (0x1UL << ADC_CFGR_CONT_Pos) /*!< 0x00002000 */
2791 #define ADC_CFGR_CONT ADC_CFGR_CONT_Msk /*!< ADC Single/continuous conversion mode for regular conversion */
2792 #define ADC_CFGR_AUTDLY_Pos (14U)
2793 #define ADC_CFGR_AUTDLY_Msk (0x1UL << ADC_CFGR_AUTDLY_Pos) /*!< 0x00004000 */
2794 #define ADC_CFGR_AUTDLY ADC_CFGR_AUTDLY_Msk /*!< ADC Delayed conversion mode */
2795
2796 #define ADC_CFGR_DISCEN_Pos (16U)
2797 #define ADC_CFGR_DISCEN_Msk (0x1UL << ADC_CFGR_DISCEN_Pos) /*!< 0x00010000 */
2798 #define ADC_CFGR_DISCEN ADC_CFGR_DISCEN_Msk /*!< ADC Discontinuous mode for regular channels */
2799
2800 #define ADC_CFGR_DISCNUM_Pos (17U)
2801 #define ADC_CFGR_DISCNUM_Msk (0x7UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x000E0000 */
2802 #define ADC_CFGR_DISCNUM ADC_CFGR_DISCNUM_Msk /*!< ADC Discontinuous mode channel count */
2803 #define ADC_CFGR_DISCNUM_0 (0x1UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00020000 */
2804 #define ADC_CFGR_DISCNUM_1 (0x2UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00040000 */
2805 #define ADC_CFGR_DISCNUM_2 (0x4UL << ADC_CFGR_DISCNUM_Pos) /*!< 0x00080000 */
2806
2807 #define ADC_CFGR_JDISCEN_Pos (20U)
2808 #define ADC_CFGR_JDISCEN_Msk (0x1UL << ADC_CFGR_JDISCEN_Pos) /*!< 0x00100000 */
2809 #define ADC_CFGR_JDISCEN ADC_CFGR_JDISCEN_Msk /*!< ADC Discontinuous mode on injected channels */
2810 #define ADC_CFGR_JQM_Pos (21U)
2811 #define ADC_CFGR_JQM_Msk (0x1UL << ADC_CFGR_JQM_Pos) /*!< 0x00200000 */
2812 #define ADC_CFGR_JQM ADC_CFGR_JQM_Msk /*!< ADC JSQR Queue mode */
2813 #define ADC_CFGR_AWD1SGL_Pos (22U)
2814 #define ADC_CFGR_AWD1SGL_Msk (0x1UL << ADC_CFGR_AWD1SGL_Pos) /*!< 0x00400000 */
2815 #define ADC_CFGR_AWD1SGL ADC_CFGR_AWD1SGL_Msk /*!< Enable the watchdog 1 on a single channel or on all channels */
2816 #define ADC_CFGR_AWD1EN_Pos (23U)
2817 #define ADC_CFGR_AWD1EN_Msk (0x1UL << ADC_CFGR_AWD1EN_Pos) /*!< 0x00800000 */
2818 #define ADC_CFGR_AWD1EN ADC_CFGR_AWD1EN_Msk /*!< ADC Analog watchdog 1 enable on regular Channels */
2819 #define ADC_CFGR_JAWD1EN_Pos (24U)
2820 #define ADC_CFGR_JAWD1EN_Msk (0x1UL << ADC_CFGR_JAWD1EN_Pos) /*!< 0x01000000 */
2821 #define ADC_CFGR_JAWD1EN ADC_CFGR_JAWD1EN_Msk /*!< ADC Analog watchdog 1 enable on injected Channels */
2822 #define ADC_CFGR_JAUTO_Pos (25U)
2823 #define ADC_CFGR_JAUTO_Msk (0x1UL << ADC_CFGR_JAUTO_Pos) /*!< 0x02000000 */
2824 #define ADC_CFGR_JAUTO ADC_CFGR_JAUTO_Msk /*!< ADC Automatic injected group conversion */
2825
2826 #define ADC_CFGR_AWD1CH_Pos (26U)
2827 #define ADC_CFGR_AWD1CH_Msk (0x1FUL << ADC_CFGR_AWD1CH_Pos) /*!< 0x7C000000 */
2828 #define ADC_CFGR_AWD1CH ADC_CFGR_AWD1CH_Msk /*!< ADC Analog watchdog 1 Channel selection */
2829 #define ADC_CFGR_AWD1CH_0 (0x01UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x04000000 */
2830 #define ADC_CFGR_AWD1CH_1 (0x02UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x08000000 */
2831 #define ADC_CFGR_AWD1CH_2 (0x04UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x10000000 */
2832 #define ADC_CFGR_AWD1CH_3 (0x08UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x20000000 */
2833 #define ADC_CFGR_AWD1CH_4 (0x10UL << ADC_CFGR_AWD1CH_Pos) /*!< 0x40000000 */
2834
2835 #define ADC_CFGR_JQDIS_Pos (31U)
2836 #define ADC_CFGR_JQDIS_Msk (0x1UL << ADC_CFGR_JQDIS_Pos) /*!< 0x80000000 */
2837 #define ADC_CFGR_JQDIS ADC_CFGR_JQDIS_Msk /*!< ADC Injected queue disable */
2838
2839 /******************** Bit definition for ADC_CFGR2 register ********************/
2840 #define ADC_CFGR2_ROVSE_Pos (0U)
2841 #define ADC_CFGR2_ROVSE_Msk (0x1UL << ADC_CFGR2_ROVSE_Pos) /*!< 0x00000001 */
2842 #define ADC_CFGR2_ROVSE ADC_CFGR2_ROVSE_Msk /*!< ADC Regular group oversampler enable */
2843 #define ADC_CFGR2_JOVSE_Pos (1U)
2844 #define ADC_CFGR2_JOVSE_Msk (0x1UL << ADC_CFGR2_JOVSE_Pos) /*!< 0x00000002 */
2845 #define ADC_CFGR2_JOVSE ADC_CFGR2_JOVSE_Msk /*!< ADC Injected group oversampler enable */
2846
2847 #define ADC_CFGR2_OVSS_Pos (5U)
2848 #define ADC_CFGR2_OVSS_Msk (0xFUL << ADC_CFGR2_OVSS_Pos) /*!< 0x000001E0 */
2849 #define ADC_CFGR2_OVSS ADC_CFGR2_OVSS_Msk /*!< ADC Regular Oversampling shift */
2850 #define ADC_CFGR2_OVSS_0 (0x1UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000020 */
2851 #define ADC_CFGR2_OVSS_1 (0x2UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000040 */
2852 #define ADC_CFGR2_OVSS_2 (0x4UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000080 */
2853 #define ADC_CFGR2_OVSS_3 (0x8UL << ADC_CFGR2_OVSS_Pos) /*!< 0x00000100 */
2854
2855 #define ADC_CFGR2_TROVS_Pos (9U)
2856 #define ADC_CFGR2_TROVS_Msk (0x1UL << ADC_CFGR2_TROVS_Pos) /*!< 0x00000200 */
2857 #define ADC_CFGR2_TROVS ADC_CFGR2_TROVS_Msk /*!< ADC Triggered regular Oversampling */
2858 #define ADC_CFGR2_ROVSM_Pos (10U)
2859 #define ADC_CFGR2_ROVSM_Msk (0x1UL << ADC_CFGR2_ROVSM_Pos) /*!< 0x00000400 */
2860 #define ADC_CFGR2_ROVSM ADC_CFGR2_ROVSM_Msk /*!< ADC Regular oversampling mode */
2861
2862 #define ADC_CFGR2_RSHIFT1_Pos (11U)
2863 #define ADC_CFGR2_RSHIFT1_Msk (0x1UL << ADC_CFGR2_RSHIFT1_Pos) /*!< 0x00000800 */
2864 #define ADC_CFGR2_RSHIFT1 ADC_CFGR2_RSHIFT1_Msk /*!< ADC Right-shift data after Offset 1 correction */
2865 #define ADC_CFGR2_RSHIFT2_Pos (12U)
2866 #define ADC_CFGR2_RSHIFT2_Msk (0x1UL << ADC_CFGR2_RSHIFT2_Pos) /*!< 0x00001000 */
2867 #define ADC_CFGR2_RSHIFT2 ADC_CFGR2_RSHIFT2_Msk /*!< ADC Right-shift data after Offset 2 correction */
2868 #define ADC_CFGR2_RSHIFT3_Pos (13U)
2869 #define ADC_CFGR2_RSHIFT3_Msk (0x1UL << ADC_CFGR2_RSHIFT3_Pos) /*!< 0x00002000 */
2870 #define ADC_CFGR2_RSHIFT3 ADC_CFGR2_RSHIFT3_Msk /*!< ADC Right-shift data after Offset 3 correction */
2871 #define ADC_CFGR2_RSHIFT4_Pos (14U)
2872 #define ADC_CFGR2_RSHIFT4_Msk (0x1UL << ADC_CFGR2_RSHIFT4_Pos) /*!< 0x00004000 */
2873 #define ADC_CFGR2_RSHIFT4 ADC_CFGR2_RSHIFT4_Msk /*!< ADC Right-shift data after Offset 4 correction */
2874
2875 #define ADC_CFGR2_OVSR_Pos (16U)
2876 #define ADC_CFGR2_OVSR_Msk (0x3FFUL << ADC_CFGR2_OVSR_Pos) /*!< 0x03FF0000 */
2877 #define ADC_CFGR2_OVSR ADC_CFGR2_OVSR_Msk /*!< ADC oversampling Ratio */
2878 #define ADC_CFGR2_OVSR_0 (0x001UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00010000 */
2879 #define ADC_CFGR2_OVSR_1 (0x002UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00020000 */
2880 #define ADC_CFGR2_OVSR_2 (0x004UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00040000 */
2881 #define ADC_CFGR2_OVSR_3 (0x008UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00080000 */
2882 #define ADC_CFGR2_OVSR_4 (0x010UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00100000 */
2883 #define ADC_CFGR2_OVSR_5 (0x020UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00200000 */
2884 #define ADC_CFGR2_OVSR_6 (0x040UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00400000 */
2885 #define ADC_CFGR2_OVSR_7 (0x080UL << ADC_CFGR2_OVSR_Pos) /*!< 0x00800000 */
2886 #define ADC_CFGR2_OVSR_8 (0x100UL << ADC_CFGR2_OVSR_Pos) /*!< 0x01000000 */
2887 #define ADC_CFGR2_OVSR_9 (0x200UL << ADC_CFGR2_OVSR_Pos) /*!< 0x02000000 */
2888
2889 #define ADC_CFGR2_LSHIFT_Pos (28U)
2890 #define ADC_CFGR2_LSHIFT_Msk (0xFUL << ADC_CFGR2_LSHIFT_Pos) /*!< 0xF0000000 */
2891 #define ADC_CFGR2_LSHIFT ADC_CFGR2_LSHIFT_Msk /*!< ADC Left shift factor */
2892 #define ADC_CFGR2_LSHIFT_0 (0x1UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x10000000 */
2893 #define ADC_CFGR2_LSHIFT_1 (0x2UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x20000000 */
2894 #define ADC_CFGR2_LSHIFT_2 (0x4UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x40000000 */
2895 #define ADC_CFGR2_LSHIFT_3 (0x8UL << ADC_CFGR2_LSHIFT_Pos) /*!< 0x80000000 */
2896
2897 /******************** Bit definition for ADC_SMPR1 register ********************/
2898 #define ADC_SMPR1_SMP0_Pos (0U)
2899 #define ADC_SMPR1_SMP0_Msk (0x7UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000007 */
2900 #define ADC_SMPR1_SMP0 ADC_SMPR1_SMP0_Msk /*!< ADC Channel 0 Sampling time selection */
2901 #define ADC_SMPR1_SMP0_0 (0x1UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000001 */
2902 #define ADC_SMPR1_SMP0_1 (0x2UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000002 */
2903 #define ADC_SMPR1_SMP0_2 (0x4UL << ADC_SMPR1_SMP0_Pos) /*!< 0x00000004 */
2904
2905 #define ADC_SMPR1_SMP1_Pos (3U)
2906 #define ADC_SMPR1_SMP1_Msk (0x7UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000038 */
2907 #define ADC_SMPR1_SMP1 ADC_SMPR1_SMP1_Msk /*!< ADC Channel 1 Sampling time selection */
2908 #define ADC_SMPR1_SMP1_0 (0x1UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000008 */
2909 #define ADC_SMPR1_SMP1_1 (0x2UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000010 */
2910 #define ADC_SMPR1_SMP1_2 (0x4UL << ADC_SMPR1_SMP1_Pos) /*!< 0x00000020 */
2911
2912 #define ADC_SMPR1_SMP2_Pos (6U)
2913 #define ADC_SMPR1_SMP2_Msk (0x7UL << ADC_SMPR1_SMP2_Pos) /*!< 0x000001C0 */
2914 #define ADC_SMPR1_SMP2 ADC_SMPR1_SMP2_Msk /*!< ADC Channel 2 Sampling time selection */
2915 #define ADC_SMPR1_SMP2_0 (0x1UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000040 */
2916 #define ADC_SMPR1_SMP2_1 (0x2UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000080 */
2917 #define ADC_SMPR1_SMP2_2 (0x4UL << ADC_SMPR1_SMP2_Pos) /*!< 0x00000100 */
2918
2919 #define ADC_SMPR1_SMP3_Pos (9U)
2920 #define ADC_SMPR1_SMP3_Msk (0x7UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000E00 */
2921 #define ADC_SMPR1_SMP3 ADC_SMPR1_SMP3_Msk /*!< ADC Channel 3 Sampling time selection */
2922 #define ADC_SMPR1_SMP3_0 (0x1UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000200 */
2923 #define ADC_SMPR1_SMP3_1 (0x2UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000400 */
2924 #define ADC_SMPR1_SMP3_2 (0x4UL << ADC_SMPR1_SMP3_Pos) /*!< 0x00000800 */
2925
2926 #define ADC_SMPR1_SMP4_Pos (12U)
2927 #define ADC_SMPR1_SMP4_Msk (0x7UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00007000 */
2928 #define ADC_SMPR1_SMP4 ADC_SMPR1_SMP4_Msk /*!< ADC Channel 4 Sampling time selection */
2929 #define ADC_SMPR1_SMP4_0 (0x1UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00001000 */
2930 #define ADC_SMPR1_SMP4_1 (0x2UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00002000 */
2931 #define ADC_SMPR1_SMP4_2 (0x4UL << ADC_SMPR1_SMP4_Pos) /*!< 0x00004000 */
2932
2933 #define ADC_SMPR1_SMP5_Pos (15U)
2934 #define ADC_SMPR1_SMP5_Msk (0x7UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00038000 */
2935 #define ADC_SMPR1_SMP5 ADC_SMPR1_SMP5_Msk /*!< ADC Channel 5 Sampling time selection */
2936 #define ADC_SMPR1_SMP5_0 (0x1UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00008000 */
2937 #define ADC_SMPR1_SMP5_1 (0x2UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00010000 */
2938 #define ADC_SMPR1_SMP5_2 (0x4UL << ADC_SMPR1_SMP5_Pos) /*!< 0x00020000 */
2939
2940 #define ADC_SMPR1_SMP6_Pos (18U)
2941 #define ADC_SMPR1_SMP6_Msk (0x7UL << ADC_SMPR1_SMP6_Pos) /*!< 0x001C0000 */
2942 #define ADC_SMPR1_SMP6 ADC_SMPR1_SMP6_Msk /*!< ADC Channel 6 Sampling time selection */
2943 #define ADC_SMPR1_SMP6_0 (0x1UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00040000 */
2944 #define ADC_SMPR1_SMP6_1 (0x2UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00080000 */
2945 #define ADC_SMPR1_SMP6_2 (0x4UL << ADC_SMPR1_SMP6_Pos) /*!< 0x00100000 */
2946
2947 #define ADC_SMPR1_SMP7_Pos (21U)
2948 #define ADC_SMPR1_SMP7_Msk (0x7UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00E00000 */
2949 #define ADC_SMPR1_SMP7 ADC_SMPR1_SMP7_Msk /*!< ADC Channel 7 Sampling time selection */
2950 #define ADC_SMPR1_SMP7_0 (0x1UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00200000 */
2951 #define ADC_SMPR1_SMP7_1 (0x2UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00400000 */
2952 #define ADC_SMPR1_SMP7_2 (0x4UL << ADC_SMPR1_SMP7_Pos) /*!< 0x00800000 */
2953
2954 #define ADC_SMPR1_SMP8_Pos (24U)
2955 #define ADC_SMPR1_SMP8_Msk (0x7UL << ADC_SMPR1_SMP8_Pos) /*!< 0x07000000 */
2956 #define ADC_SMPR1_SMP8 ADC_SMPR1_SMP8_Msk /*!< ADC Channel 8 Sampling time selection */
2957 #define ADC_SMPR1_SMP8_0 (0x1UL << ADC_SMPR1_SMP8_Pos) /*!< 0x01000000 */
2958 #define ADC_SMPR1_SMP8_1 (0x2UL << ADC_SMPR1_SMP8_Pos) /*!< 0x02000000 */
2959 #define ADC_SMPR1_SMP8_2 (0x4UL << ADC_SMPR1_SMP8_Pos) /*!< 0x04000000 */
2960
2961 #define ADC_SMPR1_SMP9_Pos (27U)
2962 #define ADC_SMPR1_SMP9_Msk (0x7UL << ADC_SMPR1_SMP9_Pos) /*!< 0x38000000 */
2963 #define ADC_SMPR1_SMP9 ADC_SMPR1_SMP9_Msk /*!< ADC Channel 9 Sampling time selection */
2964 #define ADC_SMPR1_SMP9_0 (0x1UL << ADC_SMPR1_SMP9_Pos) /*!< 0x08000000 */
2965 #define ADC_SMPR1_SMP9_1 (0x2UL << ADC_SMPR1_SMP9_Pos) /*!< 0x10000000 */
2966 #define ADC_SMPR1_SMP9_2 (0x4UL << ADC_SMPR1_SMP9_Pos) /*!< 0x20000000 */
2967
2968 /******************** Bit definition for ADC_SMPR2 register ********************/
2969 #define ADC_SMPR2_SMP10_Pos (0U)
2970 #define ADC_SMPR2_SMP10_Msk (0x7UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000007 */
2971 #define ADC_SMPR2_SMP10 ADC_SMPR2_SMP10_Msk /*!< ADC Channel 10 Sampling time selection */
2972 #define ADC_SMPR2_SMP10_0 (0x1UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000001 */
2973 #define ADC_SMPR2_SMP10_1 (0x2UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000002 */
2974 #define ADC_SMPR2_SMP10_2 (0x4UL << ADC_SMPR2_SMP10_Pos) /*!< 0x00000004 */
2975
2976 #define ADC_SMPR2_SMP11_Pos (3U)
2977 #define ADC_SMPR2_SMP11_Msk (0x7UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000038 */
2978 #define ADC_SMPR2_SMP11 ADC_SMPR2_SMP11_Msk /*!< ADC Channel 11 Sampling time selection */
2979 #define ADC_SMPR2_SMP11_0 (0x1UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000008 */
2980 #define ADC_SMPR2_SMP11_1 (0x2UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000010 */
2981 #define ADC_SMPR2_SMP11_2 (0x4UL << ADC_SMPR2_SMP11_Pos) /*!< 0x00000020 */
2982
2983 #define ADC_SMPR2_SMP12_Pos (6U)
2984 #define ADC_SMPR2_SMP12_Msk (0x7UL << ADC_SMPR2_SMP12_Pos) /*!< 0x000001C0 */
2985 #define ADC_SMPR2_SMP12 ADC_SMPR2_SMP12_Msk /*!< ADC Channel 12 Sampling time selection */
2986 #define ADC_SMPR2_SMP12_0 (0x1UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000040 */
2987 #define ADC_SMPR2_SMP12_1 (0x2UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000080 */
2988 #define ADC_SMPR2_SMP12_2 (0x4UL << ADC_SMPR2_SMP12_Pos) /*!< 0x00000100 */
2989
2990 #define ADC_SMPR2_SMP13_Pos (9U)
2991 #define ADC_SMPR2_SMP13_Msk (0x7UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000E00 */
2992 #define ADC_SMPR2_SMP13 ADC_SMPR2_SMP13_Msk /*!< ADC Channel 13 Sampling time selection */
2993 #define ADC_SMPR2_SMP13_0 (0x1UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000200 */
2994 #define ADC_SMPR2_SMP13_1 (0x2UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000400 */
2995 #define ADC_SMPR2_SMP13_2 (0x4UL << ADC_SMPR2_SMP13_Pos) /*!< 0x00000800 */
2996
2997 #define ADC_SMPR2_SMP14_Pos (12U)
2998 #define ADC_SMPR2_SMP14_Msk (0x7UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00007000 */
2999 #define ADC_SMPR2_SMP14 ADC_SMPR2_SMP14_Msk /*!< ADC Channel 14 Sampling time selection */
3000 #define ADC_SMPR2_SMP14_0 (0x1UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00001000 */
3001 #define ADC_SMPR2_SMP14_1 (0x2UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00002000 */
3002 #define ADC_SMPR2_SMP14_2 (0x4UL << ADC_SMPR2_SMP14_Pos) /*!< 0x00004000 */
3003
3004 #define ADC_SMPR2_SMP15_Pos (15U)
3005 #define ADC_SMPR2_SMP15_Msk (0x7UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00038000 */
3006 #define ADC_SMPR2_SMP15 ADC_SMPR2_SMP15_Msk /*!< ADC Channel 15 Sampling time selection */
3007 #define ADC_SMPR2_SMP15_0 (0x1UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00008000 */
3008 #define ADC_SMPR2_SMP15_1 (0x2UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00010000 */
3009 #define ADC_SMPR2_SMP15_2 (0x4UL << ADC_SMPR2_SMP15_Pos) /*!< 0x00020000 */
3010
3011 #define ADC_SMPR2_SMP16_Pos (18U)
3012 #define ADC_SMPR2_SMP16_Msk (0x7UL << ADC_SMPR2_SMP16_Pos) /*!< 0x001C0000 */
3013 #define ADC_SMPR2_SMP16 ADC_SMPR2_SMP16_Msk /*!< ADC Channel 16 Sampling time selection */
3014 #define ADC_SMPR2_SMP16_0 (0x1UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00040000 */
3015 #define ADC_SMPR2_SMP16_1 (0x2UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00080000 */
3016 #define ADC_SMPR2_SMP16_2 (0x4UL << ADC_SMPR2_SMP16_Pos) /*!< 0x00100000 */
3017
3018 #define ADC_SMPR2_SMP17_Pos (21U)
3019 #define ADC_SMPR2_SMP17_Msk (0x7UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00E00000 */
3020 #define ADC_SMPR2_SMP17 ADC_SMPR2_SMP17_Msk /*!< ADC Channel 17 Sampling time selection */
3021 #define ADC_SMPR2_SMP17_0 (0x1UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00200000 */
3022 #define ADC_SMPR2_SMP17_1 (0x2UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00400000 */
3023 #define ADC_SMPR2_SMP17_2 (0x4UL << ADC_SMPR2_SMP17_Pos) /*!< 0x00800000 */
3024
3025 #define ADC_SMPR2_SMP18_Pos (24U)
3026 #define ADC_SMPR2_SMP18_Msk (0x7UL << ADC_SMPR2_SMP18_Pos) /*!< 0x07000000 */
3027 #define ADC_SMPR2_SMP18 ADC_SMPR2_SMP18_Msk /*!< ADC Channel 18 Sampling time selection */
3028 #define ADC_SMPR2_SMP18_0 (0x1UL << ADC_SMPR2_SMP18_Pos) /*!< 0x01000000 */
3029 #define ADC_SMPR2_SMP18_1 (0x2UL << ADC_SMPR2_SMP18_Pos) /*!< 0x02000000 */
3030 #define ADC_SMPR2_SMP18_2 (0x4UL << ADC_SMPR2_SMP18_Pos) /*!< 0x04000000 */
3031
3032 #define ADC_SMPR2_SMP19_Pos (27U)
3033 #define ADC_SMPR2_SMP19_Msk (0x7UL << ADC_SMPR2_SMP19_Pos) /*!< 0x38000000 */
3034 #define ADC_SMPR2_SMP19 ADC_SMPR2_SMP19_Msk /*!< ADC Channel 19 Sampling time selection */
3035 #define ADC_SMPR2_SMP19_0 (0x1UL << ADC_SMPR2_SMP19_Pos) /*!< 0x08000000 */
3036 #define ADC_SMPR2_SMP19_1 (0x2UL << ADC_SMPR2_SMP19_Pos) /*!< 0x10000000 */
3037 #define ADC_SMPR2_SMP19_2 (0x4UL << ADC_SMPR2_SMP19_Pos) /*!< 0x20000000 */
3038
3039 /******************** Bit definition for ADC_PCSEL register ********************/
3040 #define ADC_PCSEL_PCSEL_Pos (0U)
3041 #define ADC_PCSEL_PCSEL_Msk (0xFFFFFUL << ADC_PCSEL_PCSEL_Pos) /*!< 0x000FFFFF */
3042 #define ADC_PCSEL_PCSEL ADC_PCSEL_PCSEL_Msk /*!< ADC pre channel selection */
3043 #define ADC_PCSEL_PCSEL_0 (0x00001UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000001 */
3044 #define ADC_PCSEL_PCSEL_1 (0x00002UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000002 */
3045 #define ADC_PCSEL_PCSEL_2 (0x00004UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000004 */
3046 #define ADC_PCSEL_PCSEL_3 (0x00008UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000008 */
3047 #define ADC_PCSEL_PCSEL_4 (0x00010UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000010 */
3048 #define ADC_PCSEL_PCSEL_5 (0x00020UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000020 */
3049 #define ADC_PCSEL_PCSEL_6 (0x00040UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000040 */
3050 #define ADC_PCSEL_PCSEL_7 (0x00080UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000080 */
3051 #define ADC_PCSEL_PCSEL_8 (0x00100UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000100 */
3052 #define ADC_PCSEL_PCSEL_9 (0x00200UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000200 */
3053 #define ADC_PCSEL_PCSEL_10 (0x00400UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000400 */
3054 #define ADC_PCSEL_PCSEL_11 (0x00800UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00000800 */
3055 #define ADC_PCSEL_PCSEL_12 (0x01000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00001000 */
3056 #define ADC_PCSEL_PCSEL_13 (0x02000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00002000 */
3057 #define ADC_PCSEL_PCSEL_14 (0x04000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00004000 */
3058 #define ADC_PCSEL_PCSEL_15 (0x08000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00008000 */
3059 #define ADC_PCSEL_PCSEL_16 (0x10000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00010000 */
3060 #define ADC_PCSEL_PCSEL_17 (0x20000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00020000 */
3061 #define ADC_PCSEL_PCSEL_18 (0x40000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00040000 */
3062 #define ADC_PCSEL_PCSEL_19 (0x80000UL << ADC_PCSEL_PCSEL_Pos) /*!< 0x00080000 */
3063
3064 /***************** Bit definition for ADC_LTR1, 2, 3 registers *****************/
3065 #define ADC_LTR_LT_Pos (0U)
3066 #define ADC_LTR_LT_Msk (0x3FFFFFFUL << ADC_LTR_LT_Pos) /*!< 0x03FFFFFF */
3067 #define ADC_LTR_LT ADC_LTR_LT_Msk /*!< ADC Analog watchdog 1, 2 and 3 lower threshold */
3068
3069 /***************** Bit definition for ADC_HTR1, 2, 3 registers ****************/
3070 #define ADC_HTR_HT_Pos (0U)
3071 #define ADC_HTR_HT_Msk (0x3FFFFFFUL << ADC_HTR_HT_Pos) /*!< 0x03FFFFFF */
3072 #define ADC_HTR_HT ADC_HTR_HT_Msk /*!< ADC Analog watchdog 1,2 and 3 higher threshold */
3073
3074
3075 /******************** Bit definition for ADC_SQR1 register ********************/
3076 #define ADC_SQR1_L_Pos (0U)
3077 #define ADC_SQR1_L_Msk (0xFUL << ADC_SQR1_L_Pos) /*!< 0x0000000F */
3078 #define ADC_SQR1_L ADC_SQR1_L_Msk /*!< ADC regular channel sequence lenght */
3079 #define ADC_SQR1_L_0 (0x1UL << ADC_SQR1_L_Pos) /*!< 0x00000001 */
3080 #define ADC_SQR1_L_1 (0x2UL << ADC_SQR1_L_Pos) /*!< 0x00000002 */
3081 #define ADC_SQR1_L_2 (0x4UL << ADC_SQR1_L_Pos) /*!< 0x00000004 */
3082 #define ADC_SQR1_L_3 (0x8UL << ADC_SQR1_L_Pos) /*!< 0x00000008 */
3083
3084 #define ADC_SQR1_SQ1_Pos (6U)
3085 #define ADC_SQR1_SQ1_Msk (0x1FUL << ADC_SQR1_SQ1_Pos) /*!< 0x000007C0 */
3086 #define ADC_SQR1_SQ1 ADC_SQR1_SQ1_Msk /*!< ADC 1st conversion in regular sequence */
3087 #define ADC_SQR1_SQ1_0 (0x01UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000040 */
3088 #define ADC_SQR1_SQ1_1 (0x02UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000080 */
3089 #define ADC_SQR1_SQ1_2 (0x04UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000100 */
3090 #define ADC_SQR1_SQ1_3 (0x08UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000200 */
3091 #define ADC_SQR1_SQ1_4 (0x10UL << ADC_SQR1_SQ1_Pos) /*!< 0x00000400 */
3092
3093 #define ADC_SQR1_SQ2_Pos (12U)
3094 #define ADC_SQR1_SQ2_Msk (0x1FUL << ADC_SQR1_SQ2_Pos) /*!< 0x0001F000 */
3095 #define ADC_SQR1_SQ2 ADC_SQR1_SQ2_Msk /*!< ADC 2nd conversion in regular sequence */
3096 #define ADC_SQR1_SQ2_0 (0x01UL << ADC_SQR1_SQ2_Pos) /*!< 0x00001000 */
3097 #define ADC_SQR1_SQ2_1 (0x02UL << ADC_SQR1_SQ2_Pos) /*!< 0x00002000 */
3098 #define ADC_SQR1_SQ2_2 (0x04UL << ADC_SQR1_SQ2_Pos) /*!< 0x00004000 */
3099 #define ADC_SQR1_SQ2_3 (0x08UL << ADC_SQR1_SQ2_Pos) /*!< 0x00008000 */
3100 #define ADC_SQR1_SQ2_4 (0x10UL << ADC_SQR1_SQ2_Pos) /*!< 0x00010000 */
3101
3102 #define ADC_SQR1_SQ3_Pos (18U)
3103 #define ADC_SQR1_SQ3_Msk (0x1FUL << ADC_SQR1_SQ3_Pos) /*!< 0x007C0000 */
3104 #define ADC_SQR1_SQ3 ADC_SQR1_SQ3_Msk /*!< ADC 3rd conversion in regular sequence */
3105 #define ADC_SQR1_SQ3_0 (0x01UL << ADC_SQR1_SQ3_Pos) /*!< 0x00040000 */
3106 #define ADC_SQR1_SQ3_1 (0x02UL << ADC_SQR1_SQ3_Pos) /*!< 0x00080000 */
3107 #define ADC_SQR1_SQ3_2 (0x04UL << ADC_SQR1_SQ3_Pos) /*!< 0x00100000 */
3108 #define ADC_SQR1_SQ3_3 (0x08UL << ADC_SQR1_SQ3_Pos) /*!< 0x00200000 */
3109 #define ADC_SQR1_SQ3_4 (0x10UL << ADC_SQR1_SQ3_Pos) /*!< 0x00400000 */
3110
3111 #define ADC_SQR1_SQ4_Pos (24U)
3112 #define ADC_SQR1_SQ4_Msk (0x1FUL << ADC_SQR1_SQ4_Pos) /*!< 0x1F000000 */
3113 #define ADC_SQR1_SQ4 ADC_SQR1_SQ4_Msk /*!< ADC 4th conversion in regular sequence */
3114 #define ADC_SQR1_SQ4_0 (0x01UL << ADC_SQR1_SQ4_Pos) /*!< 0x01000000 */
3115 #define ADC_SQR1_SQ4_1 (0x02UL << ADC_SQR1_SQ4_Pos) /*!< 0x02000000 */
3116 #define ADC_SQR1_SQ4_2 (0x04UL << ADC_SQR1_SQ4_Pos) /*!< 0x04000000 */
3117 #define ADC_SQR1_SQ4_3 (0x08UL << ADC_SQR1_SQ4_Pos) /*!< 0x08000000 */
3118 #define ADC_SQR1_SQ4_4 (0x10UL << ADC_SQR1_SQ4_Pos) /*!< 0x10000000 */
3119
3120 /******************** Bit definition for ADC_SQR2 register ********************/
3121 #define ADC_SQR2_SQ5_Pos (0U)
3122 #define ADC_SQR2_SQ5_Msk (0x1FUL << ADC_SQR2_SQ5_Pos) /*!< 0x0000001F */
3123 #define ADC_SQR2_SQ5 ADC_SQR2_SQ5_Msk /*!< ADC 5th conversion in regular sequence */
3124 #define ADC_SQR2_SQ5_0 (0x01UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000001 */
3125 #define ADC_SQR2_SQ5_1 (0x02UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000002 */
3126 #define ADC_SQR2_SQ5_2 (0x04UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000004 */
3127 #define ADC_SQR2_SQ5_3 (0x08UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000008 */
3128 #define ADC_SQR2_SQ5_4 (0x10UL << ADC_SQR2_SQ5_Pos) /*!< 0x00000010 */
3129
3130 #define ADC_SQR2_SQ6_Pos (6U)
3131 #define ADC_SQR2_SQ6_Msk (0x1FUL << ADC_SQR2_SQ6_Pos) /*!< 0x000007C0 */
3132 #define ADC_SQR2_SQ6 ADC_SQR2_SQ6_Msk /*!< ADC 6th conversion in regular sequence */
3133 #define ADC_SQR2_SQ6_0 (0x01UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000040 */
3134 #define ADC_SQR2_SQ6_1 (0x02UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000080 */
3135 #define ADC_SQR2_SQ6_2 (0x04UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000100 */
3136 #define ADC_SQR2_SQ6_3 (0x08UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000200 */
3137 #define ADC_SQR2_SQ6_4 (0x10UL << ADC_SQR2_SQ6_Pos) /*!< 0x00000400 */
3138
3139 #define ADC_SQR2_SQ7_Pos (12U)
3140 #define ADC_SQR2_SQ7_Msk (0x1FUL << ADC_SQR2_SQ7_Pos) /*!< 0x0001F000 */
3141 #define ADC_SQR2_SQ7 ADC_SQR2_SQ7_Msk /*!< ADC 7th conversion in regular sequence */
3142 #define ADC_SQR2_SQ7_0 (0x01UL << ADC_SQR2_SQ7_Pos) /*!< 0x00001000 */
3143 #define ADC_SQR2_SQ7_1 (0x02UL << ADC_SQR2_SQ7_Pos) /*!< 0x00002000 */
3144 #define ADC_SQR2_SQ7_2 (0x04UL << ADC_SQR2_SQ7_Pos) /*!< 0x00004000 */
3145 #define ADC_SQR2_SQ7_3 (0x08UL << ADC_SQR2_SQ7_Pos) /*!< 0x00008000 */
3146 #define ADC_SQR2_SQ7_4 (0x10UL << ADC_SQR2_SQ7_Pos) /*!< 0x00010000 */
3147
3148 #define ADC_SQR2_SQ8_Pos (18U)
3149 #define ADC_SQR2_SQ8_Msk (0x1FUL << ADC_SQR2_SQ8_Pos) /*!< 0x007C0000 */
3150 #define ADC_SQR2_SQ8 ADC_SQR2_SQ8_Msk /*!< ADC 8th conversion in regular sequence */
3151 #define ADC_SQR2_SQ8_0 (0x01UL << ADC_SQR2_SQ8_Pos) /*!< 0x00040000 */
3152 #define ADC_SQR2_SQ8_1 (0x02UL << ADC_SQR2_SQ8_Pos) /*!< 0x00080000 */
3153 #define ADC_SQR2_SQ8_2 (0x04UL << ADC_SQR2_SQ8_Pos) /*!< 0x00100000 */
3154 #define ADC_SQR2_SQ8_3 (0x08UL << ADC_SQR2_SQ8_Pos) /*!< 0x00200000 */
3155 #define ADC_SQR2_SQ8_4 (0x10UL << ADC_SQR2_SQ8_Pos) /*!< 0x00400000 */
3156
3157 #define ADC_SQR2_SQ9_Pos (24U)
3158 #define ADC_SQR2_SQ9_Msk (0x1FUL << ADC_SQR2_SQ9_Pos) /*!< 0x1F000000 */
3159 #define ADC_SQR2_SQ9 ADC_SQR2_SQ9_Msk /*!< ADC 9th conversion in regular sequence */
3160 #define ADC_SQR2_SQ9_0 (0x01UL << ADC_SQR2_SQ9_Pos) /*!< 0x01000000 */
3161 #define ADC_SQR2_SQ9_1 (0x02UL << ADC_SQR2_SQ9_Pos) /*!< 0x02000000 */
3162 #define ADC_SQR2_SQ9_2 (0x04UL << ADC_SQR2_SQ9_Pos) /*!< 0x04000000 */
3163 #define ADC_SQR2_SQ9_3 (0x08UL << ADC_SQR2_SQ9_Pos) /*!< 0x08000000 */
3164 #define ADC_SQR2_SQ9_4 (0x10UL << ADC_SQR2_SQ9_Pos) /*!< 0x10000000 */
3165
3166 /******************** Bit definition for ADC_SQR3 register ********************/
3167 #define ADC_SQR3_SQ10_Pos (0U)
3168 #define ADC_SQR3_SQ10_Msk (0x1FUL << ADC_SQR3_SQ10_Pos) /*!< 0x0000001F */
3169 #define ADC_SQR3_SQ10 ADC_SQR3_SQ10_Msk /*!< ADC 10th conversion in regular sequence */
3170 #define ADC_SQR3_SQ10_0 (0x01UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000001 */
3171 #define ADC_SQR3_SQ10_1 (0x02UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000002 */
3172 #define ADC_SQR3_SQ10_2 (0x04UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000004 */
3173 #define ADC_SQR3_SQ10_3 (0x08UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000008 */
3174 #define ADC_SQR3_SQ10_4 (0x10UL << ADC_SQR3_SQ10_Pos) /*!< 0x00000010 */
3175
3176 #define ADC_SQR3_SQ11_Pos (6U)
3177 #define ADC_SQR3_SQ11_Msk (0x1FUL << ADC_SQR3_SQ11_Pos) /*!< 0x000007C0 */
3178 #define ADC_SQR3_SQ11 ADC_SQR3_SQ11_Msk /*!< ADC 11th conversion in regular sequence */
3179 #define ADC_SQR3_SQ11_0 (0x01UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000040 */
3180 #define ADC_SQR3_SQ11_1 (0x02UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000080 */
3181 #define ADC_SQR3_SQ11_2 (0x04UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000100 */
3182 #define ADC_SQR3_SQ11_3 (0x08UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000200 */
3183 #define ADC_SQR3_SQ11_4 (0x10UL << ADC_SQR3_SQ11_Pos) /*!< 0x00000400 */
3184
3185 #define ADC_SQR3_SQ12_Pos (12U)
3186 #define ADC_SQR3_SQ12_Msk (0x1FUL << ADC_SQR3_SQ12_Pos) /*!< 0x0001F000 */
3187 #define ADC_SQR3_SQ12 ADC_SQR3_SQ12_Msk /*!< ADC 12th conversion in regular sequence */
3188 #define ADC_SQR3_SQ12_0 (0x01UL << ADC_SQR3_SQ12_Pos) /*!< 0x00001000 */
3189 #define ADC_SQR3_SQ12_1 (0x02UL << ADC_SQR3_SQ12_Pos) /*!< 0x00002000 */
3190 #define ADC_SQR3_SQ12_2 (0x04UL << ADC_SQR3_SQ12_Pos) /*!< 0x00004000 */
3191 #define ADC_SQR3_SQ12_3 (0x08UL << ADC_SQR3_SQ12_Pos) /*!< 0x00008000 */
3192 #define ADC_SQR3_SQ12_4 (0x10UL << ADC_SQR3_SQ12_Pos) /*!< 0x00010000 */
3193
3194 #define ADC_SQR3_SQ13_Pos (18U)
3195 #define ADC_SQR3_SQ13_Msk (0x1FUL << ADC_SQR3_SQ13_Pos) /*!< 0x007C0000 */
3196 #define ADC_SQR3_SQ13 ADC_SQR3_SQ13_Msk /*!< ADC 13th conversion in regular sequence */
3197 #define ADC_SQR3_SQ13_0 (0x01UL << ADC_SQR3_SQ13_Pos) /*!< 0x00040000 */
3198 #define ADC_SQR3_SQ13_1 (0x02UL << ADC_SQR3_SQ13_Pos) /*!< 0x00080000 */
3199 #define ADC_SQR3_SQ13_2 (0x04UL << ADC_SQR3_SQ13_Pos) /*!< 0x00100000 */
3200 #define ADC_SQR3_SQ13_3 (0x08UL << ADC_SQR3_SQ13_Pos) /*!< 0x00200000 */
3201 #define ADC_SQR3_SQ13_4 (0x10UL << ADC_SQR3_SQ13_Pos) /*!< 0x00400000 */
3202
3203 #define ADC_SQR3_SQ14_Pos (24U)
3204 #define ADC_SQR3_SQ14_Msk (0x1FUL << ADC_SQR3_SQ14_Pos) /*!< 0x1F000000 */
3205 #define ADC_SQR3_SQ14 ADC_SQR3_SQ14_Msk /*!< ADC 14th conversion in regular sequence */
3206 #define ADC_SQR3_SQ14_0 (0x01UL << ADC_SQR3_SQ14_Pos) /*!< 0x01000000 */
3207 #define ADC_SQR3_SQ14_1 (0x02UL << ADC_SQR3_SQ14_Pos) /*!< 0x02000000 */
3208 #define ADC_SQR3_SQ14_2 (0x04UL << ADC_SQR3_SQ14_Pos) /*!< 0x04000000 */
3209 #define ADC_SQR3_SQ14_3 (0x08UL << ADC_SQR3_SQ14_Pos) /*!< 0x08000000 */
3210 #define ADC_SQR3_SQ14_4 (0x10UL << ADC_SQR3_SQ14_Pos) /*!< 0x10000000 */
3211
3212 /******************** Bit definition for ADC_SQR4 register ********************/
3213 #define ADC_SQR4_SQ15_Pos (0U)
3214 #define ADC_SQR4_SQ15_Msk (0x1FUL << ADC_SQR4_SQ15_Pos) /*!< 0x0000001F */
3215 #define ADC_SQR4_SQ15 ADC_SQR4_SQ15_Msk /*!< ADC 15th conversion in regular sequence */
3216 #define ADC_SQR4_SQ15_0 (0x01UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000001 */
3217 #define ADC_SQR4_SQ15_1 (0x02UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000002 */
3218 #define ADC_SQR4_SQ15_2 (0x04UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000004 */
3219 #define ADC_SQR4_SQ15_3 (0x08UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000008 */
3220 #define ADC_SQR4_SQ15_4 (0x10UL << ADC_SQR4_SQ15_Pos) /*!< 0x00000010 */
3221
3222 #define ADC_SQR4_SQ16_Pos (6U)
3223 #define ADC_SQR4_SQ16_Msk (0x1FUL << ADC_SQR4_SQ16_Pos) /*!< 0x000007C0 */
3224 #define ADC_SQR4_SQ16 ADC_SQR4_SQ16_Msk /*!< ADC 16th conversion in regular sequence */
3225 #define ADC_SQR4_SQ16_0 (0x01UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000040 */
3226 #define ADC_SQR4_SQ16_1 (0x02UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000080 */
3227 #define ADC_SQR4_SQ16_2 (0x04UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000100 */
3228 #define ADC_SQR4_SQ16_3 (0x08UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000200 */
3229 #define ADC_SQR4_SQ16_4 (0x10UL << ADC_SQR4_SQ16_Pos) /*!< 0x00000400 */
3230 /******************** Bit definition for ADC_DR register ********************/
3231 #define ADC_DR_RDATA_Pos (0U)
3232 #define ADC_DR_RDATA_Msk (0xFFFFFFFFUL << ADC_DR_RDATA_Pos) /*!< 0xFFFFFFFF */
3233 #define ADC_DR_RDATA ADC_DR_RDATA_Msk /*!< ADC regular Data converted */
3234
3235 /******************** Bit definition for ADC_JSQR register ********************/
3236 #define ADC_JSQR_JL_Pos (0U)
3237 #define ADC_JSQR_JL_Msk (0x3UL << ADC_JSQR_JL_Pos) /*!< 0x00000003 */
3238 #define ADC_JSQR_JL ADC_JSQR_JL_Msk /*!< ADC injected channel sequence length */
3239 #define ADC_JSQR_JL_0 (0x1UL << ADC_JSQR_JL_Pos) /*!< 0x00000001 */
3240 #define ADC_JSQR_JL_1 (0x2UL << ADC_JSQR_JL_Pos) /*!< 0x00000002 */
3241
3242 #define ADC_JSQR_JEXTSEL_Pos (2U)
3243 #define ADC_JSQR_JEXTSEL_Msk (0x1FUL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x0000007C */
3244 #define ADC_JSQR_JEXTSEL ADC_JSQR_JEXTSEL_Msk /*!< ADC external trigger selection for injected group */
3245 #define ADC_JSQR_JEXTSEL_0 (0x01UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000004 */
3246 #define ADC_JSQR_JEXTSEL_1 (0x02UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000008 */
3247 #define ADC_JSQR_JEXTSEL_2 (0x04UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000010 */
3248 #define ADC_JSQR_JEXTSEL_3 (0x08UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000020 */
3249 #define ADC_JSQR_JEXTSEL_4 (0x10UL << ADC_JSQR_JEXTSEL_Pos) /*!< 0x00000040 */
3250
3251 #define ADC_JSQR_JEXTEN_Pos (7U)
3252 #define ADC_JSQR_JEXTEN_Msk (0x3UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000180 */
3253 #define ADC_JSQR_JEXTEN ADC_JSQR_JEXTEN_Msk /*!< ADC external trigger enable and polarity selection for injected channels */
3254 #define ADC_JSQR_JEXTEN_0 (0x1UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000080 */
3255 #define ADC_JSQR_JEXTEN_1 (0x2UL << ADC_JSQR_JEXTEN_Pos) /*!< 0x00000100 */
3256
3257 #define ADC_JSQR_JSQ1_Pos (9U)
3258 #define ADC_JSQR_JSQ1_Msk (0x1FUL << ADC_JSQR_JSQ1_Pos) /*!< 0x00003E00 */
3259 #define ADC_JSQR_JSQ1 ADC_JSQR_JSQ1_Msk /*!< ADC 1st conversion in injected sequence */
3260 #define ADC_JSQR_JSQ1_0 (0x01UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000200 */
3261 #define ADC_JSQR_JSQ1_1 (0x02UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000400 */
3262 #define ADC_JSQR_JSQ1_2 (0x04UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00000800 */
3263 #define ADC_JSQR_JSQ1_3 (0x08UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00001000 */
3264 #define ADC_JSQR_JSQ1_4 (0x10UL << ADC_JSQR_JSQ1_Pos) /*!< 0x00002000 */
3265
3266 #define ADC_JSQR_JSQ2_Pos (15U)
3267 #define ADC_JSQR_JSQ2_Msk (0x1FUL << ADC_JSQR_JSQ2_Pos) /*!< 0x000F8000 */
3268 #define ADC_JSQR_JSQ2 ADC_JSQR_JSQ2_Msk /*!< ADC 2nd conversion in injected sequence */
3269 #define ADC_JSQR_JSQ2_0 (0x01UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00008000 */
3270 #define ADC_JSQR_JSQ2_1 (0x02UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00010000 */
3271 #define ADC_JSQR_JSQ2_2 (0x04UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00020000 */
3272 #define ADC_JSQR_JSQ2_3 (0x08UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00040000 */
3273 #define ADC_JSQR_JSQ2_4 (0x10UL << ADC_JSQR_JSQ2_Pos) /*!< 0x00080000 */
3274
3275 #define ADC_JSQR_JSQ3_Pos (21U)
3276 #define ADC_JSQR_JSQ3_Msk (0x1FUL << ADC_JSQR_JSQ3_Pos) /*!< 0x03E00000 */
3277 #define ADC_JSQR_JSQ3 ADC_JSQR_JSQ3_Msk /*!< ADC 3rd conversion in injected sequence */
3278 #define ADC_JSQR_JSQ3_0 (0x01UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00200000 */
3279 #define ADC_JSQR_JSQ3_1 (0x02UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00400000 */
3280 #define ADC_JSQR_JSQ3_2 (0x04UL << ADC_JSQR_JSQ3_Pos) /*!< 0x00800000 */
3281 #define ADC_JSQR_JSQ3_3 (0x08UL << ADC_JSQR_JSQ3_Pos) /*!< 0x01000000 */
3282 #define ADC_JSQR_JSQ3_4 (0x10UL << ADC_JSQR_JSQ3_Pos) /*!< 0x02000000 */
3283
3284 #define ADC_JSQR_JSQ4_Pos (27U)
3285 #define ADC_JSQR_JSQ4_Msk (0x1FUL << ADC_JSQR_JSQ4_Pos) /*!< 0xF8000000 */
3286 #define ADC_JSQR_JSQ4 ADC_JSQR_JSQ4_Msk /*!< ADC 4th conversion in injected sequence */
3287 #define ADC_JSQR_JSQ4_0 (0x01UL << ADC_JSQR_JSQ4_Pos) /*!< 0x08000000 */
3288 #define ADC_JSQR_JSQ4_1 (0x02UL << ADC_JSQR_JSQ4_Pos) /*!< 0x10000000 */
3289 #define ADC_JSQR_JSQ4_2 (0x04UL << ADC_JSQR_JSQ4_Pos) /*!< 0x20000000 */
3290 #define ADC_JSQR_JSQ4_3 (0x08UL << ADC_JSQR_JSQ4_Pos) /*!< 0x40000000 */
3291 #define ADC_JSQR_JSQ4_4 (0x10UL << ADC_JSQR_JSQ4_Pos) /*!< 0x80000000 */
3292
3293 /******************** Bit definition for ADC_OFR1 register ********************/
3294 #define ADC_OFR1_OFFSET1_Pos (0U)
3295 #define ADC_OFR1_OFFSET1_Msk (0x3FFFFFFUL << ADC_OFR1_OFFSET1_Pos) /*!< 0x03FFFFFF */
3296 #define ADC_OFR1_OFFSET1 ADC_OFR1_OFFSET1_Msk /*!< ADC data offset 1 for channel programmed into bits OFFSET1_CH[4:0] */
3297 #define ADC_OFR1_OFFSET1_0 (0x0000001UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000001 */
3298 #define ADC_OFR1_OFFSET1_1 (0x0000002UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000002 */
3299 #define ADC_OFR1_OFFSET1_2 (0x0000004UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000004 */
3300 #define ADC_OFR1_OFFSET1_3 (0x0000008UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000008 */
3301 #define ADC_OFR1_OFFSET1_4 (0x0000010UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000010 */
3302 #define ADC_OFR1_OFFSET1_5 (0x0000020UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000020 */
3303 #define ADC_OFR1_OFFSET1_6 (0x0000040UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000040 */
3304 #define ADC_OFR1_OFFSET1_7 (0x0000080UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000080 */
3305 #define ADC_OFR1_OFFSET1_8 (0x0000100UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000100 */
3306 #define ADC_OFR1_OFFSET1_9 (0x0000200UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000200 */
3307 #define ADC_OFR1_OFFSET1_10 (0x0000400UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000400 */
3308 #define ADC_OFR1_OFFSET1_11 (0x0000800UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00000800 */
3309 #define ADC_OFR1_OFFSET1_12 (0x0001000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00001000 */
3310 #define ADC_OFR1_OFFSET1_13 (0x0002000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00002000 */
3311 #define ADC_OFR1_OFFSET1_14 (0x0004000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00004000 */
3312 #define ADC_OFR1_OFFSET1_15 (0x0008000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00008000 */
3313 #define ADC_OFR1_OFFSET1_16 (0x0010000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00010000 */
3314 #define ADC_OFR1_OFFSET1_17 (0x0020000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00020000 */
3315 #define ADC_OFR1_OFFSET1_18 (0x0040000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00040000 */
3316 #define ADC_OFR1_OFFSET1_19 (0x0080000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00080000 */
3317 #define ADC_OFR1_OFFSET1_20 (0x0100000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00100000 */
3318 #define ADC_OFR1_OFFSET1_21 (0x0200000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00200000 */
3319 #define ADC_OFR1_OFFSET1_22 (0x0400000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00400000 */
3320 #define ADC_OFR1_OFFSET1_23 (0x0800000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x00800000 */
3321 #define ADC_OFR1_OFFSET1_24 (0x1000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x01000000 */
3322 #define ADC_OFR1_OFFSET1_25 (0x2000000UL << ADC_OFR1_OFFSET1_Pos) /*!< 0x02000000 */
3323
3324 #define ADC_OFR1_OFFSET1_CH_Pos (26U)
3325 #define ADC_OFR1_OFFSET1_CH_Msk (0x1FUL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x7C000000 */
3326 #define ADC_OFR1_OFFSET1_CH ADC_OFR1_OFFSET1_CH_Msk /*!< ADC Channel selection for the data offset 1 */
3327 #define ADC_OFR1_OFFSET1_CH_0 (0x01UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x04000000 */
3328 #define ADC_OFR1_OFFSET1_CH_1 (0x02UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x08000000 */
3329 #define ADC_OFR1_OFFSET1_CH_2 (0x04UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x10000000 */
3330 #define ADC_OFR1_OFFSET1_CH_3 (0x08UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x20000000 */
3331 #define ADC_OFR1_OFFSET1_CH_4 (0x10UL << ADC_OFR1_OFFSET1_CH_Pos) /*!< 0x40000000 */
3332
3333 #define ADC_OFR1_SSATE_Pos (31U)
3334 #define ADC_OFR1_SSATE_Msk (0x1UL << ADC_OFR1_SSATE_Pos) /*!< 0x80000000 */
3335 #define ADC_OFR1_SSATE ADC_OFR1_SSATE_Msk /*!< ADC Signed saturation Enable */
3336
3337
3338 /******************** Bit definition for ADC_OFR2 register ********************/
3339 #define ADC_OFR2_OFFSET2_Pos (0U)
3340 #define ADC_OFR2_OFFSET2_Msk (0x3FFFFFFUL << ADC_OFR2_OFFSET2_Pos) /*!< 0x03FFFFFF */
3341 #define ADC_OFR2_OFFSET2 ADC_OFR2_OFFSET2_Msk /*!< ADC data offset 2 for channel programmed into bits OFFSET2_CH[4:0] */
3342 #define ADC_OFR2_OFFSET2_0 (0x0000001UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000001 */
3343 #define ADC_OFR2_OFFSET2_1 (0x0000002UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000002 */
3344 #define ADC_OFR2_OFFSET2_2 (0x0000004UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000004 */
3345 #define ADC_OFR2_OFFSET2_3 (0x0000008UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000008 */
3346 #define ADC_OFR2_OFFSET2_4 (0x0000010UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000010 */
3347 #define ADC_OFR2_OFFSET2_5 (0x0000020UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000020 */
3348 #define ADC_OFR2_OFFSET2_6 (0x0000040UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000040 */
3349 #define ADC_OFR2_OFFSET2_7 (0x0000080UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000080 */
3350 #define ADC_OFR2_OFFSET2_8 (0x0000100UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000100 */
3351 #define ADC_OFR2_OFFSET2_9 (0x0000200UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000200 */
3352 #define ADC_OFR2_OFFSET2_10 (0x0000400UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000400 */
3353 #define ADC_OFR2_OFFSET2_11 (0x0000800UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00000800 */
3354 #define ADC_OFR2_OFFSET2_12 (0x0001000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00001000 */
3355 #define ADC_OFR2_OFFSET2_13 (0x0002000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00002000 */
3356 #define ADC_OFR2_OFFSET2_14 (0x0004000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00004000 */
3357 #define ADC_OFR2_OFFSET2_15 (0x0008000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00008000 */
3358 #define ADC_OFR2_OFFSET2_16 (0x0010000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00010000 */
3359 #define ADC_OFR2_OFFSET2_17 (0x0020000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00020000 */
3360 #define ADC_OFR2_OFFSET2_18 (0x0040000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00040000 */
3361 #define ADC_OFR2_OFFSET2_19 (0x0080000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00080000 */
3362 #define ADC_OFR2_OFFSET2_20 (0x0100000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00100000 */
3363 #define ADC_OFR2_OFFSET2_21 (0x0200000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00200000 */
3364 #define ADC_OFR2_OFFSET2_22 (0x0400000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00400000 */
3365 #define ADC_OFR2_OFFSET2_23 (0x0800000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x00800000 */
3366 #define ADC_OFR2_OFFSET2_24 (0x1000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x01000000 */
3367 #define ADC_OFR2_OFFSET2_25 (0x2000000UL << ADC_OFR2_OFFSET2_Pos) /*!< 0x02000000 */
3368
3369 #define ADC_OFR2_OFFSET2_CH_Pos (26U)
3370 #define ADC_OFR2_OFFSET2_CH_Msk (0x1FUL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x7C000000 */
3371 #define ADC_OFR2_OFFSET2_CH ADC_OFR2_OFFSET2_CH_Msk /*!< ADC Channel selection for the data offset 2 */
3372 #define ADC_OFR2_OFFSET2_CH_0 (0x01UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x04000000 */
3373 #define ADC_OFR2_OFFSET2_CH_1 (0x02UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x08000000 */
3374 #define ADC_OFR2_OFFSET2_CH_2 (0x04UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x10000000 */
3375 #define ADC_OFR2_OFFSET2_CH_3 (0x08UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x20000000 */
3376 #define ADC_OFR2_OFFSET2_CH_4 (0x10UL << ADC_OFR2_OFFSET2_CH_Pos) /*!< 0x40000000 */
3377
3378 #define ADC_OFR2_SSATE_Pos (31U)
3379 #define ADC_OFR2_SSATE_Msk (0x1UL << ADC_OFR2_SSATE_Pos) /*!< 0x80000000 */
3380 #define ADC_OFR2_SSATE ADC_OFR2_SSATE_Msk /*!< ADC Signed saturation Enable */
3381
3382
3383 /******************** Bit definition for ADC_OFR3 register ********************/
3384 #define ADC_OFR3_OFFSET3_Pos (0U)
3385 #define ADC_OFR3_OFFSET3_Msk (0x3FFFFFFUL << ADC_OFR3_OFFSET3_Pos) /*!< 0x03FFFFFF */
3386 #define ADC_OFR3_OFFSET3 ADC_OFR3_OFFSET3_Msk /*!< ADC data offset 3 for channel programmed into bits OFFSET3_CH[4:0] */
3387 #define ADC_OFR3_OFFSET3_0 (0x0000001UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000001 */
3388 #define ADC_OFR3_OFFSET3_1 (0x0000002UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000002 */
3389 #define ADC_OFR3_OFFSET3_2 (0x0000004UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000004 */
3390 #define ADC_OFR3_OFFSET3_3 (0x0000008UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000008 */
3391 #define ADC_OFR3_OFFSET3_4 (0x0000010UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000010 */
3392 #define ADC_OFR3_OFFSET3_5 (0x0000020UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000020 */
3393 #define ADC_OFR3_OFFSET3_6 (0x0000040UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000040 */
3394 #define ADC_OFR3_OFFSET3_7 (0x0000080UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000080 */
3395 #define ADC_OFR3_OFFSET3_8 (0x0000100UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000100 */
3396 #define ADC_OFR3_OFFSET3_9 (0x0000200UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000200 */
3397 #define ADC_OFR3_OFFSET3_10 (0x0000400UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000400 */
3398 #define ADC_OFR3_OFFSET3_11 (0x0000800UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00000800 */
3399 #define ADC_OFR3_OFFSET3_12 (0x0001000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00001000 */
3400 #define ADC_OFR3_OFFSET3_13 (0x0002000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00002000 */
3401 #define ADC_OFR3_OFFSET3_14 (0x0004000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00004000 */
3402 #define ADC_OFR3_OFFSET3_15 (0x0008000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00008000 */
3403 #define ADC_OFR3_OFFSET3_16 (0x0010000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00010000 */
3404 #define ADC_OFR3_OFFSET3_17 (0x0020000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00020000 */
3405 #define ADC_OFR3_OFFSET3_18 (0x0040000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00040000 */
3406 #define ADC_OFR3_OFFSET3_19 (0x0080000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00080000 */
3407 #define ADC_OFR3_OFFSET3_20 (0x0100000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00100000 */
3408 #define ADC_OFR3_OFFSET3_21 (0x0200000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00200000 */
3409 #define ADC_OFR3_OFFSET3_22 (0x0400000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00400000 */
3410 #define ADC_OFR3_OFFSET3_23 (0x0800000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x00800000 */
3411 #define ADC_OFR3_OFFSET3_24 (0x1000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x01000000 */
3412 #define ADC_OFR3_OFFSET3_25 (0x2000000UL << ADC_OFR3_OFFSET3_Pos) /*!< 0x02000000 */
3413
3414 #define ADC_OFR3_OFFSET3_CH_Pos (26U)
3415 #define ADC_OFR3_OFFSET3_CH_Msk (0x1FUL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x7C000000 */
3416 #define ADC_OFR3_OFFSET3_CH ADC_OFR3_OFFSET3_CH_Msk /*!< ADC Channel selection for the data offset 3 */
3417 #define ADC_OFR3_OFFSET3_CH_0 (0x01UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x04000000 */
3418 #define ADC_OFR3_OFFSET3_CH_1 (0x02UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x08000000 */
3419 #define ADC_OFR3_OFFSET3_CH_2 (0x04UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x10000000 */
3420 #define ADC_OFR3_OFFSET3_CH_3 (0x08UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x20000000 */
3421 #define ADC_OFR3_OFFSET3_CH_4 (0x10UL << ADC_OFR3_OFFSET3_CH_Pos) /*!< 0x40000000 */
3422
3423 #define ADC_OFR3_SSATE_Pos (31U)
3424 #define ADC_OFR3_SSATE_Msk (0x1UL << ADC_OFR3_SSATE_Pos) /*!< 0x80000000 */
3425 #define ADC_OFR3_SSATE ADC_OFR3_SSATE_Msk /*!< ADC Signed saturation Enable */
3426
3427
3428 /******************** Bit definition for ADC_OFR4 register ********************/
3429 #define ADC_OFR4_OFFSET4_Pos (0U)
3430 #define ADC_OFR4_OFFSET4_Msk (0x3FFFFFFUL << ADC_OFR4_OFFSET4_Pos) /*!< 0x03FFFFFF */
3431 #define ADC_OFR4_OFFSET4 ADC_OFR4_OFFSET4_Msk /*!< ADC data offset 4 for channel programmed into bits OFFSET4_CH[4:0] */
3432 #define ADC_OFR4_OFFSET4_0 (0x0000001UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000001 */
3433 #define ADC_OFR4_OFFSET4_1 (0x0000002UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000002 */
3434 #define ADC_OFR4_OFFSET4_2 (0x0000004UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000004 */
3435 #define ADC_OFR4_OFFSET4_3 (0x0000008UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000008 */
3436 #define ADC_OFR4_OFFSET4_4 (0x0000010UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000010 */
3437 #define ADC_OFR4_OFFSET4_5 (0x0000020UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000020 */
3438 #define ADC_OFR4_OFFSET4_6 (0x0000040UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000040 */
3439 #define ADC_OFR4_OFFSET4_7 (0x0000080UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000080 */
3440 #define ADC_OFR4_OFFSET4_8 (0x0000100UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000100 */
3441 #define ADC_OFR4_OFFSET4_9 (0x0000200UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000200 */
3442 #define ADC_OFR4_OFFSET4_10 (0x0000400UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000400 */
3443 #define ADC_OFR4_OFFSET4_11 (0x0000800UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00000800 */
3444 #define ADC_OFR4_OFFSET4_12 (0x0001000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00001000 */
3445 #define ADC_OFR4_OFFSET4_13 (0x0002000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00002000 */
3446 #define ADC_OFR4_OFFSET4_14 (0x0004000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00004000 */
3447 #define ADC_OFR4_OFFSET4_15 (0x0008000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00008000 */
3448 #define ADC_OFR4_OFFSET4_16 (0x0010000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00010000 */
3449 #define ADC_OFR4_OFFSET4_17 (0x0020000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00020000 */
3450 #define ADC_OFR4_OFFSET4_18 (0x0040000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00040000 */
3451 #define ADC_OFR4_OFFSET4_19 (0x0080000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00080000 */
3452 #define ADC_OFR4_OFFSET4_20 (0x0100000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00100000 */
3453 #define ADC_OFR4_OFFSET4_21 (0x0200000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00200000 */
3454 #define ADC_OFR4_OFFSET4_22 (0x0400000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00400000 */
3455 #define ADC_OFR4_OFFSET4_23 (0x0800000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x00800000 */
3456 #define ADC_OFR4_OFFSET4_24 (0x1000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x01000000 */
3457 #define ADC_OFR4_OFFSET4_25 (0x2000000UL << ADC_OFR4_OFFSET4_Pos) /*!< 0x02000000 */
3458
3459 #define ADC_OFR4_OFFSET4_CH_Pos (26U)
3460 #define ADC_OFR4_OFFSET4_CH_Msk (0x1FUL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x7C000000 */
3461 #define ADC_OFR4_OFFSET4_CH ADC_OFR4_OFFSET4_CH_Msk /*!< ADC Channel selection for the data offset 4 */
3462 #define ADC_OFR4_OFFSET4_CH_0 (0x01UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x04000000 */
3463 #define ADC_OFR4_OFFSET4_CH_1 (0x02UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x08000000 */
3464 #define ADC_OFR4_OFFSET4_CH_2 (0x04UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x10000000 */
3465 #define ADC_OFR4_OFFSET4_CH_3 (0x08UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x20000000 */
3466 #define ADC_OFR4_OFFSET4_CH_4 (0x10UL << ADC_OFR4_OFFSET4_CH_Pos) /*!< 0x40000000 */
3467
3468 #define ADC_OFR4_SSATE_Pos (31U)
3469 #define ADC_OFR4_SSATE_Msk (0x1UL << ADC_OFR4_SSATE_Pos) /*!< 0x80000000 */
3470 #define ADC_OFR4_SSATE ADC_OFR4_SSATE_Msk /*!< ADC Signed saturation Enable */
3471
3472
3473 /******************** Bit definition for ADC_JDR1 register ********************/
3474 #define ADC_JDR1_JDATA_Pos (0U)
3475 #define ADC_JDR1_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR1_JDATA_Pos) /*!< 0xFFFFFFFF */
3476 #define ADC_JDR1_JDATA ADC_JDR1_JDATA_Msk /*!< ADC Injected DATA */
3477 #define ADC_JDR1_JDATA_0 (0x00000001UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000001 */
3478 #define ADC_JDR1_JDATA_1 (0x00000002UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000002 */
3479 #define ADC_JDR1_JDATA_2 (0x00000004UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000004 */
3480 #define ADC_JDR1_JDATA_3 (0x00000008UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000008 */
3481 #define ADC_JDR1_JDATA_4 (0x00000010UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000010 */
3482 #define ADC_JDR1_JDATA_5 (0x00000020UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000020 */
3483 #define ADC_JDR1_JDATA_6 (0x00000040UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000040 */
3484 #define ADC_JDR1_JDATA_7 (0x00000080UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000080 */
3485 #define ADC_JDR1_JDATA_8 (0x00000100UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000100 */
3486 #define ADC_JDR1_JDATA_9 (0x00000200UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000200 */
3487 #define ADC_JDR1_JDATA_10 (0x00000400UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000400 */
3488 #define ADC_JDR1_JDATA_11 (0x00000800UL << ADC_JDR1_JDATA_Pos) /*!< 0x00000800 */
3489 #define ADC_JDR1_JDATA_12 (0x00001000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00001000 */
3490 #define ADC_JDR1_JDATA_13 (0x00002000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00002000 */
3491 #define ADC_JDR1_JDATA_14 (0x00004000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00004000 */
3492 #define ADC_JDR1_JDATA_15 (0x00008000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00008000 */
3493 #define ADC_JDR1_JDATA_16 (0x00010000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00010000 */
3494 #define ADC_JDR1_JDATA_17 (0x00020000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00020000 */
3495 #define ADC_JDR1_JDATA_18 (0x00040000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00040000 */
3496 #define ADC_JDR1_JDATA_19 (0x00080000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00080000 */
3497 #define ADC_JDR1_JDATA_20 (0x00100000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00100000 */
3498 #define ADC_JDR1_JDATA_21 (0x00200000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00200000 */
3499 #define ADC_JDR1_JDATA_22 (0x00400000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00400000 */
3500 #define ADC_JDR1_JDATA_23 (0x00800000UL << ADC_JDR1_JDATA_Pos) /*!< 0x00800000 */
3501 #define ADC_JDR1_JDATA_24 (0x01000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x01000000 */
3502 #define ADC_JDR1_JDATA_25 (0x02000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x02000000 */
3503 #define ADC_JDR1_JDATA_26 (0x04000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x04000000 */
3504 #define ADC_JDR1_JDATA_27 (0x08000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x08000000 */
3505 #define ADC_JDR1_JDATA_28 (0x10000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x10000000 */
3506 #define ADC_JDR1_JDATA_29 (0x20000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x20000000 */
3507 #define ADC_JDR1_JDATA_30 (0x40000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x40000000 */
3508 #define ADC_JDR1_JDATA_31 (0x80000000UL << ADC_JDR1_JDATA_Pos) /*!< 0x80000000 */
3509
3510 /******************** Bit definition for ADC_JDR2 register ********************/
3511 #define ADC_JDR2_JDATA_Pos (0U)
3512 #define ADC_JDR2_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR2_JDATA_Pos) /*!< 0xFFFFFFFF */
3513 #define ADC_JDR2_JDATA ADC_JDR2_JDATA_Msk /*!< ADC Injected DATA */
3514 #define ADC_JDR2_JDATA_0 (0x00000001UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000001 */
3515 #define ADC_JDR2_JDATA_1 (0x00000002UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000002 */
3516 #define ADC_JDR2_JDATA_2 (0x00000004UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000004 */
3517 #define ADC_JDR2_JDATA_3 (0x00000008UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000008 */
3518 #define ADC_JDR2_JDATA_4 (0x00000010UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000010 */
3519 #define ADC_JDR2_JDATA_5 (0x00000020UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000020 */
3520 #define ADC_JDR2_JDATA_6 (0x00000040UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000040 */
3521 #define ADC_JDR2_JDATA_7 (0x00000080UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000080 */
3522 #define ADC_JDR2_JDATA_8 (0x00000100UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000100 */
3523 #define ADC_JDR2_JDATA_9 (0x00000200UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000200 */
3524 #define ADC_JDR2_JDATA_10 (0x00000400UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000400 */
3525 #define ADC_JDR2_JDATA_11 (0x00000800UL << ADC_JDR2_JDATA_Pos) /*!< 0x00000800 */
3526 #define ADC_JDR2_JDATA_12 (0x00001000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00001000 */
3527 #define ADC_JDR2_JDATA_13 (0x00002000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00002000 */
3528 #define ADC_JDR2_JDATA_14 (0x00004000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00004000 */
3529 #define ADC_JDR2_JDATA_15 (0x00008000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00008000 */
3530 #define ADC_JDR2_JDATA_16 (0x00010000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00010000 */
3531 #define ADC_JDR2_JDATA_17 (0x00020000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00020000 */
3532 #define ADC_JDR2_JDATA_18 (0x00040000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00040000 */
3533 #define ADC_JDR2_JDATA_19 (0x00080000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00080000 */
3534 #define ADC_JDR2_JDATA_20 (0x00100000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00100000 */
3535 #define ADC_JDR2_JDATA_21 (0x00200000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00200000 */
3536 #define ADC_JDR2_JDATA_22 (0x00400000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00400000 */
3537 #define ADC_JDR2_JDATA_23 (0x00800000UL << ADC_JDR2_JDATA_Pos) /*!< 0x00800000 */
3538 #define ADC_JDR2_JDATA_24 (0x01000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x01000000 */
3539 #define ADC_JDR2_JDATA_25 (0x02000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x02000000 */
3540 #define ADC_JDR2_JDATA_26 (0x04000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x04000000 */
3541 #define ADC_JDR2_JDATA_27 (0x08000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x08000000 */
3542 #define ADC_JDR2_JDATA_28 (0x10000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x10000000 */
3543 #define ADC_JDR2_JDATA_29 (0x20000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x20000000 */
3544 #define ADC_JDR2_JDATA_30 (0x40000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x40000000 */
3545 #define ADC_JDR2_JDATA_31 (0x80000000UL << ADC_JDR2_JDATA_Pos) /*!< 0x80000000 */
3546
3547 /******************** Bit definition for ADC_JDR3 register ********************/
3548 #define ADC_JDR3_JDATA_Pos (0U)
3549 #define ADC_JDR3_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR3_JDATA_Pos) /*!< 0xFFFFFFFF */
3550 #define ADC_JDR3_JDATA ADC_JDR3_JDATA_Msk /*!< ADC Injected DATA */
3551 #define ADC_JDR3_JDATA_0 (0x00000001UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000001 */
3552 #define ADC_JDR3_JDATA_1 (0x00000002UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000002 */
3553 #define ADC_JDR3_JDATA_2 (0x00000004UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000004 */
3554 #define ADC_JDR3_JDATA_3 (0x00000008UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000008 */
3555 #define ADC_JDR3_JDATA_4 (0x00000010UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000010 */
3556 #define ADC_JDR3_JDATA_5 (0x00000020UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000020 */
3557 #define ADC_JDR3_JDATA_6 (0x00000040UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000040 */
3558 #define ADC_JDR3_JDATA_7 (0x00000080UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000080 */
3559 #define ADC_JDR3_JDATA_8 (0x00000100UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000100 */
3560 #define ADC_JDR3_JDATA_9 (0x00000200UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000200 */
3561 #define ADC_JDR3_JDATA_10 (0x00000400UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000400 */
3562 #define ADC_JDR3_JDATA_11 (0x00000800UL << ADC_JDR3_JDATA_Pos) /*!< 0x00000800 */
3563 #define ADC_JDR3_JDATA_12 (0x00001000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00001000 */
3564 #define ADC_JDR3_JDATA_13 (0x00002000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00002000 */
3565 #define ADC_JDR3_JDATA_14 (0x00004000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00004000 */
3566 #define ADC_JDR3_JDATA_15 (0x00008000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00008000 */
3567 #define ADC_JDR3_JDATA_16 (0x00010000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00010000 */
3568 #define ADC_JDR3_JDATA_17 (0x00020000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00020000 */
3569 #define ADC_JDR3_JDATA_18 (0x00040000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00040000 */
3570 #define ADC_JDR3_JDATA_19 (0x00080000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00080000 */
3571 #define ADC_JDR3_JDATA_20 (0x00100000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00100000 */
3572 #define ADC_JDR3_JDATA_21 (0x00200000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00200000 */
3573 #define ADC_JDR3_JDATA_22 (0x00400000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00400000 */
3574 #define ADC_JDR3_JDATA_23 (0x00800000UL << ADC_JDR3_JDATA_Pos) /*!< 0x00800000 */
3575 #define ADC_JDR3_JDATA_24 (0x01000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x01000000 */
3576 #define ADC_JDR3_JDATA_25 (0x02000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x02000000 */
3577 #define ADC_JDR3_JDATA_26 (0x04000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x04000000 */
3578 #define ADC_JDR3_JDATA_27 (0x08000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x08000000 */
3579 #define ADC_JDR3_JDATA_28 (0x10000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x10000000 */
3580 #define ADC_JDR3_JDATA_29 (0x20000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x20000000 */
3581 #define ADC_JDR3_JDATA_30 (0x40000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x40000000 */
3582 #define ADC_JDR3_JDATA_31 (0x80000000UL << ADC_JDR3_JDATA_Pos) /*!< 0x80000000 */
3583
3584 /******************** Bit definition for ADC_JDR4 register ********************/
3585 #define ADC_JDR4_JDATA_Pos (0U)
3586 #define ADC_JDR4_JDATA_Msk (0xFFFFFFFFUL << ADC_JDR4_JDATA_Pos) /*!< 0xFFFFFFFF */
3587 #define ADC_JDR4_JDATA ADC_JDR4_JDATA_Msk /*!< ADC Injected DATA */
3588 #define ADC_JDR4_JDATA_0 (0x00000001UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000001 */
3589 #define ADC_JDR4_JDATA_1 (0x00000002UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000002 */
3590 #define ADC_JDR4_JDATA_2 (0x00000004UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000004 */
3591 #define ADC_JDR4_JDATA_3 (0x00000008UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000008 */
3592 #define ADC_JDR4_JDATA_4 (0x00000010UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000010 */
3593 #define ADC_JDR4_JDATA_5 (0x00000020UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000020 */
3594 #define ADC_JDR4_JDATA_6 (0x00000040UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000040 */
3595 #define ADC_JDR4_JDATA_7 (0x00000080UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000080 */
3596 #define ADC_JDR4_JDATA_8 (0x00000100UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000100 */
3597 #define ADC_JDR4_JDATA_9 (0x00000200UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000200 */
3598 #define ADC_JDR4_JDATA_10 (0x00000400UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000400 */
3599 #define ADC_JDR4_JDATA_11 (0x00000800UL << ADC_JDR4_JDATA_Pos) /*!< 0x00000800 */
3600 #define ADC_JDR4_JDATA_12 (0x00001000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00001000 */
3601 #define ADC_JDR4_JDATA_13 (0x00002000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00002000 */
3602 #define ADC_JDR4_JDATA_14 (0x00004000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00004000 */
3603 #define ADC_JDR4_JDATA_15 (0x00008000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00008000 */
3604 #define ADC_JDR4_JDATA_16 (0x00010000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00010000 */
3605 #define ADC_JDR4_JDATA_17 (0x00020000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00020000 */
3606 #define ADC_JDR4_JDATA_18 (0x00040000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00040000 */
3607 #define ADC_JDR4_JDATA_19 (0x00080000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00080000 */
3608 #define ADC_JDR4_JDATA_20 (0x00100000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00100000 */
3609 #define ADC_JDR4_JDATA_21 (0x00200000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00200000 */
3610 #define ADC_JDR4_JDATA_22 (0x00400000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00400000 */
3611 #define ADC_JDR4_JDATA_23 (0x00800000UL << ADC_JDR4_JDATA_Pos) /*!< 0x00800000 */
3612 #define ADC_JDR4_JDATA_24 (0x01000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x01000000 */
3613 #define ADC_JDR4_JDATA_25 (0x02000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x02000000 */
3614 #define ADC_JDR4_JDATA_26 (0x04000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x04000000 */
3615 #define ADC_JDR4_JDATA_27 (0x08000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x08000000 */
3616 #define ADC_JDR4_JDATA_28 (0x10000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x10000000 */
3617 #define ADC_JDR4_JDATA_29 (0x20000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x20000000 */
3618 #define ADC_JDR4_JDATA_30 (0x40000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x40000000 */
3619 #define ADC_JDR4_JDATA_31 (0x80000000UL << ADC_JDR4_JDATA_Pos) /*!< 0x80000000 */
3620
3621 /******************** Bit definition for ADC_AWD2CR register ********************/
3622 #define ADC_AWD2CR_AWD2CH_Pos (0U)
3623 #define ADC_AWD2CR_AWD2CH_Msk (0xFFFFFUL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x000FFFFF */
3624 #define ADC_AWD2CR_AWD2CH ADC_AWD2CR_AWD2CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3625 #define ADC_AWD2CR_AWD2CH_0 (0x00001UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000001 */
3626 #define ADC_AWD2CR_AWD2CH_1 (0x00002UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000002 */
3627 #define ADC_AWD2CR_AWD2CH_2 (0x00004UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000004 */
3628 #define ADC_AWD2CR_AWD2CH_3 (0x00008UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000008 */
3629 #define ADC_AWD2CR_AWD2CH_4 (0x00010UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000010 */
3630 #define ADC_AWD2CR_AWD2CH_5 (0x00020UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000020 */
3631 #define ADC_AWD2CR_AWD2CH_6 (0x00040UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000040 */
3632 #define ADC_AWD2CR_AWD2CH_7 (0x00080UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000080 */
3633 #define ADC_AWD2CR_AWD2CH_8 (0x00100UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000100 */
3634 #define ADC_AWD2CR_AWD2CH_9 (0x00200UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000200 */
3635 #define ADC_AWD2CR_AWD2CH_10 (0x00400UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000400 */
3636 #define ADC_AWD2CR_AWD2CH_11 (0x00800UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00000800 */
3637 #define ADC_AWD2CR_AWD2CH_12 (0x01000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00001000 */
3638 #define ADC_AWD2CR_AWD2CH_13 (0x02000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00002000 */
3639 #define ADC_AWD2CR_AWD2CH_14 (0x04000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00004000 */
3640 #define ADC_AWD2CR_AWD2CH_15 (0x08000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00008000 */
3641 #define ADC_AWD2CR_AWD2CH_16 (0x10000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00010000 */
3642 #define ADC_AWD2CR_AWD2CH_17 (0x20000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00020000 */
3643 #define ADC_AWD2CR_AWD2CH_18 (0x40000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00040000 */
3644 #define ADC_AWD2CR_AWD2CH_19 (0x80000UL << ADC_AWD2CR_AWD2CH_Pos) /*!< 0x00080000 */
3645
3646 /******************** Bit definition for ADC_AWD3CR register ********************/
3647 #define ADC_AWD3CR_AWD3CH_Pos (0U)
3648 #define ADC_AWD3CR_AWD3CH_Msk (0xFFFFFUL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x000FFFFF */
3649 #define ADC_AWD3CR_AWD3CH ADC_AWD3CR_AWD3CH_Msk /*!< ADC Analog watchdog 2 channel selection */
3650 #define ADC_AWD3CR_AWD3CH_0 (0x00001UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000001 */
3651 #define ADC_AWD3CR_AWD3CH_1 (0x00002UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000002 */
3652 #define ADC_AWD3CR_AWD3CH_2 (0x00004UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000004 */
3653 #define ADC_AWD3CR_AWD3CH_3 (0x00008UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000008 */
3654 #define ADC_AWD3CR_AWD3CH_4 (0x00010UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000010 */
3655 #define ADC_AWD3CR_AWD3CH_5 (0x00020UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000020 */
3656 #define ADC_AWD3CR_AWD3CH_6 (0x00040UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000040 */
3657 #define ADC_AWD3CR_AWD3CH_7 (0x00080UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000080 */
3658 #define ADC_AWD3CR_AWD3CH_8 (0x00100UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000100 */
3659 #define ADC_AWD3CR_AWD3CH_9 (0x00200UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000200 */
3660 #define ADC_AWD3CR_AWD3CH_10 (0x00400UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000400 */
3661 #define ADC_AWD3CR_AWD3CH_11 (0x00800UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00000800 */
3662 #define ADC_AWD3CR_AWD3CH_12 (0x01000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00001000 */
3663 #define ADC_AWD3CR_AWD3CH_13 (0x02000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00002000 */
3664 #define ADC_AWD3CR_AWD3CH_14 (0x04000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00004000 */
3665 #define ADC_AWD3CR_AWD3CH_15 (0x08000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00008000 */
3666 #define ADC_AWD3CR_AWD3CH_16 (0x10000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00010000 */
3667 #define ADC_AWD3CR_AWD3CH_17 (0x20000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00020000 */
3668 #define ADC_AWD3CR_AWD3CH_18 (0x40000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00040000 */
3669 #define ADC_AWD3CR_AWD3CH_19 (0x80000UL << ADC_AWD3CR_AWD3CH_Pos) /*!< 0x00080000 */
3670
3671 /******************** Bit definition for ADC_DIFSEL register ********************/
3672 #define ADC_DIFSEL_DIFSEL_Pos (0U)
3673 #define ADC_DIFSEL_DIFSEL_Msk (0xFFFFFUL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x000FFFFF */
3674 #define ADC_DIFSEL_DIFSEL ADC_DIFSEL_DIFSEL_Msk /*!< ADC differential modes for channels 1 to 18 */
3675 #define ADC_DIFSEL_DIFSEL_0 (0x00001UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000001 */
3676 #define ADC_DIFSEL_DIFSEL_1 (0x00002UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000002 */
3677 #define ADC_DIFSEL_DIFSEL_2 (0x00004UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000004 */
3678 #define ADC_DIFSEL_DIFSEL_3 (0x00008UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000008 */
3679 #define ADC_DIFSEL_DIFSEL_4 (0x00010UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000010 */
3680 #define ADC_DIFSEL_DIFSEL_5 (0x00020UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000020 */
3681 #define ADC_DIFSEL_DIFSEL_6 (0x00040UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000040 */
3682 #define ADC_DIFSEL_DIFSEL_7 (0x00080UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000080 */
3683 #define ADC_DIFSEL_DIFSEL_8 (0x00100UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000100 */
3684 #define ADC_DIFSEL_DIFSEL_9 (0x00200UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000200 */
3685 #define ADC_DIFSEL_DIFSEL_10 (0x00400UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000400 */
3686 #define ADC_DIFSEL_DIFSEL_11 (0x00800UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00000800 */
3687 #define ADC_DIFSEL_DIFSEL_12 (0x01000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00001000 */
3688 #define ADC_DIFSEL_DIFSEL_13 (0x02000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00002000 */
3689 #define ADC_DIFSEL_DIFSEL_14 (0x04000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00004000 */
3690 #define ADC_DIFSEL_DIFSEL_15 (0x08000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00008000 */
3691 #define ADC_DIFSEL_DIFSEL_16 (0x10000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00010000 */
3692 #define ADC_DIFSEL_DIFSEL_17 (0x20000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00020000 */
3693 #define ADC_DIFSEL_DIFSEL_18 (0x40000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00040000 */
3694 #define ADC_DIFSEL_DIFSEL_19 (0x80000UL << ADC_DIFSEL_DIFSEL_Pos) /*!< 0x00080000 */
3695
3696 /******************** Bit definition for ADC_CALFACT register ********************/
3697 #define ADC_CALFACT_CALFACT_S_Pos (0U)
3698 #define ADC_CALFACT_CALFACT_S_Msk (0x7FFUL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x000007FF */
3699 #define ADC_CALFACT_CALFACT_S ADC_CALFACT_CALFACT_S_Msk /*!< ADC calibration factors in single-ended mode */
3700 #define ADC_CALFACT_CALFACT_S_0 (0x001UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000001 */
3701 #define ADC_CALFACT_CALFACT_S_1 (0x002UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000002 */
3702 #define ADC_CALFACT_CALFACT_S_2 (0x004UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000004 */
3703 #define ADC_CALFACT_CALFACT_S_3 (0x008UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000008 */
3704 #define ADC_CALFACT_CALFACT_S_4 (0x010UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000010 */
3705 #define ADC_CALFACT_CALFACT_S_5 (0x020UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000020 */
3706 #define ADC_CALFACT_CALFACT_S_6 (0x040UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000040 */
3707 #define ADC_CALFACT_CALFACT_S_7 (0x080UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000080 */
3708 #define ADC_CALFACT_CALFACT_S_8 (0x100UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000100 */
3709 #define ADC_CALFACT_CALFACT_S_9 (0x200UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000200 */
3710 #define ADC_CALFACT_CALFACT_S_10 (0x400UL << ADC_CALFACT_CALFACT_S_Pos) /*!< 0x00000400 */
3711 #define ADC_CALFACT_CALFACT_D_Pos (16U)
3712 #define ADC_CALFACT_CALFACT_D_Msk (0x7FFUL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x07FF0000 */
3713 #define ADC_CALFACT_CALFACT_D ADC_CALFACT_CALFACT_D_Msk /*!< ADC calibration factors in differential mode */
3714 #define ADC_CALFACT_CALFACT_D_0 (0x001UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00010000 */
3715 #define ADC_CALFACT_CALFACT_D_1 (0x002UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00020000 */
3716 #define ADC_CALFACT_CALFACT_D_2 (0x004UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00040000 */
3717 #define ADC_CALFACT_CALFACT_D_3 (0x008UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00080000 */
3718 #define ADC_CALFACT_CALFACT_D_4 (0x010UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00100000 */
3719 #define ADC_CALFACT_CALFACT_D_5 (0x020UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00200000 */
3720 #define ADC_CALFACT_CALFACT_D_6 (0x040UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00400000 */
3721 #define ADC_CALFACT_CALFACT_D_7 (0x080UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x00800000 */
3722 #define ADC_CALFACT_CALFACT_D_8 (0x100UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x01000000 */
3723 #define ADC_CALFACT_CALFACT_D_9 (0x200UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x02000000 */
3724 #define ADC_CALFACT_CALFACT_D_10 (0x400UL << ADC_CALFACT_CALFACT_D_Pos) /*!< 0x04000000 */
3725
3726 /******************** Bit definition for ADC_CALFACT2 register ********************/
3727 #define ADC_CALFACT2_LINCALFACT_Pos (0U)
3728 #define ADC_CALFACT2_LINCALFACT_Msk (0x3FFFFFFFUL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x3FFFFFFF */
3729 #define ADC_CALFACT2_LINCALFACT ADC_CALFACT2_LINCALFACT_Msk /*!< ADC Linearity calibration factors */
3730 #define ADC_CALFACT2_LINCALFACT_0 (0x00000001UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000001 */
3731 #define ADC_CALFACT2_LINCALFACT_1 (0x00000002UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000002 */
3732 #define ADC_CALFACT2_LINCALFACT_2 (0x00000004UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000004 */
3733 #define ADC_CALFACT2_LINCALFACT_3 (0x00000008UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000008 */
3734 #define ADC_CALFACT2_LINCALFACT_4 (0x00000010UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000010 */
3735 #define ADC_CALFACT2_LINCALFACT_5 (0x00000020UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000020 */
3736 #define ADC_CALFACT2_LINCALFACT_6 (0x00000040UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000040 */
3737 #define ADC_CALFACT2_LINCALFACT_7 (0x00000080UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000080 */
3738 #define ADC_CALFACT2_LINCALFACT_8 (0x00000100UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000100 */
3739 #define ADC_CALFACT2_LINCALFACT_9 (0x00000200UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000200 */
3740 #define ADC_CALFACT2_LINCALFACT_10 (0x00000400UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000400 */
3741 #define ADC_CALFACT2_LINCALFACT_11 (0x00000800UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00000800 */
3742 #define ADC_CALFACT2_LINCALFACT_12 (0x00001000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00001000 */
3743 #define ADC_CALFACT2_LINCALFACT_13 (0x00002000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00002000 */
3744 #define ADC_CALFACT2_LINCALFACT_14 (0x00004000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00004000 */
3745 #define ADC_CALFACT2_LINCALFACT_15 (0x00008000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00008000 */
3746 #define ADC_CALFACT2_LINCALFACT_16 (0x00010000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00010000 */
3747 #define ADC_CALFACT2_LINCALFACT_17 (0x00020000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00020000 */
3748 #define ADC_CALFACT2_LINCALFACT_18 (0x00040000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00040000 */
3749 #define ADC_CALFACT2_LINCALFACT_19 (0x00080000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00080000 */
3750 #define ADC_CALFACT2_LINCALFACT_20 (0x00100000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00100000 */
3751 #define ADC_CALFACT2_LINCALFACT_21 (0x00200000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00200000 */
3752 #define ADC_CALFACT2_LINCALFACT_22 (0x00400000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00400000 */
3753 #define ADC_CALFACT2_LINCALFACT_23 (0x00800000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x00800000 */
3754 #define ADC_CALFACT2_LINCALFACT_24 (0x01000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x01000000 */
3755 #define ADC_CALFACT2_LINCALFACT_25 (0x02000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x02000000 */
3756 #define ADC_CALFACT2_LINCALFACT_26 (0x04000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x04000000 */
3757 #define ADC_CALFACT2_LINCALFACT_27 (0x08000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x08000000 */
3758 #define ADC_CALFACT2_LINCALFACT_28 (0x10000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x10000000 */
3759 #define ADC_CALFACT2_LINCALFACT_29 (0x20000000UL << ADC_CALFACT2_LINCALFACT_Pos) /*!< 0x20000000 */
3760
3761 /************************* ADC Common registers *****************************/
3762 /******************** Bit definition for ADC_CSR register ********************/
3763 #define ADC_CSR_ADRDY_MST_Pos (0U)
3764 #define ADC_CSR_ADRDY_MST_Msk (0x1UL << ADC_CSR_ADRDY_MST_Pos) /*!< 0x00000001 */
3765 #define ADC_CSR_ADRDY_MST ADC_CSR_ADRDY_MST_Msk /*!< Master ADC ready */
3766 #define ADC_CSR_EOSMP_MST_Pos (1U)
3767 #define ADC_CSR_EOSMP_MST_Msk (0x1UL << ADC_CSR_EOSMP_MST_Pos) /*!< 0x00000002 */
3768 #define ADC_CSR_EOSMP_MST ADC_CSR_EOSMP_MST_Msk /*!< End of sampling phase flag of the master ADC */
3769 #define ADC_CSR_EOC_MST_Pos (2U)
3770 #define ADC_CSR_EOC_MST_Msk (0x1UL << ADC_CSR_EOC_MST_Pos) /*!< 0x00000004 */
3771 #define ADC_CSR_EOC_MST ADC_CSR_EOC_MST_Msk /*!< End of regular conversion of the master ADC */
3772 #define ADC_CSR_EOS_MST_Pos (3U)
3773 #define ADC_CSR_EOS_MST_Msk (0x1UL << ADC_CSR_EOS_MST_Pos) /*!< 0x00000008 */
3774 #define ADC_CSR_EOS_MST ADC_CSR_EOS_MST_Msk /*!< End of regular sequence flag of the master ADC */
3775 #define ADC_CSR_OVR_MST_Pos (4U)
3776 #define ADC_CSR_OVR_MST_Msk (0x1UL << ADC_CSR_OVR_MST_Pos) /*!< 0x00000010 */
3777 #define ADC_CSR_OVR_MST ADC_CSR_OVR_MST_Msk /*!< Overrun flag of the master ADC */
3778 #define ADC_CSR_JEOC_MST_Pos (5U)
3779 #define ADC_CSR_JEOC_MST_Msk (0x1UL << ADC_CSR_JEOC_MST_Pos) /*!< 0x00000020 */
3780 #define ADC_CSR_JEOC_MST ADC_CSR_JEOC_MST_Msk /*!< End of injected conversion of the master ADC */
3781 #define ADC_CSR_JEOS_MST_Pos (6U)
3782 #define ADC_CSR_JEOS_MST_Msk (0x1UL << ADC_CSR_JEOS_MST_Pos) /*!< 0x00000040 */
3783 #define ADC_CSR_JEOS_MST ADC_CSR_JEOS_MST_Msk /*!< End of injected sequence flag of the master ADC */
3784 #define ADC_CSR_AWD1_MST_Pos (7U)
3785 #define ADC_CSR_AWD1_MST_Msk (0x1UL << ADC_CSR_AWD1_MST_Pos) /*!< 0x00000080 */
3786 #define ADC_CSR_AWD1_MST ADC_CSR_AWD1_MST_Msk /*!< Analog watchdog 1 flag of the master ADC */
3787 #define ADC_CSR_AWD2_MST_Pos (8U)
3788 #define ADC_CSR_AWD2_MST_Msk (0x1UL << ADC_CSR_AWD2_MST_Pos) /*!< 0x00000100 */
3789 #define ADC_CSR_AWD2_MST ADC_CSR_AWD2_MST_Msk /*!< Analog watchdog 2 flag of the master ADC */
3790 #define ADC_CSR_AWD3_MST_Pos (9U)
3791 #define ADC_CSR_AWD3_MST_Msk (0x1UL << ADC_CSR_AWD3_MST_Pos) /*!< 0x00000200 */
3792 #define ADC_CSR_AWD3_MST ADC_CSR_AWD3_MST_Msk /*!< Analog watchdog 3 flag of the master ADC */
3793 #define ADC_CSR_JQOVF_MST_Pos (10U)
3794 #define ADC_CSR_JQOVF_MST_Msk (0x1UL << ADC_CSR_JQOVF_MST_Pos) /*!< 0x00000400 */
3795 #define ADC_CSR_JQOVF_MST ADC_CSR_JQOVF_MST_Msk /*!< Injected context queue overflow flag of the master ADC */
3796 #define ADC_CSR_ADRDY_SLV_Pos (16U)
3797 #define ADC_CSR_ADRDY_SLV_Msk (0x1UL << ADC_CSR_ADRDY_SLV_Pos) /*!< 0x00010000 */
3798 #define ADC_CSR_ADRDY_SLV ADC_CSR_ADRDY_SLV_Msk /*!< Slave ADC ready */
3799 #define ADC_CSR_EOSMP_SLV_Pos (17U)
3800 #define ADC_CSR_EOSMP_SLV_Msk (0x1UL << ADC_CSR_EOSMP_SLV_Pos) /*!< 0x00020000 */
3801 #define ADC_CSR_EOSMP_SLV ADC_CSR_EOSMP_SLV_Msk /*!< End of sampling phase flag of the slave ADC */
3802 #define ADC_CSR_EOC_SLV_Pos (18U)
3803 #define ADC_CSR_EOC_SLV_Msk (0x1UL << ADC_CSR_EOC_SLV_Pos) /*!< 0x00040000 */
3804 #define ADC_CSR_EOC_SLV ADC_CSR_EOC_SLV_Msk /*!< End of regular conversion of the slave ADC */
3805 #define ADC_CSR_EOS_SLV_Pos (19U)
3806 #define ADC_CSR_EOS_SLV_Msk (0x1UL << ADC_CSR_EOS_SLV_Pos) /*!< 0x00080000 */
3807 #define ADC_CSR_EOS_SLV ADC_CSR_EOS_SLV_Msk /*!< End of regular sequence flag of the slave ADC */
3808 #define ADC_CSR_OVR_SLV_Pos (20U)
3809 #define ADC_CSR_OVR_SLV_Msk (0x1UL << ADC_CSR_OVR_SLV_Pos) /*!< 0x00100000 */
3810 #define ADC_CSR_OVR_SLV ADC_CSR_OVR_SLV_Msk /*!< Overrun flag of the slave ADC */
3811 #define ADC_CSR_JEOC_SLV_Pos (21U)
3812 #define ADC_CSR_JEOC_SLV_Msk (0x1UL << ADC_CSR_JEOC_SLV_Pos) /*!< 0x00200000 */
3813 #define ADC_CSR_JEOC_SLV ADC_CSR_JEOC_SLV_Msk /*!< End of injected conversion of the slave ADC */
3814 #define ADC_CSR_JEOS_SLV_Pos (22U)
3815 #define ADC_CSR_JEOS_SLV_Msk (0x1UL << ADC_CSR_JEOS_SLV_Pos) /*!< 0x00400000 */
3816 #define ADC_CSR_JEOS_SLV ADC_CSR_JEOS_SLV_Msk /*!< End of injected sequence flag of the slave ADC */
3817 #define ADC_CSR_AWD1_SLV_Pos (23U)
3818 #define ADC_CSR_AWD1_SLV_Msk (0x1UL << ADC_CSR_AWD1_SLV_Pos) /*!< 0x00800000 */
3819 #define ADC_CSR_AWD1_SLV ADC_CSR_AWD1_SLV_Msk /*!< Analog watchdog 1 flag of the slave ADC */
3820 #define ADC_CSR_AWD2_SLV_Pos (24U)
3821 #define ADC_CSR_AWD2_SLV_Msk (0x1UL << ADC_CSR_AWD2_SLV_Pos) /*!< 0x01000000 */
3822 #define ADC_CSR_AWD2_SLV ADC_CSR_AWD2_SLV_Msk /*!< Analog watchdog 2 flag of the slave ADC */
3823 #define ADC_CSR_AWD3_SLV_Pos (25U)
3824 #define ADC_CSR_AWD3_SLV_Msk (0x1UL << ADC_CSR_AWD3_SLV_Pos) /*!< 0x02000000 */
3825 #define ADC_CSR_AWD3_SLV ADC_CSR_AWD3_SLV_Msk /*!< Analog watchdog 3 flag of the slave ADC */
3826 #define ADC_CSR_JQOVF_SLV_Pos (26U)
3827 #define ADC_CSR_JQOVF_SLV_Msk (0x1UL << ADC_CSR_JQOVF_SLV_Pos) /*!< 0x04000000 */
3828 #define ADC_CSR_JQOVF_SLV ADC_CSR_JQOVF_SLV_Msk /*!< Injected context queue overflow flag of the slave ADC */
3829
3830 /******************** Bit definition for ADC_CCR register ********************/
3831 #define ADC_CCR_DUAL_Pos (0U)
3832 #define ADC_CCR_DUAL_Msk (0x1FUL << ADC_CCR_DUAL_Pos) /*!< 0x0000001F */
3833 #define ADC_CCR_DUAL ADC_CCR_DUAL_Msk /*!< Dual ADC mode selection */
3834 #define ADC_CCR_DUAL_0 (0x01UL << ADC_CCR_DUAL_Pos) /*!< 0x00000001 */
3835 #define ADC_CCR_DUAL_1 (0x02UL << ADC_CCR_DUAL_Pos) /*!< 0x00000002 */
3836 #define ADC_CCR_DUAL_2 (0x04UL << ADC_CCR_DUAL_Pos) /*!< 0x00000004 */
3837 #define ADC_CCR_DUAL_3 (0x08UL << ADC_CCR_DUAL_Pos) /*!< 0x00000008 */
3838 #define ADC_CCR_DUAL_4 (0x10UL << ADC_CCR_DUAL_Pos) /*!< 0x00000010 */
3839
3840 #define ADC_CCR_DELAY_Pos (8U)
3841 #define ADC_CCR_DELAY_Msk (0xFUL << ADC_CCR_DELAY_Pos) /*!< 0x00000F00 */
3842 #define ADC_CCR_DELAY ADC_CCR_DELAY_Msk /*!< Delay between 2 sampling phases */
3843 #define ADC_CCR_DELAY_0 (0x1UL << ADC_CCR_DELAY_Pos) /*!< 0x00000100 */
3844 #define ADC_CCR_DELAY_1 (0x2UL << ADC_CCR_DELAY_Pos) /*!< 0x00000200 */
3845 #define ADC_CCR_DELAY_2 (0x4UL << ADC_CCR_DELAY_Pos) /*!< 0x00000400 */
3846 #define ADC_CCR_DELAY_3 (0x8UL << ADC_CCR_DELAY_Pos) /*!< 0x00000800 */
3847
3848
3849 #define ADC_CCR_DAMDF_Pos (14U)
3850 #define ADC_CCR_DAMDF_Msk (0x3UL << ADC_CCR_DAMDF_Pos) /*!< 0x0000C000 */
3851 #define ADC_CCR_DAMDF ADC_CCR_DAMDF_Msk /*!< Dual ADC mode Data format */
3852 #define ADC_CCR_DAMDF_0 (0x1UL << ADC_CCR_DAMDF_Pos) /*!< 0x00004000 */
3853 #define ADC_CCR_DAMDF_1 (0x2UL << ADC_CCR_DAMDF_Pos) /*!< 0x00008000 */
3854
3855 #define ADC_CCR_CKMODE_Pos (16U)
3856 #define ADC_CCR_CKMODE_Msk (0x3UL << ADC_CCR_CKMODE_Pos) /*!< 0x00030000 */
3857 #define ADC_CCR_CKMODE ADC_CCR_CKMODE_Msk /*!< ADC clock mode */
3858 #define ADC_CCR_CKMODE_0 (0x1UL << ADC_CCR_CKMODE_Pos) /*!< 0x00010000 */
3859 #define ADC_CCR_CKMODE_1 (0x2UL << ADC_CCR_CKMODE_Pos) /*!< 0x00020000 */
3860
3861 #define ADC_CCR_PRESC_Pos (18U)
3862 #define ADC_CCR_PRESC_Msk (0xFUL << ADC_CCR_PRESC_Pos) /*!< 0x003C0000 */
3863 #define ADC_CCR_PRESC ADC_CCR_PRESC_Msk /*!< ADC prescaler */
3864 #define ADC_CCR_PRESC_0 (0x1UL << ADC_CCR_PRESC_Pos) /*!< 0x00040000 */
3865 #define ADC_CCR_PRESC_1 (0x2UL << ADC_CCR_PRESC_Pos) /*!< 0x00080000 */
3866 #define ADC_CCR_PRESC_2 (0x4UL << ADC_CCR_PRESC_Pos) /*!< 0x00100000 */
3867 #define ADC_CCR_PRESC_3 (0x8UL << ADC_CCR_PRESC_Pos) /*!< 0x00200000 */
3868
3869 #define ADC_CCR_VREFEN_Pos (22U)
3870 #define ADC_CCR_VREFEN_Msk (0x1UL << ADC_CCR_VREFEN_Pos) /*!< 0x00400000 */
3871 #define ADC_CCR_VREFEN ADC_CCR_VREFEN_Msk /*!< VREFINT enable */
3872 #define ADC_CCR_TSEN_Pos (23U)
3873 #define ADC_CCR_TSEN_Msk (0x1UL << ADC_CCR_TSEN_Pos) /*!< 0x00800000 */
3874 #define ADC_CCR_TSEN ADC_CCR_TSEN_Msk /*!< Temperature sensor enable */
3875 #define ADC_CCR_VBATEN_Pos (24U)
3876 #define ADC_CCR_VBATEN_Msk (0x1UL << ADC_CCR_VBATEN_Pos) /*!< 0x01000000 */
3877 #define ADC_CCR_VBATEN ADC_CCR_VBATEN_Msk /*!< VBAT enable */
3878
3879 /******************** Bit definition for ADC_CDR register *******************/
3880 #define ADC_CDR_RDATA_MST_Pos (0U)
3881 #define ADC_CDR_RDATA_MST_Msk (0xFFFFUL << ADC_CDR_RDATA_MST_Pos) /*!< 0x0000FFFF */
3882 #define ADC_CDR_RDATA_MST ADC_CDR_RDATA_MST_Msk /*!< ADC multimode master group regular conversion data */
3883
3884 #define ADC_CDR_RDATA_SLV_Pos (16U)
3885 #define ADC_CDR_RDATA_SLV_Msk (0xFFFFUL << ADC_CDR_RDATA_SLV_Pos) /*!< 0xFFFF0000 */
3886 #define ADC_CDR_RDATA_SLV ADC_CDR_RDATA_SLV_Msk /*!< ADC multimode slave group regular conversion data */
3887
3888 /******************** Bit definition for ADC_CDR2 register ******************/
3889 #define ADC_CDR2_RDATA_ALT_Pos (0U)
3890 #define ADC_CDR2_RDATA_ALT_Msk (0xFFFFFFFFUL << ADC_CDR2_RDATA_ALT_Pos) /*!< 0xFFFFFFFF */
3891 #define ADC_CDR2_RDATA_ALT ADC_CDR2_RDATA_ALT_Msk /*!< Regular data of the master/slave alternated ADCs */
3892
3893
3894 /******************************************************************************/
3895 /* */
3896 /* VREFBUF */
3897 /* */
3898 /******************************************************************************/
3899 /******************* Bit definition for VREFBUF_CSR register ****************/
3900 #define VREFBUF_CSR_ENVR_Pos (0U)
3901 #define VREFBUF_CSR_ENVR_Msk (0x1UL << VREFBUF_CSR_ENVR_Pos) /*!< 0x00000001 */
3902 #define VREFBUF_CSR_ENVR VREFBUF_CSR_ENVR_Msk /*!<Voltage reference buffer enable */
3903 #define VREFBUF_CSR_HIZ_Pos (1U)
3904 #define VREFBUF_CSR_HIZ_Msk (0x1UL << VREFBUF_CSR_HIZ_Pos) /*!< 0x00000002 */
3905 #define VREFBUF_CSR_HIZ VREFBUF_CSR_HIZ_Msk /*!<High impedance mode */
3906 #define VREFBUF_CSR_VRR_Pos (3U)
3907 #define VREFBUF_CSR_VRR_Msk (0x1UL << VREFBUF_CSR_VRR_Pos) /*!< 0x00000008 */
3908 #define VREFBUF_CSR_VRR VREFBUF_CSR_VRR_Msk /*!<Voltage reference buffer ready */
3909 #define VREFBUF_CSR_VRS_Pos (4U)
3910 #define VREFBUF_CSR_VRS_Msk (0x7UL << VREFBUF_CSR_VRS_Pos) /*!< 0x00000070 */
3911 #define VREFBUF_CSR_VRS VREFBUF_CSR_VRS_Msk /*!<Voltage reference scale */
3912
3913 #define VREFBUF_CSR_VRS_OUT1 ((uint32_t)0x00000000) /*!<Voltage reference VREF_OUT1 */
3914 #define VREFBUF_CSR_VRS_OUT2_Pos (4U)
3915 #define VREFBUF_CSR_VRS_OUT2_Msk (0x1UL << VREFBUF_CSR_VRS_OUT2_Pos) /*!< 0x00000010 */
3916 #define VREFBUF_CSR_VRS_OUT2 VREFBUF_CSR_VRS_OUT2_Msk /*!<Voltage reference VREF_OUT2 */
3917 #define VREFBUF_CSR_VRS_OUT3_Pos (5U)
3918 #define VREFBUF_CSR_VRS_OUT3_Msk (0x1UL << VREFBUF_CSR_VRS_OUT3_Pos) /*!< 0x00000020 */
3919 #define VREFBUF_CSR_VRS_OUT3 VREFBUF_CSR_VRS_OUT3_Msk /*!<Voltage reference VREF_OUT3 */
3920 #define VREFBUF_CSR_VRS_OUT4_Pos (4U)
3921 #define VREFBUF_CSR_VRS_OUT4_Msk (0x3UL << VREFBUF_CSR_VRS_OUT4_Pos) /*!< 0x00000030 */
3922 #define VREFBUF_CSR_VRS_OUT4 VREFBUF_CSR_VRS_OUT4_Msk /*!<Voltage reference VREF_OUT4 */
3923
3924 /******************* Bit definition for VREFBUF_CCR register ****************/
3925 #define VREFBUF_CCR_TRIM_Pos (0U)
3926 #define VREFBUF_CCR_TRIM_Msk (0x3FUL << VREFBUF_CCR_TRIM_Pos) /*!< 0x0000003F */
3927 #define VREFBUF_CCR_TRIM VREFBUF_CCR_TRIM_Msk /*!<TRIM[5:0] bits (Trimming code) */
3928
3929 /******************************************************************************/
3930 /* */
3931 /* Flexible Datarate Controller Area Network */
3932 /* */
3933 /******************************************************************************/
3934 /*!<FDCAN control and status registers */
3935 /***************** Bit definition for FDCAN_CREL register *******************/
3936 #define FDCAN_CREL_DAY_Pos (0U)
3937 #define FDCAN_CREL_DAY_Msk (0xFFUL << FDCAN_CREL_DAY_Pos) /*!< 0x000000FF */
3938 #define FDCAN_CREL_DAY FDCAN_CREL_DAY_Msk /*!<Timestamp Day */
3939 #define FDCAN_CREL_MON_Pos (8U)
3940 #define FDCAN_CREL_MON_Msk (0xFFUL << FDCAN_CREL_MON_Pos) /*!< 0x0000FF00 */
3941 #define FDCAN_CREL_MON FDCAN_CREL_MON_Msk /*!<Timestamp Month */
3942 #define FDCAN_CREL_YEAR_Pos (16U)
3943 #define FDCAN_CREL_YEAR_Msk (0xFUL << FDCAN_CREL_YEAR_Pos) /*!< 0x000F0000 */
3944 #define FDCAN_CREL_YEAR FDCAN_CREL_YEAR_Msk /*!<Timestamp Year */
3945 #define FDCAN_CREL_SUBSTEP_Pos (20U)
3946 #define FDCAN_CREL_SUBSTEP_Msk (0xFUL << FDCAN_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
3947 #define FDCAN_CREL_SUBSTEP FDCAN_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
3948 #define FDCAN_CREL_STEP_Pos (24U)
3949 #define FDCAN_CREL_STEP_Msk (0xFUL << FDCAN_CREL_STEP_Pos) /*!< 0x0F000000 */
3950 #define FDCAN_CREL_STEP FDCAN_CREL_STEP_Msk /*!<Step of Core release */
3951 #define FDCAN_CREL_REL_Pos (28U)
3952 #define FDCAN_CREL_REL_Msk (0xFUL << FDCAN_CREL_REL_Pos) /*!< 0xF0000000 */
3953 #define FDCAN_CREL_REL FDCAN_CREL_REL_Msk /*!<Core release */
3954
3955 /***************** Bit definition for FDCAN_ENDN register *******************/
3956 #define FDCAN_ENDN_ETV_Pos (0U)
3957 #define FDCAN_ENDN_ETV_Msk (0xFFFFFFFFUL << FDCAN_ENDN_ETV_Pos) /*!< 0xFFFFFFFF */
3958 #define FDCAN_ENDN_ETV FDCAN_ENDN_ETV_Msk /*!<Endiannes Test Value */
3959
3960 /***************** Bit definition for FDCAN_DBTP register *******************/
3961 #define FDCAN_DBTP_DSJW_Pos (0U)
3962 #define FDCAN_DBTP_DSJW_Msk (0xFUL << FDCAN_DBTP_DSJW_Pos) /*!< 0x0000000F */
3963 #define FDCAN_DBTP_DSJW FDCAN_DBTP_DSJW_Msk /*!<Synchronization Jump Width */
3964 #define FDCAN_DBTP_DTSEG2_Pos (4U)
3965 #define FDCAN_DBTP_DTSEG2_Msk (0xFUL << FDCAN_DBTP_DTSEG2_Pos) /*!< 0x000000F0 */
3966 #define FDCAN_DBTP_DTSEG2 FDCAN_DBTP_DTSEG2_Msk /*!<Data time segment after sample point */
3967 #define FDCAN_DBTP_DTSEG1_Pos (8U)
3968 #define FDCAN_DBTP_DTSEG1_Msk (0x1FUL << FDCAN_DBTP_DTSEG1_Pos) /*!< 0x00001F00 */
3969 #define FDCAN_DBTP_DTSEG1 FDCAN_DBTP_DTSEG1_Msk /*!<Data time segment before sample point */
3970 #define FDCAN_DBTP_DBRP_Pos (16U)
3971 #define FDCAN_DBTP_DBRP_Msk (0x1FUL << FDCAN_DBTP_DBRP_Pos) /*!< 0x001F0000 */
3972 #define FDCAN_DBTP_DBRP FDCAN_DBTP_DBRP_Msk /*!<Data BIt Rate Prescaler */
3973 #define FDCAN_DBTP_TDC_Pos (23U)
3974 #define FDCAN_DBTP_TDC_Msk (0x1UL << FDCAN_DBTP_TDC_Pos) /*!< 0x00800000 */
3975 #define FDCAN_DBTP_TDC FDCAN_DBTP_TDC_Msk /*!<Transceiver Delay Compensation */
3976
3977 /***************** Bit definition for FDCAN_TEST register *******************/
3978 #define FDCAN_TEST_LBCK_Pos (4U)
3979 #define FDCAN_TEST_LBCK_Msk (0x1UL << FDCAN_TEST_LBCK_Pos) /*!< 0x00000010 */
3980 #define FDCAN_TEST_LBCK FDCAN_TEST_LBCK_Msk /*!<Loop Back mode */
3981 #define FDCAN_TEST_TX_Pos (5U)
3982 #define FDCAN_TEST_TX_Msk (0x3UL << FDCAN_TEST_TX_Pos) /*!< 0x00000060 */
3983 #define FDCAN_TEST_TX FDCAN_TEST_TX_Msk /*!<Control of Transmit Pin */
3984 #define FDCAN_TEST_RX_Pos (7U)
3985 #define FDCAN_TEST_RX_Msk (0x1UL << FDCAN_TEST_RX_Pos) /*!< 0x00000080 */
3986 #define FDCAN_TEST_RX FDCAN_TEST_RX_Msk /*!<Receive Pin */
3987
3988 /***************** Bit definition for FDCAN_RWD register ********************/
3989 #define FDCAN_RWD_WDC_Pos (0U)
3990 #define FDCAN_RWD_WDC_Msk (0xFFUL << FDCAN_RWD_WDC_Pos) /*!< 0x000000FF */
3991 #define FDCAN_RWD_WDC FDCAN_RWD_WDC_Msk /*!<Watchdog configuration */
3992 #define FDCAN_RWD_WDV_Pos (8U)
3993 #define FDCAN_RWD_WDV_Msk (0xFFUL << FDCAN_RWD_WDV_Pos) /*!< 0x0000FF00 */
3994 #define FDCAN_RWD_WDV FDCAN_RWD_WDV_Msk /*!<Watchdog value */
3995
3996 /***************** Bit definition for FDCAN_CCCR register ********************/
3997 #define FDCAN_CCCR_INIT_Pos (0U)
3998 #define FDCAN_CCCR_INIT_Msk (0x1UL << FDCAN_CCCR_INIT_Pos) /*!< 0x00000001 */
3999 #define FDCAN_CCCR_INIT FDCAN_CCCR_INIT_Msk /*!<Initialization */
4000 #define FDCAN_CCCR_CCE_Pos (1U)
4001 #define FDCAN_CCCR_CCE_Msk (0x1UL << FDCAN_CCCR_CCE_Pos) /*!< 0x00000002 */
4002 #define FDCAN_CCCR_CCE FDCAN_CCCR_CCE_Msk /*!<Configuration Change Enable */
4003 #define FDCAN_CCCR_ASM_Pos (2U)
4004 #define FDCAN_CCCR_ASM_Msk (0x1UL << FDCAN_CCCR_ASM_Pos) /*!< 0x00000004 */
4005 #define FDCAN_CCCR_ASM FDCAN_CCCR_ASM_Msk /*!<ASM Restricted Operation Mode */
4006 #define FDCAN_CCCR_CSA_Pos (3U)
4007 #define FDCAN_CCCR_CSA_Msk (0x1UL << FDCAN_CCCR_CSA_Pos) /*!< 0x00000008 */
4008 #define FDCAN_CCCR_CSA FDCAN_CCCR_CSA_Msk /*!<Clock Stop Acknowledge */
4009 #define FDCAN_CCCR_CSR_Pos (4U)
4010 #define FDCAN_CCCR_CSR_Msk (0x1UL << FDCAN_CCCR_CSR_Pos) /*!< 0x00000010 */
4011 #define FDCAN_CCCR_CSR FDCAN_CCCR_CSR_Msk /*!<Clock Stop Request */
4012 #define FDCAN_CCCR_MON_Pos (5U)
4013 #define FDCAN_CCCR_MON_Msk (0x1UL << FDCAN_CCCR_MON_Pos) /*!< 0x00000020 */
4014 #define FDCAN_CCCR_MON FDCAN_CCCR_MON_Msk /*!<Bus Monitoring Mode */
4015 #define FDCAN_CCCR_DAR_Pos (6U)
4016 #define FDCAN_CCCR_DAR_Msk (0x1UL << FDCAN_CCCR_DAR_Pos) /*!< 0x00000040 */
4017 #define FDCAN_CCCR_DAR FDCAN_CCCR_DAR_Msk /*!<Disable Automatic Retransmission */
4018 #define FDCAN_CCCR_TEST_Pos (7U)
4019 #define FDCAN_CCCR_TEST_Msk (0x1UL << FDCAN_CCCR_TEST_Pos) /*!< 0x00000080 */
4020 #define FDCAN_CCCR_TEST FDCAN_CCCR_TEST_Msk /*!<Test Mode Enable */
4021 #define FDCAN_CCCR_FDOE_Pos (8U)
4022 #define FDCAN_CCCR_FDOE_Msk (0x1UL << FDCAN_CCCR_FDOE_Pos) /*!< 0x00000100 */
4023 #define FDCAN_CCCR_FDOE FDCAN_CCCR_FDOE_Msk /*!<FD Operation Enable */
4024 #define FDCAN_CCCR_BRSE_Pos (9U)
4025 #define FDCAN_CCCR_BRSE_Msk (0x1UL << FDCAN_CCCR_BRSE_Pos) /*!< 0x00000200 */
4026 #define FDCAN_CCCR_BRSE FDCAN_CCCR_BRSE_Msk /*!<FDCAN Bit Rate Switching */
4027 #define FDCAN_CCCR_PXHD_Pos (12U)
4028 #define FDCAN_CCCR_PXHD_Msk (0x1UL << FDCAN_CCCR_PXHD_Pos) /*!< 0x00001000 */
4029 #define FDCAN_CCCR_PXHD FDCAN_CCCR_PXHD_Msk /*!<Protocol Exception Handling Disable */
4030 #define FDCAN_CCCR_EFBI_Pos (13U)
4031 #define FDCAN_CCCR_EFBI_Msk (0x1UL << FDCAN_CCCR_EFBI_Pos) /*!< 0x00002000 */
4032 #define FDCAN_CCCR_EFBI FDCAN_CCCR_EFBI_Msk /*!<Edge Filtering during Bus Integration */
4033 #define FDCAN_CCCR_TXP_Pos (14U)
4034 #define FDCAN_CCCR_TXP_Msk (0x1UL << FDCAN_CCCR_TXP_Pos) /*!< 0x00004000 */
4035 #define FDCAN_CCCR_TXP FDCAN_CCCR_TXP_Msk /*!<Two CAN bit times Pause */
4036 #define FDCAN_CCCR_NISO_Pos (15U)
4037 #define FDCAN_CCCR_NISO_Msk (0x1UL << FDCAN_CCCR_NISO_Pos) /*!< 0x00008000 */
4038 #define FDCAN_CCCR_NISO FDCAN_CCCR_NISO_Msk /*!<Non ISO Operation */
4039
4040 /***************** Bit definition for FDCAN_NBTP register ********************/
4041 #define FDCAN_NBTP_NTSEG2_Pos (0U)
4042 #define FDCAN_NBTP_NTSEG2_Msk (0x7FUL << FDCAN_NBTP_NTSEG2_Pos) /*!< 0x0000007F */
4043 #define FDCAN_NBTP_NTSEG2 FDCAN_NBTP_NTSEG2_Msk /*!<Nominal Time segment after sample point */
4044 #define FDCAN_NBTP_NTSEG1_Pos (8U)
4045 #define FDCAN_NBTP_NTSEG1_Msk (0xFFUL << FDCAN_NBTP_NTSEG1_Pos) /*!< 0x0000FF00 */
4046 #define FDCAN_NBTP_NTSEG1 FDCAN_NBTP_NTSEG1_Msk /*!<Nominal Time segment before sample point */
4047 #define FDCAN_NBTP_NBRP_Pos (16U)
4048 #define FDCAN_NBTP_NBRP_Msk (0x1FFUL << FDCAN_NBTP_NBRP_Pos) /*!< 0x01FF0000 */
4049 #define FDCAN_NBTP_NBRP FDCAN_NBTP_NBRP_Msk /*!<Bit Rate Prescaler */
4050 #define FDCAN_NBTP_NSJW_Pos (25U)
4051 #define FDCAN_NBTP_NSJW_Msk (0x7FUL << FDCAN_NBTP_NSJW_Pos) /*!< 0xFE000000 */
4052 #define FDCAN_NBTP_NSJW FDCAN_NBTP_NSJW_Msk /*!<Nominal (Re)Synchronization Jump Width */
4053
4054 /***************** Bit definition for FDCAN_TSCC register ********************/
4055 #define FDCAN_TSCC_TSS_Pos (0U)
4056 #define FDCAN_TSCC_TSS_Msk (0x3UL << FDCAN_TSCC_TSS_Pos) /*!< 0x00000003 */
4057 #define FDCAN_TSCC_TSS FDCAN_TSCC_TSS_Msk /*!<Timestamp Select */
4058 #define FDCAN_TSCC_TCP_Pos (16U)
4059 #define FDCAN_TSCC_TCP_Msk (0xFUL << FDCAN_TSCC_TCP_Pos) /*!< 0x000F0000 */
4060 #define FDCAN_TSCC_TCP FDCAN_TSCC_TCP_Msk /*!<Timestamp Counter Prescaler */
4061
4062 /***************** Bit definition for FDCAN_TSCV register ********************/
4063 #define FDCAN_TSCV_TSC_Pos (0U)
4064 #define FDCAN_TSCV_TSC_Msk (0xFFFFUL << FDCAN_TSCV_TSC_Pos) /*!< 0x0000FFFF */
4065 #define FDCAN_TSCV_TSC FDCAN_TSCV_TSC_Msk /*!<Timestamp Counter */
4066
4067 /***************** Bit definition for FDCAN_TOCC register ********************/
4068 #define FDCAN_TOCC_ETOC_Pos (0U)
4069 #define FDCAN_TOCC_ETOC_Msk (0x1UL << FDCAN_TOCC_ETOC_Pos) /*!< 0x00000001 */
4070 #define FDCAN_TOCC_ETOC FDCAN_TOCC_ETOC_Msk /*!<Enable Timeout Counter */
4071 #define FDCAN_TOCC_TOS_Pos (1U)
4072 #define FDCAN_TOCC_TOS_Msk (0x3UL << FDCAN_TOCC_TOS_Pos) /*!< 0x00000006 */
4073 #define FDCAN_TOCC_TOS FDCAN_TOCC_TOS_Msk /*!<Timeout Select */
4074 #define FDCAN_TOCC_TOP_Pos (16U)
4075 #define FDCAN_TOCC_TOP_Msk (0xFFFFUL << FDCAN_TOCC_TOP_Pos) /*!< 0xFFFF0000 */
4076 #define FDCAN_TOCC_TOP FDCAN_TOCC_TOP_Msk /*!<Timeout Period */
4077
4078 /***************** Bit definition for FDCAN_TOCV register ********************/
4079 #define FDCAN_TOCV_TOC_Pos (0U)
4080 #define FDCAN_TOCV_TOC_Msk (0xFFFFUL << FDCAN_TOCV_TOC_Pos) /*!< 0x0000FFFF */
4081 #define FDCAN_TOCV_TOC FDCAN_TOCV_TOC_Msk /*!<Timeout Counter */
4082
4083 /***************** Bit definition for FDCAN_ECR register *********************/
4084 #define FDCAN_ECR_TEC_Pos (0U)
4085 #define FDCAN_ECR_TEC_Msk (0xFUL << FDCAN_ECR_TEC_Pos) /*!< 0x0000000F */
4086 #define FDCAN_ECR_TEC FDCAN_ECR_TEC_Msk /*!<Transmit Error Counter */
4087 #define FDCAN_ECR_REC_Pos (8U)
4088 #define FDCAN_ECR_REC_Msk (0x7FUL << FDCAN_ECR_REC_Pos) /*!< 0x00007F00 */
4089 #define FDCAN_ECR_REC FDCAN_ECR_REC_Msk /*!<Receive Error Counter */
4090 #define FDCAN_ECR_RP_Pos (15U)
4091 #define FDCAN_ECR_RP_Msk (0x1UL << FDCAN_ECR_RP_Pos) /*!< 0x00008000 */
4092 #define FDCAN_ECR_RP FDCAN_ECR_RP_Msk /*!<Receive Error Passive */
4093 #define FDCAN_ECR_CEL_Pos (16U)
4094 #define FDCAN_ECR_CEL_Msk (0xFFUL << FDCAN_ECR_CEL_Pos) /*!< 0x00FF0000 */
4095 #define FDCAN_ECR_CEL FDCAN_ECR_CEL_Msk /*!<CAN Error Logging */
4096
4097 /***************** Bit definition for FDCAN_PSR register *********************/
4098 #define FDCAN_PSR_LEC_Pos (0U)
4099 #define FDCAN_PSR_LEC_Msk (0x7UL << FDCAN_PSR_LEC_Pos) /*!< 0x00000007 */
4100 #define FDCAN_PSR_LEC FDCAN_PSR_LEC_Msk /*!<Last Error Code */
4101 #define FDCAN_PSR_ACT_Pos (3U)
4102 #define FDCAN_PSR_ACT_Msk (0x3UL << FDCAN_PSR_ACT_Pos) /*!< 0x00000018 */
4103 #define FDCAN_PSR_ACT FDCAN_PSR_ACT_Msk /*!<Activity */
4104 #define FDCAN_PSR_EP_Pos (5U)
4105 #define FDCAN_PSR_EP_Msk (0x1UL << FDCAN_PSR_EP_Pos) /*!< 0x00000020 */
4106 #define FDCAN_PSR_EP FDCAN_PSR_EP_Msk /*!<Error Passive */
4107 #define FDCAN_PSR_EW_Pos (6U)
4108 #define FDCAN_PSR_EW_Msk (0x1UL << FDCAN_PSR_EW_Pos) /*!< 0x00000040 */
4109 #define FDCAN_PSR_EW FDCAN_PSR_EW_Msk /*!<Warning Status */
4110 #define FDCAN_PSR_BO_Pos (7U)
4111 #define FDCAN_PSR_BO_Msk (0x1UL << FDCAN_PSR_BO_Pos) /*!< 0x00000080 */
4112 #define FDCAN_PSR_BO FDCAN_PSR_BO_Msk /*!<Bus_Off Status */
4113 #define FDCAN_PSR_DLEC_Pos (8U)
4114 #define FDCAN_PSR_DLEC_Msk (0x7UL << FDCAN_PSR_DLEC_Pos) /*!< 0x00000700 */
4115 #define FDCAN_PSR_DLEC FDCAN_PSR_DLEC_Msk /*!<Data Last Error Code */
4116 #define FDCAN_PSR_RESI_Pos (11U)
4117 #define FDCAN_PSR_RESI_Msk (0x1UL << FDCAN_PSR_RESI_Pos) /*!< 0x00000800 */
4118 #define FDCAN_PSR_RESI FDCAN_PSR_RESI_Msk /*!<ESI flag of last received FDCAN Message */
4119 #define FDCAN_PSR_RBRS_Pos (12U)
4120 #define FDCAN_PSR_RBRS_Msk (0x1UL << FDCAN_PSR_RBRS_Pos) /*!< 0x00001000 */
4121 #define FDCAN_PSR_RBRS FDCAN_PSR_RBRS_Msk /*!<BRS flag of last received FDCAN Message */
4122 #define FDCAN_PSR_REDL_Pos (13U)
4123 #define FDCAN_PSR_REDL_Msk (0x1UL << FDCAN_PSR_REDL_Pos) /*!< 0x00002000 */
4124 #define FDCAN_PSR_REDL FDCAN_PSR_REDL_Msk /*!<Received FDCAN Message */
4125 #define FDCAN_PSR_PXE_Pos (14U)
4126 #define FDCAN_PSR_PXE_Msk (0x1UL << FDCAN_PSR_PXE_Pos) /*!< 0x00004000 */
4127 #define FDCAN_PSR_PXE FDCAN_PSR_PXE_Msk /*!<Protocol Exception Event */
4128 #define FDCAN_PSR_TDCV_Pos (16U)
4129 #define FDCAN_PSR_TDCV_Msk (0x7FUL << FDCAN_PSR_TDCV_Pos) /*!< 0x007F0000 */
4130 #define FDCAN_PSR_TDCV FDCAN_PSR_TDCV_Msk /*!<Transmitter Delay Compensation Value */
4131
4132 /***************** Bit definition for FDCAN_TDCR register ********************/
4133 #define FDCAN_TDCR_TDCF_Pos (0U)
4134 #define FDCAN_TDCR_TDCF_Msk (0x7FUL << FDCAN_TDCR_TDCF_Pos) /*!< 0x0000007F */
4135 #define FDCAN_TDCR_TDCF FDCAN_TDCR_TDCF_Msk /*!<Transmitter Delay Compensation Filter */
4136 #define FDCAN_TDCR_TDCO_Pos (8U)
4137 #define FDCAN_TDCR_TDCO_Msk (0x7FUL << FDCAN_TDCR_TDCO_Pos) /*!< 0x00007F00 */
4138 #define FDCAN_TDCR_TDCO FDCAN_TDCR_TDCO_Msk /*!<Transmitter Delay Compensation Offset */
4139
4140 /***************** Bit definition for FDCAN_IR register **********************/
4141 #define FDCAN_IR_RF0N_Pos (0U)
4142 #define FDCAN_IR_RF0N_Msk (0x1UL << FDCAN_IR_RF0N_Pos) /*!< 0x00000001 */
4143 #define FDCAN_IR_RF0N FDCAN_IR_RF0N_Msk /*!<Rx FIFO 0 New Message */
4144 #define FDCAN_IR_RF0W_Pos (1U)
4145 #define FDCAN_IR_RF0W_Msk (0x1UL << FDCAN_IR_RF0W_Pos) /*!< 0x00000002 */
4146 #define FDCAN_IR_RF0W FDCAN_IR_RF0W_Msk /*!<Rx FIFO 0 Watermark Reached */
4147 #define FDCAN_IR_RF0F_Pos (2U)
4148 #define FDCAN_IR_RF0F_Msk (0x1UL << FDCAN_IR_RF0F_Pos) /*!< 0x00000004 */
4149 #define FDCAN_IR_RF0F FDCAN_IR_RF0F_Msk /*!<Rx FIFO 0 Full */
4150 #define FDCAN_IR_RF0L_Pos (3U)
4151 #define FDCAN_IR_RF0L_Msk (0x1UL << FDCAN_IR_RF0L_Pos) /*!< 0x00000008 */
4152 #define FDCAN_IR_RF0L FDCAN_IR_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4153 #define FDCAN_IR_RF1N_Pos (4U)
4154 #define FDCAN_IR_RF1N_Msk (0x1UL << FDCAN_IR_RF1N_Pos) /*!< 0x00000010 */
4155 #define FDCAN_IR_RF1N FDCAN_IR_RF1N_Msk /*!<Rx FIFO 1 New Message */
4156 #define FDCAN_IR_RF1W_Pos (5U)
4157 #define FDCAN_IR_RF1W_Msk (0x1UL << FDCAN_IR_RF1W_Pos) /*!< 0x00000020 */
4158 #define FDCAN_IR_RF1W FDCAN_IR_RF1W_Msk /*!<Rx FIFO 1 Watermark Reached */
4159 #define FDCAN_IR_RF1F_Pos (6U)
4160 #define FDCAN_IR_RF1F_Msk (0x1UL << FDCAN_IR_RF1F_Pos) /*!< 0x00000040 */
4161 #define FDCAN_IR_RF1F FDCAN_IR_RF1F_Msk /*!<Rx FIFO 1 Full */
4162 #define FDCAN_IR_RF1L_Pos (7U)
4163 #define FDCAN_IR_RF1L_Msk (0x1UL << FDCAN_IR_RF1L_Pos) /*!< 0x00000080 */
4164 #define FDCAN_IR_RF1L FDCAN_IR_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4165 #define FDCAN_IR_HPM_Pos (8U)
4166 #define FDCAN_IR_HPM_Msk (0x1UL << FDCAN_IR_HPM_Pos) /*!< 0x00000100 */
4167 #define FDCAN_IR_HPM FDCAN_IR_HPM_Msk /*!<High Priority Message */
4168 #define FDCAN_IR_TC_Pos (9U)
4169 #define FDCAN_IR_TC_Msk (0x1UL << FDCAN_IR_TC_Pos) /*!< 0x00000200 */
4170 #define FDCAN_IR_TC FDCAN_IR_TC_Msk /*!<Transmission Completed */
4171 #define FDCAN_IR_TCF_Pos (10U)
4172 #define FDCAN_IR_TCF_Msk (0x1UL << FDCAN_IR_TCF_Pos) /*!< 0x00000400 */
4173 #define FDCAN_IR_TCF FDCAN_IR_TCF_Msk /*!<Transmission Cancellation Finished */
4174 #define FDCAN_IR_TFE_Pos (11U)
4175 #define FDCAN_IR_TFE_Msk (0x1UL << FDCAN_IR_TFE_Pos) /*!< 0x00000800 */
4176 #define FDCAN_IR_TFE FDCAN_IR_TFE_Msk /*!<Tx FIFO Empty */
4177 #define FDCAN_IR_TEFN_Pos (12U)
4178 #define FDCAN_IR_TEFN_Msk (0x1UL << FDCAN_IR_TEFN_Pos) /*!< 0x00001000 */
4179 #define FDCAN_IR_TEFN FDCAN_IR_TEFN_Msk /*!<Tx Event FIFO New Entry */
4180 #define FDCAN_IR_TEFW_Pos (13U)
4181 #define FDCAN_IR_TEFW_Msk (0x1UL << FDCAN_IR_TEFW_Pos) /*!< 0x00002000 */
4182 #define FDCAN_IR_TEFW FDCAN_IR_TEFW_Msk /*!<Tx Event FIFO Watermark Reached */
4183 #define FDCAN_IR_TEFF_Pos (14U)
4184 #define FDCAN_IR_TEFF_Msk (0x1UL << FDCAN_IR_TEFF_Pos) /*!< 0x00004000 */
4185 #define FDCAN_IR_TEFF FDCAN_IR_TEFF_Msk /*!<Tx Event FIFO Full */
4186 #define FDCAN_IR_TEFL_Pos (15U)
4187 #define FDCAN_IR_TEFL_Msk (0x1UL << FDCAN_IR_TEFL_Pos) /*!< 0x00008000 */
4188 #define FDCAN_IR_TEFL FDCAN_IR_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4189 #define FDCAN_IR_TSW_Pos (16U)
4190 #define FDCAN_IR_TSW_Msk (0x1UL << FDCAN_IR_TSW_Pos) /*!< 0x00010000 */
4191 #define FDCAN_IR_TSW FDCAN_IR_TSW_Msk /*!<Timestamp Wraparound */
4192 #define FDCAN_IR_MRAF_Pos (17U)
4193 #define FDCAN_IR_MRAF_Msk (0x1UL << FDCAN_IR_MRAF_Pos) /*!< 0x00020000 */
4194 #define FDCAN_IR_MRAF FDCAN_IR_MRAF_Msk /*!<Message RAM Access Failure */
4195 #define FDCAN_IR_TOO_Pos (18U)
4196 #define FDCAN_IR_TOO_Msk (0x1UL << FDCAN_IR_TOO_Pos) /*!< 0x00040000 */
4197 #define FDCAN_IR_TOO FDCAN_IR_TOO_Msk /*!<Timeout Occurred */
4198 #define FDCAN_IR_DRX_Pos (19U)
4199 #define FDCAN_IR_DRX_Msk (0x1UL << FDCAN_IR_DRX_Pos) /*!< 0x00080000 */
4200 #define FDCAN_IR_DRX FDCAN_IR_DRX_Msk /*!<Message stored to Dedicated Rx Buffer */
4201 #define FDCAN_IR_ELO_Pos (22U)
4202 #define FDCAN_IR_ELO_Msk (0x1UL << FDCAN_IR_ELO_Pos) /*!< 0x00400000 */
4203 #define FDCAN_IR_ELO FDCAN_IR_ELO_Msk /*!<Error Logging Overflow */
4204 #define FDCAN_IR_EP_Pos (23U)
4205 #define FDCAN_IR_EP_Msk (0x1UL << FDCAN_IR_EP_Pos) /*!< 0x00800000 */
4206 #define FDCAN_IR_EP FDCAN_IR_EP_Msk /*!<Error Passive */
4207 #define FDCAN_IR_EW_Pos (24U)
4208 #define FDCAN_IR_EW_Msk (0x1UL << FDCAN_IR_EW_Pos) /*!< 0x01000000 */
4209 #define FDCAN_IR_EW FDCAN_IR_EW_Msk /*!<Warning Status */
4210 #define FDCAN_IR_BO_Pos (25U)
4211 #define FDCAN_IR_BO_Msk (0x1UL << FDCAN_IR_BO_Pos) /*!< 0x02000000 */
4212 #define FDCAN_IR_BO FDCAN_IR_BO_Msk /*!<Bus_Off Status */
4213 #define FDCAN_IR_WDI_Pos (26U)
4214 #define FDCAN_IR_WDI_Msk (0x1UL << FDCAN_IR_WDI_Pos) /*!< 0x04000000 */
4215 #define FDCAN_IR_WDI FDCAN_IR_WDI_Msk /*!<Watchdog Interrupt */
4216 #define FDCAN_IR_PEA_Pos (27U)
4217 #define FDCAN_IR_PEA_Msk (0x1UL << FDCAN_IR_PEA_Pos) /*!< 0x08000000 */
4218 #define FDCAN_IR_PEA FDCAN_IR_PEA_Msk /*!<Protocol Error in Arbitration Phase */
4219 #define FDCAN_IR_PED_Pos (28U)
4220 #define FDCAN_IR_PED_Msk (0x1UL << FDCAN_IR_PED_Pos) /*!< 0x10000000 */
4221 #define FDCAN_IR_PED FDCAN_IR_PED_Msk /*!<Protocol Error in Data Phase */
4222 #define FDCAN_IR_ARA_Pos (29U)
4223 #define FDCAN_IR_ARA_Msk (0x1UL << FDCAN_IR_ARA_Pos) /*!< 0x20000000 */
4224 #define FDCAN_IR_ARA FDCAN_IR_ARA_Msk /*!<Access to Reserved Address */
4225
4226 /***************** Bit definition for FDCAN_IE register **********************/
4227 #define FDCAN_IE_RF0NE_Pos (0U)
4228 #define FDCAN_IE_RF0NE_Msk (0x1UL << FDCAN_IE_RF0NE_Pos) /*!< 0x00000001 */
4229 #define FDCAN_IE_RF0NE FDCAN_IE_RF0NE_Msk /*!<Rx FIFO 0 New Message Enable */
4230 #define FDCAN_IE_RF0WE_Pos (1U)
4231 #define FDCAN_IE_RF0WE_Msk (0x1UL << FDCAN_IE_RF0WE_Pos) /*!< 0x00000002 */
4232 #define FDCAN_IE_RF0WE FDCAN_IE_RF0WE_Msk /*!<Rx FIFO 0 Watermark Reached Enable */
4233 #define FDCAN_IE_RF0FE_Pos (2U)
4234 #define FDCAN_IE_RF0FE_Msk (0x1UL << FDCAN_IE_RF0FE_Pos) /*!< 0x00000004 */
4235 #define FDCAN_IE_RF0FE FDCAN_IE_RF0FE_Msk /*!<Rx FIFO 0 Full Enable */
4236 #define FDCAN_IE_RF0LE_Pos (3U)
4237 #define FDCAN_IE_RF0LE_Msk (0x1UL << FDCAN_IE_RF0LE_Pos) /*!< 0x00000008 */
4238 #define FDCAN_IE_RF0LE FDCAN_IE_RF0LE_Msk /*!<Rx FIFO 0 Message Lost Enable */
4239 #define FDCAN_IE_RF1NE_Pos (4U)
4240 #define FDCAN_IE_RF1NE_Msk (0x1UL << FDCAN_IE_RF1NE_Pos) /*!< 0x00000010 */
4241 #define FDCAN_IE_RF1NE FDCAN_IE_RF1NE_Msk /*!<Rx FIFO 1 New Message Enable */
4242 #define FDCAN_IE_RF1WE_Pos (5U)
4243 #define FDCAN_IE_RF1WE_Msk (0x1UL << FDCAN_IE_RF1WE_Pos) /*!< 0x00000020 */
4244 #define FDCAN_IE_RF1WE FDCAN_IE_RF1WE_Msk /*!<Rx FIFO 1 Watermark Reached Enable */
4245 #define FDCAN_IE_RF1FE_Pos (6U)
4246 #define FDCAN_IE_RF1FE_Msk (0x1UL << FDCAN_IE_RF1FE_Pos) /*!< 0x00000040 */
4247 #define FDCAN_IE_RF1FE FDCAN_IE_RF1FE_Msk /*!<Rx FIFO 1 Full Enable */
4248 #define FDCAN_IE_RF1LE_Pos (7U)
4249 #define FDCAN_IE_RF1LE_Msk (0x1UL << FDCAN_IE_RF1LE_Pos) /*!< 0x00000080 */
4250 #define FDCAN_IE_RF1LE FDCAN_IE_RF1LE_Msk /*!<Rx FIFO 1 Message Lost Enable */
4251 #define FDCAN_IE_HPME_Pos (8U)
4252 #define FDCAN_IE_HPME_Msk (0x1UL << FDCAN_IE_HPME_Pos) /*!< 0x00000100 */
4253 #define FDCAN_IE_HPME FDCAN_IE_HPME_Msk /*!<High Priority Message Enable */
4254 #define FDCAN_IE_TCE_Pos (9U)
4255 #define FDCAN_IE_TCE_Msk (0x1UL << FDCAN_IE_TCE_Pos) /*!< 0x00000200 */
4256 #define FDCAN_IE_TCE FDCAN_IE_TCE_Msk /*!<Transmission Completed Enable */
4257 #define FDCAN_IE_TCFE_Pos (10U)
4258 #define FDCAN_IE_TCFE_Msk (0x1UL << FDCAN_IE_TCFE_Pos) /*!< 0x00000400 */
4259 #define FDCAN_IE_TCFE FDCAN_IE_TCFE_Msk /*!<Transmission Cancellation Finished Enable */
4260 #define FDCAN_IE_TFEE_Pos (11U)
4261 #define FDCAN_IE_TFEE_Msk (0x1UL << FDCAN_IE_TFEE_Pos) /*!< 0x00000800 */
4262 #define FDCAN_IE_TFEE FDCAN_IE_TFEE_Msk /*!<Tx FIFO Empty Enable */
4263 #define FDCAN_IE_TEFNE_Pos (12U)
4264 #define FDCAN_IE_TEFNE_Msk (0x1UL << FDCAN_IE_TEFNE_Pos) /*!< 0x00001000 */
4265 #define FDCAN_IE_TEFNE FDCAN_IE_TEFNE_Msk /*!<Tx Event FIFO New Entry Enable */
4266 #define FDCAN_IE_TEFWE_Pos (13U)
4267 #define FDCAN_IE_TEFWE_Msk (0x1UL << FDCAN_IE_TEFWE_Pos) /*!< 0x00002000 */
4268 #define FDCAN_IE_TEFWE FDCAN_IE_TEFWE_Msk /*!<Tx Event FIFO Watermark Reached Enable */
4269 #define FDCAN_IE_TEFFE_Pos (14U)
4270 #define FDCAN_IE_TEFFE_Msk (0x1UL << FDCAN_IE_TEFFE_Pos) /*!< 0x00004000 */
4271 #define FDCAN_IE_TEFFE FDCAN_IE_TEFFE_Msk /*!<Tx Event FIFO Full Enable */
4272 #define FDCAN_IE_TEFLE_Pos (15U)
4273 #define FDCAN_IE_TEFLE_Msk (0x1UL << FDCAN_IE_TEFLE_Pos) /*!< 0x00008000 */
4274 #define FDCAN_IE_TEFLE FDCAN_IE_TEFLE_Msk /*!<Tx Event FIFO Element Lost Enable */
4275 #define FDCAN_IE_TSWE_Pos (16U)
4276 #define FDCAN_IE_TSWE_Msk (0x1UL << FDCAN_IE_TSWE_Pos) /*!< 0x00010000 */
4277 #define FDCAN_IE_TSWE FDCAN_IE_TSWE_Msk /*!<Timestamp Wraparound Enable */
4278 #define FDCAN_IE_MRAFE_Pos (17U)
4279 #define FDCAN_IE_MRAFE_Msk (0x1UL << FDCAN_IE_MRAFE_Pos) /*!< 0x00020000 */
4280 #define FDCAN_IE_MRAFE FDCAN_IE_MRAFE_Msk /*!<Message RAM Access Failure Enable */
4281 #define FDCAN_IE_TOOE_Pos (18U)
4282 #define FDCAN_IE_TOOE_Msk (0x1UL << FDCAN_IE_TOOE_Pos) /*!< 0x00040000 */
4283 #define FDCAN_IE_TOOE FDCAN_IE_TOOE_Msk /*!<Timeout Occurred Enable */
4284 #define FDCAN_IE_DRXE_Pos (19U)
4285 #define FDCAN_IE_DRXE_Msk (0x1UL << FDCAN_IE_DRXE_Pos) /*!< 0x00080000 */
4286 #define FDCAN_IE_DRXE FDCAN_IE_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Enable */
4287 #define FDCAN_IE_BECE_Pos (20U)
4288 #define FDCAN_IE_BECE_Msk (0x1UL << FDCAN_IE_BECE_Pos) /*!< 0x00100000 */
4289 #define FDCAN_IE_BECE FDCAN_IE_BECE_Msk /*!<Bit Error Corrected Interrupt Enable */
4290 #define FDCAN_IE_BEUE_Pos (21U)
4291 #define FDCAN_IE_BEUE_Msk (0x1UL << FDCAN_IE_BEUE_Pos) /*!< 0x00200000 */
4292 #define FDCAN_IE_BEUE FDCAN_IE_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Enable */
4293 #define FDCAN_IE_ELOE_Pos (22U)
4294 #define FDCAN_IE_ELOE_Msk (0x1UL << FDCAN_IE_ELOE_Pos) /*!< 0x00400000 */
4295 #define FDCAN_IE_ELOE FDCAN_IE_ELOE_Msk /*!<Error Logging Overflow Enable */
4296 #define FDCAN_IE_EPE_Pos (23U)
4297 #define FDCAN_IE_EPE_Msk (0x1UL << FDCAN_IE_EPE_Pos) /*!< 0x00800000 */
4298 #define FDCAN_IE_EPE FDCAN_IE_EPE_Msk /*!<Error Passive Enable */
4299 #define FDCAN_IE_EWE_Pos (24U)
4300 #define FDCAN_IE_EWE_Msk (0x1UL << FDCAN_IE_EWE_Pos) /*!< 0x01000000 */
4301 #define FDCAN_IE_EWE FDCAN_IE_EWE_Msk /*!<Warning Status Enable */
4302 #define FDCAN_IE_BOE_Pos (25U)
4303 #define FDCAN_IE_BOE_Msk (0x1UL << FDCAN_IE_BOE_Pos) /*!< 0x02000000 */
4304 #define FDCAN_IE_BOE FDCAN_IE_BOE_Msk /*!<Bus_Off Status Enable */
4305 #define FDCAN_IE_WDIE_Pos (26U)
4306 #define FDCAN_IE_WDIE_Msk (0x1UL << FDCAN_IE_WDIE_Pos) /*!< 0x04000000 */
4307 #define FDCAN_IE_WDIE FDCAN_IE_WDIE_Msk /*!<Watchdog Interrupt Enable */
4308 #define FDCAN_IE_PEAE_Pos (27U)
4309 #define FDCAN_IE_PEAE_Msk (0x1UL << FDCAN_IE_PEAE_Pos) /*!< 0x08000000 */
4310 #define FDCAN_IE_PEAE FDCAN_IE_PEAE_Msk /*!<Protocol Error in Arbitration Phase Enable */
4311 #define FDCAN_IE_PEDE_Pos (28U)
4312 #define FDCAN_IE_PEDE_Msk (0x1UL << FDCAN_IE_PEDE_Pos) /*!< 0x10000000 */
4313 #define FDCAN_IE_PEDE FDCAN_IE_PEDE_Msk /*!<Protocol Error in Data Phase Enable */
4314 #define FDCAN_IE_ARAE_Pos (29U)
4315 #define FDCAN_IE_ARAE_Msk (0x1UL << FDCAN_IE_ARAE_Pos) /*!< 0x20000000 */
4316 #define FDCAN_IE_ARAE FDCAN_IE_ARAE_Msk /*!<Access to Reserved Address Enable */
4317
4318 /***************** Bit definition for FDCAN_ILS register **********************/
4319 #define FDCAN_ILS_RF0NL_Pos (0U)
4320 #define FDCAN_ILS_RF0NL_Msk (0x1UL << FDCAN_ILS_RF0NL_Pos) /*!< 0x00000001 */
4321 #define FDCAN_ILS_RF0NL FDCAN_ILS_RF0NL_Msk /*!<Rx FIFO 0 New Message Line */
4322 #define FDCAN_ILS_RF0WL_Pos (1U)
4323 #define FDCAN_ILS_RF0WL_Msk (0x1UL << FDCAN_ILS_RF0WL_Pos) /*!< 0x00000002 */
4324 #define FDCAN_ILS_RF0WL FDCAN_ILS_RF0WL_Msk /*!<Rx FIFO 0 Watermark Reached Line */
4325 #define FDCAN_ILS_RF0FL_Pos (2U)
4326 #define FDCAN_ILS_RF0FL_Msk (0x1UL << FDCAN_ILS_RF0FL_Pos) /*!< 0x00000004 */
4327 #define FDCAN_ILS_RF0FL FDCAN_ILS_RF0FL_Msk /*!<Rx FIFO 0 Full Line */
4328 #define FDCAN_ILS_RF0LL_Pos (3U)
4329 #define FDCAN_ILS_RF0LL_Msk (0x1UL << FDCAN_ILS_RF0LL_Pos) /*!< 0x00000008 */
4330 #define FDCAN_ILS_RF0LL FDCAN_ILS_RF0LL_Msk /*!<Rx FIFO 0 Message Lost Line */
4331 #define FDCAN_ILS_RF1NL_Pos (4U)
4332 #define FDCAN_ILS_RF1NL_Msk (0x1UL << FDCAN_ILS_RF1NL_Pos) /*!< 0x00000010 */
4333 #define FDCAN_ILS_RF1NL FDCAN_ILS_RF1NL_Msk /*!<Rx FIFO 1 New Message Line */
4334 #define FDCAN_ILS_RF1WL_Pos (5U)
4335 #define FDCAN_ILS_RF1WL_Msk (0x1UL << FDCAN_ILS_RF1WL_Pos) /*!< 0x00000020 */
4336 #define FDCAN_ILS_RF1WL FDCAN_ILS_RF1WL_Msk /*!<Rx FIFO 1 Watermark Reached Line */
4337 #define FDCAN_ILS_RF1FL_Pos (6U)
4338 #define FDCAN_ILS_RF1FL_Msk (0x1UL << FDCAN_ILS_RF1FL_Pos) /*!< 0x00000040 */
4339 #define FDCAN_ILS_RF1FL FDCAN_ILS_RF1FL_Msk /*!<Rx FIFO 1 Full Line */
4340 #define FDCAN_ILS_RF1LL_Pos (7U)
4341 #define FDCAN_ILS_RF1LL_Msk (0x1UL << FDCAN_ILS_RF1LL_Pos) /*!< 0x00000080 */
4342 #define FDCAN_ILS_RF1LL FDCAN_ILS_RF1LL_Msk /*!<Rx FIFO 1 Message Lost Line */
4343 #define FDCAN_ILS_HPML_Pos (8U)
4344 #define FDCAN_ILS_HPML_Msk (0x1UL << FDCAN_ILS_HPML_Pos) /*!< 0x00000100 */
4345 #define FDCAN_ILS_HPML FDCAN_ILS_HPML_Msk /*!<High Priority Message Line */
4346 #define FDCAN_ILS_TCL_Pos (9U)
4347 #define FDCAN_ILS_TCL_Msk (0x1UL << FDCAN_ILS_TCL_Pos) /*!< 0x00000200 */
4348 #define FDCAN_ILS_TCL FDCAN_ILS_TCL_Msk /*!<Transmission Completed Line */
4349 #define FDCAN_ILS_TCFL_Pos (10U)
4350 #define FDCAN_ILS_TCFL_Msk (0x1UL << FDCAN_ILS_TCFL_Pos) /*!< 0x00000400 */
4351 #define FDCAN_ILS_TCFL FDCAN_ILS_TCFL_Msk /*!<Transmission Cancellation Finished Line */
4352 #define FDCAN_ILS_TFEL_Pos (11U)
4353 #define FDCAN_ILS_TFEL_Msk (0x1UL << FDCAN_ILS_TFEL_Pos) /*!< 0x00000800 */
4354 #define FDCAN_ILS_TFEL FDCAN_ILS_TFEL_Msk /*!<Tx FIFO Empty Line */
4355 #define FDCAN_ILS_TEFNL_Pos (12U)
4356 #define FDCAN_ILS_TEFNL_Msk (0x1UL << FDCAN_ILS_TEFNL_Pos) /*!< 0x00001000 */
4357 #define FDCAN_ILS_TEFNL FDCAN_ILS_TEFNL_Msk /*!<Tx Event FIFO New Entry Line */
4358 #define FDCAN_ILS_TEFWL_Pos (13U)
4359 #define FDCAN_ILS_TEFWL_Msk (0x1UL << FDCAN_ILS_TEFWL_Pos) /*!< 0x00002000 */
4360 #define FDCAN_ILS_TEFWL FDCAN_ILS_TEFWL_Msk /*!<Tx Event FIFO Watermark Reached Line */
4361 #define FDCAN_ILS_TEFFL_Pos (14U)
4362 #define FDCAN_ILS_TEFFL_Msk (0x1UL << FDCAN_ILS_TEFFL_Pos) /*!< 0x00004000 */
4363 #define FDCAN_ILS_TEFFL FDCAN_ILS_TEFFL_Msk /*!<Tx Event FIFO Full Line */
4364 #define FDCAN_ILS_TEFLL_Pos (15U)
4365 #define FDCAN_ILS_TEFLL_Msk (0x1UL << FDCAN_ILS_TEFLL_Pos) /*!< 0x00008000 */
4366 #define FDCAN_ILS_TEFLL FDCAN_ILS_TEFLL_Msk /*!<Tx Event FIFO Element Lost Line */
4367 #define FDCAN_ILS_TSWL_Pos (16U)
4368 #define FDCAN_ILS_TSWL_Msk (0x1UL << FDCAN_ILS_TSWL_Pos) /*!< 0x00010000 */
4369 #define FDCAN_ILS_TSWL FDCAN_ILS_TSWL_Msk /*!<Timestamp Wraparound Line */
4370 #define FDCAN_ILS_MRAFE_Pos (17U)
4371 #define FDCAN_ILS_MRAFE_Msk (0x1UL << FDCAN_ILS_MRAFE_Pos) /*!< 0x00020000 */
4372 #define FDCAN_ILS_MRAFE FDCAN_ILS_MRAFE_Msk /*!<Message RAM Access Failure Line */
4373 #define FDCAN_ILS_TOOE_Pos (18U)
4374 #define FDCAN_ILS_TOOE_Msk (0x1UL << FDCAN_ILS_TOOE_Pos) /*!< 0x00040000 */
4375 #define FDCAN_ILS_TOOE FDCAN_ILS_TOOE_Msk /*!<Timeout Occurred Line */
4376 #define FDCAN_ILS_DRXE_Pos (19U)
4377 #define FDCAN_ILS_DRXE_Msk (0x1UL << FDCAN_ILS_DRXE_Pos) /*!< 0x00080000 */
4378 #define FDCAN_ILS_DRXE FDCAN_ILS_DRXE_Msk /*!<Message stored to Dedicated Rx Buffer Line */
4379 #define FDCAN_ILS_BECE_Pos (20U)
4380 #define FDCAN_ILS_BECE_Msk (0x1UL << FDCAN_ILS_BECE_Pos) /*!< 0x00100000 */
4381 #define FDCAN_ILS_BECE FDCAN_ILS_BECE_Msk /*!<Bit Error Corrected Interrupt Line */
4382 #define FDCAN_ILS_BEUE_Pos (21U)
4383 #define FDCAN_ILS_BEUE_Msk (0x1UL << FDCAN_ILS_BEUE_Pos) /*!< 0x00200000 */
4384 #define FDCAN_ILS_BEUE FDCAN_ILS_BEUE_Msk /*!<Bit Error Uncorrected Interrupt Line */
4385 #define FDCAN_ILS_ELOE_Pos (22U)
4386 #define FDCAN_ILS_ELOE_Msk (0x1UL << FDCAN_ILS_ELOE_Pos) /*!< 0x00400000 */
4387 #define FDCAN_ILS_ELOE FDCAN_ILS_ELOE_Msk /*!<Error Logging Overflow Line */
4388 #define FDCAN_ILS_EPE_Pos (23U)
4389 #define FDCAN_ILS_EPE_Msk (0x1UL << FDCAN_ILS_EPE_Pos) /*!< 0x00800000 */
4390 #define FDCAN_ILS_EPE FDCAN_ILS_EPE_Msk /*!<Error Passive Line */
4391 #define FDCAN_ILS_EWE_Pos (24U)
4392 #define FDCAN_ILS_EWE_Msk (0x1UL << FDCAN_ILS_EWE_Pos) /*!< 0x01000000 */
4393 #define FDCAN_ILS_EWE FDCAN_ILS_EWE_Msk /*!<Warning Status Line */
4394 #define FDCAN_ILS_BOE_Pos (25U)
4395 #define FDCAN_ILS_BOE_Msk (0x1UL << FDCAN_ILS_BOE_Pos) /*!< 0x02000000 */
4396 #define FDCAN_ILS_BOE FDCAN_ILS_BOE_Msk /*!<Bus_Off Status Line */
4397 #define FDCAN_ILS_WDIE_Pos (26U)
4398 #define FDCAN_ILS_WDIE_Msk (0x1UL << FDCAN_ILS_WDIE_Pos) /*!< 0x04000000 */
4399 #define FDCAN_ILS_WDIE FDCAN_ILS_WDIE_Msk /*!<Watchdog Interrupt Line */
4400 #define FDCAN_ILS_PEAE_Pos (27U)
4401 #define FDCAN_ILS_PEAE_Msk (0x1UL << FDCAN_ILS_PEAE_Pos) /*!< 0x08000000 */
4402 #define FDCAN_ILS_PEAE FDCAN_ILS_PEAE_Msk /*!<Protocol Error in Arbitration Phase Line */
4403 #define FDCAN_ILS_PEDE_Pos (28U)
4404 #define FDCAN_ILS_PEDE_Msk (0x1UL << FDCAN_ILS_PEDE_Pos) /*!< 0x10000000 */
4405 #define FDCAN_ILS_PEDE FDCAN_ILS_PEDE_Msk /*!<Protocol Error in Data Phase Line */
4406 #define FDCAN_ILS_ARAE_Pos (29U)
4407 #define FDCAN_ILS_ARAE_Msk (0x1UL << FDCAN_ILS_ARAE_Pos) /*!< 0x20000000 */
4408 #define FDCAN_ILS_ARAE FDCAN_ILS_ARAE_Msk /*!<Access to Reserved Address Line */
4409
4410 /***************** Bit definition for FDCAN_ILE register **********************/
4411 #define FDCAN_ILE_EINT0_Pos (0U)
4412 #define FDCAN_ILE_EINT0_Msk (0x1UL << FDCAN_ILE_EINT0_Pos) /*!< 0x00000001 */
4413 #define FDCAN_ILE_EINT0 FDCAN_ILE_EINT0_Msk /*!<Enable Interrupt Line 0 */
4414 #define FDCAN_ILE_EINT1_Pos (1U)
4415 #define FDCAN_ILE_EINT1_Msk (0x1UL << FDCAN_ILE_EINT1_Pos) /*!< 0x00000002 */
4416 #define FDCAN_ILE_EINT1 FDCAN_ILE_EINT1_Msk /*!<Enable Interrupt Line 1 */
4417
4418 /***************** Bit definition for FDCAN_GFC register **********************/
4419 #define FDCAN_GFC_RRFE_Pos (0U)
4420 #define FDCAN_GFC_RRFE_Msk (0x1UL << FDCAN_GFC_RRFE_Pos) /*!< 0x00000001 */
4421 #define FDCAN_GFC_RRFE FDCAN_GFC_RRFE_Msk /*!<Reject Remote Frames Extended */
4422 #define FDCAN_GFC_RRFS_Pos (1U)
4423 #define FDCAN_GFC_RRFS_Msk (0x1UL << FDCAN_GFC_RRFS_Pos) /*!< 0x00000002 */
4424 #define FDCAN_GFC_RRFS FDCAN_GFC_RRFS_Msk /*!<Reject Remote Frames Standard */
4425 #define FDCAN_GFC_ANFE_Pos (2U)
4426 #define FDCAN_GFC_ANFE_Msk (0x3UL << FDCAN_GFC_ANFE_Pos) /*!< 0x0000000C */
4427 #define FDCAN_GFC_ANFE FDCAN_GFC_ANFE_Msk /*!<Accept Non-matching Frames Extended */
4428 #define FDCAN_GFC_ANFS_Pos (4U)
4429 #define FDCAN_GFC_ANFS_Msk (0x3UL << FDCAN_GFC_ANFS_Pos) /*!< 0x00000030 */
4430 #define FDCAN_GFC_ANFS FDCAN_GFC_ANFS_Msk /*!<Accept Non-matching Frames Standard */
4431
4432 /***************** Bit definition for FDCAN_SIDFC register ********************/
4433 #define FDCAN_SIDFC_FLSSA_Pos (2U)
4434 #define FDCAN_SIDFC_FLSSA_Msk (0x3FFFUL << FDCAN_SIDFC_FLSSA_Pos) /*!< 0x0000FFFC */
4435 #define FDCAN_SIDFC_FLSSA FDCAN_SIDFC_FLSSA_Msk /*!<Filter List Standard Start Address */
4436 #define FDCAN_SIDFC_LSS_Pos (16U)
4437 #define FDCAN_SIDFC_LSS_Msk (0xFFUL << FDCAN_SIDFC_LSS_Pos) /*!< 0x00FF0000 */
4438 #define FDCAN_SIDFC_LSS FDCAN_SIDFC_LSS_Msk /*!<List Size Standard */
4439
4440 /***************** Bit definition for FDCAN_XIDFC register ********************/
4441 #define FDCAN_XIDFC_FLESA_Pos (2U)
4442 #define FDCAN_XIDFC_FLESA_Msk (0x3FFFUL << FDCAN_XIDFC_FLESA_Pos) /*!< 0x0000FFFC */
4443 #define FDCAN_XIDFC_FLESA FDCAN_XIDFC_FLESA_Msk /*!<Filter List Standard Start Address */
4444 #define FDCAN_XIDFC_LSE_Pos (16U)
4445 #define FDCAN_XIDFC_LSE_Msk (0x7FUL << FDCAN_XIDFC_LSE_Pos) /*!< 0x007F0000 */
4446 #define FDCAN_XIDFC_LSE FDCAN_XIDFC_LSE_Msk /*!<List Size Extended */
4447
4448 /***************** Bit definition for FDCAN_XIDAM register ********************/
4449 #define FDCAN_XIDAM_EIDM_Pos (0U)
4450 #define FDCAN_XIDAM_EIDM_Msk (0x1FFFFFFFUL << FDCAN_XIDAM_EIDM_Pos) /*!< 0x1FFFFFFF */
4451 #define FDCAN_XIDAM_EIDM FDCAN_XIDAM_EIDM_Msk /*!<Extended ID Mask */
4452
4453 /***************** Bit definition for FDCAN_HPMS register *********************/
4454 #define FDCAN_HPMS_BIDX_Pos (0U)
4455 #define FDCAN_HPMS_BIDX_Msk (0x3FUL << FDCAN_HPMS_BIDX_Pos) /*!< 0x0000003F */
4456 #define FDCAN_HPMS_BIDX FDCAN_HPMS_BIDX_Msk /*!<Buffer Index */
4457 #define FDCAN_HPMS_MSI_Pos (6U)
4458 #define FDCAN_HPMS_MSI_Msk (0x3UL << FDCAN_HPMS_MSI_Pos) /*!< 0x000000C0 */
4459 #define FDCAN_HPMS_MSI FDCAN_HPMS_MSI_Msk /*!<Message Storage Indicator */
4460 #define FDCAN_HPMS_FIDX_Pos (8U)
4461 #define FDCAN_HPMS_FIDX_Msk (0x7FUL << FDCAN_HPMS_FIDX_Pos) /*!< 0x00007F00 */
4462 #define FDCAN_HPMS_FIDX FDCAN_HPMS_FIDX_Msk /*!<Filter Index */
4463 #define FDCAN_HPMS_FLST_Pos (15U)
4464 #define FDCAN_HPMS_FLST_Msk (0x1UL << FDCAN_HPMS_FLST_Pos) /*!< 0x00008000 */
4465 #define FDCAN_HPMS_FLST FDCAN_HPMS_FLST_Msk /*!<Filter List */
4466
4467 /***************** Bit definition for FDCAN_NDAT1 register ********************/
4468 #define FDCAN_NDAT1_ND0_Pos (0U)
4469 #define FDCAN_NDAT1_ND0_Msk (0x1UL << FDCAN_NDAT1_ND0_Pos) /*!< 0x00000001 */
4470 #define FDCAN_NDAT1_ND0 FDCAN_NDAT1_ND0_Msk /*!<New Data flag of Rx Buffer 0 */
4471 #define FDCAN_NDAT1_ND1_Pos (1U)
4472 #define FDCAN_NDAT1_ND1_Msk (0x1UL << FDCAN_NDAT1_ND1_Pos) /*!< 0x00000002 */
4473 #define FDCAN_NDAT1_ND1 FDCAN_NDAT1_ND1_Msk /*!<New Data flag of Rx Buffer 1 */
4474 #define FDCAN_NDAT1_ND2_Pos (2U)
4475 #define FDCAN_NDAT1_ND2_Msk (0x1UL << FDCAN_NDAT1_ND2_Pos) /*!< 0x00000004 */
4476 #define FDCAN_NDAT1_ND2 FDCAN_NDAT1_ND2_Msk /*!<New Data flag of Rx Buffer 2 */
4477 #define FDCAN_NDAT1_ND3_Pos (3U)
4478 #define FDCAN_NDAT1_ND3_Msk (0x1UL << FDCAN_NDAT1_ND3_Pos) /*!< 0x00000008 */
4479 #define FDCAN_NDAT1_ND3 FDCAN_NDAT1_ND3_Msk /*!<New Data flag of Rx Buffer 3 */
4480 #define FDCAN_NDAT1_ND4_Pos (4U)
4481 #define FDCAN_NDAT1_ND4_Msk (0x1UL << FDCAN_NDAT1_ND4_Pos) /*!< 0x00000010 */
4482 #define FDCAN_NDAT1_ND4 FDCAN_NDAT1_ND4_Msk /*!<New Data flag of Rx Buffer 4 */
4483 #define FDCAN_NDAT1_ND5_Pos (5U)
4484 #define FDCAN_NDAT1_ND5_Msk (0x1UL << FDCAN_NDAT1_ND5_Pos) /*!< 0x00000020 */
4485 #define FDCAN_NDAT1_ND5 FDCAN_NDAT1_ND5_Msk /*!<New Data flag of Rx Buffer 5 */
4486 #define FDCAN_NDAT1_ND6_Pos (6U)
4487 #define FDCAN_NDAT1_ND6_Msk (0x1UL << FDCAN_NDAT1_ND6_Pos) /*!< 0x00000040 */
4488 #define FDCAN_NDAT1_ND6 FDCAN_NDAT1_ND6_Msk /*!<New Data flag of Rx Buffer 6 */
4489 #define FDCAN_NDAT1_ND7_Pos (7U)
4490 #define FDCAN_NDAT1_ND7_Msk (0x1UL << FDCAN_NDAT1_ND7_Pos) /*!< 0x00000080 */
4491 #define FDCAN_NDAT1_ND7 FDCAN_NDAT1_ND7_Msk /*!<New Data flag of Rx Buffer 7 */
4492 #define FDCAN_NDAT1_ND8_Pos (8U)
4493 #define FDCAN_NDAT1_ND8_Msk (0x1UL << FDCAN_NDAT1_ND8_Pos) /*!< 0x00000100 */
4494 #define FDCAN_NDAT1_ND8 FDCAN_NDAT1_ND8_Msk /*!<New Data flag of Rx Buffer 8 */
4495 #define FDCAN_NDAT1_ND9_Pos (9U)
4496 #define FDCAN_NDAT1_ND9_Msk (0x1UL << FDCAN_NDAT1_ND9_Pos) /*!< 0x00000200 */
4497 #define FDCAN_NDAT1_ND9 FDCAN_NDAT1_ND9_Msk /*!<New Data flag of Rx Buffer 9 */
4498 #define FDCAN_NDAT1_ND10_Pos (10U)
4499 #define FDCAN_NDAT1_ND10_Msk (0x1UL << FDCAN_NDAT1_ND10_Pos) /*!< 0x00000400 */
4500 #define FDCAN_NDAT1_ND10 FDCAN_NDAT1_ND10_Msk /*!<New Data flag of Rx Buffer 10 */
4501 #define FDCAN_NDAT1_ND11_Pos (11U)
4502 #define FDCAN_NDAT1_ND11_Msk (0x1UL << FDCAN_NDAT1_ND11_Pos) /*!< 0x00000800 */
4503 #define FDCAN_NDAT1_ND11 FDCAN_NDAT1_ND11_Msk /*!<New Data flag of Rx Buffer 11 */
4504 #define FDCAN_NDAT1_ND12_Pos (12U)
4505 #define FDCAN_NDAT1_ND12_Msk (0x1UL << FDCAN_NDAT1_ND12_Pos) /*!< 0x00001000 */
4506 #define FDCAN_NDAT1_ND12 FDCAN_NDAT1_ND12_Msk /*!<New Data flag of Rx Buffer 12 */
4507 #define FDCAN_NDAT1_ND13_Pos (13U)
4508 #define FDCAN_NDAT1_ND13_Msk (0x1UL << FDCAN_NDAT1_ND13_Pos) /*!< 0x00002000 */
4509 #define FDCAN_NDAT1_ND13 FDCAN_NDAT1_ND13_Msk /*!<New Data flag of Rx Buffer 13 */
4510 #define FDCAN_NDAT1_ND14_Pos (14U)
4511 #define FDCAN_NDAT1_ND14_Msk (0x1UL << FDCAN_NDAT1_ND14_Pos) /*!< 0x00004000 */
4512 #define FDCAN_NDAT1_ND14 FDCAN_NDAT1_ND14_Msk /*!<New Data flag of Rx Buffer 14 */
4513 #define FDCAN_NDAT1_ND15_Pos (15U)
4514 #define FDCAN_NDAT1_ND15_Msk (0x1UL << FDCAN_NDAT1_ND15_Pos) /*!< 0x00008000 */
4515 #define FDCAN_NDAT1_ND15 FDCAN_NDAT1_ND15_Msk /*!<New Data flag of Rx Buffer 15 */
4516 #define FDCAN_NDAT1_ND16_Pos (16U)
4517 #define FDCAN_NDAT1_ND16_Msk (0x1UL << FDCAN_NDAT1_ND16_Pos) /*!< 0x00010000 */
4518 #define FDCAN_NDAT1_ND16 FDCAN_NDAT1_ND16_Msk /*!<New Data flag of Rx Buffer 16 */
4519 #define FDCAN_NDAT1_ND17_Pos (17U)
4520 #define FDCAN_NDAT1_ND17_Msk (0x1UL << FDCAN_NDAT1_ND17_Pos) /*!< 0x00020000 */
4521 #define FDCAN_NDAT1_ND17 FDCAN_NDAT1_ND17_Msk /*!<New Data flag of Rx Buffer 17 */
4522 #define FDCAN_NDAT1_ND18_Pos (18U)
4523 #define FDCAN_NDAT1_ND18_Msk (0x1UL << FDCAN_NDAT1_ND18_Pos) /*!< 0x00040000 */
4524 #define FDCAN_NDAT1_ND18 FDCAN_NDAT1_ND18_Msk /*!<New Data flag of Rx Buffer 18 */
4525 #define FDCAN_NDAT1_ND19_Pos (19U)
4526 #define FDCAN_NDAT1_ND19_Msk (0x1UL << FDCAN_NDAT1_ND19_Pos) /*!< 0x00080000 */
4527 #define FDCAN_NDAT1_ND19 FDCAN_NDAT1_ND19_Msk /*!<New Data flag of Rx Buffer 19 */
4528 #define FDCAN_NDAT1_ND20_Pos (20U)
4529 #define FDCAN_NDAT1_ND20_Msk (0x1UL << FDCAN_NDAT1_ND20_Pos) /*!< 0x00100000 */
4530 #define FDCAN_NDAT1_ND20 FDCAN_NDAT1_ND20_Msk /*!<New Data flag of Rx Buffer 20 */
4531 #define FDCAN_NDAT1_ND21_Pos (21U)
4532 #define FDCAN_NDAT1_ND21_Msk (0x1UL << FDCAN_NDAT1_ND21_Pos) /*!< 0x00200000 */
4533 #define FDCAN_NDAT1_ND21 FDCAN_NDAT1_ND21_Msk /*!<New Data flag of Rx Buffer 21 */
4534 #define FDCAN_NDAT1_ND22_Pos (22U)
4535 #define FDCAN_NDAT1_ND22_Msk (0x1UL << FDCAN_NDAT1_ND22_Pos) /*!< 0x00400000 */
4536 #define FDCAN_NDAT1_ND22 FDCAN_NDAT1_ND22_Msk /*!<New Data flag of Rx Buffer 22 */
4537 #define FDCAN_NDAT1_ND23_Pos (23U)
4538 #define FDCAN_NDAT1_ND23_Msk (0x1UL << FDCAN_NDAT1_ND23_Pos) /*!< 0x00800000 */
4539 #define FDCAN_NDAT1_ND23 FDCAN_NDAT1_ND23_Msk /*!<New Data flag of Rx Buffer 23 */
4540 #define FDCAN_NDAT1_ND24_Pos (24U)
4541 #define FDCAN_NDAT1_ND24_Msk (0x1UL << FDCAN_NDAT1_ND24_Pos) /*!< 0x01000000 */
4542 #define FDCAN_NDAT1_ND24 FDCAN_NDAT1_ND24_Msk /*!<New Data flag of Rx Buffer 24 */
4543 #define FDCAN_NDAT1_ND25_Pos (25U)
4544 #define FDCAN_NDAT1_ND25_Msk (0x1UL << FDCAN_NDAT1_ND25_Pos) /*!< 0x02000000 */
4545 #define FDCAN_NDAT1_ND25 FDCAN_NDAT1_ND25_Msk /*!<New Data flag of Rx Buffer 25 */
4546 #define FDCAN_NDAT1_ND26_Pos (26U)
4547 #define FDCAN_NDAT1_ND26_Msk (0x1UL << FDCAN_NDAT1_ND26_Pos) /*!< 0x04000000 */
4548 #define FDCAN_NDAT1_ND26 FDCAN_NDAT1_ND26_Msk /*!<New Data flag of Rx Buffer 26 */
4549 #define FDCAN_NDAT1_ND27_Pos (27U)
4550 #define FDCAN_NDAT1_ND27_Msk (0x1UL << FDCAN_NDAT1_ND27_Pos) /*!< 0x08000000 */
4551 #define FDCAN_NDAT1_ND27 FDCAN_NDAT1_ND27_Msk /*!<New Data flag of Rx Buffer 27 */
4552 #define FDCAN_NDAT1_ND28_Pos (28U)
4553 #define FDCAN_NDAT1_ND28_Msk (0x1UL << FDCAN_NDAT1_ND28_Pos) /*!< 0x10000000 */
4554 #define FDCAN_NDAT1_ND28 FDCAN_NDAT1_ND28_Msk /*!<New Data flag of Rx Buffer 28 */
4555 #define FDCAN_NDAT1_ND29_Pos (29U)
4556 #define FDCAN_NDAT1_ND29_Msk (0x1UL << FDCAN_NDAT1_ND29_Pos) /*!< 0x20000000 */
4557 #define FDCAN_NDAT1_ND29 FDCAN_NDAT1_ND29_Msk /*!<New Data flag of Rx Buffer 29 */
4558 #define FDCAN_NDAT1_ND30_Pos (30U)
4559 #define FDCAN_NDAT1_ND30_Msk (0x1UL << FDCAN_NDAT1_ND30_Pos) /*!< 0x40000000 */
4560 #define FDCAN_NDAT1_ND30 FDCAN_NDAT1_ND30_Msk /*!<New Data flag of Rx Buffer 30 */
4561 #define FDCAN_NDAT1_ND31_Pos (31U)
4562 #define FDCAN_NDAT1_ND31_Msk (0x1UL << FDCAN_NDAT1_ND31_Pos) /*!< 0x80000000 */
4563 #define FDCAN_NDAT1_ND31 FDCAN_NDAT1_ND31_Msk /*!<New Data flag of Rx Buffer 31 */
4564
4565 /***************** Bit definition for FDCAN_NDAT2 register ********************/
4566 #define FDCAN_NDAT2_ND32_Pos (0U)
4567 #define FDCAN_NDAT2_ND32_Msk (0x1UL << FDCAN_NDAT2_ND32_Pos) /*!< 0x00000001 */
4568 #define FDCAN_NDAT2_ND32 FDCAN_NDAT2_ND32_Msk /*!<New Data flag of Rx Buffer 32 */
4569 #define FDCAN_NDAT2_ND33_Pos (1U)
4570 #define FDCAN_NDAT2_ND33_Msk (0x1UL << FDCAN_NDAT2_ND33_Pos) /*!< 0x00000002 */
4571 #define FDCAN_NDAT2_ND33 FDCAN_NDAT2_ND33_Msk /*!<New Data flag of Rx Buffer 33 */
4572 #define FDCAN_NDAT2_ND34_Pos (2U)
4573 #define FDCAN_NDAT2_ND34_Msk (0x1UL << FDCAN_NDAT2_ND34_Pos) /*!< 0x00000004 */
4574 #define FDCAN_NDAT2_ND34 FDCAN_NDAT2_ND34_Msk /*!<New Data flag of Rx Buffer 34 */
4575 #define FDCAN_NDAT2_ND35_Pos (3U)
4576 #define FDCAN_NDAT2_ND35_Msk (0x1UL << FDCAN_NDAT2_ND35_Pos) /*!< 0x00000008 */
4577 #define FDCAN_NDAT2_ND35 FDCAN_NDAT2_ND35_Msk /*!<New Data flag of Rx Buffer 35 */
4578 #define FDCAN_NDAT2_ND36_Pos (4U)
4579 #define FDCAN_NDAT2_ND36_Msk (0x1UL << FDCAN_NDAT2_ND36_Pos) /*!< 0x00000010 */
4580 #define FDCAN_NDAT2_ND36 FDCAN_NDAT2_ND36_Msk /*!<New Data flag of Rx Buffer 36 */
4581 #define FDCAN_NDAT2_ND37_Pos (5U)
4582 #define FDCAN_NDAT2_ND37_Msk (0x1UL << FDCAN_NDAT2_ND37_Pos) /*!< 0x00000020 */
4583 #define FDCAN_NDAT2_ND37 FDCAN_NDAT2_ND37_Msk /*!<New Data flag of Rx Buffer 37 */
4584 #define FDCAN_NDAT2_ND38_Pos (6U)
4585 #define FDCAN_NDAT2_ND38_Msk (0x1UL << FDCAN_NDAT2_ND38_Pos) /*!< 0x00000040 */
4586 #define FDCAN_NDAT2_ND38 FDCAN_NDAT2_ND38_Msk /*!<New Data flag of Rx Buffer 38 */
4587 #define FDCAN_NDAT2_ND39_Pos (7U)
4588 #define FDCAN_NDAT2_ND39_Msk (0x1UL << FDCAN_NDAT2_ND39_Pos) /*!< 0x00000080 */
4589 #define FDCAN_NDAT2_ND39 FDCAN_NDAT2_ND39_Msk /*!<New Data flag of Rx Buffer 39 */
4590 #define FDCAN_NDAT2_ND40_Pos (8U)
4591 #define FDCAN_NDAT2_ND40_Msk (0x1UL << FDCAN_NDAT2_ND40_Pos) /*!< 0x00000100 */
4592 #define FDCAN_NDAT2_ND40 FDCAN_NDAT2_ND40_Msk /*!<New Data flag of Rx Buffer 40 */
4593 #define FDCAN_NDAT2_ND41_Pos (9U)
4594 #define FDCAN_NDAT2_ND41_Msk (0x1UL << FDCAN_NDAT2_ND41_Pos) /*!< 0x00000200 */
4595 #define FDCAN_NDAT2_ND41 FDCAN_NDAT2_ND41_Msk /*!<New Data flag of Rx Buffer 41 */
4596 #define FDCAN_NDAT2_ND42_Pos (10U)
4597 #define FDCAN_NDAT2_ND42_Msk (0x1UL << FDCAN_NDAT2_ND42_Pos) /*!< 0x00000400 */
4598 #define FDCAN_NDAT2_ND42 FDCAN_NDAT2_ND42_Msk /*!<New Data flag of Rx Buffer 42 */
4599 #define FDCAN_NDAT2_ND43_Pos (11U)
4600 #define FDCAN_NDAT2_ND43_Msk (0x1UL << FDCAN_NDAT2_ND43_Pos) /*!< 0x00000800 */
4601 #define FDCAN_NDAT2_ND43 FDCAN_NDAT2_ND43_Msk /*!<New Data flag of Rx Buffer 43 */
4602 #define FDCAN_NDAT2_ND44_Pos (12U)
4603 #define FDCAN_NDAT2_ND44_Msk (0x1UL << FDCAN_NDAT2_ND44_Pos) /*!< 0x00001000 */
4604 #define FDCAN_NDAT2_ND44 FDCAN_NDAT2_ND44_Msk /*!<New Data flag of Rx Buffer 44 */
4605 #define FDCAN_NDAT2_ND45_Pos (13U)
4606 #define FDCAN_NDAT2_ND45_Msk (0x1UL << FDCAN_NDAT2_ND45_Pos) /*!< 0x00002000 */
4607 #define FDCAN_NDAT2_ND45 FDCAN_NDAT2_ND45_Msk /*!<New Data flag of Rx Buffer 45 */
4608 #define FDCAN_NDAT2_ND46_Pos (14U)
4609 #define FDCAN_NDAT2_ND46_Msk (0x1UL << FDCAN_NDAT2_ND46_Pos) /*!< 0x00004000 */
4610 #define FDCAN_NDAT2_ND46 FDCAN_NDAT2_ND46_Msk /*!<New Data flag of Rx Buffer 46 */
4611 #define FDCAN_NDAT2_ND47_Pos (15U)
4612 #define FDCAN_NDAT2_ND47_Msk (0x1UL << FDCAN_NDAT2_ND47_Pos) /*!< 0x00008000 */
4613 #define FDCAN_NDAT2_ND47 FDCAN_NDAT2_ND47_Msk /*!<New Data flag of Rx Buffer 47 */
4614 #define FDCAN_NDAT2_ND48_Pos (16U)
4615 #define FDCAN_NDAT2_ND48_Msk (0x1UL << FDCAN_NDAT2_ND48_Pos) /*!< 0x00010000 */
4616 #define FDCAN_NDAT2_ND48 FDCAN_NDAT2_ND48_Msk /*!<New Data flag of Rx Buffer 48 */
4617 #define FDCAN_NDAT2_ND49_Pos (17U)
4618 #define FDCAN_NDAT2_ND49_Msk (0x1UL << FDCAN_NDAT2_ND49_Pos) /*!< 0x00020000 */
4619 #define FDCAN_NDAT2_ND49 FDCAN_NDAT2_ND49_Msk /*!<New Data flag of Rx Buffer 49 */
4620 #define FDCAN_NDAT2_ND50_Pos (18U)
4621 #define FDCAN_NDAT2_ND50_Msk (0x1UL << FDCAN_NDAT2_ND50_Pos) /*!< 0x00040000 */
4622 #define FDCAN_NDAT2_ND50 FDCAN_NDAT2_ND50_Msk /*!<New Data flag of Rx Buffer 50 */
4623 #define FDCAN_NDAT2_ND51_Pos (19U)
4624 #define FDCAN_NDAT2_ND51_Msk (0x1UL << FDCAN_NDAT2_ND51_Pos) /*!< 0x00080000 */
4625 #define FDCAN_NDAT2_ND51 FDCAN_NDAT2_ND51_Msk /*!<New Data flag of Rx Buffer 51 */
4626 #define FDCAN_NDAT2_ND52_Pos (20U)
4627 #define FDCAN_NDAT2_ND52_Msk (0x1UL << FDCAN_NDAT2_ND52_Pos) /*!< 0x00100000 */
4628 #define FDCAN_NDAT2_ND52 FDCAN_NDAT2_ND52_Msk /*!<New Data flag of Rx Buffer 52 */
4629 #define FDCAN_NDAT2_ND53_Pos (21U)
4630 #define FDCAN_NDAT2_ND53_Msk (0x1UL << FDCAN_NDAT2_ND53_Pos) /*!< 0x00200000 */
4631 #define FDCAN_NDAT2_ND53 FDCAN_NDAT2_ND53_Msk /*!<New Data flag of Rx Buffer 53 */
4632 #define FDCAN_NDAT2_ND54_Pos (22U)
4633 #define FDCAN_NDAT2_ND54_Msk (0x1UL << FDCAN_NDAT2_ND54_Pos) /*!< 0x00400000 */
4634 #define FDCAN_NDAT2_ND54 FDCAN_NDAT2_ND54_Msk /*!<New Data flag of Rx Buffer 54 */
4635 #define FDCAN_NDAT2_ND55_Pos (23U)
4636 #define FDCAN_NDAT2_ND55_Msk (0x1UL << FDCAN_NDAT2_ND55_Pos) /*!< 0x00800000 */
4637 #define FDCAN_NDAT2_ND55 FDCAN_NDAT2_ND55_Msk /*!<New Data flag of Rx Buffer 55 */
4638 #define FDCAN_NDAT2_ND56_Pos (24U)
4639 #define FDCAN_NDAT2_ND56_Msk (0x1UL << FDCAN_NDAT2_ND56_Pos) /*!< 0x01000000 */
4640 #define FDCAN_NDAT2_ND56 FDCAN_NDAT2_ND56_Msk /*!<New Data flag of Rx Buffer 56 */
4641 #define FDCAN_NDAT2_ND57_Pos (25U)
4642 #define FDCAN_NDAT2_ND57_Msk (0x1UL << FDCAN_NDAT2_ND57_Pos) /*!< 0x02000000 */
4643 #define FDCAN_NDAT2_ND57 FDCAN_NDAT2_ND57_Msk /*!<New Data flag of Rx Buffer 57 */
4644 #define FDCAN_NDAT2_ND58_Pos (26U)
4645 #define FDCAN_NDAT2_ND58_Msk (0x1UL << FDCAN_NDAT2_ND58_Pos) /*!< 0x04000000 */
4646 #define FDCAN_NDAT2_ND58 FDCAN_NDAT2_ND58_Msk /*!<New Data flag of Rx Buffer 58 */
4647 #define FDCAN_NDAT2_ND59_Pos (27U)
4648 #define FDCAN_NDAT2_ND59_Msk (0x1UL << FDCAN_NDAT2_ND59_Pos) /*!< 0x08000000 */
4649 #define FDCAN_NDAT2_ND59 FDCAN_NDAT2_ND59_Msk /*!<New Data flag of Rx Buffer 59 */
4650 #define FDCAN_NDAT2_ND60_Pos (28U)
4651 #define FDCAN_NDAT2_ND60_Msk (0x1UL << FDCAN_NDAT2_ND60_Pos) /*!< 0x10000000 */
4652 #define FDCAN_NDAT2_ND60 FDCAN_NDAT2_ND60_Msk /*!<New Data flag of Rx Buffer 60 */
4653 #define FDCAN_NDAT2_ND61_Pos (29U)
4654 #define FDCAN_NDAT2_ND61_Msk (0x1UL << FDCAN_NDAT2_ND61_Pos) /*!< 0x20000000 */
4655 #define FDCAN_NDAT2_ND61 FDCAN_NDAT2_ND61_Msk /*!<New Data flag of Rx Buffer 61 */
4656 #define FDCAN_NDAT2_ND62_Pos (30U)
4657 #define FDCAN_NDAT2_ND62_Msk (0x1UL << FDCAN_NDAT2_ND62_Pos) /*!< 0x40000000 */
4658 #define FDCAN_NDAT2_ND62 FDCAN_NDAT2_ND62_Msk /*!<New Data flag of Rx Buffer 62 */
4659 #define FDCAN_NDAT2_ND63_Pos (31U)
4660 #define FDCAN_NDAT2_ND63_Msk (0x1UL << FDCAN_NDAT2_ND63_Pos) /*!< 0x80000000 */
4661 #define FDCAN_NDAT2_ND63 FDCAN_NDAT2_ND63_Msk /*!<New Data flag of Rx Buffer 63 */
4662
4663 /***************** Bit definition for FDCAN_RXF0C register ********************/
4664 #define FDCAN_RXF0C_F0SA_Pos (2U)
4665 #define FDCAN_RXF0C_F0SA_Msk (0x3FFFUL << FDCAN_RXF0C_F0SA_Pos) /*!< 0x0000FFFC */
4666 #define FDCAN_RXF0C_F0SA FDCAN_RXF0C_F0SA_Msk /*!<Rx FIFO 0 Start Address */
4667 #define FDCAN_RXF0C_F0S_Pos (16U)
4668 #define FDCAN_RXF0C_F0S_Msk (0x7FUL << FDCAN_RXF0C_F0S_Pos) /*!< 0x007F0000 */
4669 #define FDCAN_RXF0C_F0S FDCAN_RXF0C_F0S_Msk /*!<Number of Rx FIFO 0 elements */
4670 #define FDCAN_RXF0C_F0WM_Pos (24U)
4671 #define FDCAN_RXF0C_F0WM_Msk (0x7FUL << FDCAN_RXF0C_F0WM_Pos) /*!< 0x7F000000 */
4672 #define FDCAN_RXF0C_F0WM FDCAN_RXF0C_F0WM_Msk /*!<FIFO 0 Watermark */
4673 #define FDCAN_RXF0C_F0OM_Pos (31U)
4674 #define FDCAN_RXF0C_F0OM_Msk (0x1UL << FDCAN_RXF0C_F0OM_Pos) /*!< 0x80000000 */
4675 #define FDCAN_RXF0C_F0OM FDCAN_RXF0C_F0OM_Msk /*!<FIFO 0 Operation Mode */
4676
4677 /***************** Bit definition for FDCAN_RXF0S register ********************/
4678 #define FDCAN_RXF0S_F0FL_Pos (0U)
4679 #define FDCAN_RXF0S_F0FL_Msk (0x7FUL << FDCAN_RXF0S_F0FL_Pos) /*!< 0x0000007F */
4680 #define FDCAN_RXF0S_F0FL FDCAN_RXF0S_F0FL_Msk /*!<Rx FIFO 0 Fill Level */
4681 #define FDCAN_RXF0S_F0GI_Pos (8U)
4682 #define FDCAN_RXF0S_F0GI_Msk (0x3FUL << FDCAN_RXF0S_F0GI_Pos) /*!< 0x00003F00 */
4683 #define FDCAN_RXF0S_F0GI FDCAN_RXF0S_F0GI_Msk /*!<Rx FIFO 0 Get Index */
4684 #define FDCAN_RXF0S_F0PI_Pos (16U)
4685 #define FDCAN_RXF0S_F0PI_Msk (0x3FUL << FDCAN_RXF0S_F0PI_Pos) /*!< 0x003F0000 */
4686 #define FDCAN_RXF0S_F0PI FDCAN_RXF0S_F0PI_Msk /*!<Rx FIFO 0 Put Index */
4687 #define FDCAN_RXF0S_F0F_Pos (24U)
4688 #define FDCAN_RXF0S_F0F_Msk (0x1UL << FDCAN_RXF0S_F0F_Pos) /*!< 0x01000000 */
4689 #define FDCAN_RXF0S_F0F FDCAN_RXF0S_F0F_Msk /*!<Rx FIFO 0 Full */
4690 #define FDCAN_RXF0S_RF0L_Pos (25U)
4691 #define FDCAN_RXF0S_RF0L_Msk (0x1UL << FDCAN_RXF0S_RF0L_Pos) /*!< 0x02000000 */
4692 #define FDCAN_RXF0S_RF0L FDCAN_RXF0S_RF0L_Msk /*!<Rx FIFO 0 Message Lost */
4693
4694 /***************** Bit definition for FDCAN_RXF0A register ********************/
4695 #define FDCAN_RXF0A_F0AI_Pos (0U)
4696 #define FDCAN_RXF0A_F0AI_Msk (0x3FUL << FDCAN_RXF0A_F0AI_Pos) /*!< 0x0000003F */
4697 #define FDCAN_RXF0A_F0AI FDCAN_RXF0A_F0AI_Msk /*!<Rx FIFO 0 Acknowledge Index */
4698
4699 /***************** Bit definition for FDCAN_RXBC register ********************/
4700 #define FDCAN_RXBC_RBSA_Pos (2U)
4701 #define FDCAN_RXBC_RBSA_Msk (0x3FFFUL << FDCAN_RXBC_RBSA_Pos) /*!< 0x0000FFFC */
4702 #define FDCAN_RXBC_RBSA FDCAN_RXBC_RBSA_Msk /*!<Rx Buffer Start Address */
4703
4704 /***************** Bit definition for FDCAN_RXF1C register ********************/
4705 #define FDCAN_RXF1C_F1SA_Pos (2U)
4706 #define FDCAN_RXF1C_F1SA_Msk (0x3FFFUL << FDCAN_RXF1C_F1SA_Pos) /*!< 0x0000FFFC */
4707 #define FDCAN_RXF1C_F1SA FDCAN_RXF1C_F1SA_Msk /*!<Rx FIFO 1 Start Address */
4708 #define FDCAN_RXF1C_F1S_Pos (16U)
4709 #define FDCAN_RXF1C_F1S_Msk (0x7FUL << FDCAN_RXF1C_F1S_Pos) /*!< 0x007F0000 */
4710 #define FDCAN_RXF1C_F1S FDCAN_RXF1C_F1S_Msk /*!<Number of Rx FIFO 1 elements */
4711 #define FDCAN_RXF1C_F1WM_Pos (24U)
4712 #define FDCAN_RXF1C_F1WM_Msk (0x7FUL << FDCAN_RXF1C_F1WM_Pos) /*!< 0x7F000000 */
4713 #define FDCAN_RXF1C_F1WM FDCAN_RXF1C_F1WM_Msk /*!<Rx FIFO 1 Watermark */
4714 #define FDCAN_RXF1C_F1OM_Pos (31U)
4715 #define FDCAN_RXF1C_F1OM_Msk (0x1UL << FDCAN_RXF1C_F1OM_Pos) /*!< 0x80000000 */
4716 #define FDCAN_RXF1C_F1OM FDCAN_RXF1C_F1OM_Msk /*!<FIFO 1 Operation Mode */
4717
4718 /***************** Bit definition for FDCAN_RXF1S register ********************/
4719 #define FDCAN_RXF1S_F1FL_Pos (0U)
4720 #define FDCAN_RXF1S_F1FL_Msk (0x7FUL << FDCAN_RXF1S_F1FL_Pos) /*!< 0x0000007F */
4721 #define FDCAN_RXF1S_F1FL FDCAN_RXF1S_F1FL_Msk /*!<Rx FIFO 1 Fill Level */
4722 #define FDCAN_RXF1S_F1GI_Pos (8U)
4723 #define FDCAN_RXF1S_F1GI_Msk (0x3FUL << FDCAN_RXF1S_F1GI_Pos) /*!< 0x00003F00 */
4724 #define FDCAN_RXF1S_F1GI FDCAN_RXF1S_F1GI_Msk /*!<Rx FIFO 1 Get Index */
4725 #define FDCAN_RXF1S_F1PI_Pos (16U)
4726 #define FDCAN_RXF1S_F1PI_Msk (0x3FUL << FDCAN_RXF1S_F1PI_Pos) /*!< 0x003F0000 */
4727 #define FDCAN_RXF1S_F1PI FDCAN_RXF1S_F1PI_Msk /*!<Rx FIFO 1 Put Index */
4728 #define FDCAN_RXF1S_F1F_Pos (24U)
4729 #define FDCAN_RXF1S_F1F_Msk (0x1UL << FDCAN_RXF1S_F1F_Pos) /*!< 0x01000000 */
4730 #define FDCAN_RXF1S_F1F FDCAN_RXF1S_F1F_Msk /*!<Rx FIFO 1 Full */
4731 #define FDCAN_RXF1S_RF1L_Pos (25U)
4732 #define FDCAN_RXF1S_RF1L_Msk (0x1UL << FDCAN_RXF1S_RF1L_Pos) /*!< 0x02000000 */
4733 #define FDCAN_RXF1S_RF1L FDCAN_RXF1S_RF1L_Msk /*!<Rx FIFO 1 Message Lost */
4734
4735 /***************** Bit definition for FDCAN_RXF1A register ********************/
4736 #define FDCAN_RXF1A_F1AI_Pos (0U)
4737 #define FDCAN_RXF1A_F1AI_Msk (0x3FUL << FDCAN_RXF1A_F1AI_Pos) /*!< 0x0000003F */
4738 #define FDCAN_RXF1A_F1AI FDCAN_RXF1A_F1AI_Msk /*!<Rx FIFO 1 Acknowledge Index */
4739
4740 /***************** Bit definition for FDCAN_RXESC register ********************/
4741 #define FDCAN_RXESC_F0DS_Pos (0U)
4742 #define FDCAN_RXESC_F0DS_Msk (0x7UL << FDCAN_RXESC_F0DS_Pos) /*!< 0x00000007 */
4743 #define FDCAN_RXESC_F0DS FDCAN_RXESC_F0DS_Msk /*!<Rx FIFO 1 Data Field Size */
4744 #define FDCAN_RXESC_F1DS_Pos (4U)
4745 #define FDCAN_RXESC_F1DS_Msk (0x7UL << FDCAN_RXESC_F1DS_Pos) /*!< 0x00000070 */
4746 #define FDCAN_RXESC_F1DS FDCAN_RXESC_F1DS_Msk /*!<Rx FIFO 0 Data Field Size */
4747 #define FDCAN_RXESC_RBDS_Pos (8U)
4748 #define FDCAN_RXESC_RBDS_Msk (0x7UL << FDCAN_RXESC_RBDS_Pos) /*!< 0x00000700 */
4749 #define FDCAN_RXESC_RBDS FDCAN_RXESC_RBDS_Msk /*!<Rx Buffer Data Field Size */
4750
4751 /***************** Bit definition for FDCAN_TXBC register *********************/
4752 #define FDCAN_TXBC_TBSA_Pos (2U)
4753 #define FDCAN_TXBC_TBSA_Msk (0x3FFFUL << FDCAN_TXBC_TBSA_Pos) /*!< 0x0000FFFC */
4754 #define FDCAN_TXBC_TBSA FDCAN_TXBC_TBSA_Msk /*!<Tx Buffers Start Address */
4755 #define FDCAN_TXBC_NDTB_Pos (16U)
4756 #define FDCAN_TXBC_NDTB_Msk (0x3FUL << FDCAN_TXBC_NDTB_Pos) /*!< 0x003F0000 */
4757 #define FDCAN_TXBC_NDTB FDCAN_TXBC_NDTB_Msk /*!<Number of Dedicated Transmit Buffers */
4758 #define FDCAN_TXBC_TFQS_Pos (24U)
4759 #define FDCAN_TXBC_TFQS_Msk (0x3FUL << FDCAN_TXBC_TFQS_Pos) /*!< 0x3F000000 */
4760 #define FDCAN_TXBC_TFQS FDCAN_TXBC_TFQS_Msk /*!<Transmit FIFO/Queue Size */
4761 #define FDCAN_TXBC_TFQM_Pos (30U)
4762 #define FDCAN_TXBC_TFQM_Msk (0x1UL << FDCAN_TXBC_TFQM_Pos) /*!< 0x40000000 */
4763 #define FDCAN_TXBC_TFQM FDCAN_TXBC_TFQM_Msk /*!<Tx FIFO/Queue Mode */
4764
4765 /***************** Bit definition for FDCAN_TXFQS register *********************/
4766 #define FDCAN_TXFQS_TFFL_Pos (0U)
4767 #define FDCAN_TXFQS_TFFL_Msk (0x3FUL << FDCAN_TXFQS_TFFL_Pos) /*!< 0x0000003F */
4768 #define FDCAN_TXFQS_TFFL FDCAN_TXFQS_TFFL_Msk /*!<Tx FIFO Free Level */
4769 #define FDCAN_TXFQS_TFGI_Pos (8U)
4770 #define FDCAN_TXFQS_TFGI_Msk (0x1FUL << FDCAN_TXFQS_TFGI_Pos) /*!< 0x00001F00 */
4771 #define FDCAN_TXFQS_TFGI FDCAN_TXFQS_TFGI_Msk /*!<Tx FIFO Get Index */
4772 #define FDCAN_TXFQS_TFQPI_Pos (16U)
4773 #define FDCAN_TXFQS_TFQPI_Msk (0x1FUL << FDCAN_TXFQS_TFQPI_Pos) /*!< 0x001F0000 */
4774 #define FDCAN_TXFQS_TFQPI FDCAN_TXFQS_TFQPI_Msk /*!<Tx FIFO/Queue Put Index */
4775 #define FDCAN_TXFQS_TFQF_Pos (21U)
4776 #define FDCAN_TXFQS_TFQF_Msk (0x1UL << FDCAN_TXFQS_TFQF_Pos) /*!< 0x00200000 */
4777 #define FDCAN_TXFQS_TFQF FDCAN_TXFQS_TFQF_Msk /*!<Tx FIFO/Queue Full */
4778
4779 /***************** Bit definition for FDCAN_TXESC register *********************/
4780 #define FDCAN_TXESC_TBDS_Pos (0U)
4781 #define FDCAN_TXESC_TBDS_Msk (0x7UL << FDCAN_TXESC_TBDS_Pos) /*!< 0x00000007 */
4782 #define FDCAN_TXESC_TBDS FDCAN_TXESC_TBDS_Msk /*!<Tx Buffer Data Field Size */
4783
4784 /***************** Bit definition for FDCAN_TXBRP register *********************/
4785 #define FDCAN_TXBRP_TRP_Pos (0U)
4786 #define FDCAN_TXBRP_TRP_Msk (0xFFFFFFFFUL << FDCAN_TXBRP_TRP_Pos) /*!< 0xFFFFFFFF */
4787 #define FDCAN_TXBRP_TRP FDCAN_TXBRP_TRP_Msk /*!<Transmission Request Pending */
4788
4789 /***************** Bit definition for FDCAN_TXBAR register *********************/
4790 #define FDCAN_TXBAR_AR_Pos (0U)
4791 #define FDCAN_TXBAR_AR_Msk (0xFFFFFFFFUL << FDCAN_TXBAR_AR_Pos) /*!< 0xFFFFFFFF */
4792 #define FDCAN_TXBAR_AR FDCAN_TXBAR_AR_Msk /*!<Add Request */
4793
4794 /***************** Bit definition for FDCAN_TXBCR register *********************/
4795 #define FDCAN_TXBCR_CR_Pos (0U)
4796 #define FDCAN_TXBCR_CR_Msk (0xFFFFFFFFUL << FDCAN_TXBCR_CR_Pos) /*!< 0xFFFFFFFF */
4797 #define FDCAN_TXBCR_CR FDCAN_TXBCR_CR_Msk /*!<Cancellation Request */
4798
4799 /***************** Bit definition for FDCAN_TXBTO register *********************/
4800 #define FDCAN_TXBTO_TO_Pos (0U)
4801 #define FDCAN_TXBTO_TO_Msk (0xFFFFFFFFUL << FDCAN_TXBTO_TO_Pos) /*!< 0xFFFFFFFF */
4802 #define FDCAN_TXBTO_TO FDCAN_TXBTO_TO_Msk /*!<Transmission Occurred */
4803
4804 /***************** Bit definition for FDCAN_TXBCF register *********************/
4805 #define FDCAN_TXBCF_CF_Pos (0U)
4806 #define FDCAN_TXBCF_CF_Msk (0xFFFFFFFFUL << FDCAN_TXBCF_CF_Pos) /*!< 0xFFFFFFFF */
4807 #define FDCAN_TXBCF_CF FDCAN_TXBCF_CF_Msk /*!<Cancellation Finished */
4808
4809 /***************** Bit definition for FDCAN_TXBTIE register ********************/
4810 #define FDCAN_TXBTIE_TIE_Pos (0U)
4811 #define FDCAN_TXBTIE_TIE_Msk (0xFFFFFFFFUL << FDCAN_TXBTIE_TIE_Pos) /*!< 0xFFFFFFFF */
4812 #define FDCAN_TXBTIE_TIE FDCAN_TXBTIE_TIE_Msk /*!<Transmission Interrupt Enable */
4813
4814 /***************** Bit definition for FDCAN_ TXBCIE register *******************/
4815 #define FDCAN_TXBCIE_CFIE_Pos (0U)
4816 #define FDCAN_TXBCIE_CFIE_Msk (0xFFFFFFFFUL << FDCAN_TXBCIE_CFIE_Pos) /*!< 0xFFFFFFFF */
4817 #define FDCAN_TXBCIE_CFIE FDCAN_TXBCIE_CFIE_Msk /*!<Cancellation Finished Interrupt Enable */
4818
4819 /***************** Bit definition for FDCAN_TXEFC register *********************/
4820 #define FDCAN_TXEFC_EFSA_Pos (2U)
4821 #define FDCAN_TXEFC_EFSA_Msk (0x3FFFUL << FDCAN_TXEFC_EFSA_Pos) /*!< 0x0000FFFC */
4822 #define FDCAN_TXEFC_EFSA FDCAN_TXEFC_EFSA_Msk /*!<Event FIFO Start Address */
4823 #define FDCAN_TXEFC_EFS_Pos (16U)
4824 #define FDCAN_TXEFC_EFS_Msk (0x3FUL << FDCAN_TXEFC_EFS_Pos) /*!< 0x003F0000 */
4825 #define FDCAN_TXEFC_EFS FDCAN_TXEFC_EFS_Msk /*!<Event FIFO Size */
4826 #define FDCAN_TXEFC_EFWM_Pos (24U)
4827 #define FDCAN_TXEFC_EFWM_Msk (0x3FUL << FDCAN_TXEFC_EFWM_Pos) /*!< 0x3F000000 */
4828 #define FDCAN_TXEFC_EFWM FDCAN_TXEFC_EFWM_Msk /*!<Event FIFO Watermark */
4829
4830 /***************** Bit definition for FDCAN_TXEFS register *********************/
4831 #define FDCAN_TXEFS_EFFL_Pos (0U)
4832 #define FDCAN_TXEFS_EFFL_Msk (0x3FUL << FDCAN_TXEFS_EFFL_Pos) /*!< 0x0000003F */
4833 #define FDCAN_TXEFS_EFFL FDCAN_TXEFS_EFFL_Msk /*!<Event FIFO Fill Level */
4834 #define FDCAN_TXEFS_EFGI_Pos (8U)
4835 #define FDCAN_TXEFS_EFGI_Msk (0x1FUL << FDCAN_TXEFS_EFGI_Pos) /*!< 0x00001F00 */
4836 #define FDCAN_TXEFS_EFGI FDCAN_TXEFS_EFGI_Msk /*!<Event FIFO Get Index */
4837 #define FDCAN_TXEFS_EFPI_Pos (16U)
4838 #define FDCAN_TXEFS_EFPI_Msk (0x1FUL << FDCAN_TXEFS_EFPI_Pos) /*!< 0x001F0000 */
4839 #define FDCAN_TXEFS_EFPI FDCAN_TXEFS_EFPI_Msk /*!<Event FIFO Put Index */
4840 #define FDCAN_TXEFS_EFF_Pos (24U)
4841 #define FDCAN_TXEFS_EFF_Msk (0x1UL << FDCAN_TXEFS_EFF_Pos) /*!< 0x01000000 */
4842 #define FDCAN_TXEFS_EFF FDCAN_TXEFS_EFF_Msk /*!<Event FIFO Full */
4843 #define FDCAN_TXEFS_TEFL_Pos (25U)
4844 #define FDCAN_TXEFS_TEFL_Msk (0x1UL << FDCAN_TXEFS_TEFL_Pos) /*!< 0x02000000 */
4845 #define FDCAN_TXEFS_TEFL FDCAN_TXEFS_TEFL_Msk /*!<Tx Event FIFO Element Lost */
4846
4847 /***************** Bit definition for FDCAN_TXEFA register *********************/
4848 #define FDCAN_TXEFA_EFAI_Pos (0U)
4849 #define FDCAN_TXEFA_EFAI_Msk (0x1FUL << FDCAN_TXEFA_EFAI_Pos) /*!< 0x0000001F */
4850 #define FDCAN_TXEFA_EFAI FDCAN_TXEFA_EFAI_Msk /*!<Event FIFO Acknowledge Index */
4851
4852 /***************** Bit definition for FDCAN_TTTMC register *********************/
4853 #define FDCAN_TTTMC_TMSA_Pos (2U)
4854 #define FDCAN_TTTMC_TMSA_Msk (0x3FFFUL << FDCAN_TTTMC_TMSA_Pos) /*!< 0x0000FFFC */
4855 #define FDCAN_TTTMC_TMSA FDCAN_TTTMC_TMSA_Msk /*!<Trigger Memory Start Address */
4856 #define FDCAN_TTTMC_TME_Pos (16U)
4857 #define FDCAN_TTTMC_TME_Msk (0x7FUL << FDCAN_TTTMC_TME_Pos) /*!< 0x007F0000 */
4858 #define FDCAN_TTTMC_TME FDCAN_TTTMC_TME_Msk /*!<Trigger Memory Elements */
4859
4860 /***************** Bit definition for FDCAN_TTRMC register *********************/
4861 #define FDCAN_TTRMC_RID_Pos (0U)
4862 #define FDCAN_TTRMC_RID_Msk (0x1FFFFFFFUL << FDCAN_TTRMC_RID_Pos) /*!< 0x1FFFFFFF */
4863 #define FDCAN_TTRMC_RID FDCAN_TTRMC_RID_Msk /*!<Reference Identifier */
4864 #define FDCAN_TTRMC_XTD_Pos (30U)
4865 #define FDCAN_TTRMC_XTD_Msk (0x1UL << FDCAN_TTRMC_XTD_Pos) /*!< 0x40000000 */
4866 #define FDCAN_TTRMC_XTD FDCAN_TTRMC_XTD_Msk /*!< Extended Identifier */
4867 #define FDCAN_TTRMC_RMPS_Pos (31U)
4868 #define FDCAN_TTRMC_RMPS_Msk (0x1UL << FDCAN_TTRMC_RMPS_Pos) /*!< 0x80000000 */
4869 #define FDCAN_TTRMC_RMPS FDCAN_TTRMC_RMPS_Msk /*!<Reference Message Payload Select */
4870
4871 /***************** Bit definition for FDCAN_TTOCF register *********************/
4872 #define FDCAN_TTOCF_OM_Pos (0U)
4873 #define FDCAN_TTOCF_OM_Msk (0x3UL << FDCAN_TTOCF_OM_Pos) /*!< 0x00000003 */
4874 #define FDCAN_TTOCF_OM FDCAN_TTOCF_OM_Msk /*!<Operation Mode */
4875 #define FDCAN_TTOCF_GEN_Pos (3U)
4876 #define FDCAN_TTOCF_GEN_Msk (0x1UL << FDCAN_TTOCF_GEN_Pos) /*!< 0x00000008 */
4877 #define FDCAN_TTOCF_GEN FDCAN_TTOCF_GEN_Msk /*!<Gap Enable */
4878 #define FDCAN_TTOCF_TM_Pos (4U)
4879 #define FDCAN_TTOCF_TM_Msk (0x1UL << FDCAN_TTOCF_TM_Pos) /*!< 0x00000010 */
4880 #define FDCAN_TTOCF_TM FDCAN_TTOCF_TM_Msk /*!<Time Master */
4881 #define FDCAN_TTOCF_LDSDL_Pos (5U)
4882 #define FDCAN_TTOCF_LDSDL_Msk (0x7UL << FDCAN_TTOCF_LDSDL_Pos) /*!< 0x000000E0 */
4883 #define FDCAN_TTOCF_LDSDL FDCAN_TTOCF_LDSDL_Msk /*!<LD of Synchronization Deviation Limit */
4884 #define FDCAN_TTOCF_IRTO_Pos (8U)
4885 #define FDCAN_TTOCF_IRTO_Msk (0x7FUL << FDCAN_TTOCF_IRTO_Pos) /*!< 0x00007F00 */
4886 #define FDCAN_TTOCF_IRTO FDCAN_TTOCF_IRTO_Msk /*!<Initial Reference Trigger Offset */
4887 #define FDCAN_TTOCF_EECS_Pos (15U)
4888 #define FDCAN_TTOCF_EECS_Msk (0x1UL << FDCAN_TTOCF_EECS_Pos) /*!< 0x00008000 */
4889 #define FDCAN_TTOCF_EECS FDCAN_TTOCF_EECS_Msk /*!<Enable External Clock Synchronization */
4890 #define FDCAN_TTOCF_AWL_Pos (16U)
4891 #define FDCAN_TTOCF_AWL_Msk (0xFFUL << FDCAN_TTOCF_AWL_Pos) /*!< 0x00FF0000 */
4892 #define FDCAN_TTOCF_AWL FDCAN_TTOCF_AWL_Msk /*!<Application Watchdog Limit */
4893 #define FDCAN_TTOCF_EGTF_Pos (24U)
4894 #define FDCAN_TTOCF_EGTF_Msk (0x1UL << FDCAN_TTOCF_EGTF_Pos) /*!< 0x01000000 */
4895 #define FDCAN_TTOCF_EGTF FDCAN_TTOCF_EGTF_Msk /*!<Enable Global Time Filtering */
4896 #define FDCAN_TTOCF_ECC_Pos (25U)
4897 #define FDCAN_TTOCF_ECC_Msk (0x1UL << FDCAN_TTOCF_ECC_Pos) /*!< 0x02000000 */
4898 #define FDCAN_TTOCF_ECC FDCAN_TTOCF_ECC_Msk /*!<Enable Clock Calibration */
4899 #define FDCAN_TTOCF_EVTP_Pos (26U)
4900 #define FDCAN_TTOCF_EVTP_Msk (0x1UL << FDCAN_TTOCF_EVTP_Pos) /*!< 0x04000000 */
4901 #define FDCAN_TTOCF_EVTP FDCAN_TTOCF_EVTP_Msk /*!<Event Trigger Polarity */
4902
4903 /***************** Bit definition for FDCAN_TTMLM register *********************/
4904 #define FDCAN_TTMLM_CCM_Pos (0U)
4905 #define FDCAN_TTMLM_CCM_Msk (0x3FUL << FDCAN_TTMLM_CCM_Pos) /*!< 0x0000003F */
4906 #define FDCAN_TTMLM_CCM FDCAN_TTMLM_CCM_Msk /*!<Cycle Count Max */
4907 #define FDCAN_TTMLM_CSS_Pos (6U)
4908 #define FDCAN_TTMLM_CSS_Msk (0x3UL << FDCAN_TTMLM_CSS_Pos) /*!< 0x000000C0 */
4909 #define FDCAN_TTMLM_CSS FDCAN_TTMLM_CSS_Msk /*!<Cycle Start Synchronization */
4910 #define FDCAN_TTMLM_TXEW_Pos (8U)
4911 #define FDCAN_TTMLM_TXEW_Msk (0xFUL << FDCAN_TTMLM_TXEW_Pos) /*!< 0x00000F00 */
4912 #define FDCAN_TTMLM_TXEW FDCAN_TTMLM_TXEW_Msk /*!<Tx Enable Window */
4913 #define FDCAN_TTMLM_ENTT_Pos (16U)
4914 #define FDCAN_TTMLM_ENTT_Msk (0xFFFUL << FDCAN_TTMLM_ENTT_Pos) /*!< 0x0FFF0000 */
4915 #define FDCAN_TTMLM_ENTT FDCAN_TTMLM_ENTT_Msk /*!<Expected Number of Tx Triggers */
4916
4917 /***************** Bit definition for FDCAN_TURCF register *********************/
4918 #define FDCAN_TURCF_NCL_Pos (0U)
4919 #define FDCAN_TURCF_NCL_Msk (0xFFFFUL << FDCAN_TURCF_NCL_Pos) /*!< 0x0000FFFF */
4920 #define FDCAN_TURCF_NCL FDCAN_TURCF_NCL_Msk /*!<Numerator Configuration Low */
4921 #define FDCAN_TURCF_DC_Pos (16U)
4922 #define FDCAN_TURCF_DC_Msk (0x3FFFUL << FDCAN_TURCF_DC_Pos) /*!< 0x3FFF0000 */
4923 #define FDCAN_TURCF_DC FDCAN_TURCF_DC_Msk /*!<Denominator Configuration */
4924 #define FDCAN_TURCF_ELT_Pos (31U)
4925 #define FDCAN_TURCF_ELT_Msk (0x1UL << FDCAN_TURCF_ELT_Pos) /*!< 0x80000000 */
4926 #define FDCAN_TURCF_ELT FDCAN_TURCF_ELT_Msk /*!<Enable Local Time */
4927
4928 /***************** Bit definition for FDCAN_TTOCN register ********************/
4929 #define FDCAN_TTOCN_SGT_Pos (0U)
4930 #define FDCAN_TTOCN_SGT_Msk (0x1UL << FDCAN_TTOCN_SGT_Pos) /*!< 0x00000001 */
4931 #define FDCAN_TTOCN_SGT FDCAN_TTOCN_SGT_Msk /*!<Set Global time */
4932 #define FDCAN_TTOCN_ECS_Pos (1U)
4933 #define FDCAN_TTOCN_ECS_Msk (0x1UL << FDCAN_TTOCN_ECS_Pos) /*!< 0x00000002 */
4934 #define FDCAN_TTOCN_ECS FDCAN_TTOCN_ECS_Msk /*!<External Clock Synchronization */
4935 #define FDCAN_TTOCN_SWP_Pos (2U)
4936 #define FDCAN_TTOCN_SWP_Msk (0x1UL << FDCAN_TTOCN_SWP_Pos) /*!< 0x00000004 */
4937 #define FDCAN_TTOCN_SWP FDCAN_TTOCN_SWP_Msk /*!<Stop Watch Polarity */
4938 #define FDCAN_TTOCN_SWS_Pos (3U)
4939 #define FDCAN_TTOCN_SWS_Msk (0x3UL << FDCAN_TTOCN_SWS_Pos) /*!< 0x00000018 */
4940 #define FDCAN_TTOCN_SWS FDCAN_TTOCN_SWS_Msk /*!<Stop Watch Source */
4941 #define FDCAN_TTOCN_RTIE_Pos (5U)
4942 #define FDCAN_TTOCN_RTIE_Msk (0x1UL << FDCAN_TTOCN_RTIE_Pos) /*!< 0x00000020 */
4943 #define FDCAN_TTOCN_RTIE FDCAN_TTOCN_RTIE_Msk /*!<Register Time Mark Interrupt Pulse Enable */
4944 #define FDCAN_TTOCN_TMC_Pos (6U)
4945 #define FDCAN_TTOCN_TMC_Msk (0x3UL << FDCAN_TTOCN_TMC_Pos) /*!< 0x000000C0 */
4946 #define FDCAN_TTOCN_TMC FDCAN_TTOCN_TMC_Msk /*!<Register Time Mark Compare */
4947 #define FDCAN_TTOCN_TTIE_Pos (8U)
4948 #define FDCAN_TTOCN_TTIE_Msk (0x1UL << FDCAN_TTOCN_TTIE_Pos) /*!< 0x00000100 */
4949 #define FDCAN_TTOCN_TTIE FDCAN_TTOCN_TTIE_Msk /*!<Trigger Time Mark Interrupt Pulse Enable */
4950 #define FDCAN_TTOCN_GCS_Pos (9U)
4951 #define FDCAN_TTOCN_GCS_Msk (0x1UL << FDCAN_TTOCN_GCS_Pos) /*!< 0x00000200 */
4952 #define FDCAN_TTOCN_GCS FDCAN_TTOCN_GCS_Msk /*!<Gap Control Select */
4953 #define FDCAN_TTOCN_FGP_Pos (10U)
4954 #define FDCAN_TTOCN_FGP_Msk (0x1UL << FDCAN_TTOCN_FGP_Pos) /*!< 0x00000400 */
4955 #define FDCAN_TTOCN_FGP FDCAN_TTOCN_FGP_Msk /*!<Finish Gap */
4956 #define FDCAN_TTOCN_TMG_Pos (11U)
4957 #define FDCAN_TTOCN_TMG_Msk (0x1UL << FDCAN_TTOCN_TMG_Pos) /*!< 0x00000800 */
4958 #define FDCAN_TTOCN_TMG FDCAN_TTOCN_TMG_Msk /*!<Time Mark Gap */
4959 #define FDCAN_TTOCN_NIG_Pos (12U)
4960 #define FDCAN_TTOCN_NIG_Msk (0x1UL << FDCAN_TTOCN_NIG_Pos) /*!< 0x00001000 */
4961 #define FDCAN_TTOCN_NIG FDCAN_TTOCN_NIG_Msk /*!<Next is Gap */
4962 #define FDCAN_TTOCN_ESCN_Pos (13U)
4963 #define FDCAN_TTOCN_ESCN_Msk (0x1UL << FDCAN_TTOCN_ESCN_Pos) /*!< 0x00002000 */
4964 #define FDCAN_TTOCN_ESCN FDCAN_TTOCN_ESCN_Msk /*!<External Synchronization Control */
4965 #define FDCAN_TTOCN_LCKC_Pos (15U)
4966 #define FDCAN_TTOCN_LCKC_Msk (0x1UL << FDCAN_TTOCN_LCKC_Pos) /*!< 0x00008000 */
4967 #define FDCAN_TTOCN_LCKC FDCAN_TTOCN_LCKC_Msk /*!<TT Operation Control Register Locked */
4968
4969 /***************** Bit definition for FDCAN_TTGTP register ********************/
4970 #define FDCAN_TTGTP_TP_Pos (0U)
4971 #define FDCAN_TTGTP_TP_Msk (0xFFFFUL << FDCAN_TTGTP_TP_Pos) /*!< 0x0000FFFF */
4972 #define FDCAN_TTGTP_TP FDCAN_TTGTP_TP_Msk /*!<Time Preset */
4973 #define FDCAN_TTGTP_CTP_Pos (16U)
4974 #define FDCAN_TTGTP_CTP_Msk (0xFFFFUL << FDCAN_TTGTP_CTP_Pos) /*!< 0xFFFF0000 */
4975 #define FDCAN_TTGTP_CTP FDCAN_TTGTP_CTP_Msk /*!<Cycle Time Target Phase */
4976
4977 /***************** Bit definition for FDCAN_TTTMK register ********************/
4978 #define FDCAN_TTTMK_TM_Pos (0U)
4979 #define FDCAN_TTTMK_TM_Msk (0xFFFFUL << FDCAN_TTTMK_TM_Pos) /*!< 0x0000FFFF */
4980 #define FDCAN_TTTMK_TM FDCAN_TTTMK_TM_Msk /*!<Time Mark */
4981 #define FDCAN_TTTMK_TICC_Pos (16U)
4982 #define FDCAN_TTTMK_TICC_Msk (0x7FUL << FDCAN_TTTMK_TICC_Pos) /*!< 0x007F0000 */
4983 #define FDCAN_TTTMK_TICC FDCAN_TTTMK_TICC_Msk /*!<Time Mark Cycle Code */
4984 #define FDCAN_TTTMK_LCKM_Pos (31U)
4985 #define FDCAN_TTTMK_LCKM_Msk (0x1UL << FDCAN_TTTMK_LCKM_Pos) /*!< 0x80000000 */
4986 #define FDCAN_TTTMK_LCKM FDCAN_TTTMK_LCKM_Msk /*!<TT Time Mark Register Locked */
4987
4988 /***************** Bit definition for FDCAN_TTIR register ********************/
4989 #define FDCAN_TTIR_SBC_Pos (0U)
4990 #define FDCAN_TTIR_SBC_Msk (0x1UL << FDCAN_TTIR_SBC_Pos) /*!< 0x00000001 */
4991 #define FDCAN_TTIR_SBC FDCAN_TTIR_SBC_Msk /*!<Start of Basic Cycle */
4992 #define FDCAN_TTIR_SMC_Pos (1U)
4993 #define FDCAN_TTIR_SMC_Msk (0x1UL << FDCAN_TTIR_SMC_Pos) /*!< 0x00000002 */
4994 #define FDCAN_TTIR_SMC FDCAN_TTIR_SMC_Msk /*!<Start of Matrix Cycle */
4995 #define FDCAN_TTIR_CSM_Pos (2U)
4996 #define FDCAN_TTIR_CSM_Msk (0x1UL << FDCAN_TTIR_CSM_Pos) /*!< 0x00000004 */
4997 #define FDCAN_TTIR_CSM FDCAN_TTIR_CSM_Msk /*!<Change of Synchronization Mode */
4998 #define FDCAN_TTIR_SOG_Pos (3U)
4999 #define FDCAN_TTIR_SOG_Msk (0x1UL << FDCAN_TTIR_SOG_Pos) /*!< 0x00000008 */
5000 #define FDCAN_TTIR_SOG FDCAN_TTIR_SOG_Msk /*!<Start of Gap */
5001 #define FDCAN_TTIR_RTMI_Pos (4U)
5002 #define FDCAN_TTIR_RTMI_Msk (0x1UL << FDCAN_TTIR_RTMI_Pos) /*!< 0x00000010 */
5003 #define FDCAN_TTIR_RTMI FDCAN_TTIR_RTMI_Msk /*!<Register Time Mark Interrupt */
5004 #define FDCAN_TTIR_TTMI_Pos (5U)
5005 #define FDCAN_TTIR_TTMI_Msk (0x1UL << FDCAN_TTIR_TTMI_Pos) /*!< 0x00000020 */
5006 #define FDCAN_TTIR_TTMI FDCAN_TTIR_TTMI_Msk /*!<Trigger Time Mark Event Internal */
5007 #define FDCAN_TTIR_SWE_Pos (6U)
5008 #define FDCAN_TTIR_SWE_Msk (0x1UL << FDCAN_TTIR_SWE_Pos) /*!< 0x00000040 */
5009 #define FDCAN_TTIR_SWE FDCAN_TTIR_SWE_Msk /*!<Stop Watch Event */
5010 #define FDCAN_TTIR_GTW_Pos (7U)
5011 #define FDCAN_TTIR_GTW_Msk (0x1UL << FDCAN_TTIR_GTW_Pos) /*!< 0x00000080 */
5012 #define FDCAN_TTIR_GTW FDCAN_TTIR_GTW_Msk /*!<Global Time Wrap */
5013 #define FDCAN_TTIR_GTD_Pos (8U)
5014 #define FDCAN_TTIR_GTD_Msk (0x1UL << FDCAN_TTIR_GTD_Pos) /*!< 0x00000100 */
5015 #define FDCAN_TTIR_GTD FDCAN_TTIR_GTD_Msk /*!<Global Time Discontinuity */
5016 #define FDCAN_TTIR_GTE_Pos (9U)
5017 #define FDCAN_TTIR_GTE_Msk (0x1UL << FDCAN_TTIR_GTE_Pos) /*!< 0x00000200 */
5018 #define FDCAN_TTIR_GTE FDCAN_TTIR_GTE_Msk /*!<Global Time Error */
5019 #define FDCAN_TTIR_TXU_Pos (10U)
5020 #define FDCAN_TTIR_TXU_Msk (0x1UL << FDCAN_TTIR_TXU_Pos) /*!< 0x00000400 */
5021 #define FDCAN_TTIR_TXU FDCAN_TTIR_TXU_Msk /*!<Tx Count Underflow */
5022 #define FDCAN_TTIR_TXO_Pos (11U)
5023 #define FDCAN_TTIR_TXO_Msk (0x1UL << FDCAN_TTIR_TXO_Pos) /*!< 0x00000800 */
5024 #define FDCAN_TTIR_TXO FDCAN_TTIR_TXO_Msk /*!<Tx Count Overflow */
5025 #define FDCAN_TTIR_SE1_Pos (12U)
5026 #define FDCAN_TTIR_SE1_Msk (0x1UL << FDCAN_TTIR_SE1_Pos) /*!< 0x00001000 */
5027 #define FDCAN_TTIR_SE1 FDCAN_TTIR_SE1_Msk /*!<Scheduling Error 1 */
5028 #define FDCAN_TTIR_SE2_Pos (13U)
5029 #define FDCAN_TTIR_SE2_Msk (0x1UL << FDCAN_TTIR_SE2_Pos) /*!< 0x00002000 */
5030 #define FDCAN_TTIR_SE2 FDCAN_TTIR_SE2_Msk /*!<Scheduling Error 2 */
5031 #define FDCAN_TTIR_ELC_Pos (14U)
5032 #define FDCAN_TTIR_ELC_Msk (0x1UL << FDCAN_TTIR_ELC_Pos) /*!< 0x00004000 */
5033 #define FDCAN_TTIR_ELC FDCAN_TTIR_ELC_Msk /*!<Error Level Changed */
5034 #define FDCAN_TTIR_IWT_Pos (15U)
5035 #define FDCAN_TTIR_IWT_Msk (0x1UL << FDCAN_TTIR_IWT_Pos) /*!< 0x00008000 */
5036 #define FDCAN_TTIR_IWT FDCAN_TTIR_IWT_Msk /*!<Initialization Watch Trigger */
5037 #define FDCAN_TTIR_WT_Pos (16U)
5038 #define FDCAN_TTIR_WT_Msk (0x1UL << FDCAN_TTIR_WT_Pos) /*!< 0x00010000 */
5039 #define FDCAN_TTIR_WT FDCAN_TTIR_WT_Msk /*!<Watch Trigger */
5040 #define FDCAN_TTIR_AW_Pos (17U)
5041 #define FDCAN_TTIR_AW_Msk (0x1UL << FDCAN_TTIR_AW_Pos) /*!< 0x00020000 */
5042 #define FDCAN_TTIR_AW FDCAN_TTIR_AW_Msk /*!<Application Watchdog */
5043 #define FDCAN_TTIR_CER_Pos (18U)
5044 #define FDCAN_TTIR_CER_Msk (0x1UL << FDCAN_TTIR_CER_Pos) /*!< 0x00040000 */
5045 #define FDCAN_TTIR_CER FDCAN_TTIR_CER_Msk /*!<Configuration Error */
5046
5047 /***************** Bit definition for FDCAN_TTIE register ********************/
5048 #define FDCAN_TTIE_SBCE_Pos (0U)
5049 #define FDCAN_TTIE_SBCE_Msk (0x1UL << FDCAN_TTIE_SBCE_Pos) /*!< 0x00000001 */
5050 #define FDCAN_TTIE_SBCE FDCAN_TTIE_SBCE_Msk /*!<Start of Basic Cycle Interrupt Enable */
5051 #define FDCAN_TTIE_SMCE_Pos (1U)
5052 #define FDCAN_TTIE_SMCE_Msk (0x1UL << FDCAN_TTIE_SMCE_Pos) /*!< 0x00000002 */
5053 #define FDCAN_TTIE_SMCE FDCAN_TTIE_SMCE_Msk /*!<Start of Matrix Cycle Interrupt Enable */
5054 #define FDCAN_TTIE_CSME_Pos (2U)
5055 #define FDCAN_TTIE_CSME_Msk (0x1UL << FDCAN_TTIE_CSME_Pos) /*!< 0x00000004 */
5056 #define FDCAN_TTIE_CSME FDCAN_TTIE_CSME_Msk /*!<Change of Synchronization Mode Interrupt Enable */
5057 #define FDCAN_TTIE_SOGE_Pos (3U)
5058 #define FDCAN_TTIE_SOGE_Msk (0x1UL << FDCAN_TTIE_SOGE_Pos) /*!< 0x00000008 */
5059 #define FDCAN_TTIE_SOGE FDCAN_TTIE_SOGE_Msk /*!<Start of Gap Interrupt Enable */
5060 #define FDCAN_TTIE_RTMIE_Pos (4U)
5061 #define FDCAN_TTIE_RTMIE_Msk (0x1UL << FDCAN_TTIE_RTMIE_Pos) /*!< 0x00000010 */
5062 #define FDCAN_TTIE_RTMIE FDCAN_TTIE_RTMIE_Msk /*!<Register Time Mark Interrupt Interrupt Enable */
5063 #define FDCAN_TTIE_TTMIE_Pos (5U)
5064 #define FDCAN_TTIE_TTMIE_Msk (0x1UL << FDCAN_TTIE_TTMIE_Pos) /*!< 0x00000020 */
5065 #define FDCAN_TTIE_TTMIE FDCAN_TTIE_TTMIE_Msk /*!<Trigger Time Mark Event Internal Interrupt Enable */
5066 #define FDCAN_TTIE_SWEE_Pos (6U)
5067 #define FDCAN_TTIE_SWEE_Msk (0x1UL << FDCAN_TTIE_SWEE_Pos) /*!< 0x00000040 */
5068 #define FDCAN_TTIE_SWEE FDCAN_TTIE_SWEE_Msk /*!<Stop Watch Event Interrupt Enable */
5069 #define FDCAN_TTIE_GTWE_Pos (7U)
5070 #define FDCAN_TTIE_GTWE_Msk (0x1UL << FDCAN_TTIE_GTWE_Pos) /*!< 0x00000080 */
5071 #define FDCAN_TTIE_GTWE FDCAN_TTIE_GTWE_Msk /*!<Global Time Wrap Interrupt Enable */
5072 #define FDCAN_TTIE_GTDE_Pos (8U)
5073 #define FDCAN_TTIE_GTDE_Msk (0x1UL << FDCAN_TTIE_GTDE_Pos) /*!< 0x00000100 */
5074 #define FDCAN_TTIE_GTDE FDCAN_TTIE_GTDE_Msk /*!<Global Time Discontinuity Interrupt Enable */
5075 #define FDCAN_TTIE_GTEE_Pos (9U)
5076 #define FDCAN_TTIE_GTEE_Msk (0x1UL << FDCAN_TTIE_GTEE_Pos) /*!< 0x00000200 */
5077 #define FDCAN_TTIE_GTEE FDCAN_TTIE_GTEE_Msk /*!<Global Time Error Interrupt Enable */
5078 #define FDCAN_TTIE_TXUE_Pos (10U)
5079 #define FDCAN_TTIE_TXUE_Msk (0x1UL << FDCAN_TTIE_TXUE_Pos) /*!< 0x00000400 */
5080 #define FDCAN_TTIE_TXUE FDCAN_TTIE_TXUE_Msk /*!<Tx Count Underflow Interrupt Enable */
5081 #define FDCAN_TTIE_TXOE_Pos (11U)
5082 #define FDCAN_TTIE_TXOE_Msk (0x1UL << FDCAN_TTIE_TXOE_Pos) /*!< 0x00000800 */
5083 #define FDCAN_TTIE_TXOE FDCAN_TTIE_TXOE_Msk /*!<Tx Count Overflow Interrupt Enable */
5084 #define FDCAN_TTIE_SE1E_Pos (12U)
5085 #define FDCAN_TTIE_SE1E_Msk (0x1UL << FDCAN_TTIE_SE1E_Pos) /*!< 0x00001000 */
5086 #define FDCAN_TTIE_SE1E FDCAN_TTIE_SE1E_Msk /*!<Scheduling Error 1 Interrupt Enable */
5087 #define FDCAN_TTIE_SE2E_Pos (13U)
5088 #define FDCAN_TTIE_SE2E_Msk (0x1UL << FDCAN_TTIE_SE2E_Pos) /*!< 0x00002000 */
5089 #define FDCAN_TTIE_SE2E FDCAN_TTIE_SE2E_Msk /*!<Scheduling Error 2 Interrupt Enable */
5090 #define FDCAN_TTIE_ELCE_Pos (14U)
5091 #define FDCAN_TTIE_ELCE_Msk (0x1UL << FDCAN_TTIE_ELCE_Pos) /*!< 0x00004000 */
5092 #define FDCAN_TTIE_ELCE FDCAN_TTIE_ELCE_Msk /*!<Error Level Changed Interrupt Enable */
5093 #define FDCAN_TTIE_IWTE_Pos (15U)
5094 #define FDCAN_TTIE_IWTE_Msk (0x1UL << FDCAN_TTIE_IWTE_Pos) /*!< 0x00008000 */
5095 #define FDCAN_TTIE_IWTE FDCAN_TTIE_IWTE_Msk /*!<Initialization Watch Trigger Interrupt Enable */
5096 #define FDCAN_TTIE_WTE_Pos (16U)
5097 #define FDCAN_TTIE_WTE_Msk (0x1UL << FDCAN_TTIE_WTE_Pos) /*!< 0x00010000 */
5098 #define FDCAN_TTIE_WTE FDCAN_TTIE_WTE_Msk /*!<Watch Trigger Interrupt Enable */
5099 #define FDCAN_TTIE_AWE_Pos (17U)
5100 #define FDCAN_TTIE_AWE_Msk (0x1UL << FDCAN_TTIE_AWE_Pos) /*!< 0x00020000 */
5101 #define FDCAN_TTIE_AWE FDCAN_TTIE_AWE_Msk /*!<Application Watchdog Interrupt Enable */
5102 #define FDCAN_TTIE_CERE_Pos (18U)
5103 #define FDCAN_TTIE_CERE_Msk (0x1UL << FDCAN_TTIE_CERE_Pos) /*!< 0x00040000 */
5104 #define FDCAN_TTIE_CERE FDCAN_TTIE_CERE_Msk /*!<Configuration Error Interrupt Enable */
5105
5106 /***************** Bit definition for FDCAN_TTILS register ********************/
5107 #define FDCAN_TTILS_SBCS_Pos (0U)
5108 #define FDCAN_TTILS_SBCS_Msk (0x1UL << FDCAN_TTILS_SBCS_Pos) /*!< 0x00000001 */
5109 #define FDCAN_TTILS_SBCS FDCAN_TTILS_SBCS_Msk /*!<Start of Basic Cycle Interrupt Line */
5110 #define FDCAN_TTILS_SMCS_Pos (1U)
5111 #define FDCAN_TTILS_SMCS_Msk (0x1UL << FDCAN_TTILS_SMCS_Pos) /*!< 0x00000002 */
5112 #define FDCAN_TTILS_SMCS FDCAN_TTILS_SMCS_Msk /*!<Start of Matrix Cycle Interrupt Line */
5113 #define FDCAN_TTILS_CSMS_Pos (2U)
5114 #define FDCAN_TTILS_CSMS_Msk (0x1UL << FDCAN_TTILS_CSMS_Pos) /*!< 0x00000004 */
5115 #define FDCAN_TTILS_CSMS FDCAN_TTILS_CSMS_Msk /*!<Change of Synchronization Mode Interrupt Line */
5116 #define FDCAN_TTILS_SOGS_Pos (3U)
5117 #define FDCAN_TTILS_SOGS_Msk (0x1UL << FDCAN_TTILS_SOGS_Pos) /*!< 0x00000008 */
5118 #define FDCAN_TTILS_SOGS FDCAN_TTILS_SOGS_Msk /*!<Start of Gap Interrupt Line */
5119 #define FDCAN_TTILS_RTMIS_Pos (4U)
5120 #define FDCAN_TTILS_RTMIS_Msk (0x1UL << FDCAN_TTILS_RTMIS_Pos) /*!< 0x00000010 */
5121 #define FDCAN_TTILS_RTMIS FDCAN_TTILS_RTMIS_Msk /*!<Register Time Mark Interrupt Interrupt Line */
5122 #define FDCAN_TTILS_TTMIS_Pos (5U)
5123 #define FDCAN_TTILS_TTMIS_Msk (0x1UL << FDCAN_TTILS_TTMIS_Pos) /*!< 0x00000020 */
5124 #define FDCAN_TTILS_TTMIS FDCAN_TTILS_TTMIS_Msk /*!<Trigger Time Mark Event Internal Interrupt Line */
5125 #define FDCAN_TTILS_SWES_Pos (6U)
5126 #define FDCAN_TTILS_SWES_Msk (0x1UL << FDCAN_TTILS_SWES_Pos) /*!< 0x00000040 */
5127 #define FDCAN_TTILS_SWES FDCAN_TTILS_SWES_Msk /*!<Stop Watch Event Interrupt Line */
5128 #define FDCAN_TTILS_GTWS_Pos (7U)
5129 #define FDCAN_TTILS_GTWS_Msk (0x1UL << FDCAN_TTILS_GTWS_Pos) /*!< 0x00000080 */
5130 #define FDCAN_TTILS_GTWS FDCAN_TTILS_GTWS_Msk /*!<Global Time Wrap Interrupt Line */
5131 #define FDCAN_TTILS_GTDS_Pos (8U)
5132 #define FDCAN_TTILS_GTDS_Msk (0x1UL << FDCAN_TTILS_GTDS_Pos) /*!< 0x00000100 */
5133 #define FDCAN_TTILS_GTDS FDCAN_TTILS_GTDS_Msk /*!<Global Time Discontinuity Interrupt Line */
5134 #define FDCAN_TTILS_GTES_Pos (9U)
5135 #define FDCAN_TTILS_GTES_Msk (0x1UL << FDCAN_TTILS_GTES_Pos) /*!< 0x00000200 */
5136 #define FDCAN_TTILS_GTES FDCAN_TTILS_GTES_Msk /*!<Global Time Error Interrupt Line */
5137 #define FDCAN_TTILS_TXUS_Pos (10U)
5138 #define FDCAN_TTILS_TXUS_Msk (0x1UL << FDCAN_TTILS_TXUS_Pos) /*!< 0x00000400 */
5139 #define FDCAN_TTILS_TXUS FDCAN_TTILS_TXUS_Msk /*!<Tx Count Underflow Interrupt Line */
5140 #define FDCAN_TTILS_TXOS_Pos (11U)
5141 #define FDCAN_TTILS_TXOS_Msk (0x1UL << FDCAN_TTILS_TXOS_Pos) /*!< 0x00000800 */
5142 #define FDCAN_TTILS_TXOS FDCAN_TTILS_TXOS_Msk /*!<Tx Count Overflow Interrupt Line */
5143 #define FDCAN_TTILS_SE1S_Pos (12U)
5144 #define FDCAN_TTILS_SE1S_Msk (0x1UL << FDCAN_TTILS_SE1S_Pos) /*!< 0x00001000 */
5145 #define FDCAN_TTILS_SE1S FDCAN_TTILS_SE1S_Msk /*!<Scheduling Error 1 Interrupt Line */
5146 #define FDCAN_TTILS_SE2S_Pos (13U)
5147 #define FDCAN_TTILS_SE2S_Msk (0x1UL << FDCAN_TTILS_SE2S_Pos) /*!< 0x00002000 */
5148 #define FDCAN_TTILS_SE2S FDCAN_TTILS_SE2S_Msk /*!<Scheduling Error 2 Interrupt Line */
5149 #define FDCAN_TTILS_ELCS_Pos (14U)
5150 #define FDCAN_TTILS_ELCS_Msk (0x1UL << FDCAN_TTILS_ELCS_Pos) /*!< 0x00004000 */
5151 #define FDCAN_TTILS_ELCS FDCAN_TTILS_ELCS_Msk /*!<Error Level Changed Interrupt Line */
5152 #define FDCAN_TTILS_IWTS_Pos (15U)
5153 #define FDCAN_TTILS_IWTS_Msk (0x1UL << FDCAN_TTILS_IWTS_Pos) /*!< 0x00008000 */
5154 #define FDCAN_TTILS_IWTS FDCAN_TTILS_IWTS_Msk /*!<Initialization Watch Trigger Interrupt Line */
5155 #define FDCAN_TTILS_WTS_Pos (16U)
5156 #define FDCAN_TTILS_WTS_Msk (0x1UL << FDCAN_TTILS_WTS_Pos) /*!< 0x00010000 */
5157 #define FDCAN_TTILS_WTS FDCAN_TTILS_WTS_Msk /*!<Watch Trigger Interrupt Line */
5158 #define FDCAN_TTILS_AWS_Pos (17U)
5159 #define FDCAN_TTILS_AWS_Msk (0x1UL << FDCAN_TTILS_AWS_Pos) /*!< 0x00020000 */
5160 #define FDCAN_TTILS_AWS FDCAN_TTILS_AWS_Msk /*!<Application Watchdog Interrupt Line */
5161 #define FDCAN_TTILS_CERS_Pos (18U)
5162 #define FDCAN_TTILS_CERS_Msk (0x1UL << FDCAN_TTILS_CERS_Pos) /*!< 0x00040000 */
5163 #define FDCAN_TTILS_CERS FDCAN_TTILS_CERS_Msk /*!<Configuration Error Interrupt Line */
5164
5165 /***************** Bit definition for FDCAN_TTOST register ********************/
5166 #define FDCAN_TTOST_EL_Pos (0U)
5167 #define FDCAN_TTOST_EL_Msk (0x3UL << FDCAN_TTOST_EL_Pos) /*!< 0x00000003 */
5168 #define FDCAN_TTOST_EL FDCAN_TTOST_EL_Msk /*!<Error Level */
5169 #define FDCAN_TTOST_MS_Pos (2U)
5170 #define FDCAN_TTOST_MS_Msk (0x3UL << FDCAN_TTOST_MS_Pos) /*!< 0x0000000C */
5171 #define FDCAN_TTOST_MS FDCAN_TTOST_MS_Msk /*!<Master State */
5172 #define FDCAN_TTOST_SYS_Pos (4U)
5173 #define FDCAN_TTOST_SYS_Msk (0x3UL << FDCAN_TTOST_SYS_Pos) /*!< 0x00000030 */
5174 #define FDCAN_TTOST_SYS FDCAN_TTOST_SYS_Msk /*!<Synchronization State */
5175 #define FDCAN_TTOST_QGTP_Pos (6U)
5176 #define FDCAN_TTOST_QGTP_Msk (0x1UL << FDCAN_TTOST_QGTP_Pos) /*!< 0x00000040 */
5177 #define FDCAN_TTOST_QGTP FDCAN_TTOST_QGTP_Msk /*!<Quality of Global Time Phase */
5178 #define FDCAN_TTOST_QCS_Pos (7U)
5179 #define FDCAN_TTOST_QCS_Msk (0x1UL << FDCAN_TTOST_QCS_Pos) /*!< 0x00000080 */
5180 #define FDCAN_TTOST_QCS FDCAN_TTOST_QCS_Msk /*!<Quality of Clock Speed */
5181 #define FDCAN_TTOST_RTO_Pos (8U)
5182 #define FDCAN_TTOST_RTO_Msk (0xFFUL << FDCAN_TTOST_RTO_Pos) /*!< 0x0000FF00 */
5183 #define FDCAN_TTOST_RTO FDCAN_TTOST_RTO_Msk /*!<Reference Trigger Offset */
5184 #define FDCAN_TTOST_WGTD_Pos (22U)
5185 #define FDCAN_TTOST_WGTD_Msk (0x1UL << FDCAN_TTOST_WGTD_Pos) /*!< 0x00400000 */
5186 #define FDCAN_TTOST_WGTD FDCAN_TTOST_WGTD_Msk /*!<Wait for Global Time Discontinuity */
5187 #define FDCAN_TTOST_GFI_Pos (23U)
5188 #define FDCAN_TTOST_GFI_Msk (0x1UL << FDCAN_TTOST_GFI_Pos) /*!< 0x00800000 */
5189 #define FDCAN_TTOST_GFI FDCAN_TTOST_GFI_Msk /*!<Gap Finished Indicator */
5190 #define FDCAN_TTOST_TMP_Pos (24U)
5191 #define FDCAN_TTOST_TMP_Msk (0x7UL << FDCAN_TTOST_TMP_Pos) /*!< 0x07000000 */
5192 #define FDCAN_TTOST_TMP FDCAN_TTOST_TMP_Msk /*!<Time Master Priority */
5193 #define FDCAN_TTOST_GSI_Pos (27U)
5194 #define FDCAN_TTOST_GSI_Msk (0x1UL << FDCAN_TTOST_GSI_Pos) /*!< 0x08000000 */
5195 #define FDCAN_TTOST_GSI FDCAN_TTOST_GSI_Msk /*!<Gap Started Indicator */
5196 #define FDCAN_TTOST_WFE_Pos (28U)
5197 #define FDCAN_TTOST_WFE_Msk (0x1UL << FDCAN_TTOST_WFE_Pos) /*!< 0x10000000 */
5198 #define FDCAN_TTOST_WFE FDCAN_TTOST_WFE_Msk /*!<Wait for Event */
5199 #define FDCAN_TTOST_AWE_Pos (29U)
5200 #define FDCAN_TTOST_AWE_Msk (0x1UL << FDCAN_TTOST_AWE_Pos) /*!< 0x20000000 */
5201 #define FDCAN_TTOST_AWE FDCAN_TTOST_AWE_Msk /*!<Application Watchdog Event */
5202 #define FDCAN_TTOST_WECS_Pos (30U)
5203 #define FDCAN_TTOST_WECS_Msk (0x1UL << FDCAN_TTOST_WECS_Pos) /*!< 0x40000000 */
5204 #define FDCAN_TTOST_WECS FDCAN_TTOST_WECS_Msk /*!<Wait for External Clock Synchronization */
5205 #define FDCAN_TTOST_SPL_Pos (31U)
5206 #define FDCAN_TTOST_SPL_Msk (0x1UL << FDCAN_TTOST_SPL_Pos) /*!< 0x80000000 */
5207 #define FDCAN_TTOST_SPL FDCAN_TTOST_SPL_Msk /*!<Schedule Phase Lock */
5208
5209 /***************** Bit definition for FDCAN_TURNA register ********************/
5210 #define FDCAN_TURNA_NAV_Pos (0U)
5211 #define FDCAN_TURNA_NAV_Msk (0x3FFFFUL << FDCAN_TURNA_NAV_Pos) /*!< 0x0003FFFF */
5212 #define FDCAN_TURNA_NAV FDCAN_TURNA_NAV_Msk /*!<Numerator Actual Value */
5213
5214 /***************** Bit definition for FDCAN_TTLGT register ********************/
5215 #define FDCAN_TTLGT_LT_Pos (0U)
5216 #define FDCAN_TTLGT_LT_Msk (0xFFFFUL << FDCAN_TTLGT_LT_Pos) /*!< 0x0000FFFF */
5217 #define FDCAN_TTLGT_LT FDCAN_TTLGT_LT_Msk /*!<Local Time */
5218 #define FDCAN_TTLGT_GT_Pos (16U)
5219 #define FDCAN_TTLGT_GT_Msk (0xFFFFUL << FDCAN_TTLGT_GT_Pos) /*!< 0xFFFF0000 */
5220 #define FDCAN_TTLGT_GT FDCAN_TTLGT_GT_Msk /*!<Global Time */
5221
5222 /***************** Bit definition for FDCAN_TTCTC register ********************/
5223 #define FDCAN_TTCTC_CT_Pos (0U)
5224 #define FDCAN_TTCTC_CT_Msk (0xFFFFUL << FDCAN_TTCTC_CT_Pos) /*!< 0x0000FFFF */
5225 #define FDCAN_TTCTC_CT FDCAN_TTCTC_CT_Msk /*!<Cycle Time */
5226 #define FDCAN_TTCTC_CC_Pos (16U)
5227 #define FDCAN_TTCTC_CC_Msk (0x3FUL << FDCAN_TTCTC_CC_Pos) /*!< 0x003F0000 */
5228 #define FDCAN_TTCTC_CC FDCAN_TTCTC_CC_Msk /*!<Cycle Count */
5229
5230 /***************** Bit definition for FDCAN_TTCPT register ********************/
5231 #define FDCAN_TTCPT_CCV_Pos (0U)
5232 #define FDCAN_TTCPT_CCV_Msk (0x3FUL << FDCAN_TTCPT_CCV_Pos) /*!< 0x0000003F */
5233 #define FDCAN_TTCPT_CCV FDCAN_TTCPT_CCV_Msk /*!<Cycle Count Value */
5234 #define FDCAN_TTCPT_SWV_Pos (16U)
5235 #define FDCAN_TTCPT_SWV_Msk (0xFFFFUL << FDCAN_TTCPT_SWV_Pos) /*!< 0xFFFF0000 */
5236 #define FDCAN_TTCPT_SWV FDCAN_TTCPT_SWV_Msk /*!<Stop Watch Value */
5237
5238 /***************** Bit definition for FDCAN_TTCSM register ********************/
5239 #define FDCAN_TTCSM_CSM_Pos (0U)
5240 #define FDCAN_TTCSM_CSM_Msk (0xFFFFUL << FDCAN_TTCSM_CSM_Pos) /*!< 0x0000FFFF */
5241 #define FDCAN_TTCSM_CSM FDCAN_TTCSM_CSM_Msk /*!<Cycle Sync Mark */
5242
5243 /***************** Bit definition for FDCAN_TTTS register *********************/
5244 #define FDCAN_TTTS_SWTSEL_Pos (0U)
5245 #define FDCAN_TTTS_SWTSEL_Msk (0x3UL << FDCAN_TTTS_SWTSEL_Pos) /*!< 0x00000003 */
5246 #define FDCAN_TTTS_SWTSEL FDCAN_TTTS_SWTSEL_Msk /*!<Stop watch trigger input selection */
5247 #define FDCAN_TTTS_EVTSEL_Pos (4U)
5248 #define FDCAN_TTTS_EVTSEL_Msk (0x3UL << FDCAN_TTTS_EVTSEL_Pos) /*!< 0x00000030 */
5249 #define FDCAN_TTTS_EVTSEL FDCAN_TTTS_EVTSEL_Msk /*!<Event trigger input selection */
5250
5251 /********************************************************************************/
5252 /* */
5253 /* FDCANCCU (Clock Calibration unit) */
5254 /* */
5255 /********************************************************************************/
5256
5257 /***************** Bit definition for FDCANCCU_CREL register ******************/
5258 #define FDCANCCU_CREL_DAY_Pos (0U)
5259 #define FDCANCCU_CREL_DAY_Msk (0xFFUL << FDCANCCU_CREL_DAY_Pos) /*!< 0x000000FF */
5260 #define FDCANCCU_CREL_DAY FDCANCCU_CREL_DAY_Msk /*!<Timestamp Day */
5261 #define FDCANCCU_CREL_MON_Pos (8U)
5262 #define FDCANCCU_CREL_MON_Msk (0xFFUL << FDCANCCU_CREL_MON_Pos) /*!< 0x0000FF00 */
5263 #define FDCANCCU_CREL_MON FDCANCCU_CREL_MON_Msk /*!<Timestamp Month */
5264 #define FDCANCCU_CREL_YEAR_Pos (16U)
5265 #define FDCANCCU_CREL_YEAR_Msk (0xFUL << FDCANCCU_CREL_YEAR_Pos) /*!< 0x000F0000 */
5266 #define FDCANCCU_CREL_YEAR FDCANCCU_CREL_YEAR_Msk /*!<Timestamp Year */
5267 #define FDCANCCU_CREL_SUBSTEP_Pos (20U)
5268 #define FDCANCCU_CREL_SUBSTEP_Msk (0xFUL << FDCANCCU_CREL_SUBSTEP_Pos) /*!< 0x00F00000 */
5269 #define FDCANCCU_CREL_SUBSTEP FDCANCCU_CREL_SUBSTEP_Msk /*!<Sub-step of Core release */
5270 #define FDCANCCU_CREL_STEP_Pos (24U)
5271 #define FDCANCCU_CREL_STEP_Msk (0xFUL << FDCANCCU_CREL_STEP_Pos) /*!< 0x0F000000 */
5272 #define FDCANCCU_CREL_STEP FDCANCCU_CREL_STEP_Msk /*!<Step of Core release */
5273 #define FDCANCCU_CREL_REL_Pos (28U)
5274 #define FDCANCCU_CREL_REL_Msk (0xFUL << FDCANCCU_CREL_REL_Pos) /*!< 0xF0000000 */
5275 #define FDCANCCU_CREL_REL FDCANCCU_CREL_REL_Msk /*!<Core release */
5276
5277 /***************** Bit definition for FDCANCCU_CCFG register ******************/
5278 #define FDCANCCU_CCFG_TQBT_Pos (0U)
5279 #define FDCANCCU_CCFG_TQBT_Msk (0x1FUL << FDCANCCU_CCFG_TQBT_Pos) /*!< 0x0000001F */
5280 #define FDCANCCU_CCFG_TQBT FDCANCCU_CCFG_TQBT_Msk /*!<Time Quanta per Bit Time */
5281 #define FDCANCCU_CCFG_BCC_Pos (6U)
5282 #define FDCANCCU_CCFG_BCC_Msk (0x1UL << FDCANCCU_CCFG_BCC_Pos) /*!< 0x00000040 */
5283 #define FDCANCCU_CCFG_BCC FDCANCCU_CCFG_BCC_Msk /*!<Bypass Clock Calibration */
5284 #define FDCANCCU_CCFG_CFL_Pos (7U)
5285 #define FDCANCCU_CCFG_CFL_Msk (0x1UL << FDCANCCU_CCFG_CFL_Pos) /*!< 0x00000080 */
5286 #define FDCANCCU_CCFG_CFL FDCANCCU_CCFG_CFL_Msk /*!<Calibration Field Length */
5287 #define FDCANCCU_CCFG_OCPM_Pos (8U)
5288 #define FDCANCCU_CCFG_OCPM_Msk (0xFFUL << FDCANCCU_CCFG_OCPM_Pos) /*!< 0x0000FF00 */
5289 #define FDCANCCU_CCFG_OCPM FDCANCCU_CCFG_OCPM_Msk /*!<Oscillator Clock Periods Minimum */
5290 #define FDCANCCU_CCFG_CDIV_Pos (16U)
5291 #define FDCANCCU_CCFG_CDIV_Msk (0xFUL << FDCANCCU_CCFG_CDIV_Pos) /*!< 0x000F0000 */
5292 #define FDCANCCU_CCFG_CDIV FDCANCCU_CCFG_CDIV_Msk /*!<Clock Divider */
5293 #define FDCANCCU_CCFG_SWR_Pos (31U)
5294 #define FDCANCCU_CCFG_SWR_Msk (0x1UL << FDCANCCU_CCFG_SWR_Pos) /*!< 0x80000000 */
5295 #define FDCANCCU_CCFG_SWR FDCANCCU_CCFG_SWR_Msk /*!<Software Reset */
5296
5297 /***************** Bit definition for FDCANCCU_CSTAT register *****************/
5298 #define FDCANCCU_CSTAT_OCPC_Pos (0U)
5299 #define FDCANCCU_CSTAT_OCPC_Msk (0x3FFFFUL << FDCANCCU_CSTAT_OCPC_Pos) /*!< 0x0003FFFF */
5300 #define FDCANCCU_CSTAT_OCPC FDCANCCU_CSTAT_OCPC_Msk /*!<Oscillator Clock Period Counter */
5301 #define FDCANCCU_CSTAT_TQC_Pos (18U)
5302 #define FDCANCCU_CSTAT_TQC_Msk (0x7FFUL << FDCANCCU_CSTAT_TQC_Pos) /*!< 0x1FFC0000 */
5303 #define FDCANCCU_CSTAT_TQC FDCANCCU_CSTAT_TQC_Msk /*!<Time Quanta Counter */
5304 #define FDCANCCU_CSTAT_CALS_Pos (30U)
5305 #define FDCANCCU_CSTAT_CALS_Msk (0x3UL << FDCANCCU_CSTAT_CALS_Pos) /*!< 0xC0000000 */
5306 #define FDCANCCU_CSTAT_CALS FDCANCCU_CSTAT_CALS_Msk /*!<Calibration State */
5307
5308 /****************** Bit definition for FDCANCCU_CWD register ******************/
5309 #define FDCANCCU_CWD_WDC_Pos (0U)
5310 #define FDCANCCU_CWD_WDC_Msk (0xFFFFUL << FDCANCCU_CWD_WDC_Pos) /*!< 0x0000FFFF */
5311 #define FDCANCCU_CWD_WDC FDCANCCU_CWD_WDC_Msk /*!<Watchdog Configuration */
5312 #define FDCANCCU_CWD_WDV_Pos (16U)
5313 #define FDCANCCU_CWD_WDV_Msk (0xFFFFUL << FDCANCCU_CWD_WDV_Pos) /*!< 0xFFFF0000 */
5314 #define FDCANCCU_CWD_WDV FDCANCCU_CWD_WDV_Msk /*!<Watchdog Value */
5315
5316 /****************** Bit definition for FDCANCCU_IR register *******************/
5317 #define FDCANCCU_IR_CWE_Pos (0U)
5318 #define FDCANCCU_IR_CWE_Msk (0x1UL << FDCANCCU_IR_CWE_Pos) /*!< 0x00000001 */
5319 #define FDCANCCU_IR_CWE FDCANCCU_IR_CWE_Msk /*!<Calibration Watchdog Event */
5320 #define FDCANCCU_IR_CSC_Pos (1U)
5321 #define FDCANCCU_IR_CSC_Msk (0x1UL << FDCANCCU_IR_CSC_Pos) /*!< 0x00000002 */
5322 #define FDCANCCU_IR_CSC FDCANCCU_IR_CSC_Msk /*!<Calibration State Changed */
5323
5324 /****************** Bit definition for FDCANCCU_IE register *******************/
5325 #define FDCANCCU_IE_CWEE_Pos (0U)
5326 #define FDCANCCU_IE_CWEE_Msk (0x1UL << FDCANCCU_IE_CWEE_Pos) /*!< 0x00000001 */
5327 #define FDCANCCU_IE_CWEE FDCANCCU_IE_CWEE_Msk /*!<Calibration Watchdog Event Enable */
5328 #define FDCANCCU_IE_CSCE_Pos (1U)
5329 #define FDCANCCU_IE_CSCE_Msk (0x1UL << FDCANCCU_IE_CSCE_Pos) /*!< 0x00000002 */
5330 #define FDCANCCU_IE_CSCE FDCANCCU_IE_CSCE_Msk /*!<Calibration State Changed Enable */
5331
5332 /******************************************************************************/
5333 /* */
5334 /* HDMI-CEC (CEC) */
5335 /* */
5336 /******************************************************************************/
5337
5338 /******************* Bit definition for CEC_CR register *********************/
5339 #define CEC_CR_CECEN_Pos (0U)
5340 #define CEC_CR_CECEN_Msk (0x1UL << CEC_CR_CECEN_Pos) /*!< 0x00000001 */
5341 #define CEC_CR_CECEN CEC_CR_CECEN_Msk /*!< CEC Enable */
5342 #define CEC_CR_TXSOM_Pos (1U)
5343 #define CEC_CR_TXSOM_Msk (0x1UL << CEC_CR_TXSOM_Pos) /*!< 0x00000002 */
5344 #define CEC_CR_TXSOM CEC_CR_TXSOM_Msk /*!< CEC Tx Start Of Message */
5345 #define CEC_CR_TXEOM_Pos (2U)
5346 #define CEC_CR_TXEOM_Msk (0x1UL << CEC_CR_TXEOM_Pos) /*!< 0x00000004 */
5347 #define CEC_CR_TXEOM CEC_CR_TXEOM_Msk /*!< CEC Tx End Of Message */
5348
5349 /******************* Bit definition for CEC_CFGR register *******************/
5350 #define CEC_CFGR_SFT_Pos (0U)
5351 #define CEC_CFGR_SFT_Msk (0x7UL << CEC_CFGR_SFT_Pos) /*!< 0x00000007 */
5352 #define CEC_CFGR_SFT CEC_CFGR_SFT_Msk /*!< CEC Signal Free Time */
5353 #define CEC_CFGR_RXTOL_Pos (3U)
5354 #define CEC_CFGR_RXTOL_Msk (0x1UL << CEC_CFGR_RXTOL_Pos) /*!< 0x00000008 */
5355 #define CEC_CFGR_RXTOL CEC_CFGR_RXTOL_Msk /*!< CEC Tolerance */
5356 #define CEC_CFGR_BRESTP_Pos (4U)
5357 #define CEC_CFGR_BRESTP_Msk (0x1UL << CEC_CFGR_BRESTP_Pos) /*!< 0x00000010 */
5358 #define CEC_CFGR_BRESTP CEC_CFGR_BRESTP_Msk /*!< CEC Rx Stop */
5359 #define CEC_CFGR_BREGEN_Pos (5U)
5360 #define CEC_CFGR_BREGEN_Msk (0x1UL << CEC_CFGR_BREGEN_Pos) /*!< 0x00000020 */
5361 #define CEC_CFGR_BREGEN CEC_CFGR_BREGEN_Msk /*!< CEC Bit Rising Error generation */
5362 #define CEC_CFGR_LBPEGEN_Pos (6U)
5363 #define CEC_CFGR_LBPEGEN_Msk (0x1UL << CEC_CFGR_LBPEGEN_Pos) /*!< 0x00000040 */
5364 #define CEC_CFGR_LBPEGEN CEC_CFGR_LBPEGEN_Msk /*!< CEC Long Bit Period Error generation */
5365 #define CEC_CFGR_SFTOPT_Pos (8U)
5366 #define CEC_CFGR_SFTOPT_Msk (0x1UL << CEC_CFGR_SFTOPT_Pos) /*!< 0x00000100 */
5367 #define CEC_CFGR_SFTOPT CEC_CFGR_SFTOPT_Msk /*!< CEC Signal Free Time optional */
5368 #define CEC_CFGR_BRDNOGEN_Pos (7U)
5369 #define CEC_CFGR_BRDNOGEN_Msk (0x1UL << CEC_CFGR_BRDNOGEN_Pos) /*!< 0x00000080 */
5370 #define CEC_CFGR_BRDNOGEN CEC_CFGR_BRDNOGEN_Msk /*!< CEC Broadcast No error generation */
5371 #define CEC_CFGR_OAR_Pos (16U)
5372 #define CEC_CFGR_OAR_Msk (0x7FFFUL << CEC_CFGR_OAR_Pos) /*!< 0x7FFF0000 */
5373 #define CEC_CFGR_OAR CEC_CFGR_OAR_Msk /*!< CEC Own Address */
5374 #define CEC_CFGR_LSTN_Pos (31U)
5375 #define CEC_CFGR_LSTN_Msk (0x1UL << CEC_CFGR_LSTN_Pos) /*!< 0x80000000 */
5376 #define CEC_CFGR_LSTN CEC_CFGR_LSTN_Msk /*!< CEC Listen mode */
5377
5378 /******************* Bit definition for CEC_TXDR register *******************/
5379 #define CEC_TXDR_TXD_Pos (0U)
5380 #define CEC_TXDR_TXD_Msk (0xFFUL << CEC_TXDR_TXD_Pos) /*!< 0x000000FF */
5381 #define CEC_TXDR_TXD CEC_TXDR_TXD_Msk /*!< CEC Tx Data */
5382
5383 /******************* Bit definition for CEC_RXDR register *******************/
5384 #define CEC_RXDR_RXD_Pos (0U)
5385 #define CEC_RXDR_RXD_Msk (0xFFUL << CEC_RXDR_RXD_Pos) /*!< 0x000000FF */
5386 #define CEC_RXDR_RXD CEC_RXDR_RXD_Msk /*!< CEC Rx Data */
5387
5388 /******************* Bit definition for CEC_ISR register ********************/
5389 #define CEC_ISR_RXBR_Pos (0U)
5390 #define CEC_ISR_RXBR_Msk (0x1UL << CEC_ISR_RXBR_Pos) /*!< 0x00000001 */
5391 #define CEC_ISR_RXBR CEC_ISR_RXBR_Msk /*!< CEC Rx-Byte Received */
5392 #define CEC_ISR_RXEND_Pos (1U)
5393 #define CEC_ISR_RXEND_Msk (0x1UL << CEC_ISR_RXEND_Pos) /*!< 0x00000002 */
5394 #define CEC_ISR_RXEND CEC_ISR_RXEND_Msk /*!< CEC End Of Reception */
5395 #define CEC_ISR_RXOVR_Pos (2U)
5396 #define CEC_ISR_RXOVR_Msk (0x1UL << CEC_ISR_RXOVR_Pos) /*!< 0x00000004 */
5397 #define CEC_ISR_RXOVR CEC_ISR_RXOVR_Msk /*!< CEC Rx-Overrun */
5398 #define CEC_ISR_BRE_Pos (3U)
5399 #define CEC_ISR_BRE_Msk (0x1UL << CEC_ISR_BRE_Pos) /*!< 0x00000008 */
5400 #define CEC_ISR_BRE CEC_ISR_BRE_Msk /*!< CEC Rx Bit Rising Error */
5401 #define CEC_ISR_SBPE_Pos (4U)
5402 #define CEC_ISR_SBPE_Msk (0x1UL << CEC_ISR_SBPE_Pos) /*!< 0x00000010 */
5403 #define CEC_ISR_SBPE CEC_ISR_SBPE_Msk /*!< CEC Rx Short Bit period Error */
5404 #define CEC_ISR_LBPE_Pos (5U)
5405 #define CEC_ISR_LBPE_Msk (0x1UL << CEC_ISR_LBPE_Pos) /*!< 0x00000020 */
5406 #define CEC_ISR_LBPE CEC_ISR_LBPE_Msk /*!< CEC Rx Long Bit period Error */
5407 #define CEC_ISR_RXACKE_Pos (6U)
5408 #define CEC_ISR_RXACKE_Msk (0x1UL << CEC_ISR_RXACKE_Pos) /*!< 0x00000040 */
5409 #define CEC_ISR_RXACKE CEC_ISR_RXACKE_Msk /*!< CEC Rx Missing Acknowledge */
5410 #define CEC_ISR_ARBLST_Pos (7U)
5411 #define CEC_ISR_ARBLST_Msk (0x1UL << CEC_ISR_ARBLST_Pos) /*!< 0x00000080 */
5412 #define CEC_ISR_ARBLST CEC_ISR_ARBLST_Msk /*!< CEC Arbitration Lost */
5413 #define CEC_ISR_TXBR_Pos (8U)
5414 #define CEC_ISR_TXBR_Msk (0x1UL << CEC_ISR_TXBR_Pos) /*!< 0x00000100 */
5415 #define CEC_ISR_TXBR CEC_ISR_TXBR_Msk /*!< CEC Tx Byte Request */
5416 #define CEC_ISR_TXEND_Pos (9U)
5417 #define CEC_ISR_TXEND_Msk (0x1UL << CEC_ISR_TXEND_Pos) /*!< 0x00000200 */
5418 #define CEC_ISR_TXEND CEC_ISR_TXEND_Msk /*!< CEC End of Transmission */
5419 #define CEC_ISR_TXUDR_Pos (10U)
5420 #define CEC_ISR_TXUDR_Msk (0x1UL << CEC_ISR_TXUDR_Pos) /*!< 0x00000400 */
5421 #define CEC_ISR_TXUDR CEC_ISR_TXUDR_Msk /*!< CEC Tx-Buffer Underrun */
5422 #define CEC_ISR_TXERR_Pos (11U)
5423 #define CEC_ISR_TXERR_Msk (0x1UL << CEC_ISR_TXERR_Pos) /*!< 0x00000800 */
5424 #define CEC_ISR_TXERR CEC_ISR_TXERR_Msk /*!< CEC Tx-Error */
5425 #define CEC_ISR_TXACKE_Pos (12U)
5426 #define CEC_ISR_TXACKE_Msk (0x1UL << CEC_ISR_TXACKE_Pos) /*!< 0x00001000 */
5427 #define CEC_ISR_TXACKE CEC_ISR_TXACKE_Msk /*!< CEC Tx Missing Acknowledge */
5428
5429 /******************* Bit definition for CEC_IER register ********************/
5430 #define CEC_IER_RXBRIE_Pos (0U)
5431 #define CEC_IER_RXBRIE_Msk (0x1UL << CEC_IER_RXBRIE_Pos) /*!< 0x00000001 */
5432 #define CEC_IER_RXBRIE CEC_IER_RXBRIE_Msk /*!< CEC Rx-Byte Received IT Enable */
5433 #define CEC_IER_RXENDIE_Pos (1U)
5434 #define CEC_IER_RXENDIE_Msk (0x1UL << CEC_IER_RXENDIE_Pos) /*!< 0x00000002 */
5435 #define CEC_IER_RXENDIE CEC_IER_RXENDIE_Msk /*!< CEC End Of Reception IT Enable */
5436 #define CEC_IER_RXOVRIE_Pos (2U)
5437 #define CEC_IER_RXOVRIE_Msk (0x1UL << CEC_IER_RXOVRIE_Pos) /*!< 0x00000004 */
5438 #define CEC_IER_RXOVRIE CEC_IER_RXOVRIE_Msk /*!< CEC Rx-Overrun IT Enable */
5439 #define CEC_IER_BREIE_Pos (3U)
5440 #define CEC_IER_BREIE_Msk (0x1UL << CEC_IER_BREIE_Pos) /*!< 0x00000008 */
5441 #define CEC_IER_BREIE CEC_IER_BREIE_Msk /*!< CEC Rx Bit Rising Error IT Enable */
5442 #define CEC_IER_SBPEIE_Pos (4U)
5443 #define CEC_IER_SBPEIE_Msk (0x1UL << CEC_IER_SBPEIE_Pos) /*!< 0x00000010 */
5444 #define CEC_IER_SBPEIE CEC_IER_SBPEIE_Msk /*!< CEC Rx Short Bit period Error IT Enable */
5445 #define CEC_IER_LBPEIE_Pos (5U)
5446 #define CEC_IER_LBPEIE_Msk (0x1UL << CEC_IER_LBPEIE_Pos) /*!< 0x00000020 */
5447 #define CEC_IER_LBPEIE CEC_IER_LBPEIE_Msk /*!< CEC Rx Long Bit period Error IT Enable */
5448 #define CEC_IER_RXACKEIE_Pos (6U)
5449 #define CEC_IER_RXACKEIE_Msk (0x1UL << CEC_IER_RXACKEIE_Pos) /*!< 0x00000040 */
5450 #define CEC_IER_RXACKEIE CEC_IER_RXACKEIE_Msk /*!< CEC Rx Missing Acknowledge IT Enable */
5451 #define CEC_IER_ARBLSTIE_Pos (7U)
5452 #define CEC_IER_ARBLSTIE_Msk (0x1UL << CEC_IER_ARBLSTIE_Pos) /*!< 0x00000080 */
5453 #define CEC_IER_ARBLSTIE CEC_IER_ARBLSTIE_Msk /*!< CEC Arbitration Lost IT Enable */
5454 #define CEC_IER_TXBRIE_Pos (8U)
5455 #define CEC_IER_TXBRIE_Msk (0x1UL << CEC_IER_TXBRIE_Pos) /*!< 0x00000100 */
5456 #define CEC_IER_TXBRIE CEC_IER_TXBRIE_Msk /*!< CEC Tx Byte Request IT Enable */
5457 #define CEC_IER_TXENDIE_Pos (9U)
5458 #define CEC_IER_TXENDIE_Msk (0x1UL << CEC_IER_TXENDIE_Pos) /*!< 0x00000200 */
5459 #define CEC_IER_TXENDIE CEC_IER_TXENDIE_Msk /*!< CEC End of Transmission IT Enable */
5460 #define CEC_IER_TXUDRIE_Pos (10U)
5461 #define CEC_IER_TXUDRIE_Msk (0x1UL << CEC_IER_TXUDRIE_Pos) /*!< 0x00000400 */
5462 #define CEC_IER_TXUDRIE CEC_IER_TXUDRIE_Msk /*!< CEC Tx-Buffer Underrun IT Enable */
5463 #define CEC_IER_TXERRIE_Pos (11U)
5464 #define CEC_IER_TXERRIE_Msk (0x1UL << CEC_IER_TXERRIE_Pos) /*!< 0x00000800 */
5465 #define CEC_IER_TXERRIE CEC_IER_TXERRIE_Msk /*!< CEC Tx-Error IT Enable */
5466 #define CEC_IER_TXACKEIE_Pos (12U)
5467 #define CEC_IER_TXACKEIE_Msk (0x1UL << CEC_IER_TXACKEIE_Pos) /*!< 0x00001000 */
5468 #define CEC_IER_TXACKEIE CEC_IER_TXACKEIE_Msk /*!< CEC Tx Missing Acknowledge IT Enable */
5469
5470 /******************************************************************************/
5471 /* */
5472 /* CRC calculation unit */
5473 /* */
5474 /******************************************************************************/
5475 /******************* Bit definition for CRC_DR register *********************/
5476 #define CRC_DR_DR_Pos (0U)
5477 #define CRC_DR_DR_Msk (0xFFFFFFFFUL << CRC_DR_DR_Pos) /*!< 0xFFFFFFFF */
5478 #define CRC_DR_DR CRC_DR_DR_Msk /*!< Data register bits */
5479
5480 /******************* Bit definition for CRC_IDR register ********************/
5481 #define CRC_IDR_IDR_Pos (0U)
5482 #define CRC_IDR_IDR_Msk (0xFFFFFFFFUL << CRC_IDR_IDR_Pos) /*!< 0xFFFFFFFF */
5483 #define CRC_IDR_IDR CRC_IDR_IDR_Msk /*!< General-purpose 32-bit data register bits */
5484
5485 /******************** Bit definition for CRC_CR register ********************/
5486 #define CRC_CR_RESET_Pos (0U)
5487 #define CRC_CR_RESET_Msk (0x1UL << CRC_CR_RESET_Pos) /*!< 0x00000001 */
5488 #define CRC_CR_RESET CRC_CR_RESET_Msk /*!< RESET the CRC computation unit bit */
5489 #define CRC_CR_POLYSIZE_Pos (3U)
5490 #define CRC_CR_POLYSIZE_Msk (0x3UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000018 */
5491 #define CRC_CR_POLYSIZE CRC_CR_POLYSIZE_Msk /*!< Polynomial size bits */
5492 #define CRC_CR_POLYSIZE_0 (0x1UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000008 */
5493 #define CRC_CR_POLYSIZE_1 (0x2UL << CRC_CR_POLYSIZE_Pos) /*!< 0x00000010 */
5494 #define CRC_CR_REV_IN_Pos (5U)
5495 #define CRC_CR_REV_IN_Msk (0x3UL << CRC_CR_REV_IN_Pos) /*!< 0x00000060 */
5496 #define CRC_CR_REV_IN CRC_CR_REV_IN_Msk /*!< REV_IN Reverse Input Data bits */
5497 #define CRC_CR_REV_IN_0 (0x1UL << CRC_CR_REV_IN_Pos) /*!< 0x00000020 */
5498 #define CRC_CR_REV_IN_1 (0x2UL << CRC_CR_REV_IN_Pos) /*!< 0x00000040 */
5499 #define CRC_CR_REV_OUT_Pos (7U)
5500 #define CRC_CR_REV_OUT_Msk (0x1UL << CRC_CR_REV_OUT_Pos) /*!< 0x00000080 */
5501 #define CRC_CR_REV_OUT CRC_CR_REV_OUT_Msk /*!< REV_OUT Reverse Output Data bits */
5502
5503 /******************* Bit definition for CRC_INIT register *******************/
5504 #define CRC_INIT_INIT_Pos (0U)
5505 #define CRC_INIT_INIT_Msk (0xFFFFFFFFUL << CRC_INIT_INIT_Pos) /*!< 0xFFFFFFFF */
5506 #define CRC_INIT_INIT CRC_INIT_INIT_Msk /*!< Initial CRC value bits */
5507
5508 /******************* Bit definition for CRC_POL register ********************/
5509 #define CRC_POL_POL_Pos (0U)
5510 #define CRC_POL_POL_Msk (0xFFFFFFFFUL << CRC_POL_POL_Pos) /*!< 0xFFFFFFFF */
5511 #define CRC_POL_POL CRC_POL_POL_Msk /*!< Coefficients of the polynomial */
5512
5513 /******************************************************************************/
5514 /* */
5515 /* CRS Clock Recovery System */
5516 /******************************************************************************/
5517
5518 /******************* Bit definition for CRS_CR register *********************/
5519 #define CRS_CR_SYNCOKIE_Pos (0U)
5520 #define CRS_CR_SYNCOKIE_Msk (0x1UL << CRS_CR_SYNCOKIE_Pos) /*!< 0x00000001 */
5521 #define CRS_CR_SYNCOKIE CRS_CR_SYNCOKIE_Msk /*!< SYNC event OK interrupt enable */
5522 #define CRS_CR_SYNCWARNIE_Pos (1U)
5523 #define CRS_CR_SYNCWARNIE_Msk (0x1UL << CRS_CR_SYNCWARNIE_Pos) /*!< 0x00000002 */
5524 #define CRS_CR_SYNCWARNIE CRS_CR_SYNCWARNIE_Msk /*!< SYNC warning interrupt enable */
5525 #define CRS_CR_ERRIE_Pos (2U)
5526 #define CRS_CR_ERRIE_Msk (0x1UL << CRS_CR_ERRIE_Pos) /*!< 0x00000004 */
5527 #define CRS_CR_ERRIE CRS_CR_ERRIE_Msk /*!< SYNC error or trimming error interrupt enable */
5528 #define CRS_CR_ESYNCIE_Pos (3U)
5529 #define CRS_CR_ESYNCIE_Msk (0x1UL << CRS_CR_ESYNCIE_Pos) /*!< 0x00000008 */
5530 #define CRS_CR_ESYNCIE CRS_CR_ESYNCIE_Msk /*!< Expected SYNC interrupt enable */
5531 #define CRS_CR_CEN_Pos (5U)
5532 #define CRS_CR_CEN_Msk (0x1UL << CRS_CR_CEN_Pos) /*!< 0x00000020 */
5533 #define CRS_CR_CEN CRS_CR_CEN_Msk /*!< Frequency error counter enable */
5534 #define CRS_CR_AUTOTRIMEN_Pos (6U)
5535 #define CRS_CR_AUTOTRIMEN_Msk (0x1UL << CRS_CR_AUTOTRIMEN_Pos) /*!< 0x00000040 */
5536 #define CRS_CR_AUTOTRIMEN CRS_CR_AUTOTRIMEN_Msk /*!< Automatic trimming enable */
5537 #define CRS_CR_SWSYNC_Pos (7U)
5538 #define CRS_CR_SWSYNC_Msk (0x1UL << CRS_CR_SWSYNC_Pos) /*!< 0x00000080 */
5539 #define CRS_CR_SWSYNC CRS_CR_SWSYNC_Msk /*!< Generate software SYNC event */
5540 #define CRS_CR_TRIM_Pos (8U)
5541 #define CRS_CR_TRIM_Msk (0x3FUL << CRS_CR_TRIM_Pos) /*!< 0x00003F00 */
5542 #define CRS_CR_TRIM CRS_CR_TRIM_Msk /*!< HSI48 oscillator smooth trimming */
5543
5544 /******************* Bit definition for CRS_CFGR register *********************/
5545 #define CRS_CFGR_RELOAD_Pos (0U)
5546 #define CRS_CFGR_RELOAD_Msk (0xFFFFUL << CRS_CFGR_RELOAD_Pos) /*!< 0x0000FFFF */
5547 #define CRS_CFGR_RELOAD CRS_CFGR_RELOAD_Msk /*!< Counter reload value */
5548 #define CRS_CFGR_FELIM_Pos (16U)
5549 #define CRS_CFGR_FELIM_Msk (0xFFUL << CRS_CFGR_FELIM_Pos) /*!< 0x00FF0000 */
5550 #define CRS_CFGR_FELIM CRS_CFGR_FELIM_Msk /*!< Frequency error limit */
5551
5552 #define CRS_CFGR_SYNCDIV_Pos (24U)
5553 #define CRS_CFGR_SYNCDIV_Msk (0x7UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x07000000 */
5554 #define CRS_CFGR_SYNCDIV CRS_CFGR_SYNCDIV_Msk /*!< SYNC divider */
5555 #define CRS_CFGR_SYNCDIV_0 (0x1UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x01000000 */
5556 #define CRS_CFGR_SYNCDIV_1 (0x2UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x02000000 */
5557 #define CRS_CFGR_SYNCDIV_2 (0x4UL << CRS_CFGR_SYNCDIV_Pos) /*!< 0x04000000 */
5558
5559 #define CRS_CFGR_SYNCSRC_Pos (28U)
5560 #define CRS_CFGR_SYNCSRC_Msk (0x3UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x30000000 */
5561 #define CRS_CFGR_SYNCSRC CRS_CFGR_SYNCSRC_Msk /*!< SYNC signal source selection */
5562 #define CRS_CFGR_SYNCSRC_0 (0x1UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x10000000 */
5563 #define CRS_CFGR_SYNCSRC_1 (0x2UL << CRS_CFGR_SYNCSRC_Pos) /*!< 0x20000000 */
5564
5565 #define CRS_CFGR_SYNCPOL_Pos (31U)
5566 #define CRS_CFGR_SYNCPOL_Msk (0x1UL << CRS_CFGR_SYNCPOL_Pos) /*!< 0x80000000 */
5567 #define CRS_CFGR_SYNCPOL CRS_CFGR_SYNCPOL_Msk /*!< SYNC polarity selection */
5568
5569 /******************* Bit definition for CRS_ISR register *********************/
5570 #define CRS_ISR_SYNCOKF_Pos (0U)
5571 #define CRS_ISR_SYNCOKF_Msk (0x1UL << CRS_ISR_SYNCOKF_Pos) /*!< 0x00000001 */
5572 #define CRS_ISR_SYNCOKF CRS_ISR_SYNCOKF_Msk /*!< SYNC event OK flag */
5573 #define CRS_ISR_SYNCWARNF_Pos (1U)
5574 #define CRS_ISR_SYNCWARNF_Msk (0x1UL << CRS_ISR_SYNCWARNF_Pos) /*!< 0x00000002 */
5575 #define CRS_ISR_SYNCWARNF CRS_ISR_SYNCWARNF_Msk /*!< SYNC warning flag */
5576 #define CRS_ISR_ERRF_Pos (2U)
5577 #define CRS_ISR_ERRF_Msk (0x1UL << CRS_ISR_ERRF_Pos) /*!< 0x00000004 */
5578 #define CRS_ISR_ERRF CRS_ISR_ERRF_Msk /*!< Error flag */
5579 #define CRS_ISR_ESYNCF_Pos (3U)
5580 #define CRS_ISR_ESYNCF_Msk (0x1UL << CRS_ISR_ESYNCF_Pos) /*!< 0x00000008 */
5581 #define CRS_ISR_ESYNCF CRS_ISR_ESYNCF_Msk /*!< Expected SYNC flag */
5582 #define CRS_ISR_SYNCERR_Pos (8U)
5583 #define CRS_ISR_SYNCERR_Msk (0x1UL << CRS_ISR_SYNCERR_Pos) /*!< 0x00000100 */
5584 #define CRS_ISR_SYNCERR CRS_ISR_SYNCERR_Msk /*!< SYNC error */
5585 #define CRS_ISR_SYNCMISS_Pos (9U)
5586 #define CRS_ISR_SYNCMISS_Msk (0x1UL << CRS_ISR_SYNCMISS_Pos) /*!< 0x00000200 */
5587 #define CRS_ISR_SYNCMISS CRS_ISR_SYNCMISS_Msk /*!< SYNC missed */
5588 #define CRS_ISR_TRIMOVF_Pos (10U)
5589 #define CRS_ISR_TRIMOVF_Msk (0x1UL << CRS_ISR_TRIMOVF_Pos) /*!< 0x00000400 */
5590 #define CRS_ISR_TRIMOVF CRS_ISR_TRIMOVF_Msk /*!< Trimming overflow or underflow */
5591 #define CRS_ISR_FEDIR_Pos (15U)
5592 #define CRS_ISR_FEDIR_Msk (0x1UL << CRS_ISR_FEDIR_Pos) /*!< 0x00008000 */
5593 #define CRS_ISR_FEDIR CRS_ISR_FEDIR_Msk /*!< Frequency error direction */
5594 #define CRS_ISR_FECAP_Pos (16U)
5595 #define CRS_ISR_FECAP_Msk (0xFFFFUL << CRS_ISR_FECAP_Pos) /*!< 0xFFFF0000 */
5596 #define CRS_ISR_FECAP CRS_ISR_FECAP_Msk /*!< Frequency error capture */
5597
5598 /******************* Bit definition for CRS_ICR register *********************/
5599 #define CRS_ICR_SYNCOKC_Pos (0U)
5600 #define CRS_ICR_SYNCOKC_Msk (0x1UL << CRS_ICR_SYNCOKC_Pos) /*!< 0x00000001 */
5601 #define CRS_ICR_SYNCOKC CRS_ICR_SYNCOKC_Msk /*!< SYNC event OK clear flag */
5602 #define CRS_ICR_SYNCWARNC_Pos (1U)
5603 #define CRS_ICR_SYNCWARNC_Msk (0x1UL << CRS_ICR_SYNCWARNC_Pos) /*!< 0x00000002 */
5604 #define CRS_ICR_SYNCWARNC CRS_ICR_SYNCWARNC_Msk /*!< SYNC warning clear flag */
5605 #define CRS_ICR_ERRC_Pos (2U)
5606 #define CRS_ICR_ERRC_Msk (0x1UL << CRS_ICR_ERRC_Pos) /*!< 0x00000004 */
5607 #define CRS_ICR_ERRC CRS_ICR_ERRC_Msk /*!< Error clear flag */
5608 #define CRS_ICR_ESYNCC_Pos (3U)
5609 #define CRS_ICR_ESYNCC_Msk (0x1UL << CRS_ICR_ESYNCC_Pos) /*!< 0x00000008 */
5610 #define CRS_ICR_ESYNCC CRS_ICR_ESYNCC_Msk /*!< Expected SYNC clear flag */
5611
5612 /******************************************************************************/
5613 /* */
5614 /* Crypto Processor */
5615 /* */
5616 /******************************************************************************/
5617 /******************************** CRYP VER **********************************/
5618 #define CRYP_VER_2_2
5619 /******************* Bits definition for CRYP_CR register ********************/
5620 #define CRYP_CR_ALGODIR_Pos (2U)
5621 #define CRYP_CR_ALGODIR_Msk (0x1UL << CRYP_CR_ALGODIR_Pos) /*!< 0x00000004 */
5622 #define CRYP_CR_ALGODIR CRYP_CR_ALGODIR_Msk
5623
5624 #define CRYP_CR_ALGOMODE_Pos (3U)
5625 #define CRYP_CR_ALGOMODE_Msk (0x10007UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00080038 */
5626 #define CRYP_CR_ALGOMODE CRYP_CR_ALGOMODE_Msk
5627 #define CRYP_CR_ALGOMODE_0 (0x00001UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000008 */
5628 #define CRYP_CR_ALGOMODE_1 (0x00002UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000010 */
5629 #define CRYP_CR_ALGOMODE_2 (0x00004UL << CRYP_CR_ALGOMODE_Pos) /*!< 0x00000020 */
5630 #define CRYP_CR_ALGOMODE_TDES_ECB ((uint32_t)0x00000000)
5631 #define CRYP_CR_ALGOMODE_TDES_CBC_Pos (3U)
5632 #define CRYP_CR_ALGOMODE_TDES_CBC_Msk (0x1UL << CRYP_CR_ALGOMODE_TDES_CBC_Pos) /*!< 0x00000008 */
5633 #define CRYP_CR_ALGOMODE_TDES_CBC CRYP_CR_ALGOMODE_TDES_CBC_Msk
5634 #define CRYP_CR_ALGOMODE_DES_ECB_Pos (4U)
5635 #define CRYP_CR_ALGOMODE_DES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_DES_ECB_Pos) /*!< 0x00000010 */
5636 #define CRYP_CR_ALGOMODE_DES_ECB CRYP_CR_ALGOMODE_DES_ECB_Msk
5637 #define CRYP_CR_ALGOMODE_DES_CBC_Pos (3U)
5638 #define CRYP_CR_ALGOMODE_DES_CBC_Msk (0x3UL << CRYP_CR_ALGOMODE_DES_CBC_Pos) /*!< 0x00000018 */
5639 #define CRYP_CR_ALGOMODE_DES_CBC CRYP_CR_ALGOMODE_DES_CBC_Msk
5640 #define CRYP_CR_ALGOMODE_AES_ECB_Pos (5U)
5641 #define CRYP_CR_ALGOMODE_AES_ECB_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_ECB_Pos) /*!< 0x00000020 */
5642 #define CRYP_CR_ALGOMODE_AES_ECB CRYP_CR_ALGOMODE_AES_ECB_Msk
5643 #define CRYP_CR_ALGOMODE_AES_CBC_Pos (3U)
5644 #define CRYP_CR_ALGOMODE_AES_CBC_Msk (0x5UL << CRYP_CR_ALGOMODE_AES_CBC_Pos) /*!< 0x00000028 */
5645 #define CRYP_CR_ALGOMODE_AES_CBC CRYP_CR_ALGOMODE_AES_CBC_Msk
5646 #define CRYP_CR_ALGOMODE_AES_CTR_Pos (4U)
5647 #define CRYP_CR_ALGOMODE_AES_CTR_Msk (0x3UL << CRYP_CR_ALGOMODE_AES_CTR_Pos) /*!< 0x00000030 */
5648 #define CRYP_CR_ALGOMODE_AES_CTR CRYP_CR_ALGOMODE_AES_CTR_Msk
5649 #define CRYP_CR_ALGOMODE_AES_KEY_Pos (3U)
5650 #define CRYP_CR_ALGOMODE_AES_KEY_Msk (0x7UL << CRYP_CR_ALGOMODE_AES_KEY_Pos) /*!< 0x00000038 */
5651 #define CRYP_CR_ALGOMODE_AES_KEY CRYP_CR_ALGOMODE_AES_KEY_Msk
5652 #define CRYP_CR_ALGOMODE_AES_GCM_Pos (19U)
5653 #define CRYP_CR_ALGOMODE_AES_GCM_Msk (0x1UL << CRYP_CR_ALGOMODE_AES_GCM_Pos) /*!< 0x00080000 */
5654 #define CRYP_CR_ALGOMODE_AES_GCM CRYP_CR_ALGOMODE_AES_GCM_Msk
5655 #define CRYP_CR_ALGOMODE_AES_CCM_Pos (3U)
5656 #define CRYP_CR_ALGOMODE_AES_CCM_Msk (0x10001UL << CRYP_CR_ALGOMODE_AES_CCM_Pos) /*!< 0x00080008 */
5657 #define CRYP_CR_ALGOMODE_AES_CCM CRYP_CR_ALGOMODE_AES_CCM_Msk
5658
5659 #define CRYP_CR_DATATYPE_Pos (6U)
5660 #define CRYP_CR_DATATYPE_Msk (0x3UL << CRYP_CR_DATATYPE_Pos) /*!< 0x000000C0 */
5661 #define CRYP_CR_DATATYPE CRYP_CR_DATATYPE_Msk
5662 #define CRYP_CR_DATATYPE_0 (0x1UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000040 */
5663 #define CRYP_CR_DATATYPE_1 (0x2UL << CRYP_CR_DATATYPE_Pos) /*!< 0x00000080 */
5664 #define CRYP_CR_KEYSIZE_Pos (8U)
5665 #define CRYP_CR_KEYSIZE_Msk (0x3UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000300 */
5666 #define CRYP_CR_KEYSIZE CRYP_CR_KEYSIZE_Msk
5667 #define CRYP_CR_KEYSIZE_0 (0x1UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000100 */
5668 #define CRYP_CR_KEYSIZE_1 (0x2UL << CRYP_CR_KEYSIZE_Pos) /*!< 0x00000200 */
5669 #define CRYP_CR_FFLUSH_Pos (14U)
5670 #define CRYP_CR_FFLUSH_Msk (0x1UL << CRYP_CR_FFLUSH_Pos) /*!< 0x00004000 */
5671 #define CRYP_CR_FFLUSH CRYP_CR_FFLUSH_Msk
5672 #define CRYP_CR_CRYPEN_Pos (15U)
5673 #define CRYP_CR_CRYPEN_Msk (0x1UL << CRYP_CR_CRYPEN_Pos) /*!< 0x00008000 */
5674 #define CRYP_CR_CRYPEN CRYP_CR_CRYPEN_Msk
5675
5676 #define CRYP_CR_GCM_CCMPH_Pos (16U)
5677 #define CRYP_CR_GCM_CCMPH_Msk (0x3UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00030000 */
5678 #define CRYP_CR_GCM_CCMPH CRYP_CR_GCM_CCMPH_Msk
5679 #define CRYP_CR_GCM_CCMPH_0 (0x1UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00010000 */
5680 #define CRYP_CR_GCM_CCMPH_1 (0x2UL << CRYP_CR_GCM_CCMPH_Pos) /*!< 0x00020000 */
5681 #define CRYP_CR_ALGOMODE_3 ((uint32_t)0x00080000)
5682 #define CRYP_CR_NPBLB_Pos (20U)
5683 #define CRYP_CR_NPBLB_Msk (0xFUL << CRYP_CR_NPBLB_Pos) /*!< 0x00F00000 */
5684 #define CRYP_CR_NPBLB CRYP_CR_NPBLB_Msk
5685
5686 /****************** Bits definition for CRYP_SR register *********************/
5687 #define CRYP_SR_IFEM_Pos (0U)
5688 #define CRYP_SR_IFEM_Msk (0x1UL << CRYP_SR_IFEM_Pos) /*!< 0x00000001 */
5689 #define CRYP_SR_IFEM CRYP_SR_IFEM_Msk
5690 #define CRYP_SR_IFNF_Pos (1U)
5691 #define CRYP_SR_IFNF_Msk (0x1UL << CRYP_SR_IFNF_Pos) /*!< 0x00000002 */
5692 #define CRYP_SR_IFNF CRYP_SR_IFNF_Msk
5693 #define CRYP_SR_OFNE_Pos (2U)
5694 #define CRYP_SR_OFNE_Msk (0x1UL << CRYP_SR_OFNE_Pos) /*!< 0x00000004 */
5695 #define CRYP_SR_OFNE CRYP_SR_OFNE_Msk
5696 #define CRYP_SR_OFFU_Pos (3U)
5697 #define CRYP_SR_OFFU_Msk (0x1UL << CRYP_SR_OFFU_Pos) /*!< 0x00000008 */
5698 #define CRYP_SR_OFFU CRYP_SR_OFFU_Msk
5699 #define CRYP_SR_BUSY_Pos (4U)
5700 #define CRYP_SR_BUSY_Msk (0x1UL << CRYP_SR_BUSY_Pos) /*!< 0x00000010 */
5701 #define CRYP_SR_BUSY CRYP_SR_BUSY_Msk
5702 /****************** Bits definition for CRYP_DMACR register ******************/
5703 #define CRYP_DMACR_DIEN_Pos (0U)
5704 #define CRYP_DMACR_DIEN_Msk (0x1UL << CRYP_DMACR_DIEN_Pos) /*!< 0x00000001 */
5705 #define CRYP_DMACR_DIEN CRYP_DMACR_DIEN_Msk
5706 #define CRYP_DMACR_DOEN_Pos (1U)
5707 #define CRYP_DMACR_DOEN_Msk (0x1UL << CRYP_DMACR_DOEN_Pos) /*!< 0x00000002 */
5708 #define CRYP_DMACR_DOEN CRYP_DMACR_DOEN_Msk
5709 /***************** Bits definition for CRYP_IMSCR register ******************/
5710 #define CRYP_IMSCR_INIM_Pos (0U)
5711 #define CRYP_IMSCR_INIM_Msk (0x1UL << CRYP_IMSCR_INIM_Pos) /*!< 0x00000001 */
5712 #define CRYP_IMSCR_INIM CRYP_IMSCR_INIM_Msk
5713 #define CRYP_IMSCR_OUTIM_Pos (1U)
5714 #define CRYP_IMSCR_OUTIM_Msk (0x1UL << CRYP_IMSCR_OUTIM_Pos) /*!< 0x00000002 */
5715 #define CRYP_IMSCR_OUTIM CRYP_IMSCR_OUTIM_Msk
5716 /****************** Bits definition for CRYP_RISR register *******************/
5717 #define CRYP_RISR_INRIS_Pos (0U)
5718 #define CRYP_RISR_INRIS_Msk (0x1UL << CRYP_RISR_INRIS_Pos) /*!< 0x00000001 */
5719 #define CRYP_RISR_INRIS CRYP_RISR_INRIS_Msk
5720 #define CRYP_RISR_OUTRIS_Pos (1U)
5721 #define CRYP_RISR_OUTRIS_Msk (0x1UL << CRYP_RISR_OUTRIS_Pos) /*!< 0x00000002 */
5722 #define CRYP_RISR_OUTRIS CRYP_RISR_OUTRIS_Msk
5723 /****************** Bits definition for CRYP_MISR register *******************/
5724 #define CRYP_MISR_INMIS_Pos (0U)
5725 #define CRYP_MISR_INMIS_Msk (0x1UL << CRYP_MISR_INMIS_Pos) /*!< 0x00000001 */
5726 #define CRYP_MISR_INMIS CRYP_MISR_INMIS_Msk
5727 #define CRYP_MISR_OUTMIS_Pos (1U)
5728 #define CRYP_MISR_OUTMIS_Msk (0x1UL << CRYP_MISR_OUTMIS_Pos) /*!< 0x00000002 */
5729 #define CRYP_MISR_OUTMIS CRYP_MISR_OUTMIS_Msk
5730
5731 /******************************************************************************/
5732 /* */
5733 /* Digital to Analog Converter */
5734 /* */
5735 /******************************************************************************/
5736 /******************** Bit definition for DAC_CR register ********************/
5737 #define DAC_CR_EN1_Pos (0U)
5738 #define DAC_CR_EN1_Msk (0x1UL << DAC_CR_EN1_Pos) /*!< 0x00000001 */
5739 #define DAC_CR_EN1 DAC_CR_EN1_Msk /*!<DAC channel1 enable */
5740 #define DAC_CR_TEN1_Pos (1U)
5741 #define DAC_CR_TEN1_Msk (0x1UL << DAC_CR_TEN1_Pos) /*!< 0x00000002 */
5742 #define DAC_CR_TEN1 DAC_CR_TEN1_Msk /*!<DAC channel1 Trigger enable */
5743
5744 #define DAC_CR_TSEL1_Pos (2U)
5745 #define DAC_CR_TSEL1_Msk (0xFUL << DAC_CR_TSEL1_Pos) /*!< 0x0000003C */
5746 #define DAC_CR_TSEL1 DAC_CR_TSEL1_Msk /*!<TSEL1[2:0] (DAC channel1 Trigger selection) */
5747 #define DAC_CR_TSEL1_0 (0x1UL << DAC_CR_TSEL1_Pos) /*!< 0x00000004 */
5748 #define DAC_CR_TSEL1_1 (0x2UL << DAC_CR_TSEL1_Pos) /*!< 0x00000008 */
5749 #define DAC_CR_TSEL1_2 (0x4UL << DAC_CR_TSEL1_Pos) /*!< 0x00000010 */
5750 #define DAC_CR_TSEL1_3 (0x8UL << DAC_CR_TSEL1_Pos) /*!< 0x00000020 */
5751
5752
5753 #define DAC_CR_WAVE1_Pos (6U)
5754 #define DAC_CR_WAVE1_Msk (0x3UL << DAC_CR_WAVE1_Pos) /*!< 0x000000C0 */
5755 #define DAC_CR_WAVE1 DAC_CR_WAVE1_Msk /*!<WAVE1[1:0] (DAC channel1 noise/triangle wave generation enable) */
5756 #define DAC_CR_WAVE1_0 (0x1UL << DAC_CR_WAVE1_Pos) /*!< 0x00000040 */
5757 #define DAC_CR_WAVE1_1 (0x2UL << DAC_CR_WAVE1_Pos) /*!< 0x00000080 */
5758
5759 #define DAC_CR_MAMP1_Pos (8U)
5760 #define DAC_CR_MAMP1_Msk (0xFUL << DAC_CR_MAMP1_Pos) /*!< 0x00000F00 */
5761 #define DAC_CR_MAMP1 DAC_CR_MAMP1_Msk /*!<MAMP1[3:0] (DAC channel1 Mask/Amplitude selector) */
5762 #define DAC_CR_MAMP1_0 (0x1UL << DAC_CR_MAMP1_Pos) /*!< 0x00000100 */
5763 #define DAC_CR_MAMP1_1 (0x2UL << DAC_CR_MAMP1_Pos) /*!< 0x00000200 */
5764 #define DAC_CR_MAMP1_2 (0x4UL << DAC_CR_MAMP1_Pos) /*!< 0x00000400 */
5765 #define DAC_CR_MAMP1_3 (0x8UL << DAC_CR_MAMP1_Pos) /*!< 0x00000800 */
5766
5767 #define DAC_CR_DMAEN1_Pos (12U)
5768 #define DAC_CR_DMAEN1_Msk (0x1UL << DAC_CR_DMAEN1_Pos) /*!< 0x00001000 */
5769 #define DAC_CR_DMAEN1 DAC_CR_DMAEN1_Msk /*!<DAC channel1 DMA enable */
5770 #define DAC_CR_DMAUDRIE1_Pos (13U)
5771 #define DAC_CR_DMAUDRIE1_Msk (0x1UL << DAC_CR_DMAUDRIE1_Pos) /*!< 0x00002000 */
5772 #define DAC_CR_DMAUDRIE1 DAC_CR_DMAUDRIE1_Msk /*!<DAC channel 1 DMA underrun interrupt enable >*/
5773 #define DAC_CR_CEN1_Pos (14U)
5774 #define DAC_CR_CEN1_Msk (0x1UL << DAC_CR_CEN1_Pos) /*!< 0x00004000 */
5775 #define DAC_CR_CEN1 DAC_CR_CEN1_Msk /*!<DAC channel 1 calibration enable >*/
5776
5777 #define DAC_CR_EN2_Pos (16U)
5778 #define DAC_CR_EN2_Msk (0x1UL << DAC_CR_EN2_Pos) /*!< 0x00010000 */
5779 #define DAC_CR_EN2 DAC_CR_EN2_Msk /*!<DAC channel2 enable */
5780 #define DAC_CR_TEN2_Pos (17U)
5781 #define DAC_CR_TEN2_Msk (0x1UL << DAC_CR_TEN2_Pos) /*!< 0x00020000 */
5782 #define DAC_CR_TEN2 DAC_CR_TEN2_Msk /*!<DAC channel2 Trigger enable */
5783
5784 #define DAC_CR_TSEL2_Pos (18U)
5785 #define DAC_CR_TSEL2_Msk (0xFUL << DAC_CR_TSEL2_Pos) /*!< 0x003C0000 */
5786 #define DAC_CR_TSEL2 DAC_CR_TSEL2_Msk /*!<TSEL2[2:0] (DAC channel2 Trigger selection) */
5787 #define DAC_CR_TSEL2_0 (0x1UL << DAC_CR_TSEL2_Pos) /*!< 0x00040000 */
5788 #define DAC_CR_TSEL2_1 (0x2UL << DAC_CR_TSEL2_Pos) /*!< 0x00080000 */
5789 #define DAC_CR_TSEL2_2 (0x4UL << DAC_CR_TSEL2_Pos) /*!< 0x00100000 */
5790 #define DAC_CR_TSEL2_3 (0x8UL << DAC_CR_TSEL2_Pos) /*!< 0x00200000 */
5791
5792
5793 #define DAC_CR_WAVE2_Pos (22U)
5794 #define DAC_CR_WAVE2_Msk (0x3UL << DAC_CR_WAVE2_Pos) /*!< 0x00C00000 */
5795 #define DAC_CR_WAVE2 DAC_CR_WAVE2_Msk /*!<WAVE2[1:0] (DAC channel2 noise/triangle wave generation enable) */
5796 #define DAC_CR_WAVE2_0 (0x1UL << DAC_CR_WAVE2_Pos) /*!< 0x00400000 */
5797 #define DAC_CR_WAVE2_1 (0x2UL << DAC_CR_WAVE2_Pos) /*!< 0x00800000 */
5798
5799 #define DAC_CR_MAMP2_Pos (24U)
5800 #define DAC_CR_MAMP2_Msk (0xFUL << DAC_CR_MAMP2_Pos) /*!< 0x0F000000 */
5801 #define DAC_CR_MAMP2 DAC_CR_MAMP2_Msk /*!<MAMP2[3:0] (DAC channel2 Mask/Amplitude selector) */
5802 #define DAC_CR_MAMP2_0 (0x1UL << DAC_CR_MAMP2_Pos) /*!< 0x01000000 */
5803 #define DAC_CR_MAMP2_1 (0x2UL << DAC_CR_MAMP2_Pos) /*!< 0x02000000 */
5804 #define DAC_CR_MAMP2_2 (0x4UL << DAC_CR_MAMP2_Pos) /*!< 0x04000000 */
5805 #define DAC_CR_MAMP2_3 (0x8UL << DAC_CR_MAMP2_Pos) /*!< 0x08000000 */
5806
5807 #define DAC_CR_DMAEN2_Pos (28U)
5808 #define DAC_CR_DMAEN2_Msk (0x1UL << DAC_CR_DMAEN2_Pos) /*!< 0x10000000 */
5809 #define DAC_CR_DMAEN2 DAC_CR_DMAEN2_Msk /*!<DAC channel2 DMA enabled */
5810 #define DAC_CR_DMAUDRIE2_Pos (29U)
5811 #define DAC_CR_DMAUDRIE2_Msk (0x1UL << DAC_CR_DMAUDRIE2_Pos) /*!< 0x20000000 */
5812 #define DAC_CR_DMAUDRIE2 DAC_CR_DMAUDRIE2_Msk /*!<DAC channel2 DMA underrun interrupt enable >*/
5813 #define DAC_CR_CEN2_Pos (30U)
5814 #define DAC_CR_CEN2_Msk (0x1UL << DAC_CR_CEN2_Pos) /*!< 0x40000000 */
5815 #define DAC_CR_CEN2 DAC_CR_CEN2_Msk /*!<DAC channel2 calibration enable >*/
5816
5817 /***************** Bit definition for DAC_SWTRIGR register ******************/
5818 #define DAC_SWTRIGR_SWTRIG1_Pos (0U)
5819 #define DAC_SWTRIGR_SWTRIG1_Msk (0x1UL << DAC_SWTRIGR_SWTRIG1_Pos) /*!< 0x00000001 */
5820 #define DAC_SWTRIGR_SWTRIG1 DAC_SWTRIGR_SWTRIG1_Msk /*!<DAC channel1 software trigger */
5821 #define DAC_SWTRIGR_SWTRIG2_Pos (1U)
5822 #define DAC_SWTRIGR_SWTRIG2_Msk (0x1UL << DAC_SWTRIGR_SWTRIG2_Pos) /*!< 0x00000002 */
5823 #define DAC_SWTRIGR_SWTRIG2 DAC_SWTRIGR_SWTRIG2_Msk /*!<DAC channel2 software trigger */
5824
5825 /***************** Bit definition for DAC_DHR12R1 register ******************/
5826 #define DAC_DHR12R1_DACC1DHR_Pos (0U)
5827 #define DAC_DHR12R1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12R1_DACC1DHR_Pos) /*!< 0x00000FFF */
5828 #define DAC_DHR12R1_DACC1DHR DAC_DHR12R1_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5829
5830 /***************** Bit definition for DAC_DHR12L1 register ******************/
5831 #define DAC_DHR12L1_DACC1DHR_Pos (4U)
5832 #define DAC_DHR12L1_DACC1DHR_Msk (0xFFFUL << DAC_DHR12L1_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5833 #define DAC_DHR12L1_DACC1DHR DAC_DHR12L1_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5834
5835 /****************** Bit definition for DAC_DHR8R1 register ******************/
5836 #define DAC_DHR8R1_DACC1DHR_Pos (0U)
5837 #define DAC_DHR8R1_DACC1DHR_Msk (0xFFUL << DAC_DHR8R1_DACC1DHR_Pos) /*!< 0x000000FF */
5838 #define DAC_DHR8R1_DACC1DHR DAC_DHR8R1_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5839
5840 /***************** Bit definition for DAC_DHR12R2 register ******************/
5841 #define DAC_DHR12R2_DACC2DHR_Pos (0U)
5842 #define DAC_DHR12R2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12R2_DACC2DHR_Pos) /*!< 0x00000FFF */
5843 #define DAC_DHR12R2_DACC2DHR DAC_DHR12R2_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5844
5845 /***************** Bit definition for DAC_DHR12L2 register ******************/
5846 #define DAC_DHR12L2_DACC2DHR_Pos (4U)
5847 #define DAC_DHR12L2_DACC2DHR_Msk (0xFFFUL << DAC_DHR12L2_DACC2DHR_Pos) /*!< 0x0000FFF0 */
5848 #define DAC_DHR12L2_DACC2DHR DAC_DHR12L2_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5849
5850 /****************** Bit definition for DAC_DHR8R2 register ******************/
5851 #define DAC_DHR8R2_DACC2DHR_Pos (0U)
5852 #define DAC_DHR8R2_DACC2DHR_Msk (0xFFUL << DAC_DHR8R2_DACC2DHR_Pos) /*!< 0x000000FF */
5853 #define DAC_DHR8R2_DACC2DHR DAC_DHR8R2_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5854
5855 /***************** Bit definition for DAC_DHR12RD register ******************/
5856 #define DAC_DHR12RD_DACC1DHR_Pos (0U)
5857 #define DAC_DHR12RD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC1DHR_Pos) /*!< 0x00000FFF */
5858 #define DAC_DHR12RD_DACC1DHR DAC_DHR12RD_DACC1DHR_Msk /*!<DAC channel1 12-bit Right aligned data */
5859 #define DAC_DHR12RD_DACC2DHR_Pos (16U)
5860 #define DAC_DHR12RD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12RD_DACC2DHR_Pos) /*!< 0x0FFF0000 */
5861 #define DAC_DHR12RD_DACC2DHR DAC_DHR12RD_DACC2DHR_Msk /*!<DAC channel2 12-bit Right aligned data */
5862
5863 /***************** Bit definition for DAC_DHR12LD register ******************/
5864 #define DAC_DHR12LD_DACC1DHR_Pos (4U)
5865 #define DAC_DHR12LD_DACC1DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC1DHR_Pos) /*!< 0x0000FFF0 */
5866 #define DAC_DHR12LD_DACC1DHR DAC_DHR12LD_DACC1DHR_Msk /*!<DAC channel1 12-bit Left aligned data */
5867 #define DAC_DHR12LD_DACC2DHR_Pos (20U)
5868 #define DAC_DHR12LD_DACC2DHR_Msk (0xFFFUL << DAC_DHR12LD_DACC2DHR_Pos) /*!< 0xFFF00000 */
5869 #define DAC_DHR12LD_DACC2DHR DAC_DHR12LD_DACC2DHR_Msk /*!<DAC channel2 12-bit Left aligned data */
5870
5871 /****************** Bit definition for DAC_DHR8RD register ******************/
5872 #define DAC_DHR8RD_DACC1DHR_Pos (0U)
5873 #define DAC_DHR8RD_DACC1DHR_Msk (0xFFUL << DAC_DHR8RD_DACC1DHR_Pos) /*!< 0x000000FF */
5874 #define DAC_DHR8RD_DACC1DHR DAC_DHR8RD_DACC1DHR_Msk /*!<DAC channel1 8-bit Right aligned data */
5875 #define DAC_DHR8RD_DACC2DHR_Pos (8U)
5876 #define DAC_DHR8RD_DACC2DHR_Msk (0xFFUL << DAC_DHR8RD_DACC2DHR_Pos) /*!< 0x0000FF00 */
5877 #define DAC_DHR8RD_DACC2DHR DAC_DHR8RD_DACC2DHR_Msk /*!<DAC channel2 8-bit Right aligned data */
5878
5879 /******************* Bit definition for DAC_DOR1 register *******************/
5880 #define DAC_DOR1_DACC1DOR_Pos (0U)
5881 #define DAC_DOR1_DACC1DOR_Msk (0xFFFUL << DAC_DOR1_DACC1DOR_Pos) /*!< 0x00000FFF */
5882 #define DAC_DOR1_DACC1DOR DAC_DOR1_DACC1DOR_Msk /*!<DAC channel1 data output */
5883
5884 /******************* Bit definition for DAC_DOR2 register *******************/
5885 #define DAC_DOR2_DACC2DOR_Pos (0U)
5886 #define DAC_DOR2_DACC2DOR_Msk (0xFFFUL << DAC_DOR2_DACC2DOR_Pos) /*!< 0x00000FFF */
5887 #define DAC_DOR2_DACC2DOR DAC_DOR2_DACC2DOR_Msk /*!<DAC channel2 data output */
5888
5889 /******************** Bit definition for DAC_SR register ********************/
5890 #define DAC_SR_DMAUDR1_Pos (13U)
5891 #define DAC_SR_DMAUDR1_Msk (0x1UL << DAC_SR_DMAUDR1_Pos) /*!< 0x00002000 */
5892 #define DAC_SR_DMAUDR1 DAC_SR_DMAUDR1_Msk /*!<DAC channel1 DMA underrun flag */
5893 #define DAC_SR_CAL_FLAG1_Pos (14U)
5894 #define DAC_SR_CAL_FLAG1_Msk (0x1UL << DAC_SR_CAL_FLAG1_Pos) /*!< 0x00004000 */
5895 #define DAC_SR_CAL_FLAG1 DAC_SR_CAL_FLAG1_Msk /*!<DAC channel1 calibration offset status */
5896 #define DAC_SR_BWST1_Pos (15U)
5897 #define DAC_SR_BWST1_Msk (0x4001UL << DAC_SR_BWST1_Pos) /*!< 0x20008000 */
5898 #define DAC_SR_BWST1 DAC_SR_BWST1_Msk /*!<DAC channel1 busy writing sample time flag */
5899
5900 #define DAC_SR_DMAUDR2_Pos (29U)
5901 #define DAC_SR_DMAUDR2_Msk (0x1UL << DAC_SR_DMAUDR2_Pos) /*!< 0x20000000 */
5902 #define DAC_SR_DMAUDR2 DAC_SR_DMAUDR2_Msk /*!<DAC channel2 DMA underrun flag */
5903 #define DAC_SR_CAL_FLAG2_Pos (30U)
5904 #define DAC_SR_CAL_FLAG2_Msk (0x1UL << DAC_SR_CAL_FLAG2_Pos) /*!< 0x40000000 */
5905 #define DAC_SR_CAL_FLAG2 DAC_SR_CAL_FLAG2_Msk /*!<DAC channel2 calibration offset status */
5906 #define DAC_SR_BWST2_Pos (31U)
5907 #define DAC_SR_BWST2_Msk (0x1UL << DAC_SR_BWST2_Pos) /*!< 0x80000000 */
5908 #define DAC_SR_BWST2 DAC_SR_BWST2_Msk /*!<DAC channel2 busy writing sample time flag */
5909
5910 /******************* Bit definition for DAC_CCR register ********************/
5911 #define DAC_CCR_OTRIM1_Pos (0U)
5912 #define DAC_CCR_OTRIM1_Msk (0x1FUL << DAC_CCR_OTRIM1_Pos) /*!< 0x0000001F */
5913 #define DAC_CCR_OTRIM1 DAC_CCR_OTRIM1_Msk /*!<DAC channel1 offset trimming value */
5914 #define DAC_CCR_OTRIM2_Pos (16U)
5915 #define DAC_CCR_OTRIM2_Msk (0x1FUL << DAC_CCR_OTRIM2_Pos) /*!< 0x001F0000 */
5916 #define DAC_CCR_OTRIM2 DAC_CCR_OTRIM2_Msk /*!<DAC channel2 offset trimming value */
5917
5918 /******************* Bit definition for DAC_MCR register *******************/
5919 #define DAC_MCR_MODE1_Pos (0U)
5920 #define DAC_MCR_MODE1_Msk (0x7UL << DAC_MCR_MODE1_Pos) /*!< 0x00000007 */
5921 #define DAC_MCR_MODE1 DAC_MCR_MODE1_Msk /*!<MODE1[2:0] (DAC channel1 mode) */
5922 #define DAC_MCR_MODE1_0 (0x1UL << DAC_MCR_MODE1_Pos) /*!< 0x00000001 */
5923 #define DAC_MCR_MODE1_1 (0x2UL << DAC_MCR_MODE1_Pos) /*!< 0x00000002 */
5924 #define DAC_MCR_MODE1_2 (0x4UL << DAC_MCR_MODE1_Pos) /*!< 0x00000004 */
5925
5926 #define DAC_MCR_MODE2_Pos (16U)
5927 #define DAC_MCR_MODE2_Msk (0x7UL << DAC_MCR_MODE2_Pos) /*!< 0x00070000 */
5928 #define DAC_MCR_MODE2 DAC_MCR_MODE2_Msk /*!<MODE2[2:0] (DAC channel2 mode) */
5929 #define DAC_MCR_MODE2_0 (0x1UL << DAC_MCR_MODE2_Pos) /*!< 0x00010000 */
5930 #define DAC_MCR_MODE2_1 (0x2UL << DAC_MCR_MODE2_Pos) /*!< 0x00020000 */
5931 #define DAC_MCR_MODE2_2 (0x4UL << DAC_MCR_MODE2_Pos) /*!< 0x00040000 */
5932
5933 /****************** Bit definition for DAC_SHSR1 register ******************/
5934 #define DAC_SHSR1_TSAMPLE1_Pos (0U)
5935 #define DAC_SHSR1_TSAMPLE1_Msk (0x3FFUL << DAC_SHSR1_TSAMPLE1_Pos) /*!< 0x000003FF */
5936 #define DAC_SHSR1_TSAMPLE1 DAC_SHSR1_TSAMPLE1_Msk /*!<DAC channel1 sample time */
5937
5938 /****************** Bit definition for DAC_SHSR2 register ******************/
5939 #define DAC_SHSR2_TSAMPLE2_Pos (0U)
5940 #define DAC_SHSR2_TSAMPLE2_Msk (0x3FFUL << DAC_SHSR2_TSAMPLE2_Pos) /*!< 0x000003FF */
5941 #define DAC_SHSR2_TSAMPLE2 DAC_SHSR2_TSAMPLE2_Msk /*!<DAC channel2 sample time */
5942
5943 /****************** Bit definition for DAC_SHHR register ******************/
5944 #define DAC_SHHR_THOLD1_Pos (0U)
5945 #define DAC_SHHR_THOLD1_Msk (0x3FFUL << DAC_SHHR_THOLD1_Pos) /*!< 0x000003FF */
5946 #define DAC_SHHR_THOLD1 DAC_SHHR_THOLD1_Msk /*!<DAC channel1 hold time */
5947 #define DAC_SHHR_THOLD2_Pos (16U)
5948 #define DAC_SHHR_THOLD2_Msk (0x3FFUL << DAC_SHHR_THOLD2_Pos) /*!< 0x03FF0000 */
5949 #define DAC_SHHR_THOLD2 DAC_SHHR_THOLD2_Msk /*!<DAC channel2 hold time */
5950
5951 /****************** Bit definition for DAC_SHRR register ******************/
5952 #define DAC_SHRR_TREFRESH1_Pos (0U)
5953 #define DAC_SHRR_TREFRESH1_Msk (0xFFUL << DAC_SHRR_TREFRESH1_Pos) /*!< 0x000000FF */
5954 #define DAC_SHRR_TREFRESH1 DAC_SHRR_TREFRESH1_Msk /*!<DAC channel1 refresh time */
5955 #define DAC_SHRR_TREFRESH2_Pos (16U)
5956 #define DAC_SHRR_TREFRESH2_Msk (0xFFUL << DAC_SHRR_TREFRESH2_Pos) /*!< 0x00FF0000 */
5957 #define DAC_SHRR_TREFRESH2 DAC_SHRR_TREFRESH2_Msk /*!<DAC channel2 refresh time */
5958
5959 /******************************************************************************/
5960 /* */
5961 /* DCMI */
5962 /* */
5963 /******************************************************************************/
5964 /******************** Bits definition for DCMI_CR register ******************/
5965 #define DCMI_CR_CAPTURE_Pos (0U)
5966 #define DCMI_CR_CAPTURE_Msk (0x1UL << DCMI_CR_CAPTURE_Pos) /*!< 0x00000001 */
5967 #define DCMI_CR_CAPTURE DCMI_CR_CAPTURE_Msk
5968 #define DCMI_CR_CM_Pos (1U)
5969 #define DCMI_CR_CM_Msk (0x1UL << DCMI_CR_CM_Pos) /*!< 0x00000002 */
5970 #define DCMI_CR_CM DCMI_CR_CM_Msk
5971 #define DCMI_CR_CROP_Pos (2U)
5972 #define DCMI_CR_CROP_Msk (0x1UL << DCMI_CR_CROP_Pos) /*!< 0x00000004 */
5973 #define DCMI_CR_CROP DCMI_CR_CROP_Msk
5974 #define DCMI_CR_JPEG_Pos (3U)
5975 #define DCMI_CR_JPEG_Msk (0x1UL << DCMI_CR_JPEG_Pos) /*!< 0x00000008 */
5976 #define DCMI_CR_JPEG DCMI_CR_JPEG_Msk
5977 #define DCMI_CR_ESS_Pos (4U)
5978 #define DCMI_CR_ESS_Msk (0x1UL << DCMI_CR_ESS_Pos) /*!< 0x00000010 */
5979 #define DCMI_CR_ESS DCMI_CR_ESS_Msk
5980 #define DCMI_CR_PCKPOL_Pos (5U)
5981 #define DCMI_CR_PCKPOL_Msk (0x1UL << DCMI_CR_PCKPOL_Pos) /*!< 0x00000020 */
5982 #define DCMI_CR_PCKPOL DCMI_CR_PCKPOL_Msk
5983 #define DCMI_CR_HSPOL_Pos (6U)
5984 #define DCMI_CR_HSPOL_Msk (0x1UL << DCMI_CR_HSPOL_Pos) /*!< 0x00000040 */
5985 #define DCMI_CR_HSPOL DCMI_CR_HSPOL_Msk
5986 #define DCMI_CR_VSPOL_Pos (7U)
5987 #define DCMI_CR_VSPOL_Msk (0x1UL << DCMI_CR_VSPOL_Pos) /*!< 0x00000080 */
5988 #define DCMI_CR_VSPOL DCMI_CR_VSPOL_Msk
5989 #define DCMI_CR_FCRC_0 ((uint32_t)0x00000100U)
5990 #define DCMI_CR_FCRC_1 ((uint32_t)0x00000200U)
5991 #define DCMI_CR_EDM_0 ((uint32_t)0x00000400U)
5992 #define DCMI_CR_EDM_1 ((uint32_t)0x00000800U)
5993 #define DCMI_CR_CRE_Pos (12U)
5994 #define DCMI_CR_CRE_Msk (0x1UL << DCMI_CR_CRE_Pos) /*!< 0x00001000 */
5995 #define DCMI_CR_CRE DCMI_CR_CRE_Msk
5996 #define DCMI_CR_ENABLE_Pos (14U)
5997 #define DCMI_CR_ENABLE_Msk (0x1UL << DCMI_CR_ENABLE_Pos) /*!< 0x00004000 */
5998 #define DCMI_CR_ENABLE DCMI_CR_ENABLE_Msk
5999 #define DCMI_CR_BSM_Pos (16U)
6000 #define DCMI_CR_BSM_Msk (0x3UL << DCMI_CR_BSM_Pos) /*!< 0x00030000 */
6001 #define DCMI_CR_BSM DCMI_CR_BSM_Msk
6002 #define DCMI_CR_BSM_0 (0x1UL << DCMI_CR_BSM_Pos) /*!< 0x00010000 */
6003 #define DCMI_CR_BSM_1 (0x2UL << DCMI_CR_BSM_Pos) /*!< 0x00020000 */
6004 #define DCMI_CR_OEBS_Pos (18U)
6005 #define DCMI_CR_OEBS_Msk (0x1UL << DCMI_CR_OEBS_Pos) /*!< 0x00040000 */
6006 #define DCMI_CR_OEBS DCMI_CR_OEBS_Msk
6007 #define DCMI_CR_LSM_Pos (19U)
6008 #define DCMI_CR_LSM_Msk (0x1UL << DCMI_CR_LSM_Pos) /*!< 0x00080000 */
6009 #define DCMI_CR_LSM DCMI_CR_LSM_Msk
6010 #define DCMI_CR_OELS_Pos (20U)
6011 #define DCMI_CR_OELS_Msk (0x1UL << DCMI_CR_OELS_Pos) /*!< 0x00100000 */
6012 #define DCMI_CR_OELS DCMI_CR_OELS_Msk
6013
6014 /******************** Bits definition for DCMI_SR register ******************/
6015 #define DCMI_SR_HSYNC_Pos (0U)
6016 #define DCMI_SR_HSYNC_Msk (0x1UL << DCMI_SR_HSYNC_Pos) /*!< 0x00000001 */
6017 #define DCMI_SR_HSYNC DCMI_SR_HSYNC_Msk
6018 #define DCMI_SR_VSYNC_Pos (1U)
6019 #define DCMI_SR_VSYNC_Msk (0x1UL << DCMI_SR_VSYNC_Pos) /*!< 0x00000002 */
6020 #define DCMI_SR_VSYNC DCMI_SR_VSYNC_Msk
6021 #define DCMI_SR_FNE_Pos (2U)
6022 #define DCMI_SR_FNE_Msk (0x1UL << DCMI_SR_FNE_Pos) /*!< 0x00000004 */
6023 #define DCMI_SR_FNE DCMI_SR_FNE_Msk
6024
6025 /******************** Bits definition for DCMI_RIS register ****************/
6026 #define DCMI_RIS_FRAME_RIS_Pos (0U)
6027 #define DCMI_RIS_FRAME_RIS_Msk (0x1UL << DCMI_RIS_FRAME_RIS_Pos) /*!< 0x00000001 */
6028 #define DCMI_RIS_FRAME_RIS DCMI_RIS_FRAME_RIS_Msk
6029 #define DCMI_RIS_OVR_RIS_Pos (1U)
6030 #define DCMI_RIS_OVR_RIS_Msk (0x1UL << DCMI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
6031 #define DCMI_RIS_OVR_RIS DCMI_RIS_OVR_RIS_Msk
6032 #define DCMI_RIS_ERR_RIS_Pos (2U)
6033 #define DCMI_RIS_ERR_RIS_Msk (0x1UL << DCMI_RIS_ERR_RIS_Pos) /*!< 0x00000004 */
6034 #define DCMI_RIS_ERR_RIS DCMI_RIS_ERR_RIS_Msk
6035 #define DCMI_RIS_VSYNC_RIS_Pos (3U)
6036 #define DCMI_RIS_VSYNC_RIS_Msk (0x1UL << DCMI_RIS_VSYNC_RIS_Pos) /*!< 0x00000008 */
6037 #define DCMI_RIS_VSYNC_RIS DCMI_RIS_VSYNC_RIS_Msk
6038 #define DCMI_RIS_LINE_RIS_Pos (4U)
6039 #define DCMI_RIS_LINE_RIS_Msk (0x1UL << DCMI_RIS_LINE_RIS_Pos) /*!< 0x00000010 */
6040 #define DCMI_RIS_LINE_RIS DCMI_RIS_LINE_RIS_Msk
6041
6042 /******************** Bits definition for DCMI_IER register *****************/
6043 #define DCMI_IER_FRAME_IE_Pos (0U)
6044 #define DCMI_IER_FRAME_IE_Msk (0x1UL << DCMI_IER_FRAME_IE_Pos) /*!< 0x00000001 */
6045 #define DCMI_IER_FRAME_IE DCMI_IER_FRAME_IE_Msk
6046 #define DCMI_IER_OVR_IE_Pos (1U)
6047 #define DCMI_IER_OVR_IE_Msk (0x1UL << DCMI_IER_OVR_IE_Pos) /*!< 0x00000002 */
6048 #define DCMI_IER_OVR_IE DCMI_IER_OVR_IE_Msk
6049 #define DCMI_IER_ERR_IE_Pos (2U)
6050 #define DCMI_IER_ERR_IE_Msk (0x1UL << DCMI_IER_ERR_IE_Pos) /*!< 0x00000004 */
6051 #define DCMI_IER_ERR_IE DCMI_IER_ERR_IE_Msk
6052 #define DCMI_IER_VSYNC_IE_Pos (3U)
6053 #define DCMI_IER_VSYNC_IE_Msk (0x1UL << DCMI_IER_VSYNC_IE_Pos) /*!< 0x00000008 */
6054 #define DCMI_IER_VSYNC_IE DCMI_IER_VSYNC_IE_Msk
6055 #define DCMI_IER_LINE_IE_Pos (4U)
6056 #define DCMI_IER_LINE_IE_Msk (0x1UL << DCMI_IER_LINE_IE_Pos) /*!< 0x00000010 */
6057 #define DCMI_IER_LINE_IE DCMI_IER_LINE_IE_Msk
6058
6059
6060 /******************** Bits definition for DCMI_MIS register *****************/
6061 #define DCMI_MIS_FRAME_MIS_Pos (0U)
6062 #define DCMI_MIS_FRAME_MIS_Msk (0x1UL << DCMI_MIS_FRAME_MIS_Pos) /*!< 0x00000001 */
6063 #define DCMI_MIS_FRAME_MIS DCMI_MIS_FRAME_MIS_Msk
6064 #define DCMI_MIS_OVR_MIS_Pos (1U)
6065 #define DCMI_MIS_OVR_MIS_Msk (0x1UL << DCMI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
6066 #define DCMI_MIS_OVR_MIS DCMI_MIS_OVR_MIS_Msk
6067 #define DCMI_MIS_ERR_MIS_Pos (2U)
6068 #define DCMI_MIS_ERR_MIS_Msk (0x1UL << DCMI_MIS_ERR_MIS_Pos) /*!< 0x00000004 */
6069 #define DCMI_MIS_ERR_MIS DCMI_MIS_ERR_MIS_Msk
6070 #define DCMI_MIS_VSYNC_MIS_Pos (3U)
6071 #define DCMI_MIS_VSYNC_MIS_Msk (0x1UL << DCMI_MIS_VSYNC_MIS_Pos) /*!< 0x00000008 */
6072 #define DCMI_MIS_VSYNC_MIS DCMI_MIS_VSYNC_MIS_Msk
6073 #define DCMI_MIS_LINE_MIS_Pos (4U)
6074 #define DCMI_MIS_LINE_MIS_Msk (0x1UL << DCMI_MIS_LINE_MIS_Pos) /*!< 0x00000010 */
6075 #define DCMI_MIS_LINE_MIS DCMI_MIS_LINE_MIS_Msk
6076
6077
6078 /******************** Bits definition for DCMI_ICR register *****************/
6079 #define DCMI_ICR_FRAME_ISC_Pos (0U)
6080 #define DCMI_ICR_FRAME_ISC_Msk (0x1UL << DCMI_ICR_FRAME_ISC_Pos) /*!< 0x00000001 */
6081 #define DCMI_ICR_FRAME_ISC DCMI_ICR_FRAME_ISC_Msk
6082 #define DCMI_ICR_OVR_ISC_Pos (1U)
6083 #define DCMI_ICR_OVR_ISC_Msk (0x1UL << DCMI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
6084 #define DCMI_ICR_OVR_ISC DCMI_ICR_OVR_ISC_Msk
6085 #define DCMI_ICR_ERR_ISC_Pos (2U)
6086 #define DCMI_ICR_ERR_ISC_Msk (0x1UL << DCMI_ICR_ERR_ISC_Pos) /*!< 0x00000004 */
6087 #define DCMI_ICR_ERR_ISC DCMI_ICR_ERR_ISC_Msk
6088 #define DCMI_ICR_VSYNC_ISC_Pos (3U)
6089 #define DCMI_ICR_VSYNC_ISC_Msk (0x1UL << DCMI_ICR_VSYNC_ISC_Pos) /*!< 0x00000008 */
6090 #define DCMI_ICR_VSYNC_ISC DCMI_ICR_VSYNC_ISC_Msk
6091 #define DCMI_ICR_LINE_ISC_Pos (4U)
6092 #define DCMI_ICR_LINE_ISC_Msk (0x1UL << DCMI_ICR_LINE_ISC_Pos) /*!< 0x00000010 */
6093 #define DCMI_ICR_LINE_ISC DCMI_ICR_LINE_ISC_Msk
6094
6095
6096 /******************** Bits definition for DCMI_ESCR register ******************/
6097 #define DCMI_ESCR_FSC_Pos (0U)
6098 #define DCMI_ESCR_FSC_Msk (0xFFUL << DCMI_ESCR_FSC_Pos) /*!< 0x000000FF */
6099 #define DCMI_ESCR_FSC DCMI_ESCR_FSC_Msk
6100 #define DCMI_ESCR_LSC_Pos (8U)
6101 #define DCMI_ESCR_LSC_Msk (0xFFUL << DCMI_ESCR_LSC_Pos) /*!< 0x0000FF00 */
6102 #define DCMI_ESCR_LSC DCMI_ESCR_LSC_Msk
6103 #define DCMI_ESCR_LEC_Pos (16U)
6104 #define DCMI_ESCR_LEC_Msk (0xFFUL << DCMI_ESCR_LEC_Pos) /*!< 0x00FF0000 */
6105 #define DCMI_ESCR_LEC DCMI_ESCR_LEC_Msk
6106 #define DCMI_ESCR_FEC_Pos (24U)
6107 #define DCMI_ESCR_FEC_Msk (0xFFUL << DCMI_ESCR_FEC_Pos) /*!< 0xFF000000 */
6108 #define DCMI_ESCR_FEC DCMI_ESCR_FEC_Msk
6109
6110 /******************** Bits definition for DCMI_ESUR register ******************/
6111 #define DCMI_ESUR_FSU_Pos (0U)
6112 #define DCMI_ESUR_FSU_Msk (0xFFUL << DCMI_ESUR_FSU_Pos) /*!< 0x000000FF */
6113 #define DCMI_ESUR_FSU DCMI_ESUR_FSU_Msk
6114 #define DCMI_ESUR_LSU_Pos (8U)
6115 #define DCMI_ESUR_LSU_Msk (0xFFUL << DCMI_ESUR_LSU_Pos) /*!< 0x0000FF00 */
6116 #define DCMI_ESUR_LSU DCMI_ESUR_LSU_Msk
6117 #define DCMI_ESUR_LEU_Pos (16U)
6118 #define DCMI_ESUR_LEU_Msk (0xFFUL << DCMI_ESUR_LEU_Pos) /*!< 0x00FF0000 */
6119 #define DCMI_ESUR_LEU DCMI_ESUR_LEU_Msk
6120 #define DCMI_ESUR_FEU_Pos (24U)
6121 #define DCMI_ESUR_FEU_Msk (0xFFUL << DCMI_ESUR_FEU_Pos) /*!< 0xFF000000 */
6122 #define DCMI_ESUR_FEU DCMI_ESUR_FEU_Msk
6123
6124 /******************** Bits definition for DCMI_CWSTRT register ******************/
6125 #define DCMI_CWSTRT_HOFFCNT_Pos (0U)
6126 #define DCMI_CWSTRT_HOFFCNT_Msk (0x3FFFUL << DCMI_CWSTRT_HOFFCNT_Pos) /*!< 0x00003FFF */
6127 #define DCMI_CWSTRT_HOFFCNT DCMI_CWSTRT_HOFFCNT_Msk
6128 #define DCMI_CWSTRT_VST_Pos (16U)
6129 #define DCMI_CWSTRT_VST_Msk (0x1FFFUL << DCMI_CWSTRT_VST_Pos) /*!< 0x1FFF0000 */
6130 #define DCMI_CWSTRT_VST DCMI_CWSTRT_VST_Msk
6131
6132 /******************** Bits definition for DCMI_CWSIZE register ******************/
6133 #define DCMI_CWSIZE_CAPCNT_Pos (0U)
6134 #define DCMI_CWSIZE_CAPCNT_Msk (0x3FFFUL << DCMI_CWSIZE_CAPCNT_Pos) /*!< 0x00003FFF */
6135 #define DCMI_CWSIZE_CAPCNT DCMI_CWSIZE_CAPCNT_Msk
6136 #define DCMI_CWSIZE_VLINE_Pos (16U)
6137 #define DCMI_CWSIZE_VLINE_Msk (0x3FFFUL << DCMI_CWSIZE_VLINE_Pos) /*!< 0x3FFF0000 */
6138 #define DCMI_CWSIZE_VLINE DCMI_CWSIZE_VLINE_Msk
6139
6140 /******************** Bits definition for DCMI_DR register ******************/
6141 #define DCMI_DR_BYTE0_Pos (0U)
6142 #define DCMI_DR_BYTE0_Msk (0xFFUL << DCMI_DR_BYTE0_Pos) /*!< 0x000000FF */
6143 #define DCMI_DR_BYTE0 DCMI_DR_BYTE0_Msk
6144 #define DCMI_DR_BYTE1_Pos (8U)
6145 #define DCMI_DR_BYTE1_Msk (0xFFUL << DCMI_DR_BYTE1_Pos) /*!< 0x0000FF00 */
6146 #define DCMI_DR_BYTE1 DCMI_DR_BYTE1_Msk
6147 #define DCMI_DR_BYTE2_Pos (16U)
6148 #define DCMI_DR_BYTE2_Msk (0xFFUL << DCMI_DR_BYTE2_Pos) /*!< 0x00FF0000 */
6149 #define DCMI_DR_BYTE2 DCMI_DR_BYTE2_Msk
6150 #define DCMI_DR_BYTE3_Pos (24U)
6151 #define DCMI_DR_BYTE3_Msk (0xFFUL << DCMI_DR_BYTE3_Pos) /*!< 0xFF000000 */
6152 #define DCMI_DR_BYTE3 DCMI_DR_BYTE3_Msk
6153
6154 /******************************************************************************/
6155 /* */
6156 /* Digital Filter for Sigma Delta Modulators */
6157 /* */
6158 /******************************************************************************/
6159
6160 /**************** DFSDM channel configuration registers ********************/
6161
6162 /*************** Bit definition for DFSDM_CHCFGR1 register ******************/
6163 #define DFSDM_CHCFGR1_DFSDMEN_Pos (31U)
6164 #define DFSDM_CHCFGR1_DFSDMEN_Msk (0x1UL << DFSDM_CHCFGR1_DFSDMEN_Pos) /*!< 0x80000000 */
6165 #define DFSDM_CHCFGR1_DFSDMEN DFSDM_CHCFGR1_DFSDMEN_Msk /*!< Global enable for DFSDM interface */
6166 #define DFSDM_CHCFGR1_CKOUTSRC_Pos (30U)
6167 #define DFSDM_CHCFGR1_CKOUTSRC_Msk (0x1UL << DFSDM_CHCFGR1_CKOUTSRC_Pos) /*!< 0x40000000 */
6168 #define DFSDM_CHCFGR1_CKOUTSRC DFSDM_CHCFGR1_CKOUTSRC_Msk /*!< Output serial clock source selection */
6169 #define DFSDM_CHCFGR1_CKOUTDIV_Pos (16U)
6170 #define DFSDM_CHCFGR1_CKOUTDIV_Msk (0xFFUL << DFSDM_CHCFGR1_CKOUTDIV_Pos) /*!< 0x00FF0000 */
6171 #define DFSDM_CHCFGR1_CKOUTDIV DFSDM_CHCFGR1_CKOUTDIV_Msk /*!< CKOUTDIV[7:0] output serial clock divider */
6172 #define DFSDM_CHCFGR1_DATPACK_Pos (14U)
6173 #define DFSDM_CHCFGR1_DATPACK_Msk (0x3UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x0000C000 */
6174 #define DFSDM_CHCFGR1_DATPACK DFSDM_CHCFGR1_DATPACK_Msk /*!< DATPACK[1:0] Data packing mode */
6175 #define DFSDM_CHCFGR1_DATPACK_1 (0x2UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00008000 */
6176 #define DFSDM_CHCFGR1_DATPACK_0 (0x1UL << DFSDM_CHCFGR1_DATPACK_Pos) /*!< 0x00004000 */
6177 #define DFSDM_CHCFGR1_DATMPX_Pos (12U)
6178 #define DFSDM_CHCFGR1_DATMPX_Msk (0x3UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00003000 */
6179 #define DFSDM_CHCFGR1_DATMPX DFSDM_CHCFGR1_DATMPX_Msk /*!< DATMPX[1:0] Input data multiplexer for channel y */
6180 #define DFSDM_CHCFGR1_DATMPX_1 (0x2UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00002000 */
6181 #define DFSDM_CHCFGR1_DATMPX_0 (0x1UL << DFSDM_CHCFGR1_DATMPX_Pos) /*!< 0x00001000 */
6182 #define DFSDM_CHCFGR1_CHINSEL_Pos (8U)
6183 #define DFSDM_CHCFGR1_CHINSEL_Msk (0x1UL << DFSDM_CHCFGR1_CHINSEL_Pos) /*!< 0x00000100 */
6184 #define DFSDM_CHCFGR1_CHINSEL DFSDM_CHCFGR1_CHINSEL_Msk /*!< Serial inputs selection for channel y */
6185 #define DFSDM_CHCFGR1_CHEN_Pos (7U)
6186 #define DFSDM_CHCFGR1_CHEN_Msk (0x1UL << DFSDM_CHCFGR1_CHEN_Pos) /*!< 0x00000080 */
6187 #define DFSDM_CHCFGR1_CHEN DFSDM_CHCFGR1_CHEN_Msk /*!< Channel y enable */
6188 #define DFSDM_CHCFGR1_CKABEN_Pos (6U)
6189 #define DFSDM_CHCFGR1_CKABEN_Msk (0x1UL << DFSDM_CHCFGR1_CKABEN_Pos) /*!< 0x00000040 */
6190 #define DFSDM_CHCFGR1_CKABEN DFSDM_CHCFGR1_CKABEN_Msk /*!< Clock absence detector enable on channel y */
6191 #define DFSDM_CHCFGR1_SCDEN_Pos (5U)
6192 #define DFSDM_CHCFGR1_SCDEN_Msk (0x1UL << DFSDM_CHCFGR1_SCDEN_Pos) /*!< 0x00000020 */
6193 #define DFSDM_CHCFGR1_SCDEN DFSDM_CHCFGR1_SCDEN_Msk /*!< Short circuit detector enable on channel y */
6194 #define DFSDM_CHCFGR1_SPICKSEL_Pos (2U)
6195 #define DFSDM_CHCFGR1_SPICKSEL_Msk (0x3UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x0000000C */
6196 #define DFSDM_CHCFGR1_SPICKSEL DFSDM_CHCFGR1_SPICKSEL_Msk /*!< SPICKSEL[1:0] SPI clock select for channel y */
6197 #define DFSDM_CHCFGR1_SPICKSEL_1 (0x2UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000008 */
6198 #define DFSDM_CHCFGR1_SPICKSEL_0 (0x1UL << DFSDM_CHCFGR1_SPICKSEL_Pos) /*!< 0x00000004 */
6199 #define DFSDM_CHCFGR1_SITP_Pos (0U)
6200 #define DFSDM_CHCFGR1_SITP_Msk (0x3UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000003 */
6201 #define DFSDM_CHCFGR1_SITP DFSDM_CHCFGR1_SITP_Msk /*!< SITP[1:0] Serial interface type for channel y */
6202 #define DFSDM_CHCFGR1_SITP_1 (0x2UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000002 */
6203 #define DFSDM_CHCFGR1_SITP_0 (0x1UL << DFSDM_CHCFGR1_SITP_Pos) /*!< 0x00000001 */
6204
6205 /*************** Bit definition for DFSDM_CHCFGR2 register ******************/
6206 #define DFSDM_CHCFGR2_OFFSET_Pos (8U)
6207 #define DFSDM_CHCFGR2_OFFSET_Msk (0xFFFFFFUL << DFSDM_CHCFGR2_OFFSET_Pos) /*!< 0xFFFFFF00 */
6208 #define DFSDM_CHCFGR2_OFFSET DFSDM_CHCFGR2_OFFSET_Msk /*!< OFFSET[23:0] 24-bit calibration offset for channel y */
6209 #define DFSDM_CHCFGR2_DTRBS_Pos (3U)
6210 #define DFSDM_CHCFGR2_DTRBS_Msk (0x1FUL << DFSDM_CHCFGR2_DTRBS_Pos) /*!< 0x000000F8 */
6211 #define DFSDM_CHCFGR2_DTRBS DFSDM_CHCFGR2_DTRBS_Msk /*!< DTRBS[4:0] Data right bit-shift for channel y */
6212
6213 /****************** Bit definition for DFSDM_CHAWSCDR register *****************/
6214 #define DFSDM_CHAWSCDR_AWFORD_Pos (22U)
6215 #define DFSDM_CHAWSCDR_AWFORD_Msk (0x3UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00C00000 */
6216 #define DFSDM_CHAWSCDR_AWFORD DFSDM_CHAWSCDR_AWFORD_Msk /*!< AWFORD[1:0] Analog watchdog Sinc filter order on channel y */
6217 #define DFSDM_CHAWSCDR_AWFORD_1 (0x2UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00800000 */
6218 #define DFSDM_CHAWSCDR_AWFORD_0 (0x1UL << DFSDM_CHAWSCDR_AWFORD_Pos) /*!< 0x00400000 */
6219 #define DFSDM_CHAWSCDR_AWFOSR_Pos (16U)
6220 #define DFSDM_CHAWSCDR_AWFOSR_Msk (0x1FUL << DFSDM_CHAWSCDR_AWFOSR_Pos) /*!< 0x001F0000 */
6221 #define DFSDM_CHAWSCDR_AWFOSR DFSDM_CHAWSCDR_AWFOSR_Msk /*!< AWFOSR[4:0] Analog watchdog filter oversampling ratio on channel y */
6222 #define DFSDM_CHAWSCDR_BKSCD_Pos (12U)
6223 #define DFSDM_CHAWSCDR_BKSCD_Msk (0xFUL << DFSDM_CHAWSCDR_BKSCD_Pos) /*!< 0x0000F000 */
6224 #define DFSDM_CHAWSCDR_BKSCD DFSDM_CHAWSCDR_BKSCD_Msk /*!< BKSCD[3:0] Break signal assignment for short circuit detector on channel y */
6225 #define DFSDM_CHAWSCDR_SCDT_Pos (0U)
6226 #define DFSDM_CHAWSCDR_SCDT_Msk (0xFFUL << DFSDM_CHAWSCDR_SCDT_Pos) /*!< 0x000000FF */
6227 #define DFSDM_CHAWSCDR_SCDT DFSDM_CHAWSCDR_SCDT_Msk /*!< SCDT[7:0] Short circuit detector threshold for channel y */
6228
6229 /**************** Bit definition for DFSDM_CHWDATR register *******************/
6230 #define DFSDM_CHWDATR_WDATA_Pos (0U)
6231 #define DFSDM_CHWDATR_WDATA_Msk (0xFFFFUL << DFSDM_CHWDATR_WDATA_Pos) /*!< 0x0000FFFF */
6232 #define DFSDM_CHWDATR_WDATA DFSDM_CHWDATR_WDATA_Msk /*!< WDATA[15:0] Input channel y watchdog data */
6233
6234 /**************** Bit definition for DFSDM_CHDATINR register *****************/
6235 #define DFSDM_CHDATINR_INDAT0_Pos (0U)
6236 #define DFSDM_CHDATINR_INDAT0_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT0_Pos) /*!< 0x0000FFFF */
6237 #define DFSDM_CHDATINR_INDAT0 DFSDM_CHDATINR_INDAT0_Msk /*!< INDAT0[31:16] Input data for channel y or channel (y+1) */
6238 #define DFSDM_CHDATINR_INDAT1_Pos (16U)
6239 #define DFSDM_CHDATINR_INDAT1_Msk (0xFFFFUL << DFSDM_CHDATINR_INDAT1_Pos) /*!< 0xFFFF0000 */
6240 #define DFSDM_CHDATINR_INDAT1 DFSDM_CHDATINR_INDAT1_Msk /*!< INDAT0[15:0] Input data for channel y */
6241
6242 /**************** Bit definition for DFSDM_CHDLYR register *****************/
6243 #define DFSDM_CHDLYR_PLSSKP_Pos (0U)
6244 #define DFSDM_CHDLYR_PLSSKP_Msk (0x3FUL << DFSDM_CHDLYR_PLSSKP_Pos) /*!< 0x0000003F*/
6245 #define DFSDM_CHDLYR_PLSSKP DFSDM_CHDLYR_PLSSKP_Msk
6246 /************************ DFSDM module registers ****************************/
6247
6248 /******************** Bit definition for DFSDM_FLTCR1 register *******************/
6249 #define DFSDM_FLTCR1_AWFSEL_Pos (30U)
6250 #define DFSDM_FLTCR1_AWFSEL_Msk (0x1UL << DFSDM_FLTCR1_AWFSEL_Pos) /*!< 0x40000000 */
6251 #define DFSDM_FLTCR1_AWFSEL DFSDM_FLTCR1_AWFSEL_Msk /*!< Analog watchdog fast mode select */
6252 #define DFSDM_FLTCR1_FAST_Pos (29U)
6253 #define DFSDM_FLTCR1_FAST_Msk (0x1UL << DFSDM_FLTCR1_FAST_Pos) /*!< 0x20000000 */
6254 #define DFSDM_FLTCR1_FAST DFSDM_FLTCR1_FAST_Msk /*!< Fast conversion mode selection */
6255 #define DFSDM_FLTCR1_RCH_Pos (24U)
6256 #define DFSDM_FLTCR1_RCH_Msk (0x7UL << DFSDM_FLTCR1_RCH_Pos) /*!< 0x07000000 */
6257 #define DFSDM_FLTCR1_RCH DFSDM_FLTCR1_RCH_Msk /*!< RCH[2:0] Regular channel selection */
6258 #define DFSDM_FLTCR1_RDMAEN_Pos (21U)
6259 #define DFSDM_FLTCR1_RDMAEN_Msk (0x1UL << DFSDM_FLTCR1_RDMAEN_Pos) /*!< 0x00200000 */
6260 #define DFSDM_FLTCR1_RDMAEN DFSDM_FLTCR1_RDMAEN_Msk /*!< DMA channel enabled to read data for the regular conversion */
6261 #define DFSDM_FLTCR1_RSYNC_Pos (19U)
6262 #define DFSDM_FLTCR1_RSYNC_Msk (0x1UL << DFSDM_FLTCR1_RSYNC_Pos) /*!< 0x00080000 */
6263 #define DFSDM_FLTCR1_RSYNC DFSDM_FLTCR1_RSYNC_Msk /*!< Launch regular conversion synchronously with DFSDMx */
6264 #define DFSDM_FLTCR1_RCONT_Pos (18U)
6265 #define DFSDM_FLTCR1_RCONT_Msk (0x1UL << DFSDM_FLTCR1_RCONT_Pos) /*!< 0x00040000 */
6266 #define DFSDM_FLTCR1_RCONT DFSDM_FLTCR1_RCONT_Msk /*!< Continuous mode selection for regular conversions */
6267 #define DFSDM_FLTCR1_RSWSTART_Pos (17U)
6268 #define DFSDM_FLTCR1_RSWSTART_Msk (0x1UL << DFSDM_FLTCR1_RSWSTART_Pos) /*!< 0x00020000 */
6269 #define DFSDM_FLTCR1_RSWSTART DFSDM_FLTCR1_RSWSTART_Msk /*!< Software start of a conversion on the regular channel */
6270 #define DFSDM_FLTCR1_JEXTEN_Pos (13U)
6271 #define DFSDM_FLTCR1_JEXTEN_Msk (0x3UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00006000 */
6272 #define DFSDM_FLTCR1_JEXTEN DFSDM_FLTCR1_JEXTEN_Msk /*!< JEXTEN[1:0] Trigger enable and trigger edge selection for injected conversions */
6273 #define DFSDM_FLTCR1_JEXTEN_1 (0x2UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00004000 */
6274 #define DFSDM_FLTCR1_JEXTEN_0 (0x1UL << DFSDM_FLTCR1_JEXTEN_Pos) /*!< 0x00002000 */
6275 #define DFSDM_FLTCR1_JEXTSEL_Pos (8U)
6276 #define DFSDM_FLTCR1_JEXTSEL_Msk (0x1FUL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001F00 */
6277 #define DFSDM_FLTCR1_JEXTSEL DFSDM_FLTCR1_JEXTSEL_Msk /*!< JEXTSEL[4:0]Trigger signal selection for launching injected conversions */
6278 #define DFSDM_FLTCR1_JEXTSEL_0 (0x01UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000100 */
6279 #define DFSDM_FLTCR1_JEXTSEL_1 (0x02UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000200 */
6280 #define DFSDM_FLTCR1_JEXTSEL_2 (0x04UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000400 */
6281 #define DFSDM_FLTCR1_JEXTSEL_3 (0x08UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00000800 */
6282 #define DFSDM_FLTCR1_JEXTSEL_4 (0x10UL << DFSDM_FLTCR1_JEXTSEL_Pos) /*!< 0x00001000 */
6283
6284 #define DFSDM_FLTCR1_JDMAEN_Pos (5U)
6285 #define DFSDM_FLTCR1_JDMAEN_Msk (0x1UL << DFSDM_FLTCR1_JDMAEN_Pos) /*!< 0x00000020 */
6286 #define DFSDM_FLTCR1_JDMAEN DFSDM_FLTCR1_JDMAEN_Msk /*!< DMA channel enabled to read data for the injected channel group */
6287 #define DFSDM_FLTCR1_JSCAN_Pos (4U)
6288 #define DFSDM_FLTCR1_JSCAN_Msk (0x1UL << DFSDM_FLTCR1_JSCAN_Pos) /*!< 0x00000010 */
6289 #define DFSDM_FLTCR1_JSCAN DFSDM_FLTCR1_JSCAN_Msk /*!< Scanning conversion in continuous mode selection for injected conversions */
6290 #define DFSDM_FLTCR1_JSYNC_Pos (3U)
6291 #define DFSDM_FLTCR1_JSYNC_Msk (0x1UL << DFSDM_FLTCR1_JSYNC_Pos) /*!< 0x00000008 */
6292 #define DFSDM_FLTCR1_JSYNC DFSDM_FLTCR1_JSYNC_Msk /*!< Launch an injected conversion synchronously with DFSDMx JSWSTART trigger */
6293 #define DFSDM_FLTCR1_JSWSTART_Pos (1U)
6294 #define DFSDM_FLTCR1_JSWSTART_Msk (0x1UL << DFSDM_FLTCR1_JSWSTART_Pos) /*!< 0x00000002 */
6295 #define DFSDM_FLTCR1_JSWSTART DFSDM_FLTCR1_JSWSTART_Msk /*!< Start the conversion of the injected group of channels */
6296 #define DFSDM_FLTCR1_DFEN_Pos (0U)
6297 #define DFSDM_FLTCR1_DFEN_Msk (0x1UL << DFSDM_FLTCR1_DFEN_Pos) /*!< 0x00000001 */
6298 #define DFSDM_FLTCR1_DFEN DFSDM_FLTCR1_DFEN_Msk /*!< DFSDM enable */
6299
6300 /******************** Bit definition for DFSDM_FLTCR2 register *******************/
6301 #define DFSDM_FLTCR2_AWDCH_Pos (16U)
6302 #define DFSDM_FLTCR2_AWDCH_Msk (0xFFUL << DFSDM_FLTCR2_AWDCH_Pos) /*!< 0x00FF0000 */
6303 #define DFSDM_FLTCR2_AWDCH DFSDM_FLTCR2_AWDCH_Msk /*!< AWDCH[7:0] Analog watchdog channel selection */
6304 #define DFSDM_FLTCR2_EXCH_Pos (8U)
6305 #define DFSDM_FLTCR2_EXCH_Msk (0xFFUL << DFSDM_FLTCR2_EXCH_Pos) /*!< 0x0000FF00 */
6306 #define DFSDM_FLTCR2_EXCH DFSDM_FLTCR2_EXCH_Msk /*!< EXCH[7:0] Extreme detector channel selection */
6307 #define DFSDM_FLTCR2_CKABIE_Pos (6U)
6308 #define DFSDM_FLTCR2_CKABIE_Msk (0x1UL << DFSDM_FLTCR2_CKABIE_Pos) /*!< 0x00000040 */
6309 #define DFSDM_FLTCR2_CKABIE DFSDM_FLTCR2_CKABIE_Msk /*!< Clock absence interrupt enable */
6310 #define DFSDM_FLTCR2_SCDIE_Pos (5U)
6311 #define DFSDM_FLTCR2_SCDIE_Msk (0x1UL << DFSDM_FLTCR2_SCDIE_Pos) /*!< 0x00000020 */
6312 #define DFSDM_FLTCR2_SCDIE DFSDM_FLTCR2_SCDIE_Msk /*!< Short circuit detector interrupt enable */
6313 #define DFSDM_FLTCR2_AWDIE_Pos (4U)
6314 #define DFSDM_FLTCR2_AWDIE_Msk (0x1UL << DFSDM_FLTCR2_AWDIE_Pos) /*!< 0x00000010 */
6315 #define DFSDM_FLTCR2_AWDIE DFSDM_FLTCR2_AWDIE_Msk /*!< Analog watchdog interrupt enable */
6316 #define DFSDM_FLTCR2_ROVRIE_Pos (3U)
6317 #define DFSDM_FLTCR2_ROVRIE_Msk (0x1UL << DFSDM_FLTCR2_ROVRIE_Pos) /*!< 0x00000008 */
6318 #define DFSDM_FLTCR2_ROVRIE DFSDM_FLTCR2_ROVRIE_Msk /*!< Regular data overrun interrupt enable */
6319 #define DFSDM_FLTCR2_JOVRIE_Pos (2U)
6320 #define DFSDM_FLTCR2_JOVRIE_Msk (0x1UL << DFSDM_FLTCR2_JOVRIE_Pos) /*!< 0x00000004 */
6321 #define DFSDM_FLTCR2_JOVRIE DFSDM_FLTCR2_JOVRIE_Msk /*!< Injected data overrun interrupt enable */
6322 #define DFSDM_FLTCR2_REOCIE_Pos (1U)
6323 #define DFSDM_FLTCR2_REOCIE_Msk (0x1UL << DFSDM_FLTCR2_REOCIE_Pos) /*!< 0x00000002 */
6324 #define DFSDM_FLTCR2_REOCIE DFSDM_FLTCR2_REOCIE_Msk /*!< Regular end of conversion interrupt enable */
6325 #define DFSDM_FLTCR2_JEOCIE_Pos (0U)
6326 #define DFSDM_FLTCR2_JEOCIE_Msk (0x1UL << DFSDM_FLTCR2_JEOCIE_Pos) /*!< 0x00000001 */
6327 #define DFSDM_FLTCR2_JEOCIE DFSDM_FLTCR2_JEOCIE_Msk /*!< Injected end of conversion interrupt enable */
6328
6329 /******************** Bit definition for DFSDM_FLTISR register *******************/
6330 #define DFSDM_FLTISR_SCDF_Pos (24U)
6331 #define DFSDM_FLTISR_SCDF_Msk (0xFFUL << DFSDM_FLTISR_SCDF_Pos) /*!< 0xFF000000 */
6332 #define DFSDM_FLTISR_SCDF DFSDM_FLTISR_SCDF_Msk /*!< SCDF[7:0] Short circuit detector flag */
6333 #define DFSDM_FLTISR_CKABF_Pos (16U)
6334 #define DFSDM_FLTISR_CKABF_Msk (0xFFUL << DFSDM_FLTISR_CKABF_Pos) /*!< 0x00FF0000 */
6335 #define DFSDM_FLTISR_CKABF DFSDM_FLTISR_CKABF_Msk /*!< CKABF[7:0] Clock absence flag */
6336 #define DFSDM_FLTISR_RCIP_Pos (14U)
6337 #define DFSDM_FLTISR_RCIP_Msk (0x1UL << DFSDM_FLTISR_RCIP_Pos) /*!< 0x00004000 */
6338 #define DFSDM_FLTISR_RCIP DFSDM_FLTISR_RCIP_Msk /*!< Regular conversion in progress status */
6339 #define DFSDM_FLTISR_JCIP_Pos (13U)
6340 #define DFSDM_FLTISR_JCIP_Msk (0x1UL << DFSDM_FLTISR_JCIP_Pos) /*!< 0x00002000 */
6341 #define DFSDM_FLTISR_JCIP DFSDM_FLTISR_JCIP_Msk /*!< Injected conversion in progress status */
6342 #define DFSDM_FLTISR_AWDF_Pos (4U)
6343 #define DFSDM_FLTISR_AWDF_Msk (0x1UL << DFSDM_FLTISR_AWDF_Pos) /*!< 0x00000010 */
6344 #define DFSDM_FLTISR_AWDF DFSDM_FLTISR_AWDF_Msk /*!< Analog watchdog */
6345 #define DFSDM_FLTISR_ROVRF_Pos (3U)
6346 #define DFSDM_FLTISR_ROVRF_Msk (0x1UL << DFSDM_FLTISR_ROVRF_Pos) /*!< 0x00000008 */
6347 #define DFSDM_FLTISR_ROVRF DFSDM_FLTISR_ROVRF_Msk /*!< Regular conversion overrun flag */
6348 #define DFSDM_FLTISR_JOVRF_Pos (2U)
6349 #define DFSDM_FLTISR_JOVRF_Msk (0x1UL << DFSDM_FLTISR_JOVRF_Pos) /*!< 0x00000004 */
6350 #define DFSDM_FLTISR_JOVRF DFSDM_FLTISR_JOVRF_Msk /*!< Injected conversion overrun flag */
6351 #define DFSDM_FLTISR_REOCF_Pos (1U)
6352 #define DFSDM_FLTISR_REOCF_Msk (0x1UL << DFSDM_FLTISR_REOCF_Pos) /*!< 0x00000002 */
6353 #define DFSDM_FLTISR_REOCF DFSDM_FLTISR_REOCF_Msk /*!< End of regular conversion flag */
6354 #define DFSDM_FLTISR_JEOCF_Pos (0U)
6355 #define DFSDM_FLTISR_JEOCF_Msk (0x1UL << DFSDM_FLTISR_JEOCF_Pos) /*!< 0x00000001 */
6356 #define DFSDM_FLTISR_JEOCF DFSDM_FLTISR_JEOCF_Msk /*!< End of injected conversion flag */
6357
6358 /******************** Bit definition for DFSDM_FLTICR register *******************/
6359 #define DFSDM_FLTICR_CLRSCDF_Pos (24U)
6360 #define DFSDM_FLTICR_CLRSCDF_Msk (0xFFUL << DFSDM_FLTICR_CLRSCDF_Pos) /*!< 0xFF000000 */
6361 #define DFSDM_FLTICR_CLRSCDF DFSDM_FLTICR_CLRSCDF_Msk /*!< CLRSCSDF[7:0] Clear the short circuit detector flag */
6362 #define DFSDM_FLTICR_CLRCKABF_Pos (16U)
6363 #define DFSDM_FLTICR_CLRCKABF_Msk (0xFFUL << DFSDM_FLTICR_CLRCKABF_Pos) /*!< 0x00FF0000 */
6364 #define DFSDM_FLTICR_CLRCKABF DFSDM_FLTICR_CLRCKABF_Msk /*!< CLRCKABF[7:0] Clear the clock absence flag */
6365 #define DFSDM_FLTICR_CLRROVRF_Pos (3U)
6366 #define DFSDM_FLTICR_CLRROVRF_Msk (0x1UL << DFSDM_FLTICR_CLRROVRF_Pos) /*!< 0x00000008 */
6367 #define DFSDM_FLTICR_CLRROVRF DFSDM_FLTICR_CLRROVRF_Msk /*!< Clear the regular conversion overrun flag */
6368 #define DFSDM_FLTICR_CLRJOVRF_Pos (2U)
6369 #define DFSDM_FLTICR_CLRJOVRF_Msk (0x1UL << DFSDM_FLTICR_CLRJOVRF_Pos) /*!< 0x00000004 */
6370 #define DFSDM_FLTICR_CLRJOVRF DFSDM_FLTICR_CLRJOVRF_Msk /*!< Clear the injected conversion overrun flag */
6371
6372 /******************* Bit definition for DFSDM_FLTJCHGR register ******************/
6373 #define DFSDM_FLTJCHGR_JCHG_Pos (0U)
6374 #define DFSDM_FLTJCHGR_JCHG_Msk (0xFFUL << DFSDM_FLTJCHGR_JCHG_Pos) /*!< 0x000000FF */
6375 #define DFSDM_FLTJCHGR_JCHG DFSDM_FLTJCHGR_JCHG_Msk /*!< JCHG[7:0] Injected channel group selection */
6376
6377 /******************** Bit definition for DFSDM_FLTFCR register *******************/
6378 #define DFSDM_FLTFCR_FORD_Pos (29U)
6379 #define DFSDM_FLTFCR_FORD_Msk (0x7UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0xE0000000 */
6380 #define DFSDM_FLTFCR_FORD DFSDM_FLTFCR_FORD_Msk /*!< FORD[2:0] Sinc filter order */
6381 #define DFSDM_FLTFCR_FORD_2 (0x4UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x80000000 */
6382 #define DFSDM_FLTFCR_FORD_1 (0x2UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x40000000 */
6383 #define DFSDM_FLTFCR_FORD_0 (0x1UL << DFSDM_FLTFCR_FORD_Pos) /*!< 0x20000000 */
6384 #define DFSDM_FLTFCR_FOSR_Pos (16U)
6385 #define DFSDM_FLTFCR_FOSR_Msk (0x3FFUL << DFSDM_FLTFCR_FOSR_Pos) /*!< 0x03FF0000 */
6386 #define DFSDM_FLTFCR_FOSR DFSDM_FLTFCR_FOSR_Msk /*!< FOSR[9:0] Sinc filter oversampling ratio (decimation rate) */
6387 #define DFSDM_FLTFCR_IOSR_Pos (0U)
6388 #define DFSDM_FLTFCR_IOSR_Msk (0xFFUL << DFSDM_FLTFCR_IOSR_Pos) /*!< 0x000000FF */
6389 #define DFSDM_FLTFCR_IOSR DFSDM_FLTFCR_IOSR_Msk /*!< IOSR[7:0] Integrator oversampling ratio (averaging length) */
6390
6391 /****************** Bit definition for DFSDM_FLTJDATAR register *****************/
6392 #define DFSDM_FLTJDATAR_JDATA_Pos (8U)
6393 #define DFSDM_FLTJDATAR_JDATA_Msk (0xFFFFFFUL << DFSDM_FLTJDATAR_JDATA_Pos) /*!< 0xFFFFFF00 */
6394 #define DFSDM_FLTJDATAR_JDATA DFSDM_FLTJDATAR_JDATA_Msk /*!< JDATA[23:0] Injected group conversion data */
6395 #define DFSDM_FLTJDATAR_JDATACH_Pos (0U)
6396 #define DFSDM_FLTJDATAR_JDATACH_Msk (0x7UL << DFSDM_FLTJDATAR_JDATACH_Pos) /*!< 0x00000007 */
6397 #define DFSDM_FLTJDATAR_JDATACH DFSDM_FLTJDATAR_JDATACH_Msk /*!< JDATACH[2:0] Injected channel most recently converted */
6398
6399 /****************** Bit definition for DFSDM_FLTRDATAR register *****************/
6400 #define DFSDM_FLTRDATAR_RDATA_Pos (8U)
6401 #define DFSDM_FLTRDATAR_RDATA_Msk (0xFFFFFFUL << DFSDM_FLTRDATAR_RDATA_Pos) /*!< 0xFFFFFF00 */
6402 #define DFSDM_FLTRDATAR_RDATA DFSDM_FLTRDATAR_RDATA_Msk /*!< RDATA[23:0] Regular channel conversion data */
6403 #define DFSDM_FLTRDATAR_RPEND_Pos (4U)
6404 #define DFSDM_FLTRDATAR_RPEND_Msk (0x1UL << DFSDM_FLTRDATAR_RPEND_Pos) /*!< 0x00000010 */
6405 #define DFSDM_FLTRDATAR_RPEND DFSDM_FLTRDATAR_RPEND_Msk /*!< RPEND Regular channel pending data */
6406 #define DFSDM_FLTRDATAR_RDATACH_Pos (0U)
6407 #define DFSDM_FLTRDATAR_RDATACH_Msk (0x7UL << DFSDM_FLTRDATAR_RDATACH_Pos) /*!< 0x00000007 */
6408 #define DFSDM_FLTRDATAR_RDATACH DFSDM_FLTRDATAR_RDATACH_Msk /*!< RDATACH[2:0] Regular channel most recently converted */
6409
6410 /****************** Bit definition for DFSDM_FLTAWHTR register ******************/
6411 #define DFSDM_FLTAWHTR_AWHT_Pos (8U)
6412 #define DFSDM_FLTAWHTR_AWHT_Msk (0xFFFFFFUL << DFSDM_FLTAWHTR_AWHT_Pos) /*!< 0xFFFFFF00 */
6413 #define DFSDM_FLTAWHTR_AWHT DFSDM_FLTAWHTR_AWHT_Msk /*!< AWHT[23:0] Analog watchdog high threshold */
6414 #define DFSDM_FLTAWHTR_BKAWH_Pos (0U)
6415 #define DFSDM_FLTAWHTR_BKAWH_Msk (0xFUL << DFSDM_FLTAWHTR_BKAWH_Pos) /*!< 0x0000000F */
6416 #define DFSDM_FLTAWHTR_BKAWH DFSDM_FLTAWHTR_BKAWH_Msk /*!< BKAWH[3:0] Break signal assignment to analog watchdog high threshold event */
6417
6418 /****************** Bit definition for DFSDM_FLTAWLTR register ******************/
6419 #define DFSDM_FLTAWLTR_AWLT_Pos (8U)
6420 #define DFSDM_FLTAWLTR_AWLT_Msk (0xFFFFFFUL << DFSDM_FLTAWLTR_AWLT_Pos) /*!< 0xFFFFFF00 */
6421 #define DFSDM_FLTAWLTR_AWLT DFSDM_FLTAWLTR_AWLT_Msk /*!< AWHT[23:0] Analog watchdog low threshold */
6422 #define DFSDM_FLTAWLTR_BKAWL_Pos (0U)
6423 #define DFSDM_FLTAWLTR_BKAWL_Msk (0xFUL << DFSDM_FLTAWLTR_BKAWL_Pos) /*!< 0x0000000F */
6424 #define DFSDM_FLTAWLTR_BKAWL DFSDM_FLTAWLTR_BKAWL_Msk /*!< BKAWL[3:0] Break signal assignment to analog watchdog low threshold event */
6425
6426 /****************** Bit definition for DFSDM_FLTAWSR register ******************/
6427 #define DFSDM_FLTAWSR_AWHTF_Pos (8U)
6428 #define DFSDM_FLTAWSR_AWHTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWHTF_Pos) /*!< 0x0000FF00 */
6429 #define DFSDM_FLTAWSR_AWHTF DFSDM_FLTAWSR_AWHTF_Msk /*!< AWHTF[15:8] Analog watchdog high threshold error on given channels */
6430 #define DFSDM_FLTAWSR_AWLTF_Pos (0U)
6431 #define DFSDM_FLTAWSR_AWLTF_Msk (0xFFUL << DFSDM_FLTAWSR_AWLTF_Pos) /*!< 0x000000FF */
6432 #define DFSDM_FLTAWSR_AWLTF DFSDM_FLTAWSR_AWLTF_Msk /*!< AWLTF[7:0] Analog watchdog low threshold error on given channels */
6433
6434 /****************** Bit definition for DFSDM_FLTAWCFR) register *****************/
6435 #define DFSDM_FLTAWCFR_CLRAWHTF_Pos (8U)
6436 #define DFSDM_FLTAWCFR_CLRAWHTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWHTF_Pos) /*!< 0x0000FF00 */
6437 #define DFSDM_FLTAWCFR_CLRAWHTF DFSDM_FLTAWCFR_CLRAWHTF_Msk /*!< CLRAWHTF[15:8] Clear the Analog watchdog high threshold flag */
6438 #define DFSDM_FLTAWCFR_CLRAWLTF_Pos (0U)
6439 #define DFSDM_FLTAWCFR_CLRAWLTF_Msk (0xFFUL << DFSDM_FLTAWCFR_CLRAWLTF_Pos) /*!< 0x000000FF */
6440 #define DFSDM_FLTAWCFR_CLRAWLTF DFSDM_FLTAWCFR_CLRAWLTF_Msk /*!< CLRAWLTF[7:0] Clear the Analog watchdog low threshold flag */
6441
6442 /****************** Bit definition for DFSDM_FLTEXMAX register ******************/
6443 #define DFSDM_FLTEXMAX_EXMAX_Pos (8U)
6444 #define DFSDM_FLTEXMAX_EXMAX_Msk (0xFFFFFFUL << DFSDM_FLTEXMAX_EXMAX_Pos) /*!< 0xFFFFFF00 */
6445 #define DFSDM_FLTEXMAX_EXMAX DFSDM_FLTEXMAX_EXMAX_Msk /*!< EXMAX[23:0] Extreme detector maximum value */
6446 #define DFSDM_FLTEXMAX_EXMAXCH_Pos (0U)
6447 #define DFSDM_FLTEXMAX_EXMAXCH_Msk (0x7UL << DFSDM_FLTEXMAX_EXMAXCH_Pos) /*!< 0x00000007 */
6448 #define DFSDM_FLTEXMAX_EXMAXCH DFSDM_FLTEXMAX_EXMAXCH_Msk /*!< EXMAXCH[2:0] Extreme detector maximum data channel */
6449
6450 /****************** Bit definition for DFSDM_FLTEXMIN register ******************/
6451 #define DFSDM_FLTEXMIN_EXMIN_Pos (8U)
6452 #define DFSDM_FLTEXMIN_EXMIN_Msk (0xFFFFFFUL << DFSDM_FLTEXMIN_EXMIN_Pos) /*!< 0xFFFFFF00 */
6453 #define DFSDM_FLTEXMIN_EXMIN DFSDM_FLTEXMIN_EXMIN_Msk /*!< EXMIN[23:0] Extreme detector minimum value */
6454 #define DFSDM_FLTEXMIN_EXMINCH_Pos (0U)
6455 #define DFSDM_FLTEXMIN_EXMINCH_Msk (0x7UL << DFSDM_FLTEXMIN_EXMINCH_Pos) /*!< 0x00000007 */
6456 #define DFSDM_FLTEXMIN_EXMINCH DFSDM_FLTEXMIN_EXMINCH_Msk /*!< EXMINCH[2:0] Extreme detector minimum data channel */
6457
6458 /****************** Bit definition for DFSDM_FLTCNVTIMR register ******************/
6459 #define DFSDM_FLTCNVTIMR_CNVCNT_Pos (4U)
6460 #define DFSDM_FLTCNVTIMR_CNVCNT_Msk (0xFFFFFFFUL << DFSDM_FLTCNVTIMR_CNVCNT_Pos) /*!< 0xFFFFFFF0 */
6461 #define DFSDM_FLTCNVTIMR_CNVCNT DFSDM_FLTCNVTIMR_CNVCNT_Msk /*!< CNVCNT[27:0]: 28-bit timer counting conversion time */
6462
6463 /******************************************************************************/
6464 /* */
6465 /* BDMA Controller */
6466 /* */
6467 /******************************************************************************/
6468
6469 /******************* Bit definition for BDMA_ISR register ********************/
6470 #define BDMA_ISR_GIF0_Pos (0U)
6471 #define BDMA_ISR_GIF0_Msk (0x1UL << BDMA_ISR_GIF0_Pos) /*!< 0x00000001 */
6472 #define BDMA_ISR_GIF0 BDMA_ISR_GIF0_Msk /*!< Channel 0 Global interrupt flag */
6473 #define BDMA_ISR_TCIF0_Pos (1U)
6474 #define BDMA_ISR_TCIF0_Msk (0x1UL << BDMA_ISR_TCIF0_Pos) /*!< 0x00000002 */
6475 #define BDMA_ISR_TCIF0 BDMA_ISR_TCIF0_Msk /*!< Channel 0 Transfer Complete flag */
6476 #define BDMA_ISR_HTIF0_Pos (2U)
6477 #define BDMA_ISR_HTIF0_Msk (0x1UL << BDMA_ISR_HTIF0_Pos) /*!< 0x00000004 */
6478 #define BDMA_ISR_HTIF0 BDMA_ISR_HTIF0_Msk /*!< Channel 0 Half Transfer flag */
6479 #define BDMA_ISR_TEIF0_Pos (3U)
6480 #define BDMA_ISR_TEIF0_Msk (0x1UL << BDMA_ISR_TEIF0_Pos) /*!< 0x00000008 */
6481 #define BDMA_ISR_TEIF0 BDMA_ISR_TEIF0_Msk /*!< Channel 0 Transfer Error flag */
6482 #define BDMA_ISR_GIF1_Pos (4U)
6483 #define BDMA_ISR_GIF1_Msk (0x1UL << BDMA_ISR_GIF1_Pos) /*!< 0x00000010 */
6484 #define BDMA_ISR_GIF1 BDMA_ISR_GIF1_Msk /*!< Channel 1 Global interrupt flag */
6485 #define BDMA_ISR_TCIF1_Pos (5U)
6486 #define BDMA_ISR_TCIF1_Msk (0x1UL << BDMA_ISR_TCIF1_Pos) /*!< 0x00000020 */
6487 #define BDMA_ISR_TCIF1 BDMA_ISR_TCIF1_Msk /*!< Channel 1 Transfer Complete flag */
6488 #define BDMA_ISR_HTIF1_Pos (6U)
6489 #define BDMA_ISR_HTIF1_Msk (0x1UL << BDMA_ISR_HTIF1_Pos) /*!< 0x00000040 */
6490 #define BDMA_ISR_HTIF1 BDMA_ISR_HTIF1_Msk /*!< Channel 1 Half Transfer flag */
6491 #define BDMA_ISR_TEIF1_Pos (7U)
6492 #define BDMA_ISR_TEIF1_Msk (0x1UL << BDMA_ISR_TEIF1_Pos) /*!< 0x00000080 */
6493 #define BDMA_ISR_TEIF1 BDMA_ISR_TEIF1_Msk /*!< Channel 1 Transfer Error flag */
6494 #define BDMA_ISR_GIF2_Pos (8U)
6495 #define BDMA_ISR_GIF2_Msk (0x1UL << BDMA_ISR_GIF2_Pos) /*!< 0x00000100 */
6496 #define BDMA_ISR_GIF2 BDMA_ISR_GIF2_Msk /*!< Channel 2 Global interrupt flag */
6497 #define BDMA_ISR_TCIF2_Pos (9U)
6498 #define BDMA_ISR_TCIF2_Msk (0x1UL << BDMA_ISR_TCIF2_Pos) /*!< 0x00000200 */
6499 #define BDMA_ISR_TCIF2 BDMA_ISR_TCIF2_Msk /*!< Channel 2 Transfer Complete flag */
6500 #define BDMA_ISR_HTIF2_Pos (10U)
6501 #define BDMA_ISR_HTIF2_Msk (0x1UL << BDMA_ISR_HTIF2_Pos) /*!< 0x00000400 */
6502 #define BDMA_ISR_HTIF2 BDMA_ISR_HTIF2_Msk /*!< Channel 2 Half Transfer flag */
6503 #define BDMA_ISR_TEIF2_Pos (11U)
6504 #define BDMA_ISR_TEIF2_Msk (0x1UL << BDMA_ISR_TEIF2_Pos) /*!< 0x00000800 */
6505 #define BDMA_ISR_TEIF2 BDMA_ISR_TEIF2_Msk /*!< Channel 2 Transfer Error flag */
6506 #define BDMA_ISR_GIF3_Pos (12U)
6507 #define BDMA_ISR_GIF3_Msk (0x1UL << BDMA_ISR_GIF3_Pos) /*!< 0x00001000 */
6508 #define BDMA_ISR_GIF3 BDMA_ISR_GIF3_Msk /*!< Channel 3 Global interrupt flag */
6509 #define BDMA_ISR_TCIF3_Pos (13U)
6510 #define BDMA_ISR_TCIF3_Msk (0x1UL << BDMA_ISR_TCIF3_Pos) /*!< 0x00002000 */
6511 #define BDMA_ISR_TCIF3 BDMA_ISR_TCIF3_Msk /*!< Channel 3 Transfer Complete flag */
6512 #define BDMA_ISR_HTIF3_Pos (14U)
6513 #define BDMA_ISR_HTIF3_Msk (0x1UL << BDMA_ISR_HTIF3_Pos) /*!< 0x00004000 */
6514 #define BDMA_ISR_HTIF3 BDMA_ISR_HTIF3_Msk /*!< Channel 3 Half Transfer flag */
6515 #define BDMA_ISR_TEIF3_Pos (15U)
6516 #define BDMA_ISR_TEIF3_Msk (0x1UL << BDMA_ISR_TEIF3_Pos) /*!< 0x00008000 */
6517 #define BDMA_ISR_TEIF3 BDMA_ISR_TEIF3_Msk /*!< Channel 3 Transfer Error flag */
6518 #define BDMA_ISR_GIF4_Pos (16U)
6519 #define BDMA_ISR_GIF4_Msk (0x1UL << BDMA_ISR_GIF4_Pos) /*!< 0x00010000 */
6520 #define BDMA_ISR_GIF4 BDMA_ISR_GIF4_Msk /*!< Channel 4 Global interrupt flag */
6521 #define BDMA_ISR_TCIF4_Pos (17U)
6522 #define BDMA_ISR_TCIF4_Msk (0x1UL << BDMA_ISR_TCIF4_Pos) /*!< 0x00020000 */
6523 #define BDMA_ISR_TCIF4 BDMA_ISR_TCIF4_Msk /*!< Channel 4 Transfer Complete flag */
6524 #define BDMA_ISR_HTIF4_Pos (18U)
6525 #define BDMA_ISR_HTIF4_Msk (0x1UL << BDMA_ISR_HTIF4_Pos) /*!< 0x00040000 */
6526 #define BDMA_ISR_HTIF4 BDMA_ISR_HTIF4_Msk /*!< Channel 4 Half Transfer flag */
6527 #define BDMA_ISR_TEIF4_Pos (19U)
6528 #define BDMA_ISR_TEIF4_Msk (0x1UL << BDMA_ISR_TEIF4_Pos) /*!< 0x00080000 */
6529 #define BDMA_ISR_TEIF4 BDMA_ISR_TEIF4_Msk /*!< Channel 4 Transfer Error flag */
6530 #define BDMA_ISR_GIF5_Pos (20U)
6531 #define BDMA_ISR_GIF5_Msk (0x1UL << BDMA_ISR_GIF5_Pos) /*!< 0x00100000 */
6532 #define BDMA_ISR_GIF5 BDMA_ISR_GIF5_Msk /*!< Channel 5 Global interrupt flag */
6533 #define BDMA_ISR_TCIF5_Pos (21U)
6534 #define BDMA_ISR_TCIF5_Msk (0x1UL << BDMA_ISR_TCIF5_Pos) /*!< 0x00200000 */
6535 #define BDMA_ISR_TCIF5 BDMA_ISR_TCIF5_Msk /*!< Channel 5 Transfer Complete flag */
6536 #define BDMA_ISR_HTIF5_Pos (22U)
6537 #define BDMA_ISR_HTIF5_Msk (0x1UL << BDMA_ISR_HTIF5_Pos) /*!< 0x00400000 */
6538 #define BDMA_ISR_HTIF5 BDMA_ISR_HTIF5_Msk /*!< Channel 5 Half Transfer flag */
6539 #define BDMA_ISR_TEIF5_Pos (23U)
6540 #define BDMA_ISR_TEIF5_Msk (0x1UL << BDMA_ISR_TEIF5_Pos) /*!< 0x00800000 */
6541 #define BDMA_ISR_TEIF5 BDMA_ISR_TEIF5_Msk /*!< Channel 5 Transfer Error flag */
6542 #define BDMA_ISR_GIF6_Pos (24U)
6543 #define BDMA_ISR_GIF6_Msk (0x1UL << BDMA_ISR_GIF6_Pos) /*!< 0x01000000 */
6544 #define BDMA_ISR_GIF6 BDMA_ISR_GIF6_Msk /*!< Channel 6 Global interrupt flag */
6545 #define BDMA_ISR_TCIF6_Pos (25U)
6546 #define BDMA_ISR_TCIF6_Msk (0x1UL << BDMA_ISR_TCIF6_Pos) /*!< 0x02000000 */
6547 #define BDMA_ISR_TCIF6 BDMA_ISR_TCIF6_Msk /*!< Channel 6 Transfer Complete flag */
6548 #define BDMA_ISR_HTIF6_Pos (26U)
6549 #define BDMA_ISR_HTIF6_Msk (0x1UL << BDMA_ISR_HTIF6_Pos) /*!< 0x04000000 */
6550 #define BDMA_ISR_HTIF6 BDMA_ISR_HTIF6_Msk /*!< Channel 6 Half Transfer flag */
6551 #define BDMA_ISR_TEIF6_Pos (27U)
6552 #define BDMA_ISR_TEIF6_Msk (0x1UL << BDMA_ISR_TEIF6_Pos) /*!< 0x08000000 */
6553 #define BDMA_ISR_TEIF6 BDMA_ISR_TEIF6_Msk /*!< Channel 6 Transfer Error flag */
6554 #define BDMA_ISR_GIF7_Pos (28U)
6555 #define BDMA_ISR_GIF7_Msk (0x1UL << BDMA_ISR_GIF7_Pos) /*!< 0x10000000 */
6556 #define BDMA_ISR_GIF7 BDMA_ISR_GIF7_Msk /*!< Channel 7 Global interrupt flag */
6557 #define BDMA_ISR_TCIF7_Pos (29U)
6558 #define BDMA_ISR_TCIF7_Msk (0x1UL << BDMA_ISR_TCIF7_Pos) /*!< 0x20000000 */
6559 #define BDMA_ISR_TCIF7 BDMA_ISR_TCIF7_Msk /*!< Channel 7 Transfer Complete flag */
6560 #define BDMA_ISR_HTIF7_Pos (30U)
6561 #define BDMA_ISR_HTIF7_Msk (0x1UL << BDMA_ISR_HTIF7_Pos) /*!< 0x40000000 */
6562 #define BDMA_ISR_HTIF7 BDMA_ISR_HTIF7_Msk /*!< Channel 7 Half Transfer flag */
6563 #define BDMA_ISR_TEIF7_Pos (31U)
6564 #define BDMA_ISR_TEIF7_Msk (0x1UL << BDMA_ISR_TEIF7_Pos) /*!< 0x80000000 */
6565 #define BDMA_ISR_TEIF7 BDMA_ISR_TEIF7_Msk /*!< Channel 7 Transfer Error flag */
6566
6567 /******************* Bit definition for BDMA_IFCR register *******************/
6568 #define BDMA_IFCR_CGIF0_Pos (0U)
6569 #define BDMA_IFCR_CGIF0_Msk (0x1UL << BDMA_IFCR_CGIF0_Pos) /*!< 0x00000001 */
6570 #define BDMA_IFCR_CGIF0 BDMA_IFCR_CGIF0_Msk /*!< Channel 0 Global interrupt clearr */
6571 #define BDMA_IFCR_CTCIF0_Pos (1U)
6572 #define BDMA_IFCR_CTCIF0_Msk (0x1UL << BDMA_IFCR_CTCIF0_Pos) /*!< 0x00000002 */
6573 #define BDMA_IFCR_CTCIF0 BDMA_IFCR_CTCIF0_Msk /*!< Channel 0 Transfer Complete clear */
6574 #define BDMA_IFCR_CHTIF0_Pos (2U)
6575 #define BDMA_IFCR_CHTIF0_Msk (0x1UL << BDMA_IFCR_CHTIF0_Pos) /*!< 0x00000004 */
6576 #define BDMA_IFCR_CHTIF0 BDMA_IFCR_CHTIF0_Msk /*!< Channel 0 Half Transfer clear */
6577 #define BDMA_IFCR_CTEIF0_Pos (3U)
6578 #define BDMA_IFCR_CTEIF0_Msk (0x1UL << BDMA_IFCR_CTEIF0_Pos) /*!< 0x00000008 */
6579 #define BDMA_IFCR_CTEIF0 BDMA_IFCR_CTEIF0_Msk /*!< Channel 0 Transfer Error clear */
6580 #define BDMA_IFCR_CGIF1_Pos (4U)
6581 #define BDMA_IFCR_CGIF1_Msk (0x1UL << BDMA_IFCR_CGIF1_Pos) /*!< 0x00000010 */
6582 #define BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1_Msk /*!< Channel 1 Global interrupt clear */
6583 #define BDMA_IFCR_CTCIF1_Pos (5U)
6584 #define BDMA_IFCR_CTCIF1_Msk (0x1UL << BDMA_IFCR_CTCIF1_Pos) /*!< 0x00000020 */
6585 #define BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1_Msk /*!< Channel 1 Transfer Complete clear */
6586 #define BDMA_IFCR_CHTIF1_Pos (6U)
6587 #define BDMA_IFCR_CHTIF1_Msk (0x1UL << BDMA_IFCR_CHTIF1_Pos) /*!< 0x00000040 */
6588 #define BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1_Msk /*!< Channel 1 Half Transfer clear */
6589 #define BDMA_IFCR_CTEIF1_Pos (7U)
6590 #define BDMA_IFCR_CTEIF1_Msk (0x1UL << BDMA_IFCR_CTEIF1_Pos) /*!< 0x00000080 */
6591 #define BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1_Msk /*!< Channel 1 Transfer Error clear */
6592 #define BDMA_IFCR_CGIF2_Pos (8U)
6593 #define BDMA_IFCR_CGIF2_Msk (0x1UL << BDMA_IFCR_CGIF2_Pos) /*!< 0x00000100 */
6594 #define BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2_Msk /*!< Channel 2 Global interrupt clear */
6595 #define BDMA_IFCR_CTCIF2_Pos (9U)
6596 #define BDMA_IFCR_CTCIF2_Msk (0x1UL << BDMA_IFCR_CTCIF2_Pos) /*!< 0x00000200 */
6597 #define BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2_Msk /*!< Channel 2 Transfer Complete clear */
6598 #define BDMA_IFCR_CHTIF2_Pos (10U)
6599 #define BDMA_IFCR_CHTIF2_Msk (0x1UL << BDMA_IFCR_CHTIF2_Pos) /*!< 0x00000400 */
6600 #define BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2_Msk /*!< Channel 2 Half Transfer clear */
6601 #define BDMA_IFCR_CTEIF2_Pos (11U)
6602 #define BDMA_IFCR_CTEIF2_Msk (0x1UL << BDMA_IFCR_CTEIF2_Pos) /*!< 0x00000800 */
6603 #define BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2_Msk /*!< Channel 2 Transfer Error clear */
6604 #define BDMA_IFCR_CGIF3_Pos (12U)
6605 #define BDMA_IFCR_CGIF3_Msk (0x1UL << BDMA_IFCR_CGIF3_Pos) /*!< 0x00001000 */
6606 #define BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3_Msk /*!< Channel 3 Global interrupt clear */
6607 #define BDMA_IFCR_CTCIF3_Pos (13U)
6608 #define BDMA_IFCR_CTCIF3_Msk (0x1UL << BDMA_IFCR_CTCIF3_Pos) /*!< 0x00002000 */
6609 #define BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3_Msk /*!< Channel 3 Transfer Complete clear */
6610 #define BDMA_IFCR_CHTIF3_Pos (14U)
6611 #define BDMA_IFCR_CHTIF3_Msk (0x1UL << BDMA_IFCR_CHTIF3_Pos) /*!< 0x00004000 */
6612 #define BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3_Msk /*!< Channel 3 Half Transfer clear */
6613 #define BDMA_IFCR_CTEIF3_Pos (15U)
6614 #define BDMA_IFCR_CTEIF3_Msk (0x1UL << BDMA_IFCR_CTEIF3_Pos) /*!< 0x00008000 */
6615 #define BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3_Msk /*!< Channel 3 Transfer Error clear */
6616 #define BDMA_IFCR_CGIF4_Pos (16U)
6617 #define BDMA_IFCR_CGIF4_Msk (0x1UL << BDMA_IFCR_CGIF4_Pos) /*!< 0x00010000 */
6618 #define BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4_Msk /*!< Channel 4 Global interrupt clear */
6619 #define BDMA_IFCR_CTCIF4_Pos (17U)
6620 #define BDMA_IFCR_CTCIF4_Msk (0x1UL << BDMA_IFCR_CTCIF4_Pos) /*!< 0x00020000 */
6621 #define BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4_Msk /*!< Channel 4 Transfer Complete clear */
6622 #define BDMA_IFCR_CHTIF4_Pos (18U)
6623 #define BDMA_IFCR_CHTIF4_Msk (0x1UL << BDMA_IFCR_CHTIF4_Pos) /*!< 0x00040000 */
6624 #define BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4_Msk /*!< Channel 4 Half Transfer clear */
6625 #define BDMA_IFCR_CTEIF4_Pos (19U)
6626 #define BDMA_IFCR_CTEIF4_Msk (0x1UL << BDMA_IFCR_CTEIF4_Pos) /*!< 0x00080000 */
6627 #define BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4_Msk /*!< Channel 4 Transfer Error clear */
6628 #define BDMA_IFCR_CGIF5_Pos (20U)
6629 #define BDMA_IFCR_CGIF5_Msk (0x1UL << BDMA_IFCR_CGIF5_Pos) /*!< 0x00100000 */
6630 #define BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5_Msk /*!< Channel 5 Global interrupt clear */
6631 #define BDMA_IFCR_CTCIF5_Pos (21U)
6632 #define BDMA_IFCR_CTCIF5_Msk (0x1UL << BDMA_IFCR_CTCIF5_Pos) /*!< 0x00200000 */
6633 #define BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5_Msk /*!< Channel 5 Transfer Complete clear */
6634 #define BDMA_IFCR_CHTIF5_Pos (22U)
6635 #define BDMA_IFCR_CHTIF5_Msk (0x1UL << BDMA_IFCR_CHTIF5_Pos) /*!< 0x00400000 */
6636 #define BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5_Msk /*!< Channel 5 Half Transfer clear */
6637 #define BDMA_IFCR_CTEIF5_Pos (23U)
6638 #define BDMA_IFCR_CTEIF5_Msk (0x1UL << BDMA_IFCR_CTEIF5_Pos) /*!< 0x00800000 */
6639 #define BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5_Msk /*!< Channel 5 Transfer Error clear */
6640 #define BDMA_IFCR_CGIF6_Pos (24U)
6641 #define BDMA_IFCR_CGIF6_Msk (0x1UL << BDMA_IFCR_CGIF6_Pos) /*!< 0x01000000 */
6642 #define BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6_Msk /*!< Channel 6 Global interrupt clear */
6643 #define BDMA_IFCR_CTCIF6_Pos (25U)
6644 #define BDMA_IFCR_CTCIF6_Msk (0x1UL << BDMA_IFCR_CTCIF6_Pos) /*!< 0x02000000 */
6645 #define BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6_Msk /*!< Channel 6 Transfer Complete clear */
6646 #define BDMA_IFCR_CHTIF6_Pos (26U)
6647 #define BDMA_IFCR_CHTIF6_Msk (0x1UL << BDMA_IFCR_CHTIF6_Pos) /*!< 0x04000000 */
6648 #define BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6_Msk /*!< Channel 6 Half Transfer clear */
6649 #define BDMA_IFCR_CTEIF6_Pos (27U)
6650 #define BDMA_IFCR_CTEIF6_Msk (0x1UL << BDMA_IFCR_CTEIF6_Pos) /*!< 0x08000000 */
6651 #define BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6_Msk /*!< Channel 6 Transfer Error clear */
6652 #define BDMA_IFCR_CGIF7_Pos (28U)
6653 #define BDMA_IFCR_CGIF7_Msk (0x1UL << BDMA_IFCR_CGIF7_Pos) /*!< 0x10000000 */
6654 #define BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7_Msk /*!< Channel 7 Global interrupt clear */
6655 #define BDMA_IFCR_CTCIF7_Pos (29U)
6656 #define BDMA_IFCR_CTCIF7_Msk (0x1UL << BDMA_IFCR_CTCIF7_Pos) /*!< 0x20000000 */
6657 #define BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7_Msk /*!< Channel 7 Transfer Complete clear */
6658 #define BDMA_IFCR_CHTIF7_Pos (30U)
6659 #define BDMA_IFCR_CHTIF7_Msk (0x1UL << BDMA_IFCR_CHTIF7_Pos) /*!< 0x40000000 */
6660 #define BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7_Msk /*!< Channel 7 Half Transfer clear */
6661 #define BDMA_IFCR_CTEIF7_Pos (31U)
6662 #define BDMA_IFCR_CTEIF7_Msk (0x1UL << BDMA_IFCR_CTEIF7_Pos) /*!< 0x80000000 */
6663 #define BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7_Msk /*!< Channel 7 Transfer Error clear */
6664
6665 /******************* Bit definition for BDMA_CCR register ********************/
6666 #define BDMA_CCR_EN_Pos (0U)
6667 #define BDMA_CCR_EN_Msk (0x1UL << BDMA_CCR_EN_Pos) /*!< 0x00000001 */
6668 #define BDMA_CCR_EN BDMA_CCR_EN_Msk /*!< Channel enable */
6669 #define BDMA_CCR_TCIE_Pos (1U)
6670 #define BDMA_CCR_TCIE_Msk (0x1UL << BDMA_CCR_TCIE_Pos) /*!< 0x00000002 */
6671 #define BDMA_CCR_TCIE BDMA_CCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6672 #define BDMA_CCR_HTIE_Pos (2U)
6673 #define BDMA_CCR_HTIE_Msk (0x1UL << BDMA_CCR_HTIE_Pos) /*!< 0x00000004 */
6674 #define BDMA_CCR_HTIE BDMA_CCR_HTIE_Msk /*!< Half Transfer interrupt enable */
6675 #define BDMA_CCR_TEIE_Pos (3U)
6676 #define BDMA_CCR_TEIE_Msk (0x1UL << BDMA_CCR_TEIE_Pos) /*!< 0x00000008 */
6677 #define BDMA_CCR_TEIE BDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
6678 #define BDMA_CCR_DIR_Pos (4U)
6679 #define BDMA_CCR_DIR_Msk (0x1UL << BDMA_CCR_DIR_Pos) /*!< 0x00000010 */
6680 #define BDMA_CCR_DIR BDMA_CCR_DIR_Msk /*!< Data transfer direction */
6681 #define BDMA_CCR_CIRC_Pos (5U)
6682 #define BDMA_CCR_CIRC_Msk (0x1UL << BDMA_CCR_CIRC_Pos) /*!< 0x00000020 */
6683 #define BDMA_CCR_CIRC BDMA_CCR_CIRC_Msk /*!< Circular mode */
6684 #define BDMA_CCR_PINC_Pos (6U)
6685 #define BDMA_CCR_PINC_Msk (0x1UL << BDMA_CCR_PINC_Pos) /*!< 0x00000040 */
6686 #define BDMA_CCR_PINC BDMA_CCR_PINC_Msk /*!< Peripheral increment mode */
6687 #define BDMA_CCR_MINC_Pos (7U)
6688 #define BDMA_CCR_MINC_Msk (0x1UL << BDMA_CCR_MINC_Pos) /*!< 0x00000080 */
6689 #define BDMA_CCR_MINC BDMA_CCR_MINC_Msk /*!< Memory increment mode */
6690
6691 #define BDMA_CCR_PSIZE_Pos (8U)
6692 #define BDMA_CCR_PSIZE_Msk (0x3UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000300 */
6693 #define BDMA_CCR_PSIZE BDMA_CCR_PSIZE_Msk /*!< PSIZE[1:0] bits (Peripheral size) */
6694 #define BDMA_CCR_PSIZE_0 (0x1UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000100 */
6695 #define BDMA_CCR_PSIZE_1 (0x2UL << BDMA_CCR_PSIZE_Pos) /*!< 0x00000200 */
6696
6697 #define BDMA_CCR_MSIZE_Pos (10U)
6698 #define BDMA_CCR_MSIZE_Msk (0x3UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000C00 */
6699 #define BDMA_CCR_MSIZE BDMA_CCR_MSIZE_Msk /*!< MSIZE[1:0] bits (Memory size) */
6700 #define BDMA_CCR_MSIZE_0 (0x1UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000400 */
6701 #define BDMA_CCR_MSIZE_1 (0x2UL << BDMA_CCR_MSIZE_Pos) /*!< 0x00000800 */
6702
6703 #define BDMA_CCR_PL_Pos (12U)
6704 #define BDMA_CCR_PL_Msk (0x3UL << BDMA_CCR_PL_Pos) /*!< 0x00003000 */
6705 #define BDMA_CCR_PL BDMA_CCR_PL_Msk /*!< PL[1:0] bits(Channel Priority level)*/
6706 #define BDMA_CCR_PL_0 (0x1UL << BDMA_CCR_PL_Pos) /*!< 0x00001000 */
6707 #define BDMA_CCR_PL_1 (0x2UL << BDMA_CCR_PL_Pos) /*!< 0x00002000 */
6708
6709 #define BDMA_CCR_MEM2MEM_Pos (14U)
6710 #define BDMA_CCR_MEM2MEM_Msk (0x1UL << BDMA_CCR_MEM2MEM_Pos) /*!< 0x00004000 */
6711 #define BDMA_CCR_MEM2MEM BDMA_CCR_MEM2MEM_Msk /*!< Memory to memory mode */
6712 #define BDMA_CCR_DBM_Pos (15U)
6713 #define BDMA_CCR_DBM_Msk (0x1UL << BDMA_CCR_DBM_Pos) /*!< 0x0000A000 */
6714 #define BDMA_CCR_DBM BDMA_CCR_DBM_Msk /*!< Memory to memory mode */
6715 #define BDMA_CCR_CT_Pos (16U)
6716 #define BDMA_CCR_CT_Msk (0x1UL << BDMA_CCR_CT_Pos) /*!< 0x00010000 */
6717 #define BDMA_CCR_CT BDMA_CCR_CT_Msk /*!< Memory to memory mode */
6718
6719 /****************** Bit definition for BDMA_CNDTR register *******************/
6720 #define BDMA_CNDTR_NDT_Pos (0U)
6721 #define BDMA_CNDTR_NDT_Msk (0xFFFFUL << BDMA_CNDTR_NDT_Pos) /*!< 0x0000FFFF */
6722 #define BDMA_CNDTR_NDT BDMA_CNDTR_NDT_Msk /*!< Number of data to Transfer */
6723
6724 /****************** Bit definition for BDMA_CPAR register ********************/
6725 #define BDMA_CPAR_PA_Pos (0U)
6726 #define BDMA_CPAR_PA_Msk (0xFFFFFFFFUL << BDMA_CPAR_PA_Pos) /*!< 0xFFFFFFFF */
6727 #define BDMA_CPAR_PA BDMA_CPAR_PA_Msk /*!< Peripheral Address */
6728
6729 /****************** Bit definition for BDMA_CM0AR register ********************/
6730 #define BDMA_CM0AR_MA_Pos (0U)
6731 #define BDMA_CM0AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM0AR_MA_Pos) /*!< 0xFFFFFFFF */
6732 #define BDMA_CM0AR_MA BDMA_CM0AR_MA_Msk /*!< Memory Address */
6733
6734 /****************** Bit definition for BDMA_CM1AR register ********************/
6735 #define BDMA_CM1AR_MA_Pos (0U)
6736 #define BDMA_CM1AR_MA_Msk (0xFFFFFFFFUL << BDMA_CM1AR_MA_Pos) /*!< 0xFFFFFFFF */
6737 #define BDMA_CM1AR_MA BDMA_CM1AR_MA_Msk /*!< Memory Address */
6738
6739 /******************************************************************************/
6740 /* */
6741 /* DMA Controller */
6742 /* */
6743 /******************************************************************************/
6744 /******************** Bits definition for DMA_SxCR register *****************/
6745 #define DMA_SxCR_MBURST_Pos (23U)
6746 #define DMA_SxCR_MBURST_Msk (0x3UL << DMA_SxCR_MBURST_Pos) /*!< 0x01800000 */
6747 #define DMA_SxCR_MBURST DMA_SxCR_MBURST_Msk /*!< Memory burst transfer configuration */
6748 #define DMA_SxCR_MBURST_0 (0x1UL << DMA_SxCR_MBURST_Pos) /*!< 0x00800000 */
6749 #define DMA_SxCR_MBURST_1 (0x2UL << DMA_SxCR_MBURST_Pos) /*!< 0x01000000 */
6750 #define DMA_SxCR_PBURST_Pos (21U)
6751 #define DMA_SxCR_PBURST_Msk (0x3UL << DMA_SxCR_PBURST_Pos) /*!< 0x00600000 */
6752 #define DMA_SxCR_PBURST DMA_SxCR_PBURST_Msk /*!< Peripheral burst transfer configuration */
6753 #define DMA_SxCR_PBURST_0 (0x1UL << DMA_SxCR_PBURST_Pos) /*!< 0x00200000 */
6754 #define DMA_SxCR_PBURST_1 (0x2UL << DMA_SxCR_PBURST_Pos) /*!< 0x00400000 */
6755 #define DMA_SxCR_CT_Pos (19U)
6756 #define DMA_SxCR_CT_Msk (0x1UL << DMA_SxCR_CT_Pos) /*!< 0x00080000 */
6757 #define DMA_SxCR_CT DMA_SxCR_CT_Msk /*!< Current target (only in double buffer mode) */
6758 #define DMA_SxCR_DBM_Pos (18U)
6759 #define DMA_SxCR_DBM_Msk (0x1UL << DMA_SxCR_DBM_Pos) /*!< 0x00040000 */
6760 #define DMA_SxCR_DBM DMA_SxCR_DBM_Msk /*!< Double buffer mode */
6761 #define DMA_SxCR_PL_Pos (16U)
6762 #define DMA_SxCR_PL_Msk (0x3UL << DMA_SxCR_PL_Pos) /*!< 0x00030000 */
6763 #define DMA_SxCR_PL DMA_SxCR_PL_Msk /*!< Priority level */
6764 #define DMA_SxCR_PL_0 (0x1UL << DMA_SxCR_PL_Pos) /*!< 0x00010000 */
6765 #define DMA_SxCR_PL_1 (0x2UL << DMA_SxCR_PL_Pos) /*!< 0x00020000 */
6766 #define DMA_SxCR_PINCOS_Pos (15U)
6767 #define DMA_SxCR_PINCOS_Msk (0x1UL << DMA_SxCR_PINCOS_Pos) /*!< 0x00008000 */
6768 #define DMA_SxCR_PINCOS DMA_SxCR_PINCOS_Msk /*!< Peripheral increment offset size */
6769 #define DMA_SxCR_MSIZE_Pos (13U)
6770 #define DMA_SxCR_MSIZE_Msk (0x3UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00006000 */
6771 #define DMA_SxCR_MSIZE DMA_SxCR_MSIZE_Msk /*!< Memory data size */
6772 #define DMA_SxCR_MSIZE_0 (0x1UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00002000 */
6773 #define DMA_SxCR_MSIZE_1 (0x2UL << DMA_SxCR_MSIZE_Pos) /*!< 0x00004000 */
6774 #define DMA_SxCR_PSIZE_Pos (11U)
6775 #define DMA_SxCR_PSIZE_Msk (0x3UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001800 */
6776 #define DMA_SxCR_PSIZE DMA_SxCR_PSIZE_Msk /*< Peripheral data size */
6777 #define DMA_SxCR_PSIZE_0 (0x1UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00000800 */
6778 #define DMA_SxCR_PSIZE_1 (0x2UL << DMA_SxCR_PSIZE_Pos) /*!< 0x00001000 */
6779 #define DMA_SxCR_MINC_Pos (10U)
6780 #define DMA_SxCR_MINC_Msk (0x1UL << DMA_SxCR_MINC_Pos) /*!< 0x00000400 */
6781 #define DMA_SxCR_MINC DMA_SxCR_MINC_Msk /*!< Memory increment mode */
6782 #define DMA_SxCR_PINC_Pos (9U)
6783 #define DMA_SxCR_PINC_Msk (0x1UL << DMA_SxCR_PINC_Pos) /*!< 0x00000200 */
6784 #define DMA_SxCR_PINC DMA_SxCR_PINC_Msk /*!< Peripheral increment mode */
6785 #define DMA_SxCR_CIRC_Pos (8U)
6786 #define DMA_SxCR_CIRC_Msk (0x1UL << DMA_SxCR_CIRC_Pos) /*!< 0x00000100 */
6787 #define DMA_SxCR_CIRC DMA_SxCR_CIRC_Msk /*!< Circular mode */
6788 #define DMA_SxCR_DIR_Pos (6U)
6789 #define DMA_SxCR_DIR_Msk (0x3UL << DMA_SxCR_DIR_Pos) /*!< 0x000000C0 */
6790 #define DMA_SxCR_DIR DMA_SxCR_DIR_Msk /*!< Data transfer direction */
6791 #define DMA_SxCR_DIR_0 (0x1UL << DMA_SxCR_DIR_Pos) /*!< 0x00000040 */
6792 #define DMA_SxCR_DIR_1 (0x2UL << DMA_SxCR_DIR_Pos) /*!< 0x00000080 */
6793 #define DMA_SxCR_PFCTRL_Pos (5U)
6794 #define DMA_SxCR_PFCTRL_Msk (0x1UL << DMA_SxCR_PFCTRL_Pos) /*!< 0x00000020 */
6795 #define DMA_SxCR_PFCTRL DMA_SxCR_PFCTRL_Msk /*!< Peripheral flow controller */
6796 #define DMA_SxCR_TCIE_Pos (4U)
6797 #define DMA_SxCR_TCIE_Msk (0x1UL << DMA_SxCR_TCIE_Pos) /*!< 0x00000010 */
6798 #define DMA_SxCR_TCIE DMA_SxCR_TCIE_Msk /*!< Transfer complete interrupt enable */
6799 #define DMA_SxCR_HTIE_Pos (3U)
6800 #define DMA_SxCR_HTIE_Msk (0x1UL << DMA_SxCR_HTIE_Pos) /*!< 0x00000008 */
6801 #define DMA_SxCR_HTIE DMA_SxCR_HTIE_Msk /*!< Half transfer interrupt enable */
6802 #define DMA_SxCR_TEIE_Pos (2U)
6803 #define DMA_SxCR_TEIE_Msk (0x1UL << DMA_SxCR_TEIE_Pos) /*!< 0x00000004 */
6804 #define DMA_SxCR_TEIE DMA_SxCR_TEIE_Msk /*!< Transfer error interrupt enable */
6805 #define DMA_SxCR_DMEIE_Pos (1U)
6806 #define DMA_SxCR_DMEIE_Msk (0x1UL << DMA_SxCR_DMEIE_Pos) /*!< 0x00000002 */
6807 #define DMA_SxCR_DMEIE DMA_SxCR_DMEIE_Msk /*!< Direct mode error interrupt enable */
6808 #define DMA_SxCR_EN_Pos (0U)
6809 #define DMA_SxCR_EN_Msk (0x1UL << DMA_SxCR_EN_Pos) /*!< 0x00000001 */
6810 #define DMA_SxCR_EN DMA_SxCR_EN_Msk /*!< Stream enable / flag stream ready when read low */
6811
6812 /******************** Bits definition for DMA_SxCNDTR register **************/
6813 #define DMA_SxNDT_Pos (0U)
6814 #define DMA_SxNDT_Msk (0xFFFFUL << DMA_SxNDT_Pos) /*!< 0x0000FFFF */
6815 #define DMA_SxNDT DMA_SxNDT_Msk /*!< Number of data items to transfer */
6816 #define DMA_SxNDT_0 (0x0001UL << DMA_SxNDT_Pos) /*!< 0x00000001 */
6817 #define DMA_SxNDT_1 (0x0002UL << DMA_SxNDT_Pos) /*!< 0x00000002 */
6818 #define DMA_SxNDT_2 (0x0004UL << DMA_SxNDT_Pos) /*!< 0x00000004 */
6819 #define DMA_SxNDT_3 (0x0008UL << DMA_SxNDT_Pos) /*!< 0x00000008 */
6820 #define DMA_SxNDT_4 (0x0010UL << DMA_SxNDT_Pos) /*!< 0x00000010 */
6821 #define DMA_SxNDT_5 (0x0020UL << DMA_SxNDT_Pos) /*!< 0x00000020 */
6822 #define DMA_SxNDT_6 (0x0040UL << DMA_SxNDT_Pos) /*!< 0x00000040 */
6823 #define DMA_SxNDT_7 (0x0080UL << DMA_SxNDT_Pos) /*!< 0x00000080 */
6824 #define DMA_SxNDT_8 (0x0100UL << DMA_SxNDT_Pos) /*!< 0x00000100 */
6825 #define DMA_SxNDT_9 (0x0200UL << DMA_SxNDT_Pos) /*!< 0x00000200 */
6826 #define DMA_SxNDT_10 (0x0400UL << DMA_SxNDT_Pos) /*!< 0x00000400 */
6827 #define DMA_SxNDT_11 (0x0800UL << DMA_SxNDT_Pos) /*!< 0x00000800 */
6828 #define DMA_SxNDT_12 (0x1000UL << DMA_SxNDT_Pos) /*!< 0x00001000 */
6829 #define DMA_SxNDT_13 (0x2000UL << DMA_SxNDT_Pos) /*!< 0x00002000 */
6830 #define DMA_SxNDT_14 (0x4000UL << DMA_SxNDT_Pos) /*!< 0x00004000 */
6831 #define DMA_SxNDT_15 (0x8000UL << DMA_SxNDT_Pos) /*!< 0x00008000 */
6832
6833 /******************** Bits definition for DMA_SxFCR register ****************/
6834 #define DMA_SxFCR_FEIE_Pos (7U)
6835 #define DMA_SxFCR_FEIE_Msk (0x1UL << DMA_SxFCR_FEIE_Pos) /*!< 0x00000080 */
6836 #define DMA_SxFCR_FEIE DMA_SxFCR_FEIE_Msk /*!< FIFO error interrupt enable */
6837 #define DMA_SxFCR_FS_Pos (3U)
6838 #define DMA_SxFCR_FS_Msk (0x7UL << DMA_SxFCR_FS_Pos) /*!< 0x00000038 */
6839 #define DMA_SxFCR_FS DMA_SxFCR_FS_Msk /*!< FIFO status */
6840 #define DMA_SxFCR_FS_0 (0x1UL << DMA_SxFCR_FS_Pos) /*!< 0x00000008 */
6841 #define DMA_SxFCR_FS_1 (0x2UL << DMA_SxFCR_FS_Pos) /*!< 0x00000010 */
6842 #define DMA_SxFCR_FS_2 (0x4UL << DMA_SxFCR_FS_Pos) /*!< 0x00000020 */
6843 #define DMA_SxFCR_DMDIS_Pos (2U)
6844 #define DMA_SxFCR_DMDIS_Msk (0x1UL << DMA_SxFCR_DMDIS_Pos) /*!< 0x00000004 */
6845 #define DMA_SxFCR_DMDIS DMA_SxFCR_DMDIS_Msk /*!< Direct mode disable */
6846 #define DMA_SxFCR_FTH_Pos (0U)
6847 #define DMA_SxFCR_FTH_Msk (0x3UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000003 */
6848 #define DMA_SxFCR_FTH DMA_SxFCR_FTH_Msk /*!< FIFO threshold selection */
6849 #define DMA_SxFCR_FTH_0 (0x1UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000001 */
6850 #define DMA_SxFCR_FTH_1 (0x2UL << DMA_SxFCR_FTH_Pos) /*!< 0x00000002 */
6851
6852 /******************** Bits definition for DMA_LISR register *****************/
6853 #define DMA_LISR_TCIF3_Pos (27U)
6854 #define DMA_LISR_TCIF3_Msk (0x1UL << DMA_LISR_TCIF3_Pos) /*!< 0x08000000 */
6855 #define DMA_LISR_TCIF3 DMA_LISR_TCIF3_Msk /*!< Stream 3 transfer complete interrupt flag */
6856 #define DMA_LISR_HTIF3_Pos (26U)
6857 #define DMA_LISR_HTIF3_Msk (0x1UL << DMA_LISR_HTIF3_Pos) /*!< 0x04000000 */
6858 #define DMA_LISR_HTIF3 DMA_LISR_HTIF3_Msk /*!< Stream 3 half transfer interrupt flag */
6859 #define DMA_LISR_TEIF3_Pos (25U)
6860 #define DMA_LISR_TEIF3_Msk (0x1UL << DMA_LISR_TEIF3_Pos) /*!< 0x02000000 */
6861 #define DMA_LISR_TEIF3 DMA_LISR_TEIF3_Msk /*!< Stream 3 transfer error interrupt flag */
6862 #define DMA_LISR_DMEIF3_Pos (24U)
6863 #define DMA_LISR_DMEIF3_Msk (0x1UL << DMA_LISR_DMEIF3_Pos) /*!< 0x01000000 */
6864 #define DMA_LISR_DMEIF3 DMA_LISR_DMEIF3_Msk /*!< Stream 3 direct mode error interrupt flag */
6865 #define DMA_LISR_FEIF3_Pos (22U)
6866 #define DMA_LISR_FEIF3_Msk (0x1UL << DMA_LISR_FEIF3_Pos) /*!< 0x00400000 */
6867 #define DMA_LISR_FEIF3 DMA_LISR_FEIF3_Msk /*!< Stream 3 FIFO error interrupt flag */
6868 #define DMA_LISR_TCIF2_Pos (21U)
6869 #define DMA_LISR_TCIF2_Msk (0x1UL << DMA_LISR_TCIF2_Pos) /*!< 0x00200000 */
6870 #define DMA_LISR_TCIF2 DMA_LISR_TCIF2_Msk /*!< Stream 2 transfer complete interrupt flag */
6871 #define DMA_LISR_HTIF2_Pos (20U)
6872 #define DMA_LISR_HTIF2_Msk (0x1UL << DMA_LISR_HTIF2_Pos) /*!< 0x00100000 */
6873 #define DMA_LISR_HTIF2 DMA_LISR_HTIF2_Msk /*!< Stream 2 half transfer interrupt flag */
6874 #define DMA_LISR_TEIF2_Pos (19U)
6875 #define DMA_LISR_TEIF2_Msk (0x1UL << DMA_LISR_TEIF2_Pos) /*!< 0x00080000 */
6876 #define DMA_LISR_TEIF2 DMA_LISR_TEIF2_Msk /*!< Stream 2 transfer error interrupt flag */
6877 #define DMA_LISR_DMEIF2_Pos (18U)
6878 #define DMA_LISR_DMEIF2_Msk (0x1UL << DMA_LISR_DMEIF2_Pos) /*!< 0x00040000 */
6879 #define DMA_LISR_DMEIF2 DMA_LISR_DMEIF2_Msk /*!< Stream 2 direct mode error interrupt flag */
6880 #define DMA_LISR_FEIF2_Pos (16U)
6881 #define DMA_LISR_FEIF2_Msk (0x1UL << DMA_LISR_FEIF2_Pos) /*!< 0x00010000 */
6882 #define DMA_LISR_FEIF2 DMA_LISR_FEIF2_Msk /*!< Stream 2 FIFO error interrupt flag */
6883 #define DMA_LISR_TCIF1_Pos (11U)
6884 #define DMA_LISR_TCIF1_Msk (0x1UL << DMA_LISR_TCIF1_Pos) /*!< 0x00000800 */
6885 #define DMA_LISR_TCIF1 DMA_LISR_TCIF1_Msk /*!< Stream 1 transfer complete interrupt flag */
6886 #define DMA_LISR_HTIF1_Pos (10U)
6887 #define DMA_LISR_HTIF1_Msk (0x1UL << DMA_LISR_HTIF1_Pos) /*!< 0x00000400 */
6888 #define DMA_LISR_HTIF1 DMA_LISR_HTIF1_Msk /*!< Stream 1 half transfer interrupt flag */
6889 #define DMA_LISR_TEIF1_Pos (9U)
6890 #define DMA_LISR_TEIF1_Msk (0x1UL << DMA_LISR_TEIF1_Pos) /*!< 0x00000200 */
6891 #define DMA_LISR_TEIF1 DMA_LISR_TEIF1_Msk /*!< Stream 1 transfer error interrupt flag */
6892 #define DMA_LISR_DMEIF1_Pos (8U)
6893 #define DMA_LISR_DMEIF1_Msk (0x1UL << DMA_LISR_DMEIF1_Pos) /*!< 0x00000100 */
6894 #define DMA_LISR_DMEIF1 DMA_LISR_DMEIF1_Msk /*!< Stream 1 direct mode error interrupt flag */
6895 #define DMA_LISR_FEIF1_Pos (6U)
6896 #define DMA_LISR_FEIF1_Msk (0x1UL << DMA_LISR_FEIF1_Pos) /*!< 0x00000040 */
6897 #define DMA_LISR_FEIF1 DMA_LISR_FEIF1_Msk /*!< Stream 1 FIFO error interrupt flag */
6898 #define DMA_LISR_TCIF0_Pos (5U)
6899 #define DMA_LISR_TCIF0_Msk (0x1UL << DMA_LISR_TCIF0_Pos) /*!< 0x00000020 */
6900 #define DMA_LISR_TCIF0 DMA_LISR_TCIF0_Msk /*!< Stream 0 transfer complete interrupt flag */
6901 #define DMA_LISR_HTIF0_Pos (4U)
6902 #define DMA_LISR_HTIF0_Msk (0x1UL << DMA_LISR_HTIF0_Pos) /*!< 0x00000010 */
6903 #define DMA_LISR_HTIF0 DMA_LISR_HTIF0_Msk /*!< Stream 0 half transfer interrupt flag */
6904 #define DMA_LISR_TEIF0_Pos (3U)
6905 #define DMA_LISR_TEIF0_Msk (0x1UL << DMA_LISR_TEIF0_Pos) /*!< 0x00000008 */
6906 #define DMA_LISR_TEIF0 DMA_LISR_TEIF0_Msk /*!< Stream 0 transfer error interrupt flag */
6907 #define DMA_LISR_DMEIF0_Pos (2U)
6908 #define DMA_LISR_DMEIF0_Msk (0x1UL << DMA_LISR_DMEIF0_Pos) /*!< 0x00000004 */
6909 #define DMA_LISR_DMEIF0 DMA_LISR_DMEIF0_Msk /*!< Stream 0 direct mode error interrupt flag */
6910 #define DMA_LISR_FEIF0_Pos (0U)
6911 #define DMA_LISR_FEIF0_Msk (0x1UL << DMA_LISR_FEIF0_Pos) /*!< 0x00000001 */
6912 #define DMA_LISR_FEIF0 DMA_LISR_FEIF0_Msk /*!< Stream 0 FIFO error interrupt flag */
6913
6914 /******************** Bits definition for DMA_HISR register *****************/
6915 #define DMA_HISR_TCIF7_Pos (27U)
6916 #define DMA_HISR_TCIF7_Msk (0x1UL << DMA_HISR_TCIF7_Pos) /*!< 0x08000000 */
6917 #define DMA_HISR_TCIF7 DMA_HISR_TCIF7_Msk /*!< Stream 7 transfer complete interrupt flag */
6918 #define DMA_HISR_HTIF7_Pos (26U)
6919 #define DMA_HISR_HTIF7_Msk (0x1UL << DMA_HISR_HTIF7_Pos) /*!< 0x04000000 */
6920 #define DMA_HISR_HTIF7 DMA_HISR_HTIF7_Msk /*!< Stream 7 half transfer interrupt flag */
6921 #define DMA_HISR_TEIF7_Pos (25U)
6922 #define DMA_HISR_TEIF7_Msk (0x1UL << DMA_HISR_TEIF7_Pos) /*!< 0x02000000 */
6923 #define DMA_HISR_TEIF7 DMA_HISR_TEIF7_Msk /*!< Stream 7 transfer error interrupt flag */
6924 #define DMA_HISR_DMEIF7_Pos (24U)
6925 #define DMA_HISR_DMEIF7_Msk (0x1UL << DMA_HISR_DMEIF7_Pos) /*!< 0x01000000 */
6926 #define DMA_HISR_DMEIF7 DMA_HISR_DMEIF7_Msk /*!< Stream 7 direct mode error interrupt flag */
6927 #define DMA_HISR_FEIF7_Pos (22U)
6928 #define DMA_HISR_FEIF7_Msk (0x1UL << DMA_HISR_FEIF7_Pos) /*!< 0x00400000 */
6929 #define DMA_HISR_FEIF7 DMA_HISR_FEIF7_Msk /*!< Stream 7 FIFO error interrupt flag */
6930 #define DMA_HISR_TCIF6_Pos (21U)
6931 #define DMA_HISR_TCIF6_Msk (0x1UL << DMA_HISR_TCIF6_Pos) /*!< 0x00200000 */
6932 #define DMA_HISR_TCIF6 DMA_HISR_TCIF6_Msk /*!< Stream 6 transfer complete interrupt flag */
6933 #define DMA_HISR_HTIF6_Pos (20U)
6934 #define DMA_HISR_HTIF6_Msk (0x1UL << DMA_HISR_HTIF6_Pos) /*!< 0x00100000 */
6935 #define DMA_HISR_HTIF6 DMA_HISR_HTIF6_Msk /*!< Stream 6 half transfer interrupt flag */
6936 #define DMA_HISR_TEIF6_Pos (19U)
6937 #define DMA_HISR_TEIF6_Msk (0x1UL << DMA_HISR_TEIF6_Pos) /*!< 0x00080000 */
6938 #define DMA_HISR_TEIF6 DMA_HISR_TEIF6_Msk /*!< Stream 6 transfer error interrupt flag */
6939 #define DMA_HISR_DMEIF6_Pos (18U)
6940 #define DMA_HISR_DMEIF6_Msk (0x1UL << DMA_HISR_DMEIF6_Pos) /*!< 0x00040000 */
6941 #define DMA_HISR_DMEIF6 DMA_HISR_DMEIF6_Msk /*!< Stream 6 direct mode error interrupt flag */
6942 #define DMA_HISR_FEIF6_Pos (16U)
6943 #define DMA_HISR_FEIF6_Msk (0x1UL << DMA_HISR_FEIF6_Pos) /*!< 0x00010000 */
6944 #define DMA_HISR_FEIF6 DMA_HISR_FEIF6_Msk /*!< Stream 6 FIFO error interrupt flag */
6945 #define DMA_HISR_TCIF5_Pos (11U)
6946 #define DMA_HISR_TCIF5_Msk (0x1UL << DMA_HISR_TCIF5_Pos) /*!< 0x00000800 */
6947 #define DMA_HISR_TCIF5 DMA_HISR_TCIF5_Msk /*!< Stream 5 transfer complete interrupt flag */
6948 #define DMA_HISR_HTIF5_Pos (10U)
6949 #define DMA_HISR_HTIF5_Msk (0x1UL << DMA_HISR_HTIF5_Pos) /*!< 0x00000400 */
6950 #define DMA_HISR_HTIF5 DMA_HISR_HTIF5_Msk /*!< Stream 5 half transfer interrupt flag */
6951 #define DMA_HISR_TEIF5_Pos (9U)
6952 #define DMA_HISR_TEIF5_Msk (0x1UL << DMA_HISR_TEIF5_Pos) /*!< 0x00000200 */
6953 #define DMA_HISR_TEIF5 DMA_HISR_TEIF5_Msk /*!< Stream 5 transfer error interrupt flag */
6954 #define DMA_HISR_DMEIF5_Pos (8U)
6955 #define DMA_HISR_DMEIF5_Msk (0x1UL << DMA_HISR_DMEIF5_Pos) /*!< 0x00000100 */
6956 #define DMA_HISR_DMEIF5 DMA_HISR_DMEIF5_Msk /*!< Stream 5 direct mode error interrupt flag */
6957 #define DMA_HISR_FEIF5_Pos (6U)
6958 #define DMA_HISR_FEIF5_Msk (0x1UL << DMA_HISR_FEIF5_Pos) /*!< 0x00000040 */
6959 #define DMA_HISR_FEIF5 DMA_HISR_FEIF5_Msk /*!< Stream 5 FIFO error interrupt flag */
6960 #define DMA_HISR_TCIF4_Pos (5U)
6961 #define DMA_HISR_TCIF4_Msk (0x1UL << DMA_HISR_TCIF4_Pos) /*!< 0x00000020 */
6962 #define DMA_HISR_TCIF4 DMA_HISR_TCIF4_Msk /*!< Stream 4 transfer complete interrupt flag */
6963 #define DMA_HISR_HTIF4_Pos (4U)
6964 #define DMA_HISR_HTIF4_Msk (0x1UL << DMA_HISR_HTIF4_Pos) /*!< 0x00000010 */
6965 #define DMA_HISR_HTIF4 DMA_HISR_HTIF4_Msk /*!< Stream 4 half transfer interrupt flag */
6966 #define DMA_HISR_TEIF4_Pos (3U)
6967 #define DMA_HISR_TEIF4_Msk (0x1UL << DMA_HISR_TEIF4_Pos) /*!< 0x00000008 */
6968 #define DMA_HISR_TEIF4 DMA_HISR_TEIF4_Msk /*!< Stream 4 transfer error interrupt flag */
6969 #define DMA_HISR_DMEIF4_Pos (2U)
6970 #define DMA_HISR_DMEIF4_Msk (0x1UL << DMA_HISR_DMEIF4_Pos) /*!< 0x00000004 */
6971 #define DMA_HISR_DMEIF4 DMA_HISR_DMEIF4_Msk /*!< Stream 4 direct mode error interrupt flag */
6972 #define DMA_HISR_FEIF4_Pos (0U)
6973 #define DMA_HISR_FEIF4_Msk (0x1UL << DMA_HISR_FEIF4_Pos) /*!< 0x00000001 */
6974 #define DMA_HISR_FEIF4 DMA_HISR_FEIF4_Msk /*!< Stream 4 FIFO error interrupt flag */
6975
6976 /******************** Bits definition for DMA_LIFCR register ****************/
6977 #define DMA_LIFCR_CTCIF3_Pos (27U)
6978 #define DMA_LIFCR_CTCIF3_Msk (0x1UL << DMA_LIFCR_CTCIF3_Pos) /*!< 0x08000000 */
6979 #define DMA_LIFCR_CTCIF3 DMA_LIFCR_CTCIF3_Msk /*!< Stream 3 clear transfer complete interrupt flag */
6980 #define DMA_LIFCR_CHTIF3_Pos (26U)
6981 #define DMA_LIFCR_CHTIF3_Msk (0x1UL << DMA_LIFCR_CHTIF3_Pos) /*!< 0x04000000 */
6982 #define DMA_LIFCR_CHTIF3 DMA_LIFCR_CHTIF3_Msk /*!< Stream 3 clear half transfer interrupt flag */
6983 #define DMA_LIFCR_CTEIF3_Pos (25U)
6984 #define DMA_LIFCR_CTEIF3_Msk (0x1UL << DMA_LIFCR_CTEIF3_Pos) /*!< 0x02000000 */
6985 #define DMA_LIFCR_CTEIF3 DMA_LIFCR_CTEIF3_Msk /*!< Stream 3 clear transfer error interrupt flag */
6986 #define DMA_LIFCR_CDMEIF3_Pos (24U)
6987 #define DMA_LIFCR_CDMEIF3_Msk (0x1UL << DMA_LIFCR_CDMEIF3_Pos) /*!< 0x01000000 */
6988 #define DMA_LIFCR_CDMEIF3 DMA_LIFCR_CDMEIF3_Msk /*!< Stream 3 clear direct mode error interrupt flag */
6989 #define DMA_LIFCR_CFEIF3_Pos (22U)
6990 #define DMA_LIFCR_CFEIF3_Msk (0x1UL << DMA_LIFCR_CFEIF3_Pos) /*!< 0x00400000 */
6991 #define DMA_LIFCR_CFEIF3 DMA_LIFCR_CFEIF3_Msk /*!< Stream 3 clear FIFO error interrupt flag */
6992 #define DMA_LIFCR_CTCIF2_Pos (21U)
6993 #define DMA_LIFCR_CTCIF2_Msk (0x1UL << DMA_LIFCR_CTCIF2_Pos) /*!< 0x00200000 */
6994 #define DMA_LIFCR_CTCIF2 DMA_LIFCR_CTCIF2_Msk /*!< Stream 2 clear transfer complete interrupt flag */
6995 #define DMA_LIFCR_CHTIF2_Pos (20U)
6996 #define DMA_LIFCR_CHTIF2_Msk (0x1UL << DMA_LIFCR_CHTIF2_Pos) /*!< 0x00100000 */
6997 #define DMA_LIFCR_CHTIF2 DMA_LIFCR_CHTIF2_Msk /*!< Stream 2 clear half transfer interrupt flag */
6998 #define DMA_LIFCR_CTEIF2_Pos (19U)
6999 #define DMA_LIFCR_CTEIF2_Msk (0x1UL << DMA_LIFCR_CTEIF2_Pos) /*!< 0x00080000 */
7000 #define DMA_LIFCR_CTEIF2 DMA_LIFCR_CTEIF2_Msk /*!< Stream 2 clear transfer error interrupt flag */
7001 #define DMA_LIFCR_CDMEIF2_Pos (18U)
7002 #define DMA_LIFCR_CDMEIF2_Msk (0x1UL << DMA_LIFCR_CDMEIF2_Pos) /*!< 0x00040000 */
7003 #define DMA_LIFCR_CDMEIF2 DMA_LIFCR_CDMEIF2_Msk /*!< Stream 2 clear direct mode error interrupt flag */
7004 #define DMA_LIFCR_CFEIF2_Pos (16U)
7005 #define DMA_LIFCR_CFEIF2_Msk (0x1UL << DMA_LIFCR_CFEIF2_Pos) /*!< 0x00010000 */
7006 #define DMA_LIFCR_CFEIF2 DMA_LIFCR_CFEIF2_Msk /*!< Stream 2 clear FIFO error interrupt flag */
7007 #define DMA_LIFCR_CTCIF1_Pos (11U)
7008 #define DMA_LIFCR_CTCIF1_Msk (0x1UL << DMA_LIFCR_CTCIF1_Pos) /*!< 0x00000800 */
7009 #define DMA_LIFCR_CTCIF1 DMA_LIFCR_CTCIF1_Msk /*!< Stream 1 clear transfer complete interrupt flag */
7010 #define DMA_LIFCR_CHTIF1_Pos (10U)
7011 #define DMA_LIFCR_CHTIF1_Msk (0x1UL << DMA_LIFCR_CHTIF1_Pos) /*!< 0x00000400 */
7012 #define DMA_LIFCR_CHTIF1 DMA_LIFCR_CHTIF1_Msk /*!< Stream 1 clear half transfer interrupt flag */
7013 #define DMA_LIFCR_CTEIF1_Pos (9U)
7014 #define DMA_LIFCR_CTEIF1_Msk (0x1UL << DMA_LIFCR_CTEIF1_Pos) /*!< 0x00000200 */
7015 #define DMA_LIFCR_CTEIF1 DMA_LIFCR_CTEIF1_Msk /*!< Stream 1 clear transfer error interrupt flag */
7016 #define DMA_LIFCR_CDMEIF1_Pos (8U)
7017 #define DMA_LIFCR_CDMEIF1_Msk (0x1UL << DMA_LIFCR_CDMEIF1_Pos) /*!< 0x00000100 */
7018 #define DMA_LIFCR_CDMEIF1 DMA_LIFCR_CDMEIF1_Msk /*!< Stream 1 clear direct mode error interrupt flag */
7019 #define DMA_LIFCR_CFEIF1_Pos (6U)
7020 #define DMA_LIFCR_CFEIF1_Msk (0x1UL << DMA_LIFCR_CFEIF1_Pos) /*!< 0x00000040 */
7021 #define DMA_LIFCR_CFEIF1 DMA_LIFCR_CFEIF1_Msk /*!< Stream 1 clear FIFO error interrupt flag */
7022 #define DMA_LIFCR_CTCIF0_Pos (5U)
7023 #define DMA_LIFCR_CTCIF0_Msk (0x1UL << DMA_LIFCR_CTCIF0_Pos) /*!< 0x00000020 */
7024 #define DMA_LIFCR_CTCIF0 DMA_LIFCR_CTCIF0_Msk /*!< Stream 0 clear transfer complete interrupt flag */
7025 #define DMA_LIFCR_CHTIF0_Pos (4U)
7026 #define DMA_LIFCR_CHTIF0_Msk (0x1UL << DMA_LIFCR_CHTIF0_Pos) /*!< 0x00000010 */
7027 #define DMA_LIFCR_CHTIF0 DMA_LIFCR_CHTIF0_Msk /*!< Stream 0 clear half transfer interrupt flag */
7028 #define DMA_LIFCR_CTEIF0_Pos (3U)
7029 #define DMA_LIFCR_CTEIF0_Msk (0x1UL << DMA_LIFCR_CTEIF0_Pos) /*!< 0x00000008 */
7030 #define DMA_LIFCR_CTEIF0 DMA_LIFCR_CTEIF0_Msk /*!< Stream 0 clear transfer error interrupt flag */
7031 #define DMA_LIFCR_CDMEIF0_Pos (2U)
7032 #define DMA_LIFCR_CDMEIF0_Msk (0x1UL << DMA_LIFCR_CDMEIF0_Pos) /*!< 0x00000004 */
7033 #define DMA_LIFCR_CDMEIF0 DMA_LIFCR_CDMEIF0_Msk /*!< Stream 0 clear direct mode error interrupt flag */
7034 #define DMA_LIFCR_CFEIF0_Pos (0U)
7035 #define DMA_LIFCR_CFEIF0_Msk (0x1UL << DMA_LIFCR_CFEIF0_Pos) /*!< 0x00000001 */
7036 #define DMA_LIFCR_CFEIF0 DMA_LIFCR_CFEIF0_Msk /*!< Stream 0 clear FIFO error interrupt flag */
7037
7038 /******************** Bits definition for DMA_HIFCR register ****************/
7039 #define DMA_HIFCR_CTCIF7_Pos (27U)
7040 #define DMA_HIFCR_CTCIF7_Msk (0x1UL << DMA_HIFCR_CTCIF7_Pos) /*!< 0x08000000 */
7041 #define DMA_HIFCR_CTCIF7 DMA_HIFCR_CTCIF7_Msk /*!< Stream 7 clear transfer complete interrupt flag */
7042 #define DMA_HIFCR_CHTIF7_Pos (26U)
7043 #define DMA_HIFCR_CHTIF7_Msk (0x1UL << DMA_HIFCR_CHTIF7_Pos) /*!< 0x04000000 */
7044 #define DMA_HIFCR_CHTIF7 DMA_HIFCR_CHTIF7_Msk /*!< Stream 7 clear half transfer interrupt flag */
7045 #define DMA_HIFCR_CTEIF7_Pos (25U)
7046 #define DMA_HIFCR_CTEIF7_Msk (0x1UL << DMA_HIFCR_CTEIF7_Pos) /*!< 0x02000000 */
7047 #define DMA_HIFCR_CTEIF7 DMA_HIFCR_CTEIF7_Msk /*!< Stream 7 clear transfer error interrupt flag */
7048 #define DMA_HIFCR_CDMEIF7_Pos (24U)
7049 #define DMA_HIFCR_CDMEIF7_Msk (0x1UL << DMA_HIFCR_CDMEIF7_Pos) /*!< 0x01000000 */
7050 #define DMA_HIFCR_CDMEIF7 DMA_HIFCR_CDMEIF7_Msk /*!< Stream 7 clear direct mode error interrupt flag */
7051 #define DMA_HIFCR_CFEIF7_Pos (22U)
7052 #define DMA_HIFCR_CFEIF7_Msk (0x1UL << DMA_HIFCR_CFEIF7_Pos) /*!< 0x00400000 */
7053 #define DMA_HIFCR_CFEIF7 DMA_HIFCR_CFEIF7_Msk /*!< Stream 7 clear FIFO error interrupt flag */
7054 #define DMA_HIFCR_CTCIF6_Pos (21U)
7055 #define DMA_HIFCR_CTCIF6_Msk (0x1UL << DMA_HIFCR_CTCIF6_Pos) /*!< 0x00200000 */
7056 #define DMA_HIFCR_CTCIF6 DMA_HIFCR_CTCIF6_Msk /*!< Stream 6 clear transfer complete interrupt flag */
7057 #define DMA_HIFCR_CHTIF6_Pos (20U)
7058 #define DMA_HIFCR_CHTIF6_Msk (0x1UL << DMA_HIFCR_CHTIF6_Pos) /*!< 0x00100000 */
7059 #define DMA_HIFCR_CHTIF6 DMA_HIFCR_CHTIF6_Msk /*!< Stream 6 clear half transfer interrupt flag */
7060 #define DMA_HIFCR_CTEIF6_Pos (19U)
7061 #define DMA_HIFCR_CTEIF6_Msk (0x1UL << DMA_HIFCR_CTEIF6_Pos) /*!< 0x00080000 */
7062 #define DMA_HIFCR_CTEIF6 DMA_HIFCR_CTEIF6_Msk /*!< Stream 6 clear transfer error interrupt flag */
7063 #define DMA_HIFCR_CDMEIF6_Pos (18U)
7064 #define DMA_HIFCR_CDMEIF6_Msk (0x1UL << DMA_HIFCR_CDMEIF6_Pos) /*!< 0x00040000 */
7065 #define DMA_HIFCR_CDMEIF6 DMA_HIFCR_CDMEIF6_Msk /*!< Stream 6 clear direct mode error interrupt flag */
7066 #define DMA_HIFCR_CFEIF6_Pos (16U)
7067 #define DMA_HIFCR_CFEIF6_Msk (0x1UL << DMA_HIFCR_CFEIF6_Pos) /*!< 0x00010000 */
7068 #define DMA_HIFCR_CFEIF6 DMA_HIFCR_CFEIF6_Msk /*!< Stream 6 clear FIFO error interrupt flag */
7069 #define DMA_HIFCR_CTCIF5_Pos (11U)
7070 #define DMA_HIFCR_CTCIF5_Msk (0x1UL << DMA_HIFCR_CTCIF5_Pos) /*!< 0x00000800 */
7071 #define DMA_HIFCR_CTCIF5 DMA_HIFCR_CTCIF5_Msk /*!< Stream 5 clear transfer complete interrupt flag */
7072 #define DMA_HIFCR_CHTIF5_Pos (10U)
7073 #define DMA_HIFCR_CHTIF5_Msk (0x1UL << DMA_HIFCR_CHTIF5_Pos) /*!< 0x00000400 */
7074 #define DMA_HIFCR_CHTIF5 DMA_HIFCR_CHTIF5_Msk /*!< Stream 5 clear half transfer interrupt flag */
7075 #define DMA_HIFCR_CTEIF5_Pos (9U)
7076 #define DMA_HIFCR_CTEIF5_Msk (0x1UL << DMA_HIFCR_CTEIF5_Pos) /*!< 0x00000200 */
7077 #define DMA_HIFCR_CTEIF5 DMA_HIFCR_CTEIF5_Msk /*!< Stream 5 clear transfer error interrupt flag */
7078 #define DMA_HIFCR_CDMEIF5_Pos (8U)
7079 #define DMA_HIFCR_CDMEIF5_Msk (0x1UL << DMA_HIFCR_CDMEIF5_Pos) /*!< 0x00000100 */
7080 #define DMA_HIFCR_CDMEIF5 DMA_HIFCR_CDMEIF5_Msk /*!< Stream 5 clear direct mode error interrupt flag */
7081 #define DMA_HIFCR_CFEIF5_Pos (6U)
7082 #define DMA_HIFCR_CFEIF5_Msk (0x1UL << DMA_HIFCR_CFEIF5_Pos) /*!< 0x00000040 */
7083 #define DMA_HIFCR_CFEIF5 DMA_HIFCR_CFEIF5_Msk /*!< Stream 5 clear FIFO error interrupt flag */
7084 #define DMA_HIFCR_CTCIF4_Pos (5U)
7085 #define DMA_HIFCR_CTCIF4_Msk (0x1UL << DMA_HIFCR_CTCIF4_Pos) /*!< 0x00000020 */
7086 #define DMA_HIFCR_CTCIF4 DMA_HIFCR_CTCIF4_Msk /*!< Stream 4 clear transfer complete interrupt flag */
7087 #define DMA_HIFCR_CHTIF4_Pos (4U)
7088 #define DMA_HIFCR_CHTIF4_Msk (0x1UL << DMA_HIFCR_CHTIF4_Pos) /*!< 0x00000010 */
7089 #define DMA_HIFCR_CHTIF4 DMA_HIFCR_CHTIF4_Msk /*!< Stream 4 clear half transfer interrupt flag */
7090 #define DMA_HIFCR_CTEIF4_Pos (3U)
7091 #define DMA_HIFCR_CTEIF4_Msk (0x1UL << DMA_HIFCR_CTEIF4_Pos) /*!< 0x00000008 */
7092 #define DMA_HIFCR_CTEIF4 DMA_HIFCR_CTEIF4_Msk /*!< Stream 4 clear transfer error interrupt flag */
7093 #define DMA_HIFCR_CDMEIF4_Pos (2U)
7094 #define DMA_HIFCR_CDMEIF4_Msk (0x1UL << DMA_HIFCR_CDMEIF4_Pos) /*!< 0x00000004 */
7095 #define DMA_HIFCR_CDMEIF4 DMA_HIFCR_CDMEIF4_Msk /*!< Stream 4 clear direct mode error interrupt flag */
7096 #define DMA_HIFCR_CFEIF4_Pos (0U)
7097 #define DMA_HIFCR_CFEIF4_Msk (0x1UL << DMA_HIFCR_CFEIF4_Pos) /*!< 0x00000001 */
7098 #define DMA_HIFCR_CFEIF4 DMA_HIFCR_CFEIF4_Msk /*!< Stream 4 clear FIFO error interrupt flag */
7099
7100 /****************** Bit definition for DMA_SxPAR register ********************/
7101 #define DMA_SxPAR_PA_Pos (0U)
7102 #define DMA_SxPAR_PA_Msk (0xFFFFFFFFUL << DMA_SxPAR_PA_Pos) /*!< 0xFFFFFFFF */
7103 #define DMA_SxPAR_PA DMA_SxPAR_PA_Msk /*!< Peripheral Address */
7104
7105 /****************** Bit definition for DMA_SxM0AR register ********************/
7106 #define DMA_SxM0AR_M0A_Pos (0U)
7107 #define DMA_SxM0AR_M0A_Msk (0xFFFFFFFFUL << DMA_SxM0AR_M0A_Pos) /*!< 0xFFFFFFFF */
7108 #define DMA_SxM0AR_M0A DMA_SxM0AR_M0A_Msk /*!< Memory 0 Address */
7109
7110 /****************** Bit definition for DMA_SxM1AR register ********************/
7111 #define DMA_SxM1AR_M1A_Pos (0U)
7112 #define DMA_SxM1AR_M1A_Msk (0xFFFFFFFFUL << DMA_SxM1AR_M1A_Pos) /*!< 0xFFFFFFFF */
7113 #define DMA_SxM1AR_M1A DMA_SxM1AR_M1A_Msk /*!< Memory 1 Address */
7114
7115 /******************************************************************************/
7116 /* */
7117 /* DMAMUX Controller */
7118 /* */
7119 /******************************************************************************/
7120 /******************** Bits definition for DMAMUX_CxCR register **************/
7121 #define DMAMUX_CxCR_DMAREQ_ID_Pos (0U)
7122 #define DMAMUX_CxCR_DMAREQ_ID_Msk (0xFFUL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x000000FF */
7123 #define DMAMUX_CxCR_DMAREQ_ID DMAMUX_CxCR_DMAREQ_ID_Msk /*!< DMA request identification */
7124 #define DMAMUX_CxCR_DMAREQ_ID_0 (0x01UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000001 */
7125 #define DMAMUX_CxCR_DMAREQ_ID_1 (0x02UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000002 */
7126 #define DMAMUX_CxCR_DMAREQ_ID_2 (0x04UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000004 */
7127 #define DMAMUX_CxCR_DMAREQ_ID_3 (0x08UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000008 */
7128 #define DMAMUX_CxCR_DMAREQ_ID_4 (0x10UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000010 */
7129 #define DMAMUX_CxCR_DMAREQ_ID_5 (0x20UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000020 */
7130 #define DMAMUX_CxCR_DMAREQ_ID_6 (0x40UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000040 */
7131 #define DMAMUX_CxCR_DMAREQ_ID_7 (0x80UL << DMAMUX_CxCR_DMAREQ_ID_Pos) /*!< 0x00000080 */
7132 #define DMAMUX_CxCR_SOIE_Pos (8U)
7133 #define DMAMUX_CxCR_SOIE_Msk (0x1UL << DMAMUX_CxCR_SOIE_Pos) /*!< 0x00000100 */
7134 #define DMAMUX_CxCR_SOIE DMAMUX_CxCR_SOIE_Msk /*!< Synchronization overrun interrupt enable */
7135 #define DMAMUX_CxCR_EGE_Pos (9U)
7136 #define DMAMUX_CxCR_EGE_Msk (0x1UL << DMAMUX_CxCR_EGE_Pos) /*!< 0x00000200 */
7137 #define DMAMUX_CxCR_EGE DMAMUX_CxCR_EGE_Msk /*!< Event generation enable */
7138 #define DMAMUX_CxCR_SE_Pos (16U)
7139 #define DMAMUX_CxCR_SE_Msk (0x1UL << DMAMUX_CxCR_SE_Pos) /*!< 0x00010000 */
7140 #define DMAMUX_CxCR_SE DMAMUX_CxCR_SE_Msk /*!< Synchronization enable */
7141 #define DMAMUX_CxCR_SPOL_Pos (17U)
7142 #define DMAMUX_CxCR_SPOL_Msk (0x3UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00060000 */
7143 #define DMAMUX_CxCR_SPOL DMAMUX_CxCR_SPOL_Msk /*!< Synchronization polarity */
7144 #define DMAMUX_CxCR_SPOL_0 (0x1UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00020000 */
7145 #define DMAMUX_CxCR_SPOL_1 (0x2UL << DMAMUX_CxCR_SPOL_Pos) /*!< 0x00040000 */
7146 #define DMAMUX_CxCR_NBREQ_Pos (19U)
7147 #define DMAMUX_CxCR_NBREQ_Msk (0x1FUL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00F80000 */
7148 #define DMAMUX_CxCR_NBREQ DMAMUX_CxCR_NBREQ_Msk /*!< Number of DMA requests minus 1 to forward */
7149 #define DMAMUX_CxCR_NBREQ_0 (0x01UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00080000 */
7150 #define DMAMUX_CxCR_NBREQ_1 (0x02UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00100000 */
7151 #define DMAMUX_CxCR_NBREQ_2 (0x04UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00200000 */
7152 #define DMAMUX_CxCR_NBREQ_3 (0x08UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00400000 */
7153 #define DMAMUX_CxCR_NBREQ_4 (0x10UL << DMAMUX_CxCR_NBREQ_Pos) /*!< 0x00800000 */
7154 #define DMAMUX_CxCR_SYNC_ID_Pos (24U)
7155 #define DMAMUX_CxCR_SYNC_ID_Msk (0x1FUL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x1F000000 */
7156 #define DMAMUX_CxCR_SYNC_ID DMAMUX_CxCR_SYNC_ID_Msk /*!< Synchronization identification */
7157 #define DMAMUX_CxCR_SYNC_ID_0 (0x01UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x01000000 */
7158 #define DMAMUX_CxCR_SYNC_ID_1 (0x02UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x02000000 */
7159 #define DMAMUX_CxCR_SYNC_ID_2 (0x04UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x04000000 */
7160 #define DMAMUX_CxCR_SYNC_ID_3 (0x08UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x08000000 */
7161 #define DMAMUX_CxCR_SYNC_ID_4 (0x10UL << DMAMUX_CxCR_SYNC_ID_Pos) /*!< 0x10000000 */
7162
7163 /******************** Bits definition for DMAMUX_CSR register **************/
7164 #define DMAMUX_CSR_SOF0_Pos (0U)
7165 #define DMAMUX_CSR_SOF0_Msk (0x1UL << DMAMUX_CSR_SOF0_Pos) /*!< 0x00000001 */
7166 #define DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0_Msk /*!< Channel 0 Synchronization overrun event flag */
7167 #define DMAMUX_CSR_SOF1_Pos (1U)
7168 #define DMAMUX_CSR_SOF1_Msk (0x1UL << DMAMUX_CSR_SOF1_Pos) /*!< 0x00000002 */
7169 #define DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1_Msk /*!< Channel 1 Synchronization overrun event flag */
7170 #define DMAMUX_CSR_SOF2_Pos (2U)
7171 #define DMAMUX_CSR_SOF2_Msk (0x1UL << DMAMUX_CSR_SOF2_Pos) /*!< 0x00000004 */
7172 #define DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2_Msk /*!< Channel 2 Synchronization overrun event flag */
7173 #define DMAMUX_CSR_SOF3_Pos (3U)
7174 #define DMAMUX_CSR_SOF3_Msk (0x1UL << DMAMUX_CSR_SOF3_Pos) /*!< 0x00000008 */
7175 #define DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3_Msk /*!< Channel 3 Synchronization overrun event flag */
7176 #define DMAMUX_CSR_SOF4_Pos (4U)
7177 #define DMAMUX_CSR_SOF4_Msk (0x1UL << DMAMUX_CSR_SOF4_Pos) /*!< 0x00000010 */
7178 #define DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4_Msk /*!< Channel 4 Synchronization overrun event flag */
7179 #define DMAMUX_CSR_SOF5_Pos (5U)
7180 #define DMAMUX_CSR_SOF5_Msk (0x1UL << DMAMUX_CSR_SOF5_Pos) /*!< 0x00000020 */
7181 #define DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5_Msk /*!< Channel 5 Synchronization overrun event flag */
7182 #define DMAMUX_CSR_SOF6_Pos (6U)
7183 #define DMAMUX_CSR_SOF6_Msk (0x1UL << DMAMUX_CSR_SOF6_Pos) /*!< 0x00000040 */
7184 #define DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6_Msk /*!< Channel 6 Synchronization overrun event flag */
7185 #define DMAMUX_CSR_SOF7_Pos (7U)
7186 #define DMAMUX_CSR_SOF7_Msk (0x1UL << DMAMUX_CSR_SOF7_Pos) /*!< 0x00000080 */
7187 #define DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7_Msk /*!< Channel 7 Synchronization overrun event flag */
7188 #define DMAMUX_CSR_SOF8_Pos (8U)
7189 #define DMAMUX_CSR_SOF8_Msk (0x1UL << DMAMUX_CSR_SOF8_Pos) /*!< 0x00000100 */
7190 #define DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8_Msk /*!< Channel 8 Synchronization overrun event flag */
7191 #define DMAMUX_CSR_SOF9_Pos (9U)
7192 #define DMAMUX_CSR_SOF9_Msk (0x1UL << DMAMUX_CSR_SOF9_Pos) /*!< 0x00000200 */
7193 #define DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9_Msk /*!< Channel 9 Synchronization overrun event flag */
7194 #define DMAMUX_CSR_SOF10_Pos (10U)
7195 #define DMAMUX_CSR_SOF10_Msk (0x1UL << DMAMUX_CSR_SOF10_Pos) /*!< 0x00000400 */
7196 #define DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10_Msk /*!< Channel 10 Synchronization overrun event flag */
7197 #define DMAMUX_CSR_SOF11_Pos (11U)
7198 #define DMAMUX_CSR_SOF11_Msk (0x1UL << DMAMUX_CSR_SOF11_Pos) /*!< 0x00000800 */
7199 #define DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11_Msk /*!< Channel 11 Synchronization overrun event flag */
7200 #define DMAMUX_CSR_SOF12_Pos (12U)
7201 #define DMAMUX_CSR_SOF12_Msk (0x1UL << DMAMUX_CSR_SOF12_Pos) /*!< 0x00001000 */
7202 #define DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12_Msk /*!< Channel 12 Synchronization overrun event flag */
7203 #define DMAMUX_CSR_SOF13_Pos (13U)
7204 #define DMAMUX_CSR_SOF13_Msk (0x1UL << DMAMUX_CSR_SOF13_Pos) /*!< 0x00002000 */
7205 #define DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13_Msk /*!< Channel 13 Synchronization overrun event flag */
7206 #define DMAMUX_CSR_SOF14_Pos (14U)
7207 #define DMAMUX_CSR_SOF14_Msk (0x1UL << DMAMUX_CSR_SOF14_Pos) /*!< 0x00004000 */
7208 #define DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14_Msk /*!< Channel 14 Synchronization overrun event flag */
7209 #define DMAMUX_CSR_SOF15_Pos (15U)
7210 #define DMAMUX_CSR_SOF15_Msk (0x1UL << DMAMUX_CSR_SOF15_Pos) /*!< 0x00008000 */
7211 #define DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15_Msk /*!< Channel 15 Synchronization overrun event flag */
7212
7213 /******************** Bits definition for DMAMUX_CFR register **************/
7214 #define DMAMUX_CFR_CSOF0_Pos (0U)
7215 #define DMAMUX_CFR_CSOF0_Msk (0x1UL << DMAMUX_CFR_CSOF0_Pos) /*!< 0x00000001 */
7216 #define DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0_Msk /*!< Channel 0 Clear synchronization overrun event flag */
7217 #define DMAMUX_CFR_CSOF1_Pos (1U)
7218 #define DMAMUX_CFR_CSOF1_Msk (0x1UL << DMAMUX_CFR_CSOF1_Pos) /*!< 0x00000002 */
7219 #define DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1_Msk /*!< Channel 1 Clear synchronization overrun event flag */
7220 #define DMAMUX_CFR_CSOF2_Pos (2U)
7221 #define DMAMUX_CFR_CSOF2_Msk (0x1UL << DMAMUX_CFR_CSOF2_Pos) /*!< 0x00000004 */
7222 #define DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2_Msk /*!< Channel 2 Clear synchronization overrun event flag */
7223 #define DMAMUX_CFR_CSOF3_Pos (3U)
7224 #define DMAMUX_CFR_CSOF3_Msk (0x1UL << DMAMUX_CFR_CSOF3_Pos) /*!< 0x00000008 */
7225 #define DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3_Msk /*!< Channel 3 Clear synchronization overrun event flag */
7226 #define DMAMUX_CFR_CSOF4_Pos (4U)
7227 #define DMAMUX_CFR_CSOF4_Msk (0x1UL << DMAMUX_CFR_CSOF4_Pos) /*!< 0x00000010 */
7228 #define DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4_Msk /*!< Channel 4 Clear synchronization overrun event flag */
7229 #define DMAMUX_CFR_CSOF5_Pos (5U)
7230 #define DMAMUX_CFR_CSOF5_Msk (0x1UL << DMAMUX_CFR_CSOF5_Pos) /*!< 0x00000020 */
7231 #define DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5_Msk /*!< Channel 5 Clear synchronization overrun event flag */
7232 #define DMAMUX_CFR_CSOF6_Pos (6U)
7233 #define DMAMUX_CFR_CSOF6_Msk (0x1UL << DMAMUX_CFR_CSOF6_Pos) /*!< 0x00000040 */
7234 #define DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6_Msk /*!< Channel 6 Clear synchronization overrun event flag */
7235 #define DMAMUX_CFR_CSOF7_Pos (7U)
7236 #define DMAMUX_CFR_CSOF7_Msk (0x1UL << DMAMUX_CFR_CSOF7_Pos) /*!< 0x00000080 */
7237 #define DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7_Msk /*!< Channel 7 Clear synchronization overrun event flag */
7238 #define DMAMUX_CFR_CSOF8_Pos (8U)
7239 #define DMAMUX_CFR_CSOF8_Msk (0x1UL << DMAMUX_CFR_CSOF8_Pos) /*!< 0x00000100 */
7240 #define DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8_Msk /*!< Channel 8 Clear synchronization overrun event flag */
7241 #define DMAMUX_CFR_CSOF9_Pos (9U)
7242 #define DMAMUX_CFR_CSOF9_Msk (0x1UL << DMAMUX_CFR_CSOF9_Pos) /*!< 0x00000200 */
7243 #define DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9_Msk /*!< Channel 9 Clear synchronization overrun event flag */
7244 #define DMAMUX_CFR_CSOF10_Pos (10U)
7245 #define DMAMUX_CFR_CSOF10_Msk (0x1UL << DMAMUX_CFR_CSOF10_Pos) /*!< 0x00000400 */
7246 #define DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10_Msk /*!< Channel 10 Clear synchronization overrun event flag */
7247 #define DMAMUX_CFR_CSOF11_Pos (11U)
7248 #define DMAMUX_CFR_CSOF11_Msk (0x1UL << DMAMUX_CFR_CSOF11_Pos) /*!< 0x00000800 */
7249 #define DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11_Msk /*!< Channel 11 Clear synchronization overrun event flag */
7250 #define DMAMUX_CFR_CSOF12_Pos (12U)
7251 #define DMAMUX_CFR_CSOF12_Msk (0x1UL << DMAMUX_CFR_CSOF12_Pos) /*!< 0x00001000 */
7252 #define DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12_Msk /*!< Channel 12 Clear synchronization overrun event flag */
7253 #define DMAMUX_CFR_CSOF13_Pos (13U)
7254 #define DMAMUX_CFR_CSOF13_Msk (0x1UL << DMAMUX_CFR_CSOF13_Pos) /*!< 0x00002000 */
7255 #define DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13_Msk /*!< Channel 13 Clear synchronization overrun event flag */
7256 #define DMAMUX_CFR_CSOF14_Pos (14U)
7257 #define DMAMUX_CFR_CSOF14_Msk (0x1UL << DMAMUX_CFR_CSOF14_Pos) /*!< 0x00004000 */
7258 #define DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14_Msk /*!< Channel 14 Clear synchronization overrun event flag */
7259 #define DMAMUX_CFR_CSOF15_Pos (15U)
7260 #define DMAMUX_CFR_CSOF15_Msk (0x1UL << DMAMUX_CFR_CSOF15_Pos) /*!< 0x00008000 */
7261 #define DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15_Msk /*!< Channel 15 Clear synchronization overrun event flag */
7262
7263 /******************** Bits definition for DMAMUX_RGxCR register ************/
7264 #define DMAMUX_RGxCR_SIG_ID_Pos (0U)
7265 #define DMAMUX_RGxCR_SIG_ID_Msk (0x1FUL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x0000001F */
7266 #define DMAMUX_RGxCR_SIG_ID DMAMUX_RGxCR_SIG_ID_Msk /*!< Signal identification */
7267 #define DMAMUX_RGxCR_SIG_ID_0 (0x01UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000001 */
7268 #define DMAMUX_RGxCR_SIG_ID_1 (0x02UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000002 */
7269 #define DMAMUX_RGxCR_SIG_ID_2 (0x04UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000004 */
7270 #define DMAMUX_RGxCR_SIG_ID_3 (0x08UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000008 */
7271 #define DMAMUX_RGxCR_SIG_ID_4 (0x10UL << DMAMUX_RGxCR_SIG_ID_Pos) /*!< 0x00000010 */
7272 #define DMAMUX_RGxCR_OIE_Pos (8U)
7273 #define DMAMUX_RGxCR_OIE_Msk (0x1UL << DMAMUX_RGxCR_OIE_Pos) /*!< 0x00000100 */
7274 #define DMAMUX_RGxCR_OIE DMAMUX_RGxCR_OIE_Msk /*!< Trigger overrun interrupt enable */
7275 #define DMAMUX_RGxCR_GE_Pos (16U)
7276 #define DMAMUX_RGxCR_GE_Msk (0x1UL << DMAMUX_RGxCR_GE_Pos) /*!< 0x00010000 */
7277 #define DMAMUX_RGxCR_GE DMAMUX_RGxCR_GE_Msk /*!< DMA request generator enable */
7278 #define DMAMUX_RGxCR_GPOL_Pos (17U)
7279 #define DMAMUX_RGxCR_GPOL_Msk (0x3UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00060000 */
7280 #define DMAMUX_RGxCR_GPOL DMAMUX_RGxCR_GPOL_Msk /*!< DMA request generator trigger polarity */
7281 #define DMAMUX_RGxCR_GPOL_0 (0x1UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00020000 */
7282 #define DMAMUX_RGxCR_GPOL_1 (0x2UL << DMAMUX_RGxCR_GPOL_Pos) /*!< 0x00040000 */
7283 #define DMAMUX_RGxCR_GNBREQ_Pos (19U)
7284 #define DMAMUX_RGxCR_GNBREQ_Msk (0x1FUL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00F80000 */
7285 #define DMAMUX_RGxCR_GNBREQ DMAMUX_RGxCR_GNBREQ_Msk /*!< Number of DMA requests to be generated */
7286 #define DMAMUX_RGxCR_GNBREQ_0 (0x01UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00080000 */
7287 #define DMAMUX_RGxCR_GNBREQ_1 (0x02UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00100000 */
7288 #define DMAMUX_RGxCR_GNBREQ_2 (0x04UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00200000 */
7289 #define DMAMUX_RGxCR_GNBREQ_3 (0x08UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00400000 */
7290 #define DMAMUX_RGxCR_GNBREQ_4 (0x10UL << DMAMUX_RGxCR_GNBREQ_Pos) /*!< 0x00800000 */
7291
7292 /******************** Bits definition for DMAMUX_RGSR register **************/
7293 #define DMAMUX_RGSR_OF0_Pos (0U)
7294 #define DMAMUX_RGSR_OF0_Msk (0x1UL << DMAMUX_RGSR_OF0_Pos) /*!< 0x00000001 */
7295 #define DMAMUX_RGSR_OF0 DMAMUX_RGSR_OF0_Msk /*!< Request generator channel 0 Trigger overrun event flag */
7296 #define DMAMUX_RGSR_OF1_Pos (1U)
7297 #define DMAMUX_RGSR_OF1_Msk (0x1UL << DMAMUX_RGSR_OF1_Pos) /*!< 0x00000002 */
7298 #define DMAMUX_RGSR_OF1 DMAMUX_RGSR_OF1_Msk /*!< Request generator channel 1 Trigger overrun event flag */
7299 #define DMAMUX_RGSR_OF2_Pos (2U)
7300 #define DMAMUX_RGSR_OF2_Msk (0x1UL << DMAMUX_RGSR_OF2_Pos) /*!< 0x00000004 */
7301 #define DMAMUX_RGSR_OF2 DMAMUX_RGSR_OF2_Msk /*!< Request generator channel 2 Trigger overrun event flag */
7302 #define DMAMUX_RGSR_OF3_Pos (3U)
7303 #define DMAMUX_RGSR_OF3_Msk (0x1UL << DMAMUX_RGSR_OF3_Pos) /*!< 0x00000008 */
7304 #define DMAMUX_RGSR_OF3 DMAMUX_RGSR_OF3_Msk /*!< Request generator channel 3 Trigger overrun event flag */
7305 #define DMAMUX_RGSR_OF4_Pos (4U)
7306 #define DMAMUX_RGSR_OF4_Msk (0x1UL << DMAMUX_RGSR_OF4_Pos) /*!< 0x00000010 */
7307 #define DMAMUX_RGSR_OF4 DMAMUX_RGSR_OF4_Msk /*!< Request generator channel 4 Trigger overrun event flag */
7308 #define DMAMUX_RGSR_OF5_Pos (5U)
7309 #define DMAMUX_RGSR_OF5_Msk (0x1UL << DMAMUX_RGSR_OF5_Pos) /*!< 0x00000020 */
7310 #define DMAMUX_RGSR_OF5 DMAMUX_RGSR_OF5_Msk /*!< Request generator channel 5 Trigger overrun event flag */
7311 #define DMAMUX_RGSR_OF6_Pos (6U)
7312 #define DMAMUX_RGSR_OF6_Msk (0x1UL << DMAMUX_RGSR_OF6_Pos) /*!< 0x00000040 */
7313 #define DMAMUX_RGSR_OF6 DMAMUX_RGSR_OF6_Msk /*!< Request generator channel 6 Trigger overrun event flag */
7314 #define DMAMUX_RGSR_OF7_Pos (7U)
7315 #define DMAMUX_RGSR_OF7_Msk (0x1UL << DMAMUX_RGSR_OF7_Pos) /*!< 0x00000080 */
7316 #define DMAMUX_RGSR_OF7 DMAMUX_RGSR_OF7_Msk /*!< Request generator channel 7 Trigger overrun event flag */
7317
7318 /******************** Bits definition for DMAMUX_RGCFR register **************/
7319 #define DMAMUX_RGCFR_COF0_Pos (0U)
7320 #define DMAMUX_RGCFR_COF0_Msk (0x1UL << DMAMUX_RGCFR_COF0_Pos) /*!< 0x00000001 */
7321 #define DMAMUX_RGCFR_COF0 DMAMUX_RGCFR_COF0_Msk /*!< Request generator channel 0 Clear trigger overrun event flag */
7322 #define DMAMUX_RGCFR_COF1_Pos (1U)
7323 #define DMAMUX_RGCFR_COF1_Msk (0x1UL << DMAMUX_RGCFR_COF1_Pos) /*!< 0x00000002 */
7324 #define DMAMUX_RGCFR_COF1 DMAMUX_RGCFR_COF1_Msk /*!< Request generator channel 1 Clear trigger overrun event flag */
7325 #define DMAMUX_RGCFR_COF2_Pos (2U)
7326 #define DMAMUX_RGCFR_COF2_Msk (0x1UL << DMAMUX_RGCFR_COF2_Pos) /*!< 0x00000004 */
7327 #define DMAMUX_RGCFR_COF2 DMAMUX_RGCFR_COF2_Msk /*!< Request generator channel 2 Clear trigger overrun event flag */
7328 #define DMAMUX_RGCFR_COF3_Pos (3U)
7329 #define DMAMUX_RGCFR_COF3_Msk (0x1UL << DMAMUX_RGCFR_COF3_Pos) /*!< 0x00000008 */
7330 #define DMAMUX_RGCFR_COF3 DMAMUX_RGCFR_COF3_Msk /*!< Request generator channel 3 Clear trigger overrun event flag */
7331 #define DMAMUX_RGCFR_COF4_Pos (4U)
7332 #define DMAMUX_RGCFR_COF4_Msk (0x1UL << DMAMUX_RGCFR_COF4_Pos) /*!< 0x00000010 */
7333 #define DMAMUX_RGCFR_COF4 DMAMUX_RGCFR_COF4_Msk /*!< Request generator channel 4 Clear trigger overrun event flag */
7334 #define DMAMUX_RGCFR_COF5_Pos (5U)
7335 #define DMAMUX_RGCFR_COF5_Msk (0x1UL << DMAMUX_RGCFR_COF5_Pos) /*!< 0x00000020 */
7336 #define DMAMUX_RGCFR_COF5 DMAMUX_RGCFR_COF5_Msk /*!< Request generator channel 5 Clear trigger overrun event flag */
7337 #define DMAMUX_RGCFR_COF6_Pos (6U)
7338 #define DMAMUX_RGCFR_COF6_Msk (0x1UL << DMAMUX_RGCFR_COF6_Pos) /*!< 0x00000040 */
7339 #define DMAMUX_RGCFR_COF6 DMAMUX_RGCFR_COF6_Msk /*!< Request generator channel 6 Clear trigger overrun event flag */
7340 #define DMAMUX_RGCFR_COF7_Pos (7U)
7341 #define DMAMUX_RGCFR_COF7_Msk (0x1UL << DMAMUX_RGCFR_COF7_Pos) /*!< 0x00000080 */
7342 #define DMAMUX_RGCFR_COF7 DMAMUX_RGCFR_COF7_Msk /*!< Request generator channel 7 Clear trigger overrun event flag */
7343
7344 /******************************************************************************/
7345 /* */
7346 /* AHB Master DMA2D Controller (DMA2D) */
7347 /* */
7348 /******************************************************************************/
7349
7350 /******************** Bit definition for DMA2D_CR register ******************/
7351
7352 #define DMA2D_CR_START_Pos (0U)
7353 #define DMA2D_CR_START_Msk (0x1UL << DMA2D_CR_START_Pos) /*!< 0x00000001 */
7354 #define DMA2D_CR_START DMA2D_CR_START_Msk /*!< Start transfer */
7355 #define DMA2D_CR_SUSP_Pos (1U)
7356 #define DMA2D_CR_SUSP_Msk (0x1UL << DMA2D_CR_SUSP_Pos) /*!< 0x00000002 */
7357 #define DMA2D_CR_SUSP DMA2D_CR_SUSP_Msk /*!< Suspend transfer */
7358 #define DMA2D_CR_ABORT_Pos (2U)
7359 #define DMA2D_CR_ABORT_Msk (0x1UL << DMA2D_CR_ABORT_Pos) /*!< 0x00000004 */
7360 #define DMA2D_CR_ABORT DMA2D_CR_ABORT_Msk /*!< Abort transfer */
7361 #define DMA2D_CR_LOM_Pos (6U)
7362 #define DMA2D_CR_LOM_Msk (0x1UL << DMA2D_CR_LOM_Pos) /*!< 0x00000040 */
7363 #define DMA2D_CR_LOM DMA2D_CR_LOM_Msk /*!< Line Offset Mode */
7364 #define DMA2D_CR_TEIE_Pos (8U)
7365 #define DMA2D_CR_TEIE_Msk (0x1UL << DMA2D_CR_TEIE_Pos) /*!< 0x00000100 */
7366 #define DMA2D_CR_TEIE DMA2D_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
7367 #define DMA2D_CR_TCIE_Pos (9U)
7368 #define DMA2D_CR_TCIE_Msk (0x1UL << DMA2D_CR_TCIE_Pos) /*!< 0x00000200 */
7369 #define DMA2D_CR_TCIE DMA2D_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
7370 #define DMA2D_CR_TWIE_Pos (10U)
7371 #define DMA2D_CR_TWIE_Msk (0x1UL << DMA2D_CR_TWIE_Pos) /*!< 0x00000400 */
7372 #define DMA2D_CR_TWIE DMA2D_CR_TWIE_Msk /*!< Transfer Watermark Interrupt Enable */
7373 #define DMA2D_CR_CAEIE_Pos (11U)
7374 #define DMA2D_CR_CAEIE_Msk (0x1UL << DMA2D_CR_CAEIE_Pos) /*!< 0x00000800 */
7375 #define DMA2D_CR_CAEIE DMA2D_CR_CAEIE_Msk /*!< CLUT Access Error Interrupt Enable */
7376 #define DMA2D_CR_CTCIE_Pos (12U)
7377 #define DMA2D_CR_CTCIE_Msk (0x1UL << DMA2D_CR_CTCIE_Pos) /*!< 0x00001000 */
7378 #define DMA2D_CR_CTCIE DMA2D_CR_CTCIE_Msk /*!< CLUT Transfer Complete Interrupt Enable */
7379 #define DMA2D_CR_CEIE_Pos (13U)
7380 #define DMA2D_CR_CEIE_Msk (0x1UL << DMA2D_CR_CEIE_Pos) /*!< 0x00002000 */
7381 #define DMA2D_CR_CEIE DMA2D_CR_CEIE_Msk /*!< Configuration Error Interrupt Enable */
7382 #define DMA2D_CR_MODE_Pos (16U)
7383 #define DMA2D_CR_MODE_Msk (0x7UL << DMA2D_CR_MODE_Pos) /*!< 0x00070000 */
7384 #define DMA2D_CR_MODE DMA2D_CR_MODE_Msk /*!< DMA2D Mode[2:0] */
7385 #define DMA2D_CR_MODE_0 (0x1UL << DMA2D_CR_MODE_Pos) /*!< 0x00010000 */
7386 #define DMA2D_CR_MODE_1 (0x2UL << DMA2D_CR_MODE_Pos) /*!< 0x00020000 */
7387 #define DMA2D_CR_MODE_2 (0x4UL << DMA2D_CR_MODE_Pos) /*!< 0x00040000 */
7388
7389 /******************** Bit definition for DMA2D_ISR register *****************/
7390
7391 #define DMA2D_ISR_TEIF_Pos (0U)
7392 #define DMA2D_ISR_TEIF_Msk (0x1UL << DMA2D_ISR_TEIF_Pos) /*!< 0x00000001 */
7393 #define DMA2D_ISR_TEIF DMA2D_ISR_TEIF_Msk /*!< Transfer Error Interrupt Flag */
7394 #define DMA2D_ISR_TCIF_Pos (1U)
7395 #define DMA2D_ISR_TCIF_Msk (0x1UL << DMA2D_ISR_TCIF_Pos) /*!< 0x00000002 */
7396 #define DMA2D_ISR_TCIF DMA2D_ISR_TCIF_Msk /*!< Transfer Complete Interrupt Flag */
7397 #define DMA2D_ISR_TWIF_Pos (2U)
7398 #define DMA2D_ISR_TWIF_Msk (0x1UL << DMA2D_ISR_TWIF_Pos) /*!< 0x00000004 */
7399 #define DMA2D_ISR_TWIF DMA2D_ISR_TWIF_Msk /*!< Transfer Watermark Interrupt Flag */
7400 #define DMA2D_ISR_CAEIF_Pos (3U)
7401 #define DMA2D_ISR_CAEIF_Msk (0x1UL << DMA2D_ISR_CAEIF_Pos) /*!< 0x00000008 */
7402 #define DMA2D_ISR_CAEIF DMA2D_ISR_CAEIF_Msk /*!< CLUT Access Error Interrupt Flag */
7403 #define DMA2D_ISR_CTCIF_Pos (4U)
7404 #define DMA2D_ISR_CTCIF_Msk (0x1UL << DMA2D_ISR_CTCIF_Pos) /*!< 0x00000010 */
7405 #define DMA2D_ISR_CTCIF DMA2D_ISR_CTCIF_Msk /*!< CLUT Transfer Complete Interrupt Flag */
7406 #define DMA2D_ISR_CEIF_Pos (5U)
7407 #define DMA2D_ISR_CEIF_Msk (0x1UL << DMA2D_ISR_CEIF_Pos) /*!< 0x00000020 */
7408 #define DMA2D_ISR_CEIF DMA2D_ISR_CEIF_Msk /*!< Configuration Error Interrupt Flag */
7409
7410 /******************** Bit definition for DMA2D_IFCR register ****************/
7411
7412 #define DMA2D_IFCR_CTEIF_Pos (0U)
7413 #define DMA2D_IFCR_CTEIF_Msk (0x1UL << DMA2D_IFCR_CTEIF_Pos) /*!< 0x00000001 */
7414 #define DMA2D_IFCR_CTEIF DMA2D_IFCR_CTEIF_Msk /*!< Clears Transfer Error Interrupt Flag */
7415 #define DMA2D_IFCR_CTCIF_Pos (1U)
7416 #define DMA2D_IFCR_CTCIF_Msk (0x1UL << DMA2D_IFCR_CTCIF_Pos) /*!< 0x00000002 */
7417 #define DMA2D_IFCR_CTCIF DMA2D_IFCR_CTCIF_Msk /*!< Clears Transfer Complete Interrupt Flag */
7418 #define DMA2D_IFCR_CTWIF_Pos (2U)
7419 #define DMA2D_IFCR_CTWIF_Msk (0x1UL << DMA2D_IFCR_CTWIF_Pos) /*!< 0x00000004 */
7420 #define DMA2D_IFCR_CTWIF DMA2D_IFCR_CTWIF_Msk /*!< Clears Transfer Watermark Interrupt Flag */
7421 #define DMA2D_IFCR_CAECIF_Pos (3U)
7422 #define DMA2D_IFCR_CAECIF_Msk (0x1UL << DMA2D_IFCR_CAECIF_Pos) /*!< 0x00000008 */
7423 #define DMA2D_IFCR_CAECIF DMA2D_IFCR_CAECIF_Msk /*!< Clears CLUT Access Error Interrupt Flag */
7424 #define DMA2D_IFCR_CCTCIF_Pos (4U)
7425 #define DMA2D_IFCR_CCTCIF_Msk (0x1UL << DMA2D_IFCR_CCTCIF_Pos) /*!< 0x00000010 */
7426 #define DMA2D_IFCR_CCTCIF DMA2D_IFCR_CCTCIF_Msk /*!< Clears CLUT Transfer Complete Interrupt Flag */
7427 #define DMA2D_IFCR_CCEIF_Pos (5U)
7428 #define DMA2D_IFCR_CCEIF_Msk (0x1UL << DMA2D_IFCR_CCEIF_Pos) /*!< 0x00000020 */
7429 #define DMA2D_IFCR_CCEIF DMA2D_IFCR_CCEIF_Msk /*!< Clears Configuration Error Interrupt Flag */
7430
7431 /******************** Bit definition for DMA2D_FGMAR register ***************/
7432
7433 #define DMA2D_FGMAR_MA_Pos (0U)
7434 #define DMA2D_FGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7435 #define DMA2D_FGMAR_MA DMA2D_FGMAR_MA_Msk /*!< Foreground Memory Address */
7436
7437 /******************** Bit definition for DMA2D_FGOR register ****************/
7438
7439 #define DMA2D_FGOR_LO_Pos (0U)
7440 #define DMA2D_FGOR_LO_Msk (0xFFFFUL << DMA2D_FGOR_LO_Pos) /*!< 0x0000FFFF */
7441 #define DMA2D_FGOR_LO DMA2D_FGOR_LO_Msk /*!< Line Offset */
7442
7443 /******************** Bit definition for DMA2D_BGMAR register ***************/
7444
7445 #define DMA2D_BGMAR_MA_Pos (0U)
7446 #define DMA2D_BGMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGMAR_MA_Pos) /*!< 0xFFFFFFFF */
7447 #define DMA2D_BGMAR_MA DMA2D_BGMAR_MA_Msk /*!< Background Memory Address */
7448
7449 /******************** Bit definition for DMA2D_BGOR register ****************/
7450
7451 #define DMA2D_BGOR_LO_Pos (0U)
7452 #define DMA2D_BGOR_LO_Msk (0xFFFFUL << DMA2D_BGOR_LO_Pos) /*!< 0x0000FFFF */
7453 #define DMA2D_BGOR_LO DMA2D_BGOR_LO_Msk /*!< Line Offset */
7454
7455 /******************** Bit definition for DMA2D_FGPFCCR register *************/
7456
7457 #define DMA2D_FGPFCCR_CM_Pos (0U)
7458 #define DMA2D_FGPFCCR_CM_Msk (0xFUL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x0000000F */
7459 #define DMA2D_FGPFCCR_CM DMA2D_FGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7460 #define DMA2D_FGPFCCR_CM_0 (0x1UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000001 */
7461 #define DMA2D_FGPFCCR_CM_1 (0x2UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000002 */
7462 #define DMA2D_FGPFCCR_CM_2 (0x4UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000004 */
7463 #define DMA2D_FGPFCCR_CM_3 (0x8UL << DMA2D_FGPFCCR_CM_Pos) /*!< 0x00000008 */
7464 #define DMA2D_FGPFCCR_CCM_Pos (4U)
7465 #define DMA2D_FGPFCCR_CCM_Msk (0x1UL << DMA2D_FGPFCCR_CCM_Pos) /*!< 0x00000010 */
7466 #define DMA2D_FGPFCCR_CCM DMA2D_FGPFCCR_CCM_Msk /*!< CLUT Color mode */
7467 #define DMA2D_FGPFCCR_START_Pos (5U)
7468 #define DMA2D_FGPFCCR_START_Msk (0x1UL << DMA2D_FGPFCCR_START_Pos) /*!< 0x00000020 */
7469 #define DMA2D_FGPFCCR_START DMA2D_FGPFCCR_START_Msk /*!< Start */
7470 #define DMA2D_FGPFCCR_CS_Pos (8U)
7471 #define DMA2D_FGPFCCR_CS_Msk (0xFFUL << DMA2D_FGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7472 #define DMA2D_FGPFCCR_CS DMA2D_FGPFCCR_CS_Msk /*!< CLUT size */
7473 #define DMA2D_FGPFCCR_AM_Pos (16U)
7474 #define DMA2D_FGPFCCR_AM_Msk (0x3UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00030000 */
7475 #define DMA2D_FGPFCCR_AM DMA2D_FGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7476 #define DMA2D_FGPFCCR_AM_0 (0x1UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00010000 */
7477 #define DMA2D_FGPFCCR_AM_1 (0x2UL << DMA2D_FGPFCCR_AM_Pos) /*!< 0x00020000 */
7478 #define DMA2D_FGPFCCR_CSS_Pos (18U)
7479 #define DMA2D_FGPFCCR_CSS_Msk (0x3UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x000C0000 */
7480 #define DMA2D_FGPFCCR_CSS DMA2D_FGPFCCR_CSS_Msk /* !< Chroma Sub-Sampling */
7481 #define DMA2D_FGPFCCR_CSS_0 (0x1UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00040000 */
7482 #define DMA2D_FGPFCCR_CSS_1 (0x2UL << DMA2D_FGPFCCR_CSS_Pos) /*!< 0x00080000 */
7483 #define DMA2D_FGPFCCR_AI_Pos (20U)
7484 #define DMA2D_FGPFCCR_AI_Msk (0x1UL << DMA2D_FGPFCCR_AI_Pos) /*!< 0x00100000 */
7485 #define DMA2D_FGPFCCR_AI DMA2D_FGPFCCR_AI_Msk /*!< Foreground Input Alpha Inverted */
7486 #define DMA2D_FGPFCCR_RBS_Pos (21U)
7487 #define DMA2D_FGPFCCR_RBS_Msk (0x1UL << DMA2D_FGPFCCR_RBS_Pos) /*!< 0x00200000 */
7488 #define DMA2D_FGPFCCR_RBS DMA2D_FGPFCCR_RBS_Msk /*!< Foreground Input Red Blue Swap */
7489 #define DMA2D_FGPFCCR_ALPHA_Pos (24U)
7490 #define DMA2D_FGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_FGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7491 #define DMA2D_FGPFCCR_ALPHA DMA2D_FGPFCCR_ALPHA_Msk /*!< Alpha value */
7492
7493 /******************** Bit definition for DMA2D_FGCOLR register **************/
7494
7495 #define DMA2D_FGCOLR_BLUE_Pos (0U)
7496 #define DMA2D_FGCOLR_BLUE_Msk (0xFFUL << DMA2D_FGCOLR_BLUE_Pos) /*!< 0x000000FF */
7497 #define DMA2D_FGCOLR_BLUE DMA2D_FGCOLR_BLUE_Msk /*!< Foreground Blue Value */
7498 #define DMA2D_FGCOLR_GREEN_Pos (8U)
7499 #define DMA2D_FGCOLR_GREEN_Msk (0xFFUL << DMA2D_FGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7500 #define DMA2D_FGCOLR_GREEN DMA2D_FGCOLR_GREEN_Msk /*!< Foreground Green Value */
7501 #define DMA2D_FGCOLR_RED_Pos (16U)
7502 #define DMA2D_FGCOLR_RED_Msk (0xFFUL << DMA2D_FGCOLR_RED_Pos) /*!< 0x00FF0000 */
7503 #define DMA2D_FGCOLR_RED DMA2D_FGCOLR_RED_Msk /*!< Foreground Red Value */
7504
7505 /******************** Bit definition for DMA2D_BGPFCCR register *************/
7506
7507 #define DMA2D_BGPFCCR_CM_Pos (0U)
7508 #define DMA2D_BGPFCCR_CM_Msk (0xFUL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x0000000F */
7509 #define DMA2D_BGPFCCR_CM DMA2D_BGPFCCR_CM_Msk /*!< Input color mode CM[3:0] */
7510 #define DMA2D_BGPFCCR_CM_0 (0x1UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000001 */
7511 #define DMA2D_BGPFCCR_CM_1 (0x2UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000002 */
7512 #define DMA2D_BGPFCCR_CM_2 (0x4UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000004 */
7513 #define DMA2D_BGPFCCR_CM_3 (0x8UL << DMA2D_BGPFCCR_CM_Pos) /*!< 0x00000008 */
7514 #define DMA2D_BGPFCCR_CCM_Pos (4U)
7515 #define DMA2D_BGPFCCR_CCM_Msk (0x1UL << DMA2D_BGPFCCR_CCM_Pos) /*!< 0x00000010 */
7516 #define DMA2D_BGPFCCR_CCM DMA2D_BGPFCCR_CCM_Msk /*!< CLUT Color mode */
7517 #define DMA2D_BGPFCCR_START_Pos (5U)
7518 #define DMA2D_BGPFCCR_START_Msk (0x1UL << DMA2D_BGPFCCR_START_Pos) /*!< 0x00000020 */
7519 #define DMA2D_BGPFCCR_START DMA2D_BGPFCCR_START_Msk /*!< Start */
7520 #define DMA2D_BGPFCCR_CS_Pos (8U)
7521 #define DMA2D_BGPFCCR_CS_Msk (0xFFUL << DMA2D_BGPFCCR_CS_Pos) /*!< 0x0000FF00 */
7522 #define DMA2D_BGPFCCR_CS DMA2D_BGPFCCR_CS_Msk /*!< CLUT size */
7523 #define DMA2D_BGPFCCR_AM_Pos (16U)
7524 #define DMA2D_BGPFCCR_AM_Msk (0x3UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00030000 */
7525 #define DMA2D_BGPFCCR_AM DMA2D_BGPFCCR_AM_Msk /*!< Alpha mode AM[1:0] */
7526 #define DMA2D_BGPFCCR_AM_0 (0x1UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00010000 */
7527 #define DMA2D_BGPFCCR_AM_1 (0x2UL << DMA2D_BGPFCCR_AM_Pos) /*!< 0x00020000 */
7528 #define DMA2D_BGPFCCR_AI_Pos (20U)
7529 #define DMA2D_BGPFCCR_AI_Msk (0x1UL << DMA2D_BGPFCCR_AI_Pos) /*!< 0x00100000 */
7530 #define DMA2D_BGPFCCR_AI DMA2D_BGPFCCR_AI_Msk /*!< background Input Alpha Inverted */
7531 #define DMA2D_BGPFCCR_RBS_Pos (21U)
7532 #define DMA2D_BGPFCCR_RBS_Msk (0x1UL << DMA2D_BGPFCCR_RBS_Pos) /*!< 0x00200000 */
7533 #define DMA2D_BGPFCCR_RBS DMA2D_BGPFCCR_RBS_Msk /*!< Background Input Red Blue Swap */
7534 #define DMA2D_BGPFCCR_ALPHA_Pos (24U)
7535 #define DMA2D_BGPFCCR_ALPHA_Msk (0xFFUL << DMA2D_BGPFCCR_ALPHA_Pos) /*!< 0xFF000000 */
7536 #define DMA2D_BGPFCCR_ALPHA DMA2D_BGPFCCR_ALPHA_Msk /*!< background Input Alpha value */
7537
7538 /******************** Bit definition for DMA2D_BGCOLR register **************/
7539
7540 #define DMA2D_BGCOLR_BLUE_Pos (0U)
7541 #define DMA2D_BGCOLR_BLUE_Msk (0xFFUL << DMA2D_BGCOLR_BLUE_Pos) /*!< 0x000000FF */
7542 #define DMA2D_BGCOLR_BLUE DMA2D_BGCOLR_BLUE_Msk /*!< Background Blue Value */
7543 #define DMA2D_BGCOLR_GREEN_Pos (8U)
7544 #define DMA2D_BGCOLR_GREEN_Msk (0xFFUL << DMA2D_BGCOLR_GREEN_Pos) /*!< 0x0000FF00 */
7545 #define DMA2D_BGCOLR_GREEN DMA2D_BGCOLR_GREEN_Msk /*!< Background Green Value */
7546 #define DMA2D_BGCOLR_RED_Pos (16U)
7547 #define DMA2D_BGCOLR_RED_Msk (0xFFUL << DMA2D_BGCOLR_RED_Pos) /*!< 0x00FF0000 */
7548 #define DMA2D_BGCOLR_RED DMA2D_BGCOLR_RED_Msk /*!< Background Red Value */
7549
7550 /******************** Bit definition for DMA2D_FGCMAR register **************/
7551
7552 #define DMA2D_FGCMAR_MA_Pos (0U)
7553 #define DMA2D_FGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_FGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7554 #define DMA2D_FGCMAR_MA DMA2D_FGCMAR_MA_Msk /*!< Foreground CLUT Memory Address */
7555
7556 /******************** Bit definition for DMA2D_BGCMAR register **************/
7557
7558 #define DMA2D_BGCMAR_MA_Pos (0U)
7559 #define DMA2D_BGCMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_BGCMAR_MA_Pos) /*!< 0xFFFFFFFF */
7560 #define DMA2D_BGCMAR_MA DMA2D_BGCMAR_MA_Msk /*!< Background CLUT Memory Address */
7561
7562 /******************** Bit definition for DMA2D_OPFCCR register **************/
7563
7564 #define DMA2D_OPFCCR_CM_Pos (0U)
7565 #define DMA2D_OPFCCR_CM_Msk (0x7UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000007 */
7566 #define DMA2D_OPFCCR_CM DMA2D_OPFCCR_CM_Msk /*!< Output Color mode CM[2:0] */
7567 #define DMA2D_OPFCCR_CM_0 (0x1UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000001 */
7568 #define DMA2D_OPFCCR_CM_1 (0x2UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000002 */
7569 #define DMA2D_OPFCCR_CM_2 (0x4UL << DMA2D_OPFCCR_CM_Pos) /*!< 0x00000004 */
7570 #define DMA2D_OPFCCR_SB_Pos (8U)
7571 #define DMA2D_OPFCCR_SB_Msk (0x1UL << DMA2D_OPFCCR_SB_Pos) /*!< 0x00000100 */
7572 #define DMA2D_OPFCCR_SB DMA2D_OPFCCR_SB_Msk /*!< Swap Bytes */
7573 #define DMA2D_OPFCCR_AI_Pos (20U)
7574 #define DMA2D_OPFCCR_AI_Msk (0x1UL << DMA2D_OPFCCR_AI_Pos) /*!< 0x00100000 */
7575 #define DMA2D_OPFCCR_AI DMA2D_OPFCCR_AI_Msk /*!< Output Alpha Inverted */
7576 #define DMA2D_OPFCCR_RBS_Pos (21U)
7577 #define DMA2D_OPFCCR_RBS_Msk (0x1UL << DMA2D_OPFCCR_RBS_Pos) /*!< 0x00200000 */
7578 #define DMA2D_OPFCCR_RBS DMA2D_OPFCCR_RBS_Msk /*!< Output Red Blue Swap */
7579
7580 /******************** Bit definition for DMA2D_OCOLR register ***************/
7581
7582 /*!<Mode_ARGB8888/RGB888 */
7583
7584 #define DMA2D_OCOLR_BLUE_1_Pos (0U)
7585 #define DMA2D_OCOLR_BLUE_1_Msk (0xFFUL <<DMA2D_OCOLR_BLUE_1_Pos) /*0x000000FFU*/
7586 #define DMA2D_OCOLR_BLUE_1 DMA2D_OCOLR_BLUE_1_Msk /*!< Output BLUE Value */
7587 #define DMA2D_OCOLR_GREEN_1_Pos (8U)
7588 #define DMA2D_OCOLR_GREEN_1_Msk (0xFFUL<<DMA2D_OCOLR_GREEN_1_Pos) /*0x0000FF00U)*/
7589 #define DMA2D_OCOLR_GREEN_1 DMA2D_OCOLR_GREEN_1_Msk /*!< Output GREEN Value */
7590 #define DMA2D_OCOLR_RED_1_Pos (16U)
7591 #define DMA2D_OCOLR_RED_1_Msk (0xFFUL << DMA2D_OCOLR_RED_1_Pos) /*0x00FF0000U */
7592 #define DMA2D_OCOLR_RED_1 DMA2D_OCOLR_RED_1_Msk /*!< Output Red Value */
7593 #define DMA2D_OCOLR_ALPHA_1_Pos (24U)
7594 #define DMA2D_OCOLR_ALPHA_1_Msk (0xFFUL << DMA2D_OCOLR_ALPHA_1_Pos) /*0xFF000000U*/
7595 #define DMA2D_OCOLR_ALPHA_1 DMA2D_OCOLR_ALPHA_1_Msk /*!< Output Alpha Channel Value */
7596
7597 /*!<Mode_RGB565 */
7598 #define DMA2D_OCOLR_BLUE_2_Pos (0U)
7599 #define DMA2D_OCOLR_BLUE_2_Msk (0x1FUL <<DMA2D_OCOLR_BLUE_2_Pos) /*0x0000001FU*/
7600 #define DMA2D_OCOLR_BLUE_2 DMA2D_OCOLR_BLUE_2_Msk /*!< Output BLUE Value */
7601 #define DMA2D_OCOLR_GREEN_2_Pos (5U)
7602 #define DMA2D_OCOLR_GREEN_2_Msk (0x7EUL << DMA2D_OCOLR_GREEN_2_Pos) /* 0x000007E0U */
7603 #define DMA2D_OCOLR_GREEN_2 DMA2D_OCOLR_GREEN_2_Msk /*!< Output GREEN Value */
7604 #define DMA2D_OCOLR_RED_2_Pos (11U)
7605 #define DMA2D_OCOLR_RED_2_Msk (0xF8UL<<DMA2D_OCOLR_RED_2_Pos) /*0x0000F800U*/
7606 #define DMA2D_OCOLR_RED_2 DMA2D_OCOLR_RED_2_Msk /*!< Output Red Value */
7607
7608 /*!<Mode_ARGB1555 */
7609 #define DMA2D_OCOLR_BLUE_3_Pos (0U)
7610 #define DMA2D_OCOLR_BLUE_3_Msk (0x1FUL << DMA2D_OCOLR_BLUE_3_Pos) /*0x0000001FU*/
7611 #define DMA2D_OCOLR_BLUE_3 DMA2D_OCOLR_BLUE_3_Msk /*!< Output BLUE Value */
7612 #define DMA2D_OCOLR_GREEN_3_Pos (5U)
7613 #define DMA2D_OCOLR_GREEN_3_Msk (0x3EUL << DMA2D_OCOLR_GREEN_3_Pos) /*0x000003E0U*/
7614 #define DMA2D_OCOLR_GREEN_3 DMA2D_OCOLR_GREEN_3_Msk /*!< Output GREEN Value */
7615 #define DMA2D_OCOLR_RED_3_Pos (10U)
7616 #define DMA2D_OCOLR_RED_3_Msk (0x7CUL << DMA2D_OCOLR_RED_3_Pos) /* 0x00007C00U*/
7617 #define DMA2D_OCOLR_RED_3 DMA2D_OCOLR_RED_3_Msk /*!< Output Red Value */
7618 #define DMA2D_OCOLR_ALPHA_3_Pos (15U)
7619 #define DMA2D_OCOLR_ALPHA_3_Msk (0x1UL << DMA2D_OCOLR_ALPHA_3_Pos) /*0x00008000U*/
7620 #define DMA2D_OCOLR_ALPHA_3 DMA2D_OCOLR_ALPHA_3_Msk /*!< Output Alpha Channel Value */
7621
7622 /*!<Mode_ARGB4444 */
7623 #define DMA2D_OCOLR_BLUE_4_Pos (0U)
7624 #define DMA2D_OCOLR_BLUE_4_Msk (0xFUL << DMA2D_OCOLR_BLUE_4_Pos) /*0x0000000FU*/
7625 #define DMA2D_OCOLR_BLUE_4 DMA2D_OCOLR_BLUE_4_Msk /*!< Output BLUE Value */
7626 #define DMA2D_OCOLR_GREEN_4_Pos (4U)
7627 #define DMA2D_OCOLR_GREEN_4_Msk (0xFUL << DMA2D_OCOLR_GREEN_4_Pos) /*0x000000F0U*/
7628 #define DMA2D_OCOLR_GREEN_4 DMA2D_OCOLR_GREEN_4_Msk /*!< Output GREEN Value */
7629 #define DMA2D_OCOLR_RED_4_Pos (8U)
7630 #define DMA2D_OCOLR_RED_4_Msk (0xFUL << DMA2D_OCOLR_RED_4_Pos) /*0x00000F00U*/
7631 #define DMA2D_OCOLR_RED_4 DMA2D_OCOLR_RED_4_Msk /*!< Output Red Value */
7632 #define DMA2D_OCOLR_ALPHA_4_Pos (12U)
7633 #define DMA2D_OCOLR_ALPHA_4_Msk (0xFUL << DMA2D_OCOLR_ALPHA_4_Pos) /*0x0000F000U*/
7634 #define DMA2D_OCOLR_ALPHA_4 DMA2D_OCOLR_ALPHA_4_Msk /*!< Output Alpha Channel Value */
7635
7636 /******************** Bit definition for DMA2D_OMAR register ****************/
7637
7638 #define DMA2D_OMAR_MA_Pos (0U)
7639 #define DMA2D_OMAR_MA_Msk (0xFFFFFFFFUL << DMA2D_OMAR_MA_Pos) /*!< 0xFFFFFFFF */
7640 #define DMA2D_OMAR_MA DMA2D_OMAR_MA_Msk /*!< Output Memory Address */
7641
7642 /******************** Bit definition for DMA2D_OOR register *****************/
7643
7644 #define DMA2D_OOR_LO_Pos (0U)
7645 #define DMA2D_OOR_LO_Msk (0xFFFFUL << DMA2D_OOR_LO_Pos) /*!< 0x0000FFFF */
7646 #define DMA2D_OOR_LO DMA2D_OOR_LO_Msk /*!< Output Line Offset */
7647
7648 /******************** Bit definition for DMA2D_NLR register *****************/
7649
7650 #define DMA2D_NLR_NL_Pos (0U)
7651 #define DMA2D_NLR_NL_Msk (0xFFFFUL << DMA2D_NLR_NL_Pos) /*!< 0x0000FFFF */
7652 #define DMA2D_NLR_NL DMA2D_NLR_NL_Msk /*!< Number of Lines */
7653 #define DMA2D_NLR_PL_Pos (16U)
7654 #define DMA2D_NLR_PL_Msk (0x3FFFUL << DMA2D_NLR_PL_Pos) /*!< 0x3FFF0000 */
7655 #define DMA2D_NLR_PL DMA2D_NLR_PL_Msk /*!< Pixel per Lines */
7656
7657 /******************** Bit definition for DMA2D_LWR register *****************/
7658
7659 #define DMA2D_LWR_LW_Pos (0U)
7660 #define DMA2D_LWR_LW_Msk (0xFFFFUL << DMA2D_LWR_LW_Pos) /*!< 0x0000FFFF */
7661 #define DMA2D_LWR_LW DMA2D_LWR_LW_Msk /*!< Line Watermark */
7662
7663 /******************** Bit definition for DMA2D_AMTCR register ***************/
7664
7665 #define DMA2D_AMTCR_EN_Pos (0U)
7666 #define DMA2D_AMTCR_EN_Msk (0x1UL << DMA2D_AMTCR_EN_Pos) /*!< 0x00000001 */
7667 #define DMA2D_AMTCR_EN DMA2D_AMTCR_EN_Msk /*!< Enable */
7668 #define DMA2D_AMTCR_DT_Pos (8U)
7669 #define DMA2D_AMTCR_DT_Msk (0xFFUL << DMA2D_AMTCR_DT_Pos) /*!< 0x0000FF00 */
7670 #define DMA2D_AMTCR_DT DMA2D_AMTCR_DT_Msk /*!< Dead Time */
7671
7672
7673 /******************** Bit definition for DMA2D_FGCLUT register **************/
7674
7675 /******************** Bit definition for DMA2D_BGCLUT register **************/
7676
7677
7678 /******************************************************************************/
7679 /* */
7680 /* External Interrupt/Event Controller */
7681 /* */
7682 /******************************************************************************/
7683 /****************** Bit definition for EXTI_RTSR1 register *******************/
7684 #define EXTI_RTSR1_TR_Pos (0U)
7685 #define EXTI_RTSR1_TR_Msk (0x3FFFFFUL << EXTI_RTSR1_TR_Pos) /*!< 0x003FFFFF */
7686 #define EXTI_RTSR1_TR EXTI_RTSR1_TR_Msk /*!< Rising trigger event configuration bit */
7687 #define EXTI_RTSR1_TR0_Pos (0U)
7688 #define EXTI_RTSR1_TR0_Msk (0x1UL << EXTI_RTSR1_TR0_Pos) /*!< 0x00000001 */
7689 #define EXTI_RTSR1_TR0 EXTI_RTSR1_TR0_Msk /*!< Rising trigger event configuration bit of line 0 */
7690 #define EXTI_RTSR1_TR1_Pos (1U)
7691 #define EXTI_RTSR1_TR1_Msk (0x1UL << EXTI_RTSR1_TR1_Pos) /*!< 0x00000002 */
7692 #define EXTI_RTSR1_TR1 EXTI_RTSR1_TR1_Msk /*!< Rising trigger event configuration bit of line 1 */
7693 #define EXTI_RTSR1_TR2_Pos (2U)
7694 #define EXTI_RTSR1_TR2_Msk (0x1UL << EXTI_RTSR1_TR2_Pos) /*!< 0x00000004 */
7695 #define EXTI_RTSR1_TR2 EXTI_RTSR1_TR2_Msk /*!< Rising trigger event configuration bit of line 2 */
7696 #define EXTI_RTSR1_TR3_Pos (3U)
7697 #define EXTI_RTSR1_TR3_Msk (0x1UL << EXTI_RTSR1_TR3_Pos) /*!< 0x00000008 */
7698 #define EXTI_RTSR1_TR3 EXTI_RTSR1_TR3_Msk /*!< Rising trigger event configuration bit of line 3 */
7699 #define EXTI_RTSR1_TR4_Pos (4U)
7700 #define EXTI_RTSR1_TR4_Msk (0x1UL << EXTI_RTSR1_TR4_Pos) /*!< 0x00000010 */
7701 #define EXTI_RTSR1_TR4 EXTI_RTSR1_TR4_Msk /*!< Rising trigger event configuration bit of line 4 */
7702 #define EXTI_RTSR1_TR5_Pos (5U)
7703 #define EXTI_RTSR1_TR5_Msk (0x1UL << EXTI_RTSR1_TR5_Pos) /*!< 0x00000020 */
7704 #define EXTI_RTSR1_TR5 EXTI_RTSR1_TR5_Msk /*!< Rising trigger event configuration bit of line 5 */
7705 #define EXTI_RTSR1_TR6_Pos (6U)
7706 #define EXTI_RTSR1_TR6_Msk (0x1UL << EXTI_RTSR1_TR6_Pos) /*!< 0x00000040 */
7707 #define EXTI_RTSR1_TR6 EXTI_RTSR1_TR6_Msk /*!< Rising trigger event configuration bit of line 6 */
7708 #define EXTI_RTSR1_TR7_Pos (7U)
7709 #define EXTI_RTSR1_TR7_Msk (0x1UL << EXTI_RTSR1_TR7_Pos) /*!< 0x00000080 */
7710 #define EXTI_RTSR1_TR7 EXTI_RTSR1_TR7_Msk /*!< Rising trigger event configuration bit of line 7 */
7711 #define EXTI_RTSR1_TR8_Pos (8U)
7712 #define EXTI_RTSR1_TR8_Msk (0x1UL << EXTI_RTSR1_TR8_Pos) /*!< 0x00000100 */
7713 #define EXTI_RTSR1_TR8 EXTI_RTSR1_TR8_Msk /*!< Rising trigger event configuration bit of line 8 */
7714 #define EXTI_RTSR1_TR9_Pos (9U)
7715 #define EXTI_RTSR1_TR9_Msk (0x1UL << EXTI_RTSR1_TR9_Pos) /*!< 0x00000200 */
7716 #define EXTI_RTSR1_TR9 EXTI_RTSR1_TR9_Msk /*!< Rising trigger event configuration bit of line 9 */
7717 #define EXTI_RTSR1_TR10_Pos (10U)
7718 #define EXTI_RTSR1_TR10_Msk (0x1UL << EXTI_RTSR1_TR10_Pos) /*!< 0x00000400 */
7719 #define EXTI_RTSR1_TR10 EXTI_RTSR1_TR10_Msk /*!< Rising trigger event configuration bit of line 10 */
7720 #define EXTI_RTSR1_TR11_Pos (11U)
7721 #define EXTI_RTSR1_TR11_Msk (0x1UL << EXTI_RTSR1_TR11_Pos) /*!< 0x00000800 */
7722 #define EXTI_RTSR1_TR11 EXTI_RTSR1_TR11_Msk /*!< Rising trigger event configuration bit of line 11 */
7723 #define EXTI_RTSR1_TR12_Pos (12U)
7724 #define EXTI_RTSR1_TR12_Msk (0x1UL << EXTI_RTSR1_TR12_Pos) /*!< 0x00001000 */
7725 #define EXTI_RTSR1_TR12 EXTI_RTSR1_TR12_Msk /*!< Rising trigger event configuration bit of line 12 */
7726 #define EXTI_RTSR1_TR13_Pos (13U)
7727 #define EXTI_RTSR1_TR13_Msk (0x1UL << EXTI_RTSR1_TR13_Pos) /*!< 0x00002000 */
7728 #define EXTI_RTSR1_TR13 EXTI_RTSR1_TR13_Msk /*!< Rising trigger event configuration bit of line 13 */
7729 #define EXTI_RTSR1_TR14_Pos (14U)
7730 #define EXTI_RTSR1_TR14_Msk (0x1UL << EXTI_RTSR1_TR14_Pos) /*!< 0x00004000 */
7731 #define EXTI_RTSR1_TR14 EXTI_RTSR1_TR14_Msk /*!< Rising trigger event configuration bit of line 14 */
7732 #define EXTI_RTSR1_TR15_Pos (15U)
7733 #define EXTI_RTSR1_TR15_Msk (0x1UL << EXTI_RTSR1_TR15_Pos) /*!< 0x00008000 */
7734 #define EXTI_RTSR1_TR15 EXTI_RTSR1_TR15_Msk /*!< Rising trigger event configuration bit of line 15 */
7735 #define EXTI_RTSR1_TR16_Pos (16U)
7736 #define EXTI_RTSR1_TR16_Msk (0x1UL << EXTI_RTSR1_TR16_Pos) /*!< 0x00010000 */
7737 #define EXTI_RTSR1_TR16 EXTI_RTSR1_TR16_Msk /*!< Rising trigger event configuration bit of line 16 */
7738 #define EXTI_RTSR1_TR17_Pos (17U)
7739 #define EXTI_RTSR1_TR17_Msk (0x1UL << EXTI_RTSR1_TR17_Pos) /*!< 0x00020000 */
7740 #define EXTI_RTSR1_TR17 EXTI_RTSR1_TR17_Msk /*!< Rising trigger event configuration bit of line 17 */
7741 #define EXTI_RTSR1_TR18_Pos (18U)
7742 #define EXTI_RTSR1_TR18_Msk (0x1UL << EXTI_RTSR1_TR18_Pos) /*!< 0x00040000 */
7743 #define EXTI_RTSR1_TR18 EXTI_RTSR1_TR18_Msk /*!< Rising trigger event configuration bit of line 18 */
7744 #define EXTI_RTSR1_TR19_Pos (19U)
7745 #define EXTI_RTSR1_TR19_Msk (0x1UL << EXTI_RTSR1_TR19_Pos) /*!< 0x00080000 */
7746 #define EXTI_RTSR1_TR19 EXTI_RTSR1_TR19_Msk /*!< Rising trigger event configuration bit of line 19 */
7747 #define EXTI_RTSR1_TR20_Pos (20U)
7748 #define EXTI_RTSR1_TR20_Msk (0x1UL << EXTI_RTSR1_TR20_Pos) /*!< 0x00100000 */
7749 #define EXTI_RTSR1_TR20 EXTI_RTSR1_TR20_Msk /*!< Rising trigger event configuration bit of line 20 */
7750 #define EXTI_RTSR1_TR21_Pos (21U)
7751 #define EXTI_RTSR1_TR21_Msk (0x1UL << EXTI_RTSR1_TR21_Pos) /*!< 0x00200000 */
7752 #define EXTI_RTSR1_TR21 EXTI_RTSR1_TR21_Msk /*!< Rising trigger event configuration bit of line 21 */
7753
7754 /****************** Bit definition for EXTI_FTSR1 register *******************/
7755 #define EXTI_FTSR1_TR_Pos (0U)
7756 #define EXTI_FTSR1_TR_Msk (0x3FFFFFUL << EXTI_FTSR1_TR_Pos) /*!< 0x003FFFFF */
7757 #define EXTI_FTSR1_TR EXTI_FTSR1_TR_Msk /*!< Falling trigger event configuration bit */
7758 #define EXTI_FTSR1_TR0_Pos (0U)
7759 #define EXTI_FTSR1_TR0_Msk (0x1UL << EXTI_FTSR1_TR0_Pos) /*!< 0x00000001 */
7760 #define EXTI_FTSR1_TR0 EXTI_FTSR1_TR0_Msk /*!< Falling trigger event configuration bit of line 0 */
7761 #define EXTI_FTSR1_TR1_Pos (1U)
7762 #define EXTI_FTSR1_TR1_Msk (0x1UL << EXTI_FTSR1_TR1_Pos) /*!< 0x00000002 */
7763 #define EXTI_FTSR1_TR1 EXTI_FTSR1_TR1_Msk /*!< Falling trigger event configuration bit of line 1 */
7764 #define EXTI_FTSR1_TR2_Pos (2U)
7765 #define EXTI_FTSR1_TR2_Msk (0x1UL << EXTI_FTSR1_TR2_Pos) /*!< 0x00000004 */
7766 #define EXTI_FTSR1_TR2 EXTI_FTSR1_TR2_Msk /*!< Falling trigger event configuration bit of line 2 */
7767 #define EXTI_FTSR1_TR3_Pos (3U)
7768 #define EXTI_FTSR1_TR3_Msk (0x1UL << EXTI_FTSR1_TR3_Pos) /*!< 0x00000008 */
7769 #define EXTI_FTSR1_TR3 EXTI_FTSR1_TR3_Msk /*!< Falling trigger event configuration bit of line 3 */
7770 #define EXTI_FTSR1_TR4_Pos (4U)
7771 #define EXTI_FTSR1_TR4_Msk (0x1UL << EXTI_FTSR1_TR4_Pos) /*!< 0x00000010 */
7772 #define EXTI_FTSR1_TR4 EXTI_FTSR1_TR4_Msk /*!< Falling trigger event configuration bit of line 4 */
7773 #define EXTI_FTSR1_TR5_Pos (5U)
7774 #define EXTI_FTSR1_TR5_Msk (0x1UL << EXTI_FTSR1_TR5_Pos) /*!< 0x00000020 */
7775 #define EXTI_FTSR1_TR5 EXTI_FTSR1_TR5_Msk /*!< Falling trigger event configuration bit of line 5 */
7776 #define EXTI_FTSR1_TR6_Pos (6U)
7777 #define EXTI_FTSR1_TR6_Msk (0x1UL << EXTI_FTSR1_TR6_Pos) /*!< 0x00000040 */
7778 #define EXTI_FTSR1_TR6 EXTI_FTSR1_TR6_Msk /*!< Falling trigger event configuration bit of line 6 */
7779 #define EXTI_FTSR1_TR7_Pos (7U)
7780 #define EXTI_FTSR1_TR7_Msk (0x1UL << EXTI_FTSR1_TR7_Pos) /*!< 0x00000080 */
7781 #define EXTI_FTSR1_TR7 EXTI_FTSR1_TR7_Msk /*!< Falling trigger event configuration bit of line 7 */
7782 #define EXTI_FTSR1_TR8_Pos (8U)
7783 #define EXTI_FTSR1_TR8_Msk (0x1UL << EXTI_FTSR1_TR8_Pos) /*!< 0x00000100 */
7784 #define EXTI_FTSR1_TR8 EXTI_FTSR1_TR8_Msk /*!< Falling trigger event configuration bit of line 8 */
7785 #define EXTI_FTSR1_TR9_Pos (9U)
7786 #define EXTI_FTSR1_TR9_Msk (0x1UL << EXTI_FTSR1_TR9_Pos) /*!< 0x00000200 */
7787 #define EXTI_FTSR1_TR9 EXTI_FTSR1_TR9_Msk /*!< Falling trigger event configuration bit of line 9 */
7788 #define EXTI_FTSR1_TR10_Pos (10U)
7789 #define EXTI_FTSR1_TR10_Msk (0x1UL << EXTI_FTSR1_TR10_Pos) /*!< 0x00000400 */
7790 #define EXTI_FTSR1_TR10 EXTI_FTSR1_TR10_Msk /*!< Falling trigger event configuration bit of line 10 */
7791 #define EXTI_FTSR1_TR11_Pos (11U)
7792 #define EXTI_FTSR1_TR11_Msk (0x1UL << EXTI_FTSR1_TR11_Pos) /*!< 0x00000800 */
7793 #define EXTI_FTSR1_TR11 EXTI_FTSR1_TR11_Msk /*!< Falling trigger event configuration bit of line 11 */
7794 #define EXTI_FTSR1_TR12_Pos (12U)
7795 #define EXTI_FTSR1_TR12_Msk (0x1UL << EXTI_FTSR1_TR12_Pos) /*!< 0x00001000 */
7796 #define EXTI_FTSR1_TR12 EXTI_FTSR1_TR12_Msk /*!< Falling trigger event configuration bit of line 12 */
7797 #define EXTI_FTSR1_TR13_Pos (13U)
7798 #define EXTI_FTSR1_TR13_Msk (0x1UL << EXTI_FTSR1_TR13_Pos) /*!< 0x00002000 */
7799 #define EXTI_FTSR1_TR13 EXTI_FTSR1_TR13_Msk /*!< Falling trigger event configuration bit of line 13 */
7800 #define EXTI_FTSR1_TR14_Pos (14U)
7801 #define EXTI_FTSR1_TR14_Msk (0x1UL << EXTI_FTSR1_TR14_Pos) /*!< 0x00004000 */
7802 #define EXTI_FTSR1_TR14 EXTI_FTSR1_TR14_Msk /*!< Falling trigger event configuration bit of line 14 */
7803 #define EXTI_FTSR1_TR15_Pos (15U)
7804 #define EXTI_FTSR1_TR15_Msk (0x1UL << EXTI_FTSR1_TR15_Pos) /*!< 0x00008000 */
7805 #define EXTI_FTSR1_TR15 EXTI_FTSR1_TR15_Msk /*!< Falling trigger event configuration bit of line 15 */
7806 #define EXTI_FTSR1_TR16_Pos (16U)
7807 #define EXTI_FTSR1_TR16_Msk (0x1UL << EXTI_FTSR1_TR16_Pos) /*!< 0x00010000 */
7808 #define EXTI_FTSR1_TR16 EXTI_FTSR1_TR16_Msk /*!< Falling trigger event configuration bit of line 16 */
7809 #define EXTI_FTSR1_TR17_Pos (17U)
7810 #define EXTI_FTSR1_TR17_Msk (0x1UL << EXTI_FTSR1_TR17_Pos) /*!< 0x00020000 */
7811 #define EXTI_FTSR1_TR17 EXTI_FTSR1_TR17_Msk /*!< Falling trigger event configuration bit of line 17 */
7812 #define EXTI_FTSR1_TR18_Pos (18U)
7813 #define EXTI_FTSR1_TR18_Msk (0x1UL << EXTI_FTSR1_TR18_Pos) /*!< 0x00040000 */
7814 #define EXTI_FTSR1_TR18 EXTI_FTSR1_TR18_Msk /*!< Falling trigger event configuration bit of line 18 */
7815 #define EXTI_FTSR1_TR19_Pos (19U)
7816 #define EXTI_FTSR1_TR19_Msk (0x1UL << EXTI_FTSR1_TR19_Pos) /*!< 0x00080000 */
7817 #define EXTI_FTSR1_TR19 EXTI_FTSR1_TR19_Msk /*!< Falling trigger event configuration bit of line 19 */
7818 #define EXTI_FTSR1_TR20_Pos (20U)
7819 #define EXTI_FTSR1_TR20_Msk (0x1UL << EXTI_FTSR1_TR20_Pos) /*!< 0x00100000 */
7820 #define EXTI_FTSR1_TR20 EXTI_FTSR1_TR20_Msk /*!< Falling trigger event configuration bit of line 20 */
7821 #define EXTI_FTSR1_TR21_Pos (21U)
7822 #define EXTI_FTSR1_TR21_Msk (0x1UL << EXTI_FTSR1_TR21_Pos) /*!< 0x00200000 */
7823 #define EXTI_FTSR1_TR21 EXTI_FTSR1_TR21_Msk /*!< Falling trigger event configuration bit of line 21 */
7824
7825 /****************** Bit definition for EXTI_SWIER1 register ******************/
7826 #define EXTI_SWIER1_SWIER0_Pos (0U)
7827 #define EXTI_SWIER1_SWIER0_Msk (0x1UL << EXTI_SWIER1_SWIER0_Pos) /*!< 0x00000001 */
7828 #define EXTI_SWIER1_SWIER0 EXTI_SWIER1_SWIER0_Msk /*!< Software Interrupt on line 0 */
7829 #define EXTI_SWIER1_SWIER1_Pos (1U)
7830 #define EXTI_SWIER1_SWIER1_Msk (0x1UL << EXTI_SWIER1_SWIER1_Pos) /*!< 0x00000002 */
7831 #define EXTI_SWIER1_SWIER1 EXTI_SWIER1_SWIER1_Msk /*!< Software Interrupt on line 1 */
7832 #define EXTI_SWIER1_SWIER2_Pos (2U)
7833 #define EXTI_SWIER1_SWIER2_Msk (0x1UL << EXTI_SWIER1_SWIER2_Pos) /*!< 0x00000004 */
7834 #define EXTI_SWIER1_SWIER2 EXTI_SWIER1_SWIER2_Msk /*!< Software Interrupt on line 2 */
7835 #define EXTI_SWIER1_SWIER3_Pos (3U)
7836 #define EXTI_SWIER1_SWIER3_Msk (0x1UL << EXTI_SWIER1_SWIER3_Pos) /*!< 0x00000008 */
7837 #define EXTI_SWIER1_SWIER3 EXTI_SWIER1_SWIER3_Msk /*!< Software Interrupt on line 3 */
7838 #define EXTI_SWIER1_SWIER4_Pos (4U)
7839 #define EXTI_SWIER1_SWIER4_Msk (0x1UL << EXTI_SWIER1_SWIER4_Pos) /*!< 0x00000010 */
7840 #define EXTI_SWIER1_SWIER4 EXTI_SWIER1_SWIER4_Msk /*!< Software Interrupt on line 4 */
7841 #define EXTI_SWIER1_SWIER5_Pos (5U)
7842 #define EXTI_SWIER1_SWIER5_Msk (0x1UL << EXTI_SWIER1_SWIER5_Pos) /*!< 0x00000020 */
7843 #define EXTI_SWIER1_SWIER5 EXTI_SWIER1_SWIER5_Msk /*!< Software Interrupt on line 5 */
7844 #define EXTI_SWIER1_SWIER6_Pos (6U)
7845 #define EXTI_SWIER1_SWIER6_Msk (0x1UL << EXTI_SWIER1_SWIER6_Pos) /*!< 0x00000040 */
7846 #define EXTI_SWIER1_SWIER6 EXTI_SWIER1_SWIER6_Msk /*!< Software Interrupt on line 6 */
7847 #define EXTI_SWIER1_SWIER7_Pos (7U)
7848 #define EXTI_SWIER1_SWIER7_Msk (0x1UL << EXTI_SWIER1_SWIER7_Pos) /*!< 0x00000080 */
7849 #define EXTI_SWIER1_SWIER7 EXTI_SWIER1_SWIER7_Msk /*!< Software Interrupt on line 7 */
7850 #define EXTI_SWIER1_SWIER8_Pos (8U)
7851 #define EXTI_SWIER1_SWIER8_Msk (0x1UL << EXTI_SWIER1_SWIER8_Pos) /*!< 0x00000100 */
7852 #define EXTI_SWIER1_SWIER8 EXTI_SWIER1_SWIER8_Msk /*!< Software Interrupt on line 8 */
7853 #define EXTI_SWIER1_SWIER9_Pos (9U)
7854 #define EXTI_SWIER1_SWIER9_Msk (0x1UL << EXTI_SWIER1_SWIER9_Pos) /*!< 0x00000200 */
7855 #define EXTI_SWIER1_SWIER9 EXTI_SWIER1_SWIER9_Msk /*!< Software Interrupt on line 9 */
7856 #define EXTI_SWIER1_SWIER10_Pos (10U)
7857 #define EXTI_SWIER1_SWIER10_Msk (0x1UL << EXTI_SWIER1_SWIER10_Pos) /*!< 0x00000400 */
7858 #define EXTI_SWIER1_SWIER10 EXTI_SWIER1_SWIER10_Msk /*!< Software Interrupt on line 10 */
7859 #define EXTI_SWIER1_SWIER11_Pos (11U)
7860 #define EXTI_SWIER1_SWIER11_Msk (0x1UL << EXTI_SWIER1_SWIER11_Pos) /*!< 0x00000800 */
7861 #define EXTI_SWIER1_SWIER11 EXTI_SWIER1_SWIER11_Msk /*!< Software Interrupt on line 11 */
7862 #define EXTI_SWIER1_SWIER12_Pos (12U)
7863 #define EXTI_SWIER1_SWIER12_Msk (0x1UL << EXTI_SWIER1_SWIER12_Pos) /*!< 0x00001000 */
7864 #define EXTI_SWIER1_SWIER12 EXTI_SWIER1_SWIER12_Msk /*!< Software Interrupt on line 12 */
7865 #define EXTI_SWIER1_SWIER13_Pos (13U)
7866 #define EXTI_SWIER1_SWIER13_Msk (0x1UL << EXTI_SWIER1_SWIER13_Pos) /*!< 0x00002000 */
7867 #define EXTI_SWIER1_SWIER13 EXTI_SWIER1_SWIER13_Msk /*!< Software Interrupt on line 13 */
7868 #define EXTI_SWIER1_SWIER14_Pos (14U)
7869 #define EXTI_SWIER1_SWIER14_Msk (0x1UL << EXTI_SWIER1_SWIER14_Pos) /*!< 0x00004000 */
7870 #define EXTI_SWIER1_SWIER14 EXTI_SWIER1_SWIER14_Msk /*!< Software Interrupt on line 14 */
7871 #define EXTI_SWIER1_SWIER15_Pos (15U)
7872 #define EXTI_SWIER1_SWIER15_Msk (0x1UL << EXTI_SWIER1_SWIER15_Pos) /*!< 0x00008000 */
7873 #define EXTI_SWIER1_SWIER15 EXTI_SWIER1_SWIER15_Msk /*!< Software Interrupt on line 15 */
7874 #define EXTI_SWIER1_SWIER16_Pos (16U)
7875 #define EXTI_SWIER1_SWIER16_Msk (0x1UL << EXTI_SWIER1_SWIER16_Pos) /*!< 0x00010000 */
7876 #define EXTI_SWIER1_SWIER16 EXTI_SWIER1_SWIER16_Msk /*!< Software Interrupt on line 16 */
7877 #define EXTI_SWIER1_SWIER17_Pos (17U)
7878 #define EXTI_SWIER1_SWIER17_Msk (0x1UL << EXTI_SWIER1_SWIER17_Pos) /*!< 0x00020000 */
7879 #define EXTI_SWIER1_SWIER17 EXTI_SWIER1_SWIER17_Msk /*!< Software Interrupt on line 17 */
7880 #define EXTI_SWIER1_SWIER18_Pos (18U)
7881 #define EXTI_SWIER1_SWIER18_Msk (0x1UL << EXTI_SWIER1_SWIER18_Pos) /*!< 0x00040000 */
7882 #define EXTI_SWIER1_SWIER18 EXTI_SWIER1_SWIER18_Msk /*!< Software Interrupt on line 18 */
7883 #define EXTI_SWIER1_SWIER19_Pos (19U)
7884 #define EXTI_SWIER1_SWIER19_Msk (0x1UL << EXTI_SWIER1_SWIER19_Pos) /*!< 0x00080000 */
7885 #define EXTI_SWIER1_SWIER19 EXTI_SWIER1_SWIER19_Msk /*!< Software Interrupt on line 19 */
7886 #define EXTI_SWIER1_SWIER20_Pos (20U)
7887 #define EXTI_SWIER1_SWIER20_Msk (0x1UL << EXTI_SWIER1_SWIER20_Pos) /*!< 0x00100000 */
7888 #define EXTI_SWIER1_SWIER20 EXTI_SWIER1_SWIER20_Msk /*!< Software Interrupt on line 20 */
7889 #define EXTI_SWIER1_SWIER21_Pos (21U)
7890 #define EXTI_SWIER1_SWIER21_Msk (0x1UL << EXTI_SWIER1_SWIER21_Pos) /*!< 0x00200000 */
7891 #define EXTI_SWIER1_SWIER21 EXTI_SWIER1_SWIER21_Msk /*!< Software Interrupt on line 21 */
7892
7893 /****************** Bit definition for EXTI_D3PMR1 register ******************/
7894 #define EXTI_D3PMR1_MR0_Pos (0U)
7895 #define EXTI_D3PMR1_MR0_Msk (0x1UL << EXTI_D3PMR1_MR0_Pos) /*!< 0x00000001 */
7896 #define EXTI_D3PMR1_MR0 EXTI_D3PMR1_MR0_Msk /*!< Pending Mask Event for line 0 */
7897 #define EXTI_D3PMR1_MR1_Pos (1U)
7898 #define EXTI_D3PMR1_MR1_Msk (0x1UL << EXTI_D3PMR1_MR1_Pos) /*!< 0x00000002 */
7899 #define EXTI_D3PMR1_MR1 EXTI_D3PMR1_MR1_Msk /*!< Pending Mask Event for line 1 */
7900 #define EXTI_D3PMR1_MR2_Pos (2U)
7901 #define EXTI_D3PMR1_MR2_Msk (0x1UL << EXTI_D3PMR1_MR2_Pos) /*!< 0x00000004 */
7902 #define EXTI_D3PMR1_MR2 EXTI_D3PMR1_MR2_Msk /*!< Pending Mask Event for line 2 */
7903 #define EXTI_D3PMR1_MR3_Pos (3U)
7904 #define EXTI_D3PMR1_MR3_Msk (0x1UL << EXTI_D3PMR1_MR3_Pos) /*!< 0x00000008 */
7905 #define EXTI_D3PMR1_MR3 EXTI_D3PMR1_MR3_Msk /*!< Pending Mask Event for line 3 */
7906 #define EXTI_D3PMR1_MR4_Pos (4U)
7907 #define EXTI_D3PMR1_MR4_Msk (0x1UL << EXTI_D3PMR1_MR4_Pos) /*!< 0x00000010 */
7908 #define EXTI_D3PMR1_MR4 EXTI_D3PMR1_MR4_Msk /*!< Pending Mask Event for line 4 */
7909 #define EXTI_D3PMR1_MR5_Pos (5U)
7910 #define EXTI_D3PMR1_MR5_Msk (0x1UL << EXTI_D3PMR1_MR5_Pos) /*!< 0x00000020 */
7911 #define EXTI_D3PMR1_MR5 EXTI_D3PMR1_MR5_Msk /*!< Pending Mask Event for line 5 */
7912 #define EXTI_D3PMR1_MR6_Pos (6U)
7913 #define EXTI_D3PMR1_MR6_Msk (0x1UL << EXTI_D3PMR1_MR6_Pos) /*!< 0x00000040 */
7914 #define EXTI_D3PMR1_MR6 EXTI_D3PMR1_MR6_Msk /*!< Pending Mask Event for line 6 */
7915 #define EXTI_D3PMR1_MR7_Pos (7U)
7916 #define EXTI_D3PMR1_MR7_Msk (0x1UL << EXTI_D3PMR1_MR7_Pos) /*!< 0x00000080 */
7917 #define EXTI_D3PMR1_MR7 EXTI_D3PMR1_MR7_Msk /*!< Pending Mask Event for line 7 */
7918 #define EXTI_D3PMR1_MR8_Pos (8U)
7919 #define EXTI_D3PMR1_MR8_Msk (0x1UL << EXTI_D3PMR1_MR8_Pos) /*!< 0x00000100 */
7920 #define EXTI_D3PMR1_MR8 EXTI_D3PMR1_MR8_Msk /*!< Pending Mask Event for line 8 */
7921 #define EXTI_D3PMR1_MR9_Pos (9U)
7922 #define EXTI_D3PMR1_MR9_Msk (0x1UL << EXTI_D3PMR1_MR9_Pos) /*!< 0x00000200 */
7923 #define EXTI_D3PMR1_MR9 EXTI_D3PMR1_MR9_Msk /*!< Pending Mask Event for line 9 */
7924 #define EXTI_D3PMR1_MR10_Pos (10U)
7925 #define EXTI_D3PMR1_MR10_Msk (0x1UL << EXTI_D3PMR1_MR10_Pos) /*!< 0x00000400 */
7926 #define EXTI_D3PMR1_MR10 EXTI_D3PMR1_MR10_Msk /*!< Pending Mask Event for line 10 */
7927 #define EXTI_D3PMR1_MR11_Pos (11U)
7928 #define EXTI_D3PMR1_MR11_Msk (0x1UL << EXTI_D3PMR1_MR11_Pos) /*!< 0x00000800 */
7929 #define EXTI_D3PMR1_MR11 EXTI_D3PMR1_MR11_Msk /*!< Pending Mask Event for line 11 */
7930 #define EXTI_D3PMR1_MR12_Pos (12U)
7931 #define EXTI_D3PMR1_MR12_Msk (0x1UL << EXTI_D3PMR1_MR12_Pos) /*!< 0x00001000 */
7932 #define EXTI_D3PMR1_MR12 EXTI_D3PMR1_MR12_Msk /*!< Pending Mask Event for line 12 */
7933 #define EXTI_D3PMR1_MR13_Pos (13U)
7934 #define EXTI_D3PMR1_MR13_Msk (0x1UL << EXTI_D3PMR1_MR13_Pos) /*!< 0x00002000 */
7935 #define EXTI_D3PMR1_MR13 EXTI_D3PMR1_MR13_Msk /*!< Pending Mask Event for line 13 */
7936 #define EXTI_D3PMR1_MR14_Pos (14U)
7937 #define EXTI_D3PMR1_MR14_Msk (0x1UL << EXTI_D3PMR1_MR14_Pos) /*!< 0x00004000 */
7938 #define EXTI_D3PMR1_MR14 EXTI_D3PMR1_MR14_Msk /*!< Pending Mask Event for line 14 */
7939 #define EXTI_D3PMR1_MR15_Pos (15U)
7940 #define EXTI_D3PMR1_MR15_Msk (0x1UL << EXTI_D3PMR1_MR15_Pos) /*!< 0x00008000 */
7941 #define EXTI_D3PMR1_MR15 EXTI_D3PMR1_MR15_Msk /*!< Pending Mask Event for line 15 */
7942 #define EXTI_D3PMR1_MR19_Pos (19U)
7943 #define EXTI_D3PMR1_MR19_Msk (0x1UL << EXTI_D3PMR1_MR19_Pos) /*!< 0x00080000 */
7944 #define EXTI_D3PMR1_MR19 EXTI_D3PMR1_MR19_Msk /*!< Pending Mask Event for line 19 */
7945 #define EXTI_D3PMR1_MR20_Pos (20U)
7946 #define EXTI_D3PMR1_MR20_Msk (0x1UL << EXTI_D3PMR1_MR20_Pos) /*!< 0x00100000 */
7947 #define EXTI_D3PMR1_MR20 EXTI_D3PMR1_MR20_Msk /*!< Pending Mask Event for line 20 */
7948 #define EXTI_D3PMR1_MR21_Pos (21U)
7949 #define EXTI_D3PMR1_MR21_Msk (0x1UL << EXTI_D3PMR1_MR21_Pos) /*!< 0x00200000 */
7950 #define EXTI_D3PMR1_MR21 EXTI_D3PMR1_MR21_Msk /*!< Pending Mask Event for line 21 */
7951 #define EXTI_D3PMR1_MR25_Pos (24U)
7952 #define EXTI_D3PMR1_MR25_Msk (0x1UL << EXTI_D3PMR1_MR25_Pos) /*!< 0x01000000 */
7953 #define EXTI_D3PMR1_MR25 EXTI_D3PMR1_MR25_Msk /*!< Pending Mask Event for line 25 */
7954
7955 /******************* Bit definition for EXTI_D3PCR1L register ****************/
7956 #define EXTI_D3PCR1L_PCS0_Pos (0U)
7957 #define EXTI_D3PCR1L_PCS0_Msk (0x3UL << EXTI_D3PCR1L_PCS0_Pos) /*!< 0x00000003 */
7958 #define EXTI_D3PCR1L_PCS0 EXTI_D3PCR1L_PCS0_Msk /*!< D3 Pending request clear input signal selection on line 0 */
7959 #define EXTI_D3PCR1L_PCS1_Pos (2U)
7960 #define EXTI_D3PCR1L_PCS1_Msk (0x3UL << EXTI_D3PCR1L_PCS1_Pos) /*!< 0x000000C0 */
7961 #define EXTI_D3PCR1L_PCS1 EXTI_D3PCR1L_PCS1_Msk /*!< D3 Pending request clear input signal selection on line 1 */
7962 #define EXTI_D3PCR1L_PCS2_Pos (4U)
7963 #define EXTI_D3PCR1L_PCS2_Msk (0x3UL << EXTI_D3PCR1L_PCS2_Pos) /*!< 0x00000030 */
7964 #define EXTI_D3PCR1L_PCS2 EXTI_D3PCR1L_PCS2_Msk /*!< D3 Pending request clear input signal selection on line 2 */
7965 #define EXTI_D3PCR1L_PCS3_Pos (6U)
7966 #define EXTI_D3PCR1L_PCS3_Msk (0x3UL << EXTI_D3PCR1L_PCS3_Pos) /*!< 0x000000C0 */
7967 #define EXTI_D3PCR1L_PCS3 EXTI_D3PCR1L_PCS3_Msk /*!< D3 Pending request clear input signal selection on line 3 */
7968 #define EXTI_D3PCR1L_PCS4_Pos (8U)
7969 #define EXTI_D3PCR1L_PCS4_Msk (0x3UL << EXTI_D3PCR1L_PCS4_Pos) /*!< 0x00000300 */
7970 #define EXTI_D3PCR1L_PCS4 EXTI_D3PCR1L_PCS4_Msk /*!< D3 Pending request clear input signal selection on line 4 */
7971 #define EXTI_D3PCR1L_PCS5_Pos (10U)
7972 #define EXTI_D3PCR1L_PCS5_Msk (0x3UL << EXTI_D3PCR1L_PCS5_Pos) /*!< 0x00000C00 */
7973 #define EXTI_D3PCR1L_PCS5 EXTI_D3PCR1L_PCS5_Msk /*!< D3 Pending request clear input signal selection on line 5 */
7974 #define EXTI_D3PCR1L_PCS6_Pos (12U)
7975 #define EXTI_D3PCR1L_PCS6_Msk (0x3UL << EXTI_D3PCR1L_PCS6_Pos) /*!< 0x00003000 */
7976 #define EXTI_D3PCR1L_PCS6 EXTI_D3PCR1L_PCS6_Msk /*!< D3 Pending request clear input signal selection on line 6 */
7977 #define EXTI_D3PCR1L_PCS7_Pos (14U)
7978 #define EXTI_D3PCR1L_PCS7_Msk (0x3UL << EXTI_D3PCR1L_PCS7_Pos) /*!< 0x0000C000 */
7979 #define EXTI_D3PCR1L_PCS7 EXTI_D3PCR1L_PCS7_Msk /*!< D3 Pending request clear input signal selection on line 7 */
7980 #define EXTI_D3PCR1L_PCS8_Pos (16U)
7981 #define EXTI_D3PCR1L_PCS8_Msk (0x3UL << EXTI_D3PCR1L_PCS8_Pos) /*!< 0x00030000 */
7982 #define EXTI_D3PCR1L_PCS8 EXTI_D3PCR1L_PCS8_Msk /*!< D3 Pending request clear input signal selection on line 8 */
7983 #define EXTI_D3PCR1L_PCS9_Pos (18U)
7984 #define EXTI_D3PCR1L_PCS9_Msk (0x3UL << EXTI_D3PCR1L_PCS9_Pos) /*!< 0x000C0000 */
7985 #define EXTI_D3PCR1L_PCS9 EXTI_D3PCR1L_PCS9_Msk /*!< D3 Pending request clear input signal selection on line 9 */
7986 #define EXTI_D3PCR1L_PCS10_Pos (20U)
7987 #define EXTI_D3PCR1L_PCS10_Msk (0x3UL << EXTI_D3PCR1L_PCS10_Pos) /*!< 0x00300000 */
7988 #define EXTI_D3PCR1L_PCS10 EXTI_D3PCR1L_PCS10_Msk /*!< D3 Pending request clear input signal selection on line 10*/
7989 #define EXTI_D3PCR1L_PCS11_Pos (22U)
7990 #define EXTI_D3PCR1L_PCS11_Msk (0x3UL << EXTI_D3PCR1L_PCS11_Pos) /*!< 0x00C00000 */
7991 #define EXTI_D3PCR1L_PCS11 EXTI_D3PCR1L_PCS11_Msk /*!< D3 Pending request clear input signal selection on line 11*/
7992 #define EXTI_D3PCR1L_PCS12_Pos (24U)
7993 #define EXTI_D3PCR1L_PCS12_Msk (0x3UL << EXTI_D3PCR1L_PCS12_Pos) /*!< 0x03000000 */
7994 #define EXTI_D3PCR1L_PCS12 EXTI_D3PCR1L_PCS12_Msk /*!< D3 Pending request clear input signal selection on line 12*/
7995 #define EXTI_D3PCR1L_PCS13_Pos (26U)
7996 #define EXTI_D3PCR1L_PCS13_Msk (0x3UL << EXTI_D3PCR1L_PCS13_Pos) /*!< 0x0C000000 */
7997 #define EXTI_D3PCR1L_PCS13 EXTI_D3PCR1L_PCS13_Msk /*!< D3 Pending request clear input signal selection on line 13*/
7998 #define EXTI_D3PCR1L_PCS14_Pos (28U)
7999 #define EXTI_D3PCR1L_PCS14_Msk (0x3UL << EXTI_D3PCR1L_PCS14_Pos) /*!< 0x30000000 */
8000 #define EXTI_D3PCR1L_PCS14 EXTI_D3PCR1L_PCS14_Msk /*!< D3 Pending request clear input signal selection on line 14*/
8001 #define EXTI_D3PCR1L_PCS15_Pos (30U)
8002 #define EXTI_D3PCR1L_PCS15_Msk (0x3UL << EXTI_D3PCR1L_PCS15_Pos) /*!< 0xC0000000 */
8003 #define EXTI_D3PCR1L_PCS15 EXTI_D3PCR1L_PCS15_Msk /*!< D3 Pending request clear input signal selection on line 15*/
8004
8005 /******************* Bit definition for EXTI_D3PCR1H register ****************/
8006 #define EXTI_D3PCR1H_PCS19_Pos (6U)
8007 #define EXTI_D3PCR1H_PCS19_Msk (0x3UL << EXTI_D3PCR1H_PCS19_Pos) /*!< 0x000000C0 */
8008 #define EXTI_D3PCR1H_PCS19 EXTI_D3PCR1H_PCS19_Msk /*!< D3 Pending request clear input signal selection on line 19 */
8009 #define EXTI_D3PCR1H_PCS20_Pos (8U)
8010 #define EXTI_D3PCR1H_PCS20_Msk (0x3UL << EXTI_D3PCR1H_PCS20_Pos) /*!< 0x00000300 */
8011 #define EXTI_D3PCR1H_PCS20 EXTI_D3PCR1H_PCS20_Msk /*!< D3 Pending request clear input signal selection on line 20 */
8012 #define EXTI_D3PCR1H_PCS21_Pos (10U)
8013 #define EXTI_D3PCR1H_PCS21_Msk (0x3UL << EXTI_D3PCR1H_PCS21_Pos) /*!< 0x00000C00 */
8014 #define EXTI_D3PCR1H_PCS21 EXTI_D3PCR1H_PCS21_Msk /*!< D3 Pending request clear input signal selection on line 21 */
8015 #define EXTI_D3PCR1H_PCS25_Pos (18U)
8016 #define EXTI_D3PCR1H_PCS25_Msk (0x3UL << EXTI_D3PCR1H_PCS25_Pos) /*!< 0x000C0000 */
8017 #define EXTI_D3PCR1H_PCS25 EXTI_D3PCR1H_PCS25_Msk /*!< D3 Pending request clear input signal selection on line 25 */
8018
8019 /****************** Bit definition for EXTI_RTSR2 register *******************/
8020 #define EXTI_RTSR2_TR_Pos (17U)
8021 #define EXTI_RTSR2_TR_Msk (0x5UL << EXTI_RTSR2_TR_Pos) /*!< 0x000A0000 */
8022 #define EXTI_RTSR2_TR EXTI_RTSR2_TR_Msk /*!< Rising trigger event configuration bit */
8023 #define EXTI_RTSR2_TR49_Pos (17U)
8024 #define EXTI_RTSR2_TR49_Msk (0x1UL << EXTI_RTSR2_TR49_Pos) /*!< 0x00020000 */
8025 #define EXTI_RTSR2_TR49 EXTI_RTSR2_TR49_Msk /*!< Rising trigger event configuration bit of line 49 */
8026 #define EXTI_RTSR2_TR51_Pos (19U)
8027 #define EXTI_RTSR2_TR51_Msk (0x1UL << EXTI_RTSR2_TR51_Pos) /*!< 0x00080000 */
8028 #define EXTI_RTSR2_TR51 EXTI_RTSR2_TR51_Msk /*!< Rising trigger event configuration bit of line 51 */
8029
8030 /****************** Bit definition for EXTI_FTSR2 register *******************/
8031 #define EXTI_FTSR2_TR_Pos (17U)
8032 #define EXTI_FTSR2_TR_Msk (0x5UL << EXTI_FTSR2_TR_Pos) /*!< 0x000A0000 */
8033 #define EXTI_FTSR2_TR EXTI_FTSR2_TR_Msk /*!< Falling trigger event configuration bit */
8034 #define EXTI_FTSR2_TR49_Pos (17U)
8035 #define EXTI_FTSR2_TR49_Msk (0x1UL << EXTI_FTSR2_TR49_Pos) /*!< 0x00020000 */
8036 #define EXTI_FTSR2_TR49 EXTI_FTSR2_TR49_Msk /*!< Falling trigger event configuration bit of line 49 */
8037 #define EXTI_FTSR2_TR51_Pos (19U)
8038 #define EXTI_FTSR2_TR51_Msk (0x1UL << EXTI_FTSR2_TR51_Pos) /*!< 0x00080000 */
8039 #define EXTI_FTSR2_TR51 EXTI_FTSR2_TR51_Msk /*!< Falling trigger event configuration bit of line 51 */
8040
8041 /****************** Bit definition for EXTI_SWIER2 register ******************/
8042 #define EXTI_SWIER2_SWIER49_Pos (17U)
8043 #define EXTI_SWIER2_SWIER49_Msk (0x1UL << EXTI_SWIER2_SWIER49_Pos) /*!< 0x00020000 */
8044 #define EXTI_SWIER2_SWIER49 EXTI_SWIER2_SWIER49_Msk /*!< Software Interrupt on line 49 */
8045 #define EXTI_SWIER2_SWIER51_Pos (19U)
8046 #define EXTI_SWIER2_SWIER51_Msk (0x1UL << EXTI_SWIER2_SWIER51_Pos) /*!< 0x00080000 */
8047 #define EXTI_SWIER2_SWIER51 EXTI_SWIER2_SWIER51_Msk /*!< Software Interrupt on line 51 */
8048
8049 /****************** Bit definition for EXTI_D3PMR2 register ******************/
8050 #define EXTI_D3PMR2_MR34_Pos (2U)
8051 #define EXTI_D3PMR2_MR34_Msk (0x1UL << EXTI_D3PMR2_MR34_Pos) /*!< 0x00000004 */
8052 #define EXTI_D3PMR2_MR34 EXTI_D3PMR2_MR34_Msk /*!< Pending Mask Event for line 34 */
8053 #define EXTI_D3PMR2_MR35_Pos (3U)
8054 #define EXTI_D3PMR2_MR35_Msk (0x1UL << EXTI_D3PMR2_MR35_Pos) /*!< 0x00000008 */
8055 #define EXTI_D3PMR2_MR35 EXTI_D3PMR2_MR35_Msk /*!< Pending Mask Event for line 35 */
8056 #define EXTI_D3PMR2_MR41_Pos (9U)
8057 #define EXTI_D3PMR2_MR41_Msk (0x1UL << EXTI_D3PMR2_MR41_Pos) /*!< 0x00000200 */
8058 #define EXTI_D3PMR2_MR41 EXTI_D3PMR2_MR41_Msk /*!< Pending Mask Event for line 41 */
8059 #define EXTI_D3PMR2_MR48_Pos (16U)
8060 #define EXTI_D3PMR2_MR48_Msk (0x1UL << EXTI_D3PMR2_MR48_Pos) /*!< 0x00010000 */
8061 #define EXTI_D3PMR2_MR48 EXTI_D3PMR2_MR48_Msk /*!< Pending Mask Event for line 48 */
8062 #define EXTI_D3PMR2_MR49_Pos (17U)
8063 #define EXTI_D3PMR2_MR49_Msk (0x1UL << EXTI_D3PMR2_MR49_Pos) /*!< 0x00020000 */
8064 #define EXTI_D3PMR2_MR49 EXTI_D3PMR2_MR49_Msk /*!< Pending Mask Event for line 49 */
8065 #define EXTI_D3PMR2_MR50_Pos (18U)
8066 #define EXTI_D3PMR2_MR50_Msk (0x1UL << EXTI_D3PMR2_MR50_Pos) /*!< 0x00040000 */
8067 #define EXTI_D3PMR2_MR50 EXTI_D3PMR2_MR50_Msk /*!< Pending Mask Event for line 50 */
8068 #define EXTI_D3PMR2_MR51_Pos (19U)
8069 #define EXTI_D3PMR2_MR51_Msk (0x1UL << EXTI_D3PMR2_MR51_Pos) /*!< 0x00080000 */
8070 #define EXTI_D3PMR2_MR51 EXTI_D3PMR2_MR51_Msk /*!< Pending Mask Event for line 51 */
8071 /******************* Bit definition for EXTI_D3PCR2L register ****************/
8072 #define EXTI_D3PCR2L_PCS34_Pos (4U)
8073 #define EXTI_D3PCR2L_PCS34_Msk (0x3UL << EXTI_D3PCR2L_PCS34_Pos) /*!< 0x00000030 */
8074 #define EXTI_D3PCR2L_PCS34 EXTI_D3PCR2L_PCS34_Msk /*!< D3 Pending request clear input signal selection on line 34 */
8075 #define EXTI_D3PCR2L_PCS35_Pos (6U)
8076 #define EXTI_D3PCR2L_PCS35_Msk (0x3UL << EXTI_D3PCR2L_PCS35_Pos) /*!< 0x000000C0 */
8077 #define EXTI_D3PCR2L_PCS35 EXTI_D3PCR2L_PCS35_Msk /*!< D3 Pending request clear input signal selection on line 35 */
8078 #define EXTI_D3PCR2L_PCS41_Pos (18U)
8079 #define EXTI_D3PCR2L_PCS41_Msk (0x3UL << EXTI_D3PCR2L_PCS41_Pos) /*!< 0x000C0000 */
8080 #define EXTI_D3PCR2L_PCS41 EXTI_D3PCR2L_PCS41_Msk /*!< D3 Pending request clear input signal selection on line 41 */
8081
8082
8083 /******************* Bit definition for EXTI_D3PCR2H register ****************/
8084 #define EXTI_D3PCR2H_PCS48_Pos (0U)
8085 #define EXTI_D3PCR2H_PCS48_Msk (0x3UL << EXTI_D3PCR2H_PCS48_Pos) /*!< 0x00000003 */
8086 #define EXTI_D3PCR2H_PCS48 EXTI_D3PCR2H_PCS48_Msk /*!< D3 Pending request clear input signal selection on line 48 */
8087 #define EXTI_D3PCR2H_PCS49_Pos (2U)
8088 #define EXTI_D3PCR2H_PCS49_Msk (0x3UL << EXTI_D3PCR2H_PCS49_Pos) /*!< 0x0000000C */
8089 #define EXTI_D3PCR2H_PCS49 EXTI_D3PCR2H_PCS49_Msk /*!< D3 Pending request clear input signal selection on line 49 */
8090 #define EXTI_D3PCR2H_PCS50_Pos (4U)
8091 #define EXTI_D3PCR2H_PCS50_Msk (0x3UL << EXTI_D3PCR2H_PCS50_Pos) /*!< 0x00000030 */
8092 #define EXTI_D3PCR2H_PCS50 EXTI_D3PCR2H_PCS50_Msk /*!< D3 Pending request clear input signal selection on line 50 */
8093 #define EXTI_D3PCR2H_PCS51_Pos (6U)
8094 #define EXTI_D3PCR2H_PCS51_Msk (0x3UL << EXTI_D3PCR2H_PCS51_Pos) /*!< 0x000000C0 */
8095 #define EXTI_D3PCR2H_PCS51 EXTI_D3PCR2H_PCS51_Msk /*!< D3 Pending request clear input signal selection on line 51 */
8096 /****************** Bit definition for EXTI_RTSR3 register *******************/
8097 #define EXTI_RTSR3_TR_Pos (18U)
8098 #define EXTI_RTSR3_TR_Msk (0x9UL << EXTI_RTSR3_TR_Pos) /*!< 0x00240000 */
8099 #define EXTI_RTSR3_TR EXTI_RTSR3_TR_Msk /*!< Rising trigger event configuration bit */
8100 #define EXTI_RTSR3_TR82_Pos (18U)
8101 #define EXTI_RTSR3_TR82_Msk (0x1UL << EXTI_RTSR3_TR82_Pos) /*!< 0x00040000 */
8102 #define EXTI_RTSR3_TR82 EXTI_RTSR3_TR82_Msk /*!< Rising trigger event configuration bit of line 82 */
8103 #define EXTI_RTSR3_TR85_Pos (21U)
8104 #define EXTI_RTSR3_TR85_Msk (0x1UL << EXTI_RTSR3_TR85_Pos) /*!< 0x00200000 */
8105 #define EXTI_RTSR3_TR85 EXTI_RTSR3_TR85_Msk /*!< Rising trigger event configuration bit of line 85 */
8106
8107 /****************** Bit definition for EXTI_FTSR3 register *******************/
8108 #define EXTI_FTSR3_TR_Pos (18U)
8109 #define EXTI_FTSR3_TR_Msk (0x9UL << EXTI_FTSR3_TR_Pos) /*!< 0x00240000 */
8110 #define EXTI_FTSR3_TR EXTI_FTSR3_TR_Msk /*!< Falling trigger event configuration bit */
8111 #define EXTI_FTSR3_TR82_Pos (18U)
8112 #define EXTI_FTSR3_TR82_Msk (0x1UL << EXTI_FTSR3_TR82_Pos) /*!< 0x00040000 */
8113 #define EXTI_FTSR3_TR82 EXTI_FTSR3_TR82_Msk /*!< Falling trigger event configuration bit of line 82 */
8114 #define EXTI_FTSR3_TR85_Pos (21U)
8115 #define EXTI_FTSR3_TR85_Msk (0x1UL << EXTI_FTSR3_TR85_Pos) /*!< 0x00200000 */
8116 #define EXTI_FTSR3_TR85 EXTI_FTSR3_TR85_Msk /*!< Falling trigger event configuration bit of line 85 */
8117
8118 /****************** Bit definition for EXTI_SWIER3 register ******************/
8119 #define EXTI_SWIER3_SWI_Pos (18U)
8120 #define EXTI_SWIER3_SWI_Msk (0x9UL << EXTI_SWIER3_SWI_Pos) /*!< 0x00240000 */
8121 #define EXTI_SWIER3_SWI EXTI_SWIER3_SWI_Msk /*!< Software Interrupt event bit */
8122 #define EXTI_SWIER3_SWIER82_Pos (18U)
8123 #define EXTI_SWIER3_SWIER82_Msk (0x1UL << EXTI_SWIER3_SWIER82_Pos) /*!< 0x00040000 */
8124 #define EXTI_SWIER3_SWIER82 EXTI_SWIER3_SWIER82_Msk /*!< Software Interrupt on line 82 */
8125 #define EXTI_SWIER3_SWIER85_Pos (21U)
8126 #define EXTI_SWIER3_SWIER85_Msk (0x1UL << EXTI_SWIER3_SWIER85_Pos) /*!< 0x00200000 */
8127 #define EXTI_SWIER3_SWIER85 EXTI_SWIER3_SWIER85_Msk /*!< Software Interrupt on line 85 */
8128
8129 /****************** Bit definition for EXTI_D3PMR3 register ******************/
8130 #define EXTI_D3PMR3_MR88_Pos (24U)
8131 #define EXTI_D3PMR3_MR88_Msk (0x1UL << EXTI_D3PMR3_MR88_Pos) /*!< 0x01000000 */
8132 #define EXTI_D3PMR3_MR88 EXTI_D3PMR3_MR88_Msk /*!< Pending Mask Event for line 88 */
8133
8134 /******************* Bit definition for EXTI_D3PCR3H register ****************/
8135 #define EXTI_D3PCR3H_PCS88_Pos (16U)
8136 #define EXTI_D3PCR3H_PCS88_Msk (0x3UL << EXTI_D3PCR3H_PCS88_Pos) /*!< 0x00030000 */
8137 #define EXTI_D3PCR3H_PCS88 EXTI_D3PCR3H_PCS88_Msk /*!< D3 Pending request clear input signal selection on line 88 */
8138
8139 /******************* Bit definition for EXTI_IMR1 register *******************/
8140 #define EXTI_IMR1_IM_Pos (0U)
8141 #define EXTI_IMR1_IM_Msk (0xFFFFFFFFUL << EXTI_IMR1_IM_Pos) /*!< 0xFFFFFFFF */
8142 #define EXTI_IMR1_IM EXTI_IMR1_IM_Msk /*!< Interrupt Mask */
8143 #define EXTI_IMR1_IM0_Pos (0U)
8144 #define EXTI_IMR1_IM0_Msk (0x1UL << EXTI_IMR1_IM0_Pos) /*!< 0x00000001 */
8145 #define EXTI_IMR1_IM0 EXTI_IMR1_IM0_Msk /*!< Interrupt Mask on line 0 */
8146 #define EXTI_IMR1_IM1_Pos (1U)
8147 #define EXTI_IMR1_IM1_Msk (0x1UL << EXTI_IMR1_IM1_Pos) /*!< 0x00000002 */
8148 #define EXTI_IMR1_IM1 EXTI_IMR1_IM1_Msk /*!< Interrupt Mask on line 1 */
8149 #define EXTI_IMR1_IM2_Pos (2U)
8150 #define EXTI_IMR1_IM2_Msk (0x1UL << EXTI_IMR1_IM2_Pos) /*!< 0x00000004 */
8151 #define EXTI_IMR1_IM2 EXTI_IMR1_IM2_Msk /*!< Interrupt Mask on line 2 */
8152 #define EXTI_IMR1_IM3_Pos (3U)
8153 #define EXTI_IMR1_IM3_Msk (0x1UL << EXTI_IMR1_IM3_Pos) /*!< 0x00000008 */
8154 #define EXTI_IMR1_IM3 EXTI_IMR1_IM3_Msk /*!< Interrupt Mask on line 3 */
8155 #define EXTI_IMR1_IM4_Pos (4U)
8156 #define EXTI_IMR1_IM4_Msk (0x1UL << EXTI_IMR1_IM4_Pos) /*!< 0x00000010 */
8157 #define EXTI_IMR1_IM4 EXTI_IMR1_IM4_Msk /*!< Interrupt Mask on line 4 */
8158 #define EXTI_IMR1_IM5_Pos (5U)
8159 #define EXTI_IMR1_IM5_Msk (0x1UL << EXTI_IMR1_IM5_Pos) /*!< 0x00000020 */
8160 #define EXTI_IMR1_IM5 EXTI_IMR1_IM5_Msk /*!< Interrupt Mask on line 5 */
8161 #define EXTI_IMR1_IM6_Pos (6U)
8162 #define EXTI_IMR1_IM6_Msk (0x1UL << EXTI_IMR1_IM6_Pos) /*!< 0x00000040 */
8163 #define EXTI_IMR1_IM6 EXTI_IMR1_IM6_Msk /*!< Interrupt Mask on line 6 */
8164 #define EXTI_IMR1_IM7_Pos (7U)
8165 #define EXTI_IMR1_IM7_Msk (0x1UL << EXTI_IMR1_IM7_Pos) /*!< 0x00000080 */
8166 #define EXTI_IMR1_IM7 EXTI_IMR1_IM7_Msk /*!< Interrupt Mask on line 7 */
8167 #define EXTI_IMR1_IM8_Pos (8U)
8168 #define EXTI_IMR1_IM8_Msk (0x1UL << EXTI_IMR1_IM8_Pos) /*!< 0x00000100 */
8169 #define EXTI_IMR1_IM8 EXTI_IMR1_IM8_Msk /*!< Interrupt Mask on line 8 */
8170 #define EXTI_IMR1_IM9_Pos (9U)
8171 #define EXTI_IMR1_IM9_Msk (0x1UL << EXTI_IMR1_IM9_Pos) /*!< 0x00000200 */
8172 #define EXTI_IMR1_IM9 EXTI_IMR1_IM9_Msk /*!< Interrupt Mask on line 9 */
8173 #define EXTI_IMR1_IM10_Pos (10U)
8174 #define EXTI_IMR1_IM10_Msk (0x1UL << EXTI_IMR1_IM10_Pos) /*!< 0x00000400 */
8175 #define EXTI_IMR1_IM10 EXTI_IMR1_IM10_Msk /*!< Interrupt Mask on line 10 */
8176 #define EXTI_IMR1_IM11_Pos (11U)
8177 #define EXTI_IMR1_IM11_Msk (0x1UL << EXTI_IMR1_IM11_Pos) /*!< 0x00000800 */
8178 #define EXTI_IMR1_IM11 EXTI_IMR1_IM11_Msk /*!< Interrupt Mask on line 11 */
8179 #define EXTI_IMR1_IM12_Pos (12U)
8180 #define EXTI_IMR1_IM12_Msk (0x1UL << EXTI_IMR1_IM12_Pos) /*!< 0x00001000 */
8181 #define EXTI_IMR1_IM12 EXTI_IMR1_IM12_Msk /*!< Interrupt Mask on line 12 */
8182 #define EXTI_IMR1_IM13_Pos (13U)
8183 #define EXTI_IMR1_IM13_Msk (0x1UL << EXTI_IMR1_IM13_Pos) /*!< 0x00002000 */
8184 #define EXTI_IMR1_IM13 EXTI_IMR1_IM13_Msk /*!< Interrupt Mask on line 13 */
8185 #define EXTI_IMR1_IM14_Pos (14U)
8186 #define EXTI_IMR1_IM14_Msk (0x1UL << EXTI_IMR1_IM14_Pos) /*!< 0x00004000 */
8187 #define EXTI_IMR1_IM14 EXTI_IMR1_IM14_Msk /*!< Interrupt Mask on line 14 */
8188 #define EXTI_IMR1_IM15_Pos (15U)
8189 #define EXTI_IMR1_IM15_Msk (0x1UL << EXTI_IMR1_IM15_Pos) /*!< 0x00008000 */
8190 #define EXTI_IMR1_IM15 EXTI_IMR1_IM15_Msk /*!< Interrupt Mask on line 15 */
8191 #define EXTI_IMR1_IM16_Pos (16U)
8192 #define EXTI_IMR1_IM16_Msk (0x1UL << EXTI_IMR1_IM16_Pos) /*!< 0x00010000 */
8193 #define EXTI_IMR1_IM16 EXTI_IMR1_IM16_Msk /*!< Interrupt Mask on line 16 */
8194 #define EXTI_IMR1_IM17_Pos (17U)
8195 #define EXTI_IMR1_IM17_Msk (0x1UL << EXTI_IMR1_IM17_Pos) /*!< 0x00020000 */
8196 #define EXTI_IMR1_IM17 EXTI_IMR1_IM17_Msk /*!< Interrupt Mask on line 17 */
8197 #define EXTI_IMR1_IM18_Pos (18U)
8198 #define EXTI_IMR1_IM18_Msk (0x1UL << EXTI_IMR1_IM18_Pos) /*!< 0x00040000 */
8199 #define EXTI_IMR1_IM18 EXTI_IMR1_IM18_Msk /*!< Interrupt Mask on line 18 */
8200 #define EXTI_IMR1_IM19_Pos (19U)
8201 #define EXTI_IMR1_IM19_Msk (0x1UL << EXTI_IMR1_IM19_Pos) /*!< 0x00080000 */
8202 #define EXTI_IMR1_IM19 EXTI_IMR1_IM19_Msk /*!< Interrupt Mask on line 19 */
8203 #define EXTI_IMR1_IM20_Pos (20U)
8204 #define EXTI_IMR1_IM20_Msk (0x1UL << EXTI_IMR1_IM20_Pos) /*!< 0x00100000 */
8205 #define EXTI_IMR1_IM20 EXTI_IMR1_IM20_Msk /*!< Interrupt Mask on line 20 */
8206 #define EXTI_IMR1_IM21_Pos (21U)
8207 #define EXTI_IMR1_IM21_Msk (0x1UL << EXTI_IMR1_IM21_Pos) /*!< 0x00200000 */
8208 #define EXTI_IMR1_IM21 EXTI_IMR1_IM21_Msk /*!< Interrupt Mask on line 21 */
8209 #define EXTI_IMR1_IM22_Pos (22U)
8210 #define EXTI_IMR1_IM22_Msk (0x1UL << EXTI_IMR1_IM22_Pos) /*!< 0x00400000 */
8211 #define EXTI_IMR1_IM22 EXTI_IMR1_IM22_Msk /*!< Interrupt Mask on line 22 */
8212 #define EXTI_IMR1_IM23_Pos (23U)
8213 #define EXTI_IMR1_IM23_Msk (0x1UL << EXTI_IMR1_IM23_Pos) /*!< 0x00800000 */
8214 #define EXTI_IMR1_IM23 EXTI_IMR1_IM23_Msk /*!< Interrupt Mask on line 23 */
8215 #define EXTI_IMR1_IM24_Pos (24U)
8216 #define EXTI_IMR1_IM24_Msk (0x1UL << EXTI_IMR1_IM24_Pos) /*!< 0x01000000 */
8217 #define EXTI_IMR1_IM24 EXTI_IMR1_IM24_Msk /*!< Interrupt Mask on line 24 */
8218 #define EXTI_IMR1_IM25_Pos (25U)
8219 #define EXTI_IMR1_IM25_Msk (0x1UL << EXTI_IMR1_IM25_Pos) /*!< 0x02000000 */
8220 #define EXTI_IMR1_IM25 EXTI_IMR1_IM25_Msk /*!< Interrupt Mask on line 25 */
8221 #define EXTI_IMR1_IM26_Pos (26U)
8222 #define EXTI_IMR1_IM26_Msk (0x1UL << EXTI_IMR1_IM26_Pos) /*!< 0x04000000 */
8223 #define EXTI_IMR1_IM26 EXTI_IMR1_IM26_Msk /*!< Interrupt Mask on line 26 */
8224 #define EXTI_IMR1_IM27_Pos (27U)
8225 #define EXTI_IMR1_IM27_Msk (0x1UL << EXTI_IMR1_IM27_Pos) /*!< 0x08000000 */
8226 #define EXTI_IMR1_IM27 EXTI_IMR1_IM27_Msk /*!< Interrupt Mask on line 27 */
8227 #define EXTI_IMR1_IM28_Pos (28U)
8228 #define EXTI_IMR1_IM28_Msk (0x1UL << EXTI_IMR1_IM28_Pos) /*!< 0x10000000 */
8229 #define EXTI_IMR1_IM28 EXTI_IMR1_IM28_Msk /*!< Interrupt Mask on line 28 */
8230 #define EXTI_IMR1_IM29_Pos (29U)
8231 #define EXTI_IMR1_IM29_Msk (0x1UL << EXTI_IMR1_IM29_Pos) /*!< 0x20000000 */
8232 #define EXTI_IMR1_IM29 EXTI_IMR1_IM29_Msk /*!< Interrupt Mask on line 29 */
8233 #define EXTI_IMR1_IM30_Pos (30U)
8234 #define EXTI_IMR1_IM30_Msk (0x1UL << EXTI_IMR1_IM30_Pos) /*!< 0x40000000 */
8235 #define EXTI_IMR1_IM30 EXTI_IMR1_IM30_Msk /*!< Interrupt Mask on line 30 */
8236 #define EXTI_IMR1_IM31_Pos (31U)
8237 #define EXTI_IMR1_IM31_Msk (0x1UL << EXTI_IMR1_IM31_Pos) /*!< 0x80000000 */
8238 #define EXTI_IMR1_IM31 EXTI_IMR1_IM31_Msk /*!< Interrupt Mask on line 31 */
8239
8240 /******************* Bit definition for EXTI_EMR1 register *******************/
8241 #define EXTI_EMR1_EM_Pos (0U)
8242 #define EXTI_EMR1_EM_Msk (0xFFFFFFFFUL << EXTI_EMR1_EM_Pos) /*!< 0xFFFFFFFF */
8243 #define EXTI_EMR1_EM EXTI_EMR1_EM_Msk /*!< Event Mask */
8244 #define EXTI_EMR1_EM0_Pos (0U)
8245 #define EXTI_EMR1_EM0_Msk (0x1UL << EXTI_EMR1_EM0_Pos) /*!< 0x00000001 */
8246 #define EXTI_EMR1_EM0 EXTI_EMR1_EM0_Msk /*!< Event Mask on line 0 */
8247 #define EXTI_EMR1_EM1_Pos (1U)
8248 #define EXTI_EMR1_EM1_Msk (0x1UL << EXTI_EMR1_EM1_Pos) /*!< 0x00000002 */
8249 #define EXTI_EMR1_EM1 EXTI_EMR1_EM1_Msk /*!< Event Mask on line 1 */
8250 #define EXTI_EMR1_EM2_Pos (2U)
8251 #define EXTI_EMR1_EM2_Msk (0x1UL << EXTI_EMR1_EM2_Pos) /*!< 0x00000004 */
8252 #define EXTI_EMR1_EM2 EXTI_EMR1_EM2_Msk /*!< Event Mask on line 2 */
8253 #define EXTI_EMR1_EM3_Pos (3U)
8254 #define EXTI_EMR1_EM3_Msk (0x1UL << EXTI_EMR1_EM3_Pos) /*!< 0x00000008 */
8255 #define EXTI_EMR1_EM3 EXTI_EMR1_EM3_Msk /*!< Event Mask on line 3 */
8256 #define EXTI_EMR1_EM4_Pos (4U)
8257 #define EXTI_EMR1_EM4_Msk (0x1UL << EXTI_EMR1_EM4_Pos) /*!< 0x00000010 */
8258 #define EXTI_EMR1_EM4 EXTI_EMR1_EM4_Msk /*!< Event Mask on line 4 */
8259 #define EXTI_EMR1_EM5_Pos (5U)
8260 #define EXTI_EMR1_EM5_Msk (0x1UL << EXTI_EMR1_EM5_Pos) /*!< 0x00000020 */
8261 #define EXTI_EMR1_EM5 EXTI_EMR1_EM5_Msk /*!< Event Mask on line 5 */
8262 #define EXTI_EMR1_EM6_Pos (6U)
8263 #define EXTI_EMR1_EM6_Msk (0x1UL << EXTI_EMR1_EM6_Pos) /*!< 0x00000040 */
8264 #define EXTI_EMR1_EM6 EXTI_EMR1_EM6_Msk /*!< Event Mask on line 6 */
8265 #define EXTI_EMR1_EM7_Pos (7U)
8266 #define EXTI_EMR1_EM7_Msk (0x1UL << EXTI_EMR1_EM7_Pos) /*!< 0x00000080 */
8267 #define EXTI_EMR1_EM7 EXTI_EMR1_EM7_Msk /*!< Event Mask on line 7 */
8268 #define EXTI_EMR1_EM8_Pos (8U)
8269 #define EXTI_EMR1_EM8_Msk (0x1UL << EXTI_EMR1_EM8_Pos) /*!< 0x00000100 */
8270 #define EXTI_EMR1_EM8 EXTI_EMR1_EM8_Msk /*!< Event Mask on line 8 */
8271 #define EXTI_EMR1_EM9_Pos (9U)
8272 #define EXTI_EMR1_EM9_Msk (0x1UL << EXTI_EMR1_EM9_Pos) /*!< 0x00000200 */
8273 #define EXTI_EMR1_EM9 EXTI_EMR1_EM9_Msk /*!< Event Mask on line 9 */
8274 #define EXTI_EMR1_EM10_Pos (10U)
8275 #define EXTI_EMR1_EM10_Msk (0x1UL << EXTI_EMR1_EM10_Pos) /*!< 0x00000400 */
8276 #define EXTI_EMR1_EM10 EXTI_EMR1_EM10_Msk /*!< Event Mask on line 10 */
8277 #define EXTI_EMR1_EM11_Pos (11U)
8278 #define EXTI_EMR1_EM11_Msk (0x1UL << EXTI_EMR1_EM11_Pos) /*!< 0x00000800 */
8279 #define EXTI_EMR1_EM11 EXTI_EMR1_EM11_Msk /*!< Event Mask on line 11 */
8280 #define EXTI_EMR1_EM12_Pos (12U)
8281 #define EXTI_EMR1_EM12_Msk (0x1UL << EXTI_EMR1_EM12_Pos) /*!< 0x00001000 */
8282 #define EXTI_EMR1_EM12 EXTI_EMR1_EM12_Msk /*!< Event Mask on line 12 */
8283 #define EXTI_EMR1_EM13_Pos (13U)
8284 #define EXTI_EMR1_EM13_Msk (0x1UL << EXTI_EMR1_EM13_Pos) /*!< 0x00002000 */
8285 #define EXTI_EMR1_EM13 EXTI_EMR1_EM13_Msk /*!< Event Mask on line 13 */
8286 #define EXTI_EMR1_EM14_Pos (14U)
8287 #define EXTI_EMR1_EM14_Msk (0x1UL << EXTI_EMR1_EM14_Pos) /*!< 0x00004000 */
8288 #define EXTI_EMR1_EM14 EXTI_EMR1_EM14_Msk /*!< Event Mask on line 14 */
8289 #define EXTI_EMR1_EM15_Pos (15U)
8290 #define EXTI_EMR1_EM15_Msk (0x1UL << EXTI_EMR1_EM15_Pos) /*!< 0x00008000 */
8291 #define EXTI_EMR1_EM15 EXTI_EMR1_EM15_Msk /*!< Event Mask on line 15 */
8292 #define EXTI_EMR1_EM16_Pos (16U)
8293 #define EXTI_EMR1_EM16_Msk (0x1UL << EXTI_EMR1_EM16_Pos) /*!< 0x00010000 */
8294 #define EXTI_EMR1_EM16 EXTI_EMR1_EM16_Msk /*!< Event Mask on line 16 */
8295 #define EXTI_EMR1_EM17_Pos (17U)
8296 #define EXTI_EMR1_EM17_Msk (0x1UL << EXTI_EMR1_EM17_Pos) /*!< 0x00020000 */
8297 #define EXTI_EMR1_EM17 EXTI_EMR1_EM17_Msk /*!< Event Mask on line 17 */
8298 #define EXTI_EMR1_EM18_Pos (18U)
8299 #define EXTI_EMR1_EM18_Msk (0x1UL << EXTI_EMR1_EM18_Pos) /*!< 0x00040000 */
8300 #define EXTI_EMR1_EM18 EXTI_EMR1_EM18_Msk /*!< Event Mask on line 18 */
8301 #define EXTI_EMR1_EM20_Pos (20U)
8302 #define EXTI_EMR1_EM20_Msk (0x1UL << EXTI_EMR1_EM20_Pos) /*!< 0x00100000 */
8303 #define EXTI_EMR1_EM20 EXTI_EMR1_EM20_Msk /*!< Event Mask on line 20 */
8304 #define EXTI_EMR1_EM21_Pos (21U)
8305 #define EXTI_EMR1_EM21_Msk (0x1UL << EXTI_EMR1_EM21_Pos) /*!< 0x00200000 */
8306 #define EXTI_EMR1_EM21 EXTI_EMR1_EM21_Msk /*!< Event Mask on line 21 */
8307 #define EXTI_EMR1_EM22_Pos (22U)
8308 #define EXTI_EMR1_EM22_Msk (0x1UL << EXTI_EMR1_EM22_Pos) /*!< 0x00400000 */
8309 #define EXTI_EMR1_EM22 EXTI_EMR1_EM22_Msk /*!< Event Mask on line 22 */
8310 #define EXTI_EMR1_EM23_Pos (23U)
8311 #define EXTI_EMR1_EM23_Msk (0x1UL << EXTI_EMR1_EM23_Pos) /*!< 0x00800000 */
8312 #define EXTI_EMR1_EM23 EXTI_EMR1_EM23_Msk /*!< Event Mask on line 23 */
8313 #define EXTI_EMR1_EM24_Pos (24U)
8314 #define EXTI_EMR1_EM24_Msk (0x1UL << EXTI_EMR1_EM24_Pos) /*!< 0x01000000 */
8315 #define EXTI_EMR1_EM24 EXTI_EMR1_EM24_Msk /*!< Event Mask on line 24 */
8316 #define EXTI_EMR1_EM25_Pos (25U)
8317 #define EXTI_EMR1_EM25_Msk (0x1UL << EXTI_EMR1_EM25_Pos) /*!< 0x02000000 */
8318 #define EXTI_EMR1_EM25 EXTI_EMR1_EM25_Msk /*!< Event Mask on line 25 */
8319 #define EXTI_EMR1_EM26_Pos (26U)
8320 #define EXTI_EMR1_EM26_Msk (0x1UL << EXTI_EMR1_EM26_Pos) /*!< 0x04000000 */
8321 #define EXTI_EMR1_EM26 EXTI_EMR1_EM26_Msk /*!< Event Mask on line 26 */
8322 #define EXTI_EMR1_EM27_Pos (27U)
8323 #define EXTI_EMR1_EM27_Msk (0x1UL << EXTI_EMR1_EM27_Pos) /*!< 0x08000000 */
8324 #define EXTI_EMR1_EM27 EXTI_EMR1_EM27_Msk /*!< Event Mask on line 27 */
8325 #define EXTI_EMR1_EM28_Pos (28U)
8326 #define EXTI_EMR1_EM28_Msk (0x1UL << EXTI_EMR1_EM28_Pos) /*!< 0x10000000 */
8327 #define EXTI_EMR1_EM28 EXTI_EMR1_EM28_Msk /*!< Event Mask on line 28 */
8328 #define EXTI_EMR1_EM29_Pos (29U)
8329 #define EXTI_EMR1_EM29_Msk (0x1UL << EXTI_EMR1_EM29_Pos) /*!< 0x20000000 */
8330 #define EXTI_EMR1_EM29 EXTI_EMR1_EM29_Msk /*!< Event Mask on line 29 */
8331 #define EXTI_EMR1_EM30_Pos (30U)
8332 #define EXTI_EMR1_EM30_Msk (0x1UL << EXTI_EMR1_EM30_Pos) /*!< 0x40000000 */
8333 #define EXTI_EMR1_EM30 EXTI_EMR1_EM30_Msk /*!< Event Mask on line 30 */
8334 #define EXTI_EMR1_EM31_Pos (31U)
8335 #define EXTI_EMR1_EM31_Msk (0x1UL << EXTI_EMR1_EM31_Pos) /*!< 0x80000000 */
8336 #define EXTI_EMR1_EM31 EXTI_EMR1_EM31_Msk /*!< Event Mask on line 31 */
8337
8338 /******************* Bit definition for EXTI_PR1 register ********************/
8339 #define EXTI_PR1_PR_Pos (0U)
8340 #define EXTI_PR1_PR_Msk (0x3FFFFFUL << EXTI_PR1_PR_Pos) /*!< 0x003FFFFF */
8341 #define EXTI_PR1_PR EXTI_PR1_PR_Msk /*!< Pending bit */
8342 #define EXTI_PR1_PR0_Pos (0U)
8343 #define EXTI_PR1_PR0_Msk (0x1UL << EXTI_PR1_PR0_Pos) /*!< 0x00000001 */
8344 #define EXTI_PR1_PR0 EXTI_PR1_PR0_Msk /*!< Pending bit for line 0 */
8345 #define EXTI_PR1_PR1_Pos (1U)
8346 #define EXTI_PR1_PR1_Msk (0x1UL << EXTI_PR1_PR1_Pos) /*!< 0x00000002 */
8347 #define EXTI_PR1_PR1 EXTI_PR1_PR1_Msk /*!< Pending bit for line 1 */
8348 #define EXTI_PR1_PR2_Pos (2U)
8349 #define EXTI_PR1_PR2_Msk (0x1UL << EXTI_PR1_PR2_Pos) /*!< 0x00000004 */
8350 #define EXTI_PR1_PR2 EXTI_PR1_PR2_Msk /*!< Pending bit for line 2 */
8351 #define EXTI_PR1_PR3_Pos (3U)
8352 #define EXTI_PR1_PR3_Msk (0x1UL << EXTI_PR1_PR3_Pos) /*!< 0x00000008 */
8353 #define EXTI_PR1_PR3 EXTI_PR1_PR3_Msk /*!< Pending bit for line 3 */
8354 #define EXTI_PR1_PR4_Pos (4U)
8355 #define EXTI_PR1_PR4_Msk (0x1UL << EXTI_PR1_PR4_Pos) /*!< 0x00000010 */
8356 #define EXTI_PR1_PR4 EXTI_PR1_PR4_Msk /*!< Pending bit for line 4 */
8357 #define EXTI_PR1_PR5_Pos (5U)
8358 #define EXTI_PR1_PR5_Msk (0x1UL << EXTI_PR1_PR5_Pos) /*!< 0x00000020 */
8359 #define EXTI_PR1_PR5 EXTI_PR1_PR5_Msk /*!< Pending bit for line 5 */
8360 #define EXTI_PR1_PR6_Pos (6U)
8361 #define EXTI_PR1_PR6_Msk (0x1UL << EXTI_PR1_PR6_Pos) /*!< 0x00000040 */
8362 #define EXTI_PR1_PR6 EXTI_PR1_PR6_Msk /*!< Pending bit for line 6 */
8363 #define EXTI_PR1_PR7_Pos (7U)
8364 #define EXTI_PR1_PR7_Msk (0x1UL << EXTI_PR1_PR7_Pos) /*!< 0x00000080 */
8365 #define EXTI_PR1_PR7 EXTI_PR1_PR7_Msk /*!< Pending bit for line 7 */
8366 #define EXTI_PR1_PR8_Pos (8U)
8367 #define EXTI_PR1_PR8_Msk (0x1UL << EXTI_PR1_PR8_Pos) /*!< 0x00000100 */
8368 #define EXTI_PR1_PR8 EXTI_PR1_PR8_Msk /*!< Pending bit for line 8 */
8369 #define EXTI_PR1_PR9_Pos (9U)
8370 #define EXTI_PR1_PR9_Msk (0x1UL << EXTI_PR1_PR9_Pos) /*!< 0x00000200 */
8371 #define EXTI_PR1_PR9 EXTI_PR1_PR9_Msk /*!< Pending bit for line 9 */
8372 #define EXTI_PR1_PR10_Pos (10U)
8373 #define EXTI_PR1_PR10_Msk (0x1UL << EXTI_PR1_PR10_Pos) /*!< 0x00000400 */
8374 #define EXTI_PR1_PR10 EXTI_PR1_PR10_Msk /*!< Pending bit for line 10 */
8375 #define EXTI_PR1_PR11_Pos (11U)
8376 #define EXTI_PR1_PR11_Msk (0x1UL << EXTI_PR1_PR11_Pos) /*!< 0x00000800 */
8377 #define EXTI_PR1_PR11 EXTI_PR1_PR11_Msk /*!< Pending bit for line 11 */
8378 #define EXTI_PR1_PR12_Pos (12U)
8379 #define EXTI_PR1_PR12_Msk (0x1UL << EXTI_PR1_PR12_Pos) /*!< 0x00001000 */
8380 #define EXTI_PR1_PR12 EXTI_PR1_PR12_Msk /*!< Pending bit for line 12 */
8381 #define EXTI_PR1_PR13_Pos (13U)
8382 #define EXTI_PR1_PR13_Msk (0x1UL << EXTI_PR1_PR13_Pos) /*!< 0x00002000 */
8383 #define EXTI_PR1_PR13 EXTI_PR1_PR13_Msk /*!< Pending bit for line 13 */
8384 #define EXTI_PR1_PR14_Pos (14U)
8385 #define EXTI_PR1_PR14_Msk (0x1UL << EXTI_PR1_PR14_Pos) /*!< 0x00004000 */
8386 #define EXTI_PR1_PR14 EXTI_PR1_PR14_Msk /*!< Pending bit for line 14 */
8387 #define EXTI_PR1_PR15_Pos (15U)
8388 #define EXTI_PR1_PR15_Msk (0x1UL << EXTI_PR1_PR15_Pos) /*!< 0x00008000 */
8389 #define EXTI_PR1_PR15 EXTI_PR1_PR15_Msk /*!< Pending bit for line 15 */
8390 #define EXTI_PR1_PR16_Pos (16U)
8391 #define EXTI_PR1_PR16_Msk (0x1UL << EXTI_PR1_PR16_Pos) /*!< 0x00010000 */
8392 #define EXTI_PR1_PR16 EXTI_PR1_PR16_Msk /*!< Pending bit for line 16 */
8393 #define EXTI_PR1_PR17_Pos (17U)
8394 #define EXTI_PR1_PR17_Msk (0x1UL << EXTI_PR1_PR17_Pos) /*!< 0x00020000 */
8395 #define EXTI_PR1_PR17 EXTI_PR1_PR17_Msk /*!< Pending bit for line 17 */
8396 #define EXTI_PR1_PR18_Pos (18U)
8397 #define EXTI_PR1_PR18_Msk (0x1UL << EXTI_PR1_PR18_Pos) /*!< 0x00040000 */
8398 #define EXTI_PR1_PR18 EXTI_PR1_PR18_Msk /*!< Pending bit for line 18 */
8399 #define EXTI_PR1_PR19_Pos (19U)
8400 #define EXTI_PR1_PR19_Msk (0x1UL << EXTI_PR1_PR19_Pos) /*!< 0x00080000 */
8401 #define EXTI_PR1_PR19 EXTI_PR1_PR19_Msk /*!< Pending bit for line 19 */
8402 #define EXTI_PR1_PR20_Pos (20U)
8403 #define EXTI_PR1_PR20_Msk (0x1UL << EXTI_PR1_PR20_Pos) /*!< 0x00100000 */
8404 #define EXTI_PR1_PR20 EXTI_PR1_PR20_Msk /*!< Pending bit for line 20 */
8405 #define EXTI_PR1_PR21_Pos (21U)
8406 #define EXTI_PR1_PR21_Msk (0x1UL << EXTI_PR1_PR21_Pos) /*!< 0x00200000 */
8407 #define EXTI_PR1_PR21 EXTI_PR1_PR21_Msk /*!< Pending bit for line 21 */
8408
8409 /******************* Bit definition for EXTI_IMR2 register *******************/
8410 #define EXTI_IMR2_IM_Pos (0U)
8411 #define EXTI_IMR2_IM_Msk (0xFFFF8FFFUL << EXTI_IMR2_IM_Pos) /*!< 0xFFFF8FFF */
8412 #define EXTI_IMR2_IM EXTI_IMR2_IM_Msk /*!< Interrupt Mask */
8413 #define EXTI_IMR2_IM32_Pos (0U)
8414 #define EXTI_IMR2_IM32_Msk (0x1UL << EXTI_IMR2_IM32_Pos) /*!< 0x00000001 */
8415 #define EXTI_IMR2_IM32 EXTI_IMR2_IM32_Msk /*!< Interrupt Mask on line 32 */
8416 #define EXTI_IMR2_IM33_Pos (1U)
8417 #define EXTI_IMR2_IM33_Msk (0x1UL << EXTI_IMR2_IM33_Pos) /*!< 0x00000002 */
8418 #define EXTI_IMR2_IM33 EXTI_IMR2_IM33_Msk /*!< Interrupt Mask on line 33 */
8419 #define EXTI_IMR2_IM34_Pos (2U)
8420 #define EXTI_IMR2_IM34_Msk (0x1UL << EXTI_IMR2_IM34_Pos) /*!< 0x00000004 */
8421 #define EXTI_IMR2_IM34 EXTI_IMR2_IM34_Msk /*!< Interrupt Mask on line 34 */
8422 #define EXTI_IMR2_IM35_Pos (3U)
8423 #define EXTI_IMR2_IM35_Msk (0x1UL << EXTI_IMR2_IM35_Pos) /*!< 0x00000008 */
8424 #define EXTI_IMR2_IM35 EXTI_IMR2_IM35_Msk /*!< Interrupt Mask on line 35 */
8425 #define EXTI_IMR2_IM36_Pos (4U)
8426 #define EXTI_IMR2_IM36_Msk (0x1UL << EXTI_IMR2_IM36_Pos) /*!< 0x00000010 */
8427 #define EXTI_IMR2_IM36 EXTI_IMR2_IM36_Msk /*!< Interrupt Mask on line 36 */
8428 #define EXTI_IMR2_IM37_Pos (5U)
8429 #define EXTI_IMR2_IM37_Msk (0x1UL << EXTI_IMR2_IM37_Pos) /*!< 0x00000020 */
8430 #define EXTI_IMR2_IM37 EXTI_IMR2_IM37_Msk /*!< Interrupt Mask on line 37 */
8431 #define EXTI_IMR2_IM38_Pos (6U)
8432 #define EXTI_IMR2_IM38_Msk (0x1UL << EXTI_IMR2_IM38_Pos) /*!< 0x00000040 */
8433 #define EXTI_IMR2_IM38 EXTI_IMR2_IM38_Msk /*!< Interrupt Mask on line 38 */
8434 #define EXTI_IMR2_IM39_Pos (7U)
8435 #define EXTI_IMR2_IM39_Msk (0x1UL << EXTI_IMR2_IM39_Pos) /*!< 0x00000080 */
8436 #define EXTI_IMR2_IM39 EXTI_IMR2_IM39_Msk /*!< Interrupt Mask on line 39 */
8437 #define EXTI_IMR2_IM40_Pos (8U)
8438 #define EXTI_IMR2_IM40_Msk (0x1UL << EXTI_IMR2_IM40_Pos) /*!< 0x00000100 */
8439 #define EXTI_IMR2_IM40 EXTI_IMR2_IM40_Msk /*!< Interrupt Mask on line 40 */
8440 #define EXTI_IMR2_IM41_Pos (9U)
8441 #define EXTI_IMR2_IM41_Msk (0x1UL << EXTI_IMR2_IM41_Pos) /*!< 0x00000200 */
8442 #define EXTI_IMR2_IM41 EXTI_IMR2_IM41_Msk /*!< Interrupt Mask on line 41 */
8443 #define EXTI_IMR2_IM42_Pos (10U)
8444 #define EXTI_IMR2_IM42_Msk (0x1UL << EXTI_IMR2_IM42_Pos) /*!< 0x00000400 */
8445 #define EXTI_IMR2_IM42 EXTI_IMR2_IM42_Msk /*!< Interrupt Mask on line 42 */
8446 #define EXTI_IMR2_IM43_Pos (11U)
8447 #define EXTI_IMR2_IM43_Msk (0x1UL << EXTI_IMR2_IM43_Pos) /*!< 0x00000800 */
8448 #define EXTI_IMR2_IM43 EXTI_IMR2_IM43_Msk /*!< Interrupt Mask on line 43 */
8449 #define EXTI_IMR2_IM47_Pos (15U)
8450 #define EXTI_IMR2_IM47_Msk (0x1UL << EXTI_IMR2_IM47_Pos) /*!< 0x00008000 */
8451 #define EXTI_IMR2_IM47 EXTI_IMR2_IM47_Msk /*!< Interrupt Mask on line 47 */
8452 #define EXTI_IMR2_IM48_Pos (16U)
8453 #define EXTI_IMR2_IM48_Msk (0x1UL << EXTI_IMR2_IM48_Pos) /*!< 0x00010000 */
8454 #define EXTI_IMR2_IM48 EXTI_IMR2_IM48_Msk /*!< Interrupt Mask on line 48 */
8455 #define EXTI_IMR2_IM49_Pos (17U)
8456 #define EXTI_IMR2_IM49_Msk (0x1UL << EXTI_IMR2_IM49_Pos) /*!< 0x00020000 */
8457 #define EXTI_IMR2_IM49 EXTI_IMR2_IM49_Msk /*!< Interrupt Mask on line 49 */
8458 #define EXTI_IMR2_IM50_Pos (18U)
8459 #define EXTI_IMR2_IM50_Msk (0x1UL << EXTI_IMR2_IM50_Pos) /*!< 0x00040000 */
8460 #define EXTI_IMR2_IM50 EXTI_IMR2_IM50_Msk /*!< Interrupt Mask on line 50 */
8461 #define EXTI_IMR2_IM51_Pos (19U)
8462 #define EXTI_IMR2_IM51_Msk (0x1UL << EXTI_IMR2_IM51_Pos) /*!< 0x00080000 */
8463 #define EXTI_IMR2_IM51 EXTI_IMR2_IM51_Msk /*!< Interrupt Mask on line 51 */
8464 #define EXTI_IMR2_IM52_Pos (20U)
8465 #define EXTI_IMR2_IM52_Msk (0x1UL << EXTI_IMR2_IM52_Pos) /*!< 0x00100000 */
8466 #define EXTI_IMR2_IM52 EXTI_IMR2_IM52_Msk /*!< Interrupt Mask on line 52 */
8467 #define EXTI_IMR2_IM53_Pos (21U)
8468 #define EXTI_IMR2_IM53_Msk (0x1UL << EXTI_IMR2_IM53_Pos) /*!< 0x00200000 */
8469 #define EXTI_IMR2_IM53 EXTI_IMR2_IM53_Msk /*!< Interrupt Mask on line 53 */
8470 #define EXTI_IMR2_IM54_Pos (22U)
8471 #define EXTI_IMR2_IM54_Msk (0x1UL << EXTI_IMR2_IM54_Pos) /*!< 0x00400000 */
8472 #define EXTI_IMR2_IM54 EXTI_IMR2_IM54_Msk /*!< Interrupt Mask on line 54 */
8473 #define EXTI_IMR2_IM55_Pos (23U)
8474 #define EXTI_IMR2_IM55_Msk (0x1UL << EXTI_IMR2_IM55_Pos) /*!< 0x00800000 */
8475 #define EXTI_IMR2_IM55 EXTI_IMR2_IM55_Msk /*!< Interrupt Mask on line 55 */
8476 #define EXTI_IMR2_IM56_Pos (24U)
8477 #define EXTI_IMR2_IM56_Msk (0x1UL << EXTI_IMR2_IM56_Pos) /*!< 0x01000000 */
8478 #define EXTI_IMR2_IM56 EXTI_IMR2_IM56_Msk /*!< Interrupt Mask on line 56 */
8479 #define EXTI_IMR2_IM57_Pos (25U)
8480 #define EXTI_IMR2_IM57_Msk (0x1UL << EXTI_IMR2_IM57_Pos) /*!< 0x02000000 */
8481 #define EXTI_IMR2_IM57 EXTI_IMR2_IM57_Msk /*!< Interrupt Mask on line 57 */
8482 #define EXTI_IMR2_IM58_Pos (26U)
8483 #define EXTI_IMR2_IM58_Msk (0x1UL << EXTI_IMR2_IM58_Pos) /*!< 0x04000000 */
8484 #define EXTI_IMR2_IM58 EXTI_IMR2_IM58_Msk /*!< Interrupt Mask on line 58 */
8485 #define EXTI_IMR2_IM59_Pos (27U)
8486 #define EXTI_IMR2_IM59_Msk (0x1UL << EXTI_IMR2_IM59_Pos) /*!< 0x08000000 */
8487 #define EXTI_IMR2_IM59 EXTI_IMR2_IM59_Msk /*!< Interrupt Mask on line 59 */
8488 #define EXTI_IMR2_IM60_Pos (28U)
8489 #define EXTI_IMR2_IM60_Msk (0x1UL << EXTI_IMR2_IM60_Pos) /*!< 0x10000000 */
8490 #define EXTI_IMR2_IM60 EXTI_IMR2_IM60_Msk /*!< Interrupt Mask on line 60 */
8491 #define EXTI_IMR2_IM61_Pos (29U)
8492 #define EXTI_IMR2_IM61_Msk (0x1UL << EXTI_IMR2_IM61_Pos) /*!< 0x20000000 */
8493 #define EXTI_IMR2_IM61 EXTI_IMR2_IM61_Msk /*!< Interrupt Mask on line 61 */
8494 #define EXTI_IMR2_IM62_Pos (30U)
8495 #define EXTI_IMR2_IM62_Msk (0x1UL << EXTI_IMR2_IM62_Pos) /*!< 0x40000000 */
8496 #define EXTI_IMR2_IM62 EXTI_IMR2_IM62_Msk /*!< Interrupt Mask on line 62 */
8497 #define EXTI_IMR2_IM63_Pos (31U)
8498 #define EXTI_IMR2_IM63_Msk (0x1UL << EXTI_IMR2_IM63_Pos) /*!< 0x80000000 */
8499 #define EXTI_IMR2_IM63 EXTI_IMR2_IM63_Msk /*!< Interrupt Mask on line 63 */
8500
8501 /******************* Bit definition for EXTI_EMR2 register *******************/
8502 #define EXTI_EMR2_EM_Pos (0U)
8503 #define EXTI_EMR2_EM_Msk (0xFFFF8FFFUL << EXTI_EMR2_EM_Pos) /*!< 0xFFFF8FFF */
8504 #define EXTI_EMR2_EM EXTI_EMR2_EM_Msk /*!< Event Mask */
8505 #define EXTI_EMR2_EM32_Pos (0U)
8506 #define EXTI_EMR2_EM32_Msk (0x1UL << EXTI_EMR2_EM32_Pos) /*!< 0x00000001 */
8507 #define EXTI_EMR2_EM32 EXTI_EMR2_EM32_Msk /*!< Event Mask on line 32*/
8508 #define EXTI_EMR2_EM33_Pos (1U)
8509 #define EXTI_EMR2_EM33_Msk (0x1UL << EXTI_EMR2_EM33_Pos) /*!< 0x00000002 */
8510 #define EXTI_EMR2_EM33 EXTI_EMR2_EM33_Msk /*!< Event Mask on line 33*/
8511 #define EXTI_EMR2_EM34_Pos (2U)
8512 #define EXTI_EMR2_EM34_Msk (0x1UL << EXTI_EMR2_EM34_Pos) /*!< 0x00000004 */
8513 #define EXTI_EMR2_EM34 EXTI_EMR2_EM34_Msk /*!< Event Mask on line 34*/
8514 #define EXTI_EMR2_EM35_Pos (3U)
8515 #define EXTI_EMR2_EM35_Msk (0x1UL << EXTI_EMR2_EM35_Pos) /*!< 0x00000008 */
8516 #define EXTI_EMR2_EM35 EXTI_EMR2_EM35_Msk /*!< Event Mask on line 35*/
8517 #define EXTI_EMR2_EM36_Pos (4U)
8518 #define EXTI_EMR2_EM36_Msk (0x1UL << EXTI_EMR2_EM36_Pos) /*!< 0x00000010 */
8519 #define EXTI_EMR2_EM36 EXTI_EMR2_EM36_Msk /*!< Event Mask on line 36*/
8520 #define EXTI_EMR2_EM37_Pos (5U)
8521 #define EXTI_EMR2_EM37_Msk (0x1UL << EXTI_EMR2_EM37_Pos) /*!< 0x00000020 */
8522 #define EXTI_EMR2_EM37 EXTI_EMR2_EM37_Msk /*!< Event Mask on line 37*/
8523 #define EXTI_EMR2_EM38_Pos (6U)
8524 #define EXTI_EMR2_EM38_Msk (0x1UL << EXTI_EMR2_EM38_Pos) /*!< 0x00000040 */
8525 #define EXTI_EMR2_EM38 EXTI_EMR2_EM38_Msk /*!< Event Mask on line 38*/
8526 #define EXTI_EMR2_EM39_Pos (7U)
8527 #define EXTI_EMR2_EM39_Msk (0x1UL << EXTI_EMR2_EM39_Pos) /*!< 0x00000080 */
8528 #define EXTI_EMR2_EM39 EXTI_EMR2_EM39_Msk /*!< Event Mask on line 39*/
8529 #define EXTI_EMR2_EM40_Pos (8U)
8530 #define EXTI_EMR2_EM40_Msk (0x1UL << EXTI_EMR2_EM40_Pos) /*!< 0x00000100 */
8531 #define EXTI_EMR2_EM40 EXTI_EMR2_EM40_Msk /*!< Event Mask on line 40*/
8532 #define EXTI_EMR2_EM41_Pos (9U)
8533 #define EXTI_EMR2_EM41_Msk (0x1UL << EXTI_EMR2_EM41_Pos) /*!< 0x00000200 */
8534 #define EXTI_EMR2_EM41 EXTI_EMR2_EM41_Msk /*!< Event Mask on line 41*/
8535 #define EXTI_EMR2_EM42_Pos (10U)
8536 #define EXTI_EMR2_EM42_Msk (0x1UL << EXTI_EMR2_EM42_Pos) /*!< 0x00000400 */
8537 #define EXTI_EMR2_EM42 EXTI_EMR2_EM42_Msk /*!< Event Mask on line 42 */
8538 #define EXTI_EMR2_EM43_Pos (11U)
8539 #define EXTI_EMR2_EM43_Msk (0x1UL << EXTI_EMR2_EM43_Pos) /*!< 0x00000800 */
8540 #define EXTI_EMR2_EM43 EXTI_EMR2_EM43_Msk /*!< Event Mask on line 43 */
8541 #define EXTI_EMR2_EM47_Pos (15U)
8542 #define EXTI_EMR2_EM47_Msk (0x1UL << EXTI_EMR2_EM47_Pos) /*!< 0x00008000 */
8543 #define EXTI_EMR2_EM47 EXTI_EMR2_EM47_Msk /*!< Event Mask on line 47 */
8544 #define EXTI_EMR2_EM48_Pos (16U)
8545 #define EXTI_EMR2_EM48_Msk (0x1UL << EXTI_EMR2_EM48_Pos) /*!< 0x00010000 */
8546 #define EXTI_EMR2_EM48 EXTI_EMR2_EM48_Msk /*!< Event Mask on line 48 */
8547 #define EXTI_EMR2_EM49_Pos (17U)
8548 #define EXTI_EMR2_EM49_Msk (0x1UL << EXTI_EMR2_EM49_Pos) /*!< 0x00020000 */
8549 #define EXTI_EMR2_EM49 EXTI_EMR2_EM49_Msk /*!< Event Mask on line 49 */
8550 #define EXTI_EMR2_EM50_Pos (18U)
8551 #define EXTI_EMR2_EM50_Msk (0x1UL << EXTI_EMR2_EM50_Pos) /*!< 0x00040000 */
8552 #define EXTI_EMR2_EM50 EXTI_EMR2_EM50_Msk /*!< Event Mask on line 50 */
8553 #define EXTI_EMR2_EM51_Pos (19U)
8554 #define EXTI_EMR2_EM51_Msk (0x1UL << EXTI_EMR2_EM51_Pos) /*!< 0x00080000 */
8555 #define EXTI_EMR2_EM51 EXTI_EMR2_EM51_Msk /*!< Event Mask on line 51 */
8556 #define EXTI_EMR2_EM52_Pos (20U)
8557 #define EXTI_EMR2_EM52_Msk (0x1UL << EXTI_EMR2_EM52_Pos) /*!< 0x00100000 */
8558 #define EXTI_EMR2_EM52 EXTI_EMR2_EM52_Msk /*!< Event Mask on line 52 */
8559 #define EXTI_EMR2_EM53_Pos (21U)
8560 #define EXTI_EMR2_EM53_Msk (0x1UL << EXTI_EMR2_EM53_Pos) /*!< 0x00200000 */
8561 #define EXTI_EMR2_EM53 EXTI_EMR2_EM53_Msk /*!< Event Mask on line 53 */
8562 #define EXTI_EMR2_EM54_Pos (22U)
8563 #define EXTI_EMR2_EM54_Msk (0x1UL << EXTI_EMR2_EM54_Pos) /*!< 0x00400000 */
8564 #define EXTI_EMR2_EM54 EXTI_EMR2_EM54_Msk /*!< Event Mask on line 54 */
8565 #define EXTI_EMR2_EM55_Pos (23U)
8566 #define EXTI_EMR2_EM55_Msk (0x1UL << EXTI_EMR2_EM55_Pos) /*!< 0x00800000 */
8567 #define EXTI_EMR2_EM55 EXTI_EMR2_EM55_Msk /*!< Event Mask on line 55 */
8568 #define EXTI_EMR2_EM56_Pos (24U)
8569 #define EXTI_EMR2_EM56_Msk (0x1UL << EXTI_EMR2_EM56_Pos) /*!< 0x01000000 */
8570 #define EXTI_EMR2_EM56 EXTI_EMR2_EM56_Msk /*!< Event Mask on line 56 */
8571 #define EXTI_EMR2_EM57_Pos (25U)
8572 #define EXTI_EMR2_EM57_Msk (0x1UL << EXTI_EMR2_EM57_Pos) /*!< 0x02000000 */
8573 #define EXTI_EMR2_EM57 EXTI_EMR2_EM57_Msk /*!< Event Mask on line 57 */
8574 #define EXTI_EMR2_EM58_Pos (26U)
8575 #define EXTI_EMR2_EM58_Msk (0x1UL << EXTI_EMR2_EM58_Pos) /*!< 0x04000000 */
8576 #define EXTI_EMR2_EM58 EXTI_EMR2_EM58_Msk /*!< Event Mask on line 58 */
8577 #define EXTI_EMR2_EM59_Pos (27U)
8578 #define EXTI_EMR2_EM59_Msk (0x1UL << EXTI_EMR2_EM59_Pos) /*!< 0x08000000 */
8579 #define EXTI_EMR2_EM59 EXTI_EMR2_EM59_Msk /*!< Event Mask on line 59 */
8580 #define EXTI_EMR2_EM60_Pos (28U)
8581 #define EXTI_EMR2_EM60_Msk (0x1UL << EXTI_EMR2_EM60_Pos) /*!< 0x10000000 */
8582 #define EXTI_EMR2_EM60 EXTI_EMR2_EM60_Msk /*!< Event Mask on line 60 */
8583 #define EXTI_EMR2_EM61_Pos (29U)
8584 #define EXTI_EMR2_EM61_Msk (0x1UL << EXTI_EMR2_EM61_Pos) /*!< 0x20000000 */
8585 #define EXTI_EMR2_EM61 EXTI_EMR2_EM61_Msk /*!< Event Mask on line 61 */
8586 #define EXTI_EMR2_EM62_Pos (30U)
8587 #define EXTI_EMR2_EM62_Msk (0x1UL << EXTI_EMR2_EM62_Pos) /*!< 0x40000000 */
8588 #define EXTI_EMR2_EM62 EXTI_EMR2_EM62_Msk /*!< Event Mask on line 62 */
8589 #define EXTI_EMR2_EM63_Pos (31U)
8590 #define EXTI_EMR2_EM63_Msk (0x1UL << EXTI_EMR2_EM63_Pos) /*!< 0x80000000 */
8591 #define EXTI_EMR2_EM63 EXTI_EMR2_EM63_Msk /*!< Event Mask on line 63 */
8592
8593 /******************* Bit definition for EXTI_PR2 register ********************/
8594 #define EXTI_PR2_PR_Pos (17U)
8595 #define EXTI_PR2_PR_Msk (0x5UL << EXTI_PR2_PR_Pos) /*!< 0x000A0000 */
8596 #define EXTI_PR2_PR EXTI_PR2_PR_Msk /*!< Pending bit */
8597 #define EXTI_PR2_PR49_Pos (17U)
8598 #define EXTI_PR2_PR49_Msk (0x1UL << EXTI_PR2_PR49_Pos) /*!< 0x00020000 */
8599 #define EXTI_PR2_PR49 EXTI_PR2_PR49_Msk /*!< Pending bit for line 49 */
8600 #define EXTI_PR2_PR51_Pos (19U)
8601 #define EXTI_PR2_PR51_Msk (0x1UL << EXTI_PR2_PR51_Pos) /*!< 0x00080000 */
8602 #define EXTI_PR2_PR51 EXTI_PR2_PR51_Msk /*!< Pending bit for line 51 */
8603
8604 /******************* Bit definition for EXTI_IMR3 register *******************/
8605 #define EXTI_IMR3_IM_Pos (0U)
8606 #define EXTI_IMR3_IM_Msk (0x001A527FFUL << EXTI_IMR3_IM_Pos) /*!< 0x001A527FF */
8607 #define EXTI_IMR3_IM EXTI_IMR3_IM_Msk /*!< Interrupt Mask */
8608 #define EXTI_IMR3_IM64_Pos (0U)
8609 #define EXTI_IMR3_IM64_Msk (0x1UL << EXTI_IMR3_IM64_Pos) /*!< 0x00000001 */
8610 #define EXTI_IMR3_IM64 EXTI_IMR3_IM64_Msk /*!< Interrupt Mask on line 64 */
8611 #define EXTI_IMR3_IM65_Pos (1U)
8612 #define EXTI_IMR3_IM65_Msk (0x1UL << EXTI_IMR3_IM65_Pos) /*!< 0x00000002 */
8613 #define EXTI_IMR3_IM65 EXTI_IMR3_IM65_Msk /*!< Interrupt Mask on line 65 */
8614 #define EXTI_IMR3_IM66_Pos (2U)
8615 #define EXTI_IMR3_IM66_Msk (0x1UL << EXTI_IMR3_IM66_Pos) /*!< 0x00000004 */
8616 #define EXTI_IMR3_IM66 EXTI_IMR3_IM66_Msk /*!< Interrupt Mask on line 66 */
8617 #define EXTI_IMR3_IM67_Pos (3U)
8618 #define EXTI_IMR3_IM67_Msk (0x1UL << EXTI_IMR3_IM67_Pos) /*!< 0x00000008 */
8619 #define EXTI_IMR3_IM67 EXTI_IMR3_IM67_Msk /*!< Interrupt Mask on line 67 */
8620 #define EXTI_IMR3_IM68_Pos (4U)
8621 #define EXTI_IMR3_IM68_Msk (0x1UL << EXTI_IMR3_IM68_Pos) /*!< 0x00000010 */
8622 #define EXTI_IMR3_IM68 EXTI_IMR3_IM68_Msk /*!< Interrupt Mask on line 68 */
8623 #define EXTI_IMR3_IM69_Pos (5U)
8624 #define EXTI_IMR3_IM69_Msk (0x1UL << EXTI_IMR3_IM69_Pos) /*!< 0x00000020 */
8625 #define EXTI_IMR3_IM69 EXTI_IMR3_IM69_Msk /*!< Interrupt Mask on line 69 */
8626 #define EXTI_IMR3_IM70_Pos (6U)
8627 #define EXTI_IMR3_IM70_Msk (0x1UL << EXTI_IMR3_IM70_Pos) /*!< 0x00000040 */
8628 #define EXTI_IMR3_IM70 EXTI_IMR3_IM70_Msk /*!< Interrupt Mask on line 70 */
8629 #define EXTI_IMR3_IM71_Pos (7U)
8630 #define EXTI_IMR3_IM71_Msk (0x1UL << EXTI_IMR3_IM71_Pos) /*!< 0x00000080 */
8631 #define EXTI_IMR3_IM71 EXTI_IMR3_IM71_Msk /*!< Interrupt Mask on line 71 */
8632 #define EXTI_IMR3_IM72_Pos (8U)
8633 #define EXTI_IMR3_IM72_Msk (0x1UL << EXTI_IMR3_IM72_Pos) /*!< 0x00000100 */
8634 #define EXTI_IMR3_IM72 EXTI_IMR3_IM72_Msk /*!< Interrupt Mask on line 72 */
8635 #define EXTI_IMR3_IM73_Pos (9U)
8636 #define EXTI_IMR3_IM73_Msk (0x1UL << EXTI_IMR3_IM73_Pos) /*!< 0x00000200 */
8637 #define EXTI_IMR3_IM73 EXTI_IMR3_IM73_Msk /*!< Interrupt Mask on line 73 */
8638 #define EXTI_IMR3_IM74_Pos (10U)
8639 #define EXTI_IMR3_IM74_Msk (0x1UL << EXTI_IMR3_IM74_Pos) /*!< 0x00000400 */
8640 #define EXTI_IMR3_IM74 EXTI_IMR3_IM74_Msk /*!< Interrupt Mask on line 74 */
8641 #define EXTI_IMR3_IM77_Pos (13U)
8642 #define EXTI_IMR3_IM77_Msk (0x1UL << EXTI_IMR3_IM77_Pos) /*!< 0x00002000 */
8643 #define EXTI_IMR3_IM77 EXTI_IMR3_IM77_Msk /*!< Interrupt Mask on line 77 */
8644 #define EXTI_IMR3_IM80_Pos (16U)
8645 #define EXTI_IMR3_IM80_Msk (0x1UL << EXTI_IMR3_IM80_Pos) /*!< 0x00010000 */
8646 #define EXTI_IMR3_IM80 EXTI_IMR3_IM80_Msk /*!< Interrupt Mask on line 80 */
8647 #define EXTI_IMR3_IM82_Pos (18U)
8648 #define EXTI_IMR3_IM82_Msk (0x1UL << EXTI_IMR3_IM82_Pos) /*!< 0x00040000 */
8649 #define EXTI_IMR3_IM82 EXTI_IMR3_IM82_Msk /*!< Interrupt Mask on line 82 */
8650 #define EXTI_IMR3_IM85_Pos (21U)
8651 #define EXTI_IMR3_IM85_Msk (0x1UL << EXTI_IMR3_IM85_Pos) /*!< 0x00200000 */
8652 #define EXTI_IMR3_IM85 EXTI_IMR3_IM85_Msk /*!< Interrupt Mask on line 85 */
8653 #define EXTI_IMR3_IM87_Pos (23U)
8654 #define EXTI_IMR3_IM87_Msk (0x1UL << EXTI_IMR3_IM87_Pos) /*!< 0x00800000 */
8655 #define EXTI_IMR3_IM87 EXTI_IMR3_IM87_Msk /*!< Interrupt Mask on line 87 */
8656
8657
8658 #define EXTI_IMR3_IM88_Pos (24U)
8659 #define EXTI_IMR3_IM88_Msk (0x1UL << EXTI_IMR3_IM88_Pos) /*!< 0x01000000 */
8660 #define EXTI_IMR3_IM88 EXTI_IMR3_IM88_Msk /*!< Interrupt Mask on line 88 */
8661
8662 /******************* Bit definition for EXTI_EMR3 register *******************/
8663 #define EXTI_EMR3_EM_Pos (0U)
8664 #define EXTI_EMR3_EM_Msk (0x01A527FFUL << EXTI_EMR3_EM_Pos) /*!< 0x01A527FF */
8665 #define EXTI_EMR3_EM EXTI_EMR3_EM_Msk /*!< Event Mask */
8666 #define EXTI_EMR3_EM64_Pos (0U)
8667 #define EXTI_EMR3_EM64_Msk (0x1UL << EXTI_EMR3_EM64_Pos) /*!< 0x00000001 */
8668 #define EXTI_EMR3_EM64 EXTI_EMR3_EM64_Msk /*!< Event Mask on line 64*/
8669 #define EXTI_EMR3_EM65_Pos (1U)
8670 #define EXTI_EMR3_EM65_Msk (0x1UL << EXTI_EMR3_EM65_Pos) /*!< 0x00000002 */
8671 #define EXTI_EMR3_EM65 EXTI_EMR3_EM65_Msk /*!< Event Mask on line 65*/
8672 #define EXTI_EMR3_EM66_Pos (2U)
8673 #define EXTI_EMR3_EM66_Msk (0x1UL << EXTI_EMR3_EM66_Pos) /*!< 0x00000004 */
8674 #define EXTI_EMR3_EM66 EXTI_EMR3_EM66_Msk /*!< Event Mask on line 66*/
8675 #define EXTI_EMR3_EM67_Pos (3U)
8676 #define EXTI_EMR3_EM67_Msk (0x1UL << EXTI_EMR3_EM67_Pos) /*!< 0x00000008 */
8677 #define EXTI_EMR3_EM67 EXTI_EMR3_EM67_Msk /*!< Event Mask on line 67*/
8678 #define EXTI_EMR3_EM68_Pos (4U)
8679 #define EXTI_EMR3_EM68_Msk (0x1UL << EXTI_EMR3_EM68_Pos) /*!< 0x00000010 */
8680 #define EXTI_EMR3_EM68 EXTI_EMR3_EM68_Msk /*!< Event Mask on line 68*/
8681 #define EXTI_EMR3_EM69_Pos (5U)
8682 #define EXTI_EMR3_EM69_Msk (0x1UL << EXTI_EMR3_EM69_Pos) /*!< 0x00000020 */
8683 #define EXTI_EMR3_EM69 EXTI_EMR3_EM69_Msk /*!< Event Mask on line 69*/
8684 #define EXTI_EMR3_EM70_Pos (6U)
8685 #define EXTI_EMR3_EM70_Msk (0x1UL << EXTI_EMR3_EM70_Pos) /*!< 0x00000040 */
8686 #define EXTI_EMR3_EM70 EXTI_EMR3_EM70_Msk /*!< Event Mask on line 70*/
8687 #define EXTI_EMR3_EM71_Pos (7U)
8688 #define EXTI_EMR3_EM71_Msk (0x1UL << EXTI_EMR3_EM71_Pos) /*!< 0x00000080 */
8689 #define EXTI_EMR3_EM71 EXTI_EMR3_EM71_Msk /*!< Event Mask on line 71*/
8690 #define EXTI_EMR3_EM72_Pos (8U)
8691 #define EXTI_EMR3_EM72_Msk (0x1UL << EXTI_EMR3_EM72_Pos) /*!< 0x00000100 */
8692 #define EXTI_EMR3_EM72 EXTI_EMR3_EM72_Msk /*!< Event Mask on line 72*/
8693 #define EXTI_EMR3_EM73_Pos (9U)
8694 #define EXTI_EMR3_EM73_Msk (0x1UL << EXTI_EMR3_EM73_Pos) /*!< 0x00000200 */
8695 #define EXTI_EMR3_EM73 EXTI_EMR3_EM73_Msk /*!< Event Mask on line 73*/
8696 #define EXTI_EMR3_EM74_Pos (10U)
8697 #define EXTI_EMR3_EM74_Msk (0x1UL << EXTI_EMR3_EM74_Pos) /*!< 0x00000400 */
8698 #define EXTI_EMR3_EM74 EXTI_EMR3_EM74_Msk /*!< Event Mask on line 74 */
8699 #define EXTI_EMR3_EM77_Pos (13U)
8700 #define EXTI_EMR3_EM77_Msk (0x1UL << EXTI_EMR3_EM77_Pos) /*!< 0x00002000 */
8701 #define EXTI_EMR3_EM77 EXTI_EMR3_EM77_Msk /*!< Event Mask on line 77 */
8702 #define EXTI_EMR3_EM80_Pos (16U)
8703 #define EXTI_EMR3_EM80_Msk (0x1UL << EXTI_EMR3_EM80_Pos) /*!< 0x00010000 */
8704 #define EXTI_EMR3_EM80 EXTI_EMR3_EM80_Msk /*!< Event Mask on line 80 */
8705 #define EXTI_EMR3_EM81_Pos (17U)
8706 #define EXTI_EMR3_EM81_Msk (0x1UL << EXTI_EMR3_EM81_Pos) /*!< 0x00020000 */
8707 #define EXTI_EMR3_EM81 EXTI_EMR3_EM81_Msk /*!< Event Mask on line 81 */
8708 #define EXTI_EMR3_EM82_Pos (18U)
8709 #define EXTI_EMR3_EM82_Msk (0x1UL << EXTI_EMR3_EM82_Pos) /*!< 0x00040000 */
8710 #define EXTI_EMR3_EM82 EXTI_EMR3_EM82_Msk /*!< Event Mask on line 82 */
8711 #define EXTI_EMR3_EM85_Pos (21U)
8712 #define EXTI_EMR3_EM85_Msk (0x1UL << EXTI_EMR3_EM85_Pos) /*!< 0x00200000 */
8713 #define EXTI_EMR3_EM85 EXTI_EMR3_EM85_Msk /*!< Event Mask on line 85 */
8714 #define EXTI_EMR3_EM87_Pos (23U)
8715 #define EXTI_EMR3_EM87_Msk (0x1UL << EXTI_EMR3_EM87_Pos) /*!< 0x00800000 */
8716 #define EXTI_EMR3_EM87 EXTI_EMR3_EM87_Msk /*!< Event Mask on line 87 */
8717
8718 #define EXTI_EMR3_EM88_Pos (24U)
8719 #define EXTI_EMR3_EM88_Msk (0x1UL << EXTI_EMR3_EM88_Pos) /*!< 0x01000000 */
8720 #define EXTI_EMR3_EM88 EXTI_EMR3_EM88_Msk /*!< Event Mask on line 88 */
8721
8722 /******************* Bit definition for EXTI_PR3 register ********************/
8723 #define EXTI_PR3_PR_Pos (18U)
8724 #define EXTI_PR3_PR_Msk (0x9UL << EXTI_PR3_PR_Pos) /*!< 0x00240000 */
8725 #define EXTI_PR3_PR EXTI_PR3_PR_Msk /*!< Pending bit */
8726 #define EXTI_PR3_PR82_Pos (18U)
8727 #define EXTI_PR3_PR82_Msk (0x1UL << EXTI_PR3_PR82_Pos) /*!< 0x00040000 */
8728 #define EXTI_PR3_PR82 EXTI_PR3_PR82_Msk /*!< Pending bit for line 82 */
8729 #define EXTI_PR3_PR85_Pos (21U)
8730 #define EXTI_PR3_PR85_Msk (0x1UL << EXTI_PR3_PR85_Pos) /*!< 0x00200000 */
8731 #define EXTI_PR3_PR85 EXTI_PR3_PR85_Msk /*!< Pending bit for line 85 */
8732 /******************************************************************************/
8733 /* */
8734 /* FLASH */
8735 /* */
8736 /******************************************************************************/
8737 /*
8738 * @brief FLASH Global Defines
8739 */
8740 #define FLASH_SECTOR_TOTAL 16U /* 16 sectors */
8741 #define FLASH_SECTOR_SIZE 0x00002000UL /* 8 KB */
8742 #define FLASH_SIZE 0x00020000UL /* 128 KB */
8743 #define FLASH_BANK_SIZE FLASH_SIZE /* 128 KB */
8744 #define FLASH_LATENCY_DEFAULT FLASH_ACR_LATENCY_3WS /* FLASH Three Latency cycles */
8745 #define FLASH_NB_32BITWORD_IN_FLASHWORD 4U /* 128 bits */
8746
8747 /******************* Bits definition for FLASH_ACR register **********************/
8748 #define FLASH_ACR_LATENCY_Pos (0U)
8749 #define FLASH_ACR_LATENCY_Msk (0xFUL << FLASH_ACR_LATENCY_Pos) /*!< 0x0000000F */
8750 #define FLASH_ACR_LATENCY FLASH_ACR_LATENCY_Msk /*!< Read Latency */
8751 #define FLASH_ACR_LATENCY_0WS (0x00000000UL)
8752 #define FLASH_ACR_LATENCY_1WS (0x00000001UL)
8753 #define FLASH_ACR_LATENCY_2WS (0x00000002UL)
8754 #define FLASH_ACR_LATENCY_3WS (0x00000003UL)
8755 #define FLASH_ACR_LATENCY_4WS (0x00000004UL)
8756 #define FLASH_ACR_LATENCY_5WS (0x00000005UL)
8757 #define FLASH_ACR_LATENCY_6WS (0x00000006UL)
8758 #define FLASH_ACR_LATENCY_7WS (0x00000007UL)
8759 #define FLASH_ACR_LATENCY_8WS (0x00000008UL)
8760 #define FLASH_ACR_LATENCY_9WS (0x00000009UL)
8761 #define FLASH_ACR_LATENCY_10WS (0x0000000AUL)
8762 #define FLASH_ACR_LATENCY_11WS (0x0000000BUL)
8763 #define FLASH_ACR_LATENCY_12WS (0x0000000CUL)
8764 #define FLASH_ACR_LATENCY_13WS (0x0000000DUL)
8765 #define FLASH_ACR_LATENCY_14WS (0x0000000EUL)
8766 #define FLASH_ACR_LATENCY_15WS (0x0000000FUL)
8767 #define FLASH_ACR_WRHIGHFREQ_Pos (4U)
8768 #define FLASH_ACR_WRHIGHFREQ_Msk (0x3UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000030 */
8769 #define FLASH_ACR_WRHIGHFREQ FLASH_ACR_WRHIGHFREQ_Msk /*!< Flash signal delay */
8770 #define FLASH_ACR_WRHIGHFREQ_0 (0x1UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000010 */
8771 #define FLASH_ACR_WRHIGHFREQ_1 (0x2UL << FLASH_ACR_WRHIGHFREQ_Pos) /*!< 0x00000020 */
8772
8773 /******************* Bits definition for FLASH_CR register ***********************/
8774 #define FLASH_CR_LOCK_Pos (0U)
8775 #define FLASH_CR_LOCK_Msk (0x1UL << FLASH_CR_LOCK_Pos) /*!< 0x00000001 */
8776 #define FLASH_CR_LOCK FLASH_CR_LOCK_Msk /*!< Configuration lock bit */
8777 #define FLASH_CR_PG_Pos (1U)
8778 #define FLASH_CR_PG_Msk (0x1UL << FLASH_CR_PG_Pos) /*!< 0x00000002 */
8779 #define FLASH_CR_PG FLASH_CR_PG_Msk /*!< Internal buffer control bit */
8780 #define FLASH_CR_SER_Pos (2U)
8781 #define FLASH_CR_SER_Msk (0x1UL << FLASH_CR_SER_Pos) /*!< 0x00000004 */
8782 #define FLASH_CR_SER FLASH_CR_SER_Msk /*!< Sector erase request */
8783 #define FLASH_CR_BER_Pos (3U)
8784 #define FLASH_CR_BER_Msk (0x1UL << FLASH_CR_BER_Pos) /*!< 0x00000008 */
8785 #define FLASH_CR_BER FLASH_CR_BER_Msk /*!< Bank erase request */
8786 #define FLASH_CR_FW_Pos (4U)
8787 #define FLASH_CR_FW_Msk (0x1UL << FLASH_CR_FW_Pos) /*!< 0x00000010 */
8788 #define FLASH_CR_FW FLASH_CR_FW_Msk /*!< Write forcing control bit */
8789 #define FLASH_CR_START_Pos (5U)
8790 #define FLASH_CR_START_Msk (0x1UL << FLASH_CR_START_Pos) /*!< 0x00000020 */
8791 #define FLASH_CR_START FLASH_CR_START_Msk /*!< Erase start control bit */
8792 #define FLASH_CR_SNB_Pos (6U)
8793 #define FLASH_CR_SNB_Msk (0x7FUL << FLASH_CR_SNB_Pos) /*!< 0x00001FC0 */
8794 #define FLASH_CR_SNB FLASH_CR_SNB_Msk /*!< Sector erase selection number */
8795 #define FLASH_CR_SNB_0 (0x01UL << FLASH_CR_SNB_Pos) /*!< 0x00000040 */
8796 #define FLASH_CR_SNB_1 (0x02UL << FLASH_CR_SNB_Pos) /*!< 0x00000080 */
8797 #define FLASH_CR_SNB_2 (0x04UL << FLASH_CR_SNB_Pos) /*!< 0x00000100 */
8798 #define FLASH_CR_SNB_3 (0x08UL << FLASH_CR_SNB_Pos) /*!< 0x00000200 */
8799 #define FLASH_CR_SNB_4 (0x10UL << FLASH_CR_SNB_Pos) /*!< 0x00000400 */
8800 #define FLASH_CR_SNB_5 (0x20UL << FLASH_CR_SNB_Pos) /*!< 0x00000800 */
8801 #define FLASH_CR_SNB_6 (0x40UL << FLASH_CR_SNB_Pos) /*!< 0x00001000 */
8802 #define FLASH_CR_CRC_EN_Pos (15U)
8803 #define FLASH_CR_CRC_EN_Msk (0x1UL << FLASH_CR_CRC_EN_Pos) /*!< 0x00008000 */
8804 #define FLASH_CR_CRC_EN FLASH_CR_CRC_EN_Msk /*!< CRC control bit */
8805 #define FLASH_CR_EOPIE_Pos (16U)
8806 #define FLASH_CR_EOPIE_Msk (0x1UL << FLASH_CR_EOPIE_Pos) /*!< 0x00010000 */
8807 #define FLASH_CR_EOPIE FLASH_CR_EOPIE_Msk /*!< End-of-program interrupt control bit */
8808 #define FLASH_CR_WRPERRIE_Pos (17U)
8809 #define FLASH_CR_WRPERRIE_Msk (0x1UL << FLASH_CR_WRPERRIE_Pos) /*!< 0x00020000 */
8810 #define FLASH_CR_WRPERRIE FLASH_CR_WRPERRIE_Msk /*!< Write protection error interrupt enable bit */
8811 #define FLASH_CR_PGSERRIE_Pos (18U)
8812 #define FLASH_CR_PGSERRIE_Msk (0x1UL << FLASH_CR_PGSERRIE_Pos) /*!< 0x00040000 */
8813 #define FLASH_CR_PGSERRIE FLASH_CR_PGSERRIE_Msk /*!< Programming sequence error interrupt enable bit */
8814 #define FLASH_CR_STRBERRIE_Pos (19U)
8815 #define FLASH_CR_STRBERRIE_Msk (0x1UL << FLASH_CR_STRBERRIE_Pos) /*!< 0x00080000 */
8816 #define FLASH_CR_STRBERRIE FLASH_CR_STRBERRIE_Msk /*!< Strobe error interrupt enable bit */
8817 #define FLASH_CR_INCERRIE_Pos (21U)
8818 #define FLASH_CR_INCERRIE_Msk (0x1UL << FLASH_CR_INCERRIE_Pos) /*!< 0x00200000 */
8819 #define FLASH_CR_INCERRIE FLASH_CR_INCERRIE_Msk /*!< Inconsistency error interrupt enable bit */
8820 #define FLASH_CR_RDPERRIE_Pos (23U)
8821 #define FLASH_CR_RDPERRIE_Msk (0x1UL << FLASH_CR_RDPERRIE_Pos) /*!< 0x00800000 */
8822 #define FLASH_CR_RDPERRIE FLASH_CR_RDPERRIE_Msk /*!< Read protection error interrupt enable bit */
8823 #define FLASH_CR_RDSERRIE_Pos (24U)
8824 #define FLASH_CR_RDSERRIE_Msk (0x1UL << FLASH_CR_RDSERRIE_Pos) /*!< 0x01000000 */
8825 #define FLASH_CR_RDSERRIE FLASH_CR_RDSERRIE_Msk /*!< Secure error interrupt enable bit */
8826 #define FLASH_CR_SNECCERRIE_Pos (25U)
8827 #define FLASH_CR_SNECCERRIE_Msk (0x1UL << FLASH_CR_SNECCERRIE_Pos) /*!< 0x02000000 */
8828 #define FLASH_CR_SNECCERRIE FLASH_CR_SNECCERRIE_Msk /*!< ECC single correction error interrupt enable bit */
8829 #define FLASH_CR_DBECCERRIE_Pos (26U)
8830 #define FLASH_CR_DBECCERRIE_Msk (0x1UL << FLASH_CR_DBECCERRIE_Pos) /*!< 0x04000000 */
8831 #define FLASH_CR_DBECCERRIE FLASH_CR_DBECCERRIE_Msk /*!< ECC double detection error interrupt enable bit */
8832 #define FLASH_CR_CRCENDIE_Pos (27U)
8833 #define FLASH_CR_CRCENDIE_Msk (0x1UL << FLASH_CR_CRCENDIE_Pos) /*!< 0x08000000 */
8834 #define FLASH_CR_CRCENDIE FLASH_CR_CRCENDIE_Msk /*!< CRC end of calculation interrupt enable bit */
8835 #define FLASH_CR_CRCRDERRIE_Pos (28U)
8836 #define FLASH_CR_CRCRDERRIE_Msk (0x1UL << FLASH_CR_CRCRDERRIE_Pos) /*!< 0x10000000 */
8837 #define FLASH_CR_CRCRDERRIE FLASH_CR_CRCRDERRIE_Msk /*!< CRC read error interrupt enable bit */
8838
8839 /******************* Bits definition for FLASH_SR register ***********************/
8840 #define FLASH_SR_BSY_Pos (0U)
8841 #define FLASH_SR_BSY_Msk (0x1UL << FLASH_SR_BSY_Pos) /*!< 0x00000001 */
8842 #define FLASH_SR_BSY FLASH_SR_BSY_Msk /*!< Busy flag */
8843 #define FLASH_SR_WBNE_Pos (1U)
8844 #define FLASH_SR_WBNE_Msk (0x1UL << FLASH_SR_WBNE_Pos) /*!< 0x00000002 */
8845 #define FLASH_SR_WBNE FLASH_SR_WBNE_Msk /*!< Write buffer not empty flag */
8846 #define FLASH_SR_QW_Pos (2U)
8847 #define FLASH_SR_QW_Msk (0x1UL << FLASH_SR_QW_Pos) /*!< 0x00000004 */
8848 #define FLASH_SR_QW FLASH_SR_QW_Msk /*!< Wait queue flag */
8849 #define FLASH_SR_CRC_BUSY_Pos (3U)
8850 #define FLASH_SR_CRC_BUSY_Msk (0x1UL << FLASH_SR_CRC_BUSY_Pos) /*!< 0x00000008 */
8851 #define FLASH_SR_CRC_BUSY FLASH_SR_CRC_BUSY_Msk /*!< CRC busy flag */
8852 #define FLASH_SR_EOP_Pos (16U)
8853 #define FLASH_SR_EOP_Msk (0x1UL << FLASH_SR_EOP_Pos) /*!< 0x00010000 */
8854 #define FLASH_SR_EOP FLASH_SR_EOP_Msk /*!< End-of-program flag */
8855 #define FLASH_SR_WRPERR_Pos (17U)
8856 #define FLASH_SR_WRPERR_Msk (0x1UL << FLASH_SR_WRPERR_Pos) /*!< 0x00020000 */
8857 #define FLASH_SR_WRPERR FLASH_SR_WRPERR_Msk /*!< Write protection error flag */
8858 #define FLASH_SR_PGSERR_Pos (18U)
8859 #define FLASH_SR_PGSERR_Msk (0x1UL << FLASH_SR_PGSERR_Pos) /*!< 0x00040000 */
8860 #define FLASH_SR_PGSERR FLASH_SR_PGSERR_Msk /*!< Programming sequence error flag */
8861 #define FLASH_SR_STRBERR_Pos (19U)
8862 #define FLASH_SR_STRBERR_Msk (0x1UL << FLASH_SR_STRBERR_Pos) /*!< 0x00080000 */
8863 #define FLASH_SR_STRBERR FLASH_SR_STRBERR_Msk /*!< Strobe error flag */
8864 #define FLASH_SR_INCERR_Pos (21U)
8865 #define FLASH_SR_INCERR_Msk (0x1UL << FLASH_SR_INCERR_Pos) /*!< 0x00200000 */
8866 #define FLASH_SR_INCERR FLASH_SR_INCERR_Msk /*!< Inconsistency error flag */
8867 #define FLASH_SR_RDPERR_Pos (23U)
8868 #define FLASH_SR_RDPERR_Msk (0x1UL << FLASH_SR_RDPERR_Pos) /*!< 0x00800000 */
8869 #define FLASH_SR_RDPERR FLASH_SR_RDPERR_Msk /*!< Read protection error flag */
8870 #define FLASH_SR_RDSERR_Pos (24U)
8871 #define FLASH_SR_RDSERR_Msk (0x1UL << FLASH_SR_RDSERR_Pos) /*!< 0x01000000 */
8872 #define FLASH_SR_RDSERR FLASH_SR_RDSERR_Msk /*!< Secure error flag */
8873 #define FLASH_SR_SNECCERR_Pos (25U)
8874 #define FLASH_SR_SNECCERR_Msk (0x1UL << FLASH_SR_SNECCERR_Pos) /*!< 0x02000000 */
8875 #define FLASH_SR_SNECCERR FLASH_SR_SNECCERR_Msk /*!< Single correction error flag */
8876 #define FLASH_SR_DBECCERR_Pos (26U)
8877 #define FLASH_SR_DBECCERR_Msk (0x1UL << FLASH_SR_DBECCERR_Pos) /*!< 0x04000000 */
8878 #define FLASH_SR_DBECCERR FLASH_SR_DBECCERR_Msk /*!< ECC double detection error flag */
8879 #define FLASH_SR_CRCEND_Pos (27U)
8880 #define FLASH_SR_CRCEND_Msk (0x1UL << FLASH_SR_CRCEND_Pos) /*!< 0x08000000 */
8881 #define FLASH_SR_CRCEND FLASH_SR_CRCEND_Msk /*!< CRC end of calculation flag */
8882 #define FLASH_SR_CRCRDERR_Pos (28U)
8883 #define FLASH_SR_CRCRDERR_Msk (0x1UL << FLASH_SR_CRCRDERR_Pos) /*!< 0x10000000 */
8884 #define FLASH_SR_CRCRDERR FLASH_SR_CRCRDERR_Msk /*!< CRC read error flag */
8885
8886 /******************* Bits definition for FLASH_CCR register *******************/
8887 #define FLASH_CCR_CLR_EOP_Pos (16U)
8888 #define FLASH_CCR_CLR_EOP_Msk (0x1UL << FLASH_CCR_CLR_EOP_Pos) /*!< 0x00010000 */
8889 #define FLASH_CCR_CLR_EOP FLASH_CCR_CLR_EOP_Msk /*!< EOP flag clear bit */
8890 #define FLASH_CCR_CLR_WRPERR_Pos (17U)
8891 #define FLASH_CCR_CLR_WRPERR_Msk (0x1UL << FLASH_CCR_CLR_WRPERR_Pos) /*!< 0x00020000 */
8892 #define FLASH_CCR_CLR_WRPERR FLASH_CCR_CLR_WRPERR_Msk /*!< WRPERR flag clear bit */
8893 #define FLASH_CCR_CLR_PGSERR_Pos (18U)
8894 #define FLASH_CCR_CLR_PGSERR_Msk (0x1UL << FLASH_CCR_CLR_PGSERR_Pos) /*!< 0x00040000 */
8895 #define FLASH_CCR_CLR_PGSERR FLASH_CCR_CLR_PGSERR_Msk /*!< PGSERR flag clear bit */
8896 #define FLASH_CCR_CLR_STRBERR_Pos (19U)
8897 #define FLASH_CCR_CLR_STRBERR_Msk (0x1UL << FLASH_CCR_CLR_STRBERR_Pos) /*!< 0x00080000 */
8898 #define FLASH_CCR_CLR_STRBERR FLASH_CCR_CLR_STRBERR_Msk /*!< STRBERR flag clear bit */
8899 #define FLASH_CCR_CLR_INCERR_Pos (21U)
8900 #define FLASH_CCR_CLR_INCERR_Msk (0x1UL << FLASH_CCR_CLR_INCERR_Pos) /*!< 0x00200000 */
8901 #define FLASH_CCR_CLR_INCERR FLASH_CCR_CLR_INCERR_Msk /*!< INCERR flag clear bit */
8902 #define FLASH_CCR_CLR_RDPERR_Pos (23U)
8903 #define FLASH_CCR_CLR_RDPERR_Msk (0x1UL << FLASH_CCR_CLR_RDPERR_Pos) /*!< 0x00800000 */
8904 #define FLASH_CCR_CLR_RDPERR FLASH_CCR_CLR_RDPERR_Msk /*!< RDPERR flag clear bit */
8905 #define FLASH_CCR_CLR_RDSERR_Pos (24U)
8906 #define FLASH_CCR_CLR_RDSERR_Msk (0x1UL << FLASH_CCR_CLR_RDSERR_Pos) /*!< 0x01000000 */
8907 #define FLASH_CCR_CLR_RDSERR FLASH_CCR_CLR_RDSERR_Msk /*!< RDSERR flag clear bit */
8908 #define FLASH_CCR_CLR_SNECCERR_Pos (25U)
8909 #define FLASH_CCR_CLR_SNECCERR_Msk (0x1UL << FLASH_CCR_CLR_SNECCERR_Pos) /*!< 0x02000000 */
8910 #define FLASH_CCR_CLR_SNECCERR FLASH_CCR_CLR_SNECCERR_Msk /*!< SNECCERR flag clear bit */
8911 #define FLASH_CCR_CLR_DBECCERR_Pos (26U)
8912 #define FLASH_CCR_CLR_DBECCERR_Msk (0x1UL << FLASH_CCR_CLR_DBECCERR_Pos) /*!< 0x04000000 */
8913 #define FLASH_CCR_CLR_DBECCERR FLASH_CCR_CLR_DBECCERR_Msk /*!< DBECCERR flag clear bit */
8914 #define FLASH_CCR_CLR_CRCEND_Pos (27U)
8915 #define FLASH_CCR_CLR_CRCEND_Msk (0x1UL << FLASH_CCR_CLR_CRCEND_Pos) /*!< 0x08000000 */
8916 #define FLASH_CCR_CLR_CRCEND FLASH_CCR_CLR_CRCEND_Msk /*!< CRCEND flag clear bit */
8917 #define FLASH_CCR_CLR_CRCRDERR_Pos (28U)
8918 #define FLASH_CCR_CLR_CRCRDERR_Msk (0x1UL << FLASH_CCR_CLR_CRCRDERR_Pos) /*!< 0x10000000 */
8919 #define FLASH_CCR_CLR_CRCRDERR FLASH_CCR_CLR_CRCRDERR_Msk /*!< CRCRDERR flag clear bit */
8920
8921 /******************* Bits definition for FLASH_OPTCR register *******************/
8922 #define FLASH_OPTCR_OPTLOCK_Pos (0U)
8923 #define FLASH_OPTCR_OPTLOCK_Msk (0x1UL << FLASH_OPTCR_OPTLOCK_Pos) /*!< 0x00000001 */
8924 #define FLASH_OPTCR_OPTLOCK FLASH_OPTCR_OPTLOCK_Msk /*!< FLASH_OPTCR lock option configuration bit */
8925 #define FLASH_OPTCR_OPTSTART_Pos (1U)
8926 #define FLASH_OPTCR_OPTSTART_Msk (0x1UL << FLASH_OPTCR_OPTSTART_Pos) /*!< 0x00000002 */
8927 #define FLASH_OPTCR_OPTSTART FLASH_OPTCR_OPTSTART_Msk /*!< Option byte start change option configuration bit */
8928 #define FLASH_OPTCR_MER_Pos (4U)
8929 #define FLASH_OPTCR_MER_Msk (0x1UL << FLASH_OPTCR_MER_Pos) /*!< 0x00000010 */
8930 #define FLASH_OPTCR_MER FLASH_OPTCR_MER_Msk /*!< Mass erase request */
8931 #define FLASH_OPTCR_PG_OTP_Pos (5U)
8932 #define FLASH_OPTCR_PG_OTP_Msk (0x1UL << FLASH_OPTCR_PG_OTP_Pos) /*!< 0x00000020 */
8933 #define FLASH_OPTCR_PG_OTP FLASH_OPTCR_PG_OTP_Msk /*!< OTP program control bit */
8934 #define FLASH_OPTCR_OPTCHANGEERRIE_Pos (30U)
8935 #define FLASH_OPTCR_OPTCHANGEERRIE_Msk (0x1UL << FLASH_OPTCR_OPTCHANGEERRIE_Pos) /*!< 0x40000000 */
8936 #define FLASH_OPTCR_OPTCHANGEERRIE FLASH_OPTCR_OPTCHANGEERRIE_Msk /*!< Option byte change error interrupt enable bit */
8937 #define FLASH_OPTCR_SWAP_BANK_Pos (31U)
8938 #define FLASH_OPTCR_SWAP_BANK_Msk (0x1UL << FLASH_OPTCR_SWAP_BANK_Pos) /*!< 0x80000000 */
8939 #define FLASH_OPTCR_SWAP_BANK FLASH_OPTCR_SWAP_BANK_Msk /*!< Bank swapping option configuration bit */
8940
8941 /******************* Bits definition for FLASH_OPTSR register ***************/
8942 #define FLASH_OPTSR_OPT_BUSY_Pos (0U)
8943 #define FLASH_OPTSR_OPT_BUSY_Msk (0x1UL << FLASH_OPTSR_OPT_BUSY_Pos) /*!< 0x00000001 */
8944 #define FLASH_OPTSR_OPT_BUSY FLASH_OPTSR_OPT_BUSY_Msk /*!< Option byte change ongoing flag */
8945 #define FLASH_OPTSR_BOR_LEV_Pos (2U)
8946 #define FLASH_OPTSR_BOR_LEV_Msk (0x3UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x0000000C */
8947 #define FLASH_OPTSR_BOR_LEV FLASH_OPTSR_BOR_LEV_Msk /*!< Brownout level option status bit */
8948 #define FLASH_OPTSR_BOR_LEV_0 (0x1UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000004 */
8949 #define FLASH_OPTSR_BOR_LEV_1 (0x2UL << FLASH_OPTSR_BOR_LEV_Pos) /*!< 0x00000008 */
8950 #define FLASH_OPTSR_IWDG1_SW_Pos (4U)
8951 #define FLASH_OPTSR_IWDG1_SW_Msk (0x1UL << FLASH_OPTSR_IWDG1_SW_Pos) /*!< 0x00000010 */
8952 #define FLASH_OPTSR_IWDG1_SW FLASH_OPTSR_IWDG1_SW_Msk /*!< IWDG1 control mode option status bit */
8953 #define FLASH_OPTSR_NRST_STOP_D1_Pos (6U)
8954 #define FLASH_OPTSR_NRST_STOP_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STOP_D1_Pos) /*!< 0x00000040 */
8955 #define FLASH_OPTSR_NRST_STOP_D1 FLASH_OPTSR_NRST_STOP_D1_Msk /*!< D1 domain DStop entry reset option status bit */
8956 #define FLASH_OPTSR_NRST_STBY_D1_Pos (7U)
8957 #define FLASH_OPTSR_NRST_STBY_D1_Msk (0x1UL << FLASH_OPTSR_NRST_STBY_D1_Pos) /*!< 0x00000080 */
8958 #define FLASH_OPTSR_NRST_STBY_D1 FLASH_OPTSR_NRST_STBY_D1_Msk /*!< D1 domain DStandby entry reset option status bit */
8959 #define FLASH_OPTSR_RDP_Pos (8U)
8960 #define FLASH_OPTSR_RDP_Msk (0xFFUL << FLASH_OPTSR_RDP_Pos) /*!< 0x0000FF00 */
8961 #define FLASH_OPTSR_RDP FLASH_OPTSR_RDP_Msk /*!< Readout protection level option status byte */
8962 #define FLASH_OPTSR_VDDMMC_HSLV_Pos (16U)
8963 #define FLASH_OPTSR_VDDMMC_HSLV_Msk (0x1UL << FLASH_OPTSR_VDDMMC_HSLV_Pos) /*!< 0x00010000 */
8964 #define FLASH_OPTSR_VDDMMC_HSLV FLASH_OPTSR_VDDMMC_HSLV_Msk /*!< VDDMMC I/O high-speed at low-voltage status bit (below 2.5V) */
8965 #define FLASH_OPTSR_FZ_IWDG_STOP_Pos (17U)
8966 #define FLASH_OPTSR_FZ_IWDG_STOP_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_STOP_Pos) /*!< 0x00020000 */
8967 #define FLASH_OPTSR_FZ_IWDG_STOP FLASH_OPTSR_FZ_IWDG_STOP_Msk /*!< IWDG Stop mode freeze option status bit */
8968 #define FLASH_OPTSR_FZ_IWDG_SDBY_Pos (18U)
8969 #define FLASH_OPTSR_FZ_IWDG_SDBY_Msk (0x1UL << FLASH_OPTSR_FZ_IWDG_SDBY_Pos) /*!< 0x00040000 */
8970 #define FLASH_OPTSR_FZ_IWDG_SDBY FLASH_OPTSR_FZ_IWDG_SDBY_Msk /*!< IWDG Standby mode freeze option status bit */
8971 #define FLASH_OPTSR_ST_RAM_SIZE_Pos (19U)
8972 #define FLASH_OPTSR_ST_RAM_SIZE_Msk (0x3UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00180000 */
8973 #define FLASH_OPTSR_ST_RAM_SIZE FLASH_OPTSR_ST_RAM_SIZE_Msk /*!< ST RAM size option status */
8974 #define FLASH_OPTSR_ST_RAM_SIZE_0 (0x1UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00080000 */
8975 #define FLASH_OPTSR_ST_RAM_SIZE_1 (0x2UL << FLASH_OPTSR_ST_RAM_SIZE_Pos) /*!< 0x00100000 */
8976 #define FLASH_OPTSR_SECURITY_Pos (21U)
8977 #define FLASH_OPTSR_SECURITY_Msk (0x1UL << FLASH_OPTSR_SECURITY_Pos) /*!< 0x00200000 */
8978 #define FLASH_OPTSR_SECURITY FLASH_OPTSR_SECURITY_Msk /*!< Security enable option status bit */
8979 #define FLASH_OPTSR_IO_HSLV_Pos (29U)
8980 #define FLASH_OPTSR_IO_HSLV_Msk (0x1UL << FLASH_OPTSR_IO_HSLV_Pos) /*!< 0x20000000 */
8981 #define FLASH_OPTSR_IO_HSLV FLASH_OPTSR_IO_HSLV_Msk /*!< I/O high-speed at low-voltage status bit */
8982 #define FLASH_OPTSR_OPTCHANGEERR_Pos (30U)
8983 #define FLASH_OPTSR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTSR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
8984 #define FLASH_OPTSR_OPTCHANGEERR FLASH_OPTSR_OPTCHANGEERR_Msk /*!< Option byte change error flag */
8985 #define FLASH_OPTSR_SWAP_BANK_OPT_Pos (31U)
8986 #define FLASH_OPTSR_SWAP_BANK_OPT_Msk (0x1UL << FLASH_OPTSR_SWAP_BANK_OPT_Pos) /*!< 0x80000000 */
8987 #define FLASH_OPTSR_SWAP_BANK_OPT FLASH_OPTSR_SWAP_BANK_OPT_Msk /*!< Bank swapping option status bit */
8988
8989 /******************* Bits definition for FLASH_OPTCCR register *******************/
8990 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos (30U)
8991 #define FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk (0x1UL << FLASH_OPTCCR_CLR_OPTCHANGEERR_Pos) /*!< 0x40000000 */
8992 #define FLASH_OPTCCR_CLR_OPTCHANGEERR FLASH_OPTCCR_CLR_OPTCHANGEERR_Msk /*!< OPTCHANGEERR reset bit */
8993
8994 /******************* Bits definition for FLASH_PRAR register *********************/
8995 #define FLASH_PRAR_PROT_AREA_START_Pos (0U)
8996 #define FLASH_PRAR_PROT_AREA_START_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_START_Pos) /*!< 0x00000FFF */
8997 #define FLASH_PRAR_PROT_AREA_START FLASH_PRAR_PROT_AREA_START_Msk /*!< PCROP area start status bits */
8998 #define FLASH_PRAR_PROT_AREA_END_Pos (16U)
8999 #define FLASH_PRAR_PROT_AREA_END_Msk (0xFFFUL << FLASH_PRAR_PROT_AREA_END_Pos) /*!< 0x0FFF0000 */
9000 #define FLASH_PRAR_PROT_AREA_END FLASH_PRAR_PROT_AREA_END_Msk /*!< PCROP area end status bits */
9001 #define FLASH_PRAR_DMEP_Pos (31U)
9002 #define FLASH_PRAR_DMEP_Msk (0x1UL << FLASH_PRAR_DMEP_Pos) /*!< 0x80000000 */
9003 #define FLASH_PRAR_DMEP FLASH_PRAR_DMEP_Msk /*!< PCROP protected erase enable option status bit */
9004
9005 /******************* Bits definition for FLASH_SCAR register *********************/
9006 #define FLASH_SCAR_SEC_AREA_START_Pos (0U)
9007 #define FLASH_SCAR_SEC_AREA_START_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_START_Pos) /*!< 0x00000FFF */
9008 #define FLASH_SCAR_SEC_AREA_START FLASH_SCAR_SEC_AREA_START_Msk /*!< Secure-only area start status bits */
9009 #define FLASH_SCAR_SEC_AREA_END_Pos (16U)
9010 #define FLASH_SCAR_SEC_AREA_END_Msk (0xFFFUL << FLASH_SCAR_SEC_AREA_END_Pos) /*!< 0x0FFF0000 */
9011 #define FLASH_SCAR_SEC_AREA_END FLASH_SCAR_SEC_AREA_END_Msk /*!< Secure-only area end status bits */
9012 #define FLASH_SCAR_DMES_Pos (31U)
9013 #define FLASH_SCAR_DMES_Msk (0x1UL << FLASH_SCAR_DMES_Pos) /*!< 0x80000000 */
9014 #define FLASH_SCAR_DMES FLASH_SCAR_DMES_Msk /*!< Secure access protected erase enable option status bit */
9015
9016 /******************* Bits definition for FLASH_WPSN register *********************/
9017 #define FLASH_WPSN_WRPSN_Pos (0U)
9018 #define FLASH_WPSN_WRPSN_Msk (0xFFFFFFFFUL << FLASH_WPSN_WRPSN_Pos) /*!< 0xFFFFFFFF */
9019 #define FLASH_WPSN_WRPSN FLASH_WPSN_WRPSN_Msk /*!< Sector write protection option status byte */
9020
9021 /******************* Bits definition for FLASH_BOOT_CUR register ****************/
9022 #define FLASH_BOOT_ADD0_Pos (0U)
9023 #define FLASH_BOOT_ADD0_Msk (0xFFFFUL << FLASH_BOOT_ADD0_Pos) /*!< 0x0000FFFF */
9024 #define FLASH_BOOT_ADD0 FLASH_BOOT_ADD0_Msk /*!< Arm Cortex-M7 boot address 0 */
9025 #define FLASH_BOOT_ADD1_Pos (16U)
9026 #define FLASH_BOOT_ADD1_Msk (0xFFFFUL << FLASH_BOOT_ADD1_Pos) /*!< 0xFFFF0000 */
9027 #define FLASH_BOOT_ADD1 FLASH_BOOT_ADD1_Msk /*!< Arm Cortex-M7 boot address 1 */
9028
9029
9030 /******************* Bits definition for FLASH_CRCCR register ********************/
9031 #define FLASH_CRCCR_CRC_SECT_Pos (0U)
9032 #define FLASH_CRCCR_CRC_SECT_Msk (0x3FUL << FLASH_CRCCR_CRC_SECT_Pos) /*!< 0x0000003F */
9033 #define FLASH_CRCCR_CRC_SECT FLASH_CRCCR_CRC_SECT_Msk /*!< CRC sector number */
9034 #define FLASH_CRCCR_CRC_BY_SECT_Pos (8U)
9035 #define FLASH_CRCCR_CRC_BY_SECT_Msk (0x1UL << FLASH_CRCCR_CRC_BY_SECT_Pos) /*!< 0x00000100 */
9036 #define FLASH_CRCCR_CRC_BY_SECT FLASH_CRCCR_CRC_BY_SECT_Msk /*!< CRC sector mode select bit */
9037 #define FLASH_CRCCR_ADD_SECT_Pos (9U)
9038 #define FLASH_CRCCR_ADD_SECT_Msk (0x1UL << FLASH_CRCCR_ADD_SECT_Pos) /*!< 0x00000200 */
9039 #define FLASH_CRCCR_ADD_SECT FLASH_CRCCR_ADD_SECT_Msk /*!< CRC sector select bit */
9040 #define FLASH_CRCCR_CLEAN_SECT_Pos (10U)
9041 #define FLASH_CRCCR_CLEAN_SECT_Msk (0x1UL << FLASH_CRCCR_CLEAN_SECT_Pos) /*!< 0x00000400 */
9042 #define FLASH_CRCCR_CLEAN_SECT FLASH_CRCCR_CLEAN_SECT_Msk /*!< CRC sector list clear bit */
9043 #define FLASH_CRCCR_START_CRC_Pos (16U)
9044 #define FLASH_CRCCR_START_CRC_Msk (0x1UL << FLASH_CRCCR_START_CRC_Pos) /*!< 0x00010000 */
9045 #define FLASH_CRCCR_START_CRC FLASH_CRCCR_START_CRC_Msk /*!< CRC start bit */
9046 #define FLASH_CRCCR_CLEAN_CRC_Pos (17U)
9047 #define FLASH_CRCCR_CLEAN_CRC_Msk (0x1UL << FLASH_CRCCR_CLEAN_CRC_Pos) /*!< 0x00020000 */
9048 #define FLASH_CRCCR_CLEAN_CRC FLASH_CRCCR_CLEAN_CRC_Msk /*!< CRC clear bit */
9049 #define FLASH_CRCCR_CRC_BURST_Pos (20U)
9050 #define FLASH_CRCCR_CRC_BURST_Msk (0x3UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00300000 */
9051 #define FLASH_CRCCR_CRC_BURST FLASH_CRCCR_CRC_BURST_Msk /*!< CRC burst size */
9052 #define FLASH_CRCCR_CRC_BURST_0 (0x1UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00100000 */
9053 #define FLASH_CRCCR_CRC_BURST_1 (0x2UL << FLASH_CRCCR_CRC_BURST_Pos) /*!< 0x00200000 */
9054 #define FLASH_CRCCR_ALL_BANK_Pos (22U)
9055 #define FLASH_CRCCR_ALL_BANK_Msk (0x1UL << FLASH_CRCCR_ALL_BANK_Pos) /*!< 0x00400000 */
9056 #define FLASH_CRCCR_ALL_BANK FLASH_CRCCR_ALL_BANK_Msk /*!< CRC select bit */
9057
9058 /******************* Bits definition for FLASH_CRCSADD register ****************/
9059 #define FLASH_CRCSADD_CRC_START_ADDR_Pos (0U)
9060 #define FLASH_CRCSADD_CRC_START_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCSADD_CRC_START_ADDR_Pos) /*!< 0xFFFFFFFF */
9061 #define FLASH_CRCSADD_CRC_START_ADDR FLASH_CRCSADD_CRC_START_ADDR_Msk /*!< CRC start address */
9062
9063 /******************* Bits definition for FLASH_CRCEADD register ****************/
9064 #define FLASH_CRCEADD_CRC_END_ADDR_Pos (0U)
9065 #define FLASH_CRCEADD_CRC_END_ADDR_Msk (0xFFFFFFFFUL << FLASH_CRCEADD_CRC_END_ADDR_Pos) /*!< 0xFFFFFFFF */
9066 #define FLASH_CRCEADD_CRC_END_ADDR FLASH_CRCEADD_CRC_END_ADDR_Msk /*!< CRC end address */
9067
9068 /******************* Bits definition for FLASH_CRCDATA register ***************/
9069 #define FLASH_CRCDATA_CRC_DATA_Pos (0U)
9070 #define FLASH_CRCDATA_CRC_DATA_Msk (0xFFFFFFFFUL << FLASH_CRCDATA_CRC_DATA_Pos) /*!< 0xFFFFFFFF */
9071 #define FLASH_CRCDATA_CRC_DATA FLASH_CRCDATA_CRC_DATA_Msk /*!< CRC result */
9072
9073 /******************* Bits definition for FLASH_ECC_FA register *******************/
9074 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Pos (0U)
9075 #define FLASH_ECC_FA_FAIL_ECC_ADDR_Msk (0xFFFFUL << FLASH_ECC_FA_FAIL_ECC_ADDR_Pos) /*!< 0x0000FFFF */
9076 #define FLASH_ECC_FA_FAIL_ECC_ADDR FLASH_ECC_FA_FAIL_ECC_ADDR_Msk /*!< ECC error address */
9077 #define FLASH_ECC_FA_OTP_FAIL_ECC_Pos (31U)
9078 #define FLASH_ECC_FA_OTP_FAIL_ECC_Msk (0x1UL << FLASH_ECC_FA_OTP_FAIL_ECC_Pos) /*!< 0x80000000 */
9079 #define FLASH_ECC_FA_OTP_FAIL_ECC FLASH_ECC_FA_OTP_FAIL_ECC_Msk /*!< OTP ECC error bit */
9080
9081 /******************* Bits definition for FLASH_OTPBL register *******************/
9082 #define FLASH_OTPBL_LOCKBL_Pos (0U)
9083 #define FLASH_OTPBL_LOCKBL_Msk (0xFFFFUL << FLASH_OTPBL_LOCKBL_Pos) /*!< 0x0000FFFF */
9084 #define FLASH_OTPBL_LOCKBL FLASH_OTPBL_LOCKBL_Msk /*!< OTP Block Lock */
9085
9086 /******************************************************************************/
9087 /* */
9088 /* Flexible Memory Controller */
9089 /* */
9090 /******************************************************************************/
9091 /****************** Bit definition for FMC_BCR1 register *******************/
9092 #define FMC_BCR1_CCLKEN_Pos (20U)
9093 #define FMC_BCR1_CCLKEN_Msk (0x1UL << FMC_BCR1_CCLKEN_Pos) /*!< 0x00100000 */
9094 #define FMC_BCR1_CCLKEN FMC_BCR1_CCLKEN_Msk /*!<Continous clock enable */
9095 #define FMC_BCR1_WFDIS_Pos (21U)
9096 #define FMC_BCR1_WFDIS_Msk (0x1UL << FMC_BCR1_WFDIS_Pos) /*!< 0x00200000 */
9097 #define FMC_BCR1_WFDIS FMC_BCR1_WFDIS_Msk /*!<Write FIFO Disable */
9098
9099 #define FMC_BCR1_BMAP_Pos (24U)
9100 #define FMC_BCR1_BMAP_Msk (0x3UL << FMC_BCR1_BMAP_Pos) /*!< 0x03000000 */
9101 #define FMC_BCR1_BMAP FMC_BCR1_BMAP_Msk /*!<BMAP[1:0] FMC bank mapping */
9102 #define FMC_BCR1_BMAP_0 (0x1UL << FMC_BCR1_BMAP_Pos) /*!< 0x01000000 */
9103 #define FMC_BCR1_BMAP_1 (0x2UL << FMC_BCR1_BMAP_Pos) /*!< 0x02000000 */
9104
9105 #define FMC_BCR1_FMCEN_Pos (31U)
9106 #define FMC_BCR1_FMCEN_Msk (0x1UL << FMC_BCR1_FMCEN_Pos) /*!< 0x80000000 */
9107 #define FMC_BCR1_FMCEN FMC_BCR1_FMCEN_Msk /*!<FMC controller Enable */
9108 /****************** Bit definition for FMC_BCRx registers (x=1..4) *********/
9109 #define FMC_BCRx_MBKEN_Pos (0U)
9110 #define FMC_BCRx_MBKEN_Msk (0x1UL << FMC_BCRx_MBKEN_Pos) /*!< 0x00000001 */
9111 #define FMC_BCRx_MBKEN FMC_BCRx_MBKEN_Msk /*!<Memory bank enable bit */
9112 #define FMC_BCRx_MUXEN_Pos (1U)
9113 #define FMC_BCRx_MUXEN_Msk (0x1UL << FMC_BCRx_MUXEN_Pos) /*!< 0x00000002 */
9114 #define FMC_BCRx_MUXEN FMC_BCRx_MUXEN_Msk /*!<Address/data multiplexing enable bit */
9115
9116 #define FMC_BCRx_MTYP_Pos (2U)
9117 #define FMC_BCRx_MTYP_Msk (0x3UL << FMC_BCRx_MTYP_Pos) /*!< 0x0000000C */
9118 #define FMC_BCRx_MTYP FMC_BCRx_MTYP_Msk /*!<MTYP[1:0] bits (Memory type) */
9119 #define FMC_BCRx_MTYP_0 (0x1UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000004 */
9120 #define FMC_BCRx_MTYP_1 (0x2UL << FMC_BCRx_MTYP_Pos) /*!< 0x00000008 */
9121
9122 #define FMC_BCRx_MWID_Pos (4U)
9123 #define FMC_BCRx_MWID_Msk (0x3UL << FMC_BCRx_MWID_Pos) /*!< 0x00000030 */
9124 #define FMC_BCRx_MWID FMC_BCRx_MWID_Msk /*!<MWID[1:0] bits (Memory data bus width) */
9125 #define FMC_BCRx_MWID_0 (0x1UL << FMC_BCRx_MWID_Pos) /*!< 0x00000010 */
9126 #define FMC_BCRx_MWID_1 (0x2UL << FMC_BCRx_MWID_Pos) /*!< 0x00000020 */
9127
9128 #define FMC_BCRx_FACCEN_Pos (6U)
9129 #define FMC_BCRx_FACCEN_Msk (0x1UL << FMC_BCRx_FACCEN_Pos) /*!< 0x00000040 */
9130 #define FMC_BCRx_FACCEN FMC_BCRx_FACCEN_Msk /*!<Flash access enable */
9131 #define FMC_BCRx_BURSTEN_Pos (8U)
9132 #define FMC_BCRx_BURSTEN_Msk (0x1UL << FMC_BCRx_BURSTEN_Pos) /*!< 0x00000100 */
9133 #define FMC_BCRx_BURSTEN FMC_BCRx_BURSTEN_Msk /*!<Burst enable bit */
9134 #define FMC_BCRx_WAITPOL_Pos (9U)
9135 #define FMC_BCRx_WAITPOL_Msk (0x1UL << FMC_BCRx_WAITPOL_Pos) /*!< 0x00000200 */
9136 #define FMC_BCRx_WAITPOL FMC_BCRx_WAITPOL_Msk /*!<Wait signal polarity bit */
9137 #define FMC_BCRx_WAITCFG_Pos (11U)
9138 #define FMC_BCRx_WAITCFG_Msk (0x1UL << FMC_BCRx_WAITCFG_Pos) /*!< 0x00000800 */
9139 #define FMC_BCRx_WAITCFG FMC_BCRx_WAITCFG_Msk /*!<Wait timing configuration */
9140 #define FMC_BCRx_WREN_Pos (12U)
9141 #define FMC_BCRx_WREN_Msk (0x1UL << FMC_BCRx_WREN_Pos) /*!< 0x00001000 */
9142 #define FMC_BCRx_WREN FMC_BCRx_WREN_Msk /*!<Write enable bit */
9143 #define FMC_BCRx_WAITEN_Pos (13U)
9144 #define FMC_BCRx_WAITEN_Msk (0x1UL << FMC_BCRx_WAITEN_Pos) /*!< 0x00002000 */
9145 #define FMC_BCRx_WAITEN FMC_BCRx_WAITEN_Msk /*!<Wait enable bit */
9146 #define FMC_BCRx_EXTMOD_Pos (14U)
9147 #define FMC_BCRx_EXTMOD_Msk (0x1UL << FMC_BCRx_EXTMOD_Pos) /*!< 0x00004000 */
9148 #define FMC_BCRx_EXTMOD FMC_BCRx_EXTMOD_Msk /*!<Extended mode enable */
9149 #define FMC_BCRx_ASYNCWAIT_Pos (15U)
9150 #define FMC_BCRx_ASYNCWAIT_Msk (0x1UL << FMC_BCRx_ASYNCWAIT_Pos) /*!< 0x00008000 */
9151 #define FMC_BCRx_ASYNCWAIT FMC_BCRx_ASYNCWAIT_Msk /*!<Asynchronous wait */
9152
9153 #define FMC_BCRx_CPSIZE_Pos (16U)
9154 #define FMC_BCRx_CPSIZE_Msk (0x7UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00070000 */
9155 #define FMC_BCRx_CPSIZE FMC_BCRx_CPSIZE_Msk /*!<PSIZE[2:0] bits CRAM Page Size */
9156 #define FMC_BCRx_CPSIZE_0 (0x1UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00010000 */
9157 #define FMC_BCRx_CPSIZE_1 (0x2UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00020000 */
9158 #define FMC_BCRx_CPSIZE_2 (0x4UL << FMC_BCRx_CPSIZE_Pos) /*!< 0x00040000 */
9159
9160 #define FMC_BCRx_CBURSTRW_Pos (19U)
9161 #define FMC_BCRx_CBURSTRW_Msk (0x1UL << FMC_BCRx_CBURSTRW_Pos) /*!< 0x00080000 */
9162 #define FMC_BCRx_CBURSTRW FMC_BCRx_CBURSTRW_Msk /*!<Write burst enable */
9163
9164 /****************** Bit definition for FMC_BTRx registers (x=1..4) *********/
9165 #define FMC_BTRx_ADDSET_Pos (0U)
9166 #define FMC_BTRx_ADDSET_Msk (0xFUL << FMC_BTRx_ADDSET_Pos) /*!< 0x0000000F */
9167 #define FMC_BTRx_ADDSET FMC_BTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
9168 #define FMC_BTRx_ADDSET_0 (0x1UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000001 */
9169 #define FMC_BTRx_ADDSET_1 (0x2UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000002 */
9170 #define FMC_BTRx_ADDSET_2 (0x4UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000004 */
9171 #define FMC_BTRx_ADDSET_3 (0x8UL << FMC_BTRx_ADDSET_Pos) /*!< 0x00000008 */
9172
9173 #define FMC_BTRx_ADDHLD_Pos (4U)
9174 #define FMC_BTRx_ADDHLD_Msk (0xFUL << FMC_BTRx_ADDHLD_Pos) /*!< 0x000000F0 */
9175 #define FMC_BTRx_ADDHLD FMC_BTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9176 #define FMC_BTRx_ADDHLD_0 (0x1UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000010 */
9177 #define FMC_BTRx_ADDHLD_1 (0x2UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000020 */
9178 #define FMC_BTRx_ADDHLD_2 (0x4UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000040 */
9179 #define FMC_BTRx_ADDHLD_3 (0x8UL << FMC_BTRx_ADDHLD_Pos) /*!< 0x00000080 */
9180
9181 #define FMC_BTRx_DATAST_Pos (8U)
9182 #define FMC_BTRx_DATAST_Msk (0xFFUL << FMC_BTRx_DATAST_Pos) /*!< 0x0000FF00 */
9183 #define FMC_BTRx_DATAST FMC_BTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
9184 #define FMC_BTRx_DATAST_0 (0x01UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000100 */
9185 #define FMC_BTRx_DATAST_1 (0x02UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000200 */
9186 #define FMC_BTRx_DATAST_2 (0x04UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000400 */
9187 #define FMC_BTRx_DATAST_3 (0x08UL << FMC_BTRx_DATAST_Pos) /*!< 0x00000800 */
9188 #define FMC_BTRx_DATAST_4 (0x10UL << FMC_BTRx_DATAST_Pos) /*!< 0x00001000 */
9189 #define FMC_BTRx_DATAST_5 (0x20UL << FMC_BTRx_DATAST_Pos) /*!< 0x00002000 */
9190 #define FMC_BTRx_DATAST_6 (0x40UL << FMC_BTRx_DATAST_Pos) /*!< 0x00004000 */
9191 #define FMC_BTRx_DATAST_7 (0x80UL << FMC_BTRx_DATAST_Pos) /*!< 0x00008000 */
9192
9193 #define FMC_BTRx_BUSTURN_Pos (16U)
9194 #define FMC_BTRx_BUSTURN_Msk (0xFUL << FMC_BTRx_BUSTURN_Pos) /*!< 0x000F0000 */
9195 #define FMC_BTRx_BUSTURN FMC_BTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9196 #define FMC_BTRx_BUSTURN_0 (0x1UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00010000 */
9197 #define FMC_BTRx_BUSTURN_1 (0x2UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00020000 */
9198 #define FMC_BTRx_BUSTURN_2 (0x4UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00040000 */
9199 #define FMC_BTRx_BUSTURN_3 (0x8UL << FMC_BTRx_BUSTURN_Pos) /*!< 0x00080000 */
9200
9201 #define FMC_BTRx_CLKDIV_Pos (20U)
9202 #define FMC_BTRx_CLKDIV_Msk (0xFUL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00F00000 */
9203 #define FMC_BTRx_CLKDIV FMC_BTRx_CLKDIV_Msk /*!<CLKDIV[3:0] bits (Clock divide ratio) */
9204 #define FMC_BTRx_CLKDIV_0 (0x1UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00100000 */
9205 #define FMC_BTRx_CLKDIV_1 (0x2UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00200000 */
9206 #define FMC_BTRx_CLKDIV_2 (0x4UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00400000 */
9207 #define FMC_BTRx_CLKDIV_3 (0x8UL << FMC_BTRx_CLKDIV_Pos) /*!< 0x00800000 */
9208
9209 #define FMC_BTRx_DATLAT_Pos (24U)
9210 #define FMC_BTRx_DATLAT_Msk (0xFUL << FMC_BTRx_DATLAT_Pos) /*!< 0x0F000000 */
9211 #define FMC_BTRx_DATLAT FMC_BTRx_DATLAT_Msk /*!<DATLA[3:0] bits (Data latency) */
9212 #define FMC_BTRx_DATLAT_0 (0x1UL << FMC_BTRx_DATLAT_Pos) /*!< 0x01000000 */
9213 #define FMC_BTRx_DATLAT_1 (0x2UL << FMC_BTRx_DATLAT_Pos) /*!< 0x02000000 */
9214 #define FMC_BTRx_DATLAT_2 (0x4UL << FMC_BTRx_DATLAT_Pos) /*!< 0x04000000 */
9215 #define FMC_BTRx_DATLAT_3 (0x8UL << FMC_BTRx_DATLAT_Pos) /*!< 0x08000000 */
9216
9217 #define FMC_BTRx_ACCMOD_Pos (28U)
9218 #define FMC_BTRx_ACCMOD_Msk (0x3UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x30000000 */
9219 #define FMC_BTRx_ACCMOD FMC_BTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9220 #define FMC_BTRx_ACCMOD_0 (0x1UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x10000000 */
9221 #define FMC_BTRx_ACCMOD_1 (0x2UL << FMC_BTRx_ACCMOD_Pos) /*!< 0x20000000 */
9222
9223 /****************** Bit definition for FMC_BWTRx registers (x=1..4) *********/
9224 #define FMC_BWTRx_ADDSET_Pos (0U)
9225 #define FMC_BWTRx_ADDSET_Msk (0xFUL << FMC_BWTRx_ADDSET_Pos) /*!< 0x0000000F */
9226 #define FMC_BWTRx_ADDSET FMC_BWTRx_ADDSET_Msk /*!<ADDSET[3:0] bits (Address setup phase duration) */
9227 #define FMC_BWTRx_ADDSET_0 (0x1UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000001 */
9228 #define FMC_BWTRx_ADDSET_1 (0x2UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000002 */
9229 #define FMC_BWTRx_ADDSET_2 (0x4UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000004 */
9230 #define FMC_BWTRx_ADDSET_3 (0x8UL << FMC_BWTRx_ADDSET_Pos) /*!< 0x00000008 */
9231
9232 #define FMC_BWTRx_ADDHLD_Pos (4U)
9233 #define FMC_BWTRx_ADDHLD_Msk (0xFUL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x000000F0 */
9234 #define FMC_BWTRx_ADDHLD FMC_BWTRx_ADDHLD_Msk /*!<ADDHLD[3:0] bits (Address-hold phase duration) */
9235 #define FMC_BWTRx_ADDHLD_0 (0x1UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000010 */
9236 #define FMC_BWTRx_ADDHLD_1 (0x2UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000020 */
9237 #define FMC_BWTRx_ADDHLD_2 (0x4UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000040 */
9238 #define FMC_BWTRx_ADDHLD_3 (0x8UL << FMC_BWTRx_ADDHLD_Pos) /*!< 0x00000080 */
9239
9240 #define FMC_BWTRx_DATAST_Pos (8U)
9241 #define FMC_BWTRx_DATAST_Msk (0xFFUL << FMC_BWTRx_DATAST_Pos) /*!< 0x0000FF00 */
9242 #define FMC_BWTRx_DATAST FMC_BWTRx_DATAST_Msk /*!<DATAST [3:0] bits (Data-phase duration) */
9243 #define FMC_BWTRx_DATAST_0 (0x01UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000100 */
9244 #define FMC_BWTRx_DATAST_1 (0x02UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000200 */
9245 #define FMC_BWTRx_DATAST_2 (0x04UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000400 */
9246 #define FMC_BWTRx_DATAST_3 (0x08UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00000800 */
9247 #define FMC_BWTRx_DATAST_4 (0x10UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00001000 */
9248 #define FMC_BWTRx_DATAST_5 (0x20UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00002000 */
9249 #define FMC_BWTRx_DATAST_6 (0x40UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00004000 */
9250 #define FMC_BWTRx_DATAST_7 (0x80UL << FMC_BWTRx_DATAST_Pos) /*!< 0x00008000 */
9251
9252 #define FMC_BWTRx_BUSTURN_Pos (16U)
9253 #define FMC_BWTRx_BUSTURN_Msk (0xFUL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x000F0000 */
9254 #define FMC_BWTRx_BUSTURN FMC_BWTRx_BUSTURN_Msk /*!<BUSTURN[3:0] bits (Bus turnaround phase duration) */
9255 #define FMC_BWTRx_BUSTURN_0 (0x1UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00010000 */
9256 #define FMC_BWTRx_BUSTURN_1 (0x2UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00020000 */
9257 #define FMC_BWTRx_BUSTURN_2 (0x4UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00040000 */
9258 #define FMC_BWTRx_BUSTURN_3 (0x8UL << FMC_BWTRx_BUSTURN_Pos) /*!< 0x00080000 */
9259
9260 #define FMC_BWTRx_ACCMOD_Pos (28U)
9261 #define FMC_BWTRx_ACCMOD_Msk (0x3UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x30000000 */
9262 #define FMC_BWTRx_ACCMOD FMC_BWTRx_ACCMOD_Msk /*!<ACCMOD[1:0] bits (Access mode) */
9263 #define FMC_BWTRx_ACCMOD_0 (0x1UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x10000000 */
9264 #define FMC_BWTRx_ACCMOD_1 (0x2UL << FMC_BWTRx_ACCMOD_Pos) /*!< 0x20000000 */
9265
9266 /****************** Bit definition for FMC_PCR register *******************/
9267 #define FMC_PCR_PWAITEN_Pos (1U)
9268 #define FMC_PCR_PWAITEN_Msk (0x1UL << FMC_PCR_PWAITEN_Pos) /*!< 0x00000002 */
9269 #define FMC_PCR_PWAITEN FMC_PCR_PWAITEN_Msk /*!<Wait feature enable bit */
9270 #define FMC_PCR_PBKEN_Pos (2U)
9271 #define FMC_PCR_PBKEN_Msk (0x1UL << FMC_PCR_PBKEN_Pos) /*!< 0x00000004 */
9272 #define FMC_PCR_PBKEN FMC_PCR_PBKEN_Msk /*!<NAND Flash memory bank enable bit */
9273
9274 #define FMC_PCR_PWID_Pos (4U)
9275 #define FMC_PCR_PWID_Msk (0x3UL << FMC_PCR_PWID_Pos) /*!< 0x00000030 */
9276 #define FMC_PCR_PWID FMC_PCR_PWID_Msk /*!<PWID[1:0] bits (NAND Flash databus width) */
9277 #define FMC_PCR_PWID_0 (0x1UL << FMC_PCR_PWID_Pos) /*!< 0x00000010 */
9278 #define FMC_PCR_PWID_1 (0x2UL << FMC_PCR_PWID_Pos) /*!< 0x00000020 */
9279
9280 #define FMC_PCR_ECCEN_Pos (6U)
9281 #define FMC_PCR_ECCEN_Msk (0x1UL << FMC_PCR_ECCEN_Pos) /*!< 0x00000040 */
9282 #define FMC_PCR_ECCEN FMC_PCR_ECCEN_Msk /*!<ECC computation logic enable bit */
9283
9284 #define FMC_PCR_TCLR_Pos (9U)
9285 #define FMC_PCR_TCLR_Msk (0xFUL << FMC_PCR_TCLR_Pos) /*!< 0x00001E00 */
9286 #define FMC_PCR_TCLR FMC_PCR_TCLR_Msk /*!<TCLR[3:0] bits (CLE to RE delay) */
9287 #define FMC_PCR_TCLR_0 (0x1UL << FMC_PCR_TCLR_Pos) /*!< 0x00000200 */
9288 #define FMC_PCR_TCLR_1 (0x2UL << FMC_PCR_TCLR_Pos) /*!< 0x00000400 */
9289 #define FMC_PCR_TCLR_2 (0x4UL << FMC_PCR_TCLR_Pos) /*!< 0x00000800 */
9290 #define FMC_PCR_TCLR_3 (0x8UL << FMC_PCR_TCLR_Pos) /*!< 0x00001000 */
9291
9292 #define FMC_PCR_TAR_Pos (13U)
9293 #define FMC_PCR_TAR_Msk (0xFUL << FMC_PCR_TAR_Pos) /*!< 0x0001E000 */
9294 #define FMC_PCR_TAR FMC_PCR_TAR_Msk /*!<TAR[3:0] bits (ALE to RE delay) */
9295 #define FMC_PCR_TAR_0 (0x1UL << FMC_PCR_TAR_Pos) /*!< 0x00002000 */
9296 #define FMC_PCR_TAR_1 (0x2UL << FMC_PCR_TAR_Pos) /*!< 0x00004000 */
9297 #define FMC_PCR_TAR_2 (0x4UL << FMC_PCR_TAR_Pos) /*!< 0x00008000 */
9298 #define FMC_PCR_TAR_3 (0x8UL << FMC_PCR_TAR_Pos) /*!< 0x00010000 */
9299
9300 #define FMC_PCR_ECCPS_Pos (17U)
9301 #define FMC_PCR_ECCPS_Msk (0x7UL << FMC_PCR_ECCPS_Pos) /*!< 0x000E0000 */
9302 #define FMC_PCR_ECCPS FMC_PCR_ECCPS_Msk /*!<ECCPS[1:0] bits (ECC page size) */
9303 #define FMC_PCR_ECCPS_0 (0x1UL << FMC_PCR_ECCPS_Pos) /*!< 0x00020000 */
9304 #define FMC_PCR_ECCPS_1 (0x2UL << FMC_PCR_ECCPS_Pos) /*!< 0x00040000 */
9305 #define FMC_PCR_ECCPS_2 (0x4UL << FMC_PCR_ECCPS_Pos) /*!< 0x00080000 */
9306
9307 /******************* Bit definition for FMC_SR register *******************/
9308 #define FMC_SR_IRS_Pos (0U)
9309 #define FMC_SR_IRS_Msk (0x1UL << FMC_SR_IRS_Pos) /*!< 0x00000001 */
9310 #define FMC_SR_IRS FMC_SR_IRS_Msk /*!<Interrupt Rising Edge status */
9311 #define FMC_SR_ILS_Pos (1U)
9312 #define FMC_SR_ILS_Msk (0x1UL << FMC_SR_ILS_Pos) /*!< 0x00000002 */
9313 #define FMC_SR_ILS FMC_SR_ILS_Msk /*!<Interrupt Level status */
9314 #define FMC_SR_IFS_Pos (2U)
9315 #define FMC_SR_IFS_Msk (0x1UL << FMC_SR_IFS_Pos) /*!< 0x00000004 */
9316 #define FMC_SR_IFS FMC_SR_IFS_Msk /*!<Interrupt Falling Edge status */
9317 #define FMC_SR_IREN_Pos (3U)
9318 #define FMC_SR_IREN_Msk (0x1UL << FMC_SR_IREN_Pos) /*!< 0x00000008 */
9319 #define FMC_SR_IREN FMC_SR_IREN_Msk /*!<Interrupt Rising Edge detection Enable bit */
9320 #define FMC_SR_ILEN_Pos (4U)
9321 #define FMC_SR_ILEN_Msk (0x1UL << FMC_SR_ILEN_Pos) /*!< 0x00000010 */
9322 #define FMC_SR_ILEN FMC_SR_ILEN_Msk /*!<Interrupt Level detection Enable bit */
9323 #define FMC_SR_IFEN_Pos (5U)
9324 #define FMC_SR_IFEN_Msk (0x1UL << FMC_SR_IFEN_Pos) /*!< 0x00000020 */
9325 #define FMC_SR_IFEN FMC_SR_IFEN_Msk /*!<Interrupt Falling Edge detection Enable bit */
9326 #define FMC_SR_FEMPT_Pos (6U)
9327 #define FMC_SR_FEMPT_Msk (0x1UL << FMC_SR_FEMPT_Pos) /*!< 0x00000040 */
9328 #define FMC_SR_FEMPT FMC_SR_FEMPT_Msk /*!<FIFO empty */
9329
9330 /****************** Bit definition for FMC_PMEM register ******************/
9331 #define FMC_PMEM_MEMSET_Pos (0U)
9332 #define FMC_PMEM_MEMSET_Msk (0xFFUL << FMC_PMEM_MEMSET_Pos) /*!< 0x000000FF */
9333 #define FMC_PMEM_MEMSET FMC_PMEM_MEMSET_Msk /*!<MEMSET[7:0] bits (Common memory setup time) */
9334 #define FMC_PMEM_MEMSET_0 (0x01UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000001 */
9335 #define FMC_PMEM_MEMSET_1 (0x02UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000002 */
9336 #define FMC_PMEM_MEMSET_2 (0x04UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000004 */
9337 #define FMC_PMEM_MEMSET_3 (0x08UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000008 */
9338 #define FMC_PMEM_MEMSET_4 (0x10UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000010 */
9339 #define FMC_PMEM_MEMSET_5 (0x20UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000020 */
9340 #define FMC_PMEM_MEMSET_6 (0x40UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000040 */
9341 #define FMC_PMEM_MEMSET_7 (0x80UL << FMC_PMEM_MEMSET_Pos) /*!< 0x00000080 */
9342
9343 #define FMC_PMEM_MEMWAIT_Pos (8U)
9344 #define FMC_PMEM_MEMWAIT_Msk (0xFFUL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x0000FF00 */
9345 #define FMC_PMEM_MEMWAIT FMC_PMEM_MEMWAIT_Msk /*!<MEMWAIT[7:0] bits (Common memory wait time) */
9346 #define FMC_PMEM_MEMWAIT_0 (0x01UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000100 */
9347 #define FMC_PMEM_MEMWAIT_1 (0x02UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000200 */
9348 #define FMC_PMEM_MEMWAIT_2 (0x04UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000400 */
9349 #define FMC_PMEM_MEMWAIT_3 (0x08UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00000800 */
9350 #define FMC_PMEM_MEMWAIT_4 (0x10UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00001000 */
9351 #define FMC_PMEM_MEMWAIT_5 (0x20UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00002000 */
9352 #define FMC_PMEM_MEMWAIT_6 (0x40UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00004000 */
9353 #define FMC_PMEM_MEMWAIT_7 (0x80UL << FMC_PMEM_MEMWAIT_Pos) /*!< 0x00008000 */
9354
9355 #define FMC_PMEM_MEMHOLD_Pos (16U)
9356 #define FMC_PMEM_MEMHOLD_Msk (0xFFUL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00FF0000 */
9357 #define FMC_PMEM_MEMHOLD FMC_PMEM_MEMHOLD_Msk /*!<MEMHOLD[7:0] bits (Common memory hold time) */
9358 #define FMC_PMEM_MEMHOLD_0 (0x01UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00010000 */
9359 #define FMC_PMEM_MEMHOLD_1 (0x02UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00020000 */
9360 #define FMC_PMEM_MEMHOLD_2 (0x04UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00040000 */
9361 #define FMC_PMEM_MEMHOLD_3 (0x08UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00080000 */
9362 #define FMC_PMEM_MEMHOLD_4 (0x10UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00100000 */
9363 #define FMC_PMEM_MEMHOLD_5 (0x20UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00200000 */
9364 #define FMC_PMEM_MEMHOLD_6 (0x40UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00400000 */
9365 #define FMC_PMEM_MEMHOLD_7 (0x80UL << FMC_PMEM_MEMHOLD_Pos) /*!< 0x00800000 */
9366
9367 #define FMC_PMEM_MEMHIZ_Pos (24U)
9368 #define FMC_PMEM_MEMHIZ_Msk (0xFFUL << FMC_PMEM_MEMHIZ_Pos) /*!< 0xFF000000 */
9369 #define FMC_PMEM_MEMHIZ FMC_PMEM_MEMHIZ_Msk /*!<MEMHIZ[7:0] bits (Common memory databus HiZ time) */
9370 #define FMC_PMEM_MEMHIZ_0 (0x01UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x01000000 */
9371 #define FMC_PMEM_MEMHIZ_1 (0x02UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x02000000 */
9372 #define FMC_PMEM_MEMHIZ_2 (0x04UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x04000000 */
9373 #define FMC_PMEM_MEMHIZ_3 (0x08UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x08000000 */
9374 #define FMC_PMEM_MEMHIZ_4 (0x10UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x10000000 */
9375 #define FMC_PMEM_MEMHIZ_5 (0x20UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x20000000 */
9376 #define FMC_PMEM_MEMHIZ_6 (0x40UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x40000000 */
9377 #define FMC_PMEM_MEMHIZ_7 (0x80UL << FMC_PMEM_MEMHIZ_Pos) /*!< 0x80000000 */
9378
9379 /****************** Bit definition for FMC_PATT register ******************/
9380 #define FMC_PATT_ATTSET_Pos (0U)
9381 #define FMC_PATT_ATTSET_Msk (0xFFUL << FMC_PATT_ATTSET_Pos) /*!< 0x000000FF */
9382 #define FMC_PATT_ATTSET FMC_PATT_ATTSET_Msk /*!<ATTSET[7:0] bits (Attribute memory setup time) */
9383 #define FMC_PATT_ATTSET_0 (0x01UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000001 */
9384 #define FMC_PATT_ATTSET_1 (0x02UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000002 */
9385 #define FMC_PATT_ATTSET_2 (0x04UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000004 */
9386 #define FMC_PATT_ATTSET_3 (0x08UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000008 */
9387 #define FMC_PATT_ATTSET_4 (0x10UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000010 */
9388 #define FMC_PATT_ATTSET_5 (0x20UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000020 */
9389 #define FMC_PATT_ATTSET_6 (0x40UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000040 */
9390 #define FMC_PATT_ATTSET_7 (0x80UL << FMC_PATT_ATTSET_Pos) /*!< 0x00000080 */
9391
9392 #define FMC_PATT_ATTWAIT_Pos (8U)
9393 #define FMC_PATT_ATTWAIT_Msk (0xFFUL << FMC_PATT_ATTWAIT_Pos) /*!< 0x0000FF00 */
9394 #define FMC_PATT_ATTWAIT FMC_PATT_ATTWAIT_Msk /*!<ATTWAIT[7:0] bits (Attribute memory wait time) */
9395 #define FMC_PATT_ATTWAIT_0 (0x01UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000100 */
9396 #define FMC_PATT_ATTWAIT_1 (0x02UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000200 */
9397 #define FMC_PATT_ATTWAIT_2 (0x04UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000400 */
9398 #define FMC_PATT_ATTWAIT_3 (0x08UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00000800 */
9399 #define FMC_PATT_ATTWAIT_4 (0x10UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00001000 */
9400 #define FMC_PATT_ATTWAIT_5 (0x20UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00002000 */
9401 #define FMC_PATT_ATTWAIT_6 (0x40UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00004000 */
9402 #define FMC_PATT_ATTWAIT_7 (0x80UL << FMC_PATT_ATTWAIT_Pos) /*!< 0x00008000 */
9403
9404 #define FMC_PATT_ATTHOLD_Pos (16U)
9405 #define FMC_PATT_ATTHOLD_Msk (0xFFUL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00FF0000 */
9406 #define FMC_PATT_ATTHOLD FMC_PATT_ATTHOLD_Msk /*!<ATTHOLD[7:0] bits (Attribute memory hold time) */
9407 #define FMC_PATT_ATTHOLD_0 (0x01UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00010000 */
9408 #define FMC_PATT_ATTHOLD_1 (0x02UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00020000 */
9409 #define FMC_PATT_ATTHOLD_2 (0x04UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00040000 */
9410 #define FMC_PATT_ATTHOLD_3 (0x08UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00080000 */
9411 #define FMC_PATT_ATTHOLD_4 (0x10UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00100000 */
9412 #define FMC_PATT_ATTHOLD_5 (0x20UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00200000 */
9413 #define FMC_PATT_ATTHOLD_6 (0x40UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00400000 */
9414 #define FMC_PATT_ATTHOLD_7 (0x80UL << FMC_PATT_ATTHOLD_Pos) /*!< 0x00800000 */
9415
9416 #define FMC_PATT_ATTHIZ_Pos (24U)
9417 #define FMC_PATT_ATTHIZ_Msk (0xFFUL << FMC_PATT_ATTHIZ_Pos) /*!< 0xFF000000 */
9418 #define FMC_PATT_ATTHIZ FMC_PATT_ATTHIZ_Msk /*!<ATTHIZ[7:0] bits (Attribute memory databus HiZ time) */
9419 #define FMC_PATT_ATTHIZ_0 (0x01UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x01000000 */
9420 #define FMC_PATT_ATTHIZ_1 (0x02UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x02000000 */
9421 #define FMC_PATT_ATTHIZ_2 (0x04UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x04000000 */
9422 #define FMC_PATT_ATTHIZ_3 (0x08UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x08000000 */
9423 #define FMC_PATT_ATTHIZ_4 (0x10UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x10000000 */
9424 #define FMC_PATT_ATTHIZ_5 (0x20UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x20000000 */
9425 #define FMC_PATT_ATTHIZ_6 (0x40UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x40000000 */
9426 #define FMC_PATT_ATTHIZ_7 (0x80UL << FMC_PATT_ATTHIZ_Pos) /*!< 0x80000000 */
9427
9428 /****************** Bit definition for FMC_ECCR3 register ******************/
9429 #define FMC_ECCR3_ECC3_Pos (0U)
9430 #define FMC_ECCR3_ECC3_Msk (0xFFFFFFFFUL << FMC_ECCR3_ECC3_Pos) /*!< 0xFFFFFFFF */
9431 #define FMC_ECCR3_ECC3 FMC_ECCR3_ECC3_Msk /*!<ECC result */
9432
9433 /****************** Bit definition for FMC_SDCRx registers (x=1..4) *********/
9434 #define FMC_SDCRx_NC_Pos (0U)
9435 #define FMC_SDCRx_NC_Msk (0x3UL << FMC_SDCRx_NC_Pos) /*!< 0x00000003 */
9436 #define FMC_SDCRx_NC FMC_SDCRx_NC_Msk /*!<NC[1:0] bits (Number of column bits) */
9437 #define FMC_SDCRx_NC_0 (0x1UL << FMC_SDCRx_NC_Pos) /*!< 0x00000001 */
9438 #define FMC_SDCRx_NC_1 (0x2UL << FMC_SDCRx_NC_Pos) /*!< 0x00000002 */
9439
9440 #define FMC_SDCRx_NR_Pos (2U)
9441 #define FMC_SDCRx_NR_Msk (0x3UL << FMC_SDCRx_NR_Pos) /*!< 0x0000000C */
9442 #define FMC_SDCRx_NR FMC_SDCRx_NR_Msk /*!<NR[1:0] bits (Number of row bits) */
9443 #define FMC_SDCRx_NR_0 (0x1UL << FMC_SDCRx_NR_Pos) /*!< 0x00000004 */
9444 #define FMC_SDCRx_NR_1 (0x2UL << FMC_SDCRx_NR_Pos) /*!< 0x00000008 */
9445
9446 #define FMC_SDCRx_MWID_Pos (4U)
9447 #define FMC_SDCRx_MWID_Msk (0x3UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000030 */
9448 #define FMC_SDCRx_MWID FMC_SDCRx_MWID_Msk /*!<NR[1:0] bits (Number of row bits) */
9449 #define FMC_SDCRx_MWID_0 (0x1UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000010 */
9450 #define FMC_SDCRx_MWID_1 (0x2UL << FMC_SDCRx_MWID_Pos) /*!< 0x00000020 */
9451
9452 #define FMC_SDCRx_NB_Pos (6U)
9453 #define FMC_SDCRx_NB_Msk (0x1UL << FMC_SDCRx_NB_Pos) /*!< 0x00000040 */
9454 #define FMC_SDCRx_NB FMC_SDCRx_NB_Msk /*!<Number of internal bank */
9455
9456 #define FMC_SDCRx_CAS_Pos (7U)
9457 #define FMC_SDCRx_CAS_Msk (0x3UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000180 */
9458 #define FMC_SDCRx_CAS FMC_SDCRx_CAS_Msk /*!<CAS[1:0] bits (CAS latency) */
9459 #define FMC_SDCRx_CAS_0 (0x1UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000080 */
9460 #define FMC_SDCRx_CAS_1 (0x2UL << FMC_SDCRx_CAS_Pos) /*!< 0x00000100 */
9461
9462 #define FMC_SDCRx_WP_Pos (9U)
9463 #define FMC_SDCRx_WP_Msk (0x1UL << FMC_SDCRx_WP_Pos) /*!< 0x00000200 */
9464 #define FMC_SDCRx_WP FMC_SDCRx_WP_Msk /*!<Write protection */
9465
9466 #define FMC_SDCRx_SDCLK_Pos (10U)
9467 #define FMC_SDCRx_SDCLK_Msk (0x3UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000C00 */
9468 #define FMC_SDCRx_SDCLK FMC_SDCRx_SDCLK_Msk /*!<SDRAM clock configuration */
9469 #define FMC_SDCRx_SDCLK_0 (0x1UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000400 */
9470 #define FMC_SDCRx_SDCLK_1 (0x2UL << FMC_SDCRx_SDCLK_Pos) /*!< 0x00000800 */
9471
9472 #define FMC_SDCRx_RBURST_Pos (12U)
9473 #define FMC_SDCRx_RBURST_Msk (0x1UL << FMC_SDCRx_RBURST_Pos) /*!< 0x00001000 */
9474 #define FMC_SDCRx_RBURST FMC_SDCRx_RBURST_Msk /*!<Read burst */
9475
9476 #define FMC_SDCRx_RPIPE_Pos (13U)
9477 #define FMC_SDCRx_RPIPE_Msk (0x3UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00006000 */
9478 #define FMC_SDCRx_RPIPE FMC_SDCRx_RPIPE_Msk /*!<Write protection */
9479 #define FMC_SDCRx_RPIPE_0 (0x1UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00002000 */
9480 #define FMC_SDCRx_RPIPE_1 (0x2UL << FMC_SDCRx_RPIPE_Pos) /*!< 0x00004000 */
9481
9482 /****************** Bit definition for FMC_SDTRx(1,2) register ******************/
9483 #define FMC_SDTRx_TMRD_Pos (0U)
9484 #define FMC_SDTRx_TMRD_Msk (0xFUL << FMC_SDTRx_TMRD_Pos) /*!< 0x0000000F */
9485 #define FMC_SDTRx_TMRD FMC_SDTRx_TMRD_Msk /*!<TMRD[3:0] bits (Load mode register to active) */
9486 #define FMC_SDTRx_TMRD_0 (0x1UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000001 */
9487 #define FMC_SDTRx_TMRD_1 (0x2UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000002 */
9488 #define FMC_SDTRx_TMRD_2 (0x4UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000004 */
9489 #define FMC_SDTRx_TMRD_3 (0x8UL << FMC_SDTRx_TMRD_Pos) /*!< 0x00000008 */
9490
9491 #define FMC_SDTRx_TXSR_Pos (4U)
9492 #define FMC_SDTRx_TXSR_Msk (0xFUL << FMC_SDTRx_TXSR_Pos) /*!< 0x000000F0 */
9493 #define FMC_SDTRx_TXSR FMC_SDTRx_TXSR_Msk /*!<TXSR[3:0] bits (Exit self refresh) */
9494 #define FMC_SDTRx_TXSR_0 (0x1UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000010 */
9495 #define FMC_SDTRx_TXSR_1 (0x2UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000020 */
9496 #define FMC_SDTRx_TXSR_2 (0x4UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000040 */
9497 #define FMC_SDTRx_TXSR_3 (0x8UL << FMC_SDTRx_TXSR_Pos) /*!< 0x00000080 */
9498
9499 #define FMC_SDTRx_TRAS_Pos (8U)
9500 #define FMC_SDTRx_TRAS_Msk (0xFUL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000F00 */
9501 #define FMC_SDTRx_TRAS FMC_SDTRx_TRAS_Msk /*!<TRAS[3:0] bits (Self refresh time) */
9502 #define FMC_SDTRx_TRAS_0 (0x1UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000100 */
9503 #define FMC_SDTRx_TRAS_1 (0x2UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000200 */
9504 #define FMC_SDTRx_TRAS_2 (0x4UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000400 */
9505 #define FMC_SDTRx_TRAS_3 (0x8UL << FMC_SDTRx_TRAS_Pos) /*!< 0x00000800 */
9506
9507 #define FMC_SDTRx_TRC_Pos (12U)
9508 #define FMC_SDTRx_TRC_Msk (0xFUL << FMC_SDTRx_TRC_Pos) /*!< 0x0000F000 */
9509 #define FMC_SDTRx_TRC FMC_SDTRx_TRC_Msk /*!<TRC[2:0] bits (Row cycle delay) */
9510 #define FMC_SDTRx_TRC_0 (0x1UL << FMC_SDTRx_TRC_Pos) /*!< 0x00001000 */
9511 #define FMC_SDTRx_TRC_1 (0x2UL << FMC_SDTRx_TRC_Pos) /*!< 0x00002000 */
9512 #define FMC_SDTRx_TRC_2 (0x4UL << FMC_SDTRx_TRC_Pos) /*!< 0x00004000 */
9513
9514 #define FMC_SDTRx_TWR_Pos (16U)
9515 #define FMC_SDTRx_TWR_Msk (0xFUL << FMC_SDTRx_TWR_Pos) /*!< 0x000F0000 */
9516 #define FMC_SDTRx_TWR FMC_SDTRx_TWR_Msk /*!<TRC[2:0] bits (Write recovery delay) */
9517 #define FMC_SDTRx_TWR_0 (0x1UL << FMC_SDTRx_TWR_Pos) /*!< 0x00010000 */
9518 #define FMC_SDTRx_TWR_1 (0x2UL << FMC_SDTRx_TWR_Pos) /*!< 0x00020000 */
9519 #define FMC_SDTRx_TWR_2 (0x4UL << FMC_SDTRx_TWR_Pos) /*!< 0x00040000 */
9520
9521 #define FMC_SDTRx_TRP_Pos (20U)
9522 #define FMC_SDTRx_TRP_Msk (0xFUL << FMC_SDTRx_TRP_Pos) /*!< 0x00F00000 */
9523 #define FMC_SDTRx_TRP FMC_SDTRx_TRP_Msk /*!<TRP[2:0] bits (Row precharge delay) */
9524 #define FMC_SDTRx_TRP_0 (0x1UL << FMC_SDTRx_TRP_Pos) /*!< 0x00100000 */
9525 #define FMC_SDTRx_TRP_1 (0x2UL << FMC_SDTRx_TRP_Pos) /*!< 0x00200000 */
9526 #define FMC_SDTRx_TRP_2 (0x4UL << FMC_SDTRx_TRP_Pos) /*!< 0x00400000 */
9527
9528 #define FMC_SDTRx_TRCD_Pos (24U)
9529 #define FMC_SDTRx_TRCD_Msk (0xFUL << FMC_SDTRx_TRCD_Pos) /*!< 0x0F000000 */
9530 #define FMC_SDTRx_TRCD FMC_SDTRx_TRCD_Msk /*!<TRP[2:0] bits (Row to column delay) */
9531 #define FMC_SDTRx_TRCD_0 (0x1UL << FMC_SDTRx_TRCD_Pos) /*!< 0x01000000 */
9532 #define FMC_SDTRx_TRCD_1 (0x2UL << FMC_SDTRx_TRCD_Pos) /*!< 0x02000000 */
9533 #define FMC_SDTRx_TRCD_2 (0x4UL << FMC_SDTRx_TRCD_Pos) /*!< 0x04000000 */
9534
9535 /****************** Bit definition for FMC_SDCMR register ******************/
9536 #define FMC_SDCMR_MODE_Pos (0U)
9537 #define FMC_SDCMR_MODE_Msk (0x7UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000007 */
9538 #define FMC_SDCMR_MODE FMC_SDCMR_MODE_Msk /*!<MODE[2:0] bits (Command mode) */
9539 #define FMC_SDCMR_MODE_0 (0x1UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000001 */
9540 #define FMC_SDCMR_MODE_1 (0x2UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000002 */
9541 #define FMC_SDCMR_MODE_2 (0x3UL << FMC_SDCMR_MODE_Pos) /*!< 0x00000003 */
9542
9543 #define FMC_SDCMR_CTB2_Pos (3U)
9544 #define FMC_SDCMR_CTB2_Msk (0x1UL << FMC_SDCMR_CTB2_Pos) /*!< 0x00000008 */
9545 #define FMC_SDCMR_CTB2 FMC_SDCMR_CTB2_Msk /*!<Command target 2 */
9546
9547 #define FMC_SDCMR_CTB1_Pos (4U)
9548 #define FMC_SDCMR_CTB1_Msk (0x1UL << FMC_SDCMR_CTB1_Pos) /*!< 0x00000010 */
9549 #define FMC_SDCMR_CTB1 FMC_SDCMR_CTB1_Msk /*!<Command target 1 */
9550
9551 #define FMC_SDCMR_NRFS_Pos (5U)
9552 #define FMC_SDCMR_NRFS_Msk (0xFUL << FMC_SDCMR_NRFS_Pos) /*!< 0x000001E0 */
9553 #define FMC_SDCMR_NRFS FMC_SDCMR_NRFS_Msk /*!<NRFS[3:0] bits (Number of auto-refresh) */
9554 #define FMC_SDCMR_NRFS_0 (0x1UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000020 */
9555 #define FMC_SDCMR_NRFS_1 (0x2UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000040 */
9556 #define FMC_SDCMR_NRFS_2 (0x4UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000080 */
9557 #define FMC_SDCMR_NRFS_3 (0x8UL << FMC_SDCMR_NRFS_Pos) /*!< 0x00000100 */
9558
9559 #define FMC_SDCMR_MRD_Pos (9U)
9560 #define FMC_SDCMR_MRD_Msk (0x1FFFUL << FMC_SDCMR_MRD_Pos) /*!< 0x003FFE00 */
9561 #define FMC_SDCMR_MRD FMC_SDCMR_MRD_Msk /*!<MRD[12:0] bits (Mode register definition) */
9562
9563 /****************** Bit definition for FMC_SDRTR register ******************/
9564 #define FMC_SDRTR_CRE_Pos (0U)
9565 #define FMC_SDRTR_CRE_Msk (0x1UL << FMC_SDRTR_CRE_Pos) /*!< 0x00000001 */
9566 #define FMC_SDRTR_CRE FMC_SDRTR_CRE_Msk /*!<Clear refresh error flag */
9567
9568 #define FMC_SDRTR_COUNT_Pos (1U)
9569 #define FMC_SDRTR_COUNT_Msk (0x1FFFUL << FMC_SDRTR_COUNT_Pos) /*!< 0x00003FFE */
9570 #define FMC_SDRTR_COUNT FMC_SDRTR_COUNT_Msk /*!<COUNT[12:0] bits (Refresh timer count) */
9571
9572 #define FMC_SDRTR_REIE_Pos (14U)
9573 #define FMC_SDRTR_REIE_Msk (0x1UL << FMC_SDRTR_REIE_Pos) /*!< 0x00004000 */
9574 #define FMC_SDRTR_REIE FMC_SDRTR_REIE_Msk /*!<RES interupt enable */
9575
9576 /****************** Bit definition for FMC_SDSR register ******************/
9577 #define FMC_SDSR_RE_Pos (0U)
9578 #define FMC_SDSR_RE_Msk (0x1UL << FMC_SDSR_RE_Pos) /*!< 0x00000001 */
9579 #define FMC_SDSR_RE FMC_SDSR_RE_Msk /*!<Refresh error flag */
9580
9581 #define FMC_SDSR_MODES1_Pos (1U)
9582 #define FMC_SDSR_MODES1_Msk (0x3UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000006 */
9583 #define FMC_SDSR_MODES1 FMC_SDSR_MODES1_Msk /*!<MODES1[1:0]bits (Status mode for bank 1) */
9584 #define FMC_SDSR_MODES1_0 (0x1UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000002 */
9585 #define FMC_SDSR_MODES1_1 (0x2UL << FMC_SDSR_MODES1_Pos) /*!< 0x00000004 */
9586
9587 #define FMC_SDSR_MODES2_Pos (3U)
9588 #define FMC_SDSR_MODES2_Msk (0x3UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000018 */
9589 #define FMC_SDSR_MODES2 FMC_SDSR_MODES2_Msk /*!<MODES2[1:0]bits (Status mode for bank 2) */
9590 #define FMC_SDSR_MODES2_0 (0x1UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000008 */
9591 #define FMC_SDSR_MODES2_1 (0x2UL << FMC_SDSR_MODES2_Pos) /*!< 0x00000010 */
9592
9593 /******************************************************************************/
9594 /* */
9595 /* Graphic MMU (GFXMMU) */
9596 /* */
9597 /******************************************************************************/
9598 /****************** Bits definition for GFXMMU_CR register ********************/
9599 #define GFXMMU_CR_B0OIE_Pos (0U)
9600 #define GFXMMU_CR_B0OIE_Msk (0x1UL << GFXMMU_CR_B0OIE_Pos) /*!< 0x00000001 */
9601 #define GFXMMU_CR_B0OIE GFXMMU_CR_B0OIE_Msk /*!< Buffer 0 overflow interrupt enable */
9602 #define GFXMMU_CR_B1OIE_Pos (1U)
9603 #define GFXMMU_CR_B1OIE_Msk (0x1UL << GFXMMU_CR_B1OIE_Pos) /*!< 0x00000002 */
9604 #define GFXMMU_CR_B1OIE GFXMMU_CR_B1OIE_Msk /*!< Buffer 1 overflow interrupt enable */
9605 #define GFXMMU_CR_B2OIE_Pos (2U)
9606 #define GFXMMU_CR_B2OIE_Msk (0x1UL << GFXMMU_CR_B2OIE_Pos) /*!< 0x00000004 */
9607 #define GFXMMU_CR_B2OIE GFXMMU_CR_B2OIE_Msk /*!< Buffer 2 overflow interrupt enable */
9608 #define GFXMMU_CR_B3OIE_Pos (3U)
9609 #define GFXMMU_CR_B3OIE_Msk (0x1UL << GFXMMU_CR_B3OIE_Pos) /*!< 0x00000008 */
9610 #define GFXMMU_CR_B3OIE GFXMMU_CR_B3OIE_Msk /*!< Buffer 3 overflow interrupt enable */
9611 #define GFXMMU_CR_AMEIE_Pos (4U)
9612 #define GFXMMU_CR_AMEIE_Msk (0x1UL << GFXMMU_CR_AMEIE_Pos) /*!< 0x00000010 */
9613 #define GFXMMU_CR_AMEIE GFXMMU_CR_AMEIE_Msk /*!< AHB master error interrupt enable */
9614 #define GFXMMU_CR_192BM_Pos (6U)
9615 #define GFXMMU_CR_192BM_Msk (0x1UL << GFXMMU_CR_192BM_Pos) /*!< 0x00000040 */
9616 #define GFXMMU_CR_192BM GFXMMU_CR_192BM_Msk /*!< 192 block mode */
9617 #define GFXMMU_CR_CE_Pos (7U)
9618 #define GFXMMU_CR_CE_Msk (0x1UL << GFXMMU_CR_CE_Pos) /*!< 0x00000080 */
9619 #define GFXMMU_CR_CE GFXMMU_CR_CE_Msk /*!< Cache Enable */
9620 #define GFXMMU_CR_CL_Pos (8U)
9621 #define GFXMMU_CR_CL_Msk (0x1UL << GFXMMU_CR_CL_Pos) /*!< 0x00000100 */
9622 #define GFXMMU_CR_CL GFXMMU_CR_CL_Msk /*!< Cache Lock */
9623 #define GFXMMU_CR_CLB_Pos (9U)
9624 #define GFXMMU_CR_CLB_Msk (0x3UL << GFXMMU_CR_CLB_Pos) /*!< 0x00000600 */
9625 #define GFXMMU_CR_CLB GFXMMU_CR_CLB_Msk /*!< CLB[1:0]: Cache Lock Buffer */
9626 #define GFXMMU_CR_CLB_0 (0x1UL << GFXMMU_CR_CLB_Pos) /*!< Cache locked on buffer 1 */
9627 #define GFXMMU_CR_CLB_1 (0x2UL << GFXMMU_CR_CLB_Pos) /*!< Cache locked on buffer 2 */
9628 #define GFXMMU_CR_FC_Pos (11U)
9629 #define GFXMMU_CR_FC_Msk (0x1UL << GFXMMU_CR_FC_Pos) /*!< 0x00000800 */
9630 #define GFXMMU_CR_FC GFXMMU_CR_FC_Msk /*!< Force Caching */
9631 #define GFXMMU_CR_PD_Pos (12U)
9632 #define GFXMMU_CR_PD_Msk (0x1UL << GFXMMU_CR_PD_Pos) /*!< 0x00001000 */
9633 #define GFXMMU_CR_PD GFXMMU_CR_PD_Msk /*!< Prefetch Disable */
9634 #define GFXMMU_CR_OC_Pos (16U)
9635 #define GFXMMU_CR_OC_Msk (0x1UL << GFXMMU_CR_OC_Pos) /*!< 0x00002000 */
9636 #define GFXMMU_CR_OC GFXMMU_CR_OC_Msk /*!< Outter Cachability */
9637 #define GFXMMU_CR_OB_Pos (17U)
9638 #define GFXMMU_CR_OB_Msk (0x1UL << GFXMMU_CR_OB_Pos) /*!< 0x00002000 */
9639 #define GFXMMU_CR_OB GFXMMU_CR_OB_Msk /*!< Outter Bufferability */
9640
9641 /****************** Bits definition for GFXMMU_SR register ********************/
9642 #define GFXMMU_SR_B0OF_Pos (0U)
9643 #define GFXMMU_SR_B0OF_Msk (0x1UL << GFXMMU_SR_B0OF_Pos) /*!< 0x00000001 */
9644 #define GFXMMU_SR_B0OF GFXMMU_SR_B0OF_Msk /*!< Buffer 0 overflow flag */
9645 #define GFXMMU_SR_B1OF_Pos (1U)
9646 #define GFXMMU_SR_B1OF_Msk (0x1UL << GFXMMU_SR_B1OF_Pos) /*!< 0x00000002 */
9647 #define GFXMMU_SR_B1OF GFXMMU_SR_B1OF_Msk /*!< Buffer 1 overflow flag */
9648 #define GFXMMU_SR_B2OF_Pos (2U)
9649 #define GFXMMU_SR_B2OF_Msk (0x1UL << GFXMMU_SR_B2OF_Pos) /*!< 0x00000004 */
9650 #define GFXMMU_SR_B2OF GFXMMU_SR_B2OF_Msk /*!< Buffer 2 overflow flag */
9651 #define GFXMMU_SR_B3OF_Pos (3U)
9652 #define GFXMMU_SR_B3OF_Msk (0x1UL << GFXMMU_SR_B3OF_Pos) /*!< 0x00000008 */
9653 #define GFXMMU_SR_B3OF GFXMMU_SR_B3OF_Msk /*!< Buffer 3 overflow flag */
9654 #define GFXMMU_SR_AMEF_Pos (4U)
9655 #define GFXMMU_SR_AMEF_Msk (0x1UL << GFXMMU_SR_AMEF_Pos) /*!< 0x00000010 */
9656 #define GFXMMU_SR_AMEF GFXMMU_SR_AMEF_Msk /*!< AHB master error flag */
9657
9658 /****************** Bits definition for GFXMMU_FCR register *******************/
9659 #define GFXMMU_FCR_CB0OF_Pos (0U)
9660 #define GFXMMU_FCR_CB0OF_Msk (0x1UL << GFXMMU_FCR_CB0OF_Pos) /*!< 0x00000001 */
9661 #define GFXMMU_FCR_CB0OF GFXMMU_FCR_CB0OF_Msk /*!< Clear buffer 0 overflow flag */
9662 #define GFXMMU_FCR_CB1OF_Pos (1U)
9663 #define GFXMMU_FCR_CB1OF_Msk (0x1UL << GFXMMU_FCR_CB1OF_Pos) /*!< 0x00000002 */
9664 #define GFXMMU_FCR_CB1OF GFXMMU_FCR_CB1OF_Msk /*!< Clear buffer 1 overflow flag */
9665 #define GFXMMU_FCR_CB2OF_Pos (2U)
9666 #define GFXMMU_FCR_CB2OF_Msk (0x1UL << GFXMMU_FCR_CB2OF_Pos) /*!< 0x00000004 */
9667 #define GFXMMU_FCR_CB2OF GFXMMU_FCR_CB2OF_Msk /*!< Clear buffer 2 overflow flag */
9668 #define GFXMMU_FCR_CB3OF_Pos (3U)
9669 #define GFXMMU_FCR_CB3OF_Msk (0x1UL << GFXMMU_FCR_CB3OF_Pos) /*!< 0x00000008 */
9670 #define GFXMMU_FCR_CB3OF GFXMMU_FCR_CB3OF_Msk /*!< Clear buffer 3 overflow flag */
9671 #define GFXMMU_FCR_CAMEF_Pos (4U)
9672 #define GFXMMU_FCR_CAMEF_Msk (0x1UL << GFXMMU_FCR_CAMEF_Pos) /*!< 0x00000010 */
9673 #define GFXMMU_FCR_CAMEF GFXMMU_FCR_CAMEF_Msk /*!< Clear AHB master error flag */
9674
9675 /****************** Bits definition for GFXMMU_CCR register *******************/
9676 #define GFXMMU_CCR_FF_Pos (0U)
9677 #define GFXMMU_CCR_FF_Msk (0x1UL << GFXMMU_CCR_FF_Pos) /*!< 0x00000001 */
9678 #define GFXMMU_CCR_FF GFXMMU_CCR_FF_Msk /*!< Clear buffer 0 overflow flag */
9679 #define GFXMMU_CCR_FI_Pos (1U)
9680 #define GFXMMU_CCR_FI_Msk (0x1UL << GFXMMU_CCR_FI_Pos) /*!< 0x00000002 */
9681 #define GFXMMU_CCR_FI GFXMMU_CCR_FI_Msk /*!< Clear buffer 1 overflow flag */
9682
9683 /****************** Bits definition for GFXMMU_DVR register *******************/
9684 #define GFXMMU_DVR_DV_Pos (0U)
9685 #define GFXMMU_DVR_DV_Msk (0xFFFFFFFFUL << GFXMMU_DVR_DV_Pos) /*!< 0xFFFFFFFF */
9686 #define GFXMMU_DVR_DV GFXMMU_DVR_DV_Msk /*!< DV[31:0] bits (Default value) */
9687
9688 /****************** Bits definition for GFXMMU_B0CR register ******************/
9689 #define GFXMMU_B0CR_PBO_Pos (4U)
9690 #define GFXMMU_B0CR_PBO_Msk (0x7FFFFUL << GFXMMU_B0CR_PBO_Pos) /*!< 0x007FFFF0 */
9691 #define GFXMMU_B0CR_PBO GFXMMU_B0CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9692 #define GFXMMU_B0CR_PBBA_Pos (23U)
9693 #define GFXMMU_B0CR_PBBA_Msk (0x1FFUL << GFXMMU_B0CR_PBBA_Pos) /*!< 0xFF800000 */
9694 #define GFXMMU_B0CR_PBBA GFXMMU_B0CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9695
9696 /****************** Bits definition for GFXMMU_B1CR register ******************/
9697 #define GFXMMU_B1CR_PBO_Pos (4U)
9698 #define GFXMMU_B1CR_PBO_Msk (0x7FFFFUL << GFXMMU_B1CR_PBO_Pos) /*!< 0x007FFFF0 */
9699 #define GFXMMU_B1CR_PBO GFXMMU_B1CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9700 #define GFXMMU_B1CR_PBBA_Pos (23U)
9701 #define GFXMMU_B1CR_PBBA_Msk (0x1FFUL << GFXMMU_B1CR_PBBA_Pos) /*!< 0xFF800000 */
9702 #define GFXMMU_B1CR_PBBA GFXMMU_B1CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9703
9704 /****************** Bits definition for GFXMMU_B2CR register ******************/
9705 #define GFXMMU_B2CR_PBO_Pos (4U)
9706 #define GFXMMU_B2CR_PBO_Msk (0x7FFFFUL << GFXMMU_B2CR_PBO_Pos) /*!< 0x007FFFF0 */
9707 #define GFXMMU_B2CR_PBO GFXMMU_B2CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9708 #define GFXMMU_B2CR_PBBA_Pos (23U)
9709 #define GFXMMU_B2CR_PBBA_Msk (0x1FFUL << GFXMMU_B2CR_PBBA_Pos) /*!< 0xFF800000 */
9710 #define GFXMMU_B2CR_PBBA GFXMMU_B2CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9711
9712 /****************** Bits definition for GFXMMU_B3CR register ******************/
9713 #define GFXMMU_B3CR_PBO_Pos (4U)
9714 #define GFXMMU_B3CR_PBO_Msk (0x7FFFFUL << GFXMMU_B3CR_PBO_Pos) /*!< 0x007FFFF0 */
9715 #define GFXMMU_B3CR_PBO GFXMMU_B3CR_PBO_Msk /*!< PB0[22:4] bits (Physical buffer offset) */
9716 #define GFXMMU_B3CR_PBBA_Pos (23U)
9717 #define GFXMMU_B3CR_PBBA_Msk (0x1FFUL << GFXMMU_B3CR_PBBA_Pos) /*!< 0xFF800000 */
9718 #define GFXMMU_B3CR_PBBA GFXMMU_B3CR_PBBA_Msk /*!< PBBA[31:23] bits (Physical buffer base address) */
9719
9720 /****************** Bits definition for GFXMMU_HWCFGR register ****************/
9721 #define GFXMMU_HWCFGR_TBD_Pos (0U)
9722 #define GFXMMU_HWCFGR_TBD_Msk (0xFFFFFFFFUL << GFXMMU_HWCFGR_TBD_Pos) /*!< 0xFFFFFFFF */
9723 #define GFXMMU_HWCFGR_TBD GFXMMU_HWCFGR_TBD_Msk /*!< TBD[31:0] bits (To be defined) */
9724
9725 /****************** Bits definition for GFXMMU_VERR register ******************/
9726 #define GFXMMU_VERR_MINREV_Pos (0U)
9727 #define GFXMMU_VERR_MINREV_Msk (0xFUL << GFXMMU_VERR_MINREV_Pos) /*!< 0x0000000F */
9728 #define GFXMMU_VERR_MINREV GFXMMU_VERR_MINREV_Msk /*!< MINREV[3:0] bits (Minor revision) */
9729 #define GFXMMU_VERR_MAJREV_Pos (4U)
9730 #define GFXMMU_VERR_MAJREV_Msk (0xFUL << GFXMMU_VERR_MAJREV_Pos) /*!< 0x000000F0 */
9731 #define GFXMMU_VERR_MAJREV GFXMMU_VERR_MAJREV_Msk /*!< MAJREV[3:0] bits (Major revision) */
9732
9733 /****************** Bits definition for GFXMMU_IPIDR register *****************/
9734 #define GFXMMU_IPIDR_ID_Pos (0U)
9735 #define GFXMMU_IPIDR_ID_Msk (0xFFFFFFFFUL << GFXMMU_IPIDR_ID_Pos) /*!< 0xFFFFFFFF */
9736 #define GFXMMU_IPIDR_ID GFXMMU_IPIDR_ID_Msk /*!< ID[31:0] bits (Identification code) */
9737
9738 /****************** Bits definition for GFXMMU_SIDR register ******************/
9739 #define GFXMMU_SIDR_SID_Pos (0U)
9740 #define GFXMMU_SIDR_SID_Msk (0xFFFFFFFFUL << GFXMMU_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
9741 #define GFXMMU_SIDR_SID GFXMMU_SIDR_SID_Msk /*!< SID[31:0] bits (Size and id) */
9742
9743 /****************** Bits definition for GFXMMU_LUTxL register *****************/
9744 #define GFXMMU_LUTxL_EN_Pos (0U)
9745 #define GFXMMU_LUTxL_EN_Msk (0x1UL << GFXMMU_LUTxL_EN_Pos) /*!< 0x00000001 */
9746 #define GFXMMU_LUTxL_EN GFXMMU_LUTxL_EN_Msk /*!< Enable */
9747 #define GFXMMU_LUTxL_FVB_Pos (8U)
9748 #define GFXMMU_LUTxL_FVB_Msk (0xFFUL << GFXMMU_LUTxL_FVB_Pos) /*!< 0x0000FF00 */
9749 #define GFXMMU_LUTxL_FVB GFXMMU_LUTxL_FVB_Msk /*!< FVB[7:0] bits (First visible block) */
9750 #define GFXMMU_LUTxL_LVB_Pos (16U)
9751 #define GFXMMU_LUTxL_LVB_Msk (0xFFUL << GFXMMU_LUTxL_LVB_Pos) /*!< 0x00FF0000 */
9752 #define GFXMMU_LUTxL_LVB GFXMMU_LUTxL_LVB_Msk /*!< LVB[7:0] bits (Last visible block) */
9753
9754 /****************** Bits definition for GFXMMU_LUTxH register *****************/
9755 #define GFXMMU_LUTxH_LO_Pos (4U)
9756 #define GFXMMU_LUTxH_LO_Msk (0x3FFFFUL << GFXMMU_LUTxH_LO_Pos) /*!< 0x003FFFF0 */
9757 #define GFXMMU_LUTxH_LO GFXMMU_LUTxH_LO_Msk /*!< LO[21:4] bits (Line offset) */
9758
9759 /******************************************************************************/
9760 /* */
9761 /* General Purpose I/O */
9762 /* */
9763 /******************************************************************************/
9764 /****************** Bits definition for GPIO_MODER register *****************/
9765 #define GPIO_MODER_MODE0_Pos (0U)
9766 #define GPIO_MODER_MODE0_Msk (0x3UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000003 */
9767 #define GPIO_MODER_MODE0 GPIO_MODER_MODE0_Msk
9768 #define GPIO_MODER_MODE0_0 (0x1UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000001 */
9769 #define GPIO_MODER_MODE0_1 (0x2UL << GPIO_MODER_MODE0_Pos) /*!< 0x00000002 */
9770
9771 #define GPIO_MODER_MODE1_Pos (2U)
9772 #define GPIO_MODER_MODE1_Msk (0x3UL << GPIO_MODER_MODE1_Pos) /*!< 0x0000000C */
9773 #define GPIO_MODER_MODE1 GPIO_MODER_MODE1_Msk
9774 #define GPIO_MODER_MODE1_0 (0x1UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000004 */
9775 #define GPIO_MODER_MODE1_1 (0x2UL << GPIO_MODER_MODE1_Pos) /*!< 0x00000008 */
9776
9777 #define GPIO_MODER_MODE2_Pos (4U)
9778 #define GPIO_MODER_MODE2_Msk (0x3UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000030 */
9779 #define GPIO_MODER_MODE2 GPIO_MODER_MODE2_Msk
9780 #define GPIO_MODER_MODE2_0 (0x1UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000010 */
9781 #define GPIO_MODER_MODE2_1 (0x2UL << GPIO_MODER_MODE2_Pos) /*!< 0x00000020 */
9782
9783 #define GPIO_MODER_MODE3_Pos (6U)
9784 #define GPIO_MODER_MODE3_Msk (0x3UL << GPIO_MODER_MODE3_Pos) /*!< 0x000000C0 */
9785 #define GPIO_MODER_MODE3 GPIO_MODER_MODE3_Msk
9786 #define GPIO_MODER_MODE3_0 (0x1UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000040 */
9787 #define GPIO_MODER_MODE3_1 (0x2UL << GPIO_MODER_MODE3_Pos) /*!< 0x00000080 */
9788
9789 #define GPIO_MODER_MODE4_Pos (8U)
9790 #define GPIO_MODER_MODE4_Msk (0x3UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000300 */
9791 #define GPIO_MODER_MODE4 GPIO_MODER_MODE4_Msk
9792 #define GPIO_MODER_MODE4_0 (0x1UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000100 */
9793 #define GPIO_MODER_MODE4_1 (0x2UL << GPIO_MODER_MODE4_Pos) /*!< 0x00000200 */
9794
9795 #define GPIO_MODER_MODE5_Pos (10U)
9796 #define GPIO_MODER_MODE5_Msk (0x3UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000C00 */
9797 #define GPIO_MODER_MODE5 GPIO_MODER_MODE5_Msk
9798 #define GPIO_MODER_MODE5_0 (0x1UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000400 */
9799 #define GPIO_MODER_MODE5_1 (0x2UL << GPIO_MODER_MODE5_Pos) /*!< 0x00000800 */
9800
9801 #define GPIO_MODER_MODE6_Pos (12U)
9802 #define GPIO_MODER_MODE6_Msk (0x3UL << GPIO_MODER_MODE6_Pos) /*!< 0x00003000 */
9803 #define GPIO_MODER_MODE6 GPIO_MODER_MODE6_Msk
9804 #define GPIO_MODER_MODE6_0 (0x1UL << GPIO_MODER_MODE6_Pos) /*!< 0x00001000 */
9805 #define GPIO_MODER_MODE6_1 (0x2UL << GPIO_MODER_MODE6_Pos) /*!< 0x00002000 */
9806
9807 #define GPIO_MODER_MODE7_Pos (14U)
9808 #define GPIO_MODER_MODE7_Msk (0x3UL << GPIO_MODER_MODE7_Pos) /*!< 0x0000C000 */
9809 #define GPIO_MODER_MODE7 GPIO_MODER_MODE7_Msk
9810 #define GPIO_MODER_MODE7_0 (0x1UL << GPIO_MODER_MODE7_Pos) /*!< 0x00004000 */
9811 #define GPIO_MODER_MODE7_1 (0x2UL << GPIO_MODER_MODE7_Pos) /*!< 0x00008000 */
9812
9813 #define GPIO_MODER_MODE8_Pos (16U)
9814 #define GPIO_MODER_MODE8_Msk (0x3UL << GPIO_MODER_MODE8_Pos) /*!< 0x00030000 */
9815 #define GPIO_MODER_MODE8 GPIO_MODER_MODE8_Msk
9816 #define GPIO_MODER_MODE8_0 (0x1UL << GPIO_MODER_MODE8_Pos) /*!< 0x00010000 */
9817 #define GPIO_MODER_MODE8_1 (0x2UL << GPIO_MODER_MODE8_Pos) /*!< 0x00020000 */
9818
9819 #define GPIO_MODER_MODE9_Pos (18U)
9820 #define GPIO_MODER_MODE9_Msk (0x3UL << GPIO_MODER_MODE9_Pos) /*!< 0x000C0000 */
9821 #define GPIO_MODER_MODE9 GPIO_MODER_MODE9_Msk
9822 #define GPIO_MODER_MODE9_0 (0x1UL << GPIO_MODER_MODE9_Pos) /*!< 0x00040000 */
9823 #define GPIO_MODER_MODE9_1 (0x2UL << GPIO_MODER_MODE9_Pos) /*!< 0x00080000 */
9824
9825 #define GPIO_MODER_MODE10_Pos (20U)
9826 #define GPIO_MODER_MODE10_Msk (0x3UL << GPIO_MODER_MODE10_Pos) /*!< 0x00300000 */
9827 #define GPIO_MODER_MODE10 GPIO_MODER_MODE10_Msk
9828 #define GPIO_MODER_MODE10_0 (0x1UL << GPIO_MODER_MODE10_Pos) /*!< 0x00100000 */
9829 #define GPIO_MODER_MODE10_1 (0x2UL << GPIO_MODER_MODE10_Pos) /*!< 0x00200000 */
9830
9831 #define GPIO_MODER_MODE11_Pos (22U)
9832 #define GPIO_MODER_MODE11_Msk (0x3UL << GPIO_MODER_MODE11_Pos) /*!< 0x00C00000 */
9833 #define GPIO_MODER_MODE11 GPIO_MODER_MODE11_Msk
9834 #define GPIO_MODER_MODE11_0 (0x1UL << GPIO_MODER_MODE11_Pos) /*!< 0x00400000 */
9835 #define GPIO_MODER_MODE11_1 (0x2UL << GPIO_MODER_MODE11_Pos) /*!< 0x00800000 */
9836
9837 #define GPIO_MODER_MODE12_Pos (24U)
9838 #define GPIO_MODER_MODE12_Msk (0x3UL << GPIO_MODER_MODE12_Pos) /*!< 0x03000000 */
9839 #define GPIO_MODER_MODE12 GPIO_MODER_MODE12_Msk
9840 #define GPIO_MODER_MODE12_0 (0x1UL << GPIO_MODER_MODE12_Pos) /*!< 0x01000000 */
9841 #define GPIO_MODER_MODE12_1 (0x2UL << GPIO_MODER_MODE12_Pos) /*!< 0x02000000 */
9842
9843 #define GPIO_MODER_MODE13_Pos (26U)
9844 #define GPIO_MODER_MODE13_Msk (0x3UL << GPIO_MODER_MODE13_Pos) /*!< 0x0C000000 */
9845 #define GPIO_MODER_MODE13 GPIO_MODER_MODE13_Msk
9846 #define GPIO_MODER_MODE13_0 (0x1UL << GPIO_MODER_MODE13_Pos) /*!< 0x04000000 */
9847 #define GPIO_MODER_MODE13_1 (0x2UL << GPIO_MODER_MODE13_Pos) /*!< 0x08000000 */
9848
9849 #define GPIO_MODER_MODE14_Pos (28U)
9850 #define GPIO_MODER_MODE14_Msk (0x3UL << GPIO_MODER_MODE14_Pos) /*!< 0x30000000 */
9851 #define GPIO_MODER_MODE14 GPIO_MODER_MODE14_Msk
9852 #define GPIO_MODER_MODE14_0 (0x1UL << GPIO_MODER_MODE14_Pos) /*!< 0x10000000 */
9853 #define GPIO_MODER_MODE14_1 (0x2UL << GPIO_MODER_MODE14_Pos) /*!< 0x20000000 */
9854
9855 #define GPIO_MODER_MODE15_Pos (30U)
9856 #define GPIO_MODER_MODE15_Msk (0x3UL << GPIO_MODER_MODE15_Pos) /*!< 0xC0000000 */
9857 #define GPIO_MODER_MODE15 GPIO_MODER_MODE15_Msk
9858 #define GPIO_MODER_MODE15_0 (0x1UL << GPIO_MODER_MODE15_Pos) /*!< 0x40000000 */
9859 #define GPIO_MODER_MODE15_1 (0x2UL << GPIO_MODER_MODE15_Pos) /*!< 0x80000000 */
9860
9861 /****************** Bits definition for GPIO_OTYPER register ****************/
9862 #define GPIO_OTYPER_OT0_Pos (0U)
9863 #define GPIO_OTYPER_OT0_Msk (0x1UL << GPIO_OTYPER_OT0_Pos) /*!< 0x00000001 */
9864 #define GPIO_OTYPER_OT0 GPIO_OTYPER_OT0_Msk
9865 #define GPIO_OTYPER_OT1_Pos (1U)
9866 #define GPIO_OTYPER_OT1_Msk (0x1UL << GPIO_OTYPER_OT1_Pos) /*!< 0x00000002 */
9867 #define GPIO_OTYPER_OT1 GPIO_OTYPER_OT1_Msk
9868 #define GPIO_OTYPER_OT2_Pos (2U)
9869 #define GPIO_OTYPER_OT2_Msk (0x1UL << GPIO_OTYPER_OT2_Pos) /*!< 0x00000004 */
9870 #define GPIO_OTYPER_OT2 GPIO_OTYPER_OT2_Msk
9871 #define GPIO_OTYPER_OT3_Pos (3U)
9872 #define GPIO_OTYPER_OT3_Msk (0x1UL << GPIO_OTYPER_OT3_Pos) /*!< 0x00000008 */
9873 #define GPIO_OTYPER_OT3 GPIO_OTYPER_OT3_Msk
9874 #define GPIO_OTYPER_OT4_Pos (4U)
9875 #define GPIO_OTYPER_OT4_Msk (0x1UL << GPIO_OTYPER_OT4_Pos) /*!< 0x00000010 */
9876 #define GPIO_OTYPER_OT4 GPIO_OTYPER_OT4_Msk
9877 #define GPIO_OTYPER_OT5_Pos (5U)
9878 #define GPIO_OTYPER_OT5_Msk (0x1UL << GPIO_OTYPER_OT5_Pos) /*!< 0x00000020 */
9879 #define GPIO_OTYPER_OT5 GPIO_OTYPER_OT5_Msk
9880 #define GPIO_OTYPER_OT6_Pos (6U)
9881 #define GPIO_OTYPER_OT6_Msk (0x1UL << GPIO_OTYPER_OT6_Pos) /*!< 0x00000040 */
9882 #define GPIO_OTYPER_OT6 GPIO_OTYPER_OT6_Msk
9883 #define GPIO_OTYPER_OT7_Pos (7U)
9884 #define GPIO_OTYPER_OT7_Msk (0x1UL << GPIO_OTYPER_OT7_Pos) /*!< 0x00000080 */
9885 #define GPIO_OTYPER_OT7 GPIO_OTYPER_OT7_Msk
9886 #define GPIO_OTYPER_OT8_Pos (8U)
9887 #define GPIO_OTYPER_OT8_Msk (0x1UL << GPIO_OTYPER_OT8_Pos) /*!< 0x00000100 */
9888 #define GPIO_OTYPER_OT8 GPIO_OTYPER_OT8_Msk
9889 #define GPIO_OTYPER_OT9_Pos (9U)
9890 #define GPIO_OTYPER_OT9_Msk (0x1UL << GPIO_OTYPER_OT9_Pos) /*!< 0x00000200 */
9891 #define GPIO_OTYPER_OT9 GPIO_OTYPER_OT9_Msk
9892 #define GPIO_OTYPER_OT10_Pos (10U)
9893 #define GPIO_OTYPER_OT10_Msk (0x1UL << GPIO_OTYPER_OT10_Pos) /*!< 0x00000400 */
9894 #define GPIO_OTYPER_OT10 GPIO_OTYPER_OT10_Msk
9895 #define GPIO_OTYPER_OT11_Pos (11U)
9896 #define GPIO_OTYPER_OT11_Msk (0x1UL << GPIO_OTYPER_OT11_Pos) /*!< 0x00000800 */
9897 #define GPIO_OTYPER_OT11 GPIO_OTYPER_OT11_Msk
9898 #define GPIO_OTYPER_OT12_Pos (12U)
9899 #define GPIO_OTYPER_OT12_Msk (0x1UL << GPIO_OTYPER_OT12_Pos) /*!< 0x00001000 */
9900 #define GPIO_OTYPER_OT12 GPIO_OTYPER_OT12_Msk
9901 #define GPIO_OTYPER_OT13_Pos (13U)
9902 #define GPIO_OTYPER_OT13_Msk (0x1UL << GPIO_OTYPER_OT13_Pos) /*!< 0x00002000 */
9903 #define GPIO_OTYPER_OT13 GPIO_OTYPER_OT13_Msk
9904 #define GPIO_OTYPER_OT14_Pos (14U)
9905 #define GPIO_OTYPER_OT14_Msk (0x1UL << GPIO_OTYPER_OT14_Pos) /*!< 0x00004000 */
9906 #define GPIO_OTYPER_OT14 GPIO_OTYPER_OT14_Msk
9907 #define GPIO_OTYPER_OT15_Pos (15U)
9908 #define GPIO_OTYPER_OT15_Msk (0x1UL << GPIO_OTYPER_OT15_Pos) /*!< 0x00008000 */
9909 #define GPIO_OTYPER_OT15 GPIO_OTYPER_OT15_Msk
9910
9911 /****************** Bits definition for GPIO_OSPEEDR register ***************/
9912 #define GPIO_OSPEEDR_OSPEED0_Pos (0U)
9913 #define GPIO_OSPEEDR_OSPEED0_Msk (0x3UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000003 */
9914 #define GPIO_OSPEEDR_OSPEED0 GPIO_OSPEEDR_OSPEED0_Msk
9915 #define GPIO_OSPEEDR_OSPEED0_0 (0x1UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000001 */
9916 #define GPIO_OSPEEDR_OSPEED0_1 (0x2UL << GPIO_OSPEEDR_OSPEED0_Pos) /*!< 0x00000002 */
9917
9918 #define GPIO_OSPEEDR_OSPEED1_Pos (2U)
9919 #define GPIO_OSPEEDR_OSPEED1_Msk (0x3UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x0000000C */
9920 #define GPIO_OSPEEDR_OSPEED1 GPIO_OSPEEDR_OSPEED1_Msk
9921 #define GPIO_OSPEEDR_OSPEED1_0 (0x1UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000004 */
9922 #define GPIO_OSPEEDR_OSPEED1_1 (0x2UL << GPIO_OSPEEDR_OSPEED1_Pos) /*!< 0x00000008 */
9923
9924 #define GPIO_OSPEEDR_OSPEED2_Pos (4U)
9925 #define GPIO_OSPEEDR_OSPEED2_Msk (0x3UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000030 */
9926 #define GPIO_OSPEEDR_OSPEED2 GPIO_OSPEEDR_OSPEED2_Msk
9927 #define GPIO_OSPEEDR_OSPEED2_0 (0x1UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000010 */
9928 #define GPIO_OSPEEDR_OSPEED2_1 (0x2UL << GPIO_OSPEEDR_OSPEED2_Pos) /*!< 0x00000020 */
9929
9930 #define GPIO_OSPEEDR_OSPEED3_Pos (6U)
9931 #define GPIO_OSPEEDR_OSPEED3_Msk (0x3UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x000000C0 */
9932 #define GPIO_OSPEEDR_OSPEED3 GPIO_OSPEEDR_OSPEED3_Msk
9933 #define GPIO_OSPEEDR_OSPEED3_0 (0x1UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000040 */
9934 #define GPIO_OSPEEDR_OSPEED3_1 (0x2UL << GPIO_OSPEEDR_OSPEED3_Pos) /*!< 0x00000080 */
9935
9936 #define GPIO_OSPEEDR_OSPEED4_Pos (8U)
9937 #define GPIO_OSPEEDR_OSPEED4_Msk (0x3UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000300 */
9938 #define GPIO_OSPEEDR_OSPEED4 GPIO_OSPEEDR_OSPEED4_Msk
9939 #define GPIO_OSPEEDR_OSPEED4_0 (0x1UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000100 */
9940 #define GPIO_OSPEEDR_OSPEED4_1 (0x2UL << GPIO_OSPEEDR_OSPEED4_Pos) /*!< 0x00000200 */
9941
9942 #define GPIO_OSPEEDR_OSPEED5_Pos (10U)
9943 #define GPIO_OSPEEDR_OSPEED5_Msk (0x3UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000C00 */
9944 #define GPIO_OSPEEDR_OSPEED5 GPIO_OSPEEDR_OSPEED5_Msk
9945 #define GPIO_OSPEEDR_OSPEED5_0 (0x1UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000400 */
9946 #define GPIO_OSPEEDR_OSPEED5_1 (0x2UL << GPIO_OSPEEDR_OSPEED5_Pos) /*!< 0x00000800 */
9947
9948 #define GPIO_OSPEEDR_OSPEED6_Pos (12U)
9949 #define GPIO_OSPEEDR_OSPEED6_Msk (0x3UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00003000 */
9950 #define GPIO_OSPEEDR_OSPEED6 GPIO_OSPEEDR_OSPEED6_Msk
9951 #define GPIO_OSPEEDR_OSPEED6_0 (0x1UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00001000 */
9952 #define GPIO_OSPEEDR_OSPEED6_1 (0x2UL << GPIO_OSPEEDR_OSPEED6_Pos) /*!< 0x00002000 */
9953
9954 #define GPIO_OSPEEDR_OSPEED7_Pos (14U)
9955 #define GPIO_OSPEEDR_OSPEED7_Msk (0x3UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x0000C000 */
9956 #define GPIO_OSPEEDR_OSPEED7 GPIO_OSPEEDR_OSPEED7_Msk
9957 #define GPIO_OSPEEDR_OSPEED7_0 (0x1UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00004000 */
9958 #define GPIO_OSPEEDR_OSPEED7_1 (0x2UL << GPIO_OSPEEDR_OSPEED7_Pos) /*!< 0x00008000 */
9959
9960 #define GPIO_OSPEEDR_OSPEED8_Pos (16U)
9961 #define GPIO_OSPEEDR_OSPEED8_Msk (0x3UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00030000 */
9962 #define GPIO_OSPEEDR_OSPEED8 GPIO_OSPEEDR_OSPEED8_Msk
9963 #define GPIO_OSPEEDR_OSPEED8_0 (0x1UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00010000 */
9964 #define GPIO_OSPEEDR_OSPEED8_1 (0x2UL << GPIO_OSPEEDR_OSPEED8_Pos) /*!< 0x00020000 */
9965
9966 #define GPIO_OSPEEDR_OSPEED9_Pos (18U)
9967 #define GPIO_OSPEEDR_OSPEED9_Msk (0x3UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x000C0000 */
9968 #define GPIO_OSPEEDR_OSPEED9 GPIO_OSPEEDR_OSPEED9_Msk
9969 #define GPIO_OSPEEDR_OSPEED9_0 (0x1UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00040000 */
9970 #define GPIO_OSPEEDR_OSPEED9_1 (0x2UL << GPIO_OSPEEDR_OSPEED9_Pos) /*!< 0x00080000 */
9971
9972 #define GPIO_OSPEEDR_OSPEED10_Pos (20U)
9973 #define GPIO_OSPEEDR_OSPEED10_Msk (0x3UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00300000 */
9974 #define GPIO_OSPEEDR_OSPEED10 GPIO_OSPEEDR_OSPEED10_Msk
9975 #define GPIO_OSPEEDR_OSPEED10_0 (0x1UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00100000 */
9976 #define GPIO_OSPEEDR_OSPEED10_1 (0x2UL << GPIO_OSPEEDR_OSPEED10_Pos) /*!< 0x00200000 */
9977
9978 #define GPIO_OSPEEDR_OSPEED11_Pos (22U)
9979 #define GPIO_OSPEEDR_OSPEED11_Msk (0x3UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00C00000 */
9980 #define GPIO_OSPEEDR_OSPEED11 GPIO_OSPEEDR_OSPEED11_Msk
9981 #define GPIO_OSPEEDR_OSPEED11_0 (0x1UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00400000 */
9982 #define GPIO_OSPEEDR_OSPEED11_1 (0x2UL << GPIO_OSPEEDR_OSPEED11_Pos) /*!< 0x00800000 */
9983
9984 #define GPIO_OSPEEDR_OSPEED12_Pos (24U)
9985 #define GPIO_OSPEEDR_OSPEED12_Msk (0x3UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x03000000 */
9986 #define GPIO_OSPEEDR_OSPEED12 GPIO_OSPEEDR_OSPEED12_Msk
9987 #define GPIO_OSPEEDR_OSPEED12_0 (0x1UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x01000000 */
9988 #define GPIO_OSPEEDR_OSPEED12_1 (0x2UL << GPIO_OSPEEDR_OSPEED12_Pos) /*!< 0x02000000 */
9989
9990 #define GPIO_OSPEEDR_OSPEED13_Pos (26U)
9991 #define GPIO_OSPEEDR_OSPEED13_Msk (0x3UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x0C000000 */
9992 #define GPIO_OSPEEDR_OSPEED13 GPIO_OSPEEDR_OSPEED13_Msk
9993 #define GPIO_OSPEEDR_OSPEED13_0 (0x1UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x04000000 */
9994 #define GPIO_OSPEEDR_OSPEED13_1 (0x2UL << GPIO_OSPEEDR_OSPEED13_Pos) /*!< 0x08000000 */
9995
9996 #define GPIO_OSPEEDR_OSPEED14_Pos (28U)
9997 #define GPIO_OSPEEDR_OSPEED14_Msk (0x3UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x30000000 */
9998 #define GPIO_OSPEEDR_OSPEED14 GPIO_OSPEEDR_OSPEED14_Msk
9999 #define GPIO_OSPEEDR_OSPEED14_0 (0x1UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x10000000 */
10000 #define GPIO_OSPEEDR_OSPEED14_1 (0x2UL << GPIO_OSPEEDR_OSPEED14_Pos) /*!< 0x20000000 */
10001
10002 #define GPIO_OSPEEDR_OSPEED15_Pos (30U)
10003 #define GPIO_OSPEEDR_OSPEED15_Msk (0x3UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0xC0000000 */
10004 #define GPIO_OSPEEDR_OSPEED15 GPIO_OSPEEDR_OSPEED15_Msk
10005 #define GPIO_OSPEEDR_OSPEED15_0 (0x1UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x40000000 */
10006 #define GPIO_OSPEEDR_OSPEED15_1 (0x2UL << GPIO_OSPEEDR_OSPEED15_Pos) /*!< 0x80000000 */
10007
10008 /****************** Bits definition for GPIO_PUPDR register *****************/
10009 #define GPIO_PUPDR_PUPD0_Pos (0U)
10010 #define GPIO_PUPDR_PUPD0_Msk (0x3UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000003 */
10011 #define GPIO_PUPDR_PUPD0 GPIO_PUPDR_PUPD0_Msk
10012 #define GPIO_PUPDR_PUPD0_0 (0x1UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000001 */
10013 #define GPIO_PUPDR_PUPD0_1 (0x2UL << GPIO_PUPDR_PUPD0_Pos) /*!< 0x00000002 */
10014
10015 #define GPIO_PUPDR_PUPD1_Pos (2U)
10016 #define GPIO_PUPDR_PUPD1_Msk (0x3UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x0000000C */
10017 #define GPIO_PUPDR_PUPD1 GPIO_PUPDR_PUPD1_Msk
10018 #define GPIO_PUPDR_PUPD1_0 (0x1UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000004 */
10019 #define GPIO_PUPDR_PUPD1_1 (0x2UL << GPIO_PUPDR_PUPD1_Pos) /*!< 0x00000008 */
10020
10021 #define GPIO_PUPDR_PUPD2_Pos (4U)
10022 #define GPIO_PUPDR_PUPD2_Msk (0x3UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000030 */
10023 #define GPIO_PUPDR_PUPD2 GPIO_PUPDR_PUPD2_Msk
10024 #define GPIO_PUPDR_PUPD2_0 (0x1UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000010 */
10025 #define GPIO_PUPDR_PUPD2_1 (0x2UL << GPIO_PUPDR_PUPD2_Pos) /*!< 0x00000020 */
10026
10027 #define GPIO_PUPDR_PUPD3_Pos (6U)
10028 #define GPIO_PUPDR_PUPD3_Msk (0x3UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x000000C0 */
10029 #define GPIO_PUPDR_PUPD3 GPIO_PUPDR_PUPD3_Msk
10030 #define GPIO_PUPDR_PUPD3_0 (0x1UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000040 */
10031 #define GPIO_PUPDR_PUPD3_1 (0x2UL << GPIO_PUPDR_PUPD3_Pos) /*!< 0x00000080 */
10032
10033 #define GPIO_PUPDR_PUPD4_Pos (8U)
10034 #define GPIO_PUPDR_PUPD4_Msk (0x3UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000300 */
10035 #define GPIO_PUPDR_PUPD4 GPIO_PUPDR_PUPD4_Msk
10036 #define GPIO_PUPDR_PUPD4_0 (0x1UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000100 */
10037 #define GPIO_PUPDR_PUPD4_1 (0x2UL << GPIO_PUPDR_PUPD4_Pos) /*!< 0x00000200 */
10038
10039 #define GPIO_PUPDR_PUPD5_Pos (10U)
10040 #define GPIO_PUPDR_PUPD5_Msk (0x3UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000C00 */
10041 #define GPIO_PUPDR_PUPD5 GPIO_PUPDR_PUPD5_Msk
10042 #define GPIO_PUPDR_PUPD5_0 (0x1UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000400 */
10043 #define GPIO_PUPDR_PUPD5_1 (0x2UL << GPIO_PUPDR_PUPD5_Pos) /*!< 0x00000800 */
10044
10045 #define GPIO_PUPDR_PUPD6_Pos (12U)
10046 #define GPIO_PUPDR_PUPD6_Msk (0x3UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00003000 */
10047 #define GPIO_PUPDR_PUPD6 GPIO_PUPDR_PUPD6_Msk
10048 #define GPIO_PUPDR_PUPD6_0 (0x1UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00001000 */
10049 #define GPIO_PUPDR_PUPD6_1 (0x2UL << GPIO_PUPDR_PUPD6_Pos) /*!< 0x00002000 */
10050
10051 #define GPIO_PUPDR_PUPD7_Pos (14U)
10052 #define GPIO_PUPDR_PUPD7_Msk (0x3UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x0000C000 */
10053 #define GPIO_PUPDR_PUPD7 GPIO_PUPDR_PUPD7_Msk
10054 #define GPIO_PUPDR_PUPD7_0 (0x1UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00004000 */
10055 #define GPIO_PUPDR_PUPD7_1 (0x2UL << GPIO_PUPDR_PUPD7_Pos) /*!< 0x00008000 */
10056
10057 #define GPIO_PUPDR_PUPD8_Pos (16U)
10058 #define GPIO_PUPDR_PUPD8_Msk (0x3UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00030000 */
10059 #define GPIO_PUPDR_PUPD8 GPIO_PUPDR_PUPD8_Msk
10060 #define GPIO_PUPDR_PUPD8_0 (0x1UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00010000 */
10061 #define GPIO_PUPDR_PUPD8_1 (0x2UL << GPIO_PUPDR_PUPD8_Pos) /*!< 0x00020000 */
10062
10063 #define GPIO_PUPDR_PUPD9_Pos (18U)
10064 #define GPIO_PUPDR_PUPD9_Msk (0x3UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x000C0000 */
10065 #define GPIO_PUPDR_PUPD9 GPIO_PUPDR_PUPD9_Msk
10066 #define GPIO_PUPDR_PUPD9_0 (0x1UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00040000 */
10067 #define GPIO_PUPDR_PUPD9_1 (0x2UL << GPIO_PUPDR_PUPD9_Pos) /*!< 0x00080000 */
10068
10069 #define GPIO_PUPDR_PUPD10_Pos (20U)
10070 #define GPIO_PUPDR_PUPD10_Msk (0x3UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00300000 */
10071 #define GPIO_PUPDR_PUPD10 GPIO_PUPDR_PUPD10_Msk
10072 #define GPIO_PUPDR_PUPD10_0 (0x1UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00100000 */
10073 #define GPIO_PUPDR_PUPD10_1 (0x2UL << GPIO_PUPDR_PUPD10_Pos) /*!< 0x00200000 */
10074
10075 #define GPIO_PUPDR_PUPD11_Pos (22U)
10076 #define GPIO_PUPDR_PUPD11_Msk (0x3UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00C00000 */
10077 #define GPIO_PUPDR_PUPD11 GPIO_PUPDR_PUPD11_Msk
10078 #define GPIO_PUPDR_PUPD11_0 (0x1UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00400000 */
10079 #define GPIO_PUPDR_PUPD11_1 (0x2UL << GPIO_PUPDR_PUPD11_Pos) /*!< 0x00800000 */
10080
10081 #define GPIO_PUPDR_PUPD12_Pos (24U)
10082 #define GPIO_PUPDR_PUPD12_Msk (0x3UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x03000000 */
10083 #define GPIO_PUPDR_PUPD12 GPIO_PUPDR_PUPD12_Msk
10084 #define GPIO_PUPDR_PUPD12_0 (0x1UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x01000000 */
10085 #define GPIO_PUPDR_PUPD12_1 (0x2UL << GPIO_PUPDR_PUPD12_Pos) /*!< 0x02000000 */
10086
10087 #define GPIO_PUPDR_PUPD13_Pos (26U)
10088 #define GPIO_PUPDR_PUPD13_Msk (0x3UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x0C000000 */
10089 #define GPIO_PUPDR_PUPD13 GPIO_PUPDR_PUPD13_Msk
10090 #define GPIO_PUPDR_PUPD13_0 (0x1UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x04000000 */
10091 #define GPIO_PUPDR_PUPD13_1 (0x2UL << GPIO_PUPDR_PUPD13_Pos) /*!< 0x08000000 */
10092
10093 #define GPIO_PUPDR_PUPD14_Pos (28U)
10094 #define GPIO_PUPDR_PUPD14_Msk (0x3UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x30000000 */
10095 #define GPIO_PUPDR_PUPD14 GPIO_PUPDR_PUPD14_Msk
10096 #define GPIO_PUPDR_PUPD14_0 (0x1UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x10000000 */
10097 #define GPIO_PUPDR_PUPD14_1 (0x2UL << GPIO_PUPDR_PUPD14_Pos) /*!< 0x20000000 */
10098
10099 #define GPIO_PUPDR_PUPD15_Pos (30U)
10100 #define GPIO_PUPDR_PUPD15_Msk (0x3UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0xC0000000 */
10101 #define GPIO_PUPDR_PUPD15 GPIO_PUPDR_PUPD15_Msk
10102 #define GPIO_PUPDR_PUPD15_0 (0x1UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x40000000 */
10103 #define GPIO_PUPDR_PUPD15_1 (0x2UL << GPIO_PUPDR_PUPD15_Pos) /*!< 0x80000000 */
10104
10105 /****************** Bits definition for GPIO_IDR register *******************/
10106 #define GPIO_IDR_ID0_Pos (0U)
10107 #define GPIO_IDR_ID0_Msk (0x1UL << GPIO_IDR_ID0_Pos) /*!< 0x00000001 */
10108 #define GPIO_IDR_ID0 GPIO_IDR_ID0_Msk
10109 #define GPIO_IDR_ID1_Pos (1U)
10110 #define GPIO_IDR_ID1_Msk (0x1UL << GPIO_IDR_ID1_Pos) /*!< 0x00000002 */
10111 #define GPIO_IDR_ID1 GPIO_IDR_ID1_Msk
10112 #define GPIO_IDR_ID2_Pos (2U)
10113 #define GPIO_IDR_ID2_Msk (0x1UL << GPIO_IDR_ID2_Pos) /*!< 0x00000004 */
10114 #define GPIO_IDR_ID2 GPIO_IDR_ID2_Msk
10115 #define GPIO_IDR_ID3_Pos (3U)
10116 #define GPIO_IDR_ID3_Msk (0x1UL << GPIO_IDR_ID3_Pos) /*!< 0x00000008 */
10117 #define GPIO_IDR_ID3 GPIO_IDR_ID3_Msk
10118 #define GPIO_IDR_ID4_Pos (4U)
10119 #define GPIO_IDR_ID4_Msk (0x1UL << GPIO_IDR_ID4_Pos) /*!< 0x00000010 */
10120 #define GPIO_IDR_ID4 GPIO_IDR_ID4_Msk
10121 #define GPIO_IDR_ID5_Pos (5U)
10122 #define GPIO_IDR_ID5_Msk (0x1UL << GPIO_IDR_ID5_Pos) /*!< 0x00000020 */
10123 #define GPIO_IDR_ID5 GPIO_IDR_ID5_Msk
10124 #define GPIO_IDR_ID6_Pos (6U)
10125 #define GPIO_IDR_ID6_Msk (0x1UL << GPIO_IDR_ID6_Pos) /*!< 0x00000040 */
10126 #define GPIO_IDR_ID6 GPIO_IDR_ID6_Msk
10127 #define GPIO_IDR_ID7_Pos (7U)
10128 #define GPIO_IDR_ID7_Msk (0x1UL << GPIO_IDR_ID7_Pos) /*!< 0x00000080 */
10129 #define GPIO_IDR_ID7 GPIO_IDR_ID7_Msk
10130 #define GPIO_IDR_ID8_Pos (8U)
10131 #define GPIO_IDR_ID8_Msk (0x1UL << GPIO_IDR_ID8_Pos) /*!< 0x00000100 */
10132 #define GPIO_IDR_ID8 GPIO_IDR_ID8_Msk
10133 #define GPIO_IDR_ID9_Pos (9U)
10134 #define GPIO_IDR_ID9_Msk (0x1UL << GPIO_IDR_ID9_Pos) /*!< 0x00000200 */
10135 #define GPIO_IDR_ID9 GPIO_IDR_ID9_Msk
10136 #define GPIO_IDR_ID10_Pos (10U)
10137 #define GPIO_IDR_ID10_Msk (0x1UL << GPIO_IDR_ID10_Pos) /*!< 0x00000400 */
10138 #define GPIO_IDR_ID10 GPIO_IDR_ID10_Msk
10139 #define GPIO_IDR_ID11_Pos (11U)
10140 #define GPIO_IDR_ID11_Msk (0x1UL << GPIO_IDR_ID11_Pos) /*!< 0x00000800 */
10141 #define GPIO_IDR_ID11 GPIO_IDR_ID11_Msk
10142 #define GPIO_IDR_ID12_Pos (12U)
10143 #define GPIO_IDR_ID12_Msk (0x1UL << GPIO_IDR_ID12_Pos) /*!< 0x00001000 */
10144 #define GPIO_IDR_ID12 GPIO_IDR_ID12_Msk
10145 #define GPIO_IDR_ID13_Pos (13U)
10146 #define GPIO_IDR_ID13_Msk (0x1UL << GPIO_IDR_ID13_Pos) /*!< 0x00002000 */
10147 #define GPIO_IDR_ID13 GPIO_IDR_ID13_Msk
10148 #define GPIO_IDR_ID14_Pos (14U)
10149 #define GPIO_IDR_ID14_Msk (0x1UL << GPIO_IDR_ID14_Pos) /*!< 0x00004000 */
10150 #define GPIO_IDR_ID14 GPIO_IDR_ID14_Msk
10151 #define GPIO_IDR_ID15_Pos (15U)
10152 #define GPIO_IDR_ID15_Msk (0x1UL << GPIO_IDR_ID15_Pos) /*!< 0x00008000 */
10153 #define GPIO_IDR_ID15 GPIO_IDR_ID15_Msk
10154
10155 /****************** Bits definition for GPIO_ODR register *******************/
10156 #define GPIO_ODR_OD0_Pos (0U)
10157 #define GPIO_ODR_OD0_Msk (0x1UL << GPIO_ODR_OD0_Pos) /*!< 0x00000001 */
10158 #define GPIO_ODR_OD0 GPIO_ODR_OD0_Msk
10159 #define GPIO_ODR_OD1_Pos (1U)
10160 #define GPIO_ODR_OD1_Msk (0x1UL << GPIO_ODR_OD1_Pos) /*!< 0x00000002 */
10161 #define GPIO_ODR_OD1 GPIO_ODR_OD1_Msk
10162 #define GPIO_ODR_OD2_Pos (2U)
10163 #define GPIO_ODR_OD2_Msk (0x1UL << GPIO_ODR_OD2_Pos) /*!< 0x00000004 */
10164 #define GPIO_ODR_OD2 GPIO_ODR_OD2_Msk
10165 #define GPIO_ODR_OD3_Pos (3U)
10166 #define GPIO_ODR_OD3_Msk (0x1UL << GPIO_ODR_OD3_Pos) /*!< 0x00000008 */
10167 #define GPIO_ODR_OD3 GPIO_ODR_OD3_Msk
10168 #define GPIO_ODR_OD4_Pos (4U)
10169 #define GPIO_ODR_OD4_Msk (0x1UL << GPIO_ODR_OD4_Pos) /*!< 0x00000010 */
10170 #define GPIO_ODR_OD4 GPIO_ODR_OD4_Msk
10171 #define GPIO_ODR_OD5_Pos (5U)
10172 #define GPIO_ODR_OD5_Msk (0x1UL << GPIO_ODR_OD5_Pos) /*!< 0x00000020 */
10173 #define GPIO_ODR_OD5 GPIO_ODR_OD5_Msk
10174 #define GPIO_ODR_OD6_Pos (6U)
10175 #define GPIO_ODR_OD6_Msk (0x1UL << GPIO_ODR_OD6_Pos) /*!< 0x00000040 */
10176 #define GPIO_ODR_OD6 GPIO_ODR_OD6_Msk
10177 #define GPIO_ODR_OD7_Pos (7U)
10178 #define GPIO_ODR_OD7_Msk (0x1UL << GPIO_ODR_OD7_Pos) /*!< 0x00000080 */
10179 #define GPIO_ODR_OD7 GPIO_ODR_OD7_Msk
10180 #define GPIO_ODR_OD8_Pos (8U)
10181 #define GPIO_ODR_OD8_Msk (0x1UL << GPIO_ODR_OD8_Pos) /*!< 0x00000100 */
10182 #define GPIO_ODR_OD8 GPIO_ODR_OD8_Msk
10183 #define GPIO_ODR_OD9_Pos (9U)
10184 #define GPIO_ODR_OD9_Msk (0x1UL << GPIO_ODR_OD9_Pos) /*!< 0x00000200 */
10185 #define GPIO_ODR_OD9 GPIO_ODR_OD9_Msk
10186 #define GPIO_ODR_OD10_Pos (10U)
10187 #define GPIO_ODR_OD10_Msk (0x1UL << GPIO_ODR_OD10_Pos) /*!< 0x00000400 */
10188 #define GPIO_ODR_OD10 GPIO_ODR_OD10_Msk
10189 #define GPIO_ODR_OD11_Pos (11U)
10190 #define GPIO_ODR_OD11_Msk (0x1UL << GPIO_ODR_OD11_Pos) /*!< 0x00000800 */
10191 #define GPIO_ODR_OD11 GPIO_ODR_OD11_Msk
10192 #define GPIO_ODR_OD12_Pos (12U)
10193 #define GPIO_ODR_OD12_Msk (0x1UL << GPIO_ODR_OD12_Pos) /*!< 0x00001000 */
10194 #define GPIO_ODR_OD12 GPIO_ODR_OD12_Msk
10195 #define GPIO_ODR_OD13_Pos (13U)
10196 #define GPIO_ODR_OD13_Msk (0x1UL << GPIO_ODR_OD13_Pos) /*!< 0x00002000 */
10197 #define GPIO_ODR_OD13 GPIO_ODR_OD13_Msk
10198 #define GPIO_ODR_OD14_Pos (14U)
10199 #define GPIO_ODR_OD14_Msk (0x1UL << GPIO_ODR_OD14_Pos) /*!< 0x00004000 */
10200 #define GPIO_ODR_OD14 GPIO_ODR_OD14_Msk
10201 #define GPIO_ODR_OD15_Pos (15U)
10202 #define GPIO_ODR_OD15_Msk (0x1UL << GPIO_ODR_OD15_Pos) /*!< 0x00008000 */
10203 #define GPIO_ODR_OD15 GPIO_ODR_OD15_Msk
10204
10205 /****************** Bits definition for GPIO_BSRR register ******************/
10206 #define GPIO_BSRR_BS0_Pos (0U)
10207 #define GPIO_BSRR_BS0_Msk (0x1UL << GPIO_BSRR_BS0_Pos) /*!< 0x00000001 */
10208 #define GPIO_BSRR_BS0 GPIO_BSRR_BS0_Msk
10209 #define GPIO_BSRR_BS1_Pos (1U)
10210 #define GPIO_BSRR_BS1_Msk (0x1UL << GPIO_BSRR_BS1_Pos) /*!< 0x00000002 */
10211 #define GPIO_BSRR_BS1 GPIO_BSRR_BS1_Msk
10212 #define GPIO_BSRR_BS2_Pos (2U)
10213 #define GPIO_BSRR_BS2_Msk (0x1UL << GPIO_BSRR_BS2_Pos) /*!< 0x00000004 */
10214 #define GPIO_BSRR_BS2 GPIO_BSRR_BS2_Msk
10215 #define GPIO_BSRR_BS3_Pos (3U)
10216 #define GPIO_BSRR_BS3_Msk (0x1UL << GPIO_BSRR_BS3_Pos) /*!< 0x00000008 */
10217 #define GPIO_BSRR_BS3 GPIO_BSRR_BS3_Msk
10218 #define GPIO_BSRR_BS4_Pos (4U)
10219 #define GPIO_BSRR_BS4_Msk (0x1UL << GPIO_BSRR_BS4_Pos) /*!< 0x00000010 */
10220 #define GPIO_BSRR_BS4 GPIO_BSRR_BS4_Msk
10221 #define GPIO_BSRR_BS5_Pos (5U)
10222 #define GPIO_BSRR_BS5_Msk (0x1UL << GPIO_BSRR_BS5_Pos) /*!< 0x00000020 */
10223 #define GPIO_BSRR_BS5 GPIO_BSRR_BS5_Msk
10224 #define GPIO_BSRR_BS6_Pos (6U)
10225 #define GPIO_BSRR_BS6_Msk (0x1UL << GPIO_BSRR_BS6_Pos) /*!< 0x00000040 */
10226 #define GPIO_BSRR_BS6 GPIO_BSRR_BS6_Msk
10227 #define GPIO_BSRR_BS7_Pos (7U)
10228 #define GPIO_BSRR_BS7_Msk (0x1UL << GPIO_BSRR_BS7_Pos) /*!< 0x00000080 */
10229 #define GPIO_BSRR_BS7 GPIO_BSRR_BS7_Msk
10230 #define GPIO_BSRR_BS8_Pos (8U)
10231 #define GPIO_BSRR_BS8_Msk (0x1UL << GPIO_BSRR_BS8_Pos) /*!< 0x00000100 */
10232 #define GPIO_BSRR_BS8 GPIO_BSRR_BS8_Msk
10233 #define GPIO_BSRR_BS9_Pos (9U)
10234 #define GPIO_BSRR_BS9_Msk (0x1UL << GPIO_BSRR_BS9_Pos) /*!< 0x00000200 */
10235 #define GPIO_BSRR_BS9 GPIO_BSRR_BS9_Msk
10236 #define GPIO_BSRR_BS10_Pos (10U)
10237 #define GPIO_BSRR_BS10_Msk (0x1UL << GPIO_BSRR_BS10_Pos) /*!< 0x00000400 */
10238 #define GPIO_BSRR_BS10 GPIO_BSRR_BS10_Msk
10239 #define GPIO_BSRR_BS11_Pos (11U)
10240 #define GPIO_BSRR_BS11_Msk (0x1UL << GPIO_BSRR_BS11_Pos) /*!< 0x00000800 */
10241 #define GPIO_BSRR_BS11 GPIO_BSRR_BS11_Msk
10242 #define GPIO_BSRR_BS12_Pos (12U)
10243 #define GPIO_BSRR_BS12_Msk (0x1UL << GPIO_BSRR_BS12_Pos) /*!< 0x00001000 */
10244 #define GPIO_BSRR_BS12 GPIO_BSRR_BS12_Msk
10245 #define GPIO_BSRR_BS13_Pos (13U)
10246 #define GPIO_BSRR_BS13_Msk (0x1UL << GPIO_BSRR_BS13_Pos) /*!< 0x00002000 */
10247 #define GPIO_BSRR_BS13 GPIO_BSRR_BS13_Msk
10248 #define GPIO_BSRR_BS14_Pos (14U)
10249 #define GPIO_BSRR_BS14_Msk (0x1UL << GPIO_BSRR_BS14_Pos) /*!< 0x00004000 */
10250 #define GPIO_BSRR_BS14 GPIO_BSRR_BS14_Msk
10251 #define GPIO_BSRR_BS15_Pos (15U)
10252 #define GPIO_BSRR_BS15_Msk (0x1UL << GPIO_BSRR_BS15_Pos) /*!< 0x00008000 */
10253 #define GPIO_BSRR_BS15 GPIO_BSRR_BS15_Msk
10254 #define GPIO_BSRR_BR0_Pos (16U)
10255 #define GPIO_BSRR_BR0_Msk (0x1UL << GPIO_BSRR_BR0_Pos) /*!< 0x00010000 */
10256 #define GPIO_BSRR_BR0 GPIO_BSRR_BR0_Msk
10257 #define GPIO_BSRR_BR1_Pos (17U)
10258 #define GPIO_BSRR_BR1_Msk (0x1UL << GPIO_BSRR_BR1_Pos) /*!< 0x00020000 */
10259 #define GPIO_BSRR_BR1 GPIO_BSRR_BR1_Msk
10260 #define GPIO_BSRR_BR2_Pos (18U)
10261 #define GPIO_BSRR_BR2_Msk (0x1UL << GPIO_BSRR_BR2_Pos) /*!< 0x00040000 */
10262 #define GPIO_BSRR_BR2 GPIO_BSRR_BR2_Msk
10263 #define GPIO_BSRR_BR3_Pos (19U)
10264 #define GPIO_BSRR_BR3_Msk (0x1UL << GPIO_BSRR_BR3_Pos) /*!< 0x00080000 */
10265 #define GPIO_BSRR_BR3 GPIO_BSRR_BR3_Msk
10266 #define GPIO_BSRR_BR4_Pos (20U)
10267 #define GPIO_BSRR_BR4_Msk (0x1UL << GPIO_BSRR_BR4_Pos) /*!< 0x00100000 */
10268 #define GPIO_BSRR_BR4 GPIO_BSRR_BR4_Msk
10269 #define GPIO_BSRR_BR5_Pos (21U)
10270 #define GPIO_BSRR_BR5_Msk (0x1UL << GPIO_BSRR_BR5_Pos) /*!< 0x00200000 */
10271 #define GPIO_BSRR_BR5 GPIO_BSRR_BR5_Msk
10272 #define GPIO_BSRR_BR6_Pos (22U)
10273 #define GPIO_BSRR_BR6_Msk (0x1UL << GPIO_BSRR_BR6_Pos) /*!< 0x00400000 */
10274 #define GPIO_BSRR_BR6 GPIO_BSRR_BR6_Msk
10275 #define GPIO_BSRR_BR7_Pos (23U)
10276 #define GPIO_BSRR_BR7_Msk (0x1UL << GPIO_BSRR_BR7_Pos) /*!< 0x00800000 */
10277 #define GPIO_BSRR_BR7 GPIO_BSRR_BR7_Msk
10278 #define GPIO_BSRR_BR8_Pos (24U)
10279 #define GPIO_BSRR_BR8_Msk (0x1UL << GPIO_BSRR_BR8_Pos) /*!< 0x01000000 */
10280 #define GPIO_BSRR_BR8 GPIO_BSRR_BR8_Msk
10281 #define GPIO_BSRR_BR9_Pos (25U)
10282 #define GPIO_BSRR_BR9_Msk (0x1UL << GPIO_BSRR_BR9_Pos) /*!< 0x02000000 */
10283 #define GPIO_BSRR_BR9 GPIO_BSRR_BR9_Msk
10284 #define GPIO_BSRR_BR10_Pos (26U)
10285 #define GPIO_BSRR_BR10_Msk (0x1UL << GPIO_BSRR_BR10_Pos) /*!< 0x04000000 */
10286 #define GPIO_BSRR_BR10 GPIO_BSRR_BR10_Msk
10287 #define GPIO_BSRR_BR11_Pos (27U)
10288 #define GPIO_BSRR_BR11_Msk (0x1UL << GPIO_BSRR_BR11_Pos) /*!< 0x08000000 */
10289 #define GPIO_BSRR_BR11 GPIO_BSRR_BR11_Msk
10290 #define GPIO_BSRR_BR12_Pos (28U)
10291 #define GPIO_BSRR_BR12_Msk (0x1UL << GPIO_BSRR_BR12_Pos) /*!< 0x10000000 */
10292 #define GPIO_BSRR_BR12 GPIO_BSRR_BR12_Msk
10293 #define GPIO_BSRR_BR13_Pos (29U)
10294 #define GPIO_BSRR_BR13_Msk (0x1UL << GPIO_BSRR_BR13_Pos) /*!< 0x20000000 */
10295 #define GPIO_BSRR_BR13 GPIO_BSRR_BR13_Msk
10296 #define GPIO_BSRR_BR14_Pos (30U)
10297 #define GPIO_BSRR_BR14_Msk (0x1UL << GPIO_BSRR_BR14_Pos) /*!< 0x40000000 */
10298 #define GPIO_BSRR_BR14 GPIO_BSRR_BR14_Msk
10299 #define GPIO_BSRR_BR15_Pos (31U)
10300 #define GPIO_BSRR_BR15_Msk (0x1UL << GPIO_BSRR_BR15_Pos) /*!< 0x80000000 */
10301 #define GPIO_BSRR_BR15 GPIO_BSRR_BR15_Msk
10302
10303 /****************** Bit definition for GPIO_LCKR register *********************/
10304 #define GPIO_LCKR_LCK0_Pos (0U)
10305 #define GPIO_LCKR_LCK0_Msk (0x1UL << GPIO_LCKR_LCK0_Pos) /*!< 0x00000001 */
10306 #define GPIO_LCKR_LCK0 GPIO_LCKR_LCK0_Msk
10307 #define GPIO_LCKR_LCK1_Pos (1U)
10308 #define GPIO_LCKR_LCK1_Msk (0x1UL << GPIO_LCKR_LCK1_Pos) /*!< 0x00000002 */
10309 #define GPIO_LCKR_LCK1 GPIO_LCKR_LCK1_Msk
10310 #define GPIO_LCKR_LCK2_Pos (2U)
10311 #define GPIO_LCKR_LCK2_Msk (0x1UL << GPIO_LCKR_LCK2_Pos) /*!< 0x00000004 */
10312 #define GPIO_LCKR_LCK2 GPIO_LCKR_LCK2_Msk
10313 #define GPIO_LCKR_LCK3_Pos (3U)
10314 #define GPIO_LCKR_LCK3_Msk (0x1UL << GPIO_LCKR_LCK3_Pos) /*!< 0x00000008 */
10315 #define GPIO_LCKR_LCK3 GPIO_LCKR_LCK3_Msk
10316 #define GPIO_LCKR_LCK4_Pos (4U)
10317 #define GPIO_LCKR_LCK4_Msk (0x1UL << GPIO_LCKR_LCK4_Pos) /*!< 0x00000010 */
10318 #define GPIO_LCKR_LCK4 GPIO_LCKR_LCK4_Msk
10319 #define GPIO_LCKR_LCK5_Pos (5U)
10320 #define GPIO_LCKR_LCK5_Msk (0x1UL << GPIO_LCKR_LCK5_Pos) /*!< 0x00000020 */
10321 #define GPIO_LCKR_LCK5 GPIO_LCKR_LCK5_Msk
10322 #define GPIO_LCKR_LCK6_Pos (6U)
10323 #define GPIO_LCKR_LCK6_Msk (0x1UL << GPIO_LCKR_LCK6_Pos) /*!< 0x00000040 */
10324 #define GPIO_LCKR_LCK6 GPIO_LCKR_LCK6_Msk
10325 #define GPIO_LCKR_LCK7_Pos (7U)
10326 #define GPIO_LCKR_LCK7_Msk (0x1UL << GPIO_LCKR_LCK7_Pos) /*!< 0x00000080 */
10327 #define GPIO_LCKR_LCK7 GPIO_LCKR_LCK7_Msk
10328 #define GPIO_LCKR_LCK8_Pos (8U)
10329 #define GPIO_LCKR_LCK8_Msk (0x1UL << GPIO_LCKR_LCK8_Pos) /*!< 0x00000100 */
10330 #define GPIO_LCKR_LCK8 GPIO_LCKR_LCK8_Msk
10331 #define GPIO_LCKR_LCK9_Pos (9U)
10332 #define GPIO_LCKR_LCK9_Msk (0x1UL << GPIO_LCKR_LCK9_Pos) /*!< 0x00000200 */
10333 #define GPIO_LCKR_LCK9 GPIO_LCKR_LCK9_Msk
10334 #define GPIO_LCKR_LCK10_Pos (10U)
10335 #define GPIO_LCKR_LCK10_Msk (0x1UL << GPIO_LCKR_LCK10_Pos) /*!< 0x00000400 */
10336 #define GPIO_LCKR_LCK10 GPIO_LCKR_LCK10_Msk
10337 #define GPIO_LCKR_LCK11_Pos (11U)
10338 #define GPIO_LCKR_LCK11_Msk (0x1UL << GPIO_LCKR_LCK11_Pos) /*!< 0x00000800 */
10339 #define GPIO_LCKR_LCK11 GPIO_LCKR_LCK11_Msk
10340 #define GPIO_LCKR_LCK12_Pos (12U)
10341 #define GPIO_LCKR_LCK12_Msk (0x1UL << GPIO_LCKR_LCK12_Pos) /*!< 0x00001000 */
10342 #define GPIO_LCKR_LCK12 GPIO_LCKR_LCK12_Msk
10343 #define GPIO_LCKR_LCK13_Pos (13U)
10344 #define GPIO_LCKR_LCK13_Msk (0x1UL << GPIO_LCKR_LCK13_Pos) /*!< 0x00002000 */
10345 #define GPIO_LCKR_LCK13 GPIO_LCKR_LCK13_Msk
10346 #define GPIO_LCKR_LCK14_Pos (14U)
10347 #define GPIO_LCKR_LCK14_Msk (0x1UL << GPIO_LCKR_LCK14_Pos) /*!< 0x00004000 */
10348 #define GPIO_LCKR_LCK14 GPIO_LCKR_LCK14_Msk
10349 #define GPIO_LCKR_LCK15_Pos (15U)
10350 #define GPIO_LCKR_LCK15_Msk (0x1UL << GPIO_LCKR_LCK15_Pos) /*!< 0x00008000 */
10351 #define GPIO_LCKR_LCK15 GPIO_LCKR_LCK15_Msk
10352 #define GPIO_LCKR_LCKK_Pos (16U)
10353 #define GPIO_LCKR_LCKK_Msk (0x1UL << GPIO_LCKR_LCKK_Pos) /*!< 0x00010000 */
10354 #define GPIO_LCKR_LCKK GPIO_LCKR_LCKK_Msk
10355
10356 /****************** Bit definition for GPIO_AFRL register ********************/
10357 #define GPIO_AFRL_AFSEL0_Pos (0U)
10358 #define GPIO_AFRL_AFSEL0_Msk (0xFUL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x0000000F */
10359 #define GPIO_AFRL_AFSEL0 GPIO_AFRL_AFSEL0_Msk
10360 #define GPIO_AFRL_AFSEL0_0 (0x1UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000001 */
10361 #define GPIO_AFRL_AFSEL0_1 (0x2UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000002 */
10362 #define GPIO_AFRL_AFSEL0_2 (0x4UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000004 */
10363 #define GPIO_AFRL_AFSEL0_3 (0x8UL << GPIO_AFRL_AFSEL0_Pos) /*!< 0x00000008 */
10364 #define GPIO_AFRL_AFSEL1_Pos (4U)
10365 #define GPIO_AFRL_AFSEL1_Msk (0xFUL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x000000F0 */
10366 #define GPIO_AFRL_AFSEL1 GPIO_AFRL_AFSEL1_Msk
10367 #define GPIO_AFRL_AFSEL1_0 (0x1UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000010 */
10368 #define GPIO_AFRL_AFSEL1_1 (0x2UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000020 */
10369 #define GPIO_AFRL_AFSEL1_2 (0x4UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000040 */
10370 #define GPIO_AFRL_AFSEL1_3 (0x8UL << GPIO_AFRL_AFSEL1_Pos) /*!< 0x00000080 */
10371 #define GPIO_AFRL_AFSEL2_Pos (8U)
10372 #define GPIO_AFRL_AFSEL2_Msk (0xFUL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000F00 */
10373 #define GPIO_AFRL_AFSEL2 GPIO_AFRL_AFSEL2_Msk
10374 #define GPIO_AFRL_AFSEL2_0 (0x1UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000100 */
10375 #define GPIO_AFRL_AFSEL2_1 (0x2UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000200 */
10376 #define GPIO_AFRL_AFSEL2_2 (0x4UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000400 */
10377 #define GPIO_AFRL_AFSEL2_3 (0x8UL << GPIO_AFRL_AFSEL2_Pos) /*!< 0x00000800 */
10378 #define GPIO_AFRL_AFSEL3_Pos (12U)
10379 #define GPIO_AFRL_AFSEL3_Msk (0xFUL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x0000F000 */
10380 #define GPIO_AFRL_AFSEL3 GPIO_AFRL_AFSEL3_Msk
10381 #define GPIO_AFRL_AFSEL3_0 (0x1UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00001000 */
10382 #define GPIO_AFRL_AFSEL3_1 (0x2UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00002000 */
10383 #define GPIO_AFRL_AFSEL3_2 (0x4UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00004000 */
10384 #define GPIO_AFRL_AFSEL3_3 (0x8UL << GPIO_AFRL_AFSEL3_Pos) /*!< 0x00008000 */
10385 #define GPIO_AFRL_AFSEL4_Pos (16U)
10386 #define GPIO_AFRL_AFSEL4_Msk (0xFUL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x000F0000 */
10387 #define GPIO_AFRL_AFSEL4 GPIO_AFRL_AFSEL4_Msk
10388 #define GPIO_AFRL_AFSEL4_0 (0x1UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00010000 */
10389 #define GPIO_AFRL_AFSEL4_1 (0x2UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00020000 */
10390 #define GPIO_AFRL_AFSEL4_2 (0x4UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00040000 */
10391 #define GPIO_AFRL_AFSEL4_3 (0x8UL << GPIO_AFRL_AFSEL4_Pos) /*!< 0x00080000 */
10392 #define GPIO_AFRL_AFSEL5_Pos (20U)
10393 #define GPIO_AFRL_AFSEL5_Msk (0xFUL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00F00000 */
10394 #define GPIO_AFRL_AFSEL5 GPIO_AFRL_AFSEL5_Msk
10395 #define GPIO_AFRL_AFSEL5_0 (0x1UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00100000 */
10396 #define GPIO_AFRL_AFSEL5_1 (0x2UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00200000 */
10397 #define GPIO_AFRL_AFSEL5_2 (0x4UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00400000 */
10398 #define GPIO_AFRL_AFSEL5_3 (0x8UL << GPIO_AFRL_AFSEL5_Pos) /*!< 0x00800000 */
10399 #define GPIO_AFRL_AFSEL6_Pos (24U)
10400 #define GPIO_AFRL_AFSEL6_Msk (0xFUL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x0F000000 */
10401 #define GPIO_AFRL_AFSEL6 GPIO_AFRL_AFSEL6_Msk
10402 #define GPIO_AFRL_AFSEL6_0 (0x1UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x01000000 */
10403 #define GPIO_AFRL_AFSEL6_1 (0x2UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x02000000 */
10404 #define GPIO_AFRL_AFSEL6_2 (0x4UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x04000000 */
10405 #define GPIO_AFRL_AFSEL6_3 (0x8UL << GPIO_AFRL_AFSEL6_Pos) /*!< 0x08000000 */
10406 #define GPIO_AFRL_AFSEL7_Pos (28U)
10407 #define GPIO_AFRL_AFSEL7_Msk (0xFUL << GPIO_AFRL_AFSEL7_Pos) /*!< 0xF0000000 */
10408 #define GPIO_AFRL_AFSEL7 GPIO_AFRL_AFSEL7_Msk
10409 #define GPIO_AFRL_AFSEL7_0 (0x1UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x10000000 */
10410 #define GPIO_AFRL_AFSEL7_1 (0x2UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x20000000 */
10411 #define GPIO_AFRL_AFSEL7_2 (0x4UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x40000000 */
10412 #define GPIO_AFRL_AFSEL7_3 (0x8UL << GPIO_AFRL_AFSEL7_Pos) /*!< 0x80000000 */
10413
10414 /* Legacy defines */
10415 #define GPIO_AFRL_AFRL0 GPIO_AFRL_AFSEL0
10416 #define GPIO_AFRL_AFRL1 GPIO_AFRL_AFSEL1
10417 #define GPIO_AFRL_AFRL2 GPIO_AFRL_AFSEL2
10418 #define GPIO_AFRL_AFRL3 GPIO_AFRL_AFSEL3
10419 #define GPIO_AFRL_AFRL4 GPIO_AFRL_AFSEL4
10420 #define GPIO_AFRL_AFRL5 GPIO_AFRL_AFSEL5
10421 #define GPIO_AFRL_AFRL6 GPIO_AFRL_AFSEL6
10422 #define GPIO_AFRL_AFRL7 GPIO_AFRL_AFSEL7
10423
10424 /****************** Bit definition for GPIO_AFRH register ********************/
10425 #define GPIO_AFRH_AFSEL8_Pos (0U)
10426 #define GPIO_AFRH_AFSEL8_Msk (0xFUL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x0000000F */
10427 #define GPIO_AFRH_AFSEL8 GPIO_AFRH_AFSEL8_Msk
10428 #define GPIO_AFRH_AFSEL8_0 (0x1UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000001 */
10429 #define GPIO_AFRH_AFSEL8_1 (0x2UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000002 */
10430 #define GPIO_AFRH_AFSEL8_2 (0x4UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000004 */
10431 #define GPIO_AFRH_AFSEL8_3 (0x8UL << GPIO_AFRH_AFSEL8_Pos) /*!< 0x00000008 */
10432 #define GPIO_AFRH_AFSEL9_Pos (4U)
10433 #define GPIO_AFRH_AFSEL9_Msk (0xFUL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x000000F0 */
10434 #define GPIO_AFRH_AFSEL9 GPIO_AFRH_AFSEL9_Msk
10435 #define GPIO_AFRH_AFSEL9_0 (0x1UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000010 */
10436 #define GPIO_AFRH_AFSEL9_1 (0x2UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000020 */
10437 #define GPIO_AFRH_AFSEL9_2 (0x4UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000040 */
10438 #define GPIO_AFRH_AFSEL9_3 (0x8UL << GPIO_AFRH_AFSEL9_Pos) /*!< 0x00000080 */
10439 #define GPIO_AFRH_AFSEL10_Pos (8U)
10440 #define GPIO_AFRH_AFSEL10_Msk (0xFUL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000F00 */
10441 #define GPIO_AFRH_AFSEL10 GPIO_AFRH_AFSEL10_Msk
10442 #define GPIO_AFRH_AFSEL10_0 (0x1UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000100 */
10443 #define GPIO_AFRH_AFSEL10_1 (0x2UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000200 */
10444 #define GPIO_AFRH_AFSEL10_2 (0x4UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000400 */
10445 #define GPIO_AFRH_AFSEL10_3 (0x8UL << GPIO_AFRH_AFSEL10_Pos) /*!< 0x00000800 */
10446 #define GPIO_AFRH_AFSEL11_Pos (12U)
10447 #define GPIO_AFRH_AFSEL11_Msk (0xFUL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x0000F000 */
10448 #define GPIO_AFRH_AFSEL11 GPIO_AFRH_AFSEL11_Msk
10449 #define GPIO_AFRH_AFSEL11_0 (0x1UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00001000 */
10450 #define GPIO_AFRH_AFSEL11_1 (0x2UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00002000 */
10451 #define GPIO_AFRH_AFSEL11_2 (0x4UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00004000 */
10452 #define GPIO_AFRH_AFSEL11_3 (0x8UL << GPIO_AFRH_AFSEL11_Pos) /*!< 0x00008000 */
10453 #define GPIO_AFRH_AFSEL12_Pos (16U)
10454 #define GPIO_AFRH_AFSEL12_Msk (0xFUL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x000F0000 */
10455 #define GPIO_AFRH_AFSEL12 GPIO_AFRH_AFSEL12_Msk
10456 #define GPIO_AFRH_AFSEL12_0 (0x1UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00010000 */
10457 #define GPIO_AFRH_AFSEL12_1 (0x2UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00020000 */
10458 #define GPIO_AFRH_AFSEL12_2 (0x4UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00040000 */
10459 #define GPIO_AFRH_AFSEL12_3 (0x8UL << GPIO_AFRH_AFSEL12_Pos) /*!< 0x00080000 */
10460 #define GPIO_AFRH_AFSEL13_Pos (20U)
10461 #define GPIO_AFRH_AFSEL13_Msk (0xFUL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00F00000 */
10462 #define GPIO_AFRH_AFSEL13 GPIO_AFRH_AFSEL13_Msk
10463 #define GPIO_AFRH_AFSEL13_0 (0x1UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00100000 */
10464 #define GPIO_AFRH_AFSEL13_1 (0x2UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00200000 */
10465 #define GPIO_AFRH_AFSEL13_2 (0x4UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00400000 */
10466 #define GPIO_AFRH_AFSEL13_3 (0x8UL << GPIO_AFRH_AFSEL13_Pos) /*!< 0x00800000 */
10467 #define GPIO_AFRH_AFSEL14_Pos (24U)
10468 #define GPIO_AFRH_AFSEL14_Msk (0xFUL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x0F000000 */
10469 #define GPIO_AFRH_AFSEL14 GPIO_AFRH_AFSEL14_Msk
10470 #define GPIO_AFRH_AFSEL14_0 (0x1UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x01000000 */
10471 #define GPIO_AFRH_AFSEL14_1 (0x2UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x02000000 */
10472 #define GPIO_AFRH_AFSEL14_2 (0x4UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x04000000 */
10473 #define GPIO_AFRH_AFSEL14_3 (0x8UL << GPIO_AFRH_AFSEL14_Pos) /*!< 0x08000000 */
10474 #define GPIO_AFRH_AFSEL15_Pos (28U)
10475 #define GPIO_AFRH_AFSEL15_Msk (0xFUL << GPIO_AFRH_AFSEL15_Pos) /*!< 0xF0000000 */
10476 #define GPIO_AFRH_AFSEL15 GPIO_AFRH_AFSEL15_Msk
10477 #define GPIO_AFRH_AFSEL15_0 (0x1UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x10000000 */
10478 #define GPIO_AFRH_AFSEL15_1 (0x2UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x20000000 */
10479 #define GPIO_AFRH_AFSEL15_2 (0x4UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x40000000 */
10480 #define GPIO_AFRH_AFSEL15_3 (0x8UL << GPIO_AFRH_AFSEL15_Pos) /*!< 0x80000000 */
10481
10482 /* Legacy defines */
10483 #define GPIO_AFRH_AFRH0 GPIO_AFRH_AFSEL8
10484 #define GPIO_AFRH_AFRH1 GPIO_AFRH_AFSEL9
10485 #define GPIO_AFRH_AFRH2 GPIO_AFRH_AFSEL10
10486 #define GPIO_AFRH_AFRH3 GPIO_AFRH_AFSEL11
10487 #define GPIO_AFRH_AFRH4 GPIO_AFRH_AFSEL12
10488 #define GPIO_AFRH_AFRH5 GPIO_AFRH_AFSEL13
10489 #define GPIO_AFRH_AFRH6 GPIO_AFRH_AFSEL14
10490 #define GPIO_AFRH_AFRH7 GPIO_AFRH_AFSEL15
10491
10492 /******************************************************************************/
10493 /* */
10494 /* HSEM HW Semaphore */
10495 /* */
10496 /******************************************************************************/
10497 /******************** Bit definition for HSEM_R register ********************/
10498 #define HSEM_R_PROCID_Pos (0U)
10499 #define HSEM_R_PROCID_Msk (0xFFUL << HSEM_R_PROCID_Pos) /*!< 0x000000FF */
10500 #define HSEM_R_PROCID HSEM_R_PROCID_Msk /*!<Semaphore ProcessID */
10501 #define HSEM_R_COREID_Pos (8U)
10502 #define HSEM_R_COREID_Msk (0xFFUL << HSEM_R_COREID_Pos) /*!< 0x0000FF00 */
10503 #define HSEM_R_COREID HSEM_R_COREID_Msk /*!<Semaphore CoreID. */
10504 #define HSEM_R_LOCK_Pos (31U)
10505 #define HSEM_R_LOCK_Msk (0x1UL << HSEM_R_LOCK_Pos) /*!< 0x80000000 */
10506 #define HSEM_R_LOCK HSEM_R_LOCK_Msk /*!<Lock indication. */
10507
10508 /******************** Bit definition for HSEM_RLR register ******************/
10509 #define HSEM_RLR_PROCID_Pos (0U)
10510 #define HSEM_RLR_PROCID_Msk (0xFFUL << HSEM_RLR_PROCID_Pos) /*!< 0x000000FF */
10511 #define HSEM_RLR_PROCID HSEM_RLR_PROCID_Msk /*!<Semaphore ProcessID */
10512 #define HSEM_RLR_COREID_Pos (8U)
10513 #define HSEM_RLR_COREID_Msk (0xFFUL << HSEM_RLR_COREID_Pos) /*!< 0x0000FF00 */
10514 #define HSEM_RLR_COREID HSEM_RLR_COREID_Msk /*!<Semaphore CoreID. */
10515 #define HSEM_RLR_LOCK_Pos (31U)
10516 #define HSEM_RLR_LOCK_Msk (0x1UL << HSEM_RLR_LOCK_Pos) /*!< 0x80000000 */
10517 #define HSEM_RLR_LOCK HSEM_RLR_LOCK_Msk /*!<Lock indication. */
10518
10519 /******************** Bit definition for HSEM_C1IER register *****************/
10520 #define HSEM_C1IER_ISE0_Pos (0U)
10521 #define HSEM_C1IER_ISE0_Msk (0x1UL << HSEM_C1IER_ISE0_Pos) /*!< 0x00000001 */
10522 #define HSEM_C1IER_ISE0 HSEM_C1IER_ISE0_Msk /*!<semaphore 0 , interrupt 0 enable bit. */
10523 #define HSEM_C1IER_ISE1_Pos (1U)
10524 #define HSEM_C1IER_ISE1_Msk (0x1UL << HSEM_C1IER_ISE1_Pos) /*!< 0x00000002 */
10525 #define HSEM_C1IER_ISE1 HSEM_C1IER_ISE1_Msk /*!<semaphore 1 , interrupt 0 enable bit. */
10526 #define HSEM_C1IER_ISE2_Pos (2U)
10527 #define HSEM_C1IER_ISE2_Msk (0x1UL << HSEM_C1IER_ISE2_Pos) /*!< 0x00000004 */
10528 #define HSEM_C1IER_ISE2 HSEM_C1IER_ISE2_Msk /*!<semaphore 2 , interrupt 0 enable bit. */
10529 #define HSEM_C1IER_ISE3_Pos (3U)
10530 #define HSEM_C1IER_ISE3_Msk (0x1UL << HSEM_C1IER_ISE3_Pos) /*!< 0x00000008 */
10531 #define HSEM_C1IER_ISE3 HSEM_C1IER_ISE3_Msk /*!<semaphore 3 , interrupt 0 enable bit. */
10532 #define HSEM_C1IER_ISE4_Pos (4U)
10533 #define HSEM_C1IER_ISE4_Msk (0x1UL << HSEM_C1IER_ISE4_Pos) /*!< 0x00000010 */
10534 #define HSEM_C1IER_ISE4 HSEM_C1IER_ISE4_Msk /*!<semaphore 4 , interrupt 0 enable bit. */
10535 #define HSEM_C1IER_ISE5_Pos (5U)
10536 #define HSEM_C1IER_ISE5_Msk (0x1UL << HSEM_C1IER_ISE5_Pos) /*!< 0x00000020 */
10537 #define HSEM_C1IER_ISE5 HSEM_C1IER_ISE5_Msk /*!<semaphore 5 interrupt 0 enable bit. */
10538 #define HSEM_C1IER_ISE6_Pos (6U)
10539 #define HSEM_C1IER_ISE6_Msk (0x1UL << HSEM_C1IER_ISE6_Pos) /*!< 0x00000040 */
10540 #define HSEM_C1IER_ISE6 HSEM_C1IER_ISE6_Msk /*!<semaphore 6 interrupt 0 enable bit. */
10541 #define HSEM_C1IER_ISE7_Pos (7U)
10542 #define HSEM_C1IER_ISE7_Msk (0x1UL << HSEM_C1IER_ISE7_Pos) /*!< 0x00000080 */
10543 #define HSEM_C1IER_ISE7 HSEM_C1IER_ISE7_Msk /*!<semaphore 7 interrupt 0 enable bit. */
10544 #define HSEM_C1IER_ISE8_Pos (8U)
10545 #define HSEM_C1IER_ISE8_Msk (0x1UL << HSEM_C1IER_ISE8_Pos) /*!< 0x00000100 */
10546 #define HSEM_C1IER_ISE8 HSEM_C1IER_ISE8_Msk /*!<semaphore 8 interrupt 0 enable bit. */
10547 #define HSEM_C1IER_ISE9_Pos (9U)
10548 #define HSEM_C1IER_ISE9_Msk (0x1UL << HSEM_C1IER_ISE9_Pos) /*!< 0x00000200 */
10549 #define HSEM_C1IER_ISE9 HSEM_C1IER_ISE9_Msk /*!<semaphore 9 interrupt 0 enable bit. */
10550 #define HSEM_C1IER_ISE10_Pos (10U)
10551 #define HSEM_C1IER_ISE10_Msk (0x1UL << HSEM_C1IER_ISE10_Pos) /*!< 0x00000400 */
10552 #define HSEM_C1IER_ISE10 HSEM_C1IER_ISE10_Msk /*!<semaphore 10 interrupt 0 enable bit. */
10553 #define HSEM_C1IER_ISE11_Pos (11U)
10554 #define HSEM_C1IER_ISE11_Msk (0x1UL << HSEM_C1IER_ISE11_Pos) /*!< 0x00000800 */
10555 #define HSEM_C1IER_ISE11 HSEM_C1IER_ISE11_Msk /*!<semaphore 11 interrupt 0 enable bit. */
10556 #define HSEM_C1IER_ISE12_Pos (12U)
10557 #define HSEM_C1IER_ISE12_Msk (0x1UL << HSEM_C1IER_ISE12_Pos) /*!< 0x00001000 */
10558 #define HSEM_C1IER_ISE12 HSEM_C1IER_ISE12_Msk /*!<semaphore 12 interrupt 0 enable bit. */
10559 #define HSEM_C1IER_ISE13_Pos (13U)
10560 #define HSEM_C1IER_ISE13_Msk (0x1UL << HSEM_C1IER_ISE13_Pos) /*!< 0x00002000 */
10561 #define HSEM_C1IER_ISE13 HSEM_C1IER_ISE13_Msk /*!<semaphore 13 interrupt 0 enable bit. */
10562 #define HSEM_C1IER_ISE14_Pos (14U)
10563 #define HSEM_C1IER_ISE14_Msk (0x1UL << HSEM_C1IER_ISE14_Pos) /*!< 0x00004000 */
10564 #define HSEM_C1IER_ISE14 HSEM_C1IER_ISE14_Msk /*!<semaphore 14 interrupt 0 enable bit. */
10565 #define HSEM_C1IER_ISE15_Pos (15U)
10566 #define HSEM_C1IER_ISE15_Msk (0x1UL << HSEM_C1IER_ISE15_Pos) /*!< 0x00008000 */
10567 #define HSEM_C1IER_ISE15 HSEM_C1IER_ISE15_Msk /*!<semaphore 15 interrupt 0 enable bit. */
10568 #define HSEM_C1IER_ISE16_Pos (16U)
10569 #define HSEM_C1IER_ISE16_Msk (0x1UL << HSEM_C1IER_ISE16_Pos) /*!< 0x00010000 */
10570 #define HSEM_C1IER_ISE16 HSEM_C1IER_ISE16_Msk /*!<semaphore 16 interrupt 0 enable bit. */
10571 #define HSEM_C1IER_ISE17_Pos (17U)
10572 #define HSEM_C1IER_ISE17_Msk (0x1UL << HSEM_C1IER_ISE17_Pos) /*!< 0x00020000 */
10573 #define HSEM_C1IER_ISE17 HSEM_C1IER_ISE17_Msk /*!<semaphore 17 interrupt 0 enable bit. */
10574 #define HSEM_C1IER_ISE18_Pos (18U)
10575 #define HSEM_C1IER_ISE18_Msk (0x1UL << HSEM_C1IER_ISE18_Pos) /*!< 0x00040000 */
10576 #define HSEM_C1IER_ISE18 HSEM_C1IER_ISE18_Msk /*!<semaphore 18 interrupt 0 enable bit. */
10577 #define HSEM_C1IER_ISE19_Pos (19U)
10578 #define HSEM_C1IER_ISE19_Msk (0x1UL << HSEM_C1IER_ISE19_Pos) /*!< 0x00080000 */
10579 #define HSEM_C1IER_ISE19 HSEM_C1IER_ISE19_Msk /*!<semaphore 19 interrupt 0 enable bit. */
10580 #define HSEM_C1IER_ISE20_Pos (20U)
10581 #define HSEM_C1IER_ISE20_Msk (0x1UL << HSEM_C1IER_ISE20_Pos) /*!< 0x00100000 */
10582 #define HSEM_C1IER_ISE20 HSEM_C1IER_ISE20_Msk /*!<semaphore 20 interrupt 0 enable bit. */
10583 #define HSEM_C1IER_ISE21_Pos (21U)
10584 #define HSEM_C1IER_ISE21_Msk (0x1UL << HSEM_C1IER_ISE21_Pos) /*!< 0x00200000 */
10585 #define HSEM_C1IER_ISE21 HSEM_C1IER_ISE21_Msk /*!<semaphore 21 interrupt 0 enable bit. */
10586 #define HSEM_C1IER_ISE22_Pos (22U)
10587 #define HSEM_C1IER_ISE22_Msk (0x1UL << HSEM_C1IER_ISE22_Pos) /*!< 0x00400000 */
10588 #define HSEM_C1IER_ISE22 HSEM_C1IER_ISE22_Msk /*!<semaphore 22 interrupt 0 enable bit. */
10589 #define HSEM_C1IER_ISE23_Pos (23U)
10590 #define HSEM_C1IER_ISE23_Msk (0x1UL << HSEM_C1IER_ISE23_Pos) /*!< 0x00800000 */
10591 #define HSEM_C1IER_ISE23 HSEM_C1IER_ISE23_Msk /*!<semaphore 23 interrupt 0 enable bit. */
10592 #define HSEM_C1IER_ISE24_Pos (24U)
10593 #define HSEM_C1IER_ISE24_Msk (0x1UL << HSEM_C1IER_ISE24_Pos) /*!< 0x01000000 */
10594 #define HSEM_C1IER_ISE24 HSEM_C1IER_ISE24_Msk /*!<semaphore 24 interrupt 0 enable bit. */
10595 #define HSEM_C1IER_ISE25_Pos (25U)
10596 #define HSEM_C1IER_ISE25_Msk (0x1UL << HSEM_C1IER_ISE25_Pos) /*!< 0x02000000 */
10597 #define HSEM_C1IER_ISE25 HSEM_C1IER_ISE25_Msk /*!<semaphore 25 interrupt 0 enable bit. */
10598 #define HSEM_C1IER_ISE26_Pos (26U)
10599 #define HSEM_C1IER_ISE26_Msk (0x1UL << HSEM_C1IER_ISE26_Pos) /*!< 0x04000000 */
10600 #define HSEM_C1IER_ISE26 HSEM_C1IER_ISE26_Msk /*!<semaphore 26 interrupt 0 enable bit. */
10601 #define HSEM_C1IER_ISE27_Pos (27U)
10602 #define HSEM_C1IER_ISE27_Msk (0x1UL << HSEM_C1IER_ISE27_Pos) /*!< 0x08000000 */
10603 #define HSEM_C1IER_ISE27 HSEM_C1IER_ISE27_Msk /*!<semaphore 27 interrupt 0 enable bit. */
10604 #define HSEM_C1IER_ISE28_Pos (28U)
10605 #define HSEM_C1IER_ISE28_Msk (0x1UL << HSEM_C1IER_ISE28_Pos) /*!< 0x10000000 */
10606 #define HSEM_C1IER_ISE28 HSEM_C1IER_ISE28_Msk /*!<semaphore 28 interrupt 0 enable bit. */
10607 #define HSEM_C1IER_ISE29_Pos (29U)
10608 #define HSEM_C1IER_ISE29_Msk (0x1UL << HSEM_C1IER_ISE29_Pos) /*!< 0x20000000 */
10609 #define HSEM_C1IER_ISE29 HSEM_C1IER_ISE29_Msk /*!<semaphore 29 interrupt 0 enable bit. */
10610 #define HSEM_C1IER_ISE30_Pos (30U)
10611 #define HSEM_C1IER_ISE30_Msk (0x1UL << HSEM_C1IER_ISE30_Pos) /*!< 0x40000000 */
10612 #define HSEM_C1IER_ISE30 HSEM_C1IER_ISE30_Msk /*!<semaphore 30 interrupt 0 enable bit. */
10613 #define HSEM_C1IER_ISE31_Pos (31U)
10614 #define HSEM_C1IER_ISE31_Msk (0x1UL << HSEM_C1IER_ISE31_Pos) /*!< 0x80000000 */
10615 #define HSEM_C1IER_ISE31 HSEM_C1IER_ISE31_Msk /*!<semaphore 31 interrupt 0 enable bit. */
10616
10617 /******************** Bit definition for HSEM_C1ICR register *****************/
10618 #define HSEM_C1ICR_ISC0_Pos (0U)
10619 #define HSEM_C1ICR_ISC0_Msk (0x1UL << HSEM_C1ICR_ISC0_Pos) /*!< 0x00000001 */
10620 #define HSEM_C1ICR_ISC0 HSEM_C1ICR_ISC0_Msk /*!<semaphore 0 , interrupt 0 clear bit. */
10621 #define HSEM_C1ICR_ISC1_Pos (1U)
10622 #define HSEM_C1ICR_ISC1_Msk (0x1UL << HSEM_C1ICR_ISC1_Pos) /*!< 0x00000002 */
10623 #define HSEM_C1ICR_ISC1 HSEM_C1ICR_ISC1_Msk /*!<semaphore 1 , interrupt 0 clear bit. */
10624 #define HSEM_C1ICR_ISC2_Pos (2U)
10625 #define HSEM_C1ICR_ISC2_Msk (0x1UL << HSEM_C1ICR_ISC2_Pos) /*!< 0x00000004 */
10626 #define HSEM_C1ICR_ISC2 HSEM_C1ICR_ISC2_Msk /*!<semaphore 2 , interrupt 0 clear bit. */
10627 #define HSEM_C1ICR_ISC3_Pos (3U)
10628 #define HSEM_C1ICR_ISC3_Msk (0x1UL << HSEM_C1ICR_ISC3_Pos) /*!< 0x00000008 */
10629 #define HSEM_C1ICR_ISC3 HSEM_C1ICR_ISC3_Msk /*!<semaphore 3 , interrupt 0 clear bit. */
10630 #define HSEM_C1ICR_ISC4_Pos (4U)
10631 #define HSEM_C1ICR_ISC4_Msk (0x1UL << HSEM_C1ICR_ISC4_Pos) /*!< 0x00000010 */
10632 #define HSEM_C1ICR_ISC4 HSEM_C1ICR_ISC4_Msk /*!<semaphore 4 , interrupt 0 clear bit. */
10633 #define HSEM_C1ICR_ISC5_Pos (5U)
10634 #define HSEM_C1ICR_ISC5_Msk (0x1UL << HSEM_C1ICR_ISC5_Pos) /*!< 0x00000020 */
10635 #define HSEM_C1ICR_ISC5 HSEM_C1ICR_ISC5_Msk /*!<semaphore 5 interrupt 0 clear bit. */
10636 #define HSEM_C1ICR_ISC6_Pos (6U)
10637 #define HSEM_C1ICR_ISC6_Msk (0x1UL << HSEM_C1ICR_ISC6_Pos) /*!< 0x00000040 */
10638 #define HSEM_C1ICR_ISC6 HSEM_C1ICR_ISC6_Msk /*!<semaphore 6 interrupt 0 clear bit. */
10639 #define HSEM_C1ICR_ISC7_Pos (7U)
10640 #define HSEM_C1ICR_ISC7_Msk (0x1UL << HSEM_C1ICR_ISC7_Pos) /*!< 0x00000080 */
10641 #define HSEM_C1ICR_ISC7 HSEM_C1ICR_ISC7_Msk /*!<semaphore 7 interrupt 0 clear bit. */
10642 #define HSEM_C1ICR_ISC8_Pos (8U)
10643 #define HSEM_C1ICR_ISC8_Msk (0x1UL << HSEM_C1ICR_ISC8_Pos) /*!< 0x00000100 */
10644 #define HSEM_C1ICR_ISC8 HSEM_C1ICR_ISC8_Msk /*!<semaphore 8 interrupt 0 clear bit. */
10645 #define HSEM_C1ICR_ISC9_Pos (9U)
10646 #define HSEM_C1ICR_ISC9_Msk (0x1UL << HSEM_C1ICR_ISC9_Pos) /*!< 0x00000200 */
10647 #define HSEM_C1ICR_ISC9 HSEM_C1ICR_ISC9_Msk /*!<semaphore 9 interrupt 0 clear bit. */
10648 #define HSEM_C1ICR_ISC10_Pos (10U)
10649 #define HSEM_C1ICR_ISC10_Msk (0x1UL << HSEM_C1ICR_ISC10_Pos) /*!< 0x00000400 */
10650 #define HSEM_C1ICR_ISC10 HSEM_C1ICR_ISC10_Msk /*!<semaphore 10 interrupt 0 clear bit. */
10651 #define HSEM_C1ICR_ISC11_Pos (11U)
10652 #define HSEM_C1ICR_ISC11_Msk (0x1UL << HSEM_C1ICR_ISC11_Pos) /*!< 0x00000800 */
10653 #define HSEM_C1ICR_ISC11 HSEM_C1ICR_ISC11_Msk /*!<semaphore 11 interrupt 0 clear bit. */
10654 #define HSEM_C1ICR_ISC12_Pos (12U)
10655 #define HSEM_C1ICR_ISC12_Msk (0x1UL << HSEM_C1ICR_ISC12_Pos) /*!< 0x00001000 */
10656 #define HSEM_C1ICR_ISC12 HSEM_C1ICR_ISC12_Msk /*!<semaphore 12 interrupt 0 clear bit. */
10657 #define HSEM_C1ICR_ISC13_Pos (13U)
10658 #define HSEM_C1ICR_ISC13_Msk (0x1UL << HSEM_C1ICR_ISC13_Pos) /*!< 0x00002000 */
10659 #define HSEM_C1ICR_ISC13 HSEM_C1ICR_ISC13_Msk /*!<semaphore 13 interrupt 0 clear bit. */
10660 #define HSEM_C1ICR_ISC14_Pos (14U)
10661 #define HSEM_C1ICR_ISC14_Msk (0x1UL << HSEM_C1ICR_ISC14_Pos) /*!< 0x00004000 */
10662 #define HSEM_C1ICR_ISC14 HSEM_C1ICR_ISC14_Msk /*!<semaphore 14 interrupt 0 clear bit. */
10663 #define HSEM_C1ICR_ISC15_Pos (15U)
10664 #define HSEM_C1ICR_ISC15_Msk (0x1UL << HSEM_C1ICR_ISC15_Pos) /*!< 0x00008000 */
10665 #define HSEM_C1ICR_ISC15 HSEM_C1ICR_ISC15_Msk /*!<semaphore 15 interrupt 0 clear bit. */
10666 #define HSEM_C1ICR_ISC16_Pos (16U)
10667 #define HSEM_C1ICR_ISC16_Msk (0x1UL << HSEM_C1ICR_ISC16_Pos) /*!< 0x00010000 */
10668 #define HSEM_C1ICR_ISC16 HSEM_C1ICR_ISC16_Msk /*!<semaphore 16 interrupt 0 clear bit. */
10669 #define HSEM_C1ICR_ISC17_Pos (17U)
10670 #define HSEM_C1ICR_ISC17_Msk (0x1UL << HSEM_C1ICR_ISC17_Pos) /*!< 0x00020000 */
10671 #define HSEM_C1ICR_ISC17 HSEM_C1ICR_ISC17_Msk /*!<semaphore 17 interrupt 0 clear bit. */
10672 #define HSEM_C1ICR_ISC18_Pos (18U)
10673 #define HSEM_C1ICR_ISC18_Msk (0x1UL << HSEM_C1ICR_ISC18_Pos) /*!< 0x00040000 */
10674 #define HSEM_C1ICR_ISC18 HSEM_C1ICR_ISC18_Msk /*!<semaphore 18 interrupt 0 clear bit. */
10675 #define HSEM_C1ICR_ISC19_Pos (19U)
10676 #define HSEM_C1ICR_ISC19_Msk (0x1UL << HSEM_C1ICR_ISC19_Pos) /*!< 0x00080000 */
10677 #define HSEM_C1ICR_ISC19 HSEM_C1ICR_ISC19_Msk /*!<semaphore 19 interrupt 0 clear bit. */
10678 #define HSEM_C1ICR_ISC20_Pos (20U)
10679 #define HSEM_C1ICR_ISC20_Msk (0x1UL << HSEM_C1ICR_ISC20_Pos) /*!< 0x00100000 */
10680 #define HSEM_C1ICR_ISC20 HSEM_C1ICR_ISC20_Msk /*!<semaphore 20 interrupt 0 clear bit. */
10681 #define HSEM_C1ICR_ISC21_Pos (21U)
10682 #define HSEM_C1ICR_ISC21_Msk (0x1UL << HSEM_C1ICR_ISC21_Pos) /*!< 0x00200000 */
10683 #define HSEM_C1ICR_ISC21 HSEM_C1ICR_ISC21_Msk /*!<semaphore 21 interrupt 0 clear bit. */
10684 #define HSEM_C1ICR_ISC22_Pos (22U)
10685 #define HSEM_C1ICR_ISC22_Msk (0x1UL << HSEM_C1ICR_ISC22_Pos) /*!< 0x00400000 */
10686 #define HSEM_C1ICR_ISC22 HSEM_C1ICR_ISC22_Msk /*!<semaphore 22 interrupt 0 clear bit. */
10687 #define HSEM_C1ICR_ISC23_Pos (23U)
10688 #define HSEM_C1ICR_ISC23_Msk (0x1UL << HSEM_C1ICR_ISC23_Pos) /*!< 0x00800000 */
10689 #define HSEM_C1ICR_ISC23 HSEM_C1ICR_ISC23_Msk /*!<semaphore 23 interrupt 0 clear bit. */
10690 #define HSEM_C1ICR_ISC24_Pos (24U)
10691 #define HSEM_C1ICR_ISC24_Msk (0x1UL << HSEM_C1ICR_ISC24_Pos) /*!< 0x01000000 */
10692 #define HSEM_C1ICR_ISC24 HSEM_C1ICR_ISC24_Msk /*!<semaphore 24 interrupt 0 clear bit. */
10693 #define HSEM_C1ICR_ISC25_Pos (25U)
10694 #define HSEM_C1ICR_ISC25_Msk (0x1UL << HSEM_C1ICR_ISC25_Pos) /*!< 0x02000000 */
10695 #define HSEM_C1ICR_ISC25 HSEM_C1ICR_ISC25_Msk /*!<semaphore 25 interrupt 0 clear bit. */
10696 #define HSEM_C1ICR_ISC26_Pos (26U)
10697 #define HSEM_C1ICR_ISC26_Msk (0x1UL << HSEM_C1ICR_ISC26_Pos) /*!< 0x04000000 */
10698 #define HSEM_C1ICR_ISC26 HSEM_C1ICR_ISC26_Msk /*!<semaphore 26 interrupt 0 clear bit. */
10699 #define HSEM_C1ICR_ISC27_Pos (27U)
10700 #define HSEM_C1ICR_ISC27_Msk (0x1UL << HSEM_C1ICR_ISC27_Pos) /*!< 0x08000000 */
10701 #define HSEM_C1ICR_ISC27 HSEM_C1ICR_ISC27_Msk /*!<semaphore 27 interrupt 0 clear bit. */
10702 #define HSEM_C1ICR_ISC28_Pos (28U)
10703 #define HSEM_C1ICR_ISC28_Msk (0x1UL << HSEM_C1ICR_ISC28_Pos) /*!< 0x10000000 */
10704 #define HSEM_C1ICR_ISC28 HSEM_C1ICR_ISC28_Msk /*!<semaphore 28 interrupt 0 clear bit. */
10705 #define HSEM_C1ICR_ISC29_Pos (29U)
10706 #define HSEM_C1ICR_ISC29_Msk (0x1UL << HSEM_C1ICR_ISC29_Pos) /*!< 0x20000000 */
10707 #define HSEM_C1ICR_ISC29 HSEM_C1ICR_ISC29_Msk /*!<semaphore 29 interrupt 0 clear bit. */
10708 #define HSEM_C1ICR_ISC30_Pos (30U)
10709 #define HSEM_C1ICR_ISC30_Msk (0x1UL << HSEM_C1ICR_ISC30_Pos) /*!< 0x40000000 */
10710 #define HSEM_C1ICR_ISC30 HSEM_C1ICR_ISC30_Msk /*!<semaphore 30 interrupt 0 clear bit. */
10711 #define HSEM_C1ICR_ISC31_Pos (31U)
10712 #define HSEM_C1ICR_ISC31_Msk (0x1UL << HSEM_C1ICR_ISC31_Pos) /*!< 0x80000000 */
10713 #define HSEM_C1ICR_ISC31 HSEM_C1ICR_ISC31_Msk /*!<semaphore 31 interrupt 0 clear bit. */
10714
10715 /******************** Bit definition for HSEM_C1ISR register *****************/
10716 #define HSEM_C1ISR_ISF0_Pos (0U)
10717 #define HSEM_C1ISR_ISF0_Msk (0x1UL << HSEM_C1ISR_ISF0_Pos) /*!< 0x00000001 */
10718 #define HSEM_C1ISR_ISF0 HSEM_C1ISR_ISF0_Msk /*!<semaphore 0 interrupt 0 status bit. */
10719 #define HSEM_C1ISR_ISF1_Pos (1U)
10720 #define HSEM_C1ISR_ISF1_Msk (0x1UL << HSEM_C1ISR_ISF1_Pos) /*!< 0x00000002 */
10721 #define HSEM_C1ISR_ISF1 HSEM_C1ISR_ISF1_Msk /*!<semaphore 1 interrupt 0 status bit. */
10722 #define HSEM_C1ISR_ISF2_Pos (2U)
10723 #define HSEM_C1ISR_ISF2_Msk (0x1UL << HSEM_C1ISR_ISF2_Pos) /*!< 0x00000004 */
10724 #define HSEM_C1ISR_ISF2 HSEM_C1ISR_ISF2_Msk /*!<semaphore 2 interrupt 0 status bit. */
10725 #define HSEM_C1ISR_ISF3_Pos (3U)
10726 #define HSEM_C1ISR_ISF3_Msk (0x1UL << HSEM_C1ISR_ISF3_Pos) /*!< 0x00000008 */
10727 #define HSEM_C1ISR_ISF3 HSEM_C1ISR_ISF3_Msk /*!<semaphore 3 interrupt 0 status bit. */
10728 #define HSEM_C1ISR_ISF4_Pos (4U)
10729 #define HSEM_C1ISR_ISF4_Msk (0x1UL << HSEM_C1ISR_ISF4_Pos) /*!< 0x00000010 */
10730 #define HSEM_C1ISR_ISF4 HSEM_C1ISR_ISF4_Msk /*!<semaphore 4 interrupt 0 status bit. */
10731 #define HSEM_C1ISR_ISF5_Pos (5U)
10732 #define HSEM_C1ISR_ISF5_Msk (0x1UL << HSEM_C1ISR_ISF5_Pos) /*!< 0x00000020 */
10733 #define HSEM_C1ISR_ISF5 HSEM_C1ISR_ISF5_Msk /*!<semaphore 5 interrupt 0 status bit. */
10734 #define HSEM_C1ISR_ISF6_Pos (6U)
10735 #define HSEM_C1ISR_ISF6_Msk (0x1UL << HSEM_C1ISR_ISF6_Pos) /*!< 0x00000040 */
10736 #define HSEM_C1ISR_ISF6 HSEM_C1ISR_ISF6_Msk /*!<semaphore 6 interrupt 0 status bit. */
10737 #define HSEM_C1ISR_ISF7_Pos (7U)
10738 #define HSEM_C1ISR_ISF7_Msk (0x1UL << HSEM_C1ISR_ISF7_Pos) /*!< 0x00000080 */
10739 #define HSEM_C1ISR_ISF7 HSEM_C1ISR_ISF7_Msk /*!<semaphore 7 interrupt 0 status bit. */
10740 #define HSEM_C1ISR_ISF8_Pos (8U)
10741 #define HSEM_C1ISR_ISF8_Msk (0x1UL << HSEM_C1ISR_ISF8_Pos) /*!< 0x00000100 */
10742 #define HSEM_C1ISR_ISF8 HSEM_C1ISR_ISF8_Msk /*!<semaphore 8 interrupt 0 status bit. */
10743 #define HSEM_C1ISR_ISF9_Pos (9U)
10744 #define HSEM_C1ISR_ISF9_Msk (0x1UL << HSEM_C1ISR_ISF9_Pos) /*!< 0x00000200 */
10745 #define HSEM_C1ISR_ISF9 HSEM_C1ISR_ISF9_Msk /*!<semaphore 9 interrupt 0 status bit. */
10746 #define HSEM_C1ISR_ISF10_Pos (10U)
10747 #define HSEM_C1ISR_ISF10_Msk (0x1UL << HSEM_C1ISR_ISF10_Pos) /*!< 0x00000400 */
10748 #define HSEM_C1ISR_ISF10 HSEM_C1ISR_ISF10_Msk /*!<semaphore 10 interrupt 0 status bit. */
10749 #define HSEM_C1ISR_ISF11_Pos (11U)
10750 #define HSEM_C1ISR_ISF11_Msk (0x1UL << HSEM_C1ISR_ISF11_Pos) /*!< 0x00000800 */
10751 #define HSEM_C1ISR_ISF11 HSEM_C1ISR_ISF11_Msk /*!<semaphore 11 interrupt 0 status bit. */
10752 #define HSEM_C1ISR_ISF12_Pos (12U)
10753 #define HSEM_C1ISR_ISF12_Msk (0x1UL << HSEM_C1ISR_ISF12_Pos) /*!< 0x00001000 */
10754 #define HSEM_C1ISR_ISF12 HSEM_C1ISR_ISF12_Msk /*!<semaphore 12 interrupt 0 status bit. */
10755 #define HSEM_C1ISR_ISF13_Pos (13U)
10756 #define HSEM_C1ISR_ISF13_Msk (0x1UL << HSEM_C1ISR_ISF13_Pos) /*!< 0x00002000 */
10757 #define HSEM_C1ISR_ISF13 HSEM_C1ISR_ISF13_Msk /*!<semaphore 13 interrupt 0 status bit. */
10758 #define HSEM_C1ISR_ISF14_Pos (14U)
10759 #define HSEM_C1ISR_ISF14_Msk (0x1UL << HSEM_C1ISR_ISF14_Pos) /*!< 0x00004000 */
10760 #define HSEM_C1ISR_ISF14 HSEM_C1ISR_ISF14_Msk /*!<semaphore 14 interrupt 0 status bit. */
10761 #define HSEM_C1ISR_ISF15_Pos (15U)
10762 #define HSEM_C1ISR_ISF15_Msk (0x1UL << HSEM_C1ISR_ISF15_Pos) /*!< 0x00008000 */
10763 #define HSEM_C1ISR_ISF15 HSEM_C1ISR_ISF15_Msk /*!<semaphore 15 interrupt 0 status bit. */
10764 #define HSEM_C1ISR_ISF16_Pos (16U)
10765 #define HSEM_C1ISR_ISF16_Msk (0x1UL << HSEM_C1ISR_ISF16_Pos) /*!< 0x00010000 */
10766 #define HSEM_C1ISR_ISF16 HSEM_C1ISR_ISF16_Msk /*!<semaphore 16 interrupt 0 status bit. */
10767 #define HSEM_C1ISR_ISF17_Pos (17U)
10768 #define HSEM_C1ISR_ISF17_Msk (0x1UL << HSEM_C1ISR_ISF17_Pos) /*!< 0x00020000 */
10769 #define HSEM_C1ISR_ISF17 HSEM_C1ISR_ISF17_Msk /*!<semaphore 17 interrupt 0 status bit. */
10770 #define HSEM_C1ISR_ISF18_Pos (18U)
10771 #define HSEM_C1ISR_ISF18_Msk (0x1UL << HSEM_C1ISR_ISF18_Pos) /*!< 0x00040000 */
10772 #define HSEM_C1ISR_ISF18 HSEM_C1ISR_ISF18_Msk /*!<semaphore 18 interrupt 0 status bit. */
10773 #define HSEM_C1ISR_ISF19_Pos (19U)
10774 #define HSEM_C1ISR_ISF19_Msk (0x1UL << HSEM_C1ISR_ISF19_Pos) /*!< 0x00080000 */
10775 #define HSEM_C1ISR_ISF19 HSEM_C1ISR_ISF19_Msk /*!<semaphore 19 interrupt 0 status bit. */
10776 #define HSEM_C1ISR_ISF20_Pos (20U)
10777 #define HSEM_C1ISR_ISF20_Msk (0x1UL << HSEM_C1ISR_ISF20_Pos) /*!< 0x00100000 */
10778 #define HSEM_C1ISR_ISF20 HSEM_C1ISR_ISF20_Msk /*!<semaphore 20 interrupt 0 status bit. */
10779 #define HSEM_C1ISR_ISF21_Pos (21U)
10780 #define HSEM_C1ISR_ISF21_Msk (0x1UL << HSEM_C1ISR_ISF21_Pos) /*!< 0x00200000 */
10781 #define HSEM_C1ISR_ISF21 HSEM_C1ISR_ISF21_Msk /*!<semaphore 21 interrupt 0 status bit. */
10782 #define HSEM_C1ISR_ISF22_Pos (22U)
10783 #define HSEM_C1ISR_ISF22_Msk (0x1UL << HSEM_C1ISR_ISF22_Pos) /*!< 0x00400000 */
10784 #define HSEM_C1ISR_ISF22 HSEM_C1ISR_ISF22_Msk /*!<semaphore 22 interrupt 0 status bit. */
10785 #define HSEM_C1ISR_ISF23_Pos (23U)
10786 #define HSEM_C1ISR_ISF23_Msk (0x1UL << HSEM_C1ISR_ISF23_Pos) /*!< 0x00800000 */
10787 #define HSEM_C1ISR_ISF23 HSEM_C1ISR_ISF23_Msk /*!<semaphore 23 interrupt 0 status bit. */
10788 #define HSEM_C1ISR_ISF24_Pos (24U)
10789 #define HSEM_C1ISR_ISF24_Msk (0x1UL << HSEM_C1ISR_ISF24_Pos) /*!< 0x01000000 */
10790 #define HSEM_C1ISR_ISF24 HSEM_C1ISR_ISF24_Msk /*!<semaphore 24 interrupt 0 status bit. */
10791 #define HSEM_C1ISR_ISF25_Pos (25U)
10792 #define HSEM_C1ISR_ISF25_Msk (0x1UL << HSEM_C1ISR_ISF25_Pos) /*!< 0x02000000 */
10793 #define HSEM_C1ISR_ISF25 HSEM_C1ISR_ISF25_Msk /*!<semaphore 25 interrupt 0 status bit. */
10794 #define HSEM_C1ISR_ISF26_Pos (26U)
10795 #define HSEM_C1ISR_ISF26_Msk (0x1UL << HSEM_C1ISR_ISF26_Pos) /*!< 0x04000000 */
10796 #define HSEM_C1ISR_ISF26 HSEM_C1ISR_ISF26_Msk /*!<semaphore 26 interrupt 0 status bit. */
10797 #define HSEM_C1ISR_ISF27_Pos (27U)
10798 #define HSEM_C1ISR_ISF27_Msk (0x1UL << HSEM_C1ISR_ISF27_Pos) /*!< 0x08000000 */
10799 #define HSEM_C1ISR_ISF27 HSEM_C1ISR_ISF27_Msk /*!<semaphore 27 interrupt 0 status bit. */
10800 #define HSEM_C1ISR_ISF28_Pos (28U)
10801 #define HSEM_C1ISR_ISF28_Msk (0x1UL << HSEM_C1ISR_ISF28_Pos) /*!< 0x10000000 */
10802 #define HSEM_C1ISR_ISF28 HSEM_C1ISR_ISF28_Msk /*!<semaphore 28 interrupt 0 status bit. */
10803 #define HSEM_C1ISR_ISF29_Pos (29U)
10804 #define HSEM_C1ISR_ISF29_Msk (0x1UL << HSEM_C1ISR_ISF29_Pos) /*!< 0x20000000 */
10805 #define HSEM_C1ISR_ISF29 HSEM_C1ISR_ISF29_Msk /*!<semaphore 29 interrupt 0 status bit. */
10806 #define HSEM_C1ISR_ISF30_Pos (30U)
10807 #define HSEM_C1ISR_ISF30_Msk (0x1UL << HSEM_C1ISR_ISF30_Pos) /*!< 0x40000000 */
10808 #define HSEM_C1ISR_ISF30 HSEM_C1ISR_ISF30_Msk /*!<semaphore 30 interrupt 0 status bit. */
10809 #define HSEM_C1ISR_ISF31_Pos (31U)
10810 #define HSEM_C1ISR_ISF31_Msk (0x1UL << HSEM_C1ISR_ISF31_Pos) /*!< 0x80000000 */
10811 #define HSEM_C1ISR_ISF31 HSEM_C1ISR_ISF31_Msk /*!<semaphore 31 interrupt 0 status bit. */
10812
10813 /******************** Bit definition for HSEM_C1MISR register *****************/
10814 #define HSEM_C1MISR_MISF0_Pos (0U)
10815 #define HSEM_C1MISR_MISF0_Msk (0x1UL << HSEM_C1MISR_MISF0_Pos) /*!< 0x00000001 */
10816 #define HSEM_C1MISR_MISF0 HSEM_C1MISR_MISF0_Msk /*!<semaphore 0 interrupt 0 masked status bit. */
10817 #define HSEM_C1MISR_MISF1_Pos (1U)
10818 #define HSEM_C1MISR_MISF1_Msk (0x1UL << HSEM_C1MISR_MISF1_Pos) /*!< 0x00000002 */
10819 #define HSEM_C1MISR_MISF1 HSEM_C1MISR_MISF1_Msk /*!<semaphore 1 interrupt 0 masked status bit. */
10820 #define HSEM_C1MISR_MISF2_Pos (2U)
10821 #define HSEM_C1MISR_MISF2_Msk (0x1UL << HSEM_C1MISR_MISF2_Pos) /*!< 0x00000004 */
10822 #define HSEM_C1MISR_MISF2 HSEM_C1MISR_MISF2_Msk /*!<semaphore 2 interrupt 0 masked status bit. */
10823 #define HSEM_C1MISR_MISF3_Pos (3U)
10824 #define HSEM_C1MISR_MISF3_Msk (0x1UL << HSEM_C1MISR_MISF3_Pos) /*!< 0x00000008 */
10825 #define HSEM_C1MISR_MISF3 HSEM_C1MISR_MISF3_Msk /*!<semaphore 3 interrupt 0 masked status bit. */
10826 #define HSEM_C1MISR_MISF4_Pos (4U)
10827 #define HSEM_C1MISR_MISF4_Msk (0x1UL << HSEM_C1MISR_MISF4_Pos) /*!< 0x00000010 */
10828 #define HSEM_C1MISR_MISF4 HSEM_C1MISR_MISF4_Msk /*!<semaphore 4 interrupt 0 masked status bit. */
10829 #define HSEM_C1MISR_MISF5_Pos (5U)
10830 #define HSEM_C1MISR_MISF5_Msk (0x1UL << HSEM_C1MISR_MISF5_Pos) /*!< 0x00000020 */
10831 #define HSEM_C1MISR_MISF5 HSEM_C1MISR_MISF5_Msk /*!<semaphore 5 interrupt 0 masked status bit. */
10832 #define HSEM_C1MISR_MISF6_Pos (6U)
10833 #define HSEM_C1MISR_MISF6_Msk (0x1UL << HSEM_C1MISR_MISF6_Pos) /*!< 0x00000040 */
10834 #define HSEM_C1MISR_MISF6 HSEM_C1MISR_MISF6_Msk /*!<semaphore 6 interrupt 0 masked status bit. */
10835 #define HSEM_C1MISR_MISF7_Pos (7U)
10836 #define HSEM_C1MISR_MISF7_Msk (0x1UL << HSEM_C1MISR_MISF7_Pos) /*!< 0x00000080 */
10837 #define HSEM_C1MISR_MISF7 HSEM_C1MISR_MISF7_Msk /*!<semaphore 7 interrupt 0 masked status bit. */
10838 #define HSEM_C1MISR_MISF8_Pos (8U)
10839 #define HSEM_C1MISR_MISF8_Msk (0x1UL << HSEM_C1MISR_MISF8_Pos) /*!< 0x00000100 */
10840 #define HSEM_C1MISR_MISF8 HSEM_C1MISR_MISF8_Msk /*!<semaphore 8 interrupt 0 masked status bit. */
10841 #define HSEM_C1MISR_MISF9_Pos (9U)
10842 #define HSEM_C1MISR_MISF9_Msk (0x1UL << HSEM_C1MISR_MISF9_Pos) /*!< 0x00000200 */
10843 #define HSEM_C1MISR_MISF9 HSEM_C1MISR_MISF9_Msk /*!<semaphore 9 interrupt 0 masked status bit. */
10844 #define HSEM_C1MISR_MISF10_Pos (10U)
10845 #define HSEM_C1MISR_MISF10_Msk (0x1UL << HSEM_C1MISR_MISF10_Pos) /*!< 0x00000400 */
10846 #define HSEM_C1MISR_MISF10 HSEM_C1MISR_MISF10_Msk /*!<semaphore 10 interrupt 0 masked status bit. */
10847 #define HSEM_C1MISR_MISF11_Pos (11U)
10848 #define HSEM_C1MISR_MISF11_Msk (0x1UL << HSEM_C1MISR_MISF11_Pos) /*!< 0x00000800 */
10849 #define HSEM_C1MISR_MISF11 HSEM_C1MISR_MISF11_Msk /*!<semaphore 11 interrupt 0 masked status bit. */
10850 #define HSEM_C1MISR_MISF12_Pos (12U)
10851 #define HSEM_C1MISR_MISF12_Msk (0x1UL << HSEM_C1MISR_MISF12_Pos) /*!< 0x00001000 */
10852 #define HSEM_C1MISR_MISF12 HSEM_C1MISR_MISF12_Msk /*!<semaphore 12 interrupt 0 masked status bit. */
10853 #define HSEM_C1MISR_MISF13_Pos (13U)
10854 #define HSEM_C1MISR_MISF13_Msk (0x1UL << HSEM_C1MISR_MISF13_Pos) /*!< 0x00002000 */
10855 #define HSEM_C1MISR_MISF13 HSEM_C1MISR_MISF13_Msk /*!<semaphore 13 interrupt 0 masked status bit. */
10856 #define HSEM_C1MISR_MISF14_Pos (14U)
10857 #define HSEM_C1MISR_MISF14_Msk (0x1UL << HSEM_C1MISR_MISF14_Pos) /*!< 0x00004000 */
10858 #define HSEM_C1MISR_MISF14 HSEM_C1MISR_MISF14_Msk /*!<semaphore 14 interrupt 0 masked status bit. */
10859 #define HSEM_C1MISR_MISF15_Pos (15U)
10860 #define HSEM_C1MISR_MISF15_Msk (0x1UL << HSEM_C1MISR_MISF15_Pos) /*!< 0x00008000 */
10861 #define HSEM_C1MISR_MISF15 HSEM_C1MISR_MISF15_Msk /*!<semaphore 15 interrupt 0 masked status bit. */
10862 #define HSEM_C1MISR_MISF16_Pos (16U)
10863 #define HSEM_C1MISR_MISF16_Msk (0x1UL << HSEM_C1MISR_MISF16_Pos) /*!< 0x00010000 */
10864 #define HSEM_C1MISR_MISF16 HSEM_C1MISR_MISF16_Msk /*!<semaphore 16 interrupt 0 masked status bit. */
10865 #define HSEM_C1MISR_MISF17_Pos (17U)
10866 #define HSEM_C1MISR_MISF17_Msk (0x1UL << HSEM_C1MISR_MISF17_Pos) /*!< 0x00020000 */
10867 #define HSEM_C1MISR_MISF17 HSEM_C1MISR_MISF17_Msk /*!<semaphore 17 interrupt 0 masked status bit. */
10868 #define HSEM_C1MISR_MISF18_Pos (18U)
10869 #define HSEM_C1MISR_MISF18_Msk (0x1UL << HSEM_C1MISR_MISF18_Pos) /*!< 0x00040000 */
10870 #define HSEM_C1MISR_MISF18 HSEM_C1MISR_MISF18_Msk /*!<semaphore 18 interrupt 0 masked status bit. */
10871 #define HSEM_C1MISR_MISF19_Pos (19U)
10872 #define HSEM_C1MISR_MISF19_Msk (0x1UL << HSEM_C1MISR_MISF19_Pos) /*!< 0x00080000 */
10873 #define HSEM_C1MISR_MISF19 HSEM_C1MISR_MISF19_Msk /*!<semaphore 19 interrupt 0 masked status bit. */
10874 #define HSEM_C1MISR_MISF20_Pos (20U)
10875 #define HSEM_C1MISR_MISF20_Msk (0x1UL << HSEM_C1MISR_MISF20_Pos) /*!< 0x00100000 */
10876 #define HSEM_C1MISR_MISF20 HSEM_C1MISR_MISF20_Msk /*!<semaphore 20 interrupt 0 masked status bit. */
10877 #define HSEM_C1MISR_MISF21_Pos (21U)
10878 #define HSEM_C1MISR_MISF21_Msk (0x1UL << HSEM_C1MISR_MISF21_Pos) /*!< 0x00200000 */
10879 #define HSEM_C1MISR_MISF21 HSEM_C1MISR_MISF21_Msk /*!<semaphore 21 interrupt 0 masked status bit. */
10880 #define HSEM_C1MISR_MISF22_Pos (22U)
10881 #define HSEM_C1MISR_MISF22_Msk (0x1UL << HSEM_C1MISR_MISF22_Pos) /*!< 0x00400000 */
10882 #define HSEM_C1MISR_MISF22 HSEM_C1MISR_MISF22_Msk /*!<semaphore 22 interrupt 0 masked status bit. */
10883 #define HSEM_C1MISR_MISF23_Pos (23U)
10884 #define HSEM_C1MISR_MISF23_Msk (0x1UL << HSEM_C1MISR_MISF23_Pos) /*!< 0x00800000 */
10885 #define HSEM_C1MISR_MISF23 HSEM_C1MISR_MISF23_Msk /*!<semaphore 23 interrupt 0 masked status bit. */
10886 #define HSEM_C1MISR_MISF24_Pos (24U)
10887 #define HSEM_C1MISR_MISF24_Msk (0x1UL << HSEM_C1MISR_MISF24_Pos) /*!< 0x01000000 */
10888 #define HSEM_C1MISR_MISF24 HSEM_C1MISR_MISF24_Msk /*!<semaphore 24 interrupt 0 masked status bit. */
10889 #define HSEM_C1MISR_MISF25_Pos (25U)
10890 #define HSEM_C1MISR_MISF25_Msk (0x1UL << HSEM_C1MISR_MISF25_Pos) /*!< 0x02000000 */
10891 #define HSEM_C1MISR_MISF25 HSEM_C1MISR_MISF25_Msk /*!<semaphore 25 interrupt 0 masked status bit. */
10892 #define HSEM_C1MISR_MISF26_Pos (26U)
10893 #define HSEM_C1MISR_MISF26_Msk (0x1UL << HSEM_C1MISR_MISF26_Pos) /*!< 0x04000000 */
10894 #define HSEM_C1MISR_MISF26 HSEM_C1MISR_MISF26_Msk /*!<semaphore 26 interrupt 0 masked status bit. */
10895 #define HSEM_C1MISR_MISF27_Pos (27U)
10896 #define HSEM_C1MISR_MISF27_Msk (0x1UL << HSEM_C1MISR_MISF27_Pos) /*!< 0x08000000 */
10897 #define HSEM_C1MISR_MISF27 HSEM_C1MISR_MISF27_Msk /*!<semaphore 27 interrupt 0 masked status bit. */
10898 #define HSEM_C1MISR_MISF28_Pos (28U)
10899 #define HSEM_C1MISR_MISF28_Msk (0x1UL << HSEM_C1MISR_MISF28_Pos) /*!< 0x10000000 */
10900 #define HSEM_C1MISR_MISF28 HSEM_C1MISR_MISF28_Msk /*!<semaphore 28 interrupt 0 masked status bit. */
10901 #define HSEM_C1MISR_MISF29_Pos (29U)
10902 #define HSEM_C1MISR_MISF29_Msk (0x1UL << HSEM_C1MISR_MISF29_Pos) /*!< 0x20000000 */
10903 #define HSEM_C1MISR_MISF29 HSEM_C1MISR_MISF29_Msk /*!<semaphore 29 interrupt 0 masked status bit. */
10904 #define HSEM_C1MISR_MISF30_Pos (30U)
10905 #define HSEM_C1MISR_MISF30_Msk (0x1UL << HSEM_C1MISR_MISF30_Pos) /*!< 0x40000000 */
10906 #define HSEM_C1MISR_MISF30 HSEM_C1MISR_MISF30_Msk /*!<semaphore 30 interrupt 0 masked status bit. */
10907 #define HSEM_C1MISR_MISF31_Pos (31U)
10908 #define HSEM_C1MISR_MISF31_Msk (0x1UL << HSEM_C1MISR_MISF31_Pos) /*!< 0x80000000 */
10909 #define HSEM_C1MISR_MISF31 HSEM_C1MISR_MISF31_Msk /*!<semaphore 31 interrupt 0 masked status bit. */
10910
10911 /******************** Bit definition for HSEM_CR register *****************/
10912 #define HSEM_CR_COREID_Pos (8U)
10913 #define HSEM_CR_COREID_Msk (0xFFUL << HSEM_CR_COREID_Pos) /*!< 0x0000FF00 */
10914 #define HSEM_CR_COREID HSEM_CR_COREID_Msk /*!<CoreID of semaphores to be cleared. */
10915 #define HSEM_CR_KEY_Pos (16U)
10916 #define HSEM_CR_KEY_Msk (0xFFFFUL << HSEM_CR_KEY_Pos) /*!< 0xFFFF0000 */
10917 #define HSEM_CR_KEY HSEM_CR_KEY_Msk /*!<semaphores clear key. */
10918
10919 /******************** Bit definition for HSEM_KEYR register *****************/
10920 #define HSEM_KEYR_KEY_Pos (16U)
10921 #define HSEM_KEYR_KEY_Msk (0xFFFFUL << HSEM_KEYR_KEY_Pos) /*!< 0xFFFF0000 */
10922 #define HSEM_KEYR_KEY HSEM_KEYR_KEY_Msk /*!<semaphores clear key. */
10923
10924 /******************************************************************************/
10925 /* */
10926 /* HASH */
10927 /* */
10928 /******************************************************************************/
10929 /****************** Bits definition for HASH_CR register ********************/
10930 #define HASH_CR_INIT_Pos (2U)
10931 #define HASH_CR_INIT_Msk (0x1UL << HASH_CR_INIT_Pos) /*!< 0x00000004 */
10932 #define HASH_CR_INIT HASH_CR_INIT_Msk
10933 #define HASH_CR_DMAE_Pos (3U)
10934 #define HASH_CR_DMAE_Msk (0x1UL << HASH_CR_DMAE_Pos) /*!< 0x00000008 */
10935 #define HASH_CR_DMAE HASH_CR_DMAE_Msk
10936 #define HASH_CR_DATATYPE_Pos (4U)
10937 #define HASH_CR_DATATYPE_Msk (0x3UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000030 */
10938 #define HASH_CR_DATATYPE HASH_CR_DATATYPE_Msk
10939 #define HASH_CR_DATATYPE_0 (0x1UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000010 */
10940 #define HASH_CR_DATATYPE_1 (0x2UL << HASH_CR_DATATYPE_Pos) /*!< 0x00000020 */
10941 #define HASH_CR_MODE_Pos (6U)
10942 #define HASH_CR_MODE_Msk (0x1UL << HASH_CR_MODE_Pos) /*!< 0x00000040 */
10943 #define HASH_CR_MODE HASH_CR_MODE_Msk
10944 #define HASH_CR_ALGO_Pos (7U)
10945 #define HASH_CR_ALGO_Msk (0x801UL << HASH_CR_ALGO_Pos) /*!< 0x00040080 */
10946 #define HASH_CR_ALGO HASH_CR_ALGO_Msk
10947 #define HASH_CR_ALGO_0 (0x001UL << HASH_CR_ALGO_Pos) /*!< 0x00000080 */
10948 #define HASH_CR_ALGO_1 (0x800UL << HASH_CR_ALGO_Pos) /*!< 0x00040000 */
10949 #define HASH_CR_NBW_Pos (8U)
10950 #define HASH_CR_NBW_Msk (0xFUL << HASH_CR_NBW_Pos) /*!< 0x00000F00 */
10951 #define HASH_CR_NBW HASH_CR_NBW_Msk
10952 #define HASH_CR_NBW_0 (0x1UL << HASH_CR_NBW_Pos) /*!< 0x00000100 */
10953 #define HASH_CR_NBW_1 (0x2UL << HASH_CR_NBW_Pos) /*!< 0x00000200 */
10954 #define HASH_CR_NBW_2 (0x4UL << HASH_CR_NBW_Pos) /*!< 0x00000400 */
10955 #define HASH_CR_NBW_3 (0x8UL << HASH_CR_NBW_Pos) /*!< 0x00000800 */
10956 #define HASH_CR_DINNE_Pos (12U)
10957 #define HASH_CR_DINNE_Msk (0x1UL << HASH_CR_DINNE_Pos) /*!< 0x00001000 */
10958 #define HASH_CR_DINNE HASH_CR_DINNE_Msk
10959 #define HASH_CR_MDMAT_Pos (13U)
10960 #define HASH_CR_MDMAT_Msk (0x1UL << HASH_CR_MDMAT_Pos) /*!< 0x00002000 */
10961 #define HASH_CR_MDMAT HASH_CR_MDMAT_Msk
10962 #define HASH_CR_LKEY_Pos (16U)
10963 #define HASH_CR_LKEY_Msk (0x1UL << HASH_CR_LKEY_Pos) /*!< 0x00010000 */
10964 #define HASH_CR_LKEY HASH_CR_LKEY_Msk
10965
10966 /****************** Bits definition for HASH_STR register *******************/
10967 #define HASH_STR_NBLW_Pos (0U)
10968 #define HASH_STR_NBLW_Msk (0x1FUL << HASH_STR_NBLW_Pos) /*!< 0x0000001F */
10969 #define HASH_STR_NBLW HASH_STR_NBLW_Msk
10970 #define HASH_STR_NBLW_0 (0x01UL << HASH_STR_NBLW_Pos) /*!< 0x00000001 */
10971 #define HASH_STR_NBLW_1 (0x02UL << HASH_STR_NBLW_Pos) /*!< 0x00000002 */
10972 #define HASH_STR_NBLW_2 (0x04UL << HASH_STR_NBLW_Pos) /*!< 0x00000004 */
10973 #define HASH_STR_NBLW_3 (0x08UL << HASH_STR_NBLW_Pos) /*!< 0x00000008 */
10974 #define HASH_STR_NBLW_4 (0x10UL << HASH_STR_NBLW_Pos) /*!< 0x00000010 */
10975 #define HASH_STR_DCAL_Pos (8U)
10976 #define HASH_STR_DCAL_Msk (0x1UL << HASH_STR_DCAL_Pos) /*!< 0x00000100 */
10977 #define HASH_STR_DCAL HASH_STR_DCAL_Msk
10978
10979 /****************** Bits definition for HASH_IMR register *******************/
10980 #define HASH_IMR_DINIE_Pos (0U)
10981 #define HASH_IMR_DINIE_Msk (0x1UL << HASH_IMR_DINIE_Pos) /*!< 0x00000001 */
10982 #define HASH_IMR_DINIE HASH_IMR_DINIE_Msk
10983 #define HASH_IMR_DCIE_Pos (1U)
10984 #define HASH_IMR_DCIE_Msk (0x1UL << HASH_IMR_DCIE_Pos) /*!< 0x00000002 */
10985 #define HASH_IMR_DCIE HASH_IMR_DCIE_Msk
10986
10987 /****************** Bits definition for HASH_SR register ********************/
10988 #define HASH_SR_DINIS_Pos (0U)
10989 #define HASH_SR_DINIS_Msk (0x1UL << HASH_SR_DINIS_Pos) /*!< 0x00000001 */
10990 #define HASH_SR_DINIS HASH_SR_DINIS_Msk
10991 #define HASH_SR_DCIS_Pos (1U)
10992 #define HASH_SR_DCIS_Msk (0x1UL << HASH_SR_DCIS_Pos) /*!< 0x00000002 */
10993 #define HASH_SR_DCIS HASH_SR_DCIS_Msk
10994 #define HASH_SR_DMAS_Pos (2U)
10995 #define HASH_SR_DMAS_Msk (0x1UL << HASH_SR_DMAS_Pos) /*!< 0x00000004 */
10996 #define HASH_SR_DMAS HASH_SR_DMAS_Msk
10997 #define HASH_SR_BUSY_Pos (3U)
10998 #define HASH_SR_BUSY_Msk (0x1UL << HASH_SR_BUSY_Pos) /*!< 0x00000008 */
10999 #define HASH_SR_BUSY HASH_SR_BUSY_Msk
11000 /******************************************************************************/
11001 /* */
11002 /* Inter-integrated Circuit Interface (I2C) */
11003 /* */
11004 /******************************************************************************/
11005 /******************* Bit definition for I2C_CR1 register *******************/
11006 #define I2C_CR1_PE_Pos (0U)
11007 #define I2C_CR1_PE_Msk (0x1UL << I2C_CR1_PE_Pos) /*!< 0x00000001 */
11008 #define I2C_CR1_PE I2C_CR1_PE_Msk /*!< Peripheral enable */
11009 #define I2C_CR1_TXIE_Pos (1U)
11010 #define I2C_CR1_TXIE_Msk (0x1UL << I2C_CR1_TXIE_Pos) /*!< 0x00000002 */
11011 #define I2C_CR1_TXIE I2C_CR1_TXIE_Msk /*!< TX interrupt enable */
11012 #define I2C_CR1_RXIE_Pos (2U)
11013 #define I2C_CR1_RXIE_Msk (0x1UL << I2C_CR1_RXIE_Pos) /*!< 0x00000004 */
11014 #define I2C_CR1_RXIE I2C_CR1_RXIE_Msk /*!< RX interrupt enable */
11015 #define I2C_CR1_ADDRIE_Pos (3U)
11016 #define I2C_CR1_ADDRIE_Msk (0x1UL << I2C_CR1_ADDRIE_Pos) /*!< 0x00000008 */
11017 #define I2C_CR1_ADDRIE I2C_CR1_ADDRIE_Msk /*!< Address match interrupt enable */
11018 #define I2C_CR1_NACKIE_Pos (4U)
11019 #define I2C_CR1_NACKIE_Msk (0x1UL << I2C_CR1_NACKIE_Pos) /*!< 0x00000010 */
11020 #define I2C_CR1_NACKIE I2C_CR1_NACKIE_Msk /*!< NACK received interrupt enable */
11021 #define I2C_CR1_STOPIE_Pos (5U)
11022 #define I2C_CR1_STOPIE_Msk (0x1UL << I2C_CR1_STOPIE_Pos) /*!< 0x00000020 */
11023 #define I2C_CR1_STOPIE I2C_CR1_STOPIE_Msk /*!< STOP detection interrupt enable */
11024 #define I2C_CR1_TCIE_Pos (6U)
11025 #define I2C_CR1_TCIE_Msk (0x1UL << I2C_CR1_TCIE_Pos) /*!< 0x00000040 */
11026 #define I2C_CR1_TCIE I2C_CR1_TCIE_Msk /*!< Transfer complete interrupt enable */
11027 #define I2C_CR1_ERRIE_Pos (7U)
11028 #define I2C_CR1_ERRIE_Msk (0x1UL << I2C_CR1_ERRIE_Pos) /*!< 0x00000080 */
11029 #define I2C_CR1_ERRIE I2C_CR1_ERRIE_Msk /*!< Errors interrupt enable */
11030 #define I2C_CR1_DNF_Pos (8U)
11031 #define I2C_CR1_DNF_Msk (0xFUL << I2C_CR1_DNF_Pos) /*!< 0x00000F00 */
11032 #define I2C_CR1_DNF I2C_CR1_DNF_Msk /*!< Digital noise filter */
11033 #define I2C_CR1_ANFOFF_Pos (12U)
11034 #define I2C_CR1_ANFOFF_Msk (0x1UL << I2C_CR1_ANFOFF_Pos) /*!< 0x00001000 */
11035 #define I2C_CR1_ANFOFF I2C_CR1_ANFOFF_Msk /*!< Analog noise filter OFF */
11036 #define I2C_CR1_TXDMAEN_Pos (14U)
11037 #define I2C_CR1_TXDMAEN_Msk (0x1UL << I2C_CR1_TXDMAEN_Pos) /*!< 0x00004000 */
11038 #define I2C_CR1_TXDMAEN I2C_CR1_TXDMAEN_Msk /*!< DMA transmission requests enable */
11039 #define I2C_CR1_RXDMAEN_Pos (15U)
11040 #define I2C_CR1_RXDMAEN_Msk (0x1UL << I2C_CR1_RXDMAEN_Pos) /*!< 0x00008000 */
11041 #define I2C_CR1_RXDMAEN I2C_CR1_RXDMAEN_Msk /*!< DMA reception requests enable */
11042 #define I2C_CR1_SBC_Pos (16U)
11043 #define I2C_CR1_SBC_Msk (0x1UL << I2C_CR1_SBC_Pos) /*!< 0x00010000 */
11044 #define I2C_CR1_SBC I2C_CR1_SBC_Msk /*!< Slave byte control */
11045 #define I2C_CR1_NOSTRETCH_Pos (17U)
11046 #define I2C_CR1_NOSTRETCH_Msk (0x1UL << I2C_CR1_NOSTRETCH_Pos) /*!< 0x00020000 */
11047 #define I2C_CR1_NOSTRETCH I2C_CR1_NOSTRETCH_Msk /*!< Clock stretching disable */
11048 #define I2C_CR1_WUPEN_Pos (18U)
11049 #define I2C_CR1_WUPEN_Msk (0x1UL << I2C_CR1_WUPEN_Pos) /*!< 0x00040000 */
11050 #define I2C_CR1_WUPEN I2C_CR1_WUPEN_Msk /*!< Wakeup from STOP enable */
11051 #define I2C_CR1_GCEN_Pos (19U)
11052 #define I2C_CR1_GCEN_Msk (0x1UL << I2C_CR1_GCEN_Pos) /*!< 0x00080000 */
11053 #define I2C_CR1_GCEN I2C_CR1_GCEN_Msk /*!< General call enable */
11054 #define I2C_CR1_SMBHEN_Pos (20U)
11055 #define I2C_CR1_SMBHEN_Msk (0x1UL << I2C_CR1_SMBHEN_Pos) /*!< 0x00100000 */
11056 #define I2C_CR1_SMBHEN I2C_CR1_SMBHEN_Msk /*!< SMBus host address enable */
11057 #define I2C_CR1_SMBDEN_Pos (21U)
11058 #define I2C_CR1_SMBDEN_Msk (0x1UL << I2C_CR1_SMBDEN_Pos) /*!< 0x00200000 */
11059 #define I2C_CR1_SMBDEN I2C_CR1_SMBDEN_Msk /*!< SMBus device default address enable */
11060 #define I2C_CR1_ALERTEN_Pos (22U)
11061 #define I2C_CR1_ALERTEN_Msk (0x1UL << I2C_CR1_ALERTEN_Pos) /*!< 0x00400000 */
11062 #define I2C_CR1_ALERTEN I2C_CR1_ALERTEN_Msk /*!< SMBus alert enable */
11063 #define I2C_CR1_PECEN_Pos (23U)
11064 #define I2C_CR1_PECEN_Msk (0x1UL << I2C_CR1_PECEN_Pos) /*!< 0x00800000 */
11065 #define I2C_CR1_PECEN I2C_CR1_PECEN_Msk /*!< PEC enable */
11066
11067 /****************** Bit definition for I2C_CR2 register ********************/
11068 #define I2C_CR2_SADD_Pos (0U)
11069 #define I2C_CR2_SADD_Msk (0x3FFUL << I2C_CR2_SADD_Pos) /*!< 0x000003FF */
11070 #define I2C_CR2_SADD I2C_CR2_SADD_Msk /*!< Slave address (master mode) */
11071 #define I2C_CR2_RD_WRN_Pos (10U)
11072 #define I2C_CR2_RD_WRN_Msk (0x1UL << I2C_CR2_RD_WRN_Pos) /*!< 0x00000400 */
11073 #define I2C_CR2_RD_WRN I2C_CR2_RD_WRN_Msk /*!< Transfer direction (master mode) */
11074 #define I2C_CR2_ADD10_Pos (11U)
11075 #define I2C_CR2_ADD10_Msk (0x1UL << I2C_CR2_ADD10_Pos) /*!< 0x00000800 */
11076 #define I2C_CR2_ADD10 I2C_CR2_ADD10_Msk /*!< 10-bit addressing mode (master mode) */
11077 #define I2C_CR2_HEAD10R_Pos (12U)
11078 #define I2C_CR2_HEAD10R_Msk (0x1UL << I2C_CR2_HEAD10R_Pos) /*!< 0x00001000 */
11079 #define I2C_CR2_HEAD10R I2C_CR2_HEAD10R_Msk /*!< 10-bit address header only read direction (master mode) */
11080 #define I2C_CR2_START_Pos (13U)
11081 #define I2C_CR2_START_Msk (0x1UL << I2C_CR2_START_Pos) /*!< 0x00002000 */
11082 #define I2C_CR2_START I2C_CR2_START_Msk /*!< START generation */
11083 #define I2C_CR2_STOP_Pos (14U)
11084 #define I2C_CR2_STOP_Msk (0x1UL << I2C_CR2_STOP_Pos) /*!< 0x00004000 */
11085 #define I2C_CR2_STOP I2C_CR2_STOP_Msk /*!< STOP generation (master mode) */
11086 #define I2C_CR2_NACK_Pos (15U)
11087 #define I2C_CR2_NACK_Msk (0x1UL << I2C_CR2_NACK_Pos) /*!< 0x00008000 */
11088 #define I2C_CR2_NACK I2C_CR2_NACK_Msk /*!< NACK generation (slave mode) */
11089 #define I2C_CR2_NBYTES_Pos (16U)
11090 #define I2C_CR2_NBYTES_Msk (0xFFUL << I2C_CR2_NBYTES_Pos) /*!< 0x00FF0000 */
11091 #define I2C_CR2_NBYTES I2C_CR2_NBYTES_Msk /*!< Number of bytes */
11092 #define I2C_CR2_RELOAD_Pos (24U)
11093 #define I2C_CR2_RELOAD_Msk (0x1UL << I2C_CR2_RELOAD_Pos) /*!< 0x01000000 */
11094 #define I2C_CR2_RELOAD I2C_CR2_RELOAD_Msk /*!< NBYTES reload mode */
11095 #define I2C_CR2_AUTOEND_Pos (25U)
11096 #define I2C_CR2_AUTOEND_Msk (0x1UL << I2C_CR2_AUTOEND_Pos) /*!< 0x02000000 */
11097 #define I2C_CR2_AUTOEND I2C_CR2_AUTOEND_Msk /*!< Automatic end mode (master mode) */
11098 #define I2C_CR2_PECBYTE_Pos (26U)
11099 #define I2C_CR2_PECBYTE_Msk (0x1UL << I2C_CR2_PECBYTE_Pos) /*!< 0x04000000 */
11100 #define I2C_CR2_PECBYTE I2C_CR2_PECBYTE_Msk /*!< Packet error checking byte */
11101
11102 /******************* Bit definition for I2C_OAR1 register ******************/
11103 #define I2C_OAR1_OA1_Pos (0U)
11104 #define I2C_OAR1_OA1_Msk (0x3FFUL << I2C_OAR1_OA1_Pos) /*!< 0x000003FF */
11105 #define I2C_OAR1_OA1 I2C_OAR1_OA1_Msk /*!< Interface own address 1 */
11106 #define I2C_OAR1_OA1MODE_Pos (10U)
11107 #define I2C_OAR1_OA1MODE_Msk (0x1UL << I2C_OAR1_OA1MODE_Pos) /*!< 0x00000400 */
11108 #define I2C_OAR1_OA1MODE I2C_OAR1_OA1MODE_Msk /*!< Own address 1 10-bit mode */
11109 #define I2C_OAR1_OA1EN_Pos (15U)
11110 #define I2C_OAR1_OA1EN_Msk (0x1UL << I2C_OAR1_OA1EN_Pos) /*!< 0x00008000 */
11111 #define I2C_OAR1_OA1EN I2C_OAR1_OA1EN_Msk /*!< Own address 1 enable */
11112
11113 /******************* Bit definition for I2C_OAR2 register ******************/
11114 #define I2C_OAR2_OA2_Pos (1U)
11115 #define I2C_OAR2_OA2_Msk (0x7FUL << I2C_OAR2_OA2_Pos) /*!< 0x000000FE */
11116 #define I2C_OAR2_OA2 I2C_OAR2_OA2_Msk /*!< Interface own address 2 */
11117 #define I2C_OAR2_OA2MSK_Pos (8U)
11118 #define I2C_OAR2_OA2MSK_Msk (0x7UL << I2C_OAR2_OA2MSK_Pos) /*!< 0x00000700 */
11119 #define I2C_OAR2_OA2MSK I2C_OAR2_OA2MSK_Msk /*!< Own address 2 masks */
11120 #define I2C_OAR2_OA2NOMASK 0x00000000UL /*!< No mask */
11121 #define I2C_OAR2_OA2MASK01_Pos (8U)
11122 #define I2C_OAR2_OA2MASK01_Msk (0x1UL << I2C_OAR2_OA2MASK01_Pos) /*!< 0x00000100 */
11123 #define I2C_OAR2_OA2MASK01 I2C_OAR2_OA2MASK01_Msk /*!< OA2[1] is masked, Only OA2[7:2] are compared */
11124 #define I2C_OAR2_OA2MASK02_Pos (9U)
11125 #define I2C_OAR2_OA2MASK02_Msk (0x1UL << I2C_OAR2_OA2MASK02_Pos) /*!< 0x00000200 */
11126 #define I2C_OAR2_OA2MASK02 I2C_OAR2_OA2MASK02_Msk /*!< OA2[2:1] is masked, Only OA2[7:3] are compared */
11127 #define I2C_OAR2_OA2MASK03_Pos (8U)
11128 #define I2C_OAR2_OA2MASK03_Msk (0x3UL << I2C_OAR2_OA2MASK03_Pos) /*!< 0x00000300 */
11129 #define I2C_OAR2_OA2MASK03 I2C_OAR2_OA2MASK03_Msk /*!< OA2[3:1] is masked, Only OA2[7:4] are compared */
11130 #define I2C_OAR2_OA2MASK04_Pos (10U)
11131 #define I2C_OAR2_OA2MASK04_Msk (0x1UL << I2C_OAR2_OA2MASK04_Pos) /*!< 0x00000400 */
11132 #define I2C_OAR2_OA2MASK04 I2C_OAR2_OA2MASK04_Msk /*!< OA2[4:1] is masked, Only OA2[7:5] are compared */
11133 #define I2C_OAR2_OA2MASK05_Pos (8U)
11134 #define I2C_OAR2_OA2MASK05_Msk (0x5UL << I2C_OAR2_OA2MASK05_Pos) /*!< 0x00000500 */
11135 #define I2C_OAR2_OA2MASK05 I2C_OAR2_OA2MASK05_Msk /*!< OA2[5:1] is masked, Only OA2[7:6] are compared */
11136 #define I2C_OAR2_OA2MASK06_Pos (9U)
11137 #define I2C_OAR2_OA2MASK06_Msk (0x3UL << I2C_OAR2_OA2MASK06_Pos) /*!< 0x00000600 */
11138 #define I2C_OAR2_OA2MASK06 I2C_OAR2_OA2MASK06_Msk /*!< OA2[6:1] is masked, Only OA2[7] are compared */
11139 #define I2C_OAR2_OA2MASK07_Pos (8U)
11140 #define I2C_OAR2_OA2MASK07_Msk (0x7UL << I2C_OAR2_OA2MASK07_Pos) /*!< 0x00000700 */
11141 #define I2C_OAR2_OA2MASK07 I2C_OAR2_OA2MASK07_Msk /*!< OA2[7:1] is masked, No comparison is done */
11142 #define I2C_OAR2_OA2EN_Pos (15U)
11143 #define I2C_OAR2_OA2EN_Msk (0x1UL << I2C_OAR2_OA2EN_Pos) /*!< 0x00008000 */
11144 #define I2C_OAR2_OA2EN I2C_OAR2_OA2EN_Msk /*!< Own address 2 enable */
11145
11146 /******************* Bit definition for I2C_TIMINGR register *******************/
11147 #define I2C_TIMINGR_SCLL_Pos (0U)
11148 #define I2C_TIMINGR_SCLL_Msk (0xFFUL << I2C_TIMINGR_SCLL_Pos) /*!< 0x000000FF */
11149 #define I2C_TIMINGR_SCLL I2C_TIMINGR_SCLL_Msk /*!< SCL low period (master mode) */
11150 #define I2C_TIMINGR_SCLH_Pos (8U)
11151 #define I2C_TIMINGR_SCLH_Msk (0xFFUL << I2C_TIMINGR_SCLH_Pos) /*!< 0x0000FF00 */
11152 #define I2C_TIMINGR_SCLH I2C_TIMINGR_SCLH_Msk /*!< SCL high period (master mode) */
11153 #define I2C_TIMINGR_SDADEL_Pos (16U)
11154 #define I2C_TIMINGR_SDADEL_Msk (0xFUL << I2C_TIMINGR_SDADEL_Pos) /*!< 0x000F0000 */
11155 #define I2C_TIMINGR_SDADEL I2C_TIMINGR_SDADEL_Msk /*!< Data hold time */
11156 #define I2C_TIMINGR_SCLDEL_Pos (20U)
11157 #define I2C_TIMINGR_SCLDEL_Msk (0xFUL << I2C_TIMINGR_SCLDEL_Pos) /*!< 0x00F00000 */
11158 #define I2C_TIMINGR_SCLDEL I2C_TIMINGR_SCLDEL_Msk /*!< Data setup time */
11159 #define I2C_TIMINGR_PRESC_Pos (28U)
11160 #define I2C_TIMINGR_PRESC_Msk (0xFUL << I2C_TIMINGR_PRESC_Pos) /*!< 0xF0000000 */
11161 #define I2C_TIMINGR_PRESC I2C_TIMINGR_PRESC_Msk /*!< Timings prescaler */
11162
11163 /******************* Bit definition for I2C_TIMEOUTR register *******************/
11164 #define I2C_TIMEOUTR_TIMEOUTA_Pos (0U)
11165 #define I2C_TIMEOUTR_TIMEOUTA_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTA_Pos) /*!< 0x00000FFF */
11166 #define I2C_TIMEOUTR_TIMEOUTA I2C_TIMEOUTR_TIMEOUTA_Msk /*!< Bus timeout A */
11167 #define I2C_TIMEOUTR_TIDLE_Pos (12U)
11168 #define I2C_TIMEOUTR_TIDLE_Msk (0x1UL << I2C_TIMEOUTR_TIDLE_Pos) /*!< 0x00001000 */
11169 #define I2C_TIMEOUTR_TIDLE I2C_TIMEOUTR_TIDLE_Msk /*!< Idle clock timeout detection */
11170 #define I2C_TIMEOUTR_TIMOUTEN_Pos (15U)
11171 #define I2C_TIMEOUTR_TIMOUTEN_Msk (0x1UL << I2C_TIMEOUTR_TIMOUTEN_Pos) /*!< 0x00008000 */
11172 #define I2C_TIMEOUTR_TIMOUTEN I2C_TIMEOUTR_TIMOUTEN_Msk /*!< Clock timeout enable */
11173 #define I2C_TIMEOUTR_TIMEOUTB_Pos (16U)
11174 #define I2C_TIMEOUTR_TIMEOUTB_Msk (0xFFFUL << I2C_TIMEOUTR_TIMEOUTB_Pos) /*!< 0x0FFF0000 */
11175 #define I2C_TIMEOUTR_TIMEOUTB I2C_TIMEOUTR_TIMEOUTB_Msk /*!< Bus timeout B*/
11176 #define I2C_TIMEOUTR_TEXTEN_Pos (31U)
11177 #define I2C_TIMEOUTR_TEXTEN_Msk (0x1UL << I2C_TIMEOUTR_TEXTEN_Pos) /*!< 0x80000000 */
11178 #define I2C_TIMEOUTR_TEXTEN I2C_TIMEOUTR_TEXTEN_Msk /*!< Extended clock timeout enable */
11179
11180 /****************** Bit definition for I2C_ISR register *********************/
11181 #define I2C_ISR_TXE_Pos (0U)
11182 #define I2C_ISR_TXE_Msk (0x1UL << I2C_ISR_TXE_Pos) /*!< 0x00000001 */
11183 #define I2C_ISR_TXE I2C_ISR_TXE_Msk /*!< Transmit data register empty */
11184 #define I2C_ISR_TXIS_Pos (1U)
11185 #define I2C_ISR_TXIS_Msk (0x1UL << I2C_ISR_TXIS_Pos) /*!< 0x00000002 */
11186 #define I2C_ISR_TXIS I2C_ISR_TXIS_Msk /*!< Transmit interrupt status */
11187 #define I2C_ISR_RXNE_Pos (2U)
11188 #define I2C_ISR_RXNE_Msk (0x1UL << I2C_ISR_RXNE_Pos) /*!< 0x00000004 */
11189 #define I2C_ISR_RXNE I2C_ISR_RXNE_Msk /*!< Receive data register not empty */
11190 #define I2C_ISR_ADDR_Pos (3U)
11191 #define I2C_ISR_ADDR_Msk (0x1UL << I2C_ISR_ADDR_Pos) /*!< 0x00000008 */
11192 #define I2C_ISR_ADDR I2C_ISR_ADDR_Msk /*!< Address matched (slave mode)*/
11193 #define I2C_ISR_NACKF_Pos (4U)
11194 #define I2C_ISR_NACKF_Msk (0x1UL << I2C_ISR_NACKF_Pos) /*!< 0x00000010 */
11195 #define I2C_ISR_NACKF I2C_ISR_NACKF_Msk /*!< NACK received flag */
11196 #define I2C_ISR_STOPF_Pos (5U)
11197 #define I2C_ISR_STOPF_Msk (0x1UL << I2C_ISR_STOPF_Pos) /*!< 0x00000020 */
11198 #define I2C_ISR_STOPF I2C_ISR_STOPF_Msk /*!< STOP detection flag */
11199 #define I2C_ISR_TC_Pos (6U)
11200 #define I2C_ISR_TC_Msk (0x1UL << I2C_ISR_TC_Pos) /*!< 0x00000040 */
11201 #define I2C_ISR_TC I2C_ISR_TC_Msk /*!< Transfer complete (master mode) */
11202 #define I2C_ISR_TCR_Pos (7U)
11203 #define I2C_ISR_TCR_Msk (0x1UL << I2C_ISR_TCR_Pos) /*!< 0x00000080 */
11204 #define I2C_ISR_TCR I2C_ISR_TCR_Msk /*!< Transfer complete reload */
11205 #define I2C_ISR_BERR_Pos (8U)
11206 #define I2C_ISR_BERR_Msk (0x1UL << I2C_ISR_BERR_Pos) /*!< 0x00000100 */
11207 #define I2C_ISR_BERR I2C_ISR_BERR_Msk /*!< Bus error */
11208 #define I2C_ISR_ARLO_Pos (9U)
11209 #define I2C_ISR_ARLO_Msk (0x1UL << I2C_ISR_ARLO_Pos) /*!< 0x00000200 */
11210 #define I2C_ISR_ARLO I2C_ISR_ARLO_Msk /*!< Arbitration lost */
11211 #define I2C_ISR_OVR_Pos (10U)
11212 #define I2C_ISR_OVR_Msk (0x1UL << I2C_ISR_OVR_Pos) /*!< 0x00000400 */
11213 #define I2C_ISR_OVR I2C_ISR_OVR_Msk /*!< Overrun/Underrun */
11214 #define I2C_ISR_PECERR_Pos (11U)
11215 #define I2C_ISR_PECERR_Msk (0x1UL << I2C_ISR_PECERR_Pos) /*!< 0x00000800 */
11216 #define I2C_ISR_PECERR I2C_ISR_PECERR_Msk /*!< PEC error in reception */
11217 #define I2C_ISR_TIMEOUT_Pos (12U)
11218 #define I2C_ISR_TIMEOUT_Msk (0x1UL << I2C_ISR_TIMEOUT_Pos) /*!< 0x00001000 */
11219 #define I2C_ISR_TIMEOUT I2C_ISR_TIMEOUT_Msk /*!< Timeout or Tlow detection flag */
11220 #define I2C_ISR_ALERT_Pos (13U)
11221 #define I2C_ISR_ALERT_Msk (0x1UL << I2C_ISR_ALERT_Pos) /*!< 0x00002000 */
11222 #define I2C_ISR_ALERT I2C_ISR_ALERT_Msk /*!< SMBus alert */
11223 #define I2C_ISR_BUSY_Pos (15U)
11224 #define I2C_ISR_BUSY_Msk (0x1UL << I2C_ISR_BUSY_Pos) /*!< 0x00008000 */
11225 #define I2C_ISR_BUSY I2C_ISR_BUSY_Msk /*!< Bus busy */
11226 #define I2C_ISR_DIR_Pos (16U)
11227 #define I2C_ISR_DIR_Msk (0x1UL << I2C_ISR_DIR_Pos) /*!< 0x00010000 */
11228 #define I2C_ISR_DIR I2C_ISR_DIR_Msk /*!< Transfer direction (slave mode) */
11229 #define I2C_ISR_ADDCODE_Pos (17U)
11230 #define I2C_ISR_ADDCODE_Msk (0x7FUL << I2C_ISR_ADDCODE_Pos) /*!< 0x00FE0000 */
11231 #define I2C_ISR_ADDCODE I2C_ISR_ADDCODE_Msk /*!< Address match code (slave mode) */
11232
11233 /****************** Bit definition for I2C_ICR register *********************/
11234 #define I2C_ICR_ADDRCF_Pos (3U)
11235 #define I2C_ICR_ADDRCF_Msk (0x1UL << I2C_ICR_ADDRCF_Pos) /*!< 0x00000008 */
11236 #define I2C_ICR_ADDRCF I2C_ICR_ADDRCF_Msk /*!< Address matched clear flag */
11237 #define I2C_ICR_NACKCF_Pos (4U)
11238 #define I2C_ICR_NACKCF_Msk (0x1UL << I2C_ICR_NACKCF_Pos) /*!< 0x00000010 */
11239 #define I2C_ICR_NACKCF I2C_ICR_NACKCF_Msk /*!< NACK clear flag */
11240 #define I2C_ICR_STOPCF_Pos (5U)
11241 #define I2C_ICR_STOPCF_Msk (0x1UL << I2C_ICR_STOPCF_Pos) /*!< 0x00000020 */
11242 #define I2C_ICR_STOPCF I2C_ICR_STOPCF_Msk /*!< STOP detection clear flag */
11243 #define I2C_ICR_BERRCF_Pos (8U)
11244 #define I2C_ICR_BERRCF_Msk (0x1UL << I2C_ICR_BERRCF_Pos) /*!< 0x00000100 */
11245 #define I2C_ICR_BERRCF I2C_ICR_BERRCF_Msk /*!< Bus error clear flag */
11246 #define I2C_ICR_ARLOCF_Pos (9U)
11247 #define I2C_ICR_ARLOCF_Msk (0x1UL << I2C_ICR_ARLOCF_Pos) /*!< 0x00000200 */
11248 #define I2C_ICR_ARLOCF I2C_ICR_ARLOCF_Msk /*!< Arbitration lost clear flag */
11249 #define I2C_ICR_OVRCF_Pos (10U)
11250 #define I2C_ICR_OVRCF_Msk (0x1UL << I2C_ICR_OVRCF_Pos) /*!< 0x00000400 */
11251 #define I2C_ICR_OVRCF I2C_ICR_OVRCF_Msk /*!< Overrun/Underrun clear flag */
11252 #define I2C_ICR_PECCF_Pos (11U)
11253 #define I2C_ICR_PECCF_Msk (0x1UL << I2C_ICR_PECCF_Pos) /*!< 0x00000800 */
11254 #define I2C_ICR_PECCF I2C_ICR_PECCF_Msk /*!< PAC error clear flag */
11255 #define I2C_ICR_TIMOUTCF_Pos (12U)
11256 #define I2C_ICR_TIMOUTCF_Msk (0x1UL << I2C_ICR_TIMOUTCF_Pos) /*!< 0x00001000 */
11257 #define I2C_ICR_TIMOUTCF I2C_ICR_TIMOUTCF_Msk /*!< Timeout clear flag */
11258 #define I2C_ICR_ALERTCF_Pos (13U)
11259 #define I2C_ICR_ALERTCF_Msk (0x1UL << I2C_ICR_ALERTCF_Pos) /*!< 0x00002000 */
11260 #define I2C_ICR_ALERTCF I2C_ICR_ALERTCF_Msk /*!< Alert clear flag */
11261
11262 /****************** Bit definition for I2C_PECR register *********************/
11263 #define I2C_PECR_PEC_Pos (0U)
11264 #define I2C_PECR_PEC_Msk (0xFFUL << I2C_PECR_PEC_Pos) /*!< 0x000000FF */
11265 #define I2C_PECR_PEC I2C_PECR_PEC_Msk /*!< PEC register */
11266
11267 /****************** Bit definition for I2C_RXDR register *********************/
11268 #define I2C_RXDR_RXDATA_Pos (0U)
11269 #define I2C_RXDR_RXDATA_Msk (0xFFUL << I2C_RXDR_RXDATA_Pos) /*!< 0x000000FF */
11270 #define I2C_RXDR_RXDATA I2C_RXDR_RXDATA_Msk /*!< 8-bit receive data */
11271
11272 /****************** Bit definition for I2C_TXDR register *********************/
11273 #define I2C_TXDR_TXDATA_Pos (0U)
11274 #define I2C_TXDR_TXDATA_Msk (0xFFUL << I2C_TXDR_TXDATA_Pos) /*!< 0x000000FF */
11275 #define I2C_TXDR_TXDATA I2C_TXDR_TXDATA_Msk /*!< 8-bit transmit data */
11276
11277 /******************************************************************************/
11278 /* */
11279 /* Independent WATCHDOG */
11280 /* */
11281 /******************************************************************************/
11282 /******************* Bit definition for IWDG_KR register ********************/
11283 #define IWDG_KR_KEY_Pos (0U)
11284 #define IWDG_KR_KEY_Msk (0xFFFFUL << IWDG_KR_KEY_Pos) /*!< 0x0000FFFF */
11285 #define IWDG_KR_KEY IWDG_KR_KEY_Msk /*!<Key value (write only, read 0000h) */
11286
11287 /******************* Bit definition for IWDG_PR register ********************/
11288 #define IWDG_PR_PR_Pos (0U)
11289 #define IWDG_PR_PR_Msk (0x7UL << IWDG_PR_PR_Pos) /*!< 0x00000007 */
11290 #define IWDG_PR_PR IWDG_PR_PR_Msk /*!<PR[2:0] (Prescaler divider) */
11291 #define IWDG_PR_PR_0 (0x1UL << IWDG_PR_PR_Pos) /*!< 0x00000001 */
11292 #define IWDG_PR_PR_1 (0x2UL << IWDG_PR_PR_Pos) /*!< 0x00000002 */
11293 #define IWDG_PR_PR_2 (0x4UL << IWDG_PR_PR_Pos) /*!< 0x00000004 */
11294
11295 /******************* Bit definition for IWDG_RLR register *******************/
11296 #define IWDG_RLR_RL_Pos (0U)
11297 #define IWDG_RLR_RL_Msk (0xFFFUL << IWDG_RLR_RL_Pos) /*!< 0x00000FFF */
11298 #define IWDG_RLR_RL IWDG_RLR_RL_Msk /*!<Watchdog counter reload value */
11299
11300 /******************* Bit definition for IWDG_SR register ********************/
11301 #define IWDG_SR_PVU_Pos (0U)
11302 #define IWDG_SR_PVU_Msk (0x1UL << IWDG_SR_PVU_Pos) /*!< 0x00000001 */
11303 #define IWDG_SR_PVU IWDG_SR_PVU_Msk /*!< Watchdog prescaler value update */
11304 #define IWDG_SR_RVU_Pos (1U)
11305 #define IWDG_SR_RVU_Msk (0x1UL << IWDG_SR_RVU_Pos) /*!< 0x00000002 */
11306 #define IWDG_SR_RVU IWDG_SR_RVU_Msk /*!< Watchdog counter reload value update */
11307 #define IWDG_SR_WVU_Pos (2U)
11308 #define IWDG_SR_WVU_Msk (0x1UL << IWDG_SR_WVU_Pos) /*!< 0x00000004 */
11309 #define IWDG_SR_WVU IWDG_SR_WVU_Msk /*!< Watchdog counter window value update */
11310
11311 /******************* Bit definition for IWDG_KR register ********************/
11312 #define IWDG_WINR_WIN_Pos (0U)
11313 #define IWDG_WINR_WIN_Msk (0xFFFUL << IWDG_WINR_WIN_Pos) /*!< 0x00000FFF */
11314 #define IWDG_WINR_WIN IWDG_WINR_WIN_Msk /*!< Watchdog counter window value */
11315
11316 /******************************************************************************/
11317 /* */
11318 /* JPEG Encoder/Decoder */
11319 /* */
11320 /******************************************************************************/
11321 /******************** Bit definition for CONFR0 register ********************/
11322 #define JPEG_CONFR0_START_Pos (0U)
11323 #define JPEG_CONFR0_START_Msk (0x1UL << JPEG_CONFR0_START_Pos) /*!< 0x00000001 */
11324 #define JPEG_CONFR0_START JPEG_CONFR0_START_Msk /*!<Start/Stop bit */
11325
11326 /******************** Bit definition for CONFR1 register ********************/
11327 #define JPEG_CONFR1_NF_Pos (0U)
11328 #define JPEG_CONFR1_NF_Msk (0x3UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000003 */
11329 #define JPEG_CONFR1_NF JPEG_CONFR1_NF_Msk /*!<Number of color components */
11330 #define JPEG_CONFR1_NF_0 (0x1UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000001 */
11331 #define JPEG_CONFR1_NF_1 (0x2UL << JPEG_CONFR1_NF_Pos) /*!< 0x00000002 */
11332 #define JPEG_CONFR1_DE_Pos (3U)
11333 #define JPEG_CONFR1_DE_Msk (0x1UL << JPEG_CONFR1_DE_Pos) /*!< 0x00000008 */
11334 #define JPEG_CONFR1_DE JPEG_CONFR1_DE_Msk /*!<Decoding Enable */
11335 #define JPEG_CONFR1_COLORSPACE_Pos (4U)
11336 #define JPEG_CONFR1_COLORSPACE_Msk (0x3UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000030 */
11337 #define JPEG_CONFR1_COLORSPACE JPEG_CONFR1_COLORSPACE_Msk /*!<Color Space */
11338 #define JPEG_CONFR1_COLORSPACE_0 (0x1UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000010 */
11339 #define JPEG_CONFR1_COLORSPACE_1 (0x2UL << JPEG_CONFR1_COLORSPACE_Pos) /*!< 0x00000020 */
11340 #define JPEG_CONFR1_NS_Pos (6U)
11341 #define JPEG_CONFR1_NS_Msk (0x3UL << JPEG_CONFR1_NS_Pos) /*!< 0x000000C0 */
11342 #define JPEG_CONFR1_NS JPEG_CONFR1_NS_Msk /*!<Number of components for Scan */
11343 #define JPEG_CONFR1_NS_0 (0x1UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000040 */
11344 #define JPEG_CONFR1_NS_1 (0x2UL << JPEG_CONFR1_NS_Pos) /*!< 0x00000080 */
11345 #define JPEG_CONFR1_HDR_Pos (8U)
11346 #define JPEG_CONFR1_HDR_Msk (0x1UL << JPEG_CONFR1_HDR_Pos) /*!< 0x00000100 */
11347 #define JPEG_CONFR1_HDR JPEG_CONFR1_HDR_Msk /*!<Header Processing On/Off */
11348 #define JPEG_CONFR1_YSIZE_Pos (16U)
11349 #define JPEG_CONFR1_YSIZE_Msk (0xFFFFUL << JPEG_CONFR1_YSIZE_Pos) /*!< 0xFFFF0000 */
11350 #define JPEG_CONFR1_YSIZE JPEG_CONFR1_YSIZE_Msk /*!<Number of lines in source image */
11351
11352 /******************** Bit definition for CONFR2 register ********************/
11353 #define JPEG_CONFR2_NMCU_Pos (0U)
11354 #define JPEG_CONFR2_NMCU_Msk (0x3FFFFFFUL << JPEG_CONFR2_NMCU_Pos) /*!< 0x03FFFFFF */
11355 #define JPEG_CONFR2_NMCU JPEG_CONFR2_NMCU_Msk /*!<Number of MCU units minus 1 to encode */
11356
11357 /******************** Bit definition for CONFR3 register ********************/
11358 #define JPEG_CONFR3_XSIZE_Pos (16U)
11359 #define JPEG_CONFR3_XSIZE_Msk (0xFFFFUL << JPEG_CONFR3_XSIZE_Pos) /*!< 0xFFFF0000 */
11360 #define JPEG_CONFR3_XSIZE JPEG_CONFR3_XSIZE_Msk /*!<Number of pixels per line */
11361
11362 /******************** Bit definition for CONFR4 register ********************/
11363 #define JPEG_CONFR4_HD_Pos (0U)
11364 #define JPEG_CONFR4_HD_Msk (0x1UL << JPEG_CONFR4_HD_Pos) /*!< 0x00000001 */
11365 #define JPEG_CONFR4_HD JPEG_CONFR4_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11366 #define JPEG_CONFR4_HA_Pos (1U)
11367 #define JPEG_CONFR4_HA_Msk (0x1UL << JPEG_CONFR4_HA_Pos) /*!< 0x00000002 */
11368 #define JPEG_CONFR4_HA JPEG_CONFR4_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11369 #define JPEG_CONFR4_QT_Pos (2U)
11370 #define JPEG_CONFR4_QT_Msk (0x3UL << JPEG_CONFR4_QT_Pos) /*!< 0x0000000C */
11371 #define JPEG_CONFR4_QT JPEG_CONFR4_QT_Msk /*!<Selects quantization table associated with a color component */
11372 #define JPEG_CONFR4_QT_0 (0x1UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000004 */
11373 #define JPEG_CONFR4_QT_1 (0x2UL << JPEG_CONFR4_QT_Pos) /*!< 0x00000008 */
11374 #define JPEG_CONFR4_NB_Pos (4U)
11375 #define JPEG_CONFR4_NB_Msk (0xFUL << JPEG_CONFR4_NB_Pos) /*!< 0x000000F0 */
11376 #define JPEG_CONFR4_NB JPEG_CONFR4_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11377 #define JPEG_CONFR4_NB_0 (0x1UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000010 */
11378 #define JPEG_CONFR4_NB_1 (0x2UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000020 */
11379 #define JPEG_CONFR4_NB_2 (0x4UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000040 */
11380 #define JPEG_CONFR4_NB_3 (0x8UL << JPEG_CONFR4_NB_Pos) /*!< 0x00000080 */
11381 #define JPEG_CONFR4_VSF_Pos (8U)
11382 #define JPEG_CONFR4_VSF_Msk (0xFUL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000F00 */
11383 #define JPEG_CONFR4_VSF JPEG_CONFR4_VSF_Msk /*!<Vertical sampling factor for component 1 */
11384 #define JPEG_CONFR4_VSF_0 (0x1UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000100 */
11385 #define JPEG_CONFR4_VSF_1 (0x2UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000200 */
11386 #define JPEG_CONFR4_VSF_2 (0x4UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000400 */
11387 #define JPEG_CONFR4_VSF_3 (0x8UL << JPEG_CONFR4_VSF_Pos) /*!< 0x00000800 */
11388 #define JPEG_CONFR4_HSF_Pos (12U)
11389 #define JPEG_CONFR4_HSF_Msk (0xFUL << JPEG_CONFR4_HSF_Pos) /*!< 0x0000F000 */
11390 #define JPEG_CONFR4_HSF JPEG_CONFR4_HSF_Msk /*!<Horizontal sampling factor for component 1 */
11391 #define JPEG_CONFR4_HSF_0 (0x1UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00001000 */
11392 #define JPEG_CONFR4_HSF_1 (0x2UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00002000 */
11393 #define JPEG_CONFR4_HSF_2 (0x4UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00004000 */
11394 #define JPEG_CONFR4_HSF_3 (0x8UL << JPEG_CONFR4_HSF_Pos) /*!< 0x00008000 */
11395
11396 /******************** Bit definition for CONFR5 register ********************/
11397 #define JPEG_CONFR5_HD_Pos (0U)
11398 #define JPEG_CONFR5_HD_Msk (0x1UL << JPEG_CONFR5_HD_Pos) /*!< 0x00000001 */
11399 #define JPEG_CONFR5_HD JPEG_CONFR5_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11400 #define JPEG_CONFR5_HA_Pos (1U)
11401 #define JPEG_CONFR5_HA_Msk (0x1UL << JPEG_CONFR5_HA_Pos) /*!< 0x00000002 */
11402 #define JPEG_CONFR5_HA JPEG_CONFR5_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11403 #define JPEG_CONFR5_QT_Pos (2U)
11404 #define JPEG_CONFR5_QT_Msk (0x3UL << JPEG_CONFR5_QT_Pos) /*!< 0x0000000C */
11405 #define JPEG_CONFR5_QT JPEG_CONFR5_QT_Msk /*!<Selects quantization table associated with a color component */
11406 #define JPEG_CONFR5_QT_0 (0x1UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000004 */
11407 #define JPEG_CONFR5_QT_1 (0x2UL << JPEG_CONFR5_QT_Pos) /*!< 0x00000008 */
11408 #define JPEG_CONFR5_NB_Pos (4U)
11409 #define JPEG_CONFR5_NB_Msk (0xFUL << JPEG_CONFR5_NB_Pos) /*!< 0x000000F0 */
11410 #define JPEG_CONFR5_NB JPEG_CONFR5_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11411 #define JPEG_CONFR5_NB_0 (0x1UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000010 */
11412 #define JPEG_CONFR5_NB_1 (0x2UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000020 */
11413 #define JPEG_CONFR5_NB_2 (0x4UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000040 */
11414 #define JPEG_CONFR5_NB_3 (0x8UL << JPEG_CONFR5_NB_Pos) /*!< 0x00000080 */
11415 #define JPEG_CONFR5_VSF_Pos (8U)
11416 #define JPEG_CONFR5_VSF_Msk (0xFUL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000F00 */
11417 #define JPEG_CONFR5_VSF JPEG_CONFR5_VSF_Msk /*!<Vertical sampling factor for component 2 */
11418 #define JPEG_CONFR5_VSF_0 (0x1UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000100 */
11419 #define JPEG_CONFR5_VSF_1 (0x2UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000200 */
11420 #define JPEG_CONFR5_VSF_2 (0x4UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000400 */
11421 #define JPEG_CONFR5_VSF_3 (0x8UL << JPEG_CONFR5_VSF_Pos) /*!< 0x00000800 */
11422 #define JPEG_CONFR5_HSF_Pos (12U)
11423 #define JPEG_CONFR5_HSF_Msk (0xFUL << JPEG_CONFR5_HSF_Pos) /*!< 0x0000F000 */
11424 #define JPEG_CONFR5_HSF JPEG_CONFR5_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11425 #define JPEG_CONFR5_HSF_0 (0x1UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00001000 */
11426 #define JPEG_CONFR5_HSF_1 (0x2UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00002000 */
11427 #define JPEG_CONFR5_HSF_2 (0x4UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00004000 */
11428 #define JPEG_CONFR5_HSF_3 (0x8UL << JPEG_CONFR5_HSF_Pos) /*!< 0x00008000 */
11429
11430 /******************** Bit definition for CONFR6 register ********************/
11431 #define JPEG_CONFR6_HD_Pos (0U)
11432 #define JPEG_CONFR6_HD_Msk (0x1UL << JPEG_CONFR6_HD_Pos) /*!< 0x00000001 */
11433 #define JPEG_CONFR6_HD JPEG_CONFR6_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11434 #define JPEG_CONFR6_HA_Pos (1U)
11435 #define JPEG_CONFR6_HA_Msk (0x1UL << JPEG_CONFR6_HA_Pos) /*!< 0x00000002 */
11436 #define JPEG_CONFR6_HA JPEG_CONFR6_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11437 #define JPEG_CONFR6_QT_Pos (2U)
11438 #define JPEG_CONFR6_QT_Msk (0x3UL << JPEG_CONFR6_QT_Pos) /*!< 0x0000000C */
11439 #define JPEG_CONFR6_QT JPEG_CONFR6_QT_Msk /*!<Selects quantization table associated with a color component */
11440 #define JPEG_CONFR6_QT_0 (0x1UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000004 */
11441 #define JPEG_CONFR6_QT_1 (0x2UL << JPEG_CONFR6_QT_Pos) /*!< 0x00000008 */
11442 #define JPEG_CONFR6_NB_Pos (4U)
11443 #define JPEG_CONFR6_NB_Msk (0xFUL << JPEG_CONFR6_NB_Pos) /*!< 0x000000F0 */
11444 #define JPEG_CONFR6_NB JPEG_CONFR6_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11445 #define JPEG_CONFR6_NB_0 (0x1UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000010 */
11446 #define JPEG_CONFR6_NB_1 (0x2UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000020 */
11447 #define JPEG_CONFR6_NB_2 (0x4UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000040 */
11448 #define JPEG_CONFR6_NB_3 (0x8UL << JPEG_CONFR6_NB_Pos) /*!< 0x00000080 */
11449 #define JPEG_CONFR6_VSF_Pos (8U)
11450 #define JPEG_CONFR6_VSF_Msk (0xFUL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000F00 */
11451 #define JPEG_CONFR6_VSF JPEG_CONFR6_VSF_Msk /*!<Vertical sampling factor for component 2 */
11452 #define JPEG_CONFR6_VSF_0 (0x1UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000100 */
11453 #define JPEG_CONFR6_VSF_1 (0x2UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000200 */
11454 #define JPEG_CONFR6_VSF_2 (0x4UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000400 */
11455 #define JPEG_CONFR6_VSF_3 (0x8UL << JPEG_CONFR6_VSF_Pos) /*!< 0x00000800 */
11456 #define JPEG_CONFR6_HSF_Pos (12U)
11457 #define JPEG_CONFR6_HSF_Msk (0xFUL << JPEG_CONFR6_HSF_Pos) /*!< 0x0000F000 */
11458 #define JPEG_CONFR6_HSF JPEG_CONFR6_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11459 #define JPEG_CONFR6_HSF_0 (0x1UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00001000 */
11460 #define JPEG_CONFR6_HSF_1 (0x2UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00002000 */
11461 #define JPEG_CONFR6_HSF_2 (0x4UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00004000 */
11462 #define JPEG_CONFR6_HSF_3 (0x8UL << JPEG_CONFR6_HSF_Pos) /*!< 0x00008000 */
11463
11464 /******************** Bit definition for CONFR7 register ********************/
11465 #define JPEG_CONFR7_HD_Pos (0U)
11466 #define JPEG_CONFR7_HD_Msk (0x1UL << JPEG_CONFR7_HD_Pos) /*!< 0x00000001 */
11467 #define JPEG_CONFR7_HD JPEG_CONFR7_HD_Msk /*!<Selects the Huffman table for encoding the DC coefficients */
11468 #define JPEG_CONFR7_HA_Pos (1U)
11469 #define JPEG_CONFR7_HA_Msk (0x1UL << JPEG_CONFR7_HA_Pos) /*!< 0x00000002 */
11470 #define JPEG_CONFR7_HA JPEG_CONFR7_HA_Msk /*!<Selects the Huffman table for encoding the AC coefficients */
11471 #define JPEG_CONFR7_QT_Pos (2U)
11472 #define JPEG_CONFR7_QT_Msk (0x3UL << JPEG_CONFR7_QT_Pos) /*!< 0x0000000C */
11473 #define JPEG_CONFR7_QT JPEG_CONFR7_QT_Msk /*!<Selects quantization table associated with a color component */
11474 #define JPEG_CONFR7_QT_0 (0x1UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000004 */
11475 #define JPEG_CONFR7_QT_1 (0x2UL << JPEG_CONFR7_QT_Pos) /*!< 0x00000008 */
11476 #define JPEG_CONFR7_NB_Pos (4U)
11477 #define JPEG_CONFR7_NB_Msk (0xFUL << JPEG_CONFR7_NB_Pos) /*!< 0x000000F0 */
11478 #define JPEG_CONFR7_NB JPEG_CONFR7_NB_Msk /*!<Number of data units minus 1 that belong to a particular color in the MCU */
11479 #define JPEG_CONFR7_NB_0 (0x1UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000010 */
11480 #define JPEG_CONFR7_NB_1 (0x2UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000020 */
11481 #define JPEG_CONFR7_NB_2 (0x4UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000040 */
11482 #define JPEG_CONFR7_NB_3 (0x8UL << JPEG_CONFR7_NB_Pos) /*!< 0x00000080 */
11483 #define JPEG_CONFR7_VSF_Pos (8U)
11484 #define JPEG_CONFR7_VSF_Msk (0xFUL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000F00 */
11485 #define JPEG_CONFR7_VSF JPEG_CONFR7_VSF_Msk /*!<Vertical sampling factor for component 2 */
11486 #define JPEG_CONFR7_VSF_0 (0x1UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000100 */
11487 #define JPEG_CONFR7_VSF_1 (0x2UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000200 */
11488 #define JPEG_CONFR7_VSF_2 (0x4UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000400 */
11489 #define JPEG_CONFR7_VSF_3 (0x8UL << JPEG_CONFR7_VSF_Pos) /*!< 0x00000800 */
11490 #define JPEG_CONFR7_HSF_Pos (12U)
11491 #define JPEG_CONFR7_HSF_Msk (0xFUL << JPEG_CONFR7_HSF_Pos) /*!< 0x0000F000 */
11492 #define JPEG_CONFR7_HSF JPEG_CONFR7_HSF_Msk /*!<Horizontal sampling factor for component 2 */
11493 #define JPEG_CONFR7_HSF_0 (0x1UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00001000 */
11494 #define JPEG_CONFR7_HSF_1 (0x2UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00002000 */
11495 #define JPEG_CONFR7_HSF_2 (0x4UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00004000 */
11496 #define JPEG_CONFR7_HSF_3 (0x8UL << JPEG_CONFR7_HSF_Pos) /*!< 0x00008000 */
11497
11498 /******************** Bit definition for CR register ********************/
11499 #define JPEG_CR_JCEN_Pos (0U)
11500 #define JPEG_CR_JCEN_Msk (0x1UL << JPEG_CR_JCEN_Pos) /*!< 0x00000001 */
11501 #define JPEG_CR_JCEN JPEG_CR_JCEN_Msk /*!<Enable the JPEG Codec Core */
11502 #define JPEG_CR_IFTIE_Pos (1U)
11503 #define JPEG_CR_IFTIE_Msk (0x1UL << JPEG_CR_IFTIE_Pos) /*!< 0x00000002 */
11504 #define JPEG_CR_IFTIE JPEG_CR_IFTIE_Msk /*!<Input FIFO Threshold Interrupt Enable */
11505 #define JPEG_CR_IFNFIE_Pos (2U)
11506 #define JPEG_CR_IFNFIE_Msk (0x1UL << JPEG_CR_IFNFIE_Pos) /*!< 0x00000004 */
11507 #define JPEG_CR_IFNFIE JPEG_CR_IFNFIE_Msk /*!<Input FIFO Not Full Interrupt Enable */
11508 #define JPEG_CR_OFTIE_Pos (3U)
11509 #define JPEG_CR_OFTIE_Msk (0x1UL << JPEG_CR_OFTIE_Pos) /*!< 0x00000008 */
11510 #define JPEG_CR_OFTIE JPEG_CR_OFTIE_Msk /*!<Output FIFO Threshold Interrupt Enable */
11511 #define JPEG_CR_OFNEIE_Pos (4U)
11512 #define JPEG_CR_OFNEIE_Msk (0x1UL << JPEG_CR_OFNEIE_Pos) /*!< 0x00000010 */
11513 #define JPEG_CR_OFNEIE JPEG_CR_OFNEIE_Msk /*!<Output FIFO Not Empty Interrupt Enable */
11514 #define JPEG_CR_EOCIE_Pos (5U)
11515 #define JPEG_CR_EOCIE_Msk (0x1UL << JPEG_CR_EOCIE_Pos) /*!< 0x00000020 */
11516 #define JPEG_CR_EOCIE JPEG_CR_EOCIE_Msk /*!<End of Conversion Interrupt Enable */
11517 #define JPEG_CR_HPDIE_Pos (6U)
11518 #define JPEG_CR_HPDIE_Msk (0x1UL << JPEG_CR_HPDIE_Pos) /*!< 0x00000040 */
11519 #define JPEG_CR_HPDIE JPEG_CR_HPDIE_Msk /*!<Header Parsing Done Interrupt Enable */
11520 #define JPEG_CR_IFF_Pos (13U)
11521 #define JPEG_CR_IFF_Msk (0x1UL << JPEG_CR_IFF_Pos) /*!< 0x00002000 */
11522 #define JPEG_CR_IFF JPEG_CR_IFF_Msk /*!<Flush the input FIFO */
11523 #define JPEG_CR_OFF_Pos (14U)
11524 #define JPEG_CR_OFF_Msk (0x1UL << JPEG_CR_OFF_Pos) /*!< 0x00004000 */
11525 #define JPEG_CR_OFF JPEG_CR_OFF_Msk /*!<Flush the output FIFO */
11526
11527 /******************** Bit definition for SR register ********************/
11528 #define JPEG_SR_IFTF_Pos (1U)
11529 #define JPEG_SR_IFTF_Msk (0x1UL << JPEG_SR_IFTF_Pos) /*!< 0x00000002 */
11530 #define JPEG_SR_IFTF JPEG_SR_IFTF_Msk /*!<Input FIFO is not full and is bellow its threshold flag */
11531 #define JPEG_SR_IFNFF_Pos (2U)
11532 #define JPEG_SR_IFNFF_Msk (0x1UL << JPEG_SR_IFNFF_Pos) /*!< 0x00000004 */
11533 #define JPEG_SR_IFNFF JPEG_SR_IFNFF_Msk /*!<Input FIFO Not Full Flag, a data can be written */
11534 #define JPEG_SR_OFTF_Pos (3U)
11535 #define JPEG_SR_OFTF_Msk (0x1UL << JPEG_SR_OFTF_Pos) /*!< 0x00000008 */
11536 #define JPEG_SR_OFTF JPEG_SR_OFTF_Msk /*!<Output FIFO is not empty and has reach its threshold */
11537 #define JPEG_SR_OFNEF_Pos (4U)
11538 #define JPEG_SR_OFNEF_Msk (0x1UL << JPEG_SR_OFNEF_Pos) /*!< 0x00000010 */
11539 #define JPEG_SR_OFNEF JPEG_SR_OFNEF_Msk /*!<Output FIFO is not empty, a data is available */
11540 #define JPEG_SR_EOCF_Pos (5U)
11541 #define JPEG_SR_EOCF_Msk (0x1UL << JPEG_SR_EOCF_Pos) /*!< 0x00000020 */
11542 #define JPEG_SR_EOCF JPEG_SR_EOCF_Msk /*!<JPEG Codec core has finished the encoding or the decoding process and than last data has been sent to the output FIFO */
11543 #define JPEG_SR_HPDF_Pos (6U)
11544 #define JPEG_SR_HPDF_Msk (0x1UL << JPEG_SR_HPDF_Pos) /*!< 0x00000040 */
11545 #define JPEG_SR_HPDF JPEG_SR_HPDF_Msk /*!<JPEG Codec has finished the parsing of the headers and the internal registers have been updated */
11546 #define JPEG_SR_COF_Pos (7U)
11547 #define JPEG_SR_COF_Msk (0x1UL << JPEG_SR_COF_Pos) /*!< 0x00000080 */
11548 #define JPEG_SR_COF JPEG_SR_COF_Msk /*!<JPEG Codec operation on going flag */
11549
11550 /******************** Bit definition for CFR register ********************/
11551 #define JPEG_CFR_CEOCF_Pos (4U)
11552 #define JPEG_CFR_CEOCF_Msk (0x1UL << JPEG_CFR_CEOCF_Pos) /*!< 0x00000010 */
11553 #define JPEG_CFR_CEOCF JPEG_CFR_CEOCF_Msk /*!<Clear End of Conversion Flag */
11554 #define JPEG_CFR_CHPDF_Pos (5U)
11555 #define JPEG_CFR_CHPDF_Msk (0x1UL << JPEG_CFR_CHPDF_Pos) /*!< 0x00000020 */
11556 #define JPEG_CFR_CHPDF JPEG_CFR_CHPDF_Msk /*!<Clear Header Parsing Done Flag */
11557
11558 /******************** Bit definition for DIR register ********************/
11559 #define JPEG_DIR_DATAIN_Pos (0U)
11560 #define JPEG_DIR_DATAIN_Msk (0xFFFFFFFFUL << JPEG_DIR_DATAIN_Pos) /*!< 0xFFFFFFFF */
11561 #define JPEG_DIR_DATAIN JPEG_DIR_DATAIN_Msk /*!<Data Input FIFO */
11562
11563 /******************** Bit definition for DOR register ********************/
11564 #define JPEG_DOR_DATAOUT_Pos (0U)
11565 #define JPEG_DOR_DATAOUT_Msk (0xFFFFFFFFUL << JPEG_DOR_DATAOUT_Pos) /*!< 0xFFFFFFFF */
11566 #define JPEG_DOR_DATAOUT JPEG_DOR_DATAOUT_Msk /*!<Data Output FIFO */
11567
11568 /******************************************************************************/
11569 /* */
11570 /* LCD-TFT Display Controller (LTDC) */
11571 /* */
11572 /******************************************************************************/
11573
11574 /******************** Bit definition for LTDC_SSCR register *****************/
11575
11576 #define LTDC_SSCR_VSH_Pos (0U)
11577 #define LTDC_SSCR_VSH_Msk (0x7FFUL << LTDC_SSCR_VSH_Pos) /*!< 0x000007FF */
11578 #define LTDC_SSCR_VSH LTDC_SSCR_VSH_Msk /*!< Vertical Synchronization Height */
11579 #define LTDC_SSCR_HSW_Pos (16U)
11580 #define LTDC_SSCR_HSW_Msk (0xFFFUL << LTDC_SSCR_HSW_Pos) /*!< 0x0FFF0000 */
11581 #define LTDC_SSCR_HSW LTDC_SSCR_HSW_Msk /*!< Horizontal Synchronization Width */
11582
11583 /******************** Bit definition for LTDC_BPCR register *****************/
11584
11585 #define LTDC_BPCR_AVBP_Pos (0U)
11586 #define LTDC_BPCR_AVBP_Msk (0x7FFUL << LTDC_BPCR_AVBP_Pos) /*!< 0x000007FF */
11587 #define LTDC_BPCR_AVBP LTDC_BPCR_AVBP_Msk /*!< Accumulated Vertical Back Porch */
11588 #define LTDC_BPCR_AHBP_Pos (16U)
11589 #define LTDC_BPCR_AHBP_Msk (0xFFFUL << LTDC_BPCR_AHBP_Pos) /*!< 0x0FFF0000 */
11590 #define LTDC_BPCR_AHBP LTDC_BPCR_AHBP_Msk /*!< Accumulated Horizontal Back Porch */
11591
11592 /******************** Bit definition for LTDC_AWCR register *****************/
11593
11594 #define LTDC_AWCR_AAH_Pos (0U)
11595 #define LTDC_AWCR_AAH_Msk (0x7FFUL << LTDC_AWCR_AAH_Pos) /*!< 0x000007FF */
11596 #define LTDC_AWCR_AAH LTDC_AWCR_AAH_Msk /*!< Accumulated Active heigh */
11597 #define LTDC_AWCR_AAW_Pos (16U)
11598 #define LTDC_AWCR_AAW_Msk (0xFFFUL << LTDC_AWCR_AAW_Pos) /*!< 0x0FFF0000 */
11599 #define LTDC_AWCR_AAW LTDC_AWCR_AAW_Msk /*!< Accumulated Active Width */
11600
11601 /******************** Bit definition for LTDC_TWCR register *****************/
11602
11603 #define LTDC_TWCR_TOTALH_Pos (0U)
11604 #define LTDC_TWCR_TOTALH_Msk (0x7FFUL << LTDC_TWCR_TOTALH_Pos) /*!< 0x000007FF */
11605 #define LTDC_TWCR_TOTALH LTDC_TWCR_TOTALH_Msk /*!< Total Heigh */
11606 #define LTDC_TWCR_TOTALW_Pos (16U)
11607 #define LTDC_TWCR_TOTALW_Msk (0xFFFUL << LTDC_TWCR_TOTALW_Pos) /*!< 0x0FFF0000 */
11608 #define LTDC_TWCR_TOTALW LTDC_TWCR_TOTALW_Msk /*!< Total Width */
11609
11610 /******************** Bit definition for LTDC_GCR register ******************/
11611
11612 #define LTDC_GCR_LTDCEN_Pos (0U)
11613 #define LTDC_GCR_LTDCEN_Msk (0x1UL << LTDC_GCR_LTDCEN_Pos) /*!< 0x00000001 */
11614 #define LTDC_GCR_LTDCEN LTDC_GCR_LTDCEN_Msk /*!< LCD-TFT controller enable bit */
11615 #define LTDC_GCR_DBW_Pos (4U)
11616 #define LTDC_GCR_DBW_Msk (0x7UL << LTDC_GCR_DBW_Pos) /*!< 0x00000070 */
11617 #define LTDC_GCR_DBW LTDC_GCR_DBW_Msk /*!< Dither Blue Width */
11618 #define LTDC_GCR_DGW_Pos (8U)
11619 #define LTDC_GCR_DGW_Msk (0x7UL << LTDC_GCR_DGW_Pos) /*!< 0x00000700 */
11620 #define LTDC_GCR_DGW LTDC_GCR_DGW_Msk /*!< Dither Green Width */
11621 #define LTDC_GCR_DRW_Pos (12U)
11622 #define LTDC_GCR_DRW_Msk (0x7UL << LTDC_GCR_DRW_Pos) /*!< 0x00007000 */
11623 #define LTDC_GCR_DRW LTDC_GCR_DRW_Msk /*!< Dither Red Width */
11624 #define LTDC_GCR_DEN_Pos (16U)
11625 #define LTDC_GCR_DEN_Msk (0x1UL << LTDC_GCR_DEN_Pos) /*!< 0x00010000 */
11626 #define LTDC_GCR_DEN LTDC_GCR_DEN_Msk /*!< Dither Enable */
11627 #define LTDC_GCR_PCPOL_Pos (28U)
11628 #define LTDC_GCR_PCPOL_Msk (0x1UL << LTDC_GCR_PCPOL_Pos) /*!< 0x10000000 */
11629 #define LTDC_GCR_PCPOL LTDC_GCR_PCPOL_Msk /*!< Pixel Clock Polarity */
11630 #define LTDC_GCR_DEPOL_Pos (29U)
11631 #define LTDC_GCR_DEPOL_Msk (0x1UL << LTDC_GCR_DEPOL_Pos) /*!< 0x20000000 */
11632 #define LTDC_GCR_DEPOL LTDC_GCR_DEPOL_Msk /*!< Data Enable Polarity */
11633 #define LTDC_GCR_VSPOL_Pos (30U)
11634 #define LTDC_GCR_VSPOL_Msk (0x1UL << LTDC_GCR_VSPOL_Pos) /*!< 0x40000000 */
11635 #define LTDC_GCR_VSPOL LTDC_GCR_VSPOL_Msk /*!< Vertical Synchronization Polarity */
11636 #define LTDC_GCR_HSPOL_Pos (31U)
11637 #define LTDC_GCR_HSPOL_Msk (0x1UL << LTDC_GCR_HSPOL_Pos) /*!< 0x80000000 */
11638 #define LTDC_GCR_HSPOL LTDC_GCR_HSPOL_Msk /*!< Horizontal Synchronization Polarity */
11639
11640
11641 /******************** Bit definition for LTDC_SRCR register *****************/
11642
11643 #define LTDC_SRCR_IMR_Pos (0U)
11644 #define LTDC_SRCR_IMR_Msk (0x1UL << LTDC_SRCR_IMR_Pos) /*!< 0x00000001 */
11645 #define LTDC_SRCR_IMR LTDC_SRCR_IMR_Msk /*!< Immediate Reload */
11646 #define LTDC_SRCR_VBR_Pos (1U)
11647 #define LTDC_SRCR_VBR_Msk (0x1UL << LTDC_SRCR_VBR_Pos) /*!< 0x00000002 */
11648 #define LTDC_SRCR_VBR LTDC_SRCR_VBR_Msk /*!< Vertical Blanking Reload */
11649
11650 /******************** Bit definition for LTDC_BCCR register *****************/
11651
11652 #define LTDC_BCCR_BCBLUE_Pos (0U)
11653 #define LTDC_BCCR_BCBLUE_Msk (0xFFUL << LTDC_BCCR_BCBLUE_Pos) /*!< 0x000000FF */
11654 #define LTDC_BCCR_BCBLUE LTDC_BCCR_BCBLUE_Msk /*!< Background Blue value */
11655 #define LTDC_BCCR_BCGREEN_Pos (8U)
11656 #define LTDC_BCCR_BCGREEN_Msk (0xFFUL << LTDC_BCCR_BCGREEN_Pos) /*!< 0x0000FF00 */
11657 #define LTDC_BCCR_BCGREEN LTDC_BCCR_BCGREEN_Msk /*!< Background Green value */
11658 #define LTDC_BCCR_BCRED_Pos (16U)
11659 #define LTDC_BCCR_BCRED_Msk (0xFFUL << LTDC_BCCR_BCRED_Pos) /*!< 0x00FF0000 */
11660 #define LTDC_BCCR_BCRED LTDC_BCCR_BCRED_Msk /*!< Background Red value */
11661
11662 /******************** Bit definition for LTDC_IER register ******************/
11663
11664 #define LTDC_IER_LIE_Pos (0U)
11665 #define LTDC_IER_LIE_Msk (0x1UL << LTDC_IER_LIE_Pos) /*!< 0x00000001 */
11666 #define LTDC_IER_LIE LTDC_IER_LIE_Msk /*!< Line Interrupt Enable */
11667 #define LTDC_IER_FUIE_Pos (1U)
11668 #define LTDC_IER_FUIE_Msk (0x1UL << LTDC_IER_FUIE_Pos) /*!< 0x00000002 */
11669 #define LTDC_IER_FUIE LTDC_IER_FUIE_Msk /*!< FIFO Underrun Interrupt Enable */
11670 #define LTDC_IER_TERRIE_Pos (2U)
11671 #define LTDC_IER_TERRIE_Msk (0x1UL << LTDC_IER_TERRIE_Pos) /*!< 0x00000004 */
11672 #define LTDC_IER_TERRIE LTDC_IER_TERRIE_Msk /*!< Transfer Error Interrupt Enable */
11673 #define LTDC_IER_RRIE_Pos (3U)
11674 #define LTDC_IER_RRIE_Msk (0x1UL << LTDC_IER_RRIE_Pos) /*!< 0x00000008 */
11675 #define LTDC_IER_RRIE LTDC_IER_RRIE_Msk /*!< Register Reload interrupt enable */
11676
11677 /******************** Bit definition for LTDC_ISR register ******************/
11678
11679 #define LTDC_ISR_LIF_Pos (0U)
11680 #define LTDC_ISR_LIF_Msk (0x1UL << LTDC_ISR_LIF_Pos) /*!< 0x00000001 */
11681 #define LTDC_ISR_LIF LTDC_ISR_LIF_Msk /*!< Line Interrupt Flag */
11682 #define LTDC_ISR_FUIF_Pos (1U)
11683 #define LTDC_ISR_FUIF_Msk (0x1UL << LTDC_ISR_FUIF_Pos) /*!< 0x00000002 */
11684 #define LTDC_ISR_FUIF LTDC_ISR_FUIF_Msk /*!< FIFO Underrun Interrupt Flag */
11685 #define LTDC_ISR_TERRIF_Pos (2U)
11686 #define LTDC_ISR_TERRIF_Msk (0x1UL << LTDC_ISR_TERRIF_Pos) /*!< 0x00000004 */
11687 #define LTDC_ISR_TERRIF LTDC_ISR_TERRIF_Msk /*!< Transfer Error Interrupt Flag */
11688 #define LTDC_ISR_RRIF_Pos (3U)
11689 #define LTDC_ISR_RRIF_Msk (0x1UL << LTDC_ISR_RRIF_Pos) /*!< 0x00000008 */
11690 #define LTDC_ISR_RRIF LTDC_ISR_RRIF_Msk /*!< Register Reload interrupt Flag */
11691
11692 /******************** Bit definition for LTDC_ICR register ******************/
11693
11694 #define LTDC_ICR_CLIF_Pos (0U)
11695 #define LTDC_ICR_CLIF_Msk (0x1UL << LTDC_ICR_CLIF_Pos) /*!< 0x00000001 */
11696 #define LTDC_ICR_CLIF LTDC_ICR_CLIF_Msk /*!< Clears the Line Interrupt Flag */
11697 #define LTDC_ICR_CFUIF_Pos (1U)
11698 #define LTDC_ICR_CFUIF_Msk (0x1UL << LTDC_ICR_CFUIF_Pos) /*!< 0x00000002 */
11699 #define LTDC_ICR_CFUIF LTDC_ICR_CFUIF_Msk /*!< Clears the FIFO Underrun Interrupt Flag */
11700 #define LTDC_ICR_CTERRIF_Pos (2U)
11701 #define LTDC_ICR_CTERRIF_Msk (0x1UL << LTDC_ICR_CTERRIF_Pos) /*!< 0x00000004 */
11702 #define LTDC_ICR_CTERRIF LTDC_ICR_CTERRIF_Msk /*!< Clears the Transfer Error Interrupt Flag */
11703 #define LTDC_ICR_CRRIF_Pos (3U)
11704 #define LTDC_ICR_CRRIF_Msk (0x1UL << LTDC_ICR_CRRIF_Pos) /*!< 0x00000008 */
11705 #define LTDC_ICR_CRRIF LTDC_ICR_CRRIF_Msk /*!< Clears Register Reload interrupt Flag */
11706
11707 /******************** Bit definition for LTDC_LIPCR register ****************/
11708
11709 #define LTDC_LIPCR_LIPOS_Pos (0U)
11710 #define LTDC_LIPCR_LIPOS_Msk (0x7FFUL << LTDC_LIPCR_LIPOS_Pos) /*!< 0x000007FF */
11711 #define LTDC_LIPCR_LIPOS LTDC_LIPCR_LIPOS_Msk /*!< Line Interrupt Position */
11712
11713 /******************** Bit definition for LTDC_CPSR register *****************/
11714
11715 #define LTDC_CPSR_CYPOS_Pos (0U)
11716 #define LTDC_CPSR_CYPOS_Msk (0xFFFFUL << LTDC_CPSR_CYPOS_Pos) /*!< 0x0000FFFF */
11717 #define LTDC_CPSR_CYPOS LTDC_CPSR_CYPOS_Msk /*!< Current Y Position */
11718 #define LTDC_CPSR_CXPOS_Pos (16U)
11719 #define LTDC_CPSR_CXPOS_Msk (0xFFFFUL << LTDC_CPSR_CXPOS_Pos) /*!< 0xFFFF0000 */
11720 #define LTDC_CPSR_CXPOS LTDC_CPSR_CXPOS_Msk /*!< Current X Position */
11721
11722 /******************** Bit definition for LTDC_CDSR register *****************/
11723
11724 #define LTDC_CDSR_VDES_Pos (0U)
11725 #define LTDC_CDSR_VDES_Msk (0x1UL << LTDC_CDSR_VDES_Pos) /*!< 0x00000001 */
11726 #define LTDC_CDSR_VDES LTDC_CDSR_VDES_Msk /*!< Vertical Data Enable Status */
11727 #define LTDC_CDSR_HDES_Pos (1U)
11728 #define LTDC_CDSR_HDES_Msk (0x1UL << LTDC_CDSR_HDES_Pos) /*!< 0x00000002 */
11729 #define LTDC_CDSR_HDES LTDC_CDSR_HDES_Msk /*!< Horizontal Data Enable Status */
11730 #define LTDC_CDSR_VSYNCS_Pos (2U)
11731 #define LTDC_CDSR_VSYNCS_Msk (0x1UL << LTDC_CDSR_VSYNCS_Pos) /*!< 0x00000004 */
11732 #define LTDC_CDSR_VSYNCS LTDC_CDSR_VSYNCS_Msk /*!< Vertical Synchronization Status */
11733 #define LTDC_CDSR_HSYNCS_Pos (3U)
11734 #define LTDC_CDSR_HSYNCS_Msk (0x1UL << LTDC_CDSR_HSYNCS_Pos) /*!< 0x00000008 */
11735 #define LTDC_CDSR_HSYNCS LTDC_CDSR_HSYNCS_Msk /*!< Horizontal Synchronization Status */
11736
11737 /******************** Bit definition for LTDC_LxCR register *****************/
11738
11739 #define LTDC_LxCR_LEN_Pos (0U)
11740 #define LTDC_LxCR_LEN_Msk (0x1UL << LTDC_LxCR_LEN_Pos) /*!< 0x00000001 */
11741 #define LTDC_LxCR_LEN LTDC_LxCR_LEN_Msk /*!< Layer Enable */
11742 #define LTDC_LxCR_COLKEN_Pos (1U)
11743 #define LTDC_LxCR_COLKEN_Msk (0x1UL << LTDC_LxCR_COLKEN_Pos) /*!< 0x00000002 */
11744 #define LTDC_LxCR_COLKEN LTDC_LxCR_COLKEN_Msk /*!< Color Keying Enable */
11745 #define LTDC_LxCR_CLUTEN_Pos (4U)
11746 #define LTDC_LxCR_CLUTEN_Msk (0x1UL << LTDC_LxCR_CLUTEN_Pos) /*!< 0x00000010 */
11747 #define LTDC_LxCR_CLUTEN LTDC_LxCR_CLUTEN_Msk /*!< Color Lockup Table Enable */
11748
11749 /******************** Bit definition for LTDC_LxWHPCR register **************/
11750
11751 #define LTDC_LxWHPCR_WHSTPOS_Pos (0U)
11752 #define LTDC_LxWHPCR_WHSTPOS_Msk (0xFFFUL << LTDC_LxWHPCR_WHSTPOS_Pos) /*!< 0x00000FFF */
11753 #define LTDC_LxWHPCR_WHSTPOS LTDC_LxWHPCR_WHSTPOS_Msk /*!< Window Horizontal Start Position */
11754 #define LTDC_LxWHPCR_WHSPPOS_Pos (16U)
11755 #define LTDC_LxWHPCR_WHSPPOS_Msk (0xFFFFUL << LTDC_LxWHPCR_WHSPPOS_Pos) /*!< 0xFFFF0000 */
11756 #define LTDC_LxWHPCR_WHSPPOS LTDC_LxWHPCR_WHSPPOS_Msk /*!< Window Horizontal Stop Position */
11757
11758 /******************** Bit definition for LTDC_LxWVPCR register **************/
11759
11760 #define LTDC_LxWVPCR_WVSTPOS_Pos (0U)
11761 #define LTDC_LxWVPCR_WVSTPOS_Msk (0xFFFUL << LTDC_LxWVPCR_WVSTPOS_Pos) /*!< 0x00000FFF */
11762 #define LTDC_LxWVPCR_WVSTPOS LTDC_LxWVPCR_WVSTPOS_Msk /*!< Window Vertical Start Position */
11763 #define LTDC_LxWVPCR_WVSPPOS_Pos (16U)
11764 #define LTDC_LxWVPCR_WVSPPOS_Msk (0xFFFFUL << LTDC_LxWVPCR_WVSPPOS_Pos) /*!< 0xFFFF0000 */
11765 #define LTDC_LxWVPCR_WVSPPOS LTDC_LxWVPCR_WVSPPOS_Msk /*!< Window Vertical Stop Position */
11766
11767 /******************** Bit definition for LTDC_LxCKCR register ***************/
11768
11769 #define LTDC_LxCKCR_CKBLUE_Pos (0U)
11770 #define LTDC_LxCKCR_CKBLUE_Msk (0xFFUL << LTDC_LxCKCR_CKBLUE_Pos) /*!< 0x000000FF */
11771 #define LTDC_LxCKCR_CKBLUE LTDC_LxCKCR_CKBLUE_Msk /*!< Color Key Blue value */
11772 #define LTDC_LxCKCR_CKGREEN_Pos (8U)
11773 #define LTDC_LxCKCR_CKGREEN_Msk (0xFFUL << LTDC_LxCKCR_CKGREEN_Pos) /*!< 0x0000FF00 */
11774 #define LTDC_LxCKCR_CKGREEN LTDC_LxCKCR_CKGREEN_Msk /*!< Color Key Green value */
11775 #define LTDC_LxCKCR_CKRED_Pos (16U)
11776 #define LTDC_LxCKCR_CKRED_Msk (0xFFUL << LTDC_LxCKCR_CKRED_Pos) /*!< 0x00FF0000 */
11777 #define LTDC_LxCKCR_CKRED LTDC_LxCKCR_CKRED_Msk /*!< Color Key Red value */
11778
11779 /******************** Bit definition for LTDC_LxPFCR register ***************/
11780
11781 #define LTDC_LxPFCR_PF_Pos (0U)
11782 #define LTDC_LxPFCR_PF_Msk (0x7UL << LTDC_LxPFCR_PF_Pos) /*!< 0x00000007 */
11783 #define LTDC_LxPFCR_PF LTDC_LxPFCR_PF_Msk /*!< Pixel Format */
11784
11785 /******************** Bit definition for LTDC_LxCACR register ***************/
11786
11787 #define LTDC_LxCACR_CONSTA_Pos (0U)
11788 #define LTDC_LxCACR_CONSTA_Msk (0xFFUL << LTDC_LxCACR_CONSTA_Pos) /*!< 0x000000FF */
11789 #define LTDC_LxCACR_CONSTA LTDC_LxCACR_CONSTA_Msk /*!< Constant Alpha */
11790
11791 /******************** Bit definition for LTDC_LxDCCR register ***************/
11792
11793 #define LTDC_LxDCCR_DCBLUE_Pos (0U)
11794 #define LTDC_LxDCCR_DCBLUE_Msk (0xFFUL << LTDC_LxDCCR_DCBLUE_Pos) /*!< 0x000000FF */
11795 #define LTDC_LxDCCR_DCBLUE LTDC_LxDCCR_DCBLUE_Msk /*!< Default Color Blue */
11796 #define LTDC_LxDCCR_DCGREEN_Pos (8U)
11797 #define LTDC_LxDCCR_DCGREEN_Msk (0xFFUL << LTDC_LxDCCR_DCGREEN_Pos) /*!< 0x0000FF00 */
11798 #define LTDC_LxDCCR_DCGREEN LTDC_LxDCCR_DCGREEN_Msk /*!< Default Color Green */
11799 #define LTDC_LxDCCR_DCRED_Pos (16U)
11800 #define LTDC_LxDCCR_DCRED_Msk (0xFFUL << LTDC_LxDCCR_DCRED_Pos) /*!< 0x00FF0000 */
11801 #define LTDC_LxDCCR_DCRED LTDC_LxDCCR_DCRED_Msk /*!< Default Color Red */
11802 #define LTDC_LxDCCR_DCALPHA_Pos (24U)
11803 #define LTDC_LxDCCR_DCALPHA_Msk (0xFFUL << LTDC_LxDCCR_DCALPHA_Pos) /*!< 0xFF000000 */
11804 #define LTDC_LxDCCR_DCALPHA LTDC_LxDCCR_DCALPHA_Msk /*!< Default Color Alpha */
11805
11806 /******************** Bit definition for LTDC_LxBFCR register ***************/
11807
11808 #define LTDC_LxBFCR_BF2_Pos (0U)
11809 #define LTDC_LxBFCR_BF2_Msk (0x7UL << LTDC_LxBFCR_BF2_Pos) /*!< 0x00000007 */
11810 #define LTDC_LxBFCR_BF2 LTDC_LxBFCR_BF2_Msk /*!< Blending Factor 2 */
11811 #define LTDC_LxBFCR_BF1_Pos (8U)
11812 #define LTDC_LxBFCR_BF1_Msk (0x7UL << LTDC_LxBFCR_BF1_Pos) /*!< 0x00000700 */
11813 #define LTDC_LxBFCR_BF1 LTDC_LxBFCR_BF1_Msk /*!< Blending Factor 1 */
11814
11815 /******************** Bit definition for LTDC_LxCFBAR register **************/
11816
11817 #define LTDC_LxCFBAR_CFBADD_Pos (0U)
11818 #define LTDC_LxCFBAR_CFBADD_Msk (0xFFFFFFFFUL << LTDC_LxCFBAR_CFBADD_Pos) /*!< 0xFFFFFFFF */
11819 #define LTDC_LxCFBAR_CFBADD LTDC_LxCFBAR_CFBADD_Msk /*!< Color Frame Buffer Start Address */
11820
11821 /******************** Bit definition for LTDC_LxCFBLR register **************/
11822
11823 #define LTDC_LxCFBLR_CFBLL_Pos (0U)
11824 #define LTDC_LxCFBLR_CFBLL_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBLL_Pos) /*!< 0x00001FFF */
11825 #define LTDC_LxCFBLR_CFBLL LTDC_LxCFBLR_CFBLL_Msk /*!< Color Frame Buffer Line Length */
11826 #define LTDC_LxCFBLR_CFBP_Pos (16U)
11827 #define LTDC_LxCFBLR_CFBP_Msk (0x1FFFUL << LTDC_LxCFBLR_CFBP_Pos) /*!< 0x1FFF0000 */
11828 #define LTDC_LxCFBLR_CFBP LTDC_LxCFBLR_CFBP_Msk /*!< Color Frame Buffer Pitch in bytes */
11829
11830 /******************** Bit definition for LTDC_LxCFBLNR register *************/
11831
11832 #define LTDC_LxCFBLNR_CFBLNBR_Pos (0U)
11833 #define LTDC_LxCFBLNR_CFBLNBR_Msk (0x7FFUL << LTDC_LxCFBLNR_CFBLNBR_Pos) /*!< 0x000007FF */
11834 #define LTDC_LxCFBLNR_CFBLNBR LTDC_LxCFBLNR_CFBLNBR_Msk /*!< Frame Buffer Line Number */
11835
11836 /******************** Bit definition for LTDC_LxCLUTWR register *************/
11837
11838 #define LTDC_LxCLUTWR_BLUE_Pos (0U)
11839 #define LTDC_LxCLUTWR_BLUE_Msk (0xFFUL << LTDC_LxCLUTWR_BLUE_Pos) /*!< 0x000000FF */
11840 #define LTDC_LxCLUTWR_BLUE LTDC_LxCLUTWR_BLUE_Msk /*!< Blue value */
11841 #define LTDC_LxCLUTWR_GREEN_Pos (8U)
11842 #define LTDC_LxCLUTWR_GREEN_Msk (0xFFUL << LTDC_LxCLUTWR_GREEN_Pos) /*!< 0x0000FF00 */
11843 #define LTDC_LxCLUTWR_GREEN LTDC_LxCLUTWR_GREEN_Msk /*!< Green value */
11844 #define LTDC_LxCLUTWR_RED_Pos (16U)
11845 #define LTDC_LxCLUTWR_RED_Msk (0xFFUL << LTDC_LxCLUTWR_RED_Pos) /*!< 0x00FF0000 */
11846 #define LTDC_LxCLUTWR_RED LTDC_LxCLUTWR_RED_Msk /*!< Red value */
11847 #define LTDC_LxCLUTWR_CLUTADD_Pos (24U)
11848 #define LTDC_LxCLUTWR_CLUTADD_Msk (0xFFUL << LTDC_LxCLUTWR_CLUTADD_Pos) /*!< 0xFF000000 */
11849 #define LTDC_LxCLUTWR_CLUTADD LTDC_LxCLUTWR_CLUTADD_Msk /*!< CLUT address */
11850
11851 /******************************************************************************/
11852 /* */
11853 /* MDMA */
11854 /* */
11855 /******************************************************************************/
11856 /******************** Bit definition for MDMA_GISR0 register ****************/
11857 #define MDMA_GISR0_GIF0_Pos (0U)
11858 #define MDMA_GISR0_GIF0_Msk (0x1UL << MDMA_GISR0_GIF0_Pos) /*!< 0x00000001 */
11859 #define MDMA_GISR0_GIF0 MDMA_GISR0_GIF0_Msk /*!< Channel 0 global interrupt flag */
11860 #define MDMA_GISR0_GIF1_Pos (1U)
11861 #define MDMA_GISR0_GIF1_Msk (0x1UL << MDMA_GISR0_GIF1_Pos) /*!< 0x00000002 */
11862 #define MDMA_GISR0_GIF1 MDMA_GISR0_GIF1_Msk /*!< Channel 1 global interrupt flag */
11863 #define MDMA_GISR0_GIF2_Pos (2U)
11864 #define MDMA_GISR0_GIF2_Msk (0x1UL << MDMA_GISR0_GIF2_Pos) /*!< 0x00000004 */
11865 #define MDMA_GISR0_GIF2 MDMA_GISR0_GIF2_Msk /*!< Channel 2 global interrupt flag */
11866 #define MDMA_GISR0_GIF3_Pos (3U)
11867 #define MDMA_GISR0_GIF3_Msk (0x1UL << MDMA_GISR0_GIF3_Pos) /*!< 0x00000008 */
11868 #define MDMA_GISR0_GIF3 MDMA_GISR0_GIF3_Msk /*!< Channel 3 global interrupt flag */
11869 #define MDMA_GISR0_GIF4_Pos (4U)
11870 #define MDMA_GISR0_GIF4_Msk (0x1UL << MDMA_GISR0_GIF4_Pos) /*!< 0x00000010 */
11871 #define MDMA_GISR0_GIF4 MDMA_GISR0_GIF4_Msk /*!< Channel 4 global interrupt flag */
11872 #define MDMA_GISR0_GIF5_Pos (5U)
11873 #define MDMA_GISR0_GIF5_Msk (0x1UL << MDMA_GISR0_GIF5_Pos) /*!< 0x00000020 */
11874 #define MDMA_GISR0_GIF5 MDMA_GISR0_GIF5_Msk /*!< Channel 5 global interrupt flag */
11875 #define MDMA_GISR0_GIF6_Pos (6U)
11876 #define MDMA_GISR0_GIF6_Msk (0x1UL << MDMA_GISR0_GIF6_Pos) /*!< 0x00000040 */
11877 #define MDMA_GISR0_GIF6 MDMA_GISR0_GIF6_Msk /*!< Channel 6 global interrupt flag */
11878 #define MDMA_GISR0_GIF7_Pos (7U)
11879 #define MDMA_GISR0_GIF7_Msk (0x1UL << MDMA_GISR0_GIF7_Pos) /*!< 0x00000080 */
11880 #define MDMA_GISR0_GIF7 MDMA_GISR0_GIF7_Msk /*!< Channel 7 global interrupt flag */
11881 #define MDMA_GISR0_GIF8_Pos (8U)
11882 #define MDMA_GISR0_GIF8_Msk (0x1UL << MDMA_GISR0_GIF8_Pos) /*!< 0x00000100 */
11883 #define MDMA_GISR0_GIF8 MDMA_GISR0_GIF8_Msk /*!< Channel 8 global interrupt flag */
11884 #define MDMA_GISR0_GIF9_Pos (9U)
11885 #define MDMA_GISR0_GIF9_Msk (0x1UL << MDMA_GISR0_GIF9_Pos) /*!< 0x00000200 */
11886 #define MDMA_GISR0_GIF9 MDMA_GISR0_GIF9_Msk /*!< Channel 9 global interrupt flag */
11887 #define MDMA_GISR0_GIF10_Pos (10U)
11888 #define MDMA_GISR0_GIF10_Msk (0x1UL << MDMA_GISR0_GIF10_Pos) /*!< 0x00000400 */
11889 #define MDMA_GISR0_GIF10 MDMA_GISR0_GIF10_Msk /*!< Channel 10 global interrupt flag */
11890 #define MDMA_GISR0_GIF11_Pos (11U)
11891 #define MDMA_GISR0_GIF11_Msk (0x1UL << MDMA_GISR0_GIF11_Pos) /*!< 0x00000800 */
11892 #define MDMA_GISR0_GIF11 MDMA_GISR0_GIF11_Msk /*!< Channel 11 global interrupt flag */
11893 #define MDMA_GISR0_GIF12_Pos (12U)
11894 #define MDMA_GISR0_GIF12_Msk (0x1UL << MDMA_GISR0_GIF12_Pos) /*!< 0x00001000 */
11895 #define MDMA_GISR0_GIF12 MDMA_GISR0_GIF12_Msk /*!< Channel 12 global interrupt flag */
11896 #define MDMA_GISR0_GIF13_Pos (13U)
11897 #define MDMA_GISR0_GIF13_Msk (0x1UL << MDMA_GISR0_GIF13_Pos) /*!< 0x00002000 */
11898 #define MDMA_GISR0_GIF13 MDMA_GISR0_GIF13_Msk /*!< Channel 13 global interrupt flag */
11899 #define MDMA_GISR0_GIF14_Pos (14U)
11900 #define MDMA_GISR0_GIF14_Msk (0x1UL << MDMA_GISR0_GIF14_Pos) /*!< 0x00004000 */
11901 #define MDMA_GISR0_GIF14 MDMA_GISR0_GIF14_Msk /*!< Channel 14 global interrupt flag */
11902 #define MDMA_GISR0_GIF15_Pos (15U)
11903 #define MDMA_GISR0_GIF15_Msk (0x1UL << MDMA_GISR0_GIF15_Pos) /*!< 0x00008000 */
11904 #define MDMA_GISR0_GIF15 MDMA_GISR0_GIF15_Msk /*!< Channel 15 global interrupt flag */
11905
11906 /******************** Bit definition for MDMA_CxISR register ****************/
11907 #define MDMA_CISR_TEIF_Pos (0U)
11908 #define MDMA_CISR_TEIF_Msk (0x1UL << MDMA_CISR_TEIF_Pos) /*!< 0x00000001 */
11909 #define MDMA_CISR_TEIF MDMA_CISR_TEIF_Msk /*!< Channel x transfer error interrupt flag */
11910 #define MDMA_CISR_CTCIF_Pos (1U)
11911 #define MDMA_CISR_CTCIF_Msk (0x1UL << MDMA_CISR_CTCIF_Pos) /*!< 0x00000002 */
11912 #define MDMA_CISR_CTCIF MDMA_CISR_CTCIF_Msk /*!< Channel x Channel Transfer Complete interrupt flag */
11913 #define MDMA_CISR_BRTIF_Pos (2U)
11914 #define MDMA_CISR_BRTIF_Msk (0x1UL << MDMA_CISR_BRTIF_Pos) /*!< 0x00000004 */
11915 #define MDMA_CISR_BRTIF MDMA_CISR_BRTIF_Msk /*!< Channel x block repeat transfer complete interrupt flag */
11916 #define MDMA_CISR_BTIF_Pos (3U)
11917 #define MDMA_CISR_BTIF_Msk (0x1UL << MDMA_CISR_BTIF_Pos) /*!< 0x00000008 */
11918 #define MDMA_CISR_BTIF MDMA_CISR_BTIF_Msk /*!< Channel x block transfer complete interrupt flag */
11919 #define MDMA_CISR_TCIF_Pos (4U)
11920 #define MDMA_CISR_TCIF_Msk (0x1UL << MDMA_CISR_TCIF_Pos) /*!< 0x00000010 */
11921 #define MDMA_CISR_TCIF MDMA_CISR_TCIF_Msk /*!< Channel x buffer transfer complete interrupt flag */
11922 #define MDMA_CISR_CRQA_Pos (16U)
11923 #define MDMA_CISR_CRQA_Msk (0x1UL << MDMA_CISR_CRQA_Pos) /*!< 0x00010000 */
11924 #define MDMA_CISR_CRQA MDMA_CISR_CRQA_Msk /*!< Channel x ReQest Active flag */
11925
11926 /******************** Bit definition for MDMA_CxIFCR register ****************/
11927 #define MDMA_CIFCR_CTEIF_Pos (0U)
11928 #define MDMA_CIFCR_CTEIF_Msk (0x1UL << MDMA_CIFCR_CTEIF_Pos) /*!< 0x00000001 */
11929 #define MDMA_CIFCR_CTEIF MDMA_CIFCR_CTEIF_Msk /*!< Channel x clear transfer error interrupt flag */
11930 #define MDMA_CIFCR_CCTCIF_Pos (1U)
11931 #define MDMA_CIFCR_CCTCIF_Msk (0x1UL << MDMA_CIFCR_CCTCIF_Pos) /*!< 0x00000002 */
11932 #define MDMA_CIFCR_CCTCIF MDMA_CIFCR_CCTCIF_Msk /*!< Clear Channel transfer complete interrupt flag for channel x */
11933 #define MDMA_CIFCR_CBRTIF_Pos (2U)
11934 #define MDMA_CIFCR_CBRTIF_Msk (0x1UL << MDMA_CIFCR_CBRTIF_Pos) /*!< 0x00000004 */
11935 #define MDMA_CIFCR_CBRTIF MDMA_CIFCR_CBRTIF_Msk /*!< Channel x clear block repeat transfer complete interrupt flag */
11936 #define MDMA_CIFCR_CBTIF_Pos (3U)
11937 #define MDMA_CIFCR_CBTIF_Msk (0x1UL << MDMA_CIFCR_CBTIF_Pos) /*!< 0x00000008 */
11938 #define MDMA_CIFCR_CBTIF MDMA_CIFCR_CBTIF_Msk /*!< Channel x Clear block transfer complete interrupt flag */
11939 #define MDMA_CIFCR_CLTCIF_Pos (4U)
11940 #define MDMA_CIFCR_CLTCIF_Msk (0x1UL << MDMA_CIFCR_CLTCIF_Pos) /*!< 0x00000010 */
11941 #define MDMA_CIFCR_CLTCIF MDMA_CIFCR_CLTCIF_Msk /*!< CLear Transfer buffer Complete Interrupt Flag for channel */
11942
11943 /******************** Bit definition for MDMA_CxESR register ****************/
11944 #define MDMA_CESR_TEA_Pos (0U)
11945 #define MDMA_CESR_TEA_Msk (0x7FUL << MDMA_CESR_TEA_Pos) /*!< 0x0000007F */
11946 #define MDMA_CESR_TEA MDMA_CESR_TEA_Msk /*!< Transfer Error Address */
11947 #define MDMA_CESR_TED_Pos (7U)
11948 #define MDMA_CESR_TED_Msk (0x1UL << MDMA_CESR_TED_Pos) /*!< 0x00000080 */
11949 #define MDMA_CESR_TED MDMA_CESR_TED_Msk /*!< Transfer Error Direction */
11950 #define MDMA_CESR_TELD_Pos (8U)
11951 #define MDMA_CESR_TELD_Msk (0x1UL << MDMA_CESR_TELD_Pos) /*!< 0x00000100 */
11952 #define MDMA_CESR_TELD MDMA_CESR_TELD_Msk /*!< Transfer Error Link Data */
11953 #define MDMA_CESR_TEMD_Pos (9U)
11954 #define MDMA_CESR_TEMD_Msk (0x1UL << MDMA_CESR_TEMD_Pos) /*!< 0x00000200 */
11955 #define MDMA_CESR_TEMD MDMA_CESR_TEMD_Msk /*!< Transfer Error Mask Data */
11956 #define MDMA_CESR_ASE_Pos (10U)
11957 #define MDMA_CESR_ASE_Msk (0x1UL << MDMA_CESR_ASE_Pos) /*!< 0x00000400 */
11958 #define MDMA_CESR_ASE MDMA_CESR_ASE_Msk /*!< Address/Size Error */
11959 #define MDMA_CESR_BSE_Pos (11U)
11960 #define MDMA_CESR_BSE_Msk (0x1UL << MDMA_CESR_BSE_Pos) /*!< 0x00000800 */
11961 #define MDMA_CESR_BSE MDMA_CESR_BSE_Msk /*!< Block Size Error */
11962
11963 /******************** Bit definition for MDMA_CxCR register ****************/
11964 #define MDMA_CCR_EN_Pos (0U)
11965 #define MDMA_CCR_EN_Msk (0x1UL << MDMA_CCR_EN_Pos) /*!< 0x00000001 */
11966 #define MDMA_CCR_EN MDMA_CCR_EN_Msk /*!< Channel enable / flag channel ready when read low */
11967 #define MDMA_CCR_TEIE_Pos (1U)
11968 #define MDMA_CCR_TEIE_Msk (0x1UL << MDMA_CCR_TEIE_Pos) /*!< 0x00000002 */
11969 #define MDMA_CCR_TEIE MDMA_CCR_TEIE_Msk /*!< Transfer error interrupt enable */
11970 #define MDMA_CCR_CTCIE_Pos (2U)
11971 #define MDMA_CCR_CTCIE_Msk (0x1UL << MDMA_CCR_CTCIE_Pos) /*!< 0x00000004 */
11972 #define MDMA_CCR_CTCIE MDMA_CCR_CTCIE_Msk /*!< Channel Transfer Complete interrupt enable */
11973 #define MDMA_CCR_BRTIE_Pos (3U)
11974 #define MDMA_CCR_BRTIE_Msk (0x1UL << MDMA_CCR_BRTIE_Pos) /*!< 0x00000008 */
11975 #define MDMA_CCR_BRTIE MDMA_CCR_BRTIE_Msk /*!< Block Repeat transfer interrupt enable */
11976 #define MDMA_CCR_BTIE_Pos (4U)
11977 #define MDMA_CCR_BTIE_Msk (0x1UL << MDMA_CCR_BTIE_Pos) /*!< 0x00000010 */
11978 #define MDMA_CCR_BTIE MDMA_CCR_BTIE_Msk /*!< Block Transfer interrupt enable */
11979 #define MDMA_CCR_TCIE_Pos (5U)
11980 #define MDMA_CCR_TCIE_Msk (0x1UL << MDMA_CCR_TCIE_Pos) /*!< 0x00000020 */
11981 #define MDMA_CCR_TCIE MDMA_CCR_TCIE_Msk /*!< buffer Transfer Complete interrupt enable */
11982 #define MDMA_CCR_PL_Pos (6U)
11983 #define MDMA_CCR_PL_Msk (0x3UL << MDMA_CCR_PL_Pos) /*!< 0x000000C0 */
11984 #define MDMA_CCR_PL MDMA_CCR_PL_Msk /*!< Priority level */
11985 #define MDMA_CCR_PL_0 (0x1UL << MDMA_CCR_PL_Pos) /*!< 0x00000040 */
11986 #define MDMA_CCR_PL_1 (0x2UL << MDMA_CCR_PL_Pos) /*!< 0x00000080 */
11987 #define MDMA_CCR_BEX_Pos (12U)
11988 #define MDMA_CCR_BEX_Msk (0x1UL << MDMA_CCR_BEX_Pos) /*!< 0x00001000 */
11989 #define MDMA_CCR_BEX MDMA_CCR_BEX_Msk /*!< Byte Endianess eXchange */
11990 #define MDMA_CCR_HEX_Pos (13U)
11991 #define MDMA_CCR_HEX_Msk (0x1UL << MDMA_CCR_HEX_Pos) /*!< 0x00002000 */
11992 #define MDMA_CCR_HEX MDMA_CCR_HEX_Msk /*!< Half word Endianess eXchange */
11993 #define MDMA_CCR_WEX_Pos (14U)
11994 #define MDMA_CCR_WEX_Msk (0x1UL << MDMA_CCR_WEX_Pos) /*!< 0x00004000 */
11995 #define MDMA_CCR_WEX MDMA_CCR_WEX_Msk /*!< Word Endianess eXchange */
11996 #define MDMA_CCR_SWRQ_Pos (16U)
11997 #define MDMA_CCR_SWRQ_Msk (0x1UL << MDMA_CCR_SWRQ_Pos) /*!< 0x00010000 */
11998 #define MDMA_CCR_SWRQ MDMA_CCR_SWRQ_Msk /*!< SW ReQuest */
11999
12000 /******************** Bit definition for MDMA_CxTCR register ****************/
12001 #define MDMA_CTCR_SINC_Pos (0U)
12002 #define MDMA_CTCR_SINC_Msk (0x3UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000003 */
12003 #define MDMA_CTCR_SINC MDMA_CTCR_SINC_Msk /*!< Source increment mode */
12004 #define MDMA_CTCR_SINC_0 (0x1UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000001 */
12005 #define MDMA_CTCR_SINC_1 (0x2UL << MDMA_CTCR_SINC_Pos) /*!< 0x00000002 */
12006 #define MDMA_CTCR_DINC_Pos (2U)
12007 #define MDMA_CTCR_DINC_Msk (0x3UL << MDMA_CTCR_DINC_Pos) /*!< 0x0000000C */
12008 #define MDMA_CTCR_DINC MDMA_CTCR_DINC_Msk /*!< Source increment mode */
12009 #define MDMA_CTCR_DINC_0 (0x1UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000004 */
12010 #define MDMA_CTCR_DINC_1 (0x2UL << MDMA_CTCR_DINC_Pos) /*!< 0x00000008 */
12011 #define MDMA_CTCR_SSIZE_Pos (4U)
12012 #define MDMA_CTCR_SSIZE_Msk (0x3UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000030 */
12013 #define MDMA_CTCR_SSIZE MDMA_CTCR_SSIZE_Msk /*!< Source data size */
12014 #define MDMA_CTCR_SSIZE_0 (0x1UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000010 */
12015 #define MDMA_CTCR_SSIZE_1 (0x2UL << MDMA_CTCR_SSIZE_Pos) /*!< 0x00000020 */
12016 #define MDMA_CTCR_DSIZE_Pos (6U)
12017 #define MDMA_CTCR_DSIZE_Msk (0x3UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x000000C0 */
12018 #define MDMA_CTCR_DSIZE MDMA_CTCR_DSIZE_Msk /*!< Destination data size */
12019 #define MDMA_CTCR_DSIZE_0 (0x1UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000040 */
12020 #define MDMA_CTCR_DSIZE_1 (0x2UL << MDMA_CTCR_DSIZE_Pos) /*!< 0x00000080 */
12021 #define MDMA_CTCR_SINCOS_Pos (8U)
12022 #define MDMA_CTCR_SINCOS_Msk (0x3UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000300 */
12023 #define MDMA_CTCR_SINCOS MDMA_CTCR_SINCOS_Msk /*!< Source increment offset size */
12024 #define MDMA_CTCR_SINCOS_0 (0x1UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000100 */
12025 #define MDMA_CTCR_SINCOS_1 (0x2UL << MDMA_CTCR_SINCOS_Pos) /*!< 0x00000200 */
12026 #define MDMA_CTCR_DINCOS_Pos (10U)
12027 #define MDMA_CTCR_DINCOS_Msk (0x3UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000C00 */
12028 #define MDMA_CTCR_DINCOS MDMA_CTCR_DINCOS_Msk /*!< Destination increment offset size */
12029 #define MDMA_CTCR_DINCOS_0 (0x1UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000400 */
12030 #define MDMA_CTCR_DINCOS_1 (0x2UL << MDMA_CTCR_DINCOS_Pos) /*!< 0x00000800 */
12031 #define MDMA_CTCR_SBURST_Pos (12U)
12032 #define MDMA_CTCR_SBURST_Msk (0x7UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00007000 */
12033 #define MDMA_CTCR_SBURST MDMA_CTCR_SBURST_Msk /*!< Source burst transfer configuration */
12034 #define MDMA_CTCR_SBURST_0 (0x1UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00001000 */
12035 #define MDMA_CTCR_SBURST_1 (0x2UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00002000 */
12036 #define MDMA_CTCR_SBURST_2 (0x4UL << MDMA_CTCR_SBURST_Pos) /*!< 0x00004000 */
12037 #define MDMA_CTCR_DBURST_Pos (15U)
12038 #define MDMA_CTCR_DBURST_Msk (0x7UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00038000 */
12039 #define MDMA_CTCR_DBURST MDMA_CTCR_DBURST_Msk /*!< Destination burst transfer configuration */
12040 #define MDMA_CTCR_DBURST_0 (0x1UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00008000 */
12041 #define MDMA_CTCR_DBURST_1 (0x2UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00010000 */
12042 #define MDMA_CTCR_DBURST_2 (0x4UL << MDMA_CTCR_DBURST_Pos) /*!< 0x00020000 */
12043 #define MDMA_CTCR_TLEN_Pos (18U)
12044 #define MDMA_CTCR_TLEN_Msk (0x7FUL << MDMA_CTCR_TLEN_Pos) /*!< 0x01FC0000 */
12045 #define MDMA_CTCR_TLEN MDMA_CTCR_TLEN_Msk /*!< buffer Transfer Length (number of bytes - 1) */
12046 #define MDMA_CTCR_PKE_Pos (25U)
12047 #define MDMA_CTCR_PKE_Msk (0x1UL << MDMA_CTCR_PKE_Pos) /*!< 0x02000000 */
12048 #define MDMA_CTCR_PKE MDMA_CTCR_PKE_Msk /*!< PacK Enable */
12049 #define MDMA_CTCR_PAM_Pos (26U)
12050 #define MDMA_CTCR_PAM_Msk (0x3UL << MDMA_CTCR_PAM_Pos) /*!< 0x0C000000 */
12051 #define MDMA_CTCR_PAM MDMA_CTCR_PAM_Msk /*!< Padding/Alignement Mode */
12052 #define MDMA_CTCR_PAM_0 (0x1UL << MDMA_CTCR_PAM_Pos) /*!< 0x4000000 */
12053 #define MDMA_CTCR_PAM_1 (0x2UL << MDMA_CTCR_PAM_Pos) /*!< 0x8000000 */
12054 #define MDMA_CTCR_TRGM_Pos (28U)
12055 #define MDMA_CTCR_TRGM_Msk (0x3UL << MDMA_CTCR_TRGM_Pos) /*!< 0x30000000 */
12056 #define MDMA_CTCR_TRGM MDMA_CTCR_TRGM_Msk /*!< Trigger Mode */
12057 #define MDMA_CTCR_TRGM_0 (0x1UL << MDMA_CTCR_TRGM_Pos) /*!< 0x10000000 */
12058 #define MDMA_CTCR_TRGM_1 (0x2UL << MDMA_CTCR_TRGM_Pos) /*!< 0x20000000 */
12059 #define MDMA_CTCR_SWRM_Pos (30U)
12060 #define MDMA_CTCR_SWRM_Msk (0x1UL << MDMA_CTCR_SWRM_Pos) /*!< 0x40000000 */
12061 #define MDMA_CTCR_SWRM MDMA_CTCR_SWRM_Msk /*!< SW Request Mode */
12062 #define MDMA_CTCR_BWM_Pos (31U)
12063 #define MDMA_CTCR_BWM_Msk (0x1UL << MDMA_CTCR_BWM_Pos) /*!< 0x80000000 */
12064 #define MDMA_CTCR_BWM MDMA_CTCR_BWM_Msk /*!< Bufferable Write Mode */
12065
12066 /******************** Bit definition for MDMA_CxBNDTR register ****************/
12067 #define MDMA_CBNDTR_BNDT_Pos (0U)
12068 #define MDMA_CBNDTR_BNDT_Msk (0x1FFFFUL << MDMA_CBNDTR_BNDT_Pos) /*!< 0x0001FFFF */
12069 #define MDMA_CBNDTR_BNDT MDMA_CBNDTR_BNDT_Msk /*!< Block Number of data bytes to transfer */
12070 #define MDMA_CBNDTR_BRSUM_Pos (18U)
12071 #define MDMA_CBNDTR_BRSUM_Msk (0x1UL << MDMA_CBNDTR_BRSUM_Pos) /*!< 0x00040000 */
12072 #define MDMA_CBNDTR_BRSUM MDMA_CBNDTR_BRSUM_Msk /*!< Block Repeat Source address Update Mode */
12073 #define MDMA_CBNDTR_BRDUM_Pos (19U)
12074 #define MDMA_CBNDTR_BRDUM_Msk (0x1UL << MDMA_CBNDTR_BRDUM_Pos) /*!< 0x00080000 */
12075 #define MDMA_CBNDTR_BRDUM MDMA_CBNDTR_BRDUM_Msk /*!< Block Repeat Destination address Update Mode */
12076 #define MDMA_CBNDTR_BRC_Pos (20U)
12077 #define MDMA_CBNDTR_BRC_Msk (0xFFFUL << MDMA_CBNDTR_BRC_Pos) /*!< 0xFFF00000 */
12078 #define MDMA_CBNDTR_BRC MDMA_CBNDTR_BRC_Msk /*!< Block Repeat Count */
12079
12080 /******************** Bit definition for MDMA_CxSAR register ****************/
12081 #define MDMA_CSAR_SAR_Pos (0U)
12082 #define MDMA_CSAR_SAR_Msk (0xFFFFFFFFUL << MDMA_CSAR_SAR_Pos) /*!< 0xFFFFFFFF */
12083 #define MDMA_CSAR_SAR MDMA_CSAR_SAR_Msk /*!< Source address */
12084
12085 /******************** Bit definition for MDMA_CxDAR register ****************/
12086 #define MDMA_CDAR_DAR_Pos (0U)
12087 #define MDMA_CDAR_DAR_Msk (0xFFFFFFFFUL << MDMA_CDAR_DAR_Pos) /*!< 0xFFFFFFFF */
12088 #define MDMA_CDAR_DAR MDMA_CDAR_DAR_Msk /*!< Destination address */
12089
12090 /******************** Bit definition for MDMA_CxBRUR ************************/
12091 #define MDMA_CBRUR_SUV_Pos (0U)
12092 #define MDMA_CBRUR_SUV_Msk (0xFFFFUL << MDMA_CBRUR_SUV_Pos) /*!< 0x0000FFFF */
12093 #define MDMA_CBRUR_SUV MDMA_CBRUR_SUV_Msk /*!< Source address Update Value */
12094 #define MDMA_CBRUR_DUV_Pos (16U)
12095 #define MDMA_CBRUR_DUV_Msk (0xFFFFUL << MDMA_CBRUR_DUV_Pos) /*!< 0xFFFF0000 */
12096 #define MDMA_CBRUR_DUV MDMA_CBRUR_DUV_Msk /*!< Destination address Update Value */
12097
12098 /******************** Bit definition for MDMA_CxLAR *************************/
12099 #define MDMA_CLAR_LAR_Pos (0U)
12100 #define MDMA_CLAR_LAR_Msk (0xFFFFFFFFUL << MDMA_CLAR_LAR_Pos) /*!< 0xFFFFFFFF */
12101 #define MDMA_CLAR_LAR MDMA_CLAR_LAR_Msk /*!< Link Address Register */
12102
12103 /******************** Bit definition for MDMA_CxTBR) ************************/
12104 #define MDMA_CTBR_TSEL_Pos (0U)
12105 #define MDMA_CTBR_TSEL_Msk (0xFFUL << MDMA_CTBR_TSEL_Pos) /*!< 0x000000FF */
12106 #define MDMA_CTBR_TSEL MDMA_CTBR_TSEL_Msk /*!< Trigger SELection */
12107 #define MDMA_CTBR_SBUS_Pos (16U)
12108 #define MDMA_CTBR_SBUS_Msk (0x1UL << MDMA_CTBR_SBUS_Pos) /*!< 0x00010000 */
12109 #define MDMA_CTBR_SBUS MDMA_CTBR_SBUS_Msk /*!< Source BUS select */
12110 #define MDMA_CTBR_DBUS_Pos (17U)
12111 #define MDMA_CTBR_DBUS_Msk (0x1UL << MDMA_CTBR_DBUS_Pos) /*!< 0x00020000 */
12112 #define MDMA_CTBR_DBUS MDMA_CTBR_DBUS_Msk /*!< Destination BUS select */
12113
12114 /******************** Bit definition for MDMA_CxMAR) ************************/
12115 #define MDMA_CMAR_MAR_Pos (0U)
12116 #define MDMA_CMAR_MAR_Msk (0xFFFFFFFFUL << MDMA_CMAR_MAR_Pos) /*!< 0xFFFFFFFF */
12117 #define MDMA_CMAR_MAR MDMA_CMAR_MAR_Msk /*!< Mask address */
12118
12119 /******************** Bit definition for MDMA_CxMDR) ************************/
12120 #define MDMA_CMDR_MDR_Pos (0U)
12121 #define MDMA_CMDR_MDR_Msk (0xFFFFFFFFUL << MDMA_CMDR_MDR_Pos) /*!< 0xFFFFFFFF */
12122 #define MDMA_CMDR_MDR MDMA_CMDR_MDR_Msk /*!< Mask Data */
12123
12124 /******************************************************************************/
12125 /* */
12126 /* Operational Amplifier (OPAMP) */
12127 /* */
12128 /******************************************************************************/
12129 /********************* Bit definition for OPAMPx_CSR register ***************/
12130 #define OPAMP_CSR_OPAMPxEN_Pos (0U)
12131 #define OPAMP_CSR_OPAMPxEN_Msk (0x1UL << OPAMP_CSR_OPAMPxEN_Pos) /*!< 0x00000001 */
12132 #define OPAMP_CSR_OPAMPxEN OPAMP_CSR_OPAMPxEN_Msk /*!< OPAMP enable */
12133 #define OPAMP_CSR_FORCEVP_Pos (1U)
12134 #define OPAMP_CSR_FORCEVP_Msk (0x1UL << OPAMP_CSR_FORCEVP_Pos) /*!< 0x00000002 */
12135 #define OPAMP_CSR_FORCEVP OPAMP_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
12136
12137 #define OPAMP_CSR_VPSEL_Pos (2U)
12138 #define OPAMP_CSR_VPSEL_Msk (0x3UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x0000000C */
12139 #define OPAMP_CSR_VPSEL OPAMP_CSR_VPSEL_Msk /*!< Non inverted input selection */
12140 #define OPAMP_CSR_VPSEL_0 (0x1UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000004 */
12141 #define OPAMP_CSR_VPSEL_1 (0x2UL << OPAMP_CSR_VPSEL_Pos) /*!< 0x00000008 */
12142
12143 #define OPAMP_CSR_VMSEL_Pos (5U)
12144 #define OPAMP_CSR_VMSEL_Msk (0x3UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000060 */
12145 #define OPAMP_CSR_VMSEL OPAMP_CSR_VMSEL_Msk /*!< Inverting input selection */
12146 #define OPAMP_CSR_VMSEL_0 (0x1UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000020 */
12147 #define OPAMP_CSR_VMSEL_1 (0x2UL << OPAMP_CSR_VMSEL_Pos) /*!< 0x00000040 */
12148
12149 #define OPAMP_CSR_OPAHSM_Pos (8U)
12150 #define OPAMP_CSR_OPAHSM_Msk (0x1UL << OPAMP_CSR_OPAHSM_Pos) /*!< 0x00000100 */
12151 #define OPAMP_CSR_OPAHSM OPAMP_CSR_OPAHSM_Msk /*!< Operational amplifier high speed mode */
12152 #define OPAMP_CSR_CALON_Pos (11U)
12153 #define OPAMP_CSR_CALON_Msk (0x1UL << OPAMP_CSR_CALON_Pos) /*!< 0x00000800 */
12154 #define OPAMP_CSR_CALON OPAMP_CSR_CALON_Msk /*!< Calibration mode enable */
12155
12156 #define OPAMP_CSR_CALSEL_Pos (12U)
12157 #define OPAMP_CSR_CALSEL_Msk (0x3UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00003000 */
12158 #define OPAMP_CSR_CALSEL OPAMP_CSR_CALSEL_Msk /*!< Calibration selection */
12159 #define OPAMP_CSR_CALSEL_0 (0x1UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00001000 */
12160 #define OPAMP_CSR_CALSEL_1 (0x2UL << OPAMP_CSR_CALSEL_Pos) /*!< 0x00002000 */
12161
12162 #define OPAMP_CSR_PGGAIN_Pos (14U)
12163 #define OPAMP_CSR_PGGAIN_Msk (0xFUL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
12164 #define OPAMP_CSR_PGGAIN OPAMP_CSR_PGGAIN_Msk /*!< Operational amplifier Programmable amplifier gain value */
12165 #define OPAMP_CSR_PGGAIN_0 (0x1UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00004000 */
12166 #define OPAMP_CSR_PGGAIN_1 (0x2UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00008000 */
12167 #define OPAMP_CSR_PGGAIN_2 (0x4UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00010000 */
12168 #define OPAMP_CSR_PGGAIN_3 (0x8UL << OPAMP_CSR_PGGAIN_Pos) /*!< 0x00020000 */
12169
12170 #define OPAMP_CSR_USERTRIM_Pos (18U)
12171 #define OPAMP_CSR_USERTRIM_Msk (0x1UL << OPAMP_CSR_USERTRIM_Pos) /*!< 0x00040000 */
12172 #define OPAMP_CSR_USERTRIM OPAMP_CSR_USERTRIM_Msk /*!< User trimming enable */
12173 #define OPAMP_CSR_TSTREF_Pos (29U)
12174 #define OPAMP_CSR_TSTREF_Msk (0x1UL << OPAMP_CSR_TSTREF_Pos) /*!< 0x20000000 */
12175 #define OPAMP_CSR_TSTREF OPAMP_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
12176 #define OPAMP_CSR_CALOUT_Pos (30U)
12177 #define OPAMP_CSR_CALOUT_Msk (0x1UL << OPAMP_CSR_CALOUT_Pos) /*!< 0x40000000 */
12178 #define OPAMP_CSR_CALOUT OPAMP_CSR_CALOUT_Msk /*!< Operational amplifier calibration output */
12179
12180 /********************* Bit definition for OPAMP1_CSR register ***************/
12181 #define OPAMP1_CSR_OPAEN_Pos (0U)
12182 #define OPAMP1_CSR_OPAEN_Msk (0x1UL << OPAMP1_CSR_OPAEN_Pos) /*!< 0x00000001 */
12183 #define OPAMP1_CSR_OPAEN OPAMP1_CSR_OPAEN_Msk /*!< Operational amplifier1 Enable */
12184 #define OPAMP1_CSR_FORCEVP_Pos (1U)
12185 #define OPAMP1_CSR_FORCEVP_Msk (0x1UL << OPAMP1_CSR_FORCEVP_Pos) /*!< 0x00000002 */
12186 #define OPAMP1_CSR_FORCEVP OPAMP1_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
12187
12188 #define OPAMP1_CSR_VPSEL_Pos (2U)
12189 #define OPAMP1_CSR_VPSEL_Msk (0x3UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x0000000C */
12190 #define OPAMP1_CSR_VPSEL OPAMP1_CSR_VPSEL_Msk /*!< Non inverted input selection */
12191 #define OPAMP1_CSR_VPSEL_0 (0x1UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000004 */
12192 #define OPAMP1_CSR_VPSEL_1 (0x2UL << OPAMP1_CSR_VPSEL_Pos) /*!< 0x00000008 */
12193
12194 #define OPAMP1_CSR_VMSEL_Pos (5U)
12195 #define OPAMP1_CSR_VMSEL_Msk (0x3UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000060 */
12196 #define OPAMP1_CSR_VMSEL OPAMP1_CSR_VMSEL_Msk /*!< Inverting input selection */
12197 #define OPAMP1_CSR_VMSEL_0 (0x1UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000020 */
12198 #define OPAMP1_CSR_VMSEL_1 (0x2UL << OPAMP1_CSR_VMSEL_Pos) /*!< 0x00000040 */
12199
12200 #define OPAMP1_CSR_OPAHSM_Pos (8U)
12201 #define OPAMP1_CSR_OPAHSM_Msk (0x1UL << OPAMP1_CSR_OPAHSM_Pos) /*!< 0x00000100 */
12202 #define OPAMP1_CSR_OPAHSM OPAMP1_CSR_OPAHSM_Msk /*!< Operational amplifier1 high speed mode */
12203 #define OPAMP1_CSR_CALON_Pos (11U)
12204 #define OPAMP1_CSR_CALON_Msk (0x1UL << OPAMP1_CSR_CALON_Pos) /*!< 0x00000800 */
12205 #define OPAMP1_CSR_CALON OPAMP1_CSR_CALON_Msk /*!< Calibration mode enable */
12206
12207 #define OPAMP1_CSR_CALSEL_Pos (12U)
12208 #define OPAMP1_CSR_CALSEL_Msk (0x3UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00003000 */
12209 #define OPAMP1_CSR_CALSEL OPAMP1_CSR_CALSEL_Msk /*!< Calibration selection */
12210 #define OPAMP1_CSR_CALSEL_0 (0x1UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00001000 */
12211 #define OPAMP1_CSR_CALSEL_1 (0x2UL << OPAMP1_CSR_CALSEL_Pos) /*!< 0x00002000 */
12212
12213 #define OPAMP1_CSR_PGGAIN_Pos (14U)
12214 #define OPAMP1_CSR_PGGAIN_Msk (0xFUL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
12215 #define OPAMP1_CSR_PGGAIN OPAMP1_CSR_PGGAIN_Msk /*!< Operational amplifier1 Programmable amplifier gain value */
12216 #define OPAMP1_CSR_PGGAIN_0 (0x1UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00004000 */
12217 #define OPAMP1_CSR_PGGAIN_1 (0x2UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00008000 */
12218 #define OPAMP1_CSR_PGGAIN_2 (0x4UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00010000 */
12219 #define OPAMP1_CSR_PGGAIN_3 (0x8UL << OPAMP1_CSR_PGGAIN_Pos) /*!< 0x00020000 */
12220
12221 #define OPAMP1_CSR_USERTRIM_Pos (18U)
12222 #define OPAMP1_CSR_USERTRIM_Msk (0x1UL << OPAMP1_CSR_USERTRIM_Pos) /*!< 0x00040000 */
12223 #define OPAMP1_CSR_USERTRIM OPAMP1_CSR_USERTRIM_Msk /*!< User trimming enable */
12224 #define OPAMP1_CSR_TSTREF_Pos (29U)
12225 #define OPAMP1_CSR_TSTREF_Msk (0x1UL << OPAMP1_CSR_TSTREF_Pos) /*!< 0x20000000 */
12226 #define OPAMP1_CSR_TSTREF OPAMP1_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
12227 #define OPAMP1_CSR_CALOUT_Pos (30U)
12228 #define OPAMP1_CSR_CALOUT_Msk (0x1UL << OPAMP1_CSR_CALOUT_Pos) /*!< 0x40000000 */
12229 #define OPAMP1_CSR_CALOUT OPAMP1_CSR_CALOUT_Msk /*!< Operational amplifier1 calibration output */
12230
12231 /********************* Bit definition for OPAMP2_CSR register ***************/
12232 #define OPAMP2_CSR_OPAEN_Pos (0U)
12233 #define OPAMP2_CSR_OPAEN_Msk (0x1UL << OPAMP2_CSR_OPAEN_Pos) /*!< 0x00000001 */
12234 #define OPAMP2_CSR_OPAEN OPAMP2_CSR_OPAEN_Msk /*!< Operational amplifier2 Enable */
12235 #define OPAMP2_CSR_FORCEVP_Pos (1U)
12236 #define OPAMP2_CSR_FORCEVP_Msk (0x1UL << OPAMP2_CSR_FORCEVP_Pos) /*!< 0x00000002 */
12237 #define OPAMP2_CSR_FORCEVP OPAMP2_CSR_FORCEVP_Msk /*!< Force internal reference on VP */
12238
12239 #define OPAMP2_CSR_VPSEL_Pos (2U)
12240 #define OPAMP2_CSR_VPSEL_Msk (0x3UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x0000000C */
12241 #define OPAMP2_CSR_VPSEL OPAMP2_CSR_VPSEL_Msk /*!< Non inverted input selection */
12242 #define OPAMP2_CSR_VPSEL_0 (0x1UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000004 */
12243 #define OPAMP2_CSR_VPSEL_1 (0x2UL << OPAMP2_CSR_VPSEL_Pos) /*!< 0x00000008 */
12244
12245 #define OPAMP2_CSR_VMSEL_Pos (5U)
12246 #define OPAMP2_CSR_VMSEL_Msk (0x3UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000060 */
12247 #define OPAMP2_CSR_VMSEL OPAMP2_CSR_VMSEL_Msk /*!< Inverting input selection */
12248 #define OPAMP2_CSR_VMSEL_0 (0x1UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000020 */
12249 #define OPAMP2_CSR_VMSEL_1 (0x2UL << OPAMP2_CSR_VMSEL_Pos) /*!< 0x00000040 */
12250
12251 #define OPAMP2_CSR_OPAHSM_Pos (8U)
12252 #define OPAMP2_CSR_OPAHSM_Msk (0x1UL << OPAMP2_CSR_OPAHSM_Pos) /*!< 0x00000100 */
12253 #define OPAMP2_CSR_OPAHSM OPAMP2_CSR_OPAHSM_Msk /*!< Operational amplifier2 high speed mode */
12254 #define OPAMP2_CSR_CALON_Pos (11U)
12255 #define OPAMP2_CSR_CALON_Msk (0x1UL << OPAMP2_CSR_CALON_Pos) /*!< 0x00000800 */
12256 #define OPAMP2_CSR_CALON OPAMP2_CSR_CALON_Msk /*!< Calibration mode enable */
12257
12258 #define OPAMP2_CSR_CALSEL_Pos (12U)
12259 #define OPAMP2_CSR_CALSEL_Msk (0x3UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00003000 */
12260 #define OPAMP2_CSR_CALSEL OPAMP2_CSR_CALSEL_Msk /*!< Calibration selection */
12261 #define OPAMP2_CSR_CALSEL_0 (0x1UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00001000 */
12262 #define OPAMP2_CSR_CALSEL_1 (0x2UL << OPAMP2_CSR_CALSEL_Pos) /*!< 0x00002000 */
12263
12264 #define OPAMP2_CSR_PGGAIN_Pos (14U)
12265 #define OPAMP2_CSR_PGGAIN_Msk (0xFUL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x0003C000 */
12266 #define OPAMP2_CSR_PGGAIN OPAMP2_CSR_PGGAIN_Msk /*!< Operational amplifier2 Programmable amplifier gain value */
12267 #define OPAMP2_CSR_PGGAIN_0 (0x1UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00004000 */
12268 #define OPAMP2_CSR_PGGAIN_1 (0x2UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00008000 */
12269 #define OPAMP2_CSR_PGGAIN_2 (0x4UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00010000 */
12270 #define OPAMP2_CSR_PGGAIN_3 (0x8UL << OPAMP2_CSR_PGGAIN_Pos) /*!< 0x00020000 */
12271
12272 #define OPAMP2_CSR_USERTRIM_Pos (18U)
12273 #define OPAMP2_CSR_USERTRIM_Msk (0x1UL << OPAMP2_CSR_USERTRIM_Pos) /*!< 0x00040000 */
12274 #define OPAMP2_CSR_USERTRIM OPAMP2_CSR_USERTRIM_Msk /*!< User trimming enable */
12275 #define OPAMP2_CSR_TSTREF_Pos (29U)
12276 #define OPAMP2_CSR_TSTREF_Msk (0x1UL << OPAMP2_CSR_TSTREF_Pos) /*!< 0x20000000 */
12277 #define OPAMP2_CSR_TSTREF OPAMP2_CSR_TSTREF_Msk /*!< OpAmp calibration reference voltage output control */
12278 #define OPAMP2_CSR_CALOUT_Pos (30U)
12279 #define OPAMP2_CSR_CALOUT_Msk (0x1UL << OPAMP2_CSR_CALOUT_Pos) /*!< 0x40000000 */
12280 #define OPAMP2_CSR_CALOUT OPAMP2_CSR_CALOUT_Msk /*!< Operational amplifier2 calibration output */
12281
12282 /******************* Bit definition for OPAMP_OTR register ******************/
12283 #define OPAMP_OTR_TRIMOFFSETN_Pos (0U)
12284 #define OPAMP_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12285 #define OPAMP_OTR_TRIMOFFSETN OPAMP_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12286 #define OPAMP_OTR_TRIMOFFSETP_Pos (8U)
12287 #define OPAMP_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12288 #define OPAMP_OTR_TRIMOFFSETP OPAMP_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12289
12290 /******************* Bit definition for OPAMP1_OTR register ******************/
12291 #define OPAMP1_OTR_TRIMOFFSETN_Pos (0U)
12292 #define OPAMP1_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12293 #define OPAMP1_OTR_TRIMOFFSETN OPAMP1_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12294 #define OPAMP1_OTR_TRIMOFFSETP_Pos (8U)
12295 #define OPAMP1_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP1_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12296 #define OPAMP1_OTR_TRIMOFFSETP OPAMP1_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12297
12298 /******************* Bit definition for OPAMP2_OTR register ******************/
12299 #define OPAMP2_OTR_TRIMOFFSETN_Pos (0U)
12300 #define OPAMP2_OTR_TRIMOFFSETN_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETN_Pos) /*!< 0x0000001F */
12301 #define OPAMP2_OTR_TRIMOFFSETN OPAMP2_OTR_TRIMOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12302 #define OPAMP2_OTR_TRIMOFFSETP_Pos (8U)
12303 #define OPAMP2_OTR_TRIMOFFSETP_Msk (0x1FUL << OPAMP2_OTR_TRIMOFFSETP_Pos) /*!< 0x00001F00 */
12304 #define OPAMP2_OTR_TRIMOFFSETP OPAMP2_OTR_TRIMOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12305
12306 /******************* Bit definition for OPAMP_HSOTR register ****************/
12307 #define OPAMP_HSOTR_TRIMHSOFFSETN_Pos (0U)
12308 #define OPAMP_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12309 #define OPAMP_HSOTR_TRIMHSOFFSETN OPAMP_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12310 #define OPAMP_HSOTR_TRIMHSOFFSETP_Pos (8U)
12311 #define OPAMP_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12312 #define OPAMP_HSOTR_TRIMHSOFFSETP OPAMP_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12313
12314 /******************* Bit definition for OPAMP1_HSOTR register ****************/
12315 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Pos (0U)
12316 #define OPAMP1_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12317 #define OPAMP1_HSOTR_TRIMHSOFFSETN OPAMP1_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12318 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Pos (8U)
12319 #define OPAMP1_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP1_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12320 #define OPAMP1_HSOTR_TRIMHSOFFSETP OPAMP1_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12321
12322 /******************* Bit definition for OPAMP2_HSOTR register ****************/
12323 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Pos (0U)
12324 #define OPAMP2_HSOTR_TRIMHSOFFSETN_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETN_Pos) /*!< 0x0000001F */
12325 #define OPAMP2_HSOTR_TRIMHSOFFSETN OPAMP2_HSOTR_TRIMHSOFFSETN_Msk /*!< Trim for NMOS differential pairs */
12326 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Pos (8U)
12327 #define OPAMP2_HSOTR_TRIMHSOFFSETP_Msk (0x1FUL << OPAMP2_HSOTR_TRIMHSOFFSETP_Pos) /*!< 0x00001F00 */
12328 #define OPAMP2_HSOTR_TRIMHSOFFSETP OPAMP2_HSOTR_TRIMHSOFFSETP_Msk /*!< Trim for PMOS differential pairs */
12329
12330 /******************************************************************************/
12331 /* */
12332 /* Parallel Synchronous Slave Interface (PSSI ) */
12333 /* */
12334 /******************************************************************************/
12335
12336 /******************** Bit definition for PSSI_CR register *******************/
12337 #define PSSI_CR_OUTEN_Pos (31U)
12338 #define PSSI_CR_OUTEN_Msk (0x1UL << PSSI_CR_OUTEN_Pos) /*!< 0x80000000 */
12339 #define PSSI_CR_OUTEN PSSI_CR_OUTEN_Msk /*!< Data direction selection */
12340 #define PSSI_CR_DMAEN_Pos (30U)
12341 #define PSSI_CR_DMAEN_Msk (0x1UL << PSSI_CR_DMAEN_Pos) /*!< 0x40000000 */
12342 #define PSSI_CR_DMAEN PSSI_CR_DMAEN_Msk /*!< DMA enable */
12343 #define PSSI_CR_DERDYCFG_Pos (18U)
12344 #define PSSI_CR_DERDYCFG_Msk (0x7UL << PSSI_CR_DERDYCFG_Pos) /*!< 0x001C0000 */
12345 #define PSSI_CR_DERDYCFG PSSI_CR_DERDYCFG_Msk /*!< Data enable and ready configuration */
12346 #define PSSI_CR_ENABLE_Pos (14U)
12347 #define PSSI_CR_ENABLE_Msk (0x1UL << PSSI_CR_ENABLE_Pos) /*!< 0x00004000 */
12348 #define PSSI_CR_ENABLE PSSI_CR_ENABLE_Msk /*!< PSSI enable */
12349 #define PSSI_CR_EDM_Pos (10U)
12350 #define PSSI_CR_EDM_Msk (0x3UL << PSSI_CR_EDM_Pos) /*!< 0x00000C00 */
12351 #define PSSI_CR_EDM PSSI_CR_EDM_Msk /*!< Extended data mode */
12352 #define PSSI_CR_RDYPOL_Pos (8U)
12353 #define PSSI_CR_RDYPOL_Msk (0x1UL << PSSI_CR_RDYPOL_Pos) /*!< 0x00000C00 */
12354 #define PSSI_CR_RDYPOL PSSI_CR_RDYPOL_Msk /*!< Ready polarity */
12355 #define PSSI_CR_DEPOL_Pos (6U)
12356 #define PSSI_CR_DEPOL_Msk (0x1UL << PSSI_CR_DEPOL_Pos) /*!< 0x00000C00 */
12357 #define PSSI_CR_DEPOL PSSI_CR_DEPOL_Msk /*!< Data enable polarity */
12358 #define PSSI_CR_CKPOL_Pos (5U)
12359 #define PSSI_CR_CKPOL_Msk (0x1UL << PSSI_CR_CKPOL_Pos) /*!< 0x00000C00 */
12360 #define PSSI_CR_CKPOL PSSI_CR_CKPOL_Msk /*!< Parallel data clock polarity */
12361 /******************** Bit definition for PSSI_SR register *******************/
12362 #define PSSI_SR_RTT1B_Pos (3U)
12363 #define PSSI_SR_RTT1B_Msk (0x1UL << PSSI_SR_RTT1B_Pos) /*!< 0x00000008 */
12364 #define PSSI_SR_RTT1B PSSI_SR_RTT1B_Msk /*!< Ready to transfer one byte */
12365 #define PSSI_SR_RTT4B_Pos (2U)
12366 #define PSSI_SR_RTT4B_Msk (0x1UL << PSSI_SR_RTT4B_Pos) /*!< 0x00000004 */
12367 #define PSSI_SR_RTT4B PSSI_SR_RTT4B_Msk /*!< Ready to transfer four bytes */
12368 /******************** Bit definition for PSSI_RIS register *******************/
12369 #define PSSI_RIS_OVR_RIS_Pos (1U)
12370 #define PSSI_RIS_OVR_RIS_Msk (0x1UL << PSSI_RIS_OVR_RIS_Pos) /*!< 0x00000002 */
12371 #define PSSI_RIS_OVR_RIS PSSI_RIS_OVR_RIS_Msk /*!< Data buffer overrun/underrun raw interrupt status */
12372 /******************** Bit definition for PSSI_IER register *******************/
12373 #define PSSI_IER_OVR_IE_Pos (1U)
12374 #define PSSI_IER_OVR_IE_Msk (0x1UL << PSSI_IER_OVR_IE_Pos) /*!< 0x00000002 */
12375 #define PSSI_IER_OVR_IE PSSI_IER_OVR_IE_Msk /*!< Data buffer overrun/underrun interrupt enable */
12376 /******************** Bit definition for PSSI_MIS register *******************/
12377 #define PSSI_MIS_OVR_MIS_Pos (1U)
12378 #define PSSI_MIS_OVR_MIS_Msk (0x1UL << PSSI_MIS_OVR_MIS_Pos) /*!< 0x00000002 */
12379 #define PSSI_MIS_OVR_MIS PSSI_MIS_OVR_MIS_Msk /*!< Data buffer overrun/underrun masked interrupt status */
12380 /******************** Bit definition for PSSI_ICR register *******************/
12381 #define PSSI_ICR_OVR_ISC_Pos (1U)
12382 #define PSSI_ICR_OVR_ISC_Msk (0x1UL << PSSI_ICR_OVR_ISC_Pos) /*!< 0x00000002 */
12383 #define PSSI_ICR_OVR_ISC PSSI_ICR_OVR_ISC_Msk /*!< Data buffer overrun/underrun interrupt status clear */
12384 /******************** Bit definition for PSSI_DR register *******************/
12385 #define PSSI_DR_DR_Pos (0U)
12386 #define PSSI_DR_DR_Msk (0xFFFFFFFFUL << PSSI_DR_DR_Pos) /*!< 0xFFFFFFF */
12387 #define PSSI_DR_DR PSSI_DR_DR_Msk /*!< Data register */
12388
12389 /******************************************************************************/
12390 /* */
12391 /* On The Fly Decryption */
12392 /* */
12393 /******************************************************************************/
12394 /****************** Bit definition for OTFDEC_CR register ******************/
12395 #define OTFDEC_CR_ENC_Pos (0U)
12396 #define OTFDEC_CR_ENC_Msk (0x1UL << OTFDEC_CR_ENC_Pos) /*!< 0x00000001 */
12397 #define OTFDEC_CR_ENC OTFDEC_CR_ENC_Msk /*!< Encryption mode bit */
12398
12399 /****************** Bit definition for OTFDEC_PRIVCFGR register ************/
12400 #define OTFDEC_PRIVCFGR_PRIV_Pos (0U)
12401 #define OTFDEC_PRIVCFGR_PRIV_Msk (0x1UL << OTFDEC_PRIVCFGR_PRIV_Pos) /*!< 0x00000001 */
12402 #define OTFDEC_PRIVCFGR_PRIV OTFDEC_PRIVCFGR_PRIV_Msk /*!< Privileged access protection */
12403
12404 /****************** Bit definition for OTFDEC_REG_CONFIGR register *********/
12405 #define OTFDEC_REG_CONFIGR_REG_EN_Pos (0U)
12406 #define OTFDEC_REG_CONFIGR_REG_EN_Msk (0x1UL << OTFDEC_REG_CONFIGR_REG_EN_Pos) /*!< 0x00000001 */
12407 #define OTFDEC_REG_CONFIGR_REG_EN OTFDEC_REG_CONFIGR_REG_EN_Msk /*!< Region on-the-fly decryption enable */
12408
12409 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos (1U)
12410 #define OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_CONFIGLOCK_Pos) /*!< 0x00000002 */
12411 #define OTFDEC_REG_CONFIGR_CONFIGLOCK OTFDEC_REG_CONFIGR_CONFIGLOCK_Msk /*!< Region config lock */
12412
12413 #define OTFDEC_REG_CONFIGR_KEYLOCK_Pos (2U)
12414 #define OTFDEC_REG_CONFIGR_KEYLOCK_Msk (0x1UL << OTFDEC_REG_CONFIGR_KEYLOCK_Pos) /*!< 0x00000004 */
12415 #define OTFDEC_REG_CONFIGR_KEYLOCK OTFDEC_REG_CONFIGR_KEYLOCK_Msk /*!< Region key lock */
12416
12417 #define OTFDEC_REG_CONFIGR_MODE_Pos (4U)
12418 #define OTFDEC_REG_CONFIGR_MODE_Msk (0x3UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000030 */
12419 #define OTFDEC_REG_CONFIGR_MODE OTFDEC_REG_CONFIGR_MODE_Msk /*!< Region operating mode */
12420 #define OTFDEC_REG_CONFIGR_MODE_0 (0x1UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000010 */
12421 #define OTFDEC_REG_CONFIGR_MODE_1 (0x2UL << OTFDEC_REG_CONFIGR_MODE_Pos) /*!< 0x00000020 */
12422
12423 #define OTFDEC_REG_CONFIGR_KEYCRC_Pos (8U)
12424 #define OTFDEC_REG_CONFIGR_KEYCRC_Msk (0xFFUL << OTFDEC_REG_CONFIGR_KEYCRC_Pos) /*!< 0x0000FF00 */
12425 #define OTFDEC_REG_CONFIGR_KEYCRC OTFDEC_REG_CONFIGR_KEYCRC_Msk /*!< Region key 8-bit CRC */
12426
12427 #define OTFDEC_REG_CONFIGR_VERSION_Pos (16U)
12428 #define OTFDEC_REG_CONFIGR_VERSION_Msk (0xFFFFUL << OTFDEC_REG_CONFIGR_VERSION_Pos) /*!< 0xFFFF0000 */
12429 #define OTFDEC_REG_CONFIGR_VERSION OTFDEC_REG_CONFIGR_VERSION_Msk /*!< Region firmware version */
12430
12431 /****************** Bit definition for OTFDEC_REG_START_ADDR register ******/
12432 #define OTFDEC_REG_START_ADDR_Pos (0U)
12433 #define OTFDEC_REG_START_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_START_ADDR_Pos) /*!< 0xFFFFFFFF */
12434 #define OTFDEC_REG_START_ADDR OTFDEC_REG_START_ADDR_Msk /*!< Region AHB start address */
12435
12436 /****************** Bit definition for OTFDEC_REG_END_ADDR register ********/
12437 #define OTFDEC_REG_END_ADDR_Pos (0U)
12438 #define OTFDEC_REG_END_ADDR_Msk (0xFFFFFFFFUL << OTFDEC_REG_END_ADDR_Pos) /*!< 0xFFFFFFFF */
12439 #define OTFDEC_REG_END_ADDR OTFDEC_REG_END_ADDR_Msk /*!< Region AHB end address */
12440
12441 /****************** Bit definition for OTFDEC_REG_NONCER0 register *********/
12442 #define OTFDEC_REG_NONCER0_Pos (0U)
12443 #define OTFDEC_REG_NONCER0_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER0_Pos) /*!< 0xFFFFFFFF */
12444 #define OTFDEC_REG_NONCER0 OTFDEC_REG_NONCER0_Msk /*!< Region Nonce Register (LSB nonce[31:0]) */
12445
12446 /****************** Bit definition for OTFDEC_REG_NONCER1 register *********/
12447 #define OTFDEC_REG_NONCER1_Pos (0U)
12448 #define OTFDEC_REG_NONCER1_Msk (0xFFFFFFFFUL << OTFDEC_REG_NONCER1_Pos) /*!< 0xFFFFFFFF */
12449 #define OTFDEC_REG_NONCER1 OTFDEC_REG_NONCER1_Msk /*!< Region Nonce Register (MSB nonce[63:32]) */
12450
12451 /****************** Bit definition for OTFDEC_REG_KEYR0 register ***********/
12452 #define OTFDEC_REG_KEYR0_Pos (0U)
12453 #define OTFDEC_REG_KEYR0_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR0_Pos) /*!< 0xFFFFFFFF */
12454 #define OTFDEC_REG_KEYR0 OTFDEC_REG_KEYR0_Msk /*!< Region Key Register (LSB key[31:0]) */
12455
12456 /****************** Bit definition for OTFDEC_REG_KEYR1 register ***********/
12457 #define OTFDEC_REG_KEYR1_Pos (0U)
12458 #define OTFDEC_REG_KEYR1_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR1_Pos) /*!< 0xFFFFFFFF */
12459 #define OTFDEC_REG_KEYR1 OTFDEC_REG_KEYR1_Msk /*!< Region Key Register (key[63:32]) */
12460
12461 /****************** Bit definition for OTFDEC_REG_KEYR2 register ***********/
12462 #define OTFDEC_REG_KEYR2_Pos (0U)
12463 #define OTFDEC_REG_KEYR2_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR2_Pos) /*!< 0xFFFFFFFF */
12464 #define OTFDEC_REG_KEYR2 OTFDEC_REG_KEYR2_Msk /*!< Region Key Register (key[95:64]) */
12465
12466 /****************** Bit definition for OTFDEC_REG_KEYR3 register ***********/
12467 #define OTFDEC_REG_KEYR3_Pos (0U)
12468 #define OTFDEC_REG_KEYR3_Msk (0xFFFFFFFFUL << OTFDEC_REG_KEYR3_Pos) /*!< 0xFFFFFFFF */
12469 #define OTFDEC_REG_KEYR3 OTFDEC_REG_KEYR3_Msk /*!< Region Key Register (key[127:96]) */
12470
12471 /****************** Bit definition for OTFDEC_ISR register *****************/
12472 #define OTFDEC_ISR_SEIF_Pos (0U)
12473 #define OTFDEC_ISR_SEIF_Msk (0x1UL << OTFDEC_ISR_SEIF_Pos) /*!< 0x00000001 */
12474 #define OTFDEC_ISR_SEIF OTFDEC_ISR_SEIF_Msk /*!< Security Error Interrupt Flag status bit before enable (mask) */
12475
12476 #define OTFDEC_ISR_XONEIF_Pos (1U)
12477 #define OTFDEC_ISR_XONEIF_Msk (0x1UL << OTFDEC_ISR_XONEIF_Pos) /*!< 0x00000002 */
12478 #define OTFDEC_ISR_XONEIF OTFDEC_ISR_XONEIF_Msk /*!< Execute-only Error Interrupt Flag status bit before enable (mask) */
12479
12480 #define OTFDEC_ISR_KEIF_Pos (2U)
12481 #define OTFDEC_ISR_KEIF_Msk (0x1UL << OTFDEC_ISR_KEIF_Pos) /*!< 0x00000004 */
12482 #define OTFDEC_ISR_KEIF OTFDEC_ISR_KEIF_Msk /*!< Key Error Interrupt Flag status bit before enable (mask) */
12483
12484 /****************** Bit definition for OTFDEC_ICR register *****************/
12485 #define OTFDEC_ICR_SEIF_Pos (0U)
12486 #define OTFDEC_ICR_SEIF_Msk (0x1UL << OTFDEC_ICR_SEIF_Pos) /*!< 0x00000001 */
12487 #define OTFDEC_ICR_SEIF OTFDEC_ICR_SEIF_Msk /*!< Security Error Interrupt Flag clear bit */
12488
12489 #define OTFDEC_ICR_XONEIF_Pos (1U)
12490 #define OTFDEC_ICR_XONEIF_Msk (0x1UL << OTFDEC_ICR_XONEIF_Pos) /*!< 0x00000002 */
12491 #define OTFDEC_ICR_XONEIF OTFDEC_ICR_XONEIF_Msk /*!< Execute-only Error Interrupt Flag clear bit */
12492
12493 #define OTFDEC_ICR_KEIF_Pos (2U)
12494 #define OTFDEC_ICR_KEIF_Msk (0x1UL << OTFDEC_ICR_KEIF_Pos) /*!< 0x00000004 */
12495 #define OTFDEC_ICR_KEIF OTFDEC_ICR_KEIF_Msk /*!< Key Error Interrupt Flag clear bit */
12496
12497 /****************** Bit definition for OTFDEC_IER register *****************/
12498 #define OTFDEC_IER_SEIE_Pos (0U)
12499 #define OTFDEC_IER_SEIE_Msk (0x1UL << OTFDEC_IER_SEIE_Pos) /*!< 0x00000001 */
12500 #define OTFDEC_IER_SEIE OTFDEC_IER_SEIE_Msk /*!< Security Error Interrupt Enable bit */
12501
12502 #define OTFDEC_IER_XONEIE_Pos (1U)
12503 #define OTFDEC_IER_XONEIE_Msk (0x1UL << OTFDEC_IER_XONEIE_Pos) /*!< 0x00000002 */
12504 #define OTFDEC_IER_XONEIE OTFDEC_IER_XONEIE_Msk /*!< Execute-only Error Interrupt Enable bit */
12505
12506 #define OTFDEC_IER_KEIE_Pos (2U)
12507 #define OTFDEC_IER_KEIE_Msk (0x1UL << OTFDEC_IER_KEIE_Pos) /*!< 0x00000004 */
12508 #define OTFDEC_IER_KEIE OTFDEC_IER_KEIE_Msk
12509
12510 /******************************************************************************/
12511 /* */
12512 /* Power Control */
12513 /* */
12514 /******************************************************************************/
12515 /************************* NUMBER OF POWER DOMAINS **************************/
12516 #define POWER_DOMAINS_NUMBER 2U /*!< 2 Domains */
12517
12518 /******************** Bit definition for PWR_CR1 register *******************/
12519 #define PWR_CR1_SRDRAMSO_Pos (27U)
12520 #define PWR_CR1_SRDRAMSO_Msk (0x1UL << PWR_CR1_SRDRAMSO_Pos) /*!< 0x08000000 */
12521 #define PWR_CR1_SRDRAMSO PWR_CR1_SRDRAMSO_Msk /*!< SmartRun Domain AHB Memory Shut-Off in DStop/DStop2 Low-Power Mode */
12522 #define PWR_CR1_HSITFSO_Pos (26U)
12523 #define PWR_CR1_HSITFSO_Msk (0x1UL << PWR_CR1_HSITFSO_Pos) /*!< 0x04000000 */
12524 #define PWR_CR1_HSITFSO PWR_CR1_HSITFSO_Msk /*!< High-Speed Interfaces USB and FDCAN Memories Shut-off in DStop/DStop2 Mode */
12525 #define PWR_CR1_GFXSO_Pos (25U)
12526 #define PWR_CR1_GFXSO_Msk (0x1UL << PWR_CR1_GFXSO_Pos) /*!< 0x02000000 */
12527 #define PWR_CR1_GFXSO PWR_CR1_GFXSO_Msk /*!< GFXMMU and JPEG Memories Shut-Off in DStop/DStop2 Mode */
12528 #define PWR_CR1_ITCMSO_Pos (24U)
12529 #define PWR_CR1_ITCMSO_Msk (0x1UL << PWR_CR1_ITCMSO_Pos) /*!< 0x01000000 */
12530 #define PWR_CR1_ITCMSO PWR_CR1_ITCMSO_Msk /*!< Instruction TCM and ETM Memories Shut-Off in DStop/DStop2 Mode */
12531 #define PWR_CR1_AHBRAM2SO_Pos (23U)
12532 #define PWR_CR1_AHBRAM2SO_Msk (0x1UL << PWR_CR1_AHBRAM2SO_Pos) /*!< 0x00800000 */
12533 #define PWR_CR1_AHBRAM2SO PWR_CR1_AHBRAM2SO_Msk /*!< AHB RAM2 Shut-Off in DStop/DStop2 Mode */
12534 #define PWR_CR1_AHBRAM1SO_Pos (22U)
12535 #define PWR_CR1_AHBRAM1SO_Msk (0x1UL << PWR_CR1_AHBRAM1SO_Pos) /*!< 0x00400000 */
12536 #define PWR_CR1_AHBRAM1SO PWR_CR1_AHBRAM1SO_Msk /*!< AHB RAM1 Shut-Off in DStop/DStop2 Mode */
12537 #define PWR_CR1_AXIRAM3SO_Pos (21U)
12538 #define PWR_CR1_AXIRAM3SO_Msk (0x1UL << PWR_CR1_AXIRAM3SO_Pos) /*!< 0x00200000 */
12539 #define PWR_CR1_AXIRAM3SO PWR_CR1_AXIRAM3SO_Msk /*!< AXI RAM3 Shut-Off in DStop/DStop2 Mode */
12540 #define PWR_CR1_AXIRAM2SO_Pos (20U)
12541 #define PWR_CR1_AXIRAM2SO_Msk (0x1UL << PWR_CR1_AXIRAM2SO_Pos) /*!< 0x00100000 */
12542 #define PWR_CR1_AXIRAM2SO PWR_CR1_AXIRAM2SO_Msk /*!< AXI RAM2 Shut-Off in DStop/DStop2 Mode */
12543 #define PWR_CR1_AXIRAM1SO_Pos (19U)
12544 #define PWR_CR1_AXIRAM1SO_Msk (0x1UL << PWR_CR1_AXIRAM1SO_Pos) /*!< 0x00080000 */
12545 #define PWR_CR1_AXIRAM1SO PWR_CR1_AXIRAM1SO_Msk /*!< AXI RAM1 Shut-Off in DStop/DStop2 Mode */
12546 #define PWR_CR1_ALS_Pos (17U)
12547 #define PWR_CR1_ALS_Msk (0x3UL << PWR_CR1_ALS_Pos) /*!< 0x00060000 */
12548 #define PWR_CR1_ALS PWR_CR1_ALS_Msk /*!< Analog Voltage Detector level selection */
12549 #define PWR_CR1_ALS_0 (0x1UL << PWR_CR1_ALS_Pos) /*!< 0x00020000 */
12550 #define PWR_CR1_ALS_1 (0x2UL << PWR_CR1_ALS_Pos) /*!< 0x00040000 */
12551 #define PWR_CR1_AVDEN_Pos (16U)
12552 #define PWR_CR1_AVDEN_Msk (0x1UL << PWR_CR1_AVDEN_Pos) /*!< 0x00010000 */
12553 #define PWR_CR1_AVDEN PWR_CR1_AVDEN_Msk /*!< Analog Voltage Detector Enable */
12554 #define PWR_CR1_SVOS_Pos (14U)
12555 #define PWR_CR1_SVOS_Msk (0x3UL << PWR_CR1_SVOS_Pos) /*!< 0x0000C000 */
12556 #define PWR_CR1_SVOS PWR_CR1_SVOS_Msk /*!< System STOP mode Voltage Scaling selection */
12557 #define PWR_CR1_SVOS_0 (0x1UL << PWR_CR1_SVOS_Pos) /*!< 0x00004000 */
12558 #define PWR_CR1_SVOS_1 (0x2UL << PWR_CR1_SVOS_Pos) /*!< 0x00008000 */
12559 #define PWR_CR1_AVD_READY_Pos (13U)
12560 #define PWR_CR1_AVD_READY_Msk (0x1UL << PWR_CR1_AVD_READY_Pos) /*!< 0x00002000 */
12561 #define PWR_CR1_AVD_READY PWR_CR1_AVD_READY_Msk /*!< Analog Voltage Ready. */
12562 #define PWR_CR1_BOOSTE_Pos (12U)
12563 #define PWR_CR1_BOOSTE_Msk (0x1UL << PWR_CR1_BOOSTE_Pos) /*!< 0x00001000 */
12564 #define PWR_CR1_BOOSTE PWR_CR1_BOOSTE_Msk /*!< Analog Switch VBoost control */
12565 #define PWR_CR1_FLPS_Pos (9U)
12566 #define PWR_CR1_FLPS_Msk (0x1UL << PWR_CR1_FLPS_Pos) /*!< 0x00000200 */
12567 #define PWR_CR1_FLPS PWR_CR1_FLPS_Msk /*!< Flash low power mode in DSTOP */
12568 #define PWR_CR1_DBP_Pos (8U)
12569 #define PWR_CR1_DBP_Msk (0x1UL << PWR_CR1_DBP_Pos) /*!< 0x00000100 */
12570 #define PWR_CR1_DBP PWR_CR1_DBP_Msk /*!< Disable Back-up domain Protection */
12571 #define PWR_CR1_PLS_Pos (5U)
12572 #define PWR_CR1_PLS_Msk (0x7UL << PWR_CR1_PLS_Pos) /*!< 0x000000E0 */
12573 #define PWR_CR1_PLS PWR_CR1_PLS_Msk /*!< Programmable Voltage Detector level selection */
12574 #define PWR_CR1_PLS_0 (0x1UL << PWR_CR1_PLS_Pos) /*!< 0x00000020 */
12575 #define PWR_CR1_PLS_1 (0x2UL << PWR_CR1_PLS_Pos) /*!< 0x00000040 */
12576 #define PWR_CR1_PLS_2 (0x4UL << PWR_CR1_PLS_Pos) /*!< 0x00000080 */
12577 #define PWR_CR1_PVDEN_Pos (4U)
12578 #define PWR_CR1_PVDEN_Msk (0x1UL << PWR_CR1_PVDEN_Pos) /*!< 0x00000010 */
12579 #define PWR_CR1_PVDEN PWR_CR1_PVDEN_Msk /*!< Programmable Voltage detector enable */
12580 #define PWR_CR1_LPDS_Pos (0U)
12581 #define PWR_CR1_LPDS_Msk (0x1UL << PWR_CR1_LPDS_Pos) /*!< 0x00000001 */
12582 #define PWR_CR1_LPDS PWR_CR1_LPDS_Msk /*!< Low Power Deepsleep with SVOS3 */
12583
12584 /*!< PVD level configuration */
12585 #define PWR_CR1_PLS_LEV0 (0UL) /*!< PVD level 0 */
12586 #define PWR_CR1_PLS_LEV1_Pos (5U)
12587 #define PWR_CR1_PLS_LEV1_Msk (0x1UL << PWR_CR1_PLS_LEV1_Pos) /*!< 0x00000020 */
12588 #define PWR_CR1_PLS_LEV1 PWR_CR1_PLS_LEV1_Msk /*!< PVD level 1 */
12589 #define PWR_CR1_PLS_LEV2_Pos (6U)
12590 #define PWR_CR1_PLS_LEV2_Msk (0x1UL << PWR_CR1_PLS_LEV2_Pos) /*!< 0x00000040 */
12591 #define PWR_CR1_PLS_LEV2 PWR_CR1_PLS_LEV2_Msk /*!< PVD level 2 */
12592 #define PWR_CR1_PLS_LEV3_Pos (5U)
12593 #define PWR_CR1_PLS_LEV3_Msk (0x3UL << PWR_CR1_PLS_LEV3_Pos) /*!< 0x00000060 */
12594 #define PWR_CR1_PLS_LEV3 PWR_CR1_PLS_LEV3_Msk /*!< PVD level 3 */
12595 #define PWR_CR1_PLS_LEV4_Pos (7U)
12596 #define PWR_CR1_PLS_LEV4_Msk (0x1UL << PWR_CR1_PLS_LEV4_Pos) /*!< 0x00000080 */
12597 #define PWR_CR1_PLS_LEV4 PWR_CR1_PLS_LEV4_Msk /*!< PVD level 4 */
12598 #define PWR_CR1_PLS_LEV5_Pos (5U)
12599 #define PWR_CR1_PLS_LEV5_Msk (0x5UL << PWR_CR1_PLS_LEV5_Pos) /*!< 0x000000A0 */
12600 #define PWR_CR1_PLS_LEV5 PWR_CR1_PLS_LEV5_Msk /*!< PVD level 5 */
12601 #define PWR_CR1_PLS_LEV6_Pos (6U)
12602 #define PWR_CR1_PLS_LEV6_Msk (0x3UL << PWR_CR1_PLS_LEV6_Pos) /*!< 0x000000C0 */
12603 #define PWR_CR1_PLS_LEV6 PWR_CR1_PLS_LEV6_Msk /*!< PVD level 6 */
12604 #define PWR_CR1_PLS_LEV7_Pos (5U)
12605 #define PWR_CR1_PLS_LEV7_Msk (0x7UL << PWR_CR1_PLS_LEV7_Pos) /*!< 0x000000E0 */
12606 #define PWR_CR1_PLS_LEV7 PWR_CR1_PLS_LEV7_Msk /*!< PVD level 7 */
12607
12608 /*!< AVD level configuration */
12609 #define PWR_CR1_ALS_LEV0 (0UL) /*!< AVD level 0 */
12610 #define PWR_CR1_ALS_LEV1_Pos (17U)
12611 #define PWR_CR1_ALS_LEV1_Msk (0x1UL << PWR_CR1_ALS_LEV1_Pos) /*!< 0x00020000 */
12612 #define PWR_CR1_ALS_LEV1 PWR_CR1_ALS_LEV1_Msk /*!< AVD level 1 */
12613 #define PWR_CR1_ALS_LEV2_Pos (18U)
12614 #define PWR_CR1_ALS_LEV2_Msk (0x1UL << PWR_CR1_ALS_LEV2_Pos) /*!< 0x00040000 */
12615 #define PWR_CR1_ALS_LEV2 PWR_CR1_ALS_LEV2_Msk /*!< AVD level 2 */
12616 #define PWR_CR1_ALS_LEV3_Pos (17U)
12617 #define PWR_CR1_ALS_LEV3_Msk (0x3UL << PWR_CR1_ALS_LEV3_Pos) /*!< 0x00060000 */
12618 #define PWR_CR1_ALS_LEV3 PWR_CR1_ALS_LEV3_Msk /*!< AVD level 3 */
12619
12620 /******************** Bit definition for PWR_CSR1 register ******************/
12621 #define PWR_CSR1_MMCVDO_Pos (17U)
12622 #define PWR_CSR1_MMCVDO_Msk (0x1UL << PWR_CSR1_MMCVDO_Pos) /*!< 0x00020000 */
12623 #define PWR_CSR1_MMCVDO PWR_CSR1_MMCVDO_Msk /*!< voltage detector output on VDDMMC */
12624 #define PWR_CSR1_AVDO_Pos (16U)
12625 #define PWR_CSR1_AVDO_Msk (0x1UL << PWR_CSR1_AVDO_Pos) /*!< 0x00010000 */
12626 #define PWR_CSR1_AVDO PWR_CSR1_AVDO_Msk /*!< Analog Voltage Detect Output */
12627 #define PWR_CSR1_ACTVOS_Pos (14U)
12628 #define PWR_CSR1_ACTVOS_Msk (0x3UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x0000C000 */
12629 #define PWR_CSR1_ACTVOS PWR_CSR1_ACTVOS_Msk /*!< Current actual used VOS for VDD11 Voltage Scaling */
12630 #define PWR_CSR1_ACTVOS_0 (0x1UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00004000 */
12631 #define PWR_CSR1_ACTVOS_1 (0x2UL << PWR_CSR1_ACTVOS_Pos) /*!< 0x00008000 */
12632 #define PWR_CSR1_ACTVOSRDY_Pos (13U)
12633 #define PWR_CSR1_ACTVOSRDY_Msk (0x1UL << PWR_CSR1_ACTVOSRDY_Pos) /*!< 0x00002000 */
12634 #define PWR_CSR1_ACTVOSRDY PWR_CSR1_ACTVOSRDY_Msk /*!< Ready bit for current actual used VOS for VDD11 Voltage Scaling */
12635 #define PWR_CSR1_PVDO_Pos (4U)
12636 #define PWR_CSR1_PVDO_Msk (0x1UL << PWR_CSR1_PVDO_Pos) /*!< 0x00000010 */
12637 #define PWR_CSR1_PVDO PWR_CSR1_PVDO_Msk /*!< Programmable Voltage Detect Output */
12638
12639 /******************** Bit definition for PWR_CR2 register *******************/
12640 #define PWR_CR2_TEMPH_Pos (23U)
12641 #define PWR_CR2_TEMPH_Msk (0x1UL << PWR_CR2_TEMPH_Pos) /*!< 0x00800000 */
12642 #define PWR_CR2_TEMPH PWR_CR2_TEMPH_Msk /*!< Monitored temperature level above high threshold */
12643 #define PWR_CR2_TEMPL_Pos (22U)
12644 #define PWR_CR2_TEMPL_Msk (0x1UL << PWR_CR2_TEMPL_Pos) /*!< 0x00400000 */
12645 #define PWR_CR2_TEMPL PWR_CR2_TEMPL_Msk /*!< Monitored temperature level above low threshold */
12646 #define PWR_CR2_VBATH_Pos (21U)
12647 #define PWR_CR2_VBATH_Msk (0x1UL << PWR_CR2_VBATH_Pos) /*!< 0x00200000 */
12648 #define PWR_CR2_VBATH PWR_CR2_VBATH_Msk /*!< Monitored VBAT level above high threshold */
12649 #define PWR_CR2_VBATL_Pos (20U)
12650 #define PWR_CR2_VBATL_Msk (0x1UL << PWR_CR2_VBATL_Pos) /*!< 0x00100000 */
12651 #define PWR_CR2_VBATL PWR_CR2_VBATL_Msk /*!< Monitored VBAT level above low threshold */
12652 #define PWR_CR2_BRRDY_Pos (16U)
12653 #define PWR_CR2_BRRDY_Msk (0x1UL << PWR_CR2_BRRDY_Pos) /*!< 0x00010000 */
12654 #define PWR_CR2_BRRDY PWR_CR2_BRRDY_Msk /*!< Backup regulator ready */
12655 #define PWR_CR2_MONEN_Pos (4U)
12656 #define PWR_CR2_MONEN_Msk (0x1UL << PWR_CR2_MONEN_Pos) /*!< 0x00000010 */
12657 #define PWR_CR2_MONEN PWR_CR2_MONEN_Msk /*!< VBAT and temperature monitoring enable */
12658 #define PWR_CR2_BREN_Pos (0U)
12659 #define PWR_CR2_BREN_Msk (0x1UL << PWR_CR2_BREN_Pos) /*!< 0x00000001 */
12660 #define PWR_CR2_BREN PWR_CR2_BREN_Msk /*!< Backup regulator enable */
12661
12662 /******************** Bit definition for PWR_CR3 register *******************/
12663 #define PWR_CR3_USB33RDY_Pos (26U)
12664 #define PWR_CR3_USB33RDY_Msk (0x1UL << PWR_CR3_USB33RDY_Pos) /*!< 0x04000000 */
12665 #define PWR_CR3_USB33RDY PWR_CR3_USB33RDY_Msk /*!< USB supply ready */
12666 #define PWR_CR3_USBREGEN_Pos (25U)
12667 #define PWR_CR3_USBREGEN_Msk (0x1UL << PWR_CR3_USBREGEN_Pos) /*!< 0x02000000 */
12668 #define PWR_CR3_USBREGEN PWR_CR3_USBREGEN_Msk /*!< USB regulator enable */
12669 #define PWR_CR3_USB33DEN_Pos (24U)
12670 #define PWR_CR3_USB33DEN_Msk (0x1UL << PWR_CR3_USB33DEN_Pos) /*!< 0x01000000 */
12671 #define PWR_CR3_USB33DEN PWR_CR3_USB33DEN_Msk /*!< VDD33_USB voltage level detector enable */
12672 #define PWR_CR3_SMPSEXTRDY_Pos (16U)
12673 #define PWR_CR3_SMPSEXTRDY_Msk (0x1UL << PWR_CR3_SMPSEXTRDY_Pos) /*!< 0x00010000 */
12674 #define PWR_CR3_SMPSEXTRDY PWR_CR3_SMPSEXTRDY_Msk /*!< SMPS External supply ready */
12675 #define PWR_CR3_VBRS_Pos (9U)
12676 #define PWR_CR3_VBRS_Msk (0x1UL << PWR_CR3_VBRS_Pos) /*!< 0x00000200 */
12677 #define PWR_CR3_VBRS PWR_CR3_VBRS_Msk /*!< VBAT charging resistor selection */
12678 #define PWR_CR3_VBE_Pos (8U)
12679 #define PWR_CR3_VBE_Msk (0x1UL << PWR_CR3_VBE_Pos) /*!< 0x00000100 */
12680 #define PWR_CR3_VBE PWR_CR3_VBE_Msk /*!< VBAT charging enable */
12681 #define PWR_CR3_SMPSLEVEL_Pos (4U)
12682 #define PWR_CR3_SMPSLEVEL_Msk (0x3UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000030 */
12683 #define PWR_CR3_SMPSLEVEL PWR_CR3_SMPSLEVEL_Msk /*!< SMPS output Voltage */
12684 #define PWR_CR3_SMPSLEVEL_0 (0x1UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000010 */
12685 #define PWR_CR3_SMPSLEVEL_1 (0x2UL << PWR_CR3_SMPSLEVEL_Pos) /*!< 0x00000020 */
12686 #define PWR_CR3_SMPSEXTHP_Pos (3U)
12687 #define PWR_CR3_SMPSEXTHP_Msk (0x1UL << PWR_CR3_SMPSEXTHP_Pos) /*!< 0x00000008 */
12688 #define PWR_CR3_SMPSEXTHP PWR_CR3_SMPSEXTHP_Msk /*!< SMPS forced ON and in High Power MR mode */
12689 #define PWR_CR3_SMPSEN_Pos (2U)
12690 #define PWR_CR3_SMPSEN_Msk (0x1UL << PWR_CR3_SMPSEN_Pos) /*!< 0x00000004 */
12691 #define PWR_CR3_SMPSEN PWR_CR3_SMPSEN_Msk /*!< SMPS Enable */
12692 #define PWR_CR3_LDOEN_Pos (1U)
12693 #define PWR_CR3_LDOEN_Msk (0x1UL << PWR_CR3_LDOEN_Pos) /*!< 0x00000002 */
12694 #define PWR_CR3_LDOEN PWR_CR3_LDOEN_Msk /*!< Low Drop Output regulator enable */
12695 #define PWR_CR3_BYPASS_Pos (0U)
12696 #define PWR_CR3_BYPASS_Msk (0x1UL << PWR_CR3_BYPASS_Pos) /*!< 0x00000001 */
12697 #define PWR_CR3_BYPASS PWR_CR3_BYPASS_Msk /*!< Power Management Unit bypass */
12698
12699 /******************** Bit definition for PWR_CPUCR register *****************/
12700 #define PWR_CPUCR_RUN_SRD_Pos (11U)
12701 #define PWR_CPUCR_RUN_SRD_Msk (0x1UL << PWR_CPUCR_RUN_SRD_Pos) /*!< 0x00000800 */
12702 #define PWR_CPUCR_RUN_SRD PWR_CPUCR_RUN_SRD_Msk /*!< Keep system SRD domain in RUN mode regardless of the CPU sub-systems modes */
12703 #define PWR_CPUCR_CSSF_Pos (9U)
12704 #define PWR_CPUCR_CSSF_Msk (0x1UL << PWR_CPUCR_CSSF_Pos) /*!< 0x00000200 */
12705 #define PWR_CPUCR_CSSF PWR_CPUCR_CSSF_Msk /*!< Clear D1 domain CPU1 STANDBY, STOP and HOLD flags */
12706 #define PWR_CPUCR_SBF_Pos (6U)
12707 #define PWR_CPUCR_SBF_Msk (0x1UL << PWR_CPUCR_SBF_Pos) /*!< 0x00000040 */
12708 #define PWR_CPUCR_SBF PWR_CPUCR_SBF_Msk /*!< System STANDBY Flag */
12709 #define PWR_CPUCR_STOPF_Pos (5U)
12710 #define PWR_CPUCR_STOPF_Msk (0x1UL << PWR_CPUCR_STOPF_Pos) /*!< 0x00000020 */
12711 #define PWR_CPUCR_STOPF PWR_CPUCR_STOPF_Msk /*!< STOP Flag */
12712 #define PWR_CPUCR_PDDS_SRD_Pos (2U)
12713 #define PWR_CPUCR_PDDS_SRD_Msk (0x1UL << PWR_CPUCR_PDDS_SRD_Pos) /*!< 0x00000004 */
12714 #define PWR_CPUCR_PDDS_SRD PWR_CPUCR_PDDS_SRD_Msk /*!< System SRD domain Power Down Deepsleep */
12715 #define PWR_CPUCR_RETDS_CD_Pos (0U)
12716 #define PWR_CPUCR_RETDS_CD_Msk (0x1UL << PWR_CPUCR_RETDS_CD_Pos) /*!< 0x00000001 */
12717 #define PWR_CPUCR_RETDS_CD PWR_CPUCR_RETDS_CD_Msk /*!< CD domain Power Down Deepsleep selection */
12718 /******************** Bit definition for PWR_SRDCR register *****************/
12719 #define PWR_SRDCR_VOS_Pos (14U)
12720 #define PWR_SRDCR_VOS_Msk (0x3UL << PWR_SRDCR_VOS_Pos) /*!< 0x0000C000 */
12721 #define PWR_SRDCR_VOS PWR_SRDCR_VOS_Msk /*!< Voltage Scaling selection according performance */
12722 #define PWR_SRDCR_VOS_0 (0x1UL << PWR_SRDCR_VOS_Pos) /*!< 0x00004000 */
12723 #define PWR_SRDCR_VOS_1 (0x2UL << PWR_SRDCR_VOS_Pos) /*!< 0x00008000 */
12724 #define PWR_SRDCR_VOSRDY_Pos (13U)
12725 #define PWR_SRDCR_VOSRDY_Msk (0x1UL << PWR_SRDCR_VOSRDY_Pos) /*!< 0x00002000 */
12726 #define PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY_Msk /*!< VOS Ready bit for VDD11 Voltage Scaling output selection */
12727 /****************** Bit definition for PWR_WKUPCR register ******************/
12728 #define PWR_WKUPCR_WKUPC6_Pos (5U)
12729 #define PWR_WKUPCR_WKUPC6_Msk (0x1UL << PWR_WKUPCR_WKUPC6_Pos) /*!< 0x00000020 */
12730 #define PWR_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6_Msk /*!< Clear Wakeup Pin Flag 6 */
12731 #define PWR_WKUPCR_WKUPC5_Pos (4U)
12732 #define PWR_WKUPCR_WKUPC5_Msk (0x1UL << PWR_WKUPCR_WKUPC5_Pos) /*!< 0x00000010 */
12733 #define PWR_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5_Msk /*!< Clear Wakeup Pin Flag 5 */
12734 #define PWR_WKUPCR_WKUPC4_Pos (3U)
12735 #define PWR_WKUPCR_WKUPC4_Msk (0x1UL << PWR_WKUPCR_WKUPC4_Pos) /*!< 0x00000008 */
12736 #define PWR_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4_Msk /*!< Clear Wakeup Pin Flag 4 */
12737 #define PWR_WKUPCR_WKUPC3_Pos (2U)
12738 #define PWR_WKUPCR_WKUPC3_Msk (0x1UL << PWR_WKUPCR_WKUPC3_Pos) /*!< 0x00000004 */
12739 #define PWR_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3_Msk /*!< Clear Wakeup Pin Flag 3 */
12740 #define PWR_WKUPCR_WKUPC2_Pos (1U)
12741 #define PWR_WKUPCR_WKUPC2_Msk (0x1UL << PWR_WKUPCR_WKUPC2_Pos) /*!< 0x00000002 */
12742 #define PWR_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2_Msk /*!< Clear Wakeup Pin Flag 2 */
12743 #define PWR_WKUPCR_WKUPC1_Pos (0U)
12744 #define PWR_WKUPCR_WKUPC1_Msk (0x1UL << PWR_WKUPCR_WKUPC1_Pos) /*!< 0x00000001 */
12745 #define PWR_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1_Msk /*!< Clear Wakeup Pin Flag 1 */
12746
12747 /******************** Bit definition for PWR_WKUPFR register ****************/
12748 #define PWR_WKUPFR_WKUPF6_Pos (5U)
12749 #define PWR_WKUPFR_WKUPF6_Msk (0x1UL << PWR_WKUPFR_WKUPF6_Pos) /*!< 0x00000020 */
12750 #define PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6_Msk /*!< Wakeup Pin Flag 6 */
12751 #define PWR_WKUPFR_WKUPF5_Pos (4U)
12752 #define PWR_WKUPFR_WKUPF5_Msk (0x1UL << PWR_WKUPFR_WKUPF5_Pos) /*!< 0x00000010 */
12753 #define PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5_Msk /*!< Wakeup Pin Flag 5 */
12754 #define PWR_WKUPFR_WKUPF4_Pos (3U)
12755 #define PWR_WKUPFR_WKUPF4_Msk (0x1UL << PWR_WKUPFR_WKUPF4_Pos) /*!< 0x00000008 */
12756 #define PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4_Msk /*!< Wakeup Pin Flag 4 */
12757 #define PWR_WKUPFR_WKUPF3_Pos (2U)
12758 #define PWR_WKUPFR_WKUPF3_Msk (0x1UL << PWR_WKUPFR_WKUPF3_Pos) /*!< 0x00000004 */
12759 #define PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3_Msk /*!< Wakeup Pin Flag 3 */
12760 #define PWR_WKUPFR_WKUPF2_Pos (1U)
12761 #define PWR_WKUPFR_WKUPF2_Msk (0x1UL << PWR_WKUPFR_WKUPF2_Pos) /*!< 0x00000002 */
12762 #define PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2_Msk /*!< Wakeup Pin Flag 2 */
12763 #define PWR_WKUPFR_WKUPF1_Pos (0U)
12764 #define PWR_WKUPFR_WKUPF1_Msk (0x1UL << PWR_WKUPFR_WKUPF1_Pos) /*!< 0x00000001 */
12765 #define PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1_Msk /*!< Wakeup Pin Flag 1 */
12766
12767 /****************** Bit definition for PWR_WKUPEPR register *****************/
12768 #define PWR_WKUPEPR_WKUPPUPD6_Pos (26U)
12769 #define PWR_WKUPEPR_WKUPPUPD6_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x0C000000 */
12770 #define PWR_WKUPEPR_WKUPPUPD6 PWR_WKUPEPR_WKUPPUPD6_Msk /*!< Wakeup Pin pull configuration for WKUP6 */
12771 #define PWR_WKUPEPR_WKUPPUPD6_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x04000000 */
12772 #define PWR_WKUPEPR_WKUPPUPD6_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD6_Pos) /*!< 0x08000000 */
12773 #define PWR_WKUPEPR_WKUPPUPD5_Pos (24U)
12774 #define PWR_WKUPEPR_WKUPPUPD5_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x03000000 */
12775 #define PWR_WKUPEPR_WKUPPUPD5 PWR_WKUPEPR_WKUPPUPD5_Msk /*!< Wakeup Pin pull configuration for WKUP5 */
12776 #define PWR_WKUPEPR_WKUPPUPD5_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x01000000 */
12777 #define PWR_WKUPEPR_WKUPPUPD5_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD5_Pos) /*!< 0x02000000 */
12778 #define PWR_WKUPEPR_WKUPPUPD4_Pos (22U)
12779 #define PWR_WKUPEPR_WKUPPUPD4_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00C00000 */
12780 #define PWR_WKUPEPR_WKUPPUPD4 PWR_WKUPEPR_WKUPPUPD4_Msk /*!< Wakeup Pin pull configuration for WKUP4 */
12781 #define PWR_WKUPEPR_WKUPPUPD4_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00400000 */
12782 #define PWR_WKUPEPR_WKUPPUPD4_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD4_Pos) /*!< 0x00800000 */
12783 #define PWR_WKUPEPR_WKUPPUPD3_Pos (20U)
12784 #define PWR_WKUPEPR_WKUPPUPD3_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00300000 */
12785 #define PWR_WKUPEPR_WKUPPUPD3 PWR_WKUPEPR_WKUPPUPD3_Msk /*!< Wakeup Pin pull configuration for WKUP3 */
12786 #define PWR_WKUPEPR_WKUPPUPD3_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00100000 */
12787 #define PWR_WKUPEPR_WKUPPUPD3_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD3_Pos) /*!< 0x00200000 */
12788 #define PWR_WKUPEPR_WKUPPUPD2_Pos (18U)
12789 #define PWR_WKUPEPR_WKUPPUPD2_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x000C0000 */
12790 #define PWR_WKUPEPR_WKUPPUPD2 PWR_WKUPEPR_WKUPPUPD2_Msk /*!< Wakeup Pin pull configuration for WKUP2 */
12791 #define PWR_WKUPEPR_WKUPPUPD2_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00040000 */
12792 #define PWR_WKUPEPR_WKUPPUPD2_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD2_Pos) /*!< 0x00080000 */
12793 #define PWR_WKUPEPR_WKUPPUPD1_Pos (16U)
12794 #define PWR_WKUPEPR_WKUPPUPD1_Msk (0x3UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00030000 */
12795 #define PWR_WKUPEPR_WKUPPUPD1 PWR_WKUPEPR_WKUPPUPD1_Msk /*!< Wakeup Pin pull configuration for WKUP1 */
12796 #define PWR_WKUPEPR_WKUPPUPD1_0 (0x1UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00010000 */
12797 #define PWR_WKUPEPR_WKUPPUPD1_1 (0x2UL << PWR_WKUPEPR_WKUPPUPD1_Pos) /*!< 0x00020000 */
12798 #define PWR_WKUPEPR_WKUPP6_Pos (13U)
12799 #define PWR_WKUPEPR_WKUPP6_Msk (0x1UL << PWR_WKUPEPR_WKUPP6_Pos) /*!< 0x00002000 */
12800 #define PWR_WKUPEPR_WKUPP6 PWR_WKUPEPR_WKUPP6_Msk /*!< Wakeup Pin Polarity for WKUP6 */
12801 #define PWR_WKUPEPR_WKUPP5_Pos (12U)
12802 #define PWR_WKUPEPR_WKUPP5_Msk (0x1UL << PWR_WKUPEPR_WKUPP5_Pos) /*!< 0x00001000 */
12803 #define PWR_WKUPEPR_WKUPP5 PWR_WKUPEPR_WKUPP5_Msk /*!< Wakeup Pin Polarity for WKUP5 */
12804 #define PWR_WKUPEPR_WKUPP4_Pos (11U)
12805 #define PWR_WKUPEPR_WKUPP4_Msk (0x1UL << PWR_WKUPEPR_WKUPP4_Pos) /*!< 0x00000800 */
12806 #define PWR_WKUPEPR_WKUPP4 PWR_WKUPEPR_WKUPP4_Msk /*!< Wakeup Pin Polarity for WKUP4 */
12807 #define PWR_WKUPEPR_WKUPP3_Pos (10U)
12808 #define PWR_WKUPEPR_WKUPP3_Msk (0x1UL << PWR_WKUPEPR_WKUPP3_Pos) /*!< 0x00000400 */
12809 #define PWR_WKUPEPR_WKUPP3 PWR_WKUPEPR_WKUPP3_Msk /*!< Wakeup Pin Polarity for WKUP3 */
12810 #define PWR_WKUPEPR_WKUPP2_Pos (9U)
12811 #define PWR_WKUPEPR_WKUPP2_Msk (0x1UL << PWR_WKUPEPR_WKUPP2_Pos) /*!< 0x00000200 */
12812 #define PWR_WKUPEPR_WKUPP2 PWR_WKUPEPR_WKUPP2_Msk /*!< Wakeup Pin Polarity for WKUP2 */
12813 #define PWR_WKUPEPR_WKUPP1_Pos (8U)
12814 #define PWR_WKUPEPR_WKUPP1_Msk (0x1UL << PWR_WKUPEPR_WKUPP1_Pos) /*!< 0x00000100 */
12815 #define PWR_WKUPEPR_WKUPP1 PWR_WKUPEPR_WKUPP1_Msk /*!< Wakeup Pin Polarity for WKUP1 */
12816 #define PWR_WKUPEPR_WKUPEN6_Pos (5U)
12817 #define PWR_WKUPEPR_WKUPEN6_Msk (0x1UL << PWR_WKUPEPR_WKUPEN6_Pos) /*!< 0x00000020 */
12818 #define PWR_WKUPEPR_WKUPEN6 PWR_WKUPEPR_WKUPEN6_Msk /*!< Enable Wakeup Pin WKUP6 */
12819 #define PWR_WKUPEPR_WKUPEN5_Pos (4U)
12820 #define PWR_WKUPEPR_WKUPEN5_Msk (0x1UL << PWR_WKUPEPR_WKUPEN5_Pos) /*!< 0x00000010 */
12821 #define PWR_WKUPEPR_WKUPEN5 PWR_WKUPEPR_WKUPEN5_Msk /*!< Enable Wakeup Pin WKUP5 */
12822 #define PWR_WKUPEPR_WKUPEN4_Pos (3U)
12823 #define PWR_WKUPEPR_WKUPEN4_Msk (0x1UL << PWR_WKUPEPR_WKUPEN4_Pos) /*!< 0x00000008 */
12824 #define PWR_WKUPEPR_WKUPEN4 PWR_WKUPEPR_WKUPEN4_Msk /*!< Enable Wakeup Pin WKUP4 */
12825 #define PWR_WKUPEPR_WKUPEN3_Pos (2U)
12826 #define PWR_WKUPEPR_WKUPEN3_Msk (0x1UL << PWR_WKUPEPR_WKUPEN3_Pos) /*!< 0x00000004 */
12827 #define PWR_WKUPEPR_WKUPEN3 PWR_WKUPEPR_WKUPEN3_Msk /*!< Enable Wakeup Pin WKUP3 */
12828 #define PWR_WKUPEPR_WKUPEN2_Pos (1U)
12829 #define PWR_WKUPEPR_WKUPEN2_Msk (0x1UL << PWR_WKUPEPR_WKUPEN2_Pos) /*!< 0x00000002 */
12830 #define PWR_WKUPEPR_WKUPEN2 PWR_WKUPEPR_WKUPEN2_Msk /*!< Enable Wakeup Pin WKUP2 */
12831 #define PWR_WKUPEPR_WKUPEN1_Pos (0U)
12832 #define PWR_WKUPEPR_WKUPEN1_Msk (0x1UL << PWR_WKUPEPR_WKUPEN1_Pos) /*!< 0x00000001 */
12833 #define PWR_WKUPEPR_WKUPEN1 PWR_WKUPEPR_WKUPEN1_Msk /*!< Enable Wakeup Pin WKUP1 */
12834 #define PWR_WKUPEPR_WKUPEN_Pos (0U)
12835 #define PWR_WKUPEPR_WKUPEN_Msk (0x3FUL << PWR_WKUPEPR_WKUPEN_Pos) /*!< 0x0000003F */
12836 #define PWR_WKUPEPR_WKUPEN PWR_WKUPEPR_WKUPEN_Msk /*!< Enable all Wakeup Pin */
12837
12838 /******************************************************************************/
12839 /* */
12840 /* Reset and Clock Control */
12841 /* */
12842 /******************************************************************************/
12843 /******************************* RCC VERSION ********************************/
12844 #define RCC_VER_2_0
12845
12846 /******************** Bit definition for RCC_CR register ********************/
12847 #define RCC_CR_HSION_Pos (0U)
12848 #define RCC_CR_HSION_Msk (0x1UL << RCC_CR_HSION_Pos) /*!< 0x00000001 */
12849 #define RCC_CR_HSION RCC_CR_HSION_Msk /*!< Internal High Speed clock enable */
12850 #define RCC_CR_HSIKERON_Pos (1U)
12851 #define RCC_CR_HSIKERON_Msk (0x1UL << RCC_CR_HSIKERON_Pos) /*!< 0x00000002 */
12852 #define RCC_CR_HSIKERON RCC_CR_HSIKERON_Msk /*!< Internal High Speed clock enable for some IPs Kernel */
12853 #define RCC_CR_HSIRDY_Pos (2U)
12854 #define RCC_CR_HSIRDY_Msk (0x1UL << RCC_CR_HSIRDY_Pos) /*!< 0x00000004 */
12855 #define RCC_CR_HSIRDY RCC_CR_HSIRDY_Msk /*!< Internal High Speed clock ready flag */
12856 #define RCC_CR_HSIDIV_Pos (3U)
12857 #define RCC_CR_HSIDIV_Msk (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
12858 #define RCC_CR_HSIDIV RCC_CR_HSIDIV_Msk /*!< Internal High Speed clock divider selection */
12859 #define RCC_CR_HSIDIV_1 (0x0UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000000 */
12860 #define RCC_CR_HSIDIV_2 (0x1UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000008 */
12861 #define RCC_CR_HSIDIV_4 (0x2UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000010 */
12862 #define RCC_CR_HSIDIV_8 (0x3UL << RCC_CR_HSIDIV_Pos) /*!< 0x00000018 */
12863
12864 #define RCC_CR_HSIDIVF_Pos (5U)
12865 #define RCC_CR_HSIDIVF_Msk (0x1UL << RCC_CR_HSIDIVF_Pos) /*!< 0x00000020 */
12866 #define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_Msk /*!< HSI Divider flag */
12867 #define RCC_CR_CSION_Pos (7U)
12868 #define RCC_CR_CSION_Msk (0x1UL << RCC_CR_CSION_Pos) /*!< 0x00000080 */
12869 #define RCC_CR_CSION RCC_CR_CSION_Msk /*!< The Internal RC 4MHz oscillator clock enable */
12870 #define RCC_CR_CSIRDY_Pos (8U)
12871 #define RCC_CR_CSIRDY_Msk (0x1UL << RCC_CR_CSIRDY_Pos) /*!< 0x00000100 */
12872 #define RCC_CR_CSIRDY RCC_CR_CSIRDY_Msk /*!< The Internal RC 4MHz oscillator clock ready */
12873 #define RCC_CR_CSIKERON_Pos (9U)
12874 #define RCC_CR_CSIKERON_Msk (0x1UL << RCC_CR_CSIKERON_Pos) /*!< 0x00000200 */
12875 #define RCC_CR_CSIKERON RCC_CR_CSIKERON_Msk /*!< Internal RC 4MHz oscillator clock enable for some IPs Kernel */
12876 #define RCC_CR_HSI48ON_Pos (12U)
12877 #define RCC_CR_HSI48ON_Msk (0x1UL << RCC_CR_HSI48ON_Pos) /*!< 0x00001000 */
12878 #define RCC_CR_HSI48ON RCC_CR_HSI48ON_Msk /*!< HSI48 clock enable clock enable */
12879 #define RCC_CR_HSI48RDY_Pos (13U)
12880 #define RCC_CR_HSI48RDY_Msk (0x1UL << RCC_CR_HSI48RDY_Pos) /*!< 0x00002000 */
12881 #define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_Msk /*!< HSI48 clock ready */
12882
12883 #define RCC_CR_CPUCKRDY_Pos (14U)
12884 #define RCC_CR_CPUCKRDY_Msk (0x1UL << RCC_CR_CPUCKRDY_Pos) /*!< 0x00004000 */
12885 #define RCC_CR_CPUCKRDY RCC_CR_CPUCKRDY_Msk /*!< CPU domain clocks ready flag */
12886 #define RCC_CR_CDCKRDY_Pos (15U)
12887 #define RCC_CR_CDCKRDY_Msk (0x1UL << RCC_CR_CDCKRDY_Pos) /*!< 0x00008000 */
12888 #define RCC_CR_CDCKRDY RCC_CR_CDCKRDY_Msk /*!< CD domain clocks ready flag */
12889
12890 #define RCC_CR_HSEON_Pos (16U)
12891 #define RCC_CR_HSEON_Msk (0x1UL << RCC_CR_HSEON_Pos) /*!< 0x00010000 */
12892 #define RCC_CR_HSEON RCC_CR_HSEON_Msk /*!< External High Speed clock enable */
12893 #define RCC_CR_HSERDY_Pos (17U)
12894 #define RCC_CR_HSERDY_Msk (0x1UL << RCC_CR_HSERDY_Pos) /*!< 0x00020000 */
12895 #define RCC_CR_HSERDY RCC_CR_HSERDY_Msk /*!< External High Speed clock ready */
12896 #define RCC_CR_HSEBYP_Pos (18U)
12897 #define RCC_CR_HSEBYP_Msk (0x1UL << RCC_CR_HSEBYP_Pos) /*!< 0x00040000 */
12898 #define RCC_CR_HSEBYP RCC_CR_HSEBYP_Msk /*!< External High Speed clock Bypass */
12899 #define RCC_CR_CSSHSEON_Pos (19U)
12900 #define RCC_CR_CSSHSEON_Msk (0x1UL << RCC_CR_CSSHSEON_Pos) /*!< 0x00080000 */
12901 #define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_Msk /*!< HSE Clock security System enable */
12902
12903 #define RCC_CR_HSEEXT_Pos (20U)
12904 #define RCC_CR_HSEEXT_Msk (0x1UL << RCC_CR_HSEEXT_Pos) /*!< 0x00080000 */
12905 #define RCC_CR_HSEEXT RCC_CR_HSEEXT_Msk /*!< HSE Clock security System enable */
12906
12907 #define RCC_CR_PLL1ON_Pos (24U)
12908 #define RCC_CR_PLL1ON_Msk (0x1UL << RCC_CR_PLL1ON_Pos) /*!< 0x01000000 */
12909 #define RCC_CR_PLL1ON RCC_CR_PLL1ON_Msk /*!< System PLL1 clock enable */
12910 #define RCC_CR_PLL1RDY_Pos (25U)
12911 #define RCC_CR_PLL1RDY_Msk (0x1UL << RCC_CR_PLL1RDY_Pos) /*!< 0x02000000 */
12912 #define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_Msk /*!< System PLL1 clock ready */
12913 #define RCC_CR_PLL2ON_Pos (26U)
12914 #define RCC_CR_PLL2ON_Msk (0x1UL << RCC_CR_PLL2ON_Pos) /*!< 0x04000000 */
12915 #define RCC_CR_PLL2ON RCC_CR_PLL2ON_Msk /*!< System PLL2 clock enable */
12916 #define RCC_CR_PLL2RDY_Pos (27U)
12917 #define RCC_CR_PLL2RDY_Msk (0x1UL << RCC_CR_PLL2RDY_Pos) /*!< 0x08000000 */
12918 #define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_Msk /*!< System PLL2 clock ready */
12919 #define RCC_CR_PLL3ON_Pos (28U)
12920 #define RCC_CR_PLL3ON_Msk (0x1UL << RCC_CR_PLL3ON_Pos) /*!< 0x10000000 */
12921 #define RCC_CR_PLL3ON RCC_CR_PLL3ON_Msk /*!< System PLL3 clock enable */
12922 #define RCC_CR_PLL3RDY_Pos (29U)
12923 #define RCC_CR_PLL3RDY_Msk (0x1UL << RCC_CR_PLL3RDY_Pos) /*!< 0x20000000 */
12924 #define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_Msk /*!< System PLL3 clock ready */
12925
12926 /*Legacy */
12927 #define RCC_CR_PLLON_Pos (24U)
12928 #define RCC_CR_PLLON_Msk (0x1UL << RCC_CR_PLLON_Pos) /*!< 0x01000000 */
12929 #define RCC_CR_PLLON RCC_CR_PLLON_Msk /*!< System PLL clock enable */
12930 #define RCC_CR_PLLRDY_Pos (25U)
12931 #define RCC_CR_PLLRDY_Msk (0x1UL << RCC_CR_PLLRDY_Pos) /*!< 0x02000000 */
12932 #define RCC_CR_PLLRDY RCC_CR_PLLRDY_Msk /*!< System PLL clock ready */
12933
12934 /******************** Bit definition for RCC_HSICFGR register ***************/
12935 /*!< HSICAL configuration */
12936 #define RCC_HSICFGR_HSICAL_Pos (0U)
12937 #define RCC_HSICFGR_HSICAL_Msk (0xFFFUL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000FFF */
12938 #define RCC_HSICFGR_HSICAL RCC_HSICFGR_HSICAL_Msk /*!< HSICAL[11:0] bits */
12939 #define RCC_HSICFGR_HSICAL_0 (0x001UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000001 */
12940 #define RCC_HSICFGR_HSICAL_1 (0x002UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000002 */
12941 #define RCC_HSICFGR_HSICAL_2 (0x004UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000004 */
12942 #define RCC_HSICFGR_HSICAL_3 (0x008UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000008 */
12943 #define RCC_HSICFGR_HSICAL_4 (0x010UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000010 */
12944 #define RCC_HSICFGR_HSICAL_5 (0x020UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000020 */
12945 #define RCC_HSICFGR_HSICAL_6 (0x040UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000040 */
12946 #define RCC_HSICFGR_HSICAL_7 (0x080UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000080 */
12947 #define RCC_HSICFGR_HSICAL_8 (0x100UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000100 */
12948 #define RCC_HSICFGR_HSICAL_9 (0x200UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000200 */
12949 #define RCC_HSICFGR_HSICAL_10 (0x400UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000400 */
12950 #define RCC_HSICFGR_HSICAL_11 (0x800UL << RCC_HSICFGR_HSICAL_Pos) /*!< 0x00000800 */
12951
12952 /*!< HSITRIM configuration */
12953 #define RCC_HSICFGR_HSITRIM_Pos (24U)
12954 #define RCC_HSICFGR_HSITRIM_Msk (0x7FUL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x7F000000 */
12955 #define RCC_HSICFGR_HSITRIM RCC_HSICFGR_HSITRIM_Msk /*!< HSITRIM[6:0] bits */
12956 #define RCC_HSICFGR_HSITRIM_0 (0x01UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x01000000 */
12957 #define RCC_HSICFGR_HSITRIM_1 (0x02UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x02000000 */
12958 #define RCC_HSICFGR_HSITRIM_2 (0x04UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x04000000 */
12959 #define RCC_HSICFGR_HSITRIM_3 (0x08UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x08000000 */
12960 #define RCC_HSICFGR_HSITRIM_4 (0x10UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x10000000 */
12961 #define RCC_HSICFGR_HSITRIM_5 (0x20UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x20000000 */
12962 #define RCC_HSICFGR_HSITRIM_6 (0x40UL << RCC_HSICFGR_HSITRIM_Pos) /*!< 0x40000000 */
12963
12964
12965 /******************** Bit definition for RCC_CRRCR register *****************/
12966
12967 /*!< HSI48CAL configuration */
12968 #define RCC_CRRCR_HSI48CAL_Pos (0U)
12969 #define RCC_CRRCR_HSI48CAL_Msk (0x3FFUL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x000003FF */
12970 #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_Msk /*!< HSI48CAL[9:0] bits */
12971 #define RCC_CRRCR_HSI48CAL_0 (0x001UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000001 */
12972 #define RCC_CRRCR_HSI48CAL_1 (0x002UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000002 */
12973 #define RCC_CRRCR_HSI48CAL_2 (0x004UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000004 */
12974 #define RCC_CRRCR_HSI48CAL_3 (0x008UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000008 */
12975 #define RCC_CRRCR_HSI48CAL_4 (0x010UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000010 */
12976 #define RCC_CRRCR_HSI48CAL_5 (0x020UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000020 */
12977 #define RCC_CRRCR_HSI48CAL_6 (0x040UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000040 */
12978 #define RCC_CRRCR_HSI48CAL_7 (0x080UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000080 */
12979 #define RCC_CRRCR_HSI48CAL_8 (0x100UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000100 */
12980 #define RCC_CRRCR_HSI48CAL_9 (0x200UL << RCC_CRRCR_HSI48CAL_Pos) /*!< 0x00000200 */
12981
12982
12983 /******************** Bit definition for RCC_CSICFGR register *****************/
12984 /*!< CSICAL configuration */
12985 #define RCC_CSICFGR_CSICAL_Pos (0U)
12986 #define RCC_CSICFGR_CSICAL_Msk (0xFFUL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x000000FF */
12987 #define RCC_CSICFGR_CSICAL RCC_CSICFGR_CSICAL_Msk /*!< CSICAL[7:0] bits */
12988 #define RCC_CSICFGR_CSICAL_0 (0x01UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000001 */
12989 #define RCC_CSICFGR_CSICAL_1 (0x02UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000002 */
12990 #define RCC_CSICFGR_CSICAL_2 (0x04UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000004 */
12991 #define RCC_CSICFGR_CSICAL_3 (0x08UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000008 */
12992 #define RCC_CSICFGR_CSICAL_4 (0x10UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000010 */
12993 #define RCC_CSICFGR_CSICAL_5 (0x20UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000020 */
12994 #define RCC_CSICFGR_CSICAL_6 (0x40UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000040 */
12995 #define RCC_CSICFGR_CSICAL_7 (0x80UL << RCC_CSICFGR_CSICAL_Pos) /*!< 0x00000080 */
12996
12997 /*!< CSITRIM configuration */
12998 #define RCC_CSICFGR_CSITRIM_Pos (24U)
12999 #define RCC_CSICFGR_CSITRIM_Msk (0x3FUL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x3F000000 */
13000 #define RCC_CSICFGR_CSITRIM RCC_CSICFGR_CSITRIM_Msk /*!< CSITRIM[5:0] bits */
13001 #define RCC_CSICFGR_CSITRIM_0 (0x01UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x01000000 */
13002 #define RCC_CSICFGR_CSITRIM_1 (0x02UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x02000000 */
13003 #define RCC_CSICFGR_CSITRIM_2 (0x04UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x04000000 */
13004 #define RCC_CSICFGR_CSITRIM_3 (0x08UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x08000000 */
13005 #define RCC_CSICFGR_CSITRIM_4 (0x10UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x10000000 */
13006 #define RCC_CSICFGR_CSITRIM_5 (0x20UL << RCC_CSICFGR_CSITRIM_Pos) /*!< 0x20000000 */
13007
13008 /******************** Bit definition for RCC_CFGR register ******************/
13009 /*!< SW configuration */
13010 #define RCC_CFGR_SW_Pos (0U)
13011 #define RCC_CFGR_SW_Msk (0x7UL << RCC_CFGR_SW_Pos) /*!< 0x00000007 */
13012 #define RCC_CFGR_SW RCC_CFGR_SW_Msk /*!< SW[2:0] bits (System clock Switch) */
13013 #define RCC_CFGR_SW_0 (0x1UL << RCC_CFGR_SW_Pos) /*!< 0x00000001 */
13014 #define RCC_CFGR_SW_1 (0x2UL << RCC_CFGR_SW_Pos) /*!< 0x00000002 */
13015 #define RCC_CFGR_SW_2 (0x4UL << RCC_CFGR_SW_Pos) /*!< 0x00000004 */
13016
13017 #define RCC_CFGR_SW_HSI (0x00000000UL) /*!< HSI selection as system clock */
13018 #define RCC_CFGR_SW_CSI (0x00000001UL) /*!< CSI selection as system clock */
13019 #define RCC_CFGR_SW_HSE (0x00000002UL) /*!< HSE selection as system clock */
13020 #define RCC_CFGR_SW_PLL1 (0x00000003UL) /*!< PLL1 selection as system clock */
13021
13022 /*!< SWS configuration */
13023 #define RCC_CFGR_SWS_Pos (3U)
13024 #define RCC_CFGR_SWS_Msk (0x7UL << RCC_CFGR_SWS_Pos) /*!< 0x00000038 */
13025 #define RCC_CFGR_SWS RCC_CFGR_SWS_Msk /*!< SWS[2:0] bits (System Clock Switch Status) */
13026 #define RCC_CFGR_SWS_0 (0x1UL << RCC_CFGR_SWS_Pos) /*!< 0x00000008 */
13027 #define RCC_CFGR_SWS_1 (0x2UL << RCC_CFGR_SWS_Pos) /*!< 0x00000010 */
13028 #define RCC_CFGR_SWS_2 (0x4UL << RCC_CFGR_SWS_Pos) /*!< 0x00000020 */
13029
13030 #define RCC_CFGR_SWS_HSI (0x00000000UL) /*!< HSI used as system clock */
13031 #define RCC_CFGR_SWS_CSI (0x00000008UL) /*!< CSI used as system clock */
13032 #define RCC_CFGR_SWS_HSE (0x00000010UL) /*!< HSE used as system clock */
13033 #define RCC_CFGR_SWS_PLL1 (0x00000018UL) /*!< PLL1 used as system clock */
13034
13035 #define RCC_CFGR_STOPWUCK_Pos (6U)
13036 #define RCC_CFGR_STOPWUCK_Msk (0x1UL << RCC_CFGR_STOPWUCK_Pos) /*!< 0x00000040 */
13037 #define RCC_CFGR_STOPWUCK RCC_CFGR_STOPWUCK_Msk /*!< Wake Up from stop and CSS backup clock selection */
13038
13039 #define RCC_CFGR_STOPKERWUCK_Pos (7U)
13040 #define RCC_CFGR_STOPKERWUCK_Msk (0x1UL << RCC_CFGR_STOPKERWUCK_Pos) /*!< 0x00000080 */
13041 #define RCC_CFGR_STOPKERWUCK RCC_CFGR_STOPKERWUCK_Msk /*!< Kernel Clock Selection after a Wake Up from STOP */
13042
13043 /*!< RTCPRE configuration */
13044 #define RCC_CFGR_RTCPRE_Pos (8U)
13045 #define RCC_CFGR_RTCPRE_Msk (0x3FUL << RCC_CFGR_RTCPRE_Pos)
13046 #define RCC_CFGR_RTCPRE RCC_CFGR_RTCPRE_Msk /*!< 0x00003F00 */
13047 #define RCC_CFGR_RTCPRE_0 (0x1UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000100 */
13048 #define RCC_CFGR_RTCPRE_1 (0x2UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000200 */
13049 #define RCC_CFGR_RTCPRE_2 (0x4UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000400 */
13050 #define RCC_CFGR_RTCPRE_3 (0x8UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00000800 */
13051 #define RCC_CFGR_RTCPRE_4 (0x10UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00001000 */
13052 #define RCC_CFGR_RTCPRE_5 (0x20UL << RCC_CFGR_RTCPRE_Pos) /*!< 0x00002000 */
13053
13054
13055 /*!< TIMPRE configuration */
13056 #define RCC_CFGR_TIMPRE_Pos (15U)
13057 #define RCC_CFGR_TIMPRE_Msk (0x1UL << RCC_CFGR_TIMPRE_Pos)
13058 #define RCC_CFGR_TIMPRE RCC_CFGR_TIMPRE_Msk /*!< 0x00008000 */
13059
13060 /*!< MCO1 configuration */
13061 #define RCC_CFGR_MCO1_Pos (22U)
13062 #define RCC_CFGR_MCO1_Msk (0x7UL << RCC_CFGR_MCO1_Pos)
13063 #define RCC_CFGR_MCO1 RCC_CFGR_MCO1_Msk /*!< 0x01C00000 */
13064 #define RCC_CFGR_MCO1_0 (0x1UL << RCC_CFGR_MCO1_Pos) /*!< 0x00400000 */
13065 #define RCC_CFGR_MCO1_1 (0x2UL << RCC_CFGR_MCO1_Pos) /*!< 0x00800000 */
13066 #define RCC_CFGR_MCO1_2 (0x4UL << RCC_CFGR_MCO1_Pos) /*!< 0x01000000 */
13067
13068 #define RCC_CFGR_MCO1PRE_Pos (18U)
13069 #define RCC_CFGR_MCO1PRE_Msk (0xFUL << RCC_CFGR_MCO1PRE_Pos)
13070 #define RCC_CFGR_MCO1PRE RCC_CFGR_MCO1PRE_Msk /*!< 0x003C0000 */
13071 #define RCC_CFGR_MCO1PRE_0 (0x1UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00040000 */
13072 #define RCC_CFGR_MCO1PRE_1 (0x2UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00080000 */
13073 #define RCC_CFGR_MCO1PRE_2 (0x4UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00100000 */
13074 #define RCC_CFGR_MCO1PRE_3 (0x8UL << RCC_CFGR_MCO1PRE_Pos) /*!< 0x00200000 */
13075
13076 #define RCC_CFGR_MCO2PRE_Pos (25U)
13077 #define RCC_CFGR_MCO2PRE_Msk (0xFUL << RCC_CFGR_MCO2PRE_Pos)
13078 #define RCC_CFGR_MCO2PRE RCC_CFGR_MCO2PRE_Msk /*!< 0x1E000000 */
13079 #define RCC_CFGR_MCO2PRE_0 (0x1UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x02000000 */
13080 #define RCC_CFGR_MCO2PRE_1 (0x2UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x04000000 */
13081 #define RCC_CFGR_MCO2PRE_2 (0x4UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x08000000 */
13082 #define RCC_CFGR_MCO2PRE_3 (0x8UL << RCC_CFGR_MCO2PRE_Pos) /*!< 0x10000000 */
13083
13084 #define RCC_CFGR_MCO2_Pos (29U)
13085 #define RCC_CFGR_MCO2_Msk (0x7UL << RCC_CFGR_MCO2_Pos)
13086 #define RCC_CFGR_MCO2 RCC_CFGR_MCO2_Msk /*!< 0xE0000000 */
13087 #define RCC_CFGR_MCO2_0 (0x1UL << RCC_CFGR_MCO2_Pos) /*!< 0x20000000 */
13088 #define RCC_CFGR_MCO2_1 (0x2UL << RCC_CFGR_MCO2_Pos) /*!< 0x40000000 */
13089 #define RCC_CFGR_MCO2_2 (0x4UL << RCC_CFGR_MCO2_Pos) /*!< 0x80000000 */
13090
13091 /******************** Bit definition for RCC_D1CFGR register ******************/
13092 /*!< D1HPRE configuration */
13093 #define RCC_CDCFGR1_HPRE_Pos (0U)
13094 #define RCC_CDCFGR1_HPRE_Msk (0xFUL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x0000000F */
13095 #define RCC_CDCFGR1_HPRE RCC_CDCFGR1_HPRE_Msk /*!< HPRE[3:0] bits (AHB3 prescaler) */
13096 #define RCC_CDCFGR1_HPRE_0 (0x1UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000001 */
13097 #define RCC_CDCFGR1_HPRE_1 (0x2UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000002 */
13098 #define RCC_CDCFGR1_HPRE_2 (0x4UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000004 */
13099 #define RCC_CDCFGR1_HPRE_3 (0x8UL << RCC_CDCFGR1_HPRE_Pos) /*!< 0x00000008 */
13100
13101 #define RCC_CDCFGR1_HPRE_DIV1 ((uint32_t)0x00000000) /*!< AHB3 Clock not divided */
13102 #define RCC_CDCFGR1_HPRE_DIV2_Pos (3U)
13103 #define RCC_CDCFGR1_HPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_HPRE_DIV2_Pos) /*!< 0x00000008 */
13104 #define RCC_CDCFGR1_HPRE_DIV2 RCC_CDCFGR1_HPRE_DIV2_Msk /*!< AHB3 Clock divided by 2 */
13105 #define RCC_CDCFGR1_HPRE_DIV4_Pos (0U)
13106 #define RCC_CDCFGR1_HPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_HPRE_DIV4_Pos) /*!< 0x00000009 */
13107 #define RCC_CDCFGR1_HPRE_DIV4 RCC_CDCFGR1_HPRE_DIV4_Msk /*!< AHB3 Clock divided by 4 */
13108 #define RCC_CDCFGR1_HPRE_DIV8_Pos (1U)
13109 #define RCC_CDCFGR1_HPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_HPRE_DIV8_Pos) /*!< 0x0000000A */
13110 #define RCC_CDCFGR1_HPRE_DIV8 RCC_CDCFGR1_HPRE_DIV8_Msk /*!< AHB3 Clock divided by 8 */
13111 #define RCC_CDCFGR1_HPRE_DIV16_Pos (0U)
13112 #define RCC_CDCFGR1_HPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_HPRE_DIV16_Pos) /*!< 0x0000000B */
13113 #define RCC_CDCFGR1_HPRE_DIV16 RCC_CDCFGR1_HPRE_DIV16_Msk /*!< AHB3 Clock divided by 16 */
13114 #define RCC_CDCFGR1_HPRE_DIV64_Pos (2U)
13115 #define RCC_CDCFGR1_HPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_HPRE_DIV64_Pos) /*!< 0x0000000C */
13116 #define RCC_CDCFGR1_HPRE_DIV64 RCC_CDCFGR1_HPRE_DIV64_Msk /*!< AHB3 Clock divided by 64 */
13117 #define RCC_CDCFGR1_HPRE_DIV128_Pos (0U)
13118 #define RCC_CDCFGR1_HPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_HPRE_DIV128_Pos) /*!< 0x0000000D */
13119 #define RCC_CDCFGR1_HPRE_DIV128 RCC_CDCFGR1_HPRE_DIV128_Msk /*!< AHB3 Clock divided by 128 */
13120 #define RCC_CDCFGR1_HPRE_DIV256_Pos (1U)
13121 #define RCC_CDCFGR1_HPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_HPRE_DIV256_Pos) /*!< 0x0000000E */
13122 #define RCC_CDCFGR1_HPRE_DIV256 RCC_CDCFGR1_HPRE_DIV256_Msk /*!< AHB3 Clock divided by 256 */
13123 #define RCC_CDCFGR1_HPRE_DIV512_Pos (0U)
13124 #define RCC_CDCFGR1_HPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_HPRE_DIV512_Pos) /*!< 0x0000000F */
13125 #define RCC_CDCFGR1_HPRE_DIV512 RCC_CDCFGR1_HPRE_DIV512_Msk /*!< AHB3 Clock divided by 512 */
13126
13127 /*!< D1PPRE configuration */
13128 #define RCC_CDCFGR1_CDPPRE_Pos (4U)
13129 #define RCC_CDCFGR1_CDPPRE_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000070 */
13130 #define RCC_CDCFGR1_CDPPRE RCC_CDCFGR1_CDPPRE_Msk /*!< CDPRE[2:0] bits (APB3 prescaler) */
13131 #define RCC_CDCFGR1_CDPPRE_0 (0x1UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000010 */
13132 #define RCC_CDCFGR1_CDPPRE_1 (0x2UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000020 */
13133 #define RCC_CDCFGR1_CDPPRE_2 (0x4UL << RCC_CDCFGR1_CDPPRE_Pos) /*!< 0x00000040 */
13134
13135 #define RCC_CDCFGR1_CDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB3 clock not divided */
13136 #define RCC_CDCFGR1_CDPPRE_DIV2_Pos (6U)
13137 #define RCC_CDCFGR1_CDPPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDPPRE_DIV2_Pos) /*!< 0x00000040 */
13138 #define RCC_CDCFGR1_CDPPRE_DIV2 RCC_CDCFGR1_CDPPRE_DIV2_Msk /*!< APB3 clock divided by 2 */
13139 #define RCC_CDCFGR1_CDPPRE_DIV4_Pos (4U)
13140 #define RCC_CDCFGR1_CDPPRE_DIV4_Msk (0x5UL << RCC_CDCFGR1_CDPPRE_DIV4_Pos) /*!< 0x00000050 */
13141 #define RCC_CDCFGR1_CDPPRE_DIV4 RCC_CDCFGR1_CDPPRE_DIV4_Msk /*!< APB3 clock divided by 4 */
13142 #define RCC_CDCFGR1_CDPPRE_DIV8_Pos (5U)
13143 #define RCC_CDCFGR1_CDPPRE_DIV8_Msk (0x3UL << RCC_CDCFGR1_CDPPRE_DIV8_Pos) /*!< 0x00000060 */
13144 #define RCC_CDCFGR1_CDPPRE_DIV8 RCC_CDCFGR1_CDPPRE_DIV8_Msk /*!< APB3 clock divided by 8 */
13145 #define RCC_CDCFGR1_CDPPRE_DIV16_Pos (4U)
13146 #define RCC_CDCFGR1_CDPPRE_DIV16_Msk (0x7UL << RCC_CDCFGR1_CDPPRE_DIV16_Pos) /*!< 0x00000070 */
13147 #define RCC_CDCFGR1_CDPPRE_DIV16 RCC_CDCFGR1_CDPPRE_DIV16_Msk /*!< APB3 clock divided by 16 */
13148
13149 #define RCC_CDCFGR1_CDCPRE_Pos (8U)
13150 #define RCC_CDCFGR1_CDCPRE_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000F00 */
13151 #define RCC_CDCFGR1_CDCPRE RCC_CDCFGR1_CDCPRE_Msk /*!< CDCPRE[2:0] bits (Domain 1 Core prescaler) */
13152 #define RCC_CDCFGR1_CDCPRE_0 (0x1UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000100 */
13153 #define RCC_CDCFGR1_CDCPRE_1 (0x2UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000200 */
13154 #define RCC_CDCFGR1_CDCPRE_2 (0x4UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000400 */
13155 #define RCC_CDCFGR1_CDCPRE_3 (0x8UL << RCC_CDCFGR1_CDCPRE_Pos) /*!< 0x00000800 */
13156
13157 #define RCC_CDCFGR1_CDCPRE_DIV1 ((uint32_t)0x00000000) /*!< Domain 1 Core clock not divided */
13158 #define RCC_CDCFGR1_CDCPRE_DIV2_Pos (11U)
13159 #define RCC_CDCFGR1_CDCPRE_DIV2_Msk (0x1UL << RCC_CDCFGR1_CDCPRE_DIV2_Pos) /*!< 0x00000800 */
13160 #define RCC_CDCFGR1_CDCPRE_DIV2 RCC_CDCFGR1_CDCPRE_DIV2_Msk /*!< Domain 1 Core clock divided by 2 */
13161 #define RCC_CDCFGR1_CDCPRE_DIV4_Pos (8U)
13162 #define RCC_CDCFGR1_CDCPRE_DIV4_Msk (0x9UL << RCC_CDCFGR1_CDCPRE_DIV4_Pos) /*!< 0x00000900 */
13163 #define RCC_CDCFGR1_CDCPRE_DIV4 RCC_CDCFGR1_CDCPRE_DIV4_Msk /*!< Domain 1 Core clock divided by 4 */
13164 #define RCC_CDCFGR1_CDCPRE_DIV8_Pos (9U)
13165 #define RCC_CDCFGR1_CDCPRE_DIV8_Msk (0x5UL << RCC_CDCFGR1_CDCPRE_DIV8_Pos) /*!< 0x00000A00 */
13166 #define RCC_CDCFGR1_CDCPRE_DIV8 RCC_CDCFGR1_CDCPRE_DIV8_Msk /*!< Domain 1 Core clock divided by 8 */
13167 #define RCC_CDCFGR1_CDCPRE_DIV16_Pos (8U)
13168 #define RCC_CDCFGR1_CDCPRE_DIV16_Msk (0xBUL << RCC_CDCFGR1_CDCPRE_DIV16_Pos) /*!< 0x00000B00 */
13169 #define RCC_CDCFGR1_CDCPRE_DIV16 RCC_CDCFGR1_CDCPRE_DIV16_Msk /*!< Domain 1 Core clock divided by 16 */
13170 #define RCC_CDCFGR1_CDCPRE_DIV64_Pos (10U)
13171 #define RCC_CDCFGR1_CDCPRE_DIV64_Msk (0x3UL << RCC_CDCFGR1_CDCPRE_DIV64_Pos) /*!< 0x00000C00 */
13172 #define RCC_CDCFGR1_CDCPRE_DIV64 RCC_CDCFGR1_CDCPRE_DIV64_Msk /*!< Domain 1 Core clock divided by 64 */
13173 #define RCC_CDCFGR1_CDCPRE_DIV128_Pos (8U)
13174 #define RCC_CDCFGR1_CDCPRE_DIV128_Msk (0xDUL << RCC_CDCFGR1_CDCPRE_DIV128_Pos)/*!< 0x00000D00 */
13175 #define RCC_CDCFGR1_CDCPRE_DIV128 RCC_CDCFGR1_CDCPRE_DIV128_Msk /*!< Domain 1 Core clock divided by 128 */
13176 #define RCC_CDCFGR1_CDCPRE_DIV256_Pos (9U)
13177 #define RCC_CDCFGR1_CDCPRE_DIV256_Msk (0x7UL << RCC_CDCFGR1_CDCPRE_DIV256_Pos)/*!< 0x00000E00 */
13178 #define RCC_CDCFGR1_CDCPRE_DIV256 RCC_CDCFGR1_CDCPRE_DIV256_Msk /*!< Domain 1 Core clock divided by 256 */
13179 #define RCC_CDCFGR1_CDCPRE_DIV512_Pos (8U)
13180 #define RCC_CDCFGR1_CDCPRE_DIV512_Msk (0xFUL << RCC_CDCFGR1_CDCPRE_DIV512_Pos)/*!< 0x00000F00 */
13181 #define RCC_CDCFGR1_CDCPRE_DIV512 RCC_CDCFGR1_CDCPRE_DIV512_Msk /*!< Domain 1 Core clock divided by 512 */
13182
13183 /******************** Bit definition for RCC_CDCFGR2 register ******************/
13184 /*!< CDPPRE1 configuration */
13185 #define RCC_CDCFGR2_CDPPRE1_Pos (4U)
13186 #define RCC_CDCFGR2_CDPPRE1_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000070 */
13187 #define RCC_CDCFGR2_CDPPRE1 RCC_CDCFGR2_CDPPRE1_Msk /*!< D1PPRE1[2:0] bits (APB1 prescaler) */
13188 #define RCC_CDCFGR2_CDPPRE1_0 (0x1UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000010 */
13189 #define RCC_CDCFGR2_CDPPRE1_1 (0x2UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000020 */
13190 #define RCC_CDCFGR2_CDPPRE1_2 (0x4UL << RCC_CDCFGR2_CDPPRE1_Pos) /*!< 0x00000040 */
13191
13192 #define RCC_CDCFGR2_CDPPRE1_DIV1 ((uint32_t)0x00000000) /*!< APB1 clock not divided */
13193 #define RCC_CDCFGR2_CDPPRE1_DIV2_Pos (6U)
13194 #define RCC_CDCFGR2_CDPPRE1_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE1_DIV2_Pos) /*!< 0x00000040 */
13195 #define RCC_CDCFGR2_CDPPRE1_DIV2 RCC_CDCFGR2_CDPPRE1_DIV2_Msk /*!< APB1 clock divided by 2 */
13196 #define RCC_CDCFGR2_CDPPRE1_DIV4_Pos (4U)
13197 #define RCC_CDCFGR2_CDPPRE1_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE1_DIV4_Pos) /*!< 0x00000050 */
13198 #define RCC_CDCFGR2_CDPPRE1_DIV4 RCC_CDCFGR2_CDPPRE1_DIV4_Msk /*!< APB1 clock divided by 4 */
13199 #define RCC_CDCFGR2_CDPPRE1_DIV8_Pos (5U)
13200 #define RCC_CDCFGR2_CDPPRE1_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE1_DIV8_Pos) /*!< 0x00000060 */
13201 #define RCC_CDCFGR2_CDPPRE1_DIV8 RCC_CDCFGR2_CDPPRE1_DIV8_Msk /*!< APB1 clock divided by 8 */
13202 #define RCC_CDCFGR2_CDPPRE1_DIV16_Pos (4U)
13203 #define RCC_CDCFGR2_CDPPRE1_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE1_DIV16_Pos) /*!< 0x00000070 */
13204 #define RCC_CDCFGR2_CDPPRE1_DIV16 RCC_CDCFGR2_CDPPRE1_DIV16_Msk /*!< APB1 clock divided by 16 */
13205
13206 /*!< CDPPRE2 configuration */
13207 #define RCC_CDCFGR2_CDPPRE2_Pos (8U)
13208 #define RCC_CDCFGR2_CDPPRE2_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000700 */
13209 #define RCC_CDCFGR2_CDPPRE2 RCC_CDCFGR2_CDPPRE2_Msk /*!< CDPPRE2[2:0] bits (APB2 prescaler) */
13210 #define RCC_CDCFGR2_CDPPRE2_0 (0x1UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000100 */
13211 #define RCC_CDCFGR2_CDPPRE2_1 (0x2UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000200 */
13212 #define RCC_CDCFGR2_CDPPRE2_2 (0x4UL << RCC_CDCFGR2_CDPPRE2_Pos) /*!< 0x00000400 */
13213
13214 #define RCC_CDCFGR2_CDPPRE2_DIV1 ((uint32_t)0x00000000) /*!< APB2 clock not divided */
13215 #define RCC_CDCFGR2_CDPPRE2_DIV2_Pos (10U)
13216 #define RCC_CDCFGR2_CDPPRE2_DIV2_Msk (0x1UL << RCC_CDCFGR2_CDPPRE2_DIV2_Pos) /*!< 0x00000400 */
13217 #define RCC_CDCFGR2_CDPPRE2_DIV2 RCC_CDCFGR2_CDPPRE2_DIV2_Msk /*!< APB2 clock divided by 2 */
13218 #define RCC_CDCFGR2_CDPPRE2_DIV4_Pos (8U)
13219 #define RCC_CDCFGR2_CDPPRE2_DIV4_Msk (0x5UL << RCC_CDCFGR2_CDPPRE2_DIV4_Pos) /*!< 0x00000500 */
13220 #define RCC_CDCFGR2_CDPPRE2_DIV4 RCC_CDCFGR2_CDPPRE2_DIV4_Msk /*!< APB2 clock divided by 4 */
13221 #define RCC_CDCFGR2_CDPPRE2_DIV8_Pos (9U)
13222 #define RCC_CDCFGR2_CDPPRE2_DIV8_Msk (0x3UL << RCC_CDCFGR2_CDPPRE2_DIV8_Pos) /*!< 0x00000600 */
13223 #define RCC_CDCFGR2_CDPPRE2_DIV8 RCC_CDCFGR2_CDPPRE2_DIV8_Msk /*!< APB2 clock divided by 8 */
13224 #define RCC_CDCFGR2_CDPPRE2_DIV16_Pos (8U)
13225 #define RCC_CDCFGR2_CDPPRE2_DIV16_Msk (0x7UL << RCC_CDCFGR2_CDPPRE2_DIV16_Pos) /*!< 0x00000700 */
13226 #define RCC_CDCFGR2_CDPPRE2_DIV16 RCC_CDCFGR2_CDPPRE2_DIV16_Msk /*!< APB2 clock divided by 16 */
13227
13228 /******************** Bit definition for RCC_SRDCFGR register ******************/
13229 /*!< SRDPPRE configuration */
13230 #define RCC_SRDCFGR_SRDPPRE_Pos (4U)
13231 #define RCC_SRDCFGR_SRDPPRE_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000070 */
13232 #define RCC_SRDCFGR_SRDPPRE RCC_SRDCFGR_SRDPPRE_Msk /*!< SRDPPRE1[2:0] bits (APB4 prescaler) */
13233 #define RCC_SRDCFGR_SRDPPRE_0 (0x1UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000010 */
13234 #define RCC_SRDCFGR_SRDPPRE_1 (0x2UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000020 */
13235 #define RCC_SRDCFGR_SRDPPRE_2 (0x4UL << RCC_SRDCFGR_SRDPPRE_Pos) /*!< 0x00000040 */
13236
13237 #define RCC_SRDCFGR_SRDPPRE_DIV1 ((uint32_t)0x00000000) /*!< APB4 clock not divided */
13238 #define RCC_SRDCFGR_SRDPPRE_DIV2_Pos (6U)
13239 #define RCC_SRDCFGR_SRDPPRE_DIV2_Msk (0x1UL << RCC_SRDCFGR_SRDPPRE_DIV2_Pos) /*!< 0x00000040 */
13240 #define RCC_SRDCFGR_SRDPPRE_DIV2 RCC_SRDCFGR_SRDPPRE_DIV2_Msk /*!< APB4 clock divided by 2 */
13241 #define RCC_SRDCFGR_SRDPPRE_DIV4_Pos (4U)
13242 #define RCC_SRDCFGR_SRDPPRE_DIV4_Msk (0x5UL << RCC_SRDCFGR_SRDPPRE_DIV4_Pos) /*!< 0x00000050 */
13243 #define RCC_SRDCFGR_SRDPPRE_DIV4 RCC_SRDCFGR_SRDPPRE_DIV4_Msk /*!< APB4 clock divided by 4 */
13244 #define RCC_SRDCFGR_SRDPPRE_DIV8_Pos (5U)
13245 #define RCC_SRDCFGR_SRDPPRE_DIV8_Msk (0x3UL << RCC_SRDCFGR_SRDPPRE_DIV8_Pos) /*!< 0x00000060 */
13246 #define RCC_SRDCFGR_SRDPPRE_DIV8 RCC_SRDCFGR_SRDPPRE_DIV8_Msk /*!< APB4 clock divided by 8 */
13247 #define RCC_SRDCFGR_SRDPPRE_DIV16_Pos (4U)
13248 #define RCC_SRDCFGR_SRDPPRE_DIV16_Msk (0x7UL << RCC_SRDCFGR_SRDPPRE_DIV16_Pos) /*!< 0x00000070 */
13249 #define RCC_SRDCFGR_SRDPPRE_DIV16 RCC_SRDCFGR_SRDPPRE_DIV16_Msk /*!< APB4 clock divided by 16 */
13250
13251 /******************** Bit definition for RCC_PLLCKSELR register *************/
13252
13253 #define RCC_PLLCKSELR_PLLSRC_Pos (0U)
13254 #define RCC_PLLCKSELR_PLLSRC_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_Pos) /*!< 0x00000003 */
13255 #define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_Msk
13256
13257 #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /*!< HSI source clock selected */
13258 #define RCC_PLLCKSELR_PLLSRC_CSI_Pos (0U)
13259 #define RCC_PLLCKSELR_PLLSRC_CSI_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_CSI_Pos) /*!< 0x00000001 */
13260 #define RCC_PLLCKSELR_PLLSRC_CSI RCC_PLLCKSELR_PLLSRC_CSI_Msk /*!< CSI source clock selected */
13261 #define RCC_PLLCKSELR_PLLSRC_HSE_Pos (1U)
13262 #define RCC_PLLCKSELR_PLLSRC_HSE_Msk (0x1UL << RCC_PLLCKSELR_PLLSRC_HSE_Pos) /*!< 0x00000002 */
13263 #define RCC_PLLCKSELR_PLLSRC_HSE RCC_PLLCKSELR_PLLSRC_HSE_Msk /*!< HSE source clock selected */
13264 #define RCC_PLLCKSELR_PLLSRC_NONE_Pos (0U)
13265 #define RCC_PLLCKSELR_PLLSRC_NONE_Msk (0x3UL << RCC_PLLCKSELR_PLLSRC_NONE_Pos) /*!< 0x00000003 */
13266 #define RCC_PLLCKSELR_PLLSRC_NONE RCC_PLLCKSELR_PLLSRC_NONE_Msk /*!< No source clock selected */
13267
13268 #define RCC_PLLCKSELR_DIVM1_Pos (4U)
13269 #define RCC_PLLCKSELR_DIVM1_Msk (0x3FUL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x000003F0 */
13270 #define RCC_PLLCKSELR_DIVM1 RCC_PLLCKSELR_DIVM1_Msk
13271 #define RCC_PLLCKSELR_DIVM1_0 (0x01UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000010 */
13272 #define RCC_PLLCKSELR_DIVM1_1 (0x02UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000020 */
13273 #define RCC_PLLCKSELR_DIVM1_2 (0x04UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000040 */
13274 #define RCC_PLLCKSELR_DIVM1_3 (0x08UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000080 */
13275 #define RCC_PLLCKSELR_DIVM1_4 (0x10UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000100 */
13276 #define RCC_PLLCKSELR_DIVM1_5 (0x20UL << RCC_PLLCKSELR_DIVM1_Pos) /*!< 0x00000200 */
13277
13278 #define RCC_PLLCKSELR_DIVM2_Pos (12U)
13279 #define RCC_PLLCKSELR_DIVM2_Msk (0x3FUL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x0003F000 */
13280 #define RCC_PLLCKSELR_DIVM2 RCC_PLLCKSELR_DIVM2_Msk
13281 #define RCC_PLLCKSELR_DIVM2_0 (0x01UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00001000 */
13282 #define RCC_PLLCKSELR_DIVM2_1 (0x02UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00002000 */
13283 #define RCC_PLLCKSELR_DIVM2_2 (0x04UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00004000 */
13284 #define RCC_PLLCKSELR_DIVM2_3 (0x08UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00008000 */
13285 #define RCC_PLLCKSELR_DIVM2_4 (0x10UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00010000 */
13286 #define RCC_PLLCKSELR_DIVM2_5 (0x20UL << RCC_PLLCKSELR_DIVM2_Pos) /*!< 0x00020000 */
13287
13288 #define RCC_PLLCKSELR_DIVM3_Pos (20U)
13289 #define RCC_PLLCKSELR_DIVM3_Msk (0x3FUL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x03F00000 */
13290 #define RCC_PLLCKSELR_DIVM3 RCC_PLLCKSELR_DIVM3_Msk
13291 #define RCC_PLLCKSELR_DIVM3_0 (0x01UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00100000 */
13292 #define RCC_PLLCKSELR_DIVM3_1 (0x02UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00200000 */
13293 #define RCC_PLLCKSELR_DIVM3_2 (0x04UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00400000 */
13294 #define RCC_PLLCKSELR_DIVM3_3 (0x08UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x00800000 */
13295 #define RCC_PLLCKSELR_DIVM3_4 (0x10UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x01000000 */
13296 #define RCC_PLLCKSELR_DIVM3_5 (0x20UL << RCC_PLLCKSELR_DIVM3_Pos) /*!< 0x02000000 */
13297
13298 /******************** Bit definition for RCC_PLLCFGR register ***************/
13299
13300 #define RCC_PLLCFGR_PLL1FRACEN_Pos (0U)
13301 #define RCC_PLLCFGR_PLL1FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL1FRACEN_Pos) /*!< 0x00000001 */
13302 #define RCC_PLLCFGR_PLL1FRACEN RCC_PLLCFGR_PLL1FRACEN_Msk
13303 #define RCC_PLLCFGR_PLL1VCOSEL_Pos (1U)
13304 #define RCC_PLLCFGR_PLL1VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL1VCOSEL_Pos) /*!< 0x00000002 */
13305 #define RCC_PLLCFGR_PLL1VCOSEL RCC_PLLCFGR_PLL1VCOSEL_Msk
13306 #define RCC_PLLCFGR_PLL1RGE_Pos (2U)
13307 #define RCC_PLLCFGR_PLL1RGE_Msk (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13308 #define RCC_PLLCFGR_PLL1RGE RCC_PLLCFGR_PLL1RGE_Msk
13309 #define RCC_PLLCFGR_PLL1RGE_0 (0x0UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000000 */
13310 #define RCC_PLLCFGR_PLL1RGE_1 (0x1UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000004 */
13311 #define RCC_PLLCFGR_PLL1RGE_2 (0x2UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x00000008 */
13312 #define RCC_PLLCFGR_PLL1RGE_3 (0x3UL << RCC_PLLCFGR_PLL1RGE_Pos) /*!< 0x0000000C */
13313
13314 #define RCC_PLLCFGR_PLL2FRACEN_Pos (4U)
13315 #define RCC_PLLCFGR_PLL2FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL2FRACEN_Pos) /*!< 0x00000010 */
13316 #define RCC_PLLCFGR_PLL2FRACEN RCC_PLLCFGR_PLL2FRACEN_Msk
13317 #define RCC_PLLCFGR_PLL2VCOSEL_Pos (5U)
13318 #define RCC_PLLCFGR_PLL2VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL2VCOSEL_Pos) /*!< 0x00000020 */
13319 #define RCC_PLLCFGR_PLL2VCOSEL RCC_PLLCFGR_PLL2VCOSEL_Msk
13320 #define RCC_PLLCFGR_PLL2RGE_Pos (6U)
13321 #define RCC_PLLCFGR_PLL2RGE_Msk (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
13322 #define RCC_PLLCFGR_PLL2RGE RCC_PLLCFGR_PLL2RGE_Msk
13323 #define RCC_PLLCFGR_PLL2RGE_0 (0x0UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000000 */
13324 #define RCC_PLLCFGR_PLL2RGE_1 (0x1UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000040 */
13325 #define RCC_PLLCFGR_PLL2RGE_2 (0x2UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x00000080 */
13326 #define RCC_PLLCFGR_PLL2RGE_3 (0x3UL << RCC_PLLCFGR_PLL2RGE_Pos) /*!< 0x000000C0 */
13327
13328 #define RCC_PLLCFGR_PLL3FRACEN_Pos (8U)
13329 #define RCC_PLLCFGR_PLL3FRACEN_Msk (0x1UL << RCC_PLLCFGR_PLL3FRACEN_Pos) /*!< 0x00000100 */
13330 #define RCC_PLLCFGR_PLL3FRACEN RCC_PLLCFGR_PLL3FRACEN_Msk
13331 #define RCC_PLLCFGR_PLL3VCOSEL_Pos (9U)
13332 #define RCC_PLLCFGR_PLL3VCOSEL_Msk (0x1UL << RCC_PLLCFGR_PLL3VCOSEL_Pos) /*!< 0x00000200 */
13333 #define RCC_PLLCFGR_PLL3VCOSEL RCC_PLLCFGR_PLL3VCOSEL_Msk
13334 #define RCC_PLLCFGR_PLL3RGE_Pos (10U)
13335 #define RCC_PLLCFGR_PLL3RGE_Msk (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
13336 #define RCC_PLLCFGR_PLL3RGE RCC_PLLCFGR_PLL3RGE_Msk
13337 #define RCC_PLLCFGR_PLL3RGE_0 (0x0UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000000 */
13338 #define RCC_PLLCFGR_PLL3RGE_1 (0x1UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000400 */
13339 #define RCC_PLLCFGR_PLL3RGE_2 (0x2UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000800 */
13340 #define RCC_PLLCFGR_PLL3RGE_3 (0x3UL << RCC_PLLCFGR_PLL3RGE_Pos) /*!< 0x00000C00 */
13341
13342 #define RCC_PLLCFGR_DIVP1EN_Pos (16U)
13343 #define RCC_PLLCFGR_DIVP1EN_Msk (0x1UL << RCC_PLLCFGR_DIVP1EN_Pos) /*!< 0x00010000 */
13344 #define RCC_PLLCFGR_DIVP1EN RCC_PLLCFGR_DIVP1EN_Msk
13345 #define RCC_PLLCFGR_DIVQ1EN_Pos (17U)
13346 #define RCC_PLLCFGR_DIVQ1EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ1EN_Pos) /*!< 0x00020000 */
13347 #define RCC_PLLCFGR_DIVQ1EN RCC_PLLCFGR_DIVQ1EN_Msk
13348 #define RCC_PLLCFGR_DIVR1EN_Pos (18U)
13349 #define RCC_PLLCFGR_DIVR1EN_Msk (0x1UL << RCC_PLLCFGR_DIVR1EN_Pos) /*!< 0x00040000 */
13350 #define RCC_PLLCFGR_DIVR1EN RCC_PLLCFGR_DIVR1EN_Msk
13351
13352 #define RCC_PLLCFGR_DIVP2EN_Pos (19U)
13353 #define RCC_PLLCFGR_DIVP2EN_Msk (0x1UL << RCC_PLLCFGR_DIVP2EN_Pos) /*!< 0x00080000 */
13354 #define RCC_PLLCFGR_DIVP2EN RCC_PLLCFGR_DIVP2EN_Msk
13355 #define RCC_PLLCFGR_DIVQ2EN_Pos (20U)
13356 #define RCC_PLLCFGR_DIVQ2EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ2EN_Pos) /*!< 0x00100000 */
13357 #define RCC_PLLCFGR_DIVQ2EN RCC_PLLCFGR_DIVQ2EN_Msk
13358 #define RCC_PLLCFGR_DIVR2EN_Pos (21U)
13359 #define RCC_PLLCFGR_DIVR2EN_Msk (0x1UL << RCC_PLLCFGR_DIVR2EN_Pos) /*!< 0x00200000 */
13360 #define RCC_PLLCFGR_DIVR2EN RCC_PLLCFGR_DIVR2EN_Msk
13361
13362 #define RCC_PLLCFGR_DIVP3EN_Pos (22U)
13363 #define RCC_PLLCFGR_DIVP3EN_Msk (0x1UL << RCC_PLLCFGR_DIVP3EN_Pos) /*!< 0x00400000 */
13364 #define RCC_PLLCFGR_DIVP3EN RCC_PLLCFGR_DIVP3EN_Msk
13365 #define RCC_PLLCFGR_DIVQ3EN_Pos (23U)
13366 #define RCC_PLLCFGR_DIVQ3EN_Msk (0x1UL << RCC_PLLCFGR_DIVQ3EN_Pos) /*!< 0x00800000 */
13367 #define RCC_PLLCFGR_DIVQ3EN RCC_PLLCFGR_DIVQ3EN_Msk
13368 #define RCC_PLLCFGR_DIVR3EN_Pos (24U)
13369 #define RCC_PLLCFGR_DIVR3EN_Msk (0x1UL << RCC_PLLCFGR_DIVR3EN_Pos) /*!< 0x01000000 */
13370 #define RCC_PLLCFGR_DIVR3EN RCC_PLLCFGR_DIVR3EN_Msk
13371
13372
13373 /******************** Bit definition for RCC_PLL1DIVR register ***************/
13374 #define RCC_PLL1DIVR_N1_Pos (0U)
13375 #define RCC_PLL1DIVR_N1_Msk (0x1FFUL << RCC_PLL1DIVR_N1_Pos) /*!< 0x000001FF */
13376 #define RCC_PLL1DIVR_N1 RCC_PLL1DIVR_N1_Msk
13377 #define RCC_PLL1DIVR_P1_Pos (9U)
13378 #define RCC_PLL1DIVR_P1_Msk (0x7FUL << RCC_PLL1DIVR_P1_Pos) /*!< 0x0000FE00 */
13379 #define RCC_PLL1DIVR_P1 RCC_PLL1DIVR_P1_Msk
13380 #define RCC_PLL1DIVR_Q1_Pos (16U)
13381 #define RCC_PLL1DIVR_Q1_Msk (0x7FUL << RCC_PLL1DIVR_Q1_Pos) /*!< 0x007F0000 */
13382 #define RCC_PLL1DIVR_Q1 RCC_PLL1DIVR_Q1_Msk
13383 #define RCC_PLL1DIVR_R1_Pos (24U)
13384 #define RCC_PLL1DIVR_R1_Msk (0x7FUL << RCC_PLL1DIVR_R1_Pos) /*!< 0x7F000000 */
13385 #define RCC_PLL1DIVR_R1 RCC_PLL1DIVR_R1_Msk
13386
13387 /******************** Bit definition for RCC_PLL1FRACR register ***************/
13388 #define RCC_PLL1FRACR_FRACN1_Pos (3U)
13389 #define RCC_PLL1FRACR_FRACN1_Msk (0x1FFFUL << RCC_PLL1FRACR_FRACN1_Pos) /*!< 0x0000FFF8 */
13390 #define RCC_PLL1FRACR_FRACN1 RCC_PLL1FRACR_FRACN1_Msk
13391
13392 /******************** Bit definition for RCC_PLL2DIVR register ***************/
13393 #define RCC_PLL2DIVR_N2_Pos (0U)
13394 #define RCC_PLL2DIVR_N2_Msk (0x1FFUL << RCC_PLL2DIVR_N2_Pos) /*!< 0x000001FF */
13395 #define RCC_PLL2DIVR_N2 RCC_PLL2DIVR_N2_Msk
13396 #define RCC_PLL2DIVR_P2_Pos (9U)
13397 #define RCC_PLL2DIVR_P2_Msk (0x7FUL << RCC_PLL2DIVR_P2_Pos) /*!< 0x0000FE00 */
13398 #define RCC_PLL2DIVR_P2 RCC_PLL2DIVR_P2_Msk
13399 #define RCC_PLL2DIVR_Q2_Pos (16U)
13400 #define RCC_PLL2DIVR_Q2_Msk (0x7FUL << RCC_PLL2DIVR_Q2_Pos) /*!< 0x007F0000 */
13401 #define RCC_PLL2DIVR_Q2 RCC_PLL2DIVR_Q2_Msk
13402 #define RCC_PLL2DIVR_R2_Pos (24U)
13403 #define RCC_PLL2DIVR_R2_Msk (0x7FUL << RCC_PLL2DIVR_R2_Pos) /*!< 0x7F000000 */
13404 #define RCC_PLL2DIVR_R2 RCC_PLL2DIVR_R2_Msk
13405
13406 /******************** Bit definition for RCC_PLL2FRACR register ***************/
13407 #define RCC_PLL2FRACR_FRACN2_Pos (3U)
13408 #define RCC_PLL2FRACR_FRACN2_Msk (0x1FFFUL << RCC_PLL2FRACR_FRACN2_Pos) /*!< 0x0000FFF8 */
13409 #define RCC_PLL2FRACR_FRACN2 RCC_PLL2FRACR_FRACN2_Msk
13410
13411 /******************** Bit definition for RCC_PLL3DIVR register ***************/
13412 #define RCC_PLL3DIVR_N3_Pos (0U)
13413 #define RCC_PLL3DIVR_N3_Msk (0x1FFUL << RCC_PLL3DIVR_N3_Pos) /*!< 0x000001FF */
13414 #define RCC_PLL3DIVR_N3 RCC_PLL3DIVR_N3_Msk
13415 #define RCC_PLL3DIVR_P3_Pos (9U)
13416 #define RCC_PLL3DIVR_P3_Msk (0x7FUL << RCC_PLL3DIVR_P3_Pos) /*!< 0x0000FE00 */
13417 #define RCC_PLL3DIVR_P3 RCC_PLL3DIVR_P3_Msk
13418 #define RCC_PLL3DIVR_Q3_Pos (16U)
13419 #define RCC_PLL3DIVR_Q3_Msk (0x7FUL << RCC_PLL3DIVR_Q3_Pos) /*!< 0x007F0000 */
13420 #define RCC_PLL3DIVR_Q3 RCC_PLL3DIVR_Q3_Msk
13421 #define RCC_PLL3DIVR_R3_Pos (24U)
13422 #define RCC_PLL3DIVR_R3_Msk (0x7FUL << RCC_PLL3DIVR_R3_Pos) /*!< 0x7F000000 */
13423 #define RCC_PLL3DIVR_R3 RCC_PLL3DIVR_R3_Msk
13424
13425 /******************** Bit definition for RCC_PLL3FRACR register ***************/
13426 #define RCC_PLL3FRACR_FRACN3_Pos (3U)
13427 #define RCC_PLL3FRACR_FRACN3_Msk (0x1FFFUL << RCC_PLL3FRACR_FRACN3_Pos) /*!< 0x0000FFF8 */
13428 #define RCC_PLL3FRACR_FRACN3 RCC_PLL3FRACR_FRACN3_Msk
13429
13430 /******************** Bit definition for RCC_CDCCIPR register ***************/
13431 #define RCC_CDCCIPR_FMCSEL_Pos (0U)
13432 #define RCC_CDCCIPR_FMCSEL_Msk (0x3UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000003 */
13433 #define RCC_CDCCIPR_FMCSEL RCC_CDCCIPR_FMCSEL_Msk
13434 #define RCC_CDCCIPR_FMCSEL_0 (0x1UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000001 */
13435 #define RCC_CDCCIPR_FMCSEL_1 (0x2UL << RCC_CDCCIPR_FMCSEL_Pos) /*!< 0x00000002 */
13436 #define RCC_CDCCIPR_OCTOSPISEL_Pos (4U)
13437 #define RCC_CDCCIPR_OCTOSPISEL_Msk (0x3UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000030 */
13438 #define RCC_CDCCIPR_OCTOSPISEL RCC_CDCCIPR_OCTOSPISEL_Msk
13439 #define RCC_CDCCIPR_OCTOSPISEL_0 (0x1UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000010 */
13440 #define RCC_CDCCIPR_OCTOSPISEL_1 (0x2UL << RCC_CDCCIPR_OCTOSPISEL_Pos) /*!< 0x00000020 */
13441 #define RCC_CDCCIPR_SDMMCSEL_Pos (16U)
13442 #define RCC_CDCCIPR_SDMMCSEL_Msk (0x1UL << RCC_CDCCIPR_SDMMCSEL_Pos) /*!< 0x00010000 */
13443 #define RCC_CDCCIPR_SDMMCSEL RCC_CDCCIPR_SDMMCSEL_Msk
13444 #define RCC_CDCCIPR_CKPERSEL_Pos (28U)
13445 #define RCC_CDCCIPR_CKPERSEL_Msk (0x3UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x30000000 */
13446 #define RCC_CDCCIPR_CKPERSEL RCC_CDCCIPR_CKPERSEL_Msk
13447 #define RCC_CDCCIPR_CKPERSEL_0 (0x1UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x10000000 */
13448 #define RCC_CDCCIPR_CKPERSEL_1 (0x2UL << RCC_CDCCIPR_CKPERSEL_Pos) /*!< 0x20000000 */
13449
13450 /******************** Bit definition for RCC_CDCCIP1R register ***************/
13451 #define RCC_CDCCIP1R_SAI1SEL_Pos (0U)
13452 #define RCC_CDCCIP1R_SAI1SEL_Msk (0x7UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000007 */
13453 #define RCC_CDCCIP1R_SAI1SEL RCC_CDCCIP1R_SAI1SEL_Msk
13454 #define RCC_CDCCIP1R_SAI1SEL_0 (0x1UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000001 */
13455 #define RCC_CDCCIP1R_SAI1SEL_1 (0x2UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000002 */
13456 #define RCC_CDCCIP1R_SAI1SEL_2 (0x4UL << RCC_CDCCIP1R_SAI1SEL_Pos) /*!< 0x00000004 */
13457
13458 #define RCC_CDCCIP1R_SAI2ASEL_Pos (6U)
13459 #define RCC_CDCCIP1R_SAI2ASEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x000001C0 */
13460 #define RCC_CDCCIP1R_SAI2ASEL RCC_CDCCIP1R_SAI2ASEL_Msk
13461 #define RCC_CDCCIP1R_SAI2ASEL_0 (0x1UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000040 */
13462 #define RCC_CDCCIP1R_SAI2ASEL_1 (0x2UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000080 */
13463 #define RCC_CDCCIP1R_SAI2ASEL_2 (0x4UL << RCC_CDCCIP1R_SAI2ASEL_Pos) /*!< 0x00000100 */
13464
13465 #define RCC_CDCCIP1R_SAI2BSEL_Pos (9U)
13466 #define RCC_CDCCIP1R_SAI2BSEL_Msk (0x7UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000E00 */
13467 #define RCC_CDCCIP1R_SAI2BSEL RCC_CDCCIP1R_SAI2BSEL_Msk
13468 #define RCC_CDCCIP1R_SAI2BSEL_0 (0x1UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000200 */
13469 #define RCC_CDCCIP1R_SAI2BSEL_1 (0x2UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000400 */
13470 #define RCC_CDCCIP1R_SAI2BSEL_2 (0x4UL << RCC_CDCCIP1R_SAI2BSEL_Pos) /*!< 0x00000800 */
13471
13472 #define RCC_CDCCIP1R_SPI123SEL_Pos (12U)
13473 #define RCC_CDCCIP1R_SPI123SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00007000 */
13474 #define RCC_CDCCIP1R_SPI123SEL RCC_CDCCIP1R_SPI123SEL_Msk
13475 #define RCC_CDCCIP1R_SPI123SEL_0 (0x1UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00001000 */
13476 #define RCC_CDCCIP1R_SPI123SEL_1 (0x2UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00002000 */
13477 #define RCC_CDCCIP1R_SPI123SEL_2 (0x4UL << RCC_CDCCIP1R_SPI123SEL_Pos) /*!< 0x00004000 */
13478
13479 #define RCC_CDCCIP1R_SPI45SEL_Pos (16U)
13480 #define RCC_CDCCIP1R_SPI45SEL_Msk (0x7UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00070000 */
13481 #define RCC_CDCCIP1R_SPI45SEL RCC_CDCCIP1R_SPI45SEL_Msk
13482 #define RCC_CDCCIP1R_SPI45SEL_0 (0x1UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00010000 */
13483 #define RCC_CDCCIP1R_SPI45SEL_1 (0x2UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00020000 */
13484 #define RCC_CDCCIP1R_SPI45SEL_2 (0x4UL << RCC_CDCCIP1R_SPI45SEL_Pos) /*!< 0x00040000 */
13485
13486 #define RCC_CDCCIP1R_SPDIFSEL_Pos (20U)
13487 #define RCC_CDCCIP1R_SPDIFSEL_Msk (0x3UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00300000 */
13488 #define RCC_CDCCIP1R_SPDIFSEL RCC_CDCCIP1R_SPDIFSEL_Msk
13489 #define RCC_CDCCIP1R_SPDIFSEL_0 (0x1UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00100000 */
13490 #define RCC_CDCCIP1R_SPDIFSEL_1 (0x2UL << RCC_CDCCIP1R_SPDIFSEL_Pos) /*!< 0x00200000 */
13491
13492 #define RCC_CDCCIP1R_DFSDM1SEL_Pos (24U)
13493 #define RCC_CDCCIP1R_DFSDM1SEL_Msk (0x1UL << RCC_CDCCIP1R_DFSDM1SEL_Pos) /*!< 0x01000000 */
13494 #define RCC_CDCCIP1R_DFSDM1SEL RCC_CDCCIP1R_DFSDM1SEL_Msk
13495
13496 #define RCC_CDCCIP1R_FDCANSEL_Pos (28U)
13497 #define RCC_CDCCIP1R_FDCANSEL_Msk (0x3UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x30000000 */
13498 #define RCC_CDCCIP1R_FDCANSEL RCC_CDCCIP1R_FDCANSEL_Msk
13499 #define RCC_CDCCIP1R_FDCANSEL_0 (0x1UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x10000000 */
13500 #define RCC_CDCCIP1R_FDCANSEL_1 (0x2UL << RCC_CDCCIP1R_FDCANSEL_Pos) /*!< 0x20000000 */
13501
13502 #define RCC_CDCCIP1R_SWPSEL_Pos (31U)
13503 #define RCC_CDCCIP1R_SWPSEL_Msk (0x1UL << RCC_CDCCIP1R_SWPSEL_Pos) /*!< 0x80000000 */
13504 #define RCC_CDCCIP1R_SWPSEL RCC_CDCCIP1R_SWPSEL_Msk
13505
13506 /******************** Bit definition for RCC_CDCCIP2R register ***************/
13507 #define RCC_CDCCIP2R_USART234578SEL_Pos (0U)
13508 #define RCC_CDCCIP2R_USART234578SEL_Msk (0x7UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000007 */
13509 #define RCC_CDCCIP2R_USART234578SEL RCC_CDCCIP2R_USART234578SEL_Msk
13510 #define RCC_CDCCIP2R_USART234578SEL_0 (0x1UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000001 */
13511 #define RCC_CDCCIP2R_USART234578SEL_1 (0x2UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000002 */
13512 #define RCC_CDCCIP2R_USART234578SEL_2 (0x4UL << RCC_CDCCIP2R_USART234578SEL_Pos) /*!< 0x00000004 */
13513
13514 #define RCC_CDCCIP2R_USART16910SEL_Pos (3U)
13515 #define RCC_CDCCIP2R_USART16910SEL_Msk (0x7UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000038 */
13516 #define RCC_CDCCIP2R_USART16910SEL RCC_CDCCIP2R_USART16910SEL_Msk
13517 #define RCC_CDCCIP2R_USART16910SEL_0 (0x1UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000008 */
13518 #define RCC_CDCCIP2R_USART16910SEL_1 (0x2UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000010 */
13519 #define RCC_CDCCIP2R_USART16910SEL_2 (0x4UL << RCC_CDCCIP2R_USART16910SEL_Pos) /*!< 0x00000020 */
13520
13521 #define RCC_CDCCIP2R_RNGSEL_Pos (8U)
13522 #define RCC_CDCCIP2R_RNGSEL_Msk (0x3UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000300 */
13523 #define RCC_CDCCIP2R_RNGSEL RCC_CDCCIP2R_RNGSEL_Msk
13524 #define RCC_CDCCIP2R_RNGSEL_0 (0x1UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000100 */
13525 #define RCC_CDCCIP2R_RNGSEL_1 (0x2UL << RCC_CDCCIP2R_RNGSEL_Pos) /*!< 0x00000200 */
13526
13527 #define RCC_CDCCIP2R_I2C123SEL_Pos (12U)
13528 #define RCC_CDCCIP2R_I2C123SEL_Msk (0x3UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00003000 */
13529 #define RCC_CDCCIP2R_I2C123SEL RCC_CDCCIP2R_I2C123SEL_Msk
13530 #define RCC_CDCCIP2R_I2C123SEL_0 (0x1UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00001000 */
13531 #define RCC_CDCCIP2R_I2C123SEL_1 (0x2UL << RCC_CDCCIP2R_I2C123SEL_Pos) /*!< 0x00002000 */
13532
13533 #define RCC_CDCCIP2R_USBSEL_Pos (20U)
13534 #define RCC_CDCCIP2R_USBSEL_Msk (0x3UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00300000 */
13535 #define RCC_CDCCIP2R_USBSEL RCC_CDCCIP2R_USBSEL_Msk
13536 #define RCC_CDCCIP2R_USBSEL_0 (0x1UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00100000 */
13537 #define RCC_CDCCIP2R_USBSEL_1 (0x2UL << RCC_CDCCIP2R_USBSEL_Pos) /*!< 0x00200000 */
13538
13539 #define RCC_CDCCIP2R_CECSEL_Pos (22U)
13540 #define RCC_CDCCIP2R_CECSEL_Msk (0x3UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00C00000 */
13541 #define RCC_CDCCIP2R_CECSEL RCC_CDCCIP2R_CECSEL_Msk
13542 #define RCC_CDCCIP2R_CECSEL_0 (0x1UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00400000 */
13543 #define RCC_CDCCIP2R_CECSEL_1 (0x2UL << RCC_CDCCIP2R_CECSEL_Pos) /*!< 0x00800000 */
13544
13545 #define RCC_CDCCIP2R_LPTIM1SEL_Pos (28U)
13546 #define RCC_CDCCIP2R_LPTIM1SEL_Msk (0x7UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x70000000 */
13547 #define RCC_CDCCIP2R_LPTIM1SEL RCC_CDCCIP2R_LPTIM1SEL_Msk
13548 #define RCC_CDCCIP2R_LPTIM1SEL_0 (0x1UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x10000000 */
13549 #define RCC_CDCCIP2R_LPTIM1SEL_1 (0x2UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x20000000 */
13550 #define RCC_CDCCIP2R_LPTIM1SEL_2 (0x4UL << RCC_CDCCIP2R_LPTIM1SEL_Pos) /*!< 0x40000000 */
13551
13552 /******************** Bit definition for RCC_SRDCCIPR register ***************/
13553 #define RCC_SRDCCIPR_LPUART1SEL_Pos (0U)
13554 #define RCC_SRDCCIPR_LPUART1SEL_Msk (0x7UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000007 */
13555 #define RCC_SRDCCIPR_LPUART1SEL RCC_SRDCCIPR_LPUART1SEL_Msk
13556 #define RCC_SRDCCIPR_LPUART1SEL_0 (0x1UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000001 */
13557 #define RCC_SRDCCIPR_LPUART1SEL_1 (0x2UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000002 */
13558 #define RCC_SRDCCIPR_LPUART1SEL_2 (0x4UL << RCC_SRDCCIPR_LPUART1SEL_Pos) /*!< 0x00000004 */
13559
13560 #define RCC_SRDCCIPR_I2C4SEL_Pos (8U)
13561 #define RCC_SRDCCIPR_I2C4SEL_Msk (0x3UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000300 */
13562 #define RCC_SRDCCIPR_I2C4SEL RCC_SRDCCIPR_I2C4SEL_Msk
13563 #define RCC_SRDCCIPR_I2C4SEL_0 (0x1UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000100 */
13564 #define RCC_SRDCCIPR_I2C4SEL_1 (0x2UL << RCC_SRDCCIPR_I2C4SEL_Pos) /*!< 0x00000200 */
13565
13566 #define RCC_SRDCCIPR_LPTIM2SEL_Pos (10U)
13567 #define RCC_SRDCCIPR_LPTIM2SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00001C00 */
13568 #define RCC_SRDCCIPR_LPTIM2SEL RCC_SRDCCIPR_LPTIM2SEL_Msk
13569 #define RCC_SRDCCIPR_LPTIM2SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00000400 */
13570 #define RCC_SRDCCIPR_LPTIM2SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00000800 */
13571 #define RCC_SRDCCIPR_LPTIM2SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM2SEL_Pos) /*!< 0x00001000 */
13572
13573 #define RCC_SRDCCIPR_LPTIM3SEL_Pos (13U)
13574 #define RCC_SRDCCIPR_LPTIM3SEL_Msk (0x7UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x0000E000 */
13575 #define RCC_SRDCCIPR_LPTIM3SEL RCC_SRDCCIPR_LPTIM3SEL_Msk
13576 #define RCC_SRDCCIPR_LPTIM3SEL_0 (0x1UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00002000 */
13577 #define RCC_SRDCCIPR_LPTIM3SEL_1 (0x2UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00004000 */
13578 #define RCC_SRDCCIPR_LPTIM3SEL_2 (0x4UL << RCC_SRDCCIPR_LPTIM3SEL_Pos) /*!< 0x00008000 */
13579
13580 #define RCC_SRDCCIPR_ADCSEL_Pos (16U)
13581 #define RCC_SRDCCIPR_ADCSEL_Msk (0x3UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00030000 */
13582 #define RCC_SRDCCIPR_ADCSEL RCC_SRDCCIPR_ADCSEL_Msk
13583 #define RCC_SRDCCIPR_ADCSEL_0 (0x1UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00010000 */
13584 #define RCC_SRDCCIPR_ADCSEL_1 (0x2UL << RCC_SRDCCIPR_ADCSEL_Pos) /*!< 0x00020000 */
13585
13586 #define RCC_SRDCCIPR_DFSDM2SEL_Pos (27U)
13587 #define RCC_SRDCCIPR_DFSDM2SEL_Msk (0x1UL << RCC_SRDCCIPR_DFSDM2SEL_Pos) /*!< 0x08000000 */
13588 #define RCC_SRDCCIPR_DFSDM2SEL RCC_SRDCCIPR_DFSDM2SEL_Msk
13589
13590 #define RCC_SRDCCIPR_SPI6SEL_Pos (28U)
13591 #define RCC_SRDCCIPR_SPI6SEL_Msk (0x7UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x70000000 */
13592 #define RCC_SRDCCIPR_SPI6SEL RCC_SRDCCIPR_SPI6SEL_Msk
13593 #define RCC_SRDCCIPR_SPI6SEL_0 (0x1UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x10000000 */
13594 #define RCC_SRDCCIPR_SPI6SEL_1 (0x2UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x20000000 */
13595 #define RCC_SRDCCIPR_SPI6SEL_2 (0x4UL << RCC_SRDCCIPR_SPI6SEL_Pos) /*!< 0x40000000 */
13596
13597 /******************** Bit definition for RCC_CIER register ******************/
13598 #define RCC_CIER_LSIRDYIE_Pos (0U)
13599 #define RCC_CIER_LSIRDYIE_Msk (0x1UL << RCC_CIER_LSIRDYIE_Pos) /*!< 0x00000001 */
13600 #define RCC_CIER_LSIRDYIE RCC_CIER_LSIRDYIE_Msk
13601 #define RCC_CIER_LSERDYIE_Pos (1U)
13602 #define RCC_CIER_LSERDYIE_Msk (0x1UL << RCC_CIER_LSERDYIE_Pos) /*!< 0x00000002 */
13603 #define RCC_CIER_LSERDYIE RCC_CIER_LSERDYIE_Msk
13604 #define RCC_CIER_HSIRDYIE_Pos (2U)
13605 #define RCC_CIER_HSIRDYIE_Msk (0x1UL << RCC_CIER_HSIRDYIE_Pos) /*!< 0x00000004 */
13606 #define RCC_CIER_HSIRDYIE RCC_CIER_HSIRDYIE_Msk
13607 #define RCC_CIER_HSERDYIE_Pos (3U)
13608 #define RCC_CIER_HSERDYIE_Msk (0x1UL << RCC_CIER_HSERDYIE_Pos) /*!< 0x00000008 */
13609 #define RCC_CIER_HSERDYIE RCC_CIER_HSERDYIE_Msk
13610 #define RCC_CIER_CSIRDYIE_Pos (4U)
13611 #define RCC_CIER_CSIRDYIE_Msk (0x1UL << RCC_CIER_CSIRDYIE_Pos) /*!< 0x00000010 */
13612 #define RCC_CIER_CSIRDYIE RCC_CIER_CSIRDYIE_Msk
13613 #define RCC_CIER_HSI48RDYIE_Pos (5U)
13614 #define RCC_CIER_HSI48RDYIE_Msk (0x1UL << RCC_CIER_HSI48RDYIE_Pos) /*!< 0x00000020 */
13615 #define RCC_CIER_HSI48RDYIE RCC_CIER_HSI48RDYIE_Msk
13616 #define RCC_CIER_PLL1RDYIE_Pos (6U)
13617 #define RCC_CIER_PLL1RDYIE_Msk (0x1UL << RCC_CIER_PLL1RDYIE_Pos) /*!< 0x00000040 */
13618 #define RCC_CIER_PLL1RDYIE RCC_CIER_PLL1RDYIE_Msk
13619 #define RCC_CIER_PLL2RDYIE_Pos (7U)
13620 #define RCC_CIER_PLL2RDYIE_Msk (0x1UL << RCC_CIER_PLL2RDYIE_Pos) /*!< 0x00000080 */
13621 #define RCC_CIER_PLL2RDYIE RCC_CIER_PLL2RDYIE_Msk
13622 #define RCC_CIER_PLL3RDYIE_Pos (8U)
13623 #define RCC_CIER_PLL3RDYIE_Msk (0x1UL << RCC_CIER_PLL3RDYIE_Pos) /*!< 0x00000100 */
13624 #define RCC_CIER_PLL3RDYIE RCC_CIER_PLL3RDYIE_Msk
13625 #define RCC_CIER_LSECSSIE_Pos (9U)
13626 #define RCC_CIER_LSECSSIE_Msk (0x1UL << RCC_CIER_LSECSSIE_Pos) /*!< 0x00000200 */
13627 #define RCC_CIER_LSECSSIE RCC_CIER_LSECSSIE_Msk
13628
13629 /******************** Bit definition for RCC_CIFR register ******************/
13630 #define RCC_CIFR_LSIRDYF_Pos (0U)
13631 #define RCC_CIFR_LSIRDYF_Msk (0x1UL << RCC_CIFR_LSIRDYF_Pos) /*!< 0x00000001 */
13632 #define RCC_CIFR_LSIRDYF RCC_CIFR_LSIRDYF_Msk
13633 #define RCC_CIFR_LSERDYF_Pos (1U)
13634 #define RCC_CIFR_LSERDYF_Msk (0x1UL << RCC_CIFR_LSERDYF_Pos) /*!< 0x00000002 */
13635 #define RCC_CIFR_LSERDYF RCC_CIFR_LSERDYF_Msk
13636 #define RCC_CIFR_HSIRDYF_Pos (2U)
13637 #define RCC_CIFR_HSIRDYF_Msk (0x1UL << RCC_CIFR_HSIRDYF_Pos) /*!< 0x00000004 */
13638 #define RCC_CIFR_HSIRDYF RCC_CIFR_HSIRDYF_Msk
13639 #define RCC_CIFR_HSERDYF_Pos (3U)
13640 #define RCC_CIFR_HSERDYF_Msk (0x1UL << RCC_CIFR_HSERDYF_Pos) /*!< 0x00000008 */
13641 #define RCC_CIFR_HSERDYF RCC_CIFR_HSERDYF_Msk
13642 #define RCC_CIFR_CSIRDYF_Pos (4U)
13643 #define RCC_CIFR_CSIRDYF_Msk (0x1UL << RCC_CIFR_CSIRDYF_Pos) /*!< 0x00000010 */
13644 #define RCC_CIFR_CSIRDYF RCC_CIFR_CSIRDYF_Msk
13645 #define RCC_CIFR_HSI48RDYF_Pos (5U)
13646 #define RCC_CIFR_HSI48RDYF_Msk (0x1UL << RCC_CIFR_HSI48RDYF_Pos) /*!< 0x00000020 */
13647 #define RCC_CIFR_HSI48RDYF RCC_CIFR_HSI48RDYF_Msk
13648 #define RCC_CIFR_PLLRDYF_Pos (6U)
13649 #define RCC_CIFR_PLLRDYF_Msk (0x1UL << RCC_CIFR_PLLRDYF_Pos) /*!< 0x00000040 */
13650 #define RCC_CIFR_PLLRDYF RCC_CIFR_PLLRDYF_Msk
13651 #define RCC_CIFR_PLL2RDYF_Pos (7U)
13652 #define RCC_CIFR_PLL2RDYF_Msk (0x1UL << RCC_CIFR_PLL2RDYF_Pos) /*!< 0x00000080 */
13653 #define RCC_CIFR_PLL2RDYF RCC_CIFR_PLL2RDYF_Msk
13654 #define RCC_CIFR_PLL3RDYF_Pos (8U)
13655 #define RCC_CIFR_PLL3RDYF_Msk (0x1UL << RCC_CIFR_PLL3RDYF_Pos) /*!< 0x00000100 */
13656 #define RCC_CIFR_PLL3RDYF RCC_CIFR_PLL3RDYF_Msk
13657 #define RCC_CIFR_LSECSSF_Pos (9U)
13658 #define RCC_CIFR_LSECSSF_Msk (0x1UL << RCC_CIFR_LSECSSF_Pos) /*!< 0x00000200 */
13659 #define RCC_CIFR_LSECSSF RCC_CIFR_LSECSSF_Msk
13660 #define RCC_CIFR_HSECSSF_Pos (10U)
13661 #define RCC_CIFR_HSECSSF_Msk (0x1UL << RCC_CIFR_HSECSSF_Pos) /*!< 0x00000400 */
13662 #define RCC_CIFR_HSECSSF RCC_CIFR_HSECSSF_Msk
13663
13664 /******************** Bit definition for RCC_CICR register ******************/
13665 #define RCC_CICR_LSIRDYC_Pos (0U)
13666 #define RCC_CICR_LSIRDYC_Msk (0x1UL << RCC_CICR_LSIRDYC_Pos) /*!< 0x00000001 */
13667 #define RCC_CICR_LSIRDYC RCC_CICR_LSIRDYC_Msk
13668 #define RCC_CICR_LSERDYC_Pos (1U)
13669 #define RCC_CICR_LSERDYC_Msk (0x1UL << RCC_CICR_LSERDYC_Pos) /*!< 0x00000002 */
13670 #define RCC_CICR_LSERDYC RCC_CICR_LSERDYC_Msk
13671 #define RCC_CICR_HSIRDYC_Pos (2U)
13672 #define RCC_CICR_HSIRDYC_Msk (0x1UL << RCC_CICR_HSIRDYC_Pos) /*!< 0x00000004 */
13673 #define RCC_CICR_HSIRDYC RCC_CICR_HSIRDYC_Msk
13674 #define RCC_CICR_HSERDYC_Pos (3U)
13675 #define RCC_CICR_HSERDYC_Msk (0x1UL << RCC_CICR_HSERDYC_Pos) /*!< 0x00000008 */
13676 #define RCC_CICR_HSERDYC RCC_CICR_HSERDYC_Msk
13677 #define RCC_CICR_CSIRDYC_Pos (4U)
13678 #define RCC_CICR_CSIRDYC_Msk (0x1UL << RCC_CICR_CSIRDYC_Pos) /*!< 0x00000010 */
13679 #define RCC_CICR_CSIRDYC RCC_CICR_CSIRDYC_Msk
13680 #define RCC_CICR_HSI48RDYC_Pos (5U)
13681 #define RCC_CICR_HSI48RDYC_Msk (0x1UL << RCC_CICR_HSI48RDYC_Pos) /*!< 0x00000020 */
13682 #define RCC_CICR_HSI48RDYC RCC_CICR_HSI48RDYC_Msk
13683 #define RCC_CICR_PLLRDYC_Pos (6U)
13684 #define RCC_CICR_PLLRDYC_Msk (0x1UL << RCC_CICR_PLLRDYC_Pos) /*!< 0x00000040 */
13685 #define RCC_CICR_PLLRDYC RCC_CICR_PLLRDYC_Msk
13686 #define RCC_CICR_PLL2RDYC_Pos (7U)
13687 #define RCC_CICR_PLL2RDYC_Msk (0x1UL << RCC_CICR_PLL2RDYC_Pos) /*!< 0x00000080 */
13688 #define RCC_CICR_PLL2RDYC RCC_CICR_PLL2RDYC_Msk
13689 #define RCC_CICR_PLL3RDYC_Pos (8U)
13690 #define RCC_CICR_PLL3RDYC_Msk (0x1UL << RCC_CICR_PLL3RDYC_Pos) /*!< 0x00000100 */
13691 #define RCC_CICR_PLL3RDYC RCC_CICR_PLL3RDYC_Msk
13692 #define RCC_CICR_LSECSSC_Pos (9U)
13693 #define RCC_CICR_LSECSSC_Msk (0x1UL << RCC_CICR_LSECSSC_Pos) /*!< 0x00000200 */
13694 #define RCC_CICR_LSECSSC RCC_CICR_LSECSSC_Msk
13695 #define RCC_CICR_HSECSSC_Pos (10U)
13696 #define RCC_CICR_HSECSSC_Msk (0x1UL << RCC_CICR_HSECSSC_Pos) /*!< 0x00000400 */
13697 #define RCC_CICR_HSECSSC RCC_CICR_HSECSSC_Msk
13698
13699 /******************** Bit definition for RCC_BDCR register ******************/
13700 #define RCC_BDCR_LSEON_Pos (0U)
13701 #define RCC_BDCR_LSEON_Msk (0x1UL << RCC_BDCR_LSEON_Pos) /*!< 0x00000001 */
13702 #define RCC_BDCR_LSEON RCC_BDCR_LSEON_Msk
13703 #define RCC_BDCR_LSERDY_Pos (1U)
13704 #define RCC_BDCR_LSERDY_Msk (0x1UL << RCC_BDCR_LSERDY_Pos) /*!< 0x00000002 */
13705 #define RCC_BDCR_LSERDY RCC_BDCR_LSERDY_Msk
13706 #define RCC_BDCR_LSEBYP_Pos (2U)
13707 #define RCC_BDCR_LSEBYP_Msk (0x1UL << RCC_BDCR_LSEBYP_Pos) /*!< 0x00000004 */
13708 #define RCC_BDCR_LSEBYP RCC_BDCR_LSEBYP_Msk
13709
13710 #define RCC_BDCR_LSEDRV_Pos (3U)
13711 #define RCC_BDCR_LSEDRV_Msk (0x3UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000018 */
13712 #define RCC_BDCR_LSEDRV RCC_BDCR_LSEDRV_Msk
13713 #define RCC_BDCR_LSEDRV_0 (0x1UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000008 */
13714 #define RCC_BDCR_LSEDRV_1 (0x2UL << RCC_BDCR_LSEDRV_Pos) /*!< 0x00000010 */
13715
13716 #define RCC_BDCR_LSECSSON_Pos (5U)
13717 #define RCC_BDCR_LSECSSON_Msk (0x1UL << RCC_BDCR_LSECSSON_Pos) /*!< 0x00000020 */
13718 #define RCC_BDCR_LSECSSON RCC_BDCR_LSECSSON_Msk
13719 #define RCC_BDCR_LSECSSD_Pos (6U)
13720 #define RCC_BDCR_LSECSSD_Msk (0x1UL << RCC_BDCR_LSECSSD_Pos) /*!< 0x00000040 */
13721 #define RCC_BDCR_LSECSSD RCC_BDCR_LSECSSD_Msk
13722 #define RCC_BDCR_LSEEXT_Pos (7U)
13723 #define RCC_BDCR_LSEEXT_Msk (0x1UL << RCC_BDCR_LSEEXT_Pos) /*!< 0x00000080 */
13724 #define RCC_BDCR_LSEEXT RCC_BDCR_LSEEXT_Msk
13725
13726 #define RCC_BDCR_RTCSEL_Pos (8U)
13727 #define RCC_BDCR_RTCSEL_Msk (0x3UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000300 */
13728 #define RCC_BDCR_RTCSEL RCC_BDCR_RTCSEL_Msk
13729 #define RCC_BDCR_RTCSEL_0 (0x1UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000100 */
13730 #define RCC_BDCR_RTCSEL_1 (0x2UL << RCC_BDCR_RTCSEL_Pos) /*!< 0x00000200 */
13731
13732 #define RCC_BDCR_RTCEN_Pos (15U)
13733 #define RCC_BDCR_RTCEN_Msk (0x1UL << RCC_BDCR_RTCEN_Pos) /*!< 0x00008000 */
13734 #define RCC_BDCR_RTCEN RCC_BDCR_RTCEN_Msk
13735 #define RCC_BDCR_VSWRST_Pos (16U)
13736 #define RCC_BDCR_VSWRST_Msk (0x1UL << RCC_BDCR_VSWRST_Pos) /*!< 0x00010000 */
13737 #define RCC_BDCR_VSWRST RCC_BDCR_VSWRST_Msk
13738 /* Legacy define */
13739 #define RCC_BDCR_BDRST_Pos RCC_BDCR_VSWRST_Pos
13740 #define RCC_BDCR_BDRST_Msk RCC_BDCR_VSWRST_Msk
13741 #define RCC_BDCR_BDRST RCC_BDCR_VSWRST
13742 /******************** Bit definition for RCC_CSR register *******************/
13743 #define RCC_CSR_LSION_Pos (0U)
13744 #define RCC_CSR_LSION_Msk (0x1UL << RCC_CSR_LSION_Pos) /*!< 0x00000001 */
13745 #define RCC_CSR_LSION RCC_CSR_LSION_Msk
13746 #define RCC_CSR_LSIRDY_Pos (1U)
13747 #define RCC_CSR_LSIRDY_Msk (0x1UL << RCC_CSR_LSIRDY_Pos) /*!< 0x00000002 */
13748 #define RCC_CSR_LSIRDY RCC_CSR_LSIRDY_Msk
13749
13750
13751 /******************** Bit definition for RCC_AHB3ENR register **************/
13752 #define RCC_AHB3ENR_MDMAEN_Pos (0U)
13753 #define RCC_AHB3ENR_MDMAEN_Msk (0x1UL << RCC_AHB3ENR_MDMAEN_Pos) /*!< 0x00000001 */
13754 #define RCC_AHB3ENR_MDMAEN RCC_AHB3ENR_MDMAEN_Msk
13755 #define RCC_AHB3ENR_DMA2DEN_Pos (4U)
13756 #define RCC_AHB3ENR_DMA2DEN_Msk (0x1UL << RCC_AHB3ENR_DMA2DEN_Pos) /*!< 0x00000010 */
13757 #define RCC_AHB3ENR_DMA2DEN RCC_AHB3ENR_DMA2DEN_Msk
13758 #define RCC_AHB3ENR_JPGDECEN_Pos (5U)
13759 #define RCC_AHB3ENR_JPGDECEN_Msk (0x1UL << RCC_AHB3ENR_JPGDECEN_Pos) /*!< 0x00000020 */
13760 #define RCC_AHB3ENR_JPGDECEN RCC_AHB3ENR_JPGDECEN_Msk
13761 #define RCC_AHB3ENR_FMCEN_Pos (12U)
13762 #define RCC_AHB3ENR_FMCEN_Msk (0x1UL << RCC_AHB3ENR_FMCEN_Pos) /*!< 0x00001000 */
13763 #define RCC_AHB3ENR_FMCEN RCC_AHB3ENR_FMCEN_Msk
13764 #define RCC_AHB3ENR_OSPI1EN_Pos (14U)
13765 #define RCC_AHB3ENR_OSPI1EN_Msk (0x1UL << RCC_AHB3ENR_OSPI1EN_Pos) /*!< 0x00004000 */
13766 #define RCC_AHB3ENR_OSPI1EN RCC_AHB3ENR_OSPI1EN_Msk
13767 #define RCC_AHB3ENR_SDMMC1EN_Pos (16U)
13768 #define RCC_AHB3ENR_SDMMC1EN_Msk (0x1UL << RCC_AHB3ENR_SDMMC1EN_Pos) /*!< 0x00010000 */
13769 #define RCC_AHB3ENR_SDMMC1EN RCC_AHB3ENR_SDMMC1EN_Msk
13770 #define RCC_AHB3ENR_OSPI2EN_Pos (19U)
13771 #define RCC_AHB3ENR_OSPI2EN_Msk (0x1UL << RCC_AHB3ENR_OSPI2EN_Pos) /*!< 0x00040000 */
13772 #define RCC_AHB3ENR_OSPI2EN RCC_AHB3ENR_OSPI2EN_Msk
13773 #define RCC_AHB3ENR_IOMNGREN_Pos (21U)
13774 #define RCC_AHB3ENR_IOMNGREN_Msk (0x1UL << RCC_AHB3ENR_IOMNGREN_Pos) /*!< 0x00100000 */
13775 #define RCC_AHB3ENR_IOMNGREN RCC_AHB3ENR_IOMNGREN_Msk
13776 #define RCC_AHB3ENR_OTFDEC1EN_Pos (22U)
13777 #define RCC_AHB3ENR_OTFDEC1EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC1EN_Pos) /*!< 0x00200000 */
13778 #define RCC_AHB3ENR_OTFDEC1EN RCC_AHB3ENR_OTFDEC1EN_Msk
13779 #define RCC_AHB3ENR_OTFDEC2EN_Pos (23U)
13780 #define RCC_AHB3ENR_OTFDEC2EN_Msk (0x1UL << RCC_AHB3ENR_OTFDEC2EN_Pos) /*!< 0x00400000 */
13781 #define RCC_AHB3ENR_OTFDEC2EN RCC_AHB3ENR_OTFDEC2EN_Msk
13782 #define RCC_AHB3ENR_GFXMMUEN_Pos (24U)
13783 #define RCC_AHB3ENR_GFXMMUEN_Msk (0x1UL << RCC_AHB3ENR_GFXMMUEN_Pos) /*!< 0x00800000 */
13784 #define RCC_AHB3ENR_GFXMMUEN RCC_AHB3ENR_GFXMMUEN_Msk
13785
13786 /******************** Bit definition for RCC_AHB1ENR register ***************/
13787 #define RCC_AHB1ENR_DMA1EN_Pos (0U)
13788 #define RCC_AHB1ENR_DMA1EN_Msk (0x1UL << RCC_AHB1ENR_DMA1EN_Pos) /*!< 0x00000001 */
13789 #define RCC_AHB1ENR_DMA1EN RCC_AHB1ENR_DMA1EN_Msk
13790 #define RCC_AHB1ENR_DMA2EN_Pos (1U)
13791 #define RCC_AHB1ENR_DMA2EN_Msk (0x1UL << RCC_AHB1ENR_DMA2EN_Pos) /*!< 0x00000002 */
13792 #define RCC_AHB1ENR_DMA2EN RCC_AHB1ENR_DMA2EN_Msk
13793 #define RCC_AHB1ENR_ADC12EN_Pos (5U)
13794 #define RCC_AHB1ENR_ADC12EN_Msk (0x1UL << RCC_AHB1ENR_ADC12EN_Pos) /*!< 0x00000020 */
13795 #define RCC_AHB1ENR_ADC12EN RCC_AHB1ENR_ADC12EN_Msk
13796 #define RCC_AHB1ENR_CRCEN_Pos (9U)
13797 #define RCC_AHB1ENR_CRCEN_Msk (0x1UL << RCC_AHB1ENR_CRCEN_Pos) /*!< 0x00000200 */
13798 #define RCC_AHB1ENR_CRCEN RCC_AHB1ENR_CRCEN_Msk
13799 #define RCC_AHB1ENR_USB1OTGHSEN_Pos (25U)
13800 #define RCC_AHB1ENR_USB1OTGHSEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSEN_Pos) /*!< 0x02000000 */
13801 #define RCC_AHB1ENR_USB1OTGHSEN RCC_AHB1ENR_USB1OTGHSEN_Msk
13802 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Pos (26U)
13803 #define RCC_AHB1ENR_USB1OTGHSULPIEN_Msk (0x1UL << RCC_AHB1ENR_USB1OTGHSULPIEN_Pos) /*!< 0x04000000 */
13804 #define RCC_AHB1ENR_USB1OTGHSULPIEN RCC_AHB1ENR_USB1OTGHSULPIEN_Msk
13805
13806 /******************** Bit definition for RCC_AHB2ENR register ***************/
13807 #define RCC_AHB2ENR_DCMI_PSSIEN_Pos (0U)
13808 #define RCC_AHB2ENR_DCMI_PSSIEN_Msk (0x1UL << RCC_AHB2ENR_DCMI_PSSIEN_Pos) /*!< 0x00000001 */
13809 #define RCC_AHB2ENR_DCMI_PSSIEN RCC_AHB2ENR_DCMI_PSSIEN_Msk
13810 #define RCC_AHB2ENR_HSEMEN_Pos (2U)
13811 #define RCC_AHB2ENR_HSEMEN_Msk (0x1UL << RCC_AHB2ENR_HSEMEN_Pos) /*!< 0x00000004 */
13812 #define RCC_AHB2ENR_HSEMEN RCC_AHB2ENR_HSEMEN_Msk
13813 #define RCC_AHB2ENR_CRYPEN_Pos (4U)
13814 #define RCC_AHB2ENR_CRYPEN_Msk (0x1UL << RCC_AHB2ENR_CRYPEN_Pos) /*!< 0x00000010 */
13815 #define RCC_AHB2ENR_CRYPEN RCC_AHB2ENR_CRYPEN_Msk
13816 #define RCC_AHB2ENR_HASHEN_Pos (5U)
13817 #define RCC_AHB2ENR_HASHEN_Msk (0x1UL << RCC_AHB2ENR_HASHEN_Pos) /*!< 0x00000020 */
13818 #define RCC_AHB2ENR_HASHEN RCC_AHB2ENR_HASHEN_Msk
13819 #define RCC_AHB2ENR_RNGEN_Pos (6U)
13820 #define RCC_AHB2ENR_RNGEN_Msk (0x1UL << RCC_AHB2ENR_RNGEN_Pos) /*!< 0x00000040 */
13821 #define RCC_AHB2ENR_RNGEN RCC_AHB2ENR_RNGEN_Msk
13822 #define RCC_AHB2ENR_SDMMC2EN_Pos (9U)
13823 #define RCC_AHB2ENR_SDMMC2EN_Msk (0x1UL << RCC_AHB2ENR_SDMMC2EN_Pos) /*!< 0x00000200 */
13824 #define RCC_AHB2ENR_SDMMC2EN RCC_AHB2ENR_SDMMC2EN_Msk
13825 #define RCC_AHB2ENR_BDMA1EN_Pos (11U)
13826 #define RCC_AHB2ENR_BDMA1EN_Msk (0x1UL << RCC_AHB2ENR_BDMA1EN_Pos) /*!< 0x00000800 */
13827 #define RCC_AHB2ENR_BDMA1EN RCC_AHB2ENR_BDMA1EN_Msk
13828 #define RCC_AHB2ENR_AHBSRAM1EN_Pos (29U)
13829 #define RCC_AHB2ENR_AHBSRAM1EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM1EN_Pos) /*!< 0x20000000 */
13830 #define RCC_AHB2ENR_AHBSRAM1EN RCC_AHB2ENR_AHBSRAM1EN_Msk
13831 #define RCC_AHB2ENR_AHBSRAM2EN_Pos (30U)
13832 #define RCC_AHB2ENR_AHBSRAM2EN_Msk (0x1UL << RCC_AHB2ENR_AHBSRAM2EN_Pos) /*!< 0x40000000 */
13833 #define RCC_AHB2ENR_AHBSRAM2EN RCC_AHB2ENR_AHBSRAM2EN_Msk
13834
13835 /* Legacy define */
13836 #define RCC_AHB2ENR_DCMIEN_Pos RCC_AHB2ENR_DCMI_PSSIEN_Pos
13837 #define RCC_AHB2ENR_DCMIEN_Msk RCC_AHB2ENR_DCMI_PSSIEN_Msk
13838 #define RCC_AHB2ENR_DCMIEN RCC_AHB2ENR_DCMI_PSSIEN
13839
13840 /******************** Bit definition for RCC_AHB4ENR register ******************/
13841 #define RCC_AHB4ENR_GPIOAEN_Pos (0U)
13842 #define RCC_AHB4ENR_GPIOAEN_Msk (0x1UL << RCC_AHB4ENR_GPIOAEN_Pos) /*!< 0x00000001 */
13843 #define RCC_AHB4ENR_GPIOAEN RCC_AHB4ENR_GPIOAEN_Msk
13844 #define RCC_AHB4ENR_GPIOBEN_Pos (1U)
13845 #define RCC_AHB4ENR_GPIOBEN_Msk (0x1UL << RCC_AHB4ENR_GPIOBEN_Pos) /*!< 0x00000002 */
13846 #define RCC_AHB4ENR_GPIOBEN RCC_AHB4ENR_GPIOBEN_Msk
13847 #define RCC_AHB4ENR_GPIOCEN_Pos (2U)
13848 #define RCC_AHB4ENR_GPIOCEN_Msk (0x1UL << RCC_AHB4ENR_GPIOCEN_Pos) /*!< 0x00000004 */
13849 #define RCC_AHB4ENR_GPIOCEN RCC_AHB4ENR_GPIOCEN_Msk
13850 #define RCC_AHB4ENR_GPIODEN_Pos (3U)
13851 #define RCC_AHB4ENR_GPIODEN_Msk (0x1UL << RCC_AHB4ENR_GPIODEN_Pos) /*!< 0x00000008 */
13852 #define RCC_AHB4ENR_GPIODEN RCC_AHB4ENR_GPIODEN_Msk
13853 #define RCC_AHB4ENR_GPIOEEN_Pos (4U)
13854 #define RCC_AHB4ENR_GPIOEEN_Msk (0x1UL << RCC_AHB4ENR_GPIOEEN_Pos) /*!< 0x00000010 */
13855 #define RCC_AHB4ENR_GPIOEEN RCC_AHB4ENR_GPIOEEN_Msk
13856 #define RCC_AHB4ENR_GPIOFEN_Pos (5U)
13857 #define RCC_AHB4ENR_GPIOFEN_Msk (0x1UL << RCC_AHB4ENR_GPIOFEN_Pos) /*!< 0x00000020 */
13858 #define RCC_AHB4ENR_GPIOFEN RCC_AHB4ENR_GPIOFEN_Msk
13859 #define RCC_AHB4ENR_GPIOGEN_Pos (6U)
13860 #define RCC_AHB4ENR_GPIOGEN_Msk (0x1UL << RCC_AHB4ENR_GPIOGEN_Pos) /*!< 0x00000040 */
13861 #define RCC_AHB4ENR_GPIOGEN RCC_AHB4ENR_GPIOGEN_Msk
13862 #define RCC_AHB4ENR_GPIOHEN_Pos (7U)
13863 #define RCC_AHB4ENR_GPIOHEN_Msk (0x1UL << RCC_AHB4ENR_GPIOHEN_Pos) /*!< 0x00000080 */
13864 #define RCC_AHB4ENR_GPIOHEN RCC_AHB4ENR_GPIOHEN_Msk
13865 #define RCC_AHB4ENR_GPIOIEN_Pos (8U)
13866 #define RCC_AHB4ENR_GPIOIEN_Msk (0x1UL << RCC_AHB4ENR_GPIOIEN_Pos) /*!< 0x00000100 */
13867 #define RCC_AHB4ENR_GPIOIEN RCC_AHB4ENR_GPIOIEN_Msk
13868 #define RCC_AHB4ENR_GPIOJEN_Pos (9U)
13869 #define RCC_AHB4ENR_GPIOJEN_Msk (0x1UL << RCC_AHB4ENR_GPIOJEN_Pos) /*!< 0x00000200 */
13870 #define RCC_AHB4ENR_GPIOJEN RCC_AHB4ENR_GPIOJEN_Msk
13871 #define RCC_AHB4ENR_GPIOKEN_Pos (10U)
13872 #define RCC_AHB4ENR_GPIOKEN_Msk (0x1UL << RCC_AHB4ENR_GPIOKEN_Pos) /*!< 0x00000400 */
13873 #define RCC_AHB4ENR_GPIOKEN RCC_AHB4ENR_GPIOKEN_Msk
13874 #define RCC_AHB4ENR_BDMA2EN_Pos (21U)
13875 #define RCC_AHB4ENR_BDMA2EN_Msk (0x1UL << RCC_AHB4ENR_BDMA2EN_Pos) /*!< 0x00080000 */
13876 #define RCC_AHB4ENR_BDMA2EN RCC_AHB4ENR_BDMA2EN_Msk
13877 #define RCC_AHB4ENR_BKPRAMEN_Pos (28U)
13878 #define RCC_AHB4ENR_BKPRAMEN_Msk (0x1UL << RCC_AHB4ENR_BKPRAMEN_Pos) /*!< 0x10000000 */
13879 #define RCC_AHB4ENR_BKPRAMEN RCC_AHB4ENR_BKPRAMEN_Msk
13880 #define RCC_AHB4ENR_SRDSRAMEN_Pos (29U)
13881 #define RCC_AHB4ENR_SRDSRAMEN_Msk (0x1UL << RCC_AHB4ENR_SRDSRAMEN_Pos) /*!< 0x20000000 */
13882 #define RCC_AHB4ENR_SRDSRAMEN RCC_AHB4ENR_SRDSRAMEN_Msk
13883
13884 /******************** Bit definition for RCC_APB3ENR register ******************/
13885 #define RCC_APB3ENR_LTDCEN_Pos (3U)
13886 #define RCC_APB3ENR_LTDCEN_Msk (0x1UL << RCC_APB3ENR_LTDCEN_Pos) /*!< 0x00000008 */
13887 #define RCC_APB3ENR_LTDCEN RCC_APB3ENR_LTDCEN_Msk
13888 #define RCC_APB3ENR_WWDGEN_Pos (6U)
13889 #define RCC_APB3ENR_WWDGEN_Msk (0x1UL << RCC_APB3ENR_WWDGEN_Pos) /*!< 0x00000040 */
13890 #define RCC_APB3ENR_WWDGEN RCC_APB3ENR_WWDGEN_Msk
13891
13892 /* Legacy define */
13893 #define RCC_APB3ENR_WWDG1EN_Pos RCC_APB3ENR_WWDGEN_Pos
13894 #define RCC_APB3ENR_WWDG1EN_Msk RCC_APB3ENR_WWDGEN_Msk
13895 #define RCC_APB3ENR_WWDG1EN RCC_APB3ENR_WWDGEN
13896 /******************** Bit definition for RCC_APB1LENR register ******************/
13897
13898 #define RCC_APB1LENR_TIM2EN_Pos (0U)
13899 #define RCC_APB1LENR_TIM2EN_Msk (0x1UL << RCC_APB1LENR_TIM2EN_Pos) /*!< 0x00000001 */
13900 #define RCC_APB1LENR_TIM2EN RCC_APB1LENR_TIM2EN_Msk
13901 #define RCC_APB1LENR_TIM3EN_Pos (1U)
13902 #define RCC_APB1LENR_TIM3EN_Msk (0x1UL << RCC_APB1LENR_TIM3EN_Pos) /*!< 0x00000002 */
13903 #define RCC_APB1LENR_TIM3EN RCC_APB1LENR_TIM3EN_Msk
13904 #define RCC_APB1LENR_TIM4EN_Pos (2U)
13905 #define RCC_APB1LENR_TIM4EN_Msk (0x1UL << RCC_APB1LENR_TIM4EN_Pos) /*!< 0x00000004 */
13906 #define RCC_APB1LENR_TIM4EN RCC_APB1LENR_TIM4EN_Msk
13907 #define RCC_APB1LENR_TIM5EN_Pos (3U)
13908 #define RCC_APB1LENR_TIM5EN_Msk (0x1UL << RCC_APB1LENR_TIM5EN_Pos) /*!< 0x00000008 */
13909 #define RCC_APB1LENR_TIM5EN RCC_APB1LENR_TIM5EN_Msk
13910 #define RCC_APB1LENR_TIM6EN_Pos (4U)
13911 #define RCC_APB1LENR_TIM6EN_Msk (0x1UL << RCC_APB1LENR_TIM6EN_Pos) /*!< 0x00000010 */
13912 #define RCC_APB1LENR_TIM6EN RCC_APB1LENR_TIM6EN_Msk
13913 #define RCC_APB1LENR_TIM7EN_Pos (5U)
13914 #define RCC_APB1LENR_TIM7EN_Msk (0x1UL << RCC_APB1LENR_TIM7EN_Pos) /*!< 0x00000020 */
13915 #define RCC_APB1LENR_TIM7EN RCC_APB1LENR_TIM7EN_Msk
13916 #define RCC_APB1LENR_TIM12EN_Pos (6U)
13917 #define RCC_APB1LENR_TIM12EN_Msk (0x1UL << RCC_APB1LENR_TIM12EN_Pos) /*!< 0x00000040 */
13918 #define RCC_APB1LENR_TIM12EN RCC_APB1LENR_TIM12EN_Msk
13919 #define RCC_APB1LENR_TIM13EN_Pos (7U)
13920 #define RCC_APB1LENR_TIM13EN_Msk (0x1UL << RCC_APB1LENR_TIM13EN_Pos) /*!< 0x00000080 */
13921 #define RCC_APB1LENR_TIM13EN RCC_APB1LENR_TIM13EN_Msk
13922 #define RCC_APB1LENR_TIM14EN_Pos (8U)
13923 #define RCC_APB1LENR_TIM14EN_Msk (0x1UL << RCC_APB1LENR_TIM14EN_Pos) /*!< 0x00000100 */
13924 #define RCC_APB1LENR_TIM14EN RCC_APB1LENR_TIM14EN_Msk
13925 #define RCC_APB1LENR_LPTIM1EN_Pos (9U)
13926 #define RCC_APB1LENR_LPTIM1EN_Msk (0x1UL << RCC_APB1LENR_LPTIM1EN_Pos) /*!< 0x00000200 */
13927 #define RCC_APB1LENR_LPTIM1EN RCC_APB1LENR_LPTIM1EN_Msk
13928
13929
13930 #define RCC_APB1LENR_SPI2EN_Pos (14U)
13931 #define RCC_APB1LENR_SPI2EN_Msk (0x1UL << RCC_APB1LENR_SPI2EN_Pos) /*!< 0x00004000 */
13932 #define RCC_APB1LENR_SPI2EN RCC_APB1LENR_SPI2EN_Msk
13933 #define RCC_APB1LENR_SPI3EN_Pos (15U)
13934 #define RCC_APB1LENR_SPI3EN_Msk (0x1UL << RCC_APB1LENR_SPI3EN_Pos) /*!< 0x00008000 */
13935 #define RCC_APB1LENR_SPI3EN RCC_APB1LENR_SPI3EN_Msk
13936 #define RCC_APB1LENR_SPDIFRXEN_Pos (16U)
13937 #define RCC_APB1LENR_SPDIFRXEN_Msk (0x1UL << RCC_APB1LENR_SPDIFRXEN_Pos) /*!< 0x00010000 */
13938 #define RCC_APB1LENR_SPDIFRXEN RCC_APB1LENR_SPDIFRXEN_Msk
13939 #define RCC_APB1LENR_USART2EN_Pos (17U)
13940 #define RCC_APB1LENR_USART2EN_Msk (0x1UL << RCC_APB1LENR_USART2EN_Pos) /*!< 0x00020000 */
13941 #define RCC_APB1LENR_USART2EN RCC_APB1LENR_USART2EN_Msk
13942 #define RCC_APB1LENR_USART3EN_Pos (18U)
13943 #define RCC_APB1LENR_USART3EN_Msk (0x1UL << RCC_APB1LENR_USART3EN_Pos) /*!< 0x00040000 */
13944 #define RCC_APB1LENR_USART3EN RCC_APB1LENR_USART3EN_Msk
13945 #define RCC_APB1LENR_UART4EN_Pos (19U)
13946 #define RCC_APB1LENR_UART4EN_Msk (0x1UL << RCC_APB1LENR_UART4EN_Pos) /*!< 0x00080000 */
13947 #define RCC_APB1LENR_UART4EN RCC_APB1LENR_UART4EN_Msk
13948 #define RCC_APB1LENR_UART5EN_Pos (20U)
13949 #define RCC_APB1LENR_UART5EN_Msk (0x1UL << RCC_APB1LENR_UART5EN_Pos) /*!< 0x00100000 */
13950 #define RCC_APB1LENR_UART5EN RCC_APB1LENR_UART5EN_Msk
13951 #define RCC_APB1LENR_I2C1EN_Pos (21U)
13952 #define RCC_APB1LENR_I2C1EN_Msk (0x1UL << RCC_APB1LENR_I2C1EN_Pos) /*!< 0x00200000 */
13953 #define RCC_APB1LENR_I2C1EN RCC_APB1LENR_I2C1EN_Msk
13954 #define RCC_APB1LENR_I2C2EN_Pos (22U)
13955 #define RCC_APB1LENR_I2C2EN_Msk (0x1UL << RCC_APB1LENR_I2C2EN_Pos) /*!< 0x00400000 */
13956 #define RCC_APB1LENR_I2C2EN RCC_APB1LENR_I2C2EN_Msk
13957 #define RCC_APB1LENR_I2C3EN_Pos (23U)
13958 #define RCC_APB1LENR_I2C3EN_Msk (0x1UL << RCC_APB1LENR_I2C3EN_Pos) /*!< 0x00800000 */
13959 #define RCC_APB1LENR_I2C3EN RCC_APB1LENR_I2C3EN_Msk
13960 #define RCC_APB1LENR_CECEN_Pos (27U)
13961 #define RCC_APB1LENR_CECEN_Msk (0x1UL << RCC_APB1LENR_CECEN_Pos) /*!< 0x08000000 */
13962 #define RCC_APB1LENR_CECEN RCC_APB1LENR_CECEN_Msk
13963 #define RCC_APB1LENR_DAC12EN_Pos (29U)
13964 #define RCC_APB1LENR_DAC12EN_Msk (0x1UL << RCC_APB1LENR_DAC12EN_Pos) /*!< 0x20000000 */
13965 #define RCC_APB1LENR_DAC12EN RCC_APB1LENR_DAC12EN_Msk
13966 #define RCC_APB1LENR_UART7EN_Pos (30U)
13967 #define RCC_APB1LENR_UART7EN_Msk (0x1UL << RCC_APB1LENR_UART7EN_Pos) /*!< 0x40000000 */
13968 #define RCC_APB1LENR_UART7EN RCC_APB1LENR_UART7EN_Msk
13969 #define RCC_APB1LENR_UART8EN_Pos (31U)
13970 #define RCC_APB1LENR_UART8EN_Msk (0x1UL << RCC_APB1LENR_UART8EN_Pos) /*!< 0x80000000 */
13971 #define RCC_APB1LENR_UART8EN RCC_APB1LENR_UART8EN_Msk
13972
13973 /* Legacy define */
13974 #define RCC_APB1LENR_HDMICECEN_Pos RCC_APB1LENR_CECEN_Pos
13975 #define RCC_APB1LENR_HDMICECEN_Msk RCC_APB1LENR_CECEN_Msk
13976 #define RCC_APB1LENR_HDMICECEN RCC_APB1LENR_CECEN
13977 /******************** Bit definition for RCC_APB1HENR register ******************/
13978 #define RCC_APB1HENR_CRSEN_Pos (1U)
13979 #define RCC_APB1HENR_CRSEN_Msk (0x1UL << RCC_APB1HENR_CRSEN_Pos) /*!< 0x00000002 */
13980 #define RCC_APB1HENR_CRSEN RCC_APB1HENR_CRSEN_Msk
13981 #define RCC_APB1HENR_SWPMIEN_Pos (2U)
13982 #define RCC_APB1HENR_SWPMIEN_Msk (0x1UL << RCC_APB1HENR_SWPMIEN_Pos) /*!< 0x00000004 */
13983 #define RCC_APB1HENR_SWPMIEN RCC_APB1HENR_SWPMIEN_Msk
13984 #define RCC_APB1HENR_OPAMPEN_Pos (4U)
13985 #define RCC_APB1HENR_OPAMPEN_Msk (0x1UL << RCC_APB1HENR_OPAMPEN_Pos) /*!< 0x00000010 */
13986 #define RCC_APB1HENR_OPAMPEN RCC_APB1HENR_OPAMPEN_Msk
13987 #define RCC_APB1HENR_MDIOSEN_Pos (5U)
13988 #define RCC_APB1HENR_MDIOSEN_Msk (0x1UL << RCC_APB1HENR_MDIOSEN_Pos) /*!< 0x00000020 */
13989 #define RCC_APB1HENR_MDIOSEN RCC_APB1HENR_MDIOSEN_Msk
13990 #define RCC_APB1HENR_FDCANEN_Pos (8U)
13991 #define RCC_APB1HENR_FDCANEN_Msk (0x1UL << RCC_APB1HENR_FDCANEN_Pos) /*!< 0x00000100 */
13992 #define RCC_APB1HENR_FDCANEN RCC_APB1HENR_FDCANEN_Msk
13993
13994 /******************** Bit definition for RCC_APB2ENR register ******************/
13995 #define RCC_APB2ENR_TIM1EN_Pos (0U)
13996 #define RCC_APB2ENR_TIM1EN_Msk (0x1UL << RCC_APB2ENR_TIM1EN_Pos) /*!< 0x00000001 */
13997 #define RCC_APB2ENR_TIM1EN RCC_APB2ENR_TIM1EN_Msk
13998 #define RCC_APB2ENR_TIM8EN_Pos (1U)
13999 #define RCC_APB2ENR_TIM8EN_Msk (0x1UL << RCC_APB2ENR_TIM8EN_Pos) /*!< 0x00000002 */
14000 #define RCC_APB2ENR_TIM8EN RCC_APB2ENR_TIM8EN_Msk
14001 #define RCC_APB2ENR_USART1EN_Pos (4U)
14002 #define RCC_APB2ENR_USART1EN_Msk (0x1UL << RCC_APB2ENR_USART1EN_Pos) /*!< 0x00000010 */
14003 #define RCC_APB2ENR_USART1EN RCC_APB2ENR_USART1EN_Msk
14004 #define RCC_APB2ENR_USART6EN_Pos (5U)
14005 #define RCC_APB2ENR_USART6EN_Msk (0x1UL << RCC_APB2ENR_USART6EN_Pos) /*!< 0x00000020 */
14006 #define RCC_APB2ENR_USART6EN RCC_APB2ENR_USART6EN_Msk
14007 #define RCC_APB2ENR_UART9EN_Pos (6U)
14008 #define RCC_APB2ENR_UART9EN_Msk (0x1UL << RCC_APB2ENR_UART9EN_Pos) /*!< 0x00000040 */
14009 #define RCC_APB2ENR_UART9EN RCC_APB2ENR_UART9EN_Msk
14010 #define RCC_APB2ENR_USART10EN_Pos (7U)
14011 #define RCC_APB2ENR_USART10EN_Msk (0x1UL << RCC_APB2ENR_USART10EN_Pos) /*!< 0x00000080 */
14012 #define RCC_APB2ENR_USART10EN RCC_APB2ENR_USART10EN_Msk
14013 #define RCC_APB2ENR_SPI1EN_Pos (12U)
14014 #define RCC_APB2ENR_SPI1EN_Msk (0x1UL << RCC_APB2ENR_SPI1EN_Pos) /*!< 0x00001000 */
14015 #define RCC_APB2ENR_SPI1EN RCC_APB2ENR_SPI1EN_Msk
14016 #define RCC_APB2ENR_SPI4EN_Pos (13U)
14017 #define RCC_APB2ENR_SPI4EN_Msk (0x1UL << RCC_APB2ENR_SPI4EN_Pos) /*!< 0x00002000 */
14018 #define RCC_APB2ENR_SPI4EN RCC_APB2ENR_SPI4EN_Msk
14019 #define RCC_APB2ENR_TIM15EN_Pos (16U)
14020 #define RCC_APB2ENR_TIM15EN_Msk (0x1UL << RCC_APB2ENR_TIM15EN_Pos) /*!< 0x00010000 */
14021 #define RCC_APB2ENR_TIM15EN RCC_APB2ENR_TIM15EN_Msk
14022 #define RCC_APB2ENR_TIM16EN_Pos (17U)
14023 #define RCC_APB2ENR_TIM16EN_Msk (0x1UL << RCC_APB2ENR_TIM16EN_Pos) /*!< 0x00020000 */
14024 #define RCC_APB2ENR_TIM16EN RCC_APB2ENR_TIM16EN_Msk
14025 #define RCC_APB2ENR_TIM17EN_Pos (18U)
14026 #define RCC_APB2ENR_TIM17EN_Msk (0x1UL << RCC_APB2ENR_TIM17EN_Pos) /*!< 0x00040000 */
14027 #define RCC_APB2ENR_TIM17EN RCC_APB2ENR_TIM17EN_Msk
14028 #define RCC_APB2ENR_SPI5EN_Pos (20U)
14029 #define RCC_APB2ENR_SPI5EN_Msk (0x1UL << RCC_APB2ENR_SPI5EN_Pos) /*!< 0x00100000 */
14030 #define RCC_APB2ENR_SPI5EN RCC_APB2ENR_SPI5EN_Msk
14031 #define RCC_APB2ENR_SAI1EN_Pos (22U)
14032 #define RCC_APB2ENR_SAI1EN_Msk (0x1UL << RCC_APB2ENR_SAI1EN_Pos) /*!< 0x00400000 */
14033 #define RCC_APB2ENR_SAI1EN RCC_APB2ENR_SAI1EN_Msk
14034 #define RCC_APB2ENR_SAI2EN_Pos (23U)
14035 #define RCC_APB2ENR_SAI2EN_Msk (0x1UL << RCC_APB2ENR_SAI2EN_Pos) /*!< 0x00800000 */
14036 #define RCC_APB2ENR_SAI2EN RCC_APB2ENR_SAI2EN_Msk
14037 #define RCC_APB2ENR_DFSDM1EN_Pos (30U)
14038 #define RCC_APB2ENR_DFSDM1EN_Msk (0x1UL << RCC_APB2ENR_DFSDM1EN_Pos) /*!< 0x40000000 */
14039 #define RCC_APB2ENR_DFSDM1EN RCC_APB2ENR_DFSDM1EN_Msk
14040
14041 /******************** Bit definition for RCC_APB4ENR register ******************/
14042 #define RCC_APB4ENR_SYSCFGEN_Pos (1U)
14043 #define RCC_APB4ENR_SYSCFGEN_Msk (0x1UL << RCC_APB4ENR_SYSCFGEN_Pos) /*!< 0x00000002 */
14044 #define RCC_APB4ENR_SYSCFGEN RCC_APB4ENR_SYSCFGEN_Msk
14045 #define RCC_APB4ENR_LPUART1EN_Pos (3U)
14046 #define RCC_APB4ENR_LPUART1EN_Msk (0x1UL << RCC_APB4ENR_LPUART1EN_Pos) /*!< 0x00000008 */
14047 #define RCC_APB4ENR_LPUART1EN RCC_APB4ENR_LPUART1EN_Msk
14048 #define RCC_APB4ENR_SPI6EN_Pos (5U)
14049 #define RCC_APB4ENR_SPI6EN_Msk (0x1UL << RCC_APB4ENR_SPI6EN_Pos) /*!< 0x00000020 */
14050 #define RCC_APB4ENR_SPI6EN RCC_APB4ENR_SPI6EN_Msk
14051 #define RCC_APB4ENR_I2C4EN_Pos (7U)
14052 #define RCC_APB4ENR_I2C4EN_Msk (0x1UL << RCC_APB4ENR_I2C4EN_Pos) /*!< 0x00000080 */
14053 #define RCC_APB4ENR_I2C4EN RCC_APB4ENR_I2C4EN_Msk
14054 #define RCC_APB4ENR_LPTIM2EN_Pos (9U)
14055 #define RCC_APB4ENR_LPTIM2EN_Msk (0x1UL << RCC_APB4ENR_LPTIM2EN_Pos) /*!< 0x00000200 */
14056 #define RCC_APB4ENR_LPTIM2EN RCC_APB4ENR_LPTIM2EN_Msk
14057 #define RCC_APB4ENR_LPTIM3EN_Pos (10U)
14058 #define RCC_APB4ENR_LPTIM3EN_Msk (0x1UL << RCC_APB4ENR_LPTIM3EN_Pos) /*!< 0x00000400 */
14059 #define RCC_APB4ENR_LPTIM3EN RCC_APB4ENR_LPTIM3EN_Msk
14060 #define RCC_APB4ENR_DAC2EN_Pos (13U)
14061 #define RCC_APB4ENR_DAC2EN_Msk (0x1UL << RCC_APB4ENR_DAC2EN_Pos) /*!< 0x00002000 */
14062 #define RCC_APB4ENR_DAC2EN RCC_APB4ENR_DAC2EN_Msk
14063 #define RCC_APB4ENR_COMP12EN_Pos (14U)
14064 #define RCC_APB4ENR_COMP12EN_Msk (0x1UL << RCC_APB4ENR_COMP12EN_Pos) /*!< 0x00004000 */
14065 #define RCC_APB4ENR_COMP12EN RCC_APB4ENR_COMP12EN_Msk
14066 #define RCC_APB4ENR_VREFEN_Pos (15U)
14067 #define RCC_APB4ENR_VREFEN_Msk (0x1UL << RCC_APB4ENR_VREFEN_Pos) /*!< 0x00008000 */
14068 #define RCC_APB4ENR_VREFEN RCC_APB4ENR_VREFEN_Msk
14069 #define RCC_APB4ENR_RTCAPBEN_Pos (16U)
14070 #define RCC_APB4ENR_RTCAPBEN_Msk (0x1UL << RCC_APB4ENR_RTCAPBEN_Pos) /*!< 0x00010000 */
14071 #define RCC_APB4ENR_RTCAPBEN RCC_APB4ENR_RTCAPBEN_Msk
14072
14073 #define RCC_APB4ENR_DTSEN_Pos (26U)
14074 #define RCC_APB4ENR_DTSEN_Msk (0x1UL << RCC_APB4ENR_DTSEN_Pos) /*!< 0x04000000 */
14075 #define RCC_APB4ENR_DTSEN RCC_APB4ENR_DTSEN_Msk
14076 #define RCC_APB4ENR_DFSDM2EN_Pos (27U)
14077 #define RCC_APB4ENR_DFSDM2EN_Msk (0x1UL << RCC_APB4ENR_DFSDM2EN_Pos) /*!< 0x08000000 */
14078 #define RCC_APB4ENR_DFSDM2EN RCC_APB4ENR_DFSDM2EN_Msk
14079
14080 /******************** Bit definition for RCC_AHB3RSTR register ***************/
14081 #define RCC_AHB3RSTR_MDMARST_Pos (0U)
14082 #define RCC_AHB3RSTR_MDMARST_Msk (0x1UL << RCC_AHB3RSTR_MDMARST_Pos) /*!< 0x00000001 */
14083 #define RCC_AHB3RSTR_MDMARST RCC_AHB3RSTR_MDMARST_Msk
14084 #define RCC_AHB3RSTR_DMA2DRST_Pos (4U)
14085 #define RCC_AHB3RSTR_DMA2DRST_Msk (0x1UL << RCC_AHB3RSTR_DMA2DRST_Pos) /*!< 0x00000010 */
14086 #define RCC_AHB3RSTR_DMA2DRST RCC_AHB3RSTR_DMA2DRST_Msk
14087 #define RCC_AHB3RSTR_JPGDECRST_Pos (5U)
14088 #define RCC_AHB3RSTR_JPGDECRST_Msk (0x1UL << RCC_AHB3RSTR_JPGDECRST_Pos) /*!< 0x00000020 */
14089 #define RCC_AHB3RSTR_JPGDECRST RCC_AHB3RSTR_JPGDECRST_Msk
14090 #define RCC_AHB3RSTR_FMCRST_Pos (12U)
14091 #define RCC_AHB3RSTR_FMCRST_Msk (0x1UL << RCC_AHB3RSTR_FMCRST_Pos) /*!< 0x00001000 */
14092 #define RCC_AHB3RSTR_FMCRST RCC_AHB3RSTR_FMCRST_Msk
14093 #define RCC_AHB3RSTR_OSPI1RST_Pos (14U)
14094 #define RCC_AHB3RSTR_OSPI1RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI1RST_Pos) /*!< 0x00004000 */
14095 #define RCC_AHB3RSTR_OSPI1RST RCC_AHB3RSTR_OSPI1RST_Msk
14096 #define RCC_AHB3RSTR_SDMMC1RST_Pos (16U)
14097 #define RCC_AHB3RSTR_SDMMC1RST_Msk (0x1UL << RCC_AHB3RSTR_SDMMC1RST_Pos) /*!< 0x00010000 */
14098 #define RCC_AHB3RSTR_SDMMC1RST RCC_AHB3RSTR_SDMMC1RST_Msk
14099 #define RCC_AHB3RSTR_OSPI2RST_Pos (19U)
14100 #define RCC_AHB3RSTR_OSPI2RST_Msk (0x1UL << RCC_AHB3RSTR_OSPI2RST_Pos) /*!< 0x00008000 */
14101 #define RCC_AHB3RSTR_OSPI2RST RCC_AHB3RSTR_OSPI2RST_Msk
14102 #define RCC_AHB3RSTR_IOMNGRRST_Pos (21U)
14103 #define RCC_AHB3RSTR_IOMNGRRST_Msk (0x1UL << RCC_AHB3RSTR_IOMNGRRST_Pos) /*!< 0x00020000 */
14104 #define RCC_AHB3RSTR_IOMNGRRST RCC_AHB3RSTR_IOMNGRRST_Msk
14105 #define RCC_AHB3RSTR_OTFDEC1RST_Pos (22U)
14106 #define RCC_AHB3RSTR_OTFDEC1RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC1RST_Pos) /*!< 0x00040000 */
14107 #define RCC_AHB3RSTR_OTFDEC1RST RCC_AHB3RSTR_OTFDEC1RST_Msk
14108 #define RCC_AHB3RSTR_OTFDEC2RST_Pos (23U)
14109 #define RCC_AHB3RSTR_OTFDEC2RST_Msk (0x1UL << RCC_AHB3RSTR_OTFDEC2RST_Pos) /*!< 0x00080000 */
14110 #define RCC_AHB3RSTR_OTFDEC2RST RCC_AHB3RSTR_OTFDEC2RST_Msk
14111 #define RCC_AHB3RSTR_GFXMMURST_Pos (24U)
14112 #define RCC_AHB3RSTR_GFXMMURST_Msk (0x1UL << RCC_AHB3RSTR_GFXMMURST_Pos) /*!< 0x00100000 */
14113 #define RCC_AHB3RSTR_GFXMMURST RCC_AHB3RSTR_GFXMMURST_Msk
14114
14115
14116 /******************** Bit definition for RCC_AHB1RSTR register ***************/
14117 #define RCC_AHB1RSTR_DMA1RST_Pos (0U)
14118 #define RCC_AHB1RSTR_DMA1RST_Msk (0x1UL << RCC_AHB1RSTR_DMA1RST_Pos) /*!< 0x00000001 */
14119 #define RCC_AHB1RSTR_DMA1RST RCC_AHB1RSTR_DMA1RST_Msk
14120 #define RCC_AHB1RSTR_DMA2RST_Pos (1U)
14121 #define RCC_AHB1RSTR_DMA2RST_Msk (0x1UL << RCC_AHB1RSTR_DMA2RST_Pos) /*!< 0x00000002 */
14122 #define RCC_AHB1RSTR_DMA2RST RCC_AHB1RSTR_DMA2RST_Msk
14123 #define RCC_AHB1RSTR_ADC12RST_Pos (5U)
14124 #define RCC_AHB1RSTR_ADC12RST_Msk (0x1UL << RCC_AHB1RSTR_ADC12RST_Pos) /*!< 0x00000020 */
14125 #define RCC_AHB1RSTR_ADC12RST RCC_AHB1RSTR_ADC12RST_Msk
14126 #define RCC_AHB1RSTR_CRCRST_Pos (9U)
14127 #define RCC_AHB1RSTR_CRCRST_Msk (0x1UL << RCC_AHB1RSTR_CRCRST_Pos) /*!< 0x00000200 */
14128 #define RCC_AHB1RSTR_CRCRST RCC_AHB1RSTR_CRCRST_Msk
14129 #define RCC_AHB1RSTR_USB1OTGHSRST_Pos (25U)
14130 #define RCC_AHB1RSTR_USB1OTGHSRST_Msk (0x1UL << RCC_AHB1RSTR_USB1OTGHSRST_Pos) /*!< 0x02000000 */
14131 #define RCC_AHB1RSTR_USB1OTGHSRST RCC_AHB1RSTR_USB1OTGHSRST_Msk
14132
14133 /******************** Bit definition for RCC_AHB2RSTR register ***************/
14134 #define RCC_AHB2RSTR_DCMI_PSSIRST_Pos (0U)
14135 #define RCC_AHB2RSTR_DCMI_PSSIRST_Msk (0x1UL << RCC_AHB2RSTR_DCMI_PSSIRST_Pos) /*!< 0x00000001 */
14136 #define RCC_AHB2RSTR_DCMI_PSSIRST RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14137 #define RCC_AHB2RSTR_HSEMRST_Pos (2U)
14138 #define RCC_AHB2RSTR_HSEMRST_Msk (0x1UL << RCC_AHB2RSTR_HSEMRST_Pos) /*!< 0x00000004 */
14139 #define RCC_AHB2RSTR_HSEMRST RCC_AHB2RSTR_HSEMRST_Msk
14140 #define RCC_AHB2RSTR_CRYPRST_Pos (4U)
14141 #define RCC_AHB2RSTR_CRYPRST_Msk (0x1UL << RCC_AHB2RSTR_CRYPRST_Pos) /*!< 0x00000010 */
14142 #define RCC_AHB2RSTR_CRYPRST RCC_AHB2RSTR_CRYPRST_Msk
14143 #define RCC_AHB2RSTR_HASHRST_Pos (5U)
14144 #define RCC_AHB2RSTR_HASHRST_Msk (0x1UL << RCC_AHB2RSTR_HASHRST_Pos) /*!< 0x00000020 */
14145 #define RCC_AHB2RSTR_HASHRST RCC_AHB2RSTR_HASHRST_Msk
14146 #define RCC_AHB2RSTR_RNGRST_Pos (6U)
14147 #define RCC_AHB2RSTR_RNGRST_Msk (0x1UL << RCC_AHB2RSTR_RNGRST_Pos) /*!< 0x00000040 */
14148 #define RCC_AHB2RSTR_RNGRST RCC_AHB2RSTR_RNGRST_Msk
14149 #define RCC_AHB2RSTR_SDMMC2RST_Pos (9U)
14150 #define RCC_AHB2RSTR_SDMMC2RST_Msk (0x1UL << RCC_AHB2RSTR_SDMMC2RST_Pos) /*!< 0x00000200 */
14151 #define RCC_AHB2RSTR_SDMMC2RST RCC_AHB2RSTR_SDMMC2RST_Msk
14152 #define RCC_AHB2RSTR_BDMA1RST_Pos (11U)
14153 #define RCC_AHB2RSTR_BDMA1RST_Msk (0x1UL << RCC_AHB2RSTR_BDMA1RST_Pos) /*!< 0x00000200 */
14154 #define RCC_AHB2RSTR_BDMA1RST RCC_AHB2RSTR_BDMA1RST_Msk
14155
14156 /* Legacy define */
14157 #define RCC_AHB2RSTR_DCMIRST_Pos RCC_AHB2RSTR_DCMI_PSSIRST_Pos
14158 #define RCC_AHB2RSTR_DCMIRST_Msk RCC_AHB2RSTR_DCMI_PSSIRST_Msk
14159 #define RCC_AHB2RSTR_DCMIRST RCC_AHB2RSTR_DCMI_PSSIRST
14160 /******************** Bit definition for RCC_AHB4RSTR register ******************/
14161 #define RCC_AHB4RSTR_GPIOARST_Pos (0U)
14162 #define RCC_AHB4RSTR_GPIOARST_Msk (0x1UL << RCC_AHB4RSTR_GPIOARST_Pos) /*!< 0x00000001 */
14163 #define RCC_AHB4RSTR_GPIOARST RCC_AHB4RSTR_GPIOARST_Msk
14164 #define RCC_AHB4RSTR_GPIOBRST_Pos (1U)
14165 #define RCC_AHB4RSTR_GPIOBRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOBRST_Pos) /*!< 0x00000002 */
14166 #define RCC_AHB4RSTR_GPIOBRST RCC_AHB4RSTR_GPIOBRST_Msk
14167 #define RCC_AHB4RSTR_GPIOCRST_Pos (2U)
14168 #define RCC_AHB4RSTR_GPIOCRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOCRST_Pos) /*!< 0x00000004 */
14169 #define RCC_AHB4RSTR_GPIOCRST RCC_AHB4RSTR_GPIOCRST_Msk
14170 #define RCC_AHB4RSTR_GPIODRST_Pos (3U)
14171 #define RCC_AHB4RSTR_GPIODRST_Msk (0x1UL << RCC_AHB4RSTR_GPIODRST_Pos) /*!< 0x00000008 */
14172 #define RCC_AHB4RSTR_GPIODRST RCC_AHB4RSTR_GPIODRST_Msk
14173 #define RCC_AHB4RSTR_GPIOERST_Pos (4U)
14174 #define RCC_AHB4RSTR_GPIOERST_Msk (0x1UL << RCC_AHB4RSTR_GPIOERST_Pos) /*!< 0x00000010 */
14175 #define RCC_AHB4RSTR_GPIOERST RCC_AHB4RSTR_GPIOERST_Msk
14176 #define RCC_AHB4RSTR_GPIOFRST_Pos (5U)
14177 #define RCC_AHB4RSTR_GPIOFRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOFRST_Pos) /*!< 0x00000020 */
14178 #define RCC_AHB4RSTR_GPIOFRST RCC_AHB4RSTR_GPIOFRST_Msk
14179 #define RCC_AHB4RSTR_GPIOGRST_Pos (6U)
14180 #define RCC_AHB4RSTR_GPIOGRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOGRST_Pos) /*!< 0x00000040 */
14181 #define RCC_AHB4RSTR_GPIOGRST RCC_AHB4RSTR_GPIOGRST_Msk
14182 #define RCC_AHB4RSTR_GPIOHRST_Pos (7U)
14183 #define RCC_AHB4RSTR_GPIOHRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOHRST_Pos) /*!< 0x00000080 */
14184 #define RCC_AHB4RSTR_GPIOHRST RCC_AHB4RSTR_GPIOHRST_Msk
14185 #define RCC_AHB4RSTR_GPIOIRST_Pos (8U)
14186 #define RCC_AHB4RSTR_GPIOIRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOIRST_Pos) /*!< 0x00000100 */
14187 #define RCC_AHB4RSTR_GPIOIRST RCC_AHB4RSTR_GPIOIRST_Msk
14188 #define RCC_AHB4RSTR_GPIOJRST_Pos (9U)
14189 #define RCC_AHB4RSTR_GPIOJRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOJRST_Pos) /*!< 0x00000200 */
14190 #define RCC_AHB4RSTR_GPIOJRST RCC_AHB4RSTR_GPIOJRST_Msk
14191 #define RCC_AHB4RSTR_GPIOKRST_Pos (10U)
14192 #define RCC_AHB4RSTR_GPIOKRST_Msk (0x1UL << RCC_AHB4RSTR_GPIOKRST_Pos) /*!< 0x00000400 */
14193 #define RCC_AHB4RSTR_GPIOKRST RCC_AHB4RSTR_GPIOKRST_Msk
14194 #define RCC_AHB4RSTR_BDMA2RST_Pos (21U)
14195 #define RCC_AHB4RSTR_BDMA2RST_Msk (0x1UL << RCC_AHB4RSTR_BDMA2RST_Pos) /*!< 0x00200000 */
14196 #define RCC_AHB4RSTR_BDMA2RST RCC_AHB4RSTR_BDMA2RST_Msk
14197
14198
14199 /******************** Bit definition for RCC_APB3RSTR register ******************/
14200 #define RCC_APB3RSTR_LTDCRST_Pos (3U)
14201 #define RCC_APB3RSTR_LTDCRST_Msk (0x1UL << RCC_APB3RSTR_LTDCRST_Pos) /*!< 0x00000008 */
14202 #define RCC_APB3RSTR_LTDCRST RCC_APB3RSTR_LTDCRST_Msk
14203
14204 /******************** Bit definition for RCC_APB1LRSTR register ******************/
14205
14206 #define RCC_APB1LRSTR_TIM2RST_Pos (0U)
14207 #define RCC_APB1LRSTR_TIM2RST_Msk (0x1UL << RCC_APB1LRSTR_TIM2RST_Pos) /*!< 0x00000001 */
14208 #define RCC_APB1LRSTR_TIM2RST RCC_APB1LRSTR_TIM2RST_Msk
14209 #define RCC_APB1LRSTR_TIM3RST_Pos (1U)
14210 #define RCC_APB1LRSTR_TIM3RST_Msk (0x1UL << RCC_APB1LRSTR_TIM3RST_Pos) /*!< 0x00000002 */
14211 #define RCC_APB1LRSTR_TIM3RST RCC_APB1LRSTR_TIM3RST_Msk
14212 #define RCC_APB1LRSTR_TIM4RST_Pos (2U)
14213 #define RCC_APB1LRSTR_TIM4RST_Msk (0x1UL << RCC_APB1LRSTR_TIM4RST_Pos) /*!< 0x00000004 */
14214 #define RCC_APB1LRSTR_TIM4RST RCC_APB1LRSTR_TIM4RST_Msk
14215 #define RCC_APB1LRSTR_TIM5RST_Pos (3U)
14216 #define RCC_APB1LRSTR_TIM5RST_Msk (0x1UL << RCC_APB1LRSTR_TIM5RST_Pos) /*!< 0x00000008 */
14217 #define RCC_APB1LRSTR_TIM5RST RCC_APB1LRSTR_TIM5RST_Msk
14218 #define RCC_APB1LRSTR_TIM6RST_Pos (4U)
14219 #define RCC_APB1LRSTR_TIM6RST_Msk (0x1UL << RCC_APB1LRSTR_TIM6RST_Pos) /*!< 0x00000010 */
14220 #define RCC_APB1LRSTR_TIM6RST RCC_APB1LRSTR_TIM6RST_Msk
14221 #define RCC_APB1LRSTR_TIM7RST_Pos (5U)
14222 #define RCC_APB1LRSTR_TIM7RST_Msk (0x1UL << RCC_APB1LRSTR_TIM7RST_Pos) /*!< 0x00000020 */
14223 #define RCC_APB1LRSTR_TIM7RST RCC_APB1LRSTR_TIM7RST_Msk
14224 #define RCC_APB1LRSTR_TIM12RST_Pos (6U)
14225 #define RCC_APB1LRSTR_TIM12RST_Msk (0x1UL << RCC_APB1LRSTR_TIM12RST_Pos) /*!< 0x00000040 */
14226 #define RCC_APB1LRSTR_TIM12RST RCC_APB1LRSTR_TIM12RST_Msk
14227 #define RCC_APB1LRSTR_TIM13RST_Pos (7U)
14228 #define RCC_APB1LRSTR_TIM13RST_Msk (0x1UL << RCC_APB1LRSTR_TIM13RST_Pos) /*!< 0x00000080 */
14229 #define RCC_APB1LRSTR_TIM13RST RCC_APB1LRSTR_TIM13RST_Msk
14230 #define RCC_APB1LRSTR_TIM14RST_Pos (8U)
14231 #define RCC_APB1LRSTR_TIM14RST_Msk (0x1UL << RCC_APB1LRSTR_TIM14RST_Pos) /*!< 0x00000100 */
14232 #define RCC_APB1LRSTR_TIM14RST RCC_APB1LRSTR_TIM14RST_Msk
14233 #define RCC_APB1LRSTR_LPTIM1RST_Pos (9U)
14234 #define RCC_APB1LRSTR_LPTIM1RST_Msk (0x1UL << RCC_APB1LRSTR_LPTIM1RST_Pos) /*!< 0x00000200 */
14235 #define RCC_APB1LRSTR_LPTIM1RST RCC_APB1LRSTR_LPTIM1RST_Msk
14236 #define RCC_APB1LRSTR_SPI2RST_Pos (14U)
14237 #define RCC_APB1LRSTR_SPI2RST_Msk (0x1UL << RCC_APB1LRSTR_SPI2RST_Pos) /*!< 0x00004000 */
14238 #define RCC_APB1LRSTR_SPI2RST RCC_APB1LRSTR_SPI2RST_Msk
14239 #define RCC_APB1LRSTR_SPI3RST_Pos (15U)
14240 #define RCC_APB1LRSTR_SPI3RST_Msk (0x1UL << RCC_APB1LRSTR_SPI3RST_Pos) /*!< 0x00008000 */
14241 #define RCC_APB1LRSTR_SPI3RST RCC_APB1LRSTR_SPI3RST_Msk
14242 #define RCC_APB1LRSTR_SPDIFRXRST_Pos (16U)
14243 #define RCC_APB1LRSTR_SPDIFRXRST_Msk (0x1UL << RCC_APB1LRSTR_SPDIFRXRST_Pos) /*!< 0x00010000 */
14244 #define RCC_APB1LRSTR_SPDIFRXRST RCC_APB1LRSTR_SPDIFRXRST_Msk
14245 #define RCC_APB1LRSTR_USART2RST_Pos (17U)
14246 #define RCC_APB1LRSTR_USART2RST_Msk (0x1UL << RCC_APB1LRSTR_USART2RST_Pos) /*!< 0x00020000 */
14247 #define RCC_APB1LRSTR_USART2RST RCC_APB1LRSTR_USART2RST_Msk
14248 #define RCC_APB1LRSTR_USART3RST_Pos (18U)
14249 #define RCC_APB1LRSTR_USART3RST_Msk (0x1UL << RCC_APB1LRSTR_USART3RST_Pos) /*!< 0x00040000 */
14250 #define RCC_APB1LRSTR_USART3RST RCC_APB1LRSTR_USART3RST_Msk
14251 #define RCC_APB1LRSTR_UART4RST_Pos (19U)
14252 #define RCC_APB1LRSTR_UART4RST_Msk (0x1UL << RCC_APB1LRSTR_UART4RST_Pos) /*!< 0x00080000 */
14253 #define RCC_APB1LRSTR_UART4RST RCC_APB1LRSTR_UART4RST_Msk
14254 #define RCC_APB1LRSTR_UART5RST_Pos (20U)
14255 #define RCC_APB1LRSTR_UART5RST_Msk (0x1UL << RCC_APB1LRSTR_UART5RST_Pos) /*!< 0x00100000 */
14256 #define RCC_APB1LRSTR_UART5RST RCC_APB1LRSTR_UART5RST_Msk
14257 #define RCC_APB1LRSTR_I2C1RST_Pos (21U)
14258 #define RCC_APB1LRSTR_I2C1RST_Msk (0x1UL << RCC_APB1LRSTR_I2C1RST_Pos) /*!< 0x00200000 */
14259 #define RCC_APB1LRSTR_I2C1RST RCC_APB1LRSTR_I2C1RST_Msk
14260 #define RCC_APB1LRSTR_I2C2RST_Pos (22U)
14261 #define RCC_APB1LRSTR_I2C2RST_Msk (0x1UL << RCC_APB1LRSTR_I2C2RST_Pos) /*!< 0x00400000 */
14262 #define RCC_APB1LRSTR_I2C2RST RCC_APB1LRSTR_I2C2RST_Msk
14263 #define RCC_APB1LRSTR_I2C3RST_Pos (23U)
14264 #define RCC_APB1LRSTR_I2C3RST_Msk (0x1UL << RCC_APB1LRSTR_I2C3RST_Pos) /*!< 0x00800000 */
14265 #define RCC_APB1LRSTR_I2C3RST RCC_APB1LRSTR_I2C3RST_Msk
14266 #define RCC_APB1LRSTR_CECRST_Pos (27U)
14267 #define RCC_APB1LRSTR_CECRST_Msk (0x1UL << RCC_APB1LRSTR_CECRST_Pos) /*!< 0x08000000 */
14268 #define RCC_APB1LRSTR_CECRST RCC_APB1LRSTR_CECRST_Msk
14269 #define RCC_APB1LRSTR_DAC12RST_Pos (29U)
14270 #define RCC_APB1LRSTR_DAC12RST_Msk (0x1UL << RCC_APB1LRSTR_DAC12RST_Pos) /*!< 0x20000000 */
14271 #define RCC_APB1LRSTR_DAC12RST RCC_APB1LRSTR_DAC12RST_Msk
14272 #define RCC_APB1LRSTR_UART7RST_Pos (30U)
14273 #define RCC_APB1LRSTR_UART7RST_Msk (0x1UL << RCC_APB1LRSTR_UART7RST_Pos) /*!< 0x40000000 */
14274 #define RCC_APB1LRSTR_UART7RST RCC_APB1LRSTR_UART7RST_Msk
14275 #define RCC_APB1LRSTR_UART8RST_Pos (31U)
14276 #define RCC_APB1LRSTR_UART8RST_Msk (0x1UL << RCC_APB1LRSTR_UART8RST_Pos) /*!< 0x80000000 */
14277 #define RCC_APB1LRSTR_UART8RST RCC_APB1LRSTR_UART8RST_Msk
14278
14279 /* Legacy define */
14280 #define RCC_APB1LRSTR_HDMICECRST_Pos RCC_APB1LRSTR_CECRST_Pos
14281 #define RCC_APB1LRSTR_HDMICECRST_Msk RCC_APB1LRSTR_CECRST_Msk
14282 #define RCC_APB1LRSTR_HDMICECRST RCC_APB1LRSTR_CECRST
14283 /******************** Bit definition for RCC_APB1HRSTR register ******************/
14284 #define RCC_APB1HRSTR_CRSRST_Pos (1U)
14285 #define RCC_APB1HRSTR_CRSRST_Msk (0x1UL << RCC_APB1HRSTR_CRSRST_Pos) /*!< 0x00000002 */
14286 #define RCC_APB1HRSTR_CRSRST RCC_APB1HRSTR_CRSRST_Msk
14287 #define RCC_APB1HRSTR_SWPMIRST_Pos (2U)
14288 #define RCC_APB1HRSTR_SWPMIRST_Msk (0x1UL << RCC_APB1HRSTR_SWPMIRST_Pos) /*!< 0x00000004 */
14289 #define RCC_APB1HRSTR_SWPMIRST RCC_APB1HRSTR_SWPMIRST_Msk
14290 #define RCC_APB1HRSTR_OPAMPRST_Pos (4U)
14291 #define RCC_APB1HRSTR_OPAMPRST_Msk (0x1UL << RCC_APB1HRSTR_OPAMPRST_Pos) /*!< 0x00000010 */
14292 #define RCC_APB1HRSTR_OPAMPRST RCC_APB1HRSTR_OPAMPRST_Msk
14293 #define RCC_APB1HRSTR_MDIOSRST_Pos (5U)
14294 #define RCC_APB1HRSTR_MDIOSRST_Msk (0x1UL << RCC_APB1HRSTR_MDIOSRST_Pos) /*!< 0x00000020 */
14295 #define RCC_APB1HRSTR_MDIOSRST RCC_APB1HRSTR_MDIOSRST_Msk
14296 #define RCC_APB1HRSTR_FDCANRST_Pos (8U)
14297 #define RCC_APB1HRSTR_FDCANRST_Msk (0x1UL << RCC_APB1HRSTR_FDCANRST_Pos) /*!< 0x00000100 */
14298 #define RCC_APB1HRSTR_FDCANRST RCC_APB1HRSTR_FDCANRST_Msk
14299
14300 /******************** Bit definition for RCC_APB2RSTR register ******************/
14301 #define RCC_APB2RSTR_TIM1RST_Pos (0U)
14302 #define RCC_APB2RSTR_TIM1RST_Msk (0x1UL << RCC_APB2RSTR_TIM1RST_Pos) /*!< 0x00000001 */
14303 #define RCC_APB2RSTR_TIM1RST RCC_APB2RSTR_TIM1RST_Msk
14304 #define RCC_APB2RSTR_TIM8RST_Pos (1U)
14305 #define RCC_APB2RSTR_TIM8RST_Msk (0x1UL << RCC_APB2RSTR_TIM8RST_Pos) /*!< 0x00000002 */
14306 #define RCC_APB2RSTR_TIM8RST RCC_APB2RSTR_TIM8RST_Msk
14307 #define RCC_APB2RSTR_USART1RST_Pos (4U)
14308 #define RCC_APB2RSTR_USART1RST_Msk (0x1UL << RCC_APB2RSTR_USART1RST_Pos) /*!< 0x00000010 */
14309 #define RCC_APB2RSTR_USART1RST RCC_APB2RSTR_USART1RST_Msk
14310 #define RCC_APB2RSTR_USART6RST_Pos (5U)
14311 #define RCC_APB2RSTR_USART6RST_Msk (0x1UL << RCC_APB2RSTR_USART6RST_Pos) /*!< 0x00000020 */
14312 #define RCC_APB2RSTR_USART6RST RCC_APB2RSTR_USART6RST_Msk
14313 #define RCC_APB2RSTR_UART9RST_Pos (6U)
14314 #define RCC_APB2RSTR_UART9RST_Msk (0x1UL << RCC_APB2RSTR_UART9RST_Pos) /*!< 0x00000040 */
14315 #define RCC_APB2RSTR_UART9RST RCC_APB2RSTR_UART9RST_Msk
14316 #define RCC_APB2RSTR_USART10RST_Pos (7U)
14317 #define RCC_APB2RSTR_USART10RST_Msk (0x1UL << RCC_APB2RSTR_USART10RST_Pos) /*!< 0x00000080 */
14318 #define RCC_APB2RSTR_USART10RST RCC_APB2RSTR_USART10RST_Msk
14319 #define RCC_APB2RSTR_SPI1RST_Pos (12U)
14320 #define RCC_APB2RSTR_SPI1RST_Msk (0x1UL << RCC_APB2RSTR_SPI1RST_Pos) /*!< 0x00001000 */
14321 #define RCC_APB2RSTR_SPI1RST RCC_APB2RSTR_SPI1RST_Msk
14322 #define RCC_APB2RSTR_SPI4RST_Pos (13U)
14323 #define RCC_APB2RSTR_SPI4RST_Msk (0x1UL << RCC_APB2RSTR_SPI4RST_Pos) /*!< 0x00002000 */
14324 #define RCC_APB2RSTR_SPI4RST RCC_APB2RSTR_SPI4RST_Msk
14325 #define RCC_APB2RSTR_TIM15RST_Pos (16U)
14326 #define RCC_APB2RSTR_TIM15RST_Msk (0x1UL << RCC_APB2RSTR_TIM15RST_Pos) /*!< 0x00010000 */
14327 #define RCC_APB2RSTR_TIM15RST RCC_APB2RSTR_TIM15RST_Msk
14328 #define RCC_APB2RSTR_TIM16RST_Pos (17U)
14329 #define RCC_APB2RSTR_TIM16RST_Msk (0x1UL << RCC_APB2RSTR_TIM16RST_Pos) /*!< 0x00020000 */
14330 #define RCC_APB2RSTR_TIM16RST RCC_APB2RSTR_TIM16RST_Msk
14331 #define RCC_APB2RSTR_TIM17RST_Pos (18U)
14332 #define RCC_APB2RSTR_TIM17RST_Msk (0x1UL << RCC_APB2RSTR_TIM17RST_Pos) /*!< 0x00040000 */
14333 #define RCC_APB2RSTR_TIM17RST RCC_APB2RSTR_TIM17RST_Msk
14334 #define RCC_APB2RSTR_SPI5RST_Pos (20U)
14335 #define RCC_APB2RSTR_SPI5RST_Msk (0x1UL << RCC_APB2RSTR_SPI5RST_Pos) /*!< 0x00100000 */
14336 #define RCC_APB2RSTR_SPI5RST RCC_APB2RSTR_SPI5RST_Msk
14337 #define RCC_APB2RSTR_SAI1RST_Pos (22U)
14338 #define RCC_APB2RSTR_SAI1RST_Msk (0x1UL << RCC_APB2RSTR_SAI1RST_Pos) /*!< 0x00400000 */
14339 #define RCC_APB2RSTR_SAI1RST RCC_APB2RSTR_SAI1RST_Msk
14340 #define RCC_APB2RSTR_SAI2RST_Pos (23U)
14341 #define RCC_APB2RSTR_SAI2RST_Msk (0x1UL << RCC_APB2RSTR_SAI2RST_Pos) /*!< 0x00800000 */
14342 #define RCC_APB2RSTR_SAI2RST RCC_APB2RSTR_SAI2RST_Msk
14343 #define RCC_APB2RSTR_DFSDM1RST_Pos (30U)
14344 #define RCC_APB2RSTR_DFSDM1RST_Msk (0x1UL << RCC_APB2RSTR_DFSDM1RST_Pos) /*!< 0x10000000 */
14345 #define RCC_APB2RSTR_DFSDM1RST RCC_APB2RSTR_DFSDM1RST_Msk
14346
14347 /******************** Bit definition for RCC_APB4RSTR register ******************/
14348 #define RCC_APB4RSTR_SYSCFGRST_Pos (1U)
14349 #define RCC_APB4RSTR_SYSCFGRST_Msk (0x1UL << RCC_APB4RSTR_SYSCFGRST_Pos) /*!< 0x00000002 */
14350 #define RCC_APB4RSTR_SYSCFGRST RCC_APB4RSTR_SYSCFGRST_Msk
14351 #define RCC_APB4RSTR_LPUART1RST_Pos (3U)
14352 #define RCC_APB4RSTR_LPUART1RST_Msk (0x1UL << RCC_APB4RSTR_LPUART1RST_Pos) /*!< 0x00000008 */
14353 #define RCC_APB4RSTR_LPUART1RST RCC_APB4RSTR_LPUART1RST_Msk
14354 #define RCC_APB4RSTR_SPI6RST_Pos (5U)
14355 #define RCC_APB4RSTR_SPI6RST_Msk (0x1UL << RCC_APB4RSTR_SPI6RST_Pos) /*!< 0x00000020 */
14356 #define RCC_APB4RSTR_SPI6RST RCC_APB4RSTR_SPI6RST_Msk
14357 #define RCC_APB4RSTR_I2C4RST_Pos (7U)
14358 #define RCC_APB4RSTR_I2C4RST_Msk (0x1UL << RCC_APB4RSTR_I2C4RST_Pos) /*!< 0x00000080 */
14359 #define RCC_APB4RSTR_I2C4RST RCC_APB4RSTR_I2C4RST_Msk
14360 #define RCC_APB4RSTR_LPTIM2RST_Pos (9U)
14361 #define RCC_APB4RSTR_LPTIM2RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM2RST_Pos) /*!< 0x00000200 */
14362 #define RCC_APB4RSTR_LPTIM2RST RCC_APB4RSTR_LPTIM2RST_Msk
14363 #define RCC_APB4RSTR_LPTIM3RST_Pos (10U)
14364 #define RCC_APB4RSTR_LPTIM3RST_Msk (0x1UL << RCC_APB4RSTR_LPTIM3RST_Pos) /*!< 0x00000400 */
14365 #define RCC_APB4RSTR_LPTIM3RST RCC_APB4RSTR_LPTIM3RST_Msk
14366 #define RCC_APB4RSTR_DAC2RST_Pos (13U)
14367 #define RCC_APB4RSTR_DAC2RST_Msk (0x1UL << RCC_APB4RSTR_DAC2RST_Pos) /*!< 0x00001000 */
14368 #define RCC_APB4RSTR_DAC2RST RCC_APB4RSTR_DAC2RST_Msk
14369 #define RCC_APB4RSTR_COMP12RST_Pos (14U)
14370 #define RCC_APB4RSTR_COMP12RST_Msk (0x1UL << RCC_APB4RSTR_COMP12RST_Pos) /*!< 0x00004000 */
14371 #define RCC_APB4RSTR_COMP12RST RCC_APB4RSTR_COMP12RST_Msk
14372 #define RCC_APB4RSTR_VREFRST_Pos (15U)
14373 #define RCC_APB4RSTR_VREFRST_Msk (0x1UL << RCC_APB4RSTR_VREFRST_Pos) /*!< 0x00008000 */
14374 #define RCC_APB4RSTR_VREFRST RCC_APB4RSTR_VREFRST_Msk
14375
14376 #define RCC_APB4RSTR_DTSRST_Pos (26U)
14377 #define RCC_APB4RSTR_DTSRST_Msk (0x1UL << RCC_APB4RSTR_DTSRST_Pos) /*!< 0x04000000 */
14378 #define RCC_APB4RSTR_DTSRST RCC_APB4RSTR_DTSRST_Msk
14379 #define RCC_APB4RSTR_DFSDM2RST_Pos (27U)
14380 #define RCC_APB4RSTR_DFSDM2RST_Msk (0x1UL << RCC_APB4RSTR_DFSDM2RST_Pos) /*!< 0x08000000 */
14381 #define RCC_APB4RSTR_DFSDM2RST RCC_APB4RSTR_DFSDM2RST_Msk
14382
14383
14384 /******************** Bit definition for RCC_SRDAMR register ********************/
14385 #define RCC_SRDAMR_BDMA2AMEN_Pos (0U)
14386 #define RCC_SRDAMR_BDMA2AMEN_Msk (0x1UL << RCC_SRDAMR_BDMA2AMEN_Pos) /*!< 0x00000001 */
14387 #define RCC_SRDAMR_BDMA2AMEN RCC_SRDAMR_BDMA2AMEN_Msk
14388 #define RCC_SRDAMR_GPIOAMEN_Pos (1U)
14389 #define RCC_SRDAMR_GPIOAMEN_Msk (0x1UL << RCC_SRDAMR_GPIOAMEN_Pos) /*!< 0x00000001 */
14390 #define RCC_SRDAMR_GPIOAMEN RCC_SRDAMR_GPIOAMEN_Msk
14391 #define RCC_SRDAMR_LPUART1AMEN_Pos (3U)
14392 #define RCC_SRDAMR_LPUART1AMEN_Msk (0x1UL << RCC_SRDAMR_LPUART1AMEN_Pos) /*!< 0x00000008 */
14393 #define RCC_SRDAMR_LPUART1AMEN RCC_SRDAMR_LPUART1AMEN_Msk
14394 #define RCC_SRDAMR_SPI6AMEN_Pos (5U)
14395 #define RCC_SRDAMR_SPI6AMEN_Msk (0x1UL << RCC_SRDAMR_SPI6AMEN_Pos) /*!< 0x00000020 */
14396 #define RCC_SRDAMR_SPI6AMEN RCC_SRDAMR_SPI6AMEN_Msk
14397 #define RCC_SRDAMR_I2C4AMEN_Pos (7U)
14398 #define RCC_SRDAMR_I2C4AMEN_Msk (0x1UL << RCC_SRDAMR_I2C4AMEN_Pos) /*!< 0x00000080 */
14399 #define RCC_SRDAMR_I2C4AMEN RCC_SRDAMR_I2C4AMEN_Msk
14400 #define RCC_SRDAMR_LPTIM2AMEN_Pos (9U)
14401 #define RCC_SRDAMR_LPTIM2AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM2AMEN_Pos) /*!< 0x00000200 */
14402 #define RCC_SRDAMR_LPTIM2AMEN RCC_SRDAMR_LPTIM2AMEN_Msk
14403 #define RCC_SRDAMR_LPTIM3AMEN_Pos (10U)
14404 #define RCC_SRDAMR_LPTIM3AMEN_Msk (0x1UL << RCC_SRDAMR_LPTIM3AMEN_Pos) /*!< 0x00000400 */
14405 #define RCC_SRDAMR_LPTIM3AMEN RCC_SRDAMR_LPTIM3AMEN_Msk
14406 #define RCC_SRDAMR_DAC2AMEN_Pos (13U)
14407 #define RCC_SRDAMR_DAC2AMEN_Msk (0x1UL << RCC_SRDAMR_DAC2AMEN_Pos) /*!< 0x00004000 */
14408 #define RCC_SRDAMR_DAC2AMEN RCC_SRDAMR_DAC2AMEN_Msk
14409 #define RCC_SRDAMR_COMP12AMEN_Pos (14U)
14410 #define RCC_SRDAMR_COMP12AMEN_Msk (0x1UL << RCC_SRDAMR_COMP12AMEN_Pos) /*!< 0x00004000 */
14411 #define RCC_SRDAMR_COMP12AMEN RCC_SRDAMR_COMP12AMEN_Msk
14412 #define RCC_SRDAMR_VREFAMEN_Pos (15U)
14413 #define RCC_SRDAMR_VREFAMEN_Msk (0x1UL << RCC_SRDAMR_VREFAMEN_Pos) /*!< 0x00008000 */
14414 #define RCC_SRDAMR_VREFAMEN RCC_SRDAMR_VREFAMEN_Msk
14415 #define RCC_SRDAMR_RTCAMEN_Pos (16U)
14416 #define RCC_SRDAMR_RTCAMEN_Msk (0x1UL << RCC_SRDAMR_RTCAMEN_Pos) /*!< 0x00010000 */
14417 #define RCC_SRDAMR_RTCAMEN RCC_SRDAMR_RTCAMEN_Msk
14418 #define RCC_SRDAMR_DTSAMEN_Pos (26U)
14419 #define RCC_SRDAMR_DTSAMEN_Msk (0x1UL << RCC_SRDAMR_DTSAMEN_Pos) /*!< 0x04000000 */
14420 #define RCC_SRDAMR_DTSAMEN RCC_SRDAMR_DTSAMEN_Msk
14421 #define RCC_SRDAMR_DFSDM2AMEN_Pos (27U)
14422 #define RCC_SRDAMR_DFSDM2AMEN_Msk (0x1UL << RCC_SRDAMR_DFSDM2AMEN_Pos) /*!< 0x20000000 */
14423 #define RCC_SRDAMR_DFSDM2AMEN RCC_SRDAMR_DFSDM2AMEN_Msk
14424 #define RCC_SRDAMR_BKPRAMAMEN_Pos (28U)
14425 #define RCC_SRDAMR_BKPRAMAMEN_Msk (0x1UL << RCC_SRDAMR_BKPRAMAMEN_Pos) /*!< 0x10000000 */
14426 #define RCC_SRDAMR_BKPRAMAMEN RCC_SRDAMR_BKPRAMAMEN_Msk
14427 #define RCC_SRDAMR_SRDSRAMAMEN_Pos (29U)
14428 #define RCC_SRDAMR_SRDSRAMAMEN_Msk (0x1UL << RCC_SRDAMR_SRDSRAMAMEN_Pos) /*!< 0x20000000 */
14429 #define RCC_SRDAMR_SRDSRAMAMEN RCC_SRDAMR_SRDSRAMAMEN_Msk
14430 /******************** Bit definition for RCC_CKGAENR register ********************/
14431 #define RCC_CKGAENR_AXICKG_Pos (0U)
14432 #define RCC_CKGAENR_AXICKG_Msk (0x1UL << RCC_CKGAENR_AXICKG_Pos) /*!< 0x00000001 */
14433 #define RCC_CKGAENR_AXICKG RCC_CKGAENR_AXICKG_Msk
14434 #define RCC_CKGAENR_AHBCKG_Pos (1U)
14435 #define RCC_CKGAENR_AHBCKG_Msk (0x1UL << RCC_CKGAENR_AHBCKG_Pos) /*!< 0x00000002 */
14436 #define RCC_CKGAENR_AHBCKG RCC_CKGAENR_AHBCKG_Msk
14437 #define RCC_CKGAENR_CPUCKG_Pos (2U)
14438 #define RCC_CKGAENR_CPUCKG_Msk (0x1UL << RCC_CKGAENR_CPUCKG_Pos) /*!< 0x00000004 */
14439 #define RCC_CKGAENR_CPUCKG RCC_CKGAENR_CPUCKG_Msk
14440 #define RCC_CKGAENR_SDMMCCKG_Pos (3U)
14441 #define RCC_CKGAENR_SDMMCCKG_Msk (0x1UL << RCC_CKGAENR_SDMMCCKG_Pos) /*!< 0x00000008 */
14442 #define RCC_CKGAENR_SDMMCCKG RCC_CKGAENR_SDMMCCKG_Msk
14443 #define RCC_CKGAENR_MDMACKG_Pos (4U)
14444 #define RCC_CKGAENR_MDMACKG_Msk (0x1UL << RCC_CKGAENR_MDMACKG_Pos) /*!< 0x00000010 */
14445 #define RCC_CKGAENR_MDMACKG RCC_CKGAENR_MDMACKG_Msk
14446 #define RCC_CKGAENR_DMA2DCKG_Pos (5U)
14447 #define RCC_CKGAENR_DMA2DCKG_Msk (0x1UL << RCC_CKGAENR_DMA2DCKG_Pos) /*!< 0x00000020 */
14448 #define RCC_CKGAENR_DMA2DCKG RCC_CKGAENR_DMA2DCKG_Msk
14449 #define RCC_CKGAENR_LTDCCKG_Pos (6U)
14450 #define RCC_CKGAENR_LTDCCKG_Msk (0x1UL << RCC_CKGAENR_LTDCCKG_Pos) /*!< 0x00000040 */
14451 #define RCC_CKGAENR_LTDCCKG RCC_CKGAENR_LTDCCKG_Msk
14452 #define RCC_CKGAENR_GFXMMUMCKG_Pos (7U)
14453 #define RCC_CKGAENR_GFXMMUMCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUMCKG_Pos) /*!< 0x00000080 */
14454 #define RCC_CKGAENR_GFXMMUMCKG RCC_CKGAENR_GFXMMUMCKG_Msk
14455 #define RCC_CKGAENR_AHB12CKG_Pos (8U)
14456 #define RCC_CKGAENR_AHB12CKG_Msk (0x1UL << RCC_CKGAENR_AHB12CKG_Pos) /*!< 0x00000100 */
14457 #define RCC_CKGAENR_AHB12CKG RCC_CKGAENR_AHB12CKG_Msk
14458 #define RCC_CKGAENR_AHB34CKG_Pos (9U)
14459 #define RCC_CKGAENR_AHB34CKG_Msk (0x1UL << RCC_CKGAENR_AHB34CKG_Pos) /*!< 0x00000200 */
14460 #define RCC_CKGAENR_AHB34CKG RCC_CKGAENR_AHB34CKG_Msk
14461 #define RCC_CKGAENR_FLIFTCKG_Pos (10U)
14462 #define RCC_CKGAENR_FLIFTCKG_Msk (0x1UL << RCC_CKGAENR_FLIFTCKG_Pos) /*!< 0x00000400 */
14463 #define RCC_CKGAENR_FLIFTCKG RCC_CKGAENR_FLIFTCKG_Msk
14464 #define RCC_CKGAENR_OCTOSPI2CKG_Pos (11U)
14465 #define RCC_CKGAENR_OCTOSPI2CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI2CKG_Pos) /*!< 0x00000800 */
14466 #define RCC_CKGAENR_OCTOSPI2CKG RCC_CKGAENR_OCTOSPI2CKG_Msk
14467 #define RCC_CKGAENR_FMCCKG_Pos (12U)
14468 #define RCC_CKGAENR_FMCCKG_Msk (0x1UL << RCC_CKGAENR_FMCCKG_Pos) /*!< 0x00001000 */
14469 #define RCC_CKGAENR_FMCCKG RCC_CKGAENR_FMCCKG_Msk
14470 #define RCC_CKGAENR_OCTOSPI1CKG_Pos (13U)
14471 #define RCC_CKGAENR_OCTOSPI1CKG_Msk (0x1UL << RCC_CKGAENR_OCTOSPI1CKG_Pos) /*!< 0x00002000 */
14472 #define RCC_CKGAENR_OCTOSPI1CKG RCC_CKGAENR_OCTOSPI1CKG_Msk
14473 #define RCC_CKGAENR_AXIRAM1CKG_Pos (14U)
14474 #define RCC_CKGAENR_AXIRAM1CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM1CKG_Pos) /*!< 0x00004000 */
14475 #define RCC_CKGAENR_AXIRAM1CKG RCC_CKGAENR_AXIRAM1CKG_Msk
14476 #define RCC_CKGAENR_AXIRAM2CKG_Pos (15U)
14477 #define RCC_CKGAENR_AXIRAM2CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM2CKG_Pos) /*!< 0x00008000 */
14478 #define RCC_CKGAENR_AXIRAM2CKG RCC_CKGAENR_AXIRAM2CKG_Msk
14479 #define RCC_CKGAENR_AXIRAM3CKG_Pos (16U)
14480 #define RCC_CKGAENR_AXIRAM3CKG_Msk (0x1UL << RCC_CKGAENR_AXIRAM3CKG_Pos) /*!< 0x00010000 */
14481 #define RCC_CKGAENR_AXIRAM3CKG RCC_CKGAENR_AXIRAM3CKG_Msk
14482 #define RCC_CKGAENR_GFXMMUSCKG_Pos (17U)
14483 #define RCC_CKGAENR_GFXMMUSCKG_Msk (0x1UL << RCC_CKGAENR_GFXMMUSCKG_Pos) /*!< 0x00020000 */
14484 #define RCC_CKGAENR_GFXMMUSCKG RCC_CKGAENR_GFXMMUSCKG_Msk
14485 #define RCC_CKGAENR_ECCRAMCKG_Pos (29U)
14486 #define RCC_CKGAENR_ECCRAMCKG_Msk (0x1UL << RCC_CKGAENR_ECCRAMCKG_Pos) /*!< 0x20000000 */
14487 #define RCC_CKGAENR_ECCRAMCKG RCC_CKGAENR_ECCRAMCKG_Msk
14488 #define RCC_CKGAENR_EXTICKG_Pos (30U)
14489 #define RCC_CKGAENR_EXTICKG_Msk (0x1UL << RCC_CKGAENR_EXTICKG_Pos) /*!< 0x40000000 */
14490 #define RCC_CKGAENR_EXTICKG RCC_CKGAENR_EXTICKG_Msk
14491 #define RCC_CKGAENR_JTAGCKG_Pos (31U)
14492 #define RCC_CKGAENR_JTAGCKG_Msk (0x1UL << RCC_CKGAENR_JTAGCKG_Pos) /*!< 0x80000008 */
14493 #define RCC_CKGAENR_JTAGCKG RCC_CKGAENR_JTAGCKG_Msk
14494 /******************** Bit definition for RCC_AHB3LPENR register **************/
14495 #define RCC_AHB3LPENR_MDMALPEN_Pos (0U)
14496 #define RCC_AHB3LPENR_MDMALPEN_Msk (0x1UL << RCC_AHB3LPENR_MDMALPEN_Pos) /*!< 0x00000001 */
14497 #define RCC_AHB3LPENR_MDMALPEN RCC_AHB3LPENR_MDMALPEN_Msk
14498 #define RCC_AHB3LPENR_DMA2DLPEN_Pos (4U)
14499 #define RCC_AHB3LPENR_DMA2DLPEN_Msk (0x1UL << RCC_AHB3LPENR_DMA2DLPEN_Pos) /*!< 0x00000010 */
14500 #define RCC_AHB3LPENR_DMA2DLPEN RCC_AHB3LPENR_DMA2DLPEN_Msk
14501 #define RCC_AHB3LPENR_JPGDECLPEN_Pos (5U)
14502 #define RCC_AHB3LPENR_JPGDECLPEN_Msk (0x1UL << RCC_AHB3LPENR_JPGDECLPEN_Pos) /*!< 0x00000020 */
14503 #define RCC_AHB3LPENR_JPGDECLPEN RCC_AHB3LPENR_JPGDECLPEN_Msk
14504 #define RCC_AHB3LPENR_FLASHLPEN_Pos (8U)
14505 #define RCC_AHB3LPENR_FLASHLPEN_Msk (0x1UL << RCC_AHB3LPENR_FLASHLPEN_Pos) /*!< 0x00000100 */
14506 #define RCC_AHB3LPENR_FLASHLPEN RCC_AHB3LPENR_FLASHLPEN_Msk
14507 #define RCC_AHB3LPENR_FMCLPEN_Pos (12U)
14508 #define RCC_AHB3LPENR_FMCLPEN_Msk (0x1UL << RCC_AHB3LPENR_FMCLPEN_Pos) /*!< 0x00001000 */
14509 #define RCC_AHB3LPENR_FMCLPEN RCC_AHB3LPENR_FMCLPEN_Msk
14510 #define RCC_AHB3LPENR_OSPI1LPEN_Pos (14U)
14511 #define RCC_AHB3LPENR_OSPI1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI1LPEN_Pos) /*!< 0x00004000 */
14512 #define RCC_AHB3LPENR_OSPI1LPEN RCC_AHB3LPENR_OSPI1LPEN_Msk
14513 #define RCC_AHB3LPENR_SDMMC1LPEN_Pos (16U)
14514 #define RCC_AHB3LPENR_SDMMC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_SDMMC1LPEN_Pos) /*!< 0x00010000 */
14515 #define RCC_AHB3LPENR_SDMMC1LPEN RCC_AHB3LPENR_SDMMC1LPEN_Msk
14516 #define RCC_AHB3LPENR_OSPI2LPEN_Pos (19U)
14517 #define RCC_AHB3LPENR_OSPI2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OSPI2LPEN_Pos) /*!< 0x00080000 */
14518 #define RCC_AHB3LPENR_OSPI2LPEN RCC_AHB3LPENR_OSPI2LPEN_Msk
14519 #define RCC_AHB3LPENR_IOMNGRLPEN_Pos (21U)
14520 #define RCC_AHB3LPENR_IOMNGRLPEN_Msk (0x1UL << RCC_AHB3LPENR_IOMNGRLPEN_Pos) /*!< 0x00200000 */
14521 #define RCC_AHB3LPENR_IOMNGRLPEN RCC_AHB3LPENR_IOMNGRLPEN_Msk
14522 #define RCC_AHB3LPENR_OTFDEC1LPEN_Pos (22U)
14523 #define RCC_AHB3LPENR_OTFDEC1LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC1LPEN_Pos) /*!< 0x00400000 */
14524 #define RCC_AHB3LPENR_OTFDEC1LPEN RCC_AHB3LPENR_OTFDEC1LPEN_Msk
14525 #define RCC_AHB3LPENR_OTFDEC2LPEN_Pos (23U)
14526 #define RCC_AHB3LPENR_OTFDEC2LPEN_Msk (0x1UL << RCC_AHB3LPENR_OTFDEC2LPEN_Pos) /*!< 0x00800000 */
14527 #define RCC_AHB3LPENR_OTFDEC2LPEN RCC_AHB3LPENR_OTFDEC2LPEN_Msk
14528 #define RCC_AHB3LPENR_GFXMMULPEN_Pos (24U)
14529 #define RCC_AHB3LPENR_GFXMMULPEN_Msk (0x1UL << RCC_AHB3LPENR_GFXMMULPEN_Pos) /*!< 0x01000000 */
14530 #define RCC_AHB3LPENR_GFXMMULPEN RCC_AHB3LPENR_GFXMMULPEN_Msk
14531 #define RCC_AHB3LPENR_AXISRAM2LPEN_Pos (26U)
14532 #define RCC_AHB3LPENR_AXISRAM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM2LPEN_Pos) /*!< 0x02000000 */
14533 #define RCC_AHB3LPENR_AXISRAM2LPEN RCC_AHB3LPENR_AXISRAM2LPEN_Msk
14534 #define RCC_AHB3LPENR_AXISRAM3LPEN_Pos (27U)
14535 #define RCC_AHB3LPENR_AXISRAM3LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM3LPEN_Pos) /*!< 0x04000000 */
14536 #define RCC_AHB3LPENR_AXISRAM3LPEN RCC_AHB3LPENR_AXISRAM3LPEN_Msk
14537 #define RCC_AHB3LPENR_DTCM1LPEN_Pos (28U)
14538 #define RCC_AHB3LPENR_DTCM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM1LPEN_Pos) /*!< 0x10000000 */
14539 #define RCC_AHB3LPENR_DTCM1LPEN RCC_AHB3LPENR_DTCM1LPEN_Msk
14540 #define RCC_AHB3LPENR_DTCM2LPEN_Pos (29U)
14541 #define RCC_AHB3LPENR_DTCM2LPEN_Msk (0x1UL << RCC_AHB3LPENR_DTCM2LPEN_Pos) /*!< 0x20000000 */
14542 #define RCC_AHB3LPENR_DTCM2LPEN RCC_AHB3LPENR_DTCM2LPEN_Msk
14543 #define RCC_AHB3LPENR_ITCMLPEN_Pos (30U)
14544 #define RCC_AHB3LPENR_ITCMLPEN_Msk (0x1UL << RCC_AHB3LPENR_ITCMLPEN_Pos) /*!< 0x40000000 */
14545 #define RCC_AHB3LPENR_ITCMLPEN RCC_AHB3LPENR_ITCMLPEN_Msk
14546 #define RCC_AHB3LPENR_AXISRAM1LPEN_Pos (31U)
14547 #define RCC_AHB3LPENR_AXISRAM1LPEN_Msk (0x1UL << RCC_AHB3LPENR_AXISRAM1LPEN_Pos) /*!< 0x80000000 */
14548 #define RCC_AHB3LPENR_AXISRAM1LPEN RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14549
14550
14551 /* Legacy define */
14552 #define RCC_AHB3LPENR_AXISRAMLPEN_Pos RCC_AHB3LPENR_AXISRAM1LPEN_Pos
14553 #define RCC_AHB3LPENR_AXISRAMLPEN_Msk RCC_AHB3LPENR_AXISRAM1LPEN_Msk
14554 #define RCC_AHB3LPENR_AXISRAMLPEN RCC_AHB3LPENR_AXISRAM1LPEN
14555 /******************** Bit definition for RCC_AHB1LPENR register ***************/
14556 #define RCC_AHB1LPENR_DMA1LPEN_Pos (0U)
14557 #define RCC_AHB1LPENR_DMA1LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA1LPEN_Pos) /*!< 0x00000001 */
14558 #define RCC_AHB1LPENR_DMA1LPEN RCC_AHB1LPENR_DMA1LPEN_Msk
14559 #define RCC_AHB1LPENR_DMA2LPEN_Pos (1U)
14560 #define RCC_AHB1LPENR_DMA2LPEN_Msk (0x1UL << RCC_AHB1LPENR_DMA2LPEN_Pos) /*!< 0x00000002 */
14561 #define RCC_AHB1LPENR_DMA2LPEN RCC_AHB1LPENR_DMA2LPEN_Msk
14562 #define RCC_AHB1LPENR_ADC12LPEN_Pos (5U)
14563 #define RCC_AHB1LPENR_ADC12LPEN_Msk (0x1UL << RCC_AHB1LPENR_ADC12LPEN_Pos) /*!< 0x00000020 */
14564 #define RCC_AHB1LPENR_ADC12LPEN RCC_AHB1LPENR_ADC12LPEN_Msk
14565 #define RCC_AHB1LPENR_CRCLPEN_Pos (9U)
14566 #define RCC_AHB1LPENR_CRCLPEN_Msk (0x1UL << RCC_AHB1LPENR_CRCLPEN_Pos) /*!< 0x00008000 */
14567 #define RCC_AHB1LPENR_CRCLPEN RCC_AHB1LPENR_CRCLPEN_Msk
14568 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Pos (25U)
14569 #define RCC_AHB1LPENR_USB1OTGHSLPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSLPEN_Pos) /*!< 0x02000000 */
14570 #define RCC_AHB1LPENR_USB1OTGHSLPEN RCC_AHB1LPENR_USB1OTGHSLPEN_Msk
14571 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos (26U)
14572 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk (0x1UL << RCC_AHB1LPENR_USB1OTGHSULPILPEN_Pos) /*!< 0x04000000 */
14573 #define RCC_AHB1LPENR_USB1OTGHSULPILPEN RCC_AHB1LPENR_USB1OTGHSULPILPEN_Msk
14574
14575 /******************** Bit definition for RCC_AHB2LPENR register ***************/
14576 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Pos (0U)
14577 #define RCC_AHB2LPENR_DCMI_PSSILPEN_Msk (0x1UL << RCC_AHB2LPENR_DCMI_PSSILPEN_Pos) /*!< 0x00000001 */
14578 #define RCC_AHB2LPENR_DCMI_PSSILPEN RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14579 #define RCC_AHB2LPENR_CRYPLPEN_Pos (4U)
14580 #define RCC_AHB2LPENR_CRYPLPEN_Msk (0x1UL << RCC_AHB2LPENR_CRYPLPEN_Pos) /*!< 0x00000010 */
14581 #define RCC_AHB2LPENR_CRYPLPEN RCC_AHB2LPENR_CRYPLPEN_Msk
14582 #define RCC_AHB2LPENR_HASHLPEN_Pos (5U)
14583 #define RCC_AHB2LPENR_HASHLPEN_Msk (0x1UL << RCC_AHB2LPENR_HASHLPEN_Pos) /*!< 0x00000020 */
14584 #define RCC_AHB2LPENR_HASHLPEN RCC_AHB2LPENR_HASHLPEN_Msk
14585 #define RCC_AHB2LPENR_RNGLPEN_Pos (6U)
14586 #define RCC_AHB2LPENR_RNGLPEN_Msk (0x1UL << RCC_AHB2LPENR_RNGLPEN_Pos) /*!< 0x00000040 */
14587 #define RCC_AHB2LPENR_RNGLPEN RCC_AHB2LPENR_RNGLPEN_Msk
14588 #define RCC_AHB2LPENR_SDMMC2LPEN_Pos (9U)
14589 #define RCC_AHB2LPENR_SDMMC2LPEN_Msk (0x1UL << RCC_AHB2LPENR_SDMMC2LPEN_Pos) /*!< 0x00000200 */
14590 #define RCC_AHB2LPENR_SDMMC2LPEN RCC_AHB2LPENR_SDMMC2LPEN_Msk
14591 #define RCC_AHB2LPENR_BDMA1LPEN_Pos (11U)
14592 #define RCC_AHB2LPENR_BDMA1LPEN_Msk (0x1UL << RCC_AHB2LPENR_BDMA1LPEN_Pos) /*!< 0x00000800 */
14593 #define RCC_AHB2LPENR_BDMA1LPEN RCC_AHB2LPENR_BDMA1LPEN_Msk
14594 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Pos (29U)
14595 #define RCC_AHB2LPENR_AHBSRAM1LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM1LPEN_Pos) /*!< 0x20000000 */
14596 #define RCC_AHB2LPENR_AHBSRAM1LPEN RCC_AHB2LPENR_AHBSRAM1LPEN_Msk
14597 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Pos (30U)
14598 #define RCC_AHB2LPENR_AHBSRAM2LPEN_Msk (0x1UL << RCC_AHB2LPENR_AHBSRAM2LPEN_Pos) /*!< 0x40000000 */
14599 #define RCC_AHB2LPENR_AHBSRAM2LPEN RCC_AHB2LPENR_AHBSRAM2LPEN_Msk
14600
14601 /* Legacy define */
14602 #define RCC_AHB2LPENR_DFSDMDMALPEN_Pos RCC_AHB2LPENR_BDMA1LPEN_Pos
14603 #define RCC_AHB2LPENR_DFSDMDMALPEN_Msk RCC_AHB2LPENR_BDMA1LPEN_Msk
14604 #define RCC_AHB2LPENR_DFSDMDMALPEN RCC_AHB2LPENR_BDMA1LPEN
14605 #define RCC_AHB2LPENR_DCMILPEN_Pos RCC_AHB2LPENR_DCMI_PSSILPEN_Pos
14606 #define RCC_AHB2LPENR_DCMILPEN_Msk RCC_AHB2LPENR_DCMI_PSSILPEN_Msk
14607 #define RCC_AHB2LPENR_DCMILPEN RCC_AHB2LPENR_DCMI_PSSILPEN
14608
14609 /******************** Bit definition for RCC_AHB4LPENR register ******************/
14610 #define RCC_AHB4LPENR_GPIOALPEN_Pos (0U)
14611 #define RCC_AHB4LPENR_GPIOALPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOALPEN_Pos) /*!< 0x00000001 */
14612 #define RCC_AHB4LPENR_GPIOALPEN RCC_AHB4LPENR_GPIOALPEN_Msk
14613 #define RCC_AHB4LPENR_GPIOBLPEN_Pos (1U)
14614 #define RCC_AHB4LPENR_GPIOBLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOBLPEN_Pos) /*!< 0x00000002 */
14615 #define RCC_AHB4LPENR_GPIOBLPEN RCC_AHB4LPENR_GPIOBLPEN_Msk
14616 #define RCC_AHB4LPENR_GPIOCLPEN_Pos (2U)
14617 #define RCC_AHB4LPENR_GPIOCLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOCLPEN_Pos) /*!< 0x00000004 */
14618 #define RCC_AHB4LPENR_GPIOCLPEN RCC_AHB4LPENR_GPIOCLPEN_Msk
14619 #define RCC_AHB4LPENR_GPIODLPEN_Pos (3U)
14620 #define RCC_AHB4LPENR_GPIODLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIODLPEN_Pos) /*!< 0x00000008 */
14621 #define RCC_AHB4LPENR_GPIODLPEN RCC_AHB4LPENR_GPIODLPEN_Msk
14622 #define RCC_AHB4LPENR_GPIOELPEN_Pos (4U)
14623 #define RCC_AHB4LPENR_GPIOELPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOELPEN_Pos) /*!< 0x00000010 */
14624 #define RCC_AHB4LPENR_GPIOELPEN RCC_AHB4LPENR_GPIOELPEN_Msk
14625 #define RCC_AHB4LPENR_GPIOFLPEN_Pos (5U)
14626 #define RCC_AHB4LPENR_GPIOFLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOFLPEN_Pos) /*!< 0x00000020 */
14627 #define RCC_AHB4LPENR_GPIOFLPEN RCC_AHB4LPENR_GPIOFLPEN_Msk
14628 #define RCC_AHB4LPENR_GPIOGLPEN_Pos (6U)
14629 #define RCC_AHB4LPENR_GPIOGLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOGLPEN_Pos) /*!< 0x00000040 */
14630 #define RCC_AHB4LPENR_GPIOGLPEN RCC_AHB4LPENR_GPIOGLPEN_Msk
14631 #define RCC_AHB4LPENR_GPIOHLPEN_Pos (7U)
14632 #define RCC_AHB4LPENR_GPIOHLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOHLPEN_Pos) /*!< 0x00000080 */
14633 #define RCC_AHB4LPENR_GPIOHLPEN RCC_AHB4LPENR_GPIOHLPEN_Msk
14634 #define RCC_AHB4LPENR_GPIOILPEN_Pos (8U)
14635 #define RCC_AHB4LPENR_GPIOILPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOILPEN_Pos) /*!< 0x00000100 */
14636 #define RCC_AHB4LPENR_GPIOILPEN RCC_AHB4LPENR_GPIOILPEN_Msk
14637 #define RCC_AHB4LPENR_GPIOJLPEN_Pos (9U)
14638 #define RCC_AHB4LPENR_GPIOJLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOJLPEN_Pos) /*!< 0x00000200 */
14639 #define RCC_AHB4LPENR_GPIOJLPEN RCC_AHB4LPENR_GPIOJLPEN_Msk
14640 #define RCC_AHB4LPENR_GPIOKLPEN_Pos (10U)
14641 #define RCC_AHB4LPENR_GPIOKLPEN_Msk (0x1UL << RCC_AHB4LPENR_GPIOKLPEN_Pos) /*!< 0x00000400 */
14642 #define RCC_AHB4LPENR_GPIOKLPEN RCC_AHB4LPENR_GPIOKLPEN_Msk
14643 #define RCC_AHB4LPENR_BDMA2LPEN_Pos (21U)
14644 #define RCC_AHB4LPENR_BDMA2LPEN_Msk (0x1UL << RCC_AHB4LPENR_BDMA2LPEN_Pos) /*!< 0x00200000 */
14645 #define RCC_AHB4LPENR_BDMA2LPEN RCC_AHB4LPENR_BDMA2LPEN_Msk
14646 #define RCC_AHB4LPENR_BKPRAMLPEN_Pos (28U)
14647 #define RCC_AHB4LPENR_BKPRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_BKPRAMLPEN_Pos) /*!< 0x10000000 */
14648 #define RCC_AHB4LPENR_BKPRAMLPEN RCC_AHB4LPENR_BKPRAMLPEN_Msk
14649 #define RCC_AHB4LPENR_SRDSRAMLPEN_Pos (29U)
14650 #define RCC_AHB4LPENR_SRDSRAMLPEN_Msk (0x1UL << RCC_AHB4LPENR_SRDSRAMLPEN_Pos) /*!< 0x20000000 */
14651 #define RCC_AHB4LPENR_SRDSRAMLPEN RCC_AHB4LPENR_SRDSRAMLPEN_Msk
14652
14653 /******************** Bit definition for RCC_APB3LPENR register ******************/
14654 #define RCC_APB3LPENR_LTDCLPEN_Pos (3U)
14655 #define RCC_APB3LPENR_LTDCLPEN_Msk (0x1UL << RCC_APB3LPENR_LTDCLPEN_Pos) /*!< 0x00000008 */
14656 #define RCC_APB3LPENR_LTDCLPEN RCC_APB3LPENR_LTDCLPEN_Msk
14657 #define RCC_APB3LPENR_WWDGLPEN_Pos (6U)
14658 #define RCC_APB3LPENR_WWDGLPEN_Msk (0x1UL << RCC_APB3LPENR_WWDGLPEN_Pos) /*!< 0x00000040 */
14659 #define RCC_APB3LPENR_WWDGLPEN RCC_APB3LPENR_WWDGLPEN_Msk
14660
14661 /* Legacy define */
14662 #define RCC_APB3LPENR_WWDG1LPEN_Pos RCC_APB3LPENR_WWDGLPEN_Pos
14663 #define RCC_APB3LPENR_WWDG1LPEN_Msk RCC_APB3LPENR_WWDGLPEN_Msk
14664 #define RCC_APB3LPENR_WWDG1LPEN RCC_APB3LPENR_WWDGLPEN
14665 /******************** Bit definition for RCC_APB1LLPENR register ******************/
14666
14667 #define RCC_APB1LLPENR_TIM2LPEN_Pos (0U)
14668 #define RCC_APB1LLPENR_TIM2LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM2LPEN_Pos) /*!< 0x00000001 */
14669 #define RCC_APB1LLPENR_TIM2LPEN RCC_APB1LLPENR_TIM2LPEN_Msk
14670 #define RCC_APB1LLPENR_TIM3LPEN_Pos (1U)
14671 #define RCC_APB1LLPENR_TIM3LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM3LPEN_Pos) /*!< 0x00000002 */
14672 #define RCC_APB1LLPENR_TIM3LPEN RCC_APB1LLPENR_TIM3LPEN_Msk
14673 #define RCC_APB1LLPENR_TIM4LPEN_Pos (2U)
14674 #define RCC_APB1LLPENR_TIM4LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM4LPEN_Pos) /*!< 0x00000004 */
14675 #define RCC_APB1LLPENR_TIM4LPEN RCC_APB1LLPENR_TIM4LPEN_Msk
14676 #define RCC_APB1LLPENR_TIM5LPEN_Pos (3U)
14677 #define RCC_APB1LLPENR_TIM5LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM5LPEN_Pos) /*!< 0x00000008 */
14678 #define RCC_APB1LLPENR_TIM5LPEN RCC_APB1LLPENR_TIM5LPEN_Msk
14679 #define RCC_APB1LLPENR_TIM6LPEN_Pos (4U)
14680 #define RCC_APB1LLPENR_TIM6LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM6LPEN_Pos) /*!< 0x00000010 */
14681 #define RCC_APB1LLPENR_TIM6LPEN RCC_APB1LLPENR_TIM6LPEN_Msk
14682 #define RCC_APB1LLPENR_TIM7LPEN_Pos (5U)
14683 #define RCC_APB1LLPENR_TIM7LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM7LPEN_Pos) /*!< 0x00000020 */
14684 #define RCC_APB1LLPENR_TIM7LPEN RCC_APB1LLPENR_TIM7LPEN_Msk
14685 #define RCC_APB1LLPENR_TIM12LPEN_Pos (6U)
14686 #define RCC_APB1LLPENR_TIM12LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM12LPEN_Pos) /*!< 0x00000040 */
14687 #define RCC_APB1LLPENR_TIM12LPEN RCC_APB1LLPENR_TIM12LPEN_Msk
14688 #define RCC_APB1LLPENR_TIM13LPEN_Pos (7U)
14689 #define RCC_APB1LLPENR_TIM13LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM13LPEN_Pos) /*!< 0x00000080 */
14690 #define RCC_APB1LLPENR_TIM13LPEN RCC_APB1LLPENR_TIM13LPEN_Msk
14691 #define RCC_APB1LLPENR_TIM14LPEN_Pos (8U)
14692 #define RCC_APB1LLPENR_TIM14LPEN_Msk (0x1UL << RCC_APB1LLPENR_TIM14LPEN_Pos) /*!< 0x00000100 */
14693 #define RCC_APB1LLPENR_TIM14LPEN RCC_APB1LLPENR_TIM14LPEN_Msk
14694 #define RCC_APB1LLPENR_LPTIM1LPEN_Pos (9U)
14695 #define RCC_APB1LLPENR_LPTIM1LPEN_Msk (0x1UL << RCC_APB1LLPENR_LPTIM1LPEN_Pos) /*!< 0x00000200 */
14696 #define RCC_APB1LLPENR_LPTIM1LPEN RCC_APB1LLPENR_LPTIM1LPEN_Msk
14697
14698
14699 #define RCC_APB1LLPENR_SPI2LPEN_Pos (14U)
14700 #define RCC_APB1LLPENR_SPI2LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI2LPEN_Pos) /*!< 0x00004000 */
14701 #define RCC_APB1LLPENR_SPI2LPEN RCC_APB1LLPENR_SPI2LPEN_Msk
14702 #define RCC_APB1LLPENR_SPI3LPEN_Pos (15U)
14703 #define RCC_APB1LLPENR_SPI3LPEN_Msk (0x1UL << RCC_APB1LLPENR_SPI3LPEN_Pos) /*!< 0x00008000 */
14704 #define RCC_APB1LLPENR_SPI3LPEN RCC_APB1LLPENR_SPI3LPEN_Msk
14705 #define RCC_APB1LLPENR_SPDIFRXLPEN_Pos (16U)
14706 #define RCC_APB1LLPENR_SPDIFRXLPEN_Msk (0x1UL << RCC_APB1LLPENR_SPDIFRXLPEN_Pos) /*!< 0x00010000 */
14707 #define RCC_APB1LLPENR_SPDIFRXLPEN RCC_APB1LLPENR_SPDIFRXLPEN_Msk
14708 #define RCC_APB1LLPENR_USART2LPEN_Pos (17U)
14709 #define RCC_APB1LLPENR_USART2LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART2LPEN_Pos) /*!< 0x00020000 */
14710 #define RCC_APB1LLPENR_USART2LPEN RCC_APB1LLPENR_USART2LPEN_Msk
14711 #define RCC_APB1LLPENR_USART3LPEN_Pos (18U)
14712 #define RCC_APB1LLPENR_USART3LPEN_Msk (0x1UL << RCC_APB1LLPENR_USART3LPEN_Pos) /*!< 0x00040000 */
14713 #define RCC_APB1LLPENR_USART3LPEN RCC_APB1LLPENR_USART3LPEN_Msk
14714 #define RCC_APB1LLPENR_UART4LPEN_Pos (19U)
14715 #define RCC_APB1LLPENR_UART4LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART4LPEN_Pos) /*!< 0x00080000 */
14716 #define RCC_APB1LLPENR_UART4LPEN RCC_APB1LLPENR_UART4LPEN_Msk
14717 #define RCC_APB1LLPENR_UART5LPEN_Pos (20U)
14718 #define RCC_APB1LLPENR_UART5LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART5LPEN_Pos) /*!< 0x00100000 */
14719 #define RCC_APB1LLPENR_UART5LPEN RCC_APB1LLPENR_UART5LPEN_Msk
14720 #define RCC_APB1LLPENR_I2C1LPEN_Pos (21U)
14721 #define RCC_APB1LLPENR_I2C1LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C1LPEN_Pos) /*!< 0x00200000 */
14722 #define RCC_APB1LLPENR_I2C1LPEN RCC_APB1LLPENR_I2C1LPEN_Msk
14723 #define RCC_APB1LLPENR_I2C2LPEN_Pos (22U)
14724 #define RCC_APB1LLPENR_I2C2LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C2LPEN_Pos) /*!< 0x00400000 */
14725 #define RCC_APB1LLPENR_I2C2LPEN RCC_APB1LLPENR_I2C2LPEN_Msk
14726 #define RCC_APB1LLPENR_I2C3LPEN_Pos (23U)
14727 #define RCC_APB1LLPENR_I2C3LPEN_Msk (0x1UL << RCC_APB1LLPENR_I2C3LPEN_Pos) /*!< 0x00800000 */
14728 #define RCC_APB1LLPENR_I2C3LPEN RCC_APB1LLPENR_I2C3LPEN_Msk
14729 #define RCC_APB1LLPENR_CECLPEN_Pos (27U)
14730 #define RCC_APB1LLPENR_CECLPEN_Msk (0x1UL << RCC_APB1LLPENR_CECLPEN_Pos) /*!< 0x08000000 */
14731 #define RCC_APB1LLPENR_CECLPEN RCC_APB1LLPENR_CECLPEN_Msk
14732 #define RCC_APB1LLPENR_DAC12LPEN_Pos (29U)
14733 #define RCC_APB1LLPENR_DAC12LPEN_Msk (0x1UL << RCC_APB1LLPENR_DAC12LPEN_Pos) /*!< 0x20000000 */
14734 #define RCC_APB1LLPENR_DAC12LPEN RCC_APB1LLPENR_DAC12LPEN_Msk
14735 #define RCC_APB1LLPENR_UART7LPEN_Pos (30U)
14736 #define RCC_APB1LLPENR_UART7LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART7LPEN_Pos) /*!< 0x40000000 */
14737 #define RCC_APB1LLPENR_UART7LPEN RCC_APB1LLPENR_UART7LPEN_Msk
14738 #define RCC_APB1LLPENR_UART8LPEN_Pos (31U)
14739 #define RCC_APB1LLPENR_UART8LPEN_Msk (0x1UL << RCC_APB1LLPENR_UART8LPEN_Pos) /*!< 0x80000000 */
14740 #define RCC_APB1LLPENR_UART8LPEN RCC_APB1LLPENR_UART8LPEN_Msk
14741
14742 /* Legacy define */
14743 #define RCC_APB1LLPENR_HDMICECEN_Pos RCC_APB1LLPENR_CECLPEN_Pos
14744 #define RCC_APB1LLPENR_HDMICECEN_Msk RCC_APB1LLPENR_CECLPEN_Msk
14745 #define RCC_APB1LLPENR_HDMICECEN RCC_APB1LLPENR_CECLPEN
14746 /******************** Bit definition for RCC_APB1HLPENR register ******************/
14747 #define RCC_APB1HLPENR_CRSLPEN_Pos (1U)
14748 #define RCC_APB1HLPENR_CRSLPEN_Msk (0x1UL << RCC_APB1HLPENR_CRSLPEN_Pos) /*!< 0x00000002 */
14749 #define RCC_APB1HLPENR_CRSLPEN RCC_APB1HLPENR_CRSLPEN_Msk
14750 #define RCC_APB1HLPENR_SWPMILPEN_Pos (2U)
14751 #define RCC_APB1HLPENR_SWPMILPEN_Msk (0x1UL << RCC_APB1HLPENR_SWPMILPEN_Pos) /*!< 0x00000004 */
14752 #define RCC_APB1HLPENR_SWPMILPEN RCC_APB1HLPENR_SWPMILPEN_Msk
14753 #define RCC_APB1HLPENR_OPAMPLPEN_Pos (4U)
14754 #define RCC_APB1HLPENR_OPAMPLPEN_Msk (0x1UL << RCC_APB1HLPENR_OPAMPLPEN_Pos) /*!< 0x00000010 */
14755 #define RCC_APB1HLPENR_OPAMPLPEN RCC_APB1HLPENR_OPAMPLPEN_Msk
14756 #define RCC_APB1HLPENR_MDIOSLPEN_Pos (5U)
14757 #define RCC_APB1HLPENR_MDIOSLPEN_Msk (0x1UL << RCC_APB1HLPENR_MDIOSLPEN_Pos) /*!< 0x00000020 */
14758 #define RCC_APB1HLPENR_MDIOSLPEN RCC_APB1HLPENR_MDIOSLPEN_Msk
14759 #define RCC_APB1HLPENR_FDCANLPEN_Pos (8U)
14760 #define RCC_APB1HLPENR_FDCANLPEN_Msk (0x1UL << RCC_APB1HLPENR_FDCANLPEN_Pos) /*!< 0x00000100 */
14761 #define RCC_APB1HLPENR_FDCANLPEN RCC_APB1HLPENR_FDCANLPEN_Msk
14762
14763 /******************** Bit definition for RCC_APB2LPENR register ******************/
14764 #define RCC_APB2LPENR_TIM1LPEN_Pos (0U)
14765 #define RCC_APB2LPENR_TIM1LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM1LPEN_Pos) /*!< 0x00000001 */
14766 #define RCC_APB2LPENR_TIM1LPEN RCC_APB2LPENR_TIM1LPEN_Msk
14767 #define RCC_APB2LPENR_TIM8LPEN_Pos (1U)
14768 #define RCC_APB2LPENR_TIM8LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM8LPEN_Pos) /*!< 0x00000002 */
14769 #define RCC_APB2LPENR_TIM8LPEN RCC_APB2LPENR_TIM8LPEN_Msk
14770 #define RCC_APB2LPENR_USART1LPEN_Pos (4U)
14771 #define RCC_APB2LPENR_USART1LPEN_Msk (0x1UL << RCC_APB2LPENR_USART1LPEN_Pos) /*!< 0x00000010 */
14772 #define RCC_APB2LPENR_USART1LPEN RCC_APB2LPENR_USART1LPEN_Msk
14773 #define RCC_APB2LPENR_USART6LPEN_Pos (5U)
14774 #define RCC_APB2LPENR_USART6LPEN_Msk (0x1UL << RCC_APB2LPENR_USART6LPEN_Pos) /*!< 0x00000020 */
14775 #define RCC_APB2LPENR_USART6LPEN RCC_APB2LPENR_USART6LPEN_Msk
14776 #define RCC_APB2LPENR_UART9LPEN_Pos (6U)
14777 #define RCC_APB2LPENR_UART9LPEN_Msk (0x1UL << RCC_APB2LPENR_UART9LPEN_Pos) /*!< 0x00000040 */
14778 #define RCC_APB2LPENR_UART9LPEN RCC_APB2LPENR_UART9LPEN_Msk
14779 #define RCC_APB2LPENR_USART10LPEN_Pos (7U)
14780 #define RCC_APB2LPENR_USART10LPEN_Msk (0x1UL << RCC_APB2LPENR_USART10LPEN_Pos) /*!< 0x00000080 */
14781 #define RCC_APB2LPENR_USART10LPEN RCC_APB2LPENR_USART10LPEN_Msk
14782 #define RCC_APB2LPENR_SPI1LPEN_Pos (12U)
14783 #define RCC_APB2LPENR_SPI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI1LPEN_Pos) /*!< 0x00001000 */
14784 #define RCC_APB2LPENR_SPI1LPEN RCC_APB2LPENR_SPI1LPEN_Msk
14785 #define RCC_APB2LPENR_SPI4LPEN_Pos (13U)
14786 #define RCC_APB2LPENR_SPI4LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI4LPEN_Pos) /*!< 0x00002000 */
14787 #define RCC_APB2LPENR_SPI4LPEN RCC_APB2LPENR_SPI4LPEN_Msk
14788 #define RCC_APB2LPENR_TIM15LPEN_Pos (16U)
14789 #define RCC_APB2LPENR_TIM15LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM15LPEN_Pos) /*!< 0x00010000 */
14790 #define RCC_APB2LPENR_TIM15LPEN RCC_APB2LPENR_TIM15LPEN_Msk
14791 #define RCC_APB2LPENR_TIM16LPEN_Pos (17U)
14792 #define RCC_APB2LPENR_TIM16LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM16LPEN_Pos) /*!< 0x00020000 */
14793 #define RCC_APB2LPENR_TIM16LPEN RCC_APB2LPENR_TIM16LPEN_Msk
14794 #define RCC_APB2LPENR_TIM17LPEN_Pos (18U)
14795 #define RCC_APB2LPENR_TIM17LPEN_Msk (0x1UL << RCC_APB2LPENR_TIM17LPEN_Pos) /*!< 0x00040000 */
14796 #define RCC_APB2LPENR_TIM17LPEN RCC_APB2LPENR_TIM17LPEN_Msk
14797 #define RCC_APB2LPENR_SPI5LPEN_Pos (20U)
14798 #define RCC_APB2LPENR_SPI5LPEN_Msk (0x1UL << RCC_APB2LPENR_SPI5LPEN_Pos) /*!< 0x00100000 */
14799 #define RCC_APB2LPENR_SPI5LPEN RCC_APB2LPENR_SPI5LPEN_Msk
14800 #define RCC_APB2LPENR_SAI1LPEN_Pos (22U)
14801 #define RCC_APB2LPENR_SAI1LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI1LPEN_Pos) /*!< 0x00400000 */
14802 #define RCC_APB2LPENR_SAI1LPEN RCC_APB2LPENR_SAI1LPEN_Msk
14803 #define RCC_APB2LPENR_SAI2LPEN_Pos (23U)
14804 #define RCC_APB2LPENR_SAI2LPEN_Msk (0x1UL << RCC_APB2LPENR_SAI2LPEN_Pos) /*!< 0x00800000 */
14805 #define RCC_APB2LPENR_SAI2LPEN RCC_APB2LPENR_SAI2LPEN_Msk
14806 #define RCC_APB2LPENR_DFSDM1LPEN_Pos (30U)
14807 #define RCC_APB2LPENR_DFSDM1LPEN_Msk (0x1UL << RCC_APB2LPENR_DFSDM1LPEN_Pos) /*!< 0x40000000 */
14808 #define RCC_APB2LPENR_DFSDM1LPEN RCC_APB2LPENR_DFSDM1LPEN_Msk
14809
14810 /******************** Bit definition for RCC_APB4LPENR register ******************/
14811 #define RCC_APB4LPENR_SYSCFGLPEN_Pos (1U)
14812 #define RCC_APB4LPENR_SYSCFGLPEN_Msk (0x1UL << RCC_APB4LPENR_SYSCFGLPEN_Pos) /*!< 0x00000002 */
14813 #define RCC_APB4LPENR_SYSCFGLPEN RCC_APB4LPENR_SYSCFGLPEN_Msk
14814 #define RCC_APB4LPENR_LPUART1LPEN_Pos (3U)
14815 #define RCC_APB4LPENR_LPUART1LPEN_Msk (0x1UL << RCC_APB4LPENR_LPUART1LPEN_Pos) /*!< 0x00000008 */
14816 #define RCC_APB4LPENR_LPUART1LPEN RCC_APB4LPENR_LPUART1LPEN_Msk
14817 #define RCC_APB4LPENR_SPI6LPEN_Pos (5U)
14818 #define RCC_APB4LPENR_SPI6LPEN_Msk (0x1UL << RCC_APB4LPENR_SPI6LPEN_Pos) /*!< 0x00000020 */
14819 #define RCC_APB4LPENR_SPI6LPEN RCC_APB4LPENR_SPI6LPEN_Msk
14820 #define RCC_APB4LPENR_I2C4LPEN_Pos (7U)
14821 #define RCC_APB4LPENR_I2C4LPEN_Msk (0x1UL << RCC_APB4LPENR_I2C4LPEN_Pos) /*!< 0x00000080 */
14822 #define RCC_APB4LPENR_I2C4LPEN RCC_APB4LPENR_I2C4LPEN_Msk
14823 #define RCC_APB4LPENR_LPTIM2LPEN_Pos (9U)
14824 #define RCC_APB4LPENR_LPTIM2LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM2LPEN_Pos) /*!< 0x00000200 */
14825 #define RCC_APB4LPENR_LPTIM2LPEN RCC_APB4LPENR_LPTIM2LPEN_Msk
14826 #define RCC_APB4LPENR_LPTIM3LPEN_Pos (10U)
14827 #define RCC_APB4LPENR_LPTIM3LPEN_Msk (0x1UL << RCC_APB4LPENR_LPTIM3LPEN_Pos) /*!< 0x00000400 */
14828 #define RCC_APB4LPENR_LPTIM3LPEN RCC_APB4LPENR_LPTIM3LPEN_Msk
14829 #define RCC_APB4LPENR_DAC2LPEN_Pos (13U)
14830 #define RCC_APB4LPENR_DAC2LPEN_Msk (0x1UL << RCC_APB4LPENR_DAC2LPEN_Pos) /*!< 0x00002000 */
14831 #define RCC_APB4LPENR_DAC2LPEN RCC_APB4LPENR_DAC2LPEN_Msk
14832 #define RCC_APB4LPENR_COMP12LPEN_Pos (14U)
14833 #define RCC_APB4LPENR_COMP12LPEN_Msk (0x1UL << RCC_APB4LPENR_COMP12LPEN_Pos) /*!< 0x00004000 */
14834 #define RCC_APB4LPENR_COMP12LPEN RCC_APB4LPENR_COMP12LPEN_Msk
14835 #define RCC_APB4LPENR_VREFLPEN_Pos (15U)
14836 #define RCC_APB4LPENR_VREFLPEN_Msk (0x1UL << RCC_APB4LPENR_VREFLPEN_Pos) /*!< 0x00008000 */
14837 #define RCC_APB4LPENR_VREFLPEN RCC_APB4LPENR_VREFLPEN_Msk
14838 #define RCC_APB4LPENR_RTCAPBLPEN_Pos (16U)
14839 #define RCC_APB4LPENR_RTCAPBLPEN_Msk (0x1UL << RCC_APB4LPENR_RTCAPBLPEN_Pos) /*!< 0x00010000 */
14840 #define RCC_APB4LPENR_RTCAPBLPEN RCC_APB4LPENR_RTCAPBLPEN_Msk
14841
14842 #define RCC_APB4LPENR_DTSLPEN_Pos (26U)
14843 #define RCC_APB4LPENR_DTSLPEN_Msk (0x1UL << RCC_APB4LPENR_DTSLPEN_Pos) /*!< 0x04000000 */
14844 #define RCC_APB4LPENR_DTSLPEN RCC_APB4LPENR_DTSLPEN_Msk
14845 #define RCC_APB4LPENR_DFSDM2LPEN_Pos (27U)
14846 #define RCC_APB4LPENR_DFSDM2LPEN_Msk (0x1UL << RCC_APB4LPENR_DFSDM2LPEN_Pos) /*!< 0x08000000 */
14847 #define RCC_APB4LPENR_DFSDM2LPEN RCC_APB4LPENR_DFSDM2LPEN_Msk
14848
14849 /******************** Bit definition for RCC_RSR register *******************/
14850 #define RCC_RSR_RMVF_Pos (16U)
14851 #define RCC_RSR_RMVF_Msk (0x1UL << RCC_RSR_RMVF_Pos) /*!< 0x00010000 */
14852 #define RCC_RSR_RMVF RCC_RSR_RMVF_Msk
14853 #define RCC_RSR_CDRSTF_Pos (19U)
14854 #define RCC_RSR_CDRSTF_Msk (0x1UL << RCC_RSR_CDRSTF_Pos) /*!< 0x00080000 */
14855 #define RCC_RSR_CDRSTF RCC_RSR_CDRSTF_Msk
14856 #define RCC_RSR_BORRSTF_Pos (21U)
14857 #define RCC_RSR_BORRSTF_Msk (0x1UL << RCC_RSR_BORRSTF_Pos) /*!< 0x00200000 */
14858 #define RCC_RSR_BORRSTF RCC_RSR_BORRSTF_Msk
14859 #define RCC_RSR_PINRSTF_Pos (22U)
14860 #define RCC_RSR_PINRSTF_Msk (0x1UL << RCC_RSR_PINRSTF_Pos) /*!< 0x00400000 */
14861 #define RCC_RSR_PINRSTF RCC_RSR_PINRSTF_Msk
14862 #define RCC_RSR_PORRSTF_Pos (23U)
14863 #define RCC_RSR_PORRSTF_Msk (0x1UL << RCC_RSR_PORRSTF_Pos) /*!< 0x00800000 */
14864 #define RCC_RSR_PORRSTF RCC_RSR_PORRSTF_Msk
14865 #define RCC_RSR_SFTRSTF_Pos (24U)
14866 #define RCC_RSR_SFTRSTF_Msk (0x1UL << RCC_RSR_SFTRSTF_Pos) /*!< 0x01000000 */
14867 #define RCC_RSR_SFTRSTF RCC_RSR_SFTRSTF_Msk
14868 #define RCC_RSR_IWDGRSTF_Pos (26U)
14869 #define RCC_RSR_IWDGRSTF_Msk (0x1UL << RCC_RSR_IWDGRSTF_Pos) /*!< 0x04000000 */
14870 #define RCC_RSR_IWDGRSTF RCC_RSR_IWDGRSTF_Msk
14871 #define RCC_RSR_WWDGRSTF_Pos (28U)
14872 #define RCC_RSR_WWDGRSTF_Msk (0x1UL << RCC_RSR_WWDGRSTF_Pos) /*!< 0x10000000 */
14873 #define RCC_RSR_WWDGRSTF RCC_RSR_WWDGRSTF_Msk
14874
14875 #define RCC_RSR_LPWRRSTF_Pos (30U)
14876 #define RCC_RSR_LPWRRSTF_Msk (0x1UL << RCC_RSR_LPWRRSTF_Pos) /*!< 0x40000000 */
14877 #define RCC_RSR_LPWRRSTF RCC_RSR_LPWRRSTF_Msk
14878
14879
14880 /* Legacy define */
14881 #define RCC_RSR_IWDG1RSTF_Pos RCC_RSR_IWDGRSTF_Pos
14882 #define RCC_RSR_IWDG1RSTF_Msk RCC_RSR_IWDGRSTF_Msk
14883 #define RCC_RSR_IWDG1RSTF RCC_RSR_IWDGRSTF
14884 #define RCC_RSR_WWDG1RSTF_Pos RCC_RSR_WWDGRSTF_Pos
14885 #define RCC_RSR_WWDG1RSTF_Msk RCC_RSR_WWDGRSTF_Msk
14886 #define RCC_RSR_WWDG1RSTF RCC_RSR_WWDGRSTF
14887 /******************************************************************************/
14888 /* */
14889 /* RNG */
14890 /* */
14891 /******************************************************************************/
14892 /*************************** RNG VER **************************************/
14893 #define RNG_VER_3_1
14894 /******************** Bits definition for RNG_CR register *******************/
14895 #define RNG_CR_RNGEN_Pos (2U)
14896 #define RNG_CR_RNGEN_Msk (0x1UL << RNG_CR_RNGEN_Pos) /*!< 0x00000004 */
14897 #define RNG_CR_RNGEN RNG_CR_RNGEN_Msk
14898 #define RNG_CR_IE_Pos (3U)
14899 #define RNG_CR_IE_Msk (0x1UL << RNG_CR_IE_Pos) /*!< 0x00000008 */
14900 #define RNG_CR_IE RNG_CR_IE_Msk
14901 #define RNG_CR_CED_Pos (5U)
14902 #define RNG_CR_CED_Msk (0x1UL << RNG_CR_CED_Pos) /*!< 0x00000020 */
14903 #define RNG_CR_CED RNG_CR_CED_Msk
14904 #define RNG_CR_RNG_CONFIG3_Pos (8U)
14905 #define RNG_CR_RNG_CONFIG3_Msk (0xFUL << RNG_CR_RNG_CONFIG3_Pos) /*!< 0x00000F00 */
14906 #define RNG_CR_RNG_CONFIG3 RNG_CR_RNG_CONFIG3_Msk
14907 #define RNG_CR_NISTC_Pos (12U)
14908 #define RNG_CR_NISTC_Msk (0x1UL << RNG_CR_NISTC_Pos) /*!< 0x00001000 */
14909 #define RNG_CR_NISTC RNG_CR_NISTC_Msk
14910 #define RNG_CR_RNG_CONFIG2_Pos (13U)
14911 #define RNG_CR_RNG_CONFIG2_Msk (0x7UL << RNG_CR_RNG_CONFIG2_Pos) /*!< 0x0000E000 */
14912 #define RNG_CR_RNG_CONFIG2 RNG_CR_RNG_CONFIG2_Msk
14913 #define RNG_CR_CLKDIV_Pos (16U)
14914 #define RNG_CR_CLKDIV_Msk (0xFUL << RNG_CR_CLKDIV_Pos) /*!< 0x000F0000 */
14915 #define RNG_CR_CLKDIV RNG_CR_CLKDIV_Msk
14916 #define RNG_CR_CLKDIV_0 (0x1U << RNG_CR_CLKDIV_Pos) /*!< 0x00010000 */
14917 #define RNG_CR_CLKDIV_1 (0x2U << RNG_CR_CLKDIV_Pos) /*!< 0x00020000 */
14918 #define RNG_CR_CLKDIV_2 (0x4U << RNG_CR_CLKDIV_Pos) /*!< 0x00040000 */
14919 #define RNG_CR_CLKDIV_3 (0x8U << RNG_CR_CLKDIV_Pos) /*!< 0x00080000 */
14920 #define RNG_CR_RNG_CONFIG1_Pos (20U)
14921 #define RNG_CR_RNG_CONFIG1_Msk (0x3FUL << RNG_CR_RNG_CONFIG1_Pos) /*!< 0x03F00000 */
14922 #define RNG_CR_RNG_CONFIG1 RNG_CR_RNG_CONFIG1_Msk
14923 #define RNG_CR_CONDRST_Pos (30U)
14924 #define RNG_CR_CONDRST_Msk (0x1UL << RNG_CR_CONDRST_Pos) /*!< 0x40000000 */
14925 #define RNG_CR_CONDRST RNG_CR_CONDRST_Msk
14926 #define RNG_CR_CONFIGLOCK_Pos (31U)
14927 #define RNG_CR_CONFIGLOCK_Msk (0x1UL << RNG_CR_CONFIGLOCK_Pos) /*!< 0x80000000 */
14928 #define RNG_CR_CONFIGLOCK RNG_CR_CONFIGLOCK_Msk
14929
14930 /******************** Bits definition for RNG_SR register *******************/
14931 #define RNG_SR_DRDY_Pos (0U)
14932 #define RNG_SR_DRDY_Msk (0x1UL << RNG_SR_DRDY_Pos) /*!< 0x00000001 */
14933 #define RNG_SR_DRDY RNG_SR_DRDY_Msk
14934 #define RNG_SR_CECS_Pos (1U)
14935 #define RNG_SR_CECS_Msk (0x1UL << RNG_SR_CECS_Pos) /*!< 0x00000002 */
14936 #define RNG_SR_CECS RNG_SR_CECS_Msk
14937 #define RNG_SR_SECS_Pos (2U)
14938 #define RNG_SR_SECS_Msk (0x1UL << RNG_SR_SECS_Pos) /*!< 0x00000004 */
14939 #define RNG_SR_SECS RNG_SR_SECS_Msk
14940 #define RNG_SR_CEIS_Pos (5U)
14941 #define RNG_SR_CEIS_Msk (0x1UL << RNG_SR_CEIS_Pos) /*!< 0x00000020 */
14942 #define RNG_SR_CEIS RNG_SR_CEIS_Msk
14943 #define RNG_SR_SEIS_Pos (6U)
14944 #define RNG_SR_SEIS_Msk (0x1UL << RNG_SR_SEIS_Pos) /*!< 0x00000040 */
14945 #define RNG_SR_SEIS RNG_SR_SEIS_Msk
14946
14947 /******************************************************************************/
14948 /* */
14949 /* Real-Time Clock (RTC) */
14950 /* */
14951 /******************************************************************************/
14952 /******************** Bits definition for RTC_TR register *******************/
14953 #define RTC_TR_PM_Pos (22U)
14954 #define RTC_TR_PM_Msk (0x1UL << RTC_TR_PM_Pos) /*!< 0x00400000 */
14955 #define RTC_TR_PM RTC_TR_PM_Msk
14956 #define RTC_TR_HT_Pos (20U)
14957 #define RTC_TR_HT_Msk (0x3UL << RTC_TR_HT_Pos) /*!< 0x00300000 */
14958 #define RTC_TR_HT RTC_TR_HT_Msk
14959 #define RTC_TR_HT_0 (0x1UL << RTC_TR_HT_Pos) /*!< 0x00100000 */
14960 #define RTC_TR_HT_1 (0x2UL << RTC_TR_HT_Pos) /*!< 0x00200000 */
14961 #define RTC_TR_HU_Pos (16U)
14962 #define RTC_TR_HU_Msk (0xFUL << RTC_TR_HU_Pos) /*!< 0x000F0000 */
14963 #define RTC_TR_HU RTC_TR_HU_Msk
14964 #define RTC_TR_HU_0 (0x1UL << RTC_TR_HU_Pos) /*!< 0x00010000 */
14965 #define RTC_TR_HU_1 (0x2UL << RTC_TR_HU_Pos) /*!< 0x00020000 */
14966 #define RTC_TR_HU_2 (0x4UL << RTC_TR_HU_Pos) /*!< 0x00040000 */
14967 #define RTC_TR_HU_3 (0x8UL << RTC_TR_HU_Pos) /*!< 0x00080000 */
14968 #define RTC_TR_MNT_Pos (12U)
14969 #define RTC_TR_MNT_Msk (0x7UL << RTC_TR_MNT_Pos) /*!< 0x00007000 */
14970 #define RTC_TR_MNT RTC_TR_MNT_Msk
14971 #define RTC_TR_MNT_0 (0x1UL << RTC_TR_MNT_Pos) /*!< 0x00001000 */
14972 #define RTC_TR_MNT_1 (0x2UL << RTC_TR_MNT_Pos) /*!< 0x00002000 */
14973 #define RTC_TR_MNT_2 (0x4UL << RTC_TR_MNT_Pos) /*!< 0x00004000 */
14974 #define RTC_TR_MNU_Pos (8U)
14975 #define RTC_TR_MNU_Msk (0xFUL << RTC_TR_MNU_Pos) /*!< 0x00000F00 */
14976 #define RTC_TR_MNU RTC_TR_MNU_Msk
14977 #define RTC_TR_MNU_0 (0x1UL << RTC_TR_MNU_Pos) /*!< 0x00000100 */
14978 #define RTC_TR_MNU_1 (0x2UL << RTC_TR_MNU_Pos) /*!< 0x00000200 */
14979 #define RTC_TR_MNU_2 (0x4UL << RTC_TR_MNU_Pos) /*!< 0x00000400 */
14980 #define RTC_TR_MNU_3 (0x8UL << RTC_TR_MNU_Pos) /*!< 0x00000800 */
14981 #define RTC_TR_ST_Pos (4U)
14982 #define RTC_TR_ST_Msk (0x7UL << RTC_TR_ST_Pos) /*!< 0x00000070 */
14983 #define RTC_TR_ST RTC_TR_ST_Msk
14984 #define RTC_TR_ST_0 (0x1UL << RTC_TR_ST_Pos) /*!< 0x00000010 */
14985 #define RTC_TR_ST_1 (0x2UL << RTC_TR_ST_Pos) /*!< 0x00000020 */
14986 #define RTC_TR_ST_2 (0x4UL << RTC_TR_ST_Pos) /*!< 0x00000040 */
14987 #define RTC_TR_SU_Pos (0U)
14988 #define RTC_TR_SU_Msk (0xFUL << RTC_TR_SU_Pos) /*!< 0x0000000F */
14989 #define RTC_TR_SU RTC_TR_SU_Msk
14990 #define RTC_TR_SU_0 (0x1UL << RTC_TR_SU_Pos) /*!< 0x00000001 */
14991 #define RTC_TR_SU_1 (0x2UL << RTC_TR_SU_Pos) /*!< 0x00000002 */
14992 #define RTC_TR_SU_2 (0x4UL << RTC_TR_SU_Pos) /*!< 0x00000004 */
14993 #define RTC_TR_SU_3 (0x8UL << RTC_TR_SU_Pos) /*!< 0x00000008 */
14994
14995 /******************** Bits definition for RTC_DR register *******************/
14996 #define RTC_DR_YT_Pos (20U)
14997 #define RTC_DR_YT_Msk (0xFUL << RTC_DR_YT_Pos) /*!< 0x00F00000 */
14998 #define RTC_DR_YT RTC_DR_YT_Msk
14999 #define RTC_DR_YT_0 (0x1UL << RTC_DR_YT_Pos) /*!< 0x00100000 */
15000 #define RTC_DR_YT_1 (0x2UL << RTC_DR_YT_Pos) /*!< 0x00200000 */
15001 #define RTC_DR_YT_2 (0x4UL << RTC_DR_YT_Pos) /*!< 0x00400000 */
15002 #define RTC_DR_YT_3 (0x8UL << RTC_DR_YT_Pos) /*!< 0x00800000 */
15003 #define RTC_DR_YU_Pos (16U)
15004 #define RTC_DR_YU_Msk (0xFUL << RTC_DR_YU_Pos) /*!< 0x000F0000 */
15005 #define RTC_DR_YU RTC_DR_YU_Msk
15006 #define RTC_DR_YU_0 (0x1UL << RTC_DR_YU_Pos) /*!< 0x00010000 */
15007 #define RTC_DR_YU_1 (0x2UL << RTC_DR_YU_Pos) /*!< 0x00020000 */
15008 #define RTC_DR_YU_2 (0x4UL << RTC_DR_YU_Pos) /*!< 0x00040000 */
15009 #define RTC_DR_YU_3 (0x8UL << RTC_DR_YU_Pos) /*!< 0x00080000 */
15010 #define RTC_DR_WDU_Pos (13U)
15011 #define RTC_DR_WDU_Msk (0x7UL << RTC_DR_WDU_Pos) /*!< 0x0000E000 */
15012 #define RTC_DR_WDU RTC_DR_WDU_Msk
15013 #define RTC_DR_WDU_0 (0x1UL << RTC_DR_WDU_Pos) /*!< 0x00002000 */
15014 #define RTC_DR_WDU_1 (0x2UL << RTC_DR_WDU_Pos) /*!< 0x00004000 */
15015 #define RTC_DR_WDU_2 (0x4UL << RTC_DR_WDU_Pos) /*!< 0x00008000 */
15016 #define RTC_DR_MT_Pos (12U)
15017 #define RTC_DR_MT_Msk (0x1UL << RTC_DR_MT_Pos) /*!< 0x00001000 */
15018 #define RTC_DR_MT RTC_DR_MT_Msk
15019 #define RTC_DR_MU_Pos (8U)
15020 #define RTC_DR_MU_Msk (0xFUL << RTC_DR_MU_Pos) /*!< 0x00000F00 */
15021 #define RTC_DR_MU RTC_DR_MU_Msk
15022 #define RTC_DR_MU_0 (0x1UL << RTC_DR_MU_Pos) /*!< 0x00000100 */
15023 #define RTC_DR_MU_1 (0x2UL << RTC_DR_MU_Pos) /*!< 0x00000200 */
15024 #define RTC_DR_MU_2 (0x4UL << RTC_DR_MU_Pos) /*!< 0x00000400 */
15025 #define RTC_DR_MU_3 (0x8UL << RTC_DR_MU_Pos) /*!< 0x00000800 */
15026 #define RTC_DR_DT_Pos (4U)
15027 #define RTC_DR_DT_Msk (0x3UL << RTC_DR_DT_Pos) /*!< 0x00000030 */
15028 #define RTC_DR_DT RTC_DR_DT_Msk
15029 #define RTC_DR_DT_0 (0x1UL << RTC_DR_DT_Pos) /*!< 0x00000010 */
15030 #define RTC_DR_DT_1 (0x2UL << RTC_DR_DT_Pos) /*!< 0x00000020 */
15031 #define RTC_DR_DU_Pos (0U)
15032 #define RTC_DR_DU_Msk (0xFUL << RTC_DR_DU_Pos) /*!< 0x0000000F */
15033 #define RTC_DR_DU RTC_DR_DU_Msk
15034 #define RTC_DR_DU_0 (0x1UL << RTC_DR_DU_Pos) /*!< 0x00000001 */
15035 #define RTC_DR_DU_1 (0x2UL << RTC_DR_DU_Pos) /*!< 0x00000002 */
15036 #define RTC_DR_DU_2 (0x4UL << RTC_DR_DU_Pos) /*!< 0x00000004 */
15037 #define RTC_DR_DU_3 (0x8UL << RTC_DR_DU_Pos) /*!< 0x00000008 */
15038
15039 /******************** Bits definition for RTC_CR register *******************/
15040 #define RTC_CR_OUT2EN_Pos (31U)
15041 #define RTC_CR_OUT2EN_Msk (0x1UL << RTC_CR_OUT2EN_Pos) /*!< 0x80000000 */
15042 #define RTC_CR_OUT2EN RTC_CR_OUT2EN_Msk /*!<RTC_OUT2 output enable */
15043 #define RTC_CR_TAMPALRM_TYPE_Pos (30U)
15044 #define RTC_CR_TAMPALRM_TYPE_Msk (0x1UL << RTC_CR_TAMPALRM_TYPE_Pos) /*!< 0x40000000 */
15045 #define RTC_CR_TAMPALRM_TYPE RTC_CR_TAMPALRM_TYPE_Msk /*!<TAMPALARM output type */
15046 #define RTC_CR_TAMPALRM_PU_Pos (29U)
15047 #define RTC_CR_TAMPALRM_PU_Msk (0x1UL << RTC_CR_TAMPALRM_PU_Pos) /*!< 0x20000000 */
15048 #define RTC_CR_TAMPALRM_PU RTC_CR_TAMPALRM_PU_Msk /*!<TAMPALARM output pull-up config */
15049 #define RTC_CR_TAMPOE_Pos (26U)
15050 #define RTC_CR_TAMPOE_Msk (0x1UL << RTC_CR_TAMPOE_Pos) /*!< 0x04000000 */
15051 #define RTC_CR_TAMPOE RTC_CR_TAMPOE_Msk /*!<Tamper detection output enable on TAMPALARM */
15052 #define RTC_CR_TAMPTS_Pos (25U)
15053 #define RTC_CR_TAMPTS_Msk (0x1UL << RTC_CR_TAMPTS_Pos) /*!< 0x02000000 */
15054 #define RTC_CR_TAMPTS RTC_CR_TAMPTS_Msk /*!<Activate timestamp on tamper detection event */
15055 #define RTC_CR_ITSE_Pos (24U)
15056 #define RTC_CR_ITSE_Msk (0x1UL << RTC_CR_ITSE_Pos) /*!< 0x01000000 */
15057 #define RTC_CR_ITSE RTC_CR_ITSE_Msk
15058 #define RTC_CR_COE_Pos (23U)
15059 #define RTC_CR_COE_Msk (0x1UL << RTC_CR_COE_Pos) /*!< 0x00800000 */
15060 #define RTC_CR_COE RTC_CR_COE_Msk
15061 #define RTC_CR_OSEL_Pos (21U)
15062 #define RTC_CR_OSEL_Msk (0x3UL << RTC_CR_OSEL_Pos) /*!< 0x00600000 */
15063 #define RTC_CR_OSEL RTC_CR_OSEL_Msk
15064 #define RTC_CR_OSEL_0 (0x1UL << RTC_CR_OSEL_Pos) /*!< 0x00200000 */
15065 #define RTC_CR_OSEL_1 (0x2UL << RTC_CR_OSEL_Pos) /*!< 0x00400000 */
15066 #define RTC_CR_POL_Pos (20U)
15067 #define RTC_CR_POL_Msk (0x1UL << RTC_CR_POL_Pos) /*!< 0x00100000 */
15068 #define RTC_CR_POL RTC_CR_POL_Msk
15069 #define RTC_CR_COSEL_Pos (19U)
15070 #define RTC_CR_COSEL_Msk (0x1UL << RTC_CR_COSEL_Pos) /*!< 0x00080000 */
15071 #define RTC_CR_COSEL RTC_CR_COSEL_Msk
15072 #define RTC_CR_BKP_Pos (18U)
15073 #define RTC_CR_BKP_Msk (0x1UL << RTC_CR_BKP_Pos) /*!< 0x00040000 */
15074 #define RTC_CR_BKP RTC_CR_BKP_Msk
15075 #define RTC_CR_SUB1H_Pos (17U)
15076 #define RTC_CR_SUB1H_Msk (0x1UL << RTC_CR_SUB1H_Pos) /*!< 0x00020000 */
15077 #define RTC_CR_SUB1H RTC_CR_SUB1H_Msk
15078 #define RTC_CR_ADD1H_Pos (16U)
15079 #define RTC_CR_ADD1H_Msk (0x1UL << RTC_CR_ADD1H_Pos) /*!< 0x00010000 */
15080 #define RTC_CR_ADD1H RTC_CR_ADD1H_Msk
15081 #define RTC_CR_TSIE_Pos (15U)
15082 #define RTC_CR_TSIE_Msk (0x1UL << RTC_CR_TSIE_Pos) /*!< 0x00008000 */
15083 #define RTC_CR_TSIE RTC_CR_TSIE_Msk
15084 #define RTC_CR_WUTIE_Pos (14U)
15085 #define RTC_CR_WUTIE_Msk (0x1UL << RTC_CR_WUTIE_Pos) /*!< 0x00004000 */
15086 #define RTC_CR_WUTIE RTC_CR_WUTIE_Msk
15087 #define RTC_CR_ALRBIE_Pos (13U)
15088 #define RTC_CR_ALRBIE_Msk (0x1UL << RTC_CR_ALRBIE_Pos) /*!< 0x00002000 */
15089 #define RTC_CR_ALRBIE RTC_CR_ALRBIE_Msk
15090 #define RTC_CR_ALRAIE_Pos (12U)
15091 #define RTC_CR_ALRAIE_Msk (0x1UL << RTC_CR_ALRAIE_Pos) /*!< 0x00001000 */
15092 #define RTC_CR_ALRAIE RTC_CR_ALRAIE_Msk
15093 #define RTC_CR_TSE_Pos (11U)
15094 #define RTC_CR_TSE_Msk (0x1UL << RTC_CR_TSE_Pos) /*!< 0x00000800 */
15095 #define RTC_CR_TSE RTC_CR_TSE_Msk
15096 #define RTC_CR_WUTE_Pos (10U)
15097 #define RTC_CR_WUTE_Msk (0x1UL << RTC_CR_WUTE_Pos) /*!< 0x00000400 */
15098 #define RTC_CR_WUTE RTC_CR_WUTE_Msk
15099 #define RTC_CR_ALRBE_Pos (9U)
15100 #define RTC_CR_ALRBE_Msk (0x1UL << RTC_CR_ALRBE_Pos) /*!< 0x00000200 */
15101 #define RTC_CR_ALRBE RTC_CR_ALRBE_Msk
15102 #define RTC_CR_ALRAE_Pos (8U)
15103 #define RTC_CR_ALRAE_Msk (0x1UL << RTC_CR_ALRAE_Pos) /*!< 0x00000100 */
15104 #define RTC_CR_ALRAE RTC_CR_ALRAE_Msk
15105 #define RTC_CR_FMT_Pos (6U)
15106 #define RTC_CR_FMT_Msk (0x1UL << RTC_CR_FMT_Pos) /*!< 0x00000040 */
15107 #define RTC_CR_FMT RTC_CR_FMT_Msk
15108 #define RTC_CR_BYPSHAD_Pos (5U)
15109 #define RTC_CR_BYPSHAD_Msk (0x1UL << RTC_CR_BYPSHAD_Pos) /*!< 0x00000020 */
15110 #define RTC_CR_BYPSHAD RTC_CR_BYPSHAD_Msk
15111 #define RTC_CR_REFCKON_Pos (4U)
15112 #define RTC_CR_REFCKON_Msk (0x1UL << RTC_CR_REFCKON_Pos) /*!< 0x00000010 */
15113 #define RTC_CR_REFCKON RTC_CR_REFCKON_Msk
15114 #define RTC_CR_TSEDGE_Pos (3U)
15115 #define RTC_CR_TSEDGE_Msk (0x1UL << RTC_CR_TSEDGE_Pos) /*!< 0x00000008 */
15116 #define RTC_CR_TSEDGE RTC_CR_TSEDGE_Msk
15117 #define RTC_CR_WUCKSEL_Pos (0U)
15118 #define RTC_CR_WUCKSEL_Msk (0x7UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000007 */
15119 #define RTC_CR_WUCKSEL RTC_CR_WUCKSEL_Msk
15120 #define RTC_CR_WUCKSEL_0 (0x1UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000001 */
15121 #define RTC_CR_WUCKSEL_1 (0x2UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000002 */
15122 #define RTC_CR_WUCKSEL_2 (0x4UL << RTC_CR_WUCKSEL_Pos) /*!< 0x00000004 */
15123
15124 /******************** Bits definition for RTC_ICSR register ******************/
15125 #define RTC_ICSR_RECALPF_Pos (16U)
15126 #define RTC_ICSR_RECALPF_Msk (0x1UL << RTC_ICSR_RECALPF_Pos) /*!< 0x00010000 */
15127 #define RTC_ICSR_RECALPF RTC_ICSR_RECALPF_Msk
15128 #define RTC_ICSR_INIT_Pos (7U)
15129 #define RTC_ICSR_INIT_Msk (0x1UL << RTC_ICSR_INIT_Pos) /*!< 0x00000080 */
15130 #define RTC_ICSR_INIT RTC_ICSR_INIT_Msk
15131 #define RTC_ICSR_INITF_Pos (6U)
15132 #define RTC_ICSR_INITF_Msk (0x1UL << RTC_ICSR_INITF_Pos) /*!< 0x00000040 */
15133 #define RTC_ICSR_INITF RTC_ICSR_INITF_Msk
15134 #define RTC_ICSR_RSF_Pos (5U)
15135 #define RTC_ICSR_RSF_Msk (0x1UL << RTC_ICSR_RSF_Pos) /*!< 0x00000020 */
15136 #define RTC_ICSR_RSF RTC_ICSR_RSF_Msk
15137 #define RTC_ICSR_INITS_Pos (4U)
15138 #define RTC_ICSR_INITS_Msk (0x1UL << RTC_ICSR_INITS_Pos) /*!< 0x00000010 */
15139 #define RTC_ICSR_INITS RTC_ICSR_INITS_Msk
15140 #define RTC_ICSR_SHPF_Pos (3U)
15141 #define RTC_ICSR_SHPF_Msk (0x1UL << RTC_ICSR_SHPF_Pos) /*!< 0x00000008 */
15142 #define RTC_ICSR_SHPF RTC_ICSR_SHPF_Msk
15143 #define RTC_ICSR_WUTWF_Pos (2U)
15144 #define RTC_ICSR_WUTWF_Msk (0x1UL << RTC_ICSR_WUTWF_Pos) /*!< 0x00000004 */
15145 #define RTC_ICSR_WUTWF RTC_ICSR_WUTWF_Msk
15146 #define RTC_ICSR_ALRBWF_Pos (1U)
15147 #define RTC_ICSR_ALRBWF_Msk (0x1UL << RTC_ICSR_ALRBWF_Pos) /*!< 0x00000002 */
15148 #define RTC_ICSR_ALRBWF RTC_ICSR_ALRBWF_Msk
15149 #define RTC_ICSR_ALRAWF_Pos (0U)
15150 #define RTC_ICSR_ALRAWF_Msk (0x1UL << RTC_ICSR_ALRAWF_Pos) /*!< 0x00000001 */
15151 #define RTC_ICSR_ALRAWF RTC_ICSR_ALRAWF_Msk
15152
15153 /******************** Bits definition for RTC_PRER register *****************/
15154 #define RTC_PRER_PREDIV_A_Pos (16U)
15155 #define RTC_PRER_PREDIV_A_Msk (0x7FUL << RTC_PRER_PREDIV_A_Pos) /*!< 0x007F0000 */
15156 #define RTC_PRER_PREDIV_A RTC_PRER_PREDIV_A_Msk
15157 #define RTC_PRER_PREDIV_S_Pos (0U)
15158 #define RTC_PRER_PREDIV_S_Msk (0x7FFFUL << RTC_PRER_PREDIV_S_Pos) /*!< 0x00007FFF */
15159 #define RTC_PRER_PREDIV_S RTC_PRER_PREDIV_S_Msk
15160
15161 /******************** Bits definition for RTC_WUTR register *****************/
15162 #define RTC_WUTR_WUT_Pos (0U)
15163 #define RTC_WUTR_WUT_Msk (0xFFFFUL << RTC_WUTR_WUT_Pos) /*!< 0x0000FFFF */
15164 #define RTC_WUTR_WUT RTC_WUTR_WUT_Msk
15165
15166 /******************** Bits definition for RTC_ALRMAR register ***************/
15167 #define RTC_ALRMAR_MSK4_Pos (31U)
15168 #define RTC_ALRMAR_MSK4_Msk (0x1UL << RTC_ALRMAR_MSK4_Pos) /*!< 0x80000000 */
15169 #define RTC_ALRMAR_MSK4 RTC_ALRMAR_MSK4_Msk
15170 #define RTC_ALRMAR_WDSEL_Pos (30U)
15171 #define RTC_ALRMAR_WDSEL_Msk (0x1UL << RTC_ALRMAR_WDSEL_Pos) /*!< 0x40000000 */
15172 #define RTC_ALRMAR_WDSEL RTC_ALRMAR_WDSEL_Msk
15173 #define RTC_ALRMAR_DT_Pos (28U)
15174 #define RTC_ALRMAR_DT_Msk (0x3UL << RTC_ALRMAR_DT_Pos) /*!< 0x30000000 */
15175 #define RTC_ALRMAR_DT RTC_ALRMAR_DT_Msk
15176 #define RTC_ALRMAR_DT_0 (0x1UL << RTC_ALRMAR_DT_Pos) /*!< 0x10000000 */
15177 #define RTC_ALRMAR_DT_1 (0x2UL << RTC_ALRMAR_DT_Pos) /*!< 0x20000000 */
15178 #define RTC_ALRMAR_DU_Pos (24U)
15179 #define RTC_ALRMAR_DU_Msk (0xFUL << RTC_ALRMAR_DU_Pos) /*!< 0x0F000000 */
15180 #define RTC_ALRMAR_DU RTC_ALRMAR_DU_Msk
15181 #define RTC_ALRMAR_DU_0 (0x1UL << RTC_ALRMAR_DU_Pos) /*!< 0x01000000 */
15182 #define RTC_ALRMAR_DU_1 (0x2UL << RTC_ALRMAR_DU_Pos) /*!< 0x02000000 */
15183 #define RTC_ALRMAR_DU_2 (0x4UL << RTC_ALRMAR_DU_Pos) /*!< 0x04000000 */
15184 #define RTC_ALRMAR_DU_3 (0x8UL << RTC_ALRMAR_DU_Pos) /*!< 0x08000000 */
15185 #define RTC_ALRMAR_MSK3_Pos (23U)
15186 #define RTC_ALRMAR_MSK3_Msk (0x1UL << RTC_ALRMAR_MSK3_Pos) /*!< 0x00800000 */
15187 #define RTC_ALRMAR_MSK3 RTC_ALRMAR_MSK3_Msk
15188 #define RTC_ALRMAR_PM_Pos (22U)
15189 #define RTC_ALRMAR_PM_Msk (0x1UL << RTC_ALRMAR_PM_Pos) /*!< 0x00400000 */
15190 #define RTC_ALRMAR_PM RTC_ALRMAR_PM_Msk
15191 #define RTC_ALRMAR_HT_Pos (20U)
15192 #define RTC_ALRMAR_HT_Msk (0x3UL << RTC_ALRMAR_HT_Pos) /*!< 0x00300000 */
15193 #define RTC_ALRMAR_HT RTC_ALRMAR_HT_Msk
15194 #define RTC_ALRMAR_HT_0 (0x1UL << RTC_ALRMAR_HT_Pos) /*!< 0x00100000 */
15195 #define RTC_ALRMAR_HT_1 (0x2UL << RTC_ALRMAR_HT_Pos) /*!< 0x00200000 */
15196 #define RTC_ALRMAR_HU_Pos (16U)
15197 #define RTC_ALRMAR_HU_Msk (0xFUL << RTC_ALRMAR_HU_Pos) /*!< 0x000F0000 */
15198 #define RTC_ALRMAR_HU RTC_ALRMAR_HU_Msk
15199 #define RTC_ALRMAR_HU_0 (0x1UL << RTC_ALRMAR_HU_Pos) /*!< 0x00010000 */
15200 #define RTC_ALRMAR_HU_1 (0x2UL << RTC_ALRMAR_HU_Pos) /*!< 0x00020000 */
15201 #define RTC_ALRMAR_HU_2 (0x4UL << RTC_ALRMAR_HU_Pos) /*!< 0x00040000 */
15202 #define RTC_ALRMAR_HU_3 (0x8UL << RTC_ALRMAR_HU_Pos) /*!< 0x00080000 */
15203 #define RTC_ALRMAR_MSK2_Pos (15U)
15204 #define RTC_ALRMAR_MSK2_Msk (0x1UL << RTC_ALRMAR_MSK2_Pos) /*!< 0x00008000 */
15205 #define RTC_ALRMAR_MSK2 RTC_ALRMAR_MSK2_Msk
15206 #define RTC_ALRMAR_MNT_Pos (12U)
15207 #define RTC_ALRMAR_MNT_Msk (0x7UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00007000 */
15208 #define RTC_ALRMAR_MNT RTC_ALRMAR_MNT_Msk
15209 #define RTC_ALRMAR_MNT_0 (0x1UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00001000 */
15210 #define RTC_ALRMAR_MNT_1 (0x2UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00002000 */
15211 #define RTC_ALRMAR_MNT_2 (0x4UL << RTC_ALRMAR_MNT_Pos) /*!< 0x00004000 */
15212 #define RTC_ALRMAR_MNU_Pos (8U)
15213 #define RTC_ALRMAR_MNU_Msk (0xFUL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000F00 */
15214 #define RTC_ALRMAR_MNU RTC_ALRMAR_MNU_Msk
15215 #define RTC_ALRMAR_MNU_0 (0x1UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000100 */
15216 #define RTC_ALRMAR_MNU_1 (0x2UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000200 */
15217 #define RTC_ALRMAR_MNU_2 (0x4UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000400 */
15218 #define RTC_ALRMAR_MNU_3 (0x8UL << RTC_ALRMAR_MNU_Pos) /*!< 0x00000800 */
15219 #define RTC_ALRMAR_MSK1_Pos (7U)
15220 #define RTC_ALRMAR_MSK1_Msk (0x1UL << RTC_ALRMAR_MSK1_Pos) /*!< 0x00000080 */
15221 #define RTC_ALRMAR_MSK1 RTC_ALRMAR_MSK1_Msk
15222 #define RTC_ALRMAR_ST_Pos (4U)
15223 #define RTC_ALRMAR_ST_Msk (0x7UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000070 */
15224 #define RTC_ALRMAR_ST RTC_ALRMAR_ST_Msk
15225 #define RTC_ALRMAR_ST_0 (0x1UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000010 */
15226 #define RTC_ALRMAR_ST_1 (0x2UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000020 */
15227 #define RTC_ALRMAR_ST_2 (0x4UL << RTC_ALRMAR_ST_Pos) /*!< 0x00000040 */
15228 #define RTC_ALRMAR_SU_Pos (0U)
15229 #define RTC_ALRMAR_SU_Msk (0xFUL << RTC_ALRMAR_SU_Pos) /*!< 0x0000000F */
15230 #define RTC_ALRMAR_SU RTC_ALRMAR_SU_Msk
15231 #define RTC_ALRMAR_SU_0 (0x1UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000001 */
15232 #define RTC_ALRMAR_SU_1 (0x2UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000002 */
15233 #define RTC_ALRMAR_SU_2 (0x4UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000004 */
15234 #define RTC_ALRMAR_SU_3 (0x8UL << RTC_ALRMAR_SU_Pos) /*!< 0x00000008 */
15235
15236 /******************** Bits definition for RTC_ALRMBR register ***************/
15237 #define RTC_ALRMBR_MSK4_Pos (31U)
15238 #define RTC_ALRMBR_MSK4_Msk (0x1UL << RTC_ALRMBR_MSK4_Pos) /*!< 0x80000000 */
15239 #define RTC_ALRMBR_MSK4 RTC_ALRMBR_MSK4_Msk
15240 #define RTC_ALRMBR_WDSEL_Pos (30U)
15241 #define RTC_ALRMBR_WDSEL_Msk (0x1UL << RTC_ALRMBR_WDSEL_Pos) /*!< 0x40000000 */
15242 #define RTC_ALRMBR_WDSEL RTC_ALRMBR_WDSEL_Msk
15243 #define RTC_ALRMBR_DT_Pos (28U)
15244 #define RTC_ALRMBR_DT_Msk (0x3UL << RTC_ALRMBR_DT_Pos) /*!< 0x30000000 */
15245 #define RTC_ALRMBR_DT RTC_ALRMBR_DT_Msk
15246 #define RTC_ALRMBR_DT_0 (0x1UL << RTC_ALRMBR_DT_Pos) /*!< 0x10000000 */
15247 #define RTC_ALRMBR_DT_1 (0x2UL << RTC_ALRMBR_DT_Pos) /*!< 0x20000000 */
15248 #define RTC_ALRMBR_DU_Pos (24U)
15249 #define RTC_ALRMBR_DU_Msk (0xFUL << RTC_ALRMBR_DU_Pos) /*!< 0x0F000000 */
15250 #define RTC_ALRMBR_DU RTC_ALRMBR_DU_Msk
15251 #define RTC_ALRMBR_DU_0 (0x1UL << RTC_ALRMBR_DU_Pos) /*!< 0x01000000 */
15252 #define RTC_ALRMBR_DU_1 (0x2UL << RTC_ALRMBR_DU_Pos) /*!< 0x02000000 */
15253 #define RTC_ALRMBR_DU_2 (0x4UL << RTC_ALRMBR_DU_Pos) /*!< 0x04000000 */
15254 #define RTC_ALRMBR_DU_3 (0x8UL << RTC_ALRMBR_DU_Pos) /*!< 0x08000000 */
15255 #define RTC_ALRMBR_MSK3_Pos (23U)
15256 #define RTC_ALRMBR_MSK3_Msk (0x1UL << RTC_ALRMBR_MSK3_Pos) /*!< 0x00800000 */
15257 #define RTC_ALRMBR_MSK3 RTC_ALRMBR_MSK3_Msk
15258 #define RTC_ALRMBR_PM_Pos (22U)
15259 #define RTC_ALRMBR_PM_Msk (0x1UL << RTC_ALRMBR_PM_Pos) /*!< 0x00400000 */
15260 #define RTC_ALRMBR_PM RTC_ALRMBR_PM_Msk
15261 #define RTC_ALRMBR_HT_Pos (20U)
15262 #define RTC_ALRMBR_HT_Msk (0x3UL << RTC_ALRMBR_HT_Pos) /*!< 0x00300000 */
15263 #define RTC_ALRMBR_HT RTC_ALRMBR_HT_Msk
15264 #define RTC_ALRMBR_HT_0 (0x1UL << RTC_ALRMBR_HT_Pos) /*!< 0x00100000 */
15265 #define RTC_ALRMBR_HT_1 (0x2UL << RTC_ALRMBR_HT_Pos) /*!< 0x00200000 */
15266 #define RTC_ALRMBR_HU_Pos (16U)
15267 #define RTC_ALRMBR_HU_Msk (0xFUL << RTC_ALRMBR_HU_Pos) /*!< 0x000F0000 */
15268 #define RTC_ALRMBR_HU RTC_ALRMBR_HU_Msk
15269 #define RTC_ALRMBR_HU_0 (0x1UL << RTC_ALRMBR_HU_Pos) /*!< 0x00010000 */
15270 #define RTC_ALRMBR_HU_1 (0x2UL << RTC_ALRMBR_HU_Pos) /*!< 0x00020000 */
15271 #define RTC_ALRMBR_HU_2 (0x4UL << RTC_ALRMBR_HU_Pos) /*!< 0x00040000 */
15272 #define RTC_ALRMBR_HU_3 (0x8UL << RTC_ALRMBR_HU_Pos) /*!< 0x00080000 */
15273 #define RTC_ALRMBR_MSK2_Pos (15U)
15274 #define RTC_ALRMBR_MSK2_Msk (0x1UL << RTC_ALRMBR_MSK2_Pos) /*!< 0x00008000 */
15275 #define RTC_ALRMBR_MSK2 RTC_ALRMBR_MSK2_Msk
15276 #define RTC_ALRMBR_MNT_Pos (12U)
15277 #define RTC_ALRMBR_MNT_Msk (0x7UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00007000 */
15278 #define RTC_ALRMBR_MNT RTC_ALRMBR_MNT_Msk
15279 #define RTC_ALRMBR_MNT_0 (0x1UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00001000 */
15280 #define RTC_ALRMBR_MNT_1 (0x2UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00002000 */
15281 #define RTC_ALRMBR_MNT_2 (0x4UL << RTC_ALRMBR_MNT_Pos) /*!< 0x00004000 */
15282 #define RTC_ALRMBR_MNU_Pos (8U)
15283 #define RTC_ALRMBR_MNU_Msk (0xFUL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000F00 */
15284 #define RTC_ALRMBR_MNU RTC_ALRMBR_MNU_Msk
15285 #define RTC_ALRMBR_MNU_0 (0x1UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000100 */
15286 #define RTC_ALRMBR_MNU_1 (0x2UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000200 */
15287 #define RTC_ALRMBR_MNU_2 (0x4UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000400 */
15288 #define RTC_ALRMBR_MNU_3 (0x8UL << RTC_ALRMBR_MNU_Pos) /*!< 0x00000800 */
15289 #define RTC_ALRMBR_MSK1_Pos (7U)
15290 #define RTC_ALRMBR_MSK1_Msk (0x1UL << RTC_ALRMBR_MSK1_Pos) /*!< 0x00000080 */
15291 #define RTC_ALRMBR_MSK1 RTC_ALRMBR_MSK1_Msk
15292 #define RTC_ALRMBR_ST_Pos (4U)
15293 #define RTC_ALRMBR_ST_Msk (0x7UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000070 */
15294 #define RTC_ALRMBR_ST RTC_ALRMBR_ST_Msk
15295 #define RTC_ALRMBR_ST_0 (0x1UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000010 */
15296 #define RTC_ALRMBR_ST_1 (0x2UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000020 */
15297 #define RTC_ALRMBR_ST_2 (0x4UL << RTC_ALRMBR_ST_Pos) /*!< 0x00000040 */
15298 #define RTC_ALRMBR_SU_Pos (0U)
15299 #define RTC_ALRMBR_SU_Msk (0xFUL << RTC_ALRMBR_SU_Pos) /*!< 0x0000000F */
15300 #define RTC_ALRMBR_SU RTC_ALRMBR_SU_Msk
15301 #define RTC_ALRMBR_SU_0 (0x1UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000001 */
15302 #define RTC_ALRMBR_SU_1 (0x2UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000002 */
15303 #define RTC_ALRMBR_SU_2 (0x4UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000004 */
15304 #define RTC_ALRMBR_SU_3 (0x8UL << RTC_ALRMBR_SU_Pos) /*!< 0x00000008 */
15305
15306 /******************** Bits definition for RTC_WPR register ******************/
15307 #define RTC_WPR_KEY_Pos (0U)
15308 #define RTC_WPR_KEY_Msk (0xFFUL << RTC_WPR_KEY_Pos) /*!< 0x000000FF */
15309 #define RTC_WPR_KEY RTC_WPR_KEY_Msk
15310
15311 /******************** Bits definition for RTC_SSR register ******************/
15312 #define RTC_SSR_SS_Pos (0U)
15313 #define RTC_SSR_SS_Msk (0xFFFFUL << RTC_SSR_SS_Pos) /*!< 0x0000FFFF */
15314 #define RTC_SSR_SS RTC_SSR_SS_Msk
15315
15316 /******************** Bits definition for RTC_SHIFTR register ***************/
15317 #define RTC_SHIFTR_SUBFS_Pos (0U)
15318 #define RTC_SHIFTR_SUBFS_Msk (0x7FFFUL << RTC_SHIFTR_SUBFS_Pos) /*!< 0x00007FFF */
15319 #define RTC_SHIFTR_SUBFS RTC_SHIFTR_SUBFS_Msk
15320 #define RTC_SHIFTR_ADD1S_Pos (31U)
15321 #define RTC_SHIFTR_ADD1S_Msk (0x1UL << RTC_SHIFTR_ADD1S_Pos) /*!< 0x80000000 */
15322 #define RTC_SHIFTR_ADD1S RTC_SHIFTR_ADD1S_Msk
15323
15324 /******************** Bits definition for RTC_TSTR register *****************/
15325 #define RTC_TSTR_PM_Pos (22U)
15326 #define RTC_TSTR_PM_Msk (0x1UL << RTC_TSTR_PM_Pos) /*!< 0x00400000 */
15327 #define RTC_TSTR_PM RTC_TSTR_PM_Msk
15328 #define RTC_TSTR_HT_Pos (20U)
15329 #define RTC_TSTR_HT_Msk (0x3UL << RTC_TSTR_HT_Pos) /*!< 0x00300000 */
15330 #define RTC_TSTR_HT RTC_TSTR_HT_Msk
15331 #define RTC_TSTR_HT_0 (0x1UL << RTC_TSTR_HT_Pos) /*!< 0x00100000 */
15332 #define RTC_TSTR_HT_1 (0x2UL << RTC_TSTR_HT_Pos) /*!< 0x00200000 */
15333 #define RTC_TSTR_HU_Pos (16U)
15334 #define RTC_TSTR_HU_Msk (0xFUL << RTC_TSTR_HU_Pos) /*!< 0x000F0000 */
15335 #define RTC_TSTR_HU RTC_TSTR_HU_Msk
15336 #define RTC_TSTR_HU_0 (0x1UL << RTC_TSTR_HU_Pos) /*!< 0x00010000 */
15337 #define RTC_TSTR_HU_1 (0x2UL << RTC_TSTR_HU_Pos) /*!< 0x00020000 */
15338 #define RTC_TSTR_HU_2 (0x4UL << RTC_TSTR_HU_Pos) /*!< 0x00040000 */
15339 #define RTC_TSTR_HU_3 (0x8UL << RTC_TSTR_HU_Pos) /*!< 0x00080000 */
15340 #define RTC_TSTR_MNT_Pos (12U)
15341 #define RTC_TSTR_MNT_Msk (0x7UL << RTC_TSTR_MNT_Pos) /*!< 0x00007000 */
15342 #define RTC_TSTR_MNT RTC_TSTR_MNT_Msk
15343 #define RTC_TSTR_MNT_0 (0x1UL << RTC_TSTR_MNT_Pos) /*!< 0x00001000 */
15344 #define RTC_TSTR_MNT_1 (0x2UL << RTC_TSTR_MNT_Pos) /*!< 0x00002000 */
15345 #define RTC_TSTR_MNT_2 (0x4UL << RTC_TSTR_MNT_Pos) /*!< 0x00004000 */
15346 #define RTC_TSTR_MNU_Pos (8U)
15347 #define RTC_TSTR_MNU_Msk (0xFUL << RTC_TSTR_MNU_Pos) /*!< 0x00000F00 */
15348 #define RTC_TSTR_MNU RTC_TSTR_MNU_Msk
15349 #define RTC_TSTR_MNU_0 (0x1UL << RTC_TSTR_MNU_Pos) /*!< 0x00000100 */
15350 #define RTC_TSTR_MNU_1 (0x2UL << RTC_TSTR_MNU_Pos) /*!< 0x00000200 */
15351 #define RTC_TSTR_MNU_2 (0x4UL << RTC_TSTR_MNU_Pos) /*!< 0x00000400 */
15352 #define RTC_TSTR_MNU_3 (0x8UL << RTC_TSTR_MNU_Pos) /*!< 0x00000800 */
15353 #define RTC_TSTR_ST_Pos (4U)
15354 #define RTC_TSTR_ST_Msk (0x7UL << RTC_TSTR_ST_Pos) /*!< 0x00000070 */
15355 #define RTC_TSTR_ST RTC_TSTR_ST_Msk
15356 #define RTC_TSTR_ST_0 (0x1UL << RTC_TSTR_ST_Pos) /*!< 0x00000010 */
15357 #define RTC_TSTR_ST_1 (0x2UL << RTC_TSTR_ST_Pos) /*!< 0x00000020 */
15358 #define RTC_TSTR_ST_2 (0x4UL << RTC_TSTR_ST_Pos) /*!< 0x00000040 */
15359 #define RTC_TSTR_SU_Pos (0U)
15360 #define RTC_TSTR_SU_Msk (0xFUL << RTC_TSTR_SU_Pos) /*!< 0x0000000F */
15361 #define RTC_TSTR_SU RTC_TSTR_SU_Msk
15362 #define RTC_TSTR_SU_0 (0x1UL << RTC_TSTR_SU_Pos) /*!< 0x00000001 */
15363 #define RTC_TSTR_SU_1 (0x2UL << RTC_TSTR_SU_Pos) /*!< 0x00000002 */
15364 #define RTC_TSTR_SU_2 (0x4UL << RTC_TSTR_SU_Pos) /*!< 0x00000004 */
15365 #define RTC_TSTR_SU_3 (0x8UL << RTC_TSTR_SU_Pos) /*!< 0x00000008 */
15366
15367 /******************** Bits definition for RTC_TSDR register *****************/
15368 #define RTC_TSDR_WDU_Pos (13U)
15369 #define RTC_TSDR_WDU_Msk (0x7UL << RTC_TSDR_WDU_Pos) /*!< 0x0000E000 */
15370 #define RTC_TSDR_WDU RTC_TSDR_WDU_Msk
15371 #define RTC_TSDR_WDU_0 (0x1UL << RTC_TSDR_WDU_Pos) /*!< 0x00002000 */
15372 #define RTC_TSDR_WDU_1 (0x2UL << RTC_TSDR_WDU_Pos) /*!< 0x00004000 */
15373 #define RTC_TSDR_WDU_2 (0x4UL << RTC_TSDR_WDU_Pos) /*!< 0x00008000 */
15374 #define RTC_TSDR_MT_Pos (12U)
15375 #define RTC_TSDR_MT_Msk (0x1UL << RTC_TSDR_MT_Pos) /*!< 0x00001000 */
15376 #define RTC_TSDR_MT RTC_TSDR_MT_Msk
15377 #define RTC_TSDR_MU_Pos (8U)
15378 #define RTC_TSDR_MU_Msk (0xFUL << RTC_TSDR_MU_Pos) /*!< 0x00000F00 */
15379 #define RTC_TSDR_MU RTC_TSDR_MU_Msk
15380 #define RTC_TSDR_MU_0 (0x1UL << RTC_TSDR_MU_Pos) /*!< 0x00000100 */
15381 #define RTC_TSDR_MU_1 (0x2UL << RTC_TSDR_MU_Pos) /*!< 0x00000200 */
15382 #define RTC_TSDR_MU_2 (0x4UL << RTC_TSDR_MU_Pos) /*!< 0x00000400 */
15383 #define RTC_TSDR_MU_3 (0x8UL << RTC_TSDR_MU_Pos) /*!< 0x00000800 */
15384 #define RTC_TSDR_DT_Pos (4U)
15385 #define RTC_TSDR_DT_Msk (0x3UL << RTC_TSDR_DT_Pos) /*!< 0x00000030 */
15386 #define RTC_TSDR_DT RTC_TSDR_DT_Msk
15387 #define RTC_TSDR_DT_0 (0x1UL << RTC_TSDR_DT_Pos) /*!< 0x00000010 */
15388 #define RTC_TSDR_DT_1 (0x2UL << RTC_TSDR_DT_Pos) /*!< 0x00000020 */
15389 #define RTC_TSDR_DU_Pos (0U)
15390 #define RTC_TSDR_DU_Msk (0xFUL << RTC_TSDR_DU_Pos) /*!< 0x0000000F */
15391 #define RTC_TSDR_DU RTC_TSDR_DU_Msk
15392 #define RTC_TSDR_DU_0 (0x1UL << RTC_TSDR_DU_Pos) /*!< 0x00000001 */
15393 #define RTC_TSDR_DU_1 (0x2UL << RTC_TSDR_DU_Pos) /*!< 0x00000002 */
15394 #define RTC_TSDR_DU_2 (0x4UL << RTC_TSDR_DU_Pos) /*!< 0x00000004 */
15395 #define RTC_TSDR_DU_3 (0x8UL << RTC_TSDR_DU_Pos) /*!< 0x00000008 */
15396
15397 /******************** Bits definition for RTC_TSSSR register ****************/
15398 #define RTC_TSSSR_SS_Pos (0U)
15399 #define RTC_TSSSR_SS_Msk (0xFFFFUL << RTC_TSSSR_SS_Pos) /*!< 0x0000FFFF */
15400 #define RTC_TSSSR_SS RTC_TSSSR_SS_Msk
15401
15402 /******************** Bits definition for RTC_CALR register *****************/
15403 #define RTC_CALR_CALP_Pos (15U)
15404 #define RTC_CALR_CALP_Msk (0x1UL << RTC_CALR_CALP_Pos) /*!< 0x00008000 */
15405 #define RTC_CALR_CALP RTC_CALR_CALP_Msk
15406 #define RTC_CALR_CALW8_Pos (14U)
15407 #define RTC_CALR_CALW8_Msk (0x1UL << RTC_CALR_CALW8_Pos) /*!< 0x00004000 */
15408 #define RTC_CALR_CALW8 RTC_CALR_CALW8_Msk
15409 #define RTC_CALR_CALW16_Pos (13U)
15410 #define RTC_CALR_CALW16_Msk (0x1UL << RTC_CALR_CALW16_Pos) /*!< 0x00002000 */
15411 #define RTC_CALR_CALW16 RTC_CALR_CALW16_Msk
15412 #define RTC_CALR_CALM_Pos (0U)
15413 #define RTC_CALR_CALM_Msk (0x1FFUL << RTC_CALR_CALM_Pos) /*!< 0x000001FF */
15414 #define RTC_CALR_CALM RTC_CALR_CALM_Msk
15415 #define RTC_CALR_CALM_0 (0x001UL << RTC_CALR_CALM_Pos) /*!< 0x00000001 */
15416 #define RTC_CALR_CALM_1 (0x002UL << RTC_CALR_CALM_Pos) /*!< 0x00000002 */
15417 #define RTC_CALR_CALM_2 (0x004UL << RTC_CALR_CALM_Pos) /*!< 0x00000004 */
15418 #define RTC_CALR_CALM_3 (0x008UL << RTC_CALR_CALM_Pos) /*!< 0x00000008 */
15419 #define RTC_CALR_CALM_4 (0x010UL << RTC_CALR_CALM_Pos) /*!< 0x00000010 */
15420 #define RTC_CALR_CALM_5 (0x020UL << RTC_CALR_CALM_Pos) /*!< 0x00000020 */
15421 #define RTC_CALR_CALM_6 (0x040UL << RTC_CALR_CALM_Pos) /*!< 0x00000040 */
15422 #define RTC_CALR_CALM_7 (0x080UL << RTC_CALR_CALM_Pos) /*!< 0x00000080 */
15423 #define RTC_CALR_CALM_8 (0x100UL << RTC_CALR_CALM_Pos) /*!< 0x00000100 */
15424
15425
15426 /******************** Bits definition for RTC_ALRMASSR register *************/
15427 #define RTC_ALRMASSR_MASKSS_Pos (24U)
15428 #define RTC_ALRMASSR_MASKSS_Msk (0xFUL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x0F000000 */
15429 #define RTC_ALRMASSR_MASKSS RTC_ALRMASSR_MASKSS_Msk
15430 #define RTC_ALRMASSR_MASKSS_0 (0x1UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x01000000 */
15431 #define RTC_ALRMASSR_MASKSS_1 (0x2UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x02000000 */
15432 #define RTC_ALRMASSR_MASKSS_2 (0x4UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x04000000 */
15433 #define RTC_ALRMASSR_MASKSS_3 (0x8UL << RTC_ALRMASSR_MASKSS_Pos) /*!< 0x08000000 */
15434 #define RTC_ALRMASSR_SS_Pos (0U)
15435 #define RTC_ALRMASSR_SS_Msk (0x7FFFUL << RTC_ALRMASSR_SS_Pos) /*!< 0x00007FFF */
15436 #define RTC_ALRMASSR_SS RTC_ALRMASSR_SS_Msk
15437
15438 /******************** Bits definition for RTC_ALRMBSSR register *************/
15439 #define RTC_ALRMBSSR_MASKSS_Pos (24U)
15440 #define RTC_ALRMBSSR_MASKSS_Msk (0xFUL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x0F000000 */
15441 #define RTC_ALRMBSSR_MASKSS RTC_ALRMBSSR_MASKSS_Msk
15442 #define RTC_ALRMBSSR_MASKSS_0 (0x1UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x01000000 */
15443 #define RTC_ALRMBSSR_MASKSS_1 (0x2UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x02000000 */
15444 #define RTC_ALRMBSSR_MASKSS_2 (0x4UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x04000000 */
15445 #define RTC_ALRMBSSR_MASKSS_3 (0x8UL << RTC_ALRMBSSR_MASKSS_Pos) /*!< 0x08000000 */
15446 #define RTC_ALRMBSSR_SS_Pos (0U)
15447 #define RTC_ALRMBSSR_SS_Msk (0x7FFFUL << RTC_ALRMBSSR_SS_Pos) /*!< 0x00007FFF */
15448 #define RTC_ALRMBSSR_SS RTC_ALRMBSSR_SS_Msk
15449
15450
15451 /******************** Bits definition for RTC_SR register *******************/
15452 #define RTC_SR_ITSF_Pos (5U)
15453 #define RTC_SR_ITSF_Msk (0x1UL << RTC_SR_ITSF_Pos) /*!< 0x00000020 */
15454 #define RTC_SR_ITSF RTC_SR_ITSF_Msk
15455 #define RTC_SR_TSOVF_Pos (4U)
15456 #define RTC_SR_TSOVF_Msk (0x1UL << RTC_SR_TSOVF_Pos) /*!< 0x00000010 */
15457 #define RTC_SR_TSOVF RTC_SR_TSOVF_Msk
15458 #define RTC_SR_TSF_Pos (3U)
15459 #define RTC_SR_TSF_Msk (0x1UL << RTC_SR_TSF_Pos) /*!< 0x00000008 */
15460 #define RTC_SR_TSF RTC_SR_TSF_Msk
15461 #define RTC_SR_WUTF_Pos (2U)
15462 #define RTC_SR_WUTF_Msk (0x1UL << RTC_SR_WUTF_Pos) /*!< 0x00000004 */
15463 #define RTC_SR_WUTF RTC_SR_WUTF_Msk
15464 #define RTC_SR_ALRBF_Pos (1U)
15465 #define RTC_SR_ALRBF_Msk (0x1UL << RTC_SR_ALRBF_Pos) /*!< 0x00000002 */
15466 #define RTC_SR_ALRBF RTC_SR_ALRBF_Msk
15467 #define RTC_SR_ALRAF_Pos (0U)
15468 #define RTC_SR_ALRAF_Msk (0x1UL << RTC_SR_ALRAF_Pos) /*!< 0x00000001 */
15469 #define RTC_SR_ALRAF RTC_SR_ALRAF_Msk
15470
15471 /******************** Bits definition for RTC_MISR register *****************/
15472 #define RTC_MISR_ITSMF_Pos (5U)
15473 #define RTC_MISR_ITSMF_Msk (0x1UL << RTC_MISR_ITSMF_Pos) /*!< 0x00000020 */
15474 #define RTC_MISR_ITSMF RTC_MISR_ITSMF_Msk
15475 #define RTC_MISR_TSOVMF_Pos (4U)
15476 #define RTC_MISR_TSOVMF_Msk (0x1UL << RTC_MISR_TSOVMF_Pos) /*!< 0x00000010 */
15477 #define RTC_MISR_TSOVMF RTC_MISR_TSOVMF_Msk
15478 #define RTC_MISR_TSMF_Pos (3U)
15479 #define RTC_MISR_TSMF_Msk (0x1UL << RTC_MISR_TSMF_Pos) /*!< 0x00000008 */
15480 #define RTC_MISR_TSMF RTC_MISR_TSMF_Msk
15481 #define RTC_MISR_WUTMF_Pos (2U)
15482 #define RTC_MISR_WUTMF_Msk (0x1UL << RTC_MISR_WUTMF_Pos) /*!< 0x00000004 */
15483 #define RTC_MISR_WUTMF RTC_MISR_WUTMF_Msk
15484 #define RTC_MISR_ALRBMF_Pos (1U)
15485 #define RTC_MISR_ALRBMF_Msk (0x1UL << RTC_MISR_ALRBMF_Pos) /*!< 0x00000002 */
15486 #define RTC_MISR_ALRBMF RTC_MISR_ALRBMF_Msk
15487 #define RTC_MISR_ALRAMF_Pos (0U)
15488 #define RTC_MISR_ALRAMF_Msk (0x1UL << RTC_MISR_ALRAMF_Pos) /*!< 0x00000001 */
15489 #define RTC_MISR_ALRAMF RTC_MISR_ALRAMF_Msk
15490
15491 /******************** Bits definition for RTC_SCR register ******************/
15492 #define RTC_SCR_CITSF_Pos (5U)
15493 #define RTC_SCR_CITSF_Msk (0x1UL << RTC_SCR_CITSF_Pos) /*!< 0x00000020 */
15494 #define RTC_SCR_CITSF RTC_SCR_CITSF_Msk
15495 #define RTC_SCR_CTSOVF_Pos (4U)
15496 #define RTC_SCR_CTSOVF_Msk (0x1UL << RTC_SCR_CTSOVF_Pos) /*!< 0x00000010 */
15497 #define RTC_SCR_CTSOVF RTC_SCR_CTSOVF_Msk
15498 #define RTC_SCR_CTSF_Pos (3U)
15499 #define RTC_SCR_CTSF_Msk (0x1UL << RTC_SCR_CTSF_Pos) /*!< 0x00000008 */
15500 #define RTC_SCR_CTSF RTC_SCR_CTSF_Msk
15501 #define RTC_SCR_CWUTF_Pos (2U)
15502 #define RTC_SCR_CWUTF_Msk (0x1UL << RTC_SCR_CWUTF_Pos) /*!< 0x00000004 */
15503 #define RTC_SCR_CWUTF RTC_SCR_CWUTF_Msk
15504 #define RTC_SCR_CALRBF_Pos (1U)
15505 #define RTC_SCR_CALRBF_Msk (0x1UL << RTC_SCR_CALRBF_Pos) /*!< 0x00000002 */
15506 #define RTC_SCR_CALRBF RTC_SCR_CALRBF_Msk
15507 #define RTC_SCR_CALRAF_Pos (0U)
15508 #define RTC_SCR_CALRAF_Msk (0x1UL << RTC_SCR_CALRAF_Pos) /*!< 0x00000001 */
15509 #define RTC_SCR_CALRAF RTC_SCR_CALRAF_Msk
15510
15511 /******************************************************************************/
15512 /* */
15513 /* Tamper and backup register (TAMP) */
15514 /* */
15515 /******************************************************************************/
15516 /******************** Bits definition for TAMP_CR1 register *****************/
15517 #define TAMP_CR1_TAMP1E_Pos (0U)
15518 #define TAMP_CR1_TAMP1E_Msk (0x1UL << TAMP_CR1_TAMP1E_Pos) /*!< 0x00000001 */
15519 #define TAMP_CR1_TAMP1E TAMP_CR1_TAMP1E_Msk
15520 #define TAMP_CR1_TAMP2E_Pos (1U)
15521 #define TAMP_CR1_TAMP2E_Msk (0x1UL << TAMP_CR1_TAMP2E_Pos) /*!< 0x00000002 */
15522 #define TAMP_CR1_TAMP2E TAMP_CR1_TAMP2E_Msk
15523 #define TAMP_CR1_TAMP3E_Pos (2U)
15524 #define TAMP_CR1_TAMP3E_Msk (0x1UL << TAMP_CR1_TAMP3E_Pos) /*!< 0x00000004 */
15525 #define TAMP_CR1_TAMP3E TAMP_CR1_TAMP3E_Msk
15526 #define TAMP_CR1_ITAMP1E_Pos (16U)
15527 #define TAMP_CR1_ITAMP1E_Msk (0x1UL << TAMP_CR1_ITAMP1E_Pos) /*!< 0x00010000 */
15528 #define TAMP_CR1_ITAMP1E TAMP_CR1_ITAMP1E_Msk
15529 #define TAMP_CR1_ITAMP2E_Pos (17U)
15530 #define TAMP_CR1_ITAMP2E_Msk (0x1UL << TAMP_CR1_ITAMP2E_Pos) /*!< 0x00020000 */
15531 #define TAMP_CR1_ITAMP2E TAMP_CR1_ITAMP2E_Msk
15532 #define TAMP_CR1_ITAMP3E_Pos (18U)
15533 #define TAMP_CR1_ITAMP3E_Msk (0x1UL << TAMP_CR1_ITAMP3E_Pos) /*!< 0x00040000 */
15534 #define TAMP_CR1_ITAMP3E TAMP_CR1_ITAMP3E_Msk
15535 #define TAMP_CR1_ITAMP4E_Pos (19U)
15536 #define TAMP_CR1_ITAMP4E_Msk (0x1UL << TAMP_CR1_ITAMP4E_Pos) /*!< 0x00080000 */
15537 #define TAMP_CR1_ITAMP4E TAMP_CR1_ITAMP4E_Msk
15538 #define TAMP_CR1_ITAMP5E_Pos (20U)
15539 #define TAMP_CR1_ITAMP5E_Msk (0x1UL << TAMP_CR1_ITAMP5E_Pos) /*!< 0x00100000 */
15540 #define TAMP_CR1_ITAMP5E TAMP_CR1_ITAMP5E_Msk
15541 #define TAMP_CR1_ITAMP6E_Pos (21U)
15542 #define TAMP_CR1_ITAMP6E_Msk (0x1UL << TAMP_CR1_ITAMP6E_Pos) /*!< 0x00200000 */
15543 #define TAMP_CR1_ITAMP6E TAMP_CR1_ITAMP6E_Msk
15544 #define TAMP_CR1_ITAMP8E_Pos (23U)
15545 #define TAMP_CR1_ITAMP8E_Msk (0x1UL << TAMP_CR1_ITAMP8E_Pos) /*!< 0x00800000 */
15546 #define TAMP_CR1_ITAMP8E TAMP_CR1_ITAMP8E_Msk
15547
15548 /******************** Bits definition for TAMP_CR2 register *****************/
15549 #define TAMP_CR2_TAMP1NOERASE_Pos (0U)
15550 #define TAMP_CR2_TAMP1NOERASE_Msk (0x1UL << TAMP_CR2_TAMP1NOERASE_Pos) /*!< 0x00000001 */
15551 #define TAMP_CR2_TAMP1NOERASE TAMP_CR2_TAMP1NOERASE_Msk
15552 #define TAMP_CR2_TAMP2NOERASE_Pos (1U)
15553 #define TAMP_CR2_TAMP2NOERASE_Msk (0x1UL << TAMP_CR2_TAMP2NOERASE_Pos) /*!< 0x00000002 */
15554 #define TAMP_CR2_TAMP2NOERASE TAMP_CR2_TAMP2NOERASE_Msk
15555 #define TAMP_CR2_TAMP3NOERASE_Pos (2U)
15556 #define TAMP_CR2_TAMP3NOERASE_Msk (0x1UL << TAMP_CR2_TAMP3NOERASE_Pos) /*!< 0x00000004 */
15557 #define TAMP_CR2_TAMP3NOERASE TAMP_CR2_TAMP3NOERASE_Msk
15558 #define TAMP_CR2_TAMP1MSK_Pos (16U)
15559 #define TAMP_CR2_TAMP1MSK_Msk (0x1UL << TAMP_CR2_TAMP1MSK_Pos) /*!< 0x00010000 */
15560 #define TAMP_CR2_TAMP1MSK TAMP_CR2_TAMP1MSK_Msk
15561 #define TAMP_CR2_TAMP2MSK_Pos (17U)
15562 #define TAMP_CR2_TAMP2MSK_Msk (0x1UL << TAMP_CR2_TAMP2MSK_Pos) /*!< 0x00020000 */
15563 #define TAMP_CR2_TAMP2MSK TAMP_CR2_TAMP2MSK_Msk
15564 #define TAMP_CR2_TAMP3MSK_Pos (18U)
15565 #define TAMP_CR2_TAMP3MSK_Msk (0x1UL << TAMP_CR2_TAMP3MSK_Pos) /*!< 0x00040000 */
15566 #define TAMP_CR2_TAMP3MSK TAMP_CR2_TAMP3MSK_Msk
15567 #define TAMP_CR2_TAMP1TRG_Pos (24U)
15568 #define TAMP_CR2_TAMP1TRG_Msk (0x1UL << TAMP_CR2_TAMP1TRG_Pos) /*!< 0x01000000 */
15569 #define TAMP_CR2_TAMP1TRG TAMP_CR2_TAMP1TRG_Msk
15570 #define TAMP_CR2_TAMP2TRG_Pos (25U)
15571 #define TAMP_CR2_TAMP2TRG_Msk (0x1UL << TAMP_CR2_TAMP2TRG_Pos) /*!< 0x02000000 */
15572 #define TAMP_CR2_TAMP2TRG TAMP_CR2_TAMP2TRG_Msk
15573 #define TAMP_CR2_TAMP3TRG_Pos (26U)
15574 #define TAMP_CR2_TAMP3TRG_Msk (0x1UL << TAMP_CR2_TAMP3TRG_Pos) /*!< 0x04000000 */
15575 #define TAMP_CR2_TAMP3TRG TAMP_CR2_TAMP3TRG_Msk
15576
15577 /******************** Bits definition for TAMP_FLTCR register ***************/
15578 #define TAMP_FLTCR_TAMPFREQ_Pos (0U)
15579 #define TAMP_FLTCR_TAMPFREQ_Msk (0x7UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000007 */
15580 #define TAMP_FLTCR_TAMPFREQ TAMP_FLTCR_TAMPFREQ_Msk
15581 #define TAMP_FLTCR_TAMPFREQ_0 (0x1UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000001 */
15582 #define TAMP_FLTCR_TAMPFREQ_1 (0x2UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000002 */
15583 #define TAMP_FLTCR_TAMPFREQ_2 (0x4UL << TAMP_FLTCR_TAMPFREQ_Pos) /*!< 0x00000004 */
15584 #define TAMP_FLTCR_TAMPFLT_Pos (3U)
15585 #define TAMP_FLTCR_TAMPFLT_Msk (0x3UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000018 */
15586 #define TAMP_FLTCR_TAMPFLT TAMP_FLTCR_TAMPFLT_Msk
15587 #define TAMP_FLTCR_TAMPFLT_0 (0x1UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000008 */
15588 #define TAMP_FLTCR_TAMPFLT_1 (0x2UL << TAMP_FLTCR_TAMPFLT_Pos) /*!< 0x00000010 */
15589 #define TAMP_FLTCR_TAMPPRCH_Pos (5U)
15590 #define TAMP_FLTCR_TAMPPRCH_Msk (0x3UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000060 */
15591 #define TAMP_FLTCR_TAMPPRCH TAMP_FLTCR_TAMPPRCH_Msk
15592 #define TAMP_FLTCR_TAMPPRCH_0 (0x1UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000020 */
15593 #define TAMP_FLTCR_TAMPPRCH_1 (0x2UL << TAMP_FLTCR_TAMPPRCH_Pos) /*!< 0x00000040 */
15594 #define TAMP_FLTCR_TAMPPUDIS_Pos (7U)
15595 #define TAMP_FLTCR_TAMPPUDIS_Msk (0x1UL << TAMP_FLTCR_TAMPPUDIS_Pos) /*!< 0x00000080 */
15596 #define TAMP_FLTCR_TAMPPUDIS TAMP_FLTCR_TAMPPUDIS_Msk
15597
15598 /******************* Bits definition for TAMP_ATCR1 register ****************/
15599 #define TAMP_ATCR1_TAMP1AM_Pos (0U)
15600 #define TAMP_ATCR1_TAMP1AM_Msk (0x1UL << TAMP_ATCR1_TAMP1AM_Pos) /*!< 0x00000001 */
15601 #define TAMP_ATCR1_TAMP1AM TAMP_ATCR1_TAMP1AM_Msk
15602 #define TAMP_ATCR1_TAMP2AM_Pos (1U)
15603 #define TAMP_ATCR1_TAMP2AM_Msk (0x1UL << TAMP_ATCR1_TAMP2AM_Pos) /*!< 0x00000002 */
15604 #define TAMP_ATCR1_TAMP2AM TAMP_ATCR1_TAMP2AM_Msk
15605 #define TAMP_ATCR1_TAMP3AM_Pos (2U)
15606 #define TAMP_ATCR1_TAMP3AM_Msk (0x1UL << TAMP_ATCR1_TAMP3AM_Pos) /*!< 0x00000004 */
15607 #define TAMP_ATCR1_TAMP3AM TAMP_ATCR1_TAMP3AM_Msk
15608 #define TAMP_ATCR1_ATOSEL1_Pos (8U)
15609 #define TAMP_ATCR1_ATOSEL1_Msk (0x3UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000300 */
15610 #define TAMP_ATCR1_ATOSEL1 TAMP_ATCR1_ATOSEL1_Msk
15611 #define TAMP_ATCR1_ATOSEL1_0 (0x1UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000100 */
15612 #define TAMP_ATCR1_ATOSEL1_1 (0x2UL << TAMP_ATCR1_ATOSEL1_Pos) /*!< 0x00000200 */
15613 #define TAMP_ATCR1_ATOSEL2_Pos (10U)
15614 #define TAMP_ATCR1_ATOSEL2_Msk (0x3UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000C00 */
15615 #define TAMP_ATCR1_ATOSEL2 TAMP_ATCR1_ATOSEL2_Msk
15616 #define TAMP_ATCR1_ATOSEL2_0 (0x1UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000400 */
15617 #define TAMP_ATCR1_ATOSEL2_1 (0x2UL << TAMP_ATCR1_ATOSEL2_Pos) /*!< 0x00000800 */
15618 #define TAMP_ATCR1_ATOSEL3_Pos (12U)
15619 #define TAMP_ATCR1_ATOSEL3_Msk (0x3UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00003000 */
15620 #define TAMP_ATCR1_ATOSEL3 TAMP_ATCR1_ATOSEL3_Msk
15621 #define TAMP_ATCR1_ATOSEL3_0 (0x1UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00001000 */
15622 #define TAMP_ATCR1_ATOSEL3_1 (0x2UL << TAMP_ATCR1_ATOSEL3_Pos) /*!< 0x00002000 */
15623 #define TAMP_ATCR1_ATOSEL4_Pos (14U)
15624 #define TAMP_ATCR1_ATOSEL4_Msk (0x3UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x0000C000 */
15625 #define TAMP_ATCR1_ATOSEL4 TAMP_ATCR1_ATOSEL4_Msk
15626 #define TAMP_ATCR1_ATOSEL4_0 (0x1UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00004000 */
15627 #define TAMP_ATCR1_ATOSEL4_1 (0x2UL << TAMP_ATCR1_ATOSEL4_Pos) /*!< 0x00008000 */
15628 #define TAMP_ATCR1_ATCKSEL_Pos (16U)
15629 #define TAMP_ATCR1_ATCKSEL_Msk (0x7UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00070000 */
15630 #define TAMP_ATCR1_ATCKSEL TAMP_ATCR1_ATCKSEL_Msk
15631 #define TAMP_ATCR1_ATCKSEL_0 (0x1UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00010000 */
15632 #define TAMP_ATCR1_ATCKSEL_1 (0x2UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00020000 */
15633 #define TAMP_ATCR1_ATCKSEL_2 (0x4UL << TAMP_ATCR1_ATCKSEL_Pos) /*!< 0x00040000 */
15634 #define TAMP_ATCR1_ATPER_Pos (24U)
15635 #define TAMP_ATCR1_ATPER_Msk (0x7UL << TAMP_ATCR1_ATPER_Pos) /*!< 0x07000000 */
15636 #define TAMP_ATCR1_ATPER TAMP_ATCR1_ATPER_Msk
15637 #define TAMP_ATCR1_ATOSHARE_Pos (30U)
15638 #define TAMP_ATCR1_ATOSHARE_Msk (0x1UL << TAMP_ATCR1_ATOSHARE_Pos) /*!< 0x40000000 */
15639 #define TAMP_ATCR1_ATOSHARE TAMP_ATCR1_ATOSHARE_Msk
15640 #define TAMP_ATCR1_FLTEN_Pos (31U)
15641 #define TAMP_ATCR1_FLTEN_Msk (0x1UL << TAMP_ATCR1_FLTEN_Pos) /*!< 0x80000000 */
15642 #define TAMP_ATCR1_FLTEN TAMP_ATCR1_FLTEN_Msk
15643
15644 /******************** Bits definition for TAMP_ATSEEDR register *************/
15645 #define TAMP_ATSEEDR_SEED_Pos (0U)
15646 #define TAMP_ATSEEDR_SEED_Msk (0xFFFFFFFFUL << TAMP_ATSEEDR_SEED_Pos) /*!< 0xFFFFFFFF */
15647 #define TAMP_ATSEEDR_SEED TAMP_ATSEEDR_SEED_Msk
15648
15649 /******************** Bits definition for TAMP_ATOR register ****************/
15650 #define TAMP_ATOR_PRNG_Pos (0U)
15651 #define TAMP_ATOR_PRNG_Msk (0x000000FFUL << TAMP_ATOR_PRNG_Pos) /*!< 0x000000FF */
15652 #define TAMP_ATOR_PRNG TAMP_ATOR_PRNG_Msk
15653 #define TAMP_ATOR_SEEDF_Pos (14U)
15654 #define TAMP_ATOR_SEEDF_Msk (0x01UL << TAMP_ATOR_SEEDF_Pos) /*!< 0x00004000 */
15655 #define TAMP_ATOR_SEEDF TAMP_ATOR_SEEDF_Msk
15656 #define TAMP_ATOR_INITS_Pos (15U)
15657 #define TAMP_ATOR_INITS_Msk (0x01UL << TAMP_ATOR_INITS_Pos) /*!< 0x00008000 */
15658 #define TAMP_ATOR_INITS TAMP_ATOR_INITS_Msk
15659
15660 /******************** Bits definition for TAMP_IER register *****************/
15661 #define TAMP_IER_TAMP1IE_Pos (0U)
15662 #define TAMP_IER_TAMP1IE_Msk (0x1UL << TAMP_IER_TAMP1IE_Pos) /*!< 0x00000001 */
15663 #define TAMP_IER_TAMP1IE TAMP_IER_TAMP1IE_Msk
15664 #define TAMP_IER_TAMP2IE_Pos (1U)
15665 #define TAMP_IER_TAMP2IE_Msk (0x1UL << TAMP_IER_TAMP2IE_Pos) /*!< 0x00000002 */
15666 #define TAMP_IER_TAMP2IE TAMP_IER_TAMP2IE_Msk
15667 #define TAMP_IER_TAMP3IE_Pos (2U)
15668 #define TAMP_IER_TAMP3IE_Msk (0x1UL << TAMP_IER_TAMP3IE_Pos) /*!< 0x00000004 */
15669 #define TAMP_IER_TAMP3IE TAMP_IER_TAMP3IE_Msk
15670 #define TAMP_IER_ITAMP1IE_Pos (16U)
15671 #define TAMP_IER_ITAMP1IE_Msk (0x1UL << TAMP_IER_ITAMP1IE_Pos) /*!< 0x00010000 */
15672 #define TAMP_IER_ITAMP1IE TAMP_IER_ITAMP1IE_Msk
15673 #define TAMP_IER_ITAMP2IE_Pos (17U)
15674 #define TAMP_IER_ITAMP2IE_Msk (0x1UL << TAMP_IER_ITAMP2IE_Pos) /*!< 0x00020000 */
15675 #define TAMP_IER_ITAMP2IE TAMP_IER_ITAMP2IE_Msk
15676 #define TAMP_IER_ITAMP3IE_Pos (18U)
15677 #define TAMP_IER_ITAMP3IE_Msk (0x1UL << TAMP_IER_ITAMP3IE_Pos) /*!< 0x00040000 */
15678 #define TAMP_IER_ITAMP3IE TAMP_IER_ITAMP3IE_Msk
15679 #define TAMP_IER_ITAMP4IE_Pos (19U)
15680 #define TAMP_IER_ITAMP4IE_Msk (0x1UL << TAMP_IER_ITAMP4IE_Pos) /*!< 0x00080000 */
15681 #define TAMP_IER_ITAMP4IE TAMP_IER_ITAMP4IE_Msk
15682 #define TAMP_IER_ITAMP5IE_Pos (20U)
15683 #define TAMP_IER_ITAMP5IE_Msk (0x1UL << TAMP_IER_ITAMP5IE_Pos) /*!< 0x00100000 */
15684 #define TAMP_IER_ITAMP5IE TAMP_IER_ITAMP5IE_Msk
15685 #define TAMP_IER_ITAMP6IE_Pos (21U)
15686 #define TAMP_IER_ITAMP6IE_Msk (0x1UL << TAMP_IER_ITAMP6IE_Pos) /*!< 0x00200000 */
15687 #define TAMP_IER_ITAMP6IE TAMP_IER_ITAMP6IE_Msk
15688 #define TAMP_IER_ITAMP8IE_Pos (23U)
15689 #define TAMP_IER_ITAMP8IE_Msk (0x1UL << TAMP_IER_ITAMP8IE_Pos) /*!< 0x00800000 */
15690 #define TAMP_IER_ITAMP8IE TAMP_IER_ITAMP8IE_Msk
15691
15692 /******************** Bits definition for TAMP_SR register *****************/
15693 #define TAMP_SR_TAMP1F_Pos (0U)
15694 #define TAMP_SR_TAMP1F_Msk (0x1UL << TAMP_SR_TAMP1F_Pos) /*!< 0x00000001 */
15695 #define TAMP_SR_TAMP1F TAMP_SR_TAMP1F_Msk
15696 #define TAMP_SR_TAMP2F_Pos (1U)
15697 #define TAMP_SR_TAMP2F_Msk (0x1UL << TAMP_SR_TAMP2F_Pos) /*!< 0x00000002 */
15698 #define TAMP_SR_TAMP2F TAMP_SR_TAMP2F_Msk
15699 #define TAMP_SR_TAMP3F_Pos (2U)
15700 #define TAMP_SR_TAMP3F_Msk (0x1UL << TAMP_SR_TAMP3F_Pos) /*!< 0x00000004 */
15701 #define TAMP_SR_TAMP3F TAMP_SR_TAMP3F_Msk
15702 #define TAMP_SR_ITAMP1F_Pos (16U)
15703 #define TAMP_SR_ITAMP1F_Msk (0x1UL << TAMP_SR_ITAMP1F_Pos) /*!< 0x00010000 */
15704 #define TAMP_SR_ITAMP1F TAMP_SR_ITAMP1F_Msk
15705 #define TAMP_SR_ITAMP2F_Pos (17U)
15706 #define TAMP_SR_ITAMP2F_Msk (0x1UL << TAMP_SR_ITAMP2F_Pos) /*!< 0x00020000 */
15707 #define TAMP_SR_ITAMP2F TAMP_SR_ITAMP2F_Msk
15708 #define TAMP_SR_ITAMP3F_Pos (18U)
15709 #define TAMP_SR_ITAMP3F_Msk (0x1UL << TAMP_SR_ITAMP3F_Pos) /*!< 0x00040000 */
15710 #define TAMP_SR_ITAMP3F TAMP_SR_ITAMP3F_Msk
15711 #define TAMP_SR_ITAMP4F_Pos (19U)
15712 #define TAMP_SR_ITAMP4F_Msk (0x1UL << TAMP_SR_ITAMP4F_Pos) /*!< 0x00080000 */
15713 #define TAMP_SR_ITAMP4F TAMP_SR_ITAMP4F_Msk
15714 #define TAMP_SR_ITAMP5F_Pos (20U)
15715 #define TAMP_SR_ITAMP5F_Msk (0x1UL << TAMP_SR_ITAMP5F_Pos) /*!< 0x00100000 */
15716 #define TAMP_SR_ITAMP5F TAMP_SR_ITAMP5F_Msk
15717 #define TAMP_SR_ITAMP6F_Pos (21U)
15718 #define TAMP_SR_ITAMP6F_Msk (0x1UL << TAMP_SR_ITAMP6F_Pos) /*!< 0x00200000 */
15719 #define TAMP_SR_ITAMP6F TAMP_SR_ITAMP6F_Msk
15720 #define TAMP_SR_ITAMP8F_Pos (23U)
15721 #define TAMP_SR_ITAMP8F_Msk (0x1UL << TAMP_SR_ITAMP8F_Pos) /*!< 0x00800000 */
15722 #define TAMP_SR_ITAMP8F TAMP_SR_ITAMP8F_Msk
15723
15724 /******************** Bits definition for TAMP_MISR register ************ *****/
15725 #define TAMP_MISR_TAMP1MF_Pos (0U)
15726 #define TAMP_MISR_TAMP1MF_Msk (0x1UL << TAMP_MISR_TAMP1MF_Pos) /*!< 0x00000001 */
15727 #define TAMP_MISR_TAMP1MF TAMP_MISR_TAMP1MF_Msk
15728 #define TAMP_MISR_TAMP2MF_Pos (1U)
15729 #define TAMP_MISR_TAMP2MF_Msk (0x1UL << TAMP_MISR_TAMP2MF_Pos) /*!< 0x00000002 */
15730 #define TAMP_MISR_TAMP2MF TAMP_MISR_TAMP2MF_Msk
15731 #define TAMP_MISR_TAMP3MF_Pos (2U)
15732 #define TAMP_MISR_TAMP3MF_Msk (0x1UL << TAMP_MISR_TAMP3MF_Pos) /*!< 0x00000004 */
15733 #define TAMP_MISR_TAMP3MF TAMP_MISR_TAMP3MF_Msk
15734 #define TAMP_MISR_ITAMP1MF_Pos (16U)
15735 #define TAMP_MISR_ITAMP1MF_Msk (0x1UL << TAMP_MISR_ITAMP1MF_Pos) /*!< 0x00010000 */
15736 #define TAMP_MISR_ITAMP1MF TAMP_MISR_ITAMP1MF_Msk
15737 #define TAMP_MISR_ITAMP2MF_Pos (17U)
15738 #define TAMP_MISR_ITAMP2MF_Msk (0x1UL << TAMP_MISR_ITAMP2MF_Pos) /*!< 0x00020000 */
15739 #define TAMP_MISR_ITAMP2MF TAMP_MISR_ITAMP2MF_Msk
15740 #define TAMP_MISR_ITAMP3MF_Pos (18U)
15741 #define TAMP_MISR_ITAMP3MF_Msk (0x1UL << TAMP_MISR_ITAMP3MF_Pos) /*!< 0x00040000 */
15742 #define TAMP_MISR_ITAMP3MF TAMP_MISR_ITAMP3MF_Msk
15743 #define TAMP_MISR_ITAMP4MF_Pos (19U)
15744 #define TAMP_MISR_ITAMP4MF_Msk (0x1UL << TAMP_MISR_ITAMP4MF_Pos) /*!< 0x00080000 */
15745 #define TAMP_MISR_ITAMP4MF TAMP_MISR_ITAMP4MF_Msk
15746 #define TAMP_MISR_ITAMP5MF_Pos (20U)
15747 #define TAMP_MISR_ITAMP5MF_Msk (0x1UL << TAMP_MISR_ITAMP5MF_Pos) /*!< 0x00100000 */
15748 #define TAMP_MISR_ITAMP5MF TAMP_MISR_ITAMP5MF_Msk
15749 #define TAMP_MISR_ITAMP6MF_Pos (21U)
15750 #define TAMP_MISR_ITAMP6MF_Msk (0x1UL << TAMP_MISR_ITAMP6MF_Pos) /*!< 0x00200000 */
15751 #define TAMP_MISR_ITAMP6MF TAMP_MISR_ITAMP6MF_Msk
15752 #define TAMP_MISR_ITAMP8MF_Pos (23U)
15753 #define TAMP_MISR_ITAMP8MF_Msk (0x1UL << TAMP_MISR_ITAMP8MF_Pos) /*!< 0x00800000 */
15754 #define TAMP_MISR_ITAMP8MF TAMP_MISR_ITAMP8MF_Msk
15755
15756 /******************** Bits definition for TAMP_SCR register *****************/
15757 #define TAMP_SCR_CTAMP1F_Pos (0U)
15758 #define TAMP_SCR_CTAMP1F_Msk (0x1UL << TAMP_SCR_CTAMP1F_Pos) /*!< 0x00000001 */
15759 #define TAMP_SCR_CTAMP1F TAMP_SCR_CTAMP1F_Msk
15760 #define TAMP_SCR_CTAMP2F_Pos (1U)
15761 #define TAMP_SCR_CTAMP2F_Msk (0x1UL << TAMP_SCR_CTAMP2F_Pos) /*!< 0x00000002 */
15762 #define TAMP_SCR_CTAMP2F TAMP_SCR_CTAMP2F_Msk
15763 #define TAMP_SCR_CTAMP3F_Pos (2U)
15764 #define TAMP_SCR_CTAMP3F_Msk (0x1UL << TAMP_SCR_CTAMP3F_Pos) /*!< 0x00000004 */
15765 #define TAMP_SCR_CTAMP3F TAMP_SCR_CTAMP3F_Msk
15766 #define TAMP_SCR_CITAMP1F_Pos (16U)
15767 #define TAMP_SCR_CITAMP1F_Msk (0x1UL << TAMP_SCR_CITAMP1F_Pos) /*!< 0x00010000 */
15768 #define TAMP_SCR_CITAMP1F TAMP_SCR_CITAMP1F_Msk
15769 #define TAMP_SCR_CITAMP2F_Pos (17U)
15770 #define TAMP_SCR_CITAMP2F_Msk (0x1UL << TAMP_SCR_CITAMP2F_Pos) /*!< 0x00020000 */
15771 #define TAMP_SCR_CITAMP2F TAMP_SCR_CITAMP2F_Msk
15772 #define TAMP_SCR_CITAMP3F_Pos (18U)
15773 #define TAMP_SCR_CITAMP3F_Msk (0x1UL << TAMP_SCR_CITAMP3F_Pos) /*!< 0x00040000 */
15774 #define TAMP_SCR_CITAMP3F TAMP_SCR_CITAMP3F_Msk
15775 #define TAMP_SCR_CITAMP4F_Pos (19U)
15776 #define TAMP_SCR_CITAMP4F_Msk (0x1UL << TAMP_SCR_CITAMP4F_Pos) /*!< 0x00080000 */
15777 #define TAMP_SCR_CITAMP4F TAMP_SCR_CITAMP4F_Msk
15778 #define TAMP_SCR_CITAMP5F_Pos (20U)
15779 #define TAMP_SCR_CITAMP5F_Msk (0x1UL << TAMP_SCR_CITAMP5F_Pos) /*!< 0x00100000 */
15780 #define TAMP_SCR_CITAMP5F TAMP_SCR_CITAMP5F_Msk
15781 #define TAMP_SCR_CITAMP6F_Pos (21U)
15782 #define TAMP_SCR_CITAMP6F_Msk (0x1UL << TAMP_SCR_CITAMP6F_Pos) /*!< 0x00200000 */
15783 #define TAMP_SCR_CITAMP6F TAMP_SCR_CITAMP6F_Msk
15784 #define TAMP_SCR_CITAMP8F_Pos (23U)
15785 #define TAMP_SCR_CITAMP8F_Msk (0x1UL << TAMP_SCR_CITAMP8F_Pos) /*!< 0x00800000 */
15786 #define TAMP_SCR_CITAMP8F TAMP_SCR_CITAMP8F_Msk
15787
15788 /******************** Bits definition for TAMP_COUNTR register **************/
15789 #define TAMP_COUNTR_Pos (16U)
15790 #define TAMP_COUNTR_Msk (0xFFFFUL << TAMP_COUNTR_Pos) /*!< 0xFFFF0000 */
15791 #define TAMP_COUNTR TAMP_COUNTR_Msk
15792
15793 /******************** Bits definition for TAMP_OR register ******************/
15794 #define TAMP_OR_OUT3_RMP_Pos (0U)
15795 #define TAMP_OR_OUT3_RMP_Msk (0x1UL << TAMP_OR_OUT3_RMP_Pos) /*!< 0x00000001 */
15796 #define TAMP_OR_OUT3_RMP TAMP_OR_OUT3_RMP_Msk
15797
15798 /******************** Bits definition for TAMP_BKP0R register ***************/
15799 #define TAMP_BKP0R_Pos (0U)
15800 #define TAMP_BKP0R_Msk (0xFFFFFFFFUL << TAMP_BKP0R_Pos) /*!< 0xFFFFFFFF */
15801 #define TAMP_BKP0R TAMP_BKP0R_Msk
15802
15803 /******************** Bits definition for TAMP_BKP1R register ****************/
15804 #define TAMP_BKP1R_Pos (0U)
15805 #define TAMP_BKP1R_Msk (0xFFFFFFFFUL << TAMP_BKP1R_Pos) /*!< 0xFFFFFFFF */
15806 #define TAMP_BKP1R TAMP_BKP1R_Msk
15807
15808 /******************** Bits definition for TAMP_BKP2R register ****************/
15809 #define TAMP_BKP2R_Pos (0U)
15810 #define TAMP_BKP2R_Msk (0xFFFFFFFFUL << TAMP_BKP2R_Pos) /*!< 0xFFFFFFFF */
15811 #define TAMP_BKP2R TAMP_BKP2R_Msk
15812
15813 /******************** Bits definition for TAMP_BKP3R register ****************/
15814 #define TAMP_BKP3R_Pos (0U)
15815 #define TAMP_BKP3R_Msk (0xFFFFFFFFUL << TAMP_BKP3R_Pos) /*!< 0xFFFFFFFF */
15816 #define TAMP_BKP3R TAMP_BKP3R_Msk
15817
15818 /******************** Bits definition for TAMP_BKP4R register ****************/
15819 #define TAMP_BKP4R_Pos (0U)
15820 #define TAMP_BKP4R_Msk (0xFFFFFFFFUL << TAMP_BKP4R_Pos) /*!< 0xFFFFFFFF */
15821 #define TAMP_BKP4R TAMP_BKP4R_Msk
15822
15823 /******************** Bits definition for TAMP_BKP5R register ****************/
15824 #define TAMP_BKP5R_Pos (0U)
15825 #define TAMP_BKP5R_Msk (0xFFFFFFFFUL << TAMP_BKP5R_Pos) /*!< 0xFFFFFFFF */
15826 #define TAMP_BKP5R TAMP_BKP5R_Msk
15827
15828 /******************** Bits definition for TAMP_BKP6R register ****************/
15829 #define TAMP_BKP6R_Pos (0U)
15830 #define TAMP_BKP6R_Msk (0xFFFFFFFFUL << TAMP_BKP6R_Pos) /*!< 0xFFFFFFFF */
15831 #define TAMP_BKP6R TAMP_BKP6R_Msk
15832
15833 /******************** Bits definition for TAMP_BKP7R register ****************/
15834 #define TAMP_BKP7R_Pos (0U)
15835 #define TAMP_BKP7R_Msk (0xFFFFFFFFUL << TAMP_BKP7R_Pos) /*!< 0xFFFFFFFF */
15836 #define TAMP_BKP7R TAMP_BKP7R_Msk
15837
15838 /******************** Bits definition for TAMP_BKP8R register ****************/
15839 #define TAMP_BKP8R_Pos (0U)
15840 #define TAMP_BKP8R_Msk (0xFFFFFFFFUL << TAMP_BKP8R_Pos) /*!< 0xFFFFFFFF */
15841 #define TAMP_BKP8R TAMP_BKP8R_Msk
15842
15843 /******************** Bits definition for TAMP_BKP9R register ****************/
15844 #define TAMP_BKP9R_Pos (0U)
15845 #define TAMP_BKP9R_Msk (0xFFFFFFFFUL << TAMP_BKP9R_Pos) /*!< 0xFFFFFFFF */
15846 #define TAMP_BKP9R TAMP_BKP9R_Msk
15847
15848 /******************** Bits definition for TAMP_BKP10R register ***************/
15849 #define TAMP_BKP10R_Pos (0U)
15850 #define TAMP_BKP10R_Msk (0xFFFFFFFFUL << TAMP_BKP10R_Pos) /*!< 0xFFFFFFFF */
15851 #define TAMP_BKP10R TAMP_BKP10R_Msk
15852
15853 /******************** Bits definition for TAMP_BKP11R register ***************/
15854 #define TAMP_BKP11R_Pos (0U)
15855 #define TAMP_BKP11R_Msk (0xFFFFFFFFUL << TAMP_BKP11R_Pos) /*!< 0xFFFFFFFF */
15856 #define TAMP_BKP11R TAMP_BKP11R_Msk
15857
15858 /******************** Bits definition for TAMP_BKP12R register ***************/
15859 #define TAMP_BKP12R_Pos (0U)
15860 #define TAMP_BKP12R_Msk (0xFFFFFFFFUL << TAMP_BKP12R_Pos) /*!< 0xFFFFFFFF */
15861 #define TAMP_BKP12R TAMP_BKP12R_Msk
15862
15863 /******************** Bits definition for TAMP_BKP13R register ***************/
15864 #define TAMP_BKP13R_Pos (0U)
15865 #define TAMP_BKP13R_Msk (0xFFFFFFFFUL << TAMP_BKP13R_Pos) /*!< 0xFFFFFFFF */
15866 #define TAMP_BKP13R TAMP_BKP13R_Msk
15867
15868 /******************** Bits definition for TAMP_BKP14R register ***************/
15869 #define TAMP_BKP14R_Pos (0U)
15870 #define TAMP_BKP14R_Msk (0xFFFFFFFFUL << TAMP_BKP14R_Pos) /*!< 0xFFFFFFFF */
15871 #define TAMP_BKP14R TAMP_BKP14R_Msk
15872
15873 /******************** Bits definition for TAMP_BKP15R register ***************/
15874 #define TAMP_BKP15R_Pos (0U)
15875 #define TAMP_BKP15R_Msk (0xFFFFFFFFUL << TAMP_BKP15R_Pos) /*!< 0xFFFFFFFF */
15876 #define TAMP_BKP15R TAMP_BKP15R_Msk
15877
15878 /******************** Bits definition for TAMP_BKP16R register ***************/
15879 #define TAMP_BKP16R_Pos (0U)
15880 #define TAMP_BKP16R_Msk (0xFFFFFFFFUL << TAMP_BKP16R_Pos) /*!< 0xFFFFFFFF */
15881 #define TAMP_BKP16R TAMP_BKP16R_Msk
15882
15883 /******************** Bits definition for TAMP_BKP17R register ***************/
15884 #define TAMP_BKP17R_Pos (0U)
15885 #define TAMP_BKP17R_Msk (0xFFFFFFFFUL << TAMP_BKP17R_Pos) /*!< 0xFFFFFFFF */
15886 #define TAMP_BKP17R TAMP_BKP17R_Msk
15887
15888 /******************** Bits definition for TAMP_BKP18R register ***************/
15889 #define TAMP_BKP18R_Pos (0U)
15890 #define TAMP_BKP18R_Msk (0xFFFFFFFFUL << TAMP_BKP18R_Pos) /*!< 0xFFFFFFFF */
15891 #define TAMP_BKP18R TAMP_BKP18R_Msk
15892
15893 /******************** Bits definition for TAMP_BKP19R register ***************/
15894 #define TAMP_BKP19R_Pos (0U)
15895 #define TAMP_BKP19R_Msk (0xFFFFFFFFUL << TAMP_BKP19R_Pos) /*!< 0xFFFFFFFF */
15896 #define TAMP_BKP19R TAMP_BKP19R_Msk
15897
15898 /******************** Bits definition for TAMP_BKP20R register ***************/
15899 #define TAMP_BKP20R_Pos (0U)
15900 #define TAMP_BKP20R_Msk (0xFFFFFFFFUL << TAMP_BKP20R_Pos) /*!< 0xFFFFFFFF */
15901 #define TAMP_BKP20R TAMP_BKP20R_Msk
15902
15903 /******************** Bits definition for TAMP_BKP21R register ***************/
15904 #define TAMP_BKP21R_Pos (0U)
15905 #define TAMP_BKP21R_Msk (0xFFFFFFFFUL << TAMP_BKP21R_Pos) /*!< 0xFFFFFFFF */
15906 #define TAMP_BKP21R TAMP_BKP21R_Msk
15907
15908 /******************** Bits definition for TAMP_BKP22R register ***************/
15909 #define TAMP_BKP22R_Pos (0U)
15910 #define TAMP_BKP22R_Msk (0xFFFFFFFFUL << TAMP_BKP22R_Pos) /*!< 0xFFFFFFFF */
15911 #define TAMP_BKP22R TAMP_BKP22R_Msk
15912
15913 /******************** Bits definition for TAMP_BKP23R register ***************/
15914 #define TAMP_BKP23R_Pos (0U)
15915 #define TAMP_BKP23R_Msk (0xFFFFFFFFUL << TAMP_BKP23R_Pos) /*!< 0xFFFFFFFF */
15916 #define TAMP_BKP23R TAMP_BKP23R_Msk
15917
15918 /******************** Bits definition for TAMP_BKP24R register ***************/
15919 #define TAMP_BKP24R_Pos (0U)
15920 #define TAMP_BKP24R_Msk (0xFFFFFFFFUL << TAMP_BKP24R_Pos) /*!< 0xFFFFFFFF */
15921 #define TAMP_BKP24R TAMP_BKP24R_Msk
15922
15923 /******************** Bits definition for TAMP_BKP25R register ***************/
15924 #define TAMP_BKP25R_Pos (0U)
15925 #define TAMP_BKP25R_Msk (0xFFFFFFFFUL << TAMP_BKP25R_Pos) /*!< 0xFFFFFFFF */
15926 #define TAMP_BKP25R TAMP_BKP25R_Msk
15927
15928 /******************** Bits definition for TAMP_BKP26R register ***************/
15929 #define TAMP_BKP26R_Pos (0U)
15930 #define TAMP_BKP26R_Msk (0xFFFFFFFFUL << TAMP_BKP26R_Pos) /*!< 0xFFFFFFFF */
15931 #define TAMP_BKP26R TAMP_BKP26R_Msk
15932
15933 /******************** Bits definition for TAMP_BKP27R register ***************/
15934 #define TAMP_BKP27R_Pos (0U)
15935 #define TAMP_BKP27R_Msk (0xFFFFFFFFUL << TAMP_BKP27R_Pos) /*!< 0xFFFFFFFF */
15936 #define TAMP_BKP27R TAMP_BKP27R_Msk
15937
15938 /******************** Bits definition for TAMP_BKP28R register ***************/
15939 #define TAMP_BKP28R_Pos (0U)
15940 #define TAMP_BKP28R_Msk (0xFFFFFFFFUL << TAMP_BKP28R_Pos) /*!< 0xFFFFFFFF */
15941 #define TAMP_BKP28R TAMP_BKP28R_Msk
15942
15943 /******************** Bits definition for TAMP_BKP29R register ***************/
15944 #define TAMP_BKP29R_Pos (0U)
15945 #define TAMP_BKP29R_Msk (0xFFFFFFFFUL << TAMP_BKP29R_Pos) /*!< 0xFFFFFFFF */
15946 #define TAMP_BKP29R TAMP_BKP29R_Msk
15947
15948 /******************** Bits definition for TAMP_BKP30R register ***************/
15949 #define TAMP_BKP30R_Pos (0U)
15950 #define TAMP_BKP30R_Msk (0xFFFFFFFFUL << TAMP_BKP30R_Pos) /*!< 0xFFFFFFFF */
15951 #define TAMP_BKP30R TAMP_BKP30R_Msk
15952
15953 /******************** Bits definition for TAMP_BKP31R register ***************/
15954 #define TAMP_BKP31R_Pos (0U)
15955 #define TAMP_BKP31R_Msk (0xFFFFFFFFUL << TAMP_BKP31R_Pos) /*!< 0xFFFFFFFF */
15956 #define TAMP_BKP31R TAMP_BKP31R_Msk
15957
15958 /******************** Number of backup registers ******************************/
15959 #define TAMP_BKP_NUMBER_Pos (5U)
15960 #define TAMP_BKP_NUMBER_Msk (0x1UL << TAMP_BKP_NUMBER_Pos) /*!< 0x00000080 */
15961 #define TAMP_BKP_NUMBER TAMP_BKP_NUMBER_Msk /*!< 32 BKPREG */
15962
15963 /******************************************************************************/
15964 /* */
15965 /* SPDIF-RX Interface */
15966 /* */
15967 /******************************************************************************/
15968 /******************** Bit definition for SPDIF_CR register ******************/
15969 #define SPDIFRX_CR_SPDIFEN_Pos (0U)
15970 #define SPDIFRX_CR_SPDIFEN_Msk (0x3UL << SPDIFRX_CR_SPDIFEN_Pos) /*!< 0x00000003 */
15971 #define SPDIFRX_CR_SPDIFEN SPDIFRX_CR_SPDIFEN_Msk /*!<Peripheral Block Enable */
15972 #define SPDIFRX_CR_RXDMAEN_Pos (2U)
15973 #define SPDIFRX_CR_RXDMAEN_Msk (0x1UL << SPDIFRX_CR_RXDMAEN_Pos) /*!< 0x00000004 */
15974 #define SPDIFRX_CR_RXDMAEN SPDIFRX_CR_RXDMAEN_Msk /*!<Receiver DMA Enable for data flow */
15975 #define SPDIFRX_CR_RXSTEO_Pos (3U)
15976 #define SPDIFRX_CR_RXSTEO_Msk (0x1UL << SPDIFRX_CR_RXSTEO_Pos) /*!< 0x00000008 */
15977 #define SPDIFRX_CR_RXSTEO SPDIFRX_CR_RXSTEO_Msk /*!<Stereo Mode */
15978 #define SPDIFRX_CR_DRFMT_Pos (4U)
15979 #define SPDIFRX_CR_DRFMT_Msk (0x3UL << SPDIFRX_CR_DRFMT_Pos) /*!< 0x00000030 */
15980 #define SPDIFRX_CR_DRFMT SPDIFRX_CR_DRFMT_Msk /*!<RX Data format */
15981 #define SPDIFRX_CR_PMSK_Pos (6U)
15982 #define SPDIFRX_CR_PMSK_Msk (0x1UL << SPDIFRX_CR_PMSK_Pos) /*!< 0x00000040 */
15983 #define SPDIFRX_CR_PMSK SPDIFRX_CR_PMSK_Msk /*!<Mask Parity error bit */
15984 #define SPDIFRX_CR_VMSK_Pos (7U)
15985 #define SPDIFRX_CR_VMSK_Msk (0x1UL << SPDIFRX_CR_VMSK_Pos) /*!< 0x00000080 */
15986 #define SPDIFRX_CR_VMSK SPDIFRX_CR_VMSK_Msk /*!<Mask of Validity bit */
15987 #define SPDIFRX_CR_CUMSK_Pos (8U)
15988 #define SPDIFRX_CR_CUMSK_Msk (0x1UL << SPDIFRX_CR_CUMSK_Pos) /*!< 0x00000100 */
15989 #define SPDIFRX_CR_CUMSK SPDIFRX_CR_CUMSK_Msk /*!<Mask of channel status and user bits */
15990 #define SPDIFRX_CR_PTMSK_Pos (9U)
15991 #define SPDIFRX_CR_PTMSK_Msk (0x1UL << SPDIFRX_CR_PTMSK_Pos) /*!< 0x00000200 */
15992 #define SPDIFRX_CR_PTMSK SPDIFRX_CR_PTMSK_Msk /*!<Mask of Preamble Type bits */
15993 #define SPDIFRX_CR_CBDMAEN_Pos (10U)
15994 #define SPDIFRX_CR_CBDMAEN_Msk (0x1UL << SPDIFRX_CR_CBDMAEN_Pos) /*!< 0x00000400 */
15995 #define SPDIFRX_CR_CBDMAEN SPDIFRX_CR_CBDMAEN_Msk /*!<Control Buffer DMA ENable for control flow */
15996 #define SPDIFRX_CR_CHSEL_Pos (11U)
15997 #define SPDIFRX_CR_CHSEL_Msk (0x1UL << SPDIFRX_CR_CHSEL_Pos) /*!< 0x00000800 */
15998 #define SPDIFRX_CR_CHSEL SPDIFRX_CR_CHSEL_Msk /*!<Channel Selection */
15999 #define SPDIFRX_CR_NBTR_Pos (12U)
16000 #define SPDIFRX_CR_NBTR_Msk (0x3UL << SPDIFRX_CR_NBTR_Pos) /*!< 0x00003000 */
16001 #define SPDIFRX_CR_NBTR SPDIFRX_CR_NBTR_Msk /*!<Maximum allowed re-tries during synchronization phase */
16002 #define SPDIFRX_CR_WFA_Pos (14U)
16003 #define SPDIFRX_CR_WFA_Msk (0x1UL << SPDIFRX_CR_WFA_Pos) /*!< 0x00004000 */
16004 #define SPDIFRX_CR_WFA SPDIFRX_CR_WFA_Msk /*!<Wait For Activity */
16005 #define SPDIFRX_CR_INSEL_Pos (16U)
16006 #define SPDIFRX_CR_INSEL_Msk (0x7UL << SPDIFRX_CR_INSEL_Pos) /*!< 0x00070000 */
16007 #define SPDIFRX_CR_INSEL SPDIFRX_CR_INSEL_Msk /*!<SPDIF input selection */
16008 #define SPDIFRX_CR_CKSEN_Pos (20U)
16009 #define SPDIFRX_CR_CKSEN_Msk (0x1UL << SPDIFRX_CR_CKSEN_Pos) /*!< 0x00100000 */
16010 #define SPDIFRX_CR_CKSEN SPDIFRX_CR_CKSEN_Msk /*!<Symbol Clock Enable */
16011 #define SPDIFRX_CR_CKSBKPEN_Pos (21U)
16012 #define SPDIFRX_CR_CKSBKPEN_Msk (0x1UL << SPDIFRX_CR_CKSBKPEN_Pos) /*!< 0x00200000 */
16013 #define SPDIFRX_CR_CKSBKPEN SPDIFRX_CR_CKSBKPEN_Msk /*!<Backup Symbol Clock Enable */
16014
16015 /******************* Bit definition for SPDIFRX_IMR register *******************/
16016 #define SPDIFRX_IMR_RXNEIE_Pos (0U)
16017 #define SPDIFRX_IMR_RXNEIE_Msk (0x1UL << SPDIFRX_IMR_RXNEIE_Pos) /*!< 0x00000001 */
16018 #define SPDIFRX_IMR_RXNEIE SPDIFRX_IMR_RXNEIE_Msk /*!<RXNE interrupt enable */
16019 #define SPDIFRX_IMR_CSRNEIE_Pos (1U)
16020 #define SPDIFRX_IMR_CSRNEIE_Msk (0x1UL << SPDIFRX_IMR_CSRNEIE_Pos) /*!< 0x00000002 */
16021 #define SPDIFRX_IMR_CSRNEIE SPDIFRX_IMR_CSRNEIE_Msk /*!<Control Buffer Ready Interrupt Enable */
16022 #define SPDIFRX_IMR_PERRIE_Pos (2U)
16023 #define SPDIFRX_IMR_PERRIE_Msk (0x1UL << SPDIFRX_IMR_PERRIE_Pos) /*!< 0x00000004 */
16024 #define SPDIFRX_IMR_PERRIE SPDIFRX_IMR_PERRIE_Msk /*!<Parity error interrupt enable */
16025 #define SPDIFRX_IMR_OVRIE_Pos (3U)
16026 #define SPDIFRX_IMR_OVRIE_Msk (0x1UL << SPDIFRX_IMR_OVRIE_Pos) /*!< 0x00000008 */
16027 #define SPDIFRX_IMR_OVRIE SPDIFRX_IMR_OVRIE_Msk /*!<Overrun error Interrupt Enable */
16028 #define SPDIFRX_IMR_SBLKIE_Pos (4U)
16029 #define SPDIFRX_IMR_SBLKIE_Msk (0x1UL << SPDIFRX_IMR_SBLKIE_Pos) /*!< 0x00000010 */
16030 #define SPDIFRX_IMR_SBLKIE SPDIFRX_IMR_SBLKIE_Msk /*!<Synchronization Block Detected Interrupt Enable */
16031 #define SPDIFRX_IMR_SYNCDIE_Pos (5U)
16032 #define SPDIFRX_IMR_SYNCDIE_Msk (0x1UL << SPDIFRX_IMR_SYNCDIE_Pos) /*!< 0x00000020 */
16033 #define SPDIFRX_IMR_SYNCDIE SPDIFRX_IMR_SYNCDIE_Msk /*!<Synchronization Done */
16034 #define SPDIFRX_IMR_IFEIE_Pos (6U)
16035 #define SPDIFRX_IMR_IFEIE_Msk (0x1UL << SPDIFRX_IMR_IFEIE_Pos) /*!< 0x00000040 */
16036 #define SPDIFRX_IMR_IFEIE SPDIFRX_IMR_IFEIE_Msk /*!<Serial Interface Error Interrupt Enable */
16037
16038 /******************* Bit definition for SPDIFRX_SR register *******************/
16039 #define SPDIFRX_SR_RXNE_Pos (0U)
16040 #define SPDIFRX_SR_RXNE_Msk (0x1UL << SPDIFRX_SR_RXNE_Pos) /*!< 0x00000001 */
16041 #define SPDIFRX_SR_RXNE SPDIFRX_SR_RXNE_Msk /*!<Read data register not empty */
16042 #define SPDIFRX_SR_CSRNE_Pos (1U)
16043 #define SPDIFRX_SR_CSRNE_Msk (0x1UL << SPDIFRX_SR_CSRNE_Pos) /*!< 0x00000002 */
16044 #define SPDIFRX_SR_CSRNE SPDIFRX_SR_CSRNE_Msk /*!<The Control Buffer register is not empty */
16045 #define SPDIFRX_SR_PERR_Pos (2U)
16046 #define SPDIFRX_SR_PERR_Msk (0x1UL << SPDIFRX_SR_PERR_Pos) /*!< 0x00000004 */
16047 #define SPDIFRX_SR_PERR SPDIFRX_SR_PERR_Msk /*!<Parity error */
16048 #define SPDIFRX_SR_OVR_Pos (3U)
16049 #define SPDIFRX_SR_OVR_Msk (0x1UL << SPDIFRX_SR_OVR_Pos) /*!< 0x00000008 */
16050 #define SPDIFRX_SR_OVR SPDIFRX_SR_OVR_Msk /*!<Overrun error */
16051 #define SPDIFRX_SR_SBD_Pos (4U)
16052 #define SPDIFRX_SR_SBD_Msk (0x1UL << SPDIFRX_SR_SBD_Pos) /*!< 0x00000010 */
16053 #define SPDIFRX_SR_SBD SPDIFRX_SR_SBD_Msk /*!<Synchronization Block Detected */
16054 #define SPDIFRX_SR_SYNCD_Pos (5U)
16055 #define SPDIFRX_SR_SYNCD_Msk (0x1UL << SPDIFRX_SR_SYNCD_Pos) /*!< 0x00000020 */
16056 #define SPDIFRX_SR_SYNCD SPDIFRX_SR_SYNCD_Msk /*!<Synchronization Done */
16057 #define SPDIFRX_SR_FERR_Pos (6U)
16058 #define SPDIFRX_SR_FERR_Msk (0x1UL << SPDIFRX_SR_FERR_Pos) /*!< 0x00000040 */
16059 #define SPDIFRX_SR_FERR SPDIFRX_SR_FERR_Msk /*!<Framing error */
16060 #define SPDIFRX_SR_SERR_Pos (7U)
16061 #define SPDIFRX_SR_SERR_Msk (0x1UL << SPDIFRX_SR_SERR_Pos) /*!< 0x00000080 */
16062 #define SPDIFRX_SR_SERR SPDIFRX_SR_SERR_Msk /*!<Synchronization error */
16063 #define SPDIFRX_SR_TERR_Pos (8U)
16064 #define SPDIFRX_SR_TERR_Msk (0x1UL << SPDIFRX_SR_TERR_Pos) /*!< 0x00000100 */
16065 #define SPDIFRX_SR_TERR SPDIFRX_SR_TERR_Msk /*!<Time-out error */
16066 #define SPDIFRX_SR_WIDTH5_Pos (16U)
16067 #define SPDIFRX_SR_WIDTH5_Msk (0x7FFFUL << SPDIFRX_SR_WIDTH5_Pos) /*!< 0x7FFF0000 */
16068 #define SPDIFRX_SR_WIDTH5 SPDIFRX_SR_WIDTH5_Msk /*!<Duration of 5 symbols counted with spdif_clk */
16069
16070 /******************* Bit definition for SPDIFRX_IFCR register *******************/
16071 #define SPDIFRX_IFCR_PERRCF_Pos (2U)
16072 #define SPDIFRX_IFCR_PERRCF_Msk (0x1UL << SPDIFRX_IFCR_PERRCF_Pos) /*!< 0x00000004 */
16073 #define SPDIFRX_IFCR_PERRCF SPDIFRX_IFCR_PERRCF_Msk /*!<Clears the Parity error flag */
16074 #define SPDIFRX_IFCR_OVRCF_Pos (3U)
16075 #define SPDIFRX_IFCR_OVRCF_Msk (0x1UL << SPDIFRX_IFCR_OVRCF_Pos) /*!< 0x00000008 */
16076 #define SPDIFRX_IFCR_OVRCF SPDIFRX_IFCR_OVRCF_Msk /*!<Clears the Overrun error flag */
16077 #define SPDIFRX_IFCR_SBDCF_Pos (4U)
16078 #define SPDIFRX_IFCR_SBDCF_Msk (0x1UL << SPDIFRX_IFCR_SBDCF_Pos) /*!< 0x00000010 */
16079 #define SPDIFRX_IFCR_SBDCF SPDIFRX_IFCR_SBDCF_Msk /*!<Clears the Synchronization Block Detected flag */
16080 #define SPDIFRX_IFCR_SYNCDCF_Pos (5U)
16081 #define SPDIFRX_IFCR_SYNCDCF_Msk (0x1UL << SPDIFRX_IFCR_SYNCDCF_Pos) /*!< 0x00000020 */
16082 #define SPDIFRX_IFCR_SYNCDCF SPDIFRX_IFCR_SYNCDCF_Msk /*!<Clears the Synchronization Done flag */
16083
16084 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b00 case) *******************/
16085 #define SPDIFRX_DR0_DR_Pos (0U)
16086 #define SPDIFRX_DR0_DR_Msk (0xFFFFFFUL << SPDIFRX_DR0_DR_Pos) /*!< 0x00FFFFFF */
16087 #define SPDIFRX_DR0_DR SPDIFRX_DR0_DR_Msk /*!<Data value */
16088 #define SPDIFRX_DR0_PE_Pos (24U)
16089 #define SPDIFRX_DR0_PE_Msk (0x1UL << SPDIFRX_DR0_PE_Pos) /*!< 0x01000000 */
16090 #define SPDIFRX_DR0_PE SPDIFRX_DR0_PE_Msk /*!<Parity Error bit */
16091 #define SPDIFRX_DR0_V_Pos (25U)
16092 #define SPDIFRX_DR0_V_Msk (0x1UL << SPDIFRX_DR0_V_Pos) /*!< 0x02000000 */
16093 #define SPDIFRX_DR0_V SPDIFRX_DR0_V_Msk /*!<Validity bit */
16094 #define SPDIFRX_DR0_U_Pos (26U)
16095 #define SPDIFRX_DR0_U_Msk (0x1UL << SPDIFRX_DR0_U_Pos) /*!< 0x04000000 */
16096 #define SPDIFRX_DR0_U SPDIFRX_DR0_U_Msk /*!<User bit */
16097 #define SPDIFRX_DR0_C_Pos (27U)
16098 #define SPDIFRX_DR0_C_Msk (0x1UL << SPDIFRX_DR0_C_Pos) /*!< 0x08000000 */
16099 #define SPDIFRX_DR0_C SPDIFRX_DR0_C_Msk /*!<Channel Status bit */
16100 #define SPDIFRX_DR0_PT_Pos (28U)
16101 #define SPDIFRX_DR0_PT_Msk (0x3UL << SPDIFRX_DR0_PT_Pos) /*!< 0x30000000 */
16102 #define SPDIFRX_DR0_PT SPDIFRX_DR0_PT_Msk /*!<Preamble Type */
16103
16104 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b01 case) *******************/
16105 #define SPDIFRX_DR1_DR_Pos (8U)
16106 #define SPDIFRX_DR1_DR_Msk (0xFFFFFFUL << SPDIFRX_DR1_DR_Pos) /*!< 0xFFFFFF00 */
16107 #define SPDIFRX_DR1_DR SPDIFRX_DR1_DR_Msk /*!<Data value */
16108 #define SPDIFRX_DR1_PT_Pos (4U)
16109 #define SPDIFRX_DR1_PT_Msk (0x3UL << SPDIFRX_DR1_PT_Pos) /*!< 0x00000030 */
16110 #define SPDIFRX_DR1_PT SPDIFRX_DR1_PT_Msk /*!<Preamble Type */
16111 #define SPDIFRX_DR1_C_Pos (3U)
16112 #define SPDIFRX_DR1_C_Msk (0x1UL << SPDIFRX_DR1_C_Pos) /*!< 0x00000008 */
16113 #define SPDIFRX_DR1_C SPDIFRX_DR1_C_Msk /*!<Channel Status bit */
16114 #define SPDIFRX_DR1_U_Pos (2U)
16115 #define SPDIFRX_DR1_U_Msk (0x1UL << SPDIFRX_DR1_U_Pos) /*!< 0x00000004 */
16116 #define SPDIFRX_DR1_U SPDIFRX_DR1_U_Msk /*!<User bit */
16117 #define SPDIFRX_DR1_V_Pos (1U)
16118 #define SPDIFRX_DR1_V_Msk (0x1UL << SPDIFRX_DR1_V_Pos) /*!< 0x00000002 */
16119 #define SPDIFRX_DR1_V SPDIFRX_DR1_V_Msk /*!<Validity bit */
16120 #define SPDIFRX_DR1_PE_Pos (0U)
16121 #define SPDIFRX_DR1_PE_Msk (0x1UL << SPDIFRX_DR1_PE_Pos) /*!< 0x00000001 */
16122 #define SPDIFRX_DR1_PE SPDIFRX_DR1_PE_Msk /*!<Parity Error bit */
16123
16124 /******************* Bit definition for SPDIFRX_DR register (DRFMT = 0b10 case) *******************/
16125 #define SPDIFRX_DR1_DRNL1_Pos (16U)
16126 #define SPDIFRX_DR1_DRNL1_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL1_Pos) /*!< 0xFFFF0000 */
16127 #define SPDIFRX_DR1_DRNL1 SPDIFRX_DR1_DRNL1_Msk /*!<Data value Channel B */
16128 #define SPDIFRX_DR1_DRNL2_Pos (0U)
16129 #define SPDIFRX_DR1_DRNL2_Msk (0xFFFFUL << SPDIFRX_DR1_DRNL2_Pos) /*!< 0x0000FFFF */
16130 #define SPDIFRX_DR1_DRNL2 SPDIFRX_DR1_DRNL2_Msk /*!<Data value Channel A */
16131
16132 /******************* Bit definition for SPDIFRX_CSR register *******************/
16133 #define SPDIFRX_CSR_USR_Pos (0U)
16134 #define SPDIFRX_CSR_USR_Msk (0xFFFFUL << SPDIFRX_CSR_USR_Pos) /*!< 0x0000FFFF */
16135 #define SPDIFRX_CSR_USR SPDIFRX_CSR_USR_Msk /*!<User data information */
16136 #define SPDIFRX_CSR_CS_Pos (16U)
16137 #define SPDIFRX_CSR_CS_Msk (0xFFUL << SPDIFRX_CSR_CS_Pos) /*!< 0x00FF0000 */
16138 #define SPDIFRX_CSR_CS SPDIFRX_CSR_CS_Msk /*!<Channel A status information */
16139 #define SPDIFRX_CSR_SOB_Pos (24U)
16140 #define SPDIFRX_CSR_SOB_Msk (0x1UL << SPDIFRX_CSR_SOB_Pos) /*!< 0x01000000 */
16141 #define SPDIFRX_CSR_SOB SPDIFRX_CSR_SOB_Msk /*!<Start Of Block */
16142
16143 /******************* Bit definition for SPDIFRX_DIR register *******************/
16144 #define SPDIFRX_DIR_THI_Pos (0U)
16145 #define SPDIFRX_DIR_THI_Msk (0x1FFFUL << SPDIFRX_DIR_THI_Pos) /*!< 0x00001FFF */
16146 #define SPDIFRX_DIR_THI SPDIFRX_DIR_THI_Msk /*!<Threshold LOW */
16147 #define SPDIFRX_DIR_TLO_Pos (16U)
16148 #define SPDIFRX_DIR_TLO_Msk (0x1FFFUL << SPDIFRX_DIR_TLO_Pos) /*!< 0x1FFF0000 */
16149 #define SPDIFRX_DIR_TLO SPDIFRX_DIR_TLO_Msk /*!<Threshold HIGH */
16150
16151 /******************* Bit definition for SPDIFRX_VERR register *******************/
16152 #define SPDIFRX_VERR_MINREV_Pos (0U)
16153 #define SPDIFRX_VERR_MINREV_Msk (0xFUL << SPDIFRX_VERR_MINREV_Pos) /*!< 0x0000000F */
16154 #define SPDIFRX_VERR_MINREV SPDIFRX_VERR_MINREV_Msk /*!<SPDIFRX Minor revision */
16155 #define SPDIFRX_VERR_MAJREV_Pos (4U)
16156 #define SPDIFRX_VERR_MAJREV_Msk (0xFUL << SPDIFRX_VERR_MAJREV_Pos) /*!< 0x000000F0 */
16157 #define SPDIFRX_VERR_MAJREV SPDIFRX_VERR_MAJREV_Msk /*!<SPDIFRX Major revision */
16158
16159 /******************* Bit definition for SPDIFRX_IDR register *******************/
16160 #define SPDIFRX_IDR_ID_Pos (0U)
16161 #define SPDIFRX_IDR_ID_Msk (0xFFFFFFFFUL << SPDIFRX_IDR_ID_Pos) /*!< 0xFFFFFFFF */
16162 #define SPDIFRX_IDR_ID SPDIFRX_IDR_ID_Msk /*!<SPDIFRX identifier */
16163
16164 /******************* Bit definition for SPDIFRX_SIDR register *******************/
16165 #define SPDIFRX_SIDR_SID_Pos (0U)
16166 #define SPDIFRX_SIDR_SID_Msk (0xFFFFFFFFUL << SPDIFRX_SIDR_SID_Pos) /*!< 0xFFFFFFFF */
16167 #define SPDIFRX_SIDR_SID SPDIFRX_SIDR_SID_Msk /*!<Size of the memory region allocated to SPDIFRX registers */
16168
16169 /******************************************************************************/
16170 /* */
16171 /* Serial Audio Interface */
16172 /* */
16173 /******************************************************************************/
16174 /******************************* SAI VERSION ********************************/
16175 #define SAI_VER_V2_1
16176
16177 /******************** Bit definition for SAI_GCR register *******************/
16178 #define SAI_GCR_SYNCIN_Pos (0U)
16179 #define SAI_GCR_SYNCIN_Msk (0x3UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000003 */
16180 #define SAI_GCR_SYNCIN SAI_GCR_SYNCIN_Msk /*!<SYNCIN[1:0] bits (Synchronization Inputs) */
16181 #define SAI_GCR_SYNCIN_0 (0x1UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000001 */
16182 #define SAI_GCR_SYNCIN_1 (0x2UL << SAI_GCR_SYNCIN_Pos) /*!< 0x00000002 */
16183
16184 #define SAI_GCR_SYNCOUT_Pos (4U)
16185 #define SAI_GCR_SYNCOUT_Msk (0x3UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000030 */
16186 #define SAI_GCR_SYNCOUT SAI_GCR_SYNCOUT_Msk /*!<SYNCOUT[1:0] bits (Synchronization Outputs) */
16187 #define SAI_GCR_SYNCOUT_0 (0x1UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000010 */
16188 #define SAI_GCR_SYNCOUT_1 (0x2UL << SAI_GCR_SYNCOUT_Pos) /*!< 0x00000020 */
16189
16190 /******************* Bit definition for SAI_xCR1 register *******************/
16191 #define SAI_xCR1_MODE_Pos (0U)
16192 #define SAI_xCR1_MODE_Msk (0x3UL << SAI_xCR1_MODE_Pos) /*!< 0x00000003 */
16193 #define SAI_xCR1_MODE SAI_xCR1_MODE_Msk /*!<MODE[1:0] bits (Audio Block Mode) */
16194 #define SAI_xCR1_MODE_0 (0x1UL << SAI_xCR1_MODE_Pos) /*!< 0x00000001 */
16195 #define SAI_xCR1_MODE_1 (0x2UL << SAI_xCR1_MODE_Pos) /*!< 0x00000002 */
16196
16197 #define SAI_xCR1_PRTCFG_Pos (2U)
16198 #define SAI_xCR1_PRTCFG_Msk (0x3UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x0000000C */
16199 #define SAI_xCR1_PRTCFG SAI_xCR1_PRTCFG_Msk /*!<PRTCFG[1:0] bits (Protocol Configuration) */
16200 #define SAI_xCR1_PRTCFG_0 (0x1UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000004 */
16201 #define SAI_xCR1_PRTCFG_1 (0x2UL << SAI_xCR1_PRTCFG_Pos) /*!< 0x00000008 */
16202
16203 #define SAI_xCR1_DS_Pos (5U)
16204 #define SAI_xCR1_DS_Msk (0x7UL << SAI_xCR1_DS_Pos) /*!< 0x000000E0 */
16205 #define SAI_xCR1_DS SAI_xCR1_DS_Msk /*!<DS[1:0] bits (Data Size) */
16206 #define SAI_xCR1_DS_0 (0x1UL << SAI_xCR1_DS_Pos) /*!< 0x00000020 */
16207 #define SAI_xCR1_DS_1 (0x2UL << SAI_xCR1_DS_Pos) /*!< 0x00000040 */
16208 #define SAI_xCR1_DS_2 (0x4UL << SAI_xCR1_DS_Pos) /*!< 0x00000080 */
16209
16210 #define SAI_xCR1_LSBFIRST_Pos (8U)
16211 #define SAI_xCR1_LSBFIRST_Msk (0x1UL << SAI_xCR1_LSBFIRST_Pos) /*!< 0x00000100 */
16212 #define SAI_xCR1_LSBFIRST SAI_xCR1_LSBFIRST_Msk /*!<LSB First Configuration */
16213 #define SAI_xCR1_CKSTR_Pos (9U)
16214 #define SAI_xCR1_CKSTR_Msk (0x1UL << SAI_xCR1_CKSTR_Pos) /*!< 0x00000200 */
16215 #define SAI_xCR1_CKSTR SAI_xCR1_CKSTR_Msk /*!<ClocK STRobing edge */
16216
16217 #define SAI_xCR1_SYNCEN_Pos (10U)
16218 #define SAI_xCR1_SYNCEN_Msk (0x3UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000C00 */
16219 #define SAI_xCR1_SYNCEN SAI_xCR1_SYNCEN_Msk /*!<SYNCEN[1:0](SYNChronization ENable) */
16220 #define SAI_xCR1_SYNCEN_0 (0x1UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000400 */
16221 #define SAI_xCR1_SYNCEN_1 (0x2UL << SAI_xCR1_SYNCEN_Pos) /*!< 0x00000800 */
16222
16223 #define SAI_xCR1_MONO_Pos (12U)
16224 #define SAI_xCR1_MONO_Msk (0x1UL << SAI_xCR1_MONO_Pos) /*!< 0x00001000 */
16225 #define SAI_xCR1_MONO SAI_xCR1_MONO_Msk /*!<Mono mode */
16226 #define SAI_xCR1_OUTDRIV_Pos (13U)
16227 #define SAI_xCR1_OUTDRIV_Msk (0x1UL << SAI_xCR1_OUTDRIV_Pos) /*!< 0x00002000 */
16228 #define SAI_xCR1_OUTDRIV SAI_xCR1_OUTDRIV_Msk /*!<Output Drive */
16229 #define SAI_xCR1_SAIEN_Pos (16U)
16230 #define SAI_xCR1_SAIEN_Msk (0x1UL << SAI_xCR1_SAIEN_Pos) /*!< 0x00010000 */
16231 #define SAI_xCR1_SAIEN SAI_xCR1_SAIEN_Msk /*!<Audio Block enable */
16232 #define SAI_xCR1_DMAEN_Pos (17U)
16233 #define SAI_xCR1_DMAEN_Msk (0x1UL << SAI_xCR1_DMAEN_Pos) /*!< 0x00020000 */
16234 #define SAI_xCR1_DMAEN SAI_xCR1_DMAEN_Msk /*!<DMA enable */
16235 #define SAI_xCR1_NODIV_Pos (19U)
16236 #define SAI_xCR1_NODIV_Msk (0x1UL << SAI_xCR1_NODIV_Pos) /*!< 0x00080000 */
16237 #define SAI_xCR1_NODIV SAI_xCR1_NODIV_Msk /*!<No Divider Configuration */
16238
16239 #define SAI_xCR1_MCKDIV_Pos (20U)
16240 #define SAI_xCR1_MCKDIV_Msk (0x3FUL << SAI_xCR1_MCKDIV_Pos) /*!< 0x03F00000 */
16241 #define SAI_xCR1_MCKDIV SAI_xCR1_MCKDIV_Msk /*!<MCKDIV[5:0] (Master ClocK Divider) */
16242 #define SAI_xCR1_MCKDIV_0 (0x01UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00100000 */
16243 #define SAI_xCR1_MCKDIV_1 (0x02UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00200000 */
16244 #define SAI_xCR1_MCKDIV_2 (0x04UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00400000 */
16245 #define SAI_xCR1_MCKDIV_3 (0x08UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x00800000 */
16246 #define SAI_xCR1_MCKDIV_4 (0x10UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x01000000 */
16247 #define SAI_xCR1_MCKDIV_5 (0x20UL << SAI_xCR1_MCKDIV_Pos) /*!< 0x02000000 */
16248
16249 #define SAI_xCR1_MCKEN_Pos (27U)
16250 #define SAI_xCR1_MCKEN_Msk (0x1UL << SAI_xCR1_MCKEN_Pos) /*!< 0x08000000 */
16251 #define SAI_xCR1_MCKEN SAI_xCR1_MCKEN_Msk /*!<Master ClocK enable */
16252
16253 #define SAI_xCR1_OSR_Pos (26U)
16254 #define SAI_xCR1_OSR_Msk (0x1UL << SAI_xCR1_OSR_Pos) /*!< 0x04000000 */
16255 #define SAI_xCR1_OSR SAI_xCR1_OSR_Msk /*!<OverSampling Ratio for master clock */
16256
16257 /* Legacy define */
16258 #define SAI_xCR1_NOMCK SAI_xCR1_NODIV
16259
16260 /******************* Bit definition for SAI_xCR2 register *******************/
16261 #define SAI_xCR2_FTH_Pos (0U)
16262 #define SAI_xCR2_FTH_Msk (0x7UL << SAI_xCR2_FTH_Pos) /*!< 0x00000007 */
16263 #define SAI_xCR2_FTH SAI_xCR2_FTH_Msk /*!<FTH[2:0](Fifo THreshold) */
16264 #define SAI_xCR2_FTH_0 (0x1UL << SAI_xCR2_FTH_Pos) /*!< 0x00000001 */
16265 #define SAI_xCR2_FTH_1 (0x2UL << SAI_xCR2_FTH_Pos) /*!< 0x00000002 */
16266 #define SAI_xCR2_FTH_2 (0x4UL << SAI_xCR2_FTH_Pos) /*!< 0x00000004 */
16267
16268 #define SAI_xCR2_FFLUSH_Pos (3U)
16269 #define SAI_xCR2_FFLUSH_Msk (0x1UL << SAI_xCR2_FFLUSH_Pos) /*!< 0x00000008 */
16270 #define SAI_xCR2_FFLUSH SAI_xCR2_FFLUSH_Msk /*!<Fifo FLUSH */
16271 #define SAI_xCR2_TRIS_Pos (4U)
16272 #define SAI_xCR2_TRIS_Msk (0x1UL << SAI_xCR2_TRIS_Pos) /*!< 0x00000010 */
16273 #define SAI_xCR2_TRIS SAI_xCR2_TRIS_Msk /*!<TRIState Management on data line */
16274 #define SAI_xCR2_MUTE_Pos (5U)
16275 #define SAI_xCR2_MUTE_Msk (0x1UL << SAI_xCR2_MUTE_Pos) /*!< 0x00000020 */
16276 #define SAI_xCR2_MUTE SAI_xCR2_MUTE_Msk /*!<Mute mode */
16277 #define SAI_xCR2_MUTEVAL_Pos (6U)
16278 #define SAI_xCR2_MUTEVAL_Msk (0x1UL << SAI_xCR2_MUTEVAL_Pos) /*!< 0x00000040 */
16279 #define SAI_xCR2_MUTEVAL SAI_xCR2_MUTEVAL_Msk /*!<Muate value */
16280
16281 #define SAI_xCR2_MUTECNT_Pos (7U)
16282 #define SAI_xCR2_MUTECNT_Msk (0x3FUL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001F80 */
16283 #define SAI_xCR2_MUTECNT SAI_xCR2_MUTECNT_Msk /*!<MUTECNT[5:0] (MUTE counter) */
16284 #define SAI_xCR2_MUTECNT_0 (0x01UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000080 */
16285 #define SAI_xCR2_MUTECNT_1 (0x02UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000100 */
16286 #define SAI_xCR2_MUTECNT_2 (0x04UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000200 */
16287 #define SAI_xCR2_MUTECNT_3 (0x08UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000400 */
16288 #define SAI_xCR2_MUTECNT_4 (0x10UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00000800 */
16289 #define SAI_xCR2_MUTECNT_5 (0x20UL << SAI_xCR2_MUTECNT_Pos) /*!< 0x00001000 */
16290
16291 #define SAI_xCR2_CPL_Pos (13U)
16292 #define SAI_xCR2_CPL_Msk (0x1UL << SAI_xCR2_CPL_Pos) /*!< 0x00002000 */
16293 #define SAI_xCR2_CPL SAI_xCR2_CPL_Msk /*!< Complement Bit */
16294
16295 #define SAI_xCR2_COMP_Pos (14U)
16296 #define SAI_xCR2_COMP_Msk (0x3UL << SAI_xCR2_COMP_Pos) /*!< 0x0000C000 */
16297 #define SAI_xCR2_COMP SAI_xCR2_COMP_Msk /*!<COMP[1:0] (Companding mode) */
16298 #define SAI_xCR2_COMP_0 (0x1UL << SAI_xCR2_COMP_Pos) /*!< 0x00004000 */
16299 #define SAI_xCR2_COMP_1 (0x2UL << SAI_xCR2_COMP_Pos) /*!< 0x00008000 */
16300
16301 /****************** Bit definition for SAI_xFRCR register *******************/
16302 #define SAI_xFRCR_FRL_Pos (0U)
16303 #define SAI_xFRCR_FRL_Msk (0xFFUL << SAI_xFRCR_FRL_Pos) /*!< 0x000000FF */
16304 #define SAI_xFRCR_FRL SAI_xFRCR_FRL_Msk /*!<FRL[7:0](FRame Length) */
16305 #define SAI_xFRCR_FRL_0 (0x01UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000001 */
16306 #define SAI_xFRCR_FRL_1 (0x02UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000002 */
16307 #define SAI_xFRCR_FRL_2 (0x04UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000004 */
16308 #define SAI_xFRCR_FRL_3 (0x08UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000008 */
16309 #define SAI_xFRCR_FRL_4 (0x10UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000010 */
16310 #define SAI_xFRCR_FRL_5 (0x20UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000020 */
16311 #define SAI_xFRCR_FRL_6 (0x40UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000040 */
16312 #define SAI_xFRCR_FRL_7 (0x80UL << SAI_xFRCR_FRL_Pos) /*!< 0x00000080 */
16313
16314 #define SAI_xFRCR_FSALL_Pos (8U)
16315 #define SAI_xFRCR_FSALL_Msk (0x7FUL << SAI_xFRCR_FSALL_Pos) /*!< 0x00007F00 */
16316 #define SAI_xFRCR_FSALL SAI_xFRCR_FSALL_Msk /*!<FSALL[6:0] (Frame Synchronization Active Level Length) */
16317 #define SAI_xFRCR_FSALL_0 (0x01UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000100 */
16318 #define SAI_xFRCR_FSALL_1 (0x02UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000200 */
16319 #define SAI_xFRCR_FSALL_2 (0x04UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000400 */
16320 #define SAI_xFRCR_FSALL_3 (0x08UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00000800 */
16321 #define SAI_xFRCR_FSALL_4 (0x10UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00001000 */
16322 #define SAI_xFRCR_FSALL_5 (0x20UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00002000 */
16323 #define SAI_xFRCR_FSALL_6 (0x40UL << SAI_xFRCR_FSALL_Pos) /*!< 0x00004000 */
16324
16325 #define SAI_xFRCR_FSDEF_Pos (16U)
16326 #define SAI_xFRCR_FSDEF_Msk (0x1UL << SAI_xFRCR_FSDEF_Pos) /*!< 0x00010000 */
16327 #define SAI_xFRCR_FSDEF SAI_xFRCR_FSDEF_Msk /*!<Frame Synchronization Definition */
16328 #define SAI_xFRCR_FSPOL_Pos (17U)
16329 #define SAI_xFRCR_FSPOL_Msk (0x1UL << SAI_xFRCR_FSPOL_Pos) /*!< 0x00020000 */
16330 #define SAI_xFRCR_FSPOL SAI_xFRCR_FSPOL_Msk /*!<Frame Synchronization POLarity */
16331 #define SAI_xFRCR_FSOFF_Pos (18U)
16332 #define SAI_xFRCR_FSOFF_Msk (0x1UL << SAI_xFRCR_FSOFF_Pos) /*!< 0x00040000 */
16333 #define SAI_xFRCR_FSOFF SAI_xFRCR_FSOFF_Msk /*!<Frame Synchronization OFFset */
16334
16335 /* Legacy define */
16336 #define SAI_xFRCR_FSPO SAI_xFRCR_FSPOL
16337
16338 /****************** Bit definition for SAI_xSLOTR register *******************/
16339 #define SAI_xSLOTR_FBOFF_Pos (0U)
16340 #define SAI_xSLOTR_FBOFF_Msk (0x1FUL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x0000001F */
16341 #define SAI_xSLOTR_FBOFF SAI_xSLOTR_FBOFF_Msk /*!<FBOFF[4:0](First Bit Offset) */
16342 #define SAI_xSLOTR_FBOFF_0 (0x01UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000001 */
16343 #define SAI_xSLOTR_FBOFF_1 (0x02UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000002 */
16344 #define SAI_xSLOTR_FBOFF_2 (0x04UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000004 */
16345 #define SAI_xSLOTR_FBOFF_3 (0x08UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000008 */
16346 #define SAI_xSLOTR_FBOFF_4 (0x10UL << SAI_xSLOTR_FBOFF_Pos) /*!< 0x00000010 */
16347
16348 #define SAI_xSLOTR_SLOTSZ_Pos (6U)
16349 #define SAI_xSLOTR_SLOTSZ_Msk (0x3UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x000000C0 */
16350 #define SAI_xSLOTR_SLOTSZ SAI_xSLOTR_SLOTSZ_Msk /*!<SLOTSZ[1:0] (Slot size) */
16351 #define SAI_xSLOTR_SLOTSZ_0 (0x1UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000040 */
16352 #define SAI_xSLOTR_SLOTSZ_1 (0x2UL << SAI_xSLOTR_SLOTSZ_Pos) /*!< 0x00000080 */
16353
16354 #define SAI_xSLOTR_NBSLOT_Pos (8U)
16355 #define SAI_xSLOTR_NBSLOT_Msk (0xFUL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000F00 */
16356 #define SAI_xSLOTR_NBSLOT SAI_xSLOTR_NBSLOT_Msk /*!<NBSLOT[3:0] (Number of Slot in audio Frame) */
16357 #define SAI_xSLOTR_NBSLOT_0 (0x1UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000100 */
16358 #define SAI_xSLOTR_NBSLOT_1 (0x2UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000200 */
16359 #define SAI_xSLOTR_NBSLOT_2 (0x4UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000400 */
16360 #define SAI_xSLOTR_NBSLOT_3 (0x8UL << SAI_xSLOTR_NBSLOT_Pos) /*!< 0x00000800 */
16361
16362 #define SAI_xSLOTR_SLOTEN_Pos (16U)
16363 #define SAI_xSLOTR_SLOTEN_Msk (0xFFFFUL << SAI_xSLOTR_SLOTEN_Pos) /*!< 0xFFFF0000 */
16364 #define SAI_xSLOTR_SLOTEN SAI_xSLOTR_SLOTEN_Msk /*!<SLOTEN[15:0] (Slot Enable) */
16365
16366 /******************* Bit definition for SAI_xIMR register *******************/
16367 #define SAI_xIMR_OVRUDRIE_Pos (0U)
16368 #define SAI_xIMR_OVRUDRIE_Msk (0x1UL << SAI_xIMR_OVRUDRIE_Pos) /*!< 0x00000001 */
16369 #define SAI_xIMR_OVRUDRIE SAI_xIMR_OVRUDRIE_Msk /*!<Overrun underrun interrupt enable */
16370 #define SAI_xIMR_MUTEDETIE_Pos (1U)
16371 #define SAI_xIMR_MUTEDETIE_Msk (0x1UL << SAI_xIMR_MUTEDETIE_Pos) /*!< 0x00000002 */
16372 #define SAI_xIMR_MUTEDETIE SAI_xIMR_MUTEDETIE_Msk /*!<Mute detection interrupt enable */
16373 #define SAI_xIMR_WCKCFGIE_Pos (2U)
16374 #define SAI_xIMR_WCKCFGIE_Msk (0x1UL << SAI_xIMR_WCKCFGIE_Pos) /*!< 0x00000004 */
16375 #define SAI_xIMR_WCKCFGIE SAI_xIMR_WCKCFGIE_Msk /*!<Wrong Clock Configuration interrupt enable */
16376 #define SAI_xIMR_FREQIE_Pos (3U)
16377 #define SAI_xIMR_FREQIE_Msk (0x1UL << SAI_xIMR_FREQIE_Pos) /*!< 0x00000008 */
16378 #define SAI_xIMR_FREQIE SAI_xIMR_FREQIE_Msk /*!<FIFO request interrupt enable */
16379 #define SAI_xIMR_CNRDYIE_Pos (4U)
16380 #define SAI_xIMR_CNRDYIE_Msk (0x1UL << SAI_xIMR_CNRDYIE_Pos) /*!< 0x00000010 */
16381 #define SAI_xIMR_CNRDYIE SAI_xIMR_CNRDYIE_Msk /*!<Codec not ready interrupt enable */
16382 #define SAI_xIMR_AFSDETIE_Pos (5U)
16383 #define SAI_xIMR_AFSDETIE_Msk (0x1UL << SAI_xIMR_AFSDETIE_Pos) /*!< 0x00000020 */
16384 #define SAI_xIMR_AFSDETIE SAI_xIMR_AFSDETIE_Msk /*!<Anticipated frame synchronization detection interrupt enable */
16385 #define SAI_xIMR_LFSDETIE_Pos (6U)
16386 #define SAI_xIMR_LFSDETIE_Msk (0x1UL << SAI_xIMR_LFSDETIE_Pos) /*!< 0x00000040 */
16387 #define SAI_xIMR_LFSDETIE SAI_xIMR_LFSDETIE_Msk /*!<Late frame synchronization detection interrupt enable */
16388
16389 /******************** Bit definition for SAI_xSR register *******************/
16390 #define SAI_xSR_OVRUDR_Pos (0U)
16391 #define SAI_xSR_OVRUDR_Msk (0x1UL << SAI_xSR_OVRUDR_Pos) /*!< 0x00000001 */
16392 #define SAI_xSR_OVRUDR SAI_xSR_OVRUDR_Msk /*!<Overrun underrun */
16393 #define SAI_xSR_MUTEDET_Pos (1U)
16394 #define SAI_xSR_MUTEDET_Msk (0x1UL << SAI_xSR_MUTEDET_Pos) /*!< 0x00000002 */
16395 #define SAI_xSR_MUTEDET SAI_xSR_MUTEDET_Msk /*!<Mute detection */
16396 #define SAI_xSR_WCKCFG_Pos (2U)
16397 #define SAI_xSR_WCKCFG_Msk (0x1UL << SAI_xSR_WCKCFG_Pos) /*!< 0x00000004 */
16398 #define SAI_xSR_WCKCFG SAI_xSR_WCKCFG_Msk /*!<Wrong Clock Configuration */
16399 #define SAI_xSR_FREQ_Pos (3U)
16400 #define SAI_xSR_FREQ_Msk (0x1UL << SAI_xSR_FREQ_Pos) /*!< 0x00000008 */
16401 #define SAI_xSR_FREQ SAI_xSR_FREQ_Msk /*!<FIFO request */
16402 #define SAI_xSR_CNRDY_Pos (4U)
16403 #define SAI_xSR_CNRDY_Msk (0x1UL << SAI_xSR_CNRDY_Pos) /*!< 0x00000010 */
16404 #define SAI_xSR_CNRDY SAI_xSR_CNRDY_Msk /*!<Codec not ready */
16405 #define SAI_xSR_AFSDET_Pos (5U)
16406 #define SAI_xSR_AFSDET_Msk (0x1UL << SAI_xSR_AFSDET_Pos) /*!< 0x00000020 */
16407 #define SAI_xSR_AFSDET SAI_xSR_AFSDET_Msk /*!<Anticipated frame synchronization detection */
16408 #define SAI_xSR_LFSDET_Pos (6U)
16409 #define SAI_xSR_LFSDET_Msk (0x1UL << SAI_xSR_LFSDET_Pos) /*!< 0x00000040 */
16410 #define SAI_xSR_LFSDET SAI_xSR_LFSDET_Msk /*!<Late frame synchronization detection */
16411
16412 #define SAI_xSR_FLVL_Pos (16U)
16413 #define SAI_xSR_FLVL_Msk (0x7UL << SAI_xSR_FLVL_Pos) /*!< 0x00070000 */
16414 #define SAI_xSR_FLVL SAI_xSR_FLVL_Msk /*!<FLVL[2:0] (FIFO Level Threshold) */
16415 #define SAI_xSR_FLVL_0 (0x1UL << SAI_xSR_FLVL_Pos) /*!< 0x00010000 */
16416 #define SAI_xSR_FLVL_1 (0x2UL << SAI_xSR_FLVL_Pos) /*!< 0x00020000 */
16417 #define SAI_xSR_FLVL_2 (0x4UL << SAI_xSR_FLVL_Pos) /*!< 0x00040000 */
16418
16419 /****************** Bit definition for SAI_xCLRFR register ******************/
16420 #define SAI_xCLRFR_COVRUDR_Pos (0U)
16421 #define SAI_xCLRFR_COVRUDR_Msk (0x1UL << SAI_xCLRFR_COVRUDR_Pos) /*!< 0x00000001 */
16422 #define SAI_xCLRFR_COVRUDR SAI_xCLRFR_COVRUDR_Msk /*!<Clear Overrun underrun */
16423 #define SAI_xCLRFR_CMUTEDET_Pos (1U)
16424 #define SAI_xCLRFR_CMUTEDET_Msk (0x1UL << SAI_xCLRFR_CMUTEDET_Pos) /*!< 0x00000002 */
16425 #define SAI_xCLRFR_CMUTEDET SAI_xCLRFR_CMUTEDET_Msk /*!<Clear Mute detection */
16426 #define SAI_xCLRFR_CWCKCFG_Pos (2U)
16427 #define SAI_xCLRFR_CWCKCFG_Msk (0x1UL << SAI_xCLRFR_CWCKCFG_Pos) /*!< 0x00000004 */
16428 #define SAI_xCLRFR_CWCKCFG SAI_xCLRFR_CWCKCFG_Msk /*!<Clear Wrong Clock Configuration */
16429 #define SAI_xCLRFR_CFREQ_Pos (3U)
16430 #define SAI_xCLRFR_CFREQ_Msk (0x1UL << SAI_xCLRFR_CFREQ_Pos) /*!< 0x00000008 */
16431 #define SAI_xCLRFR_CFREQ SAI_xCLRFR_CFREQ_Msk /*!<Clear FIFO request */
16432 #define SAI_xCLRFR_CCNRDY_Pos (4U)
16433 #define SAI_xCLRFR_CCNRDY_Msk (0x1UL << SAI_xCLRFR_CCNRDY_Pos) /*!< 0x00000010 */
16434 #define SAI_xCLRFR_CCNRDY SAI_xCLRFR_CCNRDY_Msk /*!<Clear Codec not ready */
16435 #define SAI_xCLRFR_CAFSDET_Pos (5U)
16436 #define SAI_xCLRFR_CAFSDET_Msk (0x1UL << SAI_xCLRFR_CAFSDET_Pos) /*!< 0x00000020 */
16437 #define SAI_xCLRFR_CAFSDET SAI_xCLRFR_CAFSDET_Msk /*!<Clear Anticipated frame synchronization detection */
16438 #define SAI_xCLRFR_CLFSDET_Pos (6U)
16439 #define SAI_xCLRFR_CLFSDET_Msk (0x1UL << SAI_xCLRFR_CLFSDET_Pos) /*!< 0x00000040 */
16440 #define SAI_xCLRFR_CLFSDET SAI_xCLRFR_CLFSDET_Msk /*!<Clear Late frame synchronization detection */
16441
16442 /****************** Bit definition for SAI_xDR register *********************/
16443 #define SAI_xDR_DATA_Pos (0U)
16444 #define SAI_xDR_DATA_Msk (0xFFFFFFFFUL << SAI_xDR_DATA_Pos) /*!< 0xFFFFFFFF */
16445 #define SAI_xDR_DATA SAI_xDR_DATA_Msk
16446
16447 /******************* Bit definition for SAI_PDMCR register ******************/
16448 #define SAI_PDMCR_PDMEN_Pos (0U)
16449 #define SAI_PDMCR_PDMEN_Msk (0x1UL << SAI_PDMCR_PDMEN_Pos) /*!< 0x00000001 */
16450 #define SAI_PDMCR_PDMEN SAI_PDMCR_PDMEN_Msk /*!<PDM Enable */
16451
16452 #define SAI_PDMCR_MICNBR_Pos (4U)
16453 #define SAI_PDMCR_MICNBR_Msk (0x3UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000030 */
16454 #define SAI_PDMCR_MICNBR SAI_PDMCR_MICNBR_Msk /*!<Number of microphones */
16455 #define SAI_PDMCR_MICNBR_0 (0x1UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000010 */
16456 #define SAI_PDMCR_MICNBR_1 (0x2UL << SAI_PDMCR_MICNBR_Pos) /*!< 0x00000020 */
16457
16458 #define SAI_PDMCR_CKEN1_Pos (8U)
16459 #define SAI_PDMCR_CKEN1_Msk (0x1UL << SAI_PDMCR_CKEN1_Pos) /*!< 0x00000100 */
16460 #define SAI_PDMCR_CKEN1 SAI_PDMCR_CKEN1_Msk /*!<Clock enable of bitstream clock number 1 */
16461 #define SAI_PDMCR_CKEN2_Pos (9U)
16462 #define SAI_PDMCR_CKEN2_Msk (0x1UL << SAI_PDMCR_CKEN2_Pos) /*!< 0x00000200 */
16463 #define SAI_PDMCR_CKEN2 SAI_PDMCR_CKEN2_Msk /*!<Clock enable of bitstream clock number 2 */
16464 #define SAI_PDMCR_CKEN3_Pos (10U)
16465 #define SAI_PDMCR_CKEN3_Msk (0x1UL << SAI_PDMCR_CKEN3_Pos) /*!< 0x00000400 */
16466 #define SAI_PDMCR_CKEN3 SAI_PDMCR_CKEN3_Msk /*!<Clock enable of bitstream clock number 3 */
16467 #define SAI_PDMCR_CKEN4_Pos (11U)
16468 #define SAI_PDMCR_CKEN4_Msk (0x1UL << SAI_PDMCR_CKEN4_Pos) /*!< 0x00000800 */
16469 #define SAI_PDMCR_CKEN4 SAI_PDMCR_CKEN4_Msk /*!<Clock enable of bitstream clock number 4 */
16470
16471 /****************** Bit definition for SAI_PDMDLY register ******************/
16472 #define SAI_PDMDLY_DLYM1L_Pos (0U)
16473 #define SAI_PDMDLY_DLYM1L_Msk (0x7UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000007 */
16474 #define SAI_PDMDLY_DLYM1L SAI_PDMDLY_DLYM1L_Msk /*!<DLYM1L[2:0] (Delay line adjust for left microphone of pair 1) */
16475 #define SAI_PDMDLY_DLYM1L_0 (0x1UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000001 */
16476 #define SAI_PDMDLY_DLYM1L_1 (0x2UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000002 */
16477 #define SAI_PDMDLY_DLYM1L_2 (0x4UL << SAI_PDMDLY_DLYM1L_Pos) /*!< 0x00000004 */
16478
16479 #define SAI_PDMDLY_DLYM1R_Pos (4U)
16480 #define SAI_PDMDLY_DLYM1R_Msk (0x7UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000070 */
16481 #define SAI_PDMDLY_DLYM1R SAI_PDMDLY_DLYM1R_Msk /*!<DLYM1R[2:0] (Delay line adjust for right microphone of pair 1) */
16482 #define SAI_PDMDLY_DLYM1R_0 (0x1UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000010 */
16483 #define SAI_PDMDLY_DLYM1R_1 (0x2UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000020 */
16484 #define SAI_PDMDLY_DLYM1R_2 (0x4UL << SAI_PDMDLY_DLYM1R_Pos) /*!< 0x00000040 */
16485
16486 #define SAI_PDMDLY_DLYM2L_Pos (8U)
16487 #define SAI_PDMDLY_DLYM2L_Msk (0x7UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000700 */
16488 #define SAI_PDMDLY_DLYM2L SAI_PDMDLY_DLYM2L_Msk /*!<DLYM2L[2:0] (Delay line adjust for left microphone of pair 2) */
16489 #define SAI_PDMDLY_DLYM2L_0 (0x1UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000100 */
16490 #define SAI_PDMDLY_DLYM2L_1 (0x2UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000200 */
16491 #define SAI_PDMDLY_DLYM2L_2 (0x4UL << SAI_PDMDLY_DLYM2L_Pos) /*!< 0x00000400 */
16492
16493 #define SAI_PDMDLY_DLYM2R_Pos (12U)
16494 #define SAI_PDMDLY_DLYM2R_Msk (0x7UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00007000 */
16495 #define SAI_PDMDLY_DLYM2R SAI_PDMDLY_DLYM2R_Msk /*!<DLYM2R[2:0] (Delay line adjust for right microphone of pair 2)*/
16496 #define SAI_PDMDLY_DLYM2R_0 (0x1UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00001000 */
16497 #define SAI_PDMDLY_DLYM2R_1 (0x2UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00002000 */
16498 #define SAI_PDMDLY_DLYM2R_2 (0x4UL << SAI_PDMDLY_DLYM2R_Pos) /*!< 0x00004000 */
16499
16500 #define SAI_PDMDLY_DLYM3L_Pos (16U)
16501 #define SAI_PDMDLY_DLYM3L_Msk (0x7UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00070000 */
16502 #define SAI_PDMDLY_DLYM3L SAI_PDMDLY_DLYM3L_Msk /*!<DLYM3L[2:0] (Delay line adjust for left microphone of pair 3)*/
16503 #define SAI_PDMDLY_DLYM3L_0 (0x1UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00010000 */
16504 #define SAI_PDMDLY_DLYM3L_1 (0x2UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00020000 */
16505 #define SAI_PDMDLY_DLYM3L_2 (0x4UL << SAI_PDMDLY_DLYM3L_Pos) /*!< 0x00040000 */
16506
16507 #define SAI_PDMDLY_DLYM3R_Pos (20U)
16508 #define SAI_PDMDLY_DLYM3R_Msk (0x7UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00700000 */
16509 #define SAI_PDMDLY_DLYM3R SAI_PDMDLY_DLYM3R_Msk /*!<DLYM3R[2:0] (Delay line adjust for right microphone of pair 3)*/
16510 #define SAI_PDMDLY_DLYM3R_0 (0x1UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00100000 */
16511 #define SAI_PDMDLY_DLYM3R_1 (0x2UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00200000 */
16512 #define SAI_PDMDLY_DLYM3R_2 (0x4UL << SAI_PDMDLY_DLYM3R_Pos) /*!< 0x00400000 */
16513
16514 #define SAI_PDMDLY_DLYM4L_Pos (24U)
16515 #define SAI_PDMDLY_DLYM4L_Msk (0x7UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x07000000 */
16516 #define SAI_PDMDLY_DLYM4L SAI_PDMDLY_DLYM4L_Msk /*!<DLYM4L[2:0] (Delay line adjust for left microphone of pair 4)*/
16517 #define SAI_PDMDLY_DLYM4L_0 (0x1UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x01000000 */
16518 #define SAI_PDMDLY_DLYM4L_1 (0x2UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x02000000 */
16519 #define SAI_PDMDLY_DLYM4L_2 (0x4UL << SAI_PDMDLY_DLYM4L_Pos) /*!< 0x04000000 */
16520
16521 #define SAI_PDMDLY_DLYM4R_Pos (28U)
16522 #define SAI_PDMDLY_DLYM4R_Msk (0x7UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x70000000 */
16523 #define SAI_PDMDLY_DLYM4R SAI_PDMDLY_DLYM4R_Msk /*!<DLYM4R[2:0] (Delay line adjust for right microphone of pair 4)*/
16524 #define SAI_PDMDLY_DLYM4R_0 (0x1UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x10000000 */
16525 #define SAI_PDMDLY_DLYM4R_1 (0x2UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x20000000 */
16526 #define SAI_PDMDLY_DLYM4R_2 (0x4UL << SAI_PDMDLY_DLYM4R_Pos) /*!< 0x40000000 */
16527
16528 /******************************************************************************/
16529 /* */
16530 /* SDMMC Interface */
16531 /* */
16532 /******************************************************************************/
16533 /****************** Bit definition for SDMMC_POWER register ******************/
16534 #define SDMMC_POWER_PWRCTRL_Pos (0U)
16535 #define SDMMC_POWER_PWRCTRL_Msk (0x3UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000003 */
16536 #define SDMMC_POWER_PWRCTRL SDMMC_POWER_PWRCTRL_Msk /*!<PWRCTRL[1:0] bits (Power supply control bits) */
16537 #define SDMMC_POWER_PWRCTRL_0 (0x1UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000001 */
16538 #define SDMMC_POWER_PWRCTRL_1 (0x2UL << SDMMC_POWER_PWRCTRL_Pos) /*!< 0x00000002 */
16539 #define SDMMC_POWER_VSWITCH_Pos (2U)
16540 #define SDMMC_POWER_VSWITCH_Msk (0x1UL << SDMMC_POWER_VSWITCH_Pos) /*!< 0x00000004 */
16541 #define SDMMC_POWER_VSWITCH SDMMC_POWER_VSWITCH_Msk /*!<Voltage switch sequence start */
16542 #define SDMMC_POWER_VSWITCHEN_Pos (3U)
16543 #define SDMMC_POWER_VSWITCHEN_Msk (0x1UL << SDMMC_POWER_VSWITCHEN_Pos) /*!< 0x00000008 */
16544 #define SDMMC_POWER_VSWITCHEN SDMMC_POWER_VSWITCHEN_Msk /*!<Voltage switch procedure enable */
16545 #define SDMMC_POWER_DIRPOL_Pos (4U)
16546 #define SDMMC_POWER_DIRPOL_Msk (0x1UL << SDMMC_POWER_DIRPOL_Pos) /*!< 0x00000010 */
16547 #define SDMMC_POWER_DIRPOL SDMMC_POWER_DIRPOL_Msk /*!<Data and Command direction signals polarity selection */
16548
16549 /****************** Bit definition for SDMMC_CLKCR register ******************/
16550 #define SDMMC_CLKCR_CLKDIV_Pos (0U)
16551 #define SDMMC_CLKCR_CLKDIV_Msk (0x3FFUL << SDMMC_CLKCR_CLKDIV_Pos) /*!< 0x000003FF */
16552 #define SDMMC_CLKCR_CLKDIV SDMMC_CLKCR_CLKDIV_Msk /*!<Clock divide factor */
16553 #define SDMMC_CLKCR_PWRSAV_Pos (12U)
16554 #define SDMMC_CLKCR_PWRSAV_Msk (0x1UL << SDMMC_CLKCR_PWRSAV_Pos) /*!< 0x00001000 */
16555 #define SDMMC_CLKCR_PWRSAV SDMMC_CLKCR_PWRSAV_Msk /*!<Power saving configuration bit */
16556
16557 #define SDMMC_CLKCR_WIDBUS_Pos (14U)
16558 #define SDMMC_CLKCR_WIDBUS_Msk (0x3UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x0000C000 */
16559 #define SDMMC_CLKCR_WIDBUS SDMMC_CLKCR_WIDBUS_Msk /*!<WIDBUS[1:0] bits (Wide bus mode enable bit) */
16560 #define SDMMC_CLKCR_WIDBUS_0 (0x1UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00004000 */
16561 #define SDMMC_CLKCR_WIDBUS_1 (0x2UL << SDMMC_CLKCR_WIDBUS_Pos) /*!< 0x00008000 */
16562
16563 #define SDMMC_CLKCR_NEGEDGE_Pos (16U)
16564 #define SDMMC_CLKCR_NEGEDGE_Msk (0x1UL << SDMMC_CLKCR_NEGEDGE_Pos) /*!< 0x00010000 */
16565 #define SDMMC_CLKCR_NEGEDGE SDMMC_CLKCR_NEGEDGE_Msk /*!<SDMMC_CK dephasing selection bit */
16566 #define SDMMC_CLKCR_HWFC_EN_Pos (17U)
16567 #define SDMMC_CLKCR_HWFC_EN_Msk (0x1UL << SDMMC_CLKCR_HWFC_EN_Pos) /*!< 0x00020000 */
16568 #define SDMMC_CLKCR_HWFC_EN SDMMC_CLKCR_HWFC_EN_Msk /*!<HW Flow Control enable */
16569 #define SDMMC_CLKCR_DDR_Pos (18U)
16570 #define SDMMC_CLKCR_DDR_Msk (0x1UL << SDMMC_CLKCR_DDR_Pos) /*!< 0x00040000 */
16571 #define SDMMC_CLKCR_DDR SDMMC_CLKCR_DDR_Msk /*!<Data rate signaling selection */
16572 #define SDMMC_CLKCR_BUSSPEED_Pos (19U)
16573 #define SDMMC_CLKCR_BUSSPEED_Msk (0x1UL << SDMMC_CLKCR_BUSSPEED_Pos) /*!< 0x00080000 */
16574 #define SDMMC_CLKCR_BUSSPEED SDMMC_CLKCR_BUSSPEED_Msk /*!<Bus speed mode selection */
16575 #define SDMMC_CLKCR_SELCLKRX_Pos (20U)
16576 #define SDMMC_CLKCR_SELCLKRX_Msk (0x3UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00300000 */
16577 #define SDMMC_CLKCR_SELCLKRX SDMMC_CLKCR_SELCLKRX_Msk /*!<SELCLKRX[1:0] bits (Receive clock selection) */
16578 #define SDMMC_CLKCR_SELCLKRX_0 (0x1UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00100000 */
16579 #define SDMMC_CLKCR_SELCLKRX_1 (0x2UL << SDMMC_CLKCR_SELCLKRX_Pos) /*!< 0x00200000 */
16580
16581 /******************* Bit definition for SDMMC_ARG register *******************/
16582 #define SDMMC_ARG_CMDARG_Pos (0U)
16583 #define SDMMC_ARG_CMDARG_Msk (0xFFFFFFFFUL << SDMMC_ARG_CMDARG_Pos) /*!< 0xFFFFFFFF */
16584 #define SDMMC_ARG_CMDARG SDMMC_ARG_CMDARG_Msk /*!<Command argument */
16585
16586 /******************* Bit definition for SDMMC_CMD register *******************/
16587 #define SDMMC_CMD_CMDINDEX_Pos (0U)
16588 #define SDMMC_CMD_CMDINDEX_Msk (0x3FUL << SDMMC_CMD_CMDINDEX_Pos) /*!< 0x0000003F */
16589 #define SDMMC_CMD_CMDINDEX SDMMC_CMD_CMDINDEX_Msk /*!<Command Index */
16590 #define SDMMC_CMD_CMDTRANS_Pos (6U)
16591 #define SDMMC_CMD_CMDTRANS_Msk (0x1UL << SDMMC_CMD_CMDTRANS_Pos) /*!< 0x00000040 */
16592 #define SDMMC_CMD_CMDTRANS SDMMC_CMD_CMDTRANS_Msk /*!<CPSM Treats command as a Data Transfer */
16593 #define SDMMC_CMD_CMDSTOP_Pos (7U)
16594 #define SDMMC_CMD_CMDSTOP_Msk (0x1UL << SDMMC_CMD_CMDSTOP_Pos) /*!< 0x00000080 */
16595 #define SDMMC_CMD_CMDSTOP SDMMC_CMD_CMDSTOP_Msk /*!<CPSM Treats command as a Stop */
16596
16597 #define SDMMC_CMD_WAITRESP_Pos (8U)
16598 #define SDMMC_CMD_WAITRESP_Msk (0x3UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000300 */
16599 #define SDMMC_CMD_WAITRESP SDMMC_CMD_WAITRESP_Msk /*!<WAITRESP[1:0] bits (Wait for response bits) */
16600 #define SDMMC_CMD_WAITRESP_0 (0x1UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000100 */
16601 #define SDMMC_CMD_WAITRESP_1 (0x2UL << SDMMC_CMD_WAITRESP_Pos) /*!< 0x00000200 */
16602
16603 #define SDMMC_CMD_WAITINT_Pos (10U)
16604 #define SDMMC_CMD_WAITINT_Msk (0x1UL << SDMMC_CMD_WAITINT_Pos) /*!< 0x00000400 */
16605 #define SDMMC_CMD_WAITINT SDMMC_CMD_WAITINT_Msk /*!<CPSM Waits for Interrupt Request */
16606 #define SDMMC_CMD_WAITPEND_Pos (11U)
16607 #define SDMMC_CMD_WAITPEND_Msk (0x1UL << SDMMC_CMD_WAITPEND_Pos) /*!< 0x00000800 */
16608 #define SDMMC_CMD_WAITPEND SDMMC_CMD_WAITPEND_Msk /*!<CPSM Waits for ends of data transfer (CmdPend internal signal) */
16609 #define SDMMC_CMD_CPSMEN_Pos (12U)
16610 #define SDMMC_CMD_CPSMEN_Msk (0x1UL << SDMMC_CMD_CPSMEN_Pos) /*!< 0x00001000 */
16611 #define SDMMC_CMD_CPSMEN SDMMC_CMD_CPSMEN_Msk /*!<Command path state machine (CPSM) Enable bit */
16612 #define SDMMC_CMD_DTHOLD_Pos (13U)
16613 #define SDMMC_CMD_DTHOLD_Msk (0x1UL << SDMMC_CMD_DTHOLD_Pos) /*!< 0x00002000 */
16614 #define SDMMC_CMD_DTHOLD SDMMC_CMD_DTHOLD_Msk /*!<Hold new data block transmission and reception in the DPSM */
16615 #define SDMMC_CMD_BOOTMODE_Pos (14U)
16616 #define SDMMC_CMD_BOOTMODE_Msk (0x1UL << SDMMC_CMD_BOOTMODE_Pos) /*!< 0x00004000 */
16617 #define SDMMC_CMD_BOOTMODE SDMMC_CMD_BOOTMODE_Msk /*!<Boot mode */
16618 #define SDMMC_CMD_BOOTEN_Pos (15U)
16619 #define SDMMC_CMD_BOOTEN_Msk (0x1UL << SDMMC_CMD_BOOTEN_Pos) /*!< 0x00008000 */
16620 #define SDMMC_CMD_BOOTEN SDMMC_CMD_BOOTEN_Msk /*!<Enable Boot mode procedure */
16621 #define SDMMC_CMD_CMDSUSPEND_Pos (16U)
16622 #define SDMMC_CMD_CMDSUSPEND_Msk (0x1UL << SDMMC_CMD_CMDSUSPEND_Pos) /*!< 0x00010000 */
16623 #define SDMMC_CMD_CMDSUSPEND SDMMC_CMD_CMDSUSPEND_Msk /*!<CPSM Treats command as a Suspend or Resume command */
16624
16625 /***************** Bit definition for SDMMC_RESPCMD register *****************/
16626 #define SDMMC_RESPCMD_RESPCMD_Pos (0U)
16627 #define SDMMC_RESPCMD_RESPCMD_Msk (0x3FUL << SDMMC_RESPCMD_RESPCMD_Pos) /*!< 0x0000003F */
16628 #define SDMMC_RESPCMD_RESPCMD SDMMC_RESPCMD_RESPCMD_Msk /*!<Response command index */
16629
16630 /****************** Bit definition for SDMMC_RESP0 register ******************/
16631 #define SDMMC_RESP0_CARDSTATUS0_Pos (0U)
16632 #define SDMMC_RESP0_CARDSTATUS0_Msk (0xFFFFFFFFUL << SDMMC_RESP0_CARDSTATUS0_Pos) /*!< 0xFFFFFFFF */
16633 #define SDMMC_RESP0_CARDSTATUS0 SDMMC_RESP0_CARDSTATUS0_Msk /*!<Card Status */
16634
16635 /****************** Bit definition for SDMMC_RESP1 register ******************/
16636 #define SDMMC_RESP1_CARDSTATUS1_Pos (0U)
16637 #define SDMMC_RESP1_CARDSTATUS1_Msk (0xFFFFFFFFUL << SDMMC_RESP1_CARDSTATUS1_Pos) /*!< 0xFFFFFFFF */
16638 #define SDMMC_RESP1_CARDSTATUS1 SDMMC_RESP1_CARDSTATUS1_Msk /*!<Card Status */
16639
16640 /****************** Bit definition for SDMMC_RESP2 register ******************/
16641 #define SDMMC_RESP2_CARDSTATUS2_Pos (0U)
16642 #define SDMMC_RESP2_CARDSTATUS2_Msk (0xFFFFFFFFUL << SDMMC_RESP2_CARDSTATUS2_Pos) /*!< 0xFFFFFFFF */
16643 #define SDMMC_RESP2_CARDSTATUS2 SDMMC_RESP2_CARDSTATUS2_Msk /*!<Card Status */
16644
16645 /****************** Bit definition for SDMMC_RESP3 register ******************/
16646 #define SDMMC_RESP3_CARDSTATUS3_Pos (0U)
16647 #define SDMMC_RESP3_CARDSTATUS3_Msk (0xFFFFFFFFUL << SDMMC_RESP3_CARDSTATUS3_Pos) /*!< 0xFFFFFFFF */
16648 #define SDMMC_RESP3_CARDSTATUS3 SDMMC_RESP3_CARDSTATUS3_Msk /*!<Card Status */
16649
16650 /****************** Bit definition for SDMMC_RESP4 register ******************/
16651 #define SDMMC_RESP4_CARDSTATUS4_Pos (0U)
16652 #define SDMMC_RESP4_CARDSTATUS4_Msk (0xFFFFFFFFUL << SDMMC_RESP4_CARDSTATUS4_Pos) /*!< 0xFFFFFFFF */
16653 #define SDMMC_RESP4_CARDSTATUS4 SDMMC_RESP4_CARDSTATUS4_Msk /*!<Card Status */
16654
16655 /****************** Bit definition for SDMMC_DTIMER register *****************/
16656 #define SDMMC_DTIMER_DATATIME_Pos (0U)
16657 #define SDMMC_DTIMER_DATATIME_Msk (0xFFFFFFFFUL << SDMMC_DTIMER_DATATIME_Pos) /*!< 0xFFFFFFFF */
16658 #define SDMMC_DTIMER_DATATIME SDMMC_DTIMER_DATATIME_Msk /*!<Data timeout period. */
16659
16660 /****************** Bit definition for SDMMC_DLEN register *******************/
16661 #define SDMMC_DLEN_DATALENGTH_Pos (0U)
16662 #define SDMMC_DLEN_DATALENGTH_Msk (0x1FFFFFFUL << SDMMC_DLEN_DATALENGTH_Pos) /*!< 0x01FFFFFF */
16663 #define SDMMC_DLEN_DATALENGTH SDMMC_DLEN_DATALENGTH_Msk /*!<Data length value */
16664
16665 /****************** Bit definition for SDMMC_DCTRL register ******************/
16666 #define SDMMC_DCTRL_DTEN_Pos (0U)
16667 #define SDMMC_DCTRL_DTEN_Msk (0x1UL << SDMMC_DCTRL_DTEN_Pos) /*!< 0x00000001 */
16668 #define SDMMC_DCTRL_DTEN SDMMC_DCTRL_DTEN_Msk /*!<Data transfer enabled bit */
16669 #define SDMMC_DCTRL_DTDIR_Pos (1U)
16670 #define SDMMC_DCTRL_DTDIR_Msk (0x1UL << SDMMC_DCTRL_DTDIR_Pos) /*!< 0x00000002 */
16671 #define SDMMC_DCTRL_DTDIR SDMMC_DCTRL_DTDIR_Msk /*!<Data transfer direction selection */
16672 #define SDMMC_DCTRL_DTMODE_Pos (2U)
16673 #define SDMMC_DCTRL_DTMODE_Msk (0x3UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x0000000C */
16674 #define SDMMC_DCTRL_DTMODE SDMMC_DCTRL_DTMODE_Msk /*!<DTMODE[1:0] Data transfer mode selection */
16675 #define SDMMC_DCTRL_DTMODE_0 (0x1UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000004 */
16676 #define SDMMC_DCTRL_DTMODE_1 (0x2UL << SDMMC_DCTRL_DTMODE_Pos) /*!< 0x00000008 */
16677
16678 #define SDMMC_DCTRL_DBLOCKSIZE_Pos (4U)
16679 #define SDMMC_DCTRL_DBLOCKSIZE_Msk (0xFUL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x000000F0 */
16680 #define SDMMC_DCTRL_DBLOCKSIZE SDMMC_DCTRL_DBLOCKSIZE_Msk /*!<DBLOCKSIZE[3:0] bits (Data block size) */
16681 #define SDMMC_DCTRL_DBLOCKSIZE_0 (0x1UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000010 */
16682 #define SDMMC_DCTRL_DBLOCKSIZE_1 (0x2UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000020 */
16683 #define SDMMC_DCTRL_DBLOCKSIZE_2 (0x4UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000040 */
16684 #define SDMMC_DCTRL_DBLOCKSIZE_3 (0x8UL << SDMMC_DCTRL_DBLOCKSIZE_Pos) /*!< 0x00000080 */
16685
16686 #define SDMMC_DCTRL_RWSTART_Pos (8U)
16687 #define SDMMC_DCTRL_RWSTART_Msk (0x1UL << SDMMC_DCTRL_RWSTART_Pos) /*!< 0x00000100 */
16688 #define SDMMC_DCTRL_RWSTART SDMMC_DCTRL_RWSTART_Msk /*!<Read wait start */
16689 #define SDMMC_DCTRL_RWSTOP_Pos (9U)
16690 #define SDMMC_DCTRL_RWSTOP_Msk (0x1UL << SDMMC_DCTRL_RWSTOP_Pos) /*!< 0x00000200 */
16691 #define SDMMC_DCTRL_RWSTOP SDMMC_DCTRL_RWSTOP_Msk /*!<Read wait stop */
16692 #define SDMMC_DCTRL_RWMOD_Pos (10U)
16693 #define SDMMC_DCTRL_RWMOD_Msk (0x1UL << SDMMC_DCTRL_RWMOD_Pos) /*!< 0x00000400 */
16694 #define SDMMC_DCTRL_RWMOD SDMMC_DCTRL_RWMOD_Msk /*!<Read wait mode */
16695 #define SDMMC_DCTRL_SDIOEN_Pos (11U)
16696 #define SDMMC_DCTRL_SDIOEN_Msk (0x1UL << SDMMC_DCTRL_SDIOEN_Pos) /*!< 0x00000800 */
16697 #define SDMMC_DCTRL_SDIOEN SDMMC_DCTRL_SDIOEN_Msk /*!<SD I/O enable functions */
16698 #define SDMMC_DCTRL_BOOTACKEN_Pos (12U)
16699 #define SDMMC_DCTRL_BOOTACKEN_Msk (0x1UL << SDMMC_DCTRL_BOOTACKEN_Pos) /*!< 0x00001000 */
16700 #define SDMMC_DCTRL_BOOTACKEN SDMMC_DCTRL_BOOTACKEN_Msk /*!<Enable the reception of the Boot Acknowledgment */
16701 #define SDMMC_DCTRL_FIFORST_Pos (13U)
16702 #define SDMMC_DCTRL_FIFORST_Msk (0x1UL << SDMMC_DCTRL_FIFORST_Pos) /*!< 0x00002000 */
16703 #define SDMMC_DCTRL_FIFORST SDMMC_DCTRL_FIFORST_Msk /*!<FIFO reset */
16704
16705 /****************** Bit definition for SDMMC_DCOUNT register *****************/
16706 #define SDMMC_DCOUNT_DATACOUNT_Pos (0U)
16707 #define SDMMC_DCOUNT_DATACOUNT_Msk (0x1FFFFFFUL << SDMMC_DCOUNT_DATACOUNT_Pos) /*!< 0x01FFFFFF */
16708 #define SDMMC_DCOUNT_DATACOUNT SDMMC_DCOUNT_DATACOUNT_Msk /*!<Data count value */
16709
16710 /****************** Bit definition for SDMMC_STA register ********************/
16711 #define SDMMC_STA_CCRCFAIL_Pos (0U)
16712 #define SDMMC_STA_CCRCFAIL_Msk (0x1UL << SDMMC_STA_CCRCFAIL_Pos) /*!< 0x00000001 */
16713 #define SDMMC_STA_CCRCFAIL SDMMC_STA_CCRCFAIL_Msk /*!<Command response received (CRC check failed) */
16714 #define SDMMC_STA_DCRCFAIL_Pos (1U)
16715 #define SDMMC_STA_DCRCFAIL_Msk (0x1UL << SDMMC_STA_DCRCFAIL_Pos) /*!< 0x00000002 */
16716 #define SDMMC_STA_DCRCFAIL SDMMC_STA_DCRCFAIL_Msk /*!<Data block sent/received (CRC check failed) */
16717 #define SDMMC_STA_CTIMEOUT_Pos (2U)
16718 #define SDMMC_STA_CTIMEOUT_Msk (0x1UL << SDMMC_STA_CTIMEOUT_Pos) /*!< 0x00000004 */
16719 #define SDMMC_STA_CTIMEOUT SDMMC_STA_CTIMEOUT_Msk /*!<Command response timeout */
16720 #define SDMMC_STA_DTIMEOUT_Pos (3U)
16721 #define SDMMC_STA_DTIMEOUT_Msk (0x1UL << SDMMC_STA_DTIMEOUT_Pos) /*!< 0x00000008 */
16722 #define SDMMC_STA_DTIMEOUT SDMMC_STA_DTIMEOUT_Msk /*!<Data timeout */
16723 #define SDMMC_STA_TXUNDERR_Pos (4U)
16724 #define SDMMC_STA_TXUNDERR_Msk (0x1UL << SDMMC_STA_TXUNDERR_Pos) /*!< 0x00000010 */
16725 #define SDMMC_STA_TXUNDERR SDMMC_STA_TXUNDERR_Msk /*!<Transmit FIFO underrun error */
16726 #define SDMMC_STA_RXOVERR_Pos (5U)
16727 #define SDMMC_STA_RXOVERR_Msk (0x1UL << SDMMC_STA_RXOVERR_Pos) /*!< 0x00000020 */
16728 #define SDMMC_STA_RXOVERR SDMMC_STA_RXOVERR_Msk /*!<Received FIFO overrun error */
16729 #define SDMMC_STA_CMDREND_Pos (6U)
16730 #define SDMMC_STA_CMDREND_Msk (0x1UL << SDMMC_STA_CMDREND_Pos) /*!< 0x00000040 */
16731 #define SDMMC_STA_CMDREND SDMMC_STA_CMDREND_Msk /*!<Command response received (CRC check passed) */
16732 #define SDMMC_STA_CMDSENT_Pos (7U)
16733 #define SDMMC_STA_CMDSENT_Msk (0x1UL << SDMMC_STA_CMDSENT_Pos) /*!< 0x00000080 */
16734 #define SDMMC_STA_CMDSENT SDMMC_STA_CMDSENT_Msk /*!<Command sent (no response required) */
16735 #define SDMMC_STA_DATAEND_Pos (8U)
16736 #define SDMMC_STA_DATAEND_Msk (0x1UL << SDMMC_STA_DATAEND_Pos) /*!< 0x00000100 */
16737 #define SDMMC_STA_DATAEND SDMMC_STA_DATAEND_Msk /*!<Data end (data counter, SDIDCOUNT, is zero) */
16738 #define SDMMC_STA_DHOLD_Pos (9U)
16739 #define SDMMC_STA_DHOLD_Msk (0x1UL << SDMMC_STA_DHOLD_Pos) /*!< 0x00000200 */
16740 #define SDMMC_STA_DHOLD SDMMC_STA_DHOLD_Msk /*!<Data transfer Hold */
16741 #define SDMMC_STA_DBCKEND_Pos (10U)
16742 #define SDMMC_STA_DBCKEND_Msk (0x1UL << SDMMC_STA_DBCKEND_Pos) /*!< 0x00000400 */
16743 #define SDMMC_STA_DBCKEND SDMMC_STA_DBCKEND_Msk /*!<Data block sent/received (CRC check passed) */
16744 #define SDMMC_STA_DABORT_Pos (11U)
16745 #define SDMMC_STA_DABORT_Msk (0x1UL << SDMMC_STA_DABORT_Pos) /*!< 0x00000800 */
16746 #define SDMMC_STA_DABORT SDMMC_STA_DABORT_Msk /*!<Data transfer aborted by CMD12 */
16747 #define SDMMC_STA_DPSMACT_Pos (12U)
16748 #define SDMMC_STA_DPSMACT_Msk (0x1UL << SDMMC_STA_DPSMACT_Pos) /*!< 0x00001000 */
16749 #define SDMMC_STA_DPSMACT SDMMC_STA_DPSMACT_Msk /*!<Data path state machine active */
16750 #define SDMMC_STA_CPSMACT_Pos (13U)
16751 #define SDMMC_STA_CPSMACT_Msk (0x1UL << SDMMC_STA_CPSMACT_Pos) /*!< 0x00002000 */
16752 #define SDMMC_STA_CPSMACT SDMMC_STA_CPSMACT_Msk /*!<Command path state machine active */
16753 #define SDMMC_STA_TXFIFOHE_Pos (14U)
16754 #define SDMMC_STA_TXFIFOHE_Msk (0x1UL << SDMMC_STA_TXFIFOHE_Pos) /*!< 0x00004000 */
16755 #define SDMMC_STA_TXFIFOHE SDMMC_STA_TXFIFOHE_Msk /*!<Transmit FIFO Half Empty: at least 8 words can be written into the FIFO */
16756 #define SDMMC_STA_RXFIFOHF_Pos (15U)
16757 #define SDMMC_STA_RXFIFOHF_Msk (0x1UL << SDMMC_STA_RXFIFOHF_Pos) /*!< 0x00008000 */
16758 #define SDMMC_STA_RXFIFOHF SDMMC_STA_RXFIFOHF_Msk /*!<Receive FIFO Half Full: there are at least 8 words in the FIFO */
16759 #define SDMMC_STA_TXFIFOF_Pos (16U)
16760 #define SDMMC_STA_TXFIFOF_Msk (0x1UL << SDMMC_STA_TXFIFOF_Pos) /*!< 0x00010000 */
16761 #define SDMMC_STA_TXFIFOF SDMMC_STA_TXFIFOF_Msk /*!<Transmit FIFO full */
16762 #define SDMMC_STA_RXFIFOF_Pos (17U)
16763 #define SDMMC_STA_RXFIFOF_Msk (0x1UL << SDMMC_STA_RXFIFOF_Pos) /*!< 0x00020000 */
16764 #define SDMMC_STA_RXFIFOF SDMMC_STA_RXFIFOF_Msk /*!<Receive FIFO full */
16765 #define SDMMC_STA_TXFIFOE_Pos (18U)
16766 #define SDMMC_STA_TXFIFOE_Msk (0x1UL << SDMMC_STA_TXFIFOE_Pos) /*!< 0x00040000 */
16767 #define SDMMC_STA_TXFIFOE SDMMC_STA_TXFIFOE_Msk /*!<Transmit FIFO empty */
16768 #define SDMMC_STA_RXFIFOE_Pos (19U)
16769 #define SDMMC_STA_RXFIFOE_Msk (0x1UL << SDMMC_STA_RXFIFOE_Pos) /*!< 0x00080000 */
16770 #define SDMMC_STA_RXFIFOE SDMMC_STA_RXFIFOE_Msk /*!<Receive FIFO empty */
16771 #define SDMMC_STA_BUSYD0_Pos (20U)
16772 #define SDMMC_STA_BUSYD0_Msk (0x1UL << SDMMC_STA_BUSYD0_Pos) /*!< 0x00100000 */
16773 #define SDMMC_STA_BUSYD0 SDMMC_STA_BUSYD0_Msk /*!<Inverted value of SDMMC_D0 line (Busy) */
16774 #define SDMMC_STA_BUSYD0END_Pos (21U)
16775 #define SDMMC_STA_BUSYD0END_Msk (0x1UL << SDMMC_STA_BUSYD0END_Pos) /*!< 0x00200000 */
16776 #define SDMMC_STA_BUSYD0END SDMMC_STA_BUSYD0END_Msk /*!<End of SDMMC_D0 Busy following a CMD response detected */
16777 #define SDMMC_STA_SDIOIT_Pos (22U)
16778 #define SDMMC_STA_SDIOIT_Msk (0x1UL << SDMMC_STA_SDIOIT_Pos) /*!< 0x00400000 */
16779 #define SDMMC_STA_SDIOIT SDMMC_STA_SDIOIT_Msk /*!<SDIO interrupt received */
16780 #define SDMMC_STA_ACKFAIL_Pos (23U)
16781 #define SDMMC_STA_ACKFAIL_Msk (0x1UL << SDMMC_STA_ACKFAIL_Pos) /*!< 0x00800000 */
16782 #define SDMMC_STA_ACKFAIL SDMMC_STA_ACKFAIL_Msk /*!<Boot Acknowledgment received (BootAck check fail) */
16783 #define SDMMC_STA_ACKTIMEOUT_Pos (24U)
16784 #define SDMMC_STA_ACKTIMEOUT_Msk (0x1UL << SDMMC_STA_ACKTIMEOUT_Pos) /*!< 0x01000000 */
16785 #define SDMMC_STA_ACKTIMEOUT SDMMC_STA_ACKTIMEOUT_Msk /*!<Boot Acknowledgment timeout */
16786 #define SDMMC_STA_VSWEND_Pos (25U)
16787 #define SDMMC_STA_VSWEND_Msk (0x1UL << SDMMC_STA_VSWEND_Pos) /*!< 0x02000000 */
16788 #define SDMMC_STA_VSWEND SDMMC_STA_VSWEND_Msk /*!<Voltage switch critical timing section completion */
16789 #define SDMMC_STA_CKSTOP_Pos (26U)
16790 #define SDMMC_STA_CKSTOP_Msk (0x1UL << SDMMC_STA_CKSTOP_Pos) /*!< 0x04000000 */
16791 #define SDMMC_STA_CKSTOP SDMMC_STA_CKSTOP_Msk /*!<SDMMC_CK stopped in Voltage switch procedure */
16792 #define SDMMC_STA_IDMATE_Pos (27U)
16793 #define SDMMC_STA_IDMATE_Msk (0x1UL << SDMMC_STA_IDMATE_Pos) /*!< 0x08000000 */
16794 #define SDMMC_STA_IDMATE SDMMC_STA_IDMATE_Msk /*!<IDMA transfer error */
16795 #define SDMMC_STA_IDMABTC_Pos (28U)
16796 #define SDMMC_STA_IDMABTC_Msk (0x1UL << SDMMC_STA_IDMABTC_Pos) /*!< 0x10000000 */
16797 #define SDMMC_STA_IDMABTC SDMMC_STA_IDMABTC_Msk /*!<IDMA buffer transfer complete */
16798
16799 /******************* Bit definition for SDMMC_ICR register *******************/
16800 #define SDMMC_ICR_CCRCFAILC_Pos (0U)
16801 #define SDMMC_ICR_CCRCFAILC_Msk (0x1UL << SDMMC_ICR_CCRCFAILC_Pos) /*!< 0x00000001 */
16802 #define SDMMC_ICR_CCRCFAILC SDMMC_ICR_CCRCFAILC_Msk /*!<CCRCFAIL flag clear bit */
16803 #define SDMMC_ICR_DCRCFAILC_Pos (1U)
16804 #define SDMMC_ICR_DCRCFAILC_Msk (0x1UL << SDMMC_ICR_DCRCFAILC_Pos) /*!< 0x00000002 */
16805 #define SDMMC_ICR_DCRCFAILC SDMMC_ICR_DCRCFAILC_Msk /*!<DCRCFAIL flag clear bit */
16806 #define SDMMC_ICR_CTIMEOUTC_Pos (2U)
16807 #define SDMMC_ICR_CTIMEOUTC_Msk (0x1UL << SDMMC_ICR_CTIMEOUTC_Pos) /*!< 0x00000004 */
16808 #define SDMMC_ICR_CTIMEOUTC SDMMC_ICR_CTIMEOUTC_Msk /*!<CTIMEOUT flag clear bit */
16809 #define SDMMC_ICR_DTIMEOUTC_Pos (3U)
16810 #define SDMMC_ICR_DTIMEOUTC_Msk (0x1UL << SDMMC_ICR_DTIMEOUTC_Pos) /*!< 0x00000008 */
16811 #define SDMMC_ICR_DTIMEOUTC SDMMC_ICR_DTIMEOUTC_Msk /*!<DTIMEOUT flag clear bit */
16812 #define SDMMC_ICR_TXUNDERRC_Pos (4U)
16813 #define SDMMC_ICR_TXUNDERRC_Msk (0x1UL << SDMMC_ICR_TXUNDERRC_Pos) /*!< 0x00000010 */
16814 #define SDMMC_ICR_TXUNDERRC SDMMC_ICR_TXUNDERRC_Msk /*!<TXUNDERR flag clear bit */
16815 #define SDMMC_ICR_RXOVERRC_Pos (5U)
16816 #define SDMMC_ICR_RXOVERRC_Msk (0x1UL << SDMMC_ICR_RXOVERRC_Pos) /*!< 0x00000020 */
16817 #define SDMMC_ICR_RXOVERRC SDMMC_ICR_RXOVERRC_Msk /*!<RXOVERR flag clear bit */
16818 #define SDMMC_ICR_CMDRENDC_Pos (6U)
16819 #define SDMMC_ICR_CMDRENDC_Msk (0x1UL << SDMMC_ICR_CMDRENDC_Pos) /*!< 0x00000040 */
16820 #define SDMMC_ICR_CMDRENDC SDMMC_ICR_CMDRENDC_Msk /*!<CMDREND flag clear bit */
16821 #define SDMMC_ICR_CMDSENTC_Pos (7U)
16822 #define SDMMC_ICR_CMDSENTC_Msk (0x1UL << SDMMC_ICR_CMDSENTC_Pos) /*!< 0x00000080 */
16823 #define SDMMC_ICR_CMDSENTC SDMMC_ICR_CMDSENTC_Msk /*!<CMDSENT flag clear bit */
16824 #define SDMMC_ICR_DATAENDC_Pos (8U)
16825 #define SDMMC_ICR_DATAENDC_Msk (0x1UL << SDMMC_ICR_DATAENDC_Pos) /*!< 0x00000100 */
16826 #define SDMMC_ICR_DATAENDC SDMMC_ICR_DATAENDC_Msk /*!<DATAEND flag clear bit */
16827 #define SDMMC_ICR_DHOLDC_Pos (9U)
16828 #define SDMMC_ICR_DHOLDC_Msk (0x1UL << SDMMC_ICR_DHOLDC_Pos) /*!< 0x00000200 */
16829 #define SDMMC_ICR_DHOLDC SDMMC_ICR_DHOLDC_Msk /*!<DHOLD flag clear bit */
16830 #define SDMMC_ICR_DBCKENDC_Pos (10U)
16831 #define SDMMC_ICR_DBCKENDC_Msk (0x1UL << SDMMC_ICR_DBCKENDC_Pos) /*!< 0x00000400 */
16832 #define SDMMC_ICR_DBCKENDC SDMMC_ICR_DBCKENDC_Msk /*!<DBCKEND flag clear bit */
16833 #define SDMMC_ICR_DABORTC_Pos (11U)
16834 #define SDMMC_ICR_DABORTC_Msk (0x1UL << SDMMC_ICR_DABORTC_Pos) /*!< 0x00000800 */
16835 #define SDMMC_ICR_DABORTC SDMMC_ICR_DABORTC_Msk /*!<DABORTC flag clear bit */
16836 #define SDMMC_ICR_BUSYD0ENDC_Pos (21U)
16837 #define SDMMC_ICR_BUSYD0ENDC_Msk (0x1UL << SDMMC_ICR_BUSYD0ENDC_Pos) /*!< 0x00200000 */
16838 #define SDMMC_ICR_BUSYD0ENDC SDMMC_ICR_BUSYD0ENDC_Msk /*!<BUSYD0ENDC flag clear bit */
16839 #define SDMMC_ICR_SDIOITC_Pos (22U)
16840 #define SDMMC_ICR_SDIOITC_Msk (0x1UL << SDMMC_ICR_SDIOITC_Pos) /*!< 0x00400000 */
16841 #define SDMMC_ICR_SDIOITC SDMMC_ICR_SDIOITC_Msk /*!<SDIOIT flag clear bit */
16842 #define SDMMC_ICR_ACKFAILC_Pos (23U)
16843 #define SDMMC_ICR_ACKFAILC_Msk (0x1UL << SDMMC_ICR_ACKFAILC_Pos) /*!< 0x00800000 */
16844 #define SDMMC_ICR_ACKFAILC SDMMC_ICR_ACKFAILC_Msk /*!<ACKFAILC flag clear bit */
16845 #define SDMMC_ICR_ACKTIMEOUTC_Pos (24U)
16846 #define SDMMC_ICR_ACKTIMEOUTC_Msk (0x1UL << SDMMC_ICR_ACKTIMEOUTC_Pos) /*!< 0x01000000 */
16847 #define SDMMC_ICR_ACKTIMEOUTC SDMMC_ICR_ACKTIMEOUTC_Msk /*!<ACKTIMEOUTC flag clear bit */
16848 #define SDMMC_ICR_VSWENDC_Pos (25U)
16849 #define SDMMC_ICR_VSWENDC_Msk (0x1UL << SDMMC_ICR_VSWENDC_Pos) /*!< 0x02000000 */
16850 #define SDMMC_ICR_VSWENDC SDMMC_ICR_VSWENDC_Msk /*!<VSWENDC flag clear bit */
16851 #define SDMMC_ICR_CKSTOPC_Pos (26U)
16852 #define SDMMC_ICR_CKSTOPC_Msk (0x1UL << SDMMC_ICR_CKSTOPC_Pos) /*!< 0x04000000 */
16853 #define SDMMC_ICR_CKSTOPC SDMMC_ICR_CKSTOPC_Msk /*!<CKSTOPC flag clear bit */
16854 #define SDMMC_ICR_IDMATEC_Pos (27U)
16855 #define SDMMC_ICR_IDMATEC_Msk (0x1UL << SDMMC_ICR_IDMATEC_Pos) /*!< 0x08000000 */
16856 #define SDMMC_ICR_IDMATEC SDMMC_ICR_IDMATEC_Msk /*!<IDMATEC flag clear bit */
16857 #define SDMMC_ICR_IDMABTCC_Pos (28U)
16858 #define SDMMC_ICR_IDMABTCC_Msk (0x1UL << SDMMC_ICR_IDMABTCC_Pos) /*!< 0x10000000 */
16859 #define SDMMC_ICR_IDMABTCC SDMMC_ICR_IDMABTCC_Msk /*!<IDMABTCC flag clear bit */
16860
16861 /****************** Bit definition for SDMMC_MASK register *******************/
16862 #define SDMMC_MASK_CCRCFAILIE_Pos (0U)
16863 #define SDMMC_MASK_CCRCFAILIE_Msk (0x1UL << SDMMC_MASK_CCRCFAILIE_Pos) /*!< 0x00000001 */
16864 #define SDMMC_MASK_CCRCFAILIE SDMMC_MASK_CCRCFAILIE_Msk /*!<Command CRC Fail Interrupt Enable */
16865 #define SDMMC_MASK_DCRCFAILIE_Pos (1U)
16866 #define SDMMC_MASK_DCRCFAILIE_Msk (0x1UL << SDMMC_MASK_DCRCFAILIE_Pos) /*!< 0x00000002 */
16867 #define SDMMC_MASK_DCRCFAILIE SDMMC_MASK_DCRCFAILIE_Msk /*!<Data CRC Fail Interrupt Enable */
16868 #define SDMMC_MASK_CTIMEOUTIE_Pos (2U)
16869 #define SDMMC_MASK_CTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_CTIMEOUTIE_Pos) /*!< 0x00000004 */
16870 #define SDMMC_MASK_CTIMEOUTIE SDMMC_MASK_CTIMEOUTIE_Msk /*!<Command TimeOut Interrupt Enable */
16871 #define SDMMC_MASK_DTIMEOUTIE_Pos (3U)
16872 #define SDMMC_MASK_DTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_DTIMEOUTIE_Pos) /*!< 0x00000008 */
16873 #define SDMMC_MASK_DTIMEOUTIE SDMMC_MASK_DTIMEOUTIE_Msk /*!<Data TimeOut Interrupt Enable */
16874 #define SDMMC_MASK_TXUNDERRIE_Pos (4U)
16875 #define SDMMC_MASK_TXUNDERRIE_Msk (0x1UL << SDMMC_MASK_TXUNDERRIE_Pos) /*!< 0x00000010 */
16876 #define SDMMC_MASK_TXUNDERRIE SDMMC_MASK_TXUNDERRIE_Msk /*!<Tx FIFO UnderRun Error Interrupt Enable */
16877 #define SDMMC_MASK_RXOVERRIE_Pos (5U)
16878 #define SDMMC_MASK_RXOVERRIE_Msk (0x1UL << SDMMC_MASK_RXOVERRIE_Pos) /*!< 0x00000020 */
16879 #define SDMMC_MASK_RXOVERRIE SDMMC_MASK_RXOVERRIE_Msk /*!<Rx FIFO OverRun Error Interrupt Enable */
16880 #define SDMMC_MASK_CMDRENDIE_Pos (6U)
16881 #define SDMMC_MASK_CMDRENDIE_Msk (0x1UL << SDMMC_MASK_CMDRENDIE_Pos) /*!< 0x00000040 */
16882 #define SDMMC_MASK_CMDRENDIE SDMMC_MASK_CMDRENDIE_Msk /*!<Command Response Received Interrupt Enable */
16883 #define SDMMC_MASK_CMDSENTIE_Pos (7U)
16884 #define SDMMC_MASK_CMDSENTIE_Msk (0x1UL << SDMMC_MASK_CMDSENTIE_Pos) /*!< 0x00000080 */
16885 #define SDMMC_MASK_CMDSENTIE SDMMC_MASK_CMDSENTIE_Msk /*!<Command Sent Interrupt Enable */
16886 #define SDMMC_MASK_DATAENDIE_Pos (8U)
16887 #define SDMMC_MASK_DATAENDIE_Msk (0x1UL << SDMMC_MASK_DATAENDIE_Pos) /*!< 0x00000100 */
16888 #define SDMMC_MASK_DATAENDIE SDMMC_MASK_DATAENDIE_Msk /*!<Data End Interrupt Enable */
16889 #define SDMMC_MASK_DHOLDIE_Pos (9U)
16890 #define SDMMC_MASK_DHOLDIE_Msk (0x1UL << SDMMC_MASK_DHOLDIE_Pos) /*!< 0x00000200 */
16891 #define SDMMC_MASK_DHOLDIE SDMMC_MASK_DHOLDIE_Msk /*!<Data Hold Interrupt Enable */
16892 #define SDMMC_MASK_DBCKENDIE_Pos (10U)
16893 #define SDMMC_MASK_DBCKENDIE_Msk (0x1UL << SDMMC_MASK_DBCKENDIE_Pos) /*!< 0x00000400 */
16894 #define SDMMC_MASK_DBCKENDIE SDMMC_MASK_DBCKENDIE_Msk /*!<Data Block End Interrupt Enable */
16895 #define SDMMC_MASK_DABORTIE_Pos (11U)
16896 #define SDMMC_MASK_DABORTIE_Msk (0x1UL << SDMMC_MASK_DABORTIE_Pos) /*!< 0x00000800 */
16897 #define SDMMC_MASK_DABORTIE SDMMC_MASK_DABORTIE_Msk /*!<Data transfer aborted interrupt enable */
16898
16899 #define SDMMC_MASK_TXFIFOHEIE_Pos (14U)
16900 #define SDMMC_MASK_TXFIFOHEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOHEIE_Pos) /*!< 0x00004000 */
16901 #define SDMMC_MASK_TXFIFOHEIE SDMMC_MASK_TXFIFOHEIE_Msk /*!<Tx FIFO Half Empty interrupt Enable */
16902 #define SDMMC_MASK_RXFIFOHFIE_Pos (15U)
16903 #define SDMMC_MASK_RXFIFOHFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOHFIE_Pos) /*!< 0x00008000 */
16904 #define SDMMC_MASK_RXFIFOHFIE SDMMC_MASK_RXFIFOHFIE_Msk /*!<Rx FIFO Half Full interrupt Enable */
16905
16906 #define SDMMC_MASK_RXFIFOFIE_Pos (17U)
16907 #define SDMMC_MASK_RXFIFOFIE_Msk (0x1UL << SDMMC_MASK_RXFIFOFIE_Pos) /*!< 0x00020000 */
16908 #define SDMMC_MASK_RXFIFOFIE SDMMC_MASK_RXFIFOFIE_Msk /*!<Rx FIFO Full interrupt Enable */
16909 #define SDMMC_MASK_TXFIFOEIE_Pos (18U)
16910 #define SDMMC_MASK_TXFIFOEIE_Msk (0x1UL << SDMMC_MASK_TXFIFOEIE_Pos) /*!< 0x00040000 */
16911 #define SDMMC_MASK_TXFIFOEIE SDMMC_MASK_TXFIFOEIE_Msk /*!<Tx FIFO Empty interrupt Enable */
16912
16913 #define SDMMC_MASK_BUSYD0ENDIE_Pos (21U)
16914 #define SDMMC_MASK_BUSYD0ENDIE_Msk (0x1UL << SDMMC_MASK_BUSYD0ENDIE_Pos) /*!< 0x00200000 */
16915 #define SDMMC_MASK_BUSYD0ENDIE SDMMC_MASK_BUSYD0ENDIE_Msk /*!<BUSYD0ENDIE interrupt Enable */
16916 #define SDMMC_MASK_SDIOITIE_Pos (22U)
16917 #define SDMMC_MASK_SDIOITIE_Msk (0x1UL << SDMMC_MASK_SDIOITIE_Pos) /*!< 0x00400000 */
16918 #define SDMMC_MASK_SDIOITIE SDMMC_MASK_SDIOITIE_Msk /*!<SDMMC Mode Interrupt Received interrupt Enable */
16919 #define SDMMC_MASK_ACKFAILIE_Pos (23U)
16920 #define SDMMC_MASK_ACKFAILIE_Msk (0x1UL << SDMMC_MASK_ACKFAILIE_Pos) /*!< 0x00800000 */
16921 #define SDMMC_MASK_ACKFAILIE SDMMC_MASK_ACKFAILIE_Msk /*!<Acknowledgment Fail Interrupt Enable */
16922 #define SDMMC_MASK_ACKTIMEOUTIE_Pos (24U)
16923 #define SDMMC_MASK_ACKTIMEOUTIE_Msk (0x1UL << SDMMC_MASK_ACKTIMEOUTIE_Pos) /*!< 0x01000000 */
16924 #define SDMMC_MASK_ACKTIMEOUTIE SDMMC_MASK_ACKTIMEOUTIE_Msk /*!<Acknowledgment timeout Interrupt Enable */
16925 #define SDMMC_MASK_VSWENDIE_Pos (25U)
16926 #define SDMMC_MASK_VSWENDIE_Msk (0x1UL << SDMMC_MASK_VSWENDIE_Pos) /*!< 0x02000000 */
16927 #define SDMMC_MASK_VSWENDIE SDMMC_MASK_VSWENDIE_Msk /*!<Voltage switch critical timing section completion Interrupt Enable */
16928 #define SDMMC_MASK_CKSTOPIE_Pos (26U)
16929 #define SDMMC_MASK_CKSTOPIE_Msk (0x1UL << SDMMC_MASK_CKSTOPIE_Pos) /*!< 0x04000000 */
16930 #define SDMMC_MASK_CKSTOPIE SDMMC_MASK_CKSTOPIE_Msk /*!<Voltage Switch clock stopped Interrupt Enable */
16931 #define SDMMC_MASK_IDMABTCIE_Pos (28U)
16932 #define SDMMC_MASK_IDMABTCIE_Msk (0x1UL << SDMMC_MASK_IDMABTCIE_Pos) /*!< 0x10000000 */
16933 #define SDMMC_MASK_IDMABTCIE SDMMC_MASK_IDMABTCIE_Msk /*!<IDMA buffer transfer complete Interrupt Enable */
16934
16935 /***************** Bit definition for SDMMC_ACKTIME register *****************/
16936 #define SDMMC_ACKTIME_ACKTIME_Pos (0U)
16937 #define SDMMC_ACKTIME_ACKTIME_Msk (0x1FFFFFFUL << SDMMC_ACKTIME_ACKTIME_Pos) /*!< 0x01FFFFFF */
16938 #define SDMMC_ACKTIME_ACKTIME SDMMC_ACKTIME_ACKTIME_Msk /*!<Boot acknowledgment timeout period */
16939
16940 /****************** Bit definition for SDMMC_FIFO register *******************/
16941 #define SDMMC_FIFO_FIFODATA_Pos (0U)
16942 #define SDMMC_FIFO_FIFODATA_Msk (0xFFFFFFFFUL << SDMMC_FIFO_FIFODATA_Pos) /*!< 0xFFFFFFFF */
16943 #define SDMMC_FIFO_FIFODATA SDMMC_FIFO_FIFODATA_Msk /*!<Receive and transmit FIFO data */
16944
16945 /****************** Bit definition for SDMMC_IDMACTRL register ****************/
16946 #define SDMMC_IDMA_IDMAEN_Pos (0U)
16947 #define SDMMC_IDMA_IDMAEN_Msk (0x1UL << SDMMC_IDMA_IDMAEN_Pos) /*!< 0x00000001 */
16948 #define SDMMC_IDMA_IDMAEN SDMMC_IDMA_IDMAEN_Msk /*!< Enable the internal DMA of the SDMMC peripheral */
16949 #define SDMMC_IDMA_IDMABMODE_Pos (1U)
16950 #define SDMMC_IDMA_IDMABMODE_Msk (0x1UL << SDMMC_IDMA_IDMABMODE_Pos) /*!< 0x00000002 */
16951 #define SDMMC_IDMA_IDMABMODE SDMMC_IDMA_IDMABMODE_Msk /*!< Enable double buffer mode for IDMA */
16952 #define SDMMC_IDMA_IDMABACT_Pos (2U)
16953 #define SDMMC_IDMA_IDMABACT_Msk (0x1UL << SDMMC_IDMA_IDMABACT_Pos) /*!< 0x00000004 */
16954 #define SDMMC_IDMA_IDMABACT SDMMC_IDMA_IDMABACT_Msk /*!< Uses buffer 1 when double buffer mode is selected */
16955
16956 /***************** Bit definition for SDMMC_IDMABSIZE register ***************/
16957 #define SDMMC_IDMABSIZE_IDMABNDT_Pos (5U)
16958 #define SDMMC_IDMABSIZE_IDMABNDT_Msk (0xFFUL << SDMMC_IDMABSIZE_IDMABNDT_Pos) /*!< 0x00001FE0 */
16959 #define SDMMC_IDMABSIZE_IDMABNDT SDMMC_IDMABSIZE_IDMABNDT_Msk /*!< Number of transfers per buffer */
16960
16961 /***************** Bit definition for SDMMC_IDMABASE0 register ***************/
16962 #define SDMMC_IDMABASE0_IDMABASE0 ((uint32_t)0xFFFFFFFF) /*!< Buffer 0 memory base address */
16963
16964 /***************** Bit definition for SDMMC_IDMABASE1 register ***************/
16965 #define SDMMC_IDMABASE1_IDMABASE1 ((uint32_t)0xFFFFFFFF) /*!< Buffer 1 memory base address */
16966
16967 /******************************************************************************/
16968 /* */
16969 /* Delay Block Interface (DLYB) */
16970 /* */
16971 /******************************************************************************/
16972 /******************* Bit definition for DLYB_CR register ********************/
16973 #define DLYB_CR_DEN_Pos (0U)
16974 #define DLYB_CR_DEN_Msk (0x1UL << DLYB_CR_DEN_Pos) /*!< 0x00000001 */
16975 #define DLYB_CR_DEN DLYB_CR_DEN_Msk /*!<Delay Block enable */
16976 #define DLYB_CR_SEN_Pos (1U)
16977 #define DLYB_CR_SEN_Msk (0x1UL << DLYB_CR_SEN_Pos) /*!< 0x00000002 */
16978 #define DLYB_CR_SEN DLYB_CR_SEN_Msk /*!<Sampler length enable */
16979
16980
16981 /******************* Bit definition for DLYB_CFGR register ********************/
16982 #define DLYB_CFGR_SEL_Pos (0U)
16983 #define DLYB_CFGR_SEL_Msk (0xFUL << DLYB_CFGR_SEL_Pos) /*!< 0x0000000F */
16984 #define DLYB_CFGR_SEL DLYB_CFGR_SEL_Msk /*!<Select the phase for the Output clock[3:0] */
16985 #define DLYB_CFGR_SEL_0 (0x1UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000001 */
16986 #define DLYB_CFGR_SEL_1 (0x2UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000002 */
16987 #define DLYB_CFGR_SEL_2 (0x3UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000003 */
16988 #define DLYB_CFGR_SEL_3 (0x8UL << DLYB_CFGR_SEL_Pos) /*!< 0x00000008 */
16989
16990 #define DLYB_CFGR_UNIT_Pos (8U)
16991 #define DLYB_CFGR_UNIT_Msk (0x7FUL << DLYB_CFGR_UNIT_Pos) /*!< 0x00007F00 */
16992 #define DLYB_CFGR_UNIT DLYB_CFGR_UNIT_Msk /*!<Delay Defines the delay of a Unit delay cell[6:0] */
16993 #define DLYB_CFGR_UNIT_0 (0x01UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000100 */
16994 #define DLYB_CFGR_UNIT_1 (0x02UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000200 */
16995 #define DLYB_CFGR_UNIT_2 (0x04UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000400 */
16996 #define DLYB_CFGR_UNIT_3 (0x08UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00000800 */
16997 #define DLYB_CFGR_UNIT_4 (0x10UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00001000 */
16998 #define DLYB_CFGR_UNIT_5 (0x20UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00002000 */
16999 #define DLYB_CFGR_UNIT_6 (0x40UL << DLYB_CFGR_UNIT_Pos) /*!< 0x00004000 */
17000
17001 #define DLYB_CFGR_LNG_Pos (16U)
17002 #define DLYB_CFGR_LNG_Msk (0xFFFUL << DLYB_CFGR_LNG_Pos) /*!< 0x0FFF0000 */
17003 #define DLYB_CFGR_LNG DLYB_CFGR_LNG_Msk /*!<Delay line length value[11:0] */
17004 #define DLYB_CFGR_LNG_0 (0x001UL << DLYB_CFGR_LNG_Pos) /*!< 0x00010000 */
17005 #define DLYB_CFGR_LNG_1 (0x002UL << DLYB_CFGR_LNG_Pos) /*!< 0x00020000 */
17006 #define DLYB_CFGR_LNG_2 (0x004UL << DLYB_CFGR_LNG_Pos) /*!< 0x00040000 */
17007 #define DLYB_CFGR_LNG_3 (0x008UL << DLYB_CFGR_LNG_Pos) /*!< 0x00080000 */
17008 #define DLYB_CFGR_LNG_4 (0x010UL << DLYB_CFGR_LNG_Pos) /*!< 0x00100000 */
17009 #define DLYB_CFGR_LNG_5 (0x020UL << DLYB_CFGR_LNG_Pos) /*!< 0x00200000 */
17010 #define DLYB_CFGR_LNG_6 (0x040UL << DLYB_CFGR_LNG_Pos) /*!< 0x00400000 */
17011 #define DLYB_CFGR_LNG_7 (0x080UL << DLYB_CFGR_LNG_Pos) /*!< 0x00800000 */
17012 #define DLYB_CFGR_LNG_8 (0x100UL << DLYB_CFGR_LNG_Pos) /*!< 0x01000000 */
17013 #define DLYB_CFGR_LNG_9 (0x200UL << DLYB_CFGR_LNG_Pos) /*!< 0x02000000 */
17014 #define DLYB_CFGR_LNG_10 (0x400UL << DLYB_CFGR_LNG_Pos) /*!< 0x04000000 */
17015 #define DLYB_CFGR_LNG_11 (0x800UL << DLYB_CFGR_LNG_Pos) /*!< 0x08000000 */
17016
17017 #define DLYB_CFGR_LNGF_Pos (31U)
17018 #define DLYB_CFGR_LNGF_Msk (0x1UL << DLYB_CFGR_LNGF_Pos) /*!< 0x80000000 */
17019 #define DLYB_CFGR_LNGF DLYB_CFGR_LNGF_Msk /*!<Length valid flag */
17020
17021 /******************************************************************************/
17022 /* */
17023 /* Serial Peripheral Interface (SPI/I2S) */
17024 /* */
17025 /******************************************************************************/
17026 #define SPI_SPI6I2S_SUPPORT /*!<SPI6 I2S support feature */
17027 /******************* Bit definition for SPI_CR1 register ********************/
17028 #define SPI_CR1_SPE_Pos (0U)
17029 #define SPI_CR1_SPE_Msk (0x1UL << SPI_CR1_SPE_Pos) /*!< 0x00000001 */
17030 #define SPI_CR1_SPE SPI_CR1_SPE_Msk /*!<Serial Peripheral Enable */
17031 #define SPI_CR1_MASRX_Pos (8U)
17032 #define SPI_CR1_MASRX_Msk (0x1UL << SPI_CR1_MASRX_Pos) /*!< 0x00000100 */
17033 #define SPI_CR1_MASRX SPI_CR1_MASRX_Msk /*!<Master automatic SUSP in Receive mode */
17034 #define SPI_CR1_CSTART_Pos (9U)
17035 #define SPI_CR1_CSTART_Msk (0x1UL << SPI_CR1_CSTART_Pos) /*!< 0x00000200 */
17036 #define SPI_CR1_CSTART SPI_CR1_CSTART_Msk /*!<Master transfer start */
17037 #define SPI_CR1_CSUSP_Pos (10U)
17038 #define SPI_CR1_CSUSP_Msk (0x1UL << SPI_CR1_CSUSP_Pos) /*!< 0x00000400 */
17039 #define SPI_CR1_CSUSP SPI_CR1_CSUSP_Msk /*!<Master SUSPend request */
17040 #define SPI_CR1_HDDIR_Pos (11U)
17041 #define SPI_CR1_HDDIR_Msk (0x1UL << SPI_CR1_HDDIR_Pos) /*!< 0x00000800 */
17042 #define SPI_CR1_HDDIR SPI_CR1_HDDIR_Msk /*!<Rx/Tx direction at Half-duplex mode */
17043 #define SPI_CR1_SSI_Pos (12U)
17044 #define SPI_CR1_SSI_Msk (0x1UL << SPI_CR1_SSI_Pos) /*!< 0x00001000 */
17045 #define SPI_CR1_SSI SPI_CR1_SSI_Msk /*!<Internal SS signal input level */
17046 #define SPI_CR1_CRC33_17_Pos (13U)
17047 #define SPI_CR1_CRC33_17_Msk (0x1UL << SPI_CR1_CRC33_17_Pos) /*!< 0x00002000 */
17048 #define SPI_CR1_CRC33_17 SPI_CR1_CRC33_17_Msk /*!<32-bit CRC polynomial configuration */
17049 #define SPI_CR1_RCRCINI_Pos (14U)
17050 #define SPI_CR1_RCRCINI_Msk (0x1UL << SPI_CR1_RCRCINI_Pos) /*!< 0x00004000 */
17051 #define SPI_CR1_RCRCINI SPI_CR1_RCRCINI_Msk /*!<CRC init pattern control for receiver */
17052 #define SPI_CR1_TCRCINI_Pos (15U)
17053 #define SPI_CR1_TCRCINI_Msk (0x1UL << SPI_CR1_TCRCINI_Pos) /*!< 0x00008000 */
17054 #define SPI_CR1_TCRCINI SPI_CR1_TCRCINI_Msk /*!<CRC init pattern control for transmitter */
17055 #define SPI_CR1_IOLOCK_Pos (16U)
17056 #define SPI_CR1_IOLOCK_Msk (0x1UL << SPI_CR1_IOLOCK_Pos) /*!< 0x00010000 */
17057 #define SPI_CR1_IOLOCK SPI_CR1_IOLOCK_Msk /*!<Locking the AF configuration of associated IOs */
17058
17059 /******************* Bit definition for SPI_CR2 register ********************/
17060 #define SPI_CR2_TSER_Pos (16U)
17061 #define SPI_CR2_TSER_Msk (0xFFFFUL << SPI_CR2_TSER_Pos) /*!< 0xFFFF0000 */
17062 #define SPI_CR2_TSER SPI_CR2_TSER_Msk /*!<Number of data transfer extension */
17063 #define SPI_CR2_TSIZE_Pos (0U)
17064 #define SPI_CR2_TSIZE_Msk (0xFFFFUL << SPI_CR2_TSIZE_Pos) /*!< 0x0000FFFF */
17065 #define SPI_CR2_TSIZE SPI_CR2_TSIZE_Msk /*!<Number of data at current transfer */
17066
17067 /******************* Bit definition for SPI_CFG1 register ********************/
17068 #define SPI_CFG1_DSIZE_Pos (0U)
17069 #define SPI_CFG1_DSIZE_Msk (0x1FUL << SPI_CFG1_DSIZE_Pos) /*!< 0x0000001F */
17070 #define SPI_CFG1_DSIZE SPI_CFG1_DSIZE_Msk /*!<DSIZE[4:0]: Bits number in single SPI data frame */
17071 #define SPI_CFG1_DSIZE_0 (0x01UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000001 */
17072 #define SPI_CFG1_DSIZE_1 (0x02UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000002 */
17073 #define SPI_CFG1_DSIZE_2 (0x04UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000004 */
17074 #define SPI_CFG1_DSIZE_3 (0x08UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000008 */
17075 #define SPI_CFG1_DSIZE_4 (0x10UL << SPI_CFG1_DSIZE_Pos) /*!< 0x00000010 */
17076
17077 #define SPI_CFG1_FTHLV_Pos (5U)
17078 #define SPI_CFG1_FTHLV_Msk (0xFUL << SPI_CFG1_FTHLV_Pos) /*!< 0x000001E0 */
17079 #define SPI_CFG1_FTHLV SPI_CFG1_FTHLV_Msk /*!<FTHVL [3:0]: FIFO threshold level*/
17080 #define SPI_CFG1_FTHLV_0 (0x1UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000020 */
17081 #define SPI_CFG1_FTHLV_1 (0x2UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000040 */
17082 #define SPI_CFG1_FTHLV_2 (0x4UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000080 */
17083 #define SPI_CFG1_FTHLV_3 (0x8UL << SPI_CFG1_FTHLV_Pos) /*!< 0x00000100 */
17084
17085 #define SPI_CFG1_UDRCFG_Pos (9U)
17086 #define SPI_CFG1_UDRCFG_Msk (0x3UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000600 */
17087 #define SPI_CFG1_UDRCFG SPI_CFG1_UDRCFG_Msk /*!<UDRCFG[1:0]: Behavior of transmitter at underrun */
17088 #define SPI_CFG1_UDRCFG_0 (0x1UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000200 */
17089 #define SPI_CFG1_UDRCFG_1 (0x2UL << SPI_CFG1_UDRCFG_Pos) /*!< 0x00000400 */
17090
17091
17092 #define SPI_CFG1_UDRDET_Pos (11U)
17093 #define SPI_CFG1_UDRDET_Msk (0x3UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001800 */
17094 #define SPI_CFG1_UDRDET SPI_CFG1_UDRDET_Msk /*!<UDRDET[1:0]: Detection of underrun condition */
17095 #define SPI_CFG1_UDRDET_0 (0x1UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00000800 */
17096 #define SPI_CFG1_UDRDET_1 (0x2UL << SPI_CFG1_UDRDET_Pos) /*!< 0x00001000 */
17097
17098 #define SPI_CFG1_RXDMAEN_Pos (14U)
17099 #define SPI_CFG1_RXDMAEN_Msk (0x1UL << SPI_CFG1_RXDMAEN_Pos) /*!< 0x00004000 */
17100 #define SPI_CFG1_RXDMAEN SPI_CFG1_RXDMAEN_Msk /*!<Rx DMA stream enable */
17101 #define SPI_CFG1_TXDMAEN_Pos (15U)
17102 #define SPI_CFG1_TXDMAEN_Msk (0x1UL << SPI_CFG1_TXDMAEN_Pos) /*!< 0x00008000 */
17103 #define SPI_CFG1_TXDMAEN SPI_CFG1_TXDMAEN_Msk /*!<Tx DMA stream enable */
17104
17105 #define SPI_CFG1_CRCSIZE_Pos (16U)
17106 #define SPI_CFG1_CRCSIZE_Msk (0x1FUL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x001F0000 */
17107 #define SPI_CFG1_CRCSIZE SPI_CFG1_CRCSIZE_Msk /*!<CRCSIZE [4:0]: Length of CRC frame*/
17108 #define SPI_CFG1_CRCSIZE_0 (0x01UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00010000 */
17109 #define SPI_CFG1_CRCSIZE_1 (0x02UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00020000 */
17110 #define SPI_CFG1_CRCSIZE_2 (0x04UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00040000 */
17111 #define SPI_CFG1_CRCSIZE_3 (0x08UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00080000 */
17112 #define SPI_CFG1_CRCSIZE_4 (0x10UL << SPI_CFG1_CRCSIZE_Pos) /*!< 0x00100000 */
17113
17114 #define SPI_CFG1_CRCEN_Pos (22U)
17115 #define SPI_CFG1_CRCEN_Msk (0x1UL << SPI_CFG1_CRCEN_Pos) /*!< 0x00400000 */
17116 #define SPI_CFG1_CRCEN SPI_CFG1_CRCEN_Msk /*!<Hardware CRC computation enable */
17117
17118 #define SPI_CFG1_MBR_Pos (28U)
17119 #define SPI_CFG1_MBR_Msk (0x7UL << SPI_CFG1_MBR_Pos) /*!< 0x70000000 */
17120 #define SPI_CFG1_MBR SPI_CFG1_MBR_Msk /*!<Master baud rate */
17121 #define SPI_CFG1_MBR_0 (0x1UL << SPI_CFG1_MBR_Pos) /*!< 0x10000000 */
17122 #define SPI_CFG1_MBR_1 (0x2UL << SPI_CFG1_MBR_Pos) /*!< 0x20000000 */
17123 #define SPI_CFG1_MBR_2 (0x4UL << SPI_CFG1_MBR_Pos) /*!< 0x40000000 */
17124
17125 /******************* Bit definition for SPI_CFG2 register ********************/
17126 #define SPI_CFG2_MSSI_Pos (0U)
17127 #define SPI_CFG2_MSSI_Msk (0xFUL << SPI_CFG2_MSSI_Pos) /*!< 0x0000000F */
17128 #define SPI_CFG2_MSSI SPI_CFG2_MSSI_Msk /*!<Master SS Idleness */
17129 #define SPI_CFG2_MSSI_0 (0x1UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000001 */
17130 #define SPI_CFG2_MSSI_1 (0x2UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000002 */
17131 #define SPI_CFG2_MSSI_2 (0x4UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000004 */
17132 #define SPI_CFG2_MSSI_3 (0x8UL << SPI_CFG2_MSSI_Pos) /*!< 0x00000008 */
17133
17134 #define SPI_CFG2_MIDI_Pos (4U)
17135 #define SPI_CFG2_MIDI_Msk (0xFUL << SPI_CFG2_MIDI_Pos) /*!< 0x000000F0 */
17136 #define SPI_CFG2_MIDI SPI_CFG2_MIDI_Msk /*!<Master Inter-Data Idleness */
17137 #define SPI_CFG2_MIDI_0 (0x1UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000010 */
17138 #define SPI_CFG2_MIDI_1 (0x2UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000020 */
17139 #define SPI_CFG2_MIDI_2 (0x4UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000040 */
17140 #define SPI_CFG2_MIDI_3 (0x8UL << SPI_CFG2_MIDI_Pos) /*!< 0x00000080 */
17141
17142 #define SPI_CFG2_IOSWP_Pos (15U)
17143 #define SPI_CFG2_IOSWP_Msk (0x1UL << SPI_CFG2_IOSWP_Pos) /*!< 0x00008000 */
17144 #define SPI_CFG2_IOSWP SPI_CFG2_IOSWP_Msk /*!<Swap functionality of MISO and MOSI pins */
17145
17146 #define SPI_CFG2_COMM_Pos (17U)
17147 #define SPI_CFG2_COMM_Msk (0x3UL << SPI_CFG2_COMM_Pos) /*!< 0x00060000 */
17148 #define SPI_CFG2_COMM SPI_CFG2_COMM_Msk /*!<COMM [1:0]: SPI Communication Mode*/
17149 #define SPI_CFG2_COMM_0 (0x1UL << SPI_CFG2_COMM_Pos) /*!< 0x00020000 */
17150 #define SPI_CFG2_COMM_1 (0x2UL << SPI_CFG2_COMM_Pos) /*!< 0x00040000 */
17151
17152 #define SPI_CFG2_SP_Pos (19U)
17153 #define SPI_CFG2_SP_Msk (0x7UL << SPI_CFG2_SP_Pos) /*!< 0x00380000 */
17154 #define SPI_CFG2_SP SPI_CFG2_SP_Msk /*!<SP[2:0]: Serial Protocol */
17155 #define SPI_CFG2_SP_0 (0x1UL << SPI_CFG2_SP_Pos) /*!< 0x00080000 */
17156 #define SPI_CFG2_SP_1 (0x2UL << SPI_CFG2_SP_Pos) /*!< 0x00100000 */
17157 #define SPI_CFG2_SP_2 (0x4UL << SPI_CFG2_SP_Pos) /*!< 0x00200000 */
17158
17159 #define SPI_CFG2_MASTER_Pos (22U)
17160 #define SPI_CFG2_MASTER_Msk (0x1UL << SPI_CFG2_MASTER_Pos) /*!< 0x00400000 */
17161 #define SPI_CFG2_MASTER SPI_CFG2_MASTER_Msk /*!<SPI Master */
17162 #define SPI_CFG2_LSBFRST_Pos (23U)
17163 #define SPI_CFG2_LSBFRST_Msk (0x1UL << SPI_CFG2_LSBFRST_Pos) /*!< 0x00800000 */
17164 #define SPI_CFG2_LSBFRST SPI_CFG2_LSBFRST_Msk /*!<Data frame format */
17165 #define SPI_CFG2_CPHA_Pos (24U)
17166 #define SPI_CFG2_CPHA_Msk (0x1UL << SPI_CFG2_CPHA_Pos) /*!< 0x01000000 */
17167 #define SPI_CFG2_CPHA SPI_CFG2_CPHA_Msk /*!<Clock Phase */
17168 #define SPI_CFG2_CPOL_Pos (25U)
17169 #define SPI_CFG2_CPOL_Msk (0x1UL << SPI_CFG2_CPOL_Pos) /*!< 0x02000000 */
17170 #define SPI_CFG2_CPOL SPI_CFG2_CPOL_Msk /*!<Clock Polarity */
17171 #define SPI_CFG2_SSM_Pos (26U)
17172 #define SPI_CFG2_SSM_Msk (0x1UL << SPI_CFG2_SSM_Pos) /*!< 0x04000000 */
17173 #define SPI_CFG2_SSM SPI_CFG2_SSM_Msk /*!<Software slave management */
17174
17175 #define SPI_CFG2_SSIOP_Pos (28U)
17176 #define SPI_CFG2_SSIOP_Msk (0x1UL << SPI_CFG2_SSIOP_Pos) /*!< 0x10000000 */
17177 #define SPI_CFG2_SSIOP SPI_CFG2_SSIOP_Msk /*!<SS input/output polarity */
17178 #define SPI_CFG2_SSOE_Pos (29U)
17179 #define SPI_CFG2_SSOE_Msk (0x1UL << SPI_CFG2_SSOE_Pos) /*!< 0x20000000 */
17180 #define SPI_CFG2_SSOE SPI_CFG2_SSOE_Msk /*!<SS output enable */
17181 #define SPI_CFG2_SSOM_Pos (30U)
17182 #define SPI_CFG2_SSOM_Msk (0x1UL << SPI_CFG2_SSOM_Pos) /*!< 0x40000000 */
17183 #define SPI_CFG2_SSOM SPI_CFG2_SSOM_Msk /*!<SS output management in master mode */
17184
17185 #define SPI_CFG2_AFCNTR_Pos (31U)
17186 #define SPI_CFG2_AFCNTR_Msk (0x1UL << SPI_CFG2_AFCNTR_Pos) /*!< 0x80000000 */
17187 #define SPI_CFG2_AFCNTR SPI_CFG2_AFCNTR_Msk /*!<Alternate function GPIOs control */
17188
17189 /******************* Bit definition for SPI_IER register ********************/
17190 #define SPI_IER_RXPIE_Pos (0U)
17191 #define SPI_IER_RXPIE_Msk (0x1UL << SPI_IER_RXPIE_Pos) /*!< 0x00000001 */
17192 #define SPI_IER_RXPIE SPI_IER_RXPIE_Msk /*!<RXP Interrupt Enable */
17193 #define SPI_IER_TXPIE_Pos (1U)
17194 #define SPI_IER_TXPIE_Msk (0x1UL << SPI_IER_TXPIE_Pos) /*!< 0x00000002 */
17195 #define SPI_IER_TXPIE SPI_IER_TXPIE_Msk /*!<TXP interrupt enable */
17196 #define SPI_IER_DXPIE_Pos (2U)
17197 #define SPI_IER_DXPIE_Msk (0x1UL << SPI_IER_DXPIE_Pos) /*!< 0x00000004 */
17198 #define SPI_IER_DXPIE SPI_IER_DXPIE_Msk /*!<DXP interrupt enable */
17199 #define SPI_IER_EOTIE_Pos (3U)
17200 #define SPI_IER_EOTIE_Msk (0x1UL << SPI_IER_EOTIE_Pos) /*!< 0x00000008 */
17201 #define SPI_IER_EOTIE SPI_IER_EOTIE_Msk /*!<EOT/SUSP/TXC interrupt enable */
17202 #define SPI_IER_TXTFIE_Pos (4U)
17203 #define SPI_IER_TXTFIE_Msk (0x1UL << SPI_IER_TXTFIE_Pos) /*!< 0x00000010 */
17204 #define SPI_IER_TXTFIE SPI_IER_TXTFIE_Msk /*!<TXTF interrupt enable */
17205 #define SPI_IER_UDRIE_Pos (5U)
17206 #define SPI_IER_UDRIE_Msk (0x1UL << SPI_IER_UDRIE_Pos) /*!< 0x00000020 */
17207 #define SPI_IER_UDRIE SPI_IER_UDRIE_Msk /*!<UDR interrupt enable */
17208 #define SPI_IER_OVRIE_Pos (6U)
17209 #define SPI_IER_OVRIE_Msk (0x1UL << SPI_IER_OVRIE_Pos) /*!< 0x00000040 */
17210 #define SPI_IER_OVRIE SPI_IER_OVRIE_Msk /*!<OVR interrupt enable */
17211 #define SPI_IER_CRCEIE_Pos (7U)
17212 #define SPI_IER_CRCEIE_Msk (0x1UL << SPI_IER_CRCEIE_Pos) /*!< 0x00000080 */
17213 #define SPI_IER_CRCEIE SPI_IER_CRCEIE_Msk /*!<CRCE interrupt enable */
17214 #define SPI_IER_TIFREIE_Pos (8U)
17215 #define SPI_IER_TIFREIE_Msk (0x1UL << SPI_IER_TIFREIE_Pos) /*!< 0x00000100 */
17216 #define SPI_IER_TIFREIE SPI_IER_TIFREIE_Msk /*!<TI Frame Error interrupt enable */
17217 #define SPI_IER_MODFIE_Pos (9U)
17218 #define SPI_IER_MODFIE_Msk (0x1UL << SPI_IER_MODFIE_Pos) /*!< 0x00000200 */
17219 #define SPI_IER_MODFIE SPI_IER_MODFIE_Msk /*!<MODF interrupt enable */
17220 #define SPI_IER_TSERFIE_Pos (10U)
17221 #define SPI_IER_TSERFIE_Msk (0x1UL << SPI_IER_TSERFIE_Pos) /*!< 0x00000400 */
17222 #define SPI_IER_TSERFIE SPI_IER_TSERFIE_Msk /*!<TSERF interrupt enable */
17223
17224 /******************* Bit definition for SPI_SR register ********************/
17225 #define SPI_SR_RXP_Pos (0U)
17226 #define SPI_SR_RXP_Msk (0x1UL << SPI_SR_RXP_Pos) /*!< 0x00000001 */
17227 #define SPI_SR_RXP SPI_SR_RXP_Msk /*!<Rx-Packet available */
17228 #define SPI_SR_TXP_Pos (1U)
17229 #define SPI_SR_TXP_Msk (0x1UL << SPI_SR_TXP_Pos) /*!< 0x00000002 */
17230 #define SPI_SR_TXP SPI_SR_TXP_Msk /*!<Tx-Packet space available */
17231 #define SPI_SR_DXP_Pos (2U)
17232 #define SPI_SR_DXP_Msk (0x1UL << SPI_SR_DXP_Pos) /*!< 0x00000004 */
17233 #define SPI_SR_DXP SPI_SR_DXP_Msk /*!<Duplex Packet available */
17234 #define SPI_SR_EOT_Pos (3U)
17235 #define SPI_SR_EOT_Msk (0x1UL << SPI_SR_EOT_Pos) /*!< 0x00000008 */
17236 #define SPI_SR_EOT SPI_SR_EOT_Msk /*!<Duplex Packet available */
17237 #define SPI_SR_TXTF_Pos (4U)
17238 #define SPI_SR_TXTF_Msk (0x1UL << SPI_SR_TXTF_Pos) /*!< 0x00000010 */
17239 #define SPI_SR_TXTF SPI_SR_TXTF_Msk /*!<Transmission Transfer Filled */
17240 #define SPI_SR_UDR_Pos (5U)
17241 #define SPI_SR_UDR_Msk (0x1UL << SPI_SR_UDR_Pos) /*!< 0x00000020 */
17242 #define SPI_SR_UDR SPI_SR_UDR_Msk /*!<UDR at Slave transmission */
17243 #define SPI_SR_OVR_Pos (6U)
17244 #define SPI_SR_OVR_Msk (0x1UL << SPI_SR_OVR_Pos) /*!< 0x00000040 */
17245 #define SPI_SR_OVR SPI_SR_OVR_Msk /*!<Rx-Packet available */
17246 #define SPI_SR_CRCE_Pos (7U)
17247 #define SPI_SR_CRCE_Msk (0x1UL << SPI_SR_CRCE_Pos) /*!< 0x00000080 */
17248 #define SPI_SR_CRCE SPI_SR_CRCE_Msk /*!<CRC Error Detected */
17249 #define SPI_SR_TIFRE_Pos (8U)
17250 #define SPI_SR_TIFRE_Msk (0x1UL << SPI_SR_TIFRE_Pos) /*!< 0x00000100 */
17251 #define SPI_SR_TIFRE SPI_SR_TIFRE_Msk /*!<TI frame format error Detected */
17252 #define SPI_SR_MODF_Pos (9U)
17253 #define SPI_SR_MODF_Msk (0x1UL << SPI_SR_MODF_Pos) /*!< 0x00000200 */
17254 #define SPI_SR_MODF SPI_SR_MODF_Msk /*!<Mode Fault Detected */
17255 #define SPI_SR_TSERF_Pos (10U)
17256 #define SPI_SR_TSERF_Msk (0x1UL << SPI_SR_TSERF_Pos) /*!< 0x00000400 */
17257 #define SPI_SR_TSERF SPI_SR_TSERF_Msk /*!<Number of SPI data to be transacted reloaded */
17258 #define SPI_SR_SUSP_Pos (11U)
17259 #define SPI_SR_SUSP_Msk (0x1UL << SPI_SR_SUSP_Pos) /*!< 0x00000800 */
17260 #define SPI_SR_SUSP SPI_SR_SUSP_Msk /*!<SUSP is set by hardware */
17261 #define SPI_SR_TXC_Pos (12U)
17262 #define SPI_SR_TXC_Msk (0x1UL << SPI_SR_TXC_Pos) /*!< 0x00001000 */
17263 #define SPI_SR_TXC SPI_SR_TXC_Msk /*!<TxFIFO transmission complete */
17264 #define SPI_SR_RXPLVL_Pos (13U)
17265 #define SPI_SR_RXPLVL_Msk (0x3UL << SPI_SR_RXPLVL_Pos) /*!< 0x00006000 */
17266 #define SPI_SR_RXPLVL SPI_SR_RXPLVL_Msk /*!<RxFIFO Packing Level */
17267 #define SPI_SR_RXPLVL_0 (0x1UL << SPI_SR_RXPLVL_Pos) /*!< 0x00002000 */
17268 #define SPI_SR_RXPLVL_1 (0x2UL << SPI_SR_RXPLVL_Pos) /*!< 0x00004000 */
17269 #define SPI_SR_RXWNE_Pos (15U)
17270 #define SPI_SR_RXWNE_Msk (0x1UL << SPI_SR_RXWNE_Pos) /*!< 0x00008000 */
17271 #define SPI_SR_RXWNE SPI_SR_RXWNE_Msk /*!<Rx FIFO Word Not Empty */
17272 #define SPI_SR_CTSIZE_Pos (16U)
17273 #define SPI_SR_CTSIZE_Msk (0xFFFFUL << SPI_SR_CTSIZE_Pos) /*!< 0xFFFF0000 */
17274 #define SPI_SR_CTSIZE SPI_SR_CTSIZE_Msk /*!<Number of data frames remaining in TSIZE */
17275
17276 /******************* Bit definition for SPI_IFCR register ********************/
17277 #define SPI_IFCR_EOTC_Pos (3U)
17278 #define SPI_IFCR_EOTC_Msk (0x1UL << SPI_IFCR_EOTC_Pos) /*!< 0x00000008 */
17279 #define SPI_IFCR_EOTC SPI_IFCR_EOTC_Msk /*!<End Of Transfer flag clear */
17280 #define SPI_IFCR_TXTFC_Pos (4U)
17281 #define SPI_IFCR_TXTFC_Msk (0x1UL << SPI_IFCR_TXTFC_Pos) /*!< 0x00000010 */
17282 #define SPI_IFCR_TXTFC SPI_IFCR_TXTFC_Msk /*!<Transmission Transfer Filled flag clear */
17283 #define SPI_IFCR_UDRC_Pos (5U)
17284 #define SPI_IFCR_UDRC_Msk (0x1UL << SPI_IFCR_UDRC_Pos) /*!< 0x00000020 */
17285 #define SPI_IFCR_UDRC SPI_IFCR_UDRC_Msk /*!<Underrun flag clear */
17286 #define SPI_IFCR_OVRC_Pos (6U)
17287 #define SPI_IFCR_OVRC_Msk (0x1UL << SPI_IFCR_OVRC_Pos) /*!< 0x00000040 */
17288 #define SPI_IFCR_OVRC SPI_IFCR_OVRC_Msk /*!<Overrun flag clear */
17289 #define SPI_IFCR_CRCEC_Pos (7U)
17290 #define SPI_IFCR_CRCEC_Msk (0x1UL << SPI_IFCR_CRCEC_Pos) /*!< 0x00000080 */
17291 #define SPI_IFCR_CRCEC SPI_IFCR_CRCEC_Msk /*!<CRC Error flag clear */
17292 #define SPI_IFCR_TIFREC_Pos (8U)
17293 #define SPI_IFCR_TIFREC_Msk (0x1UL << SPI_IFCR_TIFREC_Pos) /*!< 0x00000100 */
17294 #define SPI_IFCR_TIFREC SPI_IFCR_TIFREC_Msk /*!<TI frame format error flag clear */
17295 #define SPI_IFCR_MODFC_Pos (9U)
17296 #define SPI_IFCR_MODFC_Msk (0x1UL << SPI_IFCR_MODFC_Pos) /*!< 0x00000200 */
17297 #define SPI_IFCR_MODFC SPI_IFCR_MODFC_Msk /*!<Mode Fault flag clear */
17298 #define SPI_IFCR_TSERFC_Pos (10U)
17299 #define SPI_IFCR_TSERFC_Msk (0x1UL << SPI_IFCR_TSERFC_Pos) /*!< 0x00000400 */
17300 #define SPI_IFCR_TSERFC SPI_IFCR_TSERFC_Msk /*!<TSERFC flag clear */
17301 #define SPI_IFCR_SUSPC_Pos (11U)
17302 #define SPI_IFCR_SUSPC_Msk (0x1UL << SPI_IFCR_SUSPC_Pos) /*!< 0x00000800 */
17303 #define SPI_IFCR_SUSPC SPI_IFCR_SUSPC_Msk /*!<SUSPend flag clear */
17304
17305 /******************* Bit definition for SPI_TXDR register ********************/
17306 #define SPI_TXDR_TXDR_Pos (0U)
17307 #define SPI_TXDR_TXDR_Msk (0xFFFFFFFFUL << SPI_TXDR_TXDR_Pos) /*!< 0xFFFFFFFF */
17308 #define SPI_TXDR_TXDR SPI_TXDR_TXDR_Msk /* Transmit Data Register */
17309
17310 /******************* Bit definition for SPI_RXDR register ********************/
17311 #define SPI_RXDR_RXDR_Pos (0U)
17312 #define SPI_RXDR_RXDR_Msk (0xFFFFFFFFUL << SPI_RXDR_RXDR_Pos) /*!< 0xFFFFFFFF */
17313 #define SPI_RXDR_RXDR SPI_RXDR_RXDR_Msk /* Receive Data Register */
17314
17315 /******************* Bit definition for SPI_CRCPOLY register ********************/
17316 #define SPI_CRCPOLY_CRCPOLY_Pos (0U)
17317 #define SPI_CRCPOLY_CRCPOLY_Msk (0xFFFFFFFFUL << SPI_CRCPOLY_CRCPOLY_Pos) /*!< 0xFFFFFFFF */
17318 #define SPI_CRCPOLY_CRCPOLY SPI_CRCPOLY_CRCPOLY_Msk /* CRC Polynomial register */
17319
17320 /******************* Bit definition for SPI_TXCRC register ********************/
17321 #define SPI_TXCRC_TXCRC_Pos (0U)
17322 #define SPI_TXCRC_TXCRC_Msk (0xFFFFFFFFUL << SPI_TXCRC_TXCRC_Pos) /*!< 0xFFFFFFFF */
17323 #define SPI_TXCRC_TXCRC SPI_TXCRC_TXCRC_Msk /* CRCRegister for transmitter */
17324
17325 /******************* Bit definition for SPI_RXCRC register ********************/
17326 #define SPI_RXCRC_RXCRC_Pos (0U)
17327 #define SPI_RXCRC_RXCRC_Msk (0xFFFFFFFFUL << SPI_RXCRC_RXCRC_Pos) /*!< 0xFFFFFFFF */
17328 #define SPI_RXCRC_RXCRC SPI_RXCRC_RXCRC_Msk /* CRCRegister for receiver */
17329
17330 /******************* Bit definition for SPI_UDRDR register ********************/
17331 #define SPI_UDRDR_UDRDR_Pos (0U)
17332 #define SPI_UDRDR_UDRDR_Msk (0xFFFFFFFFUL << SPI_UDRDR_UDRDR_Pos) /*!< 0xFFFFFFFF */
17333 #define SPI_UDRDR_UDRDR SPI_UDRDR_UDRDR_Msk /* Data at slave underrun condition */
17334
17335 /****************** Bit definition for SPI_I2SCFGR register *****************/
17336 #define SPI_I2SCFGR_I2SMOD_Pos (0U)
17337 #define SPI_I2SCFGR_I2SMOD_Msk (0x1UL << SPI_I2SCFGR_I2SMOD_Pos) /*!< 0x00000001 */
17338 #define SPI_I2SCFGR_I2SMOD SPI_I2SCFGR_I2SMOD_Msk /*!<I2S mode selection */
17339 #define SPI_I2SCFGR_I2SCFG_Pos (1U)
17340 #define SPI_I2SCFGR_I2SCFG_Msk (0x7UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x0000000E */
17341 #define SPI_I2SCFGR_I2SCFG SPI_I2SCFGR_I2SCFG_Msk /*!<I2SCFG[2:0] I2S configuration mode */
17342 #define SPI_I2SCFGR_I2SCFG_0 (0x1UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000002 */
17343 #define SPI_I2SCFGR_I2SCFG_1 (0x2UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000004 */
17344 #define SPI_I2SCFGR_I2SCFG_2 (0x4UL << SPI_I2SCFGR_I2SCFG_Pos) /*!< 0x00000008 */
17345 #define SPI_I2SCFGR_I2SSTD_Pos (4U)
17346 #define SPI_I2SCFGR_I2SSTD_Msk (0x3UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000030 */
17347 #define SPI_I2SCFGR_I2SSTD SPI_I2SCFGR_I2SSTD_Msk /*!<I2SSTD[1:0] I2S standard selection */
17348 #define SPI_I2SCFGR_I2SSTD_0 (0x1UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000010 */
17349 #define SPI_I2SCFGR_I2SSTD_1 (0x2UL << SPI_I2SCFGR_I2SSTD_Pos) /*!< 0x00000020 */
17350 #define SPI_I2SCFGR_PCMSYNC_Pos (7U)
17351 #define SPI_I2SCFGR_PCMSYNC_Msk (0x1UL << SPI_I2SCFGR_PCMSYNC_Pos) /*!< 0x00000080 */
17352 #define SPI_I2SCFGR_PCMSYNC SPI_I2SCFGR_PCMSYNC_Msk /*!<PCM frame synchronization */
17353 #define SPI_I2SCFGR_DATLEN_Pos (8U)
17354 #define SPI_I2SCFGR_DATLEN_Msk (0x3UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000300 */
17355 #define SPI_I2SCFGR_DATLEN SPI_I2SCFGR_DATLEN_Msk /*!<DATLEN[1:0] Data length to be transferred */
17356 #define SPI_I2SCFGR_DATLEN_0 (0x1UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000100 */
17357 #define SPI_I2SCFGR_DATLEN_1 (0x2UL << SPI_I2SCFGR_DATLEN_Pos) /*!< 0x00000200 */
17358 #define SPI_I2SCFGR_CHLEN_Pos (10U)
17359 #define SPI_I2SCFGR_CHLEN_Msk (0x1UL << SPI_I2SCFGR_CHLEN_Pos) /*!< 0x00000400 */
17360 #define SPI_I2SCFGR_CHLEN SPI_I2SCFGR_CHLEN_Msk /*!<Channel length (number of bits per audio channel) */
17361 #define SPI_I2SCFGR_CKPOL_Pos (11U)
17362 #define SPI_I2SCFGR_CKPOL_Msk (0x1UL << SPI_I2SCFGR_CKPOL_Pos) /*!< 0x00000800 */
17363 #define SPI_I2SCFGR_CKPOL SPI_I2SCFGR_CKPOL_Msk /*!<Steady state clock polarity */
17364 #define SPI_I2SCFGR_FIXCH_Pos (12U)
17365 #define SPI_I2SCFGR_FIXCH_Msk (0x1UL << SPI_I2SCFGR_FIXCH_Pos) /*!< 0x00001000 */
17366 #define SPI_I2SCFGR_FIXCH SPI_I2SCFGR_FIXCH_Msk /*!<Fixed channel length in SLAVE */
17367 #define SPI_I2SCFGR_WSINV_Pos (13U)
17368 #define SPI_I2SCFGR_WSINV_Msk (0x1UL << SPI_I2SCFGR_WSINV_Pos) /*!< 0x00002000 */
17369 #define SPI_I2SCFGR_WSINV SPI_I2SCFGR_WSINV_Msk /*!<Word select inversion */
17370 #define SPI_I2SCFGR_DATFMT_Pos (14U)
17371 #define SPI_I2SCFGR_DATFMT_Msk (0x1UL << SPI_I2SCFGR_DATFMT_Pos) /*!< 0x00004000 */
17372 #define SPI_I2SCFGR_DATFMT SPI_I2SCFGR_DATFMT_Msk /*!<Data format */
17373 #define SPI_I2SCFGR_I2SDIV_Pos (16U)
17374 #define SPI_I2SCFGR_I2SDIV_Msk (0xFFUL << SPI_I2SCFGR_I2SDIV_Pos) /*!< 0x00FF0000 */
17375 #define SPI_I2SCFGR_I2SDIV SPI_I2SCFGR_I2SDIV_Msk /*!<I2S Linear prescaler */
17376 #define SPI_I2SCFGR_ODD_Pos (24U)
17377 #define SPI_I2SCFGR_ODD_Msk (0x1UL << SPI_I2SCFGR_ODD_Pos) /*!< 0x01000000 */
17378 #define SPI_I2SCFGR_ODD SPI_I2SCFGR_ODD_Msk /*!<Odd factor for the prescaler */
17379 #define SPI_I2SCFGR_MCKOE_Pos (25U)
17380 #define SPI_I2SCFGR_MCKOE_Msk (0x1UL << SPI_I2SCFGR_MCKOE_Pos) /*!< 0x02000000 */
17381 #define SPI_I2SCFGR_MCKOE SPI_I2SCFGR_MCKOE_Msk /*!<Master Clock Output Enable */
17382
17383
17384
17385 /******************************************************************************/
17386 /* */
17387 /* SYSCFG */
17388 /* */
17389 /******************************************************************************/
17390
17391 /****************** Bit definition for SYSCFG_PMCR register ******************/
17392 #define SYSCFG_PMCR_I2C1_FMP_Pos (0U)
17393 #define SYSCFG_PMCR_I2C1_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C1_FMP_Pos) /*!< 0x00000001 */
17394 #define SYSCFG_PMCR_I2C1_FMP SYSCFG_PMCR_I2C1_FMP_Msk /*!< I2C1 Fast mode plus */
17395 #define SYSCFG_PMCR_I2C2_FMP_Pos (1U)
17396 #define SYSCFG_PMCR_I2C2_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C2_FMP_Pos) /*!< 0x00000002 */
17397 #define SYSCFG_PMCR_I2C2_FMP SYSCFG_PMCR_I2C2_FMP_Msk /*!< I2C2 Fast mode plus */
17398 #define SYSCFG_PMCR_I2C3_FMP_Pos (2U)
17399 #define SYSCFG_PMCR_I2C3_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C3_FMP_Pos) /*!< 0x00000004 */
17400 #define SYSCFG_PMCR_I2C3_FMP SYSCFG_PMCR_I2C3_FMP_Msk /*!< I2C3 Fast mode plus */
17401 #define SYSCFG_PMCR_I2C4_FMP_Pos (3U)
17402 #define SYSCFG_PMCR_I2C4_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C4_FMP_Pos) /*!< 0x00000008 */
17403 #define SYSCFG_PMCR_I2C4_FMP SYSCFG_PMCR_I2C4_FMP_Msk /*!< I2C4 Fast mode plus */
17404 #define SYSCFG_PMCR_I2C_PB6_FMP_Pos (4U)
17405 #define SYSCFG_PMCR_I2C_PB6_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB6_FMP_Pos) /*!< 0x00000010 */
17406 #define SYSCFG_PMCR_I2C_PB6_FMP SYSCFG_PMCR_I2C_PB6_FMP_Msk /*!< I2C PB6 Fast mode plus */
17407 #define SYSCFG_PMCR_I2C_PB7_FMP_Pos (5U)
17408 #define SYSCFG_PMCR_I2C_PB7_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB7_FMP_Pos) /*!< 0x00000020 */
17409 #define SYSCFG_PMCR_I2C_PB7_FMP SYSCFG_PMCR_I2C_PB7_FMP_Msk /*!< I2C PB7 Fast mode plus */
17410 #define SYSCFG_PMCR_I2C_PB8_FMP_Pos (6U)
17411 #define SYSCFG_PMCR_I2C_PB8_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB8_FMP_Pos) /*!< 0x00000040 */
17412 #define SYSCFG_PMCR_I2C_PB8_FMP SYSCFG_PMCR_I2C_PB8_FMP_Msk /*!< I2C PB8 Fast mode plus */
17413 #define SYSCFG_PMCR_I2C_PB9_FMP_Pos (7U)
17414 #define SYSCFG_PMCR_I2C_PB9_FMP_Msk (0x1UL << SYSCFG_PMCR_I2C_PB9_FMP_Pos) /*!< 0x00000080 */
17415 #define SYSCFG_PMCR_I2C_PB9_FMP SYSCFG_PMCR_I2C_PB9_FMP_Msk /*!< I2C PB9 Fast mode plus */
17416 #define SYSCFG_PMCR_PA0SO_Pos (24U)
17417 #define SYSCFG_PMCR_PA0SO_Msk (0x1UL << SYSCFG_PMCR_PA0SO_Pos) /*!< 0x01000000 */
17418 #define SYSCFG_PMCR_PA0SO SYSCFG_PMCR_PA0SO_Msk /*!< PA0 Switch Open */
17419 #define SYSCFG_PMCR_PA1SO_Pos (25U)
17420 #define SYSCFG_PMCR_PA1SO_Msk (0x1UL << SYSCFG_PMCR_PA1SO_Pos) /*!< 0x02000000 */
17421 #define SYSCFG_PMCR_PA1SO SYSCFG_PMCR_PA1SO_Msk /*!< PA1 Switch Open */
17422 #define SYSCFG_PMCR_PC2SO_Pos (26U)
17423 #define SYSCFG_PMCR_PC2SO_Msk (0x1UL << SYSCFG_PMCR_PC2SO_Pos) /*!< 0x04000000 */
17424 #define SYSCFG_PMCR_PC2SO SYSCFG_PMCR_PC2SO_Msk /*!< PC2 Switch Open */
17425 #define SYSCFG_PMCR_PC3SO_Pos (27U)
17426 #define SYSCFG_PMCR_PC3SO_Msk (0x1UL << SYSCFG_PMCR_PC3SO_Pos) /*!< 0x08000000 */
17427 #define SYSCFG_PMCR_PC3SO SYSCFG_PMCR_PC3SO_Msk /*!< PC3 Switch Open */
17428
17429 /***************** Bit definition for SYSCFG_EXTICR1 register ***************/
17430 #define SYSCFG_EXTICR1_EXTI0_Pos (0U)
17431 #define SYSCFG_EXTICR1_EXTI0_Msk (0xFUL << SYSCFG_EXTICR1_EXTI0_Pos) /*!< 0x0000000F */
17432 #define SYSCFG_EXTICR1_EXTI0 SYSCFG_EXTICR1_EXTI0_Msk /*!<EXTI 0 configuration */
17433 #define SYSCFG_EXTICR1_EXTI1_Pos (4U)
17434 #define SYSCFG_EXTICR1_EXTI1_Msk (0xFUL << SYSCFG_EXTICR1_EXTI1_Pos) /*!< 0x000000F0 */
17435 #define SYSCFG_EXTICR1_EXTI1 SYSCFG_EXTICR1_EXTI1_Msk /*!<EXTI 1 configuration */
17436 #define SYSCFG_EXTICR1_EXTI2_Pos (8U)
17437 #define SYSCFG_EXTICR1_EXTI2_Msk (0xFUL << SYSCFG_EXTICR1_EXTI2_Pos) /*!< 0x00000F00 */
17438 #define SYSCFG_EXTICR1_EXTI2 SYSCFG_EXTICR1_EXTI2_Msk /*!<EXTI 2 configuration */
17439 #define SYSCFG_EXTICR1_EXTI3_Pos (12U)
17440 #define SYSCFG_EXTICR1_EXTI3_Msk (0xFUL << SYSCFG_EXTICR1_EXTI3_Pos) /*!< 0x0000F000 */
17441 #define SYSCFG_EXTICR1_EXTI3 SYSCFG_EXTICR1_EXTI3_Msk /*!<EXTI 3 configuration */
17442 /**
17443 * @brief EXTI0 configuration
17444 */
17445 #define SYSCFG_EXTICR1_EXTI0_PA ((uint32_t)0x00000000) /*!<PA[0] pin */
17446 #define SYSCFG_EXTICR1_EXTI0_PB ((uint32_t)0x00000001) /*!<PB[0] pin */
17447 #define SYSCFG_EXTICR1_EXTI0_PC ((uint32_t)0x00000002) /*!<PC[0] pin */
17448 #define SYSCFG_EXTICR1_EXTI0_PD ((uint32_t)0x00000003) /*!<PD[0] pin */
17449 #define SYSCFG_EXTICR1_EXTI0_PE ((uint32_t)0x00000004) /*!<PE[0] pin */
17450 #define SYSCFG_EXTICR1_EXTI0_PF ((uint32_t)0x00000005) /*!<PF[0] pin */
17451 #define SYSCFG_EXTICR1_EXTI0_PG ((uint32_t)0x00000006) /*!<PG[0] pin */
17452 #define SYSCFG_EXTICR1_EXTI0_PH ((uint32_t)0x00000007) /*!<PH[0] pin */
17453 #define SYSCFG_EXTICR1_EXTI0_PI ((uint32_t)0x00000008) /*!<PI[0] pin */
17454 #define SYSCFG_EXTICR1_EXTI0_PJ ((uint32_t)0x00000009) /*!<PJ[0] pin */
17455 #define SYSCFG_EXTICR1_EXTI0_PK ((uint32_t)0x0000000A) /*!<PK[0] pin */
17456
17457 /**
17458 * @brief EXTI1 configuration
17459 */
17460 #define SYSCFG_EXTICR1_EXTI1_PA ((uint32_t)0x00000000) /*!<PA[1] pin */
17461 #define SYSCFG_EXTICR1_EXTI1_PB ((uint32_t)0x00000010) /*!<PB[1] pin */
17462 #define SYSCFG_EXTICR1_EXTI1_PC ((uint32_t)0x00000020) /*!<PC[1] pin */
17463 #define SYSCFG_EXTICR1_EXTI1_PD ((uint32_t)0x00000030) /*!<PD[1] pin */
17464 #define SYSCFG_EXTICR1_EXTI1_PE ((uint32_t)0x00000040) /*!<PE[1] pin */
17465 #define SYSCFG_EXTICR1_EXTI1_PF ((uint32_t)0x00000050) /*!<PF[1] pin */
17466 #define SYSCFG_EXTICR1_EXTI1_PG ((uint32_t)0x00000060) /*!<PG[1] pin */
17467 #define SYSCFG_EXTICR1_EXTI1_PH ((uint32_t)0x00000070) /*!<PH[1] pin */
17468 #define SYSCFG_EXTICR1_EXTI1_PI ((uint32_t)0x00000080) /*!<PI[1] pin */
17469 #define SYSCFG_EXTICR1_EXTI1_PJ ((uint32_t)0x00000090) /*!<PJ[1] pin */
17470 #define SYSCFG_EXTICR1_EXTI1_PK ((uint32_t)0x000000A0) /*!<PK[1] pin */
17471 /**
17472 * @brief EXTI2 configuration
17473 */
17474 #define SYSCFG_EXTICR1_EXTI2_PA ((uint32_t)0x00000000) /*!<PA[2] pin */
17475 #define SYSCFG_EXTICR1_EXTI2_PB ((uint32_t)0x00000100) /*!<PB[2] pin */
17476 #define SYSCFG_EXTICR1_EXTI2_PC ((uint32_t)0x00000200) /*!<PC[2] pin */
17477 #define SYSCFG_EXTICR1_EXTI2_PD ((uint32_t)0x00000300) /*!<PD[2] pin */
17478 #define SYSCFG_EXTICR1_EXTI2_PE ((uint32_t)0x00000400) /*!<PE[2] pin */
17479 #define SYSCFG_EXTICR1_EXTI2_PF ((uint32_t)0x00000500) /*!<PF[2] pin */
17480 #define SYSCFG_EXTICR1_EXTI2_PG ((uint32_t)0x00000600) /*!<PG[2] pin */
17481 #define SYSCFG_EXTICR1_EXTI2_PH ((uint32_t)0x00000700) /*!<PH[2] pin */
17482 #define SYSCFG_EXTICR1_EXTI2_PI ((uint32_t)0x00000800) /*!<PI[2] pin */
17483 #define SYSCFG_EXTICR1_EXTI2_PJ ((uint32_t)0x00000900) /*!<PJ[2] pin */
17484 #define SYSCFG_EXTICR1_EXTI2_PK ((uint32_t)0x00000A00) /*!<PK[2] pin */
17485
17486 /**
17487 * @brief EXTI3 configuration
17488 */
17489 #define SYSCFG_EXTICR1_EXTI3_PA ((uint32_t)0x00000000) /*!<PA[3] pin */
17490 #define SYSCFG_EXTICR1_EXTI3_PB ((uint32_t)0x00001000) /*!<PB[3] pin */
17491 #define SYSCFG_EXTICR1_EXTI3_PC ((uint32_t)0x00002000) /*!<PC[3] pin */
17492 #define SYSCFG_EXTICR1_EXTI3_PD ((uint32_t)0x00003000) /*!<PD[3] pin */
17493 #define SYSCFG_EXTICR1_EXTI3_PE ((uint32_t)0x00004000) /*!<PE[3] pin */
17494 #define SYSCFG_EXTICR1_EXTI3_PF ((uint32_t)0x00005000) /*!<PF[3] pin */
17495 #define SYSCFG_EXTICR1_EXTI3_PG ((uint32_t)0x00006000) /*!<PG[3] pin */
17496 #define SYSCFG_EXTICR1_EXTI3_PH ((uint32_t)0x00007000) /*!<PH[3] pin */
17497 #define SYSCFG_EXTICR1_EXTI3_PI ((uint32_t)0x00008000) /*!<PI[3] pin */
17498 #define SYSCFG_EXTICR1_EXTI3_PJ ((uint32_t)0x00009000) /*!<PJ[3] pin */
17499 #define SYSCFG_EXTICR1_EXTI3_PK ((uint32_t)0x0000A000) /*!<PK[3] pin */
17500
17501 /***************** Bit definition for SYSCFG_EXTICR2 register ***************/
17502 #define SYSCFG_EXTICR2_EXTI4_Pos (0U)
17503 #define SYSCFG_EXTICR2_EXTI4_Msk (0xFUL << SYSCFG_EXTICR2_EXTI4_Pos) /*!< 0x0000000F */
17504 #define SYSCFG_EXTICR2_EXTI4 SYSCFG_EXTICR2_EXTI4_Msk /*!<EXTI 4 configuration */
17505 #define SYSCFG_EXTICR2_EXTI5_Pos (4U)
17506 #define SYSCFG_EXTICR2_EXTI5_Msk (0xFUL << SYSCFG_EXTICR2_EXTI5_Pos) /*!< 0x000000F0 */
17507 #define SYSCFG_EXTICR2_EXTI5 SYSCFG_EXTICR2_EXTI5_Msk /*!<EXTI 5 configuration */
17508 #define SYSCFG_EXTICR2_EXTI6_Pos (8U)
17509 #define SYSCFG_EXTICR2_EXTI6_Msk (0xFUL << SYSCFG_EXTICR2_EXTI6_Pos) /*!< 0x00000F00 */
17510 #define SYSCFG_EXTICR2_EXTI6 SYSCFG_EXTICR2_EXTI6_Msk /*!<EXTI 6 configuration */
17511 #define SYSCFG_EXTICR2_EXTI7_Pos (12U)
17512 #define SYSCFG_EXTICR2_EXTI7_Msk (0xFUL << SYSCFG_EXTICR2_EXTI7_Pos) /*!< 0x0000F000 */
17513 #define SYSCFG_EXTICR2_EXTI7 SYSCFG_EXTICR2_EXTI7_Msk /*!<EXTI 7 configuration */
17514 /**
17515 * @brief EXTI4 configuration
17516 */
17517 #define SYSCFG_EXTICR2_EXTI4_PA ((uint32_t)0x00000000) /*!<PA[4] pin */
17518 #define SYSCFG_EXTICR2_EXTI4_PB ((uint32_t)0x00000001) /*!<PB[4] pin */
17519 #define SYSCFG_EXTICR2_EXTI4_PC ((uint32_t)0x00000002) /*!<PC[4] pin */
17520 #define SYSCFG_EXTICR2_EXTI4_PD ((uint32_t)0x00000003) /*!<PD[4] pin */
17521 #define SYSCFG_EXTICR2_EXTI4_PE ((uint32_t)0x00000004) /*!<PE[4] pin */
17522 #define SYSCFG_EXTICR2_EXTI4_PF ((uint32_t)0x00000005) /*!<PF[4] pin */
17523 #define SYSCFG_EXTICR2_EXTI4_PG ((uint32_t)0x00000006) /*!<PG[4] pin */
17524 #define SYSCFG_EXTICR2_EXTI4_PH ((uint32_t)0x00000007) /*!<PH[4] pin */
17525 #define SYSCFG_EXTICR2_EXTI4_PI ((uint32_t)0x00000008) /*!<PI[4] pin */
17526 #define SYSCFG_EXTICR2_EXTI4_PJ ((uint32_t)0x00000009) /*!<PJ[4] pin */
17527 #define SYSCFG_EXTICR2_EXTI4_PK ((uint32_t)0x0000000A) /*!<PK[4] pin */
17528 /**
17529 * @brief EXTI5 configuration
17530 */
17531 #define SYSCFG_EXTICR2_EXTI5_PA ((uint32_t)0x00000000) /*!<PA[5] pin */
17532 #define SYSCFG_EXTICR2_EXTI5_PB ((uint32_t)0x00000010) /*!<PB[5] pin */
17533 #define SYSCFG_EXTICR2_EXTI5_PC ((uint32_t)0x00000020) /*!<PC[5] pin */
17534 #define SYSCFG_EXTICR2_EXTI5_PD ((uint32_t)0x00000030) /*!<PD[5] pin */
17535 #define SYSCFG_EXTICR2_EXTI5_PE ((uint32_t)0x00000040) /*!<PE[5] pin */
17536 #define SYSCFG_EXTICR2_EXTI5_PF ((uint32_t)0x00000050) /*!<PF[5] pin */
17537 #define SYSCFG_EXTICR2_EXTI5_PG ((uint32_t)0x00000060) /*!<PG[5] pin */
17538 #define SYSCFG_EXTICR2_EXTI5_PH ((uint32_t)0x00000070) /*!<PH[5] pin */
17539 #define SYSCFG_EXTICR2_EXTI5_PI ((uint32_t)0x00000080) /*!<PI[5] pin */
17540 #define SYSCFG_EXTICR2_EXTI5_PJ ((uint32_t)0x00000090) /*!<PJ[5] pin */
17541 #define SYSCFG_EXTICR2_EXTI5_PK ((uint32_t)0x000000A0) /*!<PK[5] pin */
17542 /**
17543 * @brief EXTI6 configuration
17544 */
17545 #define SYSCFG_EXTICR2_EXTI6_PA ((uint32_t)0x00000000) /*!<PA[6] pin */
17546 #define SYSCFG_EXTICR2_EXTI6_PB ((uint32_t)0x00000100) /*!<PB[6] pin */
17547 #define SYSCFG_EXTICR2_EXTI6_PC ((uint32_t)0x00000200) /*!<PC[6] pin */
17548 #define SYSCFG_EXTICR2_EXTI6_PD ((uint32_t)0x00000300) /*!<PD[6] pin */
17549 #define SYSCFG_EXTICR2_EXTI6_PE ((uint32_t)0x00000400) /*!<PE[6] pin */
17550 #define SYSCFG_EXTICR2_EXTI6_PF ((uint32_t)0x00000500) /*!<PF[6] pin */
17551 #define SYSCFG_EXTICR2_EXTI6_PG ((uint32_t)0x00000600) /*!<PG[6] pin */
17552 #define SYSCFG_EXTICR2_EXTI6_PH ((uint32_t)0x00000700) /*!<PH[6] pin */
17553 #define SYSCFG_EXTICR2_EXTI6_PI ((uint32_t)0x00000800) /*!<PI[6] pin */
17554 #define SYSCFG_EXTICR2_EXTI6_PJ ((uint32_t)0x00000900) /*!<PJ[6] pin */
17555 #define SYSCFG_EXTICR2_EXTI6_PK ((uint32_t)0x00000A00) /*!<PK[6] pin */
17556
17557 /**
17558 * @brief EXTI7 configuration
17559 */
17560 #define SYSCFG_EXTICR2_EXTI7_PA ((uint32_t)0x00000000) /*!<PA[7] pin */
17561 #define SYSCFG_EXTICR2_EXTI7_PB ((uint32_t)0x00001000) /*!<PB[7] pin */
17562 #define SYSCFG_EXTICR2_EXTI7_PC ((uint32_t)0x00002000) /*!<PC[7] pin */
17563 #define SYSCFG_EXTICR2_EXTI7_PD ((uint32_t)0x00003000) /*!<PD[7] pin */
17564 #define SYSCFG_EXTICR2_EXTI7_PE ((uint32_t)0x00004000) /*!<PE[7] pin */
17565 #define SYSCFG_EXTICR2_EXTI7_PF ((uint32_t)0x00005000) /*!<PF[7] pin */
17566 #define SYSCFG_EXTICR2_EXTI7_PG ((uint32_t)0x00006000) /*!<PG[7] pin */
17567 #define SYSCFG_EXTICR2_EXTI7_PH ((uint32_t)0x00007000) /*!<PH[7] pin */
17568 #define SYSCFG_EXTICR2_EXTI7_PI ((uint32_t)0x00008000) /*!<PI[7] pin */
17569 #define SYSCFG_EXTICR2_EXTI7_PJ ((uint32_t)0x00009000) /*!<PJ[7] pin */
17570 #define SYSCFG_EXTICR2_EXTI7_PK ((uint32_t)0x0000A000) /*!<PK[7] pin */
17571
17572 /***************** Bit definition for SYSCFG_EXTICR3 register ***************/
17573 #define SYSCFG_EXTICR3_EXTI8_Pos (0U)
17574 #define SYSCFG_EXTICR3_EXTI8_Msk (0xFUL << SYSCFG_EXTICR3_EXTI8_Pos) /*!< 0x0000000F */
17575 #define SYSCFG_EXTICR3_EXTI8 SYSCFG_EXTICR3_EXTI8_Msk /*!<EXTI 8 configuration */
17576 #define SYSCFG_EXTICR3_EXTI9_Pos (4U)
17577 #define SYSCFG_EXTICR3_EXTI9_Msk (0xFUL << SYSCFG_EXTICR3_EXTI9_Pos) /*!< 0x000000F0 */
17578 #define SYSCFG_EXTICR3_EXTI9 SYSCFG_EXTICR3_EXTI9_Msk /*!<EXTI 9 configuration */
17579 #define SYSCFG_EXTICR3_EXTI10_Pos (8U)
17580 #define SYSCFG_EXTICR3_EXTI10_Msk (0xFUL << SYSCFG_EXTICR3_EXTI10_Pos) /*!< 0x00000F00 */
17581 #define SYSCFG_EXTICR3_EXTI10 SYSCFG_EXTICR3_EXTI10_Msk /*!<EXTI 10 configuration */
17582 #define SYSCFG_EXTICR3_EXTI11_Pos (12U)
17583 #define SYSCFG_EXTICR3_EXTI11_Msk (0xFUL << SYSCFG_EXTICR3_EXTI11_Pos) /*!< 0x0000F000 */
17584 #define SYSCFG_EXTICR3_EXTI11 SYSCFG_EXTICR3_EXTI11_Msk /*!<EXTI 11 configuration */
17585
17586 /**
17587 * @brief EXTI8 configuration
17588 */
17589 #define SYSCFG_EXTICR3_EXTI8_PA ((uint32_t)0x00000000) /*!<PA[8] pin */
17590 #define SYSCFG_EXTICR3_EXTI8_PB ((uint32_t)0x00000001) /*!<PB[8] pin */
17591 #define SYSCFG_EXTICR3_EXTI8_PC ((uint32_t)0x00000002) /*!<PC[8] pin */
17592 #define SYSCFG_EXTICR3_EXTI8_PD ((uint32_t)0x00000003) /*!<PD[8] pin */
17593 #define SYSCFG_EXTICR3_EXTI8_PE ((uint32_t)0x00000004) /*!<PE[8] pin */
17594 #define SYSCFG_EXTICR3_EXTI8_PF ((uint32_t)0x00000005) /*!<PF[8] pin */
17595 #define SYSCFG_EXTICR3_EXTI8_PG ((uint32_t)0x00000006) /*!<PG[8] pin */
17596 #define SYSCFG_EXTICR3_EXTI8_PH ((uint32_t)0x00000007) /*!<PH[8] pin */
17597 #define SYSCFG_EXTICR3_EXTI8_PI ((uint32_t)0x00000008) /*!<PI[8] pin */
17598 #define SYSCFG_EXTICR3_EXTI8_PJ ((uint32_t)0x00000009) /*!<PJ[8] pin */
17599 #define SYSCFG_EXTICR3_EXTI8_PK ((uint32_t)0x0000000A) /*!<PK[8] pin */
17600
17601 /**
17602 * @brief EXTI9 configuration
17603 */
17604 #define SYSCFG_EXTICR3_EXTI9_PA ((uint32_t)0x00000000) /*!<PA[9] pin */
17605 #define SYSCFG_EXTICR3_EXTI9_PB ((uint32_t)0x00000010) /*!<PB[9] pin */
17606 #define SYSCFG_EXTICR3_EXTI9_PC ((uint32_t)0x00000020) /*!<PC[9] pin */
17607 #define SYSCFG_EXTICR3_EXTI9_PD ((uint32_t)0x00000030) /*!<PD[9] pin */
17608 #define SYSCFG_EXTICR3_EXTI9_PE ((uint32_t)0x00000040) /*!<PE[9] pin */
17609 #define SYSCFG_EXTICR3_EXTI9_PF ((uint32_t)0x00000050) /*!<PF[9] pin */
17610 #define SYSCFG_EXTICR3_EXTI9_PG ((uint32_t)0x00000060) /*!<PG[9] pin */
17611 #define SYSCFG_EXTICR3_EXTI9_PH ((uint32_t)0x00000070) /*!<PH[9] pin */
17612 #define SYSCFG_EXTICR3_EXTI9_PI ((uint32_t)0x00000080) /*!<PI[9] pin */
17613 #define SYSCFG_EXTICR3_EXTI9_PJ ((uint32_t)0x00000090) /*!<PJ[9] pin */
17614 #define SYSCFG_EXTICR3_EXTI9_PK ((uint32_t)0x000000A0) /*!<PK[9] pin */
17615
17616 /**
17617 * @brief EXTI10 configuration
17618 */
17619 #define SYSCFG_EXTICR3_EXTI10_PA ((uint32_t)0x00000000) /*!<PA[10] pin */
17620 #define SYSCFG_EXTICR3_EXTI10_PB ((uint32_t)0x00000100) /*!<PB[10] pin */
17621 #define SYSCFG_EXTICR3_EXTI10_PC ((uint32_t)0x00000200) /*!<PC[10] pin */
17622 #define SYSCFG_EXTICR3_EXTI10_PD ((uint32_t)0x00000300) /*!<PD[10] pin */
17623 #define SYSCFG_EXTICR3_EXTI10_PE ((uint32_t)0x00000400) /*!<PE[10] pin */
17624 #define SYSCFG_EXTICR3_EXTI10_PF ((uint32_t)0x00000500) /*!<PF[10] pin */
17625 #define SYSCFG_EXTICR3_EXTI10_PG ((uint32_t)0x00000600) /*!<PG[10] pin */
17626 #define SYSCFG_EXTICR3_EXTI10_PH ((uint32_t)0x00000700) /*!<PH[10] pin */
17627 #define SYSCFG_EXTICR3_EXTI10_PI ((uint32_t)0x00000800) /*!<PI[10] pin */
17628 #define SYSCFG_EXTICR3_EXTI10_PJ ((uint32_t)0x00000900) /*!<PJ[10] pin */
17629 #define SYSCFG_EXTICR3_EXTI10_PK ((uint32_t)0x00000A00) /*!<PK[10] pin */
17630
17631 /**
17632 * @brief EXTI11 configuration
17633 */
17634 #define SYSCFG_EXTICR3_EXTI11_PA ((uint32_t)0x00000000) /*!<PA[11] pin */
17635 #define SYSCFG_EXTICR3_EXTI11_PB ((uint32_t)0x00001000) /*!<PB[11] pin */
17636 #define SYSCFG_EXTICR3_EXTI11_PC ((uint32_t)0x00002000) /*!<PC[11] pin */
17637 #define SYSCFG_EXTICR3_EXTI11_PD ((uint32_t)0x00003000) /*!<PD[11] pin */
17638 #define SYSCFG_EXTICR3_EXTI11_PE ((uint32_t)0x00004000) /*!<PE[11] pin */
17639 #define SYSCFG_EXTICR3_EXTI11_PF ((uint32_t)0x00005000) /*!<PF[11] pin */
17640 #define SYSCFG_EXTICR3_EXTI11_PG ((uint32_t)0x00006000) /*!<PG[11] pin */
17641 #define SYSCFG_EXTICR3_EXTI11_PH ((uint32_t)0x00007000) /*!<PH[11] pin */
17642 #define SYSCFG_EXTICR3_EXTI11_PI ((uint32_t)0x00008000) /*!<PI[11] pin */
17643 #define SYSCFG_EXTICR3_EXTI11_PJ ((uint32_t)0x00009000) /*!<PJ[11] pin */
17644 #define SYSCFG_EXTICR3_EXTI11_PK ((uint32_t)0x0000A000) /*!<PK[11] pin */
17645
17646 /***************** Bit definition for SYSCFG_EXTICR4 register ***************/
17647 #define SYSCFG_EXTICR4_EXTI12_Pos (0U)
17648 #define SYSCFG_EXTICR4_EXTI12_Msk (0xFUL << SYSCFG_EXTICR4_EXTI12_Pos) /*!< 0x0000000F */
17649 #define SYSCFG_EXTICR4_EXTI12 SYSCFG_EXTICR4_EXTI12_Msk /*!<EXTI 12 configuration */
17650 #define SYSCFG_EXTICR4_EXTI13_Pos (4U)
17651 #define SYSCFG_EXTICR4_EXTI13_Msk (0xFUL << SYSCFG_EXTICR4_EXTI13_Pos) /*!< 0x000000F0 */
17652 #define SYSCFG_EXTICR4_EXTI13 SYSCFG_EXTICR4_EXTI13_Msk /*!<EXTI 13 configuration */
17653 #define SYSCFG_EXTICR4_EXTI14_Pos (8U)
17654 #define SYSCFG_EXTICR4_EXTI14_Msk (0xFUL << SYSCFG_EXTICR4_EXTI14_Pos) /*!< 0x00000F00 */
17655 #define SYSCFG_EXTICR4_EXTI14 SYSCFG_EXTICR4_EXTI14_Msk /*!<EXTI 14 configuration */
17656 #define SYSCFG_EXTICR4_EXTI15_Pos (12U)
17657 #define SYSCFG_EXTICR4_EXTI15_Msk (0xFUL << SYSCFG_EXTICR4_EXTI15_Pos) /*!< 0x0000F000 */
17658 #define SYSCFG_EXTICR4_EXTI15 SYSCFG_EXTICR4_EXTI15_Msk /*!<EXTI 15 configuration */
17659 /**
17660 * @brief EXTI12 configuration
17661 */
17662 #define SYSCFG_EXTICR4_EXTI12_PA ((uint32_t)0x00000000) /*!<PA[12] pin */
17663 #define SYSCFG_EXTICR4_EXTI12_PB ((uint32_t)0x00000001) /*!<PB[12] pin */
17664 #define SYSCFG_EXTICR4_EXTI12_PC ((uint32_t)0x00000002) /*!<PC[12] pin */
17665 #define SYSCFG_EXTICR4_EXTI12_PD ((uint32_t)0x00000003) /*!<PD[12] pin */
17666 #define SYSCFG_EXTICR4_EXTI12_PE ((uint32_t)0x00000004) /*!<PE[12] pin */
17667 #define SYSCFG_EXTICR4_EXTI12_PF ((uint32_t)0x00000005) /*!<PF[12] pin */
17668 #define SYSCFG_EXTICR4_EXTI12_PG ((uint32_t)0x00000006) /*!<PG[12] pin */
17669 #define SYSCFG_EXTICR4_EXTI12_PH ((uint32_t)0x00000007) /*!<PH[12] pin */
17670 #define SYSCFG_EXTICR4_EXTI12_PI ((uint32_t)0x00000008) /*!<PI[12] pin */
17671 #define SYSCFG_EXTICR4_EXTI12_PJ ((uint32_t)0x00000009) /*!<PJ[12] pin */
17672 #define SYSCFG_EXTICR4_EXTI12_PK ((uint32_t)0x0000000A) /*!<PK[12] pin */
17673 /**
17674 * @brief EXTI13 configuration
17675 */
17676 #define SYSCFG_EXTICR4_EXTI13_PA ((uint32_t)0x00000000) /*!<PA[13] pin */
17677 #define SYSCFG_EXTICR4_EXTI13_PB ((uint32_t)0x00000010) /*!<PB[13] pin */
17678 #define SYSCFG_EXTICR4_EXTI13_PC ((uint32_t)0x00000020) /*!<PC[13] pin */
17679 #define SYSCFG_EXTICR4_EXTI13_PD ((uint32_t)0x00000030) /*!<PD[13] pin */
17680 #define SYSCFG_EXTICR4_EXTI13_PE ((uint32_t)0x00000040) /*!<PE[13] pin */
17681 #define SYSCFG_EXTICR4_EXTI13_PF ((uint32_t)0x00000050) /*!<PF[13] pin */
17682 #define SYSCFG_EXTICR4_EXTI13_PG ((uint32_t)0x00000060) /*!<PG[13] pin */
17683 #define SYSCFG_EXTICR4_EXTI13_PH ((uint32_t)0x00000070) /*!<PH[13] pin */
17684 #define SYSCFG_EXTICR4_EXTI13_PI ((uint32_t)0x00000080) /*!<PI[13] pin */
17685 #define SYSCFG_EXTICR4_EXTI13_PJ ((uint32_t)0x00000090) /*!<PJ[13] pin */
17686 #define SYSCFG_EXTICR4_EXTI13_PK ((uint32_t)0x000000A0) /*!<PK[13] pin */
17687 /**
17688 * @brief EXTI14 configuration
17689 */
17690 #define SYSCFG_EXTICR4_EXTI14_PA ((uint32_t)0x00000000) /*!<PA[14] pin */
17691 #define SYSCFG_EXTICR4_EXTI14_PB ((uint32_t)0x00000100) /*!<PB[14] pin */
17692 #define SYSCFG_EXTICR4_EXTI14_PC ((uint32_t)0x00000200) /*!<PC[14] pin */
17693 #define SYSCFG_EXTICR4_EXTI14_PD ((uint32_t)0x00000300) /*!<PD[14] pin */
17694 #define SYSCFG_EXTICR4_EXTI14_PE ((uint32_t)0x00000400) /*!<PE[14] pin */
17695 #define SYSCFG_EXTICR4_EXTI14_PF ((uint32_t)0x00000500) /*!<PF[14] pin */
17696 #define SYSCFG_EXTICR4_EXTI14_PG ((uint32_t)0x00000600) /*!<PG[14] pin */
17697 #define SYSCFG_EXTICR4_EXTI14_PH ((uint32_t)0x00000700) /*!<PH[14] pin */
17698 #define SYSCFG_EXTICR4_EXTI14_PI ((uint32_t)0x00000800) /*!<PI[14] pin */
17699 #define SYSCFG_EXTICR4_EXTI14_PJ ((uint32_t)0x00000900) /*!<PJ[14] pin */
17700 #define SYSCFG_EXTICR4_EXTI14_PK ((uint32_t)0x00000A00) /*!<PK[14] pin */
17701 /**
17702 * @brief EXTI15 configuration
17703 */
17704 #define SYSCFG_EXTICR4_EXTI15_PA ((uint32_t)0x00000000) /*!<PA[15] pin */
17705 #define SYSCFG_EXTICR4_EXTI15_PB ((uint32_t)0x00001000) /*!<PB[15] pin */
17706 #define SYSCFG_EXTICR4_EXTI15_PC ((uint32_t)0x00002000) /*!<PC[15] pin */
17707 #define SYSCFG_EXTICR4_EXTI15_PD ((uint32_t)0x00003000) /*!<PD[15] pin */
17708 #define SYSCFG_EXTICR4_EXTI15_PE ((uint32_t)0x00004000) /*!<PE[15] pin */
17709 #define SYSCFG_EXTICR4_EXTI15_PF ((uint32_t)0x00005000) /*!<PF[15] pin */
17710 #define SYSCFG_EXTICR4_EXTI15_PG ((uint32_t)0x00006000) /*!<PG[15] pin */
17711 #define SYSCFG_EXTICR4_EXTI15_PH ((uint32_t)0x00007000) /*!<PH[15] pin */
17712 #define SYSCFG_EXTICR4_EXTI15_PI ((uint32_t)0x00008000) /*!<PI[15] pin */
17713 #define SYSCFG_EXTICR4_EXTI15_PJ ((uint32_t)0x00009000) /*!<PJ[15] pin */
17714 #define SYSCFG_EXTICR4_EXTI15_PK ((uint32_t)0x0000A000) /*!<PK[15] pin */
17715
17716 /****************** Bit definition for SYSCFG_CFGR register ******************/
17717 #define SYSCFG_CFGR_PVDL_Pos (2U)
17718 #define SYSCFG_CFGR_PVDL_Msk (0x1UL << SYSCFG_CFGR_PVDL_Pos) /*!< 0x00000004 */
17719 #define SYSCFG_CFGR_PVDL SYSCFG_CFGR_PVDL_Msk /*!<PVD lock enable bit */
17720 #define SYSCFG_CFGR_FLASHL_Pos (3U)
17721 #define SYSCFG_CFGR_FLASHL_Msk (0x1UL << SYSCFG_CFGR_FLASHL_Pos) /*!< 0x00000008 */
17722 #define SYSCFG_CFGR_FLASHL SYSCFG_CFGR_FLASHL_Msk /*!<FLASH double ECC error lock bit */
17723 #define SYSCFG_CFGR_CM7L_Pos (6U)
17724 #define SYSCFG_CFGR_CM7L_Msk (0x1UL << SYSCFG_CFGR_CM7L_Pos) /*!< 0x00000040 */
17725 #define SYSCFG_CFGR_CM7L SYSCFG_CFGR_CM7L_Msk /*!<Cortex-M7 LOCKUP (Hardfault) output enable bit */
17726 #define SYSCFG_CFGR_DTCML_Pos (13U)
17727 #define SYSCFG_CFGR_DTCML_Msk (0x1UL << SYSCFG_CFGR_DTCML_Pos) /*!< 0x00002000 */
17728 #define SYSCFG_CFGR_DTCML SYSCFG_CFGR_DTCML_Msk /*!<DTCM double ECC error lock bit */
17729 #define SYSCFG_CFGR_ITCML_Pos (14U)
17730 #define SYSCFG_CFGR_ITCML_Msk (0x1UL << SYSCFG_CFGR_ITCML_Pos) /*!< 0x00004000 */
17731 #define SYSCFG_CFGR_ITCML SYSCFG_CFGR_ITCML_Msk /*!<ITCM double ECC error lock bit */
17732 /****************** Bit definition for SYSCFG_CCCSR register ******************/
17733 #define SYSCFG_CCCSR_EN_Pos (0U)
17734 #define SYSCFG_CCCSR_EN_Msk (0x1UL << SYSCFG_CCCSR_EN_Pos) /*!< 0x00000001 */
17735 #define SYSCFG_CCCSR_EN SYSCFG_CCCSR_EN_Msk /*!< I/O compensation cell enable */
17736 #define SYSCFG_CCCSR_CS_Pos (1U)
17737 #define SYSCFG_CCCSR_CS_Msk (0x1UL << SYSCFG_CCCSR_CS_Pos) /*!< 0x00000002 */
17738 #define SYSCFG_CCCSR_CS SYSCFG_CCCSR_CS_Msk /*!< I/O compensation cell code selection */
17739 #define SYSCFG_CCCSR_CS_MMC_Pos (3U)
17740 #define SYSCFG_CCCSR_CS_MMC_Msk (0x1UL << SYSCFG_CCCSR_CS_MMC_Pos) /*!< 0x00000004 */
17741 #define SYSCFG_CCCSR_CS_MMC SYSCFG_CCCSR_CS_MMC_Msk /*!< I/O compensation cell code selection */
17742 #define SYSCFG_CCCSR_READY_Pos (8U)
17743 #define SYSCFG_CCCSR_READY_Msk (0x1UL << SYSCFG_CCCSR_READY_Pos) /*!< 0x00000100 */
17744 #define SYSCFG_CCCSR_READY SYSCFG_CCCSR_READY_Msk /*!< I/O compensation cell ready flag */
17745 #define SYSCFG_CCCSR_HSLV0_Pos (16U)
17746 #define SYSCFG_CCCSR_HSLV0_Msk (0x1UL << SYSCFG_CCCSR_HSLV0_Pos) /*!< 0x00010000 */
17747 #define SYSCFG_CCCSR_HSLV0 SYSCFG_CCCSR_HSLV0_Msk /*!< High-speed at low-voltage */
17748 #define SYSCFG_CCCSR_HSLV1_Pos (17U)
17749 #define SYSCFG_CCCSR_HSLV1_Msk (0x1UL << SYSCFG_CCCSR_HSLV1_Pos) /*!< 0x00020000 */
17750 #define SYSCFG_CCCSR_HSLV1 SYSCFG_CCCSR_HSLV1_Msk /*!< High-speed at low-voltage */
17751 #define SYSCFG_CCCSR_HSLV2_Pos (18U)
17752 #define SYSCFG_CCCSR_HSLV2_Msk (0x1UL << SYSCFG_CCCSR_HSLV2_Pos) /*!< 0x00040000 */
17753 #define SYSCFG_CCCSR_HSLV2 SYSCFG_CCCSR_HSLV2_Msk /*!< High-speed at low-voltage */
17754 #define SYSCFG_CCCSR_HSLV3_Pos (19U)
17755 #define SYSCFG_CCCSR_HSLV3_Msk (0x1UL << SYSCFG_CCCSR_HSLV3_Pos) /*!< 0x00080000 */
17756 #define SYSCFG_CCCSR_HSLV3 SYSCFG_CCCSR_HSLV3_Msk /*!< High-speed at low-voltage */
17757 /****************** Bit definition for SYSCFG_CCVR register *******************/
17758 #define SYSCFG_CCVR_NCV_Pos (0U)
17759 #define SYSCFG_CCVR_NCV_Msk (0xFUL << SYSCFG_CCVR_NCV_Pos) /*!< 0x0000000F */
17760 #define SYSCFG_CCVR_NCV SYSCFG_CCVR_NCV_Msk /*!< NMOS compensation value */
17761 #define SYSCFG_CCVR_PCV_Pos (4U)
17762 #define SYSCFG_CCVR_PCV_Msk (0xFUL << SYSCFG_CCVR_PCV_Pos) /*!< 0x000000F0 */
17763 #define SYSCFG_CCVR_PCV SYSCFG_CCVR_PCV_Msk /*!< PMOS compensation value */
17764
17765 /****************** Bit definition for SYSCFG_CCCR register *******************/
17766 #define SYSCFG_CCCR_NCC_Pos (0U)
17767 #define SYSCFG_CCCR_NCC_Msk (0xFUL << SYSCFG_CCCR_NCC_Pos) /*!< 0x0000000F */
17768 #define SYSCFG_CCCR_NCC SYSCFG_CCCR_NCC_Msk /*!< NMOS compensation code */
17769 #define SYSCFG_CCCR_PCC_Pos (4U)
17770 #define SYSCFG_CCCR_PCC_Msk (0xFUL << SYSCFG_CCCR_PCC_Pos) /*!< 0x000000F0 */
17771 #define SYSCFG_CCCR_PCC SYSCFG_CCCR_PCC_Msk /*!< PMOS compensation code */
17772 #define SYSCFG_CCCR_NCC_MMC_Pos (8U)
17773 #define SYSCFG_CCCR_NCC_MMC_Msk (0xFUL << SYSCFG_CCCR_NCC_MMC_Pos) /*!< 0x00000F00 */
17774 #define SYSCFG_CCCR_NCC_MMC SYSCFG_CCCR_NCC_MMC_Msk /*!< NMOS compensation code */
17775 #define SYSCFG_CCCR_PCC_MMC_Pos (12U)
17776 #define SYSCFG_CCCR_PCC_MMC_Msk (0xFUL << SYSCFG_CCCR_PCC_MMC_Pos) /*!< 0x0000F000 */
17777 #define SYSCFG_CCCR_PCC_MMC SYSCFG_CCCR_PCC_MMC_Msk /*!< PMOS compensation code */
17778 /******************************************************************************/
17779 /* */
17780 /* Digital Temperature Sensor (DTS) */
17781 /* */
17782 /******************************************************************************/
17783
17784 /****************** Bit definition for DTS_CFGR1 register ******************/
17785 #define DTS_CFGR1_TS1_EN_Pos (0U)
17786 #define DTS_CFGR1_TS1_EN_Msk (0x1UL << DTS_CFGR1_TS1_EN_Pos) /*!< 0x00000001 */
17787 #define DTS_CFGR1_TS1_EN DTS_CFGR1_TS1_EN_Msk /*!< DTS Enable */
17788 #define DTS_CFGR1_TS1_START_Pos (4U)
17789 #define DTS_CFGR1_TS1_START_Msk (0x1UL << DTS_CFGR1_TS1_START_Pos) /*!< 0x00000010 */
17790 #define DTS_CFGR1_TS1_START DTS_CFGR1_TS1_START_Msk /*!< Proceed to a frequency measurement on DTS */
17791 #define DTS_CFGR1_TS1_INTRIG_SEL_Pos (8U)
17792 #define DTS_CFGR1_TS1_INTRIG_SEL_Msk (0xFUL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000F00 */
17793 #define DTS_CFGR1_TS1_INTRIG_SEL DTS_CFGR1_TS1_INTRIG_SEL_Msk /*!< Input triggers selection bits [3:0] for DTS */
17794 #define DTS_CFGR1_TS1_INTRIG_SEL_0 (0x1UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000100 */
17795 #define DTS_CFGR1_TS1_INTRIG_SEL_1 (0x2UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000200 */
17796 #define DTS_CFGR1_TS1_INTRIG_SEL_2 (0x4UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000400 */
17797 #define DTS_CFGR1_TS1_INTRIG_SEL_3 (0x8UL << DTS_CFGR1_TS1_INTRIG_SEL_Pos) /*!< 0x00000800 */
17798 #define DTS_CFGR1_TS1_SMP_TIME_Pos (16U)
17799 #define DTS_CFGR1_TS1_SMP_TIME_Msk (0xFUL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x000F0000 */
17800 #define DTS_CFGR1_TS1_SMP_TIME DTS_CFGR1_TS1_SMP_TIME_Msk /*!< Sample time [3:0] for DTS */
17801 #define DTS_CFGR1_TS1_SMP_TIME_0 (0x1UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00010000 */
17802 #define DTS_CFGR1_TS1_SMP_TIME_1 (0x2UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00020000 */
17803 #define DTS_CFGR1_TS1_SMP_TIME_2 (0x4UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00040000 */
17804 #define DTS_CFGR1_TS1_SMP_TIME_3 (0x8UL << DTS_CFGR1_TS1_SMP_TIME_Pos) /*!< 0x00080000 */
17805 #define DTS_CFGR1_REFCLK_SEL_Pos (20U)
17806 #define DTS_CFGR1_REFCLK_SEL_Msk (0x1UL << DTS_CFGR1_REFCLK_SEL_Pos) /*!< 0x00100000 */
17807 #define DTS_CFGR1_REFCLK_SEL DTS_CFGR1_REFCLK_SEL_Msk /*!< Reference Clock Selection */
17808 #define DTS_CFGR1_Q_MEAS_OPT_Pos (21U)
17809 #define DTS_CFGR1_Q_MEAS_OPT_Msk (0x1UL << DTS_CFGR1_Q_MEAS_OPT_Pos) /*!< 0x00200000 */
17810 #define DTS_CFGR1_Q_MEAS_OPT DTS_CFGR1_Q_MEAS_OPT_Msk /*!< Quick measure option bit */
17811 #define DTS_CFGR1_HSREF_CLK_DIV_Pos (24U)
17812 #define DTS_CFGR1_HSREF_CLK_DIV_Msk (0x7FUL << DTS_CFGR1_HSREF_CLK_DIV_Pos) /*!< 0x7F000000 */
17813 #define DTS_CFGR1_HSREF_CLK_DIV DTS_CFGR1_HSREF_CLK_DIV_Msk /*!< High Speed Clock Divider Ratio [6:0]*/
17814
17815 /****************** Bit definition for DTS_T0VALR1 register ******************/
17816 #define DTS_T0VALR1_TS1_FMT0_Pos (0U)
17817 #define DTS_T0VALR1_TS1_FMT0_Msk (0xFFFFUL << DTS_T0VALR1_TS1_FMT0_Pos) /*!< 0x0000FFFF */
17818 #define DTS_T0VALR1_TS1_FMT0 DTS_T0VALR1_TS1_FMT0_Msk /*!< Engineering value of the measured frequency at T0 for DTS */
17819 #define DTS_T0VALR1_TS1_T0_Pos (16U)
17820 #define DTS_T0VALR1_TS1_T0_Msk (0x3UL << DTS_T0VALR1_TS1_T0_Pos) /*!< 0x00030000 */
17821 #define DTS_T0VALR1_TS1_T0 DTS_T0VALR1_TS1_T0_Msk /*!< Engineering value of the DTSerature T0 for DTS */
17822
17823 /****************** Bit definition for DTS_RAMPVALR register ******************/
17824 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Pos (0U)
17825 #define DTS_RAMPVALR_TS1_RAMP_COEFF_Msk (0xFFFFUL << DTS_RAMPVALR_TS1_RAMP_COEFF_Pos) /*!< 0x0000FFFF */
17826 #define DTS_RAMPVALR_TS1_RAMP_COEFF DTS_RAMPVALR_TS1_RAMP_COEFF_Msk /*!< Engineering value of the ramp coefficient for DTS */
17827
17828 /****************** Bit definition for DTS_ITR1 register ******************/
17829 #define DTS_ITR1_TS1_LITTHD_Pos (0U)
17830 #define DTS_ITR1_TS1_LITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_LITTHD_Pos) /*!< 0x0000FFFF */
17831 #define DTS_ITR1_TS1_LITTHD DTS_ITR1_TS1_LITTHD_Msk /*!< Low interrupt threshold[15:0] for DTS */
17832 #define DTS_ITR1_TS1_HITTHD_Pos (16U)
17833 #define DTS_ITR1_TS1_HITTHD_Msk (0xFFFFUL << DTS_ITR1_TS1_HITTHD_Pos) /*!< 0xFFFF0000 */
17834 #define DTS_ITR1_TS1_HITTHD DTS_ITR1_TS1_HITTHD_Msk /*!< High interrupt threshold[15:0] for DTS */
17835
17836 /****************** Bit definition for DTS_DR register ******************/
17837 #define DTS_DR_TS1_MFREQ_Pos (0U)
17838 #define DTS_DR_TS1_MFREQ_Msk (0xFFFFUL << DTS_DR_TS1_MFREQ_Pos) /*!< 0x0000FFFF */
17839 #define DTS_DR_TS1_MFREQ DTS_DR_TS1_MFREQ_Msk /*!< Measured Frequency[15:0] for DTS */
17840
17841 /****************** Bit definition for DTS_SR register ******************/
17842 #define DTS_SR_TS1_ITEF_Pos (0U)
17843 #define DTS_SR_TS1_ITEF_Msk (0x1UL << DTS_SR_TS1_ITEF_Pos) /*!< 0x00000001 */
17844 #define DTS_SR_TS1_ITEF DTS_SR_TS1_ITEF_Msk /*!< Interrupt flag for end of measure for DTS */
17845 #define DTS_SR_TS1_ITLF_Pos (1U)
17846 #define DTS_SR_TS1_ITLF_Msk (0x1UL << DTS_SR_TS1_ITLF_Pos) /*!< 0x00000002 */
17847 #define DTS_SR_TS1_ITLF DTS_SR_TS1_ITLF_Msk /*!< Interrupt flag for low threshold for DTS */
17848 #define DTS_SR_TS1_ITHF_Pos (2U)
17849 #define DTS_SR_TS1_ITHF_Msk (0x1UL << DTS_SR_TS1_ITHF_Pos) /*!< 0x00000004 */
17850 #define DTS_SR_TS1_ITHF DTS_SR_TS1_ITHF_Msk /*!< Interrupt flag for high threshold for DTS */
17851 #define DTS_SR_TS1_AITEF_Pos (4U)
17852 #define DTS_SR_TS1_AITEF_Msk (0x1UL << DTS_SR_TS1_AITEF_Pos) /*!< 0x00000010 */
17853 #define DTS_SR_TS1_AITEF DTS_SR_TS1_AITEF_Msk /*!< Asynchronous interrupt flag for end of measure for DTS */
17854 #define DTS_SR_TS1_AITLF_Pos (5U)
17855 #define DTS_SR_TS1_AITLF_Msk (0x1UL << DTS_SR_TS1_AITLF_Pos) /*!< 0x00000020 */
17856 #define DTS_SR_TS1_AITLF DTS_SR_TS1_AITLF_Msk /*!< Asynchronous interrupt flag for low threshold for DTS */
17857 #define DTS_SR_TS1_AITHF_Pos (6U)
17858 #define DTS_SR_TS1_AITHF_Msk (0x1UL << DTS_SR_TS1_AITHF_Pos) /*!< 0x00000040 */
17859 #define DTS_SR_TS1_AITHF DTS_SR_TS1_AITHF_Msk /*!< Asynchronous interrupt flag for high threshold for DTS */
17860 #define DTS_SR_TS1_RDY_Pos (15U)
17861 #define DTS_SR_TS1_RDY_Msk (0x1UL << DTS_SR_TS1_RDY_Pos) /*!< 0x00008000 */
17862 #define DTS_SR_TS1_RDY DTS_SR_TS1_RDY_Msk /*!< DTS ready flag */
17863
17864 /****************** Bit definition for DTS_ITENR register ******************/
17865 #define DTS_ITENR_TS1_ITEEN_Pos (0U)
17866 #define DTS_ITENR_TS1_ITEEN_Msk (0x1UL << DTS_ITENR_TS1_ITEEN_Pos) /*!< 0x00000001 */
17867 #define DTS_ITENR_TS1_ITEEN DTS_ITENR_TS1_ITEEN_Msk /*!< Enable interrupt flag for end of measure for DTS */
17868 #define DTS_ITENR_TS1_ITLEN_Pos (1U)
17869 #define DTS_ITENR_TS1_ITLEN_Msk (0x1UL << DTS_ITENR_TS1_ITLEN_Pos) /*!< 0x00000002 */
17870 #define DTS_ITENR_TS1_ITLEN DTS_ITENR_TS1_ITLEN_Msk /*!< Enable interrupt flag for low threshold for DTS */
17871 #define DTS_ITENR_TS1_ITHEN_Pos (2U)
17872 #define DTS_ITENR_TS1_ITHEN_Msk (0x1UL << DTS_ITENR_TS1_ITHEN_Pos) /*!< 0x00000004 */
17873 #define DTS_ITENR_TS1_ITHEN DTS_ITENR_TS1_ITHEN_Msk /*!< Enable interrupt flag for high threshold for DTS */
17874 #define DTS_ITENR_TS1_AITEEN_Pos (4U)
17875 #define DTS_ITENR_TS1_AITEEN_Msk (0x1UL << DTS_ITENR_TS1_AITEEN_Pos) /*!< 0x00000010 */
17876 #define DTS_ITENR_TS1_AITEEN DTS_ITENR_TS1_AITEEN_Msk /*!< Enable asynchronous interrupt flag for end of measure for DTS */
17877 #define DTS_ITENR_TS1_AITLEN_Pos (5U)
17878 #define DTS_ITENR_TS1_AITLEN_Msk (0x1UL << DTS_ITENR_TS1_AITLEN_Pos) /*!< 0x00000020 */
17879 #define DTS_ITENR_TS1_AITLEN DTS_ITENR_TS1_AITLEN_Msk /*!< Enable Asynchronous interrupt flag for low threshold for DTS */
17880 #define DTS_ITENR_TS1_AITHEN_Pos (6U)
17881 #define DTS_ITENR_TS1_AITHEN_Msk (0x1UL << DTS_ITENR_TS1_AITHEN_Pos) /*!< 0x00000040 */
17882 #define DTS_ITENR_TS1_AITHEN DTS_ITENR_TS1_AITHEN_Msk /*!< Enable asynchronous interrupt flag for high threshold for DTS */
17883
17884 /****************** Bit definition for DTS_ICIFR register ******************/
17885 #define DTS_ICIFR_TS1_CITEF_Pos (0U)
17886 #define DTS_ICIFR_TS1_CITEF_Msk (0x1UL << DTS_ICIFR_TS1_CITEF_Pos) /*!< 0x00000001 */
17887 #define DTS_ICIFR_TS1_CITEF DTS_ICIFR_TS1_CITEF_Msk /*!< Clear the IT flag for End Of Measure for DTS */
17888 #define DTS_ICIFR_TS1_CITLF_Pos (1U)
17889 #define DTS_ICIFR_TS1_CITLF_Msk (0x1UL << DTS_ICIFR_TS1_CITLF_Pos) /*!< 0x00000002 */
17890 #define DTS_ICIFR_TS1_CITLF DTS_ICIFR_TS1_CITLF_Msk /*!< Clear the IT flag for low threshold for DTS */
17891 #define DTS_ICIFR_TS1_CITHF_Pos (2U)
17892 #define DTS_ICIFR_TS1_CITHF_Msk (0x1UL << DTS_ICIFR_TS1_CITHF_Pos) /*!< 0x00000004 */
17893 #define DTS_ICIFR_TS1_CITHF DTS_ICIFR_TS1_CITHF_Msk /*!< Clear the IT flag for high threshold on DTS */
17894 #define DTS_ICIFR_TS1_CAITEF_Pos (4U)
17895 #define DTS_ICIFR_TS1_CAITEF_Msk (0x1UL << DTS_ICIFR_TS1_CAITEF_Pos) /*!< 0x00000010 */
17896 #define DTS_ICIFR_TS1_CAITEF DTS_ICIFR_TS1_CAITEF_Msk /*!< Clear the asynchronous IT flag for End Of Measure for DTS */
17897 #define DTS_ICIFR_TS1_CAITLF_Pos (5U)
17898 #define DTS_ICIFR_TS1_CAITLF_Msk (0x1UL << DTS_ICIFR_TS1_CAITLF_Pos) /*!< 0x00000020 */
17899 #define DTS_ICIFR_TS1_CAITLF DTS_ICIFR_TS1_CAITLF_Msk /*!< Clear the asynchronous IT flag for low threshold for DTS */
17900 #define DTS_ICIFR_TS1_CAITHF_Pos (6U)
17901 #define DTS_ICIFR_TS1_CAITHF_Msk (0x1UL << DTS_ICIFR_TS1_CAITHF_Pos) /*!< 0x00000040 */
17902 #define DTS_ICIFR_TS1_CAITHF DTS_ICIFR_TS1_CAITHF_Msk /*!< Clear the asynchronous IT flag for high threshold on DTS */
17903
17904
17905 /******************************************************************************/
17906 /* */
17907 /* TIM */
17908 /* */
17909 /******************************************************************************/
17910 #define TIM_BREAK_INPUT_SUPPORT /*!<TIM Break input feature */
17911
17912 /******************* Bit definition for TIM_CR1 register ********************/
17913 #define TIM_CR1_CEN_Pos (0U)
17914 #define TIM_CR1_CEN_Msk (0x1UL << TIM_CR1_CEN_Pos) /*!< 0x00000001 */
17915 #define TIM_CR1_CEN TIM_CR1_CEN_Msk /*!<Counter enable */
17916 #define TIM_CR1_UDIS_Pos (1U)
17917 #define TIM_CR1_UDIS_Msk (0x1UL << TIM_CR1_UDIS_Pos) /*!< 0x00000002 */
17918 #define TIM_CR1_UDIS TIM_CR1_UDIS_Msk /*!<Update disable */
17919 #define TIM_CR1_URS_Pos (2U)
17920 #define TIM_CR1_URS_Msk (0x1UL << TIM_CR1_URS_Pos) /*!< 0x00000004 */
17921 #define TIM_CR1_URS TIM_CR1_URS_Msk /*!<Update request source */
17922 #define TIM_CR1_OPM_Pos (3U)
17923 #define TIM_CR1_OPM_Msk (0x1UL << TIM_CR1_OPM_Pos) /*!< 0x00000008 */
17924 #define TIM_CR1_OPM TIM_CR1_OPM_Msk /*!<One pulse mode */
17925 #define TIM_CR1_DIR_Pos (4U)
17926 #define TIM_CR1_DIR_Msk (0x1UL << TIM_CR1_DIR_Pos) /*!< 0x00000010 */
17927 #define TIM_CR1_DIR TIM_CR1_DIR_Msk /*!<Direction */
17928
17929 #define TIM_CR1_CMS_Pos (5U)
17930 #define TIM_CR1_CMS_Msk (0x3UL << TIM_CR1_CMS_Pos) /*!< 0x00000060 */
17931 #define TIM_CR1_CMS TIM_CR1_CMS_Msk /*!<CMS[1:0] bits (Center-aligned mode selection) */
17932 #define TIM_CR1_CMS_0 (0x1UL << TIM_CR1_CMS_Pos) /*!< 0x00000020 */
17933 #define TIM_CR1_CMS_1 (0x2UL << TIM_CR1_CMS_Pos) /*!< 0x00000040 */
17934
17935 #define TIM_CR1_ARPE_Pos (7U)
17936 #define TIM_CR1_ARPE_Msk (0x1UL << TIM_CR1_ARPE_Pos) /*!< 0x00000080 */
17937 #define TIM_CR1_ARPE TIM_CR1_ARPE_Msk /*!<Auto-reload preload enable */
17938
17939 #define TIM_CR1_CKD_Pos (8U)
17940 #define TIM_CR1_CKD_Msk (0x3UL << TIM_CR1_CKD_Pos) /*!< 0x00000300 */
17941 #define TIM_CR1_CKD TIM_CR1_CKD_Msk /*!<CKD[1:0] bits (clock division) */
17942 #define TIM_CR1_CKD_0 (0x1UL << TIM_CR1_CKD_Pos) /*!< 0x00000100 */
17943 #define TIM_CR1_CKD_1 (0x2UL << TIM_CR1_CKD_Pos) /*!< 0x00000200 */
17944
17945 #define TIM_CR1_UIFREMAP_Pos (11U)
17946 #define TIM_CR1_UIFREMAP_Msk (0x1UL << TIM_CR1_UIFREMAP_Pos) /*!< 0x00000800 */
17947 #define TIM_CR1_UIFREMAP TIM_CR1_UIFREMAP_Msk /*!<Update interrupt flag remap */
17948
17949 /******************* Bit definition for TIM_CR2 register ********************/
17950 #define TIM_CR2_CCPC_Pos (0U)
17951 #define TIM_CR2_CCPC_Msk (0x1UL << TIM_CR2_CCPC_Pos) /*!< 0x00000001 */
17952 #define TIM_CR2_CCPC TIM_CR2_CCPC_Msk /*!<Capture/Compare Preloaded Control */
17953 #define TIM_CR2_CCUS_Pos (2U)
17954 #define TIM_CR2_CCUS_Msk (0x1UL << TIM_CR2_CCUS_Pos) /*!< 0x00000004 */
17955 #define TIM_CR2_CCUS TIM_CR2_CCUS_Msk /*!<Capture/Compare Control Update Selection */
17956 #define TIM_CR2_CCDS_Pos (3U)
17957 #define TIM_CR2_CCDS_Msk (0x1UL << TIM_CR2_CCDS_Pos) /*!< 0x00000008 */
17958 #define TIM_CR2_CCDS TIM_CR2_CCDS_Msk /*!<Capture/Compare DMA Selection */
17959
17960 #define TIM_CR2_MMS_Pos (4U)
17961 #define TIM_CR2_MMS_Msk (0x7UL << TIM_CR2_MMS_Pos) /*!< 0x00000070 */
17962 #define TIM_CR2_MMS TIM_CR2_MMS_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
17963 #define TIM_CR2_MMS_0 (0x1UL << TIM_CR2_MMS_Pos) /*!< 0x00000010 */
17964 #define TIM_CR2_MMS_1 (0x2UL << TIM_CR2_MMS_Pos) /*!< 0x00000020 */
17965 #define TIM_CR2_MMS_2 (0x4UL << TIM_CR2_MMS_Pos) /*!< 0x00000040 */
17966
17967 #define TIM_CR2_TI1S_Pos (7U)
17968 #define TIM_CR2_TI1S_Msk (0x1UL << TIM_CR2_TI1S_Pos) /*!< 0x00000080 */
17969 #define TIM_CR2_TI1S TIM_CR2_TI1S_Msk /*!<TI1 Selection */
17970 #define TIM_CR2_OIS1_Pos (8U)
17971 #define TIM_CR2_OIS1_Msk (0x1UL << TIM_CR2_OIS1_Pos) /*!< 0x00000100 */
17972 #define TIM_CR2_OIS1 TIM_CR2_OIS1_Msk /*!<Output Idle state 1 (OC1 output) */
17973 #define TIM_CR2_OIS1N_Pos (9U)
17974 #define TIM_CR2_OIS1N_Msk (0x1UL << TIM_CR2_OIS1N_Pos) /*!< 0x00000200 */
17975 #define TIM_CR2_OIS1N TIM_CR2_OIS1N_Msk /*!<Output Idle state 1 (OC1N output) */
17976 #define TIM_CR2_OIS2_Pos (10U)
17977 #define TIM_CR2_OIS2_Msk (0x1UL << TIM_CR2_OIS2_Pos) /*!< 0x00000400 */
17978 #define TIM_CR2_OIS2 TIM_CR2_OIS2_Msk /*!<Output Idle state 2 (OC2 output) */
17979 #define TIM_CR2_OIS2N_Pos (11U)
17980 #define TIM_CR2_OIS2N_Msk (0x1UL << TIM_CR2_OIS2N_Pos) /*!< 0x00000800 */
17981 #define TIM_CR2_OIS2N TIM_CR2_OIS2N_Msk /*!<Output Idle state 2 (OC2N output) */
17982 #define TIM_CR2_OIS3_Pos (12U)
17983 #define TIM_CR2_OIS3_Msk (0x1UL << TIM_CR2_OIS3_Pos) /*!< 0x00001000 */
17984 #define TIM_CR2_OIS3 TIM_CR2_OIS3_Msk /*!<Output Idle state 3 (OC3 output) */
17985 #define TIM_CR2_OIS3N_Pos (13U)
17986 #define TIM_CR2_OIS3N_Msk (0x1UL << TIM_CR2_OIS3N_Pos) /*!< 0x00002000 */
17987 #define TIM_CR2_OIS3N TIM_CR2_OIS3N_Msk /*!<Output Idle state 3 (OC3N output) */
17988 #define TIM_CR2_OIS4_Pos (14U)
17989 #define TIM_CR2_OIS4_Msk (0x1UL << TIM_CR2_OIS4_Pos) /*!< 0x00004000 */
17990 #define TIM_CR2_OIS4 TIM_CR2_OIS4_Msk /*!<Output Idle state 4 (OC4 output) */
17991 #define TIM_CR2_OIS5_Pos (16U)
17992 #define TIM_CR2_OIS5_Msk (0x1UL << TIM_CR2_OIS5_Pos) /*!< 0x00010000 */
17993 #define TIM_CR2_OIS5 TIM_CR2_OIS5_Msk /*!<Output Idle state 4 (OC4 output) */
17994 #define TIM_CR2_OIS6_Pos (17U)
17995 #define TIM_CR2_OIS6_Msk (0x1UL << TIM_CR2_OIS6_Pos) /*!< 0x00020000 */
17996 #define TIM_CR2_OIS6 TIM_CR2_OIS6_Msk /*!<Output Idle state 4 (OC4 output) */
17997
17998 #define TIM_CR2_MMS2_Pos (20U)
17999 #define TIM_CR2_MMS2_Msk (0xFUL << TIM_CR2_MMS2_Pos) /*!< 0x00F00000 */
18000 #define TIM_CR2_MMS2 TIM_CR2_MMS2_Msk /*!<MMS[2:0] bits (Master Mode Selection) */
18001 #define TIM_CR2_MMS2_0 (0x1UL << TIM_CR2_MMS2_Pos) /*!< 0x00100000 */
18002 #define TIM_CR2_MMS2_1 (0x2UL << TIM_CR2_MMS2_Pos) /*!< 0x00200000 */
18003 #define TIM_CR2_MMS2_2 (0x4UL << TIM_CR2_MMS2_Pos) /*!< 0x00400000 */
18004 #define TIM_CR2_MMS2_3 (0x8UL << TIM_CR2_MMS2_Pos) /*!< 0x00800000 */
18005
18006 /******************* Bit definition for TIM_SMCR register *******************/
18007 #define TIM_SMCR_SMS_Pos (0U)
18008 #define TIM_SMCR_SMS_Msk (0x10007UL << TIM_SMCR_SMS_Pos) /*!< 0x00010007 */
18009 #define TIM_SMCR_SMS TIM_SMCR_SMS_Msk /*!<SMS[2:0] bits (Slave mode selection) */
18010 #define TIM_SMCR_SMS_0 (0x00001UL << TIM_SMCR_SMS_Pos) /*!< 0x00000001 */
18011 #define TIM_SMCR_SMS_1 (0x00002UL << TIM_SMCR_SMS_Pos) /*!< 0x00000002 */
18012 #define TIM_SMCR_SMS_2 (0x00004UL << TIM_SMCR_SMS_Pos) /*!< 0x00000004 */
18013 #define TIM_SMCR_SMS_3 (0x10000UL << TIM_SMCR_SMS_Pos) /*!< 0x00010000 */
18014
18015 #define TIM_SMCR_TS_Pos (4U)
18016 #define TIM_SMCR_TS_Msk (0x30007UL << TIM_SMCR_TS_Pos) /*!< 0x00300070 */
18017 #define TIM_SMCR_TS TIM_SMCR_TS_Msk /*!<TS[4:0] bits (Trigger selection) */
18018 #define TIM_SMCR_TS_0 (0x00001UL << TIM_SMCR_TS_Pos) /*!< 0x00000010 */
18019 #define TIM_SMCR_TS_1 (0x00002UL << TIM_SMCR_TS_Pos) /*!< 0x00000020 */
18020 #define TIM_SMCR_TS_2 (0x00004UL << TIM_SMCR_TS_Pos) /*!< 0x00000040 */
18021 #define TIM_SMCR_TS_3 (0x10000UL << TIM_SMCR_TS_Pos) /*!< 0x00100000 */
18022 #define TIM_SMCR_TS_4 (0x20000UL << TIM_SMCR_TS_Pos) /*!< 0x00200000 */
18023
18024 #define TIM_SMCR_MSM_Pos (7U)
18025 #define TIM_SMCR_MSM_Msk (0x1UL << TIM_SMCR_MSM_Pos) /*!< 0x00000080 */
18026 #define TIM_SMCR_MSM TIM_SMCR_MSM_Msk /*!<Master/slave mode */
18027
18028 #define TIM_SMCR_ETF_Pos (8U)
18029 #define TIM_SMCR_ETF_Msk (0xFUL << TIM_SMCR_ETF_Pos) /*!< 0x00000F00 */
18030 #define TIM_SMCR_ETF TIM_SMCR_ETF_Msk /*!<ETF[3:0] bits (External trigger filter) */
18031 #define TIM_SMCR_ETF_0 (0x1UL << TIM_SMCR_ETF_Pos) /*!< 0x00000100 */
18032 #define TIM_SMCR_ETF_1 (0x2UL << TIM_SMCR_ETF_Pos) /*!< 0x00000200 */
18033 #define TIM_SMCR_ETF_2 (0x4UL << TIM_SMCR_ETF_Pos) /*!< 0x00000400 */
18034 #define TIM_SMCR_ETF_3 (0x8UL << TIM_SMCR_ETF_Pos) /*!< 0x00000800 */
18035
18036 #define TIM_SMCR_ETPS_Pos (12U)
18037 #define TIM_SMCR_ETPS_Msk (0x3UL << TIM_SMCR_ETPS_Pos) /*!< 0x00003000 */
18038 #define TIM_SMCR_ETPS TIM_SMCR_ETPS_Msk /*!<ETPS[1:0] bits (External trigger prescaler) */
18039 #define TIM_SMCR_ETPS_0 (0x1UL << TIM_SMCR_ETPS_Pos) /*!< 0x00001000 */
18040 #define TIM_SMCR_ETPS_1 (0x2UL << TIM_SMCR_ETPS_Pos) /*!< 0x00002000 */
18041
18042 #define TIM_SMCR_ECE_Pos (14U)
18043 #define TIM_SMCR_ECE_Msk (0x1UL << TIM_SMCR_ECE_Pos) /*!< 0x00004000 */
18044 #define TIM_SMCR_ECE TIM_SMCR_ECE_Msk /*!<External clock enable */
18045 #define TIM_SMCR_ETP_Pos (15U)
18046 #define TIM_SMCR_ETP_Msk (0x1UL << TIM_SMCR_ETP_Pos) /*!< 0x00008000 */
18047 #define TIM_SMCR_ETP TIM_SMCR_ETP_Msk /*!<External trigger polarity */
18048
18049 /******************* Bit definition for TIM_DIER register *******************/
18050 #define TIM_DIER_UIE_Pos (0U)
18051 #define TIM_DIER_UIE_Msk (0x1UL << TIM_DIER_UIE_Pos) /*!< 0x00000001 */
18052 #define TIM_DIER_UIE TIM_DIER_UIE_Msk /*!<Update interrupt enable */
18053 #define TIM_DIER_CC1IE_Pos (1U)
18054 #define TIM_DIER_CC1IE_Msk (0x1UL << TIM_DIER_CC1IE_Pos) /*!< 0x00000002 */
18055 #define TIM_DIER_CC1IE TIM_DIER_CC1IE_Msk /*!<Capture/Compare 1 interrupt enable */
18056 #define TIM_DIER_CC2IE_Pos (2U)
18057 #define TIM_DIER_CC2IE_Msk (0x1UL << TIM_DIER_CC2IE_Pos) /*!< 0x00000004 */
18058 #define TIM_DIER_CC2IE TIM_DIER_CC2IE_Msk /*!<Capture/Compare 2 interrupt enable */
18059 #define TIM_DIER_CC3IE_Pos (3U)
18060 #define TIM_DIER_CC3IE_Msk (0x1UL << TIM_DIER_CC3IE_Pos) /*!< 0x00000008 */
18061 #define TIM_DIER_CC3IE TIM_DIER_CC3IE_Msk /*!<Capture/Compare 3 interrupt enable */
18062 #define TIM_DIER_CC4IE_Pos (4U)
18063 #define TIM_DIER_CC4IE_Msk (0x1UL << TIM_DIER_CC4IE_Pos) /*!< 0x00000010 */
18064 #define TIM_DIER_CC4IE TIM_DIER_CC4IE_Msk /*!<Capture/Compare 4 interrupt enable */
18065 #define TIM_DIER_COMIE_Pos (5U)
18066 #define TIM_DIER_COMIE_Msk (0x1UL << TIM_DIER_COMIE_Pos) /*!< 0x00000020 */
18067 #define TIM_DIER_COMIE TIM_DIER_COMIE_Msk /*!<COM interrupt enable */
18068 #define TIM_DIER_TIE_Pos (6U)
18069 #define TIM_DIER_TIE_Msk (0x1UL << TIM_DIER_TIE_Pos) /*!< 0x00000040 */
18070 #define TIM_DIER_TIE TIM_DIER_TIE_Msk /*!<Trigger interrupt enable */
18071 #define TIM_DIER_BIE_Pos (7U)
18072 #define TIM_DIER_BIE_Msk (0x1UL << TIM_DIER_BIE_Pos) /*!< 0x00000080 */
18073 #define TIM_DIER_BIE TIM_DIER_BIE_Msk /*!<Break interrupt enable */
18074 #define TIM_DIER_UDE_Pos (8U)
18075 #define TIM_DIER_UDE_Msk (0x1UL << TIM_DIER_UDE_Pos) /*!< 0x00000100 */
18076 #define TIM_DIER_UDE TIM_DIER_UDE_Msk /*!<Update DMA request enable */
18077 #define TIM_DIER_CC1DE_Pos (9U)
18078 #define TIM_DIER_CC1DE_Msk (0x1UL << TIM_DIER_CC1DE_Pos) /*!< 0x00000200 */
18079 #define TIM_DIER_CC1DE TIM_DIER_CC1DE_Msk /*!<Capture/Compare 1 DMA request enable */
18080 #define TIM_DIER_CC2DE_Pos (10U)
18081 #define TIM_DIER_CC2DE_Msk (0x1UL << TIM_DIER_CC2DE_Pos) /*!< 0x00000400 */
18082 #define TIM_DIER_CC2DE TIM_DIER_CC2DE_Msk /*!<Capture/Compare 2 DMA request enable */
18083 #define TIM_DIER_CC3DE_Pos (11U)
18084 #define TIM_DIER_CC3DE_Msk (0x1UL << TIM_DIER_CC3DE_Pos) /*!< 0x00000800 */
18085 #define TIM_DIER_CC3DE TIM_DIER_CC3DE_Msk /*!<Capture/Compare 3 DMA request enable */
18086 #define TIM_DIER_CC4DE_Pos (12U)
18087 #define TIM_DIER_CC4DE_Msk (0x1UL << TIM_DIER_CC4DE_Pos) /*!< 0x00001000 */
18088 #define TIM_DIER_CC4DE TIM_DIER_CC4DE_Msk /*!<Capture/Compare 4 DMA request enable */
18089 #define TIM_DIER_COMDE_Pos (13U)
18090 #define TIM_DIER_COMDE_Msk (0x1UL << TIM_DIER_COMDE_Pos) /*!< 0x00002000 */
18091 #define TIM_DIER_COMDE TIM_DIER_COMDE_Msk /*!<COM DMA request enable */
18092 #define TIM_DIER_TDE_Pos (14U)
18093 #define TIM_DIER_TDE_Msk (0x1UL << TIM_DIER_TDE_Pos) /*!< 0x00004000 */
18094 #define TIM_DIER_TDE TIM_DIER_TDE_Msk /*!<Trigger DMA request enable */
18095
18096 /******************** Bit definition for TIM_SR register ********************/
18097 #define TIM_SR_UIF_Pos (0U)
18098 #define TIM_SR_UIF_Msk (0x1UL << TIM_SR_UIF_Pos) /*!< 0x00000001 */
18099 #define TIM_SR_UIF TIM_SR_UIF_Msk /*!<Update interrupt Flag */
18100 #define TIM_SR_CC1IF_Pos (1U)
18101 #define TIM_SR_CC1IF_Msk (0x1UL << TIM_SR_CC1IF_Pos) /*!< 0x00000002 */
18102 #define TIM_SR_CC1IF TIM_SR_CC1IF_Msk /*!<Capture/Compare 1 interrupt Flag */
18103 #define TIM_SR_CC2IF_Pos (2U)
18104 #define TIM_SR_CC2IF_Msk (0x1UL << TIM_SR_CC2IF_Pos) /*!< 0x00000004 */
18105 #define TIM_SR_CC2IF TIM_SR_CC2IF_Msk /*!<Capture/Compare 2 interrupt Flag */
18106 #define TIM_SR_CC3IF_Pos (3U)
18107 #define TIM_SR_CC3IF_Msk (0x1UL << TIM_SR_CC3IF_Pos) /*!< 0x00000008 */
18108 #define TIM_SR_CC3IF TIM_SR_CC3IF_Msk /*!<Capture/Compare 3 interrupt Flag */
18109 #define TIM_SR_CC4IF_Pos (4U)
18110 #define TIM_SR_CC4IF_Msk (0x1UL << TIM_SR_CC4IF_Pos) /*!< 0x00000010 */
18111 #define TIM_SR_CC4IF TIM_SR_CC4IF_Msk /*!<Capture/Compare 4 interrupt Flag */
18112 #define TIM_SR_COMIF_Pos (5U)
18113 #define TIM_SR_COMIF_Msk (0x1UL << TIM_SR_COMIF_Pos) /*!< 0x00000020 */
18114 #define TIM_SR_COMIF TIM_SR_COMIF_Msk /*!<COM interrupt Flag */
18115 #define TIM_SR_TIF_Pos (6U)
18116 #define TIM_SR_TIF_Msk (0x1UL << TIM_SR_TIF_Pos) /*!< 0x00000040 */
18117 #define TIM_SR_TIF TIM_SR_TIF_Msk /*!<Trigger interrupt Flag */
18118 #define TIM_SR_BIF_Pos (7U)
18119 #define TIM_SR_BIF_Msk (0x1UL << TIM_SR_BIF_Pos) /*!< 0x00000080 */
18120 #define TIM_SR_BIF TIM_SR_BIF_Msk /*!<Break interrupt Flag */
18121 #define TIM_SR_B2IF_Pos (8U)
18122 #define TIM_SR_B2IF_Msk (0x1UL << TIM_SR_B2IF_Pos) /*!< 0x00000100 */
18123 #define TIM_SR_B2IF TIM_SR_B2IF_Msk /*!<Break2 interrupt Flag */
18124 #define TIM_SR_CC1OF_Pos (9U)
18125 #define TIM_SR_CC1OF_Msk (0x1UL << TIM_SR_CC1OF_Pos) /*!< 0x00000200 */
18126 #define TIM_SR_CC1OF TIM_SR_CC1OF_Msk /*!<Capture/Compare 1 Overcapture Flag */
18127 #define TIM_SR_CC2OF_Pos (10U)
18128 #define TIM_SR_CC2OF_Msk (0x1UL << TIM_SR_CC2OF_Pos) /*!< 0x00000400 */
18129 #define TIM_SR_CC2OF TIM_SR_CC2OF_Msk /*!<Capture/Compare 2 Overcapture Flag */
18130 #define TIM_SR_CC3OF_Pos (11U)
18131 #define TIM_SR_CC3OF_Msk (0x1UL << TIM_SR_CC3OF_Pos) /*!< 0x00000800 */
18132 #define TIM_SR_CC3OF TIM_SR_CC3OF_Msk /*!<Capture/Compare 3 Overcapture Flag */
18133 #define TIM_SR_CC4OF_Pos (12U)
18134 #define TIM_SR_CC4OF_Msk (0x1UL << TIM_SR_CC4OF_Pos) /*!< 0x00001000 */
18135 #define TIM_SR_CC4OF TIM_SR_CC4OF_Msk /*!<Capture/Compare 4 Overcapture Flag */
18136 #define TIM_SR_CC5IF_Pos (16U)
18137 #define TIM_SR_CC5IF_Msk (0x1UL << TIM_SR_CC5IF_Pos) /*!< 0x00010000 */
18138 #define TIM_SR_CC5IF TIM_SR_CC5IF_Msk /*!<Capture/Compare 5 interrupt Flag */
18139 #define TIM_SR_CC6IF_Pos (17U)
18140 #define TIM_SR_CC6IF_Msk (0x1UL << TIM_SR_CC6IF_Pos) /*!< 0x00020000 */
18141 #define TIM_SR_CC6IF TIM_SR_CC6IF_Msk /*!<Capture/Compare 6 interrupt Flag */
18142 #define TIM_SR_SBIF_Pos (13U)
18143 #define TIM_SR_SBIF_Msk (0x1UL << TIM_SR_SBIF_Pos) /*!< 0x00002000 */
18144 #define TIM_SR_SBIF TIM_SR_SBIF_Msk /*!< System Break Flag */
18145
18146 /******************* Bit definition for TIM_EGR register ********************/
18147 #define TIM_EGR_UG_Pos (0U)
18148 #define TIM_EGR_UG_Msk (0x1UL << TIM_EGR_UG_Pos) /*!< 0x00000001 */
18149 #define TIM_EGR_UG TIM_EGR_UG_Msk /*!<Update Generation */
18150 #define TIM_EGR_CC1G_Pos (1U)
18151 #define TIM_EGR_CC1G_Msk (0x1UL << TIM_EGR_CC1G_Pos) /*!< 0x00000002 */
18152 #define TIM_EGR_CC1G TIM_EGR_CC1G_Msk /*!<Capture/Compare 1 Generation */
18153 #define TIM_EGR_CC2G_Pos (2U)
18154 #define TIM_EGR_CC2G_Msk (0x1UL << TIM_EGR_CC2G_Pos) /*!< 0x00000004 */
18155 #define TIM_EGR_CC2G TIM_EGR_CC2G_Msk /*!<Capture/Compare 2 Generation */
18156 #define TIM_EGR_CC3G_Pos (3U)
18157 #define TIM_EGR_CC3G_Msk (0x1UL << TIM_EGR_CC3G_Pos) /*!< 0x00000008 */
18158 #define TIM_EGR_CC3G TIM_EGR_CC3G_Msk /*!<Capture/Compare 3 Generation */
18159 #define TIM_EGR_CC4G_Pos (4U)
18160 #define TIM_EGR_CC4G_Msk (0x1UL << TIM_EGR_CC4G_Pos) /*!< 0x00000010 */
18161 #define TIM_EGR_CC4G TIM_EGR_CC4G_Msk /*!<Capture/Compare 4 Generation */
18162 #define TIM_EGR_COMG_Pos (5U)
18163 #define TIM_EGR_COMG_Msk (0x1UL << TIM_EGR_COMG_Pos) /*!< 0x00000020 */
18164 #define TIM_EGR_COMG TIM_EGR_COMG_Msk /*!<Capture/Compare Control Update Generation */
18165 #define TIM_EGR_TG_Pos (6U)
18166 #define TIM_EGR_TG_Msk (0x1UL << TIM_EGR_TG_Pos) /*!< 0x00000040 */
18167 #define TIM_EGR_TG TIM_EGR_TG_Msk /*!<Trigger Generation */
18168 #define TIM_EGR_BG_Pos (7U)
18169 #define TIM_EGR_BG_Msk (0x1UL << TIM_EGR_BG_Pos) /*!< 0x00000080 */
18170 #define TIM_EGR_BG TIM_EGR_BG_Msk /*!<Break Generation */
18171 #define TIM_EGR_B2G_Pos (8U)
18172 #define TIM_EGR_B2G_Msk (0x1UL << TIM_EGR_B2G_Pos) /*!< 0x00000100 */
18173 #define TIM_EGR_B2G TIM_EGR_B2G_Msk /*!<Break Generation */
18174
18175
18176 /****************** Bit definition for TIM_CCMR1 register *******************/
18177 #define TIM_CCMR1_CC1S_Pos (0U)
18178 #define TIM_CCMR1_CC1S_Msk (0x3UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000003 */
18179 #define TIM_CCMR1_CC1S TIM_CCMR1_CC1S_Msk /*!<CC1S[1:0] bits (Capture/Compare 1 Selection) */
18180 #define TIM_CCMR1_CC1S_0 (0x1UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000001 */
18181 #define TIM_CCMR1_CC1S_1 (0x2UL << TIM_CCMR1_CC1S_Pos) /*!< 0x00000002 */
18182
18183 #define TIM_CCMR1_OC1FE_Pos (2U)
18184 #define TIM_CCMR1_OC1FE_Msk (0x1UL << TIM_CCMR1_OC1FE_Pos) /*!< 0x00000004 */
18185 #define TIM_CCMR1_OC1FE TIM_CCMR1_OC1FE_Msk /*!<Output Compare 1 Fast enable */
18186 #define TIM_CCMR1_OC1PE_Pos (3U)
18187 #define TIM_CCMR1_OC1PE_Msk (0x1UL << TIM_CCMR1_OC1PE_Pos) /*!< 0x00000008 */
18188 #define TIM_CCMR1_OC1PE TIM_CCMR1_OC1PE_Msk /*!<Output Compare 1 Preload enable */
18189
18190 #define TIM_CCMR1_OC1M_Pos (4U)
18191 #define TIM_CCMR1_OC1M_Msk (0x1007UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010070 */
18192 #define TIM_CCMR1_OC1M TIM_CCMR1_OC1M_Msk /*!<OC1M[2:0] bits (Output Compare 1 Mode) */
18193 #define TIM_CCMR1_OC1M_0 (0x0001UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000010 */
18194 #define TIM_CCMR1_OC1M_1 (0x0002UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000020 */
18195 #define TIM_CCMR1_OC1M_2 (0x0004UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00000040 */
18196 #define TIM_CCMR1_OC1M_3 (0x1000UL << TIM_CCMR1_OC1M_Pos) /*!< 0x00010000 */
18197
18198 #define TIM_CCMR1_OC1CE_Pos (7U)
18199 #define TIM_CCMR1_OC1CE_Msk (0x1UL << TIM_CCMR1_OC1CE_Pos) /*!< 0x00000080 */
18200 #define TIM_CCMR1_OC1CE TIM_CCMR1_OC1CE_Msk /*!<Output Compare 1Clear Enable */
18201
18202 #define TIM_CCMR1_CC2S_Pos (8U)
18203 #define TIM_CCMR1_CC2S_Msk (0x3UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000300 */
18204 #define TIM_CCMR1_CC2S TIM_CCMR1_CC2S_Msk /*!<CC2S[1:0] bits (Capture/Compare 2 Selection) */
18205 #define TIM_CCMR1_CC2S_0 (0x1UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000100 */
18206 #define TIM_CCMR1_CC2S_1 (0x2UL << TIM_CCMR1_CC2S_Pos) /*!< 0x00000200 */
18207
18208 #define TIM_CCMR1_OC2FE_Pos (10U)
18209 #define TIM_CCMR1_OC2FE_Msk (0x1UL << TIM_CCMR1_OC2FE_Pos) /*!< 0x00000400 */
18210 #define TIM_CCMR1_OC2FE TIM_CCMR1_OC2FE_Msk /*!<Output Compare 2 Fast enable */
18211 #define TIM_CCMR1_OC2PE_Pos (11U)
18212 #define TIM_CCMR1_OC2PE_Msk (0x1UL << TIM_CCMR1_OC2PE_Pos) /*!< 0x00000800 */
18213 #define TIM_CCMR1_OC2PE TIM_CCMR1_OC2PE_Msk /*!<Output Compare 2 Preload enable */
18214
18215 #define TIM_CCMR1_OC2M_Pos (12U)
18216 #define TIM_CCMR1_OC2M_Msk (0x1007UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01007000 */
18217 #define TIM_CCMR1_OC2M TIM_CCMR1_OC2M_Msk /*!<OC2M[2:0] bits (Output Compare 2 Mode) */
18218 #define TIM_CCMR1_OC2M_0 (0x0001UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00001000 */
18219 #define TIM_CCMR1_OC2M_1 (0x0002UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00002000 */
18220 #define TIM_CCMR1_OC2M_2 (0x0004UL << TIM_CCMR1_OC2M_Pos) /*!< 0x00004000 */
18221 #define TIM_CCMR1_OC2M_3 (0x1000UL << TIM_CCMR1_OC2M_Pos) /*!< 0x01000000 */
18222
18223 #define TIM_CCMR1_OC2CE_Pos (15U)
18224 #define TIM_CCMR1_OC2CE_Msk (0x1UL << TIM_CCMR1_OC2CE_Pos) /*!< 0x00008000 */
18225 #define TIM_CCMR1_OC2CE TIM_CCMR1_OC2CE_Msk /*!<Output Compare 2 Clear Enable */
18226
18227 /*----------------------------------------------------------------------------*/
18228
18229 #define TIM_CCMR1_IC1PSC_Pos (2U)
18230 #define TIM_CCMR1_IC1PSC_Msk (0x3UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x0000000C */
18231 #define TIM_CCMR1_IC1PSC TIM_CCMR1_IC1PSC_Msk /*!<IC1PSC[1:0] bits (Input Capture 1 Prescaler) */
18232 #define TIM_CCMR1_IC1PSC_0 (0x1UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000004 */
18233 #define TIM_CCMR1_IC1PSC_1 (0x2UL << TIM_CCMR1_IC1PSC_Pos) /*!< 0x00000008 */
18234
18235 #define TIM_CCMR1_IC1F_Pos (4U)
18236 #define TIM_CCMR1_IC1F_Msk (0xFUL << TIM_CCMR1_IC1F_Pos) /*!< 0x000000F0 */
18237 #define TIM_CCMR1_IC1F TIM_CCMR1_IC1F_Msk /*!<IC1F[3:0] bits (Input Capture 1 Filter) */
18238 #define TIM_CCMR1_IC1F_0 (0x1UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000010 */
18239 #define TIM_CCMR1_IC1F_1 (0x2UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000020 */
18240 #define TIM_CCMR1_IC1F_2 (0x4UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000040 */
18241 #define TIM_CCMR1_IC1F_3 (0x8UL << TIM_CCMR1_IC1F_Pos) /*!< 0x00000080 */
18242
18243 #define TIM_CCMR1_IC2PSC_Pos (10U)
18244 #define TIM_CCMR1_IC2PSC_Msk (0x3UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000C00 */
18245 #define TIM_CCMR1_IC2PSC TIM_CCMR1_IC2PSC_Msk /*!<IC2PSC[1:0] bits (Input Capture 2 Prescaler) */
18246 #define TIM_CCMR1_IC2PSC_0 (0x1UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000400 */
18247 #define TIM_CCMR1_IC2PSC_1 (0x2UL << TIM_CCMR1_IC2PSC_Pos) /*!< 0x00000800 */
18248
18249 #define TIM_CCMR1_IC2F_Pos (12U)
18250 #define TIM_CCMR1_IC2F_Msk (0xFUL << TIM_CCMR1_IC2F_Pos) /*!< 0x0000F000 */
18251 #define TIM_CCMR1_IC2F TIM_CCMR1_IC2F_Msk /*!<IC2F[3:0] bits (Input Capture 2 Filter) */
18252 #define TIM_CCMR1_IC2F_0 (0x1UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00001000 */
18253 #define TIM_CCMR1_IC2F_1 (0x2UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00002000 */
18254 #define TIM_CCMR1_IC2F_2 (0x4UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00004000 */
18255 #define TIM_CCMR1_IC2F_3 (0x8UL << TIM_CCMR1_IC2F_Pos) /*!< 0x00008000 */
18256
18257 /****************** Bit definition for TIM_CCMR2 register *******************/
18258 #define TIM_CCMR2_CC3S_Pos (0U)
18259 #define TIM_CCMR2_CC3S_Msk (0x3UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000003 */
18260 #define TIM_CCMR2_CC3S TIM_CCMR2_CC3S_Msk /*!<CC3S[1:0] bits (Capture/Compare 3 Selection) */
18261 #define TIM_CCMR2_CC3S_0 (0x1UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000001 */
18262 #define TIM_CCMR2_CC3S_1 (0x2UL << TIM_CCMR2_CC3S_Pos) /*!< 0x00000002 */
18263
18264 #define TIM_CCMR2_OC3FE_Pos (2U)
18265 #define TIM_CCMR2_OC3FE_Msk (0x1UL << TIM_CCMR2_OC3FE_Pos) /*!< 0x00000004 */
18266 #define TIM_CCMR2_OC3FE TIM_CCMR2_OC3FE_Msk /*!<Output Compare 3 Fast enable */
18267 #define TIM_CCMR2_OC3PE_Pos (3U)
18268 #define TIM_CCMR2_OC3PE_Msk (0x1UL << TIM_CCMR2_OC3PE_Pos) /*!< 0x00000008 */
18269 #define TIM_CCMR2_OC3PE TIM_CCMR2_OC3PE_Msk /*!<Output Compare 3 Preload enable */
18270
18271 #define TIM_CCMR2_OC3M_Pos (4U)
18272 #define TIM_CCMR2_OC3M_Msk (0x7UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000070 */
18273 #define TIM_CCMR2_OC3M TIM_CCMR2_OC3M_Msk /*!<OC3M[2:0] bits (Output Compare 3 Mode) */
18274 #define TIM_CCMR2_OC3M_0 (0x1UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000010 */
18275 #define TIM_CCMR2_OC3M_1 (0x2UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000020 */
18276 #define TIM_CCMR2_OC3M_2 (0x4UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00000040 */
18277 #define TIM_CCMR2_OC3M_3 (0x1000UL << TIM_CCMR2_OC3M_Pos) /*!< 0x00010000 */
18278
18279 #define TIM_CCMR2_OC3CE_Pos (7U)
18280 #define TIM_CCMR2_OC3CE_Msk (0x1UL << TIM_CCMR2_OC3CE_Pos) /*!< 0x00000080 */
18281 #define TIM_CCMR2_OC3CE TIM_CCMR2_OC3CE_Msk /*!<Output Compare 3 Clear Enable */
18282
18283 #define TIM_CCMR2_CC4S_Pos (8U)
18284 #define TIM_CCMR2_CC4S_Msk (0x3UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000300 */
18285 #define TIM_CCMR2_CC4S TIM_CCMR2_CC4S_Msk /*!<CC4S[1:0] bits (Capture/Compare 4 Selection) */
18286 #define TIM_CCMR2_CC4S_0 (0x1UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000100 */
18287 #define TIM_CCMR2_CC4S_1 (0x2UL << TIM_CCMR2_CC4S_Pos) /*!< 0x00000200 */
18288
18289 #define TIM_CCMR2_OC4FE_Pos (10U)
18290 #define TIM_CCMR2_OC4FE_Msk (0x1UL << TIM_CCMR2_OC4FE_Pos) /*!< 0x00000400 */
18291 #define TIM_CCMR2_OC4FE TIM_CCMR2_OC4FE_Msk /*!<Output Compare 4 Fast enable */
18292 #define TIM_CCMR2_OC4PE_Pos (11U)
18293 #define TIM_CCMR2_OC4PE_Msk (0x1UL << TIM_CCMR2_OC4PE_Pos) /*!< 0x00000800 */
18294 #define TIM_CCMR2_OC4PE TIM_CCMR2_OC4PE_Msk /*!<Output Compare 4 Preload enable */
18295
18296 #define TIM_CCMR2_OC4M_Pos (12U)
18297 #define TIM_CCMR2_OC4M_Msk (0x7UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00007000 */
18298 #define TIM_CCMR2_OC4M TIM_CCMR2_OC4M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
18299 #define TIM_CCMR2_OC4M_0 (0x1UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00001000 */
18300 #define TIM_CCMR2_OC4M_1 (0x2UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00002000 */
18301 #define TIM_CCMR2_OC4M_2 (0x4UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00004000 */
18302 #define TIM_CCMR2_OC4M_3 (0x100UL << TIM_CCMR2_OC4M_Pos) /*!< 0x00100000 */
18303
18304 #define TIM_CCMR2_OC4CE_Pos (15U)
18305 #define TIM_CCMR2_OC4CE_Msk (0x1UL << TIM_CCMR2_OC4CE_Pos) /*!< 0x00008000 */
18306 #define TIM_CCMR2_OC4CE TIM_CCMR2_OC4CE_Msk /*!<Output Compare 4 Clear Enable */
18307
18308 /*----------------------------------------------------------------------------*/
18309
18310 #define TIM_CCMR2_IC3PSC_Pos (2U)
18311 #define TIM_CCMR2_IC3PSC_Msk (0x3UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x0000000C */
18312 #define TIM_CCMR2_IC3PSC TIM_CCMR2_IC3PSC_Msk /*!<IC3PSC[1:0] bits (Input Capture 3 Prescaler) */
18313 #define TIM_CCMR2_IC3PSC_0 (0x1UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000004 */
18314 #define TIM_CCMR2_IC3PSC_1 (0x2UL << TIM_CCMR2_IC3PSC_Pos) /*!< 0x00000008 */
18315
18316 #define TIM_CCMR2_IC3F_Pos (4U)
18317 #define TIM_CCMR2_IC3F_Msk (0xFUL << TIM_CCMR2_IC3F_Pos) /*!< 0x000000F0 */
18318 #define TIM_CCMR2_IC3F TIM_CCMR2_IC3F_Msk /*!<IC3F[3:0] bits (Input Capture 3 Filter) */
18319 #define TIM_CCMR2_IC3F_0 (0x1UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000010 */
18320 #define TIM_CCMR2_IC3F_1 (0x2UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000020 */
18321 #define TIM_CCMR2_IC3F_2 (0x4UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000040 */
18322 #define TIM_CCMR2_IC3F_3 (0x8UL << TIM_CCMR2_IC3F_Pos) /*!< 0x00000080 */
18323
18324 #define TIM_CCMR2_IC4PSC_Pos (10U)
18325 #define TIM_CCMR2_IC4PSC_Msk (0x3UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000C00 */
18326 #define TIM_CCMR2_IC4PSC TIM_CCMR2_IC4PSC_Msk /*!<IC4PSC[1:0] bits (Input Capture 4 Prescaler) */
18327 #define TIM_CCMR2_IC4PSC_0 (0x1UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000400 */
18328 #define TIM_CCMR2_IC4PSC_1 (0x2UL << TIM_CCMR2_IC4PSC_Pos) /*!< 0x00000800 */
18329
18330 #define TIM_CCMR2_IC4F_Pos (12U)
18331 #define TIM_CCMR2_IC4F_Msk (0xFUL << TIM_CCMR2_IC4F_Pos) /*!< 0x0000F000 */
18332 #define TIM_CCMR2_IC4F TIM_CCMR2_IC4F_Msk /*!<IC4F[3:0] bits (Input Capture 4 Filter) */
18333 #define TIM_CCMR2_IC4F_0 (0x1UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00001000 */
18334 #define TIM_CCMR2_IC4F_1 (0x2UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00002000 */
18335 #define TIM_CCMR2_IC4F_2 (0x4UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00004000 */
18336 #define TIM_CCMR2_IC4F_3 (0x8UL << TIM_CCMR2_IC4F_Pos) /*!< 0x00008000 */
18337
18338 /******************* Bit definition for TIM_CCER register *******************/
18339 #define TIM_CCER_CC1E_Pos (0U)
18340 #define TIM_CCER_CC1E_Msk (0x1UL << TIM_CCER_CC1E_Pos) /*!< 0x00000001 */
18341 #define TIM_CCER_CC1E TIM_CCER_CC1E_Msk /*!<Capture/Compare 1 output enable */
18342 #define TIM_CCER_CC1P_Pos (1U)
18343 #define TIM_CCER_CC1P_Msk (0x1UL << TIM_CCER_CC1P_Pos) /*!< 0x00000002 */
18344 #define TIM_CCER_CC1P TIM_CCER_CC1P_Msk /*!<Capture/Compare 1 output Polarity */
18345 #define TIM_CCER_CC1NE_Pos (2U)
18346 #define TIM_CCER_CC1NE_Msk (0x1UL << TIM_CCER_CC1NE_Pos) /*!< 0x00000004 */
18347 #define TIM_CCER_CC1NE TIM_CCER_CC1NE_Msk /*!<Capture/Compare 1 Complementary output enable */
18348 #define TIM_CCER_CC1NP_Pos (3U)
18349 #define TIM_CCER_CC1NP_Msk (0x1UL << TIM_CCER_CC1NP_Pos) /*!< 0x00000008 */
18350 #define TIM_CCER_CC1NP TIM_CCER_CC1NP_Msk /*!<Capture/Compare 1 Complementary output Polarity */
18351 #define TIM_CCER_CC2E_Pos (4U)
18352 #define TIM_CCER_CC2E_Msk (0x1UL << TIM_CCER_CC2E_Pos) /*!< 0x00000010 */
18353 #define TIM_CCER_CC2E TIM_CCER_CC2E_Msk /*!<Capture/Compare 2 output enable */
18354 #define TIM_CCER_CC2P_Pos (5U)
18355 #define TIM_CCER_CC2P_Msk (0x1UL << TIM_CCER_CC2P_Pos) /*!< 0x00000020 */
18356 #define TIM_CCER_CC2P TIM_CCER_CC2P_Msk /*!<Capture/Compare 2 output Polarity */
18357 #define TIM_CCER_CC2NE_Pos (6U)
18358 #define TIM_CCER_CC2NE_Msk (0x1UL << TIM_CCER_CC2NE_Pos) /*!< 0x00000040 */
18359 #define TIM_CCER_CC2NE TIM_CCER_CC2NE_Msk /*!<Capture/Compare 2 Complementary output enable */
18360 #define TIM_CCER_CC2NP_Pos (7U)
18361 #define TIM_CCER_CC2NP_Msk (0x1UL << TIM_CCER_CC2NP_Pos) /*!< 0x00000080 */
18362 #define TIM_CCER_CC2NP TIM_CCER_CC2NP_Msk /*!<Capture/Compare 2 Complementary output Polarity */
18363 #define TIM_CCER_CC3E_Pos (8U)
18364 #define TIM_CCER_CC3E_Msk (0x1UL << TIM_CCER_CC3E_Pos) /*!< 0x00000100 */
18365 #define TIM_CCER_CC3E TIM_CCER_CC3E_Msk /*!<Capture/Compare 3 output enable */
18366 #define TIM_CCER_CC3P_Pos (9U)
18367 #define TIM_CCER_CC3P_Msk (0x1UL << TIM_CCER_CC3P_Pos) /*!< 0x00000200 */
18368 #define TIM_CCER_CC3P TIM_CCER_CC3P_Msk /*!<Capture/Compare 3 output Polarity */
18369 #define TIM_CCER_CC3NE_Pos (10U)
18370 #define TIM_CCER_CC3NE_Msk (0x1UL << TIM_CCER_CC3NE_Pos) /*!< 0x00000400 */
18371 #define TIM_CCER_CC3NE TIM_CCER_CC3NE_Msk /*!<Capture/Compare 3 Complementary output enable */
18372 #define TIM_CCER_CC3NP_Pos (11U)
18373 #define TIM_CCER_CC3NP_Msk (0x1UL << TIM_CCER_CC3NP_Pos) /*!< 0x00000800 */
18374 #define TIM_CCER_CC3NP TIM_CCER_CC3NP_Msk /*!<Capture/Compare 3 Complementary output Polarity */
18375 #define TIM_CCER_CC4E_Pos (12U)
18376 #define TIM_CCER_CC4E_Msk (0x1UL << TIM_CCER_CC4E_Pos) /*!< 0x00001000 */
18377 #define TIM_CCER_CC4E TIM_CCER_CC4E_Msk /*!<Capture/Compare 4 output enable */
18378 #define TIM_CCER_CC4P_Pos (13U)
18379 #define TIM_CCER_CC4P_Msk (0x1UL << TIM_CCER_CC4P_Pos) /*!< 0x00002000 */
18380 #define TIM_CCER_CC4P TIM_CCER_CC4P_Msk /*!<Capture/Compare 4 output Polarity */
18381 #define TIM_CCER_CC4NP_Pos (15U)
18382 #define TIM_CCER_CC4NP_Msk (0x1UL << TIM_CCER_CC4NP_Pos) /*!< 0x00008000 */
18383 #define TIM_CCER_CC4NP TIM_CCER_CC4NP_Msk /*!<Capture/Compare 4 Complementary output Polarity */
18384 #define TIM_CCER_CC5E_Pos (16U)
18385 #define TIM_CCER_CC5E_Msk (0x1UL << TIM_CCER_CC5E_Pos) /*!< 0x00010000 */
18386 #define TIM_CCER_CC5E TIM_CCER_CC5E_Msk /*!<Capture/Compare 5 output enable */
18387 #define TIM_CCER_CC5P_Pos (17U)
18388 #define TIM_CCER_CC5P_Msk (0x1UL << TIM_CCER_CC5P_Pos) /*!< 0x00020000 */
18389 #define TIM_CCER_CC5P TIM_CCER_CC5P_Msk /*!<Capture/Compare 5 output Polarity */
18390 #define TIM_CCER_CC6E_Pos (20U)
18391 #define TIM_CCER_CC6E_Msk (0x1UL << TIM_CCER_CC6E_Pos) /*!< 0x00100000 */
18392 #define TIM_CCER_CC6E TIM_CCER_CC6E_Msk /*!<Capture/Compare 6 output enable */
18393 #define TIM_CCER_CC6P_Pos (21U)
18394 #define TIM_CCER_CC6P_Msk (0x1UL << TIM_CCER_CC6P_Pos) /*!< 0x00200000 */
18395 #define TIM_CCER_CC6P TIM_CCER_CC6P_Msk /*!<Capture/Compare 6 output Polarity */
18396 /******************* Bit definition for TIM_CNT register ********************/
18397 #define TIM_CNT_CNT_Pos (0U)
18398 #define TIM_CNT_CNT_Msk (0xFFFFFFFFUL << TIM_CNT_CNT_Pos) /*!< 0xFFFFFFFF */
18399 #define TIM_CNT_CNT TIM_CNT_CNT_Msk /*!<Counter Value */
18400 #define TIM_CNT_UIFCPY_Pos (31U)
18401 #define TIM_CNT_UIFCPY_Msk (0x1UL << TIM_CNT_UIFCPY_Pos) /*!< 0x80000000 */
18402 #define TIM_CNT_UIFCPY TIM_CNT_UIFCPY_Msk /*!<Update interrupt flag copy */
18403 /******************* Bit definition for TIM_PSC register ********************/
18404 #define TIM_PSC_PSC_Pos (0U)
18405 #define TIM_PSC_PSC_Msk (0xFFFFUL << TIM_PSC_PSC_Pos) /*!< 0x0000FFFF */
18406 #define TIM_PSC_PSC TIM_PSC_PSC_Msk /*!<Prescaler Value */
18407
18408 /******************* Bit definition for TIM_ARR register ********************/
18409 #define TIM_ARR_ARR_Pos (0U)
18410 #define TIM_ARR_ARR_Msk (0xFFFFFFFFUL << TIM_ARR_ARR_Pos) /*!< 0xFFFFFFFF */
18411 #define TIM_ARR_ARR TIM_ARR_ARR_Msk /*!<actual auto-reload Value */
18412
18413 /******************* Bit definition for TIM_RCR register ********************/
18414 #define TIM_RCR_REP_Pos (0U)
18415 #define TIM_RCR_REP_Msk (0xFFUL << TIM_RCR_REP_Pos) /*!< 0x000000FF */
18416 #define TIM_RCR_REP TIM_RCR_REP_Msk /*!<Repetition Counter Value */
18417
18418 /******************* Bit definition for TIM_CCR1 register *******************/
18419 #define TIM_CCR1_CCR1_Pos (0U)
18420 #define TIM_CCR1_CCR1_Msk (0xFFFFUL << TIM_CCR1_CCR1_Pos) /*!< 0x0000FFFF */
18421 #define TIM_CCR1_CCR1 TIM_CCR1_CCR1_Msk /*!<Capture/Compare 1 Value */
18422
18423 /******************* Bit definition for TIM_CCR2 register *******************/
18424 #define TIM_CCR2_CCR2_Pos (0U)
18425 #define TIM_CCR2_CCR2_Msk (0xFFFFUL << TIM_CCR2_CCR2_Pos) /*!< 0x0000FFFF */
18426 #define TIM_CCR2_CCR2 TIM_CCR2_CCR2_Msk /*!<Capture/Compare 2 Value */
18427
18428 /******************* Bit definition for TIM_CCR3 register *******************/
18429 #define TIM_CCR3_CCR3_Pos (0U)
18430 #define TIM_CCR3_CCR3_Msk (0xFFFFUL << TIM_CCR3_CCR3_Pos) /*!< 0x0000FFFF */
18431 #define TIM_CCR3_CCR3 TIM_CCR3_CCR3_Msk /*!<Capture/Compare 3 Value */
18432
18433 /******************* Bit definition for TIM_CCR4 register *******************/
18434 #define TIM_CCR4_CCR4_Pos (0U)
18435 #define TIM_CCR4_CCR4_Msk (0xFFFFUL << TIM_CCR4_CCR4_Pos) /*!< 0x0000FFFF */
18436 #define TIM_CCR4_CCR4 TIM_CCR4_CCR4_Msk /*!<Capture/Compare 4 Value */
18437
18438 /******************* Bit definition for TIM_CCR5 register *******************/
18439 #define TIM_CCR5_CCR5_Pos (0U)
18440 #define TIM_CCR5_CCR5_Msk (0xFFFFFFFFUL << TIM_CCR5_CCR5_Pos) /*!< 0xFFFFFFFF */
18441 #define TIM_CCR5_CCR5 TIM_CCR5_CCR5_Msk /*!<Capture/Compare 5 Value */
18442 #define TIM_CCR5_GC5C1_Pos (29U)
18443 #define TIM_CCR5_GC5C1_Msk (0x1UL << TIM_CCR5_GC5C1_Pos) /*!< 0x20000000 */
18444 #define TIM_CCR5_GC5C1 TIM_CCR5_GC5C1_Msk /*!<Group Channel 5 and Channel 1 */
18445 #define TIM_CCR5_GC5C2_Pos (30U)
18446 #define TIM_CCR5_GC5C2_Msk (0x1UL << TIM_CCR5_GC5C2_Pos) /*!< 0x40000000 */
18447 #define TIM_CCR5_GC5C2 TIM_CCR5_GC5C2_Msk /*!<Group Channel 5 and Channel 2 */
18448 #define TIM_CCR5_GC5C3_Pos (31U)
18449 #define TIM_CCR5_GC5C3_Msk (0x1UL << TIM_CCR5_GC5C3_Pos) /*!< 0x80000000 */
18450 #define TIM_CCR5_GC5C3 TIM_CCR5_GC5C3_Msk /*!<Group Channel 5 and Channel 3 */
18451
18452 /******************* Bit definition for TIM_CCR6 register *******************/
18453 #define TIM_CCR6_CCR6_Pos (0U)
18454 #define TIM_CCR6_CCR6_Msk (0xFFFFUL << TIM_CCR6_CCR6_Pos) /*!< 0x0000FFFF */
18455 #define TIM_CCR6_CCR6 TIM_CCR6_CCR6_Msk /*!<Capture/Compare 6 Value */
18456
18457 /******************* Bit definition for TIM_BDTR register *******************/
18458 #define TIM_BDTR_DTG_Pos (0U)
18459 #define TIM_BDTR_DTG_Msk (0xFFUL << TIM_BDTR_DTG_Pos) /*!< 0x000000FF */
18460 #define TIM_BDTR_DTG TIM_BDTR_DTG_Msk /*!<DTG[0:7] bits (Dead-Time Generator set-up) */
18461 #define TIM_BDTR_DTG_0 (0x01UL << TIM_BDTR_DTG_Pos) /*!< 0x00000001 */
18462 #define TIM_BDTR_DTG_1 (0x02UL << TIM_BDTR_DTG_Pos) /*!< 0x00000002 */
18463 #define TIM_BDTR_DTG_2 (0x04UL << TIM_BDTR_DTG_Pos) /*!< 0x00000004 */
18464 #define TIM_BDTR_DTG_3 (0x08UL << TIM_BDTR_DTG_Pos) /*!< 0x00000008 */
18465 #define TIM_BDTR_DTG_4 (0x10UL << TIM_BDTR_DTG_Pos) /*!< 0x00000010 */
18466 #define TIM_BDTR_DTG_5 (0x20UL << TIM_BDTR_DTG_Pos) /*!< 0x00000020 */
18467 #define TIM_BDTR_DTG_6 (0x40UL << TIM_BDTR_DTG_Pos) /*!< 0x00000040 */
18468 #define TIM_BDTR_DTG_7 (0x80UL << TIM_BDTR_DTG_Pos) /*!< 0x00000080 */
18469
18470 #define TIM_BDTR_LOCK_Pos (8U)
18471 #define TIM_BDTR_LOCK_Msk (0x3UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000300 */
18472 #define TIM_BDTR_LOCK TIM_BDTR_LOCK_Msk /*!<LOCK[1:0] bits (Lock Configuration) */
18473 #define TIM_BDTR_LOCK_0 (0x1UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000100 */
18474 #define TIM_BDTR_LOCK_1 (0x2UL << TIM_BDTR_LOCK_Pos) /*!< 0x00000200 */
18475
18476 #define TIM_BDTR_OSSI_Pos (10U)
18477 #define TIM_BDTR_OSSI_Msk (0x1UL << TIM_BDTR_OSSI_Pos) /*!< 0x00000400 */
18478 #define TIM_BDTR_OSSI TIM_BDTR_OSSI_Msk /*!<Off-State Selection for Idle mode */
18479 #define TIM_BDTR_OSSR_Pos (11U)
18480 #define TIM_BDTR_OSSR_Msk (0x1UL << TIM_BDTR_OSSR_Pos) /*!< 0x00000800 */
18481 #define TIM_BDTR_OSSR TIM_BDTR_OSSR_Msk /*!<Off-State Selection for Run mode */
18482 #define TIM_BDTR_BKE_Pos (12U)
18483 #define TIM_BDTR_BKE_Msk (0x1UL << TIM_BDTR_BKE_Pos) /*!< 0x00001000 */
18484 #define TIM_BDTR_BKE TIM_BDTR_BKE_Msk /*!<Break enable for Break1 */
18485 #define TIM_BDTR_BKP_Pos (13U)
18486 #define TIM_BDTR_BKP_Msk (0x1UL << TIM_BDTR_BKP_Pos) /*!< 0x00002000 */
18487 #define TIM_BDTR_BKP TIM_BDTR_BKP_Msk /*!<Break Polarity for Break1 */
18488 #define TIM_BDTR_AOE_Pos (14U)
18489 #define TIM_BDTR_AOE_Msk (0x1UL << TIM_BDTR_AOE_Pos) /*!< 0x00004000 */
18490 #define TIM_BDTR_AOE TIM_BDTR_AOE_Msk /*!<Automatic Output enable */
18491 #define TIM_BDTR_MOE_Pos (15U)
18492 #define TIM_BDTR_MOE_Msk (0x1UL << TIM_BDTR_MOE_Pos) /*!< 0x00008000 */
18493 #define TIM_BDTR_MOE TIM_BDTR_MOE_Msk /*!<Main Output enable */
18494
18495 #define TIM_BDTR_BKF_Pos (16U)
18496 #define TIM_BDTR_BKF_Msk (0xFUL << TIM_BDTR_BKF_Pos) /*!< 0x000F0000 */
18497 #define TIM_BDTR_BKF TIM_BDTR_BKF_Msk /*!<Break Filter for Break1 */
18498 #define TIM_BDTR_BK2F_Pos (20U)
18499 #define TIM_BDTR_BK2F_Msk (0xFUL << TIM_BDTR_BK2F_Pos) /*!< 0x00F00000 */
18500 #define TIM_BDTR_BK2F TIM_BDTR_BK2F_Msk /*!<Break Filter for Break2 */
18501
18502 #define TIM_BDTR_BK2E_Pos (24U)
18503 #define TIM_BDTR_BK2E_Msk (0x1UL << TIM_BDTR_BK2E_Pos) /*!< 0x01000000 */
18504 #define TIM_BDTR_BK2E TIM_BDTR_BK2E_Msk /*!<Break enable for Break2 */
18505 #define TIM_BDTR_BK2P_Pos (25U)
18506 #define TIM_BDTR_BK2P_Msk (0x1UL << TIM_BDTR_BK2P_Pos) /*!< 0x02000000 */
18507 #define TIM_BDTR_BK2P TIM_BDTR_BK2P_Msk /*!<Break Polarity for Break2 */
18508
18509 /******************* Bit definition for TIM_DCR register ********************/
18510 #define TIM_DCR_DBA_Pos (0U)
18511 #define TIM_DCR_DBA_Msk (0x1FUL << TIM_DCR_DBA_Pos) /*!< 0x0000001F */
18512 #define TIM_DCR_DBA TIM_DCR_DBA_Msk /*!<DBA[4:0] bits (DMA Base Address) */
18513 #define TIM_DCR_DBA_0 (0x01UL << TIM_DCR_DBA_Pos) /*!< 0x00000001 */
18514 #define TIM_DCR_DBA_1 (0x02UL << TIM_DCR_DBA_Pos) /*!< 0x00000002 */
18515 #define TIM_DCR_DBA_2 (0x04UL << TIM_DCR_DBA_Pos) /*!< 0x00000004 */
18516 #define TIM_DCR_DBA_3 (0x08UL << TIM_DCR_DBA_Pos) /*!< 0x00000008 */
18517 #define TIM_DCR_DBA_4 (0x10UL << TIM_DCR_DBA_Pos) /*!< 0x00000010 */
18518
18519 #define TIM_DCR_DBL_Pos (8U)
18520 #define TIM_DCR_DBL_Msk (0x1FUL << TIM_DCR_DBL_Pos) /*!< 0x00001F00 */
18521 #define TIM_DCR_DBL TIM_DCR_DBL_Msk /*!<DBL[4:0] bits (DMA Burst Length) */
18522 #define TIM_DCR_DBL_0 (0x01UL << TIM_DCR_DBL_Pos) /*!< 0x00000100 */
18523 #define TIM_DCR_DBL_1 (0x02UL << TIM_DCR_DBL_Pos) /*!< 0x00000200 */
18524 #define TIM_DCR_DBL_2 (0x04UL << TIM_DCR_DBL_Pos) /*!< 0x00000400 */
18525 #define TIM_DCR_DBL_3 (0x08UL << TIM_DCR_DBL_Pos) /*!< 0x00000800 */
18526 #define TIM_DCR_DBL_4 (0x10UL << TIM_DCR_DBL_Pos) /*!< 0x00001000 */
18527
18528 /******************* Bit definition for TIM_DMAR register *******************/
18529 #define TIM_DMAR_DMAB_Pos (0U)
18530 #define TIM_DMAR_DMAB_Msk (0xFFFFUL << TIM_DMAR_DMAB_Pos) /*!< 0x0000FFFF */
18531 #define TIM_DMAR_DMAB TIM_DMAR_DMAB_Msk /*!<DMA register for burst accesses */
18532
18533 /****************** Bit definition for TIM_CCMR3 register *******************/
18534 #define TIM_CCMR3_OC5FE_Pos (2U)
18535 #define TIM_CCMR3_OC5FE_Msk (0x1UL << TIM_CCMR3_OC5FE_Pos) /*!< 0x00000004 */
18536 #define TIM_CCMR3_OC5FE TIM_CCMR3_OC5FE_Msk /*!<Output Compare 5 Fast enable */
18537 #define TIM_CCMR3_OC5PE_Pos (3U)
18538 #define TIM_CCMR3_OC5PE_Msk (0x1UL << TIM_CCMR3_OC5PE_Pos) /*!< 0x00000008 */
18539 #define TIM_CCMR3_OC5PE TIM_CCMR3_OC5PE_Msk /*!<Output Compare 5 Preload enable */
18540
18541 #define TIM_CCMR3_OC5M_Pos (4U)
18542 #define TIM_CCMR3_OC5M_Msk (0x7UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000070 */
18543 #define TIM_CCMR3_OC5M TIM_CCMR3_OC5M_Msk /*!<OC5M[2:0] bits (Output Compare 5 Mode) */
18544 #define TIM_CCMR3_OC5M_0 (0x1UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000010 */
18545 #define TIM_CCMR3_OC5M_1 (0x2UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000020 */
18546 #define TIM_CCMR3_OC5M_2 (0x4UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00000040 */
18547 #define TIM_CCMR3_OC5M_3 (0x1000UL << TIM_CCMR3_OC5M_Pos) /*!< 0x00010000 */
18548
18549 #define TIM_CCMR3_OC5CE_Pos (7U)
18550 #define TIM_CCMR3_OC5CE_Msk (0x1UL << TIM_CCMR3_OC5CE_Pos) /*!< 0x00000080 */
18551 #define TIM_CCMR3_OC5CE TIM_CCMR3_OC5CE_Msk /*!<Output Compare 5 Clear Enable */
18552
18553 #define TIM_CCMR3_OC6FE_Pos (10U)
18554 #define TIM_CCMR3_OC6FE_Msk (0x1UL << TIM_CCMR3_OC6FE_Pos) /*!< 0x00000400 */
18555 #define TIM_CCMR3_OC6FE TIM_CCMR3_OC6FE_Msk /*!<Output Compare 4 Fast enable */
18556 #define TIM_CCMR3_OC6PE_Pos (11U)
18557 #define TIM_CCMR3_OC6PE_Msk (0x1UL << TIM_CCMR3_OC6PE_Pos) /*!< 0x00000800 */
18558 #define TIM_CCMR3_OC6PE TIM_CCMR3_OC6PE_Msk /*!<Output Compare 4 Preload enable */
18559
18560 #define TIM_CCMR3_OC6M_Pos (12U)
18561 #define TIM_CCMR3_OC6M_Msk (0x7UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00007000 */
18562 #define TIM_CCMR3_OC6M TIM_CCMR3_OC6M_Msk /*!<OC4M[2:0] bits (Output Compare 4 Mode) */
18563 #define TIM_CCMR3_OC6M_0 (0x1UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00001000 */
18564 #define TIM_CCMR3_OC6M_1 (0x2UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00002000 */
18565 #define TIM_CCMR3_OC6M_2 (0x4UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00004000 */
18566 #define TIM_CCMR3_OC6M_3 (0x100UL << TIM_CCMR3_OC6M_Pos) /*!< 0x00100000 */
18567
18568 #define TIM_CCMR3_OC6CE_Pos (15U)
18569 #define TIM_CCMR3_OC6CE_Msk (0x1UL << TIM_CCMR3_OC6CE_Pos) /*!< 0x00008000 */
18570 #define TIM_CCMR3_OC6CE TIM_CCMR3_OC6CE_Msk /*!<Output Compare 4 Clear Enable */
18571 /******************* Bit definition for TIM1_AF1 register *********************/
18572 #define TIM1_AF1_BKINE_Pos (0U)
18573 #define TIM1_AF1_BKINE_Msk (0x1UL << TIM1_AF1_BKINE_Pos) /*!< 0x00000001 */
18574 #define TIM1_AF1_BKINE TIM1_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18575 #define TIM1_AF1_BKCMP1E_Pos (1U)
18576 #define TIM1_AF1_BKCMP1E_Msk (0x1UL << TIM1_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18577 #define TIM1_AF1_BKCMP1E TIM1_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18578 #define TIM1_AF1_BKCMP2E_Pos (2U)
18579 #define TIM1_AF1_BKCMP2E_Msk (0x1UL << TIM1_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18580 #define TIM1_AF1_BKCMP2E TIM1_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18581 #define TIM1_AF1_BKDF1BK0E_Pos (8U)
18582 #define TIM1_AF1_BKDF1BK0E_Msk (0x1UL << TIM1_AF1_BKDF1BK0E_Pos) /*!< 0x00000100 */
18583 #define TIM1_AF1_BKDF1BK0E TIM1_AF1_BKDF1BK0E_Msk /*!<BKDF1BK0E Break input DFSDM Break 0 */
18584 #define TIM1_AF1_BKINP_Pos (9U)
18585 #define TIM1_AF1_BKINP_Msk (0x1UL << TIM1_AF1_BKINP_Pos) /*!< 0x00000200 */
18586 #define TIM1_AF1_BKINP TIM1_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18587 #define TIM1_AF1_BKCMP1P_Pos (10U)
18588 #define TIM1_AF1_BKCMP1P_Msk (0x1UL << TIM1_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18589 #define TIM1_AF1_BKCMP1P TIM1_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18590 #define TIM1_AF1_BKCMP2P_Pos (11U)
18591 #define TIM1_AF1_BKCMP2P_Msk (0x1UL << TIM1_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18592 #define TIM1_AF1_BKCMP2P TIM1_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18593
18594 #define TIM1_AF1_ETRSEL_Pos (14U)
18595 #define TIM1_AF1_ETRSEL_Msk (0xFUL << TIM1_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18596 #define TIM1_AF1_ETRSEL TIM1_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM1 ETRSEL) */
18597 #define TIM1_AF1_ETRSEL_0 (0x1UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18598 #define TIM1_AF1_ETRSEL_1 (0x2UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18599 #define TIM1_AF1_ETRSEL_2 (0x4UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18600 #define TIM1_AF1_ETRSEL_3 (0x8UL << TIM1_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18601
18602 /******************* Bit definition for TIM1_AF2 register *********************/
18603 #define TIM1_AF2_BK2INE_Pos (0U)
18604 #define TIM1_AF2_BK2INE_Msk (0x1UL << TIM1_AF2_BK2INE_Pos) /*!< 0x00000001 */
18605 #define TIM1_AF2_BK2INE TIM1_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
18606 #define TIM1_AF2_BK2CMP1E_Pos (1U)
18607 #define TIM1_AF2_BK2CMP1E_Msk (0x1UL << TIM1_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
18608 #define TIM1_AF2_BK2CMP1E TIM1_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
18609 #define TIM1_AF2_BK2CMP2E_Pos (2U)
18610 #define TIM1_AF2_BK2CMP2E_Msk (0x1UL << TIM1_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
18611 #define TIM1_AF2_BK2CMP2E TIM1_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
18612 #define TIM1_AF2_BK2DFBK1E_Pos (8U)
18613 #define TIM1_AF2_BK2DFBK1E_Msk (0x1UL << TIM1_AF2_BK2DFBK1E_Pos) /*!< 0x00000100 */
18614 #define TIM1_AF2_BK2DFBK1E TIM1_AF2_BK2DFBK1E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 1 */
18615 #define TIM1_AF2_BK2INP_Pos (9U)
18616 #define TIM1_AF2_BK2INP_Msk (0x1UL << TIM1_AF2_BK2INP_Pos) /*!< 0x00000200 */
18617 #define TIM1_AF2_BK2INP TIM1_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
18618 #define TIM1_AF2_BK2CMP1P_Pos (10U)
18619 #define TIM1_AF2_BK2CMP1P_Msk (0x1UL << TIM1_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
18620 #define TIM1_AF2_BK2CMP1P TIM1_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
18621 #define TIM1_AF2_BK2CMP2P_Pos (11U)
18622 #define TIM1_AF2_BK2CMP2P_Msk (0x1UL << TIM1_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
18623 #define TIM1_AF2_BK2CMP2P TIM1_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
18624
18625 /******************* Bit definition for TIM_TISEL register *********************/
18626 #define TIM_TISEL_TI1SEL_Pos (0U)
18627 #define TIM_TISEL_TI1SEL_Msk (0xFUL << TIM_TISEL_TI1SEL_Pos) /*!< 0x0000000F */
18628 #define TIM_TISEL_TI1SEL TIM_TISEL_TI1SEL_Msk /*!<TI1SEL[3:0] bits (TIM TI1 SEL)*/
18629 #define TIM_TISEL_TI1SEL_0 (0x1UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000001 */
18630 #define TIM_TISEL_TI1SEL_1 (0x2UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000002 */
18631 #define TIM_TISEL_TI1SEL_2 (0x4UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000004 */
18632 #define TIM_TISEL_TI1SEL_3 (0x8UL << TIM_TISEL_TI1SEL_Pos) /*!< 0x00000008 */
18633
18634 #define TIM_TISEL_TI2SEL_Pos (8U)
18635 #define TIM_TISEL_TI2SEL_Msk (0xFUL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000F00 */
18636 #define TIM_TISEL_TI2SEL TIM_TISEL_TI2SEL_Msk /*!<TI2SEL[3:0] bits (TIM TI2 SEL)*/
18637 #define TIM_TISEL_TI2SEL_0 (0x1UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000100 */
18638 #define TIM_TISEL_TI2SEL_1 (0x2UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000200 */
18639 #define TIM_TISEL_TI2SEL_2 (0x4UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000400 */
18640 #define TIM_TISEL_TI2SEL_3 (0x8UL << TIM_TISEL_TI2SEL_Pos) /*!< 0x00000800 */
18641
18642 #define TIM_TISEL_TI3SEL_Pos (16U)
18643 #define TIM_TISEL_TI3SEL_Msk (0xFUL << TIM_TISEL_TI3SEL_Pos) /*!< 0x000F0000 */
18644 #define TIM_TISEL_TI3SEL TIM_TISEL_TI3SEL_Msk /*!<TI3SEL[3:0] bits (TIM TI3 SEL)*/
18645 #define TIM_TISEL_TI3SEL_0 (0x1UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00010000 */
18646 #define TIM_TISEL_TI3SEL_1 (0x2UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00020000 */
18647 #define TIM_TISEL_TI3SEL_2 (0x4UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00040000 */
18648 #define TIM_TISEL_TI3SEL_3 (0x8UL << TIM_TISEL_TI3SEL_Pos) /*!< 0x00080000 */
18649
18650 #define TIM_TISEL_TI4SEL_Pos (24U)
18651 #define TIM_TISEL_TI4SEL_Msk (0xFUL << TIM_TISEL_TI4SEL_Pos) /*!< 0x0F000000 */
18652 #define TIM_TISEL_TI4SEL TIM_TISEL_TI4SEL_Msk /*!<TI4SEL[3:0] bits (TIM TI4 SEL)*/
18653 #define TIM_TISEL_TI4SEL_0 (0x1UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x01000000 */
18654 #define TIM_TISEL_TI4SEL_1 (0x2UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x02000000 */
18655 #define TIM_TISEL_TI4SEL_2 (0x4UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x04000000 */
18656 #define TIM_TISEL_TI4SEL_3 (0x8UL << TIM_TISEL_TI4SEL_Pos) /*!< 0x08000000 */
18657
18658 /******************* Bit definition for TIM8_AF1 register *********************/
18659 #define TIM8_AF1_BKINE_Pos (0U)
18660 #define TIM8_AF1_BKINE_Msk (0x1UL << TIM8_AF1_BKINE_Pos) /*!< 0x00000001 */
18661 #define TIM8_AF1_BKINE TIM8_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18662 #define TIM8_AF1_BKCMP1E_Pos (1U)
18663 #define TIM8_AF1_BKCMP1E_Msk (0x1UL << TIM8_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18664 #define TIM8_AF1_BKCMP1E TIM8_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18665 #define TIM8_AF1_BKCMP2E_Pos (2U)
18666 #define TIM8_AF1_BKCMP2E_Msk (0x1UL << TIM8_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18667 #define TIM8_AF1_BKCMP2E TIM8_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18668 #define TIM8_AF1_BKDFBK2E_Pos (8U)
18669 #define TIM8_AF1_BKDFBK2E_Msk (0x1UL << TIM8_AF1_BKDFBK2E_Pos) /*!< 0x00000100 */
18670 #define TIM8_AF1_BKDFBK2E TIM8_AF1_BKDFBK2E_Msk /*!<BKDFBK2E Break input DFSDM Break 2 */
18671 #define TIM8_AF1_BKINP_Pos (9U)
18672 #define TIM8_AF1_BKINP_Msk (0x1UL << TIM8_AF1_BKINP_Pos) /*!< 0x00000200 */
18673 #define TIM8_AF1_BKINP TIM8_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18674 #define TIM8_AF1_BKCMP1P_Pos (10U)
18675 #define TIM8_AF1_BKCMP1P_Msk (0x1UL << TIM8_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18676 #define TIM8_AF1_BKCMP1P TIM8_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18677 #define TIM8_AF1_BKCMP2P_Pos (11U)
18678 #define TIM8_AF1_BKCMP2P_Msk (0x1UL << TIM8_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18679 #define TIM8_AF1_BKCMP2P TIM8_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18680
18681 #define TIM8_AF1_ETRSEL_Pos (14U)
18682 #define TIM8_AF1_ETRSEL_Msk (0xFUL << TIM8_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18683 #define TIM8_AF1_ETRSEL TIM8_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM8 ETRSEL) */
18684 #define TIM8_AF1_ETRSEL_0 (0x1UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18685 #define TIM8_AF1_ETRSEL_1 (0x2UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18686 #define TIM8_AF1_ETRSEL_2 (0x4UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18687 #define TIM8_AF1_ETRSEL_3 (0x8UL << TIM8_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18688 /******************* Bit definition for TIM8_AF2 register *********************/
18689 #define TIM8_AF2_BK2INE_Pos (0U)
18690 #define TIM8_AF2_BK2INE_Msk (0x1UL << TIM8_AF2_BK2INE_Pos) /*!< 0x00000001 */
18691 #define TIM8_AF2_BK2INE TIM8_AF2_BK2INE_Msk /*!<BK2INE Break input 2 enable bit */
18692 #define TIM8_AF2_BK2CMP1E_Pos (1U)
18693 #define TIM8_AF2_BK2CMP1E_Msk (0x1UL << TIM8_AF2_BK2CMP1E_Pos) /*!< 0x00000002 */
18694 #define TIM8_AF2_BK2CMP1E TIM8_AF2_BK2CMP1E_Msk /*!<BK2CMP1E Break2 Compare1 Enable bit */
18695 #define TIM8_AF2_BK2CMP2E_Pos (2U)
18696 #define TIM8_AF2_BK2CMP2E_Msk (0x1UL << TIM8_AF2_BK2CMP2E_Pos) /*!< 0x00000004 */
18697 #define TIM8_AF2_BK2CMP2E TIM8_AF2_BK2CMP2E_Msk /*!<BK2CMP1E Break2 Compare2 Enable bit */
18698 #define TIM8_AF2_BK2DFBK3E_Pos (8U)
18699 #define TIM8_AF2_BK2DFBK3E_Msk (0x1UL << TIM8_AF2_BK2DFBK3E_Pos) /*!< 0x00000100 */
18700 #define TIM8_AF2_BK2DFBK3E TIM8_AF2_BK2DFBK3E_Msk /*!<BK2DFBK1E Break input2 DFSDM Break 3 */
18701 #define TIM8_AF2_BK2INP_Pos (9U)
18702 #define TIM8_AF2_BK2INP_Msk (0x1UL << TIM8_AF2_BK2INP_Pos) /*!< 0x00000200 */
18703 #define TIM8_AF2_BK2INP TIM8_AF2_BK2INP_Msk /*!<BRKINP Break2 input polarity */
18704 #define TIM8_AF2_BK2CMP1P_Pos (10U)
18705 #define TIM8_AF2_BK2CMP1P_Msk (0x1UL << TIM8_AF2_BK2CMP1P_Pos) /*!< 0x00000400 */
18706 #define TIM8_AF2_BK2CMP1P TIM8_AF2_BK2CMP1P_Msk /*!<BKCMP1P Break2 COMP1 input polarity */
18707 #define TIM8_AF2_BK2CMP2P_Pos (11U)
18708 #define TIM8_AF2_BK2CMP2P_Msk (0x1UL << TIM8_AF2_BK2CMP2P_Pos) /*!< 0x00000800 */
18709 #define TIM8_AF2_BK2CMP2P TIM8_AF2_BK2CMP2P_Msk /*!<BKCMP2P Break2 COMP2 input polarity */
18710
18711 /******************* Bit definition for TIM2_AF1 register *********************/
18712 #define TIM2_AF1_ETRSEL_Pos (14U)
18713 #define TIM2_AF1_ETRSEL_Msk (0xFUL << TIM2_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18714 #define TIM2_AF1_ETRSEL TIM2_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM2 ETRSEL) */
18715 #define TIM2_AF1_ETRSEL_0 (0x1UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18716 #define TIM2_AF1_ETRSEL_1 (0x2UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18717 #define TIM2_AF1_ETRSEL_2 (0x4UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18718 #define TIM2_AF1_ETRSEL_3 (0x8UL << TIM2_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18719
18720 /******************* Bit definition for TIM3_AF1 register *********************/
18721 #define TIM3_AF1_ETRSEL_Pos (14U)
18722 #define TIM3_AF1_ETRSEL_Msk (0xFUL << TIM3_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18723 #define TIM3_AF1_ETRSEL TIM3_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM3 ETRSEL) */
18724 #define TIM3_AF1_ETRSEL_0 (0x1UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18725 #define TIM3_AF1_ETRSEL_1 (0x2UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18726 #define TIM3_AF1_ETRSEL_2 (0x4UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18727 #define TIM3_AF1_ETRSEL_3 (0x8UL << TIM3_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18728
18729 /******************* Bit definition for TIM5_AF1 register *********************/
18730 #define TIM5_AF1_ETRSEL_Pos (14U)
18731 #define TIM5_AF1_ETRSEL_Msk (0xFUL << TIM5_AF1_ETRSEL_Pos) /*!< 0x0003C000 */
18732 #define TIM5_AF1_ETRSEL TIM5_AF1_ETRSEL_Msk /*!<ETRSEL[3:0] bits (TIM5 ETRSEL) */
18733 #define TIM5_AF1_ETRSEL_0 (0x1UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00004000 */
18734 #define TIM5_AF1_ETRSEL_1 (0x2UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00008000 */
18735 #define TIM5_AF1_ETRSEL_2 (0x4UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00010000 */
18736 #define TIM5_AF1_ETRSEL_3 (0x8UL << TIM5_AF1_ETRSEL_Pos) /*!< 0x00020000 */
18737
18738 /******************* Bit definition for TIM15_AF1 register *********************/
18739 #define TIM15_AF1_BKINE_Pos (0U)
18740 #define TIM15_AF1_BKINE_Msk (0x1UL << TIM15_AF1_BKINE_Pos) /*!< 0x00000001 */
18741 #define TIM15_AF1_BKINE TIM15_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18742 #define TIM15_AF1_BKCMP1E_Pos (1U)
18743 #define TIM15_AF1_BKCMP1E_Msk (0x1UL << TIM15_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18744 #define TIM15_AF1_BKCMP1E TIM15_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18745 #define TIM15_AF1_BKCMP2E_Pos (2U)
18746 #define TIM15_AF1_BKCMP2E_Msk (0x1UL << TIM15_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18747 #define TIM15_AF1_BKCMP2E TIM15_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18748 #define TIM15_AF1_BKDF1BK2E_Pos (8U)
18749 #define TIM15_AF1_BKDF1BK2E_Msk (0x1UL << TIM15_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18750 #define TIM15_AF1_BKDF1BK2E TIM15_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[0] enable */
18751 #define TIM15_AF1_BKINP_Pos (9U)
18752 #define TIM15_AF1_BKINP_Msk (0x1UL << TIM15_AF1_BKINP_Pos) /*!< 0x00000200 */
18753 #define TIM15_AF1_BKINP TIM15_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18754 #define TIM15_AF1_BKCMP1P_Pos (10U)
18755 #define TIM15_AF1_BKCMP1P_Msk (0x1UL << TIM15_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18756 #define TIM15_AF1_BKCMP1P TIM15_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18757 #define TIM15_AF1_BKCMP2P_Pos (11U)
18758 #define TIM15_AF1_BKCMP2P_Msk (0x1UL << TIM15_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18759 #define TIM15_AF1_BKCMP2P TIM15_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18760
18761 /******************* Bit definition for TIM16_ register *********************/
18762 #define TIM16_AF1_BKINE_Pos (0U)
18763 #define TIM16_AF1_BKINE_Msk (0x1UL << TIM16_AF1_BKINE_Pos) /*!< 0x00000001 */
18764 #define TIM16_AF1_BKINE TIM16_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18765 #define TIM16_AF1_BKCMP1E_Pos (1U)
18766 #define TIM16_AF1_BKCMP1E_Msk (0x1UL << TIM16_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18767 #define TIM16_AF1_BKCMP1E TIM16_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18768 #define TIM16_AF1_BKCMP2E_Pos (2U)
18769 #define TIM16_AF1_BKCMP2E_Msk (0x1UL << TIM16_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18770 #define TIM16_AF1_BKCMP2E TIM16_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18771 #define TIM16_AF1_BKDF1BK2E_Pos (8U)
18772 #define TIM16_AF1_BKDF1BK2E_Msk (0x1UL << TIM16_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18773 #define TIM16_AF1_BKDF1BK2E TIM16_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[1] enable */
18774 #define TIM16_AF1_BKINP_Pos (9U)
18775 #define TIM16_AF1_BKINP_Msk (0x1UL << TIM16_AF1_BKINP_Pos) /*!< 0x00000200 */
18776 #define TIM16_AF1_BKINP TIM16_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18777 #define TIM16_AF1_BKCMP1P_Pos (10U)
18778 #define TIM16_AF1_BKCMP1P_Msk (0x1UL << TIM16_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18779 #define TIM16_AF1_BKCMP1P TIM16_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18780 #define TIM16_AF1_BKCMP2P_Pos (11U)
18781 #define TIM16_AF1_BKCMP2P_Msk (0x1UL << TIM16_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18782 #define TIM16_AF1_BKCMP2P TIM16_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18783
18784 /******************* Bit definition for TIM17_AF1 register *********************/
18785 #define TIM17_AF1_BKINE_Pos (0U)
18786 #define TIM17_AF1_BKINE_Msk (0x1UL << TIM17_AF1_BKINE_Pos) /*!< 0x00000001 */
18787 #define TIM17_AF1_BKINE TIM17_AF1_BKINE_Msk /*!<BKINE Break input enable bit */
18788 #define TIM17_AF1_BKCMP1E_Pos (1U)
18789 #define TIM17_AF1_BKCMP1E_Msk (0x1UL << TIM17_AF1_BKCMP1E_Pos) /*!< 0x00000002 */
18790 #define TIM17_AF1_BKCMP1E TIM17_AF1_BKCMP1E_Msk /*!<BKCMP1E Break Compare1 Enable bit */
18791 #define TIM17_AF1_BKCMP2E_Pos (2U)
18792 #define TIM17_AF1_BKCMP2E_Msk (0x1UL << TIM17_AF1_BKCMP2E_Pos) /*!< 0x00000004 */
18793 #define TIM17_AF1_BKCMP2E TIM17_AF1_BKCMP2E_Msk /*!<BKCMP1E Break Compare2 Enable bit */
18794 #define TIM17_AF1_BKDF1BK2E_Pos (8U)
18795 #define TIM17_AF1_BKDF1BK2E_Msk (0x1UL << TIM17_AF1_BKDF1BK2E_Pos) /*!< 0x00000100 */
18796 #define TIM17_AF1_BKDF1BK2E TIM17_AF1_BKDF1BK2E_Msk /*!<BRK dfsdm1_break[2] enable */
18797 #define TIM17_AF1_BKINP_Pos (9U)
18798 #define TIM17_AF1_BKINP_Msk (0x1UL << TIM17_AF1_BKINP_Pos) /*!< 0x00000200 */
18799 #define TIM17_AF1_BKINP TIM17_AF1_BKINP_Msk /*!<BRKINP Break input polarity */
18800 #define TIM17_AF1_BKCMP1P_Pos (10U)
18801 #define TIM17_AF1_BKCMP1P_Msk (0x1UL << TIM17_AF1_BKCMP1P_Pos) /*!< 0x00000400 */
18802 #define TIM17_AF1_BKCMP1P TIM17_AF1_BKCMP1P_Msk /*!<BKCMP1P Break COMP1 input polarity */
18803 #define TIM17_AF1_BKCMP2P_Pos (11U)
18804 #define TIM17_AF1_BKCMP2P_Msk (0x1UL << TIM17_AF1_BKCMP2P_Pos) /*!< 0x00000800 */
18805 #define TIM17_AF1_BKCMP2P TIM17_AF1_BKCMP2P_Msk /*!<BKCMP2P Break COMP2 input polarity */
18806
18807 /******************************************************************************/
18808 /* */
18809 /* Low Power Timer (LPTTIM) */
18810 /* */
18811 /******************************************************************************/
18812 /****************** Bit definition for LPTIM_ISR register *******************/
18813 #define LPTIM_ISR_CMPM_Pos (0U)
18814 #define LPTIM_ISR_CMPM_Msk (0x1UL << LPTIM_ISR_CMPM_Pos) /*!< 0x00000001 */
18815 #define LPTIM_ISR_CMPM LPTIM_ISR_CMPM_Msk /*!< Compare match */
18816 #define LPTIM_ISR_ARRM_Pos (1U)
18817 #define LPTIM_ISR_ARRM_Msk (0x1UL << LPTIM_ISR_ARRM_Pos) /*!< 0x00000002 */
18818 #define LPTIM_ISR_ARRM LPTIM_ISR_ARRM_Msk /*!< Autoreload match */
18819 #define LPTIM_ISR_EXTTRIG_Pos (2U)
18820 #define LPTIM_ISR_EXTTRIG_Msk (0x1UL << LPTIM_ISR_EXTTRIG_Pos) /*!< 0x00000004 */
18821 #define LPTIM_ISR_EXTTRIG LPTIM_ISR_EXTTRIG_Msk /*!< External trigger edge event */
18822 #define LPTIM_ISR_CMPOK_Pos (3U)
18823 #define LPTIM_ISR_CMPOK_Msk (0x1UL << LPTIM_ISR_CMPOK_Pos) /*!< 0x00000008 */
18824 #define LPTIM_ISR_CMPOK LPTIM_ISR_CMPOK_Msk /*!< Compare register update OK */
18825 #define LPTIM_ISR_ARROK_Pos (4U)
18826 #define LPTIM_ISR_ARROK_Msk (0x1UL << LPTIM_ISR_ARROK_Pos) /*!< 0x00000010 */
18827 #define LPTIM_ISR_ARROK LPTIM_ISR_ARROK_Msk /*!< Autoreload register update OK */
18828 #define LPTIM_ISR_UP_Pos (5U)
18829 #define LPTIM_ISR_UP_Msk (0x1UL << LPTIM_ISR_UP_Pos) /*!< 0x00000020 */
18830 #define LPTIM_ISR_UP LPTIM_ISR_UP_Msk /*!< Counter direction change down to up */
18831 #define LPTIM_ISR_DOWN_Pos (6U)
18832 #define LPTIM_ISR_DOWN_Msk (0x1UL << LPTIM_ISR_DOWN_Pos) /*!< 0x00000040 */
18833 #define LPTIM_ISR_DOWN LPTIM_ISR_DOWN_Msk /*!< Counter direction change up to down */
18834
18835 /****************** Bit definition for LPTIM_ICR register *******************/
18836 #define LPTIM_ICR_CMPMCF_Pos (0U)
18837 #define LPTIM_ICR_CMPMCF_Msk (0x1UL << LPTIM_ICR_CMPMCF_Pos) /*!< 0x00000001 */
18838 #define LPTIM_ICR_CMPMCF LPTIM_ICR_CMPMCF_Msk /*!< Compare match Clear Flag */
18839 #define LPTIM_ICR_ARRMCF_Pos (1U)
18840 #define LPTIM_ICR_ARRMCF_Msk (0x1UL << LPTIM_ICR_ARRMCF_Pos) /*!< 0x00000002 */
18841 #define LPTIM_ICR_ARRMCF LPTIM_ICR_ARRMCF_Msk /*!< Autoreload match Clear Flag */
18842 #define LPTIM_ICR_EXTTRIGCF_Pos (2U)
18843 #define LPTIM_ICR_EXTTRIGCF_Msk (0x1UL << LPTIM_ICR_EXTTRIGCF_Pos) /*!< 0x00000004 */
18844 #define LPTIM_ICR_EXTTRIGCF LPTIM_ICR_EXTTRIGCF_Msk /*!< External trigger edge event Clear Flag */
18845 #define LPTIM_ICR_CMPOKCF_Pos (3U)
18846 #define LPTIM_ICR_CMPOKCF_Msk (0x1UL << LPTIM_ICR_CMPOKCF_Pos) /*!< 0x00000008 */
18847 #define LPTIM_ICR_CMPOKCF LPTIM_ICR_CMPOKCF_Msk /*!< Compare register update OK Clear Flag */
18848 #define LPTIM_ICR_ARROKCF_Pos (4U)
18849 #define LPTIM_ICR_ARROKCF_Msk (0x1UL << LPTIM_ICR_ARROKCF_Pos) /*!< 0x00000010 */
18850 #define LPTIM_ICR_ARROKCF LPTIM_ICR_ARROKCF_Msk /*!< Autoreload register update OK Clear Flag */
18851 #define LPTIM_ICR_UPCF_Pos (5U)
18852 #define LPTIM_ICR_UPCF_Msk (0x1UL << LPTIM_ICR_UPCF_Pos) /*!< 0x00000020 */
18853 #define LPTIM_ICR_UPCF LPTIM_ICR_UPCF_Msk /*!< Counter direction change down to up Clear Flag */
18854 #define LPTIM_ICR_DOWNCF_Pos (6U)
18855 #define LPTIM_ICR_DOWNCF_Msk (0x1UL << LPTIM_ICR_DOWNCF_Pos) /*!< 0x00000040 */
18856 #define LPTIM_ICR_DOWNCF LPTIM_ICR_DOWNCF_Msk /*!< Counter direction change up to down Clear Flag */
18857
18858 /****************** Bit definition for LPTIM_IER register ********************/
18859 #define LPTIM_IER_CMPMIE_Pos (0U)
18860 #define LPTIM_IER_CMPMIE_Msk (0x1UL << LPTIM_IER_CMPMIE_Pos) /*!< 0x00000001 */
18861 #define LPTIM_IER_CMPMIE LPTIM_IER_CMPMIE_Msk /*!< Compare match Interrupt Enable */
18862 #define LPTIM_IER_ARRMIE_Pos (1U)
18863 #define LPTIM_IER_ARRMIE_Msk (0x1UL << LPTIM_IER_ARRMIE_Pos) /*!< 0x00000002 */
18864 #define LPTIM_IER_ARRMIE LPTIM_IER_ARRMIE_Msk /*!< Autoreload match Interrupt Enable */
18865 #define LPTIM_IER_EXTTRIGIE_Pos (2U)
18866 #define LPTIM_IER_EXTTRIGIE_Msk (0x1UL << LPTIM_IER_EXTTRIGIE_Pos) /*!< 0x00000004 */
18867 #define LPTIM_IER_EXTTRIGIE LPTIM_IER_EXTTRIGIE_Msk /*!< External trigger edge event Interrupt Enable */
18868 #define LPTIM_IER_CMPOKIE_Pos (3U)
18869 #define LPTIM_IER_CMPOKIE_Msk (0x1UL << LPTIM_IER_CMPOKIE_Pos) /*!< 0x00000008 */
18870 #define LPTIM_IER_CMPOKIE LPTIM_IER_CMPOKIE_Msk /*!< Compare register update OK Interrupt Enable */
18871 #define LPTIM_IER_ARROKIE_Pos (4U)
18872 #define LPTIM_IER_ARROKIE_Msk (0x1UL << LPTIM_IER_ARROKIE_Pos) /*!< 0x00000010 */
18873 #define LPTIM_IER_ARROKIE LPTIM_IER_ARROKIE_Msk /*!< Autoreload register update OK Interrupt Enable */
18874 #define LPTIM_IER_UPIE_Pos (5U)
18875 #define LPTIM_IER_UPIE_Msk (0x1UL << LPTIM_IER_UPIE_Pos) /*!< 0x00000020 */
18876 #define LPTIM_IER_UPIE LPTIM_IER_UPIE_Msk /*!< Counter direction change down to up Interrupt Enable */
18877 #define LPTIM_IER_DOWNIE_Pos (6U)
18878 #define LPTIM_IER_DOWNIE_Msk (0x1UL << LPTIM_IER_DOWNIE_Pos) /*!< 0x00000040 */
18879 #define LPTIM_IER_DOWNIE LPTIM_IER_DOWNIE_Msk /*!< Counter direction change up to down Interrupt Enable */
18880
18881 /****************** Bit definition for LPTIM_CFGR register *******************/
18882 #define LPTIM_CFGR_CKSEL_Pos (0U)
18883 #define LPTIM_CFGR_CKSEL_Msk (0x1UL << LPTIM_CFGR_CKSEL_Pos) /*!< 0x00000001 */
18884 #define LPTIM_CFGR_CKSEL LPTIM_CFGR_CKSEL_Msk /*!< Clock selector */
18885
18886 #define LPTIM_CFGR_CKPOL_Pos (1U)
18887 #define LPTIM_CFGR_CKPOL_Msk (0x3UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000006 */
18888 #define LPTIM_CFGR_CKPOL LPTIM_CFGR_CKPOL_Msk /*!< CKPOL[1:0] bits (Clock polarity) */
18889 #define LPTIM_CFGR_CKPOL_0 (0x1UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000002 */
18890 #define LPTIM_CFGR_CKPOL_1 (0x2UL << LPTIM_CFGR_CKPOL_Pos) /*!< 0x00000004 */
18891
18892 #define LPTIM_CFGR_CKFLT_Pos (3U)
18893 #define LPTIM_CFGR_CKFLT_Msk (0x3UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000018 */
18894 #define LPTIM_CFGR_CKFLT LPTIM_CFGR_CKFLT_Msk /*!< CKFLT[1:0] bits (Configurable digital filter for external clock) */
18895 #define LPTIM_CFGR_CKFLT_0 (0x1UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000008 */
18896 #define LPTIM_CFGR_CKFLT_1 (0x2UL << LPTIM_CFGR_CKFLT_Pos) /*!< 0x00000010 */
18897
18898 #define LPTIM_CFGR_TRGFLT_Pos (6U)
18899 #define LPTIM_CFGR_TRGFLT_Msk (0x3UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x000000C0 */
18900 #define LPTIM_CFGR_TRGFLT LPTIM_CFGR_TRGFLT_Msk /*!< TRGFLT[1:0] bits (Configurable digital filter for trigger) */
18901 #define LPTIM_CFGR_TRGFLT_0 (0x1UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000040 */
18902 #define LPTIM_CFGR_TRGFLT_1 (0x2UL << LPTIM_CFGR_TRGFLT_Pos) /*!< 0x00000080 */
18903
18904 #define LPTIM_CFGR_PRESC_Pos (9U)
18905 #define LPTIM_CFGR_PRESC_Msk (0x7UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000E00 */
18906 #define LPTIM_CFGR_PRESC LPTIM_CFGR_PRESC_Msk /*!< PRESC[2:0] bits (Clock prescaler) */
18907 #define LPTIM_CFGR_PRESC_0 (0x1UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000200 */
18908 #define LPTIM_CFGR_PRESC_1 (0x2UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000400 */
18909 #define LPTIM_CFGR_PRESC_2 (0x4UL << LPTIM_CFGR_PRESC_Pos) /*!< 0x00000800 */
18910
18911 #define LPTIM_CFGR_TRIGSEL_Pos (13U)
18912 #define LPTIM_CFGR_TRIGSEL_Msk (0x7UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x0000E000 */
18913 #define LPTIM_CFGR_TRIGSEL LPTIM_CFGR_TRIGSEL_Msk /*!< TRIGSEL[2:0]] bits (Trigger selector) */
18914 #define LPTIM_CFGR_TRIGSEL_0 (0x1UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00002000 */
18915 #define LPTIM_CFGR_TRIGSEL_1 (0x2UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00004000 */
18916 #define LPTIM_CFGR_TRIGSEL_2 (0x4UL << LPTIM_CFGR_TRIGSEL_Pos) /*!< 0x00008000 */
18917
18918 #define LPTIM_CFGR_TRIGEN_Pos (17U)
18919 #define LPTIM_CFGR_TRIGEN_Msk (0x3UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00060000 */
18920 #define LPTIM_CFGR_TRIGEN LPTIM_CFGR_TRIGEN_Msk /*!< TRIGEN[1:0] bits (Trigger enable and polarity) */
18921 #define LPTIM_CFGR_TRIGEN_0 (0x1UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00020000 */
18922 #define LPTIM_CFGR_TRIGEN_1 (0x2UL << LPTIM_CFGR_TRIGEN_Pos) /*!< 0x00040000 */
18923
18924 #define LPTIM_CFGR_TIMOUT_Pos (19U)
18925 #define LPTIM_CFGR_TIMOUT_Msk (0x1UL << LPTIM_CFGR_TIMOUT_Pos) /*!< 0x00080000 */
18926 #define LPTIM_CFGR_TIMOUT LPTIM_CFGR_TIMOUT_Msk /*!< Timout enable */
18927 #define LPTIM_CFGR_WAVE_Pos (20U)
18928 #define LPTIM_CFGR_WAVE_Msk (0x1UL << LPTIM_CFGR_WAVE_Pos) /*!< 0x00100000 */
18929 #define LPTIM_CFGR_WAVE LPTIM_CFGR_WAVE_Msk /*!< Waveform shape */
18930 #define LPTIM_CFGR_WAVPOL_Pos (21U)
18931 #define LPTIM_CFGR_WAVPOL_Msk (0x1UL << LPTIM_CFGR_WAVPOL_Pos) /*!< 0x00200000 */
18932 #define LPTIM_CFGR_WAVPOL LPTIM_CFGR_WAVPOL_Msk /*!< Waveform shape polarity */
18933 #define LPTIM_CFGR_PRELOAD_Pos (22U)
18934 #define LPTIM_CFGR_PRELOAD_Msk (0x1UL << LPTIM_CFGR_PRELOAD_Pos) /*!< 0x00400000 */
18935 #define LPTIM_CFGR_PRELOAD LPTIM_CFGR_PRELOAD_Msk /*!< Reg update mode */
18936 #define LPTIM_CFGR_COUNTMODE_Pos (23U)
18937 #define LPTIM_CFGR_COUNTMODE_Msk (0x1UL << LPTIM_CFGR_COUNTMODE_Pos) /*!< 0x00800000 */
18938 #define LPTIM_CFGR_COUNTMODE LPTIM_CFGR_COUNTMODE_Msk /*!< Counter mode enable */
18939 #define LPTIM_CFGR_ENC_Pos (24U)
18940 #define LPTIM_CFGR_ENC_Msk (0x1UL << LPTIM_CFGR_ENC_Pos) /*!< 0x01000000 */
18941 #define LPTIM_CFGR_ENC LPTIM_CFGR_ENC_Msk /*!< Encoder mode enable */
18942
18943 /****************** Bit definition for LPTIM_CR register ********************/
18944 #define LPTIM_CR_ENABLE_Pos (0U)
18945 #define LPTIM_CR_ENABLE_Msk (0x1UL << LPTIM_CR_ENABLE_Pos) /*!< 0x00000001 */
18946 #define LPTIM_CR_ENABLE LPTIM_CR_ENABLE_Msk /*!< LPTIMer enable */
18947 #define LPTIM_CR_SNGSTRT_Pos (1U)
18948 #define LPTIM_CR_SNGSTRT_Msk (0x40001UL << LPTIM_CR_SNGSTRT_Pos) /*!< 0x00080002 */
18949 #define LPTIM_CR_SNGSTRT LPTIM_CR_SNGSTRT_Msk /*!< Timer start in single mode */
18950 #define LPTIM_CR_CNTSTRT_Pos (2U)
18951 #define LPTIM_CR_CNTSTRT_Msk (0x1UL << LPTIM_CR_CNTSTRT_Pos) /*!< 0x00000004 */
18952 #define LPTIM_CR_CNTSTRT LPTIM_CR_CNTSTRT_Msk /*!< Timer start in continuous mode */
18953 #define LPTIM_CR_COUNTRST_Pos (3U)
18954 #define LPTIM_CR_COUNTRST_Msk (0x1UL << LPTIM_CR_COUNTRST_Pos) /*!< 0x00000008 */
18955 #define LPTIM_CR_COUNTRST LPTIM_CR_COUNTRST_Msk /*!< Timer Counter reset in synchronous mode*/
18956 #define LPTIM_CR_RSTARE_Pos (4U)
18957 #define LPTIM_CR_RSTARE_Msk (0x1UL << LPTIM_CR_RSTARE_Pos) /*!< 0x00000010 */
18958 #define LPTIM_CR_RSTARE LPTIM_CR_RSTARE_Msk /*!< Timer Counter reset after read enable (asynchronously)*/
18959
18960
18961 /****************** Bit definition for LPTIM_CMP register *******************/
18962 #define LPTIM_CMP_CMP_Pos (0U)
18963 #define LPTIM_CMP_CMP_Msk (0xFFFFUL << LPTIM_CMP_CMP_Pos) /*!< 0x0000FFFF */
18964 #define LPTIM_CMP_CMP LPTIM_CMP_CMP_Msk /*!< Compare register */
18965
18966 /****************** Bit definition for LPTIM_ARR register *******************/
18967 #define LPTIM_ARR_ARR_Pos (0U)
18968 #define LPTIM_ARR_ARR_Msk (0xFFFFUL << LPTIM_ARR_ARR_Pos) /*!< 0x0000FFFF */
18969 #define LPTIM_ARR_ARR LPTIM_ARR_ARR_Msk /*!< Auto reload register */
18970
18971 /****************** Bit definition for LPTIM_CNT register *******************/
18972 #define LPTIM_CNT_CNT_Pos (0U)
18973 #define LPTIM_CNT_CNT_Msk (0xFFFFUL << LPTIM_CNT_CNT_Pos) /*!< 0x0000FFFF */
18974 #define LPTIM_CNT_CNT LPTIM_CNT_CNT_Msk /*!< Counter register */
18975
18976 /****************** Bit definition for LPTIM_CFGR2 register *****************/
18977 #define LPTIM_CFGR2_IN1SEL_Pos (0U)
18978 #define LPTIM_CFGR2_IN1SEL_Msk (0x3UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000003 */
18979 #define LPTIM_CFGR2_IN1SEL LPTIM_CFGR2_IN1SEL_Msk /*!< IN1SEL[1:0] bits (Remap selection) */
18980 #define LPTIM_CFGR2_IN1SEL_0 (0x1UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000001 */
18981 #define LPTIM_CFGR2_IN1SEL_1 (0x2UL << LPTIM_CFGR2_IN1SEL_Pos) /*!< 0x00000002 */
18982 #define LPTIM_CFGR2_IN2SEL_Pos (4U)
18983 #define LPTIM_CFGR2_IN2SEL_Msk (0x3UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000030 */
18984 #define LPTIM_CFGR2_IN2SEL LPTIM_CFGR2_IN2SEL_Msk /*!< IN2SEL[5:4] bits (Remap selection) */
18985 #define LPTIM_CFGR2_IN2SEL_0 (0x1UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000010 */
18986 #define LPTIM_CFGR2_IN2SEL_1 (0x2UL << LPTIM_CFGR2_IN2SEL_Pos) /*!< 0x00000020 */
18987
18988 /******************************************************************************/
18989 /* */
18990 /* OCTOSPI */
18991 /* */
18992 /******************************************************************************/
18993 /***************** Bit definition for OCTOSPI_CR register *******************/
18994 #define OCTOSPI_CR_EN_Pos (0U)
18995 #define OCTOSPI_CR_EN_Msk (0x1UL << OCTOSPI_CR_EN_Pos) /*!< 0x00000001 */
18996 #define OCTOSPI_CR_EN OCTOSPI_CR_EN_Msk /*!< Enable */
18997 #define OCTOSPI_CR_ABORT_Pos (1U)
18998 #define OCTOSPI_CR_ABORT_Msk (0x1UL << OCTOSPI_CR_ABORT_Pos) /*!< 0x00000002 */
18999 #define OCTOSPI_CR_ABORT OCTOSPI_CR_ABORT_Msk /*!< Abort request */
19000 #define OCTOSPI_CR_DMAEN_Pos (2U)
19001 #define OCTOSPI_CR_DMAEN_Msk (0x1UL << OCTOSPI_CR_DMAEN_Pos) /*!< 0x00000004 */
19002 #define OCTOSPI_CR_DMAEN OCTOSPI_CR_DMAEN_Msk /*!< DMA Enable */
19003 #define OCTOSPI_CR_TCEN_Pos (3U)
19004 #define OCTOSPI_CR_TCEN_Msk (0x1UL << OCTOSPI_CR_TCEN_Pos) /*!< 0x00000008 */
19005 #define OCTOSPI_CR_TCEN OCTOSPI_CR_TCEN_Msk /*!< Timeout Counter Enable */
19006 #define OCTOSPI_CR_DQM_Pos (6U)
19007 #define OCTOSPI_CR_DQM_Msk (0x1UL << OCTOSPI_CR_DQM_Pos) /*!< 0x00000040 */
19008 #define OCTOSPI_CR_DQM OCTOSPI_CR_DQM_Msk /*!< Dual-Quad Mode */
19009 #define OCTOSPI_CR_FSEL_Pos (7U)
19010 #define OCTOSPI_CR_FSEL_Msk (0x1UL << OCTOSPI_CR_FSEL_Pos) /*!< 0x00000080 */
19011 #define OCTOSPI_CR_FSEL OCTOSPI_CR_FSEL_Msk /*!< Flash Select */
19012 #define OCTOSPI_CR_FTHRES_Pos (8U)
19013 #define OCTOSPI_CR_FTHRES_Msk (0x1FUL << OCTOSPI_CR_FTHRES_Pos) /*!< 0x00001F00 */
19014 #define OCTOSPI_CR_FTHRES OCTOSPI_CR_FTHRES_Msk /*!< FIFO Threshold Level */
19015 #define OCTOSPI_CR_TEIE_Pos (16U)
19016 #define OCTOSPI_CR_TEIE_Msk (0x1UL << OCTOSPI_CR_TEIE_Pos) /*!< 0x00010000 */
19017 #define OCTOSPI_CR_TEIE OCTOSPI_CR_TEIE_Msk /*!< Transfer Error Interrupt Enable */
19018 #define OCTOSPI_CR_TCIE_Pos (17U)
19019 #define OCTOSPI_CR_TCIE_Msk (0x1UL << OCTOSPI_CR_TCIE_Pos) /*!< 0x00020000 */
19020 #define OCTOSPI_CR_TCIE OCTOSPI_CR_TCIE_Msk /*!< Transfer Complete Interrupt Enable */
19021 #define OCTOSPI_CR_FTIE_Pos (18U)
19022 #define OCTOSPI_CR_FTIE_Msk (0x1UL << OCTOSPI_CR_FTIE_Pos) /*!< 0x00040000 */
19023 #define OCTOSPI_CR_FTIE OCTOSPI_CR_FTIE_Msk /*!< FIFO Threshold Interrupt Enable */
19024 #define OCTOSPI_CR_SMIE_Pos (19U)
19025 #define OCTOSPI_CR_SMIE_Msk (0x1UL << OCTOSPI_CR_SMIE_Pos) /*!< 0x00080000 */
19026 #define OCTOSPI_CR_SMIE OCTOSPI_CR_SMIE_Msk /*!< Status Match Interrupt Enable */
19027 #define OCTOSPI_CR_TOIE_Pos (20U)
19028 #define OCTOSPI_CR_TOIE_Msk (0x1UL << OCTOSPI_CR_TOIE_Pos) /*!< 0x00100000 */
19029 #define OCTOSPI_CR_TOIE OCTOSPI_CR_TOIE_Msk /*!< TimeOut Interrupt Enable */
19030 #define OCTOSPI_CR_APMS_Pos (22U)
19031 #define OCTOSPI_CR_APMS_Msk (0x1UL << OCTOSPI_CR_APMS_Pos) /*!< 0x00400000 */
19032 #define OCTOSPI_CR_APMS OCTOSPI_CR_APMS_Msk /*!< Automatic Poll Mode Stop */
19033 #define OCTOSPI_CR_PMM_Pos (23U)
19034 #define OCTOSPI_CR_PMM_Msk (0x1UL << OCTOSPI_CR_PMM_Pos) /*!< 0x00800000 */
19035 #define OCTOSPI_CR_PMM OCTOSPI_CR_PMM_Msk /*!< Polling Match Mode */
19036 #define OCTOSPI_CR_FMODE_Pos (28U)
19037 #define OCTOSPI_CR_FMODE_Msk (0x3UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x30000000 */
19038 #define OCTOSPI_CR_FMODE OCTOSPI_CR_FMODE_Msk /*!< Functional Mode */
19039 #define OCTOSPI_CR_FMODE_0 (0x1UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x10000000 */
19040 #define OCTOSPI_CR_FMODE_1 (0x2UL << OCTOSPI_CR_FMODE_Pos) /*!< 0x20000000 */
19041
19042 /**************** Bit definition for OCTOSPI_DCR1 register ******************/
19043 #define OCTOSPI_DCR1_CKMODE_Pos (0U)
19044 #define OCTOSPI_DCR1_CKMODE_Msk (0x1UL << OCTOSPI_DCR1_CKMODE_Pos) /*!< 0x00000001 */
19045 #define OCTOSPI_DCR1_CKMODE OCTOSPI_DCR1_CKMODE_Msk /*!< Mode 0 / Mode 3 */
19046 #define OCTOSPI_DCR1_FRCK_Pos (1U)
19047 #define OCTOSPI_DCR1_FRCK_Msk (0x1UL << OCTOSPI_DCR1_FRCK_Pos) /*!< 0x00000002 */
19048 #define OCTOSPI_DCR1_FRCK OCTOSPI_DCR1_FRCK_Msk /*!< Free Running Clock */
19049 #define OCTOSPI_DCR1_DLYBYP_Pos (3U)
19050 #define OCTOSPI_DCR1_DLYBYP_Msk (0x1UL << OCTOSPI_DCR1_DLYBYP_Pos) /*!< 0x00000008 */
19051 #define OCTOSPI_DCR1_DLYBYP OCTOSPI_DCR1_DLYBYP_Msk /*!< Delay Block */
19052 #define OCTOSPI_DCR1_CKCSHT_Pos (4U)
19053 #define OCTOSPI_DCR1_CKCSHT_Msk (0x7UL << OCTOSPI_DCR1_CKCSHT_Pos) /*!< 0x00000070 */
19054 #define OCTOSPI_DCR1_CKCSHT OCTOSPI_DCR1_CKCSHT_Msk /*!< Clocked Chip Select High Time */
19055 #define OCTOSPI_DCR1_CSHT_Pos (8U)
19056 #define OCTOSPI_DCR1_CSHT_Msk (0x7UL << OCTOSPI_DCR1_CSHT_Pos) /*!< 0x00000700 */
19057 #define OCTOSPI_DCR1_CSHT OCTOSPI_DCR1_CSHT_Msk /*!< Chip Select High Time */
19058 #define OCTOSPI_DCR1_DEVSIZE_Pos (16U)
19059 #define OCTOSPI_DCR1_DEVSIZE_Msk (0x1FUL << OCTOSPI_DCR1_DEVSIZE_Pos) /*!< 0x001F0000 */
19060 #define OCTOSPI_DCR1_DEVSIZE OCTOSPI_DCR1_DEVSIZE_Msk /*!< Device Size */
19061 #define OCTOSPI_DCR1_MTYP_Pos (24U)
19062 #define OCTOSPI_DCR1_MTYP_Msk (0x7UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x07000000 */
19063 #define OCTOSPI_DCR1_MTYP OCTOSPI_DCR1_MTYP_Msk /*!< Memory Type */
19064 #define OCTOSPI_DCR1_MTYP_0 (0x1UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x01000000 */
19065 #define OCTOSPI_DCR1_MTYP_1 (0x2UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x02000000 */
19066 #define OCTOSPI_DCR1_MTYP_2 (0x4UL << OCTOSPI_DCR1_MTYP_Pos) /*!< 0x04000000 */
19067
19068 /**************** Bit definition for OCTOSPI_DCR2 register ******************/
19069 #define OCTOSPI_DCR2_PRESCALER_Pos (0U)
19070 #define OCTOSPI_DCR2_PRESCALER_Msk (0xFFUL << OCTOSPI_DCR2_PRESCALER_Pos) /*!< 0x000000FF */
19071 #define OCTOSPI_DCR2_PRESCALER OCTOSPI_DCR2_PRESCALER_Msk /*!< Clock prescaler */
19072 #define OCTOSPI_DCR2_WRAPSIZE_Pos (16U)
19073 #define OCTOSPI_DCR2_WRAPSIZE_Msk (0x7UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00070000 */
19074 #define OCTOSPI_DCR2_WRAPSIZE OCTOSPI_DCR2_WRAPSIZE_Msk /*!< Wrap Size */
19075 #define OCTOSPI_DCR2_WRAPSIZE_0 (0x1UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00010000 */
19076 #define OCTOSPI_DCR2_WRAPSIZE_1 (0x2UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00020000 */
19077 #define OCTOSPI_DCR2_WRAPSIZE_2 (0x4UL << OCTOSPI_DCR2_WRAPSIZE_Pos) /*!< 0x00040000 */
19078
19079 /**************** Bit definition for OCTOSPI_DCR3 register ******************/
19080 #define OCTOSPI_DCR3_MAXTRAN_Pos (0U)
19081 #define OCTOSPI_DCR3_MAXTRAN_Msk (0xFFUL << OCTOSPI_DCR3_MAXTRAN_Pos) /*!< 0x000000FF */
19082 #define OCTOSPI_DCR3_MAXTRAN OCTOSPI_DCR3_MAXTRAN_Msk /*!< Maximum Transfer */
19083 #define OCTOSPI_DCR3_CSBOUND_Pos (16U)
19084 #define OCTOSPI_DCR3_CSBOUND_Msk (0x1FUL << OCTOSPI_DCR3_CSBOUND_Pos) /*!< 0x001F0000 */
19085 #define OCTOSPI_DCR3_CSBOUND OCTOSPI_DCR3_CSBOUND_Msk /*!< CS Boundary */
19086
19087 /**************** Bit definition for OCTOSPI_DCR4 register ******************/
19088 #define OCTOSPI_DCR4_REFRESH_Pos (0U)
19089 #define OCTOSPI_DCR4_REFRESH_Msk (0xFFFFFFFFUL << OCTOSPI_DCR4_REFRESH_Pos) /*!< 0xFFFFFFFF */
19090 #define OCTOSPI_DCR4_REFRESH OCTOSPI_DCR4_REFRESH_Msk /*!< Refresh rate */
19091
19092 /***************** Bit definition for OCTOSPI_SR register *******************/
19093 #define OCTOSPI_SR_TEF_Pos (0U)
19094 #define OCTOSPI_SR_TEF_Msk (0x1UL << OCTOSPI_SR_TEF_Pos) /*!< 0x00000001 */
19095 #define OCTOSPI_SR_TEF OCTOSPI_SR_TEF_Msk /*!< Transfer Error Flag */
19096 #define OCTOSPI_SR_TCF_Pos (1U)
19097 #define OCTOSPI_SR_TCF_Msk (0x1UL << OCTOSPI_SR_TCF_Pos) /*!< 0x00000002 */
19098 #define OCTOSPI_SR_TCF OCTOSPI_SR_TCF_Msk /*!< Transfer Complete Flag */
19099 #define OCTOSPI_SR_FTF_Pos (2U)
19100 #define OCTOSPI_SR_FTF_Msk (0x1UL << OCTOSPI_SR_FTF_Pos) /*!< 0x00000004 */
19101 #define OCTOSPI_SR_FTF OCTOSPI_SR_FTF_Msk /*!< FIFO Threshold Flag */
19102 #define OCTOSPI_SR_SMF_Pos (3U)
19103 #define OCTOSPI_SR_SMF_Msk (0x1UL << OCTOSPI_SR_SMF_Pos) /*!< 0x00000008 */
19104 #define OCTOSPI_SR_SMF OCTOSPI_SR_SMF_Msk /*!< Status Match Flag */
19105 #define OCTOSPI_SR_TOF_Pos (4U)
19106 #define OCTOSPI_SR_TOF_Msk (0x1UL << OCTOSPI_SR_TOF_Pos) /*!< 0x00000010 */
19107 #define OCTOSPI_SR_TOF OCTOSPI_SR_TOF_Msk /*!< Timeout Flag */
19108 #define OCTOSPI_SR_BUSY_Pos (5U)
19109 #define OCTOSPI_SR_BUSY_Msk (0x1UL << OCTOSPI_SR_BUSY_Pos) /*!< 0x00000020 */
19110 #define OCTOSPI_SR_BUSY OCTOSPI_SR_BUSY_Msk /*!< Busy */
19111 #define OCTOSPI_SR_FLEVEL_Pos (8U)
19112 #define OCTOSPI_SR_FLEVEL_Msk (0x3FUL << OCTOSPI_SR_FLEVEL_Pos) /*!< 0x00003F00 */
19113 #define OCTOSPI_SR_FLEVEL OCTOSPI_SR_FLEVEL_Msk /*!< FIFO Level */
19114
19115 /**************** Bit definition for OCTOSPI_FCR register *******************/
19116 #define OCTOSPI_FCR_CTEF_Pos (0U)
19117 #define OCTOSPI_FCR_CTEF_Msk (0x1UL << OCTOSPI_FCR_CTEF_Pos) /*!< 0x00000001 */
19118 #define OCTOSPI_FCR_CTEF OCTOSPI_FCR_CTEF_Msk /*!< Clear Transfer Error Flag */
19119 #define OCTOSPI_FCR_CTCF_Pos (1U)
19120 #define OCTOSPI_FCR_CTCF_Msk (0x1UL << OCTOSPI_FCR_CTCF_Pos) /*!< 0x00000002 */
19121 #define OCTOSPI_FCR_CTCF OCTOSPI_FCR_CTCF_Msk /*!< Clear Transfer Complete Flag */
19122 #define OCTOSPI_FCR_CSMF_Pos (3U)
19123 #define OCTOSPI_FCR_CSMF_Msk (0x1UL << OCTOSPI_FCR_CSMF_Pos) /*!< 0x00000008 */
19124 #define OCTOSPI_FCR_CSMF OCTOSPI_FCR_CSMF_Msk /*!< Clear Status Match Flag */
19125 #define OCTOSPI_FCR_CTOF_Pos (4U)
19126 #define OCTOSPI_FCR_CTOF_Msk (0x1UL << OCTOSPI_FCR_CTOF_Pos) /*!< 0x00000010 */
19127 #define OCTOSPI_FCR_CTOF OCTOSPI_FCR_CTOF_Msk /*!< Clear Timeout Flag */
19128
19129 /**************** Bit definition for OCTOSPI_DLR register *******************/
19130 #define OCTOSPI_DLR_DL_Pos (0U)
19131 #define OCTOSPI_DLR_DL_Msk (0xFFFFFFFFUL << OCTOSPI_DLR_DL_Pos) /*!< 0xFFFFFFFF */
19132 #define OCTOSPI_DLR_DL OCTOSPI_DLR_DL_Msk /*!< Data Length */
19133
19134 /***************** Bit definition for OCTOSPI_AR register *******************/
19135 #define OCTOSPI_AR_ADDRESS_Pos (0U)
19136 #define OCTOSPI_AR_ADDRESS_Msk (0xFFFFFFFFUL << OCTOSPI_AR_ADDRESS_Pos) /*!< 0xFFFFFFFF */
19137 #define OCTOSPI_AR_ADDRESS OCTOSPI_AR_ADDRESS_Msk /*!< Address */
19138
19139 /***************** Bit definition for OCTOSPI_DR register *******************/
19140 #define OCTOSPI_DR_DATA_Pos (0U)
19141 #define OCTOSPI_DR_DATA_Msk (0xFFFFFFFFUL << OCTOSPI_DR_DATA_Pos) /*!< 0xFFFFFFFF */
19142 #define OCTOSPI_DR_DATA OCTOSPI_DR_DATA_Msk /*!< Data */
19143
19144 /*************** Bit definition for OCTOSPI_PSMKR register ******************/
19145 #define OCTOSPI_PSMKR_MASK_Pos (0U)
19146 #define OCTOSPI_PSMKR_MASK_Msk (0xFFFFFFFFUL << OCTOSPI_PSMKR_MASK_Pos) /*!< 0xFFFFFFFF */
19147 #define OCTOSPI_PSMKR_MASK OCTOSPI_PSMKR_MASK_Msk /*!< Status mask */
19148
19149 /*************** Bit definition for OCTOSPI_PSMAR register ******************/
19150 #define OCTOSPI_PSMAR_MATCH_Pos (0U)
19151 #define OCTOSPI_PSMAR_MATCH_Msk (0xFFFFFFFFUL << OCTOSPI_PSMAR_MATCH_Pos) /*!< 0xFFFFFFFF */
19152 #define OCTOSPI_PSMAR_MATCH OCTOSPI_PSMAR_MATCH_Msk /*!< Status match */
19153
19154 /**************** Bit definition for OCTOSPI_PIR register *******************/
19155 #define OCTOSPI_PIR_INTERVAL_Pos (0U)
19156 #define OCTOSPI_PIR_INTERVAL_Msk (0xFFFFUL << OCTOSPI_PIR_INTERVAL_Pos) /*!< 0x0000FFFF */
19157 #define OCTOSPI_PIR_INTERVAL OCTOSPI_PIR_INTERVAL_Msk /*!< Polling Interval */
19158
19159 /**************** Bit definition for OCTOSPI_CCR register *******************/
19160 #define OCTOSPI_CCR_IMODE_Pos (0U)
19161 #define OCTOSPI_CCR_IMODE_Msk (0x7UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000007 */
19162 #define OCTOSPI_CCR_IMODE OCTOSPI_CCR_IMODE_Msk /*!< Instruction Mode */
19163 #define OCTOSPI_CCR_IMODE_0 (0x1UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000001 */
19164 #define OCTOSPI_CCR_IMODE_1 (0x2UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000002 */
19165 #define OCTOSPI_CCR_IMODE_2 (0x4UL << OCTOSPI_CCR_IMODE_Pos) /*!< 0x00000004 */
19166 #define OCTOSPI_CCR_IDTR_Pos (3U)
19167 #define OCTOSPI_CCR_IDTR_Msk (0x1UL << OCTOSPI_CCR_IDTR_Pos) /*!< 0x00000008 */
19168 #define OCTOSPI_CCR_IDTR OCTOSPI_CCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
19169 #define OCTOSPI_CCR_ISIZE_Pos (4U)
19170 #define OCTOSPI_CCR_ISIZE_Msk (0x3UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000030 */
19171 #define OCTOSPI_CCR_ISIZE OCTOSPI_CCR_ISIZE_Msk /*!< Instruction Size */
19172 #define OCTOSPI_CCR_ISIZE_0 (0x1UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000010 */
19173 #define OCTOSPI_CCR_ISIZE_1 (0x2UL << OCTOSPI_CCR_ISIZE_Pos) /*!< 0x00000020 */
19174 #define OCTOSPI_CCR_ADMODE_Pos (8U)
19175 #define OCTOSPI_CCR_ADMODE_Msk (0x7UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000700 */
19176 #define OCTOSPI_CCR_ADMODE OCTOSPI_CCR_ADMODE_Msk /*!< Address Mode */
19177 #define OCTOSPI_CCR_ADMODE_0 (0x1UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000100 */
19178 #define OCTOSPI_CCR_ADMODE_1 (0x2UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000200 */
19179 #define OCTOSPI_CCR_ADMODE_2 (0x4UL << OCTOSPI_CCR_ADMODE_Pos) /*!< 0x00000400 */
19180 #define OCTOSPI_CCR_ADDTR_Pos (11U)
19181 #define OCTOSPI_CCR_ADDTR_Msk (0x1UL << OCTOSPI_CCR_ADDTR_Pos) /*!< 0x00000800 */
19182 #define OCTOSPI_CCR_ADDTR OCTOSPI_CCR_ADDTR_Msk /*!< Address Double Transfer Rate */
19183 #define OCTOSPI_CCR_ADSIZE_Pos (12U)
19184 #define OCTOSPI_CCR_ADSIZE_Msk (0x3UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00003000 */
19185 #define OCTOSPI_CCR_ADSIZE OCTOSPI_CCR_ADSIZE_Msk /*!< Address Size */
19186 #define OCTOSPI_CCR_ADSIZE_0 (0x1UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00001000 */
19187 #define OCTOSPI_CCR_ADSIZE_1 (0x2UL << OCTOSPI_CCR_ADSIZE_Pos) /*!< 0x00002000 */
19188 #define OCTOSPI_CCR_ABMODE_Pos (16U)
19189 #define OCTOSPI_CCR_ABMODE_Msk (0x7UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00070000 */
19190 #define OCTOSPI_CCR_ABMODE OCTOSPI_CCR_ABMODE_Msk /*!< Alternate Bytes Mode */
19191 #define OCTOSPI_CCR_ABMODE_0 (0x1UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00010000 */
19192 #define OCTOSPI_CCR_ABMODE_1 (0x2UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00020000 */
19193 #define OCTOSPI_CCR_ABMODE_2 (0x4UL << OCTOSPI_CCR_ABMODE_Pos) /*!< 0x00040000 */
19194 #define OCTOSPI_CCR_ABDTR_Pos (19U)
19195 #define OCTOSPI_CCR_ABDTR_Msk (0x1UL << OCTOSPI_CCR_ABDTR_Pos) /*!< 0x00080000 */
19196 #define OCTOSPI_CCR_ABDTR OCTOSPI_CCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
19197 #define OCTOSPI_CCR_ABSIZE_Pos (20U)
19198 #define OCTOSPI_CCR_ABSIZE_Msk (0x3UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00300000 */
19199 #define OCTOSPI_CCR_ABSIZE OCTOSPI_CCR_ABSIZE_Msk /*!< Alternate Bytes Size */
19200 #define OCTOSPI_CCR_ABSIZE_0 (0x1UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00100000 */
19201 #define OCTOSPI_CCR_ABSIZE_1 (0x2UL << OCTOSPI_CCR_ABSIZE_Pos) /*!< 0x00200000 */
19202 #define OCTOSPI_CCR_DMODE_Pos (24U)
19203 #define OCTOSPI_CCR_DMODE_Msk (0x7UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x07000000 */
19204 #define OCTOSPI_CCR_DMODE OCTOSPI_CCR_DMODE_Msk /*!< Data Mode */
19205 #define OCTOSPI_CCR_DMODE_0 (0x1UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x01000000 */
19206 #define OCTOSPI_CCR_DMODE_1 (0x2UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x02000000 */
19207 #define OCTOSPI_CCR_DMODE_2 (0x4UL << OCTOSPI_CCR_DMODE_Pos) /*!< 0x04000000 */
19208 #define OCTOSPI_CCR_DDTR_Pos (27U)
19209 #define OCTOSPI_CCR_DDTR_Msk (0x1UL << OCTOSPI_CCR_DDTR_Pos) /*!< 0x08000000 */
19210 #define OCTOSPI_CCR_DDTR OCTOSPI_CCR_DDTR_Msk /*!< Data Double Transfer Rate */
19211 #define OCTOSPI_CCR_DQSE_Pos (29U)
19212 #define OCTOSPI_CCR_DQSE_Msk (0x1UL << OCTOSPI_CCR_DQSE_Pos) /*!< 0x20000000 */
19213 #define OCTOSPI_CCR_DQSE OCTOSPI_CCR_DQSE_Msk /*!< DQS Enable */
19214 #define OCTOSPI_CCR_SIOO_Pos (31U)
19215 #define OCTOSPI_CCR_SIOO_Msk (0x1UL << OCTOSPI_CCR_SIOO_Pos) /*!< 0x80000000 */
19216 #define OCTOSPI_CCR_SIOO OCTOSPI_CCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
19217
19218 /**************** Bit definition for OCTOSPI_TCR register *******************/
19219 #define OCTOSPI_TCR_DCYC_Pos (0U)
19220 #define OCTOSPI_TCR_DCYC_Msk (0x1FUL << OCTOSPI_TCR_DCYC_Pos) /*!< 0x0000001F */
19221 #define OCTOSPI_TCR_DCYC OCTOSPI_TCR_DCYC_Msk /*!< Number of Dummy Cycles */
19222 #define OCTOSPI_TCR_DHQC_Pos (28U)
19223 #define OCTOSPI_TCR_DHQC_Msk (0x1UL << OCTOSPI_TCR_DHQC_Pos) /*!< 0x10000000 */
19224 #define OCTOSPI_TCR_DHQC OCTOSPI_TCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
19225 #define OCTOSPI_TCR_SSHIFT_Pos (30U)
19226 #define OCTOSPI_TCR_SSHIFT_Msk (0x1UL << OCTOSPI_TCR_SSHIFT_Pos) /*!< 0x40000000 */
19227 #define OCTOSPI_TCR_SSHIFT OCTOSPI_TCR_SSHIFT_Msk /*!< Sample Shift */
19228
19229 /***************** Bit definition for OCTOSPI_IR register *******************/
19230 #define OCTOSPI_IR_INSTRUCTION_Pos (0U)
19231 #define OCTOSPI_IR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_IR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19232 #define OCTOSPI_IR_INSTRUCTION OCTOSPI_IR_INSTRUCTION_Msk /*!< Instruction */
19233
19234 /**************** Bit definition for OCTOSPI_ABR register *******************/
19235 #define OCTOSPI_ABR_ALTERNATE_Pos (0U)
19236 #define OCTOSPI_ABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_ABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19237 #define OCTOSPI_ABR_ALTERNATE OCTOSPI_ABR_ALTERNATE_Msk /*!< Alternate Bytes */
19238
19239 /**************** Bit definition for OCTOSPI_LPTR register ******************/
19240 #define OCTOSPI_LPTR_TIMEOUT_Pos (0U)
19241 #define OCTOSPI_LPTR_TIMEOUT_Msk (0xFFFFUL << OCTOSPI_LPTR_TIMEOUT_Pos) /*!< 0x0000FFFF */
19242 #define OCTOSPI_LPTR_TIMEOUT OCTOSPI_LPTR_TIMEOUT_Msk /*!< Timeout period */
19243
19244 /**************** Bit definition for OCTOSPI_WPCCR register *******************/
19245 #define OCTOSPI_WPCCR_IMODE_Pos (0U)
19246 #define OCTOSPI_WPCCR_IMODE_Msk (0x7UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000007 */
19247 #define OCTOSPI_WPCCR_IMODE OCTOSPI_WPCCR_IMODE_Msk /*!< Instruction Mode */
19248 #define OCTOSPI_WPCCR_IMODE_0 (0x1UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000001 */
19249 #define OCTOSPI_WPCCR_IMODE_1 (0x2UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000002 */
19250 #define OCTOSPI_WPCCR_IMODE_2 (0x4UL << OCTOSPI_WPCCR_IMODE_Pos) /*!< 0x00000004 */
19251 #define OCTOSPI_WPCCR_IDTR_Pos (3U)
19252 #define OCTOSPI_WPCCR_IDTR_Msk (0x1UL << OCTOSPI_WPCCR_IDTR_Pos) /*!< 0x00000008 */
19253 #define OCTOSPI_WPCCR_IDTR OCTOSPI_WPCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
19254 #define OCTOSPI_WPCCR_ISIZE_Pos (4U)
19255 #define OCTOSPI_WPCCR_ISIZE_Msk (0x3UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000030 */
19256 #define OCTOSPI_WPCCR_ISIZE OCTOSPI_WPCCR_ISIZE_Msk /*!< Instruction Size */
19257 #define OCTOSPI_WPCCR_ISIZE_0 (0x1UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000010 */
19258 #define OCTOSPI_WPCCR_ISIZE_1 (0x2UL << OCTOSPI_WPCCR_ISIZE_Pos) /*!< 0x00000020 */
19259 #define OCTOSPI_WPCCR_ADMODE_Pos (8U)
19260 #define OCTOSPI_WPCCR_ADMODE_Msk (0x7UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000700 */
19261 #define OCTOSPI_WPCCR_ADMODE OCTOSPI_WPCCR_ADMODE_Msk /*!< Address Mode */
19262 #define OCTOSPI_WPCCR_ADMODE_0 (0x1UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000100 */
19263 #define OCTOSPI_WPCCR_ADMODE_1 (0x2UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000200 */
19264 #define OCTOSPI_WPCCR_ADMODE_2 (0x4UL << OCTOSPI_WPCCR_ADMODE_Pos) /*!< 0x00000400 */
19265 #define OCTOSPI_WPCCR_ADDTR_Pos (11U)
19266 #define OCTOSPI_WPCCR_ADDTR_Msk (0x1UL << OCTOSPI_WPCCR_ADDTR_Pos) /*!< 0x00000800 */
19267 #define OCTOSPI_WPCCR_ADDTR OCTOSPI_WPCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
19268 #define OCTOSPI_WPCCR_ADSIZE_Pos (12U)
19269 #define OCTOSPI_WPCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00003000 */
19270 #define OCTOSPI_WPCCR_ADSIZE OCTOSPI_WPCCR_ADSIZE_Msk /*!< Address Size */
19271 #define OCTOSPI_WPCCR_ADSIZE_0 (0x1UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00001000 */
19272 #define OCTOSPI_WPCCR_ADSIZE_1 (0x2UL << OCTOSPI_WPCCR_ADSIZE_Pos) /*!< 0x00002000 */
19273 #define OCTOSPI_WPCCR_ABMODE_Pos (16U)
19274 #define OCTOSPI_WPCCR_ABMODE_Msk (0x7UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00070000 */
19275 #define OCTOSPI_WPCCR_ABMODE OCTOSPI_WPCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
19276 #define OCTOSPI_WPCCR_ABMODE_0 (0x1UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00010000 */
19277 #define OCTOSPI_WPCCR_ABMODE_1 (0x2UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00020000 */
19278 #define OCTOSPI_WPCCR_ABMODE_2 (0x4UL << OCTOSPI_WPCCR_ABMODE_Pos) /*!< 0x00040000 */
19279 #define OCTOSPI_WPCCR_ABDTR_Pos (19U)
19280 #define OCTOSPI_WPCCR_ABDTR_Msk (0x1UL << OCTOSPI_WPCCR_ABDTR_Pos) /*!< 0x00080000 */
19281 #define OCTOSPI_WPCCR_ABDTR OCTOSPI_WPCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
19282 #define OCTOSPI_WPCCR_ABSIZE_Pos (20U)
19283 #define OCTOSPI_WPCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00300000 */
19284 #define OCTOSPI_WPCCR_ABSIZE OCTOSPI_WPCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
19285 #define OCTOSPI_WPCCR_ABSIZE_0 (0x1UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00100000 */
19286 #define OCTOSPI_WPCCR_ABSIZE_1 (0x2UL << OCTOSPI_WPCCR_ABSIZE_Pos) /*!< 0x00200000 */
19287 #define OCTOSPI_WPCCR_DMODE_Pos (24U)
19288 #define OCTOSPI_WPCCR_DMODE_Msk (0x7UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x07000000 */
19289 #define OCTOSPI_WPCCR_DMODE OCTOSPI_WPCCR_DMODE_Msk /*!< Data Mode */
19290 #define OCTOSPI_WPCCR_DMODE_0 (0x1UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x01000000 */
19291 #define OCTOSPI_WPCCR_DMODE_1 (0x2UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x02000000 */
19292 #define OCTOSPI_WPCCR_DMODE_2 (0x4UL << OCTOSPI_WPCCR_DMODE_Pos) /*!< 0x04000000 */
19293 #define OCTOSPI_WPCCR_DDTR_Pos (27U)
19294 #define OCTOSPI_WPCCR_DDTR_Msk (0x1UL << OCTOSPI_WPCCR_DDTR_Pos) /*!< 0x08000000 */
19295 #define OCTOSPI_WPCCR_DDTR OCTOSPI_WPCCR_DDTR_Msk /*!< Data Double Transfer Rate */
19296 #define OCTOSPI_WPCCR_DQSE_Pos (29U)
19297 #define OCTOSPI_WPCCR_DQSE_Msk (0x1UL << OCTOSPI_WPCCR_DQSE_Pos) /*!< 0x20000000 */
19298 #define OCTOSPI_WPCCR_DQSE OCTOSPI_WPCCR_DQSE_Msk /*!< DQS Enable */
19299 #define OCTOSPI_WPCCR_SIOO_Pos (31U)
19300 #define OCTOSPI_WPCCR_SIOO_Msk (0x1UL << OCTOSPI_WPCCR_SIOO_Pos) /*!< 0x80000000 */
19301 #define OCTOSPI_WPCCR_SIOO OCTOSPI_WPCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
19302
19303 /**************** Bit definition for OCTOSPI_WPTCR register *******************/
19304 #define OCTOSPI_WPTCR_DCYC_Pos (0U)
19305 #define OCTOSPI_WPTCR_DCYC_Msk (0x1FUL << OCTOSPI_WPTCR_DCYC_Pos) /*!< 0x0000001F */
19306 #define OCTOSPI_WPTCR_DCYC OCTOSPI_WPTCR_DCYC_Msk /*!< Number of Dummy Cycles */
19307 #define OCTOSPI_WPTCR_DHQC_Pos (28U)
19308 #define OCTOSPI_WPTCR_DHQC_Msk (0x1UL << OCTOSPI_WPTCR_DHQC_Pos) /*!< 0x10000000 */
19309 #define OCTOSPI_WPTCR_DHQC OCTOSPI_WPTCR_DHQC_Msk /*!< Delay Hold Quarter Cycle */
19310 #define OCTOSPI_WPTCR_SSHIFT_Pos (30U)
19311 #define OCTOSPI_WPTCR_SSHIFT_Msk (0x1UL << OCTOSPI_WPTCR_SSHIFT_Pos) /*!< 0x40000000 */
19312 #define OCTOSPI_WPTCR_SSHIFT OCTOSPI_WPTCR_SSHIFT_Msk /*!< Sample Shift */
19313
19314 /***************** Bit definition for OCTOSPI_WPIR register *******************/
19315 #define OCTOSPI_WPIR_INSTRUCTION_Pos (0U)
19316 #define OCTOSPI_WPIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WPIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19317 #define OCTOSPI_WPIR_INSTRUCTION OCTOSPI_WPIR_INSTRUCTION_Msk /*!< Instruction */
19318
19319 /**************** Bit definition for OCTOSPI_WPABR register *******************/
19320 #define OCTOSPI_WPABR_ALTERNATE_Pos (0U)
19321 #define OCTOSPI_WPABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WPABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19322 #define OCTOSPI_WPABR_ALTERNATE OCTOSPI_WPABR_ALTERNATE_Msk /*!< Alternate Bytes */
19323
19324 /**************** Bit definition for OCTOSPI_WCCR register ******************/
19325 #define OCTOSPI_WCCR_IMODE_Pos (0U)
19326 #define OCTOSPI_WCCR_IMODE_Msk (0x7UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000007 */
19327 #define OCTOSPI_WCCR_IMODE OCTOSPI_WCCR_IMODE_Msk /*!< Instruction Mode */
19328 #define OCTOSPI_WCCR_IMODE_0 (0x1UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000001 */
19329 #define OCTOSPI_WCCR_IMODE_1 (0x2UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000002 */
19330 #define OCTOSPI_WCCR_IMODE_2 (0x4UL << OCTOSPI_WCCR_IMODE_Pos) /*!< 0x00000004 */
19331 #define OCTOSPI_WCCR_IDTR_Pos (3U)
19332 #define OCTOSPI_WCCR_IDTR_Msk (0x1UL << OCTOSPI_WCCR_IDTR_Pos) /*!< 0x00000008 */
19333 #define OCTOSPI_WCCR_IDTR OCTOSPI_WCCR_IDTR_Msk /*!< Instruction Double Transfer Rate */
19334 #define OCTOSPI_WCCR_ISIZE_Pos (4U)
19335 #define OCTOSPI_WCCR_ISIZE_Msk (0x3UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000030 */
19336 #define OCTOSPI_WCCR_ISIZE OCTOSPI_WCCR_ISIZE_Msk /*!< Instruction Size */
19337 #define OCTOSPI_WCCR_ISIZE_0 (0x1UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000010 */
19338 #define OCTOSPI_WCCR_ISIZE_1 (0x2UL << OCTOSPI_WCCR_ISIZE_Pos) /*!< 0x00000020 */
19339 #define OCTOSPI_WCCR_ADMODE_Pos (8U)
19340 #define OCTOSPI_WCCR_ADMODE_Msk (0x7UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000700 */
19341 #define OCTOSPI_WCCR_ADMODE OCTOSPI_WCCR_ADMODE_Msk /*!< Address Mode */
19342 #define OCTOSPI_WCCR_ADMODE_0 (0x1UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000100 */
19343 #define OCTOSPI_WCCR_ADMODE_1 (0x2UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000200 */
19344 #define OCTOSPI_WCCR_ADMODE_2 (0x4UL << OCTOSPI_WCCR_ADMODE_Pos) /*!< 0x00000400 */
19345 #define OCTOSPI_WCCR_ADDTR_Pos (11U)
19346 #define OCTOSPI_WCCR_ADDTR_Msk (0x1UL << OCTOSPI_WCCR_ADDTR_Pos) /*!< 0x00000800 */
19347 #define OCTOSPI_WCCR_ADDTR OCTOSPI_WCCR_ADDTR_Msk /*!< Address Double Transfer Rate */
19348 #define OCTOSPI_WCCR_ADSIZE_Pos (12U)
19349 #define OCTOSPI_WCCR_ADSIZE_Msk (0x3UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00003000 */
19350 #define OCTOSPI_WCCR_ADSIZE OCTOSPI_WCCR_ADSIZE_Msk /*!< Address Size */
19351 #define OCTOSPI_WCCR_ADSIZE_0 (0x1UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00001000 */
19352 #define OCTOSPI_WCCR_ADSIZE_1 (0x2UL << OCTOSPI_WCCR_ADSIZE_Pos) /*!< 0x00002000 */
19353 #define OCTOSPI_WCCR_ABMODE_Pos (16U)
19354 #define OCTOSPI_WCCR_ABMODE_Msk (0x7UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00070000 */
19355 #define OCTOSPI_WCCR_ABMODE OCTOSPI_WCCR_ABMODE_Msk /*!< Alternate Bytes Mode */
19356 #define OCTOSPI_WCCR_ABMODE_0 (0x1UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00010000 */
19357 #define OCTOSPI_WCCR_ABMODE_1 (0x2UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00020000 */
19358 #define OCTOSPI_WCCR_ABMODE_2 (0x4UL << OCTOSPI_WCCR_ABMODE_Pos) /*!< 0x00040000 */
19359 #define OCTOSPI_WCCR_ABDTR_Pos (19U)
19360 #define OCTOSPI_WCCR_ABDTR_Msk (0x1UL << OCTOSPI_WCCR_ABDTR_Pos) /*!< 0x00080000 */
19361 #define OCTOSPI_WCCR_ABDTR OCTOSPI_WCCR_ABDTR_Msk /*!< Alternate Bytes Double Transfer Rate */
19362 #define OCTOSPI_WCCR_ABSIZE_Pos (20U)
19363 #define OCTOSPI_WCCR_ABSIZE_Msk (0x3UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00300000 */
19364 #define OCTOSPI_WCCR_ABSIZE OCTOSPI_WCCR_ABSIZE_Msk /*!< Alternate Bytes Size */
19365 #define OCTOSPI_WCCR_ABSIZE_0 (0x1UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00100000 */
19366 #define OCTOSPI_WCCR_ABSIZE_1 (0x2UL << OCTOSPI_WCCR_ABSIZE_Pos) /*!< 0x00200000 */
19367 #define OCTOSPI_WCCR_DMODE_Pos (24U)
19368 #define OCTOSPI_WCCR_DMODE_Msk (0x7UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x07000000 */
19369 #define OCTOSPI_WCCR_DMODE OCTOSPI_WCCR_DMODE_Msk /*!< Data Mode */
19370 #define OCTOSPI_WCCR_DMODE_0 (0x1UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x01000000 */
19371 #define OCTOSPI_WCCR_DMODE_1 (0x2UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x02000000 */
19372 #define OCTOSPI_WCCR_DMODE_2 (0x4UL << OCTOSPI_WCCR_DMODE_Pos) /*!< 0x04000000 */
19373 #define OCTOSPI_WCCR_DDTR_Pos (27U)
19374 #define OCTOSPI_WCCR_DDTR_Msk (0x1UL << OCTOSPI_WCCR_DDTR_Pos) /*!< 0x08000000 */
19375 #define OCTOSPI_WCCR_DDTR OCTOSPI_WCCR_DDTR_Msk /*!< Data Double Transfer Rate */
19376 #define OCTOSPI_WCCR_DQSE_Pos (29U)
19377 #define OCTOSPI_WCCR_DQSE_Msk (0x1UL << OCTOSPI_WCCR_DQSE_Pos) /*!< 0x20000000 */
19378 #define OCTOSPI_WCCR_DQSE OCTOSPI_WCCR_DQSE_Msk /*!< DQS Enable */
19379 #define OCTOSPI_WCCR_SIOO_Pos (31U)
19380 #define OCTOSPI_WCCR_SIOO_Msk (0x1UL << OCTOSPI_WCCR_SIOO_Pos) /*!< 0x80000000 */
19381 #define OCTOSPI_WCCR_SIOO OCTOSPI_WCCR_SIOO_Msk /*!< Send Instruction Only Once Mode */
19382
19383 /**************** Bit definition for OCTOSPI_WTCR register ******************/
19384 #define OCTOSPI_WTCR_DCYC_Pos (0U)
19385 #define OCTOSPI_WTCR_DCYC_Msk (0x1FUL << OCTOSPI_WTCR_DCYC_Pos) /*!< 0x0000001F */
19386 #define OCTOSPI_WTCR_DCYC OCTOSPI_WTCR_DCYC_Msk /*!< Number of Dummy Cycles */
19387
19388 /**************** Bit definition for OCTOSPI_WIR register *******************/
19389 #define OCTOSPI_WIR_INSTRUCTION_Pos (0U)
19390 #define OCTOSPI_WIR_INSTRUCTION_Msk (0xFFFFFFFFUL << OCTOSPI_WIR_INSTRUCTION_Pos) /*!< 0xFFFFFFFF */
19391 #define OCTOSPI_WIR_INSTRUCTION OCTOSPI_WIR_INSTRUCTION_Msk /*!< Instruction */
19392
19393 /**************** Bit definition for OCTOSPI_WABR register ******************/
19394 #define OCTOSPI_WABR_ALTERNATE_Pos (0U)
19395 #define OCTOSPI_WABR_ALTERNATE_Msk (0xFFFFFFFFUL << OCTOSPI_WABR_ALTERNATE_Pos) /*!< 0xFFFFFFFF */
19396 #define OCTOSPI_WABR_ALTERNATE OCTOSPI_WABR_ALTERNATE_Msk /*!< Alternate Bytes */
19397
19398 /**************** Bit definition for OCTOSPI_HLCR register ******************/
19399 #define OCTOSPI_HLCR_LM_Pos (0U)
19400 #define OCTOSPI_HLCR_LM_Msk (0x1UL << OCTOSPI_HLCR_LM_Pos) /*!< 0x00000001 */
19401 #define OCTOSPI_HLCR_LM OCTOSPI_HLCR_LM_Msk /*!< Latency Mode */
19402 #define OCTOSPI_HLCR_WZL_Pos (1U)
19403 #define OCTOSPI_HLCR_WZL_Msk (0x1UL << OCTOSPI_HLCR_WZL_Pos) /*!< 0x00000002 */
19404 #define OCTOSPI_HLCR_WZL OCTOSPI_HLCR_WZL_Msk /*!< Write Zero Latency */
19405 #define OCTOSPI_HLCR_TACC_Pos (8U)
19406 #define OCTOSPI_HLCR_TACC_Msk (0xFFUL << OCTOSPI_HLCR_TACC_Pos) /*!< 0x0000FF00 */
19407 #define OCTOSPI_HLCR_TACC OCTOSPI_HLCR_TACC_Msk /*!< Access Time */
19408 #define OCTOSPI_HLCR_TRWR_Pos (16U)
19409 #define OCTOSPI_HLCR_TRWR_Msk (0xFFUL << OCTOSPI_HLCR_TRWR_Pos) /*!< 0x00FF0000 */
19410 #define OCTOSPI_HLCR_TRWR OCTOSPI_HLCR_TRWR_Msk /*!< Read Write Recovery Time */
19411
19412 /**************** Bit definition for OCTOSPI_VER register *******************/
19413 #define OCTOSPI_VER_VER_Pos (0U)
19414 #define OCTOSPI_VER_VER_Msk (0xFFUL << OCTOSPI_VER_VER_Pos) /*!< 0x000000FF */
19415 #define OCTOSPI_VER_VER OCTOSPI_VER_VER_Msk /*!< Version */
19416
19417 /***************** Bit definition for OCTOSPI_ID register *******************/
19418 #define OCTOSPI_ID_ID_Pos (0U)
19419 #define OCTOSPI_ID_ID_Msk (0xFFFFFFFFUL << OCTOSPI_ID_ID_Pos) /*!< 0xFFFFFFFF */
19420 #define OCTOSPI_ID_ID OCTOSPI_ID_ID_Msk /*!< Identification */
19421
19422 /**************** Bit definition for OCTOSPI_MID register *******************/
19423 #define OCTOSPI_MID_MID_Pos (0U)
19424 #define OCTOSPI_MID_MID_Msk (0xFFFFFFFFUL << OCTOSPI_MID_MID_Pos) /*!< 0xFFFFFFFF */
19425 #define OCTOSPI_MID_MID OCTOSPI_MID_MID_Msk /*!< Magic ID */
19426
19427 /******************************************************************************/
19428 /* */
19429 /* OCTOSPIM */
19430 /* */
19431 /******************************************************************************/
19432 /*************** Bit definition for OCTOSPIM_PCR register *******************/
19433 #define OCTOSPIM_PCR_CLKEN_Pos (0U)
19434 #define OCTOSPIM_PCR_CLKEN_Msk (0x1UL << OCTOSPIM_PCR_CLKEN_Pos) /*!< 0x00000001 */
19435 #define OCTOSPIM_PCR_CLKEN OCTOSPIM_PCR_CLKEN_Msk /*!< CLK/CLKn Enable for Port n */
19436 #define OCTOSPIM_PCR_CLKSRC_Pos (1U)
19437 #define OCTOSPIM_PCR_CLKSRC_Msk (0x1UL << OCTOSPIM_PCR_CLKSRC_Pos) /*!< 0x00000002 */
19438 #define OCTOSPIM_PCR_CLKSRC OCTOSPIM_PCR_CLKSRC_Msk /*!< CLK/CLKn Source for Port n */
19439 #define OCTOSPIM_PCR_DQSEN_Pos (4U)
19440 #define OCTOSPIM_PCR_DQSEN_Msk (0x1UL << OCTOSPIM_PCR_DQSEN_Pos) /*!< 0x00000010 */
19441 #define OCTOSPIM_PCR_DQSEN OCTOSPIM_PCR_DQSEN_Msk /*!< DQS Enable for Port n */
19442 #define OCTOSPIM_PCR_DQSSRC_Pos (5U)
19443 #define OCTOSPIM_PCR_DQSSRC_Msk (0x1UL << OCTOSPIM_PCR_DQSSRC_Pos) /*!< 0x00000020 */
19444 #define OCTOSPIM_PCR_DQSSRC OCTOSPIM_PCR_DQSSRC_Msk /*!< DQS Source for Port n */
19445 #define OCTOSPIM_PCR_NCSEN_Pos (8U)
19446 #define OCTOSPIM_PCR_NCSEN_Msk (0x1UL << OCTOSPIM_PCR_NCSEN_Pos) /*!< 0x00000100 */
19447 #define OCTOSPIM_PCR_NCSEN OCTOSPIM_PCR_NCSEN_Msk /*!< nCS Enable for Port n */
19448 #define OCTOSPIM_PCR_NCSSRC_Pos (9U)
19449 #define OCTOSPIM_PCR_NCSSRC_Msk (0x1UL << OCTOSPIM_PCR_NCSSRC_Pos) /*!< 0x00000200 */
19450 #define OCTOSPIM_PCR_NCSSRC OCTOSPIM_PCR_NCSSRC_Msk /*!< nCS Source for Port n */
19451 #define OCTOSPIM_PCR_IOLEN_Pos (16U)
19452 #define OCTOSPIM_PCR_IOLEN_Msk (0x1UL << OCTOSPIM_PCR_IOLEN_Pos) /*!< 0x00010000 */
19453 #define OCTOSPIM_PCR_IOLEN OCTOSPIM_PCR_IOLEN_Msk /*!< IO[3:0] Enable for Port n */
19454 #define OCTOSPIM_PCR_IOLSRC_Pos (17U)
19455 #define OCTOSPIM_PCR_IOLSRC_Msk (0x3UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00060000 */
19456 #define OCTOSPIM_PCR_IOLSRC OCTOSPIM_PCR_IOLSRC_Msk /*!< IO[3:0] Source for Port n */
19457 #define OCTOSPIM_PCR_IOLSRC_0 (0x1UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00020000 */
19458 #define OCTOSPIM_PCR_IOLSRC_1 (0x2UL << OCTOSPIM_PCR_IOLSRC_Pos) /*!< 0x00040000 */
19459 #define OCTOSPIM_PCR_IOHEN_Pos (24U)
19460 #define OCTOSPIM_PCR_IOHEN_Msk (0x1UL << OCTOSPIM_PCR_IOHEN_Pos) /*!< 0x01000000 */
19461 #define OCTOSPIM_PCR_IOHEN OCTOSPIM_PCR_IOHEN_Msk /*!< IO[7:4] Enable for Port n */
19462 #define OCTOSPIM_PCR_IOHSRC_Pos (25U)
19463 #define OCTOSPIM_PCR_IOHSRC_Msk (0x3UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x06000000 */
19464 #define OCTOSPIM_PCR_IOHSRC OCTOSPIM_PCR_IOHSRC_Msk /*!< IO[7:4] Source for Port n */
19465 #define OCTOSPIM_PCR_IOHSRC_0 (0x1UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x02000000 */
19466 #define OCTOSPIM_PCR_IOHSRC_1 (0x2UL << OCTOSPIM_PCR_IOHSRC_Pos) /*!< 0x04000000 */
19467 /******************************************************************************/
19468 /* */
19469 /* Analog Comparators (COMP) */
19470 /* */
19471 /******************************************************************************/
19472
19473 /******************* Bit definition for COMP_SR register ********************/
19474 #define COMP_SR_C1VAL_Pos (0U)
19475 #define COMP_SR_C1VAL_Msk (0x1UL << COMP_SR_C1VAL_Pos) /*!< 0x00000001 */
19476 #define COMP_SR_C1VAL COMP_SR_C1VAL_Msk
19477 #define COMP_SR_C2VAL_Pos (1U)
19478 #define COMP_SR_C2VAL_Msk (0x1UL << COMP_SR_C2VAL_Pos) /*!< 0x00000002 */
19479 #define COMP_SR_C2VAL COMP_SR_C2VAL_Msk
19480 #define COMP_SR_C1IF_Pos (16U)
19481 #define COMP_SR_C1IF_Msk (0x1UL << COMP_SR_C1IF_Pos) /*!< 0x00010000 */
19482 #define COMP_SR_C1IF COMP_SR_C1IF_Msk
19483 #define COMP_SR_C2IF_Pos (17U)
19484 #define COMP_SR_C2IF_Msk (0x1UL << COMP_SR_C2IF_Pos) /*!< 0x00020000 */
19485 #define COMP_SR_C2IF COMP_SR_C2IF_Msk
19486 /******************* Bit definition for COMP_ICFR register ********************/
19487 #define COMP_ICFR_C1IF_Pos (16U)
19488 #define COMP_ICFR_C1IF_Msk (0x1UL << COMP_ICFR_C1IF_Pos) /*!< 0x00010000 */
19489 #define COMP_ICFR_C1IF COMP_ICFR_C1IF_Msk
19490 #define COMP_ICFR_C2IF_Pos (17U)
19491 #define COMP_ICFR_C2IF_Msk (0x1UL << COMP_ICFR_C2IF_Pos) /*!< 0x00020000 */
19492 #define COMP_ICFR_C2IF COMP_ICFR_C2IF_Msk
19493 /******************* Bit definition for COMP_OR register ********************/
19494 #define COMP_OR_AFOPA6_Pos (0U)
19495 #define COMP_OR_AFOPA6_Msk (0x1UL << COMP_OR_AFOPA6_Pos) /*!< 0x00000001 */
19496 #define COMP_OR_AFOPA6 COMP_OR_AFOPA6_Msk
19497 #define COMP_OR_AFOPA8_Pos (1U)
19498 #define COMP_OR_AFOPA8_Msk (0x1UL << COMP_OR_AFOPA8_Pos) /*!< 0x00000002 */
19499 #define COMP_OR_AFOPA8 COMP_OR_AFOPA8_Msk
19500 #define COMP_OR_AFOPB12_Pos (2U)
19501 #define COMP_OR_AFOPB12_Msk (0x1UL << COMP_OR_AFOPB12_Pos) /*!< 0x00000004 */
19502 #define COMP_OR_AFOPB12 COMP_OR_AFOPB12_Msk
19503 #define COMP_OR_AFOPE6_Pos (3U)
19504 #define COMP_OR_AFOPE6_Msk (0x1UL << COMP_OR_AFOPE6_Pos) /*!< 0x00000008 */
19505 #define COMP_OR_AFOPE6 COMP_OR_AFOPE6_Msk
19506 #define COMP_OR_AFOPE15_Pos (4U)
19507 #define COMP_OR_AFOPE15_Msk (0x1UL << COMP_OR_AFOPE15_Pos) /*!< 0x00000010 */
19508 #define COMP_OR_AFOPE15 COMP_OR_AFOPE15_Msk
19509 #define COMP_OR_AFOPG2_Pos (5U)
19510 #define COMP_OR_AFOPG2_Msk (0x1UL << COMP_OR_AFOPG2_Pos) /*!< 0x00000020 */
19511 #define COMP_OR_AFOPG2 COMP_OR_AFOPG2_Msk
19512 #define COMP_OR_AFOPG3_Pos (6U)
19513 #define COMP_OR_AFOPG3_Msk (0x1UL << COMP_OR_AFOPG3_Pos) /*!< 0x00000040 */
19514 #define COMP_OR_AFOPG3 COMP_OR_AFOPG3_Msk
19515 #define COMP_OR_AFOPG4_Pos (7U)
19516 #define COMP_OR_AFOPG4_Msk (0x1UL << COMP_OR_AFOPG4_Pos) /*!< 0x00000080 */
19517 #define COMP_OR_AFOPG4 COMP_OR_AFOPG4_Msk
19518 #define COMP_OR_AFOPI1_Pos (8U)
19519 #define COMP_OR_AFOPI1_Msk (0x1UL << COMP_OR_AFOPI1_Pos) /*!< 0x00000100 */
19520 #define COMP_OR_AFOPI1 COMP_OR_AFOPI1_Msk
19521 #define COMP_OR_AFOPI4_Pos (9U)
19522 #define COMP_OR_AFOPI4_Msk (0x1UL << COMP_OR_AFOPI4_Pos) /*!< 0x00000200 */
19523 #define COMP_OR_AFOPI4 COMP_OR_AFOPI4_Msk
19524 #define COMP_OR_AFOPK2_Pos (10U)
19525 #define COMP_OR_AFOPK2_Msk (0x1UL << COMP_OR_AFOPK2_Pos) /*!< 0x00000400 */
19526 #define COMP_OR_AFOPK2 COMP_OR_AFOPK2_Msk
19527
19528 /*!< ****************** Bit definition for COMP_CFGRx register ********************/
19529 #define COMP_CFGRx_EN_Pos (0U)
19530 #define COMP_CFGRx_EN_Msk (0x1UL << COMP_CFGRx_EN_Pos) /*!< 0x00000001 */
19531 #define COMP_CFGRx_EN COMP_CFGRx_EN_Msk /*!< COMPx enable bit */
19532 #define COMP_CFGRx_BRGEN_Pos (1U)
19533 #define COMP_CFGRx_BRGEN_Msk (0x1UL << COMP_CFGRx_BRGEN_Pos) /*!< 0x00000002 */
19534 #define COMP_CFGRx_BRGEN COMP_CFGRx_BRGEN_Msk /*!< COMPx Scaler bridge enable */
19535 #define COMP_CFGRx_SCALEN_Pos (2U)
19536 #define COMP_CFGRx_SCALEN_Msk (0x1UL << COMP_CFGRx_SCALEN_Pos) /*!< 0x00000004 */
19537 #define COMP_CFGRx_SCALEN COMP_CFGRx_SCALEN_Msk /*!< COMPx Voltage scaler enable bit */
19538 #define COMP_CFGRx_POLARITY_Pos (3U)
19539 #define COMP_CFGRx_POLARITY_Msk (0x1UL << COMP_CFGRx_POLARITY_Pos) /*!< 0x00000008 */
19540 #define COMP_CFGRx_POLARITY COMP_CFGRx_POLARITY_Msk /*!< COMPx polarity selection bit */
19541 #define COMP_CFGRx_WINMODE_Pos (4U)
19542 #define COMP_CFGRx_WINMODE_Msk (0x1UL << COMP_CFGRx_WINMODE_Pos) /*!< 0x00000010 */
19543 #define COMP_CFGRx_WINMODE COMP_CFGRx_WINMODE_Msk /*!< COMPx Windows mode selection bit */
19544 #define COMP_CFGRx_ITEN_Pos (6U)
19545 #define COMP_CFGRx_ITEN_Msk (0x1UL << COMP_CFGRx_ITEN_Pos) /*!< 0x00000040 */
19546 #define COMP_CFGRx_ITEN COMP_CFGRx_ITEN_Msk /*!< COMPx interrupt enable */
19547 #define COMP_CFGRx_HYST_Pos (8U)
19548 #define COMP_CFGRx_HYST_Msk (0x3UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000300 */
19549 #define COMP_CFGRx_HYST COMP_CFGRx_HYST_Msk /*!< COMPx hysteresis selection bits */
19550 #define COMP_CFGRx_HYST_0 (0x1UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000100 */
19551 #define COMP_CFGRx_HYST_1 (0x2UL << COMP_CFGRx_HYST_Pos) /*!< 0x00000200 */
19552 #define COMP_CFGRx_PWRMODE_Pos (12U)
19553 #define COMP_CFGRx_PWRMODE_Msk (0x3UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00003000 */
19554 #define COMP_CFGRx_PWRMODE COMP_CFGRx_PWRMODE_Msk /*!< COMPx Power Mode of the comparator */
19555 #define COMP_CFGRx_PWRMODE_0 (0x1UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00001000 */
19556 #define COMP_CFGRx_PWRMODE_1 (0x2UL << COMP_CFGRx_PWRMODE_Pos) /*!< 0x00002000 */
19557 #define COMP_CFGRx_INMSEL_Pos (16U)
19558 #define COMP_CFGRx_INMSEL_Msk (0xFUL << COMP_CFGRx_INMSEL_Pos) /*!< 0x000F0000 */
19559 #define COMP_CFGRx_INMSEL COMP_CFGRx_INMSEL_Msk /*!< COMPx input minus selection bit */
19560 #define COMP_CFGRx_INMSEL_0 (0x1UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00010000 */
19561 #define COMP_CFGRx_INMSEL_1 (0x2UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00020000 */
19562 #define COMP_CFGRx_INMSEL_2 (0x4UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00040000 */
19563 #define COMP_CFGRx_INMSEL_3 (0x8UL << COMP_CFGRx_INMSEL_Pos) /*!< 0x00080000 */
19564 #define COMP_CFGRx_INPSEL_Pos (20U)
19565 #define COMP_CFGRx_INPSEL_Msk (0x1UL << COMP_CFGRx_INPSEL_Pos) /*!< 0x00100000 */
19566 #define COMP_CFGRx_INPSEL COMP_CFGRx_INPSEL_Msk /*!< COMPx input plus selection bit */
19567 #define COMP_CFGRx_INP2SEL_Pos (22U)
19568 #define COMP_CFGRx_INP2SEL_Msk (0x1UL << COMP_CFGRx_INP2SEL_Pos) /*!< 0x00400000 */
19569 #define COMP_CFGRx_INP2SEL COMP_CFGRx_INP2SEL_Msk /*!< COMPx input plus 2 selection bit */
19570 #define COMP_CFGRx_BLANKING_Pos (24U)
19571 #define COMP_CFGRx_BLANKING_Msk (0xFUL << COMP_CFGRx_BLANKING_Pos) /*!< 0x0F000000 */
19572 #define COMP_CFGRx_BLANKING COMP_CFGRx_BLANKING_Msk /*!< COMPx blanking source selection bits */
19573 #define COMP_CFGRx_BLANKING_0 (0x1UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x01000000 */
19574 #define COMP_CFGRx_BLANKING_1 (0x2UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x02000000 */
19575 #define COMP_CFGRx_BLANKING_2 (0x4UL << COMP_CFGRx_BLANKING_Pos) /*!< 0x04000000 */
19576 #define COMP_CFGRx_LOCK_Pos (31U)
19577 #define COMP_CFGRx_LOCK_Msk (0x1UL << COMP_CFGRx_LOCK_Pos) /*!< 0x80000000 */
19578 #define COMP_CFGRx_LOCK COMP_CFGRx_LOCK_Msk /*!< COMPx Lock Bit */
19579
19580
19581 /******************************************************************************/
19582 /* */
19583 /* Universal Synchronous Asynchronous Receiver Transmitter (USART) */
19584 /* */
19585 /******************************************************************************/
19586 /****************** Bit definition for USART_CR1 register *******************/
19587 #define USART_CR1_UE_Pos (0U)
19588 #define USART_CR1_UE_Msk (0x1UL << USART_CR1_UE_Pos) /*!< 0x00000001 */
19589 #define USART_CR1_UE USART_CR1_UE_Msk /*!< USART Enable */
19590 #define USART_CR1_UESM_Pos (1U)
19591 #define USART_CR1_UESM_Msk (0x1UL << USART_CR1_UESM_Pos) /*!< 0x00000002 */
19592 #define USART_CR1_UESM USART_CR1_UESM_Msk /*!< USART Enable in STOP Mode */
19593 #define USART_CR1_RE_Pos (2U)
19594 #define USART_CR1_RE_Msk (0x1UL << USART_CR1_RE_Pos) /*!< 0x00000004 */
19595 #define USART_CR1_RE USART_CR1_RE_Msk /*!< Receiver Enable */
19596 #define USART_CR1_TE_Pos (3U)
19597 #define USART_CR1_TE_Msk (0x1UL << USART_CR1_TE_Pos) /*!< 0x00000008 */
19598 #define USART_CR1_TE USART_CR1_TE_Msk /*!< Transmitter Enable */
19599 #define USART_CR1_IDLEIE_Pos (4U)
19600 #define USART_CR1_IDLEIE_Msk (0x1UL << USART_CR1_IDLEIE_Pos) /*!< 0x00000010 */
19601 #define USART_CR1_IDLEIE USART_CR1_IDLEIE_Msk /*!< IDLE Interrupt Enable */
19602 #define USART_CR1_RXNEIE_RXFNEIE_Pos (5U)
19603 #define USART_CR1_RXNEIE_RXFNEIE_Msk (0x1UL << USART_CR1_RXNEIE_RXFNEIE_Pos) /*!< 0x00000020 */
19604 #define USART_CR1_RXNEIE_RXFNEIE USART_CR1_RXNEIE_RXFNEIE_Msk /*!< RXNE and RX FIFO Not Empty Interrupt Enable */
19605 #define USART_CR1_TCIE_Pos (6U)
19606 #define USART_CR1_TCIE_Msk (0x1UL << USART_CR1_TCIE_Pos) /*!< 0x00000040 */
19607 #define USART_CR1_TCIE USART_CR1_TCIE_Msk /*!< Transmission Complete Interrupt Enable */
19608 #define USART_CR1_TXEIE_TXFNFIE_Pos (7U)
19609 #define USART_CR1_TXEIE_TXFNFIE_Msk (0x1UL << USART_CR1_TXEIE_TXFNFIE_Pos) /*!< 0x00000080 */
19610 #define USART_CR1_TXEIE_TXFNFIE USART_CR1_TXEIE_TXFNFIE_Msk /*!< TXE and TX FIFO Not Full Interrupt Enable */
19611 #define USART_CR1_PEIE_Pos (8U)
19612 #define USART_CR1_PEIE_Msk (0x1UL << USART_CR1_PEIE_Pos) /*!< 0x00000100 */
19613 #define USART_CR1_PEIE USART_CR1_PEIE_Msk /*!< PE Interrupt Enable */
19614 #define USART_CR1_PS_Pos (9U)
19615 #define USART_CR1_PS_Msk (0x1UL << USART_CR1_PS_Pos) /*!< 0x00000200 */
19616 #define USART_CR1_PS USART_CR1_PS_Msk /*!< Parity Selection */
19617 #define USART_CR1_PCE_Pos (10U)
19618 #define USART_CR1_PCE_Msk (0x1UL << USART_CR1_PCE_Pos) /*!< 0x00000400 */
19619 #define USART_CR1_PCE USART_CR1_PCE_Msk /*!< Parity Control Enable */
19620 #define USART_CR1_WAKE_Pos (11U)
19621 #define USART_CR1_WAKE_Msk (0x1UL << USART_CR1_WAKE_Pos) /*!< 0x00000800 */
19622 #define USART_CR1_WAKE USART_CR1_WAKE_Msk /*!< Receiver Wakeup method */
19623 #define USART_CR1_M_Pos (12U)
19624 #define USART_CR1_M_Msk (0x10001UL << USART_CR1_M_Pos) /*!< 0x10001000 */
19625 #define USART_CR1_M USART_CR1_M_Msk /*!< Word length */
19626 #define USART_CR1_M0_Pos (12U)
19627 #define USART_CR1_M0_Msk (0x1UL << USART_CR1_M0_Pos) /*!< 0x00001000 */
19628 #define USART_CR1_M0 USART_CR1_M0_Msk /*!< Word length - Bit 0 */
19629 #define USART_CR1_MME_Pos (13U)
19630 #define USART_CR1_MME_Msk (0x1UL << USART_CR1_MME_Pos) /*!< 0x00002000 */
19631 #define USART_CR1_MME USART_CR1_MME_Msk /*!< Mute Mode Enable */
19632 #define USART_CR1_CMIE_Pos (14U)
19633 #define USART_CR1_CMIE_Msk (0x1UL << USART_CR1_CMIE_Pos) /*!< 0x00004000 */
19634 #define USART_CR1_CMIE USART_CR1_CMIE_Msk /*!< Character match interrupt enable */
19635 #define USART_CR1_OVER8_Pos (15U)
19636 #define USART_CR1_OVER8_Msk (0x1UL << USART_CR1_OVER8_Pos) /*!< 0x00008000 */
19637 #define USART_CR1_OVER8 USART_CR1_OVER8_Msk /*!< Oversampling by 8-bit or 16-bit mode */
19638 #define USART_CR1_DEDT_Pos (16U)
19639 #define USART_CR1_DEDT_Msk (0x1FUL << USART_CR1_DEDT_Pos) /*!< 0x001F0000 */
19640 #define USART_CR1_DEDT USART_CR1_DEDT_Msk /*!< DEDT[4:0] bits (Driver Enable Deassertion Time) */
19641 #define USART_CR1_DEDT_0 (0x01UL << USART_CR1_DEDT_Pos) /*!< 0x00010000 */
19642 #define USART_CR1_DEDT_1 (0x02UL << USART_CR1_DEDT_Pos) /*!< 0x00020000 */
19643 #define USART_CR1_DEDT_2 (0x04UL << USART_CR1_DEDT_Pos) /*!< 0x00040000 */
19644 #define USART_CR1_DEDT_3 (0x08UL << USART_CR1_DEDT_Pos) /*!< 0x00080000 */
19645 #define USART_CR1_DEDT_4 (0x10UL << USART_CR1_DEDT_Pos) /*!< 0x00100000 */
19646 #define USART_CR1_DEAT_Pos (21U)
19647 #define USART_CR1_DEAT_Msk (0x1FUL << USART_CR1_DEAT_Pos) /*!< 0x03E00000 */
19648 #define USART_CR1_DEAT USART_CR1_DEAT_Msk /*!< DEAT[4:0] bits (Driver Enable Assertion Time) */
19649 #define USART_CR1_DEAT_0 (0x01UL << USART_CR1_DEAT_Pos) /*!< 0x00200000 */
19650 #define USART_CR1_DEAT_1 (0x02UL << USART_CR1_DEAT_Pos) /*!< 0x00400000 */
19651 #define USART_CR1_DEAT_2 (0x04UL << USART_CR1_DEAT_Pos) /*!< 0x00800000 */
19652 #define USART_CR1_DEAT_3 (0x08UL << USART_CR1_DEAT_Pos) /*!< 0x01000000 */
19653 #define USART_CR1_DEAT_4 (0x10UL << USART_CR1_DEAT_Pos) /*!< 0x02000000 */
19654 #define USART_CR1_RTOIE_Pos (26U)
19655 #define USART_CR1_RTOIE_Msk (0x1UL << USART_CR1_RTOIE_Pos) /*!< 0x04000000 */
19656 #define USART_CR1_RTOIE USART_CR1_RTOIE_Msk /*!< Receive Time Out interrupt enable */
19657 #define USART_CR1_EOBIE_Pos (27U)
19658 #define USART_CR1_EOBIE_Msk (0x1UL << USART_CR1_EOBIE_Pos) /*!< 0x08000000 */
19659 #define USART_CR1_EOBIE USART_CR1_EOBIE_Msk /*!< End of Block interrupt enable */
19660 #define USART_CR1_M1_Pos (28U)
19661 #define USART_CR1_M1_Msk (0x1UL << USART_CR1_M1_Pos) /*!< 0x10000000 */
19662 #define USART_CR1_M1 USART_CR1_M1_Msk /*!< Word length - Bit 1 */
19663 #define USART_CR1_FIFOEN_Pos (29U)
19664 #define USART_CR1_FIFOEN_Msk (0x1UL << USART_CR1_FIFOEN_Pos) /*!< 0x20000000 */
19665 #define USART_CR1_FIFOEN USART_CR1_FIFOEN_Msk /*!< FIFO mode enable */
19666 #define USART_CR1_TXFEIE_Pos (30U)
19667 #define USART_CR1_TXFEIE_Msk (0x1UL << USART_CR1_TXFEIE_Pos) /*!< 0x40000000 */
19668 #define USART_CR1_TXFEIE USART_CR1_TXFEIE_Msk /*!< TXFIFO empty interrupt enable */
19669 #define USART_CR1_RXFFIE_Pos (31U)
19670 #define USART_CR1_RXFFIE_Msk (0x1UL << USART_CR1_RXFFIE_Pos) /*!< 0x80000000 */
19671 #define USART_CR1_RXFFIE USART_CR1_RXFFIE_Msk /*!< RXFIFO Full interrupt enable */
19672
19673 /* Legacy define */
19674 #define USART_CR1_RXNEIE USART_CR1_RXNEIE_RXFNEIE
19675 #define USART_CR1_TXEIE USART_CR1_TXEIE_TXFNFIE
19676
19677 /****************** Bit definition for USART_CR2 register *******************/
19678 #define USART_CR2_SLVEN_Pos (0U)
19679 #define USART_CR2_SLVEN_Msk (0x1UL << USART_CR2_SLVEN_Pos) /*!< 0x00000001 */
19680 #define USART_CR2_SLVEN USART_CR2_SLVEN_Msk /*!< Synchronous Slave mode Enable */
19681 #define USART_CR2_DIS_NSS_Pos (3U)
19682 #define USART_CR2_DIS_NSS_Msk (0x1UL << USART_CR2_DIS_NSS_Pos) /*!< 0x00000008 */
19683 #define USART_CR2_DIS_NSS USART_CR2_DIS_NSS_Msk /*!< Negative Slave Select (NSS) pin management */
19684 #define USART_CR2_ADDM7_Pos (4U)
19685 #define USART_CR2_ADDM7_Msk (0x1UL << USART_CR2_ADDM7_Pos) /*!< 0x00000010 */
19686 #define USART_CR2_ADDM7 USART_CR2_ADDM7_Msk /*!< 7-bit or 4-bit Address Detection */
19687 #define USART_CR2_LBDL_Pos (5U)
19688 #define USART_CR2_LBDL_Msk (0x1UL << USART_CR2_LBDL_Pos) /*!< 0x00000020 */
19689 #define USART_CR2_LBDL USART_CR2_LBDL_Msk /*!< LIN Break Detection Length */
19690 #define USART_CR2_LBDIE_Pos (6U)
19691 #define USART_CR2_LBDIE_Msk (0x1UL << USART_CR2_LBDIE_Pos) /*!< 0x00000040 */
19692 #define USART_CR2_LBDIE USART_CR2_LBDIE_Msk /*!< LIN Break Detection Interrupt Enable */
19693 #define USART_CR2_LBCL_Pos (8U)
19694 #define USART_CR2_LBCL_Msk (0x1UL << USART_CR2_LBCL_Pos) /*!< 0x00000100 */
19695 #define USART_CR2_LBCL USART_CR2_LBCL_Msk /*!< Last Bit Clock pulse */
19696 #define USART_CR2_CPHA_Pos (9U)
19697 #define USART_CR2_CPHA_Msk (0x1UL << USART_CR2_CPHA_Pos) /*!< 0x00000200 */
19698 #define USART_CR2_CPHA USART_CR2_CPHA_Msk /*!< Clock Phase */
19699 #define USART_CR2_CPOL_Pos (10U)
19700 #define USART_CR2_CPOL_Msk (0x1UL << USART_CR2_CPOL_Pos) /*!< 0x00000400 */
19701 #define USART_CR2_CPOL USART_CR2_CPOL_Msk /*!< Clock Polarity */
19702 #define USART_CR2_CLKEN_Pos (11U)
19703 #define USART_CR2_CLKEN_Msk (0x1UL << USART_CR2_CLKEN_Pos) /*!< 0x00000800 */
19704 #define USART_CR2_CLKEN USART_CR2_CLKEN_Msk /*!< Clock Enable */
19705 #define USART_CR2_STOP_Pos (12U)
19706 #define USART_CR2_STOP_Msk (0x3UL << USART_CR2_STOP_Pos) /*!< 0x00003000 */
19707 #define USART_CR2_STOP USART_CR2_STOP_Msk /*!< STOP[1:0] bits (STOP bits) */
19708 #define USART_CR2_STOP_0 (0x1UL << USART_CR2_STOP_Pos) /*!< 0x00001000 */
19709 #define USART_CR2_STOP_1 (0x2UL << USART_CR2_STOP_Pos) /*!< 0x00002000 */
19710 #define USART_CR2_LINEN_Pos (14U)
19711 #define USART_CR2_LINEN_Msk (0x1UL << USART_CR2_LINEN_Pos) /*!< 0x00004000 */
19712 #define USART_CR2_LINEN USART_CR2_LINEN_Msk /*!< LIN mode enable */
19713 #define USART_CR2_SWAP_Pos (15U)
19714 #define USART_CR2_SWAP_Msk (0x1UL << USART_CR2_SWAP_Pos) /*!< 0x00008000 */
19715 #define USART_CR2_SWAP USART_CR2_SWAP_Msk /*!< SWAP TX/RX pins */
19716 #define USART_CR2_RXINV_Pos (16U)
19717 #define USART_CR2_RXINV_Msk (0x1UL << USART_CR2_RXINV_Pos) /*!< 0x00010000 */
19718 #define USART_CR2_RXINV USART_CR2_RXINV_Msk /*!< RX pin active level inversion */
19719 #define USART_CR2_TXINV_Pos (17U)
19720 #define USART_CR2_TXINV_Msk (0x1UL << USART_CR2_TXINV_Pos) /*!< 0x00020000 */
19721 #define USART_CR2_TXINV USART_CR2_TXINV_Msk /*!< TX pin active level inversion */
19722 #define USART_CR2_DATAINV_Pos (18U)
19723 #define USART_CR2_DATAINV_Msk (0x1UL << USART_CR2_DATAINV_Pos) /*!< 0x00040000 */
19724 #define USART_CR2_DATAINV USART_CR2_DATAINV_Msk /*!< Binary data inversion */
19725 #define USART_CR2_MSBFIRST_Pos (19U)
19726 #define USART_CR2_MSBFIRST_Msk (0x1UL << USART_CR2_MSBFIRST_Pos) /*!< 0x00080000 */
19727 #define USART_CR2_MSBFIRST USART_CR2_MSBFIRST_Msk /*!< Most Significant Bit First */
19728 #define USART_CR2_ABREN_Pos (20U)
19729 #define USART_CR2_ABREN_Msk (0x1UL << USART_CR2_ABREN_Pos) /*!< 0x00100000 */
19730 #define USART_CR2_ABREN USART_CR2_ABREN_Msk /*!< Auto Baud-Rate Enable*/
19731 #define USART_CR2_ABRMODE_Pos (21U)
19732 #define USART_CR2_ABRMODE_Msk (0x3UL << USART_CR2_ABRMODE_Pos) /*!< 0x00600000 */
19733 #define USART_CR2_ABRMODE USART_CR2_ABRMODE_Msk /*!< ABRMOD[1:0] bits (Auto Baud-Rate Mode) */
19734 #define USART_CR2_ABRMODE_0 (0x1UL << USART_CR2_ABRMODE_Pos) /*!< 0x00200000 */
19735 #define USART_CR2_ABRMODE_1 (0x2UL << USART_CR2_ABRMODE_Pos) /*!< 0x00400000 */
19736 #define USART_CR2_RTOEN_Pos (23U)
19737 #define USART_CR2_RTOEN_Msk (0x1UL << USART_CR2_RTOEN_Pos) /*!< 0x00800000 */
19738 #define USART_CR2_RTOEN USART_CR2_RTOEN_Msk /*!< Receiver Time-Out enable */
19739 #define USART_CR2_ADD_Pos (24U)
19740 #define USART_CR2_ADD_Msk (0xFFUL << USART_CR2_ADD_Pos) /*!< 0xFF000000 */
19741 #define USART_CR2_ADD USART_CR2_ADD_Msk /*!< Address of the USART node */
19742
19743 /****************** Bit definition for USART_CR3 register *******************/
19744 #define USART_CR3_EIE_Pos (0U)
19745 #define USART_CR3_EIE_Msk (0x1UL << USART_CR3_EIE_Pos) /*!< 0x00000001 */
19746 #define USART_CR3_EIE USART_CR3_EIE_Msk /*!< Error Interrupt Enable */
19747 #define USART_CR3_IREN_Pos (1U)
19748 #define USART_CR3_IREN_Msk (0x1UL << USART_CR3_IREN_Pos) /*!< 0x00000002 */
19749 #define USART_CR3_IREN USART_CR3_IREN_Msk /*!< IrDA mode Enable */
19750 #define USART_CR3_IRLP_Pos (2U)
19751 #define USART_CR3_IRLP_Msk (0x1UL << USART_CR3_IRLP_Pos) /*!< 0x00000004 */
19752 #define USART_CR3_IRLP USART_CR3_IRLP_Msk /*!< IrDA Low-Power */
19753 #define USART_CR3_HDSEL_Pos (3U)
19754 #define USART_CR3_HDSEL_Msk (0x1UL << USART_CR3_HDSEL_Pos) /*!< 0x00000008 */
19755 #define USART_CR3_HDSEL USART_CR3_HDSEL_Msk /*!< Half-Duplex Selection */
19756 #define USART_CR3_NACK_Pos (4U)
19757 #define USART_CR3_NACK_Msk (0x1UL << USART_CR3_NACK_Pos) /*!< 0x00000010 */
19758 #define USART_CR3_NACK USART_CR3_NACK_Msk /*!< SmartCard NACK enable */
19759 #define USART_CR3_SCEN_Pos (5U)
19760 #define USART_CR3_SCEN_Msk (0x1UL << USART_CR3_SCEN_Pos) /*!< 0x00000020 */
19761 #define USART_CR3_SCEN USART_CR3_SCEN_Msk /*!< SmartCard mode enable */
19762 #define USART_CR3_DMAR_Pos (6U)
19763 #define USART_CR3_DMAR_Msk (0x1UL << USART_CR3_DMAR_Pos) /*!< 0x00000040 */
19764 #define USART_CR3_DMAR USART_CR3_DMAR_Msk /*!< DMA Enable Receiver */
19765 #define USART_CR3_DMAT_Pos (7U)
19766 #define USART_CR3_DMAT_Msk (0x1UL << USART_CR3_DMAT_Pos) /*!< 0x00000080 */
19767 #define USART_CR3_DMAT USART_CR3_DMAT_Msk /*!< DMA Enable Transmitter */
19768 #define USART_CR3_RTSE_Pos (8U)
19769 #define USART_CR3_RTSE_Msk (0x1UL << USART_CR3_RTSE_Pos) /*!< 0x00000100 */
19770 #define USART_CR3_RTSE USART_CR3_RTSE_Msk /*!< RTS Enable */
19771 #define USART_CR3_CTSE_Pos (9U)
19772 #define USART_CR3_CTSE_Msk (0x1UL << USART_CR3_CTSE_Pos) /*!< 0x00000200 */
19773 #define USART_CR3_CTSE USART_CR3_CTSE_Msk /*!< CTS Enable */
19774 #define USART_CR3_CTSIE_Pos (10U)
19775 #define USART_CR3_CTSIE_Msk (0x1UL << USART_CR3_CTSIE_Pos) /*!< 0x00000400 */
19776 #define USART_CR3_CTSIE USART_CR3_CTSIE_Msk /*!< CTS Interrupt Enable */
19777 #define USART_CR3_ONEBIT_Pos (11U)
19778 #define USART_CR3_ONEBIT_Msk (0x1UL << USART_CR3_ONEBIT_Pos) /*!< 0x00000800 */
19779 #define USART_CR3_ONEBIT USART_CR3_ONEBIT_Msk /*!< One sample bit method enable */
19780 #define USART_CR3_OVRDIS_Pos (12U)
19781 #define USART_CR3_OVRDIS_Msk (0x1UL << USART_CR3_OVRDIS_Pos) /*!< 0x00001000 */
19782 #define USART_CR3_OVRDIS USART_CR3_OVRDIS_Msk /*!< Overrun Disable */
19783 #define USART_CR3_DDRE_Pos (13U)
19784 #define USART_CR3_DDRE_Msk (0x1UL << USART_CR3_DDRE_Pos) /*!< 0x00002000 */
19785 #define USART_CR3_DDRE USART_CR3_DDRE_Msk /*!< DMA Disable on Reception Error */
19786 #define USART_CR3_DEM_Pos (14U)
19787 #define USART_CR3_DEM_Msk (0x1UL << USART_CR3_DEM_Pos) /*!< 0x00004000 */
19788 #define USART_CR3_DEM USART_CR3_DEM_Msk /*!< Driver Enable Mode */
19789 #define USART_CR3_DEP_Pos (15U)
19790 #define USART_CR3_DEP_Msk (0x1UL << USART_CR3_DEP_Pos) /*!< 0x00008000 */
19791 #define USART_CR3_DEP USART_CR3_DEP_Msk /*!< Driver Enable Polarity Selection */
19792 #define USART_CR3_SCARCNT_Pos (17U)
19793 #define USART_CR3_SCARCNT_Msk (0x7UL << USART_CR3_SCARCNT_Pos) /*!< 0x000E0000 */
19794 #define USART_CR3_SCARCNT USART_CR3_SCARCNT_Msk /*!< SCARCNT[2:0] bits (SmartCard Auto-Retry Count) */
19795 #define USART_CR3_SCARCNT_0 (0x1UL << USART_CR3_SCARCNT_Pos) /*!< 0x00020000 */
19796 #define USART_CR3_SCARCNT_1 (0x2UL << USART_CR3_SCARCNT_Pos) /*!< 0x00040000 */
19797 #define USART_CR3_SCARCNT_2 (0x4UL << USART_CR3_SCARCNT_Pos) /*!< 0x00080000 */
19798 #define USART_CR3_WUS_Pos (20U)
19799 #define USART_CR3_WUS_Msk (0x3UL << USART_CR3_WUS_Pos) /*!< 0x00300000 */
19800 #define USART_CR3_WUS USART_CR3_WUS_Msk /*!< WUS[1:0] bits (Wake UP Interrupt Flag Selection) */
19801 #define USART_CR3_WUS_0 (0x1UL << USART_CR3_WUS_Pos) /*!< 0x00100000 */
19802 #define USART_CR3_WUS_1 (0x2UL << USART_CR3_WUS_Pos) /*!< 0x00200000 */
19803 #define USART_CR3_WUFIE_Pos (22U)
19804 #define USART_CR3_WUFIE_Msk (0x1UL << USART_CR3_WUFIE_Pos) /*!< 0x00400000 */
19805 #define USART_CR3_WUFIE USART_CR3_WUFIE_Msk /*!< Wake Up Interrupt Enable */
19806 #define USART_CR3_TXFTIE_Pos (23U)
19807 #define USART_CR3_TXFTIE_Msk (0x1UL << USART_CR3_TXFTIE_Pos) /*!< 0x00800000 */
19808 #define USART_CR3_TXFTIE USART_CR3_TXFTIE_Msk /*!< TXFIFO threshold interrupt enable */
19809 #define USART_CR3_TCBGTIE_Pos (24U)
19810 #define USART_CR3_TCBGTIE_Msk (0x1UL << USART_CR3_TCBGTIE_Pos) /*!< 0x01000000 */
19811 #define USART_CR3_TCBGTIE USART_CR3_TCBGTIE_Msk /*!< Transmission Complete before guard time, interrupt enable */
19812 #define USART_CR3_RXFTCFG_Pos (25U)
19813 #define USART_CR3_RXFTCFG_Msk (0x7UL << USART_CR3_RXFTCFG_Pos) /*!< 0x0E000000 */
19814 #define USART_CR3_RXFTCFG USART_CR3_RXFTCFG_Msk /*!< RXFTCFG [2:0]Receive FIFO threshold configuration */
19815 #define USART_CR3_RXFTCFG_0 (0x1UL << USART_CR3_RXFTCFG_Pos) /*!< 0x02000000 */
19816 #define USART_CR3_RXFTCFG_1 (0x2UL << USART_CR3_RXFTCFG_Pos) /*!< 0x04000000 */
19817 #define USART_CR3_RXFTCFG_2 (0x4UL << USART_CR3_RXFTCFG_Pos) /*!< 0x08000000 */
19818 #define USART_CR3_RXFTIE_Pos (28U)
19819 #define USART_CR3_RXFTIE_Msk (0x1UL << USART_CR3_RXFTIE_Pos) /*!< 0x10000000 */
19820 #define USART_CR3_RXFTIE USART_CR3_RXFTIE_Msk /*!< RXFIFO threshold interrupt enable */
19821 #define USART_CR3_TXFTCFG_Pos (29U)
19822 #define USART_CR3_TXFTCFG_Msk (0x7UL << USART_CR3_TXFTCFG_Pos) /*!< 0xE0000000 */
19823 #define USART_CR3_TXFTCFG USART_CR3_TXFTCFG_Msk /*!< TXFIFO [2:0] threshold configuration */
19824 #define USART_CR3_TXFTCFG_0 (0x1UL << USART_CR3_TXFTCFG_Pos) /*!< 0x20000000 */
19825 #define USART_CR3_TXFTCFG_1 (0x2UL << USART_CR3_TXFTCFG_Pos) /*!< 0x40000000 */
19826 #define USART_CR3_TXFTCFG_2 (0x4UL << USART_CR3_TXFTCFG_Pos) /*!< 0x80000000 */
19827
19828 /****************** Bit definition for USART_BRR register *******************/
19829 #define USART_BRR_DIV_FRACTION_Pos (0U)
19830 #define USART_BRR_DIV_FRACTION_Msk (0xFUL << USART_BRR_DIV_FRACTION_Pos) /*!< 0x0000000F */
19831 #define USART_BRR_DIV_FRACTION USART_BRR_DIV_FRACTION_Msk /*!< Fraction of USARTDIV */
19832 #define USART_BRR_DIV_MANTISSA_Pos (4U)
19833 #define USART_BRR_DIV_MANTISSA_Msk (0xFFFUL << USART_BRR_DIV_MANTISSA_Pos) /*!< 0x0000FFF0 */
19834 #define USART_BRR_DIV_MANTISSA USART_BRR_DIV_MANTISSA_Msk /*!< Mantissa of USARTDIV */
19835
19836 /****************** Bit definition for USART_GTPR register ******************/
19837 #define USART_GTPR_PSC_Pos (0U)
19838 #define USART_GTPR_PSC_Msk (0xFFUL << USART_GTPR_PSC_Pos) /*!< 0x000000FF */
19839 #define USART_GTPR_PSC USART_GTPR_PSC_Msk /*!< PSC[7:0] bits (Prescaler value) */
19840 #define USART_GTPR_GT_Pos (8U)
19841 #define USART_GTPR_GT_Msk (0xFFUL << USART_GTPR_GT_Pos) /*!< 0x0000FF00 */
19842 #define USART_GTPR_GT USART_GTPR_GT_Msk /*!< GT[7:0] bits (Guard time value) */
19843
19844 /******************* Bit definition for USART_RTOR register *****************/
19845 #define USART_RTOR_RTO_Pos (0U)
19846 #define USART_RTOR_RTO_Msk (0xFFFFFFUL << USART_RTOR_RTO_Pos) /*!< 0x00FFFFFF */
19847 #define USART_RTOR_RTO USART_RTOR_RTO_Msk /*!< Receiver Time Out Value */
19848 #define USART_RTOR_BLEN_Pos (24U)
19849 #define USART_RTOR_BLEN_Msk (0xFFUL << USART_RTOR_BLEN_Pos) /*!< 0xFF000000 */
19850 #define USART_RTOR_BLEN USART_RTOR_BLEN_Msk /*!< Block Length */
19851
19852 /******************* Bit definition for USART_RQR register ******************/
19853 #define USART_RQR_ABRRQ_Pos (0U)
19854 #define USART_RQR_ABRRQ_Msk (0x1UL << USART_RQR_ABRRQ_Pos) /*!< 0x00000001 */
19855 #define USART_RQR_ABRRQ USART_RQR_ABRRQ_Msk /*!< Auto-Baud Rate Request */
19856 #define USART_RQR_SBKRQ_Pos (1U)
19857 #define USART_RQR_SBKRQ_Msk (0x1UL << USART_RQR_SBKRQ_Pos) /*!< 0x00000002 */
19858 #define USART_RQR_SBKRQ USART_RQR_SBKRQ_Msk /*!< Send Break Request */
19859 #define USART_RQR_MMRQ_Pos (2U)
19860 #define USART_RQR_MMRQ_Msk (0x1UL << USART_RQR_MMRQ_Pos) /*!< 0x00000004 */
19861 #define USART_RQR_MMRQ USART_RQR_MMRQ_Msk /*!< Mute Mode Request */
19862 #define USART_RQR_RXFRQ_Pos (3U)
19863 #define USART_RQR_RXFRQ_Msk (0x1UL << USART_RQR_RXFRQ_Pos) /*!< 0x00000008 */
19864 #define USART_RQR_RXFRQ USART_RQR_RXFRQ_Msk /*!< Receive Data flush Request */
19865 #define USART_RQR_TXFRQ_Pos (4U)
19866 #define USART_RQR_TXFRQ_Msk (0x1UL << USART_RQR_TXFRQ_Pos) /*!< 0x00000010 */
19867 #define USART_RQR_TXFRQ USART_RQR_TXFRQ_Msk /*!< Transmit data flush Request */
19868
19869 /******************* Bit definition for USART_ISR register ******************/
19870 #define USART_ISR_PE_Pos (0U)
19871 #define USART_ISR_PE_Msk (0x1UL << USART_ISR_PE_Pos) /*!< 0x00000001 */
19872 #define USART_ISR_PE USART_ISR_PE_Msk /*!< Parity Error */
19873 #define USART_ISR_FE_Pos (1U)
19874 #define USART_ISR_FE_Msk (0x1UL << USART_ISR_FE_Pos) /*!< 0x00000002 */
19875 #define USART_ISR_FE USART_ISR_FE_Msk /*!< Framing Error */
19876 #define USART_ISR_NE_Pos (2U)
19877 #define USART_ISR_NE_Msk (0x1UL << USART_ISR_NE_Pos) /*!< 0x00000004 */
19878 #define USART_ISR_NE USART_ISR_NE_Msk /*!< Noise detected Flag */
19879 #define USART_ISR_ORE_Pos (3U)
19880 #define USART_ISR_ORE_Msk (0x1UL << USART_ISR_ORE_Pos) /*!< 0x00000008 */
19881 #define USART_ISR_ORE USART_ISR_ORE_Msk /*!< OverRun Error */
19882 #define USART_ISR_IDLE_Pos (4U)
19883 #define USART_ISR_IDLE_Msk (0x1UL << USART_ISR_IDLE_Pos) /*!< 0x00000010 */
19884 #define USART_ISR_IDLE USART_ISR_IDLE_Msk /*!< IDLE line detected */
19885 #define USART_ISR_RXNE_RXFNE_Pos (5U)
19886 #define USART_ISR_RXNE_RXFNE_Msk (0x1UL << USART_ISR_RXNE_RXFNE_Pos) /*!< 0x00000020 */
19887 #define USART_ISR_RXNE_RXFNE USART_ISR_RXNE_RXFNE_Msk /*!< Read Data Register or RX FIFO Not Empty */
19888 #define USART_ISR_TC_Pos (6U)
19889 #define USART_ISR_TC_Msk (0x1UL << USART_ISR_TC_Pos) /*!< 0x00000040 */
19890 #define USART_ISR_TC USART_ISR_TC_Msk /*!< Transmission Complete */
19891 #define USART_ISR_TXE_TXFNF_Pos (7U)
19892 #define USART_ISR_TXE_TXFNF_Msk (0x1UL << USART_ISR_TXE_TXFNF_Pos) /*!< 0x00000080 */
19893 #define USART_ISR_TXE_TXFNF USART_ISR_TXE_TXFNF_Msk /*!< Transmit Data Register Empty or TX FIFO Not Full Flag */
19894 #define USART_ISR_LBDF_Pos (8U)
19895 #define USART_ISR_LBDF_Msk (0x1UL << USART_ISR_LBDF_Pos) /*!< 0x00000100 */
19896 #define USART_ISR_LBDF USART_ISR_LBDF_Msk /*!< LIN Break Detection Flag */
19897 #define USART_ISR_CTSIF_Pos (9U)
19898 #define USART_ISR_CTSIF_Msk (0x1UL << USART_ISR_CTSIF_Pos) /*!< 0x00000200 */
19899 #define USART_ISR_CTSIF USART_ISR_CTSIF_Msk /*!< CTS interrupt flag */
19900 #define USART_ISR_CTS_Pos (10U)
19901 #define USART_ISR_CTS_Msk (0x1UL << USART_ISR_CTS_Pos) /*!< 0x00000400 */
19902 #define USART_ISR_CTS USART_ISR_CTS_Msk /*!< CTS flag */
19903 #define USART_ISR_RTOF_Pos (11U)
19904 #define USART_ISR_RTOF_Msk (0x1UL << USART_ISR_RTOF_Pos) /*!< 0x00000800 */
19905 #define USART_ISR_RTOF USART_ISR_RTOF_Msk /*!< Receiver Time Out */
19906 #define USART_ISR_EOBF_Pos (12U)
19907 #define USART_ISR_EOBF_Msk (0x1UL << USART_ISR_EOBF_Pos) /*!< 0x00001000 */
19908 #define USART_ISR_EOBF USART_ISR_EOBF_Msk /*!< End Of Block Flag */
19909 #define USART_ISR_UDR_Pos (13U)
19910 #define USART_ISR_UDR_Msk (0x1UL << USART_ISR_UDR_Pos) /*!< 0x00002000 */
19911 #define USART_ISR_UDR USART_ISR_UDR_Msk /*!< SPI slave underrun error flag */
19912 #define USART_ISR_ABRE_Pos (14U)
19913 #define USART_ISR_ABRE_Msk (0x1UL << USART_ISR_ABRE_Pos) /*!< 0x00004000 */
19914 #define USART_ISR_ABRE USART_ISR_ABRE_Msk /*!< Auto-Baud Rate Error */
19915 #define USART_ISR_ABRF_Pos (15U)
19916 #define USART_ISR_ABRF_Msk (0x1UL << USART_ISR_ABRF_Pos) /*!< 0x00008000 */
19917 #define USART_ISR_ABRF USART_ISR_ABRF_Msk /*!< Auto-Baud Rate Flag */
19918 #define USART_ISR_BUSY_Pos (16U)
19919 #define USART_ISR_BUSY_Msk (0x1UL << USART_ISR_BUSY_Pos) /*!< 0x00010000 */
19920 #define USART_ISR_BUSY USART_ISR_BUSY_Msk /*!< Busy Flag */
19921 #define USART_ISR_CMF_Pos (17U)
19922 #define USART_ISR_CMF_Msk (0x1UL << USART_ISR_CMF_Pos) /*!< 0x00020000 */
19923 #define USART_ISR_CMF USART_ISR_CMF_Msk /*!< Character Match Flag */
19924 #define USART_ISR_SBKF_Pos (18U)
19925 #define USART_ISR_SBKF_Msk (0x1UL << USART_ISR_SBKF_Pos) /*!< 0x00040000 */
19926 #define USART_ISR_SBKF USART_ISR_SBKF_Msk /*!< Send Break Flag */
19927 #define USART_ISR_RWU_Pos (19U)
19928 #define USART_ISR_RWU_Msk (0x1UL << USART_ISR_RWU_Pos) /*!< 0x00080000 */
19929 #define USART_ISR_RWU USART_ISR_RWU_Msk /*!< Receive Wake Up from mute mode Flag */
19930 #define USART_ISR_WUF_Pos (20U)
19931 #define USART_ISR_WUF_Msk (0x1UL << USART_ISR_WUF_Pos) /*!< 0x00100000 */
19932 #define USART_ISR_WUF USART_ISR_WUF_Msk /*!< Wake Up from stop mode Flag */
19933 #define USART_ISR_TEACK_Pos (21U)
19934 #define USART_ISR_TEACK_Msk (0x1UL << USART_ISR_TEACK_Pos) /*!< 0x00200000 */
19935 #define USART_ISR_TEACK USART_ISR_TEACK_Msk /*!< Transmit Enable Acknowledge Flag */
19936 #define USART_ISR_REACK_Pos (22U)
19937 #define USART_ISR_REACK_Msk (0x1UL << USART_ISR_REACK_Pos) /*!< 0x00400000 */
19938 #define USART_ISR_REACK USART_ISR_REACK_Msk /*!< Receive Enable Acknowledge Flag */
19939 #define USART_ISR_TXFE_Pos (23U)
19940 #define USART_ISR_TXFE_Msk (0x1UL << USART_ISR_TXFE_Pos) /*!< 0x00800000 */
19941 #define USART_ISR_TXFE USART_ISR_TXFE_Msk /*!< TXFIFO Empty */
19942 #define USART_ISR_RXFF_Pos (24U)
19943 #define USART_ISR_RXFF_Msk (0x1UL << USART_ISR_RXFF_Pos) /*!< 0x01000000 */
19944 #define USART_ISR_RXFF USART_ISR_RXFF_Msk /*!< RXFIFO Full Flag */
19945 #define USART_ISR_TCBGT_Pos (25U)
19946 #define USART_ISR_TCBGT_Msk (0x1UL << USART_ISR_TCBGT_Pos) /*!< 0x02000000 */
19947 #define USART_ISR_TCBGT USART_ISR_TCBGT_Msk /*!< Transmission complete before guard time Flag */
19948 #define USART_ISR_RXFT_Pos (26U)
19949 #define USART_ISR_RXFT_Msk (0x1UL << USART_ISR_RXFT_Pos) /*!< 0x04000000 */
19950 #define USART_ISR_RXFT USART_ISR_RXFT_Msk /*!< RXFIFO threshold Flag */
19951 #define USART_ISR_TXFT_Pos (27U)
19952 #define USART_ISR_TXFT_Msk (0x1UL << USART_ISR_TXFT_Pos) /*!< 0x08000000 */
19953 #define USART_ISR_TXFT USART_ISR_TXFT_Msk /*!< TXFIFO threshold Flag */
19954
19955 /******************* Bit definition for USART_ICR register ******************/
19956 #define USART_ICR_PECF_Pos (0U)
19957 #define USART_ICR_PECF_Msk (0x1UL << USART_ICR_PECF_Pos) /*!< 0x00000001 */
19958 #define USART_ICR_PECF USART_ICR_PECF_Msk /*!< Parity Error Clear Flag */
19959 #define USART_ICR_FECF_Pos (1U)
19960 #define USART_ICR_FECF_Msk (0x1UL << USART_ICR_FECF_Pos) /*!< 0x00000002 */
19961 #define USART_ICR_FECF USART_ICR_FECF_Msk /*!< Framing Error Clear Flag */
19962 #define USART_ICR_NECF_Pos (2U)
19963 #define USART_ICR_NECF_Msk (0x1UL << USART_ICR_NECF_Pos) /*!< 0x00000004 */
19964 #define USART_ICR_NECF USART_ICR_NECF_Msk /*!< Noise detected Clear Flag */
19965 #define USART_ICR_ORECF_Pos (3U)
19966 #define USART_ICR_ORECF_Msk (0x1UL << USART_ICR_ORECF_Pos) /*!< 0x00000008 */
19967 #define USART_ICR_ORECF USART_ICR_ORECF_Msk /*!< OverRun Error Clear Flag */
19968 #define USART_ICR_IDLECF_Pos (4U)
19969 #define USART_ICR_IDLECF_Msk (0x1UL << USART_ICR_IDLECF_Pos) /*!< 0x00000010 */
19970 #define USART_ICR_IDLECF USART_ICR_IDLECF_Msk /*!< IDLE line detected Clear Flag */
19971 #define USART_ICR_TXFECF_Pos (5U)
19972 #define USART_ICR_TXFECF_Msk (0x1UL << USART_ICR_TXFECF_Pos) /*!< 0x00000020 */
19973 #define USART_ICR_TXFECF USART_ICR_TXFECF_Msk /*!< TXFIFO empty clear flag */
19974 #define USART_ICR_TCCF_Pos (6U)
19975 #define USART_ICR_TCCF_Msk (0x1UL << USART_ICR_TCCF_Pos) /*!< 0x00000040 */
19976 #define USART_ICR_TCCF USART_ICR_TCCF_Msk /*!< Transmission Complete Clear Flag */
19977 #define USART_ICR_TCBGTCF_Pos (7U)
19978 #define USART_ICR_TCBGTCF_Msk (0x1UL << USART_ICR_TCBGTCF_Pos) /*!< 0x00000080 */
19979 #define USART_ICR_TCBGTCF USART_ICR_TCBGTCF_Msk /*!< Transmission complete before guard time Clear Flag */
19980 #define USART_ICR_LBDCF_Pos (8U)
19981 #define USART_ICR_LBDCF_Msk (0x1UL << USART_ICR_LBDCF_Pos) /*!< 0x00000100 */
19982 #define USART_ICR_LBDCF USART_ICR_LBDCF_Msk /*!< LIN Break Detection Clear Flag */
19983 #define USART_ICR_CTSCF_Pos (9U)
19984 #define USART_ICR_CTSCF_Msk (0x1UL << USART_ICR_CTSCF_Pos) /*!< 0x00000200 */
19985 #define USART_ICR_CTSCF USART_ICR_CTSCF_Msk /*!< CTS Interrupt Clear Flag */
19986 #define USART_ICR_RTOCF_Pos (11U)
19987 #define USART_ICR_RTOCF_Msk (0x1UL << USART_ICR_RTOCF_Pos) /*!< 0x00000800 */
19988 #define USART_ICR_RTOCF USART_ICR_RTOCF_Msk /*!< Receiver Time Out Clear Flag */
19989 #define USART_ICR_EOBCF_Pos (12U)
19990 #define USART_ICR_EOBCF_Msk (0x1UL << USART_ICR_EOBCF_Pos) /*!< 0x00001000 */
19991 #define USART_ICR_EOBCF USART_ICR_EOBCF_Msk /*!< End Of Block Clear Flag */
19992 #define USART_ICR_UDRCF_Pos (13U)
19993 #define USART_ICR_UDRCF_Msk (0x1UL << USART_ICR_UDRCF_Pos) /*!< 0x00002000 */
19994 #define USART_ICR_UDRCF USART_ICR_UDRCF_Msk /*!< SPI slave underrun clear flag */
19995 #define USART_ICR_CMCF_Pos (17U)
19996 #define USART_ICR_CMCF_Msk (0x1UL << USART_ICR_CMCF_Pos) /*!< 0x00020000 */
19997 #define USART_ICR_CMCF USART_ICR_CMCF_Msk /*!< Character Match Clear Flag */
19998 #define USART_ICR_WUCF_Pos (20U)
19999 #define USART_ICR_WUCF_Msk (0x1UL << USART_ICR_WUCF_Pos) /*!< 0x00100000 */
20000 #define USART_ICR_WUCF USART_ICR_WUCF_Msk /*!< Wake Up from stop mode Clear Flag */
20001
20002 /******************* Bit definition for USART_RDR register ******************/
20003 #define USART_RDR_RDR_Pos (0U)
20004 #define USART_RDR_RDR_Msk (0x1FFUL << USART_RDR_RDR_Pos) /*!< 0x000001FF */
20005 #define USART_RDR_RDR USART_RDR_RDR_Msk /*!< RDR[8:0] bits (Receive Data value) */
20006
20007 /******************* Bit definition for USART_TDR register ******************/
20008 #define USART_TDR_TDR_Pos (0U)
20009 #define USART_TDR_TDR_Msk (0x1FFUL << USART_TDR_TDR_Pos) /*!< 0x000001FF */
20010 #define USART_TDR_TDR USART_TDR_TDR_Msk /*!< TDR[8:0] bits (Transmit Data value) */
20011
20012 /******************* Bit definition for USART_PRESC register ******************/
20013 #define USART_PRESC_PRESCALER_Pos (0U)
20014 #define USART_PRESC_PRESCALER_Msk (0xFUL << USART_PRESC_PRESCALER_Pos) /*!< 0x0000000F */
20015 #define USART_PRESC_PRESCALER USART_PRESC_PRESCALER_Msk /*!< PRESCALER[3:0] bits (Clock prescaler) */
20016 #define USART_PRESC_PRESCALER_0 (0x1UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000001 */
20017 #define USART_PRESC_PRESCALER_1 (0x2UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000002 */
20018 #define USART_PRESC_PRESCALER_2 (0x4UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000004 */
20019 #define USART_PRESC_PRESCALER_3 (0x8UL << USART_PRESC_PRESCALER_Pos) /*!< 0x00000008 */
20020
20021 /******************************************************************************/
20022 /* */
20023 /* Single Wire Protocol Master Interface (SWPMI) */
20024 /* */
20025 /******************************************************************************/
20026
20027 /******************* Bit definition for SWPMI_CR register ********************/
20028 #define SWPMI_CR_RXDMA_Pos (0U)
20029 #define SWPMI_CR_RXDMA_Msk (0x1UL << SWPMI_CR_RXDMA_Pos) /*!< 0x00000001 */
20030 #define SWPMI_CR_RXDMA SWPMI_CR_RXDMA_Msk /*!<Reception DMA enable */
20031 #define SWPMI_CR_TXDMA_Pos (1U)
20032 #define SWPMI_CR_TXDMA_Msk (0x1UL << SWPMI_CR_TXDMA_Pos) /*!< 0x00000002 */
20033 #define SWPMI_CR_TXDMA SWPMI_CR_TXDMA_Msk /*!<Transmission DMA enable */
20034 #define SWPMI_CR_RXMODE_Pos (2U)
20035 #define SWPMI_CR_RXMODE_Msk (0x1UL << SWPMI_CR_RXMODE_Pos) /*!< 0x00000004 */
20036 #define SWPMI_CR_RXMODE SWPMI_CR_RXMODE_Msk /*!<Reception buffering mode */
20037 #define SWPMI_CR_TXMODE_Pos (3U)
20038 #define SWPMI_CR_TXMODE_Msk (0x1UL << SWPMI_CR_TXMODE_Pos) /*!< 0x00000008 */
20039 #define SWPMI_CR_TXMODE SWPMI_CR_TXMODE_Msk /*!<Transmission buffering mode */
20040 #define SWPMI_CR_LPBK_Pos (4U)
20041 #define SWPMI_CR_LPBK_Msk (0x1UL << SWPMI_CR_LPBK_Pos) /*!< 0x00000010 */
20042 #define SWPMI_CR_LPBK SWPMI_CR_LPBK_Msk /*!<Loopback mode enable */
20043 #define SWPMI_CR_SWPACT_Pos (5U)
20044 #define SWPMI_CR_SWPACT_Msk (0x1UL << SWPMI_CR_SWPACT_Pos) /*!< 0x00000020 */
20045 #define SWPMI_CR_SWPACT SWPMI_CR_SWPACT_Msk /*!<Single wire protocol master interface activate */
20046 #define SWPMI_CR_DEACT_Pos (10U)
20047 #define SWPMI_CR_DEACT_Msk (0x1UL << SWPMI_CR_DEACT_Pos) /*!< 0x00000400 */
20048 #define SWPMI_CR_DEACT SWPMI_CR_DEACT_Msk /*!<Single wire protocol master interface deactivate */
20049 #define SWPMI_CR_SWPEN_Pos (11U)
20050 #define SWPMI_CR_SWPEN_Msk (0x1UL << SWPMI_CR_SWPEN_Pos) /*!< 0x00000800 */
20051 #define SWPMI_CR_SWPEN SWPMI_CR_SWPEN_Msk /*!<Single wire protocol master transceiver enable */
20052
20053 /******************* Bit definition for SWPMI_BRR register ********************/
20054 #define SWPMI_BRR_BR_Pos (0U)
20055 #define SWPMI_BRR_BR_Msk (0xFFUL << SWPMI_BRR_BR_Pos) /*!< 0x000000FF */
20056 #define SWPMI_BRR_BR SWPMI_BRR_BR_Msk /*!<BR[7:0] bits (Bitrate prescaler) */
20057
20058 /******************* Bit definition for SWPMI_ISR register ********************/
20059 #define SWPMI_ISR_RXBFF_Pos (0U)
20060 #define SWPMI_ISR_RXBFF_Msk (0x1UL << SWPMI_ISR_RXBFF_Pos) /*!< 0x00000001 */
20061 #define SWPMI_ISR_RXBFF SWPMI_ISR_RXBFF_Msk /*!<Receive buffer full flag */
20062 #define SWPMI_ISR_TXBEF_Pos (1U)
20063 #define SWPMI_ISR_TXBEF_Msk (0x1UL << SWPMI_ISR_TXBEF_Pos) /*!< 0x00000002 */
20064 #define SWPMI_ISR_TXBEF SWPMI_ISR_TXBEF_Msk /*!<Transmit buffer empty flag */
20065 #define SWPMI_ISR_RXBERF_Pos (2U)
20066 #define SWPMI_ISR_RXBERF_Msk (0x1UL << SWPMI_ISR_RXBERF_Pos) /*!< 0x00000004 */
20067 #define SWPMI_ISR_RXBERF SWPMI_ISR_RXBERF_Msk /*!<Receive CRC error flag */
20068 #define SWPMI_ISR_RXOVRF_Pos (3U)
20069 #define SWPMI_ISR_RXOVRF_Msk (0x1UL << SWPMI_ISR_RXOVRF_Pos) /*!< 0x00000008 */
20070 #define SWPMI_ISR_RXOVRF SWPMI_ISR_RXOVRF_Msk /*!<Receive overrun error flag */
20071 #define SWPMI_ISR_TXUNRF_Pos (4U)
20072 #define SWPMI_ISR_TXUNRF_Msk (0x1UL << SWPMI_ISR_TXUNRF_Pos) /*!< 0x00000010 */
20073 #define SWPMI_ISR_TXUNRF SWPMI_ISR_TXUNRF_Msk /*!<Transmit underrun error flag */
20074 #define SWPMI_ISR_RXNE_Pos (5U)
20075 #define SWPMI_ISR_RXNE_Msk (0x1UL << SWPMI_ISR_RXNE_Pos) /*!< 0x00000020 */
20076 #define SWPMI_ISR_RXNE SWPMI_ISR_RXNE_Msk /*!<Receive data register not empty */
20077 #define SWPMI_ISR_TXE_Pos (6U)
20078 #define SWPMI_ISR_TXE_Msk (0x1UL << SWPMI_ISR_TXE_Pos) /*!< 0x00000040 */
20079 #define SWPMI_ISR_TXE SWPMI_ISR_TXE_Msk /*!<Transmit data register empty */
20080 #define SWPMI_ISR_TCF_Pos (7U)
20081 #define SWPMI_ISR_TCF_Msk (0x1UL << SWPMI_ISR_TCF_Pos) /*!< 0x00000080 */
20082 #define SWPMI_ISR_TCF SWPMI_ISR_TCF_Msk /*!<Transfer complete flag */
20083 #define SWPMI_ISR_SRF_Pos (8U)
20084 #define SWPMI_ISR_SRF_Msk (0x1UL << SWPMI_ISR_SRF_Pos) /*!< 0x00000100 */
20085 #define SWPMI_ISR_SRF SWPMI_ISR_SRF_Msk /*!<Slave resume flag */
20086 #define SWPMI_ISR_SUSP_Pos (9U)
20087 #define SWPMI_ISR_SUSP_Msk (0x1UL << SWPMI_ISR_SUSP_Pos) /*!< 0x00000200 */
20088 #define SWPMI_ISR_SUSP SWPMI_ISR_SUSP_Msk /*!<SUSPEND flag */
20089 #define SWPMI_ISR_DEACTF_Pos (10U)
20090 #define SWPMI_ISR_DEACTF_Msk (0x1UL << SWPMI_ISR_DEACTF_Pos) /*!< 0x00000400 */
20091 #define SWPMI_ISR_DEACTF SWPMI_ISR_DEACTF_Msk /*!<DEACTIVATED flag */
20092 #define SWPMI_ISR_RDYF_Pos (11U)
20093 #define SWPMI_ISR_RDYF_Msk (0x1UL << SWPMI_ISR_RDYF_Pos) /*!< 0x00000800 */
20094 #define SWPMI_ISR_RDYF SWPMI_ISR_RDYF_Msk /*!<Transceiver ready flag */
20095
20096 /******************* Bit definition for SWPMI_ICR register ********************/
20097 #define SWPMI_ICR_CRXBFF_Pos (0U)
20098 #define SWPMI_ICR_CRXBFF_Msk (0x1UL << SWPMI_ICR_CRXBFF_Pos) /*!< 0x00000001 */
20099 #define SWPMI_ICR_CRXBFF SWPMI_ICR_CRXBFF_Msk /*!<Clear receive buffer full flag */
20100 #define SWPMI_ICR_CTXBEF_Pos (1U)
20101 #define SWPMI_ICR_CTXBEF_Msk (0x1UL << SWPMI_ICR_CTXBEF_Pos) /*!< 0x00000002 */
20102 #define SWPMI_ICR_CTXBEF SWPMI_ICR_CTXBEF_Msk /*!<Clear transmit buffer empty flag */
20103 #define SWPMI_ICR_CRXBERF_Pos (2U)
20104 #define SWPMI_ICR_CRXBERF_Msk (0x1UL << SWPMI_ICR_CRXBERF_Pos) /*!< 0x00000004 */
20105 #define SWPMI_ICR_CRXBERF SWPMI_ICR_CRXBERF_Msk /*!<Clear receive CRC error flag */
20106 #define SWPMI_ICR_CRXOVRF_Pos (3U)
20107 #define SWPMI_ICR_CRXOVRF_Msk (0x1UL << SWPMI_ICR_CRXOVRF_Pos) /*!< 0x00000008 */
20108 #define SWPMI_ICR_CRXOVRF SWPMI_ICR_CRXOVRF_Msk /*!<Clear receive overrun error flag */
20109 #define SWPMI_ICR_CTXUNRF_Pos (4U)
20110 #define SWPMI_ICR_CTXUNRF_Msk (0x1UL << SWPMI_ICR_CTXUNRF_Pos) /*!< 0x00000010 */
20111 #define SWPMI_ICR_CTXUNRF SWPMI_ICR_CTXUNRF_Msk /*!<Clear transmit underrun error flag */
20112 #define SWPMI_ICR_CTCF_Pos (7U)
20113 #define SWPMI_ICR_CTCF_Msk (0x1UL << SWPMI_ICR_CTCF_Pos) /*!< 0x00000080 */
20114 #define SWPMI_ICR_CTCF SWPMI_ICR_CTCF_Msk /*!<Clear transfer complete flag */
20115 #define SWPMI_ICR_CSRF_Pos (8U)
20116 #define SWPMI_ICR_CSRF_Msk (0x1UL << SWPMI_ICR_CSRF_Pos) /*!< 0x00000100 */
20117 #define SWPMI_ICR_CSRF SWPMI_ICR_CSRF_Msk /*!<Clear slave resume flag */
20118 #define SWPMI_ICR_CRDYF_Pos (11U)
20119 #define SWPMI_ICR_CRDYF_Msk (0x1UL << SWPMI_ICR_CRDYF_Pos) /*!< 0x00000800 */
20120 #define SWPMI_ICR_CRDYF SWPMI_ICR_CRDYF_Msk /*!<Clear transceiver ready flag */
20121
20122 /******************* Bit definition for SWPMI_IER register ********************/
20123 #define SWPMI_IER_RXBFIE_Pos (0U)
20124 #define SWPMI_IER_RXBFIE_Msk (0x1UL << SWPMI_IER_RXBFIE_Pos) /*!< 0x00000001 */
20125 #define SWPMI_IER_RXBFIE SWPMI_IER_RXBFIE_Msk /*!<Receive buffer full interrupt enable */
20126 #define SWPMI_IER_TXBEIE_Pos (1U)
20127 #define SWPMI_IER_TXBEIE_Msk (0x1UL << SWPMI_IER_TXBEIE_Pos) /*!< 0x00000002 */
20128 #define SWPMI_IER_TXBEIE SWPMI_IER_TXBEIE_Msk /*!<Transmit buffer empty interrupt enable */
20129 #define SWPMI_IER_RXBERIE_Pos (2U)
20130 #define SWPMI_IER_RXBERIE_Msk (0x1UL << SWPMI_IER_RXBERIE_Pos) /*!< 0x00000004 */
20131 #define SWPMI_IER_RXBERIE SWPMI_IER_RXBERIE_Msk /*!<Receive CRC error interrupt enable */
20132 #define SWPMI_IER_RXOVRIE_Pos (3U)
20133 #define SWPMI_IER_RXOVRIE_Msk (0x1UL << SWPMI_IER_RXOVRIE_Pos) /*!< 0x00000008 */
20134 #define SWPMI_IER_RXOVRIE SWPMI_IER_RXOVRIE_Msk /*!<Receive overrun error interrupt enable */
20135 #define SWPMI_IER_TXUNRIE_Pos (4U)
20136 #define SWPMI_IER_TXUNRIE_Msk (0x1UL << SWPMI_IER_TXUNRIE_Pos) /*!< 0x00000010 */
20137 #define SWPMI_IER_TXUNRIE SWPMI_IER_TXUNRIE_Msk /*!<Transmit underrun error interrupt enable */
20138 #define SWPMI_IER_RIE_Pos (5U)
20139 #define SWPMI_IER_RIE_Msk (0x1UL << SWPMI_IER_RIE_Pos) /*!< 0x00000020 */
20140 #define SWPMI_IER_RIE SWPMI_IER_RIE_Msk /*!<Receive interrupt enable */
20141 #define SWPMI_IER_TIE_Pos (6U)
20142 #define SWPMI_IER_TIE_Msk (0x1UL << SWPMI_IER_TIE_Pos) /*!< 0x00000040 */
20143 #define SWPMI_IER_TIE SWPMI_IER_TIE_Msk /*!<Transmit interrupt enable */
20144 #define SWPMI_IER_TCIE_Pos (7U)
20145 #define SWPMI_IER_TCIE_Msk (0x1UL << SWPMI_IER_TCIE_Pos) /*!< 0x00000080 */
20146 #define SWPMI_IER_TCIE SWPMI_IER_TCIE_Msk /*!<Transmit complete interrupt enable */
20147 #define SWPMI_IER_SRIE_Pos (8U)
20148 #define SWPMI_IER_SRIE_Msk (0x1UL << SWPMI_IER_SRIE_Pos) /*!< 0x00000100 */
20149 #define SWPMI_IER_SRIE SWPMI_IER_SRIE_Msk /*!<Slave resume interrupt enable */
20150 #define SWPMI_IER_RDYIE_Pos (11U)
20151 #define SWPMI_IER_RDYIE_Msk (0x1UL << SWPMI_IER_RDYIE_Pos) /*!< 0x00000800 */
20152 #define SWPMI_IER_RDYIE SWPMI_IER_RDYIE_Msk /*!<Transceiver ready interrupt enable */
20153
20154 /******************* Bit definition for SWPMI_RFL register ********************/
20155 #define SWPMI_RFL_RFL_Pos (0U)
20156 #define SWPMI_RFL_RFL_Msk (0x1FUL << SWPMI_RFL_RFL_Pos) /*!< 0x0000001F */
20157 #define SWPMI_RFL_RFL SWPMI_RFL_RFL_Msk /*!<RFL[4:0] bits (Receive Frame length) */
20158 #define SWPMI_RFL_RFL_0_1 ((uint32_t)0x00000003) /*!<RFL[1:0] bits (number of relevant bytes for the last SWPMI_RDR register read.) */
20159
20160 /******************* Bit definition for SWPMI_TDR register ********************/
20161 #define SWPMI_TDR_TD_Pos (0U)
20162 #define SWPMI_TDR_TD_Msk (0xFFFFFFFFUL << SWPMI_TDR_TD_Pos) /*!< 0xFFFFFFFF */
20163 #define SWPMI_TDR_TD SWPMI_TDR_TD_Msk /*!<Transmit Data Register */
20164
20165 /******************* Bit definition for SWPMI_RDR register ********************/
20166 #define SWPMI_RDR_RD_Pos (0U)
20167 #define SWPMI_RDR_RD_Msk (0xFFFFFFFFUL << SWPMI_RDR_RD_Pos) /*!< 0xFFFFFFFF */
20168 #define SWPMI_RDR_RD SWPMI_RDR_RD_Msk /*!<Recive Data Register */
20169
20170
20171 /******************* Bit definition for SWPMI_OR register ********************/
20172 #define SWPMI_OR_TBYP_Pos (0U)
20173 #define SWPMI_OR_TBYP_Msk (0x1UL << SWPMI_OR_TBYP_Pos) /*!< 0x00000001 */
20174 #define SWPMI_OR_TBYP SWPMI_OR_TBYP_Msk /*!<SWP Transceiver Bypass */
20175 #define SWPMI_OR_CLASS_Pos (1U)
20176 #define SWPMI_OR_CLASS_Msk (0x1UL << SWPMI_OR_CLASS_Pos) /*!< 0x00000002 */
20177 #define SWPMI_OR_CLASS SWPMI_OR_CLASS_Msk /*!<SWP CLASS selection */
20178
20179 /******************************************************************************/
20180 /* */
20181 /* Window WATCHDOG */
20182 /* */
20183 /******************************************************************************/
20184 /******************* Bit definition for WWDG_CR register ********************/
20185 #define WWDG_CR_T_Pos (0U)
20186 #define WWDG_CR_T_Msk (0x7FUL << WWDG_CR_T_Pos) /*!< 0x0000007F */
20187 #define WWDG_CR_T WWDG_CR_T_Msk /*!<T[6:0] bits (7-Bit counter (MSB to LSB)) */
20188 #define WWDG_CR_T_0 (0x01UL << WWDG_CR_T_Pos) /*!< 0x00000001 */
20189 #define WWDG_CR_T_1 (0x02UL << WWDG_CR_T_Pos) /*!< 0x00000002 */
20190 #define WWDG_CR_T_2 (0x04UL << WWDG_CR_T_Pos) /*!< 0x00000004 */
20191 #define WWDG_CR_T_3 (0x08UL << WWDG_CR_T_Pos) /*!< 0x00000008 */
20192 #define WWDG_CR_T_4 (0x10UL << WWDG_CR_T_Pos) /*!< 0x00000010 */
20193 #define WWDG_CR_T_5 (0x20UL << WWDG_CR_T_Pos) /*!< 0x00000020 */
20194 #define WWDG_CR_T_6 (0x40UL << WWDG_CR_T_Pos) /*!< 0x00000040 */
20195
20196 #define WWDG_CR_WDGA_Pos (7U)
20197 #define WWDG_CR_WDGA_Msk (0x1UL << WWDG_CR_WDGA_Pos) /*!< 0x00000080 */
20198 #define WWDG_CR_WDGA WWDG_CR_WDGA_Msk /*!<Activation bit */
20199
20200 /******************* Bit definition for WWDG_CFR register *******************/
20201 #define WWDG_CFR_W_Pos (0U)
20202 #define WWDG_CFR_W_Msk (0x7FUL << WWDG_CFR_W_Pos) /*!< 0x0000007F */
20203 #define WWDG_CFR_W WWDG_CFR_W_Msk /*!<W[6:0] bits (7-bit window value) */
20204 #define WWDG_CFR_W_0 (0x01UL << WWDG_CFR_W_Pos) /*!< 0x00000001 */
20205 #define WWDG_CFR_W_1 (0x02UL << WWDG_CFR_W_Pos) /*!< 0x00000002 */
20206 #define WWDG_CFR_W_2 (0x04UL << WWDG_CFR_W_Pos) /*!< 0x00000004 */
20207 #define WWDG_CFR_W_3 (0x08UL << WWDG_CFR_W_Pos) /*!< 0x00000008 */
20208 #define WWDG_CFR_W_4 (0x10UL << WWDG_CFR_W_Pos) /*!< 0x00000010 */
20209 #define WWDG_CFR_W_5 (0x20UL << WWDG_CFR_W_Pos) /*!< 0x00000020 */
20210 #define WWDG_CFR_W_6 (0x40UL << WWDG_CFR_W_Pos) /*!< 0x00000040 */
20211
20212 #define WWDG_CFR_EWI_Pos (9U)
20213 #define WWDG_CFR_EWI_Msk (0x1UL << WWDG_CFR_EWI_Pos) /*!< 0x00000200 */
20214 #define WWDG_CFR_EWI WWDG_CFR_EWI_Msk /*!<Early Wakeup Interrupt */
20215
20216 #define WWDG_CFR_WDGTB_Pos (11U)
20217 #define WWDG_CFR_WDGTB_Msk (0x7UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00003800 */
20218 #define WWDG_CFR_WDGTB WWDG_CFR_WDGTB_Msk /*!<WDGTB[2:0] bits (Timer Base) */
20219 #define WWDG_CFR_WDGTB_0 (0x1UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00000800 */
20220 #define WWDG_CFR_WDGTB_1 (0x2UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00001000 */
20221 #define WWDG_CFR_WDGTB_2 (0x4UL << WWDG_CFR_WDGTB_Pos) /*!< 0x00002000 */
20222
20223 /******************* Bit definition for WWDG_SR register ********************/
20224 #define WWDG_SR_EWIF_Pos (0U)
20225 #define WWDG_SR_EWIF_Msk (0x1UL << WWDG_SR_EWIF_Pos) /*!< 0x00000001 */
20226 #define WWDG_SR_EWIF WWDG_SR_EWIF_Msk /*!<Early Wakeup Interrupt Flag */
20227
20228
20229 /******************************************************************************/
20230 /* */
20231 /* DBG */
20232 /* */
20233 /******************************************************************************/
20234
20235 /******************** Bit definition for DBGMCU_IDCODE register *************/
20236 #define DBGMCU_IDCODE_DEV_ID_Pos (0U)
20237 #define DBGMCU_IDCODE_DEV_ID_Msk (0xFFFUL << DBGMCU_IDCODE_DEV_ID_Pos) /*!< 0x00000FFF */
20238 #define DBGMCU_IDCODE_DEV_ID DBGMCU_IDCODE_DEV_ID_Msk
20239 #define DBGMCU_IDCODE_REV_ID_Pos (16U)
20240 #define DBGMCU_IDCODE_REV_ID_Msk (0xFFFFUL << DBGMCU_IDCODE_REV_ID_Pos) /*!< 0xFFFF0000 */
20241 #define DBGMCU_IDCODE_REV_ID DBGMCU_IDCODE_REV_ID_Msk
20242
20243 /******************** Bit definition for DBGMCU_CR register *****************/
20244 #define DBGMCU_CR_DBG_SLEEPCD_Pos (0U)
20245 #define DBGMCU_CR_DBG_SLEEPCD_Msk (0x1UL << DBGMCU_CR_DBG_SLEEPCD_Pos) /*!< 0x00000001 */
20246 #define DBGMCU_CR_DBG_SLEEPCD DBGMCU_CR_DBG_SLEEPCD_Msk
20247 #define DBGMCU_CR_DBG_STOPCD_Pos (1U)
20248 #define DBGMCU_CR_DBG_STOPCD_Msk (0x1UL << DBGMCU_CR_DBG_STOPCD_Pos) /*!< 0x00000002 */
20249 #define DBGMCU_CR_DBG_STOPCD DBGMCU_CR_DBG_STOPCD_Msk
20250 #define DBGMCU_CR_DBG_STANDBYCD_Pos (2U)
20251 #define DBGMCU_CR_DBG_STANDBYCD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYCD_Pos) /*!< 0x00000004 */
20252 #define DBGMCU_CR_DBG_STANDBYCD DBGMCU_CR_DBG_STANDBYCD_Msk
20253
20254 /* Legacy defines */
20255 #define DBGMCU_CR_DBG_SLEEPD1_Pos DBGMCU_CR_DBG_SLEEPCD_Pos
20256 #define DBGMCU_CR_DBG_SLEEPD1_Msk DBGMCU_CR_DBG_SLEEPCD_Msk
20257 #define DBGMCU_CR_DBG_SLEEPD1 DBGMCU_CR_DBG_SLEEPCD
20258 #define DBGMCU_CR_DBG_STOPD1_Pos DBGMCU_CR_DBG_STOPCD_Pos
20259 #define DBGMCU_CR_DBG_STOPD1_Msk DBGMCU_CR_DBG_STOPCD_Msk
20260 #define DBGMCU_CR_DBG_STOPD1 DBGMCU_CR_DBG_STOPCD
20261 #define DBGMCU_CR_DBG_STANDBYD1_Pos DBGMCU_CR_DBG_STANDBYCD_Pos
20262 #define DBGMCU_CR_DBG_STANDBYD1_Msk DBGMCU_CR_DBG_STANDBYCD_Msk
20263 #define DBGMCU_CR_DBG_STANDBYD1 DBGMCU_CR_DBG_STANDBYCD
20264 #define DBGMCU_CR_DBG_STOPSRD_Pos (7U)
20265 #define DBGMCU_CR_DBG_STOPSRD_Msk (0x1UL << DBGMCU_CR_DBG_STOPSRD_Pos) /*!< 0x00000080 */
20266 #define DBGMCU_CR_DBG_STOPSRD DBGMCU_CR_DBG_STOPSRD_Msk
20267 #define DBGMCU_CR_DBG_STANDBYSRD_Pos (8U)
20268 #define DBGMCU_CR_DBG_STANDBYSRD_Msk (0x1UL << DBGMCU_CR_DBG_STANDBYSRD_Pos) /*!< 0x00000100 */
20269 #define DBGMCU_CR_DBG_STANDBYSRD DBGMCU_CR_DBG_STANDBYSRD_Msk
20270
20271 /* Legacy defines */
20272 #define DBGMCU_CR_DBG_STOPD3_Pos DBGMCU_CR_DBG_STOPSRD_Pos
20273 #define DBGMCU_CR_DBG_STOPD3_Msk DBGMCU_CR_DBG_STOPSRD_Msk
20274 #define DBGMCU_CR_DBG_STOPD3 DBGMCU_CR_DBG_STOPSRD
20275 #define DBGMCU_CR_DBG_STANDBYD3_Pos DBGMCU_CR_DBG_STANDBYSRD_Pos
20276 #define DBGMCU_CR_DBG_STANDBYD3_Msk DBGMCU_CR_DBG_STANDBYSRD_Msk
20277 #define DBGMCU_CR_DBG_STANDBYD3 DBGMCU_CR_DBG_STANDBYSRD
20278
20279 #define DBGMCU_CR_DBG_TRACECKEN_Pos (20U)
20280 #define DBGMCU_CR_DBG_TRACECKEN_Msk (0x1UL << DBGMCU_CR_DBG_TRACECKEN_Pos) /*!< 0x00100000 */
20281 #define DBGMCU_CR_DBG_TRACECKEN DBGMCU_CR_DBG_TRACECKEN_Msk
20282 #define DBGMCU_CR_DBG_CKCDEN_Pos (21U)
20283 #define DBGMCU_CR_DBG_CKCDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKCDEN_Pos) /*!< 0x00200000 */
20284 #define DBGMCU_CR_DBG_CKCDEN DBGMCU_CR_DBG_CKCDEN_Msk
20285 #define DBGMCU_CR_DBG_CKSRDEN_Pos (22U)
20286 #define DBGMCU_CR_DBG_CKSRDEN_Msk (0x1UL << DBGMCU_CR_DBG_CKSRDEN_Pos) /*!< 0x00400000 */
20287 #define DBGMCU_CR_DBG_CKSRDEN DBGMCU_CR_DBG_CKSRDEN_Msk
20288
20289 /* Legacy defines */
20290 #define DBGMCU_CR_DBG_CKD1EN_Pos DBGMCU_CR_DBG_CKCDEN_Pos
20291 #define DBGMCU_CR_DBG_CKD1EN_Msk DBGMCU_CR_DBG_CKCDEN_Msk
20292 #define DBGMCU_CR_DBG_CKD1EN DBGMCU_CR_DBG_CKCDEN
20293 #define DBGMCU_CR_DBG_CKD3EN_Pos DBGMCU_CR_DBG_CKSRDEN_Pos
20294 #define DBGMCU_CR_DBG_CKD3EN_Msk DBGMCU_CR_DBG_CKSRDEN_Msk
20295 #define DBGMCU_CR_DBG_CKD3EN DBGMCU_CR_DBG_CKSRDEN
20296
20297 #define DBGMCU_CR_DBG_TRGOEN_Pos (28U)
20298 #define DBGMCU_CR_DBG_TRGOEN_Msk (0x1UL << DBGMCU_CR_DBG_TRGOEN_Pos) /*!< 0x10000000 */
20299 #define DBGMCU_CR_DBG_TRGOEN DBGMCU_CR_DBG_TRGOEN_Msk
20300
20301 /******************** Bit definition for APB3FZ1 register ************/
20302 #define DBGMCU_APB3FZ1_DBG_WWDG1_Pos (6U)
20303 #define DBGMCU_APB3FZ1_DBG_WWDG1_Msk (0x1UL << DBGMCU_APB3FZ1_DBG_WWDG1_Pos) /*!< 0x00000040 */
20304 #define DBGMCU_APB3FZ1_DBG_WWDG1 DBGMCU_APB3FZ1_DBG_WWDG1_Msk
20305 /******************** Bit definition for APB1LFZ1 register ************/
20306 #define DBGMCU_APB1LFZ1_DBG_TIM2_Pos (0U)
20307 #define DBGMCU_APB1LFZ1_DBG_TIM2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM2_Pos) /*!< 0x00000001 */
20308 #define DBGMCU_APB1LFZ1_DBG_TIM2 DBGMCU_APB1LFZ1_DBG_TIM2_Msk
20309 #define DBGMCU_APB1LFZ1_DBG_TIM3_Pos (1U)
20310 #define DBGMCU_APB1LFZ1_DBG_TIM3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM3_Pos) /*!< 0x00000002 */
20311 #define DBGMCU_APB1LFZ1_DBG_TIM3 DBGMCU_APB1LFZ1_DBG_TIM3_Msk
20312 #define DBGMCU_APB1LFZ1_DBG_TIM4_Pos (2U)
20313 #define DBGMCU_APB1LFZ1_DBG_TIM4_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM4_Pos) /*!< 0x00000004 */
20314 #define DBGMCU_APB1LFZ1_DBG_TIM4 DBGMCU_APB1LFZ1_DBG_TIM4_Msk
20315 #define DBGMCU_APB1LFZ1_DBG_TIM5_Pos (3U)
20316 #define DBGMCU_APB1LFZ1_DBG_TIM5_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM5_Pos) /*!< 0x00000008 */
20317 #define DBGMCU_APB1LFZ1_DBG_TIM5 DBGMCU_APB1LFZ1_DBG_TIM5_Msk
20318 #define DBGMCU_APB1LFZ1_DBG_TIM6_Pos (4U)
20319 #define DBGMCU_APB1LFZ1_DBG_TIM6_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM6_Pos) /*!< 0x00000010 */
20320 #define DBGMCU_APB1LFZ1_DBG_TIM6 DBGMCU_APB1LFZ1_DBG_TIM6_Msk
20321 #define DBGMCU_APB1LFZ1_DBG_TIM7_Pos (5U)
20322 #define DBGMCU_APB1LFZ1_DBG_TIM7_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM7_Pos) /*!< 0x00000020 */
20323 #define DBGMCU_APB1LFZ1_DBG_TIM7 DBGMCU_APB1LFZ1_DBG_TIM7_Msk
20324 #define DBGMCU_APB1LFZ1_DBG_TIM12_Pos (6U)
20325 #define DBGMCU_APB1LFZ1_DBG_TIM12_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM12_Pos) /*!< 0x00000040 */
20326 #define DBGMCU_APB1LFZ1_DBG_TIM12 DBGMCU_APB1LFZ1_DBG_TIM12_Msk
20327 #define DBGMCU_APB1LFZ1_DBG_TIM13_Pos (7U)
20328 #define DBGMCU_APB1LFZ1_DBG_TIM13_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM13_Pos) /*!< 0x00000080 */
20329 #define DBGMCU_APB1LFZ1_DBG_TIM13 DBGMCU_APB1LFZ1_DBG_TIM13_Msk
20330 #define DBGMCU_APB1LFZ1_DBG_TIM14_Pos (8U)
20331 #define DBGMCU_APB1LFZ1_DBG_TIM14_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_TIM14_Pos) /*!< 0x00000100 */
20332 #define DBGMCU_APB1LFZ1_DBG_TIM14 DBGMCU_APB1LFZ1_DBG_TIM14_Msk
20333 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos (9U)
20334 #define DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_LPTIM1_Pos) /*!< 0x00000200 */
20335 #define DBGMCU_APB1LFZ1_DBG_LPTIM1 DBGMCU_APB1LFZ1_DBG_LPTIM1_Msk
20336 #define DBGMCU_APB1LFZ1_DBG_I2C1_Pos (21U)
20337 #define DBGMCU_APB1LFZ1_DBG_I2C1_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C1_Pos) /*!< 0x00200000 */
20338 #define DBGMCU_APB1LFZ1_DBG_I2C1 DBGMCU_APB1LFZ1_DBG_I2C1_Msk
20339 #define DBGMCU_APB1LFZ1_DBG_I2C2_Pos (22U)
20340 #define DBGMCU_APB1LFZ1_DBG_I2C2_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C2_Pos) /*!< 0x00400000 */
20341 #define DBGMCU_APB1LFZ1_DBG_I2C2 DBGMCU_APB1LFZ1_DBG_I2C2_Msk
20342 #define DBGMCU_APB1LFZ1_DBG_I2C3_Pos (23U)
20343 #define DBGMCU_APB1LFZ1_DBG_I2C3_Msk (0x1UL << DBGMCU_APB1LFZ1_DBG_I2C3_Pos) /*!< 0x00800000 */
20344 #define DBGMCU_APB1LFZ1_DBG_I2C3 DBGMCU_APB1LFZ1_DBG_I2C3_Msk
20345
20346 /******************** Bit definition for APB2FZ1 register ************/
20347 #define DBGMCU_APB2FZ1_DBG_TIM1_Pos (0U)
20348 #define DBGMCU_APB2FZ1_DBG_TIM1_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM1_Pos) /*!< 0x00000001 */
20349 #define DBGMCU_APB2FZ1_DBG_TIM1 DBGMCU_APB2FZ1_DBG_TIM1_Msk
20350 #define DBGMCU_APB2FZ1_DBG_TIM8_Pos (1U)
20351 #define DBGMCU_APB2FZ1_DBG_TIM8_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM8_Pos) /*!< 0x00000002 */
20352 #define DBGMCU_APB2FZ1_DBG_TIM8 DBGMCU_APB2FZ1_DBG_TIM8_Msk
20353 #define DBGMCU_APB2FZ1_DBG_TIM15_Pos (16U)
20354 #define DBGMCU_APB2FZ1_DBG_TIM15_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM15_Pos) /*!< 0x00010000 */
20355 #define DBGMCU_APB2FZ1_DBG_TIM15 DBGMCU_APB2FZ1_DBG_TIM15_Msk
20356 #define DBGMCU_APB2FZ1_DBG_TIM16_Pos (17U)
20357 #define DBGMCU_APB2FZ1_DBG_TIM16_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM16_Pos) /*!< 0x00020000 */
20358 #define DBGMCU_APB2FZ1_DBG_TIM16 DBGMCU_APB2FZ1_DBG_TIM16_Msk
20359 #define DBGMCU_APB2FZ1_DBG_TIM17_Pos (18U)
20360 #define DBGMCU_APB2FZ1_DBG_TIM17_Msk (0x1UL << DBGMCU_APB2FZ1_DBG_TIM17_Pos) /*!< 0x00040000 */
20361 #define DBGMCU_APB2FZ1_DBG_TIM17 DBGMCU_APB2FZ1_DBG_TIM17_Msk
20362 /******************** Bit definition for APB4FZ1 register ************/
20363 #define DBGMCU_APB4FZ1_DBG_I2C4_Pos (7U)
20364 #define DBGMCU_APB4FZ1_DBG_I2C4_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_I2C4_Pos) /*!< 0x00000080 */
20365 #define DBGMCU_APB4FZ1_DBG_I2C4 DBGMCU_APB4FZ1_DBG_I2C4_Msk
20366 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Pos (9U)
20367 #define DBGMCU_APB4FZ1_DBG_LPTIM2_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM2_Pos) /*!< 0x00000200 */
20368 #define DBGMCU_APB4FZ1_DBG_LPTIM2 DBGMCU_APB4FZ1_DBG_LPTIM2_Msk
20369 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Pos (10U)
20370 #define DBGMCU_APB4FZ1_DBG_LPTIM3_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_LPTIM3_Pos) /*!< 0x00000400 */
20371 #define DBGMCU_APB4FZ1_DBG_LPTIM3 DBGMCU_APB4FZ1_DBG_LPTIM3_Msk
20372 #define DBGMCU_APB4FZ1_DBG_RTC_Pos (16U)
20373 #define DBGMCU_APB4FZ1_DBG_RTC_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_RTC_Pos) /*!< 0x00010000 */
20374 #define DBGMCU_APB4FZ1_DBG_RTC DBGMCU_APB4FZ1_DBG_RTC_Msk
20375 #define DBGMCU_APB4FZ1_DBG_IWDG1_Pos (18U)
20376 #define DBGMCU_APB4FZ1_DBG_IWDG1_Msk (0x1UL << DBGMCU_APB4FZ1_DBG_IWDG1_Pos) /*!< 0x00040000 */
20377 #define DBGMCU_APB4FZ1_DBG_IWDG1 DBGMCU_APB4FZ1_DBG_IWDG1_Msk
20378 /******************************************************************************/
20379 /* */
20380 /* RAM ECC monitoring */
20381 /* */
20382 /******************************************************************************/
20383 /****************** Bit definition for RAMECC_IER register ******************/
20384 #define RAMECC_IER_GECCDEBWIE_Pos (3U)
20385 #define RAMECC_IER_GECCDEBWIE_Msk (0x1UL << RAMECC_IER_GECCDEBWIE_Pos) /*!< 0x00000008 */
20386 #define RAMECC_IER_GECCDEBWIE RAMECC_IER_GECCDEBWIE_Msk /*!< Global ECC double error on byte write (BW) interrupt enable */
20387 #define RAMECC_IER_GECCDEIE_Pos (2U)
20388 #define RAMECC_IER_GECCDEIE_Msk (0x1UL << RAMECC_IER_GECCDEIE_Pos) /*!< 0x00000004 */
20389 #define RAMECC_IER_GECCDEIE RAMECC_IER_GECCDEIE_Msk /*!< Global ECC double error interrupt enable */
20390 #define RAMECC_IER_GECCSEIE_Pos (1U)
20391 #define RAMECC_IER_GECCSEIE_Msk (0x1UL << RAMECC_IER_GECCSEIE_Pos) /*!< 0x00000002 */
20392 #define RAMECC_IER_GECCSEIE RAMECC_IER_GECCSEIE_Msk /*!< Global ECC single error interrupt enable */
20393 #define RAMECC_IER_GIE_Pos (0U)
20394 #define RAMECC_IER_GIE_Msk (0x1UL << RAMECC_IER_GIE_Pos) /*!< 0x00000001 */
20395 #define RAMECC_IER_GIE RAMECC_IER_GIE_Msk /*!< Global interrupt enable */
20396
20397 /******************* Bit definition for RAMECC_CR register ******************/
20398 #define RAMECC_CR_ECCELEN_Pos (5U)
20399 #define RAMECC_CR_ECCELEN_Msk (0x1UL << RAMECC_CR_ECCELEN_Pos) /*!< 0x00000020 */
20400 #define RAMECC_CR_ECCELEN RAMECC_CR_ECCELEN_Msk /*!< ECC error latching enable */
20401 #define RAMECC_CR_ECCDEBWIE_Pos (4U)
20402 #define RAMECC_CR_ECCDEBWIE_Msk (0x1UL << RAMECC_CR_ECCDEBWIE_Pos) /*!< 0x00000010 */
20403 #define RAMECC_CR_ECCDEBWIE RAMECC_CR_ECCDEBWIE_Msk /*!< ECC double error on byte write (BW) interrupt enable */
20404 #define RAMECC_CR_ECCDEIE_Pos (3U)
20405 #define RAMECC_CR_ECCDEIE_Msk (0x1UL << RAMECC_CR_ECCDEIE_Pos) /*!< 0x00000008 */
20406 #define RAMECC_CR_ECCDEIE RAMECC_CR_ECCDEIE_Msk /*!< ECC double error interrupt enable */
20407 #define RAMECC_CR_ECCSEIE_Pos (2U)
20408 #define RAMECC_CR_ECCSEIE_Msk (0x1UL << RAMECC_CR_ECCSEIE_Pos) /*!< 0x00000004 */
20409 #define RAMECC_CR_ECCSEIE RAMECC_CR_ECCSEIE_Msk /*!< ECC single error interrupt enable */
20410
20411 /******************* Bit definition for RAMECC_SR register ******************/
20412 #define RAMECC_SR_DEBWDF_Pos (2U)
20413 #define RAMECC_SR_DEBWDF_Msk (0x1UL << RAMECC_SR_DEBWDF_Pos) /*!< 0x00000004 */
20414 #define RAMECC_SR_DEBWDF RAMECC_SR_DEBWDF_Msk /*!< ECC double error on byte write (BW) detected flag */
20415 #define RAMECC_SR_DEDF_Pos (1U)
20416 #define RAMECC_SR_DEDF_Msk (0x1UL << RAMECC_SR_DEDF_Pos) /*!< 0x00000002 */
20417 #define RAMECC_SR_DEDF RAMECC_SR_DEDF_Msk /*!< ECC double error detected flag */
20418 #define RAMECC_SR_SEDCF_Pos (0U)
20419 #define RAMECC_SR_SEDCF_Msk (0x1UL << RAMECC_SR_SEDCF_Pos) /*!< 0x00000001 */
20420 #define RAMECC_SR_SEDCF RAMECC_SR_SEDCF_Msk /*!< ECC single error detected and corrected flag */
20421
20422 /****************** Bit definition for RAMECC_FAR register ******************/
20423 #define RAMECC_FAR_FADD_Pos (0U)
20424 #define RAMECC_FAR_FADD_Msk (0xFFFFFFFFUL << RAMECC_FAR_FADD_Pos) /*!< 0xFFFFFFFF */
20425 #define RAMECC_FAR_FADD RAMECC_FAR_FADD_Msk /*!< ECC error failing address */
20426
20427 /****************** Bit definition for RAMECC_FDRL register *****************/
20428 #define RAMECC_FAR_FDATAL_Pos (0U)
20429 #define RAMECC_FAR_FDATAL_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAL_Pos)/*!< 0xFFFFFFFF */
20430 #define RAMECC_FAR_FDATAL RAMECC_FAR_FDATAL_Msk /*!< ECC error failing address */
20431
20432 /****************** Bit definition for RAMECC_FDRH register *****************/
20433 #define RAMECC_FAR_FDATAH_Pos (0U)
20434 #define RAMECC_FAR_FDATAH_Msk (0xFFFFFFFFUL << RAMECC_FAR_FDATAH_Pos)/*!< 0xFFFFFFFF */
20435 #define RAMECC_FAR_FDATAH RAMECC_FAR_FDATAH_Msk /* Failing data high (64-bit memory) */
20436
20437 /***************** Bit definition for RAMECC_FECR register ******************/
20438 #define RAMECC_FECR_FEC_Pos (0U)
20439 #define RAMECC_FECR_FEC_Msk (0xFFFFFFFFUL << RAMECC_FECR_FEC_Pos) /*!< 0xFFFFFFFF */
20440 #define RAMECC_FECR_FEC RAMECC_FECR_FEC_Msk /*!< Failing error code */
20441
20442 /******************************************************************************/
20443 /* */
20444 /* MDIOS */
20445 /* */
20446 /******************************************************************************/
20447 /******************** Bit definition for MDIOS_CR register *******************/
20448 #define MDIOS_CR_EN_Pos (0U)
20449 #define MDIOS_CR_EN_Msk (0x1UL << MDIOS_CR_EN_Pos) /*!< 0x00000001 */
20450 #define MDIOS_CR_EN MDIOS_CR_EN_Msk /*!< MDIOS slave peripheral enable */
20451 #define MDIOS_CR_WRIE_Pos (1U)
20452 #define MDIOS_CR_WRIE_Msk (0x1UL << MDIOS_CR_WRIE_Pos) /*!< 0x00000002 */
20453 #define MDIOS_CR_WRIE MDIOS_CR_WRIE_Msk /*!< MDIOS slave register write interrupt enable. */
20454 #define MDIOS_CR_RDIE_Pos (2U)
20455 #define MDIOS_CR_RDIE_Msk (0x1UL << MDIOS_CR_RDIE_Pos) /*!< 0x00000004 */
20456 #define MDIOS_CR_RDIE MDIOS_CR_RDIE_Msk /*!< MDIOS slave register read interrupt enable. */
20457 #define MDIOS_CR_EIE_Pos (3U)
20458 #define MDIOS_CR_EIE_Msk (0x1UL << MDIOS_CR_EIE_Pos) /*!< 0x00000008 */
20459 #define MDIOS_CR_EIE MDIOS_CR_EIE_Msk /*!< MDIOS slave register error interrupt enable. */
20460 #define MDIOS_CR_DPC_Pos (7U)
20461 #define MDIOS_CR_DPC_Msk (0x1UL << MDIOS_CR_DPC_Pos) /*!< 0x00000080 */
20462 #define MDIOS_CR_DPC MDIOS_CR_DPC_Msk /*!< MDIOS slave disable preamble check. */
20463 #define MDIOS_CR_PORT_ADDRESS_Pos (8U)
20464 #define MDIOS_CR_PORT_ADDRESS_Msk (0x1FUL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001F00 */
20465 #define MDIOS_CR_PORT_ADDRESS MDIOS_CR_PORT_ADDRESS_Msk /*!< MDIOS slave port address mask. */
20466 #define MDIOS_CR_PORT_ADDRESS_0 (0x01UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000100 */
20467 #define MDIOS_CR_PORT_ADDRESS_1 (0x02UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000200 */
20468 #define MDIOS_CR_PORT_ADDRESS_2 (0x04UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000400 */
20469 #define MDIOS_CR_PORT_ADDRESS_3 (0x08UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00000800 */
20470 #define MDIOS_CR_PORT_ADDRESS_4 (0x10UL << MDIOS_CR_PORT_ADDRESS_Pos) /*!< 0x00001000 */
20471
20472 /******************** Bit definition for MDIOS_SR register *******************/
20473 #define MDIOS_SR_PERF_Pos (0U)
20474 #define MDIOS_SR_PERF_Msk (0x1UL << MDIOS_SR_PERF_Pos) /*!< 0x00000001 */
20475 #define MDIOS_SR_PERF MDIOS_SR_PERF_Msk /*!< MDIOS slave turnaround error flag*/
20476 #define MDIOS_SR_SERF_Pos (1U)
20477 #define MDIOS_SR_SERF_Msk (0x1UL << MDIOS_SR_SERF_Pos) /*!< 0x00000002 */
20478 #define MDIOS_SR_SERF MDIOS_SR_SERF_Msk /*!< MDIOS slave start error flag */
20479 #define MDIOS_SR_TERF_Pos (2U)
20480 #define MDIOS_SR_TERF_Msk (0x1UL << MDIOS_SR_TERF_Pos) /*!< 0x00000004 */
20481 #define MDIOS_SR_TERF MDIOS_SR_TERF_Msk /*!< MDIOS slave preamble error flag */
20482
20483 /******************** Bit definition for MDIOS_CLRFR register *******************/
20484 #define MDIOS_SR_CPERF_Pos (0U)
20485 #define MDIOS_SR_CPERF_Msk (0x1UL << MDIOS_SR_CPERF_Pos) /*!< 0x00000001 */
20486 #define MDIOS_SR_CPERF MDIOS_SR_CPERF_Msk /*!< MDIOS slave Clear the turnaround error flag */
20487 #define MDIOS_SR_CSERF_Pos (1U)
20488 #define MDIOS_SR_CSERF_Msk (0x1UL << MDIOS_SR_CSERF_Pos) /*!< 0x00000002 */
20489 #define MDIOS_SR_CSERF MDIOS_SR_CSERF_Msk /*!< MDIOS slave Clear the start error flag */
20490 #define MDIOS_SR_CTERF_Pos (2U)
20491 #define MDIOS_SR_CTERF_Msk (0x1UL << MDIOS_SR_CTERF_Pos) /*!< 0x00000004 */
20492 #define MDIOS_SR_CTERF MDIOS_SR_CTERF_Msk /*!< MDIOS slave Clear the preamble error flag */
20493
20494 /******************************************************************************/
20495 /* */
20496 /* USB_OTG */
20497 /* */
20498 /******************************************************************************/
20499 /******************** Bit definition forUSB_OTG_GOTGCTL register ********************/
20500 #define USB_OTG_GOTGCTL_SRQSCS_Pos (0U)
20501 #define USB_OTG_GOTGCTL_SRQSCS_Msk (0x1UL << USB_OTG_GOTGCTL_SRQSCS_Pos) /*!< 0x00000001 */
20502 #define USB_OTG_GOTGCTL_SRQSCS USB_OTG_GOTGCTL_SRQSCS_Msk /*!< Session request success */
20503 #define USB_OTG_GOTGCTL_SRQ_Pos (1U)
20504 #define USB_OTG_GOTGCTL_SRQ_Msk (0x1UL << USB_OTG_GOTGCTL_SRQ_Pos) /*!< 0x00000002 */
20505 #define USB_OTG_GOTGCTL_SRQ USB_OTG_GOTGCTL_SRQ_Msk /*!< Session request */
20506 #define USB_OTG_GOTGCTL_VBVALOEN_Pos (2U)
20507 #define USB_OTG_GOTGCTL_VBVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOEN_Pos) /*!< 0x00000004 */
20508 #define USB_OTG_GOTGCTL_VBVALOEN USB_OTG_GOTGCTL_VBVALOEN_Msk /*!< VBUS valid override enable */
20509 #define USB_OTG_GOTGCTL_VBVALOVAL_Pos (3U)
20510 #define USB_OTG_GOTGCTL_VBVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_VBVALOVAL_Pos) /*!< 0x00000008 */
20511 #define USB_OTG_GOTGCTL_VBVALOVAL USB_OTG_GOTGCTL_VBVALOVAL_Msk /*!< VBUS valid override value */
20512 #define USB_OTG_GOTGCTL_AVALOEN_Pos (4U)
20513 #define USB_OTG_GOTGCTL_AVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOEN_Pos) /*!< 0x00000010 */
20514 #define USB_OTG_GOTGCTL_AVALOEN USB_OTG_GOTGCTL_AVALOEN_Msk /*!< A-peripheral session valid override enable */
20515 #define USB_OTG_GOTGCTL_AVALOVAL_Pos (5U)
20516 #define USB_OTG_GOTGCTL_AVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_AVALOVAL_Pos) /*!< 0x00000020 */
20517 #define USB_OTG_GOTGCTL_AVALOVAL USB_OTG_GOTGCTL_AVALOVAL_Msk /*!< A-peripheral session valid override value */
20518 #define USB_OTG_GOTGCTL_BVALOEN_Pos (6U)
20519 #define USB_OTG_GOTGCTL_BVALOEN_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOEN_Pos) /*!< 0x00000040 */
20520 #define USB_OTG_GOTGCTL_BVALOEN USB_OTG_GOTGCTL_BVALOEN_Msk /*!< B-peripheral session valid override enable */
20521 #define USB_OTG_GOTGCTL_BVALOVAL_Pos (7U)
20522 #define USB_OTG_GOTGCTL_BVALOVAL_Msk (0x1UL << USB_OTG_GOTGCTL_BVALOVAL_Pos) /*!< 0x00000080 */
20523 #define USB_OTG_GOTGCTL_BVALOVAL USB_OTG_GOTGCTL_BVALOVAL_Msk /*!< B-peripheral session valid override value */
20524 #define USB_OTG_GOTGCTL_HNGSCS_Pos (8U)
20525 #define USB_OTG_GOTGCTL_HNGSCS_Msk (0x1UL << USB_OTG_GOTGCTL_HNGSCS_Pos) /*!< 0x00000100 */
20526 #define USB_OTG_GOTGCTL_HNGSCS USB_OTG_GOTGCTL_HNGSCS_Msk /*!< Host set HNP enable */
20527 #define USB_OTG_GOTGCTL_HNPRQ_Pos (9U)
20528 #define USB_OTG_GOTGCTL_HNPRQ_Msk (0x1UL << USB_OTG_GOTGCTL_HNPRQ_Pos) /*!< 0x00000200 */
20529 #define USB_OTG_GOTGCTL_HNPRQ USB_OTG_GOTGCTL_HNPRQ_Msk /*!< HNP request */
20530 #define USB_OTG_GOTGCTL_HSHNPEN_Pos (10U)
20531 #define USB_OTG_GOTGCTL_HSHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_HSHNPEN_Pos) /*!< 0x00000400 */
20532 #define USB_OTG_GOTGCTL_HSHNPEN USB_OTG_GOTGCTL_HSHNPEN_Msk /*!< Host set HNP enable */
20533 #define USB_OTG_GOTGCTL_DHNPEN_Pos (11U)
20534 #define USB_OTG_GOTGCTL_DHNPEN_Msk (0x1UL << USB_OTG_GOTGCTL_DHNPEN_Pos) /*!< 0x00000800 */
20535 #define USB_OTG_GOTGCTL_DHNPEN USB_OTG_GOTGCTL_DHNPEN_Msk /*!< Device HNP enabled */
20536 #define USB_OTG_GOTGCTL_EHEN_Pos (12U)
20537 #define USB_OTG_GOTGCTL_EHEN_Msk (0x1UL << USB_OTG_GOTGCTL_EHEN_Pos) /*!< 0x00001000 */
20538 #define USB_OTG_GOTGCTL_EHEN USB_OTG_GOTGCTL_EHEN_Msk /*!< Embedded host enable */
20539 #define USB_OTG_GOTGCTL_CIDSTS_Pos (16U)
20540 #define USB_OTG_GOTGCTL_CIDSTS_Msk (0x1UL << USB_OTG_GOTGCTL_CIDSTS_Pos) /*!< 0x00010000 */
20541 #define USB_OTG_GOTGCTL_CIDSTS USB_OTG_GOTGCTL_CIDSTS_Msk /*!< Connector ID status */
20542 #define USB_OTG_GOTGCTL_DBCT_Pos (17U)
20543 #define USB_OTG_GOTGCTL_DBCT_Msk (0x1UL << USB_OTG_GOTGCTL_DBCT_Pos) /*!< 0x00020000 */
20544 #define USB_OTG_GOTGCTL_DBCT USB_OTG_GOTGCTL_DBCT_Msk /*!< Long/short debounce time */
20545 #define USB_OTG_GOTGCTL_ASVLD_Pos (18U)
20546 #define USB_OTG_GOTGCTL_ASVLD_Msk (0x1UL << USB_OTG_GOTGCTL_ASVLD_Pos) /*!< 0x00040000 */
20547 #define USB_OTG_GOTGCTL_ASVLD USB_OTG_GOTGCTL_ASVLD_Msk /*!< A-session valid */
20548 #define USB_OTG_GOTGCTL_BSESVLD_Pos (19U)
20549 #define USB_OTG_GOTGCTL_BSESVLD_Msk (0x1UL << USB_OTG_GOTGCTL_BSESVLD_Pos) /*!< 0x00080000 */
20550 #define USB_OTG_GOTGCTL_BSESVLD USB_OTG_GOTGCTL_BSESVLD_Msk /*!< B-session valid */
20551 #define USB_OTG_GOTGCTL_OTGVER_Pos (20U)
20552 #define USB_OTG_GOTGCTL_OTGVER_Msk (0x1UL << USB_OTG_GOTGCTL_OTGVER_Pos) /*!< 0x00100000 */
20553 #define USB_OTG_GOTGCTL_OTGVER USB_OTG_GOTGCTL_OTGVER_Msk /*!< OTG version */
20554
20555 /******************** Bit definition forUSB_OTG_HCFG register ********************/
20556
20557 #define USB_OTG_HCFG_FSLSPCS_Pos (0U)
20558 #define USB_OTG_HCFG_FSLSPCS_Msk (0x3UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000003 */
20559 #define USB_OTG_HCFG_FSLSPCS USB_OTG_HCFG_FSLSPCS_Msk /*!< FS/LS PHY clock select */
20560 #define USB_OTG_HCFG_FSLSPCS_0 (0x1UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000001 */
20561 #define USB_OTG_HCFG_FSLSPCS_1 (0x2UL << USB_OTG_HCFG_FSLSPCS_Pos) /*!< 0x00000002 */
20562 #define USB_OTG_HCFG_FSLSS_Pos (2U)
20563 #define USB_OTG_HCFG_FSLSS_Msk (0x1UL << USB_OTG_HCFG_FSLSS_Pos) /*!< 0x00000004 */
20564 #define USB_OTG_HCFG_FSLSS USB_OTG_HCFG_FSLSS_Msk /*!< FS- and LS-only support */
20565
20566 /******************** Bit definition forUSB_OTG_DCFG register ********************/
20567
20568 #define USB_OTG_DCFG_DSPD_Pos (0U)
20569 #define USB_OTG_DCFG_DSPD_Msk (0x3UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000003 */
20570 #define USB_OTG_DCFG_DSPD USB_OTG_DCFG_DSPD_Msk /*!< Device speed */
20571 #define USB_OTG_DCFG_DSPD_0 (0x1UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000001 */
20572 #define USB_OTG_DCFG_DSPD_1 (0x2UL << USB_OTG_DCFG_DSPD_Pos) /*!< 0x00000002 */
20573 #define USB_OTG_DCFG_NZLSOHSK_Pos (2U)
20574 #define USB_OTG_DCFG_NZLSOHSK_Msk (0x1UL << USB_OTG_DCFG_NZLSOHSK_Pos) /*!< 0x00000004 */
20575 #define USB_OTG_DCFG_NZLSOHSK USB_OTG_DCFG_NZLSOHSK_Msk /*!< Nonzero-length status OUT handshake */
20576
20577 #define USB_OTG_DCFG_DAD_Pos (4U)
20578 #define USB_OTG_DCFG_DAD_Msk (0x7FUL << USB_OTG_DCFG_DAD_Pos) /*!< 0x000007F0 */
20579 #define USB_OTG_DCFG_DAD USB_OTG_DCFG_DAD_Msk /*!< Device address */
20580 #define USB_OTG_DCFG_DAD_0 (0x01UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000010 */
20581 #define USB_OTG_DCFG_DAD_1 (0x02UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000020 */
20582 #define USB_OTG_DCFG_DAD_2 (0x04UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000040 */
20583 #define USB_OTG_DCFG_DAD_3 (0x08UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000080 */
20584 #define USB_OTG_DCFG_DAD_4 (0x10UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000100 */
20585 #define USB_OTG_DCFG_DAD_5 (0x20UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000200 */
20586 #define USB_OTG_DCFG_DAD_6 (0x40UL << USB_OTG_DCFG_DAD_Pos) /*!< 0x00000400 */
20587
20588 #define USB_OTG_DCFG_PFIVL_Pos (11U)
20589 #define USB_OTG_DCFG_PFIVL_Msk (0x3UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001800 */
20590 #define USB_OTG_DCFG_PFIVL USB_OTG_DCFG_PFIVL_Msk /*!< Periodic (micro)frame interval */
20591 #define USB_OTG_DCFG_PFIVL_0 (0x1UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00000800 */
20592 #define USB_OTG_DCFG_PFIVL_1 (0x2UL << USB_OTG_DCFG_PFIVL_Pos) /*!< 0x00001000 */
20593
20594 #define USB_OTG_DCFG_PERSCHIVL_Pos (24U)
20595 #define USB_OTG_DCFG_PERSCHIVL_Msk (0x3UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x03000000 */
20596 #define USB_OTG_DCFG_PERSCHIVL USB_OTG_DCFG_PERSCHIVL_Msk /*!< Periodic scheduling interval */
20597 #define USB_OTG_DCFG_PERSCHIVL_0 (0x1UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x01000000 */
20598 #define USB_OTG_DCFG_PERSCHIVL_1 (0x2UL << USB_OTG_DCFG_PERSCHIVL_Pos) /*!< 0x02000000 */
20599
20600 /******************** Bit definition forUSB_OTG_PCGCR register ********************/
20601 #define USB_OTG_PCGCR_STPPCLK_Pos (0U)
20602 #define USB_OTG_PCGCR_STPPCLK_Msk (0x1UL << USB_OTG_PCGCR_STPPCLK_Pos) /*!< 0x00000001 */
20603 #define USB_OTG_PCGCR_STPPCLK USB_OTG_PCGCR_STPPCLK_Msk /*!< Stop PHY clock */
20604 #define USB_OTG_PCGCR_GATEHCLK_Pos (1U)
20605 #define USB_OTG_PCGCR_GATEHCLK_Msk (0x1UL << USB_OTG_PCGCR_GATEHCLK_Pos) /*!< 0x00000002 */
20606 #define USB_OTG_PCGCR_GATEHCLK USB_OTG_PCGCR_GATEHCLK_Msk /*!< Gate HCLK */
20607 #define USB_OTG_PCGCR_PHYSUSP_Pos (4U)
20608 #define USB_OTG_PCGCR_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCR_PHYSUSP_Pos) /*!< 0x00000010 */
20609 #define USB_OTG_PCGCR_PHYSUSP USB_OTG_PCGCR_PHYSUSP_Msk /*!< PHY suspended */
20610
20611 /******************** Bit definition forUSB_OTG_GOTGINT register ********************/
20612 #define USB_OTG_GOTGINT_SEDET_Pos (2U)
20613 #define USB_OTG_GOTGINT_SEDET_Msk (0x1UL << USB_OTG_GOTGINT_SEDET_Pos) /*!< 0x00000004 */
20614 #define USB_OTG_GOTGINT_SEDET USB_OTG_GOTGINT_SEDET_Msk /*!< Session end detected */
20615 #define USB_OTG_GOTGINT_SRSSCHG_Pos (8U)
20616 #define USB_OTG_GOTGINT_SRSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_SRSSCHG_Pos) /*!< 0x00000100 */
20617 #define USB_OTG_GOTGINT_SRSSCHG USB_OTG_GOTGINT_SRSSCHG_Msk /*!< Session request success status change */
20618 #define USB_OTG_GOTGINT_HNSSCHG_Pos (9U)
20619 #define USB_OTG_GOTGINT_HNSSCHG_Msk (0x1UL << USB_OTG_GOTGINT_HNSSCHG_Pos) /*!< 0x00000200 */
20620 #define USB_OTG_GOTGINT_HNSSCHG USB_OTG_GOTGINT_HNSSCHG_Msk /*!< Host negotiation success status change */
20621 #define USB_OTG_GOTGINT_HNGDET_Pos (17U)
20622 #define USB_OTG_GOTGINT_HNGDET_Msk (0x1UL << USB_OTG_GOTGINT_HNGDET_Pos) /*!< 0x00020000 */
20623 #define USB_OTG_GOTGINT_HNGDET USB_OTG_GOTGINT_HNGDET_Msk /*!< Host negotiation detected */
20624 #define USB_OTG_GOTGINT_ADTOCHG_Pos (18U)
20625 #define USB_OTG_GOTGINT_ADTOCHG_Msk (0x1UL << USB_OTG_GOTGINT_ADTOCHG_Pos) /*!< 0x00040000 */
20626 #define USB_OTG_GOTGINT_ADTOCHG USB_OTG_GOTGINT_ADTOCHG_Msk /*!< A-device timeout change */
20627 #define USB_OTG_GOTGINT_DBCDNE_Pos (19U)
20628 #define USB_OTG_GOTGINT_DBCDNE_Msk (0x1UL << USB_OTG_GOTGINT_DBCDNE_Pos) /*!< 0x00080000 */
20629 #define USB_OTG_GOTGINT_DBCDNE USB_OTG_GOTGINT_DBCDNE_Msk /*!< Debounce done */
20630
20631 /******************** Bit definition forUSB_OTG_DCTL register ********************/
20632 #define USB_OTG_DCTL_RWUSIG_Pos (0U)
20633 #define USB_OTG_DCTL_RWUSIG_Msk (0x1UL << USB_OTG_DCTL_RWUSIG_Pos) /*!< 0x00000001 */
20634 #define USB_OTG_DCTL_RWUSIG USB_OTG_DCTL_RWUSIG_Msk /*!< Remote wakeup signaling */
20635 #define USB_OTG_DCTL_SDIS_Pos (1U)
20636 #define USB_OTG_DCTL_SDIS_Msk (0x1UL << USB_OTG_DCTL_SDIS_Pos) /*!< 0x00000002 */
20637 #define USB_OTG_DCTL_SDIS USB_OTG_DCTL_SDIS_Msk /*!< Soft disconnect */
20638 #define USB_OTG_DCTL_GINSTS_Pos (2U)
20639 #define USB_OTG_DCTL_GINSTS_Msk (0x1UL << USB_OTG_DCTL_GINSTS_Pos) /*!< 0x00000004 */
20640 #define USB_OTG_DCTL_GINSTS USB_OTG_DCTL_GINSTS_Msk /*!< Global IN NAK status */
20641 #define USB_OTG_DCTL_GONSTS_Pos (3U)
20642 #define USB_OTG_DCTL_GONSTS_Msk (0x1UL << USB_OTG_DCTL_GONSTS_Pos) /*!< 0x00000008 */
20643 #define USB_OTG_DCTL_GONSTS USB_OTG_DCTL_GONSTS_Msk /*!< Global OUT NAK status */
20644
20645 #define USB_OTG_DCTL_TCTL_Pos (4U)
20646 #define USB_OTG_DCTL_TCTL_Msk (0x7UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000070 */
20647 #define USB_OTG_DCTL_TCTL USB_OTG_DCTL_TCTL_Msk /*!< Test control */
20648 #define USB_OTG_DCTL_TCTL_0 (0x1UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000010 */
20649 #define USB_OTG_DCTL_TCTL_1 (0x2UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000020 */
20650 #define USB_OTG_DCTL_TCTL_2 (0x4UL << USB_OTG_DCTL_TCTL_Pos) /*!< 0x00000040 */
20651 #define USB_OTG_DCTL_SGINAK_Pos (7U)
20652 #define USB_OTG_DCTL_SGINAK_Msk (0x1UL << USB_OTG_DCTL_SGINAK_Pos) /*!< 0x00000080 */
20653 #define USB_OTG_DCTL_SGINAK USB_OTG_DCTL_SGINAK_Msk /*!< Set global IN NAK */
20654 #define USB_OTG_DCTL_CGINAK_Pos (8U)
20655 #define USB_OTG_DCTL_CGINAK_Msk (0x1UL << USB_OTG_DCTL_CGINAK_Pos) /*!< 0x00000100 */
20656 #define USB_OTG_DCTL_CGINAK USB_OTG_DCTL_CGINAK_Msk /*!< Clear global IN NAK */
20657 #define USB_OTG_DCTL_SGONAK_Pos (9U)
20658 #define USB_OTG_DCTL_SGONAK_Msk (0x1UL << USB_OTG_DCTL_SGONAK_Pos) /*!< 0x00000200 */
20659 #define USB_OTG_DCTL_SGONAK USB_OTG_DCTL_SGONAK_Msk /*!< Set global OUT NAK */
20660 #define USB_OTG_DCTL_CGONAK_Pos (10U)
20661 #define USB_OTG_DCTL_CGONAK_Msk (0x1UL << USB_OTG_DCTL_CGONAK_Pos) /*!< 0x00000400 */
20662 #define USB_OTG_DCTL_CGONAK USB_OTG_DCTL_CGONAK_Msk /*!< Clear global OUT NAK */
20663 #define USB_OTG_DCTL_POPRGDNE_Pos (11U)
20664 #define USB_OTG_DCTL_POPRGDNE_Msk (0x1UL << USB_OTG_DCTL_POPRGDNE_Pos) /*!< 0x00000800 */
20665 #define USB_OTG_DCTL_POPRGDNE USB_OTG_DCTL_POPRGDNE_Msk /*!< Power-on programming done */
20666
20667 /******************** Bit definition forUSB_OTG_HFIR register ********************/
20668 #define USB_OTG_HFIR_FRIVL_Pos (0U)
20669 #define USB_OTG_HFIR_FRIVL_Msk (0xFFFFUL << USB_OTG_HFIR_FRIVL_Pos) /*!< 0x0000FFFF */
20670 #define USB_OTG_HFIR_FRIVL USB_OTG_HFIR_FRIVL_Msk /*!< Frame interval */
20671
20672 /******************** Bit definition forUSB_OTG_HFNUM register ********************/
20673 #define USB_OTG_HFNUM_FRNUM_Pos (0U)
20674 #define USB_OTG_HFNUM_FRNUM_Msk (0xFFFFUL << USB_OTG_HFNUM_FRNUM_Pos) /*!< 0x0000FFFF */
20675 #define USB_OTG_HFNUM_FRNUM USB_OTG_HFNUM_FRNUM_Msk /*!< Frame number */
20676 #define USB_OTG_HFNUM_FTREM_Pos (16U)
20677 #define USB_OTG_HFNUM_FTREM_Msk (0xFFFFUL << USB_OTG_HFNUM_FTREM_Pos) /*!< 0xFFFF0000 */
20678 #define USB_OTG_HFNUM_FTREM USB_OTG_HFNUM_FTREM_Msk /*!< Frame time remaining */
20679
20680 /******************** Bit definition forUSB_OTG_DSTS register ********************/
20681 #define USB_OTG_DSTS_SUSPSTS_Pos (0U)
20682 #define USB_OTG_DSTS_SUSPSTS_Msk (0x1UL << USB_OTG_DSTS_SUSPSTS_Pos) /*!< 0x00000001 */
20683 #define USB_OTG_DSTS_SUSPSTS USB_OTG_DSTS_SUSPSTS_Msk /*!< Suspend status */
20684
20685 #define USB_OTG_DSTS_ENUMSPD_Pos (1U)
20686 #define USB_OTG_DSTS_ENUMSPD_Msk (0x3UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000006 */
20687 #define USB_OTG_DSTS_ENUMSPD USB_OTG_DSTS_ENUMSPD_Msk /*!< Enumerated speed */
20688 #define USB_OTG_DSTS_ENUMSPD_0 (0x1UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000002 */
20689 #define USB_OTG_DSTS_ENUMSPD_1 (0x2UL << USB_OTG_DSTS_ENUMSPD_Pos) /*!< 0x00000004 */
20690 #define USB_OTG_DSTS_EERR_Pos (3U)
20691 #define USB_OTG_DSTS_EERR_Msk (0x1UL << USB_OTG_DSTS_EERR_Pos) /*!< 0x00000008 */
20692 #define USB_OTG_DSTS_EERR USB_OTG_DSTS_EERR_Msk /*!< Erratic error */
20693 #define USB_OTG_DSTS_FNSOF_Pos (8U)
20694 #define USB_OTG_DSTS_FNSOF_Msk (0x3FFFUL << USB_OTG_DSTS_FNSOF_Pos) /*!< 0x003FFF00 */
20695 #define USB_OTG_DSTS_FNSOF USB_OTG_DSTS_FNSOF_Msk /*!< Frame number of the received SOF */
20696
20697 /******************** Bit definition forUSB_OTG_GAHBCFG register ********************/
20698 #define USB_OTG_GAHBCFG_GINT_Pos (0U)
20699 #define USB_OTG_GAHBCFG_GINT_Msk (0x1UL << USB_OTG_GAHBCFG_GINT_Pos) /*!< 0x00000001 */
20700 #define USB_OTG_GAHBCFG_GINT USB_OTG_GAHBCFG_GINT_Msk /*!< Global interrupt mask */
20701
20702 #define USB_OTG_GAHBCFG_HBSTLEN_Pos (1U)
20703 #define USB_OTG_GAHBCFG_HBSTLEN_Msk (0xFUL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< 0x0000001E */
20704 #define USB_OTG_GAHBCFG_HBSTLEN USB_OTG_GAHBCFG_HBSTLEN_Msk /*!< Burst length/type */
20705 #define USB_OTG_GAHBCFG_HBSTLEN_0 (0x0UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< Single */
20706 #define USB_OTG_GAHBCFG_HBSTLEN_1 (0x1UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR */
20707 #define USB_OTG_GAHBCFG_HBSTLEN_2 (0x3UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR4 */
20708 #define USB_OTG_GAHBCFG_HBSTLEN_3 (0x5UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR8 */
20709 #define USB_OTG_GAHBCFG_HBSTLEN_4 (0x7UL << USB_OTG_GAHBCFG_HBSTLEN_Pos) /*!< INCR16 */
20710 #define USB_OTG_GAHBCFG_DMAEN_Pos (5U)
20711 #define USB_OTG_GAHBCFG_DMAEN_Msk (0x1UL << USB_OTG_GAHBCFG_DMAEN_Pos) /*!< 0x00000020 */
20712 #define USB_OTG_GAHBCFG_DMAEN USB_OTG_GAHBCFG_DMAEN_Msk /*!< DMA enable */
20713 #define USB_OTG_GAHBCFG_TXFELVL_Pos (7U)
20714 #define USB_OTG_GAHBCFG_TXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_TXFELVL_Pos) /*!< 0x00000080 */
20715 #define USB_OTG_GAHBCFG_TXFELVL USB_OTG_GAHBCFG_TXFELVL_Msk /*!< TxFIFO empty level */
20716 #define USB_OTG_GAHBCFG_PTXFELVL_Pos (8U)
20717 #define USB_OTG_GAHBCFG_PTXFELVL_Msk (0x1UL << USB_OTG_GAHBCFG_PTXFELVL_Pos) /*!< 0x00000100 */
20718 #define USB_OTG_GAHBCFG_PTXFELVL USB_OTG_GAHBCFG_PTXFELVL_Msk /*!< Periodic TxFIFO empty level */
20719
20720 /******************** Bit definition forUSB_OTG_GUSBCFG register ********************/
20721
20722 #define USB_OTG_GUSBCFG_TOCAL_Pos (0U)
20723 #define USB_OTG_GUSBCFG_TOCAL_Msk (0x7UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000007 */
20724 #define USB_OTG_GUSBCFG_TOCAL USB_OTG_GUSBCFG_TOCAL_Msk /*!< FS timeout calibration */
20725 #define USB_OTG_GUSBCFG_TOCAL_0 (0x1UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000001 */
20726 #define USB_OTG_GUSBCFG_TOCAL_1 (0x2UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000002 */
20727 #define USB_OTG_GUSBCFG_TOCAL_2 (0x4UL << USB_OTG_GUSBCFG_TOCAL_Pos) /*!< 0x00000004 */
20728 #define USB_OTG_GUSBCFG_PHYSEL_Pos (6U)
20729 #define USB_OTG_GUSBCFG_PHYSEL_Msk (0x1UL << USB_OTG_GUSBCFG_PHYSEL_Pos) /*!< 0x00000040 */
20730 #define USB_OTG_GUSBCFG_PHYSEL USB_OTG_GUSBCFG_PHYSEL_Msk /*!< USB 2.0 high-speed ULPI PHY or USB 1.1 full-speed serial transceiver select */
20731 #define USB_OTG_GUSBCFG_SRPCAP_Pos (8U)
20732 #define USB_OTG_GUSBCFG_SRPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_SRPCAP_Pos) /*!< 0x00000100 */
20733 #define USB_OTG_GUSBCFG_SRPCAP USB_OTG_GUSBCFG_SRPCAP_Msk /*!< SRP-capable */
20734 #define USB_OTG_GUSBCFG_HNPCAP_Pos (9U)
20735 #define USB_OTG_GUSBCFG_HNPCAP_Msk (0x1UL << USB_OTG_GUSBCFG_HNPCAP_Pos) /*!< 0x00000200 */
20736 #define USB_OTG_GUSBCFG_HNPCAP USB_OTG_GUSBCFG_HNPCAP_Msk /*!< HNP-capable */
20737
20738 #define USB_OTG_GUSBCFG_TRDT_Pos (10U)
20739 #define USB_OTG_GUSBCFG_TRDT_Msk (0xFUL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00003C00 */
20740 #define USB_OTG_GUSBCFG_TRDT USB_OTG_GUSBCFG_TRDT_Msk /*!< USB turnaround time */
20741 #define USB_OTG_GUSBCFG_TRDT_0 (0x1UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000400 */
20742 #define USB_OTG_GUSBCFG_TRDT_1 (0x2UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00000800 */
20743 #define USB_OTG_GUSBCFG_TRDT_2 (0x4UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00001000 */
20744 #define USB_OTG_GUSBCFG_TRDT_3 (0x8UL << USB_OTG_GUSBCFG_TRDT_Pos) /*!< 0x00002000 */
20745 #define USB_OTG_GUSBCFG_PHYLPCS_Pos (15U)
20746 #define USB_OTG_GUSBCFG_PHYLPCS_Msk (0x1UL << USB_OTG_GUSBCFG_PHYLPCS_Pos) /*!< 0x00008000 */
20747 #define USB_OTG_GUSBCFG_PHYLPCS USB_OTG_GUSBCFG_PHYLPCS_Msk /*!< PHY Low-power clock select */
20748 #define USB_OTG_GUSBCFG_ULPIFSLS_Pos (17U)
20749 #define USB_OTG_GUSBCFG_ULPIFSLS_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIFSLS_Pos) /*!< 0x00020000 */
20750 #define USB_OTG_GUSBCFG_ULPIFSLS USB_OTG_GUSBCFG_ULPIFSLS_Msk /*!< ULPI FS/LS select */
20751 #define USB_OTG_GUSBCFG_ULPIAR_Pos (18U)
20752 #define USB_OTG_GUSBCFG_ULPIAR_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIAR_Pos) /*!< 0x00040000 */
20753 #define USB_OTG_GUSBCFG_ULPIAR USB_OTG_GUSBCFG_ULPIAR_Msk /*!< ULPI Auto-resume */
20754 #define USB_OTG_GUSBCFG_ULPICSM_Pos (19U)
20755 #define USB_OTG_GUSBCFG_ULPICSM_Msk (0x1UL << USB_OTG_GUSBCFG_ULPICSM_Pos) /*!< 0x00080000 */
20756 #define USB_OTG_GUSBCFG_ULPICSM USB_OTG_GUSBCFG_ULPICSM_Msk /*!< ULPI Clock SuspendM */
20757 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Pos (20U)
20758 #define USB_OTG_GUSBCFG_ULPIEVBUSD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSD_Pos) /*!< 0x00100000 */
20759 #define USB_OTG_GUSBCFG_ULPIEVBUSD USB_OTG_GUSBCFG_ULPIEVBUSD_Msk /*!< ULPI External VBUS Drive */
20760 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Pos (21U)
20761 #define USB_OTG_GUSBCFG_ULPIEVBUSI_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIEVBUSI_Pos) /*!< 0x00200000 */
20762 #define USB_OTG_GUSBCFG_ULPIEVBUSI USB_OTG_GUSBCFG_ULPIEVBUSI_Msk /*!< ULPI external VBUS indicator */
20763 #define USB_OTG_GUSBCFG_TSDPS_Pos (22U)
20764 #define USB_OTG_GUSBCFG_TSDPS_Msk (0x1UL << USB_OTG_GUSBCFG_TSDPS_Pos) /*!< 0x00400000 */
20765 #define USB_OTG_GUSBCFG_TSDPS USB_OTG_GUSBCFG_TSDPS_Msk /*!< TermSel DLine pulsing selection */
20766 #define USB_OTG_GUSBCFG_PCCI_Pos (23U)
20767 #define USB_OTG_GUSBCFG_PCCI_Msk (0x1UL << USB_OTG_GUSBCFG_PCCI_Pos) /*!< 0x00800000 */
20768 #define USB_OTG_GUSBCFG_PCCI USB_OTG_GUSBCFG_PCCI_Msk /*!< Indicator complement */
20769 #define USB_OTG_GUSBCFG_PTCI_Pos (24U)
20770 #define USB_OTG_GUSBCFG_PTCI_Msk (0x1UL << USB_OTG_GUSBCFG_PTCI_Pos) /*!< 0x01000000 */
20771 #define USB_OTG_GUSBCFG_PTCI USB_OTG_GUSBCFG_PTCI_Msk /*!< Indicator pass through */
20772 #define USB_OTG_GUSBCFG_ULPIIPD_Pos (25U)
20773 #define USB_OTG_GUSBCFG_ULPIIPD_Msk (0x1UL << USB_OTG_GUSBCFG_ULPIIPD_Pos) /*!< 0x02000000 */
20774 #define USB_OTG_GUSBCFG_ULPIIPD USB_OTG_GUSBCFG_ULPIIPD_Msk /*!< ULPI interface protect disable */
20775 #define USB_OTG_GUSBCFG_FHMOD_Pos (29U)
20776 #define USB_OTG_GUSBCFG_FHMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FHMOD_Pos) /*!< 0x20000000 */
20777 #define USB_OTG_GUSBCFG_FHMOD USB_OTG_GUSBCFG_FHMOD_Msk /*!< Forced host mode */
20778 #define USB_OTG_GUSBCFG_FDMOD_Pos (30U)
20779 #define USB_OTG_GUSBCFG_FDMOD_Msk (0x1UL << USB_OTG_GUSBCFG_FDMOD_Pos) /*!< 0x40000000 */
20780 #define USB_OTG_GUSBCFG_FDMOD USB_OTG_GUSBCFG_FDMOD_Msk /*!< Forced peripheral mode */
20781 #define USB_OTG_GUSBCFG_CTXPKT_Pos (31U)
20782 #define USB_OTG_GUSBCFG_CTXPKT_Msk (0x1UL << USB_OTG_GUSBCFG_CTXPKT_Pos) /*!< 0x80000000 */
20783 #define USB_OTG_GUSBCFG_CTXPKT USB_OTG_GUSBCFG_CTXPKT_Msk /*!< Corrupt Tx packet */
20784
20785 /******************** Bit definition forUSB_OTG_GRSTCTL register ********************/
20786 #define USB_OTG_GRSTCTL_CSRST_Pos (0U)
20787 #define USB_OTG_GRSTCTL_CSRST_Msk (0x1UL << USB_OTG_GRSTCTL_CSRST_Pos) /*!< 0x00000001 */
20788 #define USB_OTG_GRSTCTL_CSRST USB_OTG_GRSTCTL_CSRST_Msk /*!< Core soft reset */
20789 #define USB_OTG_GRSTCTL_HSRST_Pos (1U)
20790 #define USB_OTG_GRSTCTL_HSRST_Msk (0x1UL << USB_OTG_GRSTCTL_HSRST_Pos) /*!< 0x00000002 */
20791 #define USB_OTG_GRSTCTL_HSRST USB_OTG_GRSTCTL_HSRST_Msk /*!< HCLK soft reset */
20792 #define USB_OTG_GRSTCTL_FCRST_Pos (2U)
20793 #define USB_OTG_GRSTCTL_FCRST_Msk (0x1UL << USB_OTG_GRSTCTL_FCRST_Pos) /*!< 0x00000004 */
20794 #define USB_OTG_GRSTCTL_FCRST USB_OTG_GRSTCTL_FCRST_Msk /*!< Host frame counter reset */
20795 #define USB_OTG_GRSTCTL_RXFFLSH_Pos (4U)
20796 #define USB_OTG_GRSTCTL_RXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_RXFFLSH_Pos) /*!< 0x00000010 */
20797 #define USB_OTG_GRSTCTL_RXFFLSH USB_OTG_GRSTCTL_RXFFLSH_Msk /*!< RxFIFO flush */
20798 #define USB_OTG_GRSTCTL_TXFFLSH_Pos (5U)
20799 #define USB_OTG_GRSTCTL_TXFFLSH_Msk (0x1UL << USB_OTG_GRSTCTL_TXFFLSH_Pos) /*!< 0x00000020 */
20800 #define USB_OTG_GRSTCTL_TXFFLSH USB_OTG_GRSTCTL_TXFFLSH_Msk /*!< TxFIFO flush */
20801
20802 #define USB_OTG_GRSTCTL_TXFNUM_Pos (6U)
20803 #define USB_OTG_GRSTCTL_TXFNUM_Msk (0x1FUL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x000007C0 */
20804 #define USB_OTG_GRSTCTL_TXFNUM USB_OTG_GRSTCTL_TXFNUM_Msk /*!< TxFIFO number */
20805 #define USB_OTG_GRSTCTL_TXFNUM_0 (0x01UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000040 */
20806 #define USB_OTG_GRSTCTL_TXFNUM_1 (0x02UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000080 */
20807 #define USB_OTG_GRSTCTL_TXFNUM_2 (0x04UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000100 */
20808 #define USB_OTG_GRSTCTL_TXFNUM_3 (0x08UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000200 */
20809 #define USB_OTG_GRSTCTL_TXFNUM_4 (0x10UL << USB_OTG_GRSTCTL_TXFNUM_Pos) /*!< 0x00000400 */
20810 #define USB_OTG_GRSTCTL_DMAREQ_Pos (30U)
20811 #define USB_OTG_GRSTCTL_DMAREQ_Msk (0x1UL << USB_OTG_GRSTCTL_DMAREQ_Pos) /*!< 0x40000000 */
20812 #define USB_OTG_GRSTCTL_DMAREQ USB_OTG_GRSTCTL_DMAREQ_Msk /*!< DMA request signal */
20813 #define USB_OTG_GRSTCTL_AHBIDL_Pos (31U)
20814 #define USB_OTG_GRSTCTL_AHBIDL_Msk (0x1UL << USB_OTG_GRSTCTL_AHBIDL_Pos) /*!< 0x80000000 */
20815 #define USB_OTG_GRSTCTL_AHBIDL USB_OTG_GRSTCTL_AHBIDL_Msk /*!< AHB master idle */
20816
20817 /******************** Bit definition forUSB_OTG_DIEPMSK register ********************/
20818 #define USB_OTG_DIEPMSK_XFRCM_Pos (0U)
20819 #define USB_OTG_DIEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DIEPMSK_XFRCM_Pos) /*!< 0x00000001 */
20820 #define USB_OTG_DIEPMSK_XFRCM USB_OTG_DIEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
20821 #define USB_OTG_DIEPMSK_EPDM_Pos (1U)
20822 #define USB_OTG_DIEPMSK_EPDM_Msk (0x1UL << USB_OTG_DIEPMSK_EPDM_Pos) /*!< 0x00000002 */
20823 #define USB_OTG_DIEPMSK_EPDM USB_OTG_DIEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20824 #define USB_OTG_DIEPMSK_TOM_Pos (3U)
20825 #define USB_OTG_DIEPMSK_TOM_Msk (0x1UL << USB_OTG_DIEPMSK_TOM_Pos) /*!< 0x00000008 */
20826 #define USB_OTG_DIEPMSK_TOM USB_OTG_DIEPMSK_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
20827 #define USB_OTG_DIEPMSK_ITTXFEMSK_Pos (4U)
20828 #define USB_OTG_DIEPMSK_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPMSK_ITTXFEMSK_Pos) /*!< 0x00000010 */
20829 #define USB_OTG_DIEPMSK_ITTXFEMSK USB_OTG_DIEPMSK_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
20830 #define USB_OTG_DIEPMSK_INEPNMM_Pos (5U)
20831 #define USB_OTG_DIEPMSK_INEPNMM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNMM_Pos) /*!< 0x00000020 */
20832 #define USB_OTG_DIEPMSK_INEPNMM USB_OTG_DIEPMSK_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
20833 #define USB_OTG_DIEPMSK_INEPNEM_Pos (6U)
20834 #define USB_OTG_DIEPMSK_INEPNEM_Msk (0x1UL << USB_OTG_DIEPMSK_INEPNEM_Pos) /*!< 0x00000040 */
20835 #define USB_OTG_DIEPMSK_INEPNEM USB_OTG_DIEPMSK_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
20836 #define USB_OTG_DIEPMSK_TXFURM_Pos (8U)
20837 #define USB_OTG_DIEPMSK_TXFURM_Msk (0x1UL << USB_OTG_DIEPMSK_TXFURM_Pos) /*!< 0x00000100 */
20838 #define USB_OTG_DIEPMSK_TXFURM USB_OTG_DIEPMSK_TXFURM_Msk /*!< FIFO underrun mask */
20839 #define USB_OTG_DIEPMSK_BIM_Pos (9U)
20840 #define USB_OTG_DIEPMSK_BIM_Msk (0x1UL << USB_OTG_DIEPMSK_BIM_Pos) /*!< 0x00000200 */
20841 #define USB_OTG_DIEPMSK_BIM USB_OTG_DIEPMSK_BIM_Msk /*!< BNA interrupt mask */
20842
20843 /******************** Bit definition forUSB_OTG_HPTXSTS register ********************/
20844 #define USB_OTG_HPTXSTS_PTXFSAVL_Pos (0U)
20845 #define USB_OTG_HPTXSTS_PTXFSAVL_Msk (0xFFFFUL << USB_OTG_HPTXSTS_PTXFSAVL_Pos) /*!< 0x0000FFFF */
20846 #define USB_OTG_HPTXSTS_PTXFSAVL USB_OTG_HPTXSTS_PTXFSAVL_Msk /*!< Periodic transmit data FIFO space available */
20847
20848 #define USB_OTG_HPTXSTS_PTXQSAV_Pos (16U)
20849 #define USB_OTG_HPTXSTS_PTXQSAV_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00FF0000 */
20850 #define USB_OTG_HPTXSTS_PTXQSAV USB_OTG_HPTXSTS_PTXQSAV_Msk /*!< Periodic transmit request queue space available */
20851 #define USB_OTG_HPTXSTS_PTXQSAV_0 (0x01UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00010000 */
20852 #define USB_OTG_HPTXSTS_PTXQSAV_1 (0x02UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00020000 */
20853 #define USB_OTG_HPTXSTS_PTXQSAV_2 (0x04UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00040000 */
20854 #define USB_OTG_HPTXSTS_PTXQSAV_3 (0x08UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00080000 */
20855 #define USB_OTG_HPTXSTS_PTXQSAV_4 (0x10UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00100000 */
20856 #define USB_OTG_HPTXSTS_PTXQSAV_5 (0x20UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00200000 */
20857 #define USB_OTG_HPTXSTS_PTXQSAV_6 (0x40UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00400000 */
20858 #define USB_OTG_HPTXSTS_PTXQSAV_7 (0x80UL << USB_OTG_HPTXSTS_PTXQSAV_Pos) /*!< 0x00800000 */
20859
20860 #define USB_OTG_HPTXSTS_PTXQTOP_Pos (24U)
20861 #define USB_OTG_HPTXSTS_PTXQTOP_Msk (0xFFUL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0xFF000000 */
20862 #define USB_OTG_HPTXSTS_PTXQTOP USB_OTG_HPTXSTS_PTXQTOP_Msk /*!< Top of the periodic transmit request queue */
20863 #define USB_OTG_HPTXSTS_PTXQTOP_0 (0x01UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x01000000 */
20864 #define USB_OTG_HPTXSTS_PTXQTOP_1 (0x02UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x02000000 */
20865 #define USB_OTG_HPTXSTS_PTXQTOP_2 (0x04UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x04000000 */
20866 #define USB_OTG_HPTXSTS_PTXQTOP_3 (0x08UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x08000000 */
20867 #define USB_OTG_HPTXSTS_PTXQTOP_4 (0x10UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x10000000 */
20868 #define USB_OTG_HPTXSTS_PTXQTOP_5 (0x20UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x20000000 */
20869 #define USB_OTG_HPTXSTS_PTXQTOP_6 (0x40UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x40000000 */
20870 #define USB_OTG_HPTXSTS_PTXQTOP_7 (0x80UL << USB_OTG_HPTXSTS_PTXQTOP_Pos) /*!< 0x80000000 */
20871
20872 /******************** Bit definition forUSB_OTG_HAINT register ********************/
20873 #define USB_OTG_HAINT_HAINT_Pos (0U)
20874 #define USB_OTG_HAINT_HAINT_Msk (0xFFFFUL << USB_OTG_HAINT_HAINT_Pos) /*!< 0x0000FFFF */
20875 #define USB_OTG_HAINT_HAINT USB_OTG_HAINT_HAINT_Msk /*!< Channel interrupts */
20876
20877 /******************** Bit definition forUSB_OTG_DOEPMSK register ********************/
20878 #define USB_OTG_DOEPMSK_XFRCM_Pos (0U)
20879 #define USB_OTG_DOEPMSK_XFRCM_Msk (0x1UL << USB_OTG_DOEPMSK_XFRCM_Pos) /*!< 0x00000001 */
20880 #define USB_OTG_DOEPMSK_XFRCM USB_OTG_DOEPMSK_XFRCM_Msk /*!< Transfer completed interrupt mask */
20881 #define USB_OTG_DOEPMSK_EPDM_Pos (1U)
20882 #define USB_OTG_DOEPMSK_EPDM_Msk (0x1UL << USB_OTG_DOEPMSK_EPDM_Pos) /*!< 0x00000002 */
20883 #define USB_OTG_DOEPMSK_EPDM USB_OTG_DOEPMSK_EPDM_Msk /*!< Endpoint disabled interrupt mask */
20884 #define USB_OTG_DOEPMSK_AHBERRM_Pos (2U)
20885 #define USB_OTG_DOEPMSK_AHBERRM_Msk (0x1UL << USB_OTG_DOEPMSK_AHBERRM_Pos) /*!< 0x00000004 */
20886 #define USB_OTG_DOEPMSK_AHBERRM USB_OTG_DOEPMSK_AHBERRM_Msk /*!< OUT transaction AHB Error interrupt mask */
20887 #define USB_OTG_DOEPMSK_STUPM_Pos (3U)
20888 #define USB_OTG_DOEPMSK_STUPM_Msk (0x1UL << USB_OTG_DOEPMSK_STUPM_Pos) /*!< 0x00000008 */
20889 #define USB_OTG_DOEPMSK_STUPM USB_OTG_DOEPMSK_STUPM_Msk /*!< SETUP phase done mask */
20890 #define USB_OTG_DOEPMSK_OTEPDM_Pos (4U)
20891 #define USB_OTG_DOEPMSK_OTEPDM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPDM_Pos) /*!< 0x00000010 */
20892 #define USB_OTG_DOEPMSK_OTEPDM USB_OTG_DOEPMSK_OTEPDM_Msk /*!< OUT token received when endpoint disabled mask */
20893 #define USB_OTG_DOEPMSK_OTEPSPRM_Pos (5U)
20894 #define USB_OTG_DOEPMSK_OTEPSPRM_Msk (0x1UL << USB_OTG_DOEPMSK_OTEPSPRM_Pos) /*!< 0x00000020 */
20895 #define USB_OTG_DOEPMSK_OTEPSPRM USB_OTG_DOEPMSK_OTEPSPRM_Msk /*!< Status Phase Received mask */
20896 #define USB_OTG_DOEPMSK_B2BSTUP_Pos (6U)
20897 #define USB_OTG_DOEPMSK_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPMSK_B2BSTUP_Pos) /*!< 0x00000040 */
20898 #define USB_OTG_DOEPMSK_B2BSTUP USB_OTG_DOEPMSK_B2BSTUP_Msk /*!< Back-to-back SETUP packets received mask */
20899 #define USB_OTG_DOEPMSK_OPEM_Pos (8U)
20900 #define USB_OTG_DOEPMSK_OPEM_Msk (0x1UL << USB_OTG_DOEPMSK_OPEM_Pos) /*!< 0x00000100 */
20901 #define USB_OTG_DOEPMSK_OPEM USB_OTG_DOEPMSK_OPEM_Msk /*!< OUT packet error mask */
20902 #define USB_OTG_DOEPMSK_BOIM_Pos (9U)
20903 #define USB_OTG_DOEPMSK_BOIM_Msk (0x1UL << USB_OTG_DOEPMSK_BOIM_Pos) /*!< 0x00000200 */
20904 #define USB_OTG_DOEPMSK_BOIM USB_OTG_DOEPMSK_BOIM_Msk /*!< BNA interrupt mask */
20905 #define USB_OTG_DOEPMSK_BERRM_Pos (12U)
20906 #define USB_OTG_DOEPMSK_BERRM_Msk (0x1UL << USB_OTG_DOEPMSK_BERRM_Pos) /*!< 0x00001000 */
20907 #define USB_OTG_DOEPMSK_BERRM USB_OTG_DOEPMSK_BERRM_Msk /*!< Babble error interrupt mask */
20908 #define USB_OTG_DOEPMSK_NAKM_Pos (13U)
20909 #define USB_OTG_DOEPMSK_NAKM_Msk (0x1UL << USB_OTG_DOEPMSK_NAKM_Pos) /*!< 0x00002000 */
20910 #define USB_OTG_DOEPMSK_NAKM USB_OTG_DOEPMSK_NAKM_Msk /*!< OUT Packet NAK interrupt mask */
20911 #define USB_OTG_DOEPMSK_NYETM_Pos (14U)
20912 #define USB_OTG_DOEPMSK_NYETM_Msk (0x1UL << USB_OTG_DOEPMSK_NYETM_Pos) /*!< 0x00004000 */
20913 #define USB_OTG_DOEPMSK_NYETM USB_OTG_DOEPMSK_NYETM_Msk /*!< NYET interrupt mask */
20914
20915 /******************** Bit definition forUSB_OTG_GINTSTS register ********************/
20916 #define USB_OTG_GINTSTS_CMOD_Pos (0U)
20917 #define USB_OTG_GINTSTS_CMOD_Msk (0x1UL << USB_OTG_GINTSTS_CMOD_Pos) /*!< 0x00000001 */
20918 #define USB_OTG_GINTSTS_CMOD USB_OTG_GINTSTS_CMOD_Msk /*!< Current mode of operation */
20919 #define USB_OTG_GINTSTS_MMIS_Pos (1U)
20920 #define USB_OTG_GINTSTS_MMIS_Msk (0x1UL << USB_OTG_GINTSTS_MMIS_Pos) /*!< 0x00000002 */
20921 #define USB_OTG_GINTSTS_MMIS USB_OTG_GINTSTS_MMIS_Msk /*!< Mode mismatch interrupt */
20922 #define USB_OTG_GINTSTS_OTGINT_Pos (2U)
20923 #define USB_OTG_GINTSTS_OTGINT_Msk (0x1UL << USB_OTG_GINTSTS_OTGINT_Pos) /*!< 0x00000004 */
20924 #define USB_OTG_GINTSTS_OTGINT USB_OTG_GINTSTS_OTGINT_Msk /*!< OTG interrupt */
20925 #define USB_OTG_GINTSTS_SOF_Pos (3U)
20926 #define USB_OTG_GINTSTS_SOF_Msk (0x1UL << USB_OTG_GINTSTS_SOF_Pos) /*!< 0x00000008 */
20927 #define USB_OTG_GINTSTS_SOF USB_OTG_GINTSTS_SOF_Msk /*!< Start of frame */
20928 #define USB_OTG_GINTSTS_RXFLVL_Pos (4U)
20929 #define USB_OTG_GINTSTS_RXFLVL_Msk (0x1UL << USB_OTG_GINTSTS_RXFLVL_Pos) /*!< 0x00000010 */
20930 #define USB_OTG_GINTSTS_RXFLVL USB_OTG_GINTSTS_RXFLVL_Msk /*!< RxFIFO nonempty */
20931 #define USB_OTG_GINTSTS_NPTXFE_Pos (5U)
20932 #define USB_OTG_GINTSTS_NPTXFE_Msk (0x1UL << USB_OTG_GINTSTS_NPTXFE_Pos) /*!< 0x00000020 */
20933 #define USB_OTG_GINTSTS_NPTXFE USB_OTG_GINTSTS_NPTXFE_Msk /*!< Nonperiodic TxFIFO empty */
20934 #define USB_OTG_GINTSTS_GINAKEFF_Pos (6U)
20935 #define USB_OTG_GINTSTS_GINAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_GINAKEFF_Pos) /*!< 0x00000040 */
20936 #define USB_OTG_GINTSTS_GINAKEFF USB_OTG_GINTSTS_GINAKEFF_Msk /*!< Global IN nonperiodic NAK effective */
20937 #define USB_OTG_GINTSTS_BOUTNAKEFF_Pos (7U)
20938 #define USB_OTG_GINTSTS_BOUTNAKEFF_Msk (0x1UL << USB_OTG_GINTSTS_BOUTNAKEFF_Pos) /*!< 0x00000080 */
20939 #define USB_OTG_GINTSTS_BOUTNAKEFF USB_OTG_GINTSTS_BOUTNAKEFF_Msk /*!< Global OUT NAK effective */
20940 #define USB_OTG_GINTSTS_ESUSP_Pos (10U)
20941 #define USB_OTG_GINTSTS_ESUSP_Msk (0x1UL << USB_OTG_GINTSTS_ESUSP_Pos) /*!< 0x00000400 */
20942 #define USB_OTG_GINTSTS_ESUSP USB_OTG_GINTSTS_ESUSP_Msk /*!< Early suspend */
20943 #define USB_OTG_GINTSTS_USBSUSP_Pos (11U)
20944 #define USB_OTG_GINTSTS_USBSUSP_Msk (0x1UL << USB_OTG_GINTSTS_USBSUSP_Pos) /*!< 0x00000800 */
20945 #define USB_OTG_GINTSTS_USBSUSP USB_OTG_GINTSTS_USBSUSP_Msk /*!< USB suspend */
20946 #define USB_OTG_GINTSTS_USBRST_Pos (12U)
20947 #define USB_OTG_GINTSTS_USBRST_Msk (0x1UL << USB_OTG_GINTSTS_USBRST_Pos) /*!< 0x00001000 */
20948 #define USB_OTG_GINTSTS_USBRST USB_OTG_GINTSTS_USBRST_Msk /*!< USB reset */
20949 #define USB_OTG_GINTSTS_ENUMDNE_Pos (13U)
20950 #define USB_OTG_GINTSTS_ENUMDNE_Msk (0x1UL << USB_OTG_GINTSTS_ENUMDNE_Pos) /*!< 0x00002000 */
20951 #define USB_OTG_GINTSTS_ENUMDNE USB_OTG_GINTSTS_ENUMDNE_Msk /*!< Enumeration done */
20952 #define USB_OTG_GINTSTS_ISOODRP_Pos (14U)
20953 #define USB_OTG_GINTSTS_ISOODRP_Msk (0x1UL << USB_OTG_GINTSTS_ISOODRP_Pos) /*!< 0x00004000 */
20954 #define USB_OTG_GINTSTS_ISOODRP USB_OTG_GINTSTS_ISOODRP_Msk /*!< Isochronous OUT packet dropped interrupt */
20955 #define USB_OTG_GINTSTS_EOPF_Pos (15U)
20956 #define USB_OTG_GINTSTS_EOPF_Msk (0x1UL << USB_OTG_GINTSTS_EOPF_Pos) /*!< 0x00008000 */
20957 #define USB_OTG_GINTSTS_EOPF USB_OTG_GINTSTS_EOPF_Msk /*!< End of periodic frame interrupt */
20958 #define USB_OTG_GINTSTS_IEPINT_Pos (18U)
20959 #define USB_OTG_GINTSTS_IEPINT_Msk (0x1UL << USB_OTG_GINTSTS_IEPINT_Pos) /*!< 0x00040000 */
20960 #define USB_OTG_GINTSTS_IEPINT USB_OTG_GINTSTS_IEPINT_Msk /*!< IN endpoint interrupt */
20961 #define USB_OTG_GINTSTS_OEPINT_Pos (19U)
20962 #define USB_OTG_GINTSTS_OEPINT_Msk (0x1UL << USB_OTG_GINTSTS_OEPINT_Pos) /*!< 0x00080000 */
20963 #define USB_OTG_GINTSTS_OEPINT USB_OTG_GINTSTS_OEPINT_Msk /*!< OUT endpoint interrupt */
20964 #define USB_OTG_GINTSTS_IISOIXFR_Pos (20U)
20965 #define USB_OTG_GINTSTS_IISOIXFR_Msk (0x1UL << USB_OTG_GINTSTS_IISOIXFR_Pos) /*!< 0x00100000 */
20966 #define USB_OTG_GINTSTS_IISOIXFR USB_OTG_GINTSTS_IISOIXFR_Msk /*!< Incomplete isochronous IN transfer */
20967 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos (21U)
20968 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk (0x1UL << USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Pos) /*!< 0x00200000 */
20969 #define USB_OTG_GINTSTS_PXFR_INCOMPISOOUT USB_OTG_GINTSTS_PXFR_INCOMPISOOUT_Msk /*!< Incomplete periodic transfer */
20970 #define USB_OTG_GINTSTS_DATAFSUSP_Pos (22U)
20971 #define USB_OTG_GINTSTS_DATAFSUSP_Msk (0x1UL << USB_OTG_GINTSTS_DATAFSUSP_Pos) /*!< 0x00400000 */
20972 #define USB_OTG_GINTSTS_DATAFSUSP USB_OTG_GINTSTS_DATAFSUSP_Msk /*!< Data fetch suspended */
20973 #define USB_OTG_GINTSTS_RSTDET_Pos (23U)
20974 #define USB_OTG_GINTSTS_RSTDET_Msk (0x1UL << USB_OTG_GINTSTS_RSTDET_Pos) /*!< 0x00800000 */
20975 #define USB_OTG_GINTSTS_RSTDET USB_OTG_GINTSTS_RSTDET_Msk /*!< Reset detected interrupt */
20976 #define USB_OTG_GINTSTS_HPRTINT_Pos (24U)
20977 #define USB_OTG_GINTSTS_HPRTINT_Msk (0x1UL << USB_OTG_GINTSTS_HPRTINT_Pos) /*!< 0x01000000 */
20978 #define USB_OTG_GINTSTS_HPRTINT USB_OTG_GINTSTS_HPRTINT_Msk /*!< Host port interrupt */
20979 #define USB_OTG_GINTSTS_HCINT_Pos (25U)
20980 #define USB_OTG_GINTSTS_HCINT_Msk (0x1UL << USB_OTG_GINTSTS_HCINT_Pos) /*!< 0x02000000 */
20981 #define USB_OTG_GINTSTS_HCINT USB_OTG_GINTSTS_HCINT_Msk /*!< Host channels interrupt */
20982 #define USB_OTG_GINTSTS_PTXFE_Pos (26U)
20983 #define USB_OTG_GINTSTS_PTXFE_Msk (0x1UL << USB_OTG_GINTSTS_PTXFE_Pos) /*!< 0x04000000 */
20984 #define USB_OTG_GINTSTS_PTXFE USB_OTG_GINTSTS_PTXFE_Msk /*!< Periodic TxFIFO empty */
20985 #define USB_OTG_GINTSTS_LPMINT_Pos (27U)
20986 #define USB_OTG_GINTSTS_LPMINT_Msk (0x1UL << USB_OTG_GINTSTS_LPMINT_Pos) /*!< 0x08000000 */
20987 #define USB_OTG_GINTSTS_LPMINT USB_OTG_GINTSTS_LPMINT_Msk /*!< LPM interrupt */
20988 #define USB_OTG_GINTSTS_CIDSCHG_Pos (28U)
20989 #define USB_OTG_GINTSTS_CIDSCHG_Msk (0x1UL << USB_OTG_GINTSTS_CIDSCHG_Pos) /*!< 0x10000000 */
20990 #define USB_OTG_GINTSTS_CIDSCHG USB_OTG_GINTSTS_CIDSCHG_Msk /*!< Connector ID status change */
20991 #define USB_OTG_GINTSTS_DISCINT_Pos (29U)
20992 #define USB_OTG_GINTSTS_DISCINT_Msk (0x1UL << USB_OTG_GINTSTS_DISCINT_Pos) /*!< 0x20000000 */
20993 #define USB_OTG_GINTSTS_DISCINT USB_OTG_GINTSTS_DISCINT_Msk /*!< Disconnect detected interrupt */
20994 #define USB_OTG_GINTSTS_SRQINT_Pos (30U)
20995 #define USB_OTG_GINTSTS_SRQINT_Msk (0x1UL << USB_OTG_GINTSTS_SRQINT_Pos) /*!< 0x40000000 */
20996 #define USB_OTG_GINTSTS_SRQINT USB_OTG_GINTSTS_SRQINT_Msk /*!< Session request/new session detected interrupt */
20997 #define USB_OTG_GINTSTS_WKUINT_Pos (31U)
20998 #define USB_OTG_GINTSTS_WKUINT_Msk (0x1UL << USB_OTG_GINTSTS_WKUINT_Pos) /*!< 0x80000000 */
20999 #define USB_OTG_GINTSTS_WKUINT USB_OTG_GINTSTS_WKUINT_Msk /*!< Resume/remote wakeup detected interrupt */
21000
21001 /******************** Bit definition forUSB_OTG_GINTMSK register ********************/
21002 #define USB_OTG_GINTMSK_MMISM_Pos (1U)
21003 #define USB_OTG_GINTMSK_MMISM_Msk (0x1UL << USB_OTG_GINTMSK_MMISM_Pos) /*!< 0x00000002 */
21004 #define USB_OTG_GINTMSK_MMISM USB_OTG_GINTMSK_MMISM_Msk /*!< Mode mismatch interrupt mask */
21005 #define USB_OTG_GINTMSK_OTGINT_Pos (2U)
21006 #define USB_OTG_GINTMSK_OTGINT_Msk (0x1UL << USB_OTG_GINTMSK_OTGINT_Pos) /*!< 0x00000004 */
21007 #define USB_OTG_GINTMSK_OTGINT USB_OTG_GINTMSK_OTGINT_Msk /*!< OTG interrupt mask */
21008 #define USB_OTG_GINTMSK_SOFM_Pos (3U)
21009 #define USB_OTG_GINTMSK_SOFM_Msk (0x1UL << USB_OTG_GINTMSK_SOFM_Pos) /*!< 0x00000008 */
21010 #define USB_OTG_GINTMSK_SOFM USB_OTG_GINTMSK_SOFM_Msk /*!< Start of frame mask */
21011 #define USB_OTG_GINTMSK_RXFLVLM_Pos (4U)
21012 #define USB_OTG_GINTMSK_RXFLVLM_Msk (0x1UL << USB_OTG_GINTMSK_RXFLVLM_Pos) /*!< 0x00000010 */
21013 #define USB_OTG_GINTMSK_RXFLVLM USB_OTG_GINTMSK_RXFLVLM_Msk /*!< Receive FIFO nonempty mask */
21014 #define USB_OTG_GINTMSK_NPTXFEM_Pos (5U)
21015 #define USB_OTG_GINTMSK_NPTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_NPTXFEM_Pos) /*!< 0x00000020 */
21016 #define USB_OTG_GINTMSK_NPTXFEM USB_OTG_GINTMSK_NPTXFEM_Msk /*!< Nonperiodic TxFIFO empty mask */
21017 #define USB_OTG_GINTMSK_GINAKEFFM_Pos (6U)
21018 #define USB_OTG_GINTMSK_GINAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GINAKEFFM_Pos) /*!< 0x00000040 */
21019 #define USB_OTG_GINTMSK_GINAKEFFM USB_OTG_GINTMSK_GINAKEFFM_Msk /*!< Global nonperiodic IN NAK effective mask */
21020 #define USB_OTG_GINTMSK_GONAKEFFM_Pos (7U)
21021 #define USB_OTG_GINTMSK_GONAKEFFM_Msk (0x1UL << USB_OTG_GINTMSK_GONAKEFFM_Pos) /*!< 0x00000080 */
21022 #define USB_OTG_GINTMSK_GONAKEFFM USB_OTG_GINTMSK_GONAKEFFM_Msk /*!< Global OUT NAK effective mask */
21023 #define USB_OTG_GINTMSK_ESUSPM_Pos (10U)
21024 #define USB_OTG_GINTMSK_ESUSPM_Msk (0x1UL << USB_OTG_GINTMSK_ESUSPM_Pos) /*!< 0x00000400 */
21025 #define USB_OTG_GINTMSK_ESUSPM USB_OTG_GINTMSK_ESUSPM_Msk /*!< Early suspend mask */
21026 #define USB_OTG_GINTMSK_USBSUSPM_Pos (11U)
21027 #define USB_OTG_GINTMSK_USBSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_USBSUSPM_Pos) /*!< 0x00000800 */
21028 #define USB_OTG_GINTMSK_USBSUSPM USB_OTG_GINTMSK_USBSUSPM_Msk /*!< USB suspend mask */
21029 #define USB_OTG_GINTMSK_USBRST_Pos (12U)
21030 #define USB_OTG_GINTMSK_USBRST_Msk (0x1UL << USB_OTG_GINTMSK_USBRST_Pos) /*!< 0x00001000 */
21031 #define USB_OTG_GINTMSK_USBRST USB_OTG_GINTMSK_USBRST_Msk /*!< USB reset mask */
21032 #define USB_OTG_GINTMSK_ENUMDNEM_Pos (13U)
21033 #define USB_OTG_GINTMSK_ENUMDNEM_Msk (0x1UL << USB_OTG_GINTMSK_ENUMDNEM_Pos) /*!< 0x00002000 */
21034 #define USB_OTG_GINTMSK_ENUMDNEM USB_OTG_GINTMSK_ENUMDNEM_Msk /*!< Enumeration done mask */
21035 #define USB_OTG_GINTMSK_ISOODRPM_Pos (14U)
21036 #define USB_OTG_GINTMSK_ISOODRPM_Msk (0x1UL << USB_OTG_GINTMSK_ISOODRPM_Pos) /*!< 0x00004000 */
21037 #define USB_OTG_GINTMSK_ISOODRPM USB_OTG_GINTMSK_ISOODRPM_Msk /*!< Isochronous OUT packet dropped interrupt mask */
21038 #define USB_OTG_GINTMSK_EOPFM_Pos (15U)
21039 #define USB_OTG_GINTMSK_EOPFM_Msk (0x1UL << USB_OTG_GINTMSK_EOPFM_Pos) /*!< 0x00008000 */
21040 #define USB_OTG_GINTMSK_EOPFM USB_OTG_GINTMSK_EOPFM_Msk /*!< End of periodic frame interrupt mask */
21041 #define USB_OTG_GINTMSK_EPMISM_Pos (17U)
21042 #define USB_OTG_GINTMSK_EPMISM_Msk (0x1UL << USB_OTG_GINTMSK_EPMISM_Pos) /*!< 0x00020000 */
21043 #define USB_OTG_GINTMSK_EPMISM USB_OTG_GINTMSK_EPMISM_Msk /*!< Endpoint mismatch interrupt mask */
21044 #define USB_OTG_GINTMSK_IEPINT_Pos (18U)
21045 #define USB_OTG_GINTMSK_IEPINT_Msk (0x1UL << USB_OTG_GINTMSK_IEPINT_Pos) /*!< 0x00040000 */
21046 #define USB_OTG_GINTMSK_IEPINT USB_OTG_GINTMSK_IEPINT_Msk /*!< IN endpoints interrupt mask */
21047 #define USB_OTG_GINTMSK_OEPINT_Pos (19U)
21048 #define USB_OTG_GINTMSK_OEPINT_Msk (0x1UL << USB_OTG_GINTMSK_OEPINT_Pos) /*!< 0x00080000 */
21049 #define USB_OTG_GINTMSK_OEPINT USB_OTG_GINTMSK_OEPINT_Msk /*!< OUT endpoints interrupt mask */
21050 #define USB_OTG_GINTMSK_IISOIXFRM_Pos (20U)
21051 #define USB_OTG_GINTMSK_IISOIXFRM_Msk (0x1UL << USB_OTG_GINTMSK_IISOIXFRM_Pos) /*!< 0x00100000 */
21052 #define USB_OTG_GINTMSK_IISOIXFRM USB_OTG_GINTMSK_IISOIXFRM_Msk /*!< Incomplete isochronous IN transfer mask */
21053 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos (21U)
21054 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk (0x1UL << USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Pos) /*!< 0x00200000 */
21055 #define USB_OTG_GINTMSK_PXFRM_IISOOXFRM USB_OTG_GINTMSK_PXFRM_IISOOXFRM_Msk /*!< Incomplete periodic transfer mask */
21056 #define USB_OTG_GINTMSK_FSUSPM_Pos (22U)
21057 #define USB_OTG_GINTMSK_FSUSPM_Msk (0x1UL << USB_OTG_GINTMSK_FSUSPM_Pos) /*!< 0x00400000 */
21058 #define USB_OTG_GINTMSK_FSUSPM USB_OTG_GINTMSK_FSUSPM_Msk /*!< Data fetch suspended mask */
21059 #define USB_OTG_GINTMSK_RSTDEM_Pos (23U)
21060 #define USB_OTG_GINTMSK_RSTDEM_Msk (0x1UL << USB_OTG_GINTMSK_RSTDEM_Pos) /*!< 0x00800000 */
21061 #define USB_OTG_GINTMSK_RSTDEM USB_OTG_GINTMSK_RSTDEM_Msk /*!< Reset detected interrupt mask */
21062 #define USB_OTG_GINTMSK_PRTIM_Pos (24U)
21063 #define USB_OTG_GINTMSK_PRTIM_Msk (0x1UL << USB_OTG_GINTMSK_PRTIM_Pos) /*!< 0x01000000 */
21064 #define USB_OTG_GINTMSK_PRTIM USB_OTG_GINTMSK_PRTIM_Msk /*!< Host port interrupt mask */
21065 #define USB_OTG_GINTMSK_HCIM_Pos (25U)
21066 #define USB_OTG_GINTMSK_HCIM_Msk (0x1UL << USB_OTG_GINTMSK_HCIM_Pos) /*!< 0x02000000 */
21067 #define USB_OTG_GINTMSK_HCIM USB_OTG_GINTMSK_HCIM_Msk /*!< Host channels interrupt mask */
21068 #define USB_OTG_GINTMSK_PTXFEM_Pos (26U)
21069 #define USB_OTG_GINTMSK_PTXFEM_Msk (0x1UL << USB_OTG_GINTMSK_PTXFEM_Pos) /*!< 0x04000000 */
21070 #define USB_OTG_GINTMSK_PTXFEM USB_OTG_GINTMSK_PTXFEM_Msk /*!< Periodic TxFIFO empty mask */
21071 #define USB_OTG_GINTMSK_LPMINTM_Pos (27U)
21072 #define USB_OTG_GINTMSK_LPMINTM_Msk (0x1UL << USB_OTG_GINTMSK_LPMINTM_Pos) /*!< 0x08000000 */
21073 #define USB_OTG_GINTMSK_LPMINTM USB_OTG_GINTMSK_LPMINTM_Msk /*!< LPM interrupt Mask */
21074 #define USB_OTG_GINTMSK_CIDSCHGM_Pos (28U)
21075 #define USB_OTG_GINTMSK_CIDSCHGM_Msk (0x1UL << USB_OTG_GINTMSK_CIDSCHGM_Pos) /*!< 0x10000000 */
21076 #define USB_OTG_GINTMSK_CIDSCHGM USB_OTG_GINTMSK_CIDSCHGM_Msk /*!< Connector ID status change mask */
21077 #define USB_OTG_GINTMSK_DISCINT_Pos (29U)
21078 #define USB_OTG_GINTMSK_DISCINT_Msk (0x1UL << USB_OTG_GINTMSK_DISCINT_Pos) /*!< 0x20000000 */
21079 #define USB_OTG_GINTMSK_DISCINT USB_OTG_GINTMSK_DISCINT_Msk /*!< Disconnect detected interrupt mask */
21080 #define USB_OTG_GINTMSK_SRQIM_Pos (30U)
21081 #define USB_OTG_GINTMSK_SRQIM_Msk (0x1UL << USB_OTG_GINTMSK_SRQIM_Pos) /*!< 0x40000000 */
21082 #define USB_OTG_GINTMSK_SRQIM USB_OTG_GINTMSK_SRQIM_Msk /*!< Session request/new session detected interrupt mask */
21083 #define USB_OTG_GINTMSK_WUIM_Pos (31U)
21084 #define USB_OTG_GINTMSK_WUIM_Msk (0x1UL << USB_OTG_GINTMSK_WUIM_Pos) /*!< 0x80000000 */
21085 #define USB_OTG_GINTMSK_WUIM USB_OTG_GINTMSK_WUIM_Msk /*!< Resume/remote wakeup detected interrupt mask */
21086
21087 /******************** Bit definition forUSB_OTG_DAINT register ********************/
21088 #define USB_OTG_DAINT_IEPINT_Pos (0U)
21089 #define USB_OTG_DAINT_IEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_IEPINT_Pos) /*!< 0x0000FFFF */
21090 #define USB_OTG_DAINT_IEPINT USB_OTG_DAINT_IEPINT_Msk /*!< IN endpoint interrupt bits */
21091 #define USB_OTG_DAINT_OEPINT_Pos (16U)
21092 #define USB_OTG_DAINT_OEPINT_Msk (0xFFFFUL << USB_OTG_DAINT_OEPINT_Pos) /*!< 0xFFFF0000 */
21093 #define USB_OTG_DAINT_OEPINT USB_OTG_DAINT_OEPINT_Msk /*!< OUT endpoint interrupt bits */
21094
21095 /******************** Bit definition forUSB_OTG_HAINTMSK register ********************/
21096 #define USB_OTG_HAINTMSK_HAINTM_Pos (0U)
21097 #define USB_OTG_HAINTMSK_HAINTM_Msk (0xFFFFUL << USB_OTG_HAINTMSK_HAINTM_Pos) /*!< 0x0000FFFF */
21098 #define USB_OTG_HAINTMSK_HAINTM USB_OTG_HAINTMSK_HAINTM_Msk /*!< Channel interrupt mask */
21099
21100 /******************** Bit definition for USB_OTG_GRXSTSP register ********************/
21101 #define USB_OTG_GRXSTSP_EPNUM_Pos (0U)
21102 #define USB_OTG_GRXSTSP_EPNUM_Msk (0xFUL << USB_OTG_GRXSTSP_EPNUM_Pos) /*!< 0x0000000F */
21103 #define USB_OTG_GRXSTSP_EPNUM USB_OTG_GRXSTSP_EPNUM_Msk /*!< IN EP interrupt mask bits */
21104 #define USB_OTG_GRXSTSP_BCNT_Pos (4U)
21105 #define USB_OTG_GRXSTSP_BCNT_Msk (0x7FFUL << USB_OTG_GRXSTSP_BCNT_Pos) /*!< 0x00007FF0 */
21106 #define USB_OTG_GRXSTSP_BCNT USB_OTG_GRXSTSP_BCNT_Msk /*!< OUT EP interrupt mask bits */
21107 #define USB_OTG_GRXSTSP_DPID_Pos (15U)
21108 #define USB_OTG_GRXSTSP_DPID_Msk (0x3UL << USB_OTG_GRXSTSP_DPID_Pos) /*!< 0x00018000 */
21109 #define USB_OTG_GRXSTSP_DPID USB_OTG_GRXSTSP_DPID_Msk /*!< OUT EP interrupt mask bits */
21110 #define USB_OTG_GRXSTSP_PKTSTS_Pos (17U)
21111 #define USB_OTG_GRXSTSP_PKTSTS_Msk (0xFUL << USB_OTG_GRXSTSP_PKTSTS_Pos) /*!< 0x001E0000 */
21112 #define USB_OTG_GRXSTSP_PKTSTS USB_OTG_GRXSTSP_PKTSTS_Msk /*!< OUT EP interrupt mask bits */
21113
21114 /******************** Bit definition forUSB_OTG_DAINTMSK register ********************/
21115 #define USB_OTG_DAINTMSK_IEPM_Pos (0U)
21116 #define USB_OTG_DAINTMSK_IEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_IEPM_Pos) /*!< 0x0000FFFF */
21117 #define USB_OTG_DAINTMSK_IEPM USB_OTG_DAINTMSK_IEPM_Msk /*!< IN EP interrupt mask bits */
21118 #define USB_OTG_DAINTMSK_OEPM_Pos (16U)
21119 #define USB_OTG_DAINTMSK_OEPM_Msk (0xFFFFUL << USB_OTG_DAINTMSK_OEPM_Pos) /*!< 0xFFFF0000 */
21120 #define USB_OTG_DAINTMSK_OEPM USB_OTG_DAINTMSK_OEPM_Msk /*!< OUT EP interrupt mask bits */
21121
21122 /******************** Bit definition for OTG register ********************/
21123
21124 #define USB_OTG_CHNUM_Pos (0U)
21125 #define USB_OTG_CHNUM_Msk (0xFUL << USB_OTG_CHNUM_Pos) /*!< 0x0000000F */
21126 #define USB_OTG_CHNUM USB_OTG_CHNUM_Msk /*!< Channel number */
21127 #define USB_OTG_CHNUM_0 (0x1UL << USB_OTG_CHNUM_Pos) /*!< 0x00000001 */
21128 #define USB_OTG_CHNUM_1 (0x2UL << USB_OTG_CHNUM_Pos) /*!< 0x00000002 */
21129 #define USB_OTG_CHNUM_2 (0x4UL << USB_OTG_CHNUM_Pos) /*!< 0x00000004 */
21130 #define USB_OTG_CHNUM_3 (0x8UL << USB_OTG_CHNUM_Pos) /*!< 0x00000008 */
21131 #define USB_OTG_BCNT_Pos (4U)
21132 #define USB_OTG_BCNT_Msk (0x7FFUL << USB_OTG_BCNT_Pos) /*!< 0x00007FF0 */
21133 #define USB_OTG_BCNT USB_OTG_BCNT_Msk /*!< Byte count */
21134
21135 #define USB_OTG_DPID_Pos (15U)
21136 #define USB_OTG_DPID_Msk (0x3UL << USB_OTG_DPID_Pos) /*!< 0x00018000 */
21137 #define USB_OTG_DPID USB_OTG_DPID_Msk /*!< Data PID */
21138 #define USB_OTG_DPID_0 (0x1UL << USB_OTG_DPID_Pos) /*!< 0x00008000 */
21139 #define USB_OTG_DPID_1 (0x2UL << USB_OTG_DPID_Pos) /*!< 0x00010000 */
21140
21141 #define USB_OTG_PKTSTS_Pos (17U)
21142 #define USB_OTG_PKTSTS_Msk (0xFUL << USB_OTG_PKTSTS_Pos) /*!< 0x001E0000 */
21143 #define USB_OTG_PKTSTS USB_OTG_PKTSTS_Msk /*!< Packet status */
21144 #define USB_OTG_PKTSTS_0 (0x1UL << USB_OTG_PKTSTS_Pos) /*!< 0x00020000 */
21145 #define USB_OTG_PKTSTS_1 (0x2UL << USB_OTG_PKTSTS_Pos) /*!< 0x00040000 */
21146 #define USB_OTG_PKTSTS_2 (0x4UL << USB_OTG_PKTSTS_Pos) /*!< 0x00080000 */
21147 #define USB_OTG_PKTSTS_3 (0x8UL << USB_OTG_PKTSTS_Pos) /*!< 0x00100000 */
21148
21149 #define USB_OTG_EPNUM_Pos (0U)
21150 #define USB_OTG_EPNUM_Msk (0xFUL << USB_OTG_EPNUM_Pos) /*!< 0x0000000F */
21151 #define USB_OTG_EPNUM USB_OTG_EPNUM_Msk /*!< Endpoint number */
21152 #define USB_OTG_EPNUM_0 (0x1UL << USB_OTG_EPNUM_Pos) /*!< 0x00000001 */
21153 #define USB_OTG_EPNUM_1 (0x2UL << USB_OTG_EPNUM_Pos) /*!< 0x00000002 */
21154 #define USB_OTG_EPNUM_2 (0x4UL << USB_OTG_EPNUM_Pos) /*!< 0x00000004 */
21155 #define USB_OTG_EPNUM_3 (0x8UL << USB_OTG_EPNUM_Pos) /*!< 0x00000008 */
21156
21157 #define USB_OTG_FRMNUM_Pos (21U)
21158 #define USB_OTG_FRMNUM_Msk (0xFUL << USB_OTG_FRMNUM_Pos) /*!< 0x01E00000 */
21159 #define USB_OTG_FRMNUM USB_OTG_FRMNUM_Msk /*!< Frame number */
21160 #define USB_OTG_FRMNUM_0 (0x1UL << USB_OTG_FRMNUM_Pos) /*!< 0x00200000 */
21161 #define USB_OTG_FRMNUM_1 (0x2UL << USB_OTG_FRMNUM_Pos) /*!< 0x00400000 */
21162 #define USB_OTG_FRMNUM_2 (0x4UL << USB_OTG_FRMNUM_Pos) /*!< 0x00800000 */
21163 #define USB_OTG_FRMNUM_3 (0x8UL << USB_OTG_FRMNUM_Pos) /*!< 0x01000000 */
21164
21165 /******************** Bit definition forUSB_OTG_GRXFSIZ register ********************/
21166 #define USB_OTG_GRXFSIZ_RXFD_Pos (0U)
21167 #define USB_OTG_GRXFSIZ_RXFD_Msk (0xFFFFUL << USB_OTG_GRXFSIZ_RXFD_Pos) /*!< 0x0000FFFF */
21168 #define USB_OTG_GRXFSIZ_RXFD USB_OTG_GRXFSIZ_RXFD_Msk /*!< RxFIFO depth */
21169
21170 /******************** Bit definition forUSB_OTG_DVBUSDIS register ********************/
21171 #define USB_OTG_DVBUSDIS_VBUSDT_Pos (0U)
21172 #define USB_OTG_DVBUSDIS_VBUSDT_Msk (0xFFFFUL << USB_OTG_DVBUSDIS_VBUSDT_Pos) /*!< 0x0000FFFF */
21173 #define USB_OTG_DVBUSDIS_VBUSDT USB_OTG_DVBUSDIS_VBUSDT_Msk /*!< Device VBUS discharge time */
21174
21175 /******************** Bit definition for OTG register ********************/
21176 #define USB_OTG_NPTXFSA_Pos (0U)
21177 #define USB_OTG_NPTXFSA_Msk (0xFFFFUL << USB_OTG_NPTXFSA_Pos) /*!< 0x0000FFFF */
21178 #define USB_OTG_NPTXFSA USB_OTG_NPTXFSA_Msk /*!< Nonperiodic transmit RAM start address */
21179 #define USB_OTG_NPTXFD_Pos (16U)
21180 #define USB_OTG_NPTXFD_Msk (0xFFFFUL << USB_OTG_NPTXFD_Pos) /*!< 0xFFFF0000 */
21181 #define USB_OTG_NPTXFD USB_OTG_NPTXFD_Msk /*!< Nonperiodic TxFIFO depth */
21182 #define USB_OTG_TX0FSA_Pos (0U)
21183 #define USB_OTG_TX0FSA_Msk (0xFFFFUL << USB_OTG_TX0FSA_Pos) /*!< 0x0000FFFF */
21184 #define USB_OTG_TX0FSA USB_OTG_TX0FSA_Msk /*!< Endpoint 0 transmit RAM start address */
21185 #define USB_OTG_TX0FD_Pos (16U)
21186 #define USB_OTG_TX0FD_Msk (0xFFFFUL << USB_OTG_TX0FD_Pos) /*!< 0xFFFF0000 */
21187 #define USB_OTG_TX0FD USB_OTG_TX0FD_Msk /*!< Endpoint 0 TxFIFO depth */
21188
21189 /******************** Bit definition forUSB_OTG_DVBUSPULSE register ********************/
21190 #define USB_OTG_DVBUSPULSE_DVBUSP_Pos (0U)
21191 #define USB_OTG_DVBUSPULSE_DVBUSP_Msk (0xFFFUL << USB_OTG_DVBUSPULSE_DVBUSP_Pos) /*!< 0x00000FFF */
21192 #define USB_OTG_DVBUSPULSE_DVBUSP USB_OTG_DVBUSPULSE_DVBUSP_Msk /*!< Device VBUS pulsing time */
21193
21194 /******************** Bit definition forUSB_OTG_GNPTXSTS register ********************/
21195 #define USB_OTG_GNPTXSTS_NPTXFSAV_Pos (0U)
21196 #define USB_OTG_GNPTXSTS_NPTXFSAV_Msk (0xFFFFUL << USB_OTG_GNPTXSTS_NPTXFSAV_Pos) /*!< 0x0000FFFF */
21197 #define USB_OTG_GNPTXSTS_NPTXFSAV USB_OTG_GNPTXSTS_NPTXFSAV_Msk /*!< Nonperiodic TxFIFO space available */
21198
21199 #define USB_OTG_GNPTXSTS_NPTQXSAV_Pos (16U)
21200 #define USB_OTG_GNPTXSTS_NPTQXSAV_Msk (0xFFUL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00FF0000 */
21201 #define USB_OTG_GNPTXSTS_NPTQXSAV USB_OTG_GNPTXSTS_NPTQXSAV_Msk /*!< Nonperiodic transmit request queue space available */
21202 #define USB_OTG_GNPTXSTS_NPTQXSAV_0 (0x01UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00010000 */
21203 #define USB_OTG_GNPTXSTS_NPTQXSAV_1 (0x02UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00020000 */
21204 #define USB_OTG_GNPTXSTS_NPTQXSAV_2 (0x04UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00040000 */
21205 #define USB_OTG_GNPTXSTS_NPTQXSAV_3 (0x08UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00080000 */
21206 #define USB_OTG_GNPTXSTS_NPTQXSAV_4 (0x10UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00100000 */
21207 #define USB_OTG_GNPTXSTS_NPTQXSAV_5 (0x20UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00200000 */
21208 #define USB_OTG_GNPTXSTS_NPTQXSAV_6 (0x40UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00400000 */
21209 #define USB_OTG_GNPTXSTS_NPTQXSAV_7 (0x80UL << USB_OTG_GNPTXSTS_NPTQXSAV_Pos) /*!< 0x00800000 */
21210
21211 #define USB_OTG_GNPTXSTS_NPTXQTOP_Pos (24U)
21212 #define USB_OTG_GNPTXSTS_NPTXQTOP_Msk (0x7FUL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x7F000000 */
21213 #define USB_OTG_GNPTXSTS_NPTXQTOP USB_OTG_GNPTXSTS_NPTXQTOP_Msk /*!< Top of the nonperiodic transmit request queue */
21214 #define USB_OTG_GNPTXSTS_NPTXQTOP_0 (0x01UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x01000000 */
21215 #define USB_OTG_GNPTXSTS_NPTXQTOP_1 (0x02UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x02000000 */
21216 #define USB_OTG_GNPTXSTS_NPTXQTOP_2 (0x04UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x04000000 */
21217 #define USB_OTG_GNPTXSTS_NPTXQTOP_3 (0x08UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x08000000 */
21218 #define USB_OTG_GNPTXSTS_NPTXQTOP_4 (0x10UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x10000000 */
21219 #define USB_OTG_GNPTXSTS_NPTXQTOP_5 (0x20UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x20000000 */
21220 #define USB_OTG_GNPTXSTS_NPTXQTOP_6 (0x40UL << USB_OTG_GNPTXSTS_NPTXQTOP_Pos) /*!< 0x40000000 */
21221
21222 /******************** Bit definition forUSB_OTG_DTHRCTL register ********************/
21223 #define USB_OTG_DTHRCTL_NONISOTHREN_Pos (0U)
21224 #define USB_OTG_DTHRCTL_NONISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_NONISOTHREN_Pos) /*!< 0x00000001 */
21225 #define USB_OTG_DTHRCTL_NONISOTHREN USB_OTG_DTHRCTL_NONISOTHREN_Msk /*!< Nonisochronous IN endpoints threshold enable */
21226 #define USB_OTG_DTHRCTL_ISOTHREN_Pos (1U)
21227 #define USB_OTG_DTHRCTL_ISOTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_ISOTHREN_Pos) /*!< 0x00000002 */
21228 #define USB_OTG_DTHRCTL_ISOTHREN USB_OTG_DTHRCTL_ISOTHREN_Msk /*!< ISO IN endpoint threshold enable */
21229
21230 #define USB_OTG_DTHRCTL_TXTHRLEN_Pos (2U)
21231 #define USB_OTG_DTHRCTL_TXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x000007FC */
21232 #define USB_OTG_DTHRCTL_TXTHRLEN USB_OTG_DTHRCTL_TXTHRLEN_Msk /*!< Transmit threshold length */
21233 #define USB_OTG_DTHRCTL_TXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000004 */
21234 #define USB_OTG_DTHRCTL_TXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000008 */
21235 #define USB_OTG_DTHRCTL_TXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000010 */
21236 #define USB_OTG_DTHRCTL_TXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000020 */
21237 #define USB_OTG_DTHRCTL_TXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000040 */
21238 #define USB_OTG_DTHRCTL_TXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000080 */
21239 #define USB_OTG_DTHRCTL_TXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000100 */
21240 #define USB_OTG_DTHRCTL_TXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000200 */
21241 #define USB_OTG_DTHRCTL_TXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_TXTHRLEN_Pos) /*!< 0x00000400 */
21242 #define USB_OTG_DTHRCTL_RXTHREN_Pos (16U)
21243 #define USB_OTG_DTHRCTL_RXTHREN_Msk (0x1UL << USB_OTG_DTHRCTL_RXTHREN_Pos) /*!< 0x00010000 */
21244 #define USB_OTG_DTHRCTL_RXTHREN USB_OTG_DTHRCTL_RXTHREN_Msk /*!< Receive threshold enable */
21245
21246 #define USB_OTG_DTHRCTL_RXTHRLEN_Pos (17U)
21247 #define USB_OTG_DTHRCTL_RXTHRLEN_Msk (0x1FFUL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x03FE0000 */
21248 #define USB_OTG_DTHRCTL_RXTHRLEN USB_OTG_DTHRCTL_RXTHRLEN_Msk /*!< Receive threshold length */
21249 #define USB_OTG_DTHRCTL_RXTHRLEN_0 (0x001UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00020000 */
21250 #define USB_OTG_DTHRCTL_RXTHRLEN_1 (0x002UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00040000 */
21251 #define USB_OTG_DTHRCTL_RXTHRLEN_2 (0x004UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00080000 */
21252 #define USB_OTG_DTHRCTL_RXTHRLEN_3 (0x008UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00100000 */
21253 #define USB_OTG_DTHRCTL_RXTHRLEN_4 (0x010UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00200000 */
21254 #define USB_OTG_DTHRCTL_RXTHRLEN_5 (0x020UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00400000 */
21255 #define USB_OTG_DTHRCTL_RXTHRLEN_6 (0x040UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x00800000 */
21256 #define USB_OTG_DTHRCTL_RXTHRLEN_7 (0x080UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x01000000 */
21257 #define USB_OTG_DTHRCTL_RXTHRLEN_8 (0x100UL << USB_OTG_DTHRCTL_RXTHRLEN_Pos) /*!< 0x02000000 */
21258 #define USB_OTG_DTHRCTL_ARPEN_Pos (27U)
21259 #define USB_OTG_DTHRCTL_ARPEN_Msk (0x1UL << USB_OTG_DTHRCTL_ARPEN_Pos) /*!< 0x08000000 */
21260 #define USB_OTG_DTHRCTL_ARPEN USB_OTG_DTHRCTL_ARPEN_Msk /*!< Arbiter parking enable */
21261
21262 /******************** Bit definition forUSB_OTG_DIEPEMPMSK register ********************/
21263 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos (0U)
21264 #define USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk (0xFFFFUL << USB_OTG_DIEPEMPMSK_INEPTXFEM_Pos) /*!< 0x0000FFFF */
21265 #define USB_OTG_DIEPEMPMSK_INEPTXFEM USB_OTG_DIEPEMPMSK_INEPTXFEM_Msk /*!< IN EP Tx FIFO empty interrupt mask bits */
21266
21267 /******************** Bit definition forUSB_OTG_DEACHINT register ********************/
21268 #define USB_OTG_DEACHINT_IEP1INT_Pos (1U)
21269 #define USB_OTG_DEACHINT_IEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_IEP1INT_Pos) /*!< 0x00000002 */
21270 #define USB_OTG_DEACHINT_IEP1INT USB_OTG_DEACHINT_IEP1INT_Msk /*!< IN endpoint 1interrupt bit */
21271 #define USB_OTG_DEACHINT_OEP1INT_Pos (17U)
21272 #define USB_OTG_DEACHINT_OEP1INT_Msk (0x1UL << USB_OTG_DEACHINT_OEP1INT_Pos) /*!< 0x00020000 */
21273 #define USB_OTG_DEACHINT_OEP1INT USB_OTG_DEACHINT_OEP1INT_Msk /*!< OUT endpoint 1 interrupt bit */
21274
21275 /******************** Bit definition forUSB_OTG_GCCFG register ********************/
21276 #define USB_OTG_GCCFG_DCDET_Pos (0U)
21277 #define USB_OTG_GCCFG_DCDET_Msk (0x1UL << USB_OTG_GCCFG_DCDET_Pos) /*!< 0x00000001 */
21278 #define USB_OTG_GCCFG_DCDET USB_OTG_GCCFG_DCDET_Msk /*!< Data contact detection (DCD) status */
21279 #define USB_OTG_GCCFG_PDET_Pos (1U)
21280 #define USB_OTG_GCCFG_PDET_Msk (0x1UL << USB_OTG_GCCFG_PDET_Pos) /*!< 0x00000002 */
21281 #define USB_OTG_GCCFG_PDET USB_OTG_GCCFG_PDET_Msk /*!< Primary detection (PD) status */
21282 #define USB_OTG_GCCFG_SDET_Pos (2U)
21283 #define USB_OTG_GCCFG_SDET_Msk (0x1UL << USB_OTG_GCCFG_SDET_Pos) /*!< 0x00000004 */
21284 #define USB_OTG_GCCFG_SDET USB_OTG_GCCFG_SDET_Msk /*!< Secondary detection (SD) status */
21285 #define USB_OTG_GCCFG_PS2DET_Pos (3U)
21286 #define USB_OTG_GCCFG_PS2DET_Msk (0x1UL << USB_OTG_GCCFG_PS2DET_Pos) /*!< 0x00000008 */
21287 #define USB_OTG_GCCFG_PS2DET USB_OTG_GCCFG_PS2DET_Msk /*!< DM pull-up detection status */
21288 #define USB_OTG_GCCFG_PWRDWN_Pos (16U)
21289 #define USB_OTG_GCCFG_PWRDWN_Msk (0x1UL << USB_OTG_GCCFG_PWRDWN_Pos) /*!< 0x00010000 */
21290 #define USB_OTG_GCCFG_PWRDWN USB_OTG_GCCFG_PWRDWN_Msk /*!< Power down */
21291 #define USB_OTG_GCCFG_BCDEN_Pos (17U)
21292 #define USB_OTG_GCCFG_BCDEN_Msk (0x1UL << USB_OTG_GCCFG_BCDEN_Pos) /*!< 0x00020000 */
21293 #define USB_OTG_GCCFG_BCDEN USB_OTG_GCCFG_BCDEN_Msk /*!< Battery charging detector (BCD) enable */
21294 #define USB_OTG_GCCFG_DCDEN_Pos (18U)
21295 #define USB_OTG_GCCFG_DCDEN_Msk (0x1UL << USB_OTG_GCCFG_DCDEN_Pos) /*!< 0x00040000 */
21296 #define USB_OTG_GCCFG_DCDEN USB_OTG_GCCFG_DCDEN_Msk /*!< Data contact detection (DCD) mode enable*/
21297 #define USB_OTG_GCCFG_PDEN_Pos (19U)
21298 #define USB_OTG_GCCFG_PDEN_Msk (0x1UL << USB_OTG_GCCFG_PDEN_Pos) /*!< 0x00080000 */
21299 #define USB_OTG_GCCFG_PDEN USB_OTG_GCCFG_PDEN_Msk /*!< Primary detection (PD) mode enable*/
21300 #define USB_OTG_GCCFG_SDEN_Pos (20U)
21301 #define USB_OTG_GCCFG_SDEN_Msk (0x1UL << USB_OTG_GCCFG_SDEN_Pos) /*!< 0x00100000 */
21302 #define USB_OTG_GCCFG_SDEN USB_OTG_GCCFG_SDEN_Msk /*!< Secondary detection (SD) mode enable */
21303 #define USB_OTG_GCCFG_VBDEN_Pos (21U)
21304 #define USB_OTG_GCCFG_VBDEN_Msk (0x1UL << USB_OTG_GCCFG_VBDEN_Pos) /*!< 0x00200000 */
21305 #define USB_OTG_GCCFG_VBDEN USB_OTG_GCCFG_VBDEN_Msk /*!< Secondary detection (SD) mode enable */
21306
21307 /******************** Bit definition forUSB_OTG_GPWRDN) register ********************/
21308 #define USB_OTG_GPWRDN_ADPMEN_Pos (0U)
21309 #define USB_OTG_GPWRDN_ADPMEN_Msk (0x1UL << USB_OTG_GPWRDN_ADPMEN_Pos) /*!< 0x00000001 */
21310 #define USB_OTG_GPWRDN_ADPMEN USB_OTG_GPWRDN_ADPMEN_Msk /*!< ADP module enable */
21311 #define USB_OTG_GPWRDN_ADPIF_Pos (23U)
21312 #define USB_OTG_GPWRDN_ADPIF_Msk (0x1UL << USB_OTG_GPWRDN_ADPIF_Pos) /*!< 0x00800000 */
21313 #define USB_OTG_GPWRDN_ADPIF USB_OTG_GPWRDN_ADPIF_Msk /*!< ADP Interrupt flag */
21314
21315 /******************** Bit definition forUSB_OTG_DEACHINTMSK register ********************/
21316 #define USB_OTG_DEACHINTMSK_IEP1INTM_Pos (1U)
21317 #define USB_OTG_DEACHINTMSK_IEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_IEP1INTM_Pos) /*!< 0x00000002 */
21318 #define USB_OTG_DEACHINTMSK_IEP1INTM USB_OTG_DEACHINTMSK_IEP1INTM_Msk /*!< IN Endpoint 1 interrupt mask bit */
21319 #define USB_OTG_DEACHINTMSK_OEP1INTM_Pos (17U)
21320 #define USB_OTG_DEACHINTMSK_OEP1INTM_Msk (0x1UL << USB_OTG_DEACHINTMSK_OEP1INTM_Pos) /*!< 0x00020000 */
21321 #define USB_OTG_DEACHINTMSK_OEP1INTM USB_OTG_DEACHINTMSK_OEP1INTM_Msk /*!< OUT Endpoint 1 interrupt mask bit */
21322
21323 /******************** Bit definition forUSB_OTG_CID register ********************/
21324 #define USB_OTG_CID_PRODUCT_ID_Pos (0U)
21325 #define USB_OTG_CID_PRODUCT_ID_Msk (0xFFFFFFFFUL << USB_OTG_CID_PRODUCT_ID_Pos) /*!< 0xFFFFFFFF */
21326 #define USB_OTG_CID_PRODUCT_ID USB_OTG_CID_PRODUCT_ID_Msk /*!< Product ID field */
21327
21328 /******************** Bit definition for USB_OTG_GLPMCFG register ********************/
21329 #define USB_OTG_GLPMCFG_LPMEN_Pos (0U)
21330 #define USB_OTG_GLPMCFG_LPMEN_Msk (0x1UL << USB_OTG_GLPMCFG_LPMEN_Pos) /*!< 0x00000001 */
21331 #define USB_OTG_GLPMCFG_LPMEN USB_OTG_GLPMCFG_LPMEN_Msk /*!< LPM support enable */
21332 #define USB_OTG_GLPMCFG_LPMACK_Pos (1U)
21333 #define USB_OTG_GLPMCFG_LPMACK_Msk (0x1UL << USB_OTG_GLPMCFG_LPMACK_Pos) /*!< 0x00000002 */
21334 #define USB_OTG_GLPMCFG_LPMACK USB_OTG_GLPMCFG_LPMACK_Msk /*!< LPM Token acknowledge enable */
21335 #define USB_OTG_GLPMCFG_BESL_Pos (2U)
21336 #define USB_OTG_GLPMCFG_BESL_Msk (0xFUL << USB_OTG_GLPMCFG_BESL_Pos) /*!< 0x0000003C */
21337 #define USB_OTG_GLPMCFG_BESL USB_OTG_GLPMCFG_BESL_Msk /*!< BESL value received with last ACKed LPM Token */
21338 #define USB_OTG_GLPMCFG_REMWAKE_Pos (6U)
21339 #define USB_OTG_GLPMCFG_REMWAKE_Msk (0x1UL << USB_OTG_GLPMCFG_REMWAKE_Pos) /*!< 0x00000040 */
21340 #define USB_OTG_GLPMCFG_REMWAKE USB_OTG_GLPMCFG_REMWAKE_Msk /*!< bRemoteWake value received with last ACKed LPM Token */
21341 #define USB_OTG_GLPMCFG_L1SSEN_Pos (7U)
21342 #define USB_OTG_GLPMCFG_L1SSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1SSEN_Pos) /*!< 0x00000080 */
21343 #define USB_OTG_GLPMCFG_L1SSEN USB_OTG_GLPMCFG_L1SSEN_Msk /*!< L1 shallow sleep enable */
21344 #define USB_OTG_GLPMCFG_BESLTHRS_Pos (8U)
21345 #define USB_OTG_GLPMCFG_BESLTHRS_Msk (0xFUL << USB_OTG_GLPMCFG_BESLTHRS_Pos) /*!< 0x00000F00 */
21346 #define USB_OTG_GLPMCFG_BESLTHRS USB_OTG_GLPMCFG_BESLTHRS_Msk /*!< BESL threshold */
21347 #define USB_OTG_GLPMCFG_L1DSEN_Pos (12U)
21348 #define USB_OTG_GLPMCFG_L1DSEN_Msk (0x1UL << USB_OTG_GLPMCFG_L1DSEN_Pos) /*!< 0x00001000 */
21349 #define USB_OTG_GLPMCFG_L1DSEN USB_OTG_GLPMCFG_L1DSEN_Msk /*!< L1 deep sleep enable */
21350 #define USB_OTG_GLPMCFG_LPMRSP_Pos (13U)
21351 #define USB_OTG_GLPMCFG_LPMRSP_Msk (0x3UL << USB_OTG_GLPMCFG_LPMRSP_Pos) /*!< 0x00006000 */
21352 #define USB_OTG_GLPMCFG_LPMRSP USB_OTG_GLPMCFG_LPMRSP_Msk /*!< LPM response */
21353 #define USB_OTG_GLPMCFG_SLPSTS_Pos (15U)
21354 #define USB_OTG_GLPMCFG_SLPSTS_Msk (0x1UL << USB_OTG_GLPMCFG_SLPSTS_Pos) /*!< 0x00008000 */
21355 #define USB_OTG_GLPMCFG_SLPSTS USB_OTG_GLPMCFG_SLPSTS_Msk /*!< Port sleep status */
21356 #define USB_OTG_GLPMCFG_L1RSMOK_Pos (16U)
21357 #define USB_OTG_GLPMCFG_L1RSMOK_Msk (0x1UL << USB_OTG_GLPMCFG_L1RSMOK_Pos) /*!< 0x00010000 */
21358 #define USB_OTG_GLPMCFG_L1RSMOK USB_OTG_GLPMCFG_L1RSMOK_Msk /*!< Sleep State Resume OK */
21359 #define USB_OTG_GLPMCFG_LPMCHIDX_Pos (17U)
21360 #define USB_OTG_GLPMCFG_LPMCHIDX_Msk (0xFUL << USB_OTG_GLPMCFG_LPMCHIDX_Pos) /*!< 0x001E0000 */
21361 #define USB_OTG_GLPMCFG_LPMCHIDX USB_OTG_GLPMCFG_LPMCHIDX_Msk /*!< LPM Channel Index */
21362 #define USB_OTG_GLPMCFG_LPMRCNT_Pos (21U)
21363 #define USB_OTG_GLPMCFG_LPMRCNT_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNT_Pos) /*!< 0x00E00000 */
21364 #define USB_OTG_GLPMCFG_LPMRCNT USB_OTG_GLPMCFG_LPMRCNT_Msk /*!< LPM retry count */
21365 #define USB_OTG_GLPMCFG_SNDLPM_Pos (24U)
21366 #define USB_OTG_GLPMCFG_SNDLPM_Msk (0x1UL << USB_OTG_GLPMCFG_SNDLPM_Pos) /*!< 0x01000000 */
21367 #define USB_OTG_GLPMCFG_SNDLPM USB_OTG_GLPMCFG_SNDLPM_Msk /*!< Send LPM transaction */
21368 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Pos (25U)
21369 #define USB_OTG_GLPMCFG_LPMRCNTSTS_Msk (0x7UL << USB_OTG_GLPMCFG_LPMRCNTSTS_Pos) /*!< 0x0E000000 */
21370 #define USB_OTG_GLPMCFG_LPMRCNTSTS USB_OTG_GLPMCFG_LPMRCNTSTS_Msk /*!< LPM retry count status */
21371 #define USB_OTG_GLPMCFG_ENBESL_Pos (28U)
21372 #define USB_OTG_GLPMCFG_ENBESL_Msk (0x1UL << USB_OTG_GLPMCFG_ENBESL_Pos) /*!< 0x10000000 */
21373 #define USB_OTG_GLPMCFG_ENBESL USB_OTG_GLPMCFG_ENBESL_Msk /*!< Enable best effort service latency */
21374
21375 /******************** Bit definition forUSB_OTG_DIEPEACHMSK1 register ********************/
21376 #define USB_OTG_DIEPEACHMSK1_XFRCM_Pos (0U)
21377 #define USB_OTG_DIEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
21378 #define USB_OTG_DIEPEACHMSK1_XFRCM USB_OTG_DIEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
21379 #define USB_OTG_DIEPEACHMSK1_EPDM_Pos (1U)
21380 #define USB_OTG_DIEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
21381 #define USB_OTG_DIEPEACHMSK1_EPDM USB_OTG_DIEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
21382 #define USB_OTG_DIEPEACHMSK1_TOM_Pos (3U)
21383 #define USB_OTG_DIEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
21384 #define USB_OTG_DIEPEACHMSK1_TOM USB_OTG_DIEPEACHMSK1_TOM_Msk /*!< Timeout condition mask (nonisochronous endpoints) */
21385 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos (4U)
21386 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
21387 #define USB_OTG_DIEPEACHMSK1_ITTXFEMSK USB_OTG_DIEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
21388 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Pos (5U)
21389 #define USB_OTG_DIEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
21390 #define USB_OTG_DIEPEACHMSK1_INEPNMM USB_OTG_DIEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
21391 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Pos (6U)
21392 #define USB_OTG_DIEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
21393 #define USB_OTG_DIEPEACHMSK1_INEPNEM USB_OTG_DIEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
21394 #define USB_OTG_DIEPEACHMSK1_TXFURM_Pos (8U)
21395 #define USB_OTG_DIEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
21396 #define USB_OTG_DIEPEACHMSK1_TXFURM USB_OTG_DIEPEACHMSK1_TXFURM_Msk /*!< FIFO underrun mask */
21397 #define USB_OTG_DIEPEACHMSK1_BIM_Pos (9U)
21398 #define USB_OTG_DIEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
21399 #define USB_OTG_DIEPEACHMSK1_BIM USB_OTG_DIEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
21400 #define USB_OTG_DIEPEACHMSK1_NAKM_Pos (13U)
21401 #define USB_OTG_DIEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DIEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
21402 #define USB_OTG_DIEPEACHMSK1_NAKM USB_OTG_DIEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
21403
21404 /******************** Bit definition forUSB_OTG_HPRT register ********************/
21405 #define USB_OTG_HPRT_PCSTS_Pos (0U)
21406 #define USB_OTG_HPRT_PCSTS_Msk (0x1UL << USB_OTG_HPRT_PCSTS_Pos) /*!< 0x00000001 */
21407 #define USB_OTG_HPRT_PCSTS USB_OTG_HPRT_PCSTS_Msk /*!< Port connect status */
21408 #define USB_OTG_HPRT_PCDET_Pos (1U)
21409 #define USB_OTG_HPRT_PCDET_Msk (0x1UL << USB_OTG_HPRT_PCDET_Pos) /*!< 0x00000002 */
21410 #define USB_OTG_HPRT_PCDET USB_OTG_HPRT_PCDET_Msk /*!< Port connect detected */
21411 #define USB_OTG_HPRT_PENA_Pos (2U)
21412 #define USB_OTG_HPRT_PENA_Msk (0x1UL << USB_OTG_HPRT_PENA_Pos) /*!< 0x00000004 */
21413 #define USB_OTG_HPRT_PENA USB_OTG_HPRT_PENA_Msk /*!< Port enable */
21414 #define USB_OTG_HPRT_PENCHNG_Pos (3U)
21415 #define USB_OTG_HPRT_PENCHNG_Msk (0x1UL << USB_OTG_HPRT_PENCHNG_Pos) /*!< 0x00000008 */
21416 #define USB_OTG_HPRT_PENCHNG USB_OTG_HPRT_PENCHNG_Msk /*!< Port enable/disable change */
21417 #define USB_OTG_HPRT_POCA_Pos (4U)
21418 #define USB_OTG_HPRT_POCA_Msk (0x1UL << USB_OTG_HPRT_POCA_Pos) /*!< 0x00000010 */
21419 #define USB_OTG_HPRT_POCA USB_OTG_HPRT_POCA_Msk /*!< Port overcurrent active */
21420 #define USB_OTG_HPRT_POCCHNG_Pos (5U)
21421 #define USB_OTG_HPRT_POCCHNG_Msk (0x1UL << USB_OTG_HPRT_POCCHNG_Pos) /*!< 0x00000020 */
21422 #define USB_OTG_HPRT_POCCHNG USB_OTG_HPRT_POCCHNG_Msk /*!< Port overcurrent change */
21423 #define USB_OTG_HPRT_PRES_Pos (6U)
21424 #define USB_OTG_HPRT_PRES_Msk (0x1UL << USB_OTG_HPRT_PRES_Pos) /*!< 0x00000040 */
21425 #define USB_OTG_HPRT_PRES USB_OTG_HPRT_PRES_Msk /*!< Port resume */
21426 #define USB_OTG_HPRT_PSUSP_Pos (7U)
21427 #define USB_OTG_HPRT_PSUSP_Msk (0x1UL << USB_OTG_HPRT_PSUSP_Pos) /*!< 0x00000080 */
21428 #define USB_OTG_HPRT_PSUSP USB_OTG_HPRT_PSUSP_Msk /*!< Port suspend */
21429 #define USB_OTG_HPRT_PRST_Pos (8U)
21430 #define USB_OTG_HPRT_PRST_Msk (0x1UL << USB_OTG_HPRT_PRST_Pos) /*!< 0x00000100 */
21431 #define USB_OTG_HPRT_PRST USB_OTG_HPRT_PRST_Msk /*!< Port reset */
21432
21433 #define USB_OTG_HPRT_PLSTS_Pos (10U)
21434 #define USB_OTG_HPRT_PLSTS_Msk (0x3UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000C00 */
21435 #define USB_OTG_HPRT_PLSTS USB_OTG_HPRT_PLSTS_Msk /*!< Port line status */
21436 #define USB_OTG_HPRT_PLSTS_0 (0x1UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000400 */
21437 #define USB_OTG_HPRT_PLSTS_1 (0x2UL << USB_OTG_HPRT_PLSTS_Pos) /*!< 0x00000800 */
21438 #define USB_OTG_HPRT_PPWR_Pos (12U)
21439 #define USB_OTG_HPRT_PPWR_Msk (0x1UL << USB_OTG_HPRT_PPWR_Pos) /*!< 0x00001000 */
21440 #define USB_OTG_HPRT_PPWR USB_OTG_HPRT_PPWR_Msk /*!< Port power */
21441
21442 #define USB_OTG_HPRT_PTCTL_Pos (13U)
21443 #define USB_OTG_HPRT_PTCTL_Msk (0xFUL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x0001E000 */
21444 #define USB_OTG_HPRT_PTCTL USB_OTG_HPRT_PTCTL_Msk /*!< Port test control */
21445 #define USB_OTG_HPRT_PTCTL_0 (0x1UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00002000 */
21446 #define USB_OTG_HPRT_PTCTL_1 (0x2UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00004000 */
21447 #define USB_OTG_HPRT_PTCTL_2 (0x4UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00008000 */
21448 #define USB_OTG_HPRT_PTCTL_3 (0x8UL << USB_OTG_HPRT_PTCTL_Pos) /*!< 0x00010000 */
21449
21450 #define USB_OTG_HPRT_PSPD_Pos (17U)
21451 #define USB_OTG_HPRT_PSPD_Msk (0x3UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00060000 */
21452 #define USB_OTG_HPRT_PSPD USB_OTG_HPRT_PSPD_Msk /*!< Port speed */
21453 #define USB_OTG_HPRT_PSPD_0 (0x1UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00020000 */
21454 #define USB_OTG_HPRT_PSPD_1 (0x2UL << USB_OTG_HPRT_PSPD_Pos) /*!< 0x00040000 */
21455
21456 /******************** Bit definition forUSB_OTG_DOEPEACHMSK1 register ********************/
21457 #define USB_OTG_DOEPEACHMSK1_XFRCM_Pos (0U)
21458 #define USB_OTG_DOEPEACHMSK1_XFRCM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_XFRCM_Pos) /*!< 0x00000001 */
21459 #define USB_OTG_DOEPEACHMSK1_XFRCM USB_OTG_DOEPEACHMSK1_XFRCM_Msk /*!< Transfer completed interrupt mask */
21460 #define USB_OTG_DOEPEACHMSK1_EPDM_Pos (1U)
21461 #define USB_OTG_DOEPEACHMSK1_EPDM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_EPDM_Pos) /*!< 0x00000002 */
21462 #define USB_OTG_DOEPEACHMSK1_EPDM USB_OTG_DOEPEACHMSK1_EPDM_Msk /*!< Endpoint disabled interrupt mask */
21463 #define USB_OTG_DOEPEACHMSK1_TOM_Pos (3U)
21464 #define USB_OTG_DOEPEACHMSK1_TOM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TOM_Pos) /*!< 0x00000008 */
21465 #define USB_OTG_DOEPEACHMSK1_TOM USB_OTG_DOEPEACHMSK1_TOM_Msk /*!< Timeout condition mask */
21466 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos (4U)
21467 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Pos) /*!< 0x00000010 */
21468 #define USB_OTG_DOEPEACHMSK1_ITTXFEMSK USB_OTG_DOEPEACHMSK1_ITTXFEMSK_Msk /*!< IN token received when TxFIFO empty mask */
21469 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Pos (5U)
21470 #define USB_OTG_DOEPEACHMSK1_INEPNMM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNMM_Pos) /*!< 0x00000020 */
21471 #define USB_OTG_DOEPEACHMSK1_INEPNMM USB_OTG_DOEPEACHMSK1_INEPNMM_Msk /*!< IN token received with EP mismatch mask */
21472 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Pos (6U)
21473 #define USB_OTG_DOEPEACHMSK1_INEPNEM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_INEPNEM_Pos) /*!< 0x00000040 */
21474 #define USB_OTG_DOEPEACHMSK1_INEPNEM USB_OTG_DOEPEACHMSK1_INEPNEM_Msk /*!< IN endpoint NAK effective mask */
21475 #define USB_OTG_DOEPEACHMSK1_TXFURM_Pos (8U)
21476 #define USB_OTG_DOEPEACHMSK1_TXFURM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_TXFURM_Pos) /*!< 0x00000100 */
21477 #define USB_OTG_DOEPEACHMSK1_TXFURM USB_OTG_DOEPEACHMSK1_TXFURM_Msk /*!< OUT packet error mask */
21478 #define USB_OTG_DOEPEACHMSK1_BIM_Pos (9U)
21479 #define USB_OTG_DOEPEACHMSK1_BIM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BIM_Pos) /*!< 0x00000200 */
21480 #define USB_OTG_DOEPEACHMSK1_BIM USB_OTG_DOEPEACHMSK1_BIM_Msk /*!< BNA interrupt mask */
21481 #define USB_OTG_DOEPEACHMSK1_BERRM_Pos (12U)
21482 #define USB_OTG_DOEPEACHMSK1_BERRM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_BERRM_Pos) /*!< 0x00001000 */
21483 #define USB_OTG_DOEPEACHMSK1_BERRM USB_OTG_DOEPEACHMSK1_BERRM_Msk /*!< Bubble error interrupt mask */
21484 #define USB_OTG_DOEPEACHMSK1_NAKM_Pos (13U)
21485 #define USB_OTG_DOEPEACHMSK1_NAKM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NAKM_Pos) /*!< 0x00002000 */
21486 #define USB_OTG_DOEPEACHMSK1_NAKM USB_OTG_DOEPEACHMSK1_NAKM_Msk /*!< NAK interrupt mask */
21487 #define USB_OTG_DOEPEACHMSK1_NYETM_Pos (14U)
21488 #define USB_OTG_DOEPEACHMSK1_NYETM_Msk (0x1UL << USB_OTG_DOEPEACHMSK1_NYETM_Pos) /*!< 0x00004000 */
21489 #define USB_OTG_DOEPEACHMSK1_NYETM USB_OTG_DOEPEACHMSK1_NYETM_Msk /*!< NYET interrupt mask */
21490
21491 /******************** Bit definition forUSB_OTG_HPTXFSIZ register ********************/
21492 #define USB_OTG_HPTXFSIZ_PTXSA_Pos (0U)
21493 #define USB_OTG_HPTXFSIZ_PTXSA_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXSA_Pos) /*!< 0x0000FFFF */
21494 #define USB_OTG_HPTXFSIZ_PTXSA USB_OTG_HPTXFSIZ_PTXSA_Msk /*!< Host periodic TxFIFO start address */
21495 #define USB_OTG_HPTXFSIZ_PTXFD_Pos (16U)
21496 #define USB_OTG_HPTXFSIZ_PTXFD_Msk (0xFFFFUL << USB_OTG_HPTXFSIZ_PTXFD_Pos) /*!< 0xFFFF0000 */
21497 #define USB_OTG_HPTXFSIZ_PTXFD USB_OTG_HPTXFSIZ_PTXFD_Msk /*!< Host periodic TxFIFO depth */
21498
21499 /******************** Bit definition forUSB_OTG_DIEPCTL register ********************/
21500 #define USB_OTG_DIEPCTL_MPSIZ_Pos (0U)
21501 #define USB_OTG_DIEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DIEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
21502 #define USB_OTG_DIEPCTL_MPSIZ USB_OTG_DIEPCTL_MPSIZ_Msk /*!< Maximum packet size */
21503 #define USB_OTG_DIEPCTL_USBAEP_Pos (15U)
21504 #define USB_OTG_DIEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DIEPCTL_USBAEP_Pos) /*!< 0x00008000 */
21505 #define USB_OTG_DIEPCTL_USBAEP USB_OTG_DIEPCTL_USBAEP_Msk /*!< USB active endpoint */
21506 #define USB_OTG_DIEPCTL_EONUM_DPID_Pos (16U)
21507 #define USB_OTG_DIEPCTL_EONUM_DPID_Msk (0x1UL << USB_OTG_DIEPCTL_EONUM_DPID_Pos) /*!< 0x00010000 */
21508 #define USB_OTG_DIEPCTL_EONUM_DPID USB_OTG_DIEPCTL_EONUM_DPID_Msk /*!< Even/odd frame */
21509 #define USB_OTG_DIEPCTL_NAKSTS_Pos (17U)
21510 #define USB_OTG_DIEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DIEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
21511 #define USB_OTG_DIEPCTL_NAKSTS USB_OTG_DIEPCTL_NAKSTS_Msk /*!< NAK status */
21512
21513 #define USB_OTG_DIEPCTL_EPTYP_Pos (18U)
21514 #define USB_OTG_DIEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
21515 #define USB_OTG_DIEPCTL_EPTYP USB_OTG_DIEPCTL_EPTYP_Msk /*!< Endpoint type */
21516 #define USB_OTG_DIEPCTL_EPTYP_0 (0x1UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00040000 */
21517 #define USB_OTG_DIEPCTL_EPTYP_1 (0x2UL << USB_OTG_DIEPCTL_EPTYP_Pos) /*!< 0x00080000 */
21518 #define USB_OTG_DIEPCTL_STALL_Pos (21U)
21519 #define USB_OTG_DIEPCTL_STALL_Msk (0x1UL << USB_OTG_DIEPCTL_STALL_Pos) /*!< 0x00200000 */
21520 #define USB_OTG_DIEPCTL_STALL USB_OTG_DIEPCTL_STALL_Msk /*!< STALL handshake */
21521
21522 #define USB_OTG_DIEPCTL_TXFNUM_Pos (22U)
21523 #define USB_OTG_DIEPCTL_TXFNUM_Msk (0xFUL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x03C00000 */
21524 #define USB_OTG_DIEPCTL_TXFNUM USB_OTG_DIEPCTL_TXFNUM_Msk /*!< TxFIFO number */
21525 #define USB_OTG_DIEPCTL_TXFNUM_0 (0x1UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00400000 */
21526 #define USB_OTG_DIEPCTL_TXFNUM_1 (0x2UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x00800000 */
21527 #define USB_OTG_DIEPCTL_TXFNUM_2 (0x4UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x01000000 */
21528 #define USB_OTG_DIEPCTL_TXFNUM_3 (0x8UL << USB_OTG_DIEPCTL_TXFNUM_Pos) /*!< 0x02000000 */
21529 #define USB_OTG_DIEPCTL_CNAK_Pos (26U)
21530 #define USB_OTG_DIEPCTL_CNAK_Msk (0x1UL << USB_OTG_DIEPCTL_CNAK_Pos) /*!< 0x04000000 */
21531 #define USB_OTG_DIEPCTL_CNAK USB_OTG_DIEPCTL_CNAK_Msk /*!< Clear NAK */
21532 #define USB_OTG_DIEPCTL_SNAK_Pos (27U)
21533 #define USB_OTG_DIEPCTL_SNAK_Msk (0x1UL << USB_OTG_DIEPCTL_SNAK_Pos) /*!< 0x08000000 */
21534 #define USB_OTG_DIEPCTL_SNAK USB_OTG_DIEPCTL_SNAK_Msk /*!< Set NAK */
21535 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos (28U)
21536 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
21537 #define USB_OTG_DIEPCTL_SD0PID_SEVNFRM USB_OTG_DIEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
21538 #define USB_OTG_DIEPCTL_SODDFRM_Pos (29U)
21539 #define USB_OTG_DIEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DIEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
21540 #define USB_OTG_DIEPCTL_SODDFRM USB_OTG_DIEPCTL_SODDFRM_Msk /*!< Set odd frame */
21541 #define USB_OTG_DIEPCTL_EPDIS_Pos (30U)
21542 #define USB_OTG_DIEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DIEPCTL_EPDIS_Pos) /*!< 0x40000000 */
21543 #define USB_OTG_DIEPCTL_EPDIS USB_OTG_DIEPCTL_EPDIS_Msk /*!< Endpoint disable */
21544 #define USB_OTG_DIEPCTL_EPENA_Pos (31U)
21545 #define USB_OTG_DIEPCTL_EPENA_Msk (0x1UL << USB_OTG_DIEPCTL_EPENA_Pos) /*!< 0x80000000 */
21546 #define USB_OTG_DIEPCTL_EPENA USB_OTG_DIEPCTL_EPENA_Msk /*!< Endpoint enable */
21547
21548 /******************** Bit definition forUSB_OTG_HCCHAR register ********************/
21549 #define USB_OTG_HCCHAR_MPSIZ_Pos (0U)
21550 #define USB_OTG_HCCHAR_MPSIZ_Msk (0x7FFUL << USB_OTG_HCCHAR_MPSIZ_Pos) /*!< 0x000007FF */
21551 #define USB_OTG_HCCHAR_MPSIZ USB_OTG_HCCHAR_MPSIZ_Msk /*!< Maximum packet size */
21552
21553 #define USB_OTG_HCCHAR_EPNUM_Pos (11U)
21554 #define USB_OTG_HCCHAR_EPNUM_Msk (0xFUL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00007800 */
21555 #define USB_OTG_HCCHAR_EPNUM USB_OTG_HCCHAR_EPNUM_Msk /*!< Endpoint number */
21556 #define USB_OTG_HCCHAR_EPNUM_0 (0x1UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00000800 */
21557 #define USB_OTG_HCCHAR_EPNUM_1 (0x2UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00001000 */
21558 #define USB_OTG_HCCHAR_EPNUM_2 (0x4UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00002000 */
21559 #define USB_OTG_HCCHAR_EPNUM_3 (0x8UL << USB_OTG_HCCHAR_EPNUM_Pos) /*!< 0x00004000 */
21560 #define USB_OTG_HCCHAR_EPDIR_Pos (15U)
21561 #define USB_OTG_HCCHAR_EPDIR_Msk (0x1UL << USB_OTG_HCCHAR_EPDIR_Pos) /*!< 0x00008000 */
21562 #define USB_OTG_HCCHAR_EPDIR USB_OTG_HCCHAR_EPDIR_Msk /*!< Endpoint direction */
21563 #define USB_OTG_HCCHAR_LSDEV_Pos (17U)
21564 #define USB_OTG_HCCHAR_LSDEV_Msk (0x1UL << USB_OTG_HCCHAR_LSDEV_Pos) /*!< 0x00020000 */
21565 #define USB_OTG_HCCHAR_LSDEV USB_OTG_HCCHAR_LSDEV_Msk /*!< Low-speed device */
21566
21567 #define USB_OTG_HCCHAR_EPTYP_Pos (18U)
21568 #define USB_OTG_HCCHAR_EPTYP_Msk (0x3UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x000C0000 */
21569 #define USB_OTG_HCCHAR_EPTYP USB_OTG_HCCHAR_EPTYP_Msk /*!< Endpoint type */
21570 #define USB_OTG_HCCHAR_EPTYP_0 (0x1UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00040000 */
21571 #define USB_OTG_HCCHAR_EPTYP_1 (0x2UL << USB_OTG_HCCHAR_EPTYP_Pos) /*!< 0x00080000 */
21572
21573 #define USB_OTG_HCCHAR_MC_Pos (20U)
21574 #define USB_OTG_HCCHAR_MC_Msk (0x3UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00300000 */
21575 #define USB_OTG_HCCHAR_MC USB_OTG_HCCHAR_MC_Msk /*!< Multi Count (MC) / Error Count (EC) */
21576 #define USB_OTG_HCCHAR_MC_0 (0x1UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00100000 */
21577 #define USB_OTG_HCCHAR_MC_1 (0x2UL << USB_OTG_HCCHAR_MC_Pos) /*!< 0x00200000 */
21578
21579 #define USB_OTG_HCCHAR_DAD_Pos (22U)
21580 #define USB_OTG_HCCHAR_DAD_Msk (0x7FUL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x1FC00000 */
21581 #define USB_OTG_HCCHAR_DAD USB_OTG_HCCHAR_DAD_Msk /*!< Device address */
21582 #define USB_OTG_HCCHAR_DAD_0 (0x01UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00400000 */
21583 #define USB_OTG_HCCHAR_DAD_1 (0x02UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x00800000 */
21584 #define USB_OTG_HCCHAR_DAD_2 (0x04UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x01000000 */
21585 #define USB_OTG_HCCHAR_DAD_3 (0x08UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x02000000 */
21586 #define USB_OTG_HCCHAR_DAD_4 (0x10UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x04000000 */
21587 #define USB_OTG_HCCHAR_DAD_5 (0x20UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x08000000 */
21588 #define USB_OTG_HCCHAR_DAD_6 (0x40UL << USB_OTG_HCCHAR_DAD_Pos) /*!< 0x10000000 */
21589 #define USB_OTG_HCCHAR_ODDFRM_Pos (29U)
21590 #define USB_OTG_HCCHAR_ODDFRM_Msk (0x1UL << USB_OTG_HCCHAR_ODDFRM_Pos) /*!< 0x20000000 */
21591 #define USB_OTG_HCCHAR_ODDFRM USB_OTG_HCCHAR_ODDFRM_Msk /*!< Odd frame */
21592 #define USB_OTG_HCCHAR_CHDIS_Pos (30U)
21593 #define USB_OTG_HCCHAR_CHDIS_Msk (0x1UL << USB_OTG_HCCHAR_CHDIS_Pos) /*!< 0x40000000 */
21594 #define USB_OTG_HCCHAR_CHDIS USB_OTG_HCCHAR_CHDIS_Msk /*!< Channel disable */
21595 #define USB_OTG_HCCHAR_CHENA_Pos (31U)
21596 #define USB_OTG_HCCHAR_CHENA_Msk (0x1UL << USB_OTG_HCCHAR_CHENA_Pos) /*!< 0x80000000 */
21597 #define USB_OTG_HCCHAR_CHENA USB_OTG_HCCHAR_CHENA_Msk /*!< Channel enable */
21598
21599 /******************** Bit definition forUSB_OTG_HCSPLT register ********************/
21600
21601 #define USB_OTG_HCSPLT_PRTADDR_Pos (0U)
21602 #define USB_OTG_HCSPLT_PRTADDR_Msk (0x7FUL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x0000007F */
21603 #define USB_OTG_HCSPLT_PRTADDR USB_OTG_HCSPLT_PRTADDR_Msk /*!< Port address */
21604 #define USB_OTG_HCSPLT_PRTADDR_0 (0x01UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000001 */
21605 #define USB_OTG_HCSPLT_PRTADDR_1 (0x02UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000002 */
21606 #define USB_OTG_HCSPLT_PRTADDR_2 (0x04UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000004 */
21607 #define USB_OTG_HCSPLT_PRTADDR_3 (0x08UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000008 */
21608 #define USB_OTG_HCSPLT_PRTADDR_4 (0x10UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000010 */
21609 #define USB_OTG_HCSPLT_PRTADDR_5 (0x20UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000020 */
21610 #define USB_OTG_HCSPLT_PRTADDR_6 (0x40UL << USB_OTG_HCSPLT_PRTADDR_Pos) /*!< 0x00000040 */
21611
21612 #define USB_OTG_HCSPLT_HUBADDR_Pos (7U)
21613 #define USB_OTG_HCSPLT_HUBADDR_Msk (0x7FUL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00003F80 */
21614 #define USB_OTG_HCSPLT_HUBADDR USB_OTG_HCSPLT_HUBADDR_Msk /*!< Hub address */
21615 #define USB_OTG_HCSPLT_HUBADDR_0 (0x01UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000080 */
21616 #define USB_OTG_HCSPLT_HUBADDR_1 (0x02UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000100 */
21617 #define USB_OTG_HCSPLT_HUBADDR_2 (0x04UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000200 */
21618 #define USB_OTG_HCSPLT_HUBADDR_3 (0x08UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000400 */
21619 #define USB_OTG_HCSPLT_HUBADDR_4 (0x10UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00000800 */
21620 #define USB_OTG_HCSPLT_HUBADDR_5 (0x20UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00001000 */
21621 #define USB_OTG_HCSPLT_HUBADDR_6 (0x40UL << USB_OTG_HCSPLT_HUBADDR_Pos) /*!< 0x00002000 */
21622
21623 #define USB_OTG_HCSPLT_XACTPOS_Pos (14U)
21624 #define USB_OTG_HCSPLT_XACTPOS_Msk (0x3UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x0000C000 */
21625 #define USB_OTG_HCSPLT_XACTPOS USB_OTG_HCSPLT_XACTPOS_Msk /*!< XACTPOS */
21626 #define USB_OTG_HCSPLT_XACTPOS_0 (0x1UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00004000 */
21627 #define USB_OTG_HCSPLT_XACTPOS_1 (0x2UL << USB_OTG_HCSPLT_XACTPOS_Pos) /*!< 0x00008000 */
21628 #define USB_OTG_HCSPLT_COMPLSPLT_Pos (16U)
21629 #define USB_OTG_HCSPLT_COMPLSPLT_Msk (0x1UL << USB_OTG_HCSPLT_COMPLSPLT_Pos) /*!< 0x00010000 */
21630 #define USB_OTG_HCSPLT_COMPLSPLT USB_OTG_HCSPLT_COMPLSPLT_Msk /*!< Do complete split */
21631 #define USB_OTG_HCSPLT_SPLITEN_Pos (31U)
21632 #define USB_OTG_HCSPLT_SPLITEN_Msk (0x1UL << USB_OTG_HCSPLT_SPLITEN_Pos) /*!< 0x80000000 */
21633 #define USB_OTG_HCSPLT_SPLITEN USB_OTG_HCSPLT_SPLITEN_Msk /*!< Split enable */
21634
21635 /******************** Bit definition forUSB_OTG_HCINT register ********************/
21636 #define USB_OTG_HCINT_XFRC_Pos (0U)
21637 #define USB_OTG_HCINT_XFRC_Msk (0x1UL << USB_OTG_HCINT_XFRC_Pos) /*!< 0x00000001 */
21638 #define USB_OTG_HCINT_XFRC USB_OTG_HCINT_XFRC_Msk /*!< Transfer completed */
21639 #define USB_OTG_HCINT_CHH_Pos (1U)
21640 #define USB_OTG_HCINT_CHH_Msk (0x1UL << USB_OTG_HCINT_CHH_Pos) /*!< 0x00000002 */
21641 #define USB_OTG_HCINT_CHH USB_OTG_HCINT_CHH_Msk /*!< Channel halted */
21642 #define USB_OTG_HCINT_AHBERR_Pos (2U)
21643 #define USB_OTG_HCINT_AHBERR_Msk (0x1UL << USB_OTG_HCINT_AHBERR_Pos) /*!< 0x00000004 */
21644 #define USB_OTG_HCINT_AHBERR USB_OTG_HCINT_AHBERR_Msk /*!< AHB error */
21645 #define USB_OTG_HCINT_STALL_Pos (3U)
21646 #define USB_OTG_HCINT_STALL_Msk (0x1UL << USB_OTG_HCINT_STALL_Pos) /*!< 0x00000008 */
21647 #define USB_OTG_HCINT_STALL USB_OTG_HCINT_STALL_Msk /*!< STALL response received interrupt */
21648 #define USB_OTG_HCINT_NAK_Pos (4U)
21649 #define USB_OTG_HCINT_NAK_Msk (0x1UL << USB_OTG_HCINT_NAK_Pos) /*!< 0x00000010 */
21650 #define USB_OTG_HCINT_NAK USB_OTG_HCINT_NAK_Msk /*!< NAK response received interrupt */
21651 #define USB_OTG_HCINT_ACK_Pos (5U)
21652 #define USB_OTG_HCINT_ACK_Msk (0x1UL << USB_OTG_HCINT_ACK_Pos) /*!< 0x00000020 */
21653 #define USB_OTG_HCINT_ACK USB_OTG_HCINT_ACK_Msk /*!< ACK response received/transmitted interrupt */
21654 #define USB_OTG_HCINT_NYET_Pos (6U)
21655 #define USB_OTG_HCINT_NYET_Msk (0x1UL << USB_OTG_HCINT_NYET_Pos) /*!< 0x00000040 */
21656 #define USB_OTG_HCINT_NYET USB_OTG_HCINT_NYET_Msk /*!< Response received interrupt */
21657 #define USB_OTG_HCINT_TXERR_Pos (7U)
21658 #define USB_OTG_HCINT_TXERR_Msk (0x1UL << USB_OTG_HCINT_TXERR_Pos) /*!< 0x00000080 */
21659 #define USB_OTG_HCINT_TXERR USB_OTG_HCINT_TXERR_Msk /*!< Transaction error */
21660 #define USB_OTG_HCINT_BBERR_Pos (8U)
21661 #define USB_OTG_HCINT_BBERR_Msk (0x1UL << USB_OTG_HCINT_BBERR_Pos) /*!< 0x00000100 */
21662 #define USB_OTG_HCINT_BBERR USB_OTG_HCINT_BBERR_Msk /*!< Babble error */
21663 #define USB_OTG_HCINT_FRMOR_Pos (9U)
21664 #define USB_OTG_HCINT_FRMOR_Msk (0x1UL << USB_OTG_HCINT_FRMOR_Pos) /*!< 0x00000200 */
21665 #define USB_OTG_HCINT_FRMOR USB_OTG_HCINT_FRMOR_Msk /*!< Frame overrun */
21666 #define USB_OTG_HCINT_DTERR_Pos (10U)
21667 #define USB_OTG_HCINT_DTERR_Msk (0x1UL << USB_OTG_HCINT_DTERR_Pos) /*!< 0x00000400 */
21668 #define USB_OTG_HCINT_DTERR USB_OTG_HCINT_DTERR_Msk /*!< Data toggle error */
21669
21670 /******************** Bit definition forUSB_OTG_DIEPINT register ********************/
21671 #define USB_OTG_DIEPINT_XFRC_Pos (0U)
21672 #define USB_OTG_DIEPINT_XFRC_Msk (0x1UL << USB_OTG_DIEPINT_XFRC_Pos) /*!< 0x00000001 */
21673 #define USB_OTG_DIEPINT_XFRC USB_OTG_DIEPINT_XFRC_Msk /*!< Transfer completed interrupt */
21674 #define USB_OTG_DIEPINT_EPDISD_Pos (1U)
21675 #define USB_OTG_DIEPINT_EPDISD_Msk (0x1UL << USB_OTG_DIEPINT_EPDISD_Pos) /*!< 0x00000002 */
21676 #define USB_OTG_DIEPINT_EPDISD USB_OTG_DIEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
21677 #define USB_OTG_DIEPINT_AHBERR_Pos (2U)
21678 #define USB_OTG_DIEPINT_AHBERR_Msk (0x1UL << USB_OTG_DIEPINT_AHBERR_Pos) /*!< 0x00000004 */
21679 #define USB_OTG_DIEPINT_AHBERR USB_OTG_DIEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an IN transaction */
21680 #define USB_OTG_DIEPINT_TOC_Pos (3U)
21681 #define USB_OTG_DIEPINT_TOC_Msk (0x1UL << USB_OTG_DIEPINT_TOC_Pos) /*!< 0x00000008 */
21682 #define USB_OTG_DIEPINT_TOC USB_OTG_DIEPINT_TOC_Msk /*!< Timeout condition */
21683 #define USB_OTG_DIEPINT_ITTXFE_Pos (4U)
21684 #define USB_OTG_DIEPINT_ITTXFE_Msk (0x1UL << USB_OTG_DIEPINT_ITTXFE_Pos) /*!< 0x00000010 */
21685 #define USB_OTG_DIEPINT_ITTXFE USB_OTG_DIEPINT_ITTXFE_Msk /*!< IN token received when TxFIFO is empty */
21686 #define USB_OTG_DIEPINT_INEPNM_Pos (5U)
21687 #define USB_OTG_DIEPINT_INEPNM_Msk (0x1UL << USB_OTG_DIEPINT_INEPNM_Pos) /*!< 0x00000020 */
21688 #define USB_OTG_DIEPINT_INEPNM USB_OTG_DIEPINT_INEPNM_Msk /*!< IN token received with EP mismatch */
21689 #define USB_OTG_DIEPINT_INEPNE_Pos (6U)
21690 #define USB_OTG_DIEPINT_INEPNE_Msk (0x1UL << USB_OTG_DIEPINT_INEPNE_Pos) /*!< 0x00000040 */
21691 #define USB_OTG_DIEPINT_INEPNE USB_OTG_DIEPINT_INEPNE_Msk /*!< IN endpoint NAK effective */
21692 #define USB_OTG_DIEPINT_TXFE_Pos (7U)
21693 #define USB_OTG_DIEPINT_TXFE_Msk (0x1UL << USB_OTG_DIEPINT_TXFE_Pos) /*!< 0x00000080 */
21694 #define USB_OTG_DIEPINT_TXFE USB_OTG_DIEPINT_TXFE_Msk /*!< Transmit FIFO empty */
21695 #define USB_OTG_DIEPINT_TXFIFOUDRN_Pos (8U)
21696 #define USB_OTG_DIEPINT_TXFIFOUDRN_Msk (0x1UL << USB_OTG_DIEPINT_TXFIFOUDRN_Pos) /*!< 0x00000100 */
21697 #define USB_OTG_DIEPINT_TXFIFOUDRN USB_OTG_DIEPINT_TXFIFOUDRN_Msk /*!< Transmit Fifo Underrun */
21698 #define USB_OTG_DIEPINT_BNA_Pos (9U)
21699 #define USB_OTG_DIEPINT_BNA_Msk (0x1UL << USB_OTG_DIEPINT_BNA_Pos) /*!< 0x00000200 */
21700 #define USB_OTG_DIEPINT_BNA USB_OTG_DIEPINT_BNA_Msk /*!< Buffer not available interrupt */
21701 #define USB_OTG_DIEPINT_PKTDRPSTS_Pos (11U)
21702 #define USB_OTG_DIEPINT_PKTDRPSTS_Msk (0x1UL << USB_OTG_DIEPINT_PKTDRPSTS_Pos) /*!< 0x00000800 */
21703 #define USB_OTG_DIEPINT_PKTDRPSTS USB_OTG_DIEPINT_PKTDRPSTS_Msk /*!< Packet dropped status */
21704 #define USB_OTG_DIEPINT_BERR_Pos (12U)
21705 #define USB_OTG_DIEPINT_BERR_Msk (0x1UL << USB_OTG_DIEPINT_BERR_Pos) /*!< 0x00001000 */
21706 #define USB_OTG_DIEPINT_BERR USB_OTG_DIEPINT_BERR_Msk /*!< Babble error interrupt */
21707 #define USB_OTG_DIEPINT_NAK_Pos (13U)
21708 #define USB_OTG_DIEPINT_NAK_Msk (0x1UL << USB_OTG_DIEPINT_NAK_Pos) /*!< 0x00002000 */
21709 #define USB_OTG_DIEPINT_NAK USB_OTG_DIEPINT_NAK_Msk /*!< NAK interrupt */
21710
21711 /******************** Bit definition forUSB_OTG_HCINTMSK register ********************/
21712 #define USB_OTG_HCINTMSK_XFRCM_Pos (0U)
21713 #define USB_OTG_HCINTMSK_XFRCM_Msk (0x1UL << USB_OTG_HCINTMSK_XFRCM_Pos) /*!< 0x00000001 */
21714 #define USB_OTG_HCINTMSK_XFRCM USB_OTG_HCINTMSK_XFRCM_Msk /*!< Transfer completed mask */
21715 #define USB_OTG_HCINTMSK_CHHM_Pos (1U)
21716 #define USB_OTG_HCINTMSK_CHHM_Msk (0x1UL << USB_OTG_HCINTMSK_CHHM_Pos) /*!< 0x00000002 */
21717 #define USB_OTG_HCINTMSK_CHHM USB_OTG_HCINTMSK_CHHM_Msk /*!< Channel halted mask */
21718 #define USB_OTG_HCINTMSK_AHBERR_Pos (2U)
21719 #define USB_OTG_HCINTMSK_AHBERR_Msk (0x1UL << USB_OTG_HCINTMSK_AHBERR_Pos) /*!< 0x00000004 */
21720 #define USB_OTG_HCINTMSK_AHBERR USB_OTG_HCINTMSK_AHBERR_Msk /*!< AHB error */
21721 #define USB_OTG_HCINTMSK_STALLM_Pos (3U)
21722 #define USB_OTG_HCINTMSK_STALLM_Msk (0x1UL << USB_OTG_HCINTMSK_STALLM_Pos) /*!< 0x00000008 */
21723 #define USB_OTG_HCINTMSK_STALLM USB_OTG_HCINTMSK_STALLM_Msk /*!< STALL response received interrupt mask */
21724 #define USB_OTG_HCINTMSK_NAKM_Pos (4U)
21725 #define USB_OTG_HCINTMSK_NAKM_Msk (0x1UL << USB_OTG_HCINTMSK_NAKM_Pos) /*!< 0x00000010 */
21726 #define USB_OTG_HCINTMSK_NAKM USB_OTG_HCINTMSK_NAKM_Msk /*!< NAK response received interrupt mask */
21727 #define USB_OTG_HCINTMSK_ACKM_Pos (5U)
21728 #define USB_OTG_HCINTMSK_ACKM_Msk (0x1UL << USB_OTG_HCINTMSK_ACKM_Pos) /*!< 0x00000020 */
21729 #define USB_OTG_HCINTMSK_ACKM USB_OTG_HCINTMSK_ACKM_Msk /*!< ACK response received/transmitted interrupt mask */
21730 #define USB_OTG_HCINTMSK_NYET_Pos (6U)
21731 #define USB_OTG_HCINTMSK_NYET_Msk (0x1UL << USB_OTG_HCINTMSK_NYET_Pos) /*!< 0x00000040 */
21732 #define USB_OTG_HCINTMSK_NYET USB_OTG_HCINTMSK_NYET_Msk /*!< response received interrupt mask */
21733 #define USB_OTG_HCINTMSK_TXERRM_Pos (7U)
21734 #define USB_OTG_HCINTMSK_TXERRM_Msk (0x1UL << USB_OTG_HCINTMSK_TXERRM_Pos) /*!< 0x00000080 */
21735 #define USB_OTG_HCINTMSK_TXERRM USB_OTG_HCINTMSK_TXERRM_Msk /*!< Transaction error mask */
21736 #define USB_OTG_HCINTMSK_BBERRM_Pos (8U)
21737 #define USB_OTG_HCINTMSK_BBERRM_Msk (0x1UL << USB_OTG_HCINTMSK_BBERRM_Pos) /*!< 0x00000100 */
21738 #define USB_OTG_HCINTMSK_BBERRM USB_OTG_HCINTMSK_BBERRM_Msk /*!< Babble error mask */
21739 #define USB_OTG_HCINTMSK_FRMORM_Pos (9U)
21740 #define USB_OTG_HCINTMSK_FRMORM_Msk (0x1UL << USB_OTG_HCINTMSK_FRMORM_Pos) /*!< 0x00000200 */
21741 #define USB_OTG_HCINTMSK_FRMORM USB_OTG_HCINTMSK_FRMORM_Msk /*!< Frame overrun mask */
21742 #define USB_OTG_HCINTMSK_DTERRM_Pos (10U)
21743 #define USB_OTG_HCINTMSK_DTERRM_Msk (0x1UL << USB_OTG_HCINTMSK_DTERRM_Pos) /*!< 0x00000400 */
21744 #define USB_OTG_HCINTMSK_DTERRM USB_OTG_HCINTMSK_DTERRM_Msk /*!< Data toggle error mask */
21745
21746 /******************** Bit definition for USB_OTG_DIEPTSIZ register ********************/
21747
21748 #define USB_OTG_DIEPTSIZ_XFRSIZ_Pos (0U)
21749 #define USB_OTG_DIEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DIEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21750 #define USB_OTG_DIEPTSIZ_XFRSIZ USB_OTG_DIEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
21751 #define USB_OTG_DIEPTSIZ_PKTCNT_Pos (19U)
21752 #define USB_OTG_DIEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DIEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21753 #define USB_OTG_DIEPTSIZ_PKTCNT USB_OTG_DIEPTSIZ_PKTCNT_Msk /*!< Packet count */
21754 #define USB_OTG_DIEPTSIZ_MULCNT_Pos (29U)
21755 #define USB_OTG_DIEPTSIZ_MULCNT_Msk (0x3UL << USB_OTG_DIEPTSIZ_MULCNT_Pos) /*!< 0x60000000 */
21756 #define USB_OTG_DIEPTSIZ_MULCNT USB_OTG_DIEPTSIZ_MULCNT_Msk /*!< Packet count */
21757 /******************** Bit definition forUSB_OTG_HCTSIZ register ********************/
21758 #define USB_OTG_HCTSIZ_XFRSIZ_Pos (0U)
21759 #define USB_OTG_HCTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_HCTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21760 #define USB_OTG_HCTSIZ_XFRSIZ USB_OTG_HCTSIZ_XFRSIZ_Msk /*!< Transfer size */
21761 #define USB_OTG_HCTSIZ_PKTCNT_Pos (19U)
21762 #define USB_OTG_HCTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_HCTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21763 #define USB_OTG_HCTSIZ_PKTCNT USB_OTG_HCTSIZ_PKTCNT_Msk /*!< Packet count */
21764 #define USB_OTG_HCTSIZ_DOPING_Pos (31U)
21765 #define USB_OTG_HCTSIZ_DOPING_Msk (0x1UL << USB_OTG_HCTSIZ_DOPING_Pos) /*!< 0x80000000 */
21766 #define USB_OTG_HCTSIZ_DOPING USB_OTG_HCTSIZ_DOPING_Msk /*!< Do PING */
21767 #define USB_OTG_HCTSIZ_DPID_Pos (29U)
21768 #define USB_OTG_HCTSIZ_DPID_Msk (0x3UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x60000000 */
21769 #define USB_OTG_HCTSIZ_DPID USB_OTG_HCTSIZ_DPID_Msk /*!< Data PID */
21770 #define USB_OTG_HCTSIZ_DPID_0 (0x1UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x20000000 */
21771 #define USB_OTG_HCTSIZ_DPID_1 (0x2UL << USB_OTG_HCTSIZ_DPID_Pos) /*!< 0x40000000 */
21772
21773 /******************** Bit definition forUSB_OTG_DIEPDMA register ********************/
21774 #define USB_OTG_DIEPDMA_DMAADDR_Pos (0U)
21775 #define USB_OTG_DIEPDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_DIEPDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
21776 #define USB_OTG_DIEPDMA_DMAADDR USB_OTG_DIEPDMA_DMAADDR_Msk /*!< DMA address */
21777
21778 /******************** Bit definition forUSB_OTG_HCDMA register ********************/
21779 #define USB_OTG_HCDMA_DMAADDR_Pos (0U)
21780 #define USB_OTG_HCDMA_DMAADDR_Msk (0xFFFFFFFFUL << USB_OTG_HCDMA_DMAADDR_Pos) /*!< 0xFFFFFFFF */
21781 #define USB_OTG_HCDMA_DMAADDR USB_OTG_HCDMA_DMAADDR_Msk /*!< DMA address */
21782
21783 /******************** Bit definition forUSB_OTG_DTXFSTS register ********************/
21784 #define USB_OTG_DTXFSTS_INEPTFSAV_Pos (0U)
21785 #define USB_OTG_DTXFSTS_INEPTFSAV_Msk (0xFFFFUL << USB_OTG_DTXFSTS_INEPTFSAV_Pos) /*!< 0x0000FFFF */
21786 #define USB_OTG_DTXFSTS_INEPTFSAV USB_OTG_DTXFSTS_INEPTFSAV_Msk /*!< IN endpoint TxFIFO space available */
21787
21788 /******************** Bit definition forUSB_OTG_DIEPTXF register ********************/
21789 #define USB_OTG_DIEPTXF_INEPTXSA_Pos (0U)
21790 #define USB_OTG_DIEPTXF_INEPTXSA_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXSA_Pos) /*!< 0x0000FFFF */
21791 #define USB_OTG_DIEPTXF_INEPTXSA USB_OTG_DIEPTXF_INEPTXSA_Msk /*!< IN endpoint FIFOx transmit RAM start address */
21792 #define USB_OTG_DIEPTXF_INEPTXFD_Pos (16U)
21793 #define USB_OTG_DIEPTXF_INEPTXFD_Msk (0xFFFFUL << USB_OTG_DIEPTXF_INEPTXFD_Pos) /*!< 0xFFFF0000 */
21794 #define USB_OTG_DIEPTXF_INEPTXFD USB_OTG_DIEPTXF_INEPTXFD_Msk /*!< IN endpoint TxFIFO depth */
21795
21796 /******************** Bit definition forUSB_OTG_DOEPCTL register ********************/
21797
21798 #define USB_OTG_DOEPCTL_MPSIZ_Pos (0U)
21799 #define USB_OTG_DOEPCTL_MPSIZ_Msk (0x7FFUL << USB_OTG_DOEPCTL_MPSIZ_Pos) /*!< 0x000007FF */
21800 #define USB_OTG_DOEPCTL_MPSIZ USB_OTG_DOEPCTL_MPSIZ_Msk /*!< Maximum packet size */ /*!<Bit 1 */
21801 #define USB_OTG_DOEPCTL_USBAEP_Pos (15U)
21802 #define USB_OTG_DOEPCTL_USBAEP_Msk (0x1UL << USB_OTG_DOEPCTL_USBAEP_Pos) /*!< 0x00008000 */
21803 #define USB_OTG_DOEPCTL_USBAEP USB_OTG_DOEPCTL_USBAEP_Msk /*!< USB active endpoint */
21804 #define USB_OTG_DOEPCTL_NAKSTS_Pos (17U)
21805 #define USB_OTG_DOEPCTL_NAKSTS_Msk (0x1UL << USB_OTG_DOEPCTL_NAKSTS_Pos) /*!< 0x00020000 */
21806 #define USB_OTG_DOEPCTL_NAKSTS USB_OTG_DOEPCTL_NAKSTS_Msk /*!< NAK status */
21807 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos (28U)
21808 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Pos) /*!< 0x10000000 */
21809 #define USB_OTG_DOEPCTL_SD0PID_SEVNFRM USB_OTG_DOEPCTL_SD0PID_SEVNFRM_Msk /*!< Set DATA0 PID */
21810 #define USB_OTG_DOEPCTL_SODDFRM_Pos (29U)
21811 #define USB_OTG_DOEPCTL_SODDFRM_Msk (0x1UL << USB_OTG_DOEPCTL_SODDFRM_Pos) /*!< 0x20000000 */
21812 #define USB_OTG_DOEPCTL_SODDFRM USB_OTG_DOEPCTL_SODDFRM_Msk /*!< Set odd frame */
21813 #define USB_OTG_DOEPCTL_EPTYP_Pos (18U)
21814 #define USB_OTG_DOEPCTL_EPTYP_Msk (0x3UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x000C0000 */
21815 #define USB_OTG_DOEPCTL_EPTYP USB_OTG_DOEPCTL_EPTYP_Msk /*!< Endpoint type */
21816 #define USB_OTG_DOEPCTL_EPTYP_0 (0x1UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00040000 */
21817 #define USB_OTG_DOEPCTL_EPTYP_1 (0x2UL << USB_OTG_DOEPCTL_EPTYP_Pos) /*!< 0x00080000 */
21818 #define USB_OTG_DOEPCTL_SNPM_Pos (20U)
21819 #define USB_OTG_DOEPCTL_SNPM_Msk (0x1UL << USB_OTG_DOEPCTL_SNPM_Pos) /*!< 0x00100000 */
21820 #define USB_OTG_DOEPCTL_SNPM USB_OTG_DOEPCTL_SNPM_Msk /*!< Snoop mode */
21821 #define USB_OTG_DOEPCTL_STALL_Pos (21U)
21822 #define USB_OTG_DOEPCTL_STALL_Msk (0x1UL << USB_OTG_DOEPCTL_STALL_Pos) /*!< 0x00200000 */
21823 #define USB_OTG_DOEPCTL_STALL USB_OTG_DOEPCTL_STALL_Msk /*!< STALL handshake */
21824 #define USB_OTG_DOEPCTL_CNAK_Pos (26U)
21825 #define USB_OTG_DOEPCTL_CNAK_Msk (0x1UL << USB_OTG_DOEPCTL_CNAK_Pos) /*!< 0x04000000 */
21826 #define USB_OTG_DOEPCTL_CNAK USB_OTG_DOEPCTL_CNAK_Msk /*!< Clear NAK */
21827 #define USB_OTG_DOEPCTL_SNAK_Pos (27U)
21828 #define USB_OTG_DOEPCTL_SNAK_Msk (0x1UL << USB_OTG_DOEPCTL_SNAK_Pos) /*!< 0x08000000 */
21829 #define USB_OTG_DOEPCTL_SNAK USB_OTG_DOEPCTL_SNAK_Msk /*!< Set NAK */
21830 #define USB_OTG_DOEPCTL_EPDIS_Pos (30U)
21831 #define USB_OTG_DOEPCTL_EPDIS_Msk (0x1UL << USB_OTG_DOEPCTL_EPDIS_Pos) /*!< 0x40000000 */
21832 #define USB_OTG_DOEPCTL_EPDIS USB_OTG_DOEPCTL_EPDIS_Msk /*!< Endpoint disable */
21833 #define USB_OTG_DOEPCTL_EPENA_Pos (31U)
21834 #define USB_OTG_DOEPCTL_EPENA_Msk (0x1UL << USB_OTG_DOEPCTL_EPENA_Pos) /*!< 0x80000000 */
21835 #define USB_OTG_DOEPCTL_EPENA USB_OTG_DOEPCTL_EPENA_Msk /*!< Endpoint enable */
21836
21837 /******************** Bit definition forUSB_OTG_DOEPINT register ********************/
21838 #define USB_OTG_DOEPINT_XFRC_Pos (0U)
21839 #define USB_OTG_DOEPINT_XFRC_Msk (0x1UL << USB_OTG_DOEPINT_XFRC_Pos) /*!< 0x00000001 */
21840 #define USB_OTG_DOEPINT_XFRC USB_OTG_DOEPINT_XFRC_Msk /*!< Transfer completed interrupt */
21841 #define USB_OTG_DOEPINT_EPDISD_Pos (1U)
21842 #define USB_OTG_DOEPINT_EPDISD_Msk (0x1UL << USB_OTG_DOEPINT_EPDISD_Pos) /*!< 0x00000002 */
21843 #define USB_OTG_DOEPINT_EPDISD USB_OTG_DOEPINT_EPDISD_Msk /*!< Endpoint disabled interrupt */
21844 #define USB_OTG_DOEPINT_AHBERR_Pos (2U)
21845 #define USB_OTG_DOEPINT_AHBERR_Msk (0x1UL << USB_OTG_DOEPINT_AHBERR_Pos) /*!< 0x00000004 */
21846 #define USB_OTG_DOEPINT_AHBERR USB_OTG_DOEPINT_AHBERR_Msk /*!< AHB Error (AHBErr) during an OUT transaction */
21847 #define USB_OTG_DOEPINT_STUP_Pos (3U)
21848 #define USB_OTG_DOEPINT_STUP_Msk (0x1UL << USB_OTG_DOEPINT_STUP_Pos) /*!< 0x00000008 */
21849 #define USB_OTG_DOEPINT_STUP USB_OTG_DOEPINT_STUP_Msk /*!< SETUP phase done */
21850 #define USB_OTG_DOEPINT_OTEPDIS_Pos (4U)
21851 #define USB_OTG_DOEPINT_OTEPDIS_Msk (0x1UL << USB_OTG_DOEPINT_OTEPDIS_Pos) /*!< 0x00000010 */
21852 #define USB_OTG_DOEPINT_OTEPDIS USB_OTG_DOEPINT_OTEPDIS_Msk /*!< OUT token received when endpoint disabled */
21853 #define USB_OTG_DOEPINT_OTEPSPR_Pos (5U)
21854 #define USB_OTG_DOEPINT_OTEPSPR_Msk (0x1UL << USB_OTG_DOEPINT_OTEPSPR_Pos) /*!< 0x00000020 */
21855 #define USB_OTG_DOEPINT_OTEPSPR USB_OTG_DOEPINT_OTEPSPR_Msk /*!< OUT Status Phase Received interrupt */
21856 #define USB_OTG_DOEPINT_B2BSTUP_Pos (6U)
21857 #define USB_OTG_DOEPINT_B2BSTUP_Msk (0x1UL << USB_OTG_DOEPINT_B2BSTUP_Pos) /*!< 0x00000040 */
21858 #define USB_OTG_DOEPINT_B2BSTUP USB_OTG_DOEPINT_B2BSTUP_Msk /*!< Back-to-back SETUP packets received */
21859 #define USB_OTG_DOEPINT_OUTPKTERR_Pos (8U)
21860 #define USB_OTG_DOEPINT_OUTPKTERR_Msk (0x1UL << USB_OTG_DOEPINT_OUTPKTERR_Pos) /*!< 0x00000100 */
21861 #define USB_OTG_DOEPINT_OUTPKTERR USB_OTG_DOEPINT_OUTPKTERR_Msk /*!< OUT packet error */
21862 #define USB_OTG_DOEPINT_BNA_Pos (9U)
21863 #define USB_OTG_DOEPINT_BNA_Msk (0x1UL << USB_OTG_DOEPINT_BNA_Pos) /*!< 0x00000200 */
21864 #define USB_OTG_DOEPINT_BNA USB_OTG_DOEPINT_BNA_Msk /*!< Buffer not available interrupt */
21865 #define USB_OTG_DOEPINT_BERR_Pos (12U)
21866 #define USB_OTG_DOEPINT_BERR_Msk (0x1UL << USB_OTG_DOEPINT_BERR_Pos) /*!< 0x00001000 */
21867 #define USB_OTG_DOEPINT_BERR USB_OTG_DOEPINT_BERR_Msk /*!< Babble error interrupt */
21868 #define USB_OTG_DOEPINT_NAK_Pos (13U)
21869 #define USB_OTG_DOEPINT_NAK_Msk (0x1UL << USB_OTG_DOEPINT_NAK_Pos) /*!< 0x00002000 */
21870 #define USB_OTG_DOEPINT_NAK USB_OTG_DOEPINT_NAK_Msk /*!< NAK Packet is transmitted by the device */
21871 #define USB_OTG_DOEPINT_NYET_Pos (14U)
21872 #define USB_OTG_DOEPINT_NYET_Msk (0x1UL << USB_OTG_DOEPINT_NYET_Pos) /*!< 0x00004000 */
21873 #define USB_OTG_DOEPINT_NYET USB_OTG_DOEPINT_NYET_Msk /*!< NYET interrupt */
21874 #define USB_OTG_DOEPINT_STPKTRX_Pos (15U)
21875 #define USB_OTG_DOEPINT_STPKTRX_Msk (0x1UL << USB_OTG_DOEPINT_STPKTRX_Pos) /*!< 0x00008000 */
21876 #define USB_OTG_DOEPINT_STPKTRX USB_OTG_DOEPINT_STPKTRX_Msk /*!< Setup Packet Received */
21877
21878 /******************** Bit definition forUSB_OTG_DOEPTSIZ register ********************/
21879
21880 #define USB_OTG_DOEPTSIZ_XFRSIZ_Pos (0U)
21881 #define USB_OTG_DOEPTSIZ_XFRSIZ_Msk (0x7FFFFUL << USB_OTG_DOEPTSIZ_XFRSIZ_Pos) /*!< 0x0007FFFF */
21882 #define USB_OTG_DOEPTSIZ_XFRSIZ USB_OTG_DOEPTSIZ_XFRSIZ_Msk /*!< Transfer size */
21883 #define USB_OTG_DOEPTSIZ_PKTCNT_Pos (19U)
21884 #define USB_OTG_DOEPTSIZ_PKTCNT_Msk (0x3FFUL << USB_OTG_DOEPTSIZ_PKTCNT_Pos) /*!< 0x1FF80000 */
21885 #define USB_OTG_DOEPTSIZ_PKTCNT USB_OTG_DOEPTSIZ_PKTCNT_Msk /*!< Packet count */
21886
21887 #define USB_OTG_DOEPTSIZ_STUPCNT_Pos (29U)
21888 #define USB_OTG_DOEPTSIZ_STUPCNT_Msk (0x3UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x60000000 */
21889 #define USB_OTG_DOEPTSIZ_STUPCNT USB_OTG_DOEPTSIZ_STUPCNT_Msk /*!< SETUP packet count */
21890 #define USB_OTG_DOEPTSIZ_STUPCNT_0 (0x1UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x20000000 */
21891 #define USB_OTG_DOEPTSIZ_STUPCNT_1 (0x2UL << USB_OTG_DOEPTSIZ_STUPCNT_Pos) /*!< 0x40000000 */
21892
21893 /******************** Bit definition for PCGCCTL register ********************/
21894 #define USB_OTG_PCGCCTL_STOPCLK_Pos (0U)
21895 #define USB_OTG_PCGCCTL_STOPCLK_Msk (0x1UL << USB_OTG_PCGCCTL_STOPCLK_Pos) /*!< 0x00000001 */
21896 #define USB_OTG_PCGCCTL_STOPCLK USB_OTG_PCGCCTL_STOPCLK_Msk /*!< SETUP packet count */
21897 #define USB_OTG_PCGCCTL_GATECLK_Pos (1U)
21898 #define USB_OTG_PCGCCTL_GATECLK_Msk (0x1UL << USB_OTG_PCGCCTL_GATECLK_Pos) /*!< 0x00000002 */
21899 #define USB_OTG_PCGCCTL_GATECLK USB_OTG_PCGCCTL_GATECLK_Msk /*!<Bit 0 */
21900 #define USB_OTG_PCGCCTL_PHYSUSP_Pos (4U)
21901 #define USB_OTG_PCGCCTL_PHYSUSP_Msk (0x1UL << USB_OTG_PCGCCTL_PHYSUSP_Pos) /*!< 0x00000010 */
21902 #define USB_OTG_PCGCCTL_PHYSUSP USB_OTG_PCGCCTL_PHYSUSP_Msk /*!<Bit 1 */
21903
21904 /**
21905 * @}
21906 */
21907
21908 /**
21909 * @}
21910 */
21911
21912 /** @addtogroup Exported_macros
21913 * @{
21914 */
21915
21916 /******************************* ADC Instances ********************************/
21917 #define IS_ADC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == ADC1) || \
21918 ((INSTANCE) == ADC2))
21919
21920 #define IS_ADC_MULTIMODE_MASTER_INSTANCE(INSTANCE) ((INSTANCE) == ADC1)
21921
21922 #define IS_ADC_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == ADC12_COMMON)
21923
21924 /******************************** COMP Instances ******************************/
21925 #define IS_COMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == COMP1) || \
21926 ((INSTANCE) == COMP2))
21927
21928 #define IS_COMP_COMMON_INSTANCE(INSTANCE) ((INSTANCE) == COMP12_COMMON)
21929 /******************** COMP Instances with window mode capability **************/
21930 #define IS_COMP_WINDOWMODE_INSTANCE(INSTANCE) ((INSTANCE) == COMP2)
21931
21932 /******************************** DTS Instances ******************************/
21933 #define IS_DTS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == DTS)
21934
21935 /******************************* CRC Instances ********************************/
21936 #define IS_CRC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == CRC)
21937
21938 /******************************* DAC Instances ********************************/
21939 #define IS_DAC_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DAC1)|| \
21940 ((INSTANCE) == DAC2))
21941 /******************************* DCMI Instances *******************************/
21942 #define IS_DCMI_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DCMI)
21943
21944 /******************************* DELAYBLOCK Instances *******************************/
21945 #define IS_DLYB_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DLYB_SDMMC1) || \
21946 ((INSTANCE) == DLYB_SDMMC2) || \
21947 ((INSTANCE) == DLYB_OCTOSPI1) || \
21948 ((INSTANCE) == DLYB_OCTOSPI2) )
21949 /****************************** DFSDM Instances *******************************/
21950 #define IS_DFSDM_FILTER_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Filter0) || \
21951 ((INSTANCE) == DFSDM1_Filter1) || \
21952 ((INSTANCE) == DFSDM1_Filter2) || \
21953 ((INSTANCE) == DFSDM1_Filter3) || \
21954 ((INSTANCE) == DFSDM1_Filter4) || \
21955 ((INSTANCE) == DFSDM1_Filter5) || \
21956 ((INSTANCE) == DFSDM1_Filter6) || \
21957 ((INSTANCE) == DFSDM1_Filter7) || \
21958 ((INSTANCE) == DFSDM2_Filter0))
21959 #define IS_DFSDM_CHANNEL_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DFSDM1_Channel0) || \
21960 ((INSTANCE) == DFSDM1_Channel1) || \
21961 ((INSTANCE) == DFSDM1_Channel2) || \
21962 ((INSTANCE) == DFSDM1_Channel3) || \
21963 ((INSTANCE) == DFSDM1_Channel4) || \
21964 ((INSTANCE) == DFSDM1_Channel5) || \
21965 ((INSTANCE) == DFSDM1_Channel6) || \
21966 ((INSTANCE) == DFSDM1_Channel7) || \
21967 ((INSTANCE) == DFSDM2_Channel0) || \
21968 ((INSTANCE) == DFSDM2_Channel1))
21969 /****************************** RAMECC Instances ******************************/
21970 #define IS_RAMECC_MONITOR_ALL_INSTANCE(INSTANCE) (((INSTANCE) == RAMECC_Monitor1) || \
21971 ((INSTANCE) == RAMECC_Monitor2) || \
21972 ((INSTANCE) == RAMECC_Monitor3))
21973
21974 /******************************** DMA Instances *******************************/
21975 #define IS_DMA_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
21976 ((INSTANCE) == DMA1_Stream1) || \
21977 ((INSTANCE) == DMA1_Stream2) || \
21978 ((INSTANCE) == DMA1_Stream3) || \
21979 ((INSTANCE) == DMA1_Stream4) || \
21980 ((INSTANCE) == DMA1_Stream5) || \
21981 ((INSTANCE) == DMA1_Stream6) || \
21982 ((INSTANCE) == DMA1_Stream7) || \
21983 ((INSTANCE) == DMA2_Stream0) || \
21984 ((INSTANCE) == DMA2_Stream1) || \
21985 ((INSTANCE) == DMA2_Stream2) || \
21986 ((INSTANCE) == DMA2_Stream3) || \
21987 ((INSTANCE) == DMA2_Stream4) || \
21988 ((INSTANCE) == DMA2_Stream5) || \
21989 ((INSTANCE) == DMA2_Stream6) || \
21990 ((INSTANCE) == DMA2_Stream7) || \
21991 ((INSTANCE) == BDMA1_Channel0) || \
21992 ((INSTANCE) == BDMA1_Channel1) || \
21993 ((INSTANCE) == BDMA1_Channel2) || \
21994 ((INSTANCE) == BDMA1_Channel3) || \
21995 ((INSTANCE) == BDMA1_Channel4) || \
21996 ((INSTANCE) == BDMA1_Channel5) || \
21997 ((INSTANCE) == BDMA1_Channel6) || \
21998 ((INSTANCE) == BDMA1_Channel7) || \
21999 ((INSTANCE) == BDMA2_Channel0) || \
22000 ((INSTANCE) == BDMA2_Channel1) || \
22001 ((INSTANCE) == BDMA2_Channel2) || \
22002 ((INSTANCE) == BDMA2_Channel3) || \
22003 ((INSTANCE) == BDMA2_Channel4) || \
22004 ((INSTANCE) == BDMA2_Channel5) || \
22005 ((INSTANCE) == BDMA2_Channel6) || \
22006 ((INSTANCE) == BDMA2_Channel7))
22007
22008 /****************************** BDMA CHANNEL Instances ***************************/
22009 #define IS_BDMA_CHANNEL_INSTANCE(INSTANCE) (((INSTANCE) == BDMA1_Channel0) || \
22010 ((INSTANCE) == BDMA1_Channel1) || \
22011 ((INSTANCE) == BDMA1_Channel2) || \
22012 ((INSTANCE) == BDMA1_Channel3) || \
22013 ((INSTANCE) == BDMA1_Channel4) || \
22014 ((INSTANCE) == BDMA1_Channel5) || \
22015 ((INSTANCE) == BDMA1_Channel6) || \
22016 ((INSTANCE) == BDMA1_Channel7) || \
22017 ((INSTANCE) == BDMA2_Channel0) || \
22018 ((INSTANCE) == BDMA2_Channel1) || \
22019 ((INSTANCE) == BDMA2_Channel2) || \
22020 ((INSTANCE) == BDMA2_Channel3) || \
22021 ((INSTANCE) == BDMA2_Channel4) || \
22022 ((INSTANCE) == BDMA2_Channel5) || \
22023 ((INSTANCE) == BDMA2_Channel6) || \
22024 ((INSTANCE) == BDMA2_Channel7))
22025
22026 /****************************** DMA DMAMUX ALL Instances ***************************/
22027 #define IS_DMA_DMAMUX_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22028 ((INSTANCE) == DMA1_Stream1) || \
22029 ((INSTANCE) == DMA1_Stream2) || \
22030 ((INSTANCE) == DMA1_Stream3) || \
22031 ((INSTANCE) == DMA1_Stream4) || \
22032 ((INSTANCE) == DMA1_Stream5) || \
22033 ((INSTANCE) == DMA1_Stream6) || \
22034 ((INSTANCE) == DMA1_Stream7) || \
22035 ((INSTANCE) == DMA2_Stream0) || \
22036 ((INSTANCE) == DMA2_Stream1) || \
22037 ((INSTANCE) == DMA2_Stream2) || \
22038 ((INSTANCE) == DMA2_Stream3) || \
22039 ((INSTANCE) == DMA2_Stream4) || \
22040 ((INSTANCE) == DMA2_Stream5) || \
22041 ((INSTANCE) == DMA2_Stream6) || \
22042 ((INSTANCE) == DMA2_Stream7) || \
22043 ((INSTANCE) == BDMA2_Channel0) || \
22044 ((INSTANCE) == BDMA2_Channel1) || \
22045 ((INSTANCE) == BDMA2_Channel2) || \
22046 ((INSTANCE) == BDMA2_Channel3) || \
22047 ((INSTANCE) == BDMA2_Channel4) || \
22048 ((INSTANCE) == BDMA2_Channel5) || \
22049 ((INSTANCE) == BDMA2_Channel6) || \
22050 ((INSTANCE) == BDMA2_Channel7))
22051
22052 /****************************** BDMA DMAMUX Instances ***************************/
22053 #define IS_BDMA_CHANNEL_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == BDMA2_Channel0) || \
22054 ((INSTANCE) == BDMA2_Channel1) || \
22055 ((INSTANCE) == BDMA2_Channel2) || \
22056 ((INSTANCE) == BDMA2_Channel3) || \
22057 ((INSTANCE) == BDMA2_Channel4) || \
22058 ((INSTANCE) == BDMA2_Channel5) || \
22059 ((INSTANCE) == BDMA2_Channel6) || \
22060 ((INSTANCE) == BDMA2_Channel7))
22061
22062 /****************************** DMA STREAM Instances ***************************/
22063 #define IS_DMA_STREAM_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22064 ((INSTANCE) == DMA1_Stream1) || \
22065 ((INSTANCE) == DMA1_Stream2) || \
22066 ((INSTANCE) == DMA1_Stream3) || \
22067 ((INSTANCE) == DMA1_Stream4) || \
22068 ((INSTANCE) == DMA1_Stream5) || \
22069 ((INSTANCE) == DMA1_Stream6) || \
22070 ((INSTANCE) == DMA1_Stream7) || \
22071 ((INSTANCE) == DMA2_Stream0) || \
22072 ((INSTANCE) == DMA2_Stream1) || \
22073 ((INSTANCE) == DMA2_Stream2) || \
22074 ((INSTANCE) == DMA2_Stream3) || \
22075 ((INSTANCE) == DMA2_Stream4) || \
22076 ((INSTANCE) == DMA2_Stream5) || \
22077 ((INSTANCE) == DMA2_Stream6) || \
22078 ((INSTANCE) == DMA2_Stream7))
22079
22080 /****************************** DMA DMAMUX Instances ***************************/
22081 #define IS_DMA_STREAM_DMAMUX_INSTANCE(INSTANCE) (((INSTANCE) == DMA1_Stream0) || \
22082 ((INSTANCE) == DMA1_Stream1) || \
22083 ((INSTANCE) == DMA1_Stream2) || \
22084 ((INSTANCE) == DMA1_Stream3) || \
22085 ((INSTANCE) == DMA1_Stream4) || \
22086 ((INSTANCE) == DMA1_Stream5) || \
22087 ((INSTANCE) == DMA1_Stream6) || \
22088 ((INSTANCE) == DMA1_Stream7) || \
22089 ((INSTANCE) == DMA2_Stream0) || \
22090 ((INSTANCE) == DMA2_Stream1) || \
22091 ((INSTANCE) == DMA2_Stream2) || \
22092 ((INSTANCE) == DMA2_Stream3) || \
22093 ((INSTANCE) == DMA2_Stream4) || \
22094 ((INSTANCE) == DMA2_Stream5) || \
22095 ((INSTANCE) == DMA2_Stream6) || \
22096 ((INSTANCE) == DMA2_Stream7))
22097
22098 /******************************** DMA Request Generator Instances **************/
22099 #define IS_DMA_REQUEST_GEN_ALL_INSTANCE(INSTANCE) (((INSTANCE) == DMAMUX1_RequestGenerator0) || \
22100 ((INSTANCE) == DMAMUX1_RequestGenerator1) || \
22101 ((INSTANCE) == DMAMUX1_RequestGenerator2) || \
22102 ((INSTANCE) == DMAMUX1_RequestGenerator3) || \
22103 ((INSTANCE) == DMAMUX1_RequestGenerator4) || \
22104 ((INSTANCE) == DMAMUX1_RequestGenerator5) || \
22105 ((INSTANCE) == DMAMUX1_RequestGenerator6) || \
22106 ((INSTANCE) == DMAMUX1_RequestGenerator7) || \
22107 ((INSTANCE) == DMAMUX2_RequestGenerator0) || \
22108 ((INSTANCE) == DMAMUX2_RequestGenerator1) || \
22109 ((INSTANCE) == DMAMUX2_RequestGenerator2) || \
22110 ((INSTANCE) == DMAMUX2_RequestGenerator3) || \
22111 ((INSTANCE) == DMAMUX2_RequestGenerator4) || \
22112 ((INSTANCE) == DMAMUX2_RequestGenerator5) || \
22113 ((INSTANCE) == DMAMUX2_RequestGenerator6) || \
22114 ((INSTANCE) == DMAMUX2_RequestGenerator7))
22115
22116 /******************************* DMA2D Instances *******************************/
22117 #define IS_DMA2D_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == DMA2D)
22118
22119 /******************************* OTFDEC Instances ******************************/
22120 #define IS_OTFDEC_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == OTFDEC1) || \
22121 ((__INSTANCE__) == OTFDEC2))
22122
22123 /****************************** PSSI Instance *********************************/
22124 #define IS_PSSI_ALL_INSTANCE(INSTANCE) ((INSTANCE) == PSSI)
22125
22126 /******************************** MDMA Request Generator Instances **************/
22127 #define IS_MDMA_STREAM_ALL_INSTANCE(INSTANCE) (((INSTANCE) == MDMA_Channel0) || \
22128 ((INSTANCE) == MDMA_Channel1) || \
22129 ((INSTANCE) == MDMA_Channel2) || \
22130 ((INSTANCE) == MDMA_Channel3) || \
22131 ((INSTANCE) == MDMA_Channel4) || \
22132 ((INSTANCE) == MDMA_Channel5) || \
22133 ((INSTANCE) == MDMA_Channel6) || \
22134 ((INSTANCE) == MDMA_Channel7) || \
22135 ((INSTANCE) == MDMA_Channel8) || \
22136 ((INSTANCE) == MDMA_Channel9) || \
22137 ((INSTANCE) == MDMA_Channel10) || \
22138 ((INSTANCE) == MDMA_Channel11) || \
22139 ((INSTANCE) == MDMA_Channel12) || \
22140 ((INSTANCE) == MDMA_Channel13) || \
22141 ((INSTANCE) == MDMA_Channel14) || \
22142 ((INSTANCE) == MDMA_Channel15))
22143
22144
22145 /******************************* FDCAN Instances ******************************/
22146 #define IS_FDCAN_ALL_INSTANCE(__INSTANCE__) (((__INSTANCE__) == FDCAN1) || \
22147 ((__INSTANCE__) == FDCAN2))
22148
22149 #define IS_FDCAN_TT_INSTANCE(__INSTANCE__) ((__INSTANCE__) == FDCAN1)
22150
22151 /******************************* GFXMMU Instances *******************************/
22152 #define IS_GFXMMU_ALL_INSTANCE(INSTANCE) ((INSTANCE) == GFXMMU)
22153
22154 /******************************* GPIO Instances *******************************/
22155 #define IS_GPIO_ALL_INSTANCE(INSTANCE) (((INSTANCE) == GPIOA) || \
22156 ((INSTANCE) == GPIOB) || \
22157 ((INSTANCE) == GPIOC) || \
22158 ((INSTANCE) == GPIOD) || \
22159 ((INSTANCE) == GPIOE) || \
22160 ((INSTANCE) == GPIOF) || \
22161 ((INSTANCE) == GPIOG) || \
22162 ((INSTANCE) == GPIOH) || \
22163 ((INSTANCE) == GPIOI) || \
22164 ((INSTANCE) == GPIOJ) || \
22165 ((INSTANCE) == GPIOK))
22166
22167 /******************************* GPIO AF Instances ****************************/
22168 #define IS_GPIO_AF_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
22169
22170 /**************************** GPIO Lock Instances *****************************/
22171 /* On H7, all GPIO Bank support the Lock mechanism */
22172 #define IS_GPIO_LOCK_INSTANCE(INSTANCE) IS_GPIO_ALL_INSTANCE(INSTANCE)
22173
22174 /******************************** HSEM Instances *******************************/
22175 #define IS_HSEM_ALL_INSTANCE(INSTANCE) ((INSTANCE) == HSEM)
22176 #define HSEM_CPU1_COREID (0x00000001U) /* Semaphore Core CM7 ID */
22177 #define HSEM_CR_COREID_CPU1 (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22178 #define HSEM_CR_COREID_CURRENT (HSEM_CPU1_COREID << HSEM_CR_COREID_Pos)
22179
22180 #define HSEM_SEMID_MIN (0U) /* HSEM ID Min*/
22181 #define HSEM_SEMID_MAX (15U) /* HSEM ID Max */
22182
22183 #define HSEM_PROCESSID_MIN (0U) /* HSEM Process ID Min */
22184 #define HSEM_PROCESSID_MAX (255U) /* HSEM Process ID Max */
22185
22186 #define HSEM_CLEAR_KEY_MIN (0U) /* HSEM clear Key Min value */
22187 #define HSEM_CLEAR_KEY_MAX (0xFFFFU) /* HSEM clear Key Max value */
22188
22189 /******************************** I2C Instances *******************************/
22190 #define IS_I2C_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22191 ((INSTANCE) == I2C2) || \
22192 ((INSTANCE) == I2C3) || \
22193 ((INSTANCE) == I2C4))
22194 /************** I2C Instances : wakeup capability from stop modes *************/
22195 #define IS_I2C_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) IS_I2C_ALL_INSTANCE(INSTANCE)
22196
22197 /****************************** SMBUS Instances *******************************/
22198 #define IS_SMBUS_ALL_INSTANCE(INSTANCE) (((INSTANCE) == I2C1) || \
22199 ((INSTANCE) == I2C2) || \
22200 ((INSTANCE) == I2C3) || \
22201 ((INSTANCE) == I2C4))
22202 /******************************** I2S Instances *******************************/
22203 #define IS_I2S_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22204 ((INSTANCE) == SPI2) || \
22205 ((INSTANCE) == SPI3) || \
22206 ((INSTANCE) == SPI6))
22207
22208 /****************************** LTDC Instances ********************************/
22209 #define IS_LTDC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == LTDC)
22210
22211 /******************************* RNG Instances ********************************/
22212 #define IS_RNG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RNG)
22213
22214 /****************************** RTC Instances *********************************/
22215 #define IS_RTC_ALL_INSTANCE(INSTANCE) ((INSTANCE) == RTC)
22216
22217 /****************************** SDMMC Instances *********************************/
22218 #define IS_SDMMC_ALL_INSTANCE(_INSTANCE_) (((_INSTANCE_) == SDMMC1) || \
22219 ((_INSTANCE_) == SDMMC2))
22220
22221 /******************************** SMBUS Instances *****************************/
22222 #define IS_SMBUS_INSTANCE(INSTANCE) ((INSTANCE) == I2C1)
22223
22224 /******************************** SPI Instances *******************************/
22225 #define IS_SPI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22226 ((INSTANCE) == SPI2) || \
22227 ((INSTANCE) == SPI3) || \
22228 ((INSTANCE) == SPI4) || \
22229 ((INSTANCE) == SPI5) || \
22230 ((INSTANCE) == SPI6))
22231
22232 #define IS_SPI_HIGHEND_INSTANCE(INSTANCE) (((INSTANCE) == SPI1) || \
22233 ((INSTANCE) == SPI2) || \
22234 ((INSTANCE) == SPI3))
22235
22236 /******************************** SWPMI Instances *****************************/
22237 #define IS_SWPMI_INSTANCE(INSTANCE) ((INSTANCE) == SWPMI1)
22238
22239 /****************** LPTIM Instances : All supported instances *****************/
22240 #define IS_LPTIM_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
22241 ((INSTANCE) == LPTIM2) || \
22242 ((INSTANCE) == LPTIM3))
22243
22244 /****************** LPTIM Instances : supporting encoder interface **************/
22245 #define IS_LPTIM_ENCODER_INTERFACE_INSTANCE(INSTANCE) (((INSTANCE) == LPTIM1) || \
22246 ((INSTANCE) == LPTIM2))
22247
22248 /****************** TIM Instances : All supported instances *******************/
22249 #define IS_TIM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22250 ((INSTANCE) == TIM2) || \
22251 ((INSTANCE) == TIM3) || \
22252 ((INSTANCE) == TIM4) || \
22253 ((INSTANCE) == TIM5) || \
22254 ((INSTANCE) == TIM6) || \
22255 ((INSTANCE) == TIM7) || \
22256 ((INSTANCE) == TIM8) || \
22257 ((INSTANCE) == TIM12) || \
22258 ((INSTANCE) == TIM13) || \
22259 ((INSTANCE) == TIM14) || \
22260 ((INSTANCE) == TIM15) || \
22261 ((INSTANCE) == TIM16) || \
22262 ((INSTANCE) == TIM17))
22263
22264 /************* TIM Instances : at least 1 capture/compare channel *************/
22265 #define IS_TIM_CC1_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22266 ((INSTANCE) == TIM2) || \
22267 ((INSTANCE) == TIM3) || \
22268 ((INSTANCE) == TIM4) || \
22269 ((INSTANCE) == TIM5) || \
22270 ((INSTANCE) == TIM8) || \
22271 ((INSTANCE) == TIM12) || \
22272 ((INSTANCE) == TIM13) || \
22273 ((INSTANCE) == TIM14) || \
22274 ((INSTANCE) == TIM15) || \
22275 ((INSTANCE) == TIM16) || \
22276 ((INSTANCE) == TIM17))
22277
22278 /************ TIM Instances : at least 2 capture/compare channels *************/
22279 #define IS_TIM_CC2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22280 ((INSTANCE) == TIM2) || \
22281 ((INSTANCE) == TIM3) || \
22282 ((INSTANCE) == TIM4) || \
22283 ((INSTANCE) == TIM5) || \
22284 ((INSTANCE) == TIM8) || \
22285 ((INSTANCE) == TIM12) || \
22286 ((INSTANCE) == TIM15))
22287
22288 /************ TIM Instances : at least 3 capture/compare channels *************/
22289 #define IS_TIM_CC3_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22290 ((INSTANCE) == TIM2) || \
22291 ((INSTANCE) == TIM3) || \
22292 ((INSTANCE) == TIM4) || \
22293 ((INSTANCE) == TIM5) || \
22294 ((INSTANCE) == TIM8))
22295
22296 /************ TIM Instances : at least 4 capture/compare channels *************/
22297 #define IS_TIM_CC4_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22298 ((INSTANCE) == TIM2) || \
22299 ((INSTANCE) == TIM3) || \
22300 ((INSTANCE) == TIM4) || \
22301 ((INSTANCE) == TIM5) || \
22302 ((INSTANCE) == TIM8))
22303
22304 /************ TIM Instances : at least 5 capture/compare channels *************/
22305 #define IS_TIM_CC5_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22306 ((INSTANCE) == TIM8))
22307 /************ TIM Instances : at least 6 capture/compare channels *************/
22308 #define IS_TIM_CC6_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22309 ((INSTANCE) == TIM8))
22310
22311 /******************** TIM Instances : Advanced-control timers *****************/
22312 #define IS_TIM_ADVANCED_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22313 ((__INSTANCE__) == TIM8))
22314
22315 /******************** TIM Instances : Advanced-control timers *****************/
22316
22317 /******************* TIM Instances : Timer input XOR function *****************/
22318 #define IS_TIM_XOR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22319 ((INSTANCE) == TIM2) || \
22320 ((INSTANCE) == TIM3) || \
22321 ((INSTANCE) == TIM4) || \
22322 ((INSTANCE) == TIM5) || \
22323 ((INSTANCE) == TIM8) || \
22324 ((INSTANCE) == TIM15))
22325
22326 /****************** TIM Instances : DMA requests generation (UDE) *************/
22327 #define IS_TIM_DMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22328 ((INSTANCE) == TIM2) || \
22329 ((INSTANCE) == TIM3) || \
22330 ((INSTANCE) == TIM4) || \
22331 ((INSTANCE) == TIM5) || \
22332 ((INSTANCE) == TIM6) || \
22333 ((INSTANCE) == TIM7) || \
22334 ((INSTANCE) == TIM8) || \
22335 ((INSTANCE) == TIM15) || \
22336 ((INSTANCE) == TIM16) || \
22337 ((INSTANCE) == TIM17))
22338
22339 /************ TIM Instances : DMA requests generation (CCxDE) *****************/
22340 #define IS_TIM_DMA_CC_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22341 ((INSTANCE) == TIM2) || \
22342 ((INSTANCE) == TIM3) || \
22343 ((INSTANCE) == TIM4) || \
22344 ((INSTANCE) == TIM5) || \
22345 ((INSTANCE) == TIM8) || \
22346 ((INSTANCE) == TIM15) || \
22347 ((INSTANCE) == TIM16) || \
22348 ((INSTANCE) == TIM17))
22349
22350 /************ TIM Instances : DMA requests generation (COMDE) *****************/
22351 #define IS_TIM_CCDMA_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22352 ((INSTANCE) == TIM2) || \
22353 ((INSTANCE) == TIM3) || \
22354 ((INSTANCE) == TIM4) || \
22355 ((INSTANCE) == TIM5) || \
22356 ((INSTANCE) == TIM8) || \
22357 ((INSTANCE) == TIM15))
22358
22359 /******************** TIM Instances : DMA burst feature ***********************/
22360 #define IS_TIM_DMABURST_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22361 ((INSTANCE) == TIM2) || \
22362 ((INSTANCE) == TIM3) || \
22363 ((INSTANCE) == TIM4) || \
22364 ((INSTANCE) == TIM5) || \
22365 ((INSTANCE) == TIM8))
22366
22367 /*************** TIM Instances : external trigger reamp input available *******/
22368 #define IS_TIM_ETR_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22369 ((INSTANCE) == TIM2) || \
22370 ((INSTANCE) == TIM3) || \
22371 ((INSTANCE) == TIM4) || \
22372 ((INSTANCE) == TIM5) || \
22373 ((INSTANCE) == TIM8))
22374
22375 /****************** TIM Instances : remapping capability **********************/
22376 #define IS_TIM_REMAP_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22377 ((INSTANCE) == TIM2) || \
22378 ((INSTANCE) == TIM3) || \
22379 ((INSTANCE) == TIM5) || \
22380 ((INSTANCE) == TIM8) || \
22381 ((INSTANCE) == TIM16) || \
22382 ((INSTANCE) == TIM17))
22383
22384 /*************** TIM Instances : external trigger reamp input available *******/
22385 #define IS_TIM_ETRSEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22386 ((INSTANCE) == TIM2) || \
22387 ((INSTANCE) == TIM3) || \
22388 ((INSTANCE) == TIM5) || \
22389 ((INSTANCE) == TIM8))
22390
22391 /****** TIM Instances : master mode available (TIMx_CR2.MMS available )********/
22392 #define IS_TIM_MASTER_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22393 ((INSTANCE) == TIM2) || \
22394 ((INSTANCE) == TIM3) || \
22395 ((INSTANCE) == TIM4) || \
22396 ((INSTANCE) == TIM5) || \
22397 ((INSTANCE) == TIM6) || \
22398 ((INSTANCE) == TIM7) || \
22399 ((INSTANCE) == TIM8) || \
22400 ((INSTANCE) == TIM15))
22401
22402 /****** TIM Instances : Salve mode available (TIMx_SMCR.TS available )*********/
22403 #define IS_TIM_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22404 ((INSTANCE) == TIM2) || \
22405 ((INSTANCE) == TIM3) || \
22406 ((INSTANCE) == TIM4) || \
22407 ((INSTANCE) == TIM5) || \
22408 ((INSTANCE) == TIM8) || \
22409 ((INSTANCE) == TIM12))
22410
22411 /****** TIM Instances : TRGO2 available (TIMx_CR2.MMS2 available )*********/
22412 #define IS_TIM_TRGO2_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22413 ((INSTANCE) == TIM8))
22414
22415 /****** TIM Instances : TISEL available (TIMx_TISEL available )*********/
22416 #define IS_TIM_TISEL_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22417 ((INSTANCE) == TIM2) || \
22418 ((INSTANCE) == TIM3) || \
22419 ((INSTANCE) == TIM4) || \
22420 ((INSTANCE) == TIM5) || \
22421 ((INSTANCE) == TIM8) || \
22422 ((INSTANCE) == TIM15) || \
22423 ((INSTANCE) == TIM16) || \
22424 ((INSTANCE) == TIM17))
22425
22426 /****************** TIM Instances : supporting commutation event *************/
22427 #define IS_TIM_COMMUTATION_EVENT_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22428 ((INSTANCE) == TIM8) || \
22429 ((INSTANCE) == TIM15) || \
22430 ((INSTANCE) == TIM16) || \
22431 ((INSTANCE) == TIM17))
22432
22433 /****************** TIM Instances : supporting encoder interface **************/
22434 #define IS_TIM_ENCODER_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22435 ((__INSTANCE__) == TIM2) || \
22436 ((__INSTANCE__) == TIM3) || \
22437 ((__INSTANCE__) == TIM4) || \
22438 ((__INSTANCE__) == TIM5) || \
22439 ((__INSTANCE__) == TIM8))
22440
22441 /****** TIM Instances : TIM_CCR5_GC5C available (TIMx_CCR5.GC5C available )*********/
22442 #define IS_TIM_COMBINED3PHASEPWM_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22443 ((INSTANCE) == TIM8))
22444 /******************* TIM Instances : output(s) available **********************/
22445 #define IS_TIM_CCX_INSTANCE(INSTANCE, CHANNEL) \
22446 ((((INSTANCE) == TIM1) && \
22447 (((CHANNEL) == TIM_CHANNEL_1) || \
22448 ((CHANNEL) == TIM_CHANNEL_2) || \
22449 ((CHANNEL) == TIM_CHANNEL_3) || \
22450 ((CHANNEL) == TIM_CHANNEL_4) || \
22451 ((CHANNEL) == TIM_CHANNEL_5) || \
22452 ((CHANNEL) == TIM_CHANNEL_6))) \
22453 || \
22454 (((INSTANCE) == TIM2) && \
22455 (((CHANNEL) == TIM_CHANNEL_1) || \
22456 ((CHANNEL) == TIM_CHANNEL_2) || \
22457 ((CHANNEL) == TIM_CHANNEL_3) || \
22458 ((CHANNEL) == TIM_CHANNEL_4))) \
22459 || \
22460 (((INSTANCE) == TIM3) && \
22461 (((CHANNEL) == TIM_CHANNEL_1)|| \
22462 ((CHANNEL) == TIM_CHANNEL_2) || \
22463 ((CHANNEL) == TIM_CHANNEL_3) || \
22464 ((CHANNEL) == TIM_CHANNEL_4))) \
22465 || \
22466 (((INSTANCE) == TIM4) && \
22467 (((CHANNEL) == TIM_CHANNEL_1) || \
22468 ((CHANNEL) == TIM_CHANNEL_2) || \
22469 ((CHANNEL) == TIM_CHANNEL_3) || \
22470 ((CHANNEL) == TIM_CHANNEL_4))) \
22471 || \
22472 (((INSTANCE) == TIM5) && \
22473 (((CHANNEL) == TIM_CHANNEL_1) || \
22474 ((CHANNEL) == TIM_CHANNEL_2) || \
22475 ((CHANNEL) == TIM_CHANNEL_3) || \
22476 ((CHANNEL) == TIM_CHANNEL_4))) \
22477 || \
22478 (((INSTANCE) == TIM8) && \
22479 (((CHANNEL) == TIM_CHANNEL_1) || \
22480 ((CHANNEL) == TIM_CHANNEL_2) || \
22481 ((CHANNEL) == TIM_CHANNEL_3) || \
22482 ((CHANNEL) == TIM_CHANNEL_4) || \
22483 ((CHANNEL) == TIM_CHANNEL_5) || \
22484 ((CHANNEL) == TIM_CHANNEL_6))) \
22485 || \
22486 (((INSTANCE) == TIM12) && \
22487 (((CHANNEL) == TIM_CHANNEL_1) || \
22488 ((CHANNEL) == TIM_CHANNEL_2))) \
22489 || \
22490 (((INSTANCE) == TIM13) && \
22491 (((CHANNEL) == TIM_CHANNEL_1))) \
22492 || \
22493 (((INSTANCE) == TIM14) && \
22494 (((CHANNEL) == TIM_CHANNEL_1))) \
22495 || \
22496 (((INSTANCE) == TIM15) && \
22497 (((CHANNEL) == TIM_CHANNEL_1) || \
22498 ((CHANNEL) == TIM_CHANNEL_2))) \
22499 || \
22500 (((INSTANCE) == TIM16) && \
22501 (((CHANNEL) == TIM_CHANNEL_1))) \
22502 || \
22503 (((INSTANCE) == TIM17) && \
22504 (((CHANNEL) == TIM_CHANNEL_1))))
22505
22506 /****************** TIM Instances : supporting the break function *************/
22507 #define IS_TIM_BREAK_INSTANCE(INSTANCE)\
22508 (((INSTANCE) == TIM1) || \
22509 ((INSTANCE) == TIM8) || \
22510 ((INSTANCE) == TIM15) || \
22511 ((INSTANCE) == TIM16) || \
22512 ((INSTANCE) == TIM17))
22513
22514 /************** TIM Instances : supporting Break source selection *************/
22515 #define IS_TIM_BREAKSOURCE_INSTANCE(INSTANCE) (((INSTANCE) == TIM1) || \
22516 ((INSTANCE) == TIM8))
22517
22518 /****************** TIM Instances : supporting complementary output(s) ********/
22519 #define IS_TIM_CCXN_INSTANCE(INSTANCE, CHANNEL) \
22520 ((((INSTANCE) == TIM1) && \
22521 (((CHANNEL) == TIM_CHANNEL_1) || \
22522 ((CHANNEL) == TIM_CHANNEL_2) || \
22523 ((CHANNEL) == TIM_CHANNEL_3))) \
22524 || \
22525 (((INSTANCE) == TIM8) && \
22526 (((CHANNEL) == TIM_CHANNEL_1) || \
22527 ((CHANNEL) == TIM_CHANNEL_2) || \
22528 ((CHANNEL) == TIM_CHANNEL_3))) \
22529 || \
22530 (((INSTANCE) == TIM15) && \
22531 ((CHANNEL) == TIM_CHANNEL_1)) \
22532 || \
22533 (((INSTANCE) == TIM16) && \
22534 ((CHANNEL) == TIM_CHANNEL_1)) \
22535 || \
22536 (((INSTANCE) == TIM17) && \
22537 ((CHANNEL) == TIM_CHANNEL_1)))
22538
22539 /****************** TIM Instances : supporting counting mode selection ********/
22540 #define IS_TIM_COUNTER_MODE_SELECT_INSTANCE(INSTANCE)\
22541 (((INSTANCE) == TIM1) || \
22542 ((INSTANCE) == TIM2) || \
22543 ((INSTANCE) == TIM3) || \
22544 ((INSTANCE) == TIM4) || \
22545 ((INSTANCE) == TIM5) || \
22546 ((INSTANCE) == TIM8))
22547
22548 /****************** TIM Instances : supporting repetition counter *************/
22549 #define IS_TIM_REPETITION_COUNTER_INSTANCE(INSTANCE)\
22550 (((INSTANCE) == TIM1) || \
22551 ((INSTANCE) == TIM8) || \
22552 ((INSTANCE) == TIM15) || \
22553 ((INSTANCE) == TIM16) || \
22554 ((INSTANCE) == TIM17))
22555
22556 /****************** TIM Instances : supporting synchronization ****************/
22557 #define IS_TIM_SYNCHRO_INSTANCE(__INSTANCE__)\
22558 (((__INSTANCE__) == TIM1) || \
22559 ((__INSTANCE__) == TIM2) || \
22560 ((__INSTANCE__) == TIM3) || \
22561 ((__INSTANCE__) == TIM4) || \
22562 ((__INSTANCE__) == TIM5) || \
22563 ((__INSTANCE__) == TIM6) || \
22564 ((__INSTANCE__) == TIM8) || \
22565 ((__INSTANCE__) == TIM12) || \
22566 ((__INSTANCE__) == TIM15))
22567
22568 /****************** TIM Instances : supporting clock division *****************/
22569 #define IS_TIM_CLOCK_DIVISION_INSTANCE(INSTANCE)\
22570 (((INSTANCE) == TIM1) || \
22571 ((INSTANCE) == TIM2) || \
22572 ((INSTANCE) == TIM3) || \
22573 ((INSTANCE) == TIM4) || \
22574 ((INSTANCE) == TIM5) || \
22575 ((INSTANCE) == TIM8) || \
22576 ((INSTANCE) == TIM15) || \
22577 ((INSTANCE) == TIM16) || \
22578 ((INSTANCE) == TIM17))
22579
22580 /****************** TIM Instances : supporting external clock mode 1 for ETRF input */
22581 #define IS_TIM_CLOCKSOURCE_ETRMODE1_INSTANCE(INSTANCE)\
22582 (((INSTANCE) == TIM1) || \
22583 ((INSTANCE) == TIM2) || \
22584 ((INSTANCE) == TIM3) || \
22585 ((INSTANCE) == TIM4) || \
22586 ((INSTANCE) == TIM5) || \
22587 ((INSTANCE) == TIM8))
22588
22589 /****************** TIM Instances : supporting external clock mode 2 **********/
22590 #define IS_TIM_CLOCKSOURCE_ETRMODE2_INSTANCE(INSTANCE)\
22591 (((INSTANCE) == TIM1) || \
22592 ((INSTANCE) == TIM2) || \
22593 ((INSTANCE) == TIM3) || \
22594 ((INSTANCE) == TIM4) || \
22595 ((INSTANCE) == TIM5) || \
22596 ((INSTANCE) == TIM8))
22597
22598 /****************** TIM Instances : supporting external clock mode 1 for TIX inputs*/
22599 #define IS_TIM_CLOCKSOURCE_TIX_INSTANCE(INSTANCE)\
22600 (((INSTANCE) == TIM1) || \
22601 ((INSTANCE) == TIM2) || \
22602 ((INSTANCE) == TIM3) || \
22603 ((INSTANCE) == TIM4) || \
22604 ((INSTANCE) == TIM5) || \
22605 ((INSTANCE) == TIM8) || \
22606 ((INSTANCE) == TIM15))
22607
22608 /****************** TIM Instances : supporting internal trigger inputs(ITRX) *******/
22609 #define IS_TIM_CLOCKSOURCE_ITRX_INSTANCE(INSTANCE)\
22610 (((INSTANCE) == TIM1) || \
22611 ((INSTANCE) == TIM2) || \
22612 ((INSTANCE) == TIM3) || \
22613 ((INSTANCE) == TIM4) || \
22614 ((INSTANCE) == TIM5) || \
22615 ((INSTANCE) == TIM8) || \
22616 ((INSTANCE) == TIM15))
22617
22618 /****************** TIM Instances : supporting OCxREF clear *******************/
22619 #define IS_TIM_OCXREF_CLEAR_INSTANCE(INSTANCE)\
22620 (((INSTANCE) == TIM1) || \
22621 ((INSTANCE) == TIM2) || \
22622 ((INSTANCE) == TIM3))
22623
22624 /****************** TIM Instances : TIM_32B_COUNTER ***************************/
22625 #define IS_TIM_32B_COUNTER_INSTANCE(INSTANCE)\
22626 (((INSTANCE) == TIM2) || \
22627 ((INSTANCE) == TIM5))
22628
22629 /****************** TIM Instances : TIM_BKIN2 ***************************/
22630 #define IS_TIM_BKIN2_INSTANCE(INSTANCE)\
22631 (((INSTANCE) == TIM1) || \
22632 ((INSTANCE) == TIM8))
22633
22634 /****************** TIM Instances : supporting Hall sensor interface **********/
22635 #define IS_TIM_HALL_SENSOR_INTERFACE_INSTANCE(__INSTANCE__) (((__INSTANCE__) == TIM1) || \
22636 ((__INSTANCE__) == TIM2) || \
22637 ((__INSTANCE__) == TIM3) || \
22638 ((__INSTANCE__) == TIM4) || \
22639 ((__INSTANCE__) == TIM5) || \
22640 ((__INSTANCE__) == TIM15) || \
22641 ((__INSTANCE__) == TIM8))
22642
22643 /******************** USART Instances : Synchronous mode **********************/
22644 #define IS_USART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22645 ((INSTANCE) == USART2) || \
22646 ((INSTANCE) == USART3) || \
22647 ((INSTANCE) == USART6) || \
22648 ((INSTANCE) == USART10))
22649
22650 /******************** USART Instances : SPI slave mode ************************/
22651 #define IS_UART_SPI_SLAVE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22652 ((INSTANCE) == USART2) || \
22653 ((INSTANCE) == USART3) || \
22654 ((INSTANCE) == USART6) || \
22655 ((INSTANCE) == USART10))
22656
22657 /******************** UART Instances : Asynchronous mode **********************/
22658 #define IS_UART_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22659 ((INSTANCE) == USART2) || \
22660 ((INSTANCE) == USART3) || \
22661 ((INSTANCE) == UART4) || \
22662 ((INSTANCE) == UART5) || \
22663 ((INSTANCE) == USART6) || \
22664 ((INSTANCE) == UART7) || \
22665 ((INSTANCE) == UART8) || \
22666 ((INSTANCE) == UART9) || \
22667 ((INSTANCE) == USART10))
22668
22669 /******************** UART Instances : FIFO mode.******************************/
22670 #define IS_UART_FIFO_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22671 ((INSTANCE) == USART2) || \
22672 ((INSTANCE) == USART3) || \
22673 ((INSTANCE) == UART4) || \
22674 ((INSTANCE) == UART5) || \
22675 ((INSTANCE) == USART6) || \
22676 ((INSTANCE) == UART7) || \
22677 ((INSTANCE) == UART8) || \
22678 ((INSTANCE) == UART9) || \
22679 ((INSTANCE) == USART10)|| \
22680 ((INSTANCE) == LPUART1))
22681
22682 /****************** UART Instances : Auto Baud Rate detection *****************/
22683 #define IS_USART_AUTOBAUDRATE_DETECTION_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22684 ((INSTANCE) == USART2) || \
22685 ((INSTANCE) == USART3) || \
22686 ((INSTANCE) == UART4) || \
22687 ((INSTANCE) == UART5) || \
22688 ((INSTANCE) == USART6) || \
22689 ((INSTANCE) == UART7) || \
22690 ((INSTANCE) == UART8) || \
22691 ((INSTANCE) == UART9) || \
22692 ((INSTANCE) == USART10))
22693
22694 /*********************** UART Instances : Driver Enable ***********************/
22695 #define IS_UART_DRIVER_ENABLE_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22696 ((INSTANCE) == USART2) || \
22697 ((INSTANCE) == USART3) || \
22698 ((INSTANCE) == UART4) || \
22699 ((INSTANCE) == UART5) || \
22700 ((INSTANCE) == USART6) || \
22701 ((INSTANCE) == UART7) || \
22702 ((INSTANCE) == UART8) || \
22703 ((INSTANCE) == UART9) || \
22704 ((INSTANCE) == USART10)|| \
22705 ((INSTANCE) == LPUART1))
22706
22707 /********************* UART Instances : Half-Duplex mode **********************/
22708 #define IS_UART_HALFDUPLEX_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22709 ((INSTANCE) == USART2) || \
22710 ((INSTANCE) == USART3) || \
22711 ((INSTANCE) == UART4) || \
22712 ((INSTANCE) == UART5) || \
22713 ((INSTANCE) == USART6) || \
22714 ((INSTANCE) == UART7) || \
22715 ((INSTANCE) == UART8) || \
22716 ((INSTANCE) == UART9) || \
22717 ((INSTANCE) == USART10)|| \
22718 ((INSTANCE) == LPUART1))
22719
22720 /******************* UART Instances : Hardware Flow control *******************/
22721 #define IS_UART_HWFLOW_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22722 ((INSTANCE) == USART2) || \
22723 ((INSTANCE) == USART3) || \
22724 ((INSTANCE) == UART4) || \
22725 ((INSTANCE) == UART5) || \
22726 ((INSTANCE) == USART6) || \
22727 ((INSTANCE) == UART7) || \
22728 ((INSTANCE) == UART8) || \
22729 ((INSTANCE) == UART9) || \
22730 ((INSTANCE) == USART10)|| \
22731 ((INSTANCE) == LPUART1))
22732
22733 /************************* UART Instances : LIN mode **************************/
22734 #define IS_UART_LIN_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22735 ((INSTANCE) == USART2) || \
22736 ((INSTANCE) == USART3) || \
22737 ((INSTANCE) == UART4) || \
22738 ((INSTANCE) == UART5) || \
22739 ((INSTANCE) == USART6) || \
22740 ((INSTANCE) == UART7) || \
22741 ((INSTANCE) == UART8) || \
22742 ((INSTANCE) == UART9) || \
22743 ((INSTANCE) == USART10))
22744
22745 /****************** UART Instances : Wake-up from Stop mode *******************/
22746 #define IS_UART_WAKEUP_FROMSTOP_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22747 ((INSTANCE) == USART2) || \
22748 ((INSTANCE) == USART3) || \
22749 ((INSTANCE) == UART4) || \
22750 ((INSTANCE) == UART5) || \
22751 ((INSTANCE) == USART6) || \
22752 ((INSTANCE) == UART7) || \
22753 ((INSTANCE) == UART8) || \
22754 ((INSTANCE) == UART9) || \
22755 ((INSTANCE) == USART10)|| \
22756 ((INSTANCE) == LPUART1))
22757
22758 /************************* UART Instances : IRDA mode *************************/
22759 #define IS_IRDA_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22760 ((INSTANCE) == USART2) || \
22761 ((INSTANCE) == USART3) || \
22762 ((INSTANCE) == UART4) || \
22763 ((INSTANCE) == UART5) || \
22764 ((INSTANCE) == USART6) || \
22765 ((INSTANCE) == UART7) || \
22766 ((INSTANCE) == UART8) || \
22767 ((INSTANCE) == UART9) || \
22768 ((INSTANCE) == USART10))
22769
22770 /********************* USART Instances : Smard card mode **********************/
22771 #define IS_SMARTCARD_INSTANCE(INSTANCE) (((INSTANCE) == USART1) || \
22772 ((INSTANCE) == USART2) || \
22773 ((INSTANCE) == USART3) || \
22774 ((INSTANCE) == USART6) ||\
22775 ((INSTANCE) == USART10))
22776
22777 /****************************** LPUART Instance *******************************/
22778 #define IS_LPUART_INSTANCE(INSTANCE) ((INSTANCE) == LPUART1)
22779
22780 /****************************** IWDG Instances ********************************/
22781 #define IS_IWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == IWDG1)
22782 /****************************** USB Instances ********************************/
22783 #define IS_USB_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB)
22784
22785 /****************************** WWDG Instances ********************************/
22786 #define IS_WWDG_ALL_INSTANCE(INSTANCE) ((INSTANCE) == WWDG1)
22787 /****************************** MDIOS Instances ********************************/
22788 #define IS_MDIOS_ALL_INSTANCE(INSTANCE) ((INSTANCE) == MDIOS)
22789
22790 /****************************** CEC Instances *********************************/
22791 #define IS_CEC_ALL_INSTANCE(__INSTANCE__) ((__INSTANCE__) == CEC)
22792
22793 /****************************** SAI Instances ********************************/
22794 #define IS_SAI_ALL_INSTANCE(INSTANCE) (((INSTANCE) == SAI1_Block_A) || \
22795 ((INSTANCE) == SAI1_Block_B) || \
22796 ((INSTANCE) == SAI2_Block_A) || \
22797 ((INSTANCE) == SAI2_Block_B))
22798
22799 /****************************** SPDIFRX Instances ********************************/
22800 #define IS_SPDIFRX_ALL_INSTANCE(INSTANCE) ((INSTANCE) == SPDIFRX)
22801
22802 /****************************** OPAMP Instances *******************************/
22803 #define IS_OPAMP_ALL_INSTANCE(INSTANCE) (((INSTANCE) == OPAMP1) || \
22804 ((INSTANCE) == OPAMP2))
22805
22806 #define IS_OPAMP_COMMON_INSTANCE(COMMON_INSTANCE) ((COMMON_INSTANCE) == OPAMP12_COMMON)
22807
22808 /*********************** USB OTG PCD Instances ********************************/
22809 #define IS_PCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22810
22811 /*********************** USB OTG HCD Instances ********************************/
22812 #define IS_HCD_ALL_INSTANCE(INSTANCE) ((INSTANCE) == USB_OTG_HS)
22813
22814 /******************************************************************************/
22815 /* For a painless codes migration between the STM32H7xx device product */
22816 /* lines, or with STM32F7xx devices the aliases defined below are put */
22817 /* in place to overcome the differences in the interrupt handlers and IRQn */
22818 /* definitions. No need to update developed interrupt code when moving */
22819 /* across product lines within the same STM32H7 Family */
22820 /******************************************************************************/
22821
22822 /* Aliases for __IRQn */
22823 #define RNG_IRQn HASH_RNG_IRQn
22824 #define TIM1_BRK_TIM9_IRQn TIM1_BRK_IRQn
22825 #define TIM1_UP_TIM10_IRQn TIM1_UP_IRQn
22826 #define TIM1_TRG_COM_TIM11_IRQn TIM1_TRG_COM_IRQn
22827 #define PVD_IRQn PVD_AVD_IRQn
22828
22829 /* Aliases for BDMA __IRQn */
22830 #define BDMA_Channel0_IRQn BDMA2_Channel0_IRQn
22831 #define BDMA_Channel1_IRQn BDMA2_Channel1_IRQn
22832 #define BDMA_Channel2_IRQn BDMA2_Channel2_IRQn
22833 #define BDMA_Channel3_IRQn BDMA2_Channel3_IRQn
22834 #define BDMA_Channel4_IRQn BDMA2_Channel4_IRQn
22835 #define BDMA_Channel5_IRQn BDMA2_Channel5_IRQn
22836 #define BDMA_Channel6_IRQn BDMA2_Channel6_IRQn
22837 #define BDMA_Channel7_IRQn BDMA2_Channel7_IRQn
22838
22839 /* Aliases for PWR __IRQn */
22840 #define PVD_AVD_IRQn PVD_PVM_IRQn
22841
22842 /* Aliases for DCMI/PSSI __IRQn */
22843 #define DCMI_IRQn DCMI_PSSI_IRQn
22844
22845 /* Aliases for __IRQHandler */
22846 #define RNG_IRQHandler HASH_RNG_IRQHandler
22847 #define TIM1_BRK_TIM9_IRQHandler TIM1_BRK_IRQHandler
22848 #define TIM1_UP_TIM9_IRQHandler TIM1_UP_IRQHandler
22849 #define TIM1_TRG_COM_TIM11_IRQHandler TIM1_TRG_COM_IRQHandler
22850 #define PVD_IRQHandler PVD_AVD_IRQHandler
22851
22852
22853 /* Aliases for BDMA __IRQHandler */
22854 #define BDMA_Channel0_IRQHandler BDMA2_Channel0_IRQHandler
22855 #define BDMA_Channel1_IRQHandler BDMA2_Channel1_IRQHandler
22856 #define BDMA_Channel2_IRQHandler BDMA2_Channel2_IRQHandler
22857 #define BDMA_Channel3_IRQHandler BDMA2_Channel3_IRQHandler
22858 #define BDMA_Channel4_IRQHandler BDMA2_Channel4_IRQHandler
22859 #define BDMA_Channel5_IRQHandler BDMA2_Channel5_IRQHandler
22860 #define BDMA_Channel6_IRQHandler BDMA2_Channel6_IRQHandler
22861 #define BDMA_Channel7_IRQHandler BDMA2_Channel7_IRQHandler
22862
22863 /* Aliases for PWR __IRQHandler */
22864 #define PVD_AVD_IRQHandler PVD_PVM_IRQHandler
22865
22866 /* Aliases for DCMI/PSSI __IRQHandler */
22867 #define DCMI_IRQHandler DCMI_PSSI_IRQHandler
22868
22869 /* Alias for BDMA defines */
22870 #define BDMA_BASE BDMA2_BASE
22871 #define BDMA_Channel0_BASE BDMA2_Channel0_BASE
22872 #define BDMA_Channel1_BASE BDMA2_Channel1_BASE
22873 #define BDMA_Channel2_BASE BDMA2_Channel2_BASE
22874 #define BDMA_Channel3_BASE BDMA2_Channel3_BASE
22875 #define BDMA_Channel4_BASE BDMA2_Channel4_BASE
22876 #define BDMA_Channel5_BASE BDMA2_Channel5_BASE
22877 #define BDMA_Channel6_BASE BDMA2_Channel6_BASE
22878 #define BDMA_Channel7_BASE BDMA2_Channel7_BASE
22879
22880 #define BDMA BDMA2
22881 #define BDMA_Channel0 BDMA2_Channel0
22882 #define BDMA_Channel1 BDMA2_Channel1
22883 #define BDMA_Channel2 BDMA2_Channel2
22884 #define BDMA_Channel3 BDMA2_Channel3
22885 #define BDMA_Channel4 BDMA2_Channel4
22886 #define BDMA_Channel5 BDMA2_Channel5
22887 #define BDMA_Channel6 BDMA2_Channel6
22888 #define BDMA_Channel7 BDMA2_Channel7
22889
22890 /* Alias for PWR defines */
22891 #define PWR_CPUCR_RUN_D3 PWR_CPUCR_RUN_SRD
22892 #define PWR_CPUCR_PDDS_D3 PWR_CPUCR_PDDS_SRD
22893 #define PWR_CPUCR_PDDS_D1 PWR_CPUCR_RETDS_CD
22894
22895 #define PWR_D3CR_VOS PWR_SRDCR_VOS
22896
22897 #define PWR_D3CR_VOS_0 PWR_SRDCR_VOS_0
22898 #define PWR_D3CR_VOS_1 PWR_SRDCR_VOS_1
22899 #define PWR_D3CR_VOSRDY PWR_SRDCR_VOSRDY
22900
22901 /**
22902 * @}
22903 */
22904
22905 /**
22906 * @}
22907 */
22908
22909 /**
22910 * @}
22911 */
22912
22913 #ifdef __cplusplus
22914 }
22915 #endif /* __cplusplus */
22916
22917 #endif /* STM32H7B0xxQ_H */
22918
22919 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software