lib/main/STM32H7/Drivers/CMSIS/Device/ST/STM32H7xx/Release_Notes.html

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  25 <h1 id="release-notes-for-stm32h7xx-cmsis"><strong>Release Notes for STM32H7xx CMSIS</strong></h1>
  26 <p>Copyright © 2017 STMicroelectronics<br />
  27 </p>
  28 <a href="https://www.st.com" class="logo"><img src="_htmresc/st_logo.png" alt="ST logo" /></a>
  29 </center>
  30 </div>
  31 </div>
  32 <h1 id="license"><strong>License</strong></h1>
  33 This software component is licensed by ST under BSD 3-Clause license, the “License”; You may not use this component except in compliance with the License. You may obtain a copy of the License at:
  34 <center>
  35 <a href="https://opensource.org/licenses/BSD-3-Clause">https://opensource.org/licenses/BSD-3-Clause</a>
  36 </center>
  37 </div>
  38 <div class="col-sm-12 col-lg-8">
  39 <h1 id="update-history"><strong>Update History</strong></h1>
  40 <div class="collapse">
  41 <input type="checkbox" id="collapse-section9" checked aria-hidden="true"> <label for="collapse-section9" aria-hidden="true"><strong>V1.7.0 / 06-December-2019</strong></label>
  42 <div>
  43 <h2 id="main-changes">Main Changes</h2>
  44 <ul>
  45 <li><p>General updates to align Bit and registers definition with the STM32H7 reference manual</p></li>
  46 <li>Add support of stm32h7A3xx, stm32h7A3xxQ, stm32h7B3xx, stm32h7B3xxQ, stm32h7B0xx and stm32h7B0xxQ devices:
  47 <ul>
  48 <li>Add “stm32h7a3xx.h”, “stm32h7a3xxq.h”, “stm32h7b3xx.h”, “stm32h7b3xxq.h”, “stm32h7b0xx.h” and “stm32h7b0xxq.h” files</li>
  49 <li>Add startup files “startup_stm32h7a3xx.s”, “startup_stm32h7a3xxq.s”, “startup_stm32h7b3xx.s”, “startup_stm32h7b3xxq.s”, “startup_stm32h7b0xx.s” and “startup_stm32h7b0xxq.s” for EWARM , MDK-ARM and STM32CubeIDE toolchains</li>
  50 <li>Add part numbers list to stm32h7xx.h header file:
  51 <ul>
  52 <li>STM32H7A3xx : STM32H7A3IIK6, STM32H7A3IIT6, STM32H7A3NIH6, STM32H7A3RIT6, STM32H7A3VIH6, STM32H7A3VIT6, STM32H7A3ZIT6</li>
  53 <li>STM32H7A3xxQ : STM32H7A3QIY6Q, STM32H7A3IIK6Q, STM32H7A3IIT6Q, STM32H7A3LIH6Q, STM32H7A3VIH6Q, STM32H7A3VIT6Q, STM32H7A3AII6Q, STM32H7A3ZIT6Q</li>
  54 <li>STM32H7B3xx : STM32H7B3IIK6, STM32H7B3IIT6, STM32H7B3NIH6, STM32H7B3RIT6, STM32H7B3VIH6, STM32H7B3VIT6, STM32H7B3ZIT6</li>
  55 <li>STM32H7B3xxQ : STM32H7B3QIY6Q, STM32H7B3IIK6Q, STM32H7B3IIT6Q, STM32H7B3LIH6Q, STM32H7B3VIH6Q, STM32H7B3VIT6Q, STM32H7B3AII6Q, STM32H7B3ZIT6Q</li>
  56 <li>STM32H7B0xx : STM32H7B0ABIxQ, STM32H7B0IBTx, STM32H7B0RBTx, STM32H7B0VBTx, STM32H7B0ZBTx, STM32H7B0IBKxQ</li>
  57 </ul></li>
  58 </ul></li>
  59 <li>Update DMA2D bits definitions: Update to support Line offset mode and swap bytes features
  60 <ul>
  61 <li>Add CR_LOM (Line Ofset Mode) bit definition, Add OPFCCR_SB (Swap Bytes) bit definition</li>
  62 <li>Update CR_MODE, FGOR_LO, BGOR_LO and OOR_LO bit definition</li>
  63 </ul></li>
  64 <li>Update USB_OTG_GAHBCFG bit definition: to be aligned with LL_USB usage</li>
  65 <li><p>Add USB_OTG_DOEPMSK_AHBERRM, USB_OTG_DOEPMSK_BERRM, USB_OTG_DOEPMSK_NAKM, USB_OTG_DOEPMSK_NYETM, USB_OTG_DIEPINT_AHBERR, USB_OTG_DIEPINT_INEPNM, USB_OTG_DOEPINT_AHBERR, USB_OTG_DOEPINT_OUTPKTERR, USB_OTG_DOEPINT_BERR, USB_OTG_DOEPINT_NAK and USB_OTG_DOEPINT_STPKTRX bit definitions</p></li>
  66 <li><p>Update IS_TIM_REMAP_INSTANCE and IS_TIM_SYNCHRO_INSTANCE macro implemenation</p></li>
  67 </ul>
  68 </div>
  69 </div>
  70 <div class="collapse">
  71 <input type="checkbox" id="collapse-section8" aria-hidden="true"> <label for="collapse-section8" aria-hidden="true"><strong>V1.6.0 / 28-June-2019</strong></label>
  72 <div>
  73 <h2 id="main-changes-1">Main Changes</h2>
  74 <ul>
  75 <li>Add definition of “ART_TypeDef” structure: ART accelerator for Cortex-M4 available in Dual Core devices</li>
  76 <li>Add definition of “ART” instance: pointer to “ART_TypeDef” structure</li>
  77 <li>Add definition of “ART” bit fields: ART_CTR_EN and ART_CTR_PCACHEADDR<br />
  78 </li>
  79 <li>Update definitions of “HRTIM1_TIMA” to “HRTIM1_TIME” : pointer to HRTIM_Timerx_TypeDef structure instead of HRTIM_TIM_TypeDef</li>
  80 <li>Fix Typo in “ETH_TypeDef” definition: use uint32_t for “RESERVED16” registers instead of int32_t</li>
  81 <li>Remove useless definition of “SDMMC” instance (keep only definitions of “SDMMC1” and “SDMMC2”)</li>
  82 </ul>
  83 </div>
  84 </div>
  85 <div class="collapse">
  86 <input type="checkbox" id="collapse-section7" aria-hidden="true"> <label for="collapse-section7" aria-hidden="true"><strong>V1.5.0 / 05-April-2019</strong></label>
  87 <div>
  88 <h2 id="main-changes-2">Main Changes</h2>
  89 <ul>
  90 <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
  91 <li>Updates to aligned with STM32H7xx <strong>rev.V</strong> devices</li>
  92 <li>Add support of stm32h745xx, stm32h747xx, stm32h755xx, stm32h757xx <strong>Dual Core</strong> devices and STM32H742xx (new single core device):
  93 <ul>
  94 <li>Add “stm32h745xx.h” , “stm32h747xx.h”, “stm32h755xx.h”, “stm32h757xx.h” and “stm32h742xx.h” files</li>
  95 <li>Add startup files “startup_stm32h745xx.s”, “startup_stm32h747xx.s”, “startup_stm32h755xx.s”, “startup_stm32h757xx.s” and “startup_stm32h742xx.s” for EWARM , MDK-ARM and SW4STM32 toolchains</li>
  96 <li>Add part numbers list to stm32h7xx.h header file:
  97 <ul>
  98 <li>STM32H742xx: STM32H742VI, STM32H742ZI, STM32H742AI, STM32H742II, STM32H742BI, STM32H742XI</li>
  99 <li>STM32H743xx: STM32H743VI, STM32H743ZI, STM32H743AI, STM32H743II, STM32H743BI, STM32H743XI</li>
 100 <li>STM32H753xx: STM32H753VI, STM32H753ZI, STM32H753AI, STM32H753II, STM32H753BI, STM32H753XI</li>
 101 <li>STM32H750xx: STM32H750V, STM32H750I, STM32H750X</li>
 102 <li>STM32H747xx: STM32H747ZI, STM32H747AI, STM32H747II, STM32H747BI, STM32H747XI</li>
 103 <li>STM32H757xx: STM32H757ZI, STM32H757AI, STM32H757II, STM32H757BI, STM32H757XI</li>
 104 <li>STM32H745xx: STM32H745ZI, STM32H745II, STM32H745BI, STM32H745XI</li>
 105 <li><p>STM32H755xx: STM32H755ZI, STM32H755II, STM32H755BI, STM32H755XI</p></li>
 106 <li>Add system_stm32h7xx_singlecore.c : system initialization template source file for single core lines (STM32H743xx, STM32H753xx, STM32H750xx and STM32H742xx)</li>
 107 <li>Add system initialization template source file for dual core lines:
 108 <ul>
 109 <li>system_stm32h7xx_dualcore_boot_cm4_cm7.c: template for the boot case where Cortex-M7 and Cortex-M4 are boot at once</li>
 110 <li>system_stm32h7xx_dualcore_bootcm7_cm4gated.c: template for the boot case where Cortex-M7 is booting and Cortex-M4 is gated using FLASH Option Bytes</li>
 111 <li>system_stm32h7xx_dualcore_bootcm4_cm7gated.c: template for the boot case where Cortex-M4 is booting and Cortex-M7 is gated using FLASH Option Bytes</li>
 112 </ul></li>
 113 <li>Add EWARM, MDK-ARM and SW4STM32 <strong>Dual Core</strong> devices linker files</li>
 114 <li><p>Add EWARM STM32H742xx devices linker files</p></li>
 115 </ul></li>
 116 </ul></li>
 117 <li><strong>Registers and bit field definitions updates</strong>:
 118 <ul>
 119 <li>Update SYSCFG_TypeDef structure to add
 120 <ul>
 121 <li>Add CFGR register: allowing to control connection between double ECC RAMs/Flash errors, PVD errors and CortexM7/M4 lockup to TIM1/8/15/16/17 and HRTIMER Break inputs</li>
 122 <li>Add definitions of SYSCFG_CFGR register bit fields</li>
 123 <li>PWRCR registers: allowing to control the PWR overdrive enable/disable for Voltage Scaling zero</li>
 124 <li>Add SYSCFG_PWRCR register bit fields</li>
 125 </ul></li>
 126 <li>Update RCC_TypeDef structure according to STM32H7xx <strong>Rev.V</strong> devices:
 127 <ul>
 128 <li>ICSCR: renamed to HSICFGR, HSI Clock Calibration Register</li>
 129 <li>Rename also RCC_ICSCR_XXX bit definitions RCC_HSICFGR_XXX according to the new register HSICFGR</li>
 130 <li>CSICFGR: New registers (on <strong>Rev.V</strong> devices), CSI Clock Calibration Register</li>
 131 <li>Add dedicated RCC_CSICFGR_XXX bit definitions</li>
 132 </ul></li>
 133 <li>Keep RCC_Core_TypeDef structure used for Dual Core lines devices only: allowing RCC clock enabling/allocation for each Core(Cortex-M7/M4)
 134 <ul>
 135 <li>RCC_Core_TypeDef structure and RCC_C1_BASE/RCC_C1 definition removed from STM32H743xx/53xx and STM32H750xx lines</li>
 136 </ul></li>
 137 <li>Add CRYP_CR_NPBLB bit field definition: upon refresh of the CRYP peripheral on the STM32H7 <strong>Rev.V</strong> devices</li>
 138 <li>Update ADC_CR_BOOST bot field definition for STM32H7 <strong>Rev.V</strong> devices: 2 bits instead of 1</li>
 139 <li>Remove useless I2C_CR1_SWRST definition: alignment with the reference manual</li>
 140 <li>Add SAI_xCR1_NODIV bit field definition upon SAI peripheral update for STM32H7 <strong>Rev.V</strong> devices</li>
 141 <li>Rename SPI_TXCRC_RXCRC to SPI_RXCRC_RXCRC: typo fix and alignment with the reference manual</li>
 142 <li>Fix QUADSPI_SR_FLEVEL bit field definition: Mask on 6 bits (0x3F mask) instead of 5 bits(0x1F mask) and add definition of QUADSPI_SR_FLEVEL_6</li>
 143 <li>Add definition of SYSCFG_EXTICR3_EXTI8_PK, SYSCFG_EXTICR3_EXTI9_PK, SYSCFG_EXTICR3_EXTI10_PK, SYSCFG_EXTICR3_EXTI11_PK and SYSCFG_EXTICR4_EXTI13_PK</li>
 144 <li>Add definition of FLASH_LATENCY_DEFAULT: default safe FLASH latency</li>
 145 </ul></li>
 146 </ul>
 147 </div>
 148 </div>
 149 <div class="collapse">
 150 <input type="checkbox" id="collapse-section6" aria-hidden="true"> <label for="collapse-section6" aria-hidden="true"><strong>V1.3.1 / 31-January-2019</strong></label>
 151 <div>
 152 <h2 id="main-changes-3">Main Changes</h2>
 153 <ul>
 154 <li><strong>Patch Release on top of V1.3.0</strong></li>
 155 <li>Add Definition of UID_BASE ( Unique device ID register base address) to the STM32H7xx include files:
 156 <ul>
 157 <li>stm32h743xx.h, stm32h750xx.h and stm32h753xx.h</li>
 158 </ul></li>
 159 </ul>
 160 </div>
 161 </div>
 162 <div class="collapse">
 163 <input type="checkbox" id="collapse-section5" aria-hidden="true"> <label for="collapse-section5" aria-hidden="true"><strong>V1.4.0 / 30-November-2018</strong></label>
 164 <div>
 165 <h2 id="main-changes-4">Main Changes</h2>
 166 <ul>
 167 <li>STM32H7xx include files:
 168 <ul>
 169 <li>General updates to align Bit and registers definition with the STM32H7 reference manual</li>
 170 <li>Update "_Mask" bits definition using UL suffix for Misra-C 2012 compliance</li>
 171 <li>Add definition of <strong>RAMECC_MonitorTypeDef</strong> and <strong>RAMECC_TypeDef</strong> structure</li>
 172 <li>Add definition of <strong>RAMECC</strong> peripheral base addresses</li>
 173 <li>Add <strong>RAMECC</strong> peripheral registers bit definitions</li>
 174 <li>Add IS_RAMECC_MONITOR_ALL_INSTANCE macro</li>
 175 <li>Add <strong>EXTI</strong> SWIER3 bit definitions</li>
 176 <li>Update <strong>FLASH</strong> sector number to 8 instead of 16 (8 sectors for each bank)</li>
 177 <li>Remove extra bit definition : FLASH_CR_SNB_3 to FLASH_CR_SNB_7</li>
 178 <li>Update <strong>FLASH</strong> user option bytes bit definition</li>
 179 <li>Fix FLASH_BANK_SIZE definition: add parenthesis</li>
 180 <li>Remove <strong>PWR</strong> extra bit definition PWR_CR1_RLPSN</li>
 181 <li>Add <strong>PWR</strong> bit definition PWR_WKUPEPR_WKUPEN</li>
 182 <li>Fix typo in <strong>SDMMC</strong> bit definition: SDMMC_MASK_SDIOITIE_Pos, SDMMC_MASK_SDIOITIE_Msk and SDMMC_MASK_SDIOITIE</li>
 183 <li>Add <strong>SDMMC</strong> instance check macro: IS_SDMMC_ALL_INSTANCE</li>
 184 <li>Fix typo in <strong>SYSCFG</strong> bit definition: SYSCFG_PMCR_EPIS_SEL_Pos, SYSCFG_PMCR_EPIS_SEL_Msk, SYSCFG_PMCR_EPIS_SEL and SYSCFG_PMCR_EPIS_SEL_0 to SYSCFG_PMCR_EPIS_SEL_2</li>
 185 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR1_EXTI0_Msk, to SYSCFG_EXTICR1_EXTI3_Msk, 4 bits instead of 3</li>
 186 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR2_EXTI0_Msk, to SYSCFG_EXTICR2_EXTI3_Msk, 4 bits instead of 3</li>
 187 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR3_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI3_Msk, 4 bits instead of 3</li>
 188 <li>Fix <strong>SYSCFG</strong> bit definitions: SYSCFG_EXTICR4_EXTI0_Msk, to SYSCFG_EXTICR3_EXTI4_Msk, 4 bits instead of 3</li>
 189 <li>Fix IS_ADC_COMMON_INSTANCE macro : add parenthesis</li>
 190 <li>Fix HSEM_CR_COREID_CURRENT and HSEM_CR_COREID_CURRENT: add parenthesis</li>
 191 <li>Update <strong>USART</strong> and <strong>SMARTCARD</strong> bits definition</li>
 192 <li>Update <strong>GPIO</strong> registers and bit definition (BSRR register)</li>
 193 <li>Add IS_GPIO_AF_INSTANCE macro</li>
 194 <li>Update <strong>DAC</strong> bits definition</li>
 195 <li>Update <strong>FDCAN</strong> bits definition</li>
 196 <li>Update <strong>USB</strong> bits definition (OTEPSPRM register)</li>
 197 <li>Fix <strong>CEC</strong> bit definition (RXDR register)</li>
 198 <li>Update <strong>TIM</strong> registers and bits definition naming</li>
 199 <li>Fix IS_TIM_CCX_INSTANCE macro : add TIM_CHANNEL_4 to TIM_CHANNEL_6</li>
 200 <li>Update <strong>SPI</strong> and <strong>I2S</strong> bits definition</li>
 201 <li>Update <strong>BDMA</strong> bits definition</li>
 202 <li>Update <strong>FMC</strong> bits definition</li>
 203 </ul></li>
 204 </ul>
 205 </div>
 206 </div>
 207 <div class="collapse">
 208 <input type="checkbox" id="collapse-section4" aria-hidden="true"> <label for="collapse-section4" aria-hidden="true"><strong>V1.3.0 / 29-June-2018</strong></label>
 209 <div>
 210 <h2 id="main-changes-5">Main Changes</h2>
 211 <ul>
 212 <li>Add support for stm32h750xx value line devices:
 213 <ul>
 214 <li>Add “stm32h750xx.h” file</li>
 215 <li>Add startup files startup_stm32h750xx.s for EWARM, MDK-ARM and SW4STM32</li>
 216 </ul></li>
 217 </ul>
 218 </div>
 219 </div>
 220 <div class="collapse">
 221 <input type="checkbox" id="collapse-section3"  aria-hidden="true"> <label for="collapse-section3" aria-hidden="true"><strong>V1.2.0 / 29-December-2017</strong></label>
 222 <div>
 223 <h2 id="main-changes-6">Main Changes</h2>
 224 <ul>
 225 <li>Update FDCAN bit definition</li>
 226 <li>Update SystemCoreClockUpdate() function in system_stm32h7xx.c file to use direct register access</li>
 227 </ul>
 228 </div>
 229 </div>
 230 <div class="collapse">
 231 <input type="checkbox" id="collapse-section2" aria-hidden="true"> <label for="collapse-section2" aria-hidden="true"><strong>V1.1.0 / 31-August-2017</strong></label>
 232 <div>
 233 <h2 id="main-changes-7">Main Changes</h2>
 234 <ul>
 235 <li>Update USB OTG bit definition</li>
 236 <li>Adjust PLL fractional computation</li>
 237 </ul>
 238 </div>
 239 </div>
 240 <div class="collapse">
 241 <input type="checkbox" id="collapse-section1" aria-hidden="true"> <label for="collapse-section1" aria-hidden="true"><strong>V1.0.0 / 21-April-2017</strong></label>
 242 <div>
 243 <h2 id="main-changes-8">Main Changes</h2>
 244 <ul>
 245 <li>First official release for <strong>STM32H743xx/753xx</strong> devices</li>
 246 </ul>
 247 </div>
 248 </div>
 249 </div>
 250 </div>
 251 <footer class="sticky">
 252 For complete documentation on STM32 Microcontrollers </mark> , visit: <span style="font-color: blue;"><a href="http://www.st.com/stm32">www.st.com/stm32</a></span>
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