Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_eth.h
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1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_eth.h
4 * @author MCD Application Team
5 * @brief Header file of ETH HAL module.
6 ******************************************************************************
7 * @attention
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_ETH_H
22 #define STM32H7xx_HAL_ETH_H
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
28 #if defined(ETH)
29 /* Includes ------------------------------------------------------------------*/
30 #include "stm32h7xx_hal_def.h"
32 /** @addtogroup STM32H7xx_HAL_Driver
33 * @{
36 /** @addtogroup ETH
37 * @{
38 */
40 /* Exported types ------------------------------------------------------------*/
41 #ifndef ETH_TX_DESC_CNT
42 #define ETH_TX_DESC_CNT 4U
43 #endif
45 #ifndef ETH_RX_DESC_CNT
46 #define ETH_RX_DESC_CNT 4U
47 #endif
49 /*********************** Descriptors struct def section ************************/
50 /** @defgroup ETH_Exported_Types ETH Exported Types
51 * @{
54 /**
55 * @brief ETH DMA Descriptor structure definition
57 typedef struct
59 __IO uint32_t DESC0;
60 __IO uint32_t DESC1;
61 __IO uint32_t DESC2;
62 __IO uint32_t DESC3;
63 __IO uint32_t BackupAddr0; /* used to store rx buffer 1 address */
64 __IO uint32_t BackupAddr1; /* used to store rx buffer 2 address */
65 }ETH_DMADescTypeDef;
66 /**
70 /**
71 * @brief ETH Buffers List structure definition
73 typedef struct __ETH_BufferTypeDef
75 uint8_t *buffer; /*<! buffer address */
77 uint32_t len; /*<! buffer length */
79 struct __ETH_BufferTypeDef *next; /*<! Pointer to the next buffer in the list */
80 }ETH_BufferTypeDef;
81 /**
85 /**
86 * @brief DMA Transmit Descriptors Wrapper structure definition
88 typedef struct
90 uint32_t TxDesc[ETH_TX_DESC_CNT]; /*<! Tx DMA descriptors addresses */
92 uint32_t CurTxDesc; /*<! Current Tx descriptor index for packet transmission */
94 }ETH_TxDescListTypeDef;
95 /**
99 /**
100 * @brief Transmit Packet Configuration structure definition
102 typedef struct
104 uint32_t Attributes; /*!< Tx packet HW features capabilities.
105 This parameter can be a combination of @ref ETH_Tx_Packet_Attributes*/
107 uint32_t Length; /*!< Total packet length */
109 ETH_BufferTypeDef *TxBuffer; /*!< Tx buffers pointers */
111 uint32_t SrcAddrCtrl; /*!< Specifies the source address insertion control.
112 This parameter can be a value of @ref ETH_Tx_Packet_Source_Addr_Control */
114 uint32_t CRCPadCtrl; /*!< Specifies the CRC and Pad insertion and replacement control.
115 This parameter can be a value of @ref ETH_Tx_Packet_CRC_Pad_Control */
117 uint32_t ChecksumCtrl; /*!< Specifies the checksum insertion control.
118 This parameter can be a value of @ref ETH_Tx_Packet_Checksum_Control */
120 uint32_t MaxSegmentSize; /*!< Sets TCP maximum segment size only when TCP segmentation is enabled.
121 This parameter can be a value from 0x0 to 0x3FFF */
123 uint32_t PayloadLen; /*!< Sets Total payload length only when TCP segmentation is enabled.
124 This parameter can be a value from 0x0 to 0x3FFFF */
126 uint32_t TCPHeaderLen; /*!< Sets TCP header length only when TCP segmentation is enabled.
127 This parameter can be a value from 0x5 to 0xF */
129 uint32_t VlanTag; /*!< Sets VLAN Tag only when VLAN is enabled.
130 This parameter can be a value from 0x0 to 0xFFFF*/
132 uint32_t VlanCtrl; /*!< Specifies VLAN Tag insertion control only when VLAN is enabled.
133 This parameter can be a value of @ref ETH_Tx_Packet_VLAN_Control */
135 uint32_t InnerVlanTag; /*!< Sets Inner VLAN Tag only when Inner VLAN is enabled.
136 This parameter can be a value from 0x0 to 0x3FFFF */
138 uint32_t InnerVlanCtrl; /*!< Specifies Inner VLAN Tag insertion control only when Inner VLAN is enabled.
139 This parameter can be a value of @ref ETH_Tx_Packet_Inner_VLAN_Control */
141 }ETH_TxPacketConfig;
142 /**
146 /**
147 * @brief DMA Receive Descriptors Wrapper structure definition
149 typedef struct
151 uint32_t RxDesc[ETH_RX_DESC_CNT]; /*<! Rx DMA descriptors addresses. */
153 uint32_t CurRxDesc; /*<! Current Rx descriptor, ready for next reception. */
155 uint32_t FirstAppDesc; /*<! First descriptor of last received packet. */
157 uint32_t AppDescNbr; /*<! Number of descriptors of last received packet. */
159 uint32_t AppContextDesc; /*<! If 1 a context descriptor is present in last received packet.
160 If 0 no context descriptor is present in last received packet. */
162 uint32_t ItMode; /*<! If 1, DMA will generate the Rx complete interrupt.
163 If 0, DMA will not generate the Rx complete interrupt. */
164 }ETH_RxDescListTypeDef;
165 /**
169 /**
170 * @brief Received Packet Information structure definition
172 typedef struct
174 uint32_t SegmentCnt; /*<! Number of Rx Descriptors */
176 uint32_t VlanTag; /*<! Vlan Tag value */
178 uint32_t InnerVlanTag; /*<! Inner Vlan Tag value */
180 uint32_t Checksum; /*<! Rx Checksum status.
181 This parameter can be a value of @ref ETH_Rx_Checksum_Status */
183 uint32_t HeaderType; /*<! IP header type.
184 This parameter can be a value of @ref ETH_Rx_IP_Header_Type */
186 uint32_t PayloadType; /*<! Payload type.
187 This parameter can be a value of @ref ETH_Rx_Payload_Type */
189 uint32_t MacFilterStatus; /*<! MAC filter status.
190 This parameter can be a value of @ref ETH_Rx_MAC_Filter_Status */
192 uint32_t L3FilterStatus; /*<! L3 filter status
193 This parameter can be a value of @ref ETH_Rx_L3_Filter_Status */
195 uint32_t L4FilterStatus; /*<! L4 filter status
196 This parameter can be a value of @ref ETH_Rx_L4_Filter_Status */
198 uint32_t ErrorCode; /*<! Rx error code
199 This parameter can be a combination of @ref ETH_Rx_Error_Code */
201 } ETH_RxPacketInfo;
202 /**
206 /**
207 * @brief ETH MAC Configuration Structure definition
209 typedef struct
211 uint32_t SourceAddrControl; /*!< Selects the Source Address Insertion or Replacement Control.
212 This parameter can be a value of @ref ETH_Source_Addr_Control */
214 FunctionalState ChecksumOffload; /*!< Enables or Disable the checksum checking for received packet payloads TCP, UDP or ICMP headers */
216 uint32_t InterPacketGapVal; /*!< Sets the minimum IPG between Packet during transmission.
217 This parameter can be a value of @ref ETH_Inter_Packet_Gap */
219 FunctionalState GiantPacketSizeLimitControl; /*!< Enables or disables the Giant Packet Size Limit Control. */
221 FunctionalState Support2KPacket; /*!< Enables or disables the IEEE 802.3as Support for 2K length Packets */
223 FunctionalState CRCStripTypePacket; /*!< Enables or disables the CRC stripping for Type packets.*/
225 FunctionalState AutomaticPadCRCStrip; /*!< Enables or disables the Automatic MAC Pad/CRC Stripping.*/
227 FunctionalState Watchdog; /*!< Enables or disables the Watchdog timer on Rx path
228 When enabled, the MAC allows no more then 2048 bytes to be received.
229 When disabled, the MAC can receive up to 16384 bytes. */
231 FunctionalState Jabber; /*!< Enables or disables Jabber timer on Tx path
232 When enabled, the MAC allows no more then 2048 bytes to be sent.
233 When disabled, the MAC can send up to 16384 bytes. */
235 FunctionalState JumboPacket; /*!< Enables or disables receiving Jumbo Packet
236 When enabled, the MAC allows jumbo packets of 9,018 bytes
237 without reporting a giant packet error */
239 uint32_t Speed; /*!< Sets the Ethernet speed: 10/100 Mbps.
240 This parameter can be a value of @ref ETH_Speed */
242 uint32_t DuplexMode; /*!< Selects the MAC duplex mode: Half-Duplex or Full-Duplex mode
243 This parameter can be a value of @ref ETH_Duplex_Mode */
245 FunctionalState LoopbackMode; /*!< Enables or disables the loopback mode */
247 FunctionalState CarrierSenseBeforeTransmit; /*!< Enables or disables the Carrier Sense Before Transmission in Full Duplex Mode. */
249 FunctionalState ReceiveOwn; /*!< Enables or disables the Receive Own in Half Duplex mode. */
251 FunctionalState CarrierSenseDuringTransmit; /*!< Enables or disables the Carrier Sense During Transmission in the Half Duplex mode */
253 FunctionalState RetryTransmission; /*!< Enables or disables the MAC retry transmission, when a collision occurs in Half Duplex mode.*/
255 uint32_t BackOffLimit; /*!< Selects the BackOff limit value.
256 This parameter can be a value of @ref ETH_Back_Off_Limit */
258 FunctionalState DeferralCheck; /*!< Enables or disables the deferral check function in Half Duplex mode. */
260 uint32_t PreambleLength; /*!< Selects or not the Preamble Length for Transmit packets (Full Duplex mode).
261 This parameter can be a value of @ref ETH_Preamble_Length */
263 FunctionalState UnicastSlowProtocolPacketDetect; /*!< Enable or disables the Detection of Slow Protocol Packets with unicast address. */
265 FunctionalState SlowProtocolDetect; /*!< Enable or disables the Slow Protocol Detection. */
267 FunctionalState CRCCheckingRxPackets; /*!< Enable or disables the CRC Checking for Received Packets. */
269 uint32_t GiantPacketSizeLimit; /*!< Specifies the packet size that the MAC will declare it as Giant, If it's size is
270 greater than the value programmed in this field in units of bytes
271 This parameter must be a number between Min_Data = 0x618 (1518 byte) and Max_Data = 0x3FFF (32 Kbyte)*/
273 FunctionalState ExtendedInterPacketGap; /*!< Enable or disables the extended inter packet gap. */
275 uint32_t ExtendedInterPacketGapVal; /*!< Sets the Extended IPG between Packet during transmission.
276 This parameter can be a value from 0x0 to 0xFF */
278 FunctionalState ProgrammableWatchdog; /*!< Enable or disables the Programmable Watchdog.*/
280 uint32_t WatchdogTimeout; /*!< This field is used as watchdog timeout for a received packet
281 This parameter can be a value of @ref ETH_Watchdog_Timeout */
283 uint32_t PauseTime; /*!< This field holds the value to be used in the Pause Time field in the transmit control packet.
284 This parameter must be a number between Min_Data = 0x0 and Max_Data = 0xFFFF */
286 FunctionalState ZeroQuantaPause; /*!< Enable or disables the automatic generation of Zero Quanta Pause Control packets.*/
288 uint32_t PauseLowThreshold; /*!< This field configures the threshold of the PAUSE to be checked for automatic retransmission of PAUSE Packet.
289 This parameter can be a value of @ref ETH_Pause_Low_Threshold */
291 FunctionalState TransmitFlowControl; /*!< Enables or disables the MAC to transmit Pause packets in Full Duplex mode
292 or the MAC back pressure operation in Half Duplex mode */
294 FunctionalState UnicastPausePacketDetect; /*!< Enables or disables the MAC to detect Pause packets with unicast address of the station */
296 FunctionalState ReceiveFlowControl; /*!< Enables or disables the MAC to decodes the received Pause packet
297 and disables its transmitter for a specified (Pause) time */
299 uint32_t TransmitQueueMode; /*!< Specifies the Transmit Queue operating mode.
300 This parameter can be a value of @ref ETH_Transmit_Mode */
302 uint32_t ReceiveQueueMode; /*!< Specifies the Receive Queue operating mode.
303 This parameter can be a value of @ref ETH_Receive_Mode */
305 FunctionalState DropTCPIPChecksumErrorPacket; /*!< Enables or disables Dropping of TCPIP Checksum Error Packets. */
307 FunctionalState ForwardRxErrorPacket; /*!< Enables or disables forwarding Error Packets. */
309 FunctionalState ForwardRxUndersizedGoodPacket; /*!< Enables or disables forwarding Undersized Good Packets.*/
310 } ETH_MACConfigTypeDef;
311 /**
315 /**
316 * @brief ETH DMA Configuration Structure definition
318 typedef struct
320 uint32_t DMAArbitration; /*!< Sets the arbitration scheme between DMA Tx and Rx
321 This parameter can be a value of @ref ETH_DMA_Arbitration */
323 FunctionalState AddressAlignedBeats; /*!< Enables or disables the AHB Master interface address aligned
324 burst transfers on Read and Write channels */
326 uint32_t BurstMode; /*!< Sets the AHB Master interface burst transfers.
327 This parameter can be a value of @ref ETH_Burst_Mode */
329 FunctionalState RebuildINCRxBurst; /*!< Enables or disables the AHB Master to rebuild the pending beats
330 of any initiated burst transfer with INCRx and SINGLE transfers. */
332 FunctionalState PBLx8Mode; /*!< Enables or disables the PBL multiplication by eight. */
334 uint32_t TxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Tx DMA transaction.
335 This parameter can be a value of @ref ETH_Tx_DMA_Burst_Length */
337 FunctionalState SecondPacketOperate; /*!< Enables or disables the Operate on second Packet mode, which allows the DMA to process a second
338 Packet of Transmit data even before obtaining the status for the first one. */
340 uint32_t RxDMABurstLength; /*!< Indicates the maximum number of beats to be transferred in one Rx DMA transaction.
341 This parameter can be a value of @ref ETH_Rx_DMA_Burst_Length */
343 FunctionalState FlushRxPacket; /*!< Enables or disables the Rx Packet Flush */
345 FunctionalState TCPSegmentation; /*!< Enables or disables the TCP Segmentation */
347 uint32_t MaximumSegmentSize; /*!< Sets the maximum segment size that should be used while segmenting the packet
348 This parameter can be a value from 0x40 to 0x3FFF */
349 } ETH_DMAConfigTypeDef;
350 /**
354 /**
355 * @brief HAL ETH Media Interfaces enum definition
357 typedef enum
359 HAL_ETH_MII_MODE = 0x00U, /*!< Media Independent Interface */
360 HAL_ETH_RMII_MODE = 0x01U /*!< Reduced Media Independent Interface */
361 }ETH_MediaInterfaceTypeDef;
362 /**
366 /**
367 * @brief ETH Init Structure definition
369 typedef struct
372 uint8_t *MACAddr; /*!< MAC Address of used Hardware: must be pointer on an array of 6 bytes */
374 ETH_MediaInterfaceTypeDef MediaInterface; /*!< Selects the MII interface or the RMII interface. */
376 ETH_DMADescTypeDef *TxDesc; /*!< Provides the address of the first DMA Tx descriptor in the list */
378 ETH_DMADescTypeDef *RxDesc; /*!< Provides the address of the first DMA Rx descriptor in the list */
380 uint32_t RxBuffLen; /*!< Provides the length of Rx buffers size */
382 }ETH_InitTypeDef;
383 /**
387 /**
388 * @brief HAL State structures definition
390 typedef uint32_t HAL_ETH_StateTypeDef;
391 /**
395 /**
396 * @brief ETH Handle Structure definition
398 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
399 typedef struct __ETH_HandleTypeDef
400 #else
401 typedef struct
402 #endif
404 ETH_TypeDef *Instance; /*!< Register base address */
406 ETH_InitTypeDef Init; /*!< Ethernet Init Configuration */
408 ETH_TxDescListTypeDef TxDescList; /*!< Tx descriptor wrapper: holds all Tx descriptors list
409 addresses and current descriptor index */
411 ETH_RxDescListTypeDef RxDescList; /*!< Rx descriptor wrapper: holds all Rx descriptors list
412 addresses and current descriptor index */
414 HAL_LockTypeDef Lock; /*!< Locking object */
416 __IO HAL_ETH_StateTypeDef gState; /*!< ETH state information related to global Handle management
417 and also related to Tx operations.
418 This parameter can be a value of @ref HAL_ETH_StateTypeDef */
420 __IO HAL_ETH_StateTypeDef RxState; /*!< ETH state information related to Rx operations.
421 This parameter can be a value of @ref HAL_ETH_StateTypeDef */
423 __IO uint32_t ErrorCode; /*!< Holds the global Error code of the ETH HAL status machine
424 This parameter can be a value of of @ref ETH_Error_Code */
426 __IO uint32_t DMAErrorCode; /*!< Holds the DMA Rx Tx Error code when a DMA AIS interrupt occurs
427 This parameter can be a combination of @ref ETH_DMA_Status_Flags */
429 __IO uint32_t MACErrorCode; /*!< Holds the MAC Rx Tx Error code when a MAC Rx or Tx status interrupt occurs
430 This parameter can be a combination of @ref ETH_MAC_Rx_Tx_Status */
432 __IO uint32_t MACWakeUpEvent; /*!< Holds the Wake Up event when the MAC exit the power down mode
433 This parameter can be a value of @ref ETH_MAC_Wake_Up_Event */
435 __IO uint32_t MACLPIEvent; /*!< Holds the LPI event when the an LPI status interrupt occurs.
436 This parameter can be a value of @ref ETHEx_LPI_Event */
438 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
440 void (* TxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Tx Complete Callback */
441 void (* RxCpltCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Rx Complete Callback */
442 void (* DMAErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH DMA Error Callback */
443 void (* MACErrorCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH MAC Error Callback */
444 void (* PMTCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Power Management Callback */
445 void (* EEECallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH EEE Callback */
446 void (* WakeUpCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Wake UP Callback */
448 void (* MspInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp Init callback */
449 void (* MspDeInitCallback) ( struct __ETH_HandleTypeDef * heth); /*!< ETH Msp DeInit callback */
451 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
453 } ETH_HandleTypeDef;
454 /**
458 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
460 * @brief HAL ETH Callback ID enumeration definition
462 typedef enum
464 HAL_ETH_MSPINIT_CB_ID = 0x00U, /*!< ETH MspInit callback ID */
465 HAL_ETH_MSPDEINIT_CB_ID = 0x01U, /*!< ETH MspDeInit callback ID */
467 HAL_ETH_TX_COMPLETE_CB_ID = 0x02U, /*!< ETH Tx Complete Callback ID */
468 HAL_ETH_RX_COMPLETE_CB_ID = 0x03U, /*!< ETH Rx Complete Callback ID */
469 HAL_ETH_DMA_ERROR_CB_ID = 0x04U, /*!< ETH DMA Error Callback ID */
470 HAL_ETH_MAC_ERROR_CB_ID = 0x05U, /*!< ETH MAC Error Callback ID */
471 HAL_ETH_PMT_CB_ID = 0x06U, /*!< ETH Power Management Callback ID */
472 HAL_ETH_EEE_CB_ID = 0x07U, /*!< ETH EEE Callback ID */
473 HAL_ETH_WAKEUP_CB_ID = 0x08U /*!< ETH Wake UP Callback ID */
476 }HAL_ETH_CallbackIDTypeDef;
479 * @brief HAL ETH Callback pointer definition
481 typedef void (*pETH_CallbackTypeDef)(ETH_HandleTypeDef * heth); /*!< pointer to an ETH callback function */
483 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
485 /**
486 * @brief ETH MAC filter structure definition
488 typedef struct{
489 FunctionalState PromiscuousMode; /*!< Enable or Disable Promiscuous Mode */
491 FunctionalState ReceiveAllMode; /*!< Enable or Disable Receive All Mode */
493 FunctionalState HachOrPerfectFilter; /*!< Enable or Disable Perfect filtering in addition to Hash filtering */
495 FunctionalState HashUnicast; /*!< Enable or Disable Hash filtering on unicast packets */
497 FunctionalState HashMulticast; /*!< Enable or Disable Hash filtering on multicast packets */
499 FunctionalState PassAllMulticast; /*!< Enable or Disable passing all multicast packets */
501 FunctionalState SrcAddrFiltering; /*!< Enable or Disable source address filtering module */
503 FunctionalState SrcAddrInverseFiltering; /*!< Enable or Disable source address inverse filtering */
505 FunctionalState DestAddrInverseFiltering; /*!< Enable or Disable destination address inverse filtering */
507 FunctionalState BroadcastFilter; /*!< Enable or Disable broadcast filter */
509 uint32_t ControlPacketsFilter; /*!< Set the control packets filter
510 This parameter can be a value of @ref ETH_Control_Packets_Filter */
511 }ETH_MACFilterConfigTypeDef;
512 /**
516 /**
517 * @brief ETH Power Down structure definition
519 typedef struct{
520 FunctionalState WakeUpPacket; /*!< Enable or Disable Wake up packet detection in power down mode */
522 FunctionalState MagicPacket; /*!< Enable or Disable Magic packet detection in power down mode */
524 FunctionalState GlobalUnicast; /*!< Enable or Disable Global unicast packet detection in power down mode */
526 FunctionalState WakeUpForward; /*!< Enable or Disable Forwarding Wake up packets */
528 }ETH_PowerDownConfigTypeDef;
529 /**
534 * @}
537 /* Exported constants --------------------------------------------------------*/
538 /** @defgroup ETH_Exported_Constants ETH Exported Constants
539 * @{
542 /** @defgroup ETH_DMA_Tx_Descriptor_Bit_Definition ETH DMA Tx Descriptor Bit Definition
543 * @{
547 DMA Tx Normal Desciptor Read Format
548 -----------------------------------------------------------------------------------------------
549 TDES0 | Buffer1 or Header Address [31:0] |
550 -----------------------------------------------------------------------------------------------
551 TDES1 | Buffer2 Address [31:0] / Next Descriptor Address [31:0] |
552 -----------------------------------------------------------------------------------------------
553 TDES2 | IOC(31) | TTSE(30) | Buff2 Length[29:16] | VTIR[15:14] | Header or Buff1 Length[13:0] |
554 -----------------------------------------------------------------------------------------------
555 TDES3 | OWN(31) | CTRL[30:26] | Reserved[25:24] | CTRL[23:20] | Reserved[19:17] | Status[16:0] |
556 -----------------------------------------------------------------------------------------------
559 /**
560 * @brief Bit definition of TDES0 RF register
562 #define ETH_DMATXNDESCRF_B1AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
564 /**
565 * @brief Bit definition of TDES1 RF register
567 #define ETH_DMATXNDESCRF_B2AP ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
569 /**
570 * @brief Bit definition of TDES2 RF register
572 #define ETH_DMATXNDESCRF_IOC ((uint32_t)0x80000000U) /*!< Interrupt on Completion */
573 #define ETH_DMATXNDESCRF_TTSE ((uint32_t)0x40000000U) /*!< Transmit Timestamp Enable */
574 #define ETH_DMATXNDESCRF_B2L ((uint32_t)0x3FFF0000U) /*!< Buffer 2 Length */
575 #define ETH_DMATXNDESCRF_VTIR ((uint32_t)0x0000C000U) /*!< VLAN Tag Insertion or Replacement mask */
576 #define ETH_DMATXNDESCRF_VTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add a VLAN tag. */
577 #define ETH_DMATXNDESCRF_VTIR_REMOVE ((uint32_t)0x00004000U) /*!< Remove the VLAN tag from the packets before transmission. */
578 #define ETH_DMATXNDESCRF_VTIR_INSERT ((uint32_t)0x00008000U) /*!< Insert a VLAN tag. */
579 #define ETH_DMATXNDESCRF_VTIR_REPLACE ((uint32_t)0x0000C000U) /*!< Replace the VLAN tag. */
580 #define ETH_DMATXNDESCRF_B1L ((uint32_t)0x00003FFFU) /*!< Buffer 1 Length */
581 #define ETH_DMATXNDESCRF_HL ((uint32_t)0x000003FFU) /*!< Header Length */
583 /**
584 * @brief Bit definition of TDES3 RF register
586 #define ETH_DMATXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
587 #define ETH_DMATXNDESCRF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
588 #define ETH_DMATXNDESCRF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
589 #define ETH_DMATXNDESCRF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
590 #define ETH_DMATXNDESCRF_CPC ((uint32_t)0x0C000000U) /*!< CRC Pad Control mask */
591 #define ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT ((uint32_t)0x00000000U) /*!< CRC Pad Control: CRC and Pad Insertion */
592 #define ETH_DMATXNDESCRF_CPC_CRC_INSERT ((uint32_t)0x04000000U) /*!< CRC Pad Control: CRC Insertion (Disable Pad Insertion) */
593 #define ETH_DMATXNDESCRF_CPC_DISABLE ((uint32_t)0x08000000U) /*!< CRC Pad Control: Disable CRC Insertion */
594 #define ETH_DMATXNDESCRF_CPC_CRC_REPLACE ((uint32_t)0x0C000000U) /*!< CRC Pad Control: CRC Replacement */
595 #define ETH_DMATXNDESCRF_SAIC ((uint32_t)0x03800000U) /*!< SA Insertion Control mask*/
596 #define ETH_DMATXNDESCRF_SAIC_DISABLE ((uint32_t)0x00000000U) /*!< SA Insertion Control: Do not include the source address */
597 #define ETH_DMATXNDESCRF_SAIC_INSERT ((uint32_t)0x00800000U) /*!< SA Insertion Control: Include or insert the source address */
598 #define ETH_DMATXNDESCRF_SAIC_REPLACE ((uint32_t)0x01000000U) /*!< SA Insertion Control: Replace the source address */
599 #define ETH_DMATXNDESCRF_THL ((uint32_t)0x00780000U) /*!< TCP Header Length */
600 #define ETH_DMATXNDESCRF_TSE ((uint32_t)0x00040000U) /*!< TCP segmentation enable */
601 #define ETH_DMATXNDESCRF_CIC ((uint32_t)0x00030000U) /*!< Checksum Insertion Control: 4 cases */
602 #define ETH_DMATXNDESCRF_CIC_DISABLE ((uint32_t)0x00000000U) /*!< Do Nothing: Checksum Engine is disabled */
603 #define ETH_DMATXNDESCRF_CIC_IPHDR_INSERT ((uint32_t)0x00010000U) /*!< Only IP header checksum calculation and insertion are enabled. */
604 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT ((uint32_t)0x00020000U) /*!< IP header checksum and payload checksum calculation and insertion are
605 enabled, but pseudo header checksum is not calculated in hardware */
606 #define ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC ((uint32_t)0x00030000U) /*!< IP Header checksum and payload checksum calculation and insertion are
607 enabled, and pseudo header checksum is calculated in hardware. */
608 #define ETH_DMATXNDESCRF_TPL ((uint32_t)0x0003FFFFU) /*!< TCP Payload Length */
609 #define ETH_DMATXNDESCRF_FL ((uint32_t)0x00007FFFU) /*!< Transmit End of Ring */
612 DMA Tx Normal Descriptor Write Back Format
613 -----------------------------------------------------------------------------------------------
614 TDES0 | Timestamp Low |
615 -----------------------------------------------------------------------------------------------
616 TDES1 | Timestamp High |
617 -----------------------------------------------------------------------------------------------
618 TDES2 | Reserved[31:0] |
619 -----------------------------------------------------------------------------------------------
620 TDES3 | OWN(31) | Status[30:0] |
621 -----------------------------------------------------------------------------------------------
624 /**
625 * @brief Bit definition of TDES0 WBF register
627 #define ETH_DMATXNDESCWBF_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Buffer1 Address Pointer or TSO Header Address Pointer */
629 /**
630 * @brief Bit definition of TDES1 WBF register
632 #define ETH_DMATXNDESCWBF_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Buffer2 Address Pointer */
634 /**
635 * @brief Bit definition of TDES3 WBF register
637 #define ETH_DMATXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
638 #define ETH_DMATXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
639 #define ETH_DMATXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
640 #define ETH_DMATXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
641 #define ETH_DMATXNDESCWBF_TTSS ((uint32_t)0x00020000U) /*!< Tx Timestamp Status */
642 #define ETH_DMATXNDESCWBF_DP ((uint32_t)0x04000000U) /*!< Disable Padding */
643 #define ETH_DMATXNDESCWBF_TTSE ((uint32_t)0x02000000U) /*!< Transmit Timestamp Enable */
644 #define ETH_DMATXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error summary: OR of the following bits: IHE || UF || ED || EC || LCO || PCE || NC || LCA || FF || JT */
645 #define ETH_DMATXNDESCWBF_JT ((uint32_t)0x00004000U) /*!< Jabber Timeout */
646 #define ETH_DMATXNDESCWBF_FF ((uint32_t)0x00002000U) /*!< Packet Flushed: DMA/MTL flushed the packet due to SW flush */
647 #define ETH_DMATXNDESCWBF_PCE ((uint32_t)0x00001000U) /*!< Payload Checksum Error */
648 #define ETH_DMATXNDESCWBF_LCA ((uint32_t)0x00000800U) /*!< Loss of Carrier: carrier lost during transmission */
649 #define ETH_DMATXNDESCWBF_NC ((uint32_t)0x00000400U) /*!< No Carrier: no carrier signal from the transceiver */
650 #define ETH_DMATXNDESCWBF_LCO ((uint32_t)0x00000200U) /*!< Late Collision: transmission aborted due to collision */
651 #define ETH_DMATXNDESCWBF_EC ((uint32_t)0x00000100U) /*!< Excessive Collision: transmission aborted after 16 collisions */
652 #define ETH_DMATXNDESCWBF_CC ((uint32_t)0x000000F0U) /*!< Collision Count */
653 #define ETH_DMATXNDESCWBF_ED ((uint32_t)0x00000008U) /*!< Excessive Deferral */
654 #define ETH_DMATXNDESCWBF_UF ((uint32_t)0x00000004U) /*!< Underflow Error: late data arrival from the memory */
655 #define ETH_DMATXNDESCWBF_DB ((uint32_t)0x00000002U) /*!< Deferred Bit */
656 #define ETH_DMATXNDESCWBF_IHE ((uint32_t)0x00000004U) /*!< IP Header Error */
660 DMA Tx Context Desciptor
661 -----------------------------------------------------------------------------------------------
662 TDES0 | Timestamp Low |
663 -----------------------------------------------------------------------------------------------
664 TDES1 | Timestamp High |
665 -----------------------------------------------------------------------------------------------
666 TDES2 | Inner VLAN Tag[31:16] | Reserved(15) | Maximum Segment Size [14:0] |
667 -----------------------------------------------------------------------------------------------
668 TDES3 | OWN(31) | Status[30:0] |
669 -----------------------------------------------------------------------------------------------
672 /**
673 * @brief Bit definition of Tx context descriptor register 0
675 #define ETH_DMATXCDESC_TTSL ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp Low */
677 /**
678 * @brief Bit definition of Tx context descriptor register 1
680 #define ETH_DMATXCDESC_TTSH ((uint32_t)0xFFFFFFFFU) /*!< Transmit Packet Timestamp High */
682 /**
683 * @brief Bit definition of Tx context descriptor register 2
685 #define ETH_DMATXCDESC_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
686 #define ETH_DMATXCDESC_MSS ((uint32_t)0x00003FFFU) /*!< Maximum Segment Size */
688 /**
689 * @brief Bit definition of Tx context descriptor register 3
691 #define ETH_DMATXCDESC_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
692 #define ETH_DMATXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Context Type */
693 #define ETH_DMATXCDESC_OSTC ((uint32_t)0x08000000U) /*!< One-Step Timestamp Correction Enable */
694 #define ETH_DMATXCDESC_TCMSSV ((uint32_t)0x04000000U) /*!< One-Step Timestamp Correction Input or MSS Valid */
695 #define ETH_DMATXCDESC_CDE ((uint32_t)0x00800000U) /*!< Context Descriptor Error */
696 #define ETH_DMATXCDESC_IVTIR ((uint32_t)0x000C0000U) /*!< Inner VLAN Tag Insert or Replace Mask */
697 #define ETH_DMATXCDESC_IVTIR_DISABLE ((uint32_t)0x00000000U) /*!< Do not add the inner VLAN tag. */
698 #define ETH_DMATXCDESC_IVTIR_REMOVE ((uint32_t)0x00040000U) /*!< Remove the inner VLAN tag from the packets before transmission. */
699 #define ETH_DMATXCDESC_IVTIR_INSERT ((uint32_t)0x00080000U) /*!< Insert the inner VLAN tag. */
700 #define ETH_DMATXCDESC_IVTIR_REPLACE ((uint32_t)0x000C0000U) /*!< Replace the inner VLAN tag. */
701 #define ETH_DMATXCDESC_IVLTV ((uint32_t)0x00020000U) /*!< Inner VLAN Tag Valid */
702 #define ETH_DMATXCDESC_VLTV ((uint32_t)0x00010000U) /*!< VLAN Tag Valid */
703 #define ETH_DMATXCDESC_VT ((uint32_t)0x0000FFFFU) /*!< VLAN Tag */
706 * @}
710 /** @defgroup ETH_DMA_Rx_Descriptor_Bit_Definition ETH DMA Rx Descriptor Bit Definition
711 * @{
715 DMA Rx Normal Descriptor read format
716 -----------------------------------------------------------------------------------------------------------
717 RDES0 | Buffer1 or Header Address [31:0] |
718 -----------------------------------------------------------------------------------------------------------
719 RDES1 | Reserved |
720 -----------------------------------------------------------------------------------------------------------
721 RDES2 | Payload or Buffer2 Address[31:0] |
722 -----------------------------------------------------------------------------------------------------------
723 RDES3 | OWN(31) | IOC(30) | Reserved [29:26] | BUF2V(25) | BUF1V(24) | Reserved [23:0] |
724 -----------------------------------------------------------------------------------------------------------
727 /**
728 * @brief Bit definition of Rx normal descriptor register 0 read format
730 #define ETH_DMARXNDESCRF_BUF1AP ((uint32_t)0xFFFFFFFFU) /*!< Header or Buffer 1 Address Pointer */
732 /**
733 * @brief Bit definition of Rx normal descriptor register 2 read format
735 #define ETH_DMARXNDESCRF_BUF2AP ((uint32_t)0xFFFFFFFFU) /*!< Buffer 2 Address Pointer */
737 /**
738 * @brief Bit definition of Rx normal descriptor register 3 read format
740 #define ETH_DMARXNDESCRF_OWN ((uint32_t)0x80000000U) /*!< OWN bit: descriptor is owned by DMA engine */
741 #define ETH_DMARXNDESCRF_IOC ((uint32_t)0x40000000U) /*!< Interrupt Enabled on Completion */
742 #define ETH_DMARXNDESCRF_BUF2V ((uint32_t)0x02000000U) /*!< Buffer 2 Address Valid */
743 #define ETH_DMARXNDESCRF_BUF1V ((uint32_t)0x01000000U) /*!< Buffer 1 Address Valid */
746 DMA Rx Normal Descriptor write back format
747 ---------------------------------------------------------------------------------------------------------------------
748 RDES0 | Inner VLAN Tag[31:16] | Outer VLAN Tag[15:0] |
749 ---------------------------------------------------------------------------------------------------------------------
750 RDES1 | OAM code, or MAC Control Opcode [31:16] | Extended Status |
751 ---------------------------------------------------------------------------------------------------------------------
752 RDES2 | MAC Filter Status[31:16] | VF(15) | Reserved [14:12] | ARP Status [11:10] | Header Length [9:0] |
753 ---------------------------------------------------------------------------------------------------------------------
754 RDES3 | OWN(31) | CTXT(30) | FD(29) | LD(28) | Status[27:16] | ES(15) | Packet Length[14:0] |
755 ---------------------------------------------------------------------------------------------------------------------
758 /**
759 * @brief Bit definition of Rx normal descriptor register 0 write back format
761 #define ETH_DMARXNDESCWBF_IVT ((uint32_t)0xFFFF0000U) /*!< Inner VLAN Tag */
762 #define ETH_DMARXNDESCWBF_OVT ((uint32_t)0x0000FFFFU) /*!< Outer VLAN Tag */
764 /**
765 * @brief Bit definition of Rx normal descriptor register 1 write back format
767 #define ETH_DMARXNDESCWBF_OPC ((uint32_t)0xFFFF0000U) /*!< OAM Sub-Type Code, or MAC Control Packet opcode */
768 #define ETH_DMARXNDESCWBF_TD ((uint32_t)0x00008000U) /*!< Timestamp Dropped */
769 #define ETH_DMARXNDESCWBF_TSA ((uint32_t)0x00004000U) /*!< Timestamp Available */
770 #define ETH_DMARXNDESCWBF_PV ((uint32_t)0x00002000U) /*!< PTP Version */
771 #define ETH_DMARXNDESCWBF_PFT ((uint32_t)0x00001000U) /*!< PTP Packet Type */
772 #define ETH_DMARXNDESCWBF_PMT_NO ((uint32_t)0x00000000U) /*!< PTP Message Type: No PTP message received */
773 #define ETH_DMARXNDESCWBF_PMT_SYNC ((uint32_t)0x00000100U) /*!< PTP Message Type: SYNC (all clock types) */
774 #define ETH_DMARXNDESCWBF_PMT_FUP ((uint32_t)0x00000200U) /*!< PTP Message Type: Follow_Up (all clock types) */
775 #define ETH_DMARXNDESCWBF_PMT_DREQ ((uint32_t)0x00000300U) /*!< PTP Message Type: Delay_Req (all clock types) */
776 #define ETH_DMARXNDESCWBF_PMT_DRESP ((uint32_t)0x00000400U) /*!< PTP Message Type: Delay_Resp (all clock types) */
777 #define ETH_DMARXNDESCWBF_PMT_PDREQ ((uint32_t)0x00000500U) /*!< PTP Message Type: Pdelay_Req (in peer-to-peer transparent clock) */
778 #define ETH_DMARXNDESCWBF_PMT_PDRESP ((uint32_t)0x00000600U) /*!< PTP Message Type: Pdelay_Resp (in peer-to-peer transparent clock) */
779 #define ETH_DMARXNDESCWBF_PMT_PDRESPFUP ((uint32_t)0x00000700U) /*!< PTP Message Type: Pdelay_Resp_Follow_Up (in peer-to-peer transparent clock) */
780 #define ETH_DMARXNDESCWBF_PMT_ANNOUNCE ((uint32_t)0x00000800U) /*!< PTP Message Type: Announce */
781 #define ETH_DMARXNDESCWBF_PMT_MANAG ((uint32_t)0x00000900U) /*!< PTP Message Type: Management */
782 #define ETH_DMARXNDESCWBF_PMT_SIGN ((uint32_t)0x00000A00U) /*!< PTP Message Type: Signaling */
783 #define ETH_DMARXNDESCWBF_PMT_RESERVED ((uint32_t)0x00000F00U) /*!< PTP Message Type: PTP packet with Reserved message type */
784 #define ETH_DMARXNDESCWBF_IPCE ((uint32_t)0x00000080U) /*!< IP Payload Error */
785 #define ETH_DMARXNDESCWBF_IPCB ((uint32_t)0x00000040U) /*!< IP Checksum Bypassed */
786 #define ETH_DMARXNDESCWBF_IPV6 ((uint32_t)0x00000020U) /*!< IPv6 header Present */
787 #define ETH_DMARXNDESCWBF_IPV4 ((uint32_t)0x00000010U) /*!< IPv4 header Present */
788 #define ETH_DMARXNDESCWBF_IPHE ((uint32_t)0x00000008U) /*!< IP Header Error */
789 #define ETH_DMARXNDESCWBF_PT ((uint32_t)0x00000003U) /*!< Payload Type mask */
790 #define ETH_DMARXNDESCWBF_PT_UNKNOWN ((uint32_t)0x00000000U) /*!< Payload Type: Unknown type or IP/AV payload not processed */
791 #define ETH_DMARXNDESCWBF_PT_UDP ((uint32_t)0x00000001U) /*!< Payload Type: UDP */
792 #define ETH_DMARXNDESCWBF_PT_TCP ((uint32_t)0x00000002U) /*!< Payload Type: TCP */
793 #define ETH_DMARXNDESCWBF_PT_ICMP ((uint32_t)0x00000003U) /*!< Payload Type: ICMP */
795 /**
796 * @brief Bit definition of Rx normal descriptor register 2 write back format
798 #define ETH_DMARXNDESCWBF_L3L4FM ((uint32_t)0x20000000U) /*!< L3 and L4 Filter Number Matched: if reset filter 0 is matched , if set filter 1 is matched */
799 #define ETH_DMARXNDESCWBF_L4FM ((uint32_t)0x10000000U) /*!< Layer 4 Filter Match */
800 #define ETH_DMARXNDESCWBF_L3FM ((uint32_t)0x08000000U) /*!< Layer 3 Filter Match */
801 #define ETH_DMARXNDESCWBF_MADRM ((uint32_t)0x07F80000U) /*!< MAC Address Match or Hash Value */
802 #define ETH_DMARXNDESCWBF_HF ((uint32_t)0x00040000U) /*!< Hash Filter Status */
803 #define ETH_DMARXNDESCWBF_DAF ((uint32_t)0x00020000U) /*!< Destination Address Filter Fail */
804 #define ETH_DMARXNDESCWBF_SAF ((uint32_t)0x00010000U) /*!< SA Address Filter Fail */
805 #define ETH_DMARXNDESCWBF_VF ((uint32_t)0x00008000U) /*!< VLAN Filter Status */
806 #define ETH_DMARXNDESCWBF_ARPNR ((uint32_t)0x00000400U) /*!< ARP Reply Not Generated */
809 /**
810 * @brief Bit definition of Rx normal descriptor register 3 write back format
812 #define ETH_DMARXNDESCWBF_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
813 #define ETH_DMARXNDESCWBF_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
814 #define ETH_DMARXNDESCWBF_FD ((uint32_t)0x20000000U) /*!< First Descriptor */
815 #define ETH_DMARXNDESCWBF_LD ((uint32_t)0x10000000U) /*!< Last Descriptor */
816 #define ETH_DMARXNDESCWBF_RS2V ((uint32_t)0x08000000U) /*!< Receive Status RDES2 Valid */
817 #define ETH_DMARXNDESCWBF_RS1V ((uint32_t)0x04000000U) /*!< Receive Status RDES1 Valid */
818 #define ETH_DMARXNDESCWBF_RS0V ((uint32_t)0x02000000U) /*!< Receive Status RDES0 Valid */
819 #define ETH_DMARXNDESCWBF_CE ((uint32_t)0x01000000U) /*!< CRC Error */
820 #define ETH_DMARXNDESCWBF_GP ((uint32_t)0x00800000U) /*!< Giant Packet */
821 #define ETH_DMARXNDESCWBF_RWT ((uint32_t)0x00400000U) /*!< Receive Watchdog Timeout */
822 #define ETH_DMARXNDESCWBF_OE ((uint32_t)0x00200000U) /*!< Overflow Error */
823 #define ETH_DMARXNDESCWBF_RE ((uint32_t)0x00100000U) /*!< Receive Error */
824 #define ETH_DMARXNDESCWBF_DE ((uint32_t)0x00080000U) /*!< Dribble Bit Error */
825 #define ETH_DMARXNDESCWBF_LT ((uint32_t)0x00070000U) /*!< Length/Type Field */
826 #define ETH_DMARXNDESCWBF_LT_LP ((uint32_t)0x00000000U) /*!< The packet is a length packet */
827 #define ETH_DMARXNDESCWBF_LT_TP ((uint32_t)0x00010000U) /*!< The packet is a type packet */
828 #define ETH_DMARXNDESCWBF_LT_ARP ((uint32_t)0x00030000U) /*!< The packet is a ARP Request packet type */
829 #define ETH_DMARXNDESCWBF_LT_VLAN ((uint32_t)0x00040000U) /*!< The packet is a type packet with VLAN Tag */
830 #define ETH_DMARXNDESCWBF_LT_DVLAN ((uint32_t)0x00050000U) /*!< The packet is a type packet with Double VLAN Tag */
831 #define ETH_DMARXNDESCWBF_LT_MAC ((uint32_t)0x00060000U) /*!< The packet is a MAC Control packet type */
832 #define ETH_DMARXNDESCWBF_LT_OAM ((uint32_t)0x00070000U) /*!< The packet is a OAM packet type */
833 #define ETH_DMARXNDESCWBF_ES ((uint32_t)0x00008000U) /*!< Error Summary */
834 #define ETH_DMARXNDESCWBF_PL ((uint32_t)0x00007FFFU) /*!< Packet Length */
837 DMA Rx context Descriptor
838 ---------------------------------------------------------------------------------------------------------------------
839 RDES0 | Timestamp Low[31:0] |
840 ---------------------------------------------------------------------------------------------------------------------
841 RDES1 | Timestamp High[31:0] |
842 ---------------------------------------------------------------------------------------------------------------------
843 RDES2 | Reserved |
844 ---------------------------------------------------------------------------------------------------------------------
845 RDES3 | OWN(31) | CTXT(30) | Reserved[29:0] |
846 ---------------------------------------------------------------------------------------------------------------------
849 /**
850 * @brief Bit definition of Rx context descriptor register 0
852 #define ETH_DMARXCDESC_RTSL ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp Low */
854 /**
855 * @brief Bit definition of Rx context descriptor register 1
857 #define ETH_DMARXCDESC_RTSH ((uint32_t)0xFFFFFFFFU) /*!< Receive Packet Timestamp High */
859 /**
860 * @brief Bit definition of Rx context descriptor register 3
862 #define ETH_DMARXCDESC_OWN ((uint32_t)0x80000000U) /*!< Own Bit */
863 #define ETH_DMARXCDESC_CTXT ((uint32_t)0x40000000U) /*!< Receive Context Descriptor */
866 * @}
869 /** @defgroup ETH_Frame_settings ETH frame settings
870 * @{
872 #define ETH_MAX_PACKET_SIZE ((uint32_t)1528U) /*!< ETH_HEADER + 2*VLAN_TAG + MAX_ETH_PAYLOAD + ETH_CRC */
873 #define ETH_HEADER ((uint32_t)14U) /*!< 6 byte Dest addr, 6 byte Src addr, 2 byte length/type */
874 #define ETH_CRC ((uint32_t)4U) /*!< Ethernet CRC */
875 #define ETH_VLAN_TAG ((uint32_t)4U) /*!< optional 802.1q VLAN Tag */
876 #define ETH_MIN_PAYLOAD ((uint32_t)46U) /*!< Minimum Ethernet payload size */
877 #define ETH_MAX_PAYLOAD ((uint32_t)1500U) /*!< Maximum Ethernet payload size */
878 #define ETH_JUMBO_FRAME_PAYLOAD ((uint32_t)9000U) /*!< Jumbo frame payload size */
880 * @}
883 /** @defgroup ETH_Error_Code ETH Error Code
884 * @{
886 #define HAL_ETH_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
887 #define HAL_ETH_ERROR_PARAM ((uint32_t)0x00000001U) /*!< Busy error */
888 #define HAL_ETH_ERROR_BUSY ((uint32_t)0x00000002U) /*!< Parameter error */
889 #define HAL_ETH_ERROR_TIMEOUT ((uint32_t)0x00000004U) /*!< Timeout error */
890 #define HAL_ETH_ERROR_DMA ((uint32_t)0x00000008U) /*!< DMA transfer error */
891 #define HAL_ETH_ERROR_MAC ((uint32_t)0x00000010U) /*!< MAC transfer error */
892 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
893 #define HAL_ETH_ERROR_INVALID_CALLBACK ((uint32_t)0x00000020U) /*!< Invalid Callback error */
894 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
896 * @}
899 /** @defgroup ETH_Tx_Packet_Attributes ETH Tx Packet Attributes
900 * @{
902 #define ETH_TX_PACKETS_FEATURES_CSUM ((uint32_t)0x00000001U)
903 #define ETH_TX_PACKETS_FEATURES_SAIC ((uint32_t)0x00000002U)
904 #define ETH_TX_PACKETS_FEATURES_VLANTAG ((uint32_t)0x00000004U)
905 #define ETH_TX_PACKETS_FEATURES_INNERVLANTAG ((uint32_t)0x00000008U)
906 #define ETH_TX_PACKETS_FEATURES_TSO ((uint32_t)0x00000010U)
907 #define ETH_TX_PACKETS_FEATURES_CRCPAD ((uint32_t)0x00000020U)
909 * @}
912 /** @defgroup ETH_Tx_Packet_Source_Addr_Control ETH Tx Packet Source Addr Control
913 * @{
915 #define ETH_SRC_ADDR_CONTROL_DISABLE ETH_DMATXNDESCRF_SAIC_DISABLE
916 #define ETH_SRC_ADDR_INSERT ETH_DMATXNDESCRF_SAIC_INSERT
917 #define ETH_SRC_ADDR_REPLACE ETH_DMATXNDESCRF_SAIC_REPLACE
919 * @}
922 /** @defgroup ETH_Tx_Packet_CRC_Pad_Control ETH Tx Packet CRC Pad Control
923 * @{
925 #define ETH_CRC_PAD_DISABLE ETH_DMATXNDESCRF_CPC_DISABLE
926 #define ETH_CRC_PAD_INSERT ETH_DMATXNDESCRF_CPC_CRCPAD_INSERT
927 #define ETH_CRC_INSERT ETH_DMATXNDESCRF_CPC_CRC_INSERT
928 #define ETH_CRC_REPLACE ETH_DMATXNDESCRF_CPC_CRC_REPLACE
930 * @}
933 /** @defgroup ETH_Tx_Packet_Checksum_Control ETH Tx Packet Checksum Control
934 * @{
936 #define ETH_CHECKSUM_DISABLE ETH_DMATXNDESCRF_CIC_DISABLE
937 #define ETH_CHECKSUM_IPHDR_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_INSERT
938 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT
939 #define ETH_CHECKSUM_IPHDR_PAYLOAD_INSERT_PHDR_CALC ETH_DMATXNDESCRF_CIC_IPHDR_PAYLOAD_INSERT_PHDR_CALC
941 * @}
944 /** @defgroup ETH_Tx_Packet_VLAN_Control ETH Tx Packet VLAN Control
945 * @{
947 #define ETH_VLAN_DISABLE ETH_DMATXNDESCRF_VTIR_DISABLE
948 #define ETH_VLAN_REMOVE ETH_DMATXNDESCRF_VTIR_REMOVE
949 #define ETH_VLAN_INSERT ETH_DMATXNDESCRF_VTIR_INSERT
950 #define ETH_VLAN_REPLACE ETH_DMATXNDESCRF_VTIR_REPLACE
952 * @}
955 /** @defgroup ETH_Tx_Packet_Inner_VLAN_Control ETH Tx Packet Inner VLAN Control
956 * @{
958 #define ETH_INNER_VLAN_DISABLE ETH_DMATXCDESC_IVTIR_DISABLE
959 #define ETH_INNER_VLAN_REMOVE ETH_DMATXCDESC_IVTIR_REMOVE
960 #define ETH_INNER_VLAN_INSERT ETH_DMATXCDESC_IVTIR_INSERT
961 #define ETH_INNER_VLAN_REPLACE ETH_DMATXCDESC_IVTIR_REPLACE
963 * @}
966 /** @defgroup ETH_Rx_Checksum_Status ETH Rx Checksum Status
967 * @{
969 #define ETH_CHECKSUM_BYPASSED ETH_DMARXNDESCWBF_IPCB
970 #define ETH_CHECKSUM_IP_HEADER_ERROR ETH_DMARXNDESCWBF_IPHE
971 #define ETH_CHECKSUM_IP_PAYLOAD_ERROR ETH_DMARXNDESCWBF_IPCE
973 * @}
976 /** @defgroup ETH_Rx_IP_Header_Type ETH Rx IP Header Type
977 * @{
979 #define ETH_IP_HEADER_IPV4 ETH_DMARXNDESCWBF_IPV4
980 #define ETH_IP_HEADER_IPV6 ETH_DMARXNDESCWBF_IPV6
982 * @}
985 /** @defgroup ETH_Rx_Payload_Type ETH Rx Payload Type
986 * @{
988 #define ETH_IP_PAYLOAD_UNKNOWN ETH_DMARXNDESCWBF_PT_UNKNOWN
989 #define ETH_IP_PAYLOAD_UDP ETH_DMARXNDESCWBF_PT_UDP
990 #define ETH_IP_PAYLOAD_TCP ETH_DMARXNDESCWBF_PT_TCP
991 #define ETH_IP_PAYLOAD_ICMPN ETH_DMARXNDESCWBF_PT_ICMP
993 * @}
996 /** @defgroup ETH_Rx_MAC_Filter_Status ETH Rx MAC Filter Status
997 * @{
999 #define ETH_HASH_FILTER_PASS ETH_DMARXNDESCWBF_HF
1000 #define ETH_VLAN_FILTER_PASS ETH_DMARXNDESCWBF_VF
1001 #define ETH_DEST_ADDRESS_FAIL ETH_DMARXNDESCWBF_DAF
1002 #define ETH_SOURCE_ADDRESS_FAIL ETH_DMARXNDESCWBF_SAF
1004 * @}
1007 /** @defgroup ETH_Rx_L3_Filter_Status ETH Rx L3 Filter Status
1008 * @{
1010 #define ETH_L3_FILTER0_MATCH ETH_DMARXNDESCWBF_L3FM
1011 #define ETH_L3_FILTER1_MATCH (ETH_DMARXNDESCWBF_L3FM | ETH_DMARXNDESCWBF_L3L4FM)
1013 * @}
1016 /** @defgroup ETH_Rx_L4_Filter_Status ETH Rx L4 Filter Status
1017 * @{
1019 #define ETH_L4_FILTER0_MATCH ETH_DMARXNDESCWBF_L4FM
1020 #define ETH_L4_FILTER1_MATCH (ETH_DMARXNDESCWBF_L4FM | ETH_DMARXNDESCWBF_L3L4FM)
1022 * @}
1025 /** @defgroup ETH_Rx_Error_Code ETH Rx Error Code
1026 * @{
1028 #define ETH_DRIBBLE_BIT_ERROR ETH_DMARXNDESCWBF_DE
1029 #define ETH_RECEIVE_ERROR ETH_DMARXNDESCWBF_RE
1030 #define ETH_RECEIVE_OVERFLOW ETH_DMARXNDESCWBF_OE
1031 #define ETH_WATCHDOG_TIMEOUT ETH_DMARXNDESCWBF_RWT
1032 #define ETH_GIANT_PACKET ETH_DMARXNDESCWBF_GP
1033 #define ETH_CRC_ERROR ETH_DMARXNDESCWBF_CE
1035 * @}
1038 /** @defgroup ETH_DMA_Arbitration ETH DMA Arbitration
1039 * @{
1041 #define ETH_DMAARBITRATION_RX ETH_DMAMR_DA
1042 #define ETH_DMAARBITRATION_RX1_TX1 ((uint32_t)0x00000000U)
1043 #define ETH_DMAARBITRATION_RX2_TX1 ETH_DMAMR_PR_2_1
1044 #define ETH_DMAARBITRATION_RX3_TX1 ETH_DMAMR_PR_3_1
1045 #define ETH_DMAARBITRATION_RX4_TX1 ETH_DMAMR_PR_4_1
1046 #define ETH_DMAARBITRATION_RX5_TX1 ETH_DMAMR_PR_5_1
1047 #define ETH_DMAARBITRATION_RX6_TX1 ETH_DMAMR_PR_6_1
1048 #define ETH_DMAARBITRATION_RX7_TX1 ETH_DMAMR_PR_7_1
1049 #define ETH_DMAARBITRATION_RX8_TX1 ETH_DMAMR_PR_8_1
1050 #define ETH_DMAARBITRATION_TX (ETH_DMAMR_TXPR | ETH_DMAMR_DA)
1051 #define ETH_DMAARBITRATION_TX1_RX1 ((uint32_t)0x00000000U)
1052 #define ETH_DMAARBITRATION_TX2_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_2_1)
1053 #define ETH_DMAARBITRATION_TX3_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_3_1)
1054 #define ETH_DMAARBITRATION_TX4_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_4_1)
1055 #define ETH_DMAARBITRATION_TX5_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_5_1)
1056 #define ETH_DMAARBITRATION_TX6_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_6_1)
1057 #define ETH_DMAARBITRATION_TX7_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_7_1)
1058 #define ETH_DMAARBITRATION_TX8_RX1 (ETH_DMAMR_TXPR | ETH_DMAMR_PR_8_1)
1060 * @}
1063 /** @defgroup ETH_Burst_Mode ETH Burst Mode
1064 * @{
1066 #define ETH_BURSTLENGTH_FIXED ETH_DMASBMR_FB
1067 #define ETH_BURSTLENGTH_MIXED ETH_DMASBMR_MB
1068 #define ETH_BURSTLENGTH_UNSPECIFIED ((uint32_t)0x00000000U)
1070 * @}
1073 /** @defgroup ETH_Tx_DMA_Burst_Length ETH Tx DMA Burst Length
1074 * @{
1076 #define ETH_TXDMABURSTLENGTH_1BEAT ETH_DMACTCR_TPBL_1PBL
1077 #define ETH_TXDMABURSTLENGTH_2BEAT ETH_DMACTCR_TPBL_2PBL
1078 #define ETH_TXDMABURSTLENGTH_4BEAT ETH_DMACTCR_TPBL_4PBL
1079 #define ETH_TXDMABURSTLENGTH_8BEAT ETH_DMACTCR_TPBL_8PBL
1080 #define ETH_TXDMABURSTLENGTH_16BEAT ETH_DMACTCR_TPBL_16PBL
1081 #define ETH_TXDMABURSTLENGTH_32BEAT ETH_DMACTCR_TPBL_32PBL
1083 * @}
1086 /** @defgroup ETH_Rx_DMA_Burst_Length ETH Rx DMA Burst Length
1087 * @{
1089 #define ETH_RXDMABURSTLENGTH_1BEAT ETH_DMACRCR_RPBL_1PBL
1090 #define ETH_RXDMABURSTLENGTH_2BEAT ETH_DMACRCR_RPBL_2PBL
1091 #define ETH_RXDMABURSTLENGTH_4BEAT ETH_DMACRCR_RPBL_4PBL
1092 #define ETH_RXDMABURSTLENGTH_8BEAT ETH_DMACRCR_RPBL_8PBL
1093 #define ETH_RXDMABURSTLENGTH_16BEAT ETH_DMACRCR_RPBL_16PBL
1094 #define ETH_RXDMABURSTLENGTH_32BEAT ETH_DMACRCR_RPBL_32PBL
1096 * @}
1099 /** @defgroup ETH_DMA_Interrupts ETH DMA Interrupts
1100 * @{
1102 #define ETH_DMA_NORMAL_IT ETH_DMACIER_NIE
1103 #define ETH_DMA_ABNORMAL_IT ETH_DMACIER_AIE
1104 #define ETH_DMA_CONTEXT_DESC_ERROR_IT ETH_DMACIER_CDEE
1105 #define ETH_DMA_FATAL_BUS_ERROR_IT ETH_DMACIER_FBEE
1106 #define ETH_DMA_EARLY_RX_IT ETH_DMACIER_ERIE
1107 #define ETH_DMA_EARLY_TX_IT ETH_DMACIER_ETIE
1108 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_IT ETH_DMACIER_RWTE
1109 #define ETH_DMA_RX_PROCESS_STOPPED_IT ETH_DMACIER_RSE
1110 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_RBUE
1111 #define ETH_DMA_RX_IT ETH_DMACIER_RIE
1112 #define ETH_DMA_TX_BUFFER_UNAVAILABLE_IT ETH_DMACIER_TBUE
1113 #define ETH_DMA_TX_PROCESS_STOPPED_IT ETH_DMACIER_TXSE
1114 #define ETH_DMA_TX_IT ETH_DMACIER_TIE
1116 * @}
1119 /** @defgroup ETH_DMA_Status_Flags ETH DMA Status Flags
1120 * @{
1122 #define ETH_DMA_RX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1123 #define ETH_DMA_RX_DESC_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1 | ETH_DMACSR_REB_BIT_0)
1124 #define ETH_DMA_RX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_1)
1125 #define ETH_DMA_RX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_REB_BIT_2 | ETH_DMACSR_REB_BIT_0)
1126 #define ETH_DMA_RX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_REB_BIT_2
1127 #define ETH_DMA_TX_NO_ERROR_FLAG ((uint32_t)0x00000000U)
1128 #define ETH_DMA_TX_DESC_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1 | ETH_DMACSR_TEB_BIT_0)
1129 #define ETH_DMA_TX_DESC_WRITE_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_1)
1130 #define ETH_DMA_TX_BUFFER_READ_ERROR_FLAG (ETH_DMACSR_TEB_BIT_2 | ETH_DMACSR_TEB_BIT_0)
1131 #define ETH_DMA_TX_BUFFER_WRITE_ERROR_FLAG ETH_DMACSR_TEB_BIT_2
1132 #define ETH_DMA_CONTEXT_DESC_ERROR_FLAG ETH_DMACSR_CDE
1133 #define ETH_DMA_FATAL_BUS_ERROR_FLAG ETH_DMACSR_FBE
1134 #define ETH_DMA_EARLY_TX_IT_FLAG ETH_DMACSR_ERI
1135 #define ETH_DMA_RX_WATCHDOG_TIMEOUT_FLAG ETH_DMACSR_RWT
1136 #define ETH_DMA_RX_PROCESS_STOPPED_FLAG ETH_DMACSR_RPS
1137 #define ETH_DMA_RX_BUFFER_UNAVAILABLE_FLAG ETH_DMACSR_RBU
1138 #define ETH_DMA_TX_PROCESS_STOPPED_FLAG ETH_DMACSR_TPS
1140 * @}
1143 /** @defgroup ETH_Transmit_Mode ETH Transmit Mode
1144 * @{
1146 #define ETH_TRANSMITSTOREFORWARD ETH_MTLTQOMR_TSF
1147 #define ETH_TRANSMITTHRESHOLD_32 ETH_MTLTQOMR_TTC_32BITS
1148 #define ETH_TRANSMITTHRESHOLD_64 ETH_MTLTQOMR_TTC_64BITS
1149 #define ETH_TRANSMITTHRESHOLD_96 ETH_MTLTQOMR_TTC_96BITS
1150 #define ETH_TRANSMITTHRESHOLD_128 ETH_MTLTQOMR_TTC_128BITS
1151 #define ETH_TRANSMITTHRESHOLD_192 ETH_MTLTQOMR_TTC_192BITS
1152 #define ETH_TRANSMITTHRESHOLD_256 ETH_MTLTQOMR_TTC_256BITS
1153 #define ETH_TRANSMITTHRESHOLD_384 ETH_MTLTQOMR_TTC_384BITS
1154 #define ETH_TRANSMITTHRESHOLD_512 ETH_MTLTQOMR_TTC_512BITS
1156 * @}
1159 /** @defgroup ETH_Receive_Mode ETH Receive Mode
1160 * @{
1162 #define ETH_RECEIVESTOREFORWARD ETH_MTLRQOMR_RSF
1163 #define ETH_RECEIVETHRESHOLD8_64 ETH_MTLRQOMR_RTC_64BITS
1164 #define ETH_RECEIVETHRESHOLD8_32 ETH_MTLRQOMR_RTC_32BITS
1165 #define ETH_RECEIVETHRESHOLD8_96 ETH_MTLRQOMR_RTC_96BITS
1166 #define ETH_RECEIVETHRESHOLD8_128 ETH_MTLRQOMR_RTC_128BITS
1168 * @}
1171 /** @defgroup ETH_Pause_Low_Threshold ETH Pause Low Threshold
1172 * @{
1174 #define ETH_PAUSELOWTHRESHOLD_MINUS_4 ETH_MACTFCR_PLT_MINUS4
1175 #define ETH_PAUSELOWTHRESHOLD_MINUS_28 ETH_MACTFCR_PLT_MINUS28
1176 #define ETH_PAUSELOWTHRESHOLD_MINUS_36 ETH_MACTFCR_PLT_MINUS36
1177 #define ETH_PAUSELOWTHRESHOLD_MINUS_144 ETH_MACTFCR_PLT_MINUS144
1178 #define ETH_PAUSELOWTHRESHOLD_MINUS_256 ETH_MACTFCR_PLT_MINUS256
1179 #define ETH_PAUSELOWTHRESHOLD_MINUS_512 ETH_MACTFCR_PLT_MINUS512
1181 * @}
1184 /** @defgroup ETH_Watchdog_Timeout ETH Watchdog Timeout
1185 * @{
1187 #define ETH_WATCHDOGTIMEOUT_2KB ETH_MACWTR_WTO_2KB
1188 #define ETH_WATCHDOGTIMEOUT_3KB ETH_MACWTR_WTO_3KB
1189 #define ETH_WATCHDOGTIMEOUT_4KB ETH_MACWTR_WTO_4KB
1190 #define ETH_WATCHDOGTIMEOUT_5KB ETH_MACWTR_WTO_5KB
1191 #define ETH_WATCHDOGTIMEOUT_6KB ETH_MACWTR_WTO_6KB
1192 #define ETH_WATCHDOGTIMEOUT_7KB ETH_MACWTR_WTO_7KB
1193 #define ETH_WATCHDOGTIMEOUT_8KB ETH_MACWTR_WTO_8KB
1194 #define ETH_WATCHDOGTIMEOUT_9KB ETH_MACWTR_WTO_9KB
1195 #define ETH_WATCHDOGTIMEOUT_10KB ETH_MACWTR_WTO_10KB
1196 #define ETH_WATCHDOGTIMEOUT_11KB ETH_MACWTR_WTO_12KB
1197 #define ETH_WATCHDOGTIMEOUT_12KB ETH_MACWTR_WTO_12KB
1198 #define ETH_WATCHDOGTIMEOUT_13KB ETH_MACWTR_WTO_13KB
1199 #define ETH_WATCHDOGTIMEOUT_14KB ETH_MACWTR_WTO_14KB
1200 #define ETH_WATCHDOGTIMEOUT_15KB ETH_MACWTR_WTO_15KB
1201 #define ETH_WATCHDOGTIMEOUT_16KB ETH_MACWTR_WTO_16KB
1203 * @}
1206 /** @defgroup ETH_Inter_Packet_Gap ETH Inter Packet Gap
1207 * @{
1209 #define ETH_INTERPACKETGAP_96BIT ETH_MACCR_IPG_96BIT
1210 #define ETH_INTERPACKETGAP_88BIT ETH_MACCR_IPG_88BIT
1211 #define ETH_INTERPACKETGAP_80BIT ETH_MACCR_IPG_80BIT
1212 #define ETH_INTERPACKETGAP_72BIT ETH_MACCR_IPG_72BIT
1213 #define ETH_INTERPACKETGAP_64BIT ETH_MACCR_IPG_64BIT
1214 #define ETH_INTERPACKETGAP_56BIT ETH_MACCR_IPG_56BIT
1215 #define ETH_INTERPACKETGAP_48BIT ETH_MACCR_IPG_48BIT
1216 #define ETH_INTERPACKETGAP_40BIT ETH_MACCR_IPG_40BIT
1218 * @}
1221 /** @defgroup ETH_Speed ETH Speed
1222 * @{
1224 #define ETH_SPEED_10M ((uint32_t)0x00000000U)
1225 #define ETH_SPEED_100M ETH_MACCR_FES
1227 * @}
1230 /** @defgroup ETH_Duplex_Mode ETH Duplex Mode
1231 * @{
1233 #define ETH_FULLDUPLEX_MODE ETH_MACCR_DM
1234 #define ETH_HALFDUPLEX_MODE ((uint32_t)0x00000000U)
1236 * @}
1239 /** @defgroup ETH_Back_Off_Limit ETH Back Off Limit
1240 * @{
1242 #define ETH_BACKOFFLIMIT_10 ETH_MACCR_BL_10
1243 #define ETH_BACKOFFLIMIT_8 ETH_MACCR_BL_8
1244 #define ETH_BACKOFFLIMIT_4 ETH_MACCR_BL_4
1245 #define ETH_BACKOFFLIMIT_1 ETH_MACCR_BL_1
1247 * @}
1250 /** @defgroup ETH_Preamble_Length ETH Preamble Length
1251 * @{
1253 #define ETH_PREAMBLELENGTH_7 ETH_MACCR_PRELEN_7
1254 #define ETH_PREAMBLELENGTH_5 ETH_MACCR_PRELEN_5
1255 #define ETH_PREAMBLELENGTH_3 ETH_MACCR_PRELEN_3
1257 * @}
1260 /** @defgroup ETH_Source_Addr_Control ETH Source Addr Control
1261 * @{
1263 #define ETH_SOURCEADDRESS_DISABLE ((uint32_t)0x00000000U)
1264 #define ETH_SOURCEADDRESS_INSERT_ADDR0 ETH_MACCR_SARC_INSADDR0
1265 #define ETH_SOURCEADDRESS_INSERT_ADDR1 ETH_MACCR_SARC_INSADDR1
1266 #define ETH_SOURCEADDRESS_REPLACE_ADDR0 ETH_MACCR_SARC_REPADDR0
1267 #define ETH_SOURCEADDRESS_REPLACE_ADDR1 ETH_MACCR_SARC_REPADDR1
1269 * @}
1272 /** @defgroup ETH_Control_Packets_Filter ETH Control Packets Filter
1273 * @{
1275 #define ETH_CTRLPACKETS_BLOCK_ALL ETH_MACPFR_PCF_BLOCKALL
1276 #define ETH_CTRLPACKETS_FORWARD_ALL_EXCEPT_PA ETH_MACPFR_PCF_FORWARDALLEXCEPTPA
1277 #define ETH_CTRLPACKETS_FORWARD_ALL ETH_MACPFR_PCF_FORWARDALL
1278 #define ETH_CTRLPACKETS_FORWARD_PASSED_ADDR_FILTER ETH_MACPFR_PCF_FORWARDPASSEDADDRFILTER
1280 * @}
1283 /** @defgroup ETH_VLAN_Tag_Comparison ETH VLAN Tag Comparison
1284 * @{
1286 #define ETH_VLANTAGCOMPARISON_16BIT ((uint32_t)0x00000000U)
1287 #define ETH_VLANTAGCOMPARISON_12BIT ETH_MACVTR_ETV
1289 * @}
1292 /** @defgroup ETH_MAC_addresses ETH MAC addresses
1293 * @{
1295 #define ETH_MAC_ADDRESS0 ((uint32_t)0x00000000U)
1296 #define ETH_MAC_ADDRESS1 ((uint32_t)0x00000008U)
1297 #define ETH_MAC_ADDRESS2 ((uint32_t)0x00000010U)
1298 #define ETH_MAC_ADDRESS3 ((uint32_t)0x00000018U)
1300 * @}
1303 /** @defgroup ETH_MAC_Interrupts ETH MAC Interrupts
1304 * @{
1306 #define ETH_MAC_RX_STATUS_IT ETH_MACIER_RXSTSIE
1307 #define ETH_MAC_TX_STATUS_IT ETH_MACIER_TXSTSIE
1308 #define ETH_MAC_TIMESTAMP_IT ETH_MACIER_TSIE
1309 #define ETH_MAC_LPI_IT ETH_MACIER_LPIIE
1310 #define ETH_MAC_PMT_IT ETH_MACIER_PMTIE
1311 #define ETH_MAC_PHY_IT ETH_MACIER_PHYIE
1313 * @}
1316 /** @defgroup ETH_MAC_Wake_Up_Event ETH MAC Wake Up Event
1317 * @{
1319 #define ETH_WAKEUP_PACKET_RECIEVED ETH_MACPCSR_RWKPRCVD
1320 #define ETH_MAGIC_PACKET_RECIEVED ETH_MACPCSR_MGKPRCVD
1322 * @}
1325 /** @defgroup ETH_MAC_Rx_Tx_Status ETH MAC Rx Tx Status
1326 * @{
1328 #define ETH_RECEIVE_WATCHDOG_TIMEOUT ETH_MACRXTXSR_RWT
1329 #define ETH_EXECESSIVE_COLLISIONS ETH_MACRXTXSR_EXCOL
1330 #define ETH_LATE_COLLISIONS ETH_MACRXTXSR_LCOL
1331 #define ETH_EXECESSIVE_DEFERRAL ETH_MACRXTXSR_EXDEF
1332 #define ETH_LOSS_OF_CARRIER ETH_MACRXTXSR_LCARR
1333 #define ETH_NO_CARRIER ETH_MACRXTXSR_NCARR
1334 #define ETH_TRANSMIT_JABBR_TIMEOUT ETH_MACRXTXSR_TJT
1336 * @}
1339 /** @defgroup HAL_ETH_StateTypeDef ETH States
1340 * @{
1342 #define HAL_ETH_STATE_RESET ((uint32_t)0x00000000U) /*!< Peripheral not yet Initialized or disabled */
1343 #define HAL_ETH_STATE_READY ((uint32_t)0x00000010U) /*!< Peripheral Communication started */
1344 #define HAL_ETH_STATE_BUSY ((uint32_t)0x00000023U) /*!< an internal process is ongoing */
1345 #define HAL_ETH_STATE_BUSY_TX ((uint32_t)0x00000021U) /*!< Transmission process is ongoing */
1346 #define HAL_ETH_STATE_BUSY_RX ((uint32_t)0x00000022U) /*!< Reception process is ongoing */
1347 #define HAL_ETH_STATE_ERROR ((uint32_t)0x000000E0U) /*!< Error State */
1349 * @}
1352 * @}
1355 /* Exported macro ------------------------------------------------------------*/
1356 /** @defgroup ETH_Exported_Macros ETH Exported Macros
1357 * @{
1360 /** @brief Reset ETH handle state
1361 * @param __HANDLE__: specifies the ETH handle.
1362 * @retval None
1364 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1365 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1366 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1367 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1368 (__HANDLE__)->MspInitCallback = NULL; \
1369 (__HANDLE__)->MspDeInitCallback = NULL; \
1370 } while(0)
1371 #else
1372 #define __HAL_ETH_RESET_HANDLE_STATE(__HANDLE__) do{ \
1373 (__HANDLE__)->gState = HAL_ETH_STATE_RESET; \
1374 (__HANDLE__)->RxState = HAL_ETH_STATE_RESET; \
1375 } while(0)
1376 #endif /*USE_HAL_ETH_REGISTER_CALLBACKS */
1378 /**
1379 * @brief Enables the specified ETHERNET DMA interrupts.
1380 * @param __HANDLE__ : ETH Handle
1381 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1382 * enabled @ref ETH_DMA_Interrupts
1383 * @retval None
1385 #define __HAL_ETH_DMA_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER |= (__INTERRUPT__))
1388 * @brief Disables the specified ETHERNET DMA interrupts.
1389 * @param __HANDLE__ : ETH Handle
1390 * @param __INTERRUPT__: specifies the ETHERNET DMA interrupt sources to be
1391 * disabled. @ref ETH_DMA_Interrupts
1392 * @retval None
1394 #define __HAL_ETH_DMA_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACIER &= ~(__INTERRUPT__))
1397 * @brief Gets the ETHERNET DMA IT source enabled or disabled.
1398 * @param __HANDLE__ : ETH Handle
1399 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1400 * @retval The ETH DMA IT Source enabled or disabled
1402 #define __HAL_ETH_DMA_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACIER & (__INTERRUPT__)) == (__INTERRUPT__))
1405 * @brief Gets the ETHERNET DMA IT pending bit.
1406 * @param __HANDLE__ : ETH Handle
1407 * @param __INTERRUPT__: specifies the interrupt source to get . @ref ETH_DMA_Interrupts
1408 * @retval The state of ETH DMA IT (SET or RESET)
1410 #define __HAL_ETH_DMA_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->DMACSR & (__INTERRUPT__)) == (__INTERRUPT__))
1413 * @brief Clears the ETHERNET DMA IT pending bit.
1414 * @param __HANDLE__ : ETH Handle
1415 * @param __INTERRUPT__: specifies the interrupt pending bit to clear. @ref ETH_DMA_Interrupts
1416 * @retval None
1418 #define __HAL_ETH_DMA_CLEAR_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->DMACSR = (__INTERRUPT__))
1421 * @brief Checks whether the specified ETHERNET DMA flag is set or not.
1422 * @param __HANDLE__: ETH Handle
1423 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1424 * @retval The state of ETH DMA FLAG (SET or RESET).
1426 #define __HAL_ETH_DMA_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->Instance->DMACSR &( __FLAG__)) == ( __FLAG__))
1429 * @brief Clears the specified ETHERNET DMA flag.
1430 * @param __HANDLE__: ETH Handle
1431 * @param __FLAG__: specifies the flag to check. @ref ETH_DMA_Status_Flags
1432 * @retval The state of ETH DMA FLAG (SET or RESET).
1434 #define __HAL_ETH_DMA_CLEAR_FLAG(__HANDLE__, __FLAG__) ((__HANDLE__)->Instance->DMACSR = ( __FLAG__))
1436 /**
1437 * @brief Enables the specified ETHERNET MAC interrupts.
1438 * @param __HANDLE__ : ETH Handle
1439 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1440 * enabled @ref ETH_MAC_Interrupts
1441 * @retval None
1443 #define __HAL_ETH_MAC_ENABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER |= (__INTERRUPT__))
1445 /**
1446 * @brief Disables the specified ETHERNET MAC interrupts.
1447 * @param __HANDLE__ : ETH Handle
1448 * @param __INTERRUPT__: specifies the ETHERNET MAC interrupt sources to be
1449 * enabled @ref ETH_MAC_Interrupts
1450 * @retval None
1452 #define __HAL_ETH_MAC_DISABLE_IT(__HANDLE__, __INTERRUPT__) ((__HANDLE__)->Instance->MACIER &= ~(__INTERRUPT__))
1455 * @brief Checks whether the specified ETHERNET MAC flag is set or not.
1456 * @param __HANDLE__: ETH Handle
1457 * @param __INTERRUPT__: specifies the flag to check. @ref ETH_MAC_Interrupts
1458 * @retval The state of ETH MAC IT (SET or RESET).
1460 #define __HAL_ETH_MAC_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->Instance->MACISR &( __INTERRUPT__)) == ( __INTERRUPT__))
1462 /*!< External interrupt line 86 Connected to the ETH wakeup EXTI Line */
1463 #define ETH_WAKEUP_EXTI_LINE ((uint32_t)0x00400000U) /* !< 86 - 64 = 22 */
1466 * @brief Enable the ETH WAKEUP Exti Line.
1467 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1468 * @arg ETH_WAKEUP_EXTI_LINE
1469 * @retval None.
1471 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_IT(__EXTI_LINE__) (EXTI_D1->IMR3 |= (__EXTI_LINE__))
1474 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1475 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1476 * @arg ETH_WAKEUP_EXTI_LINE
1477 * @retval EXTI ETH WAKEUP Line Status.
1479 #define __HAL_ETH_WAKEUP_EXTI_GET_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 & (__EXTI_LINE__))
1482 * @brief Clear the ETH WAKEUP Exti flag.
1483 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1484 * @arg ETH_WAKEUP_EXTI_LINE
1485 * @retval None.
1487 #define __HAL_ETH_WAKEUP_EXTI_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D1->PR3 = (__EXTI_LINE__))
1489 #if defined(DUAL_CORE)
1491 * @brief Enable the ETH WAKEUP Exti Line by Core2.
1492 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be enabled.
1493 * @arg ETH_WAKEUP_EXTI_LINE
1494 * @retval None.
1496 #define __HAL_ETH_WAKEUP_EXTID2_ENABLE_IT(__EXTI_LINE__) (EXTI_D2->IMR3 |= (__EXTI_LINE__))
1499 * @brief checks whether the specified ETH WAKEUP Exti interrupt flag is set or not.
1500 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1501 * @arg ETH_WAKEUP_EXTI_LINE
1502 * @retval EXTI ETH WAKEUP Line Status.
1504 #define __HAL_ETH_WAKEUP_EXTID2_GET_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 & (__EXTI_LINE__))
1507 * @brief Clear the ETH WAKEUP Exti flag.
1508 * @param __EXTI_LINE__: specifies the ETH WAKEUP Exti sources to be cleared.
1509 * @arg ETH_WAKEUP_EXTI_LINE
1510 * @retval None.
1512 #define __HAL_ETH_WAKEUP_EXTID2_CLEAR_FLAG(__EXTI_LINE__) (EXTI_D2->PR3 = (__EXTI_LINE__))
1513 #endif
1516 * @brief enable rising edge interrupt on selected EXTI line.
1517 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1518 * @arg ETH_WAKEUP_EXTI_LINE
1519 * @retval None
1521 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_EDGE(__EXTI_LINE__) (EXTI->FTSR3 &= ~(__EXTI_LINE__)); \
1522 (EXTI->RTSR3 |= (__EXTI_LINE__))
1525 * @brief enable falling edge interrupt on selected EXTI line.
1526 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1527 * @arg ETH_WAKEUP_EXTI_LINE
1528 * @retval None
1530 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 &= ~(__EXTI_LINE__));\
1531 (EXTI->FTSR3 |= (__EXTI_LINE__))
1534 * @brief enable falling edge interrupt on selected EXTI line.
1535 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1536 * @arg ETH_WAKEUP_EXTI_LINE
1537 * @retval None
1539 #define __HAL_ETH_WAKEUP_EXTI_ENABLE_RISING_FALLING_EDGE(__EXTI_LINE__) (EXTI->RTSR3 |= (__EXTI_LINE__));\
1540 (EXTI->FTSR3 |= (__EXTI_LINE__))
1543 * @brief Generates a Software interrupt on selected EXTI line.
1544 * @param __EXTI_LINE__: specifies the ETH WAKEUP EXTI sources to be disabled.
1545 * @arg ETH_WAKEUP_EXTI_LINE
1546 * @retval None
1548 #define __HAL_ETH_WAKEUP_EXTI_GENERATE_SWIT(__EXTI_LINE__) (EXTI->SWIER3 |= (__EXTI_LINE__))
1551 * @}
1554 /* Include ETH HAL Extension module */
1555 #include "stm32h7xx_hal_eth_ex.h"
1557 /* Exported functions --------------------------------------------------------*/
1559 /** @addtogroup ETH_Exported_Functions
1560 * @{
1563 /** @addtogroup ETH_Exported_Functions_Group1
1564 * @{
1566 /* Initialization and de initialization functions **********************************/
1567 HAL_StatusTypeDef HAL_ETH_Init(ETH_HandleTypeDef *heth);
1568 HAL_StatusTypeDef HAL_ETH_DeInit(ETH_HandleTypeDef *heth);
1569 void HAL_ETH_MspInit(ETH_HandleTypeDef *heth);
1570 void HAL_ETH_MspDeInit(ETH_HandleTypeDef *heth);
1571 HAL_StatusTypeDef HAL_ETH_DescAssignMemory(ETH_HandleTypeDef *heth, uint32_t Index, uint8_t *pBuffer1,uint8_t *pBuffer2);
1573 /* Callbacks Register/UnRegister functions ***********************************/
1574 #if (USE_HAL_ETH_REGISTER_CALLBACKS == 1)
1575 HAL_StatusTypeDef HAL_ETH_RegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID, pETH_CallbackTypeDef pCallback);
1576 HAL_StatusTypeDef HAL_ETH_UnRegisterCallback(ETH_HandleTypeDef *heth, HAL_ETH_CallbackIDTypeDef CallbackID);
1577 #endif /* USE_HAL_ETH_REGISTER_CALLBACKS */
1580 * @}
1583 /** @addtogroup ETH_Exported_Functions_Group2
1584 * @{
1586 /* IO operation functions *******************************************************/
1587 HAL_StatusTypeDef HAL_ETH_Start(ETH_HandleTypeDef *heth);
1588 HAL_StatusTypeDef HAL_ETH_Start_IT(ETH_HandleTypeDef *heth);
1589 HAL_StatusTypeDef HAL_ETH_Stop(ETH_HandleTypeDef *heth);
1590 HAL_StatusTypeDef HAL_ETH_Stop_IT(ETH_HandleTypeDef *heth);
1592 uint8_t HAL_ETH_IsRxDataAvailable(ETH_HandleTypeDef *heth);
1593 HAL_StatusTypeDef HAL_ETH_GetRxDataBuffer(ETH_HandleTypeDef *heth, ETH_BufferTypeDef *RxBuffer);
1594 HAL_StatusTypeDef HAL_ETH_GetRxDataLength(ETH_HandleTypeDef *heth, uint32_t *Length);
1595 HAL_StatusTypeDef HAL_ETH_GetRxDataInfo(ETH_HandleTypeDef *heth, ETH_RxPacketInfo *RxPacketInfo);
1596 HAL_StatusTypeDef HAL_ETH_BuildRxDescriptors(ETH_HandleTypeDef *heth);
1598 HAL_StatusTypeDef HAL_ETH_Transmit(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig, uint32_t Timeout);
1599 HAL_StatusTypeDef HAL_ETH_Transmit_IT(ETH_HandleTypeDef *heth, ETH_TxPacketConfig *pTxConfig);
1601 HAL_StatusTypeDef HAL_ETH_WritePHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t RegValue);
1602 HAL_StatusTypeDef HAL_ETH_ReadPHYRegister(ETH_HandleTypeDef *heth, uint32_t PHYAddr, uint32_t PHYReg, uint32_t *pRegValue);
1604 void HAL_ETH_IRQHandler(ETH_HandleTypeDef *heth);
1605 void HAL_ETH_TxCpltCallback(ETH_HandleTypeDef *heth);
1606 void HAL_ETH_RxCpltCallback(ETH_HandleTypeDef *heth);
1607 void HAL_ETH_DMAErrorCallback(ETH_HandleTypeDef *heth);
1608 void HAL_ETH_MACErrorCallback(ETH_HandleTypeDef *heth);
1609 void HAL_ETH_PMTCallback(ETH_HandleTypeDef *heth);
1610 void HAL_ETH_EEECallback(ETH_HandleTypeDef *heth);
1611 void HAL_ETH_WakeUpCallback(ETH_HandleTypeDef *heth);
1613 * @}
1616 /** @addtogroup ETH_Exported_Functions_Group3
1617 * @{
1619 /* Peripheral Control functions **********************************************/
1620 /* MAC & DMA Configuration APIs **********************************************/
1621 HAL_StatusTypeDef HAL_ETH_GetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1622 HAL_StatusTypeDef HAL_ETH_GetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1623 HAL_StatusTypeDef HAL_ETH_SetMACConfig(ETH_HandleTypeDef *heth, ETH_MACConfigTypeDef *macconf);
1624 HAL_StatusTypeDef HAL_ETH_SetDMAConfig(ETH_HandleTypeDef *heth, ETH_DMAConfigTypeDef *dmaconf);
1625 void HAL_ETH_SetMDIOClockRange(ETH_HandleTypeDef *heth);
1627 /* MAC VLAN Processing APIs ************************************************/
1628 void HAL_ETH_SetRxVLANIdentifier(ETH_HandleTypeDef *heth, uint32_t ComparisonBits, uint32_t VLANIdentifier);
1630 /* MAC L2 Packet Filtering APIs **********************************************/
1631 HAL_StatusTypeDef HAL_ETH_GetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1632 HAL_StatusTypeDef HAL_ETH_SetMACFilterConfig(ETH_HandleTypeDef *heth, ETH_MACFilterConfigTypeDef *pFilterConfig);
1633 HAL_StatusTypeDef HAL_ETH_SetHashTable(ETH_HandleTypeDef *heth, uint32_t *pHashTable);
1634 HAL_StatusTypeDef HAL_ETH_SetSourceMACAddrMatch(ETH_HandleTypeDef *heth, uint32_t AddrNbr, uint8_t *pMACAddr);
1636 /* MAC Power Down APIs *****************************************************/
1637 void HAL_ETH_EnterPowerDownMode(ETH_HandleTypeDef *heth, ETH_PowerDownConfigTypeDef *pPowerDownConfig);
1638 void HAL_ETH_ExitPowerDownMode(ETH_HandleTypeDef *heth);
1639 HAL_StatusTypeDef HAL_ETH_SetWakeUpFilter(ETH_HandleTypeDef *heth, uint32_t *pFilter, uint32_t Count);
1642 * @}
1645 /** @addtogroup ETH_Exported_Functions_Group4
1646 * @{
1648 /* Peripheral State functions **************************************************/
1649 HAL_ETH_StateTypeDef HAL_ETH_GetState(ETH_HandleTypeDef *heth);
1650 uint32_t HAL_ETH_GetError(ETH_HandleTypeDef *heth);
1651 uint32_t HAL_ETH_GetDMAError(ETH_HandleTypeDef *heth);
1652 uint32_t HAL_ETH_GetMACError(ETH_HandleTypeDef *heth);
1653 uint32_t HAL_ETH_GetMACWakeUpSource(ETH_HandleTypeDef *heth);
1655 * @}
1659 * @}
1663 * @}
1667 * @}
1670 #endif /* ETH */
1672 #ifdef __cplusplus
1674 #endif
1676 #endif /* STM32H7xx_HAL_ETH_H */
1680 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/