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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_hal_fdcan.h
bloba2c479168a97b8db030f757dbf4f5be482a67565
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_hal_fdcan.h
4 * @author MCD Application Team
5 * @brief Header file of FDCAN HAL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_HAL_FDCAN_H
22 #define STM32H7xx_HAL_FDCAN_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx_hal_def.h"
30
31 /** @addtogroup STM32H7xx_HAL_Driver
32 * @{
33 */
34
35 /** @addtogroup FDCAN
36 * @{
37 */
38
39 /* Exported types ------------------------------------------------------------*/
40 /** @defgroup FDCAN_Exported_Types FDCAN Exported Types
41 * @{
42 */
43
44 /**
45 * @brief HAL State structures definition
46 */
47 typedef enum
48 {
49 HAL_FDCAN_STATE_RESET = 0x00U, /*!< FDCAN not yet initialized or disabled */
50 HAL_FDCAN_STATE_READY = 0x01U, /*!< FDCAN initialized and ready for use */
51 HAL_FDCAN_STATE_BUSY = 0x02U, /*!< FDCAN process is ongoing */
52 HAL_FDCAN_STATE_ERROR = 0x03U /*!< FDCAN error state */
53 } HAL_FDCAN_StateTypeDef;
54
55 /**
56 * @brief FDCAN Init structure definition
57 */
58 typedef struct
59 {
60 uint32_t FrameFormat; /*!< Specifies the FDCAN frame format.
61 This parameter can be a value of @ref FDCAN_frame_format */
62
63 uint32_t Mode; /*!< Specifies the FDCAN mode.
64 This parameter can be a value of @ref FDCAN_operating_mode */
65
66 FunctionalState AutoRetransmission; /*!< Enable or disable the automatic retransmission mode.
67 This parameter can be set to ENABLE or DISABLE */
68
69 FunctionalState TransmitPause; /*!< Enable or disable the Transmit Pause feature.
70 This parameter can be set to ENABLE or DISABLE */
71
72 FunctionalState ProtocolException; /*!< Enable or disable the Protocol Exception Handling.
73 This parameter can be set to ENABLE or DISABLE */
74
75 uint32_t NominalPrescaler; /*!< Specifies the value by which the oscillator frequency is
76 divided for generating the nominal bit time quanta.
77 This parameter must be a number between 1 and 512 */
78
79 uint32_t NominalSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
80 hardware is allowed to lengthen or shorten a bit to perform
81 resynchronization.
82 This parameter must be a number between 1 and 128 */
83
84 uint32_t NominalTimeSeg1; /*!< Specifies the number of time quanta in Bit Segment 1.
85 This parameter must be a number between 2 and 256 */
86
87 uint32_t NominalTimeSeg2; /*!< Specifies the number of time quanta in Bit Segment 2.
88 This parameter must be a number between 2 and 128 */
89
90 uint32_t DataPrescaler; /*!< Specifies the value by which the oscillator frequency is
91 divided for generating the data bit time quanta.
92 This parameter must be a number between 1 and 32 */
93
94 uint32_t DataSyncJumpWidth; /*!< Specifies the maximum number of time quanta the FDCAN
95 hardware is allowed to lengthen or shorten a data bit to
96 perform resynchronization.
97 This parameter must be a number between 1 and 16 */
98
99 uint32_t DataTimeSeg1; /*!< Specifies the number of time quanta in Data Bit Segment 1.
100 This parameter must be a number between 1 and 32 */
101
102 uint32_t DataTimeSeg2; /*!< Specifies the number of time quanta in Data Bit Segment 2.
103 This parameter must be a number between 1 and 16 */
104
105 uint32_t MessageRAMOffset; /*!< Specifies the message RAM start address.
106 This parameter must be a number between 0 and 2560 */
107
108 uint32_t StdFiltersNbr; /*!< Specifies the number of standard Message ID filters.
109 This parameter must be a number between 0 and 128 */
110
111 uint32_t ExtFiltersNbr; /*!< Specifies the number of extended Message ID filters.
112 This parameter must be a number between 0 and 64 */
113
114 uint32_t RxFifo0ElmtsNbr; /*!< Specifies the number of Rx FIFO0 Elements.
115 This parameter must be a number between 0 and 64 */
116
117 uint32_t RxFifo0ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 0 element.
118 This parameter can be a value of @ref FDCAN_data_field_size */
119
120 uint32_t RxFifo1ElmtsNbr; /*!< Specifies the number of Rx FIFO 1 Elements.
121 This parameter must be a number between 0 and 64 */
122
123 uint32_t RxFifo1ElmtSize; /*!< Specifies the Data Field Size in an Rx FIFO 1 element.
124 This parameter can be a value of @ref FDCAN_data_field_size */
125
126 uint32_t RxBuffersNbr; /*!< Specifies the number of Dedicated Rx Buffer elements.
127 This parameter must be a number between 0 and 64 */
128
129 uint32_t RxBufferSize; /*!< Specifies the Data Field Size in an Rx Buffer element.
130 This parameter can be a value of @ref FDCAN_data_field_size */
131
132 uint32_t TxEventsNbr; /*!< Specifies the number of Tx Event FIFO elements.
133 This parameter must be a number between 0 and 32 */
134
135 uint32_t TxBuffersNbr; /*!< Specifies the number of Dedicated Tx Buffers.
136 This parameter must be a number between 0 and 32 */
137
138 uint32_t TxFifoQueueElmtsNbr; /*!< Specifies the number of Tx Buffers used for Tx FIFO/Queue.
139 This parameter must be a number between 0 and 32 */
140
141 uint32_t TxFifoQueueMode; /*!< Tx FIFO/Queue Mode selection.
142 This parameter can be a value of @ref FDCAN_txFifoQueue_Mode */
143
144 uint32_t TxElmtSize; /*!< Specifies the Data Field Size in a Tx Element.
145 This parameter can be a value of @ref FDCAN_data_field_size */
146
147 } FDCAN_InitTypeDef;
148
149 /**
150 * @brief FDCAN clock calibration unit structure definition
151 */
152 typedef struct
153 {
154 uint32_t ClockCalibration; /*!< Enable or disable the clock calibration.
155 This parameter can be a value of @ref FDCAN_clock_calibration. */
156
157 uint32_t ClockDivider; /*!< Specifies the FDCAN kernel clock divider when the clock calibration
158 is bypassed.
159 This parameter can be a value of @ref FDCAN_clock_divider */
160
161 uint32_t MinOscClkPeriods; /*!< Configures the minimum number of periods in two CAN bit times. The
162 actual configured number of periods is MinOscClkPeriods x 32.
163 This parameter must be a number between 0x00 and 0xFF */
164
165 uint32_t CalFieldLength; /*!< Specifies the calibration field length.
166 This parameter can be a value of @ref FDCAN_calibration_field_length */
167
168 uint32_t TimeQuantaPerBitTime; /*!< Configures the number of time quanta per bit time.
169 This parameter must be a number between 4 and 25 */
170
171 uint32_t WatchdogStartValue; /*!< Start value of the Calibration Watchdog Counter.
172 If set to zero the counter is disabled.
173 This parameter must be a number between 0x0000 and 0xFFFF */
174
175 } FDCAN_ClkCalUnitTypeDef;
176
177 /**
178 * @brief FDCAN filter structure definition
179 */
180 typedef struct
181 {
182 uint32_t IdType; /*!< Specifies the identifier type.
183 This parameter can be a value of @ref FDCAN_id_type */
184
185 uint32_t FilterIndex; /*!< Specifies the filter which will be initialized.
186 This parameter must be a number between:
187 - 0 and 127, if IdType is FDCAN_STANDARD_ID
188 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
189
190 uint32_t FilterType; /*!< Specifies the filter type.
191 This parameter can be a value of @ref FDCAN_filter_type.
192 The value FDCAN_EXT_FILTER_RANGE_NO_EIDM is permitted
193 only when IdType is FDCAN_EXTENDED_ID.
194 This parameter is ignored if FilterConfig is set to
195 FDCAN_FILTER_TO_RXBUFFER */
196
197 uint32_t FilterConfig; /*!< Specifies the filter configuration.
198 This parameter can be a value of @ref FDCAN_filter_config */
199
200 uint32_t FilterID1; /*!< Specifies the filter identification 1.
201 This parameter must be a number between:
202 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
203 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
204
205 uint32_t FilterID2; /*!< Specifies the filter identification 2.
206 This parameter is ignored if FilterConfig is set to
207 FDCAN_FILTER_TO_RXBUFFER.
208 This parameter must be a number between:
209 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
210 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
211
212 uint32_t RxBufferIndex; /*!< Contains the index of the Rx buffer in which the
213 matching message will be stored.
214 This parameter must be a number between 0 and 63.
215 This parameter is ignored if FilterConfig is different
216 from FDCAN_FILTER_TO_RXBUFFER */
217
218 uint32_t IsCalibrationMsg; /*!< Specifies whether the filter is configured for
219 calibration messages.
220 This parameter is ignored if FilterConfig is different
221 from FDCAN_FILTER_TO_RXBUFFER.
222 This parameter can be:
223 - 0 : ordinary message
224 - 1 : calibration message */
225
226 } FDCAN_FilterTypeDef;
227
228 /**
229 * @brief FDCAN Tx header structure definition
230 */
231 typedef struct
232 {
233 uint32_t Identifier; /*!< Specifies the identifier.
234 This parameter must be a number between:
235 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
236 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
237
238 uint32_t IdType; /*!< Specifies the identifier type for the message that will be
239 transmitted.
240 This parameter can be a value of @ref FDCAN_id_type */
241
242 uint32_t TxFrameType; /*!< Specifies the frame type of the message that will be transmitted.
243 This parameter can be a value of @ref FDCAN_frame_type */
244
245 uint32_t DataLength; /*!< Specifies the length of the frame that will be transmitted.
246 This parameter can be a value of @ref FDCAN_data_length_code */
247
248 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
249 This parameter can be a value of @ref FDCAN_error_state_indicator */
250
251 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame will be transmitted with or without
252 bit rate switching.
253 This parameter can be a value of @ref FDCAN_bit_rate_switching */
254
255 uint32_t FDFormat; /*!< Specifies whether the Tx frame will be transmitted in classic or
256 FD format.
257 This parameter can be a value of @ref FDCAN_format */
258
259 uint32_t TxEventFifoControl; /*!< Specifies the event FIFO control.
260 This parameter can be a value of @ref FDCAN_EFC */
261
262 uint32_t MessageMarker; /*!< Specifies the message marker to be copied into Tx Event FIFO
263 element for identification of Tx message status.
264 This parameter must be a number between 0 and 0xFF */
265
266 } FDCAN_TxHeaderTypeDef;
267
268 /**
269 * @brief FDCAN Rx header structure definition
270 */
271 typedef struct
272 {
273 uint32_t Identifier; /*!< Specifies the identifier.
274 This parameter must be a number between:
275 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
276 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
277
278 uint32_t IdType; /*!< Specifies the identifier type of the received message.
279 This parameter can be a value of @ref FDCAN_id_type */
280
281 uint32_t RxFrameType; /*!< Specifies the the received message frame type.
282 This parameter can be a value of @ref FDCAN_frame_type */
283
284 uint32_t DataLength; /*!< Specifies the received frame length.
285 This parameter can be a value of @ref FDCAN_data_length_code */
286
287 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
288 This parameter can be a value of @ref FDCAN_error_state_indicator */
289
290 uint32_t BitRateSwitch; /*!< Specifies whether the Rx frame is received with or without bit
291 rate switching.
292 This parameter can be a value of @ref FDCAN_bit_rate_switching */
293
294 uint32_t FDFormat; /*!< Specifies whether the Rx frame is received in classic or FD
295 format.
296 This parameter can be a value of @ref FDCAN_format */
297
298 uint32_t RxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
299 reception.
300 This parameter must be a number between 0 and 0xFFFF */
301
302 uint32_t FilterIndex; /*!< Specifies the index of matching Rx acceptance filter element.
303 This parameter must be a number between:
304 - 0 and 127, if IdType is FDCAN_STANDARD_ID
305 - 0 and 63, if IdType is FDCAN_EXTENDED_ID */
306
307 uint32_t IsFilterMatchingFrame; /*!< Specifies whether the accepted frame did not match any Rx filter.
308 Acceptance of non-matching frames may be enabled via
309 HAL_FDCAN_ConfigGlobalFilter().
310 This parameter can be 0 or 1 */
311
312 } FDCAN_RxHeaderTypeDef;
313
314 /**
315 * @brief FDCAN Tx event FIFO structure definition
316 */
317 typedef struct
318 {
319 uint32_t Identifier; /*!< Specifies the identifier.
320 This parameter must be a number between:
321 - 0 and 0x7FF, if IdType is FDCAN_STANDARD_ID
322 - 0 and 0x1FFFFFFF, if IdType is FDCAN_EXTENDED_ID */
323
324 uint32_t IdType; /*!< Specifies the identifier type for the transmitted message.
325 This parameter can be a value of @ref FDCAN_id_type */
326
327 uint32_t TxFrameType; /*!< Specifies the frame type of the transmitted message.
328 This parameter can be a value of @ref FDCAN_frame_type */
329
330 uint32_t DataLength; /*!< Specifies the length of the transmitted frame.
331 This parameter can be a value of @ref FDCAN_data_length_code */
332
333 uint32_t ErrorStateIndicator; /*!< Specifies the error state indicator.
334 This parameter can be a value of @ref FDCAN_error_state_indicator */
335
336 uint32_t BitRateSwitch; /*!< Specifies whether the Tx frame is transmitted with or without bit
337 rate switching.
338 This parameter can be a value of @ref FDCAN_bit_rate_switching */
339
340 uint32_t FDFormat; /*!< Specifies whether the Tx frame is transmitted in classic or FD
341 format.
342 This parameter can be a value of @ref FDCAN_format */
343
344 uint32_t TxTimestamp; /*!< Specifies the timestamp counter value captured on start of frame
345 transmission.
346 This parameter must be a number between 0 and 0xFFFF */
347
348 uint32_t MessageMarker; /*!< Specifies the message marker copied into Tx Event FIFO element
349 for identification of Tx message status.
350 This parameter must be a number between 0 and 0xFF */
351
352 uint32_t EventType; /*!< Specifies the event type.
353 This parameter can be a value of @ref FDCAN_event_type */
354
355 } FDCAN_TxEventFifoTypeDef;
356
357 /**
358 * @brief FDCAN High Priority Message Status structure definition
359 */
360 typedef struct
361 {
362 uint32_t FilterList; /*!< Specifies the filter list of the matching filter element.
363 This parameter can be:
364 - 0 : Standard Filter List
365 - 1 : Extended Filter List */
366
367 uint32_t FilterIndex; /*!< Specifies the index of matching filter element.
368 This parameter can be a number between:
369 - 0 and 127, if FilterList is 0 (Standard)
370 - 0 and 63, if FilterList is 1 (Extended) */
371
372 uint32_t MessageStorage; /*!< Specifies the HP Message Storage.
373 This parameter can be a value of @ref FDCAN_hp_msg_storage */
374
375 uint32_t MessageIndex; /*!< Specifies the Index of Rx FIFO element to which the
376 message was stored.
377 This parameter is valid only when MessageStorage is:
378 FDCAN_HP_STORAGE_RXFIFO0
379 or
380 FDCAN_HP_STORAGE_RXFIFO1 */
381
382 } FDCAN_HpMsgStatusTypeDef;
383
384 /**
385 * @brief FDCAN Protocol Status structure definition
386 */
387 typedef struct
388 {
389 uint32_t LastErrorCode; /*!< Specifies the type of the last error that occurred on the FDCAN bus.
390 This parameter can be a value of @ref FDCAN_protocol_error_code */
391
392 uint32_t DataLastErrorCode; /*!< Specifies the type of the last error that occurred in the data phase of a CAN FD format
393 frame with its BRS flag set.
394 This parameter can be a value of @ref FDCAN_protocol_error_code */
395
396 uint32_t Activity; /*!< Specifies the FDCAN module communication state.
397 This parameter can be a value of @ref FDCAN_communication_state */
398
399 uint32_t ErrorPassive; /*!< Specifies the FDCAN module error status.
400 This parameter can be:
401 - 0 : The FDCAN is in Error_Active state
402 - 1 : The FDCAN is in Error_Passive state */
403
404 uint32_t Warning; /*!< Specifies the FDCAN module warning status.
405 This parameter can be:
406 - 0 : error counters (RxErrorCnt and TxErrorCnt) are below the Error_Warning limit of 96
407 - 1 : at least one of error counters has reached the Error_Warning limit of 96 */
408
409 uint32_t BusOff; /*!< Specifies the FDCAN module Bus_Off status.
410 This parameter can be:
411 - 0 : The FDCAN is not in Bus_Off state
412 - 1 : The FDCAN is in Bus_Off state */
413
414 uint32_t RxESIflag; /*!< Specifies ESI flag of last received CAN FD message.
415 This parameter can be:
416 - 0 : Last received CAN FD message did not have its ESI flag set
417 - 1 : Last received CAN FD message had its ESI flag set */
418
419 uint32_t RxBRSflag; /*!< Specifies BRS flag of last received CAN FD message.
420 This parameter can be:
421 - 0 : Last received CAN FD message did not have its BRS flag set
422 - 1 : Last received CAN FD message had its BRS flag set */
423
424 uint32_t RxFDFflag; /*!< Specifies if CAN FD message (FDF flag set) has been received since last protocol status.
425 This parameter can be:
426 - 0 : no CAN FD message received
427 - 1 : CAN FD message received */
428
429 uint32_t ProtocolException; /*!< Specifies the FDCAN module Protocol Exception status.
430 This parameter can be:
431 - 0 : No protocol exception event occurred since last read access
432 - 1 : Protocol exception event occurred */
433
434 uint32_t TDCvalue; /*!< Specifies the Transmitter Delay Compensation Value.
435 This parameter can be a number between 0 and 127 */
436
437 } FDCAN_ProtocolStatusTypeDef;
438
439 /**
440 * @brief FDCAN Error Counters structure definition
441 */
442 typedef struct
443 {
444 uint32_t TxErrorCnt; /*!< Specifies the Transmit Error Counter Value.
445 This parameter can be a number between 0 and 255 */
446
447 uint32_t RxErrorCnt; /*!< Specifies the Receive Error Counter Value.
448 This parameter can be a number between 0 and 127 */
449
450 uint32_t RxErrorPassive; /*!< Specifies the Receive Error Passive status.
451 This parameter can be:
452 - 0 : The Receive Error Counter (RxErrorCnt) is below the error passive level of 128
453 - 1 : The Receive Error Counter (RxErrorCnt) has reached the error passive level of 128 */
454
455 uint32_t ErrorLogging; /*!< Specifies the Transmit/Receive error logging counter value.
456 This parameter can be a number between 0 and 255.
457 This counter is incremented each time when a FDCAN protocol error causes the TxErrorCnt
458 or the RxErrorCnt to be incremented. The counter stops at 255; the next increment of
459 TxErrorCnt or RxErrorCnt sets interrupt flag FDCAN_FLAG_ERROR_LOGGING_OVERFLOW */
460
461 } FDCAN_ErrorCountersTypeDef;
462
463 /**
464 * @brief FDCAN TT Init structure definition
465 */
466 typedef struct
467 {
468 uint32_t OperationMode; /*!< Specifies the FDCAN Operation Mode.
469 This parameter can be a value of @ref FDCAN_operation_mode */
470
471 uint32_t GapEnable; /*!< Specifies the FDCAN TT Operation.
472 This parameter can be a value of @ref FDCAN_TT_operation.
473 This parameter is ignored if OperationMode is set to
474 FDCAN_TT_COMMUNICATION_LEVEL0 */
475
476 uint32_t TimeMaster; /*!< Specifies whether the instance is a slave or a potential master.
477 This parameter can be a value of @ref FDCAN_TT_time_master */
478
479 uint32_t SyncDevLimit; /*!< Specifies the Synchronization Deviation Limit SDL of the TUR
480 numerator : TUR = (Numerator ± SDL) / Denominator.
481 With : SDL = 2^(SyncDevLimit+5).
482 This parameter must be a number between 0 and 7 */
483
484 uint32_t InitRefTrigOffset; /*!< Specifies the Initial Reference Trigger Offset.
485 This parameter must be a number between 0 and 127 */
486
487 uint32_t ExternalClkSync; /*!< Enable or disable External Clock Synchronization.
488 This parameter can be a value of @ref FDCAN_TT_external_clk_sync.
489 This parameter is ignored if OperationMode is set to
490 FDCAN_TT_COMMUNICATION_LEVEL1 */
491
492 uint32_t AppWdgLimit; /*!< Specifies the Application Watchdog Limit : maximum time after
493 which the application has to serve the application watchdog.
494 The application watchdog is incremented once each 256 NTUs.
495 The application watchdog can be disabled by setting AppWdgLimit to 0.
496 This parameter must be a number between 0 and 255.
497 This parameter is ignored if OperationMode is set to
498 FDCAN_TT_COMMUNICATION_LEVEL0 */
499
500 uint32_t GlobalTimeFilter; /*!< Enable or disable Global Time Filtering.
501 This parameter can be a value of @ref FDCAN_TT_global_time_filtering.
502 This parameter is ignored if OperationMode is set to
503 FDCAN_TT_COMMUNICATION_LEVEL1 */
504
505 uint32_t ClockCalibration; /*!< Enable or disable Automatic Clock Calibration.
506 This parameter can be a value of @ref FDCAN_TT_auto_clk_calibration.
507 This parameter is ignored if OperationMode is set to
508 FDCAN_TT_COMMUNICATION_LEVEL1 */
509
510 uint32_t EvtTrigPolarity; /*!< Specifies the Event Trigger Polarity.
511 This parameter can be a value of @ref FDCAN_TT_event_trig_polarity.
512 This parameter is ignored if OperationMode is set to
513 FDCAN_TT_COMMUNICATION_LEVEL0 */
514
515 uint32_t BasicCyclesNbr; /*!< Specifies the nubmer of basic cycles in the system matrix.
516 This parameter can be a value of @ref FDCAN_TT_basic_cycle_number */
517
518 uint32_t CycleStartSync; /*!< Enable or disable synchronization pulse output at pin fdcan1_soc.
519 This parameter can be a value of @ref FDCAN_TT_cycle_start_sync */
520
521 uint32_t TxEnableWindow; /*!< Specifies the length of Tx enable window in NTUs.
522 This parameter must be a number between 1 and 16 */
523
524 uint32_t ExpTxTrigNbr; /*!< Specifies the number of expected Tx_Triggers in the system matrix.
525 This is the sum of Tx_Triggers for exclusive, single arbitrating and
526 merged arbitrating windows.
527 This parameter must be a number between 0 and 4095 */
528
529 uint32_t TURNumerator; /*!< Specifies the TUR (Time Unit Ratio) numerator.
530 It is adviced to set this parameter to the largest applicable value.
531 This parameter must be a number between 0x10000 and 0x1FFFF */
532
533 uint32_t TURDenominator; /*!< Specifies the TUR (Time Unit Ratio) denominator.
534 This parameter must be a number between 0x0001 and 0x3FFF */
535
536 uint32_t TriggerMemoryNbr; /*!< Specifies the number of trigger memory elements.
537 This parameter must be a number between 0 and 64 */
538
539 uint32_t StopWatchTrigSel; /*!< Specifies the input to be used as stop watch trigger.
540 This parameter can be a value of @ref FDCAN_TT_stop_watch_trig_selection */
541
542 uint32_t EventTrigSel; /*!< Specifies the input to be used as event trigger.
543 This parameter can be a value of @ref FDCAN_TT_event_trig_selection */
544
545 } FDCAN_TT_ConfigTypeDef;
546
547 /**
548 * @brief FDCAN Trigger structure definition
549 */
550 typedef struct
551 {
552 uint32_t TriggerIndex; /*!< Specifies the trigger which will be configured.
553 This parameter must be a number between 0 and 63 */
554
555 uint32_t TimeMark; /*!< Specifies the cycle time for which the trigger becomes active.
556 This parameter must be a number between 0 and 0xFFFF */
557
558 uint32_t RepeatFactor; /*!< Specifies the trigger repeat factor.
559 This parameter can be a value of @ref FDCAN_TT_Repeat_Factor */
560
561 uint32_t StartCycle; /*!< Specifies the index of the first cycle in which the trigger becomes active.
562 This parameter is ignored if RepeatFactor is set to FDCAN_TT_REPEAT_EVERY_CYCLE.
563 This parameter must be a number between 0 and RepeatFactor */
564
565 uint32_t TmEventInt; /*!< Enable or disable the internal time mark event.
566 If enabled, FDCAN_TT_FLAG_TRIG_TIME_MARK flag is set when trigger memory element
567 becomes active.
568 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_Internal */
569
570 uint32_t TmEventExt; /*!< Enable or disable the external time mark event.
571 If enabled, and if TTOCN.TTIE is set, a pulse is generated at fdcan1_tmp when
572 trigger memory element becomes active.
573 This parameter can be a value of @ref FDCAN_TT_Time_Mark_Event_External */
574
575 uint32_t TriggerType; /*!< Specifies the trigger type.
576 This parameter can be a value of @ref FDCAN_TT_Trigger_Type */
577
578 uint32_t FilterType; /*!< Specifies the filter identifier type.
579 This parameter can be a value of @ref FDCAN_id_type */
580
581 uint32_t TxBufferIndex; /*!< Specifies the index of the Tx buffer for which the trigger is valid.
582 This parameter can be a value of @ref FDCAN_Tx_location.
583 This parameter is taken in consideration only if the trigger is configured for
584 transmission. */
585
586 uint32_t FilterIndex; /*!< Specifies the filter for which the trigger is valid.
587 This parameter is taken in consideration only if the trigger is configured for
588 reception.
589 This parameter must be a number between:
590 - 0 and 127, if FilterType is FDCAN_STANDARD_ID
591 - 0 and 63, if FilterType is FDCAN_EXTENDED_ID */
592
593 } FDCAN_TriggerTypeDef;
594
595 /**
596 * @brief FDCAN TT Operation Status structure definition
597 */
598 typedef struct
599 {
600 uint32_t ErrorLevel; /*!< Specifies the type of the TT operation error level.
601 This parameter can be a value of @ref FDCAN_TT_error_level */
602
603 uint32_t MasterState; /*!< Specifies the type of the TT master state.
604 This parameter can be a value of @ref FDCAN_TT_master_state */
605
606 uint32_t SyncState; /*!< Specifies the type of the TT synchronization state.
607 This parameter can be a value of @ref FDCAN_TT_sync_state */
608
609 uint32_t GTimeQuality; /*!< Specifies the Quality of Global Time Phase.
610 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 0.
611 This parameter can be:
612 - 0 : Global time not valid
613 - 1 : Global time in phase with Time Master */
614
615 uint32_t ClockQuality; /*!< Specifies the Quality of Clock Speed.
616 This parameter is only relevant in Level 0 and Level 2, otherwise fixed to 1.
617 This parameter can be:
618 - 0 : Local clock speed not synchronized to Time Master clock speed
619 - 1 : Synchronization Deviation = SDL */
620
621 uint32_t RefTrigOffset; /*!< Specifies the Actual Reference Trigger Offset Value.
622 This parameter can be a number between 0 and 0xFF */
623
624 uint32_t GTimeDiscPending; /*!< Specifies the Global Time Discontinuity State.
625 This parameter can be:
626 - 0 : No global time preset pending
627 - 1 : Node waits for the global time preset to take effect */
628
629 uint32_t GapFinished; /*!< Specifies whether a Gap is finished.
630 This parameter can be:
631 - 0 : Reset at the end of each reference message
632 - 1 : Gap finished */
633
634 uint32_t MasterPriority; /*!< Specifies the Priority of actual Time Master.
635 This parameter can be a number between 0 and 0x7 */
636
637 uint32_t GapStarted; /*!< Specifies whether a Gap is started.
638 This parameter can be:
639 - 0 : No Gap in schedule
640 - 1 : Gap time after Basic Cycle has started */
641
642 uint32_t WaitForEvt; /*!< Specifies whether a Gap is annouced.
643 This parameter can be:
644 - 0 : No Gap announced, reset by a reference message with Next_is_Gap = 0
645 - 1 : Reference message with Next_is_Gap = 1 received */
646
647 uint32_t AppWdgEvt; /*!< Specifies the Application Watchdog State.
648 This parameter can be:
649 - 0 : Application Watchdog served in time
650 - 1 : Failed to serve Application Watchdog in time */
651
652 uint32_t ECSPending; /*!< Specifies the External Clock Synchronization State.
653 This parameter can be:
654 - 0 : No external clock synchronization pending
655 - 1 : Node waits for external clock synchronization to take effect */
656
657 uint32_t PhaseLock; /*!< Specifies the Phase Lock State.
658 This parameter can be:
659 - 0 : Phase outside range
660 - 1 : Phase inside range */
661
662 } FDCAN_TTOperationStatusTypeDef;
663
664 /**
665 * @brief FDCAN Message RAM blocks
666 */
667 typedef struct
668 {
669 uint32_t StandardFilterSA; /*!< Specifies the Standard Filter List Start Address.
670 This parameter must be a 32-bit word address */
671
672 uint32_t ExtendedFilterSA; /*!< Specifies the Extended Filter List Start Address.
673 This parameter must be a 32-bit word address */
674
675 uint32_t RxFIFO0SA; /*!< Specifies the Rx FIFO 0 Start Address.
676 This parameter must be a 32-bit word address */
677
678 uint32_t RxFIFO1SA; /*!< Specifies the Rx FIFO 1 Start Address.
679 This parameter must be a 32-bit word address */
680
681 uint32_t RxBufferSA; /*!< Specifies the Rx Buffer Start Address.
682 This parameter must be a 32-bit word address */
683
684 uint32_t TxEventFIFOSA; /*!< Specifies the Tx Event FIFO Start Address.
685 This parameter must be a 32-bit word address */
686
687 uint32_t TxBufferSA; /*!< Specifies the Tx Buffers Start Address.
688 This parameter must be a 32-bit word address */
689
690 uint32_t TxFIFOQSA; /*!< Specifies the Tx FIFO/Queue Start Address.
691 This parameter must be a 32-bit word address */
692
693 uint32_t TTMemorySA; /*!< Specifies the Trigger Memory Start Address.
694 This parameter must be a 32-bit word address */
695
696 uint32_t EndAddress; /*!< Specifies the End Address of the allocated RAM.
697 This parameter must be a 32-bit word address */
698
699 } FDCAN_MsgRamAddressTypeDef;
700
701 /**
702 * @brief FDCAN handle structure definition
703 */
704 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
705 typedef struct __FDCAN_HandleTypeDef
706 #else
707 typedef struct
708 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
709 {
710 FDCAN_GlobalTypeDef *Instance; /*!< Register base address */
711
712 TTCAN_TypeDef *ttcan; /*!< TT register base address */
713
714 FDCAN_InitTypeDef Init; /*!< FDCAN required parameters */
715
716 FDCAN_MsgRamAddressTypeDef msgRam; /*!< FDCAN Message RAM blocks */
717
718 uint32_t LatestTxFifoQRequest; /*!< FDCAN Tx buffer index
719 of latest Tx FIFO/Queue request */
720
721 __IO HAL_FDCAN_StateTypeDef State; /*!< FDCAN communication state */
722
723 HAL_LockTypeDef Lock; /*!< FDCAN locking object */
724
725 __IO uint32_t ErrorCode; /*!< FDCAN Error code */
726
727 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
728 void (* ClockCalibrationCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< FDCAN Clock Calibration callback */
729 void (* TxEventFifoCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< FDCAN Tx Event Fifo callback */
730 void (* RxFifo0Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< FDCAN Rx Fifo 0 callback */
731 void (* RxFifo1Callback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< FDCAN Rx Fifo 1 callback */
732 void (* TxFifoEmptyCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Tx Fifo Empty callback */
733 void (* TxBufferCompleteCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer complete callback */
734 void (* TxBufferAbortCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< FDCAN Tx Buffer abort callback */
735 void (* RxBufferNewMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Rx Buffer New Message callback */
736 void (* HighPriorityMessageCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN High priority message callback */
737 void (* TimestampWraparoundCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timestamp wraparound callback */
738 void (* TimeoutOccurredCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Timeout occurred callback */
739 void (* ErrorCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Error callback */
740 void (* ErrorStatusCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< FDCAN Error status callback */
741 void (* TT_ScheduleSyncCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< FDCAN T Schedule Synchronization callback */
742 void (* TT_TimeMarkCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< FDCAN TT Time Mark callback */
743 void (* TT_StopWatchCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< FDCAN TT Stop Watch callback */
744 void (* TT_GlobalTimeCallback)(struct __FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< FDCAN TT Global Time callback */
745
746 void (* MspInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp Init callback */
747 void (* MspDeInitCallback)(struct __FDCAN_HandleTypeDef *hfdcan); /*!< FDCAN Msp DeInit callback */
748 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
749
750 } FDCAN_HandleTypeDef;
751
752 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
753 /**
754 * @brief HAL FDCAN common Callback ID enumeration definition
755 */
756 typedef enum
757 {
758 HAL_FDCAN_TX_FIFO_EMPTY_CB_ID = 0x00U, /*!< FDCAN Tx Fifo Empty callback ID */
759 HAL_FDCAN_RX_BUFFER_NEW_MSG_CB_ID = 0x01U, /*!< FDCAN Rx buffer new message callback ID */
760 HAL_FDCAN_HIGH_PRIO_MESSAGE_CB_ID = 0x02U, /*!< FDCAN High priority message callback ID */
761 HAL_FDCAN_TIMESTAMP_WRAPAROUND_CB_ID = 0x03U, /*!< FDCAN Timestamp wraparound callback ID */
762 HAL_FDCAN_TIMEOUT_OCCURRED_CB_ID = 0x04U, /*!< FDCAN Timeout occurred callback ID */
763 HAL_FDCAN_ERROR_CALLBACK_CB_ID = 0x05U, /*!< FDCAN Error callback ID */
764
765 HAL_FDCAN_MSPINIT_CB_ID = 0x06U, /*!< FDCAN MspInit callback ID */
766 HAL_FDCAN_MSPDEINIT_CB_ID = 0x07U, /*!< FDCAN MspDeInit callback ID */
767
768 } HAL_FDCAN_CallbackIDTypeDef;
769
770 /**
771 * @brief HAL FDCAN Callback pointer definition
772 */
773 typedef void (*pFDCAN_CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan); /*!< pointer to a common FDCAN callback function */
774 typedef void (*pFDCAN_ClockCalibrationCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs); /*!< pointer to Clock Calibration FDCAN callback function */
775 typedef void (*pFDCAN_TxEventFifoCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs); /*!< pointer to Tx event Fifo FDCAN callback function */
776 typedef void (*pFDCAN_RxFifo0CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs); /*!< pointer to Rx Fifo 0 FDCAN callback function */
777 typedef void (*pFDCAN_RxFifo1CallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs); /*!< pointer to Rx Fifo 1 FDCAN callback function */
778 typedef void (*pFDCAN_TxBufferCompleteCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer complete FDCAN callback function */
779 typedef void (*pFDCAN_TxBufferAbortCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes); /*!< pointer to Tx Buffer abort FDCAN callback function */
780 typedef void (*pFDCAN_ErrorStatusCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs); /*!< pointer to Error Status callback function */
781 typedef void (*pFDCAN_TT_ScheduleSyncCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs); /*!< pointer to TT Schedule Synchronization FDCAN callback function */
782 typedef void (*pFDCAN_TT_TimeMarkCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs); /*!< pointer to TT Time Mark FDCAN callback function */
783 typedef void (*pFDCAN_TT_StopWatchCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount); /*!< pointer to TT Stop Watch FDCAN callback function */
784 typedef void (*pFDCAN_TT_GlobalTimeCallbackTypeDef)(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs); /*!< pointer to TT Global Time FDCAN callback function */
785 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
786
787 /**
788 * @}
789 */
790
791 /* Exported constants --------------------------------------------------------*/
792 /** @defgroup FDCAN_Exported_Constants FDCAN Exported Constants
793 * @{
794 */
795
796 /** @defgroup HAL_FDCAN_Error_Code HAL FDCAN Error Code
797 * @{
798 */
799 #define HAL_FDCAN_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error */
800 #define HAL_FDCAN_ERROR_TIMEOUT ((uint32_t)0x00000001U) /*!< Timeout error */
801 #define HAL_FDCAN_ERROR_NOT_INITIALIZED ((uint32_t)0x00000002U) /*!< Peripheral not initialized */
802 #define HAL_FDCAN_ERROR_NOT_READY ((uint32_t)0x00000004U) /*!< Peripheral not ready */
803 #define HAL_FDCAN_ERROR_NOT_STARTED ((uint32_t)0x00000008U) /*!< Peripheral not started */
804 #define HAL_FDCAN_ERROR_NOT_SUPPORTED ((uint32_t)0x00000010U) /*!< Mode not supported */
805 #define HAL_FDCAN_ERROR_PARAM ((uint32_t)0x00000020U) /*!< Parameter error */
806 #define HAL_FDCAN_ERROR_PENDING ((uint32_t)0x00000040U) /*!< Pending operation */
807 #define HAL_FDCAN_ERROR_RAM_ACCESS ((uint32_t)0x00000080U) /*!< Message RAM Access Failure */
808 #define HAL_FDCAN_ERROR_FIFO_EMPTY ((uint32_t)0x00000100U) /*!< Put element in full FIFO */
809 #define HAL_FDCAN_ERROR_FIFO_FULL ((uint32_t)0x00000200U) /*!< Get element from empty FIFO */
810 #define HAL_FDCAN_ERROR_LOG_OVERFLOW FDCAN_IR_ELO /*!< Overflow of CAN Error Logging Counter */
811 #define HAL_FDCAN_ERROR_RAM_WDG FDCAN_IR_WDI /*!< Message RAM Watchdog event occurred */
812 #define HAL_FDCAN_ERROR_PROTOCOL_ARBT FDCAN_IR_PEA /*!< Protocol Error in Arbitration Phase (Nominal Bit Time is used) */
813 #define HAL_FDCAN_ERROR_PROTOCOL_DATA FDCAN_IR_PED /*!< Protocol Error in Data Phase (Data Bit Time is used) */
814 #define HAL_FDCAN_ERROR_RESERVED_AREA FDCAN_IR_ARA /*!< Access to Reserved Address */
815 #define HAL_FDCAN_ERROR_TT_GLOBAL_TIME FDCAN_TTIR_GTE /*!< Global Time Error : Synchronization deviation exceeded limit */
816 #define HAL_FDCAN_ERROR_TT_TX_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow : Less Tx trigger than expected in one matrix cycle */
817 #define HAL_FDCAN_ERROR_TT_TX_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow : More Tx trigger than expected in one matrix cycle */
818 #define HAL_FDCAN_ERROR_TT_SCHEDULE1 FDCAN_TTIR_SE1 /*!< Scheduling error 1 */
819 #define HAL_FDCAN_ERROR_TT_SCHEDULE2 FDCAN_TTIR_SE2 /*!< Scheduling error 2 */
820 #define HAL_FDCAN_ERROR_TT_NO_INIT_REF FDCAN_TTIR_IWT /*!< No system startup due to missing reference message */
821 #define HAL_FDCAN_ERROR_TT_NO_REF FDCAN_TTIR_WT /*!< Missing reference message */
822 #define HAL_FDCAN_ERROR_TT_APPL_WDG FDCAN_TTIR_AW /*!< Application watchdog not served in time */
823 #define HAL_FDCAN_ERROR_TT_CONFIG FDCAN_TTIR_CER /*!< Error found in trigger list */
824
825 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
826 #define HAL_FDCAN_ERROR_INVALID_CALLBACK ((uint32_t)0x00000100U) /*!< Invalid Callback error */
827 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
828 /**
829 * @}
830 */
831
832 /** @defgroup FDCAN_frame_format FDCAN Frame Format
833 * @{
834 */
835 #define FDCAN_FRAME_CLASSIC ((uint32_t)0x00000000U) /*!< Classic mode */
836 #define FDCAN_FRAME_FD_NO_BRS ((uint32_t)FDCAN_CCCR_FDOE) /*!< FD mode without BitRate Switching */
837 #define FDCAN_FRAME_FD_BRS ((uint32_t)(FDCAN_CCCR_FDOE | FDCAN_CCCR_BRSE)) /*!< FD mode with BitRate Switching */
838 /**
839 * @}
840 */
841
842 /** @defgroup FDCAN_operating_mode FDCAN Operating Mode
843 * @{
844 */
845 #define FDCAN_MODE_NORMAL ((uint32_t)0x00000000U) /*!< Normal mode */
846 #define FDCAN_MODE_RESTRICTED_OPERATION ((uint32_t)0x00000001U) /*!< Restricted Operation mode */
847 #define FDCAN_MODE_BUS_MONITORING ((uint32_t)0x00000002U) /*!< Bus Monitoring mode */
848 #define FDCAN_MODE_INTERNAL_LOOPBACK ((uint32_t)0x00000003U) /*!< Internal LoopBack mode */
849 #define FDCAN_MODE_EXTERNAL_LOOPBACK ((uint32_t)0x00000004U) /*!< External LoopBack mode */
850 /**
851 * @}
852 */
853
854 /** @defgroup FDCAN_clock_calibration FDCAN Clock Calibration
855 * @{
856 */
857 #define FDCAN_CLOCK_CALIBRATION_DISABLE ((uint32_t)0x00000000U) /*!< Disable Clock Calibration */
858 #define FDCAN_CLOCK_CALIBRATION_ENABLE ((uint32_t)0x00000001U) /*!< Enable Clock Calibration */
859 /**
860 * @}
861 */
862
863 /** @defgroup FDCAN_clock_divider FDCAN Clock Divider
864 * @{
865 */
866 #define FDCAN_CLOCK_DIV1 ((uint32_t)0x00000000U) /*!< Divide kernel clock by 1 */
867 #define FDCAN_CLOCK_DIV2 ((uint32_t)0x00010000U) /*!< Divide kernel clock by 2 */
868 #define FDCAN_CLOCK_DIV4 ((uint32_t)0x00020000U) /*!< Divide kernel clock by 4 */
869 #define FDCAN_CLOCK_DIV6 ((uint32_t)0x00030000U) /*!< Divide kernel clock by 6 */
870 #define FDCAN_CLOCK_DIV8 ((uint32_t)0x00040000U) /*!< Divide kernel clock by 8 */
871 #define FDCAN_CLOCK_DIV10 ((uint32_t)0x00050000U) /*!< Divide kernel clock by 10 */
872 #define FDCAN_CLOCK_DIV12 ((uint32_t)0x00060000U) /*!< Divide kernel clock by 12 */
873 #define FDCAN_CLOCK_DIV14 ((uint32_t)0x00070000U) /*!< Divide kernel clock by 14 */
874 #define FDCAN_CLOCK_DIV16 ((uint32_t)0x00080000U) /*!< Divide kernel clock by 16 */
875 #define FDCAN_CLOCK_DIV18 ((uint32_t)0x00090000U) /*!< Divide kernel clock by 18 */
876 #define FDCAN_CLOCK_DIV20 ((uint32_t)0x000A0000U) /*!< Divide kernel clock by 20 */
877 #define FDCAN_CLOCK_DIV22 ((uint32_t)0x000B0000U) /*!< Divide kernel clock by 22 */
878 #define FDCAN_CLOCK_DIV24 ((uint32_t)0x000C0000U) /*!< Divide kernel clock by 24 */
879 #define FDCAN_CLOCK_DIV26 ((uint32_t)0x000D0000U) /*!< Divide kernel clock by 26 */
880 #define FDCAN_CLOCK_DIV28 ((uint32_t)0x000E0000U) /*!< Divide kernel clock by 28 */
881 #define FDCAN_CLOCK_DIV30 ((uint32_t)0x000F0000U) /*!< Divide kernel clock by 30 */
882 /**
883 * @}
884 */
885
886 /** @defgroup FDCAN_calibration_field_length FDCAN Calibration Field Length
887 * @{
888 */
889 #define FDCAN_CALIB_FIELD_LENGTH_32 ((uint32_t)0x00000000U) /*!< Calibration field length is 32 bits */
890 #define FDCAN_CALIB_FIELD_LENGTH_64 ((uint32_t)FDCANCCU_CCFG_CFL) /*!< Calibration field length is 64 bits */
891 /**
892 * @}
893 */
894
895 /** @defgroup FDCAN_calibration_state FDCAN Calibration State
896 * @{
897 */
898 #define FDCAN_CLOCK_NOT_CALIBRATED ((uint32_t)0x00000000U) /*!< Clock not calibrated */
899 #define FDCAN_CLOCK_BASIC_CALIBRATED ((uint32_t)0x40000000U) /*!< Clock basic calibrated */
900 #define FDCAN_CLOCK_PRECISION_CALIBRATED ((uint32_t)0x80000000U) /*!< Clock precision calibrated */
901 /**
902 * @}
903 */
904
905 /** @defgroup FDCAN_calibration_counter FDCAN Calibration Counter
906 * @{
907 */
908 #define FDCAN_CALIB_TIME_QUANTA_COUNTER ((uint32_t)0x00000000U) /*!< Time Quanta Counter */
909 #define FDCAN_CALIB_CLOCK_PERIOD_COUNTER ((uint32_t)0x00000001U) /*!< Oscillator Clock Period Counter */
910 #define FDCAN_CALIB_WATCHDOG_COUNTER ((uint32_t)0x00000002U) /*!< Calibration Watchdog Counter */
911 /**
912 * @}
913 */
914
915 /** @defgroup FDCAN_data_field_size FDCAN Data Field Size
916 * @{
917 */
918 #define FDCAN_DATA_BYTES_8 ((uint32_t)0x00000004U) /*!< 8 bytes data field */
919 #define FDCAN_DATA_BYTES_12 ((uint32_t)0x00000005U) /*!< 12 bytes data field */
920 #define FDCAN_DATA_BYTES_16 ((uint32_t)0x00000006U) /*!< 16 bytes data field */
921 #define FDCAN_DATA_BYTES_20 ((uint32_t)0x00000007U) /*!< 20 bytes data field */
922 #define FDCAN_DATA_BYTES_24 ((uint32_t)0x00000008U) /*!< 24 bytes data field */
923 #define FDCAN_DATA_BYTES_32 ((uint32_t)0x0000000AU) /*!< 32 bytes data field */
924 #define FDCAN_DATA_BYTES_48 ((uint32_t)0x0000000EU) /*!< 48 bytes data field */
925 #define FDCAN_DATA_BYTES_64 ((uint32_t)0x00000012U) /*!< 64 bytes data field */
926 /**
927 * @}
928 */
929
930 /** @defgroup FDCAN_txFifoQueue_Mode FDCAN Tx FIFO/Queue Mode
931 * @{
932 */
933 #define FDCAN_TX_FIFO_OPERATION ((uint32_t)0x00000000U) /*!< FIFO mode */
934 #define FDCAN_TX_QUEUE_OPERATION ((uint32_t)FDCAN_TXBC_TFQM) /*!< Queue mode */
935 /**
936 * @}
937 */
938
939 /** @defgroup FDCAN_id_type FDCAN ID Type
940 * @{
941 */
942 #define FDCAN_STANDARD_ID ((uint32_t)0x00000000U) /*!< Standard ID element */
943 #define FDCAN_EXTENDED_ID ((uint32_t)0x40000000U) /*!< Extended ID element */
944 /**
945 * @}
946 */
947
948 /** @defgroup FDCAN_frame_type FDCAN Frame Type
949 * @{
950 */
951 #define FDCAN_DATA_FRAME ((uint32_t)0x00000000U) /*!< Data frame */
952 #define FDCAN_REMOTE_FRAME ((uint32_t)0x20000000U) /*!< Remote frame */
953 /**
954 * @}
955 */
956
957 /** @defgroup FDCAN_data_length_code FDCAN Data Length Code
958 * @{
959 */
960 #define FDCAN_DLC_BYTES_0 ((uint32_t)0x00000000U) /*!< 0 bytes data field */
961 #define FDCAN_DLC_BYTES_1 ((uint32_t)0x00010000U) /*!< 1 bytes data field */
962 #define FDCAN_DLC_BYTES_2 ((uint32_t)0x00020000U) /*!< 2 bytes data field */
963 #define FDCAN_DLC_BYTES_3 ((uint32_t)0x00030000U) /*!< 3 bytes data field */
964 #define FDCAN_DLC_BYTES_4 ((uint32_t)0x00040000U) /*!< 4 bytes data field */
965 #define FDCAN_DLC_BYTES_5 ((uint32_t)0x00050000U) /*!< 5 bytes data field */
966 #define FDCAN_DLC_BYTES_6 ((uint32_t)0x00060000U) /*!< 6 bytes data field */
967 #define FDCAN_DLC_BYTES_7 ((uint32_t)0x00070000U) /*!< 7 bytes data field */
968 #define FDCAN_DLC_BYTES_8 ((uint32_t)0x00080000U) /*!< 8 bytes data field */
969 #define FDCAN_DLC_BYTES_12 ((uint32_t)0x00090000U) /*!< 12 bytes data field */
970 #define FDCAN_DLC_BYTES_16 ((uint32_t)0x000A0000U) /*!< 16 bytes data field */
971 #define FDCAN_DLC_BYTES_20 ((uint32_t)0x000B0000U) /*!< 20 bytes data field */
972 #define FDCAN_DLC_BYTES_24 ((uint32_t)0x000C0000U) /*!< 24 bytes data field */
973 #define FDCAN_DLC_BYTES_32 ((uint32_t)0x000D0000U) /*!< 32 bytes data field */
974 #define FDCAN_DLC_BYTES_48 ((uint32_t)0x000E0000U) /*!< 48 bytes data field */
975 #define FDCAN_DLC_BYTES_64 ((uint32_t)0x000F0000U) /*!< 64 bytes data field */
976 /**
977 * @}
978 */
979
980 /** @defgroup FDCAN_error_state_indicator FDCAN Error State Indicator
981 * @{
982 */
983 #define FDCAN_ESI_ACTIVE ((uint32_t)0x00000000U) /*!< Transmitting node is error active */
984 #define FDCAN_ESI_PASSIVE ((uint32_t)0x80000000U) /*!< Transmitting node is error passive */
985 /**
986 * @}
987 */
988
989 /** @defgroup FDCAN_bit_rate_switching FDCAN Bit Rate Switching
990 * @{
991 */
992 #define FDCAN_BRS_OFF ((uint32_t)0x00000000U) /*!< FDCAN frames transmitted/received without bit rate switching */
993 #define FDCAN_BRS_ON ((uint32_t)0x00100000U) /*!< FDCAN frames transmitted/received with bit rate switching */
994 /**
995 * @}
996 */
997
998 /** @defgroup FDCAN_format FDCAN format
999 * @{
1000 */
1001 #define FDCAN_CLASSIC_CAN ((uint32_t)0x00000000U) /*!< Frame transmitted/received in Classic CAN format */
1002 #define FDCAN_FD_CAN ((uint32_t)0x00200000U) /*!< Frame transmitted/received in FDCAN format */
1003 /**
1004 * @}
1005 */
1006
1007 /** @defgroup FDCAN_EFC FDCAN Event FIFO control
1008 * @{
1009 */
1010 #define FDCAN_NO_TX_EVENTS ((uint32_t)0x00000000U) /*!< Do not store Tx events */
1011 #define FDCAN_STORE_TX_EVENTS ((uint32_t)0x00800000U) /*!< Store Tx events */
1012 /**
1013 * @}
1014 */
1015
1016 /** @defgroup FDCAN_filter_type FDCAN Filter Type
1017 * @{
1018 */
1019 #define FDCAN_FILTER_RANGE ((uint32_t)0x00000000U) /*!< Range filter from FilterID1 to FilterID2 */
1020 #define FDCAN_FILTER_DUAL ((uint32_t)0x00000001U) /*!< Dual ID filter for FilterID1 or FilterID2 */
1021 #define FDCAN_FILTER_MASK ((uint32_t)0x00000002U) /*!< Classic filter: FilterID1 = filter, FilterID2 = mask */
1022 #define FDCAN_FILTER_RANGE_NO_EIDM ((uint32_t)0x00000003U) /*!< Range filter from FilterID1 to FilterID2, EIDM mask not applied */
1023 /**
1024 * @}
1025 */
1026
1027 /** @defgroup FDCAN_filter_config FDCAN Filter Configuration
1028 * @{
1029 */
1030 #define FDCAN_FILTER_DISABLE ((uint32_t)0x00000000U) /*!< Disable filter element */
1031 #define FDCAN_FILTER_TO_RXFIFO0 ((uint32_t)0x00000001U) /*!< Store in Rx FIFO 0 if filter matches */
1032 #define FDCAN_FILTER_TO_RXFIFO1 ((uint32_t)0x00000002U) /*!< Store in Rx FIFO 1 if filter matches */
1033 #define FDCAN_FILTER_REJECT ((uint32_t)0x00000003U) /*!< Reject ID if filter matches */
1034 #define FDCAN_FILTER_HP ((uint32_t)0x00000004U) /*!< Set high priority if filter matches */
1035 #define FDCAN_FILTER_TO_RXFIFO0_HP ((uint32_t)0x00000005U) /*!< Set high priority and store in FIFO 0 if filter matches */
1036 #define FDCAN_FILTER_TO_RXFIFO1_HP ((uint32_t)0x00000006U) /*!< Set high priority and store in FIFO 1 if filter matches */
1037 #define FDCAN_FILTER_TO_RXBUFFER ((uint32_t)0x00000007U) /*!< Store into Rx Buffer, configuration of FilterType ignored */
1038 /**
1039 * @}
1040 */
1041
1042 /** @defgroup FDCAN_Tx_location FDCAN Tx Location
1043 * @{
1044 */
1045 #define FDCAN_TX_BUFFER0 ((uint32_t)0x00000001U) /*!< Add message to Tx Buffer 0 */
1046 #define FDCAN_TX_BUFFER1 ((uint32_t)0x00000002U) /*!< Add message to Tx Buffer 1 */
1047 #define FDCAN_TX_BUFFER2 ((uint32_t)0x00000004U) /*!< Add message to Tx Buffer 2 */
1048 #define FDCAN_TX_BUFFER3 ((uint32_t)0x00000008U) /*!< Add message to Tx Buffer 3 */
1049 #define FDCAN_TX_BUFFER4 ((uint32_t)0x00000010U) /*!< Add message to Tx Buffer 4 */
1050 #define FDCAN_TX_BUFFER5 ((uint32_t)0x00000020U) /*!< Add message to Tx Buffer 5 */
1051 #define FDCAN_TX_BUFFER6 ((uint32_t)0x00000040U) /*!< Add message to Tx Buffer 6 */
1052 #define FDCAN_TX_BUFFER7 ((uint32_t)0x00000080U) /*!< Add message to Tx Buffer 7 */
1053 #define FDCAN_TX_BUFFER8 ((uint32_t)0x00000100U) /*!< Add message to Tx Buffer 8 */
1054 #define FDCAN_TX_BUFFER9 ((uint32_t)0x00000200U) /*!< Add message to Tx Buffer 9 */
1055 #define FDCAN_TX_BUFFER10 ((uint32_t)0x00000400U) /*!< Add message to Tx Buffer 10 */
1056 #define FDCAN_TX_BUFFER11 ((uint32_t)0x00000800U) /*!< Add message to Tx Buffer 11 */
1057 #define FDCAN_TX_BUFFER12 ((uint32_t)0x00001000U) /*!< Add message to Tx Buffer 12 */
1058 #define FDCAN_TX_BUFFER13 ((uint32_t)0x00002000U) /*!< Add message to Tx Buffer 13 */
1059 #define FDCAN_TX_BUFFER14 ((uint32_t)0x00004000U) /*!< Add message to Tx Buffer 14 */
1060 #define FDCAN_TX_BUFFER15 ((uint32_t)0x00008000U) /*!< Add message to Tx Buffer 15 */
1061 #define FDCAN_TX_BUFFER16 ((uint32_t)0x00010000U) /*!< Add message to Tx Buffer 16 */
1062 #define FDCAN_TX_BUFFER17 ((uint32_t)0x00020000U) /*!< Add message to Tx Buffer 17 */
1063 #define FDCAN_TX_BUFFER18 ((uint32_t)0x00040000U) /*!< Add message to Tx Buffer 18 */
1064 #define FDCAN_TX_BUFFER19 ((uint32_t)0x00080000U) /*!< Add message to Tx Buffer 19 */
1065 #define FDCAN_TX_BUFFER20 ((uint32_t)0x00100000U) /*!< Add message to Tx Buffer 20 */
1066 #define FDCAN_TX_BUFFER21 ((uint32_t)0x00200000U) /*!< Add message to Tx Buffer 21 */
1067 #define FDCAN_TX_BUFFER22 ((uint32_t)0x00400000U) /*!< Add message to Tx Buffer 22 */
1068 #define FDCAN_TX_BUFFER23 ((uint32_t)0x00800000U) /*!< Add message to Tx Buffer 23 */
1069 #define FDCAN_TX_BUFFER24 ((uint32_t)0x01000000U) /*!< Add message to Tx Buffer 24 */
1070 #define FDCAN_TX_BUFFER25 ((uint32_t)0x02000000U) /*!< Add message to Tx Buffer 25 */
1071 #define FDCAN_TX_BUFFER26 ((uint32_t)0x04000000U) /*!< Add message to Tx Buffer 26 */
1072 #define FDCAN_TX_BUFFER27 ((uint32_t)0x08000000U) /*!< Add message to Tx Buffer 27 */
1073 #define FDCAN_TX_BUFFER28 ((uint32_t)0x10000000U) /*!< Add message to Tx Buffer 28 */
1074 #define FDCAN_TX_BUFFER29 ((uint32_t)0x20000000U) /*!< Add message to Tx Buffer 29 */
1075 #define FDCAN_TX_BUFFER30 ((uint32_t)0x40000000U) /*!< Add message to Tx Buffer 30 */
1076 #define FDCAN_TX_BUFFER31 ((uint32_t)0x80000000U) /*!< Add message to Tx Buffer 31 */
1077 /**
1078 * @}
1079 */
1080
1081 /** @defgroup FDCAN_Rx_location FDCAN Rx Location
1082 * @{
1083 */
1084 #define FDCAN_RX_FIFO0 ((uint32_t)0x00000040U) /*!< Get received message from Rx FIFO 0 */
1085 #define FDCAN_RX_FIFO1 ((uint32_t)0x00000041U) /*!< Get received message from Rx FIFO 1 */
1086 #define FDCAN_RX_BUFFER0 ((uint32_t)0x00000000U) /*!< Get received message from Rx Buffer 0 */
1087 #define FDCAN_RX_BUFFER1 ((uint32_t)0x00000001U) /*!< Get received message from Rx Buffer 1 */
1088 #define FDCAN_RX_BUFFER2 ((uint32_t)0x00000002U) /*!< Get received message from Rx Buffer 2 */
1089 #define FDCAN_RX_BUFFER3 ((uint32_t)0x00000003U) /*!< Get received message from Rx Buffer 3 */
1090 #define FDCAN_RX_BUFFER4 ((uint32_t)0x00000004U) /*!< Get received message from Rx Buffer 4 */
1091 #define FDCAN_RX_BUFFER5 ((uint32_t)0x00000005U) /*!< Get received message from Rx Buffer 5 */
1092 #define FDCAN_RX_BUFFER6 ((uint32_t)0x00000006U) /*!< Get received message from Rx Buffer 6 */
1093 #define FDCAN_RX_BUFFER7 ((uint32_t)0x00000007U) /*!< Get received message from Rx Buffer 7 */
1094 #define FDCAN_RX_BUFFER8 ((uint32_t)0x00000008U) /*!< Get received message from Rx Buffer 8 */
1095 #define FDCAN_RX_BUFFER9 ((uint32_t)0x00000009U) /*!< Get received message from Rx Buffer 9 */
1096 #define FDCAN_RX_BUFFER10 ((uint32_t)0x0000000AU) /*!< Get received message from Rx Buffer 10 */
1097 #define FDCAN_RX_BUFFER11 ((uint32_t)0x0000000BU) /*!< Get received message from Rx Buffer 11 */
1098 #define FDCAN_RX_BUFFER12 ((uint32_t)0x0000000CU) /*!< Get received message from Rx Buffer 12 */
1099 #define FDCAN_RX_BUFFER13 ((uint32_t)0x0000000DU) /*!< Get received message from Rx Buffer 13 */
1100 #define FDCAN_RX_BUFFER14 ((uint32_t)0x0000000EU) /*!< Get received message from Rx Buffer 14 */
1101 #define FDCAN_RX_BUFFER15 ((uint32_t)0x0000000FU) /*!< Get received message from Rx Buffer 15 */
1102 #define FDCAN_RX_BUFFER16 ((uint32_t)0x00000010U) /*!< Get received message from Rx Buffer 16 */
1103 #define FDCAN_RX_BUFFER17 ((uint32_t)0x00000011U) /*!< Get received message from Rx Buffer 17 */
1104 #define FDCAN_RX_BUFFER18 ((uint32_t)0x00000012U) /*!< Get received message from Rx Buffer 18 */
1105 #define FDCAN_RX_BUFFER19 ((uint32_t)0x00000013U) /*!< Get received message from Rx Buffer 19 */
1106 #define FDCAN_RX_BUFFER20 ((uint32_t)0x00000014U) /*!< Get received message from Rx Buffer 20 */
1107 #define FDCAN_RX_BUFFER21 ((uint32_t)0x00000015U) /*!< Get received message from Rx Buffer 21 */
1108 #define FDCAN_RX_BUFFER22 ((uint32_t)0x00000016U) /*!< Get received message from Rx Buffer 22 */
1109 #define FDCAN_RX_BUFFER23 ((uint32_t)0x00000017U) /*!< Get received message from Rx Buffer 23 */
1110 #define FDCAN_RX_BUFFER24 ((uint32_t)0x00000018U) /*!< Get received message from Rx Buffer 24 */
1111 #define FDCAN_RX_BUFFER25 ((uint32_t)0x00000019U) /*!< Get received message from Rx Buffer 25 */
1112 #define FDCAN_RX_BUFFER26 ((uint32_t)0x0000001AU) /*!< Get received message from Rx Buffer 26 */
1113 #define FDCAN_RX_BUFFER27 ((uint32_t)0x0000001BU) /*!< Get received message from Rx Buffer 27 */
1114 #define FDCAN_RX_BUFFER28 ((uint32_t)0x0000001CU) /*!< Get received message from Rx Buffer 28 */
1115 #define FDCAN_RX_BUFFER29 ((uint32_t)0x0000001DU) /*!< Get received message from Rx Buffer 29 */
1116 #define FDCAN_RX_BUFFER30 ((uint32_t)0x0000001EU) /*!< Get received message from Rx Buffer 30 */
1117 #define FDCAN_RX_BUFFER31 ((uint32_t)0x0000001FU) /*!< Get received message from Rx Buffer 31 */
1118 #define FDCAN_RX_BUFFER32 ((uint32_t)0x00000020U) /*!< Get received message from Rx Buffer 32 */
1119 #define FDCAN_RX_BUFFER33 ((uint32_t)0x00000021U) /*!< Get received message from Rx Buffer 33 */
1120 #define FDCAN_RX_BUFFER34 ((uint32_t)0x00000022U) /*!< Get received message from Rx Buffer 34 */
1121 #define FDCAN_RX_BUFFER35 ((uint32_t)0x00000023U) /*!< Get received message from Rx Buffer 35 */
1122 #define FDCAN_RX_BUFFER36 ((uint32_t)0x00000024U) /*!< Get received message from Rx Buffer 36 */
1123 #define FDCAN_RX_BUFFER37 ((uint32_t)0x00000025U) /*!< Get received message from Rx Buffer 37 */
1124 #define FDCAN_RX_BUFFER38 ((uint32_t)0x00000026U) /*!< Get received message from Rx Buffer 38 */
1125 #define FDCAN_RX_BUFFER39 ((uint32_t)0x00000027U) /*!< Get received message from Rx Buffer 39 */
1126 #define FDCAN_RX_BUFFER40 ((uint32_t)0x00000028U) /*!< Get received message from Rx Buffer 40 */
1127 #define FDCAN_RX_BUFFER41 ((uint32_t)0x00000029U) /*!< Get received message from Rx Buffer 41 */
1128 #define FDCAN_RX_BUFFER42 ((uint32_t)0x0000002AU) /*!< Get received message from Rx Buffer 42 */
1129 #define FDCAN_RX_BUFFER43 ((uint32_t)0x0000002BU) /*!< Get received message from Rx Buffer 43 */
1130 #define FDCAN_RX_BUFFER44 ((uint32_t)0x0000002CU) /*!< Get received message from Rx Buffer 44 */
1131 #define FDCAN_RX_BUFFER45 ((uint32_t)0x0000002DU) /*!< Get received message from Rx Buffer 45 */
1132 #define FDCAN_RX_BUFFER46 ((uint32_t)0x0000002EU) /*!< Get received message from Rx Buffer 46 */
1133 #define FDCAN_RX_BUFFER47 ((uint32_t)0x0000002FU) /*!< Get received message from Rx Buffer 47 */
1134 #define FDCAN_RX_BUFFER48 ((uint32_t)0x00000030U) /*!< Get received message from Rx Buffer 48 */
1135 #define FDCAN_RX_BUFFER49 ((uint32_t)0x00000031U) /*!< Get received message from Rx Buffer 49 */
1136 #define FDCAN_RX_BUFFER50 ((uint32_t)0x00000032U) /*!< Get received message from Rx Buffer 50 */
1137 #define FDCAN_RX_BUFFER51 ((uint32_t)0x00000033U) /*!< Get received message from Rx Buffer 51 */
1138 #define FDCAN_RX_BUFFER52 ((uint32_t)0x00000034U) /*!< Get received message from Rx Buffer 52 */
1139 #define FDCAN_RX_BUFFER53 ((uint32_t)0x00000035U) /*!< Get received message from Rx Buffer 53 */
1140 #define FDCAN_RX_BUFFER54 ((uint32_t)0x00000036U) /*!< Get received message from Rx Buffer 54 */
1141 #define FDCAN_RX_BUFFER55 ((uint32_t)0x00000037U) /*!< Get received message from Rx Buffer 55 */
1142 #define FDCAN_RX_BUFFER56 ((uint32_t)0x00000038U) /*!< Get received message from Rx Buffer 56 */
1143 #define FDCAN_RX_BUFFER57 ((uint32_t)0x00000039U) /*!< Get received message from Rx Buffer 57 */
1144 #define FDCAN_RX_BUFFER58 ((uint32_t)0x0000003AU) /*!< Get received message from Rx Buffer 58 */
1145 #define FDCAN_RX_BUFFER59 ((uint32_t)0x0000003BU) /*!< Get received message from Rx Buffer 59 */
1146 #define FDCAN_RX_BUFFER60 ((uint32_t)0x0000003CU) /*!< Get received message from Rx Buffer 60 */
1147 #define FDCAN_RX_BUFFER61 ((uint32_t)0x0000003DU) /*!< Get received message from Rx Buffer 61 */
1148 #define FDCAN_RX_BUFFER62 ((uint32_t)0x0000003EU) /*!< Get received message from Rx Buffer 62 */
1149 #define FDCAN_RX_BUFFER63 ((uint32_t)0x0000003FU) /*!< Get received message from Rx Buffer 63 */
1150 /**
1151 * @}
1152 */
1153
1154 /** @defgroup FDCAN_event_type FDCAN Event Type
1155 * @{
1156 */
1157 #define FDCAN_TX_EVENT ((uint32_t)0x00400000U) /*!< Tx event */
1158 #define FDCAN_TX_IN_SPITE_OF_ABORT ((uint32_t)0x00800000U) /*!< Transmission in spite of cancellation */
1159 /**
1160 * @}
1161 */
1162
1163 /** @defgroup FDCAN_hp_msg_storage FDCAN High Priority Message Storage
1164 * @{
1165 */
1166 #define FDCAN_HP_STORAGE_NO_FIFO ((uint32_t)0x00000000U) /*!< No FIFO selected */
1167 #define FDCAN_HP_STORAGE_MSG_LOST ((uint32_t)0x00000040U) /*!< FIFO message lost */
1168 #define FDCAN_HP_STORAGE_RXFIFO0 ((uint32_t)0x00000080U) /*!< Message stored in FIFO 0 */
1169 #define FDCAN_HP_STORAGE_RXFIFO1 ((uint32_t)0x000000C0U) /*!< Message stored in FIFO 1 */
1170 /**
1171 * @}
1172 */
1173
1174 /** @defgroup FDCAN_protocol_error_code FDCAN protocol error code
1175 * @{
1176 */
1177 #define FDCAN_PROTOCOL_ERROR_NONE ((uint32_t)0x00000000U) /*!< No error occurred */
1178 #define FDCAN_PROTOCOL_ERROR_STUFF ((uint32_t)0x00000001U) /*!< Stuff error */
1179 #define FDCAN_PROTOCOL_ERROR_FORM ((uint32_t)0x00000002U) /*!< Form error */
1180 #define FDCAN_PROTOCOL_ERROR_ACK ((uint32_t)0x00000003U) /*!< Acknowledge error */
1181 #define FDCAN_PROTOCOL_ERROR_BIT1 ((uint32_t)0x00000004U) /*!< Bit 1 (recessive) error */
1182 #define FDCAN_PROTOCOL_ERROR_BIT0 ((uint32_t)0x00000005U) /*!< Bit 0 (dominant) error */
1183 #define FDCAN_PROTOCOL_ERROR_CRC ((uint32_t)0x00000006U) /*!< CRC check sum error */
1184 #define FDCAN_PROTOCOL_ERROR_NO_CHANGE ((uint32_t)0x00000007U) /*!< No change since last read */
1185 /**
1186 * @}
1187 */
1188
1189 /** @defgroup FDCAN_communication_state FDCAN communication state
1190 * @{
1191 */
1192 #define FDCAN_COM_STATE_SYNC ((uint32_t)0x00000000U) /*!< Node is synchronizing on CAN communication */
1193 #define FDCAN_COM_STATE_IDLE ((uint32_t)0x00000008U) /*!< Node is neither receiver nor transmitter */
1194 #define FDCAN_COM_STATE_RX ((uint32_t)0x00000010U) /*!< Node is operating as receiver */
1195 #define FDCAN_COM_STATE_TX ((uint32_t)0x00000018U) /*!< Node is operating as transmitter */
1196 /**
1197 * @}
1198 */
1199
1200 /** @defgroup FDCAN_FIFO_watermark FDCAN FIFO watermark
1201 * @{
1202 */
1203 #define FDCAN_CFG_TX_EVENT_FIFO ((uint32_t)0x00000000U) /*!< Tx event FIFO */
1204 #define FDCAN_CFG_RX_FIFO0 ((uint32_t)0x00000001U) /*!< Rx FIFO0 */
1205 #define FDCAN_CFG_RX_FIFO1 ((uint32_t)0x00000002U) /*!< Rx FIFO1 */
1206 /**
1207 * @}
1208 */
1209
1210 /** @defgroup FDCAN_Rx_FIFO_operation_mode FDCAN FIFO operation mode
1211 * @{
1212 */
1213 #define FDCAN_RX_FIFO_BLOCKING ((uint32_t)0x00000000U) /*!< Rx FIFO blocking mode */
1214 #define FDCAN_RX_FIFO_OVERWRITE ((uint32_t)0x80000000U) /*!< Rx FIFO overwrite mode */
1215 /**
1216 * @}
1217 */
1218
1219 /** @defgroup FDCAN_Non_Matching_Frames FDCAN non-matching frames
1220 * @{
1221 */
1222 #define FDCAN_ACCEPT_IN_RX_FIFO0 ((uint32_t)0x00000000U) /*!< Accept in Rx FIFO 0 */
1223 #define FDCAN_ACCEPT_IN_RX_FIFO1 ((uint32_t)0x00000001U) /*!< Accept in Rx FIFO 1 */
1224 #define FDCAN_REJECT ((uint32_t)0x00000002U) /*!< Reject */
1225 /**
1226 * @}
1227 */
1228
1229 /** @defgroup FDCAN_Reject_Remote_Frames FDCAN reject remote frames
1230 * @{
1231 */
1232 #define FDCAN_FILTER_REMOTE ((uint32_t)0x00000000U) /*!< Filter remote frames */
1233 #define FDCAN_REJECT_REMOTE ((uint32_t)0x00000001U) /*!< Reject all remote frames */
1234 /**
1235 * @}
1236 */
1237
1238 /** @defgroup FDCAN_Interrupt_Line FDCAN interrupt line
1239 * @{
1240 */
1241 #define FDCAN_INTERRUPT_LINE0 ((uint32_t)0x00000001U) /*!< Interrupt Line 0 */
1242 #define FDCAN_INTERRUPT_LINE1 ((uint32_t)0x00000002U) /*!< Interrupt Line 1 */
1243 /**
1244 * @}
1245 */
1246
1247 /** @defgroup FDCAN_Timestamp FDCAN timestamp
1248 * @{
1249 */
1250 #define FDCAN_TIMESTAMP_INTERNAL ((uint32_t)0x00000001U) /*!< Timestamp counter value incremented according to TCP */
1251 #define FDCAN_TIMESTAMP_EXTERNAL ((uint32_t)0x00000002U) /*!< External timestamp counter value used */
1252 /**
1253 * @}
1254 */
1255
1256 /** @defgroup FDCAN_Timestamp_Prescaler FDCAN timestamp prescaler
1257 * @{
1258 */
1259 #define FDCAN_TIMESTAMP_PRESC_1 ((uint32_t)0x00000000U) /*!< Timestamp counter time unit in equal to CAN bit time */
1260 #define FDCAN_TIMESTAMP_PRESC_2 ((uint32_t)0x00010000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 2 */
1261 #define FDCAN_TIMESTAMP_PRESC_3 ((uint32_t)0x00020000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 3 */
1262 #define FDCAN_TIMESTAMP_PRESC_4 ((uint32_t)0x00030000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 4 */
1263 #define FDCAN_TIMESTAMP_PRESC_5 ((uint32_t)0x00040000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 5 */
1264 #define FDCAN_TIMESTAMP_PRESC_6 ((uint32_t)0x00050000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 6 */
1265 #define FDCAN_TIMESTAMP_PRESC_7 ((uint32_t)0x00060000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 7 */
1266 #define FDCAN_TIMESTAMP_PRESC_8 ((uint32_t)0x00070000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 8 */
1267 #define FDCAN_TIMESTAMP_PRESC_9 ((uint32_t)0x00080000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 9 */
1268 #define FDCAN_TIMESTAMP_PRESC_10 ((uint32_t)0x00090000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 10 */
1269 #define FDCAN_TIMESTAMP_PRESC_11 ((uint32_t)0x000A0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 11 */
1270 #define FDCAN_TIMESTAMP_PRESC_12 ((uint32_t)0x000B0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 12 */
1271 #define FDCAN_TIMESTAMP_PRESC_13 ((uint32_t)0x000C0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 13 */
1272 #define FDCAN_TIMESTAMP_PRESC_14 ((uint32_t)0x000D0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 14 */
1273 #define FDCAN_TIMESTAMP_PRESC_15 ((uint32_t)0x000E0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 15 */
1274 #define FDCAN_TIMESTAMP_PRESC_16 ((uint32_t)0x000F0000U) /*!< Timestamp counter time unit in equal to CAN bit time multipled by 16 */
1275 /**
1276 * @}
1277 */
1278
1279 /** @defgroup FDCAN_Timeout_Operation FDCAN timeout operation
1280 * @{
1281 */
1282 #define FDCAN_TIMEOUT_CONTINUOUS ((uint32_t)0x00000000U) /*!< Timeout continuous operation */
1283 #define FDCAN_TIMEOUT_TX_EVENT_FIFO ((uint32_t)0x00000002U) /*!< Timeout controlled by Tx Event FIFO */
1284 #define FDCAN_TIMEOUT_RX_FIFO0 ((uint32_t)0x00000004U) /*!< Timeout controlled by Rx FIFO 0 */
1285 #define FDCAN_TIMEOUT_RX_FIFO1 ((uint32_t)0x00000006U) /*!< Timeout controlled by Rx FIFO 1 */
1286 /**
1287 * @}
1288 */
1289
1290 /** @defgroup FDCAN_TT_Reference_Message_Payload FDCAN TT reference message payload
1291 * @{
1292 */
1293 #define FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ((uint32_t)0x00000000U) /*!< Reference message has no additional payload */
1294 #define FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD ((uint32_t)FDCAN_TTRMC_RMPS) /*!< Additional payload is taken from Tx Buffer 0 */
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup FDCAN_TT_Repeat_Factor FDCAN TT repeat factor
1300 * @{
1301 */
1302 #define FDCAN_TT_REPEAT_EVERY_CYCLE ((uint32_t)0x00000000U) /*!< Trigger valid for all cycles */
1303 #define FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ((uint32_t)0x00000002U) /*!< Trigger valid every 2dn cycle */
1304 #define FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ((uint32_t)0x00000004U) /*!< Trigger valid every 4th cycle */
1305 #define FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ((uint32_t)0x00000008U) /*!< Trigger valid every 8th cycle */
1306 #define FDCAN_TT_REPEAT_EVERY_16TH_CYCLE ((uint32_t)0x00000010U) /*!< Trigger valid every 16th cycle */
1307 #define FDCAN_TT_REPEAT_EVERY_32ND_CYCLE ((uint32_t)0x00000020U) /*!< Trigger valid every 32nd cycle */
1308 #define FDCAN_TT_REPEAT_EVERY_64TH_CYCLE ((uint32_t)0x00000040U) /*!< Trigger valid every 64th cycle */
1309 /**
1310 * @}
1311 */
1312
1313 /** @defgroup FDCAN_TT_Trigger_Type FDCAN TT trigger type
1314 * @{
1315 */
1316 #define FDCAN_TT_TX_REF_TRIGGER ((uint32_t)0x00000000U) /*!< Transmit reference message in strictly time-triggered operation */
1317 #define FDCAN_TT_TX_REF_TRIGGER_GAP ((uint32_t)0x00000001U) /*!< Transmit reference message in external event-synchronized time-triggered operation */
1318 #define FDCAN_TT_TX_TRIGGER_SINGLE ((uint32_t)0x00000002U) /*!< Start a single transmission in an exclusive time window */
1319 #define FDCAN_TT_TX_TRIGGER_CONTINUOUS ((uint32_t)0x00000003U) /*!< Start a continuous transmission in an exclusive time window */
1320 #define FDCAN_TT_TX_TRIGGER_ARBITRATION ((uint32_t)0x00000004U) /*!< Start a transmission in an arbitration time window */
1321 #define FDCAN_TT_TX_TRIGGER_MERGED ((uint32_t)0x00000005U) /*!< Start a merged arbitration window */
1322 #define FDCAN_TT_WATCH_TRIGGER ((uint32_t)0x00000006U) /*!< Check for missing reference messages in strictly time-triggered operation */
1323 #define FDCAN_TT_WATCH_TRIGGER_GAP ((uint32_t)0x00000007U) /*!< Check for missing reference messages in external event-synchronized time-triggered operation */
1324 #define FDCAN_TT_RX_TRIGGER ((uint32_t)0x00000008U) /*!< Check for the reception of periodic messages in exclusive time windows */
1325 #define FDCAN_TT_TIME_BASE_TRIGGER ((uint32_t)0x00000009U) /*!< Generate internal/external events depending on TmEventInt/TmEventExt configuration */
1326 #define FDCAN_TT_END_OF_LIST ((uint32_t)0x0000000AU) /*!< Illegal trigger, to be assigned to the unused triggers after a FDCAN_TT_WATCH_TRIGGER or FDCAN_TT_WATCH_TRIGGER_GAP */
1327 /**
1328 * @}
1329 */
1330
1331 /** @defgroup FDCAN_TT_Time_Mark_Event_Internal FDCAN TT time mark event internal
1332 * @{
1333 */
1334 #define FDCAN_TT_TM_NO_INTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
1335 #define FDCAN_TT_TM_GEN_INTERNAL_EVENT ((uint32_t)0x00000020U) /*!< Internal event is generated when trigger becomes active */
1336 /**
1337 * @}
1338 */
1339
1340 /** @defgroup FDCAN_TT_Time_Mark_Event_External FDCAN TT time mark event external
1341 * @{
1342 */
1343 #define FDCAN_TT_TM_NO_EXTERNAL_EVENT ((uint32_t)0x00000000U) /*!< No action */
1344 #define FDCAN_TT_TM_GEN_EXTERNAL_EVENT ((uint32_t)0x00000010U) /*!< External event (pulse) is generated when trigger becomes active */
1345 /**
1346 * @}
1347 */
1348
1349 /** @defgroup FDCAN_operation_mode FDCAN Operation Mode
1350 * @{
1351 */
1352 #define FDCAN_TT_COMMUNICATION_LEVEL1 ((uint32_t)0x00000001U) /*!< Time triggered communication, level 1 */
1353 #define FDCAN_TT_COMMUNICATION_LEVEL2 ((uint32_t)0x00000002U) /*!< Time triggered communication, level 2 */
1354 #define FDCAN_TT_COMMUNICATION_LEVEL0 ((uint32_t)0x00000003U) /*!< Time triggered communication, level 0 */
1355 /**
1356 * @}
1357 */
1358
1359 /** @defgroup FDCAN_TT_operation FDCAN TT Operation
1360 * @{
1361 */
1362 #define FDCAN_STRICTLY_TT_OPERATION ((uint32_t)0x00000000U) /*!< Strictly time-triggered operation */
1363 #define FDCAN_EXT_EVT_SYNC_TT_OPERATION ((uint32_t)FDCAN_TTOCF_GEN) /*!< External event-synchronized time-triggered operation */
1364 /**
1365 * @}
1366 */
1367
1368 /** @defgroup FDCAN_TT_time_master FDCAN TT Time Master
1369 * @{
1370 */
1371 #define FDCAN_TT_SLAVE ((uint32_t)0x00000000U) /*!< Time slave */
1372 #define FDCAN_TT_POTENTIAL_MASTER ((uint32_t)FDCAN_TTOCF_TM) /*!< Potential time master */
1373 /**
1374 * @}
1375 */
1376
1377 /** @defgroup FDCAN_TT_external_clk_sync FDCAN TT External Clock Synchronization
1378 * @{
1379 */
1380 #define FDCAN_TT_EXT_CLK_SYNC_DISABLE ((uint32_t)0x00000000U) /*!< External clock synchronization in Level 0,2 disabled */
1381 #define FDCAN_TT_EXT_CLK_SYNC_ENABLE ((uint32_t)FDCAN_TTOCF_EECS) /*!< External clock synchronization in Level 0,2 enabled */
1382 /**
1383 * @}
1384 */
1385
1386 /** @defgroup FDCAN_TT_global_time_filtering FDCAN TT Global Time Filtering
1387 * @{
1388 */
1389 #define FDCAN_TT_GLOB_TIME_FILT_DISABLE ((uint32_t)0x00000000U) /*!< Global time filtering in Level 0,2 disabled */
1390 #define FDCAN_TT_GLOB_TIME_FILT_ENABLE ((uint32_t)FDCAN_TTOCF_EGTF) /*!< Global time filtering in Level 0,2 enabled */
1391 /**
1392 * @}
1393 */
1394
1395 /** @defgroup FDCAN_TT_auto_clk_calibration FDCAN TT Automatic Clock Calibration
1396 * @{
1397 */
1398 #define FDCAN_TT_AUTO_CLK_CALIB_DISABLE ((uint32_t)0x00000000U) /*!< Automatic clock calibration in Level 0,2 disabled */
1399 #define FDCAN_TT_AUTO_CLK_CALIB_ENABLE ((uint32_t)FDCAN_TTOCF_ECC) /*!< Automatic clock calibration in Level 0,2 enabled */
1400 /**
1401 * @}
1402 */
1403
1404 /** @defgroup FDCAN_TT_event_trig_polarity FDCAN TT Event Trigger Polarity
1405 * @{
1406 */
1407 #define FDCAN_TT_EVT_TRIG_POL_RISING ((uint32_t)0x00000000U) /*!< Rising edge trigger */
1408 #define FDCAN_TT_EVT_TRIG_POL_FALLING ((uint32_t)FDCAN_TTOCF_EVTP) /*!< Falling edge trigger */
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup FDCAN_TT_basic_cycle_number FDCAN TT Basic Cycle Number
1414 * @{
1415 */
1416 #define FDCAN_TT_CYCLES_PER_MATRIX_1 ((uint32_t)0x00000000U) /*!< 1 Basic Cycle per Matrix */
1417 #define FDCAN_TT_CYCLES_PER_MATRIX_2 ((uint32_t)0x00000001U) /*!< 2 Basic Cycles per Matrix */
1418 #define FDCAN_TT_CYCLES_PER_MATRIX_4 ((uint32_t)0x00000003U) /*!< 4 Basic Cycles per Matrix */
1419 #define FDCAN_TT_CYCLES_PER_MATRIX_8 ((uint32_t)0x00000007U) /*!< 8 Basic Cycles per Matrix */
1420 #define FDCAN_TT_CYCLES_PER_MATRIX_16 ((uint32_t)0x0000000FU) /*!< 16 Basic Cycles per Matrix */
1421 #define FDCAN_TT_CYCLES_PER_MATRIX_32 ((uint32_t)0x0000001FU) /*!< 32 Basic Cycles per Matrix */
1422 #define FDCAN_TT_CYCLES_PER_MATRIX_64 ((uint32_t)0x0000003FU) /*!< 64 Basic Cycles per Matrix */
1423 /**
1424 * @}
1425 */
1426
1427 /** @defgroup FDCAN_TT_cycle_start_sync FDCAN TT Cycle Start Sync
1428 * @{
1429 */
1430 #define FDCAN_TT_NO_SYNC_PULSE ((uint32_t)0x00000000U) /*!< No sync pulse */
1431 #define FDCAN_TT_SYNC_BASIC_CYCLE_START ((uint32_t)0x00000040U) /*!< Sync pulse at start of basic cycle */
1432 #define FDCAN_TT_SYNC_MATRIX_START ((uint32_t)0x00000080U) /*!< Sync pulse at start of matrix */
1433 /**
1434 * @}
1435 */
1436
1437 /** @defgroup FDCAN_TT_stop_watch_trig_selection FDCAN TT Stop Watch Trigger Selection
1438 * @{
1439 */
1440 #define FDCAN_TT_STOP_WATCH_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as stop watch trigger */
1441 #define FDCAN_TT_STOP_WATCH_TRIGGER_1 ((uint32_t)0x00000001U) /*!< TIM3 selected as stop watch trigger */
1442 #define FDCAN_TT_STOP_WATCH_TRIGGER_2 ((uint32_t)0x00000002U) /*!< ETH selected as stop watch trigger */
1443 #define FDCAN_TT_STOP_WATCH_TRIGGER_3 ((uint32_t)0x00000003U) /*!< HRTIM selected as stop watch trigger */
1444 /**
1445 * @}
1446 */
1447
1448 /** @defgroup FDCAN_TT_event_trig_selection FDCAN TT Event Trigger Selection
1449 * @{
1450 */
1451 #define FDCAN_TT_EVENT_TRIGGER_0 ((uint32_t)0x00000000U) /*!< TIM2 selected as event trigger */
1452 #define FDCAN_TT_EVENT_TRIGGER_1 ((uint32_t)0x00000010U) /*!< TIM3 selected as event trigger */
1453 #define FDCAN_TT_EVENT_TRIGGER_2 ((uint32_t)0x00000020U) /*!< ETH selected as event trigger */
1454 #define FDCAN_TT_EVENT_TRIGGER_3 ((uint32_t)0x00000030U) /*!< HRTIM selected as event trigger */
1455 /**
1456 * @}
1457 */
1458
1459 /** @defgroup FDCAN_TT_stop_watch_source FDCAN TT Stop Watch Source
1460 * @{
1461 */
1462 #define FDCAN_TT_STOP_WATCH_DISABLED ((uint32_t)0x00000000U) /*!< Stop Watch disabled */
1463 #define FDCAN_TT_STOP_WATCH_CYCLE_TIME ((uint32_t)0x00000008U) /*!< Actual value of cycle time is copied to Capture Time register (TTCPT.SWV) */
1464 #define FDCAN_TT_STOP_WATCH_LOCAL_TIME ((uint32_t)0x00000010U) /*!< Actual value of local time is copied to Capture Time register (TTCPT.SWV) */
1465 #define FDCAN_TT_STOP_WATCH_GLOBAL_TIME ((uint32_t)0x00000018U) /*!< Actual value of global time is copied to Capture Time register (TTCPT.SWV) */
1466 /**
1467 * @}
1468 */
1469
1470 /** @defgroup FDCAN_TT_stop_watch_polarity FDCAN TT Stop Watch Polarity
1471 * @{
1472 */
1473 #define FDCAN_TT_STOP_WATCH_RISING ((uint32_t)0x00000000U) /*!< Selected stop watch source is captured at rising edge of fdcan1_swt */
1474 #define FDCAN_TT_STOP_WATCH_FALLING ((uint32_t)0x00000004U) /*!< Selected stop watch source is captured at falling edge of fdcan1_swt */
1475 /**
1476 * @}
1477 */
1478
1479 /** @defgroup FDCAN_TT_time_mark_source FDCAN TT Time Mark Source
1480 * @{
1481 */
1482 #define FDCAN_TT_REG_TIMEMARK_DIABLED ((uint32_t)0x00000000U) /*!< No Register Time Mark Interrupt generated */
1483 #define FDCAN_TT_REG_TIMEMARK_CYC_TIME ((uint32_t)0x00000040U) /*!< Register Time Mark Interrupt if Time Mark = cycle time */
1484 #define FDCAN_TT_REG_TIMEMARK_LOC_TIME ((uint32_t)0x00000080U) /*!< Register Time Mark Interrupt if Time Mark = local time */
1485 #define FDCAN_TT_REG_TIMEMARK_GLO_TIME ((uint32_t)0x000000C0U) /*!< Register Time Mark Interrupt if Time Mark = global time */
1486 /**
1487 * @}
1488 */
1489
1490 /** @defgroup FDCAN_TT_error_level FDCAN TT Error Level
1491 * @{
1492 */
1493 #define FDCAN_TT_NO_ERROR ((uint32_t)0x00000000U) /*!< Severity 0 - No Error */
1494 #define FDCAN_TT_WARNING ((uint32_t)0x00000001U) /*!< Severity 1 - Warning */
1495 #define FDCAN_TT_ERROR ((uint32_t)0x00000002U) /*!< Severity 2 - Error */
1496 #define FDCAN_TT_SEVERE_ERROR ((uint32_t)0x00000003U) /*!< Severity 3 - Severe Error */
1497 /**
1498 * @}
1499 */
1500
1501 /** @defgroup FDCAN_TT_master_state FDCAN TT Master State
1502 * @{
1503 */
1504 #define FDCAN_TT_MASTER_OFF ((uint32_t)0x00000000U) /*!< Master_Off, no master properties relevant */
1505 #define FDCAN_TT_TIME_SLAVE ((uint32_t)0x00000004U) /*!< Operating as Time Slave */
1506 #define FDCAN_TT_BACKUP_TIME_MASTER ((uint32_t)0x00000008U) /*!< Operating as Backup Time Master */
1507 #define FDCAN_TT_CURRENT_TIME_MASTER ((uint32_t)0x0000000CU) /*!< Operating as current Time Master */
1508 /**
1509 * @}
1510 */
1511
1512 /** @defgroup FDCAN_TT_sync_state FDCAN TT Synchronization State
1513 * @{
1514 */
1515 #define FDCAN_TT_OUT_OF_SYNC ((uint32_t)0x00000000U) /*!< Out of Synchronization */
1516 #define FDCAN_TT_SYNCHRONIZING ((uint32_t)0x00000010U) /*!< Synchronizing to communication */
1517 #define FDCAN_TT_IN_GAP ((uint32_t)0x00000020U) /*!< Schedule suspended by Gap */
1518 #define FDCAN_TT_IN_SCHEDULE ((uint32_t)0x00000030U) /*!< Synchronized to schedule */
1519 /**
1520 * @}
1521 */
1522
1523 /** @defgroup Interrupt_Masks Interrupt masks
1524 * @{
1525 */
1526 #define FDCAN_IR_MASK ((uint32_t)0x3FCFFFFFU) /*!< FDCAN interrupts mask */
1527 #define CCU_IR_MASK ((uint32_t)0xC0000000U) /*!< CCU interrupts mask */
1528 /**
1529 * @}
1530 */
1531
1532 /** @defgroup FDCAN_flags FDCAN Flags
1533 * @{
1534 */
1535 #define FDCAN_FLAG_TX_COMPLETE FDCAN_IR_TC /*!< Transmission Completed */
1536 #define FDCAN_FLAG_TX_ABORT_COMPLETE FDCAN_IR_TCF /*!< Transmission Cancellation Finished */
1537 #define FDCAN_FLAG_TX_FIFO_EMPTY FDCAN_IR_TFE /*!< Tx FIFO Empty */
1538 #define FDCAN_FLAG_RX_HIGH_PRIORITY_MSG FDCAN_IR_HPM /*!< High priority message received */
1539 #define FDCAN_FLAG_RX_BUFFER_NEW_MESSAGE FDCAN_IR_DRX /*!< At least one received message stored into a Rx Buffer */
1540 #define FDCAN_FLAG_TX_EVT_FIFO_ELT_LOST FDCAN_IR_TEFL /*!< Tx Event FIFO element lost */
1541 #define FDCAN_FLAG_TX_EVT_FIFO_FULL FDCAN_IR_TEFF /*!< Tx Event FIFO full */
1542 #define FDCAN_FLAG_TX_EVT_FIFO_WATERMARK FDCAN_IR_TEFW /*!< Tx Event FIFO fill level reached watermark */
1543 #define FDCAN_FLAG_TX_EVT_FIFO_NEW_DATA FDCAN_IR_TEFN /*!< Tx Handler wrote Tx Event FIFO element */
1544 #define FDCAN_FLAG_RX_FIFO0_MESSAGE_LOST FDCAN_IR_RF0L /*!< Rx FIFO 0 message lost */
1545 #define FDCAN_FLAG_RX_FIFO0_FULL FDCAN_IR_RF0F /*!< Rx FIFO 0 full */
1546 #define FDCAN_FLAG_RX_FIFO0_WATERMARK FDCAN_IR_RF0W /*!< Rx FIFO 0 fill level reached watermark */
1547 #define FDCAN_FLAG_RX_FIFO0_NEW_MESSAGE FDCAN_IR_RF0N /*!< New message written to Rx FIFO 0 */
1548 #define FDCAN_FLAG_RX_FIFO1_MESSAGE_LOST FDCAN_IR_RF1L /*!< Rx FIFO 1 message lost */
1549 #define FDCAN_FLAG_RX_FIFO1_FULL FDCAN_IR_RF1F /*!< Rx FIFO 1 full */
1550 #define FDCAN_FLAG_RX_FIFO1_WATERMARK FDCAN_IR_RF1W /*!< Rx FIFO 1 fill level reached watermark */
1551 #define FDCAN_FLAG_RX_FIFO1_NEW_MESSAGE FDCAN_IR_RF1N /*!< New message written to Rx FIFO 1 */
1552 #define FDCAN_FLAG_RAM_ACCESS_FAILURE FDCAN_IR_MRAF /*!< Message RAM access failure occurred */
1553 #define FDCAN_FLAG_ERROR_LOGGING_OVERFLOW FDCAN_IR_ELO /*!< Overflow of FDCAN Error Logging Counter occurred */
1554 #define FDCAN_FLAG_ERROR_PASSIVE FDCAN_IR_EP /*!< Error_Passive status changed */
1555 #define FDCAN_FLAG_ERROR_WARNING FDCAN_IR_EW /*!< Error_Warning status changed */
1556 #define FDCAN_FLAG_BUS_OFF FDCAN_IR_BO /*!< Bus_Off status changed */
1557 #define FDCAN_FLAG_RAM_WATCHDOG FDCAN_IR_WDI /*!< Message RAM Watchdog event due to missing READY */
1558 #define FDCAN_FLAG_ARB_PROTOCOL_ERROR FDCAN_IR_PEA /*!< Protocol error in arbitration phase detected */
1559 #define FDCAN_FLAG_DATA_PROTOCOL_ERROR FDCAN_IR_PED /*!< Protocol error in data phase detected */
1560 #define FDCAN_FLAG_RESERVED_ADDRESS_ACCESS FDCAN_IR_ARA /*!< Access to reserved address occurred */
1561 #define FDCAN_FLAG_TIMESTAMP_WRAPAROUND FDCAN_IR_TSW /*!< Timestamp counter wrapped around */
1562 #define FDCAN_FLAG_TIMEOUT_OCCURRED FDCAN_IR_TOO /*!< Timeout reached */
1563 #define FDCAN_FLAG_CALIB_STATE_CHANGED (FDCANCCU_IR_CSC << 30) /*!< Clock calibration state changed */
1564 #define FDCAN_FLAG_CALIB_WATCHDOG_EVENT (FDCANCCU_IR_CWE << 30) /*!< Clock calibration watchdog event occurred */
1565 /**
1566 * @}
1567 */
1568
1569 /** @defgroup FDCAN_Interrupts FDCAN Interrupts
1570 * @{
1571 */
1572
1573 /** @defgroup FDCAN_Tx_Interrupts FDCAN Tx Interrupts
1574 * @{
1575 */
1576 #define FDCAN_IT_TX_COMPLETE FDCAN_IE_TCE /*!< Transmission Completed */
1577 #define FDCAN_IT_TX_ABORT_COMPLETE FDCAN_IE_TCFE /*!< Transmission Cancellation Finished */
1578 #define FDCAN_IT_TX_FIFO_EMPTY FDCAN_IE_TFEE /*!< Tx FIFO Empty */
1579 /**
1580 * @}
1581 */
1582
1583 /** @defgroup FDCAN_Rx_Interrupts FDCAN Rx Interrupts
1584 * @{
1585 */
1586 #define FDCAN_IT_RX_HIGH_PRIORITY_MSG FDCAN_IE_HPME /*!< High priority message received */
1587 #define FDCAN_IT_RX_BUFFER_NEW_MESSAGE FDCAN_IE_DRXE /*!< At least one received message stored into a Rx Buffer */
1588 /**
1589 * @}
1590 */
1591
1592 /** @defgroup FDCAN_Counter_Interrupts FDCAN Counter Interrupts
1593 * @{
1594 */
1595 #define FDCAN_IT_TIMESTAMP_WRAPAROUND FDCAN_IE_TSWE /*!< Timestamp counter wrapped around */
1596 #define FDCAN_IT_TIMEOUT_OCCURRED FDCAN_IE_TOOE /*!< Timeout reached */
1597 /**
1598 * @}
1599 */
1600
1601 /** @defgroup FDCAN_Clock_Calibration_Interrupts Clock Calibration Interrupts
1602 * @{
1603 */
1604 #define FDCAN_IT_CALIB_STATE_CHANGED (FDCANCCU_IE_CSCE << 30) /*!< Clock calibration state changed */
1605 #define FDCAN_IT_CALIB_WATCHDOG_EVENT (FDCANCCU_IE_CWEE << 30) /*!< Clock calibration watchdog event occurred */
1606 /**
1607 * @}
1608 */
1609
1610 /** @defgroup FDCAN_Tx_Event_Fifo_Interrupts FDCAN Tx Event FIFO Interrupts
1611 * @{
1612 */
1613 #define FDCAN_IT_TX_EVT_FIFO_ELT_LOST FDCAN_IE_TEFLE /*!< Tx Event FIFO element lost */
1614 #define FDCAN_IT_TX_EVT_FIFO_FULL FDCAN_IE_TEFFE /*!< Tx Event FIFO full */
1615 #define FDCAN_IT_TX_EVT_FIFO_WATERMARK FDCAN_IE_TEFWE /*!< Tx Event FIFO fill level reached watermark */
1616 #define FDCAN_IT_TX_EVT_FIFO_NEW_DATA FDCAN_IE_TEFNE /*!< Tx Handler wrote Tx Event FIFO element */
1617 /**
1618 * @}
1619 */
1620
1621 /** @defgroup FDCAN_Rx_Fifo0_Interrupts FDCAN Rx FIFO 0 Interrupts
1622 * @{
1623 */
1624 #define FDCAN_IT_RX_FIFO0_MESSAGE_LOST FDCAN_IE_RF0LE /*!< Rx FIFO 0 message lost */
1625 #define FDCAN_IT_RX_FIFO0_FULL FDCAN_IE_RF0FE /*!< Rx FIFO 0 full */
1626 #define FDCAN_IT_RX_FIFO0_WATERMARK FDCAN_IE_RF0WE /*!< Rx FIFO 0 fill level reached watermark */
1627 #define FDCAN_IT_RX_FIFO0_NEW_MESSAGE FDCAN_IE_RF0NE /*!< New message written to Rx FIFO 0 */
1628 /**
1629 * @}
1630 */
1631
1632 /** @defgroup FDCAN_Rx_Fifo1_Interrupts FDCAN Rx FIFO 1 Interrupts
1633 * @{
1634 */
1635 #define FDCAN_IT_RX_FIFO1_MESSAGE_LOST FDCAN_IE_RF1LE /*!< Rx FIFO 1 message lost */
1636 #define FDCAN_IT_RX_FIFO1_FULL FDCAN_IE_RF1FE /*!< Rx FIFO 1 full */
1637 #define FDCAN_IT_RX_FIFO1_WATERMARK FDCAN_IE_RF1WE /*!< Rx FIFO 1 fill level reached watermark */
1638 #define FDCAN_IT_RX_FIFO1_NEW_MESSAGE FDCAN_IE_RF1NE /*!< New message written to Rx FIFO 1 */
1639 /**
1640 * @}
1641 */
1642
1643 /** @defgroup FDCAN_Error_Interrupts FDCAN Error Interrupts
1644 * @{
1645 */
1646 #define FDCAN_IT_RAM_ACCESS_FAILURE FDCAN_IE_MRAFE /*!< Message RAM access failure occurred */
1647 #define FDCAN_IT_ERROR_LOGGING_OVERFLOW FDCAN_IE_ELOE /*!< Overflow of FDCAN Error Logging Counter occurred */
1648 #define FDCAN_IT_RAM_WATCHDOG FDCAN_IE_WDIE /*!< Message RAM Watchdog event due to missing READY */
1649 #define FDCAN_IT_ARB_PROTOCOL_ERROR FDCAN_IE_PEAE /*!< Protocol error in arbitration phase detected */
1650 #define FDCAN_IT_DATA_PROTOCOL_ERROR FDCAN_IE_PEDE /*!< Protocol error in data phase detected */
1651 #define FDCAN_IT_RESERVED_ADDRESS_ACCESS FDCAN_IE_ARAE /*!< Access to reserved address occurred */
1652 /**
1653 * @}
1654 */
1655
1656 /** @defgroup FDCAN_Error_Status_Interrupts FDCAN Error Status Interrupts
1657 * @{
1658 */
1659 #define FDCAN_IT_ERROR_PASSIVE FDCAN_IE_EPE /*!< Error_Passive status changed */
1660 #define FDCAN_IT_ERROR_WARNING FDCAN_IE_EWE /*!< Error_Warning status changed */
1661 #define FDCAN_IT_BUS_OFF FDCAN_IE_BOE /*!< Bus_Off status changed */
1662 /**
1663 * @}
1664 */
1665
1666 /**
1667 * @}
1668 */
1669
1670 /** @defgroup FDCAN_TTflags FDCAN TT Flags
1671 * @{
1672 */
1673 #define FDCAN_TT_FLAG_BASIC_CYCLE_START FDCAN_TTIR_SBC /*!< Start of Basic Cycle */
1674 #define FDCAN_TT_FLAG_MATRIX_CYCLE_START FDCAN_TTIR_SMC /*!< Start of Matrix Cycle */
1675 #define FDCAN_TT_FLAG_SYNC_MODE_CHANGE FDCAN_TTIR_CSM /*!< Change of Synchronization Mode */
1676 #define FDCAN_TT_FLAG_START_OF_GAP FDCAN_TTIR_SOG /*!< Start of Gap */
1677 #define FDCAN_TT_FLAG_REG_TIME_MARK FDCAN_TTIR_RTMI /*!< Register Time Mark Interrupt */
1678 #define FDCAN_TT_FLAG_TRIG_TIME_MARK FDCAN_TTIR_TTMI /*!< Trigger Time Mark Event Internal */
1679 #define FDCAN_TT_FLAG_STOP_WATCH FDCAN_TTIR_SWE /*!< Stop Watch Event */
1680 #define FDCAN_TT_FLAG_GLOBAL_TIME_WRAP FDCAN_TTIR_GTW /*!< Global Time Wrap */
1681 #define FDCAN_TT_FLAG_GLOBAL_TIME_DISC FDCAN_TTIR_GTD /*!< Global Time Discontinuity */
1682 #define FDCAN_TT_FLAG_GLOBAL_TIME_ERROR FDCAN_TTIR_GTE /*!< Global Time Error */
1683 #define FDCAN_TT_FLAG_TX_COUNT_UNDERFLOW FDCAN_TTIR_TXU /*!< Tx Count Underflow */
1684 #define FDCAN_TT_FLAG_TX_COUNT_OVERFLOW FDCAN_TTIR_TXO /*!< Tx Count Overflow */
1685 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_1 FDCAN_TTIR_SE1 /*!< Scheduling Error 1 */
1686 #define FDCAN_TT_FLAG_SCHEDULING_ERROR_2 FDCAN_TTIR_SE2 /*!< Scheduling Error 2 */
1687 #define FDCAN_TT_FLAG_ERROR_LEVEL_CHANGE FDCAN_TTIR_ELC /*!< Error Level Changed */
1688 #define FDCAN_TT_FLAG_INIT_WATCH_TRIGGER FDCAN_TTIR_IWT /*!< Initialization Watch Trigger */
1689 #define FDCAN_TT_FLAG_WATCH_TRIGGER FDCAN_TTIR_WT /*!< Watch Trigger */
1690 #define FDCAN_TT_FLAG_APPLICATION_WATCHDOG FDCAN_TTIR_AW /*!< Application Watchdog */
1691 #define FDCAN_TT_FLAG_CONFIG_ERROR FDCAN_TTIR_CER /*!< Configuration Error */
1692 /**
1693 * @}
1694 */
1695
1696 /** @defgroup FDCAN_TTInterrupts FDCAN TT Interrupts
1697 * @{
1698 */
1699
1700 /** @defgroup FDCAN_TTScheduleSynchronization_Interrupts FDCAN TT Schedule Synchronization Interrupts
1701 * @{
1702 */
1703 #define FDCAN_TT_IT_BASIC_CYCLE_START FDCAN_TTIE_SBCE /*!< Start of Basic Cycle */
1704 #define FDCAN_TT_IT_MATRIX_CYCLE_START FDCAN_TTIE_SMCE /*!< Start of Matrix Cycle */
1705 #define FDCAN_TT_IT_SYNC_MODE_CHANGE FDCAN_TTIE_CSME /*!< Change of Synchronization Mode */
1706 #define FDCAN_TT_IT_START_OF_GAP FDCAN_TTIE_SOGE /*!< Start of Gap */
1707 /**
1708 * @}
1709 */
1710
1711 /** @defgroup FDCAN_TTTimeMark_Interrupts FDCAN TT Time Mark Interrupts
1712 * @{
1713 */
1714 #define FDCAN_TT_IT_REG_TIME_MARK FDCAN_TTIE_RTMIE /*!< Register Time Mark Interrupt */
1715 #define FDCAN_TT_IT_TRIG_TIME_MARK FDCAN_TTIE_TTMIE /*!< Trigger Time Mark Event Internal */
1716 /**
1717 * @}
1718 */
1719
1720 /** @defgroup FDCAN_TTStopWatch_Interrupt FDCAN TT Stop Watch Interrupt
1721 * @{
1722 */
1723 #define FDCAN_TT_IT_STOP_WATCH FDCAN_TTIE_SWEE /*!< Stop Watch Event */
1724 /**
1725 * @}
1726 */
1727
1728 /** @defgroup FDCAN_TTGlobalTime_Interrupts FDCAN TT Global Time Interrupts
1729 * @{
1730 */
1731 #define FDCAN_TT_IT_GLOBAL_TIME_WRAP FDCAN_TTIE_GTWE /*!< Global Time Wrap */
1732 #define FDCAN_TT_IT_GLOBAL_TIME_DISC FDCAN_TTIE_GTDE /*!< Global Time Discontinuity */
1733 /**
1734 * @}
1735 */
1736
1737 /** @defgroup FDCAN_TTDisturbingError_Interrupts FDCAN TT Disturbing Error Interrupts
1738 * @{
1739 */
1740 #define FDCAN_TT_IT_GLOBAL_TIME_ERROR FDCAN_TTIE_GTEE /*!< Global Time Error */
1741 #define FDCAN_TT_IT_TX_COUNT_UNDERFLOW FDCAN_TTIE_TXUE /*!< Tx Count Underflow */
1742 #define FDCAN_TT_IT_TX_COUNT_OVERFLOW FDCAN_TTIE_TXOE /*!< Tx Count Overflow */
1743 #define FDCAN_TT_IT_SCHEDULING_ERROR_1 FDCAN_TTIE_SE1E /*!< Scheduling Error 1 */
1744 #define FDCAN_TT_IT_SCHEDULING_ERROR_2 FDCAN_TTIE_SE2E /*!< Scheduling Error 2 */
1745 #define FDCAN_TT_IT_ERROR_LEVEL_CHANGE FDCAN_TTIE_ELCE /*!< Error Level Changed */
1746 /**
1747 * @}
1748 */
1749
1750 /** @defgroup FDCAN_TTFatalError_Interrupts FDCAN TT Fatal Error Interrupts
1751 * @{
1752 */
1753 #define FDCAN_TT_IT_INIT_WATCH_TRIGGER FDCAN_TTIE_IWTE /*!< Initialization Watch Trigger */
1754 #define FDCAN_TT_IT_WATCH_TRIGGER FDCAN_TTIE_WTE /*!< Watch Trigger */
1755 #define FDCAN_TT_IT_APPLICATION_WATCHDOG FDCAN_TTIE_AWE /*!< Application Watchdog */
1756 #define FDCAN_TT_IT_CONFIG_ERROR FDCAN_TTIE_CERE /*!< Configuration Error */
1757 /**
1758 * @}
1759 */
1760
1761 /**
1762 * @}
1763 */
1764
1765 /**
1766 * @}
1767 */
1768
1769 /* Exported macro ------------------------------------------------------------*/
1770 /** @defgroup FDCAN_Exported_Macros FDCAN Exported Macros
1771 * @{
1772 */
1773
1774 /** @brief Reset FDCAN handle state.
1775 * @param __HANDLE__ FDCAN handle.
1776 * @retval None
1777 */
1778 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
1779 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) do{ \
1780 (__HANDLE__)->State = HAL_FDCAN_STATE_RESET; \
1781 (__HANDLE__)->MspInitCallback = NULL; \
1782 (__HANDLE__)->MspDeInitCallback = NULL; \
1783 } while(0)
1784 #else
1785 #define __HAL_FDCAN_RESET_HANDLE_STATE(__HANDLE__) ((__HANDLE__)->State = HAL_FDCAN_STATE_RESET)
1786 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
1787
1788 /**
1789 * @brief Enable the specified FDCAN interrupts.
1790 * @param __HANDLE__ FDCAN handle.
1791 * @param __INTERRUPT__ FDCAN interrupt.
1792 * This parameter can be any combination of @arg FDCAN_Interrupts
1793 * @retval None
1794 */
1795 #define __HAL_FDCAN_ENABLE_IT(__HANDLE__, __INTERRUPT__) \
1796 do{ \
1797 (__HANDLE__)->Instance->IE |= ((__INTERRUPT__) & FDCAN_IR_MASK); \
1798 FDCAN_CCU->IE |= (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
1799 }while(0)
1800
1801
1802 /**
1803 * @brief Disable the specified FDCAN interrupts.
1804 * @param __HANDLE__ FDCAN handle.
1805 * @param __INTERRUPT__ FDCAN interrupt.
1806 * This parameter can be any combination of @arg FDCAN_Interrupts
1807 * @retval None
1808 */
1809 #define __HAL_FDCAN_DISABLE_IT(__HANDLE__, __INTERRUPT__) \
1810 do{ \
1811 ((__HANDLE__)->Instance->IE) &= ~((__INTERRUPT__) & FDCAN_IR_MASK); \
1812 FDCAN_CCU->IE &= ~(((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
1813 }while(0)
1814
1815 /**
1816 * @brief Check whether the specified FDCAN interrupt is set or not.
1817 * @param __HANDLE__ FDCAN handle.
1818 * @param __INTERRUPT__ FDCAN interrupt.
1819 * This parameter can be one of @arg FDCAN_Interrupts
1820 * @retval ITStatus
1821 */
1822 #define __HAL_FDCAN_GET_IT(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__INTERRUPT__)) : ((FDCAN_CCU->IR << 30) & (__INTERRUPT__)))
1823
1824 /**
1825 * @brief Clear the specified FDCAN interrupts.
1826 * @param __HANDLE__ FDCAN handle.
1827 * @param __INTERRUPT__ specifies the interrupts to clear.
1828 * This parameter can be any combination of @arg FDCAN_Interrupts
1829 * @retval None
1830 */
1831 #define __HAL_FDCAN_CLEAR_IT(__HANDLE__, __INTERRUPT__) \
1832 do{ \
1833 ((__HANDLE__)->Instance->IR) = ((__INTERRUPT__) & FDCAN_IR_MASK); \
1834 FDCAN_CCU->IR = (((__INTERRUPT__) & CCU_IR_MASK) >> 30); \
1835 }while(0)
1836
1837 /**
1838 * @brief Check whether the specified FDCAN flag is set or not.
1839 * @param __HANDLE__ FDCAN handle.
1840 * @param __FLAG__ FDCAN flag.
1841 * This parameter can be one of @arg FDCAN_flags
1842 * @retval FlagStatus
1843 */
1844 #define __HAL_FDCAN_GET_FLAG(__HANDLE__, __FLAG__) (((__FLAG__) < FDCAN_FLAG_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IR & (__FLAG__)) : ((FDCAN_CCU->IR << 30) & (__FLAG__)))
1845
1846 /**
1847 * @brief Clear the specified FDCAN flags.
1848 * @param __HANDLE__ FDCAN handle.
1849 * @param __FLAG__ specifies the flags to clear.
1850 * This parameter can be any combination of @arg FDCAN_flags
1851 * @retval None
1852 */
1853 #define __HAL_FDCAN_CLEAR_FLAG(__HANDLE__, __FLAG__) \
1854 do{ \
1855 ((__HANDLE__)->Instance->IR) = ((__FLAG__) & FDCAN_IR_MASK); \
1856 FDCAN_CCU->IR = (((__FLAG__) & CCU_IR_MASK) >> 30); \
1857 }while(0)
1858
1859 /** @brief Check if the specified FDCAN interrupt source is enabled or disabled.
1860 * @param __HANDLE__ FDCAN handle.
1861 * @param __INTERRUPT__ specifies the FDCAN interrupt source to check.
1862 * This parameter can be a value of @arg FDCAN_Interrupts
1863 * @retval ITStatus
1864 */
1865 #define __HAL_FDCAN_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__INTERRUPT__) < FDCAN_IT_CALIB_WATCHDOG_EVENT) ? ((__HANDLE__)->Instance->IE & (__INTERRUPT__)) : ((FDCAN_CCU->IE << 30) & (__INTERRUPT__)))
1866
1867 /**
1868 * @brief Enable the specified FDCAN TT interrupts.
1869 * @param __HANDLE__ FDCAN handle.
1870 * @param __INTERRUPT__ FDCAN TT interrupt.
1871 * This parameter can be any combination of @arg FDCAN_TTInterrupts
1872 * @retval None
1873 */
1874 #define __HAL_FDCAN_TT_ENABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) |= (__INTERRUPT__))
1875
1876 /**
1877 * @brief Disable the specified FDCAN TT interrupts.
1878 * @param __HANDLE__ FDCAN handle.
1879 * @param __INTERRUPT__ FDCAN TT interrupt.
1880 * This parameter can be any combination of @arg FDCAN_TTInterrupts
1881 * @retval None
1882 */
1883 #define __HAL_FDCAN_TT_DISABLE_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) &= ~(__INTERRUPT__))
1884
1885 /**
1886 * @brief Check whether the specified FDCAN TT interrupt is set or not.
1887 * @param __HANDLE__ FDCAN handle.
1888 * @param __INTERRUPT__ FDCAN TT interrupt.
1889 * This parameter can be one of @arg FDCAN_TTInterrupts
1890 * @retval ITStatus
1891 */
1892 #define __HAL_FDCAN_TT_GET_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) & (__INTERRUPT__))
1893
1894 /**
1895 * @brief Clear the specified FDCAN TT interrupts.
1896 * @param __HANDLE__ FDCAN handle.
1897 * @param __INTERRUPT__ specifies the TT interrupts to clear.
1898 * This parameter can be any combination of @arg FDCAN_TTInterrupts
1899 * @retval None
1900 */
1901 #define __HAL_FDCAN_TT_CLEAR_IT(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIR) = (__INTERRUPT__))
1902
1903 /**
1904 * @brief Check whether the specified FDCAN TT flag is set or not.
1905 * @param __HANDLE__ FDCAN handle.
1906 * @param __FLAG__ FDCAN TT flag.
1907 * This parameter can be one of @arg FDCAN_TTflags
1908 * @retval FlagStatus
1909 */
1910 #define __HAL_FDCAN_TT_GET_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) & (__FLAG__))
1911
1912 /**
1913 * @brief Clear the specified FDCAN TT flags.
1914 * @param __HANDLE__ FDCAN handle.
1915 * @param __FLAG__ specifies the TT flags to clear.
1916 * This parameter can be any combination of @arg FDCAN_TTflags
1917 * @retval None
1918 */
1919 #define __HAL_FDCAN_TT_CLEAR_FLAG(__HANDLE__, __FLAG__) (((__HANDLE__)->ttcan->TTIR) = (__FLAG__))
1920
1921 /** @brief Check if the specified FDCAN TT interrupt source is enabled or disabled.
1922 * @param __HANDLE__ FDCAN handle.
1923 * @param __INTERRUPT__ specifies the FDCAN TT interrupt source to check.
1924 * This parameter can be a value of @arg FDCAN_TTInterrupts
1925 * @retval ITStatus
1926 */
1927 #define __HAL_FDCAN_TT_GET_IT_SOURCE(__HANDLE__, __INTERRUPT__) (((__HANDLE__)->ttcan->TTIE) & (__INTERRUPT__))
1928
1929 /**
1930 * @}
1931 */
1932
1933 /* Exported functions --------------------------------------------------------*/
1934 /** @addtogroup FDCAN_Exported_Functions
1935 * @{
1936 */
1937
1938 /** @addtogroup FDCAN_Exported_Functions_Group1
1939 * @{
1940 */
1941 /* Initialization and de-initialization functions *****************************/
1942 HAL_StatusTypeDef HAL_FDCAN_Init(FDCAN_HandleTypeDef *hfdcan);
1943 HAL_StatusTypeDef HAL_FDCAN_DeInit(FDCAN_HandleTypeDef *hfdcan);
1944 void HAL_FDCAN_MspInit(FDCAN_HandleTypeDef *hfdcan);
1945 void HAL_FDCAN_MspDeInit(FDCAN_HandleTypeDef *hfdcan);
1946 HAL_StatusTypeDef HAL_FDCAN_EnterPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
1947 HAL_StatusTypeDef HAL_FDCAN_ExitPowerDownMode(FDCAN_HandleTypeDef *hfdcan);
1948
1949 #if USE_HAL_FDCAN_REGISTER_CALLBACKS == 1
1950 /* Callbacks Register/UnRegister functions ***********************************/
1951 HAL_StatusTypeDef HAL_FDCAN_RegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID, pFDCAN_CallbackTypeDef pCallback);
1952 HAL_StatusTypeDef HAL_FDCAN_UnRegisterCallback(FDCAN_HandleTypeDef *hfdcan, HAL_FDCAN_CallbackIDTypeDef CallbackID);
1953 HAL_StatusTypeDef HAL_FDCAN_RegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ClockCalibrationCallbackTypeDef pCallback);
1954 HAL_StatusTypeDef HAL_FDCAN_UnRegisterClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan);
1955 HAL_StatusTypeDef HAL_FDCAN_RegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxEventFifoCallbackTypeDef pCallback);
1956 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan);
1957 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo0CallbackTypeDef pCallback);
1958 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo0Callback(FDCAN_HandleTypeDef *hfdcan);
1959 HAL_StatusTypeDef HAL_FDCAN_RegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_RxFifo1CallbackTypeDef pCallback);
1960 HAL_StatusTypeDef HAL_FDCAN_UnRegisterRxFifo1Callback(FDCAN_HandleTypeDef *hfdcan);
1961 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferCompleteCallbackTypeDef pCallback);
1962 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan);
1963 HAL_StatusTypeDef HAL_FDCAN_RegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TxBufferAbortCallbackTypeDef pCallback);
1964 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan);
1965 HAL_StatusTypeDef HAL_FDCAN_RegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_ErrorStatusCallbackTypeDef pCallback);
1966 HAL_StatusTypeDef HAL_FDCAN_UnRegisterErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan);
1967 HAL_StatusTypeDef HAL_FDCAN_RegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_ScheduleSyncCallbackTypeDef pCallback);
1968 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan);
1969 HAL_StatusTypeDef HAL_FDCAN_RegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_TimeMarkCallbackTypeDef pCallback);
1970 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTTimeMarkCallback(FDCAN_HandleTypeDef *hfdcan);
1971 HAL_StatusTypeDef HAL_FDCAN_RegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_StopWatchCallbackTypeDef pCallback);
1972 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTStopWatchCallback(FDCAN_HandleTypeDef *hfdcan);
1973 HAL_StatusTypeDef HAL_FDCAN_RegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, pFDCAN_TT_GlobalTimeCallbackTypeDef pCallback);
1974 HAL_StatusTypeDef HAL_FDCAN_UnRegisterTTGlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan);
1975 #endif /* USE_HAL_FDCAN_REGISTER_CALLBACKS */
1976 /**
1977 * @}
1978 */
1979
1980 /** @addtogroup FDCAN_Exported_Functions_Group2
1981 * @{
1982 */
1983 /* Configuration functions ****************************************************/
1984 HAL_StatusTypeDef HAL_FDCAN_ConfigClockCalibration(FDCAN_HandleTypeDef *hfdcan, FDCAN_ClkCalUnitTypeDef *sCcuConfig);
1985 uint32_t HAL_FDCAN_GetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
1986 HAL_StatusTypeDef HAL_FDCAN_ResetClockCalibrationState(FDCAN_HandleTypeDef *hfdcan);
1987 uint32_t HAL_FDCAN_GetClockCalibrationCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t Counter);
1988 HAL_StatusTypeDef HAL_FDCAN_ConfigFilter(FDCAN_HandleTypeDef *hfdcan, FDCAN_FilterTypeDef *sFilterConfig);
1989 HAL_StatusTypeDef HAL_FDCAN_ConfigGlobalFilter(FDCAN_HandleTypeDef *hfdcan, uint32_t NonMatchingStd, uint32_t NonMatchingExt, uint32_t RejectRemoteStd, uint32_t RejectRemoteExt);
1990 HAL_StatusTypeDef HAL_FDCAN_ConfigExtendedIdMask(FDCAN_HandleTypeDef *hfdcan, uint32_t Mask);
1991 HAL_StatusTypeDef HAL_FDCAN_ConfigRxFifoOverwrite(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo, uint32_t OperationMode);
1992 HAL_StatusTypeDef HAL_FDCAN_ConfigFifoWatermark(FDCAN_HandleTypeDef *hfdcan, uint32_t FIFO, uint32_t Watermark);
1993 HAL_StatusTypeDef HAL_FDCAN_ConfigRamWatchdog(FDCAN_HandleTypeDef *hfdcan, uint32_t CounterStartValue);
1994 HAL_StatusTypeDef HAL_FDCAN_ConfigTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampPrescaler);
1995 HAL_StatusTypeDef HAL_FDCAN_EnableTimestampCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimestampOperation);
1996 HAL_StatusTypeDef HAL_FDCAN_DisableTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1997 uint16_t HAL_FDCAN_GetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1998 HAL_StatusTypeDef HAL_FDCAN_ResetTimestampCounter(FDCAN_HandleTypeDef *hfdcan);
1999 HAL_StatusTypeDef HAL_FDCAN_ConfigTimeoutCounter(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeoutOperation, uint32_t TimeoutPeriod);
2000 HAL_StatusTypeDef HAL_FDCAN_EnableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2001 HAL_StatusTypeDef HAL_FDCAN_DisableTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2002 uint16_t HAL_FDCAN_GetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2003 HAL_StatusTypeDef HAL_FDCAN_ResetTimeoutCounter(FDCAN_HandleTypeDef *hfdcan);
2004 HAL_StatusTypeDef HAL_FDCAN_ConfigTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan, uint32_t TdcOffset, uint32_t TdcFilter);
2005 HAL_StatusTypeDef HAL_FDCAN_EnableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
2006 HAL_StatusTypeDef HAL_FDCAN_DisableTxDelayCompensation(FDCAN_HandleTypeDef *hfdcan);
2007 HAL_StatusTypeDef HAL_FDCAN_EnableISOMode(FDCAN_HandleTypeDef *hfdcan);
2008 HAL_StatusTypeDef HAL_FDCAN_DisableISOMode(FDCAN_HandleTypeDef *hfdcan);
2009 HAL_StatusTypeDef HAL_FDCAN_EnableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
2010 HAL_StatusTypeDef HAL_FDCAN_DisableEdgeFiltering(FDCAN_HandleTypeDef *hfdcan);
2011 /**
2012 * @}
2013 */
2014
2015 /** @addtogroup FDCAN_Exported_Functions_Group3
2016 * @{
2017 */
2018 /* Control functions **********************************************************/
2019 HAL_StatusTypeDef HAL_FDCAN_Start(FDCAN_HandleTypeDef *hfdcan);
2020 HAL_StatusTypeDef HAL_FDCAN_Stop(FDCAN_HandleTypeDef *hfdcan);
2021 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxFifoQ(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData);
2022 HAL_StatusTypeDef HAL_FDCAN_AddMessageToTxBuffer(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxHeaderTypeDef *pTxHeader, uint8_t *pTxData, uint32_t BufferIndex);
2023 HAL_StatusTypeDef HAL_FDCAN_EnableTxBufferRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
2024 uint32_t HAL_FDCAN_GetLatestTxFifoQRequestBuffer(FDCAN_HandleTypeDef *hfdcan);
2025 HAL_StatusTypeDef HAL_FDCAN_AbortTxRequest(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndex);
2026 HAL_StatusTypeDef HAL_FDCAN_GetRxMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t RxLocation, FDCAN_RxHeaderTypeDef *pRxHeader, uint8_t *pRxData);
2027 HAL_StatusTypeDef HAL_FDCAN_GetTxEvent(FDCAN_HandleTypeDef *hfdcan, FDCAN_TxEventFifoTypeDef *pTxEvent);
2028 HAL_StatusTypeDef HAL_FDCAN_GetHighPriorityMessageStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_HpMsgStatusTypeDef *HpMsgStatus);
2029 HAL_StatusTypeDef HAL_FDCAN_GetProtocolStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_ProtocolStatusTypeDef *ProtocolStatus);
2030 HAL_StatusTypeDef HAL_FDCAN_GetErrorCounters(FDCAN_HandleTypeDef *hfdcan, FDCAN_ErrorCountersTypeDef *ErrorCounters);
2031 uint32_t HAL_FDCAN_IsRxBufferMessageAvailable(FDCAN_HandleTypeDef *hfdcan, uint32_t RxBufferIndex);
2032 uint32_t HAL_FDCAN_IsTxBufferMessagePending(FDCAN_HandleTypeDef *hfdcan, uint32_t TxBufferIndex);
2033 uint32_t HAL_FDCAN_GetRxFifoFillLevel(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo);
2034 uint32_t HAL_FDCAN_GetTxFifoFreeLevel(FDCAN_HandleTypeDef *hfdcan);
2035 uint32_t HAL_FDCAN_IsRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
2036 HAL_StatusTypeDef HAL_FDCAN_ExitRestrictedOperationMode(FDCAN_HandleTypeDef *hfdcan);
2037 /**
2038 * @}
2039 */
2040
2041 /** @addtogroup FDCAN_Exported_Functions_Group4
2042 * @{
2043 */
2044 /* TT Configuration and control functions**************************************/
2045 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigOperation(FDCAN_HandleTypeDef *hfdcan, FDCAN_TT_ConfigTypeDef *pTTParams);
2046 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigReferenceMessage(FDCAN_HandleTypeDef *hfdcan, uint32_t IdType, uint32_t Identifier, uint32_t Payload);
2047 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigTrigger(FDCAN_HandleTypeDef *hfdcan, FDCAN_TriggerTypeDef *sTriggerConfig);
2048 HAL_StatusTypeDef HAL_FDCAN_TT_SetGlobalTime(FDCAN_HandleTypeDef *hfdcan, uint32_t TimePreset);
2049 HAL_StatusTypeDef HAL_FDCAN_TT_SetClockSynchronization(FDCAN_HandleTypeDef *hfdcan, uint32_t NewTURNumerator);
2050 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigStopWatch(FDCAN_HandleTypeDef *hfdcan, uint32_t Source, uint32_t Polarity);
2051 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigRegisterTimeMark(FDCAN_HandleTypeDef *hfdcan, uint32_t TimeMarkSource, uint32_t TimeMarkValue, uint32_t RepeatFactor, uint32_t StartCycle);
2052 HAL_StatusTypeDef HAL_FDCAN_TT_EnableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2053 HAL_StatusTypeDef HAL_FDCAN_TT_DisableRegisterTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2054 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2055 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTriggerTimeMarkPulse(FDCAN_HandleTypeDef *hfdcan);
2056 HAL_StatusTypeDef HAL_FDCAN_TT_EnableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
2057 HAL_StatusTypeDef HAL_FDCAN_TT_DisableHardwareGapControl(FDCAN_HandleTypeDef *hfdcan);
2058 HAL_StatusTypeDef HAL_FDCAN_TT_EnableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
2059 HAL_StatusTypeDef HAL_FDCAN_TT_DisableTimeMarkGapControl(FDCAN_HandleTypeDef *hfdcan);
2060 HAL_StatusTypeDef HAL_FDCAN_TT_SetNextIsGap(FDCAN_HandleTypeDef *hfdcan);
2061 HAL_StatusTypeDef HAL_FDCAN_TT_SetEndOfGap(FDCAN_HandleTypeDef *hfdcan);
2062 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigExternalSyncPhase(FDCAN_HandleTypeDef *hfdcan, uint32_t TargetPhase);
2063 HAL_StatusTypeDef HAL_FDCAN_TT_EnableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
2064 HAL_StatusTypeDef HAL_FDCAN_TT_DisableExternalSynchronization(FDCAN_HandleTypeDef *hfdcan);
2065 HAL_StatusTypeDef HAL_FDCAN_TT_GetOperationStatus(FDCAN_HandleTypeDef *hfdcan, FDCAN_TTOperationStatusTypeDef *TTOpStatus);
2066 /**
2067 * @}
2068 */
2069
2070 /** @addtogroup FDCAN_Exported_Functions_Group5
2071 * @{
2072 */
2073 /* Interrupts management ******************************************************/
2074 HAL_StatusTypeDef HAL_FDCAN_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t ITList, uint32_t InterruptLine);
2075 HAL_StatusTypeDef HAL_FDCAN_TT_ConfigInterruptLines(FDCAN_HandleTypeDef *hfdcan, uint32_t TTITList, uint32_t InterruptLine);
2076 HAL_StatusTypeDef HAL_FDCAN_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveITs, uint32_t BufferIndexes);
2077 HAL_StatusTypeDef HAL_FDCAN_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveITs);
2078 HAL_StatusTypeDef HAL_FDCAN_TT_ActivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t ActiveTTITs);
2079 HAL_StatusTypeDef HAL_FDCAN_TT_DeactivateNotification(FDCAN_HandleTypeDef *hfdcan, uint32_t InactiveTTITs);
2080 void HAL_FDCAN_IRQHandler(FDCAN_HandleTypeDef *hfdcan);
2081 /**
2082 * @}
2083 */
2084
2085 /** @addtogroup FDCAN_Exported_Functions_Group6
2086 * @{
2087 */
2088 /* Callback functions *********************************************************/
2089 void HAL_FDCAN_ClockCalibrationCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ClkCalibrationITs);
2090 void HAL_FDCAN_TxEventFifoCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TxEventFifoITs);
2091 void HAL_FDCAN_RxFifo0Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo0ITs);
2092 void HAL_FDCAN_RxFifo1Callback(FDCAN_HandleTypeDef *hfdcan, uint32_t RxFifo1ITs);
2093 void HAL_FDCAN_TxFifoEmptyCallback(FDCAN_HandleTypeDef *hfdcan);
2094 void HAL_FDCAN_TxBufferCompleteCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
2095 void HAL_FDCAN_TxBufferAbortCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t BufferIndexes);
2096 void HAL_FDCAN_RxBufferNewMessageCallback(FDCAN_HandleTypeDef *hfdcan);
2097 void HAL_FDCAN_HighPriorityMessageCallback(FDCAN_HandleTypeDef *hfdcan);
2098 void HAL_FDCAN_TimestampWraparoundCallback(FDCAN_HandleTypeDef *hfdcan);
2099 void HAL_FDCAN_TimeoutOccurredCallback(FDCAN_HandleTypeDef *hfdcan);
2100 void HAL_FDCAN_ErrorCallback(FDCAN_HandleTypeDef *hfdcan);
2101 void HAL_FDCAN_ErrorStatusCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t ErrorStatusITs);
2102 void HAL_FDCAN_TT_ScheduleSyncCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTSchedSyncITs);
2103 void HAL_FDCAN_TT_TimeMarkCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTTimeMarkITs);
2104 void HAL_FDCAN_TT_StopWatchCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t SWTime, uint32_t SWCycleCount);
2105 void HAL_FDCAN_TT_GlobalTimeCallback(FDCAN_HandleTypeDef *hfdcan, uint32_t TTGlobTimeITs);
2106 /**
2107 * @}
2108 */
2109
2110 /** @addtogroup FDCAN_Exported_Functions_Group7
2111 * @{
2112 */
2113 /* Peripheral State functions *************************************************/
2114 uint32_t HAL_FDCAN_GetError(FDCAN_HandleTypeDef *hfdcan);
2115 HAL_FDCAN_StateTypeDef HAL_FDCAN_GetState(FDCAN_HandleTypeDef *hfdcan);
2116 /**
2117 * @}
2118 */
2119
2120 /**
2121 * @}
2122 */
2123
2124 /* Private types -------------------------------------------------------------*/
2125 /** @defgroup FDCAN_Private_Types FDCAN Private Types
2126 * @{
2127 */
2128
2129 /**
2130 * @}
2131 */
2132
2133 /* Private variables ---------------------------------------------------------*/
2134 /** @defgroup FDCAN_Private_Variables FDCAN Private Variables
2135 * @{
2136 */
2137
2138 /**
2139 * @}
2140 */
2141
2142 /* Private constants ---------------------------------------------------------*/
2143 /** @defgroup FDCAN_Private_Constants FDCAN Private Constants
2144 * @{
2145 */
2146
2147 /**
2148 * @}
2149 */
2150
2151 /* Private macros ------------------------------------------------------------*/
2152 /** @defgroup FDCAN_Private_Macros FDCAN Private Macros
2153 * @{
2154 */
2155 #define IS_FDCAN_FRAME_FORMAT(FORMAT) (((FORMAT) == FDCAN_FRAME_CLASSIC ) || \
2156 ((FORMAT) == FDCAN_FRAME_FD_NO_BRS) || \
2157 ((FORMAT) == FDCAN_FRAME_FD_BRS ))
2158 #define IS_FDCAN_MODE(MODE) (((MODE) == FDCAN_MODE_NORMAL ) || \
2159 ((MODE) == FDCAN_MODE_RESTRICTED_OPERATION) || \
2160 ((MODE) == FDCAN_MODE_BUS_MONITORING ) || \
2161 ((MODE) == FDCAN_MODE_INTERNAL_LOOPBACK ) || \
2162 ((MODE) == FDCAN_MODE_EXTERNAL_LOOPBACK ))
2163
2164 #define IS_FDCAN_CLOCK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_DISABLE) || \
2165 ((CALIBRATION) == FDCAN_CLOCK_CALIBRATION_ENABLE ))
2166
2167 #define IS_FDCAN_CKDIV(CKDIV) (((CKDIV) == FDCAN_CLOCK_DIV1 ) || \
2168 ((CKDIV) == FDCAN_CLOCK_DIV2 ) || \
2169 ((CKDIV) == FDCAN_CLOCK_DIV4 ) || \
2170 ((CKDIV) == FDCAN_CLOCK_DIV6 ) || \
2171 ((CKDIV) == FDCAN_CLOCK_DIV8 ) || \
2172 ((CKDIV) == FDCAN_CLOCK_DIV10) || \
2173 ((CKDIV) == FDCAN_CLOCK_DIV12) || \
2174 ((CKDIV) == FDCAN_CLOCK_DIV14) || \
2175 ((CKDIV) == FDCAN_CLOCK_DIV16) || \
2176 ((CKDIV) == FDCAN_CLOCK_DIV18) || \
2177 ((CKDIV) == FDCAN_CLOCK_DIV20) || \
2178 ((CKDIV) == FDCAN_CLOCK_DIV22) || \
2179 ((CKDIV) == FDCAN_CLOCK_DIV24) || \
2180 ((CKDIV) == FDCAN_CLOCK_DIV26) || \
2181 ((CKDIV) == FDCAN_CLOCK_DIV28) || \
2182 ((CKDIV) == FDCAN_CLOCK_DIV30))
2183 #define IS_FDCAN_NOMINAL_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 512U))
2184 #define IS_FDCAN_NOMINAL_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 128U))
2185 #define IS_FDCAN_NOMINAL_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 256U))
2186 #define IS_FDCAN_NOMINAL_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 128U))
2187 #define IS_FDCAN_DATA_PRESCALER(PRESCALER) (((PRESCALER) >= 1U) && ((PRESCALER) <= 32U))
2188 #define IS_FDCAN_DATA_SJW(SJW) (((SJW) >= 1U) && ((SJW) <= 16U))
2189 #define IS_FDCAN_DATA_TSEG1(TSEG1) (((TSEG1) >= 1U) && ((TSEG1) <= 32U))
2190 #define IS_FDCAN_DATA_TSEG2(TSEG2) (((TSEG2) >= 1U) && ((TSEG2) <= 16U))
2191 #define IS_FDCAN_MAX_VALUE(VALUE, MAX) ((VALUE) <= (MAX))
2192 #define IS_FDCAN_MIN_VALUE(VALUE, MIN) ((VALUE) >= (MIN))
2193 #define IS_FDCAN_DATA_SIZE(SIZE) (((SIZE) == FDCAN_DATA_BYTES_8 ) || \
2194 ((SIZE) == FDCAN_DATA_BYTES_12) || \
2195 ((SIZE) == FDCAN_DATA_BYTES_16) || \
2196 ((SIZE) == FDCAN_DATA_BYTES_20) || \
2197 ((SIZE) == FDCAN_DATA_BYTES_24) || \
2198 ((SIZE) == FDCAN_DATA_BYTES_32) || \
2199 ((SIZE) == FDCAN_DATA_BYTES_48) || \
2200 ((SIZE) == FDCAN_DATA_BYTES_64))
2201 #define IS_FDCAN_TX_FIFO_QUEUE_MODE(MODE) (((MODE) == FDCAN_TX_FIFO_OPERATION ) || \
2202 ((MODE) == FDCAN_TX_QUEUE_OPERATION))
2203 #define IS_FDCAN_ID_TYPE(ID_TYPE) (((ID_TYPE) == FDCAN_STANDARD_ID) || \
2204 ((ID_TYPE) == FDCAN_EXTENDED_ID))
2205 #define IS_FDCAN_FILTER_CFG(CONFIG) (((CONFIG) == FDCAN_FILTER_DISABLE ) || \
2206 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0 ) || \
2207 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1 ) || \
2208 ((CONFIG) == FDCAN_FILTER_REJECT ) || \
2209 ((CONFIG) == FDCAN_FILTER_HP ) || \
2210 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO0_HP) || \
2211 ((CONFIG) == FDCAN_FILTER_TO_RXFIFO1_HP) || \
2212 ((CONFIG) == FDCAN_FILTER_TO_RXBUFFER ))
2213 #define IS_FDCAN_TX_LOCATION(LOCATION) (((LOCATION) == FDCAN_TX_BUFFER0 ) || ((LOCATION) == FDCAN_TX_BUFFER1 ) || \
2214 ((LOCATION) == FDCAN_TX_BUFFER2 ) || ((LOCATION) == FDCAN_TX_BUFFER3 ) || \
2215 ((LOCATION) == FDCAN_TX_BUFFER4 ) || ((LOCATION) == FDCAN_TX_BUFFER5 ) || \
2216 ((LOCATION) == FDCAN_TX_BUFFER6 ) || ((LOCATION) == FDCAN_TX_BUFFER7 ) || \
2217 ((LOCATION) == FDCAN_TX_BUFFER8 ) || ((LOCATION) == FDCAN_TX_BUFFER9 ) || \
2218 ((LOCATION) == FDCAN_TX_BUFFER10) || ((LOCATION) == FDCAN_TX_BUFFER11) || \
2219 ((LOCATION) == FDCAN_TX_BUFFER12) || ((LOCATION) == FDCAN_TX_BUFFER13) || \
2220 ((LOCATION) == FDCAN_TX_BUFFER14) || ((LOCATION) == FDCAN_TX_BUFFER15) || \
2221 ((LOCATION) == FDCAN_TX_BUFFER16) || ((LOCATION) == FDCAN_TX_BUFFER17) || \
2222 ((LOCATION) == FDCAN_TX_BUFFER18) || ((LOCATION) == FDCAN_TX_BUFFER19) || \
2223 ((LOCATION) == FDCAN_TX_BUFFER20) || ((LOCATION) == FDCAN_TX_BUFFER21) || \
2224 ((LOCATION) == FDCAN_TX_BUFFER22) || ((LOCATION) == FDCAN_TX_BUFFER23) || \
2225 ((LOCATION) == FDCAN_TX_BUFFER24) || ((LOCATION) == FDCAN_TX_BUFFER25) || \
2226 ((LOCATION) == FDCAN_TX_BUFFER26) || ((LOCATION) == FDCAN_TX_BUFFER27) || \
2227 ((LOCATION) == FDCAN_TX_BUFFER28) || ((LOCATION) == FDCAN_TX_BUFFER29) || \
2228 ((LOCATION) == FDCAN_TX_BUFFER30) || ((LOCATION) == FDCAN_TX_BUFFER31))
2229 #define IS_FDCAN_RX_FIFO(FIFO) (((FIFO) == FDCAN_RX_FIFO0) || \
2230 ((FIFO) == FDCAN_RX_FIFO1))
2231 #define IS_FDCAN_RX_FIFO_MODE(MODE) (((MODE) == FDCAN_RX_FIFO_BLOCKING ) || \
2232 ((MODE) == FDCAN_RX_FIFO_OVERWRITE))
2233 #define IS_FDCAN_STD_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE) || \
2234 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2235 ((TYPE) == FDCAN_FILTER_MASK ))
2236 #define IS_FDCAN_EXT_FILTER_TYPE(TYPE) (((TYPE) == FDCAN_FILTER_RANGE ) || \
2237 ((TYPE) == FDCAN_FILTER_DUAL ) || \
2238 ((TYPE) == FDCAN_FILTER_MASK ) || \
2239 ((TYPE) == FDCAN_FILTER_RANGE_NO_EIDM))
2240 #define IS_FDCAN_FRAME_TYPE(TYPE) (((TYPE) == FDCAN_DATA_FRAME ) || \
2241 ((TYPE) == FDCAN_REMOTE_FRAME))
2242 #define IS_FDCAN_DLC(DLC) (((DLC) == FDCAN_DLC_BYTES_0 ) || \
2243 ((DLC) == FDCAN_DLC_BYTES_1 ) || \
2244 ((DLC) == FDCAN_DLC_BYTES_2 ) || \
2245 ((DLC) == FDCAN_DLC_BYTES_3 ) || \
2246 ((DLC) == FDCAN_DLC_BYTES_4 ) || \
2247 ((DLC) == FDCAN_DLC_BYTES_5 ) || \
2248 ((DLC) == FDCAN_DLC_BYTES_6 ) || \
2249 ((DLC) == FDCAN_DLC_BYTES_7 ) || \
2250 ((DLC) == FDCAN_DLC_BYTES_8 ) || \
2251 ((DLC) == FDCAN_DLC_BYTES_12) || \
2252 ((DLC) == FDCAN_DLC_BYTES_16) || \
2253 ((DLC) == FDCAN_DLC_BYTES_20) || \
2254 ((DLC) == FDCAN_DLC_BYTES_24) || \
2255 ((DLC) == FDCAN_DLC_BYTES_32) || \
2256 ((DLC) == FDCAN_DLC_BYTES_48) || \
2257 ((DLC) == FDCAN_DLC_BYTES_64))
2258 #define IS_FDCAN_ESI(ESI) (((ESI) == FDCAN_ESI_ACTIVE ) || \
2259 ((ESI) == FDCAN_ESI_PASSIVE))
2260 #define IS_FDCAN_BRS(BRS) (((BRS) == FDCAN_BRS_OFF) || \
2261 ((BRS) == FDCAN_BRS_ON ))
2262 #define IS_FDCAN_FDF(FDF) (((FDF) == FDCAN_CLASSIC_CAN) || \
2263 ((FDF) == FDCAN_FD_CAN ))
2264 #define IS_FDCAN_EFC(EFC) (((EFC) == FDCAN_NO_TX_EVENTS ) || \
2265 ((EFC) == FDCAN_STORE_TX_EVENTS))
2266 #define IS_FDCAN_IT(IT) (((IT) & ~(FDCAN_IR_MASK | CCU_IR_MASK)) == 0U)
2267 #define IS_FDCAN_TT_IT(IT) (((IT) & 0xFFF80000U) == 0U)
2268 #define IS_FDCAN_FIFO_WATERMARK(FIFO) (((FIFO) == FDCAN_CFG_TX_EVENT_FIFO) || \
2269 ((FIFO) == FDCAN_CFG_RX_FIFO0 ) || \
2270 ((FIFO) == FDCAN_CFG_RX_FIFO1 ))
2271 #define IS_FDCAN_NON_MATCHING(DESTINATION) (((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO0) || \
2272 ((DESTINATION) == FDCAN_ACCEPT_IN_RX_FIFO1) || \
2273 ((DESTINATION) == FDCAN_REJECT ))
2274 #define IS_FDCAN_REJECT_REMOTE(DESTINATION) (((DESTINATION) == FDCAN_FILTER_REMOTE) || \
2275 ((DESTINATION) == FDCAN_REJECT_REMOTE))
2276 #define IS_FDCAN_IT_LINE(IT_LINE) (((IT_LINE) == FDCAN_INTERRUPT_LINE0) || \
2277 ((IT_LINE) == FDCAN_INTERRUPT_LINE1))
2278 #define IS_FDCAN_TIMESTAMP(OPERATION) (((OPERATION) == FDCAN_TIMESTAMP_INTERNAL) || \
2279 ((OPERATION) == FDCAN_TIMESTAMP_EXTERNAL))
2280 #define IS_FDCAN_TIMESTAMP_PRESCALER(PRESCALER) (((PRESCALER) == FDCAN_TIMESTAMP_PRESC_1 ) || \
2281 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_2 ) || \
2282 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_3 ) || \
2283 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_4 ) || \
2284 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_5 ) || \
2285 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_6 ) || \
2286 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_7 ) || \
2287 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_8 ) || \
2288 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_9 ) || \
2289 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_10) || \
2290 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_11) || \
2291 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_12) || \
2292 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_13) || \
2293 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_14) || \
2294 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_15) || \
2295 ((PRESCALER) == FDCAN_TIMESTAMP_PRESC_16))
2296 #define IS_FDCAN_TIMEOUT(OPERATION) (((OPERATION) == FDCAN_TIMEOUT_CONTINUOUS ) || \
2297 ((OPERATION) == FDCAN_TIMEOUT_TX_EVENT_FIFO) || \
2298 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO0 ) || \
2299 ((OPERATION) == FDCAN_TIMEOUT_RX_FIFO1 ))
2300 #define IS_FDCAN_CALIBRATION_FIELD_LENGTH(LENGTH) (((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_32) || \
2301 ((LENGTH) == FDCAN_CALIB_FIELD_LENGTH_64))
2302 #define IS_FDCAN_CALIBRATION_COUNTER(COUNTER) (((COUNTER) == FDCAN_CALIB_TIME_QUANTA_COUNTER ) || \
2303 ((COUNTER) == FDCAN_CALIB_CLOCK_PERIOD_COUNTER) || \
2304 ((COUNTER) == FDCAN_CALIB_WATCHDOG_COUNTER ))
2305 #define IS_FDCAN_TT_REFERENCE_MESSAGE_PAYLOAD(PAYLOAD) (((PAYLOAD) == FDCAN_TT_REF_MESSAGE_NO_PAYLOAD ) || \
2306 ((PAYLOAD) == FDCAN_TT_REF_MESSAGE_ADD_PAYLOAD))
2307 #define IS_FDCAN_TT_REPEAT_FACTOR(FACTOR) (((FACTOR) == FDCAN_TT_REPEAT_EVERY_CYCLE ) || \
2308 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_2ND_CYCLE ) || \
2309 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_4TH_CYCLE ) || \
2310 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_8TH_CYCLE ) || \
2311 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_16TH_CYCLE) || \
2312 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_32ND_CYCLE) || \
2313 ((FACTOR) == FDCAN_TT_REPEAT_EVERY_64TH_CYCLE))
2314 #define IS_FDCAN_TT_TRIGGER_TYPE(TYPE) (((TYPE) == FDCAN_TT_TX_REF_TRIGGER ) || \
2315 ((TYPE) == FDCAN_TT_TX_REF_TRIGGER_GAP ) || \
2316 ((TYPE) == FDCAN_TT_TX_TRIGGER_SINGLE ) || \
2317 ((TYPE) == FDCAN_TT_TX_TRIGGER_CONTINUOUS ) || \
2318 ((TYPE) == FDCAN_TT_TX_TRIGGER_ARBITRATION) || \
2319 ((TYPE) == FDCAN_TT_TX_TRIGGER_MERGED ) || \
2320 ((TYPE) == FDCAN_TT_WATCH_TRIGGER ) || \
2321 ((TYPE) == FDCAN_TT_WATCH_TRIGGER_GAP ) || \
2322 ((TYPE) == FDCAN_TT_RX_TRIGGER ) || \
2323 ((TYPE) == FDCAN_TT_TIME_BASE_TRIGGER ) || \
2324 ((TYPE) == FDCAN_TT_END_OF_LIST ))
2325 #define IS_FDCAN_TT_TM_EVENT_INTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_INTERNAL_EVENT ) || \
2326 ((EVENT) == FDCAN_TT_TM_GEN_INTERNAL_EVENT))
2327 #define IS_FDCAN_TT_TM_EVENT_EXTERNAL(EVENT) (((EVENT) == FDCAN_TT_TM_NO_EXTERNAL_EVENT ) || \
2328 ((EVENT) == FDCAN_TT_TM_GEN_EXTERNAL_EVENT))
2329 #define IS_FDCAN_OPERATION_MODE(MODE) (((MODE) == FDCAN_TT_COMMUNICATION_LEVEL1 ) || \
2330 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL2 ) || \
2331 ((MODE) == FDCAN_TT_COMMUNICATION_LEVEL0 ))
2332 #define IS_FDCAN_TT_OPERATION(OPERATION) (((OPERATION) == FDCAN_STRICTLY_TT_OPERATION ) || \
2333 ((OPERATION) == FDCAN_EXT_EVT_SYNC_TT_OPERATION))
2334 #define IS_FDCAN_TT_TIME_MASTER(FUNCTION) (((FUNCTION) == FDCAN_TT_SLAVE ) || \
2335 ((FUNCTION) == FDCAN_TT_POTENTIAL_MASTER))
2336 #define IS_FDCAN_TT_EXTERNAL_CLK_SYNC(SYNC) (((SYNC) == FDCAN_TT_EXT_CLK_SYNC_DISABLE) || \
2337 ((SYNC) == FDCAN_TT_EXT_CLK_SYNC_ENABLE ))
2338 #define IS_FDCAN_TT_GLOBAL_TIME_FILTERING(FILTERING) (((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_DISABLE) || \
2339 ((FILTERING) == FDCAN_TT_GLOB_TIME_FILT_ENABLE ))
2340 #define IS_FDCAN_TT_AUTO_CLK_CALIBRATION(CALIBRATION) (((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_DISABLE) || \
2341 ((CALIBRATION) == FDCAN_TT_AUTO_CLK_CALIB_ENABLE ))
2342 #define IS_FDCAN_TT_EVENT_TRIGGER_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_EVT_TRIG_POL_RISING ) || \
2343 ((POLARITY) == FDCAN_TT_EVT_TRIG_POL_FALLING))
2344 #define IS_FDCAN_TT_BASIC_CYCLES_NUMBER(NUMBER) (((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_1 ) || \
2345 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_2 ) || \
2346 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_4 ) || \
2347 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_8 ) || \
2348 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_16) || \
2349 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_32) || \
2350 ((NUMBER) == FDCAN_TT_CYCLES_PER_MATRIX_64))
2351 #define IS_FDCAN_TT_CYCLE_START_SYNC(SYNC) (((SYNC) == FDCAN_TT_NO_SYNC_PULSE ) || \
2352 ((SYNC) == FDCAN_TT_SYNC_BASIC_CYCLE_START) || \
2353 ((SYNC) == FDCAN_TT_SYNC_MATRIX_START ))
2354 #define IS_FDCAN_TT_TX_ENABLE_WINDOW(NTU) (((NTU) >= 1U) && ((NTU) <= 16U))
2355 #define IS_FDCAN_TT_TUR_NUMERATOR(NUMERATOR) (((NUMERATOR) >= 0x10000U) && ((NUMERATOR) <= 0x1FFFFU))
2356 #define IS_FDCAN_TT_TUR_DENOMINATOR(DENOMINATOR) (((DENOMINATOR) >= 0x0001U) && ((DENOMINATOR) <= 0x3FFFU))
2357 #define IS_FDCAN_TT_TUR_LEVEL_1(NC,DC) ((NC) >= (4U * (DC)))
2358 #define IS_FDCAN_TT_TUR_LEVEL_0_2(NC,DC) ((NC) >= (8U * (DC)))
2359 #define IS_FDCAN_TT_STOP_WATCH_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_0) || \
2360 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_1) || \
2361 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_2) || \
2362 ((TRIGGER) == FDCAN_TT_STOP_WATCH_TRIGGER_3))
2363 #define IS_FDCAN_TT_EVENT_TRIGGER(TRIGGER) (((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_0) || \
2364 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_1) || \
2365 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_2) || \
2366 ((TRIGGER) == FDCAN_TT_EVENT_TRIGGER_3))
2367 #define IS_FDCAN_TT_TIME_PRESET(TIME) (((TIME) <= 0xFFFFU) && ((TIME) != 0x8000U))
2368 #define IS_FDCAN_TT_STOP_WATCH_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_STOP_WATCH_DISABLED ) || \
2369 ((SOURCE) == FDCAN_TT_STOP_WATCH_CYCLE_TIME ) || \
2370 ((SOURCE) == FDCAN_TT_STOP_WATCH_LOCAL_TIME ) || \
2371 ((SOURCE) == FDCAN_TT_STOP_WATCH_GLOBAL_TIME))
2372 #define IS_FDCAN_TT_STOP_WATCH_POLARITY(POLARITY) (((POLARITY) == FDCAN_TT_STOP_WATCH_RISING ) || \
2373 ((POLARITY) == FDCAN_TT_STOP_WATCH_FALLING))
2374 #define IS_FDCAN_TT_REGISTER_TIME_MARK_SOURCE(SOURCE) (((SOURCE) == FDCAN_TT_REG_TIMEMARK_DIABLED ) || \
2375 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_CYC_TIME) || \
2376 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_LOC_TIME) || \
2377 ((SOURCE) == FDCAN_TT_REG_TIMEMARK_GLO_TIME))
2378 /**
2379 * @}
2380 */
2381
2382 /* Private functions prototypes ----------------------------------------------*/
2383 /** @defgroup FDCAN_Private_Functions_Prototypes FDCAN Private Functions Prototypes
2384 * @{
2385 */
2386
2387 /**
2388 * @}
2389 */
2390
2391 /* Private functions ---------------------------------------------------------*/
2392 /** @defgroup FDCAN_Private_Functions FDCAN Private Functions
2393 * @{
2394 */
2395
2396 /**
2397 * @}
2398 */
2399 /**
2400 * @}
2401 */
2402
2403 /**
2404 * @}
2405 */
2406
2407 #ifdef __cplusplus
2408 }
2409 #endif
2410
2411 #endif /* STM32H7xx_HAL_FDCAN_H */
2412
2413
2414 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software