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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_bdma.h
blob72b747a64e31d3ba2fae0052f461e6ed0e20189d
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_bdma.h
4 * @author MCD Application Team
5 * @brief Header file of BDMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_BDMA_H
21 #define STM32H7xx_LL_BDMA_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29 #include "stm32h7xx_ll_dmamux.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (BDMA) || defined (BDMA1) || defined (BDMA2)
36
37 /** @defgroup BDMA_LL BDMA
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /** @defgroup BDMA_LL_Private_Variables BDMA Private Variables
44 * @{
45 */
46 /* Array used to get the BDMA channel register offset versus channel index LL_BDMA_CHANNEL_x */
47 static const uint8_t LL_BDMA_CH_OFFSET_TAB[] =
48 {
49 (uint8_t)(BDMA_Channel0_BASE - BDMA_BASE),
50 (uint8_t)(BDMA_Channel1_BASE - BDMA_BASE),
51 (uint8_t)(BDMA_Channel2_BASE - BDMA_BASE),
52 (uint8_t)(BDMA_Channel3_BASE - BDMA_BASE),
53 (uint8_t)(BDMA_Channel4_BASE - BDMA_BASE),
54 (uint8_t)(BDMA_Channel5_BASE - BDMA_BASE),
55 (uint8_t)(BDMA_Channel6_BASE - BDMA_BASE),
56 (uint8_t)(BDMA_Channel7_BASE - BDMA_BASE)
57 };
58 /**
59 * @}
60 */
61
62 /* Private constants ---------------------------------------------------------*/
63 /* Private macros ------------------------------------------------------------*/
64 /** @defgroup BDMA_LL_Private_Macros BDMA Private Macros
65 * @{
66 */
67 #if !defined(UNUSED)
68 #define UNUSED(x) ((void)(x))
69 #endif
70 /**
71 * @}
72 */
73 /* Exported types ------------------------------------------------------------*/
74 #if defined(USE_FULL_LL_DRIVER)
75 /** @defgroup BDMA_LL_ES_INIT BDMA Exported Init structure
76 * @{
77 */
78 typedef struct
79 {
80 uint32_t PeriphOrM2MSrcAddress; /*!< Specifies the peripheral base address for BDMA transfer
81 or as Source base address in case of memory to memory transfer direction.
82
83 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
84
85 uint32_t MemoryOrM2MDstAddress; /*!< Specifies the memory base address for DMA transfer
86 or as Destination base address in case of memory to memory transfer direction.
87
88 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
89
90 uint32_t Direction; /*!< Specifies if the data will be transferred from memory to peripheral,
91 from memory to memory or from peripheral to memory.
92 This parameter can be a value of @ref BDMA_LL_EC_DIRECTION
93
94 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataTransferDirection(). */
95
96 uint32_t Mode; /*!< Specifies the normal or circular operation mode.
97 This parameter can be a value of @ref BDMA_LL_EC_MODE
98 @note: The circular buffer mode cannot be used if the memory to memory
99 data transfer direction is configured on the selected Channel
100
101 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMode(). */
102
103 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
104 is incremented or not.
105 This parameter can be a value of @ref BDMA_LL_EC_PERIPH
106
107 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphIncMode(). */
108
109 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
110 is incremented or not.
111 This parameter can be a value of @ref BDMA_LL_EC_MEMORY
112
113 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemoryIncMode(). */
114
115 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
116 in case of memory to memory transfer direction.
117 This parameter can be a value of @ref BDMA_LL_EC_PDATAALIGN
118
119 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphSize(). */
120
121 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
122 in case of memory to memory transfer direction.
123 This parameter can be a value of @ref BDMA_LL_EC_MDATAALIGN
124
125 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetMemorySize(). */
126
127 uint32_t NbData; /*!< Specifies the number of data to transfer, in data unit.
128 The data unit is equal to the source buffer configuration set in PeripheralSize
129 or MemorySize parameters depending in the transfer direction.
130 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
131
132 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetDataLength(). */
133
134 uint32_t PeriphRequest; /*!< Specifies the peripheral request.
135 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
136
137 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetPeriphRequest(). */
138
139 uint32_t Priority; /*!< Specifies the channel priority level.
140 This parameter can be a value of @ref BDMA_LL_EC_PRIORITY
141
142 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetChannelPriorityLevel(). */
143
144 uint32_t DoubleBufferMode; /*!< Specifies the double buffer mode.
145 This parameter can be a value of @ref BDMA_LL_EC_DOUBLEBUFFER_MODE
146
147 This feature can be modified afterwards using unitary function @ref LL_BDMA_EnableDoubleBufferMode() & LL_BDMA_DisableDoubleBufferMode(). */
148
149 uint32_t TargetMemInDoubleBufferMode; /*!< Specifies the target memory in double buffer mode.
150 This parameter can be a value of @ref BDMA_LL_EC_CURRENTTARGETMEM
151
152 This feature can be modified afterwards using unitary function @ref LL_BDMA_SetCurrentTargetMem(). */
153 } LL_BDMA_InitTypeDef;
154 /**
155 * @}
156 */
157 #endif /* USE_FULL_LL_DRIVER */
158
159 /* Exported constants --------------------------------------------------------*/
160 /** @defgroup BDMA_LL_Exported_Constants BDMA Exported Constants
161 * @{
162 */
163 /** @defgroup BDMA_LL_EC_CLEAR_FLAG Clear Flags Defines
164 * @brief Flags defines which can be used with LL_BDMA_WriteReg function
165 * @{
166 */
167 #define LL_BDMA_IFCR_CGIF1 BDMA_IFCR_CGIF1 /*!< Channel 1 global flag */
168 #define LL_BDMA_IFCR_CTCIF1 BDMA_IFCR_CTCIF1 /*!< Channel 1 transfer complete flag */
169 #define LL_BDMA_IFCR_CHTIF1 BDMA_IFCR_CHTIF1 /*!< Channel 1 half transfer flag */
170 #define LL_BDMA_IFCR_CTEIF1 BDMA_IFCR_CTEIF1 /*!< Channel 1 transfer error flag */
171 #define LL_BDMA_IFCR_CGIF2 BDMA_IFCR_CGIF2 /*!< Channel 2 global flag */
172 #define LL_BDMA_IFCR_CTCIF2 BDMA_IFCR_CTCIF2 /*!< Channel 2 transfer complete flag */
173 #define LL_BDMA_IFCR_CHTIF2 BDMA_IFCR_CHTIF2 /*!< Channel 2 half transfer flag */
174 #define LL_BDMA_IFCR_CTEIF2 BDMA_IFCR_CTEIF2 /*!< Channel 2 transfer error flag */
175 #define LL_BDMA_IFCR_CGIF3 BDMA_IFCR_CGIF3 /*!< Channel 3 global flag */
176 #define LL_BDMA_IFCR_CTCIF3 BDMA_IFCR_CTCIF3 /*!< Channel 3 transfer complete flag */
177 #define LL_BDMA_IFCR_CHTIF3 BDMA_IFCR_CHTIF3 /*!< Channel 3 half transfer flag */
178 #define LL_BDMA_IFCR_CTEIF3 BDMA_IFCR_CTEIF3 /*!< Channel 3 transfer error flag */
179 #define LL_BDMA_IFCR_CGIF4 BDMA_IFCR_CGIF4 /*!< Channel 4 global flag */
180 #define LL_BDMA_IFCR_CTCIF4 BDMA_IFCR_CTCIF4 /*!< Channel 4 transfer complete flag */
181 #define LL_BDMA_IFCR_CHTIF4 BDMA_IFCR_CHTIF4 /*!< Channel 4 half transfer flag */
182 #define LL_BDMA_IFCR_CTEIF4 BDMA_IFCR_CTEIF4 /*!< Channel 4 transfer error flag */
183 #define LL_BDMA_IFCR_CGIF5 BDMA_IFCR_CGIF5 /*!< Channel 5 global flag */
184 #define LL_BDMA_IFCR_CTCIF5 BDMA_IFCR_CTCIF5 /*!< Channel 5 transfer complete flag */
185 #define LL_BDMA_IFCR_CHTIF5 BDMA_IFCR_CHTIF5 /*!< Channel 5 half transfer flag */
186 #define LL_BDMA_IFCR_CTEIF5 BDMA_IFCR_CTEIF5 /*!< Channel 5 transfer error flag */
187 #define LL_BDMA_IFCR_CGIF6 BDMA_IFCR_CGIF6 /*!< Channel 6 global flag */
188 #define LL_BDMA_IFCR_CTCIF6 BDMA_IFCR_CTCIF6 /*!< Channel 6 transfer complete flag */
189 #define LL_BDMA_IFCR_CHTIF6 BDMA_IFCR_CHTIF6 /*!< Channel 6 half transfer flag */
190 #define LL_BDMA_IFCR_CTEIF6 BDMA_IFCR_CTEIF6 /*!< Channel 6 transfer error flag */
191 #define LL_BDMA_IFCR_CGIF7 BDMA_IFCR_CGIF7 /*!< Channel 7 global flag */
192 #define LL_BDMA_IFCR_CTCIF7 BDMA_IFCR_CTCIF7 /*!< Channel 7 transfer complete flag */
193 #define LL_BDMA_IFCR_CHTIF7 BDMA_IFCR_CHTIF7 /*!< Channel 7 half transfer flag */
194 #define LL_BDMA_IFCR_CTEIF7 BDMA_IFCR_CTEIF7 /*!< Channel 7 transfer error flag */
195 /**
196 * @}
197 */
198
199 /** @defgroup BDMA_LL_EC_GET_FLAG Get Flags Defines
200 * @brief Flags defines which can be used with LL_BDMA_ReadReg function
201 * @{
202 */
203 #define LL_BDMA_ISR_GIF0 BDMA_ISR_GIF0 /*!< Channel 1 global flag */
204 #define LL_BDMA_ISR_TCIF0 BDMA_ISR_TCIF0 /*!< Channel 1 transfer complete flag */
205 #define LL_BDMA_ISR_HTIF0 BDMA_ISR_HTIF0 /*!< Channel 1 half transfer flag */
206 #define LL_BDMA_ISR_TEIF0 BDMA_ISR_TEIF0 /*!< Channel 1 transfer error flag */
207 #define LL_BDMA_ISR_GIF1 BDMA_ISR_GIF1 /*!< Channel 1 global flag */
208 #define LL_BDMA_ISR_TCIF1 BDMA_ISR_TCIF1 /*!< Channel 1 transfer complete flag */
209 #define LL_BDMA_ISR_HTIF1 BDMA_ISR_HTIF1 /*!< Channel 1 half transfer flag */
210 #define LL_BDMA_ISR_TEIF1 BDMA_ISR_TEIF1 /*!< Channel 1 transfer error flag */
211 #define LL_BDMA_ISR_GIF2 BDMA_ISR_GIF2 /*!< Channel 2 global flag */
212 #define LL_BDMA_ISR_TCIF2 BDMA_ISR_TCIF2 /*!< Channel 2 transfer complete flag */
213 #define LL_BDMA_ISR_HTIF2 BDMA_ISR_HTIF2 /*!< Channel 2 half transfer flag */
214 #define LL_BDMA_ISR_TEIF2 BDMA_ISR_TEIF2 /*!< Channel 2 transfer error flag */
215 #define LL_BDMA_ISR_GIF3 BDMA_ISR_GIF3 /*!< Channel 3 global flag */
216 #define LL_BDMA_ISR_TCIF3 BDMA_ISR_TCIF3 /*!< Channel 3 transfer complete flag */
217 #define LL_BDMA_ISR_HTIF3 BDMA_ISR_HTIF3 /*!< Channel 3 half transfer flag */
218 #define LL_BDMA_ISR_TEIF3 BDMA_ISR_TEIF3 /*!< Channel 3 transfer error flag */
219 #define LL_BDMA_ISR_GIF4 BDMA_ISR_GIF4 /*!< Channel 4 global flag */
220 #define LL_BDMA_ISR_TCIF4 BDMA_ISR_TCIF4 /*!< Channel 4 transfer complete flag */
221 #define LL_BDMA_ISR_HTIF4 BDMA_ISR_HTIF4 /*!< Channel 4 half transfer flag */
222 #define LL_BDMA_ISR_TEIF4 BDMA_ISR_TEIF4 /*!< Channel 4 transfer error flag */
223 #define LL_BDMA_ISR_GIF5 BDMA_ISR_GIF5 /*!< Channel 5 global flag */
224 #define LL_BDMA_ISR_TCIF5 BDMA_ISR_TCIF5 /*!< Channel 5 transfer complete flag */
225 #define LL_BDMA_ISR_HTIF5 BDMA_ISR_HTIF5 /*!< Channel 5 half transfer flag */
226 #define LL_BDMA_ISR_TEIF5 BDMA_ISR_TEIF5 /*!< Channel 5 transfer error flag */
227 #define LL_BDMA_ISR_GIF6 BDMA_ISR_GIF6 /*!< Channel 6 global flag */
228 #define LL_BDMA_ISR_TCIF6 BDMA_ISR_TCIF6 /*!< Channel 6 transfer complete flag */
229 #define LL_BDMA_ISR_HTIF6 BDMA_ISR_HTIF6 /*!< Channel 6 half transfer flag */
230 #define LL_BDMA_ISR_TEIF6 BDMA_ISR_TEIF6 /*!< Channel 6 transfer error flag */
231 #define LL_BDMA_ISR_GIF7 BDMA_ISR_GIF7 /*!< Channel 7 global flag */
232 #define LL_BDMA_ISR_TCIF7 BDMA_ISR_TCIF7 /*!< Channel 7 transfer complete flag */
233 #define LL_BDMA_ISR_HTIF7 BDMA_ISR_HTIF7 /*!< Channel 7 half transfer flag */
234 #define LL_BDMA_ISR_TEIF7 BDMA_ISR_TEIF7 /*!< Channel 7 transfer error flag */
235 /**
236 * @}
237 */
238
239 /** @defgroup BDMA_LL_EC_IT IT Defines
240 * @brief IT defines which can be used with LL_BDMA_ReadReg and LL_BDMA_WriteReg functions
241 * @{
242 */
243 #define LL_BDMA_CCR_TCIE BDMA_CCR_TCIE /*!< Transfer complete interrupt */
244 #define LL_BDMA_CCR_HTIE BDMA_CCR_HTIE /*!< Half Transfer interrupt */
245 #define LL_BDMA_CCR_TEIE BDMA_CCR_TEIE /*!< Transfer error interrupt */
246 /**
247 * @}
248 */
249
250 /** @defgroup BDMA_LL_EC_CHANNEL CHANNEL
251 * @{
252 */
253 #define LL_BDMA_CHANNEL_0 0x00000000U /*!< DMA Channel 0 */
254 #define LL_BDMA_CHANNEL_1 0x00000001U /*!< BDMA Channel 1 */
255 #define LL_BDMA_CHANNEL_2 0x00000002U /*!< BDMA Channel 2 */
256 #define LL_BDMA_CHANNEL_3 0x00000003U /*!< BDMA Channel 3 */
257 #define LL_BDMA_CHANNEL_4 0x00000004U /*!< BDMA Channel 4 */
258 #define LL_BDMA_CHANNEL_5 0x00000005U /*!< BDMA Channel 5 */
259 #define LL_BDMA_CHANNEL_6 0x00000006U /*!< BDMA Channel 6 */
260 #define LL_BDMA_CHANNEL_7 0x00000007U /*!< BDMA Channel 7 */
261 #if defined(USE_FULL_LL_DRIVER)
262 #define LL_BDMA_CHANNEL_ALL 0xFFFF0000U /*!< BDMA Channel all (used only for function @ref LL_BDMA_DeInit(). */
263 #endif /*USE_FULL_LL_DRIVER*/
264 /**
265 * @}
266 */
267
268 /** @defgroup BDMA_LL_EC_DIRECTION Transfer Direction
269 * @{
270 */
271 #define LL_BDMA_DIRECTION_PERIPH_TO_MEMORY 0x00000000U /*!< Peripheral to memory direction */
272 #define LL_BDMA_DIRECTION_MEMORY_TO_PERIPH BDMA_CCR_DIR /*!< Memory to peripheral direction */
273 #define LL_BDMA_DIRECTION_MEMORY_TO_MEMORY BDMA_CCR_MEM2MEM /*!< Memory to memory direction */
274 /**
275 * @}
276 */
277
278 /** @defgroup BDMA_LL_EC_MODE Transfer mode
279 * @{
280 */
281 #define LL_BDMA_MODE_NORMAL 0x00000000U /*!< Normal Mode */
282 #define LL_BDMA_MODE_CIRCULAR BDMA_CCR_CIRC /*!< Circular Mode */
283 /**
284 * @}
285 */
286
287 /** @defgroup BDMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
288 * @{
289 */
290 #define LL_BDMA_DOUBLEBUFFER_MODE_DISABLE 0x00000000U /*!< Disable double buffering mode */
291 #define LL_BDMA_DOUBLEBUFFER_MODE_ENABLE BDMA_CCR_DBM /*!< Enable double buffering mode */
292 /**
293 * @}
294 */
295
296 /** @defgroup BDMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
297 * @{
298 */
299 #define LL_BDMA_CURRENTTARGETMEM0 0x00000000U /*!< Set CurrentTarget Memory to Memory 0 */
300 #define LL_BDMA_CURRENTTARGETMEM1 BDMA_CCR_CT /*!< Set CurrentTarget Memory to Memory 1 */
301 /**
302 * @}
303 */
304
305 /** @defgroup BDMA_LL_EC_PERIPH Peripheral increment mode
306 * @{
307 */
308 #define LL_BDMA_PERIPH_INCREMENT BDMA_CCR_PINC /*!< Peripheral increment mode Enable */
309 #define LL_BDMA_PERIPH_NOINCREMENT 0x00000000U /*!< Peripheral increment mode Disable */
310 /**
311 * @}
312 */
313
314 /** @defgroup BDMA_LL_EC_MEMORY Memory increment mode
315 * @{
316 */
317 #define LL_BDMA_MEMORY_INCREMENT BDMA_CCR_MINC /*!< Memory increment mode Enable */
318 #define LL_BDMA_MEMORY_NOINCREMENT 0x00000000U /*!< Memory increment mode Disable */
319 /**
320 * @}
321 */
322
323 /** @defgroup BDMA_LL_EC_PDATAALIGN Peripheral data alignment
324 * @{
325 */
326 #define LL_BDMA_PDATAALIGN_BYTE 0x00000000U /*!< Peripheral data alignment : Byte */
327 #define LL_BDMA_PDATAALIGN_HALFWORD BDMA_CCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
328 #define LL_BDMA_PDATAALIGN_WORD BDMA_CCR_PSIZE_1 /*!< Peripheral data alignment : Word */
329 /**
330 * @}
331 */
332
333 /** @defgroup BDMA_LL_EC_MDATAALIGN Memory data alignment
334 * @{
335 */
336 #define LL_BDMA_MDATAALIGN_BYTE 0x00000000U /*!< Memory data alignment : Byte */
337 #define LL_BDMA_MDATAALIGN_HALFWORD BDMA_CCR_MSIZE_0 /*!< Memory data alignment : HalfWord */
338 #define LL_BDMA_MDATAALIGN_WORD BDMA_CCR_MSIZE_1 /*!< Memory data alignment : Word */
339 /**
340 * @}
341 */
342
343 /** @defgroup BDMA_LL_EC_PRIORITY Transfer Priority level
344 * @{
345 */
346 #define LL_BDMA_PRIORITY_LOW 0x00000000U /*!< Priority level : Low */
347 #define LL_BDMA_PRIORITY_MEDIUM BDMA_CCR_PL_0 /*!< Priority level : Medium */
348 #define LL_BDMA_PRIORITY_HIGH BDMA_CCR_PL_1 /*!< Priority level : High */
349 #define LL_BDMA_PRIORITY_VERYHIGH BDMA_CCR_PL /*!< Priority level : Very_High */
350 /**
351 * @}
352 */
353
354
355 /**
356 * @}
357 */
358 /* Exported macro ------------------------------------------------------------*/
359 /** @defgroup BDMA_LL_Exported_Macros BDMA Exported Macros
360 * @{
361 */
362
363 /** @defgroup BDMA_LL_EM_WRITE_READ Common Write and read registers macros
364 * @{
365 */
366 /**
367 * @brief Write a value in BDMA register
368 * @param __INSTANCE__ BDMA Instance
369 * @param __REG__ Register to be written
370 * @param __VALUE__ Value to be written in the register
371 * @retval None
372 */
373 #define LL_BDMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
374
375 /**
376 * @brief Read a value in BDMA register
377 * @param __INSTANCE__ BDMA Instance
378 * @param __REG__ Register to be read
379 * @retval Register value
380 */
381 #define LL_BDMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
382 /**
383 * @}
384 */
385
386 /** @defgroup BDMA_LL_EM_CONVERT_DMAxCHANNELy Convert BDMAxChannely
387 * @{
388 */
389 /**
390 * @brief Convert BDMAx_Channely into BDMAx
391 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
392 * @retval BDMAx
393 */
394 #if defined (BDMA1)
395 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) \
396 (((uint32_t)(__CHANNEL_INSTANCE__) < LL_BDMA_CHANNEL_0) ? BDMA1 : BDMA)
397 #else
398 #define __LL_BDMA_GET_INSTANCE(__CHANNEL_INSTANCE__) (BDMA)
399 #endif /* BDMA1 */
400
401 /**
402 * @brief Convert BDMAx_Channely into LL_BDMA_CHANNEL_y
403 * @param __CHANNEL_INSTANCE__ BDMAx_Channely
404 * @retval LL_BDMA_CHANNEL_y
405 */
406 #if defined (BDMA1)
407 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
408 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
409 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel0)) ? LL_BDMA_CHANNEL_0 : \
410 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
411 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel1)) ? LL_BDMA_CHANNEL_1 : \
412 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
413 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel2)) ? LL_BDMA_CHANNEL_2 : \
414 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
415 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel3)) ? LL_BDMA_CHANNEL_3 : \
416 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
417 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel4)) ? LL_BDMA_CHANNEL_4 : \
418 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
419 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel5)) ? LL_BDMA_CHANNEL_5 : \
420 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
421 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA1_Channel6)) ? LL_BDMA_CHANNEL_6 : \
422 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel7)) ? LL_BDMA_CHANNEL_7 : \
423 LL_BDMA_CHANNEL_7)
424 #else
425 #define __LL_BDMA_GET_CHANNEL(__CHANNEL_INSTANCE__) \
426 (((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel0)) ? LL_BDMA_CHANNEL_0 : \
427 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel1)) ? LL_BDMA_CHANNEL_1 : \
428 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel2)) ? LL_BDMA_CHANNEL_2 : \
429 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel3)) ? LL_BDMA_CHANNEL_3 : \
430 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel4)) ? LL_BDMA_CHANNEL_4 : \
431 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel5)) ? LL_BDMA_CHANNEL_5 : \
432 ((uint32_t)(__CHANNEL_INSTANCE__) == ((uint32_t)BDMA_Channel6)) ? LL_BDMA_CHANNEL_6 : \
433 LL_BDMA_CHANNEL_7)
434 #endif /* BDMA1 */
435
436 /**
437 * @brief Convert BDMA Instance BDMAx and LL_BDMA_CHANNEL_y into BDMAx_Channely
438 * @param __BDMA_INSTANCE__ BDMAx
439 * @param __CHANNEL__ LL_BDMA_CHANNEL_y
440 * @retval BDMAx_Channely
441 */
442 #if defined (BDMA1)
443 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
444 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
445 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA1_Channel0 : \
446 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
447 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA1_Channel1 : \
448 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
449 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA1_Channel2 : \
450 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
451 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA1_Channel3 : \
452 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
453 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA1_Channel4 : \
454 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
455 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA1_Channel5 : \
456 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
457 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA1)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA1_Channel6 : \
458 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_7))) ? BDMA_Channel7 : \
459 BDMA1_Channel7)
460 #else
461 #define __LL_BDMA_GET_CHANNEL_INSTANCE(__BDMA_INSTANCE__, __CHANNEL__) \
462 ((((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_0))) ? BDMA_Channel0 : \
463 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_1))) ? BDMA_Channel1 : \
464 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_2))) ? BDMA_Channel2 : \
465 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_3))) ? BDMA_Channel3 : \
466 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_4))) ? BDMA_Channel4 : \
467 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_5))) ? BDMA_Channel5 : \
468 (((uint32_t)(__BDMA_INSTANCE__) == ((uint32_t)BDMA)) && ((uint32_t)(__CHANNEL__) == ((uint32_t)LL_BDMA_CHANNEL_6))) ? BDMA_Channel6 : \
469 BDMA_Channel7)
470 #endif /* BDMA1 */
471 /**
472 * @}
473 */
474
475 /**
476 * @}
477 */
478
479 /* Exported functions --------------------------------------------------------*/
480 /** @defgroup BDMA_LL_Exported_Functions BDMA Exported Functions
481 * @{
482 */
483
484 /** @defgroup BDMA_LL_EF_Configuration Configuration
485 * @{
486 */
487 /**
488 * @brief Enable BDMA channel.
489 * @rmtoll CCR EN LL_BDMA_EnableChannel
490 * @param BDMAx BDMA Instance
491 * @param Channel This parameter can be one of the following values:
492 * @arg @ref LL_BDMA_CHANNEL_0
493 * @arg @ref LL_BDMA_CHANNEL_1
494 * @arg @ref LL_BDMA_CHANNEL_2
495 * @arg @ref LL_BDMA_CHANNEL_3
496 * @arg @ref LL_BDMA_CHANNEL_4
497 * @arg @ref LL_BDMA_CHANNEL_5
498 * @arg @ref LL_BDMA_CHANNEL_6
499 * @arg @ref LL_BDMA_CHANNEL_7
500 * @retval None
501 */
502 __STATIC_INLINE void LL_BDMA_EnableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel)
503 {
504 uint32_t bdma_base_addr = (uint32_t)BDMAx;
505
506 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
507 }
508
509 /**
510 * @brief Disable BDMA channel.
511 * @rmtoll CCR EN LL_BDMA_DisableChannel
512 * @param BDMAx BDMA Instance
513 * @param Channel This parameter can be one of the following values:
514 * @arg @ref LL_BDMA_CHANNEL_0
515 * @arg @ref LL_BDMA_CHANNEL_1
516 * @arg @ref LL_BDMA_CHANNEL_2
517 * @arg @ref LL_BDMA_CHANNEL_3
518 * @arg @ref LL_BDMA_CHANNEL_4
519 * @arg @ref LL_BDMA_CHANNEL_5
520 * @arg @ref LL_BDMA_CHANNEL_6
521 * @arg @ref LL_BDMA_CHANNEL_7
522 * @retval None
523 */
524 __STATIC_INLINE void LL_BDMA_DisableChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel)
525 {
526 uint32_t bdma_base_addr = (uint32_t)BDMAx;
527
528 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN);
529 }
530
531 /**
532 * @brief Check if BDMA channel is enabled or disabled.
533 * @rmtoll CCR EN LL_BDMA_IsEnabledChannel
534 * @param BDMAx BDMA Instance
535 * @param Channel This parameter can be one of the following values:
536 * @arg @ref LL_BDMA_CHANNEL_0
537 * @arg @ref LL_BDMA_CHANNEL_1
538 * @arg @ref LL_BDMA_CHANNEL_2
539 * @arg @ref LL_BDMA_CHANNEL_3
540 * @arg @ref LL_BDMA_CHANNEL_4
541 * @arg @ref LL_BDMA_CHANNEL_5
542 * @arg @ref LL_BDMA_CHANNEL_6
543 * @arg @ref LL_BDMA_CHANNEL_7
544 * @retval State of bit (1 or 0).
545 */
546 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledChannel(const BDMA_TypeDef *BDMAx, uint32_t Channel)
547 {
548 uint32_t bdma_base_addr = (uint32_t)BDMAx;
549
550 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_EN) == (BDMA_CCR_EN)) ? 1UL : 0UL);
551 }
552
553 /**
554 * @brief Configure all parameters link to BDMA transfer.
555 * @rmtoll CCR DIR LL_BDMA_ConfigTransfer\n
556 * CCR MEM2MEM LL_BDMA_ConfigTransfer\n
557 * CCR CIRC LL_BDMA_ConfigTransfer\n
558 * CCR PINC LL_BDMA_ConfigTransfer\n
559 * CCR MINC LL_BDMA_ConfigTransfer\n
560 * CCR PSIZE LL_BDMA_ConfigTransfer\n
561 * CCR MSIZE LL_BDMA_ConfigTransfer\n
562 * CCR PL LL_BDMA_ConfigTransfer\n
563 * CCR DBM LL_BDMA_ConfigTransfer\n
564 * CCR CT LL_BDMA_ConfigTransfer
565 * @param BDMAx BDMA Instance
566 * @param Channel This parameter can be one of the following values:
567 * @arg @ref LL_BDMA_CHANNEL_0
568 * @arg @ref LL_BDMA_CHANNEL_1
569 * @arg @ref LL_BDMA_CHANNEL_2
570 * @arg @ref LL_BDMA_CHANNEL_3
571 * @arg @ref LL_BDMA_CHANNEL_4
572 * @arg @ref LL_BDMA_CHANNEL_5
573 * @arg @ref LL_BDMA_CHANNEL_6
574 * @arg @ref LL_BDMA_CHANNEL_7
575 * @param Configuration This parameter must be a combination of all the following values:
576 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
577 * @arg @ref LL_BDMA_MODE_NORMAL or @ref LL_BDMA_MODE_CIRCULAR
578 * @arg @ref LL_BDMA_PERIPH_INCREMENT or @ref LL_BDMA_PERIPH_NOINCREMENT
579 * @arg @ref LL_BDMA_MEMORY_INCREMENT or @ref LL_BDMA_MEMORY_NOINCREMENT
580 * @arg @ref LL_BDMA_PDATAALIGN_BYTE or @ref LL_BDMA_PDATAALIGN_HALFWORD or @ref LL_BDMA_PDATAALIGN_WORD
581 * @arg @ref LL_BDMA_MDATAALIGN_BYTE or @ref LL_BDMA_MDATAALIGN_HALFWORD or @ref LL_BDMA_MDATAALIGN_WORD
582 * @arg @ref LL_BDMA_PRIORITY_LOW or @ref LL_BDMA_PRIORITY_MEDIUM or @ref LL_BDMA_PRIORITY_HIGH or @ref LL_BDMA_PRIORITY_VERYHIGH
583 * @arg @ref LL_BDMA_DOUBLEBUFFER_MODE_DISABLE or @ref LL_BDMA_DOUBLEBUFFER_MODE_ENABLE
584 * @arg @ref LL_BDMA_CURRENTTARGETMEM0 or @ref LL_BDMA_CURRENTTARGETMEM1
585 * @retval None
586 */
587 __STATIC_INLINE void LL_BDMA_ConfigTransfer(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Configuration)
588 {
589 uint32_t bdma_base_addr = (uint32_t)BDMAx;
590
591 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
592 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM | BDMA_CCR_CIRC | BDMA_CCR_PINC | BDMA_CCR_MINC | BDMA_CCR_PSIZE | BDMA_CCR_MSIZE | BDMA_CCR_PL | \
593 BDMA_CCR_DBM | BDMA_CCR_CT, Configuration);
594 }
595
596 /**
597 * @brief Set Data transfer direction (read from peripheral or from memory).
598 * @rmtoll CCR DIR LL_BDMA_SetDataTransferDirection\n
599 * CCR MEM2MEM LL_BDMA_SetDataTransferDirection
600 * @param BDMAx BDMA Instance
601 * @param Channel This parameter can be one of the following values:
602 * @arg @ref LL_BDMA_CHANNEL_0
603 * @arg @ref LL_BDMA_CHANNEL_1
604 * @arg @ref LL_BDMA_CHANNEL_2
605 * @arg @ref LL_BDMA_CHANNEL_3
606 * @arg @ref LL_BDMA_CHANNEL_4
607 * @arg @ref LL_BDMA_CHANNEL_5
608 * @arg @ref LL_BDMA_CHANNEL_6
609 * @arg @ref LL_BDMA_CHANNEL_7
610 * @param Direction This parameter can be one of the following values:
611 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
612 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
613 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
614 * @retval None
615 */
616 __STATIC_INLINE void LL_BDMA_SetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Direction)
617 {
618 uint32_t bdma_base_addr = (uint32_t)BDMAx;
619
620 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
621 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM, Direction);
622 }
623
624 /**
625 * @brief Get Data transfer direction (read from peripheral or from memory).
626 * @rmtoll CCR DIR LL_BDMA_GetDataTransferDirection\n
627 * CCR MEM2MEM LL_BDMA_GetDataTransferDirection
628 * @param BDMAx BDMA Instance
629 * @param Channel This parameter can be one of the following values:
630 * @arg @ref LL_BDMA_CHANNEL_0
631 * @arg @ref LL_BDMA_CHANNEL_1
632 * @arg @ref LL_BDMA_CHANNEL_2
633 * @arg @ref LL_BDMA_CHANNEL_3
634 * @arg @ref LL_BDMA_CHANNEL_4
635 * @arg @ref LL_BDMA_CHANNEL_5
636 * @arg @ref LL_BDMA_CHANNEL_6
637 * @arg @ref LL_BDMA_CHANNEL_7
638 * @retval Returned value can be one of the following values:
639 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
640 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
641 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
642 */
643 __STATIC_INLINE uint32_t LL_BDMA_GetDataTransferDirection(const BDMA_TypeDef *BDMAx, uint32_t Channel)
644 {
645 uint32_t bdma_base_addr = (uint32_t)BDMAx;
646
647 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
648 BDMA_CCR_DIR | BDMA_CCR_MEM2MEM));
649 }
650
651 /**
652 * @brief Set BDMA mode circular or normal.
653 * @note The circular buffer mode cannot be used if the memory-to-memory
654 * data transfer is configured on the selected Channel.
655 * @rmtoll CCR CIRC LL_BDMA_SetMode
656 * @param BDMAx BDMA Instance
657 * @param Channel This parameter can be one of the following values:
658 * @arg @ref LL_BDMA_CHANNEL_0
659 * @arg @ref LL_BDMA_CHANNEL_1
660 * @arg @ref LL_BDMA_CHANNEL_2
661 * @arg @ref LL_BDMA_CHANNEL_3
662 * @arg @ref LL_BDMA_CHANNEL_4
663 * @arg @ref LL_BDMA_CHANNEL_5
664 * @arg @ref LL_BDMA_CHANNEL_6
665 * @arg @ref LL_BDMA_CHANNEL_7
666 * @param Mode This parameter can be one of the following values:
667 * @arg @ref LL_BDMA_MODE_NORMAL
668 * @arg @ref LL_BDMA_MODE_CIRCULAR
669 * @retval None
670 */
671 __STATIC_INLINE void LL_BDMA_SetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Mode)
672 {
673 uint32_t bdma_base_addr = (uint32_t)BDMAx;
674
675 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CIRC,
676 Mode);
677 }
678
679 /**
680 * @brief Get BDMA mode circular or normal.
681 * @rmtoll CCR CIRC LL_BDMA_GetMode
682 * @param BDMAx BDMA Instance
683 * @param Channel This parameter can be one of the following values:
684 * @arg @ref LL_BDMA_CHANNEL_0
685 * @arg @ref LL_BDMA_CHANNEL_1
686 * @arg @ref LL_BDMA_CHANNEL_2
687 * @arg @ref LL_BDMA_CHANNEL_3
688 * @arg @ref LL_BDMA_CHANNEL_4
689 * @arg @ref LL_BDMA_CHANNEL_5
690 * @arg @ref LL_BDMA_CHANNEL_6
691 * @arg @ref LL_BDMA_CHANNEL_7
692 * @retval Returned value can be one of the following values:
693 * @arg @ref LL_BDMA_MODE_NORMAL
694 * @arg @ref LL_BDMA_MODE_CIRCULAR
695 */
696 __STATIC_INLINE uint32_t LL_BDMA_GetMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
697 {
698 uint32_t bdma_base_addr = (uint32_t)BDMAx;
699
700 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
701 BDMA_CCR_CIRC));
702 }
703
704 /**
705 * @brief Set Peripheral increment mode.
706 * @rmtoll CCR PINC LL_BDMA_SetPeriphIncMode
707 * @param BDMAx BDMA Instance
708 * @param Channel This parameter can be one of the following values:
709 * @arg @ref LL_BDMA_CHANNEL_0
710 * @arg @ref LL_BDMA_CHANNEL_1
711 * @arg @ref LL_BDMA_CHANNEL_2
712 * @arg @ref LL_BDMA_CHANNEL_3
713 * @arg @ref LL_BDMA_CHANNEL_4
714 * @arg @ref LL_BDMA_CHANNEL_5
715 * @arg @ref LL_BDMA_CHANNEL_6
716 * @arg @ref LL_BDMA_CHANNEL_7
717 * @param PeriphOrM2MSrcIncMode This parameter can be one of the following values:
718 * @arg @ref LL_BDMA_PERIPH_INCREMENT
719 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
720 * @retval None
721 */
722 __STATIC_INLINE void LL_BDMA_SetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcIncMode)
723 {
724 uint32_t bdma_base_addr = (uint32_t)BDMAx;
725
726 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PINC,
727 PeriphOrM2MSrcIncMode);
728 }
729
730 /**
731 * @brief Get Peripheral increment mode.
732 * @rmtoll CCR PINC LL_BDMA_GetPeriphIncMode
733 * @param BDMAx BDMA Instance
734 * @param Channel This parameter can be one of the following values:
735 * @arg @ref LL_BDMA_CHANNEL_0
736 * @arg @ref LL_BDMA_CHANNEL_1
737 * @arg @ref LL_BDMA_CHANNEL_2
738 * @arg @ref LL_BDMA_CHANNEL_3
739 * @arg @ref LL_BDMA_CHANNEL_4
740 * @arg @ref LL_BDMA_CHANNEL_5
741 * @arg @ref LL_BDMA_CHANNEL_6
742 * @arg @ref LL_BDMA_CHANNEL_7
743 * @retval Returned value can be one of the following values:
744 * @arg @ref LL_BDMA_PERIPH_INCREMENT
745 * @arg @ref LL_BDMA_PERIPH_NOINCREMENT
746 */
747 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
748 {
749 uint32_t bdma_base_addr = (uint32_t)BDMAx;
750
751 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
752 BDMA_CCR_PINC));
753 }
754
755 /**
756 * @brief Set Memory increment mode.
757 * @rmtoll CCR MINC LL_BDMA_SetMemoryIncMode
758 * @param BDMAx BDMA Instance
759 * @param Channel This parameter can be one of the following values:
760 * @arg @ref LL_BDMA_CHANNEL_0
761 * @arg @ref LL_BDMA_CHANNEL_1
762 * @arg @ref LL_BDMA_CHANNEL_2
763 * @arg @ref LL_BDMA_CHANNEL_3
764 * @arg @ref LL_BDMA_CHANNEL_4
765 * @arg @ref LL_BDMA_CHANNEL_5
766 * @arg @ref LL_BDMA_CHANNEL_6
767 * @arg @ref LL_BDMA_CHANNEL_7
768 * @param MemoryOrM2MDstIncMode This parameter can be one of the following values:
769 * @arg @ref LL_BDMA_MEMORY_INCREMENT
770 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
771 * @retval None
772 */
773 __STATIC_INLINE void LL_BDMA_SetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstIncMode)
774 {
775 uint32_t bdma_base_addr = (uint32_t)BDMAx;
776
777 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MINC,
778 MemoryOrM2MDstIncMode);
779 }
780
781 /**
782 * @brief Get Memory increment mode.
783 * @rmtoll CCR MINC LL_BDMA_GetMemoryIncMode
784 * @param BDMAx BDMA Instance
785 * @param Channel This parameter can be one of the following values:
786 * @arg @ref LL_BDMA_CHANNEL_0
787 * @arg @ref LL_BDMA_CHANNEL_1
788 * @arg @ref LL_BDMA_CHANNEL_2
789 * @arg @ref LL_BDMA_CHANNEL_3
790 * @arg @ref LL_BDMA_CHANNEL_4
791 * @arg @ref LL_BDMA_CHANNEL_5
792 * @arg @ref LL_BDMA_CHANNEL_6
793 * @arg @ref LL_BDMA_CHANNEL_7
794 * @retval Returned value can be one of the following values:
795 * @arg @ref LL_BDMA_MEMORY_INCREMENT
796 * @arg @ref LL_BDMA_MEMORY_NOINCREMENT
797 */
798 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryIncMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
799 {
800 uint32_t bdma_base_addr = (uint32_t)BDMAx;
801
802 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
803 BDMA_CCR_MINC));
804 }
805
806 /**
807 * @brief Set Peripheral size.
808 * @rmtoll CCR PSIZE LL_BDMA_SetPeriphSize
809 * @param BDMAx BDMA Instance
810 * @param Channel This parameter can be one of the following values:
811 * @arg @ref LL_BDMA_CHANNEL_0
812 * @arg @ref LL_BDMA_CHANNEL_1
813 * @arg @ref LL_BDMA_CHANNEL_2
814 * @arg @ref LL_BDMA_CHANNEL_3
815 * @arg @ref LL_BDMA_CHANNEL_4
816 * @arg @ref LL_BDMA_CHANNEL_5
817 * @arg @ref LL_BDMA_CHANNEL_6
818 * @arg @ref LL_BDMA_CHANNEL_7
819 * @param PeriphOrM2MSrcDataSize This parameter can be one of the following values:
820 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
821 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
822 * @arg @ref LL_BDMA_PDATAALIGN_WORD
823 * @retval None
824 */
825 __STATIC_INLINE void LL_BDMA_SetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphOrM2MSrcDataSize)
826 {
827 uint32_t bdma_base_addr = (uint32_t)BDMAx;
828
829 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PSIZE,
830 PeriphOrM2MSrcDataSize);
831 }
832
833 /**
834 * @brief Get Peripheral size.
835 * @rmtoll CCR PSIZE LL_BDMA_GetPeriphSize
836 * @param BDMAx BDMA Instance
837 * @param Channel This parameter can be one of the following values:
838 * @arg @ref LL_BDMA_CHANNEL_0
839 * @arg @ref LL_BDMA_CHANNEL_1
840 * @arg @ref LL_BDMA_CHANNEL_2
841 * @arg @ref LL_BDMA_CHANNEL_3
842 * @arg @ref LL_BDMA_CHANNEL_4
843 * @arg @ref LL_BDMA_CHANNEL_5
844 * @arg @ref LL_BDMA_CHANNEL_6
845 * @arg @ref LL_BDMA_CHANNEL_7
846 * @retval Returned value can be one of the following values:
847 * @arg @ref LL_BDMA_PDATAALIGN_BYTE
848 * @arg @ref LL_BDMA_PDATAALIGN_HALFWORD
849 * @arg @ref LL_BDMA_PDATAALIGN_WORD
850 */
851 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphSize(const BDMA_TypeDef *BDMAx, uint32_t Channel)
852 {
853 uint32_t bdma_base_addr = (uint32_t)BDMAx;
854
855 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
856 BDMA_CCR_PSIZE));
857 }
858
859 /**
860 * @brief Set Memory size.
861 * @rmtoll CCR MSIZE LL_BDMA_SetMemorySize
862 * @param BDMAx BDMA Instance
863 * @param Channel This parameter can be one of the following values:
864 * @arg @ref LL_BDMA_CHANNEL_0
865 * @arg @ref LL_BDMA_CHANNEL_1
866 * @arg @ref LL_BDMA_CHANNEL_2
867 * @arg @ref LL_BDMA_CHANNEL_3
868 * @arg @ref LL_BDMA_CHANNEL_4
869 * @arg @ref LL_BDMA_CHANNEL_5
870 * @arg @ref LL_BDMA_CHANNEL_6
871 * @arg @ref LL_BDMA_CHANNEL_7
872 * @param MemoryOrM2MDstDataSize This parameter can be one of the following values:
873 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
874 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
875 * @arg @ref LL_BDMA_MDATAALIGN_WORD
876 * @retval None
877 */
878 __STATIC_INLINE void LL_BDMA_SetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryOrM2MDstDataSize)
879 {
880 uint32_t bdma_base_addr = (uint32_t)BDMAx;
881
882 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_MSIZE,
883 MemoryOrM2MDstDataSize);
884 }
885
886 /**
887 * @brief Get Memory size.
888 * @rmtoll CCR MSIZE LL_BDMA_GetMemorySize
889 * @param BDMAx BDMA Instance
890 * @param Channel This parameter can be one of the following values:
891 * @arg @ref LL_BDMA_CHANNEL_0
892 * @arg @ref LL_BDMA_CHANNEL_1
893 * @arg @ref LL_BDMA_CHANNEL_2
894 * @arg @ref LL_BDMA_CHANNEL_3
895 * @arg @ref LL_BDMA_CHANNEL_4
896 * @arg @ref LL_BDMA_CHANNEL_5
897 * @arg @ref LL_BDMA_CHANNEL_6
898 * @arg @ref LL_BDMA_CHANNEL_7
899 * @retval Returned value can be one of the following values:
900 * @arg @ref LL_BDMA_MDATAALIGN_BYTE
901 * @arg @ref LL_BDMA_MDATAALIGN_HALFWORD
902 * @arg @ref LL_BDMA_MDATAALIGN_WORD
903 */
904 __STATIC_INLINE uint32_t LL_BDMA_GetMemorySize(const BDMA_TypeDef *BDMAx, uint32_t Channel)
905 {
906 uint32_t bdma_base_addr = (uint32_t)BDMAx;
907
908 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
909 BDMA_CCR_MSIZE));
910 }
911
912 /**
913 * @brief Set Channel priority level.
914 * @rmtoll CCR PL LL_BDMA_SetChannelPriorityLevel
915 * @param BDMAx BDMA Instance
916 * @param Channel This parameter can be one of the following values:
917 * @arg @ref LL_BDMA_CHANNEL_0
918 * @arg @ref LL_BDMA_CHANNEL_1
919 * @arg @ref LL_BDMA_CHANNEL_2
920 * @arg @ref LL_BDMA_CHANNEL_3
921 * @arg @ref LL_BDMA_CHANNEL_4
922 * @arg @ref LL_BDMA_CHANNEL_5
923 * @arg @ref LL_BDMA_CHANNEL_6
924 * @arg @ref LL_BDMA_CHANNEL_7
925 * @param Priority This parameter can be one of the following values:
926 * @arg @ref LL_BDMA_PRIORITY_LOW
927 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
928 * @arg @ref LL_BDMA_PRIORITY_HIGH
929 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
930 * @retval None
931 */
932 __STATIC_INLINE void LL_BDMA_SetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Priority)
933 {
934 uint32_t bdma_base_addr = (uint32_t)BDMAx;
935
936 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_PL,
937 Priority);
938 }
939
940 /**
941 * @brief Get Channel priority level.
942 * @rmtoll CCR PL LL_BDMA_GetChannelPriorityLevel
943 * @param BDMAx BDMA Instance
944 * @param Channel This parameter can be one of the following values:
945 * @arg @ref LL_BDMA_CHANNEL_0
946 * @arg @ref LL_BDMA_CHANNEL_1
947 * @arg @ref LL_BDMA_CHANNEL_2
948 * @arg @ref LL_BDMA_CHANNEL_3
949 * @arg @ref LL_BDMA_CHANNEL_4
950 * @arg @ref LL_BDMA_CHANNEL_5
951 * @arg @ref LL_BDMA_CHANNEL_6
952 * @arg @ref LL_BDMA_CHANNEL_7
953 * @retval Returned value can be one of the following values:
954 * @arg @ref LL_BDMA_PRIORITY_LOW
955 * @arg @ref LL_BDMA_PRIORITY_MEDIUM
956 * @arg @ref LL_BDMA_PRIORITY_HIGH
957 * @arg @ref LL_BDMA_PRIORITY_VERYHIGH
958 */
959 __STATIC_INLINE uint32_t LL_BDMA_GetChannelPriorityLevel(const BDMA_TypeDef *BDMAx, uint32_t Channel)
960 {
961 uint32_t bdma_base_addr = (uint32_t)BDMAx;
962
963 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR,
964 BDMA_CCR_PL));
965 }
966
967 /**
968 * @brief Set Number of data to transfer.
969 * @note This action has no effect if
970 * channel is enabled.
971 * @rmtoll CNDTR NDT LL_BDMA_SetDataLength
972 * @param BDMAx BDMA Instance
973 * @param Channel This parameter can be one of the following values:
974 * @arg @ref LL_BDMA_CHANNEL_0
975 * @arg @ref LL_BDMA_CHANNEL_1
976 * @arg @ref LL_BDMA_CHANNEL_2
977 * @arg @ref LL_BDMA_CHANNEL_3
978 * @arg @ref LL_BDMA_CHANNEL_4
979 * @arg @ref LL_BDMA_CHANNEL_5
980 * @arg @ref LL_BDMA_CHANNEL_6
981 * @arg @ref LL_BDMA_CHANNEL_7
982 * @param NbData Between Min_Data = 0 and Max_Data = 0x0000FFFF
983 * @retval None
984 */
985 __STATIC_INLINE void LL_BDMA_SetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t NbData)
986 {
987 uint32_t bdma_base_addr = (uint32_t)BDMAx;
988
989 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
990 BDMA_CNDTR_NDT, NbData);
991 }
992
993 /**
994 * @brief Get Number of data to transfer.
995 * @note Once the channel is enabled, the return value indicate the
996 * remaining bytes to be transmitted.
997 * @rmtoll CNDTR NDT LL_BDMA_GetDataLength
998 * @param BDMAx BDMA Instance
999 * @param Channel This parameter can be one of the following values:
1000 * @arg @ref LL_BDMA_CHANNEL_0
1001 * @arg @ref LL_BDMA_CHANNEL_1
1002 * @arg @ref LL_BDMA_CHANNEL_2
1003 * @arg @ref LL_BDMA_CHANNEL_3
1004 * @arg @ref LL_BDMA_CHANNEL_4
1005 * @arg @ref LL_BDMA_CHANNEL_5
1006 * @arg @ref LL_BDMA_CHANNEL_6
1007 * @arg @ref LL_BDMA_CHANNEL_7
1008 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1009 */
1010 __STATIC_INLINE uint32_t LL_BDMA_GetDataLength(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1011 {
1012 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1013
1014 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CNDTR,
1015 BDMA_CNDTR_NDT));
1016 }
1017
1018 /**
1019 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1020 * @rmtoll CR CT LL_BDMA_SetCurrentTargetMem
1021 * @param BDMAx BDMAx Instance
1022 * @param Channel This parameter can be one of the following values:
1023 * @arg @ref LL_BDMA_CHANNEL_0
1024 * @arg @ref LL_BDMA_CHANNEL_1
1025 * @arg @ref LL_BDMA_CHANNEL_2
1026 * @arg @ref LL_BDMA_CHANNEL_3
1027 * @arg @ref LL_BDMA_CHANNEL_4
1028 * @arg @ref LL_BDMA_CHANNEL_5
1029 * @arg @ref LL_BDMA_CHANNEL_6
1030 * @arg @ref LL_BDMA_CHANNEL_7
1031 * @param CurrentMemory This parameter can be one of the following values:
1032 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1033 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1034 * @retval None
1035 */
1036 __STATIC_INLINE void LL_BDMA_SetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t CurrentMemory)
1037 {
1038 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1039
1040 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT, CurrentMemory);
1041 }
1042
1043 /**
1044 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1045 * @rmtoll CR CT LL_BDMA_GetCurrentTargetMem
1046 * @param BDMAx BDMAx Instance
1047 * @param Channel This parameter can be one of the following values:
1048 * @arg @ref LL_BDMA_CHANNEL_0
1049 * @arg @ref LL_BDMA_CHANNEL_1
1050 * @arg @ref LL_BDMA_CHANNEL_2
1051 * @arg @ref LL_BDMA_CHANNEL_3
1052 * @arg @ref LL_BDMA_CHANNEL_4
1053 * @arg @ref LL_BDMA_CHANNEL_5
1054 * @arg @ref LL_BDMA_CHANNEL_6
1055 * @arg @ref LL_BDMA_CHANNEL_7
1056 * @retval Returned value can be one of the following values:
1057 * @arg @ref LL_BDMA_CURRENTTARGETMEM0
1058 * @arg @ref LL_BDMA_CURRENTTARGETMEM1
1059 */
1060 __STATIC_INLINE uint32_t LL_BDMA_GetCurrentTargetMem(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1061 {
1062 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1063
1064 return (READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_CT));
1065 }
1066
1067 /**
1068 * @brief Enable the double buffer mode.
1069 * @rmtoll CR DBM LL_BDMA_EnableDoubleBufferMode
1070 * @param BDMAx BDMAx Instance
1071 * @param Channel This parameter can be one of the following values:
1072 * @arg @ref LL_BDMA_CHANNEL_0
1073 * @arg @ref LL_BDMA_CHANNEL_1
1074 * @arg @ref LL_BDMA_CHANNEL_2
1075 * @arg @ref LL_BDMA_CHANNEL_3
1076 * @arg @ref LL_BDMA_CHANNEL_4
1077 * @arg @ref LL_BDMA_CHANNEL_5
1078 * @arg @ref LL_BDMA_CHANNEL_6
1079 * @arg @ref LL_BDMA_CHANNEL_7
1080 * @retval None
1081 */
1082 __STATIC_INLINE void LL_BDMA_EnableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1083 {
1084 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1085
1086 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1087 }
1088
1089 /**
1090 * @brief Disable the double buffer mode.
1091 * @rmtoll CR DBM LL_BDMA_DisableDoubleBufferMode
1092 * @param BDMAx BDMAx Instance
1093 * @param Channel This parameter can be one of the following values:
1094 * @arg @ref LL_BDMA_CHANNEL_0
1095 * @arg @ref LL_BDMA_CHANNEL_1
1096 * @arg @ref LL_BDMA_CHANNEL_2
1097 * @arg @ref LL_BDMA_CHANNEL_3
1098 * @arg @ref LL_BDMA_CHANNEL_4
1099 * @arg @ref LL_BDMA_CHANNEL_5
1100 * @arg @ref LL_BDMA_CHANNEL_6
1101 * @arg @ref LL_BDMA_CHANNEL_7
1102 * @retval None
1103 */
1104 __STATIC_INLINE void LL_BDMA_DisableDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1105 {
1106 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1107
1108 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM);
1109 }
1110
1111 /**
1112 * @brief Check if double buffer mode is enabled or not.
1113 * @rmtoll CCR DBM LL_BDMA_IsEnabledDoubleBufferMode
1114 * @param BDMAx BDMAx Instance
1115 * @param Channel This parameter can be one of the following values:
1116 * @arg @ref LL_BDMA_CHANNEL_0
1117 * @arg @ref LL_BDMA_CHANNEL_1
1118 * @arg @ref LL_BDMA_CHANNEL_2
1119 * @arg @ref LL_BDMA_CHANNEL_3
1120 * @arg @ref LL_BDMA_CHANNEL_4
1121 * @arg @ref LL_BDMA_CHANNEL_5
1122 * @arg @ref LL_BDMA_CHANNEL_6
1123 * @arg @ref LL_BDMA_CHANNEL_7
1124 * @retval State of bit (1 or 0).
1125 */
1126 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledDoubleBufferMode(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1127 {
1128 register uint32_t bdma_base_addr = (uint32_t)BDMAx;
1129
1130 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_DBM) == (BDMA_CCR_DBM)) ? 1UL : 0UL);
1131 }
1132
1133 /**
1134 * @brief Configure the Source and Destination addresses.
1135 * @note This API must not be called when the BDMA channel is enabled.
1136 * @note Each IP using BDMA provides an API to get directly the register address (LL_PPP_BDMA_GetRegAddr).
1137 * @rmtoll CPAR PA LL_BDMA_ConfigAddresses\n
1138 * CMAR MA LL_BDMA_ConfigAddresses
1139 * @param BDMAx BDMA Instance
1140 * @param Channel This parameter can be one of the following values:
1141 * @arg @ref LL_BDMA_CHANNEL_0
1142 * @arg @ref LL_BDMA_CHANNEL_1
1143 * @arg @ref LL_BDMA_CHANNEL_2
1144 * @arg @ref LL_BDMA_CHANNEL_3
1145 * @arg @ref LL_BDMA_CHANNEL_4
1146 * @arg @ref LL_BDMA_CHANNEL_5
1147 * @arg @ref LL_BDMA_CHANNEL_6
1148 * @arg @ref LL_BDMA_CHANNEL_7
1149 * @param SrcAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1150 * @param DstAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1151 * @param Direction This parameter can be one of the following values:
1152 * @arg @ref LL_BDMA_DIRECTION_PERIPH_TO_MEMORY
1153 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_PERIPH
1154 * @arg @ref LL_BDMA_DIRECTION_MEMORY_TO_MEMORY
1155 * @retval None
1156 */
1157 __STATIC_INLINE void LL_BDMA_ConfigAddresses(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t SrcAddress,
1158 uint32_t DstAddress, uint32_t Direction)
1159 {
1160 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1161
1162 /* Direction Memory to Periph */
1163 if (Direction == LL_BDMA_DIRECTION_MEMORY_TO_PERIPH)
1164 {
1165 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, SrcAddress);
1166 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, DstAddress);
1167 }
1168 /* Direction Periph to Memory and Memory to Memory */
1169 else
1170 {
1171 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, SrcAddress);
1172 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, DstAddress);
1173 }
1174 }
1175
1176 /**
1177 * @brief Set the Memory address.
1178 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1179 * @note This API must not be called when the BDMA channel is enabled.
1180 * @rmtoll CMAR MA LL_BDMA_SetMemoryAddress
1181 * @param BDMAx BDMA Instance
1182 * @param Channel This parameter can be one of the following values:
1183 * @arg @ref LL_BDMA_CHANNEL_0
1184 * @arg @ref LL_BDMA_CHANNEL_1
1185 * @arg @ref LL_BDMA_CHANNEL_2
1186 * @arg @ref LL_BDMA_CHANNEL_3
1187 * @arg @ref LL_BDMA_CHANNEL_4
1188 * @arg @ref LL_BDMA_CHANNEL_5
1189 * @arg @ref LL_BDMA_CHANNEL_6
1190 * @arg @ref LL_BDMA_CHANNEL_7
1191 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1192 * @retval None
1193 */
1194 __STATIC_INLINE void LL_BDMA_SetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1195 {
1196 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1197
1198 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1199 }
1200
1201 /**
1202 * @brief Set the Peripheral address.
1203 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1204 * @note This API must not be called when the BDMA channel is enabled.
1205 * @rmtoll CPAR PA LL_BDMA_SetPeriphAddress
1206 * @param BDMAx BDMA Instance
1207 * @param Channel This parameter can be one of the following values:
1208 * @arg @ref LL_BDMA_CHANNEL_0
1209 * @arg @ref LL_BDMA_CHANNEL_1
1210 * @arg @ref LL_BDMA_CHANNEL_2
1211 * @arg @ref LL_BDMA_CHANNEL_3
1212 * @arg @ref LL_BDMA_CHANNEL_4
1213 * @arg @ref LL_BDMA_CHANNEL_5
1214 * @arg @ref LL_BDMA_CHANNEL_6
1215 * @arg @ref LL_BDMA_CHANNEL_7
1216 * @param PeriphAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1217 * @retval None
1218 */
1219 __STATIC_INLINE void LL_BDMA_SetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t PeriphAddress)
1220 {
1221 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1222
1223 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, PeriphAddress);
1224 }
1225
1226 /**
1227 * @brief Get Memory address.
1228 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1229 * @rmtoll CMAR MA LL_BDMA_GetMemoryAddress
1230 * @param BDMAx BDMA Instance
1231 * @param Channel This parameter can be one of the following values:
1232 * @arg @ref LL_BDMA_CHANNEL_0
1233 * @arg @ref LL_BDMA_CHANNEL_1
1234 * @arg @ref LL_BDMA_CHANNEL_2
1235 * @arg @ref LL_BDMA_CHANNEL_3
1236 * @arg @ref LL_BDMA_CHANNEL_4
1237 * @arg @ref LL_BDMA_CHANNEL_5
1238 * @arg @ref LL_BDMA_CHANNEL_6
1239 * @arg @ref LL_BDMA_CHANNEL_7
1240 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1241 */
1242 __STATIC_INLINE uint32_t LL_BDMA_GetMemoryAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1243 {
1244 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1245
1246 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1247 }
1248
1249 /**
1250 * @brief Get Peripheral address.
1251 * @note Interface used for direction LL_BDMA_DIRECTION_PERIPH_TO_MEMORY or LL_BDMA_DIRECTION_MEMORY_TO_PERIPH only.
1252 * @rmtoll CPAR PA LL_BDMA_GetPeriphAddress
1253 * @param BDMAx BDMA Instance
1254 * @param Channel This parameter can be one of the following values:
1255 * @arg @ref LL_BDMA_CHANNEL_0
1256 * @arg @ref LL_BDMA_CHANNEL_1
1257 * @arg @ref LL_BDMA_CHANNEL_2
1258 * @arg @ref LL_BDMA_CHANNEL_3
1259 * @arg @ref LL_BDMA_CHANNEL_4
1260 * @arg @ref LL_BDMA_CHANNEL_5
1261 * @arg @ref LL_BDMA_CHANNEL_6
1262 * @arg @ref LL_BDMA_CHANNEL_7
1263 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1264 */
1265 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1266 {
1267 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1268
1269 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1270 }
1271
1272 /**
1273 * @brief Set the Memory to Memory Source address.
1274 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1275 * @note This API must not be called when the BDMA channel is enabled.
1276 * @rmtoll CPAR PA LL_BDMA_SetM2MSrcAddress
1277 * @param BDMAx BDMA Instance
1278 * @param Channel This parameter can be one of the following values:
1279 * @arg @ref LL_BDMA_CHANNEL_0
1280 * @arg @ref LL_BDMA_CHANNEL_1
1281 * @arg @ref LL_BDMA_CHANNEL_2
1282 * @arg @ref LL_BDMA_CHANNEL_3
1283 * @arg @ref LL_BDMA_CHANNEL_4
1284 * @arg @ref LL_BDMA_CHANNEL_5
1285 * @arg @ref LL_BDMA_CHANNEL_6
1286 * @arg @ref LL_BDMA_CHANNEL_7
1287 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1288 * @retval None
1289 */
1290 __STATIC_INLINE void LL_BDMA_SetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1291 {
1292 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1293
1294 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR, MemoryAddress);
1295 }
1296
1297 /**
1298 * @brief Set the Memory to Memory Destination address.
1299 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1300 * @note This API must not be called when the BDMA channel is enabled.
1301 * @rmtoll CMAR MA LL_BDMA_SetM2MDstAddress
1302 * @param BDMAx BDMA Instance
1303 * @param Channel This parameter can be one of the following values:
1304 * @arg @ref LL_BDMA_CHANNEL_0
1305 * @arg @ref LL_BDMA_CHANNEL_1
1306 * @arg @ref LL_BDMA_CHANNEL_2
1307 * @arg @ref LL_BDMA_CHANNEL_3
1308 * @arg @ref LL_BDMA_CHANNEL_4
1309 * @arg @ref LL_BDMA_CHANNEL_5
1310 * @arg @ref LL_BDMA_CHANNEL_6
1311 * @arg @ref LL_BDMA_CHANNEL_7
1312 * @param MemoryAddress Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1313 * @retval None
1314 */
1315 __STATIC_INLINE void LL_BDMA_SetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t MemoryAddress)
1316 {
1317 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1318
1319 WRITE_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR, MemoryAddress);
1320 }
1321
1322 /**
1323 * @brief Get the Memory to Memory Source address.
1324 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1325 * @rmtoll CPAR PA LL_BDMA_GetM2MSrcAddress
1326 * @param BDMAx BDMA Instance
1327 * @param Channel This parameter can be one of the following values:
1328 * @arg @ref LL_BDMA_CHANNEL_0
1329 * @arg @ref LL_BDMA_CHANNEL_1
1330 * @arg @ref LL_BDMA_CHANNEL_2
1331 * @arg @ref LL_BDMA_CHANNEL_3
1332 * @arg @ref LL_BDMA_CHANNEL_4
1333 * @arg @ref LL_BDMA_CHANNEL_5
1334 * @arg @ref LL_BDMA_CHANNEL_6
1335 * @arg @ref LL_BDMA_CHANNEL_7
1336 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1337 */
1338 __STATIC_INLINE uint32_t LL_BDMA_GetM2MSrcAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1339 {
1340 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1341
1342 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CPAR));
1343 }
1344
1345 /**
1346 * @brief Get the Memory to Memory Destination address.
1347 * @note Interface used for direction LL_BDMA_DIRECTION_MEMORY_TO_MEMORY only.
1348 * @rmtoll CMAR MA LL_BDMA_GetM2MDstAddress
1349 * @param BDMAx BDMA Instance
1350 * @param Channel This parameter can be one of the following values:
1351 * @arg @ref LL_BDMA_CHANNEL_0
1352 * @arg @ref LL_BDMA_CHANNEL_1
1353 * @arg @ref LL_BDMA_CHANNEL_2
1354 * @arg @ref LL_BDMA_CHANNEL_3
1355 * @arg @ref LL_BDMA_CHANNEL_4
1356 * @arg @ref LL_BDMA_CHANNEL_5
1357 * @arg @ref LL_BDMA_CHANNEL_6
1358 * @arg @ref LL_BDMA_CHANNEL_7
1359 * @retval Between Min_Data = 0 and Max_Data = 0xFFFFFFFF
1360 */
1361 __STATIC_INLINE uint32_t LL_BDMA_GetM2MDstAddress(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1362 {
1363 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1364
1365 return (READ_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM0AR));
1366 }
1367
1368 /**
1369 * @brief Set Memory 1 address (used in case of Double buffer mode).
1370 * @rmtoll M1AR M1A LL_BDMA_SetMemory1Address
1371 * @param BDMAx BDMAx Instance
1372 * @param Channel This parameter can be one of the following values:
1373 * @arg @ref LL_BDMA_CHANNEL_0
1374 * @arg @ref LL_BDMA_CHANNEL_1
1375 * @arg @ref LL_BDMA_CHANNEL_2
1376 * @arg @ref LL_BDMA_CHANNEL_3
1377 * @arg @ref LL_BDMA_CHANNEL_4
1378 * @arg @ref LL_BDMA_CHANNEL_5
1379 * @arg @ref LL_BDMA_CHANNEL_6
1380 * @arg @ref LL_BDMA_CHANNEL_7
1381 * @param Address Between 0 to 0xFFFFFFFF
1382 * @retval None
1383 */
1384 __STATIC_INLINE void LL_BDMA_SetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Address)
1385 {
1386 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1387
1388 MODIFY_REG(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR, BDMA_CM1AR_MA, Address);
1389 }
1390
1391 /**
1392 * @brief Get Memory 1 address (used in case of Double buffer mode).
1393 * @rmtoll M1AR M1A LL_BDMA_GetMemory1Address
1394 * @param BDMAx BDMAx Instance
1395 * @param Channel This parameter can be one of the following values:
1396 * @arg @ref LL_BDMA_CHANNEL_0
1397 * @arg @ref LL_BDMA_CHANNEL_1
1398 * @arg @ref LL_BDMA_CHANNEL_2
1399 * @arg @ref LL_BDMA_CHANNEL_3
1400 * @arg @ref LL_BDMA_CHANNEL_4
1401 * @arg @ref LL_BDMA_CHANNEL_5
1402 * @arg @ref LL_BDMA_CHANNEL_6
1403 * @arg @ref LL_BDMA_CHANNEL_7
1404 * @retval Between 0 to 0xFFFFFFFF
1405 */
1406 __STATIC_INLINE uint32_t LL_BDMA_GetMemory1Address(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1407 {
1408 uint32_t bdma_base_addr = (uint32_t)BDMAx;
1409
1410 return (((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CM1AR);
1411 }
1412
1413 /**
1414 * @brief Set BDMA request for BDMA Channels on DMAMUX Channel x.
1415 * @note DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
1416 * @rmtoll CxCR DMAREQ_ID LL_BDMA_SetPeriphRequest
1417 * @param BDMAx BDMAx Instance
1418 * @param Channel This parameter can be one of the following values:
1419 * @arg @ref LL_BDMA_CHANNEL_0
1420 * @arg @ref LL_BDMA_CHANNEL_1
1421 * @arg @ref LL_BDMA_CHANNEL_2
1422 * @arg @ref LL_BDMA_CHANNEL_3
1423 * @arg @ref LL_BDMA_CHANNEL_4
1424 * @arg @ref LL_BDMA_CHANNEL_5
1425 * @arg @ref LL_BDMA_CHANNEL_6
1426 * @arg @ref LL_BDMA_CHANNEL_7
1427 * @param Request This parameter can be one of the following values:
1428 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1429 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1430 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1431 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1432 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1433 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1434 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1435 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1436 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1437 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1438 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1439 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1440 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1441 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1442 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1443 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1444 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1445 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1446 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1447 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1448 *
1449 * @note (*) Availability depends on devices.
1450 * @retval None
1451 */
1452 __STATIC_INLINE void LL_BDMA_SetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel, uint32_t Request)
1453 {
1454 UNUSED(BDMAx);
1455 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1456 }
1457
1458 /**
1459 * @brief Get BDMA request for BDMA Channels on DMAMUX Channel x.
1460 * @note DMAMUX channel 0 to 7 are mapped to BDMA channel 0 to 7.
1461 * @rmtoll CxCR DMAREQ_ID LL_BDMA_GetPeriphRequest
1462 * @param BDMAx BDMAx Instance
1463 * @param Channel This parameter can be one of the following values:
1464 * @arg @ref LL_BDMA_CHANNEL_0
1465 * @arg @ref LL_BDMA_CHANNEL_1
1466 * @arg @ref LL_BDMA_CHANNEL_2
1467 * @arg @ref LL_BDMA_CHANNEL_3
1468 * @arg @ref LL_BDMA_CHANNEL_4
1469 * @arg @ref LL_BDMA_CHANNEL_5
1470 * @arg @ref LL_BDMA_CHANNEL_6
1471 * @arg @ref LL_BDMA_CHANNEL_7
1472 * @retval Returned value can be one of the following values:
1473 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
1474 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
1475 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
1476 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
1477 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
1478 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
1479 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
1480 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
1481 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
1482 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
1483 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
1484 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
1485 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
1486 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
1487 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
1488 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
1489 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
1490 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
1491 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
1492 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
1493 *
1494 * @note (*) Availability depends on devices.
1495 */
1496 __STATIC_INLINE uint32_t LL_BDMA_GetPeriphRequest(const BDMA_TypeDef *BDMAx, uint32_t Channel)
1497 {
1498 UNUSED(BDMAx);
1499 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX2_Channel0 + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1500 }
1501
1502 /**
1503 * @}
1504 */
1505
1506
1507 /** @defgroup BDMA_LL_EF_FLAG_Management FLAG_Management
1508 * @{
1509 */
1510 /**
1511 * @brief Get Channel 0 global interrupt flag.
1512 * @rmtoll ISR GIF0 LL_BDMA_IsActiveFlag_GI0
1513 * @param BDMAx BDMA Instance
1514 * @retval State of bit (1 or 0).
1515 */
1516 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI0(const BDMA_TypeDef *BDMAx)
1517 {
1518 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF0) == (BDMA_ISR_GIF0)) ? 1UL : 0UL);
1519 }
1520
1521 /**
1522 * @brief Get Channel 1 global interrupt flag.
1523 * @rmtoll ISR GIF1 LL_BDMA_IsActiveFlag_GI1
1524 * @param BDMAx BDMA Instance
1525 * @retval State of bit (1 or 0).
1526 */
1527 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI1(const BDMA_TypeDef *BDMAx)
1528 {
1529 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF1) == (BDMA_ISR_GIF1)) ? 1UL : 0UL);
1530 }
1531
1532 /**
1533 * @brief Get Channel 2 global interrupt flag.
1534 * @rmtoll ISR GIF2 LL_BDMA_IsActiveFlag_GI2
1535 * @param BDMAx BDMA Instance
1536 * @retval State of bit (1 or 0).
1537 */
1538 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI2(const BDMA_TypeDef *BDMAx)
1539 {
1540 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF2) == (BDMA_ISR_GIF2)) ? 1UL : 0UL);
1541 }
1542
1543 /**
1544 * @brief Get Channel 3 global interrupt flag.
1545 * @rmtoll ISR GIF3 LL_BDMA_IsActiveFlag_GI3
1546 * @param BDMAx BDMA Instance
1547 * @retval State of bit (1 or 0).
1548 */
1549 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI3(const BDMA_TypeDef *BDMAx)
1550 {
1551 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF3) == (BDMA_ISR_GIF3)) ? 1UL : 0UL);
1552 }
1553
1554 /**
1555 * @brief Get Channel 4 global interrupt flag.
1556 * @rmtoll ISR GIF4 LL_BDMA_IsActiveFlag_GI4
1557 * @param BDMAx BDMA Instance
1558 * @retval State of bit (1 or 0).
1559 */
1560 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI4(const BDMA_TypeDef *BDMAx)
1561 {
1562 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF4) == (BDMA_ISR_GIF4)) ? 1UL : 0UL);
1563 }
1564
1565 /**
1566 * @brief Get Channel 5 global interrupt flag.
1567 * @rmtoll ISR GIF5 LL_BDMA_IsActiveFlag_GI5
1568 * @param BDMAx BDMA Instance
1569 * @retval State of bit (1 or 0).
1570 */
1571 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI5(const BDMA_TypeDef *BDMAx)
1572 {
1573 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF5) == (BDMA_ISR_GIF5)) ? 1UL : 0UL);
1574 }
1575
1576 /**
1577 * @brief Get Channel 6 global interrupt flag.
1578 * @rmtoll ISR GIF6 LL_BDMA_IsActiveFlag_GI6
1579 * @param BDMAx BDMA Instance
1580 * @retval State of bit (1 or 0).
1581 */
1582 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI6(const BDMA_TypeDef *BDMAx)
1583 {
1584 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF6) == (BDMA_ISR_GIF6)) ? 1UL : 0UL);
1585 }
1586
1587 /**
1588 * @brief Get Channel 7 global interrupt flag.
1589 * @rmtoll ISR GIF7 LL_BDMA_IsActiveFlag_GI7
1590 * @param BDMAx BDMA Instance
1591 * @retval State of bit (1 or 0).
1592 */
1593 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_GI7(const BDMA_TypeDef *BDMAx)
1594 {
1595 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_GIF7) == (BDMA_ISR_GIF7)) ? 1UL : 0UL);
1596 }
1597
1598 /**
1599 * @brief Get Channel 0 transfer complete flag.
1600 * @rmtoll ISR TCIF0 LL_BDMA_IsActiveFlag_TC0
1601 * @param BDMAx BDMA Instance
1602 * @retval State of bit (1 or 0).
1603 */
1604 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC0(const BDMA_TypeDef *BDMAx)
1605 {
1606 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF0) == (BDMA_ISR_TCIF0)) ? 1UL : 0UL);
1607 }
1608 /**
1609 * @brief Get Channel 1 transfer complete flag.
1610 * @rmtoll ISR TCIF1 LL_BDMA_IsActiveFlag_TC1
1611 * @param BDMAx BDMA Instance
1612 * @retval State of bit (1 or 0).
1613 */
1614 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC1(const BDMA_TypeDef *BDMAx)
1615 {
1616 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF1) == (BDMA_ISR_TCIF1)) ? 1UL : 0UL);
1617 }
1618
1619 /**
1620 * @brief Get Channel 2 transfer complete flag.
1621 * @rmtoll ISR TCIF2 LL_BDMA_IsActiveFlag_TC2
1622 * @param BDMAx BDMA Instance
1623 * @retval State of bit (1 or 0).
1624 */
1625 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC2(const BDMA_TypeDef *BDMAx)
1626 {
1627 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF2) == (BDMA_ISR_TCIF2)) ? 1UL : 0UL);
1628 }
1629
1630 /**
1631 * @brief Get Channel 3 transfer complete flag.
1632 * @rmtoll ISR TCIF3 LL_BDMA_IsActiveFlag_TC3
1633 * @param BDMAx BDMA Instance
1634 * @retval State of bit (1 or 0).
1635 */
1636 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC3(const BDMA_TypeDef *BDMAx)
1637 {
1638 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF3) == (BDMA_ISR_TCIF3)) ? 1UL : 0UL);
1639 }
1640
1641 /**
1642 * @brief Get Channel 4 transfer complete flag.
1643 * @rmtoll ISR TCIF4 LL_BDMA_IsActiveFlag_TC4
1644 * @param BDMAx BDMA Instance
1645 * @retval State of bit (1 or 0).
1646 */
1647 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC4(const BDMA_TypeDef *BDMAx)
1648 {
1649 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF4) == (BDMA_ISR_TCIF4)) ? 1UL : 0UL);
1650 }
1651
1652 /**
1653 * @brief Get Channel 5 transfer complete flag.
1654 * @rmtoll ISR TCIF5 LL_BDMA_IsActiveFlag_TC5
1655 * @param BDMAx BDMA Instance
1656 * @retval State of bit (1 or 0).
1657 */
1658 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC5(const BDMA_TypeDef *BDMAx)
1659 {
1660 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF5) == (BDMA_ISR_TCIF5)) ? 1UL : 0UL);
1661 }
1662
1663 /**
1664 * @brief Get Channel 6 transfer complete flag.
1665 * @rmtoll ISR TCIF6 LL_BDMA_IsActiveFlag_TC6
1666 * @param BDMAx BDMA Instance
1667 * @retval State of bit (1 or 0).
1668 */
1669 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC6(const BDMA_TypeDef *BDMAx)
1670 {
1671 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF6) == (BDMA_ISR_TCIF6)) ? 1UL : 0UL);
1672 }
1673
1674 /**
1675 * @brief Get Channel 7 transfer complete flag.
1676 * @rmtoll ISR TCIF7 LL_BDMA_IsActiveFlag_TC7
1677 * @param BDMAx BDMA Instance
1678 * @retval State of bit (1 or 0).
1679 */
1680 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TC7(const BDMA_TypeDef *BDMAx)
1681 {
1682 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TCIF7) == (BDMA_ISR_TCIF7)) ? 1UL : 0UL);
1683 }
1684
1685 /**
1686 * @brief Get Channel 0 half transfer flag.
1687 * @rmtoll ISR HTIF0 LL_BDMA_IsActiveFlag_HT0
1688 * @param BDMAx BDMA Instance
1689 * @retval State of bit (1 or 0).
1690 */
1691 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT0(const BDMA_TypeDef *BDMAx)
1692 {
1693 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF0) == (BDMA_ISR_HTIF0)) ? 1UL : 0UL);
1694 }
1695
1696 /**
1697 * @brief Get Channel 1 half transfer flag.
1698 * @rmtoll ISR HTIF1 LL_BDMA_IsActiveFlag_HT1
1699 * @param BDMAx BDMA Instance
1700 * @retval State of bit (1 or 0).
1701 */
1702 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT1(const BDMA_TypeDef *BDMAx)
1703 {
1704 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF1) == (BDMA_ISR_HTIF1)) ? 1UL : 0UL);
1705 }
1706
1707 /**
1708 * @brief Get Channel 2 half transfer flag.
1709 * @rmtoll ISR HTIF2 LL_BDMA_IsActiveFlag_HT2
1710 * @param BDMAx BDMA Instance
1711 * @retval State of bit (1 or 0).
1712 */
1713 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT2(const BDMA_TypeDef *BDMAx)
1714 {
1715 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF2) == (BDMA_ISR_HTIF2)) ? 1UL : 0UL);
1716 }
1717
1718 /**
1719 * @brief Get Channel 3 half transfer flag.
1720 * @rmtoll ISR HTIF3 LL_BDMA_IsActiveFlag_HT3
1721 * @param BDMAx BDMA Instance
1722 * @retval State of bit (1 or 0).
1723 */
1724 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT3(const BDMA_TypeDef *BDMAx)
1725 {
1726 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF3) == (BDMA_ISR_HTIF3)) ? 1UL : 0UL);
1727 }
1728
1729 /**
1730 * @brief Get Channel 4 half transfer flag.
1731 * @rmtoll ISR HTIF4 LL_BDMA_IsActiveFlag_HT4
1732 * @param BDMAx BDMA Instance
1733 * @retval State of bit (1 or 0).
1734 */
1735 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT4(const BDMA_TypeDef *BDMAx)
1736 {
1737 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF4) == (BDMA_ISR_HTIF4)) ? 1UL : 0UL);
1738 }
1739
1740 /**
1741 * @brief Get Channel 5 half transfer flag.
1742 * @rmtoll ISR HTIF5 LL_BDMA_IsActiveFlag_HT5
1743 * @param BDMAx BDMA Instance
1744 * @retval State of bit (1 or 0).
1745 */
1746 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT5(const BDMA_TypeDef *BDMAx)
1747 {
1748 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF5) == (BDMA_ISR_HTIF5)) ? 1UL : 0UL);
1749 }
1750
1751 /**
1752 * @brief Get Channel 6 half transfer flag.
1753 * @rmtoll ISR HTIF6 LL_BDMA_IsActiveFlag_HT6
1754 * @param BDMAx BDMA Instance
1755 * @retval State of bit (1 or 0).
1756 */
1757 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT6(const BDMA_TypeDef *BDMAx)
1758 {
1759 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF6) == (BDMA_ISR_HTIF6)) ? 1UL : 0UL);
1760 }
1761
1762 /**
1763 * @brief Get Channel 7 half transfer flag.
1764 * @rmtoll ISR HTIF7 LL_BDMA_IsActiveFlag_HT7
1765 * @param BDMAx BDMA Instance
1766 * @retval State of bit (1 or 0).
1767 */
1768 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_HT7(const BDMA_TypeDef *BDMAx)
1769 {
1770 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_HTIF7) == (BDMA_ISR_HTIF7)) ? 1UL : 0UL);
1771 }
1772
1773 /**
1774 * @brief Get Channel 0 transfer error flag.
1775 * @rmtoll ISR TEIF0 LL_BDMA_IsActiveFlag_TE0
1776 * @param BDMAx BDMA Instance
1777 * @retval State of bit (1 or 0).
1778 */
1779 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE0(const BDMA_TypeDef *BDMAx)
1780 {
1781 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF0) == (BDMA_ISR_TEIF0)) ? 1UL : 0UL);
1782 }
1783
1784 /**
1785 * @brief Get Channel 1 transfer error flag.
1786 * @rmtoll ISR TEIF1 LL_BDMA_IsActiveFlag_TE1
1787 * @param BDMAx BDMA Instance
1788 * @retval State of bit (1 or 0).
1789 */
1790 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE1(const BDMA_TypeDef *BDMAx)
1791 {
1792 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF1) == (BDMA_ISR_TEIF1)) ? 1UL : 0UL);
1793 }
1794
1795 /**
1796 * @brief Get Channel 2 transfer error flag.
1797 * @rmtoll ISR TEIF2 LL_BDMA_IsActiveFlag_TE2
1798 * @param BDMAx BDMA Instance
1799 * @retval State of bit (1 or 0).
1800 */
1801 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE2(const BDMA_TypeDef *BDMAx)
1802 {
1803 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF2) == (BDMA_ISR_TEIF2)) ? 1UL : 0UL);
1804 }
1805
1806 /**
1807 * @brief Get Channel 3 transfer error flag.
1808 * @rmtoll ISR TEIF3 LL_BDMA_IsActiveFlag_TE3
1809 * @param BDMAx BDMA Instance
1810 * @retval State of bit (1 or 0).
1811 */
1812 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE3(const BDMA_TypeDef *BDMAx)
1813 {
1814 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF3) == (BDMA_ISR_TEIF3)) ? 1UL : 0UL);
1815 }
1816
1817 /**
1818 * @brief Get Channel 4 transfer error flag.
1819 * @rmtoll ISR TEIF4 LL_BDMA_IsActiveFlag_TE4
1820 * @param BDMAx BDMA Instance
1821 * @retval State of bit (1 or 0).
1822 */
1823 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE4(const BDMA_TypeDef *BDMAx)
1824 {
1825 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF4) == (BDMA_ISR_TEIF4)) ? 1UL : 0UL);
1826 }
1827
1828 /**
1829 * @brief Get Channel 5 transfer error flag.
1830 * @rmtoll ISR TEIF5 LL_BDMA_IsActiveFlag_TE5
1831 * @param BDMAx BDMA Instance
1832 * @retval State of bit (1 or 0).
1833 */
1834 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE5(const BDMA_TypeDef *BDMAx)
1835 {
1836 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF5) == (BDMA_ISR_TEIF5)) ? 1UL : 0UL);
1837 }
1838
1839 /**
1840 * @brief Get Channel 6 transfer error flag.
1841 * @rmtoll ISR TEIF6 LL_BDMA_IsActiveFlag_TE6
1842 * @param BDMAx BDMA Instance
1843 * @retval State of bit (1 or 0).
1844 */
1845 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE6(const BDMA_TypeDef *BDMAx)
1846 {
1847 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF6) == (BDMA_ISR_TEIF6)) ? 1UL : 0UL);
1848 }
1849
1850 /**
1851 * @brief Get Channel 7 transfer error flag.
1852 * @rmtoll ISR TEIF7 LL_BDMA_IsActiveFlag_TE7
1853 * @param BDMAx BDMA Instance
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t LL_BDMA_IsActiveFlag_TE7(const BDMA_TypeDef *BDMAx)
1857 {
1858 return ((READ_BIT(BDMAx->ISR, BDMA_ISR_TEIF7) == (BDMA_ISR_TEIF7)) ? 1UL : 0UL);
1859 }
1860
1861 /**
1862 * @brief Clear Channel 0 global interrupt flag.
1863 * @note Do not Clear Channel 0 global interrupt flag when the channel in ON.
1864 Instead clear specific flags transfer complete, half transfer & transfer
1865 error flag with LL_DMA_ClearFlag_TC0, LL_DMA_ClearFlag_HT0,
1866 LL_DMA_ClearFlag_TE0. bug id 2.3.1 in Product Errata Sheet.
1867 * @rmtoll IFCR CGIF0 LL_BDMA_ClearFlag_GI0
1868 * @param BDMAx BDMA Instance
1869 * @retval None
1870 */
1871 __STATIC_INLINE void LL_BDMA_ClearFlag_GI0(BDMA_TypeDef *BDMAx)
1872 {
1873 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF0);
1874 }
1875
1876 /**
1877 * @brief Clear Channel 1 global interrupt flag.
1878 * @note Do not Clear Channel 1 global interrupt flag when the channel in ON.
1879 Instead clear specific flags transfer complete, half transfer & transfer
1880 error flag with LL_DMA_ClearFlag_TC1, LL_DMA_ClearFlag_HT1,
1881 LL_DMA_ClearFlag_TE1. bug id 2.3.1 in Product Errata Sheet.
1882 * @rmtoll IFCR CGIF1 LL_BDMA_ClearFlag_GI1
1883 * @param BDMAx BDMA Instance
1884 * @retval None
1885 */
1886 __STATIC_INLINE void LL_BDMA_ClearFlag_GI1(BDMA_TypeDef *BDMAx)
1887 {
1888 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF1);
1889 }
1890
1891 /**
1892 * @brief Clear Channel 2 global interrupt flag.
1893 * @note Do not Clear Channel 2 global interrupt flag when the channel in ON.
1894 Instead clear specific flags transfer complete, half transfer & transfer
1895 error flag with LL_DMA_ClearFlag_TC2, LL_DMA_ClearFlag_HT2,
1896 LL_DMA_ClearFlag_TE2. bug id 2.3.1 in Product Errata Sheet.
1897 * @rmtoll IFCR CGIF2 LL_BDMA_ClearFlag_GI2
1898 * @param BDMAx BDMA Instance
1899 * @retval None
1900 */
1901 __STATIC_INLINE void LL_BDMA_ClearFlag_GI2(BDMA_TypeDef *BDMAx)
1902 {
1903 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF2);
1904 }
1905
1906 /**
1907 * @brief Clear Channel 3 global interrupt flag.
1908 * @note Do not Clear Channel 3 global interrupt flag when the channel in ON.
1909 Instead clear specific flags transfer complete, half transfer & transfer
1910 error flag with LL_DMA_ClearFlag_TC3, LL_DMA_ClearFlag_HT3,
1911 LL_DMA_ClearFlag_TE3. bug id 2.3.1 in Product Errata Sheet.
1912 * @rmtoll IFCR CGIF3 LL_BDMA_ClearFlag_GI3
1913 * @param BDMAx BDMA Instance
1914 * @retval None
1915 */
1916 __STATIC_INLINE void LL_BDMA_ClearFlag_GI3(BDMA_TypeDef *BDMAx)
1917 {
1918 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF3);
1919 }
1920
1921 /**
1922 * @brief Clear Channel 4 global interrupt flag.
1923 * @note Do not Clear Channel 4 global interrupt flag when the channel in ON.
1924 Instead clear specific flags transfer complete, half transfer & transfer
1925 error flag with LL_DMA_ClearFlag_TC4, LL_DMA_ClearFlag_HT4,
1926 LL_DMA_ClearFlag_TE4. bug id 2.3.1 in Product Errata Sheet.
1927 * @rmtoll IFCR CGIF4 LL_BDMA_ClearFlag_GI4
1928 * @param BDMAx BDMA Instance
1929 * @retval None
1930 */
1931 __STATIC_INLINE void LL_BDMA_ClearFlag_GI4(BDMA_TypeDef *BDMAx)
1932 {
1933 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF4);
1934 }
1935
1936 /**
1937 * @brief Clear Channel 5 global interrupt flag.
1938 * @note Do not Clear Channel 5 global interrupt flag when the channel in ON.
1939 Instead clear specific flags transfer complete, half transfer & transfer
1940 error flag with LL_DMA_ClearFlag_TC5, LL_DMA_ClearFlag_HT5,
1941 LL_DMA_ClearFlag_TE5. bug id 2.3.1 in Product Errata Sheet.
1942 * @rmtoll IFCR CGIF5 LL_BDMA_ClearFlag_GI5
1943 * @param BDMAx BDMA Instance
1944 * @retval None
1945 */
1946 __STATIC_INLINE void LL_BDMA_ClearFlag_GI5(BDMA_TypeDef *BDMAx)
1947 {
1948 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF5);
1949 }
1950
1951 /**
1952 * @brief Clear Channel 6 global interrupt flag.
1953 * @note Do not Clear Channel 6 global interrupt flag when the channel in ON.
1954 Instead clear specific flags transfer complete, half transfer & transfer
1955 error flag with LL_DMA_ClearFlag_TC6, LL_DMA_ClearFlag_HT6,
1956 LL_DMA_ClearFlag_TE6. bug id 2.3.1 in Product Errata Sheet.
1957 * @rmtoll IFCR CGIF6 LL_BDMA_ClearFlag_GI6
1958 * @param BDMAx BDMA Instance
1959 * @retval None
1960 */
1961 __STATIC_INLINE void LL_BDMA_ClearFlag_GI6(BDMA_TypeDef *BDMAx)
1962 {
1963 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF6);
1964 }
1965
1966 /**
1967 * @brief Clear Channel 7 global interrupt flag.
1968 * @note Do not Clear Channel 7 global interrupt flag when the channel in ON.
1969 Instead clear specific flags transfer complete, half transfer & transfer
1970 error flag with LL_DMA_ClearFlag_TC7, LL_DMA_ClearFlag_HT7,
1971 LL_DMA_ClearFlag_TE7. bug id 2.3.1 in Product Errata Sheet.
1972 * @rmtoll IFCR CGIF7 LL_BDMA_ClearFlag_GI7
1973 * @param BDMAx BDMA Instance
1974 * @retval None
1975 */
1976 __STATIC_INLINE void LL_BDMA_ClearFlag_GI7(BDMA_TypeDef *BDMAx)
1977 {
1978 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CGIF7);
1979 }
1980
1981 /**
1982 * @brief Clear Channel 0 transfer complete flag.
1983 * @rmtoll IFCR CTCIF0 LL_BDMA_ClearFlag_TC0
1984 * @param BDMAx BDMA Instance
1985 * @retval None
1986 */
1987 __STATIC_INLINE void LL_BDMA_ClearFlag_TC0(BDMA_TypeDef *BDMAx)
1988 {
1989 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF0);
1990 }
1991
1992 /**
1993 * @brief Clear Channel 1 transfer complete flag.
1994 * @rmtoll IFCR CTCIF1 LL_BDMA_ClearFlag_TC1
1995 * @param BDMAx BDMA Instance
1996 * @retval None
1997 */
1998 __STATIC_INLINE void LL_BDMA_ClearFlag_TC1(BDMA_TypeDef *BDMAx)
1999 {
2000 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF1);
2001 }
2002
2003 /**
2004 * @brief Clear Channel 2 transfer complete flag.
2005 * @rmtoll IFCR CTCIF2 LL_BDMA_ClearFlag_TC2
2006 * @param BDMAx BDMA Instance
2007 * @retval None
2008 */
2009 __STATIC_INLINE void LL_BDMA_ClearFlag_TC2(BDMA_TypeDef *BDMAx)
2010 {
2011 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF2);
2012 }
2013
2014 /**
2015 * @brief Clear Channel 3 transfer complete flag.
2016 * @rmtoll IFCR CTCIF3 LL_BDMA_ClearFlag_TC3
2017 * @param BDMAx BDMA Instance
2018 * @retval None
2019 */
2020 __STATIC_INLINE void LL_BDMA_ClearFlag_TC3(BDMA_TypeDef *BDMAx)
2021 {
2022 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF3);
2023 }
2024
2025 /**
2026 * @brief Clear Channel 4 transfer complete flag.
2027 * @rmtoll IFCR CTCIF4 LL_BDMA_ClearFlag_TC4
2028 * @param BDMAx BDMA Instance
2029 * @retval None
2030 */
2031 __STATIC_INLINE void LL_BDMA_ClearFlag_TC4(BDMA_TypeDef *BDMAx)
2032 {
2033 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF4);
2034 }
2035
2036 /**
2037 * @brief Clear Channel 5 transfer complete flag.
2038 * @rmtoll IFCR CTCIF5 LL_BDMA_ClearFlag_TC5
2039 * @param BDMAx BDMA Instance
2040 * @retval None
2041 */
2042 __STATIC_INLINE void LL_BDMA_ClearFlag_TC5(BDMA_TypeDef *BDMAx)
2043 {
2044 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF5);
2045 }
2046
2047 /**
2048 * @brief Clear Channel 6 transfer complete flag.
2049 * @rmtoll IFCR CTCIF6 LL_BDMA_ClearFlag_TC6
2050 * @param BDMAx BDMA Instance
2051 * @retval None
2052 */
2053 __STATIC_INLINE void LL_BDMA_ClearFlag_TC6(BDMA_TypeDef *BDMAx)
2054 {
2055 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF6);
2056 }
2057
2058 /**
2059 * @brief Clear Channel 7 transfer complete flag.
2060 * @rmtoll IFCR CTCIF7 LL_BDMA_ClearFlag_TC7
2061 * @param BDMAx BDMA Instance
2062 * @retval None
2063 */
2064 __STATIC_INLINE void LL_BDMA_ClearFlag_TC7(BDMA_TypeDef *BDMAx)
2065 {
2066 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTCIF7);
2067 }
2068
2069 /**
2070 * @brief Clear Channel 0 half transfer flag.
2071 * @rmtoll IFCR CHTIF0 LL_BDMA_ClearFlag_HT0
2072 * @param BDMAx BDMA Instance
2073 * @retval None
2074 */
2075 __STATIC_INLINE void LL_BDMA_ClearFlag_HT0(BDMA_TypeDef *BDMAx)
2076 {
2077 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF0);
2078 }
2079
2080 /**
2081 * @brief Clear Channel 1 half transfer flag.
2082 * @rmtoll IFCR CHTIF1 LL_BDMA_ClearFlag_HT1
2083 * @param BDMAx BDMA Instance
2084 * @retval None
2085 */
2086 __STATIC_INLINE void LL_BDMA_ClearFlag_HT1(BDMA_TypeDef *BDMAx)
2087 {
2088 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF1);
2089 }
2090
2091 /**
2092 * @brief Clear Channel 2 half transfer flag.
2093 * @rmtoll IFCR CHTIF2 LL_BDMA_ClearFlag_HT2
2094 * @param BDMAx BDMA Instance
2095 * @retval None
2096 */
2097 __STATIC_INLINE void LL_BDMA_ClearFlag_HT2(BDMA_TypeDef *BDMAx)
2098 {
2099 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF2);
2100 }
2101
2102 /**
2103 * @brief Clear Channel 3 half transfer flag.
2104 * @rmtoll IFCR CHTIF3 LL_BDMA_ClearFlag_HT3
2105 * @param BDMAx BDMA Instance
2106 * @retval None
2107 */
2108 __STATIC_INLINE void LL_BDMA_ClearFlag_HT3(BDMA_TypeDef *BDMAx)
2109 {
2110 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF3);
2111 }
2112
2113 /**
2114 * @brief Clear Channel 4 half transfer flag.
2115 * @rmtoll IFCR CHTIF4 LL_BDMA_ClearFlag_HT4
2116 * @param BDMAx BDMA Instance
2117 * @retval None
2118 */
2119 __STATIC_INLINE void LL_BDMA_ClearFlag_HT4(BDMA_TypeDef *BDMAx)
2120 {
2121 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF4);
2122 }
2123
2124 /**
2125 * @brief Clear Channel 5 half transfer flag.
2126 * @rmtoll IFCR CHTIF5 LL_BDMA_ClearFlag_HT5
2127 * @param BDMAx BDMA Instance
2128 * @retval None
2129 */
2130 __STATIC_INLINE void LL_BDMA_ClearFlag_HT5(BDMA_TypeDef *BDMAx)
2131 {
2132 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF5);
2133 }
2134
2135 /**
2136 * @brief Clear Channel 6 half transfer flag.
2137 * @rmtoll IFCR CHTIF6 LL_BDMA_ClearFlag_HT6
2138 * @param BDMAx BDMA Instance
2139 * @retval None
2140 */
2141 __STATIC_INLINE void LL_BDMA_ClearFlag_HT6(BDMA_TypeDef *BDMAx)
2142 {
2143 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF6);
2144 }
2145
2146 /**
2147 * @brief Clear Channel 7 half transfer flag.
2148 * @rmtoll IFCR CHTIF7 LL_BDMA_ClearFlag_HT7
2149 * @param BDMAx BDMA Instance
2150 * @retval None
2151 */
2152 __STATIC_INLINE void LL_BDMA_ClearFlag_HT7(BDMA_TypeDef *BDMAx)
2153 {
2154 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CHTIF7);
2155 }
2156
2157 /**
2158 * @brief Clear Channel 0 transfer error flag.
2159 * @rmtoll IFCR CTEIF0 LL_BDMA_ClearFlag_TE0
2160 * @param BDMAx BDMA Instance
2161 * @retval None
2162 */
2163 __STATIC_INLINE void LL_BDMA_ClearFlag_TE0(BDMA_TypeDef *BDMAx)
2164 {
2165 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF0);
2166 }
2167
2168 /**
2169 * @brief Clear Channel 1 transfer error flag.
2170 * @rmtoll IFCR CTEIF1 LL_BDMA_ClearFlag_TE1
2171 * @param BDMAx BDMA Instance
2172 * @retval None
2173 */
2174 __STATIC_INLINE void LL_BDMA_ClearFlag_TE1(BDMA_TypeDef *BDMAx)
2175 {
2176 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF1);
2177 }
2178
2179 /**
2180 * @brief Clear Channel 2 transfer error flag.
2181 * @rmtoll IFCR CTEIF2 LL_BDMA_ClearFlag_TE2
2182 * @param BDMAx BDMA Instance
2183 * @retval None
2184 */
2185 __STATIC_INLINE void LL_BDMA_ClearFlag_TE2(BDMA_TypeDef *BDMAx)
2186 {
2187 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF2);
2188 }
2189
2190 /**
2191 * @brief Clear Channel 3 transfer error flag.
2192 * @rmtoll IFCR CTEIF3 LL_BDMA_ClearFlag_TE3
2193 * @param BDMAx BDMA Instance
2194 * @retval None
2195 */
2196 __STATIC_INLINE void LL_BDMA_ClearFlag_TE3(BDMA_TypeDef *BDMAx)
2197 {
2198 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF3);
2199 }
2200
2201 /**
2202 * @brief Clear Channel 4 transfer error flag.
2203 * @rmtoll IFCR CTEIF4 LL_BDMA_ClearFlag_TE4
2204 * @param BDMAx BDMA Instance
2205 * @retval None
2206 */
2207 __STATIC_INLINE void LL_BDMA_ClearFlag_TE4(BDMA_TypeDef *BDMAx)
2208 {
2209 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF4);
2210 }
2211
2212 /**
2213 * @brief Clear Channel 5 transfer error flag.
2214 * @rmtoll IFCR CTEIF5 LL_BDMA_ClearFlag_TE5
2215 * @param BDMAx BDMA Instance
2216 * @retval None
2217 */
2218 __STATIC_INLINE void LL_BDMA_ClearFlag_TE5(BDMA_TypeDef *BDMAx)
2219 {
2220 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF5);
2221 }
2222
2223 /**
2224 * @brief Clear Channel 6 transfer error flag.
2225 * @rmtoll IFCR CTEIF6 LL_BDMA_ClearFlag_TE6
2226 * @param BDMAx BDMA Instance
2227 * @retval None
2228 */
2229 __STATIC_INLINE void LL_BDMA_ClearFlag_TE6(BDMA_TypeDef *BDMAx)
2230 {
2231 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF6);
2232 }
2233
2234 /**
2235 * @brief Clear Channel 7 transfer error flag.
2236 * @rmtoll IFCR CTEIF7 LL_BDMA_ClearFlag_TE7
2237 * @param BDMAx BDMA Instance
2238 * @retval None
2239 */
2240 __STATIC_INLINE void LL_BDMA_ClearFlag_TE7(BDMA_TypeDef *BDMAx)
2241 {
2242 WRITE_REG(BDMAx->IFCR, BDMA_IFCR_CTEIF7);
2243 }
2244
2245 /**
2246 * @}
2247 */
2248
2249 /** @defgroup BDMA_LL_EF_IT_Management IT_Management
2250 * @{
2251 */
2252 /**
2253 * @brief Enable Transfer complete interrupt.
2254 * @rmtoll CCR TCIE LL_BDMA_EnableIT_TC
2255 * @param BDMAx BDMA Instance
2256 * @param Channel This parameter can be one of the following values:
2257 * @arg @ref LL_BDMA_CHANNEL_0
2258 * @arg @ref LL_BDMA_CHANNEL_1
2259 * @arg @ref LL_BDMA_CHANNEL_2
2260 * @arg @ref LL_BDMA_CHANNEL_3
2261 * @arg @ref LL_BDMA_CHANNEL_4
2262 * @arg @ref LL_BDMA_CHANNEL_5
2263 * @arg @ref LL_BDMA_CHANNEL_6
2264 * @arg @ref LL_BDMA_CHANNEL_7
2265 * @retval None
2266 */
2267 __STATIC_INLINE void LL_BDMA_EnableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2268 {
2269 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2270
2271 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2272 }
2273
2274 /**
2275 * @brief Enable Half transfer interrupt.
2276 * @rmtoll CCR HTIE LL_BDMA_EnableIT_HT
2277 * @param BDMAx BDMA Instance
2278 * @param Channel This parameter can be one of the following values:
2279 * @arg @ref LL_BDMA_CHANNEL_0
2280 * @arg @ref LL_BDMA_CHANNEL_1
2281 * @arg @ref LL_BDMA_CHANNEL_2
2282 * @arg @ref LL_BDMA_CHANNEL_3
2283 * @arg @ref LL_BDMA_CHANNEL_4
2284 * @arg @ref LL_BDMA_CHANNEL_5
2285 * @arg @ref LL_BDMA_CHANNEL_6
2286 * @arg @ref LL_BDMA_CHANNEL_7
2287 * @retval None
2288 */
2289 __STATIC_INLINE void LL_BDMA_EnableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2290 {
2291 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2292
2293 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2294 }
2295
2296 /**
2297 * @brief Enable Transfer error interrupt.
2298 * @rmtoll CCR TEIE LL_BDMA_EnableIT_TE
2299 * @param BDMAx BDMA Instance
2300 * @param Channel This parameter can be one of the following values:
2301 * @arg @ref LL_BDMA_CHANNEL_0
2302 * @arg @ref LL_BDMA_CHANNEL_1
2303 * @arg @ref LL_BDMA_CHANNEL_2
2304 * @arg @ref LL_BDMA_CHANNEL_3
2305 * @arg @ref LL_BDMA_CHANNEL_4
2306 * @arg @ref LL_BDMA_CHANNEL_5
2307 * @arg @ref LL_BDMA_CHANNEL_6
2308 * @arg @ref LL_BDMA_CHANNEL_7
2309 * @retval None
2310 */
2311 __STATIC_INLINE void LL_BDMA_EnableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2312 {
2313 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2314
2315 SET_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2316 }
2317
2318 /**
2319 * @brief Disable Transfer complete interrupt.
2320 * @rmtoll CCR TCIE LL_BDMA_DisableIT_TC
2321 * @param BDMAx BDMA Instance
2322 * @param Channel This parameter can be one of the following values:
2323 * @arg @ref LL_BDMA_CHANNEL_0
2324 * @arg @ref LL_BDMA_CHANNEL_1
2325 * @arg @ref LL_BDMA_CHANNEL_2
2326 * @arg @ref LL_BDMA_CHANNEL_3
2327 * @arg @ref LL_BDMA_CHANNEL_4
2328 * @arg @ref LL_BDMA_CHANNEL_5
2329 * @arg @ref LL_BDMA_CHANNEL_6
2330 * @arg @ref LL_BDMA_CHANNEL_7
2331 * @retval None
2332 */
2333 __STATIC_INLINE void LL_BDMA_DisableIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2334 {
2335 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2336
2337 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE);
2338 }
2339
2340 /**
2341 * @brief Disable Half transfer interrupt.
2342 * @rmtoll CCR HTIE LL_BDMA_DisableIT_HT
2343 * @param BDMAx BDMA Instance
2344 * @param Channel This parameter can be one of the following values:
2345 * @arg @ref LL_BDMA_CHANNEL_0
2346 * @arg @ref LL_BDMA_CHANNEL_1
2347 * @arg @ref LL_BDMA_CHANNEL_2
2348 * @arg @ref LL_BDMA_CHANNEL_3
2349 * @arg @ref LL_BDMA_CHANNEL_4
2350 * @arg @ref LL_BDMA_CHANNEL_5
2351 * @arg @ref LL_BDMA_CHANNEL_6
2352 * @arg @ref LL_BDMA_CHANNEL_7
2353 * @retval None
2354 */
2355 __STATIC_INLINE void LL_BDMA_DisableIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2356 {
2357 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2358
2359 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE);
2360 }
2361
2362 /**
2363 * @brief Disable Transfer error interrupt.
2364 * @rmtoll CCR TEIE LL_BDMA_DisableIT_TE
2365 * @param BDMAx BDMA Instance
2366 * @param Channel This parameter can be one of the following values:
2367 * @arg @ref LL_BDMA_CHANNEL_0
2368 * @arg @ref LL_BDMA_CHANNEL_1
2369 * @arg @ref LL_BDMA_CHANNEL_2
2370 * @arg @ref LL_BDMA_CHANNEL_3
2371 * @arg @ref LL_BDMA_CHANNEL_4
2372 * @arg @ref LL_BDMA_CHANNEL_5
2373 * @arg @ref LL_BDMA_CHANNEL_6
2374 * @arg @ref LL_BDMA_CHANNEL_7
2375 * @retval None
2376 */
2377 __STATIC_INLINE void LL_BDMA_DisableIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2378 {
2379 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2380
2381 CLEAR_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE);
2382 }
2383
2384 /**
2385 * @brief Check if Transfer complete Interrupt is enabled.
2386 * @rmtoll CCR TCIE LL_BDMA_IsEnabledIT_TC
2387 * @param BDMAx BDMA Instance
2388 * @param Channel This parameter can be one of the following values:
2389 * @arg @ref LL_BDMA_CHANNEL_0
2390 * @arg @ref LL_BDMA_CHANNEL_1
2391 * @arg @ref LL_BDMA_CHANNEL_2
2392 * @arg @ref LL_BDMA_CHANNEL_3
2393 * @arg @ref LL_BDMA_CHANNEL_4
2394 * @arg @ref LL_BDMA_CHANNEL_5
2395 * @arg @ref LL_BDMA_CHANNEL_6
2396 * @arg @ref LL_BDMA_CHANNEL_7
2397 * @retval State of bit (1 or 0).
2398 */
2399 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TC(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2400 {
2401 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2402
2403 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TCIE) == (BDMA_CCR_TCIE)) ? 1UL : 0UL);
2404 }
2405
2406 /**
2407 * @brief Check if Half transfer Interrupt is enabled.
2408 * @rmtoll CCR HTIE LL_BDMA_IsEnabledIT_HT
2409 * @param BDMAx BDMA Instance
2410 * @param Channel This parameter can be one of the following values:
2411 * @arg @ref LL_BDMA_CHANNEL_0
2412 * @arg @ref LL_BDMA_CHANNEL_1
2413 * @arg @ref LL_BDMA_CHANNEL_2
2414 * @arg @ref LL_BDMA_CHANNEL_3
2415 * @arg @ref LL_BDMA_CHANNEL_4
2416 * @arg @ref LL_BDMA_CHANNEL_5
2417 * @arg @ref LL_BDMA_CHANNEL_6
2418 * @arg @ref LL_BDMA_CHANNEL_7
2419 * @retval State of bit (1 or 0).
2420 */
2421 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_HT(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2422 {
2423 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2424
2425 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_HTIE) == (BDMA_CCR_HTIE)) ? 1UL : 0UL);
2426 }
2427
2428 /**
2429 * @brief Check if Transfer error Interrupt is enabled.
2430 * @rmtoll CCR TEIE LL_BDMA_IsEnabledIT_TE
2431 * @param BDMAx BDMA Instance
2432 * @param Channel This parameter can be one of the following values:
2433 * @arg @ref LL_BDMA_CHANNEL_0
2434 * @arg @ref LL_BDMA_CHANNEL_1
2435 * @arg @ref LL_BDMA_CHANNEL_2
2436 * @arg @ref LL_BDMA_CHANNEL_3
2437 * @arg @ref LL_BDMA_CHANNEL_4
2438 * @arg @ref LL_BDMA_CHANNEL_5
2439 * @arg @ref LL_BDMA_CHANNEL_6
2440 * @arg @ref LL_BDMA_CHANNEL_7
2441 * @retval State of bit (1 or 0).
2442 */
2443 __STATIC_INLINE uint32_t LL_BDMA_IsEnabledIT_TE(const BDMA_TypeDef *BDMAx, uint32_t Channel)
2444 {
2445 uint32_t bdma_base_addr = (uint32_t)BDMAx;
2446
2447 return ((READ_BIT(((BDMA_Channel_TypeDef *)(bdma_base_addr + LL_BDMA_CH_OFFSET_TAB[Channel]))->CCR, BDMA_CCR_TEIE) == (BDMA_CCR_TEIE)) ? 1UL : 0UL);
2448 }
2449
2450 /**
2451 * @}
2452 */
2453
2454 #if defined(USE_FULL_LL_DRIVER)
2455 /** @defgroup BDMA_LL_EF_Init Initialization and de-initialization functions
2456 * @{
2457 */
2458
2459 uint32_t LL_BDMA_Init(BDMA_TypeDef *BDMAx, uint32_t Channel, LL_BDMA_InitTypeDef *BDMA_InitStruct);
2460 uint32_t LL_BDMA_DeInit(BDMA_TypeDef *BDMAx, uint32_t Channel);
2461 void LL_BDMA_StructInit(LL_BDMA_InitTypeDef *BDMA_InitStruct);
2462
2463 /**
2464 * @}
2465 */
2466 #endif /* USE_FULL_LL_DRIVER */
2467
2468 /**
2469 * @}
2470 */
2471
2472 /**
2473 * @}
2474 */
2475
2476 #endif /* BDMA || BDMA1 || BDMA2 */
2477 /**
2478 * @}
2479 */
2480
2481 #ifdef __cplusplus
2482 }
2483 #endif
2484
2485 #endif /* STM32H7xx_LL_BDMA_H */
2486
INAV: Navigation-enabled flight control software