| blob | 639565bb466dbc8963096eb7291832ec2f6676c9 |
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma.h
4 * @author MCD Application Team
5 * @brief Header file of DMA LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>© COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMA_H
22 #define STM32H7xx_LL_DMA_H
24 #ifdef __cplusplus
26 #endif
28 /* Includes ------------------------------------------------------------------*/
32 /** @addtogroup STM32H7xx_LL_Driver
33 * @{
34 */
36 #if defined (DMA1) || defined (DMA2)
38 /** @defgroup DMA_LL DMA
39 * @{
40 */
42 /* Private types -------------------------------------------------------------*/
43 /* Private variables ---------------------------------------------------------*/
44 /** @defgroup DMA_LL_Private_Variables DMA Private Variables
45 * @{
46 */
47 /* Array used to get the DMA stream register offset versus stream index LL_DMA_STREAM_x */
49 {
58 };
61 /**
62 * @}
63 */
65 /* Private macros ------------------------------------------------------------*/
67 /**
68 * @brief Helper macro to convert DMA Instance DMAx into DMAMUX channel
69 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
70 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
71 * @param __DMA_INSTANCE__ DMAx
72 * @retval Channel_Offset (LL_DMAMUX_CHANNEL_8 or 0).
73 */
74 #define LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(__DMA_INSTANCE__) \
75 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) ? 0UL : 8UL)
77 /* Exported types ------------------------------------------------------------*/
78 #if defined(USE_FULL_LL_DRIVER)
79 /** @defgroup DMA_LL_ES_INIT DMA Exported Init structure
80 * @{
81 */
83 {
85 or as Source base address in case of memory to memory transfer direction.
87 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
90 or as Destination base address in case of memory to memory transfer direction.
92 This parameter must be a value between Min_Data = 0 and Max_Data = 0xFFFFFFFF. */
95 from memory to memory or from peripheral to memory.
96 This parameter can be a value of @ref DMA_LL_EC_DIRECTION
98 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataTransferDirection(). */
101 This parameter can be a value of @ref DMA_LL_EC_MODE
102 @note The circular buffer mode cannot be used if the memory to memory
103 data transfer direction is configured on the selected Stream
105 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMode(). */
107 uint32_t PeriphOrM2MSrcIncMode; /*!< Specifies whether the Peripheral address or Source address in case of memory to memory transfer direction
108 is incremented or not.
109 This parameter can be a value of @ref DMA_LL_EC_PERIPH
111 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphIncMode(). */
113 uint32_t MemoryOrM2MDstIncMode; /*!< Specifies whether the Memory address or Destination address in case of memory to memory transfer direction
114 is incremented or not.
115 This parameter can be a value of @ref DMA_LL_EC_MEMORY
117 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryIncMode(). */
119 uint32_t PeriphOrM2MSrcDataSize; /*!< Specifies the Peripheral data size alignment or Source data size alignment (byte, half word, word)
120 in case of memory to memory transfer direction.
121 This parameter can be a value of @ref DMA_LL_EC_PDATAALIGN
123 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphSize(). */
125 uint32_t MemoryOrM2MDstDataSize; /*!< Specifies the Memory data size alignment or Destination data size alignment (byte, half word, word)
126 in case of memory to memory transfer direction.
127 This parameter can be a value of @ref DMA_LL_EC_MDATAALIGN
129 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemorySize(). */
132 The data unit is equal to the source buffer configuration set in PeripheralSize
133 or MemorySize parameters depending in the transfer direction.
134 This parameter must be a value between Min_Data = 0 and Max_Data = 0x0000FFFF
136 This feature can be modified afterwards using unitary function @ref LL_DMA_SetDataLength(). */
139 This parameter can be a value of @ref DMAMUX_LL_EC_REQUEST
141 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphRequest(). */
144 This parameter can be a value of @ref DMA_LL_EC_PRIORITY
146 This feature can be modified afterwards using unitary function @ref LL_DMA_SetStreamPriorityLevel(). */
148 uint32_t FIFOMode; /*!< Specifies if the FIFO mode or Direct mode will be used for the specified stream.
149 This parameter can be a value of @ref DMA_LL_FIFOMODE
150 @note The Direct mode (FIFO mode disabled) cannot be used if the
151 memory-to-memory data transfer is configured on the selected stream
153 This feature can be modified afterwards using unitary functions @ref LL_DMA_EnableFifoMode() or @ref LL_DMA_EnableFifoMode() . */
156 This parameter can be a value of @ref DMA_LL_EC_FIFOTHRESHOLD
158 This feature can be modified afterwards using unitary function @ref LL_DMA_SetFIFOThreshold(). */
161 It specifies the amount of data to be transferred in a single non interruptible
162 transaction.
163 This parameter can be a value of @ref DMA_LL_EC_MBURST
164 @note The burst mode is possible only if the address Increment mode is enabled.
166 This feature can be modified afterwards using unitary function @ref LL_DMA_SetMemoryBurstxfer(). */
168 uint32_t PeriphBurst; /*!< Specifies the Burst transfer configuration for the peripheral transfers.
169 It specifies the amount of data to be transferred in a single non interruptible
170 transaction.
171 This parameter can be a value of @ref DMA_LL_EC_PBURST
172 @note The burst mode is possible only if the address Increment mode is enabled.
174 This feature can be modified afterwards using unitary function @ref LL_DMA_SetPeriphBurstxfer(). */
177 /**
178 * @}
179 */
181 /* Exported constants --------------------------------------------------------*/
182 /** @defgroup DMA_LL_Exported_Constants DMA Exported Constants
183 * @{
184 */
186 /** @defgroup DMA_LL_EC_STREAM STREAM
187 * @{
188 */
189 #define LL_DMA_STREAM_0 0x00000000U
190 #define LL_DMA_STREAM_1 0x00000001U
191 #define LL_DMA_STREAM_2 0x00000002U
192 #define LL_DMA_STREAM_3 0x00000003U
193 #define LL_DMA_STREAM_4 0x00000004U
194 #define LL_DMA_STREAM_5 0x00000005U
195 #define LL_DMA_STREAM_6 0x00000006U
196 #define LL_DMA_STREAM_7 0x00000007U
197 #define LL_DMA_STREAM_ALL 0xFFFF0000U
198 /**
199 * @}
200 */
203 /** @defgroup DMA_LL_EC_DIRECTION DIRECTION
204 * @{
205 */
209 /**
210 * @}
211 */
213 /** @defgroup DMA_LL_EC_MODE MODE
214 * @{
215 */
219 /**
220 * @}
221 */
223 /** @defgroup DMA_LL_EC_DOUBLEBUFFER_MODE DOUBLE BUFFER MODE
224 * @{
225 */
228 /**
229 * @}
230 */
232 /** @defgroup DMA_LL_EC_PERIPH PERIPH
233 * @{
234 */
237 /**
238 * @}
239 */
241 /** @defgroup DMA_LL_EC_MEMORY MEMORY
242 * @{
243 */
246 /**
247 * @}
248 */
250 /** @defgroup DMA_LL_EC_PDATAALIGN PDATAALIGN
251 * @{
252 */
254 #define LL_DMA_PDATAALIGN_HALFWORD DMA_SxCR_PSIZE_0 /*!< Peripheral data alignment : HalfWord */
256 /**
257 * @}
258 */
260 /** @defgroup DMA_LL_EC_MDATAALIGN MDATAALIGN
261 * @{
262 */
266 /**
267 * @}
268 */
270 /** @defgroup DMA_LL_EC_OFFSETSIZE OFFSETSIZE
271 * @{
272 */
273 #define LL_DMA_OFFSETSIZE_PSIZE 0x00000000U /*!< Peripheral increment offset size is linked to the PSIZE */
274 #define LL_DMA_OFFSETSIZE_FIXEDTO4 DMA_SxCR_PINCOS /*!< Peripheral increment offset size is fixed to 4 (32-bit alignment) */
275 /**
276 * @}
277 */
279 /** @defgroup DMA_LL_EC_PRIORITY PRIORITY
280 * @{
281 */
286 /**
287 * @}
288 */
291 /** @defgroup DMA_LL_EC_MBURST MBURST
292 * @{
293 */
295 #define LL_DMA_MBURST_INC4 DMA_SxCR_MBURST_0 /*!< Memory burst of 4 beats transfer configuration */
296 #define LL_DMA_MBURST_INC8 DMA_SxCR_MBURST_1 /*!< Memory burst of 8 beats transfer configuration */
297 #define LL_DMA_MBURST_INC16 (DMA_SxCR_MBURST_0 | DMA_SxCR_MBURST_1) /*!< Memory burst of 16 beats transfer configuration */
298 /**
299 * @}
300 */
302 /** @defgroup DMA_LL_EC_PBURST PBURST
303 * @{
304 */
306 #define LL_DMA_PBURST_INC4 DMA_SxCR_PBURST_0 /*!< Peripheral burst of 4 beats transfer configuration */
307 #define LL_DMA_PBURST_INC8 DMA_SxCR_PBURST_1 /*!< Peripheral burst of 8 beats transfer configuration */
308 #define LL_DMA_PBURST_INC16 (DMA_SxCR_PBURST_0 | DMA_SxCR_PBURST_1) /*!< Peripheral burst of 16 beats transfer configuration */
309 /**
310 * @}
311 */
313 /** @defgroup DMA_LL_FIFOMODE DMA_LL_FIFOMODE
314 * @{
315 */
318 /**
319 * @}
320 */
322 /** @defgroup DMA_LL_EC_FIFOSTATUS_0 FIFOSTATUS 0
323 * @{
324 */
328 #define LL_DMA_FIFOSTATUS_75_100 (DMA_SxFCR_FS_1 | DMA_SxFCR_FS_0) /*!< 3/4 < fifo_level < full */
331 /**
332 * @}
333 */
335 /** @defgroup DMA_LL_EC_FIFOTHRESHOLD FIFOTHRESHOLD
336 * @{
337 */
340 #define LL_DMA_FIFOTHRESHOLD_3_4 DMA_SxFCR_FTH_1 /*!< FIFO threshold 3 quarts full configuration */
342 /**
343 * @}
344 */
346 /** @defgroup DMA_LL_EC_CURRENTTARGETMEM CURRENTTARGETMEM
347 * @{
348 */
351 /**
352 * @}
353 */
355 /**
356 * @}
357 */
359 /* Exported macro ------------------------------------------------------------*/
360 /** @defgroup DMA_LL_Exported_Macros DMA Exported Macros
361 * @{
362 */
364 /** @defgroup DMA_LL_EM_WRITE_READ Common Write and read registers macros
365 * @{
366 */
367 /**
368 * @brief Write a value in DMA register
369 * @param __INSTANCE__ DMA Instance
370 * @param __REG__ Register to be written
371 * @param __VALUE__ Value to be written in the register
372 * @retval None
373 */
374 #define LL_DMA_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
376 /**
377 * @brief Read a value in DMA register
378 * @param __INSTANCE__ DMA Instance
379 * @param __REG__ Register to be read
380 * @retval Register value
381 */
382 #define LL_DMA_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
383 /**
384 * @}
385 */
387 /** @defgroup DMA_LL_EM_CONVERT_DMAxCHANNELy Convert DMAxStreamy
388 * @{
389 */
390 /**
391 * @brief Convert DMAx_Streamy into DMAx
392 * @param __STREAM_INSTANCE__ DMAx_Streamy
393 * @retval DMAx
394 */
395 #define __LL_DMA_GET_INSTANCE(__STREAM_INSTANCE__) \
396 (((uint32_t)(__STREAM_INSTANCE__) > ((uint32_t)DMA1_Stream7)) ? DMA2 : DMA1)
398 /**
399 * @brief Convert DMAx_Streamy into LL_DMA_STREAM_y
400 * @param __STREAM_INSTANCE__ DMAx_Streamy
401 * @retval LL_DMA_STREAM_y
402 */
403 #define __LL_DMA_GET_STREAM(__STREAM_INSTANCE__) \
404 (((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream0)) ? LL_DMA_STREAM_0 : \
405 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream0)) ? LL_DMA_STREAM_0 : \
406 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream1)) ? LL_DMA_STREAM_1 : \
407 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream1)) ? LL_DMA_STREAM_1 : \
408 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream2)) ? LL_DMA_STREAM_2 : \
409 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream2)) ? LL_DMA_STREAM_2 : \
410 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream3)) ? LL_DMA_STREAM_3 : \
411 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream3)) ? LL_DMA_STREAM_3 : \
412 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream4)) ? LL_DMA_STREAM_4 : \
413 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream4)) ? LL_DMA_STREAM_4 : \
414 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream5)) ? LL_DMA_STREAM_5 : \
415 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream5)) ? LL_DMA_STREAM_5 : \
416 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA1_Stream6)) ? LL_DMA_STREAM_6 : \
417 ((uint32_t)(__STREAM_INSTANCE__) == ((uint32_t)DMA2_Stream6)) ? LL_DMA_STREAM_6 : \
418 LL_DMA_STREAM_7)
420 /**
421 * @brief Convert DMA Instance DMAx and LL_DMA_STREAM_y into DMAx_Streamy
422 * @param __DMA_INSTANCE__ DMAx
423 * @param __STREAM__ LL_DMA_STREAM_y
424 * @retval DMAx_Streamy
425 */
426 #define __LL_DMA_GET_STREAM_INSTANCE(__DMA_INSTANCE__, __STREAM__) \
427 ((((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA1_Stream0 : \
428 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_0))) ? DMA2_Stream0 : \
429 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA1_Stream1 : \
430 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_1))) ? DMA2_Stream1 : \
431 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA1_Stream2 : \
432 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_2))) ? DMA2_Stream2 : \
433 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA1_Stream3 : \
434 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_3))) ? DMA2_Stream3 : \
435 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA1_Stream4 : \
436 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_4))) ? DMA2_Stream4 : \
437 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA1_Stream5 : \
438 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_5))) ? DMA2_Stream5 : \
439 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA1_Stream6 : \
440 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA2)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_6))) ? DMA2_Stream6 : \
441 (((uint32_t)(__DMA_INSTANCE__) == ((uint32_t)DMA1)) && ((uint32_t)(__STREAM__) == ((uint32_t)LL_DMA_STREAM_7))) ? DMA1_Stream7 : \
442 DMA2_Stream7)
444 /**
445 * @}
446 */
448 /**
449 * @}
450 */
453 /* Exported functions --------------------------------------------------------*/
454 /** @defgroup DMA_LL_Exported_Functions DMA Exported Functions
455 * @{
456 */
458 /** @defgroup DMA_LL_EF_Configuration Configuration
459 * @{
460 */
461 /**
462 * @brief Enable DMA stream.
463 * @rmtoll CR EN LL_DMA_EnableStream
464 * @param DMAx DMAx Instance
465 * @param Stream This parameter can be one of the following values:
466 * @arg @ref LL_DMA_STREAM_0
467 * @arg @ref LL_DMA_STREAM_1
468 * @arg @ref LL_DMA_STREAM_2
469 * @arg @ref LL_DMA_STREAM_3
470 * @arg @ref LL_DMA_STREAM_4
471 * @arg @ref LL_DMA_STREAM_5
472 * @arg @ref LL_DMA_STREAM_6
473 * @arg @ref LL_DMA_STREAM_7
474 * @retval None
475 */
477 {
480 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
481 }
483 /**
484 * @brief Disable DMA stream.
485 * @rmtoll CR EN LL_DMA_DisableStream
486 * @param DMAx DMAx Instance
487 * @param Stream This parameter can be one of the following values:
488 * @arg @ref LL_DMA_STREAM_0
489 * @arg @ref LL_DMA_STREAM_1
490 * @arg @ref LL_DMA_STREAM_2
491 * @arg @ref LL_DMA_STREAM_3
492 * @arg @ref LL_DMA_STREAM_4
493 * @arg @ref LL_DMA_STREAM_5
494 * @arg @ref LL_DMA_STREAM_6
495 * @arg @ref LL_DMA_STREAM_7
496 * @retval None
497 */
499 {
502 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN);
503 }
505 /**
506 * @brief Check if DMA stream is enabled or disabled.
507 * @rmtoll CR EN LL_DMA_IsEnabledStream
508 * @param DMAx DMAx Instance
509 * @param Stream This parameter can be one of the following values:
510 * @arg @ref LL_DMA_STREAM_0
511 * @arg @ref LL_DMA_STREAM_1
512 * @arg @ref LL_DMA_STREAM_2
513 * @arg @ref LL_DMA_STREAM_3
514 * @arg @ref LL_DMA_STREAM_4
515 * @arg @ref LL_DMA_STREAM_5
516 * @arg @ref LL_DMA_STREAM_6
517 * @arg @ref LL_DMA_STREAM_7
518 * @retval State of bit (1 or 0).
519 */
521 {
524 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_EN) == (DMA_SxCR_EN)) ? 1UL : 0UL);
525 }
527 /**
528 * @brief Configure all parameters linked to DMA transfer.
529 * @rmtoll CR DIR LL_DMA_ConfigTransfer\n
530 * CR CIRC LL_DMA_ConfigTransfer\n
531 * CR PINC LL_DMA_ConfigTransfer\n
532 * CR MINC LL_DMA_ConfigTransfer\n
533 * CR PSIZE LL_DMA_ConfigTransfer\n
534 * CR MSIZE LL_DMA_ConfigTransfer\n
535 * CR PL LL_DMA_ConfigTransfer\n
536 * CR PFCTRL LL_DMA_ConfigTransfer
537 * @param DMAx DMAx Instance
538 * @param Stream This parameter can be one of the following values:
539 * @arg @ref LL_DMA_STREAM_0
540 * @arg @ref LL_DMA_STREAM_1
541 * @arg @ref LL_DMA_STREAM_2
542 * @arg @ref LL_DMA_STREAM_3
543 * @arg @ref LL_DMA_STREAM_4
544 * @arg @ref LL_DMA_STREAM_5
545 * @arg @ref LL_DMA_STREAM_6
546 * @arg @ref LL_DMA_STREAM_7
547 * @param Configuration This parameter must be a combination of all the following values:
548 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY or @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH or @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
549 * @arg @ref LL_DMA_MODE_NORMAL or @ref LL_DMA_MODE_CIRCULAR or @ref LL_DMA_MODE_PFCTRL
550 * @arg @ref LL_DMA_PERIPH_INCREMENT or @ref LL_DMA_PERIPH_NOINCREMENT
551 * @arg @ref LL_DMA_MEMORY_INCREMENT or @ref LL_DMA_MEMORY_NOINCREMENT
552 * @arg @ref LL_DMA_PDATAALIGN_BYTE or @ref LL_DMA_PDATAALIGN_HALFWORD or @ref LL_DMA_PDATAALIGN_WORD
553 * @arg @ref LL_DMA_MDATAALIGN_BYTE or @ref LL_DMA_MDATAALIGN_HALFWORD or @ref LL_DMA_MDATAALIGN_WORD
554 * @arg @ref LL_DMA_PRIORITY_LOW or @ref LL_DMA_PRIORITY_MEDIUM or @ref LL_DMA_PRIORITY_HIGH or @ref LL_DMA_PRIORITY_VERYHIGH
555 *@retval None
556 */
557 __STATIC_INLINE void LL_DMA_ConfigTransfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Configuration)
558 {
562 DMA_SxCR_DIR | DMA_SxCR_CIRC | DMA_SxCR_PINC | DMA_SxCR_MINC | DMA_SxCR_PSIZE | DMA_SxCR_MSIZE | DMA_SxCR_PL | DMA_SxCR_PFCTRL,
563 Configuration);
564 }
566 /**
567 * @brief Set Data transfer direction (read from peripheral or from memory).
568 * @rmtoll CR DIR LL_DMA_SetDataTransferDirection
569 * @param DMAx DMAx Instance
570 * @param Stream This parameter can be one of the following values:
571 * @arg @ref LL_DMA_STREAM_0
572 * @arg @ref LL_DMA_STREAM_1
573 * @arg @ref LL_DMA_STREAM_2
574 * @arg @ref LL_DMA_STREAM_3
575 * @arg @ref LL_DMA_STREAM_4
576 * @arg @ref LL_DMA_STREAM_5
577 * @arg @ref LL_DMA_STREAM_6
578 * @arg @ref LL_DMA_STREAM_7
579 * @param Direction This parameter can be one of the following values:
580 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
581 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
582 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
583 * @retval None
584 */
585 __STATIC_INLINE void LL_DMA_SetDataTransferDirection(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Direction)
586 {
589 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR, Direction);
590 }
592 /**
593 * @brief Get Data transfer direction (read from peripheral or from memory).
594 * @rmtoll CR DIR LL_DMA_GetDataTransferDirection
595 * @param DMAx DMAx Instance
596 * @param Stream This parameter can be one of the following values:
597 * @arg @ref LL_DMA_STREAM_0
598 * @arg @ref LL_DMA_STREAM_1
599 * @arg @ref LL_DMA_STREAM_2
600 * @arg @ref LL_DMA_STREAM_3
601 * @arg @ref LL_DMA_STREAM_4
602 * @arg @ref LL_DMA_STREAM_5
603 * @arg @ref LL_DMA_STREAM_6
604 * @arg @ref LL_DMA_STREAM_7
605 * @retval Returned value can be one of the following values:
606 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
607 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
608 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
609 */
611 {
614 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DIR));
615 }
617 /**
618 * @brief Set DMA mode normal, circular or peripheral flow control.
619 * @rmtoll CR CIRC LL_DMA_SetMode\n
620 * CR PFCTRL LL_DMA_SetMode
621 * @param DMAx DMAx Instance
622 * @param Stream This parameter can be one of the following values:
623 * @arg @ref LL_DMA_STREAM_0
624 * @arg @ref LL_DMA_STREAM_1
625 * @arg @ref LL_DMA_STREAM_2
626 * @arg @ref LL_DMA_STREAM_3
627 * @arg @ref LL_DMA_STREAM_4
628 * @arg @ref LL_DMA_STREAM_5
629 * @arg @ref LL_DMA_STREAM_6
630 * @arg @ref LL_DMA_STREAM_7
631 * @param Mode This parameter can be one of the following values:
632 * @arg @ref LL_DMA_MODE_NORMAL
633 * @arg @ref LL_DMA_MODE_CIRCULAR
634 * @arg @ref LL_DMA_MODE_PFCTRL
635 * @retval None
636 */
638 {
641 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL, Mode);
642 }
644 /**
645 * @brief Get DMA mode normal, circular or peripheral flow control.
646 * @rmtoll CR CIRC LL_DMA_GetMode\n
647 * CR PFCTRL LL_DMA_GetMode
648 * @param DMAx DMAx Instance
649 * @param Stream This parameter can be one of the following values:
650 * @arg @ref LL_DMA_STREAM_0
651 * @arg @ref LL_DMA_STREAM_1
652 * @arg @ref LL_DMA_STREAM_2
653 * @arg @ref LL_DMA_STREAM_3
654 * @arg @ref LL_DMA_STREAM_4
655 * @arg @ref LL_DMA_STREAM_5
656 * @arg @ref LL_DMA_STREAM_6
657 * @arg @ref LL_DMA_STREAM_7
658 * @retval Returned value can be one of the following values:
659 * @arg @ref LL_DMA_MODE_NORMAL
660 * @arg @ref LL_DMA_MODE_CIRCULAR
661 * @arg @ref LL_DMA_MODE_PFCTRL
662 */
664 {
667 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CIRC | DMA_SxCR_PFCTRL));
668 }
670 /**
671 * @brief Set Peripheral increment mode.
672 * @rmtoll CR PINC LL_DMA_SetPeriphIncMode
673 * @param DMAx DMAx Instance
674 * @param Stream This parameter can be one of the following values:
675 * @arg @ref LL_DMA_STREAM_0
676 * @arg @ref LL_DMA_STREAM_1
677 * @arg @ref LL_DMA_STREAM_2
678 * @arg @ref LL_DMA_STREAM_3
679 * @arg @ref LL_DMA_STREAM_4
680 * @arg @ref LL_DMA_STREAM_5
681 * @arg @ref LL_DMA_STREAM_6
682 * @arg @ref LL_DMA_STREAM_7
683 * @param IncrementMode This parameter can be one of the following values:
684 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
685 * @arg @ref LL_DMA_PERIPH_INCREMENT
686 * @retval None
687 */
688 __STATIC_INLINE void LL_DMA_SetPeriphIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
689 {
692 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC, IncrementMode);
693 }
695 /**
696 * @brief Get Peripheral increment mode.
697 * @rmtoll CR PINC LL_DMA_GetPeriphIncMode
698 * @param DMAx DMAx Instance
699 * @param Stream This parameter can be one of the following values:
700 * @arg @ref LL_DMA_STREAM_0
701 * @arg @ref LL_DMA_STREAM_1
702 * @arg @ref LL_DMA_STREAM_2
703 * @arg @ref LL_DMA_STREAM_3
704 * @arg @ref LL_DMA_STREAM_4
705 * @arg @ref LL_DMA_STREAM_5
706 * @arg @ref LL_DMA_STREAM_6
707 * @arg @ref LL_DMA_STREAM_7
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DMA_PERIPH_NOINCREMENT
710 * @arg @ref LL_DMA_PERIPH_INCREMENT
711 */
713 {
716 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINC));
717 }
719 /**
720 * @brief Set Memory increment mode.
721 * @rmtoll CR MINC LL_DMA_SetMemoryIncMode
722 * @param DMAx DMAx Instance
723 * @param Stream This parameter can be one of the following values:
724 * @arg @ref LL_DMA_STREAM_0
725 * @arg @ref LL_DMA_STREAM_1
726 * @arg @ref LL_DMA_STREAM_2
727 * @arg @ref LL_DMA_STREAM_3
728 * @arg @ref LL_DMA_STREAM_4
729 * @arg @ref LL_DMA_STREAM_5
730 * @arg @ref LL_DMA_STREAM_6
731 * @arg @ref LL_DMA_STREAM_7
732 * @param IncrementMode This parameter can be one of the following values:
733 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
734 * @arg @ref LL_DMA_MEMORY_INCREMENT
735 * @retval None
736 */
737 __STATIC_INLINE void LL_DMA_SetMemoryIncMode(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t IncrementMode)
738 {
741 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC, IncrementMode);
742 }
744 /**
745 * @brief Get Memory increment mode.
746 * @rmtoll CR MINC LL_DMA_GetMemoryIncMode
747 * @param DMAx DMAx Instance
748 * @param Stream This parameter can be one of the following values:
749 * @arg @ref LL_DMA_STREAM_0
750 * @arg @ref LL_DMA_STREAM_1
751 * @arg @ref LL_DMA_STREAM_2
752 * @arg @ref LL_DMA_STREAM_3
753 * @arg @ref LL_DMA_STREAM_4
754 * @arg @ref LL_DMA_STREAM_5
755 * @arg @ref LL_DMA_STREAM_6
756 * @arg @ref LL_DMA_STREAM_7
757 * @retval Returned value can be one of the following values:
758 * @arg @ref LL_DMA_MEMORY_NOINCREMENT
759 * @arg @ref LL_DMA_MEMORY_INCREMENT
760 */
762 {
765 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MINC));
766 }
768 /**
769 * @brief Set Peripheral size.
770 * @rmtoll CR PSIZE LL_DMA_SetPeriphSize
771 * @param DMAx DMAx Instance
772 * @param Stream This parameter can be one of the following values:
773 * @arg @ref LL_DMA_STREAM_0
774 * @arg @ref LL_DMA_STREAM_1
775 * @arg @ref LL_DMA_STREAM_2
776 * @arg @ref LL_DMA_STREAM_3
777 * @arg @ref LL_DMA_STREAM_4
778 * @arg @ref LL_DMA_STREAM_5
779 * @arg @ref LL_DMA_STREAM_6
780 * @arg @ref LL_DMA_STREAM_7
781 * @param Size This parameter can be one of the following values:
782 * @arg @ref LL_DMA_PDATAALIGN_BYTE
783 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
784 * @arg @ref LL_DMA_PDATAALIGN_WORD
785 * @retval None
786 */
788 {
791 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE, Size);
792 }
794 /**
795 * @brief Get Peripheral size.
796 * @rmtoll CR PSIZE LL_DMA_GetPeriphSize
797 * @param DMAx DMAx Instance
798 * @param Stream This parameter can be one of the following values:
799 * @arg @ref LL_DMA_STREAM_0
800 * @arg @ref LL_DMA_STREAM_1
801 * @arg @ref LL_DMA_STREAM_2
802 * @arg @ref LL_DMA_STREAM_3
803 * @arg @ref LL_DMA_STREAM_4
804 * @arg @ref LL_DMA_STREAM_5
805 * @arg @ref LL_DMA_STREAM_6
806 * @arg @ref LL_DMA_STREAM_7
807 * @retval Returned value can be one of the following values:
808 * @arg @ref LL_DMA_PDATAALIGN_BYTE
809 * @arg @ref LL_DMA_PDATAALIGN_HALFWORD
810 * @arg @ref LL_DMA_PDATAALIGN_WORD
811 */
813 {
816 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PSIZE));
817 }
819 /**
820 * @brief Set Memory size.
821 * @rmtoll CR MSIZE LL_DMA_SetMemorySize
822 * @param DMAx DMAx Instance
823 * @param Stream This parameter can be one of the following values:
824 * @arg @ref LL_DMA_STREAM_0
825 * @arg @ref LL_DMA_STREAM_1
826 * @arg @ref LL_DMA_STREAM_2
827 * @arg @ref LL_DMA_STREAM_3
828 * @arg @ref LL_DMA_STREAM_4
829 * @arg @ref LL_DMA_STREAM_5
830 * @arg @ref LL_DMA_STREAM_6
831 * @arg @ref LL_DMA_STREAM_7
832 * @param Size This parameter can be one of the following values:
833 * @arg @ref LL_DMA_MDATAALIGN_BYTE
834 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
835 * @arg @ref LL_DMA_MDATAALIGN_WORD
836 * @retval None
837 */
839 {
842 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE, Size);
843 }
845 /**
846 * @brief Get Memory size.
847 * @rmtoll CR MSIZE LL_DMA_GetMemorySize
848 * @param DMAx DMAx Instance
849 * @param Stream This parameter can be one of the following values:
850 * @arg @ref LL_DMA_STREAM_0
851 * @arg @ref LL_DMA_STREAM_1
852 * @arg @ref LL_DMA_STREAM_2
853 * @arg @ref LL_DMA_STREAM_3
854 * @arg @ref LL_DMA_STREAM_4
855 * @arg @ref LL_DMA_STREAM_5
856 * @arg @ref LL_DMA_STREAM_6
857 * @arg @ref LL_DMA_STREAM_7
858 * @retval Returned value can be one of the following values:
859 * @arg @ref LL_DMA_MDATAALIGN_BYTE
860 * @arg @ref LL_DMA_MDATAALIGN_HALFWORD
861 * @arg @ref LL_DMA_MDATAALIGN_WORD
862 */
864 {
867 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MSIZE));
868 }
870 /**
871 * @brief Set Peripheral increment offset size.
872 * @rmtoll CR PINCOS LL_DMA_SetIncOffsetSize
873 * @param DMAx DMAx Instance
874 * @param Stream This parameter can be one of the following values:
875 * @arg @ref LL_DMA_STREAM_0
876 * @arg @ref LL_DMA_STREAM_1
877 * @arg @ref LL_DMA_STREAM_2
878 * @arg @ref LL_DMA_STREAM_3
879 * @arg @ref LL_DMA_STREAM_4
880 * @arg @ref LL_DMA_STREAM_5
881 * @arg @ref LL_DMA_STREAM_6
882 * @arg @ref LL_DMA_STREAM_7
883 * @param OffsetSize This parameter can be one of the following values:
884 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
885 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
886 * @retval None
887 */
888 __STATIC_INLINE void LL_DMA_SetIncOffsetSize(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t OffsetSize)
889 {
892 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS, OffsetSize);
893 }
895 /**
896 * @brief Get Peripheral increment offset size.
897 * @rmtoll CR PINCOS LL_DMA_GetIncOffsetSize
898 * @param DMAx DMAx Instance
899 * @param Stream This parameter can be one of the following values:
900 * @arg @ref LL_DMA_STREAM_0
901 * @arg @ref LL_DMA_STREAM_1
902 * @arg @ref LL_DMA_STREAM_2
903 * @arg @ref LL_DMA_STREAM_3
904 * @arg @ref LL_DMA_STREAM_4
905 * @arg @ref LL_DMA_STREAM_5
906 * @arg @ref LL_DMA_STREAM_6
907 * @arg @ref LL_DMA_STREAM_7
908 * @retval Returned value can be one of the following values:
909 * @arg @ref LL_DMA_OFFSETSIZE_PSIZE
910 * @arg @ref LL_DMA_OFFSETSIZE_FIXEDTO4
911 */
913 {
916 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PINCOS));
917 }
919 /**
920 * @brief Set Stream priority level.
921 * @rmtoll CR PL LL_DMA_SetStreamPriorityLevel
922 * @param DMAx DMAx Instance
923 * @param Stream This parameter can be one of the following values:
924 * @arg @ref LL_DMA_STREAM_0
925 * @arg @ref LL_DMA_STREAM_1
926 * @arg @ref LL_DMA_STREAM_2
927 * @arg @ref LL_DMA_STREAM_3
928 * @arg @ref LL_DMA_STREAM_4
929 * @arg @ref LL_DMA_STREAM_5
930 * @arg @ref LL_DMA_STREAM_6
931 * @arg @ref LL_DMA_STREAM_7
932 * @param Priority This parameter can be one of the following values:
933 * @arg @ref LL_DMA_PRIORITY_LOW
934 * @arg @ref LL_DMA_PRIORITY_MEDIUM
935 * @arg @ref LL_DMA_PRIORITY_HIGH
936 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
937 * @retval None
938 */
939 __STATIC_INLINE void LL_DMA_SetStreamPriorityLevel(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Priority)
940 {
943 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL, Priority);
944 }
946 /**
947 * @brief Get Stream priority level.
948 * @rmtoll CR PL LL_DMA_GetStreamPriorityLevel
949 * @param DMAx DMAx Instance
950 * @param Stream This parameter can be one of the following values:
951 * @arg @ref LL_DMA_STREAM_0
952 * @arg @ref LL_DMA_STREAM_1
953 * @arg @ref LL_DMA_STREAM_2
954 * @arg @ref LL_DMA_STREAM_3
955 * @arg @ref LL_DMA_STREAM_4
956 * @arg @ref LL_DMA_STREAM_5
957 * @arg @ref LL_DMA_STREAM_6
958 * @arg @ref LL_DMA_STREAM_7
959 * @retval Returned value can be one of the following values:
960 * @arg @ref LL_DMA_PRIORITY_LOW
961 * @arg @ref LL_DMA_PRIORITY_MEDIUM
962 * @arg @ref LL_DMA_PRIORITY_HIGH
963 * @arg @ref LL_DMA_PRIORITY_VERYHIGH
964 */
966 {
969 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PL));
970 }
972 /**
973 * @brief Set Number of data to transfer.
974 * @rmtoll NDTR NDT LL_DMA_SetDataLength
975 * @note This action has no effect if
976 * stream is enabled.
977 * @param DMAx DMAx Instance
978 * @param Stream This parameter can be one of the following values:
979 * @arg @ref LL_DMA_STREAM_0
980 * @arg @ref LL_DMA_STREAM_1
981 * @arg @ref LL_DMA_STREAM_2
982 * @arg @ref LL_DMA_STREAM_3
983 * @arg @ref LL_DMA_STREAM_4
984 * @arg @ref LL_DMA_STREAM_5
985 * @arg @ref LL_DMA_STREAM_6
986 * @arg @ref LL_DMA_STREAM_7
987 * @param NbData Between 0 to 0xFFFFFFFF
988 * @retval None
989 */
991 {
994 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT, NbData);
995 }
997 /**
998 * @brief Get Number of data to transfer.
999 * @rmtoll NDTR NDT LL_DMA_GetDataLength
1000 * @note Once the stream is enabled, the return value indicate the
1001 * remaining bytes to be transmitted.
1002 * @param DMAx DMAx Instance
1003 * @param Stream This parameter can be one of the following values:
1004 * @arg @ref LL_DMA_STREAM_0
1005 * @arg @ref LL_DMA_STREAM_1
1006 * @arg @ref LL_DMA_STREAM_2
1007 * @arg @ref LL_DMA_STREAM_3
1008 * @arg @ref LL_DMA_STREAM_4
1009 * @arg @ref LL_DMA_STREAM_5
1010 * @arg @ref LL_DMA_STREAM_6
1011 * @arg @ref LL_DMA_STREAM_7
1012 * @retval Between 0 to 0xFFFFFFFF
1013 */
1015 {
1018 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->NDTR, DMA_SxNDT));
1019 }
1020 /**
1021 * @brief Set DMA request for DMA Streams on DMAMUX Channel x.
1022 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1023 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1024 * @rmtoll CxCR DMAREQ_ID LL_DMA_SetPeriphRequest
1025 * @param DMAx DMAx Instance
1026 * @param Stream This parameter can be one of the following values:
1027 * @arg @ref LL_DMA_STREAM_0
1028 * @arg @ref LL_DMA_STREAM_1
1029 * @arg @ref LL_DMA_STREAM_2
1030 * @arg @ref LL_DMA_STREAM_3
1031 * @arg @ref LL_DMA_STREAM_4
1032 * @arg @ref LL_DMA_STREAM_5
1033 * @arg @ref LL_DMA_STREAM_6
1034 * @arg @ref LL_DMA_STREAM_7
1035 * @param Request This parameter can be one of the following values:
1036 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1037 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1038 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1039 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1040 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1041 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1042 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1043 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1044 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1045 * @arg @ref LL_DMAMUX1_REQ_ADC1
1046 * @arg @ref LL_DMAMUX1_REQ_ADC2
1047 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1048 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1049 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1050 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1051 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1052 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1053 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1054 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1055 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1056 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1057 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1058 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1059 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1060 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1061 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1062 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1063 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1064 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1065 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1066 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1067 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1068 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1069 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1070 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1071 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1072 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1073 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1074 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1075 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1076 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1077 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1078 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1079 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1080 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1081 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1082 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1083 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1084 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1085 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1086 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1087 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1088 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1089 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1090 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1091 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1092 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1093 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1094 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1095 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1096 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1097 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1098 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1099 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1100 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1101 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1102 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1103 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1104 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1105 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1106 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1107 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1108 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1109 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1110 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
1111 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1112 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1113 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1114 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1115 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1116 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1117 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1118 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1119 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1120 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1121 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1122 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1123 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1124 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
1125 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
1126 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1127 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1128 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1129 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1130 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1131 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1132 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1133 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1134 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1135 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1136 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1137 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1138 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1139 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1140 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1141 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1142 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1143 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1144 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1145 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1146 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1147 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1148 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1149 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1150 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1151 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1152 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1153 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1154 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1155 * @note (*) Availability depends on devices.
1156 * @retval None
1157 */
1158 __STATIC_INLINE void LL_DMA_SetPeriphRequest(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Request)
1159 {
1160 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
1161 }
1163 /**
1164 * @brief Get DMA request for DMA Channels on DMAMUX Channel x.
1165 * @note DMAMUX channel 0 to 7 are mapped to DMA1 stream 0 to 7.
1166 * DMAMUX channel 8 to 15 are mapped to DMA2 stream 0 to 7.
1167 * @rmtoll CxCR DMAREQ_ID LL_DMA_GetPeriphRequest
1168 * @param DMAx DMAx Instance
1169 * @param Stream This parameter can be one of the following values:
1170 * @arg @ref LL_DMA_STREAM_0
1171 * @arg @ref LL_DMA_STREAM_1
1172 * @arg @ref LL_DMA_STREAM_2
1173 * @arg @ref LL_DMA_STREAM_3
1174 * @arg @ref LL_DMA_STREAM_4
1175 * @arg @ref LL_DMA_STREAM_5
1176 * @arg @ref LL_DMA_STREAM_6
1177 * @arg @ref LL_DMA_STREAM_7
1178 * @retval Returned value can be one of the following values:
1179 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
1180 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
1181 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
1182 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
1183 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
1184 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
1185 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
1186 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
1187 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
1188 * @arg @ref LL_DMAMUX1_REQ_ADC1
1189 * @arg @ref LL_DMAMUX1_REQ_ADC2
1190 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
1191 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
1192 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
1193 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
1194 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
1195 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
1196 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
1197 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
1198 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
1199 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
1200 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
1201 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
1202 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
1203 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
1204 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
1205 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
1206 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
1207 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
1208 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
1209 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
1210 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
1211 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
1212 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
1213 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
1214 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
1215 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
1216 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
1217 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
1218 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
1219 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
1220 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
1221 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
1222 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
1223 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
1224 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
1225 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
1226 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
1227 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
1228 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
1229 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
1230 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
1231 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
1232 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
1233 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
1234 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
1235 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
1236 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
1237 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
1238 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
1239 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
1240 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
1241 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
1242 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
1243 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
1244 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
1245 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
1246 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
1247 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
1248 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
1249 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
1250 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
1251 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
1252 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
1253 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
1254 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
1255 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
1256 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
1257 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
1258 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
1259 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
1260 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
1261 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
1262 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
1263 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
1264 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
1265 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
1266 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
1267 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
1268 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
1269 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
1270 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
1271 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
1272 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
1273 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
1274 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
1275 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
1276 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
1277 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
1278 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
1279 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
1280 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
1281 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
1282 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
1283 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
1284 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
1285 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
1286 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
1287 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
1288 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
1289 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
1290 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
1291 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
1292 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
1293 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
1294 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1295 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
1296 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1297 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
1298 * @note (*) Availability depends on devices.
1299 */
1301 {
1302 return (READ_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)((uint32_t)DMAMUX1_Channel0 + (DMAMUX_CCR_SIZE * (Stream)) + (uint32_t)(DMAMUX_CCR_SIZE * LL_DMA_INSTANCE_TO_DMAMUX_CHANNEL(DMAx)))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
1303 }
1305 /**
1306 * @brief Set Memory burst transfer configuration.
1307 * @rmtoll CR MBURST LL_DMA_SetMemoryBurstxfer
1308 * @param DMAx DMAx Instance
1309 * @param Stream This parameter can be one of the following values:
1310 * @arg @ref LL_DMA_STREAM_0
1311 * @arg @ref LL_DMA_STREAM_1
1312 * @arg @ref LL_DMA_STREAM_2
1313 * @arg @ref LL_DMA_STREAM_3
1314 * @arg @ref LL_DMA_STREAM_4
1315 * @arg @ref LL_DMA_STREAM_5
1316 * @arg @ref LL_DMA_STREAM_6
1317 * @arg @ref LL_DMA_STREAM_7
1318 * @param Mburst This parameter can be one of the following values:
1319 * @arg @ref LL_DMA_MBURST_SINGLE
1320 * @arg @ref LL_DMA_MBURST_INC4
1321 * @arg @ref LL_DMA_MBURST_INC8
1322 * @arg @ref LL_DMA_MBURST_INC16
1323 * @retval None
1324 */
1325 __STATIC_INLINE void LL_DMA_SetMemoryBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Mburst)
1326 {
1329 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST, Mburst);
1330 }
1332 /**
1333 * @brief Get Memory burst transfer configuration.
1334 * @rmtoll CR MBURST LL_DMA_GetMemoryBurstxfer
1335 * @param DMAx DMAx Instance
1336 * @param Stream This parameter can be one of the following values:
1337 * @arg @ref LL_DMA_STREAM_0
1338 * @arg @ref LL_DMA_STREAM_1
1339 * @arg @ref LL_DMA_STREAM_2
1340 * @arg @ref LL_DMA_STREAM_3
1341 * @arg @ref LL_DMA_STREAM_4
1342 * @arg @ref LL_DMA_STREAM_5
1343 * @arg @ref LL_DMA_STREAM_6
1344 * @arg @ref LL_DMA_STREAM_7
1345 * @retval Returned value can be one of the following values:
1346 * @arg @ref LL_DMA_MBURST_SINGLE
1347 * @arg @ref LL_DMA_MBURST_INC4
1348 * @arg @ref LL_DMA_MBURST_INC8
1349 * @arg @ref LL_DMA_MBURST_INC16
1350 */
1352 {
1355 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_MBURST));
1356 }
1358 /**
1359 * @brief Set Peripheral burst transfer configuration.
1360 * @rmtoll CR PBURST LL_DMA_SetPeriphBurstxfer
1361 * @param DMAx DMAx Instance
1362 * @param Stream This parameter can be one of the following values:
1363 * @arg @ref LL_DMA_STREAM_0
1364 * @arg @ref LL_DMA_STREAM_1
1365 * @arg @ref LL_DMA_STREAM_2
1366 * @arg @ref LL_DMA_STREAM_3
1367 * @arg @ref LL_DMA_STREAM_4
1368 * @arg @ref LL_DMA_STREAM_5
1369 * @arg @ref LL_DMA_STREAM_6
1370 * @arg @ref LL_DMA_STREAM_7
1371 * @param Pburst This parameter can be one of the following values:
1372 * @arg @ref LL_DMA_PBURST_SINGLE
1373 * @arg @ref LL_DMA_PBURST_INC4
1374 * @arg @ref LL_DMA_PBURST_INC8
1375 * @arg @ref LL_DMA_PBURST_INC16
1376 * @retval None
1377 */
1378 __STATIC_INLINE void LL_DMA_SetPeriphBurstxfer(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Pburst)
1379 {
1382 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST, Pburst);
1383 }
1385 /**
1386 * @brief Get Peripheral burst transfer configuration.
1387 * @rmtoll CR PBURST LL_DMA_GetPeriphBurstxfer
1388 * @param DMAx DMAx Instance
1389 * @param Stream This parameter can be one of the following values:
1390 * @arg @ref LL_DMA_STREAM_0
1391 * @arg @ref LL_DMA_STREAM_1
1392 * @arg @ref LL_DMA_STREAM_2
1393 * @arg @ref LL_DMA_STREAM_3
1394 * @arg @ref LL_DMA_STREAM_4
1395 * @arg @ref LL_DMA_STREAM_5
1396 * @arg @ref LL_DMA_STREAM_6
1397 * @arg @ref LL_DMA_STREAM_7
1398 * @retval Returned value can be one of the following values:
1399 * @arg @ref LL_DMA_PBURST_SINGLE
1400 * @arg @ref LL_DMA_PBURST_INC4
1401 * @arg @ref LL_DMA_PBURST_INC8
1402 * @arg @ref LL_DMA_PBURST_INC16
1403 */
1405 {
1408 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_PBURST));
1409 }
1411 /**
1412 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1413 * @rmtoll CR CT LL_DMA_SetCurrentTargetMem
1414 * @param DMAx DMAx Instance
1415 * @param Stream This parameter can be one of the following values:
1416 * @arg @ref LL_DMA_STREAM_0
1417 * @arg @ref LL_DMA_STREAM_1
1418 * @arg @ref LL_DMA_STREAM_2
1419 * @arg @ref LL_DMA_STREAM_3
1420 * @arg @ref LL_DMA_STREAM_4
1421 * @arg @ref LL_DMA_STREAM_5
1422 * @arg @ref LL_DMA_STREAM_6
1423 * @arg @ref LL_DMA_STREAM_7
1424 * @param CurrentMemory This parameter can be one of the following values:
1425 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1426 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1427 * @retval None
1428 */
1429 __STATIC_INLINE void LL_DMA_SetCurrentTargetMem(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t CurrentMemory)
1430 {
1433 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT, CurrentMemory);
1434 }
1436 /**
1437 * @brief Set Current target (only in double buffer mode) to Memory 1 or Memory 0.
1438 * @rmtoll CR CT LL_DMA_GetCurrentTargetMem
1439 * @param DMAx DMAx Instance
1440 * @param Stream This parameter can be one of the following values:
1441 * @arg @ref LL_DMA_STREAM_0
1442 * @arg @ref LL_DMA_STREAM_1
1443 * @arg @ref LL_DMA_STREAM_2
1444 * @arg @ref LL_DMA_STREAM_3
1445 * @arg @ref LL_DMA_STREAM_4
1446 * @arg @ref LL_DMA_STREAM_5
1447 * @arg @ref LL_DMA_STREAM_6
1448 * @arg @ref LL_DMA_STREAM_7
1449 * @retval Returned value can be one of the following values:
1450 * @arg @ref LL_DMA_CURRENTTARGETMEM0
1451 * @arg @ref LL_DMA_CURRENTTARGETMEM1
1452 */
1454 {
1457 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_CT));
1458 }
1460 /**
1461 * @brief Enable the double buffer mode.
1462 * @rmtoll CR DBM LL_DMA_EnableDoubleBufferMode
1463 * @param DMAx DMAx Instance
1464 * @param Stream This parameter can be one of the following values:
1465 * @arg @ref LL_DMA_STREAM_0
1466 * @arg @ref LL_DMA_STREAM_1
1467 * @arg @ref LL_DMA_STREAM_2
1468 * @arg @ref LL_DMA_STREAM_3
1469 * @arg @ref LL_DMA_STREAM_4
1470 * @arg @ref LL_DMA_STREAM_5
1471 * @arg @ref LL_DMA_STREAM_6
1472 * @arg @ref LL_DMA_STREAM_7
1473 * @retval None
1474 */
1476 {
1479 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1480 }
1482 /**
1483 * @brief Disable the double buffer mode.
1484 * @rmtoll CR DBM LL_DMA_DisableDoubleBufferMode
1485 * @param DMAx DMAx Instance
1486 * @param Stream This parameter can be one of the following values:
1487 * @arg @ref LL_DMA_STREAM_0
1488 * @arg @ref LL_DMA_STREAM_1
1489 * @arg @ref LL_DMA_STREAM_2
1490 * @arg @ref LL_DMA_STREAM_3
1491 * @arg @ref LL_DMA_STREAM_4
1492 * @arg @ref LL_DMA_STREAM_5
1493 * @arg @ref LL_DMA_STREAM_6
1494 * @arg @ref LL_DMA_STREAM_7
1495 * @retval None
1496 */
1498 {
1501 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DBM);
1502 }
1504 /**
1505 * @brief Get FIFO status.
1506 * @rmtoll FCR FS LL_DMA_GetFIFOStatus
1507 * @param DMAx DMAx Instance
1508 * @param Stream This parameter can be one of the following values:
1509 * @arg @ref LL_DMA_STREAM_0
1510 * @arg @ref LL_DMA_STREAM_1
1511 * @arg @ref LL_DMA_STREAM_2
1512 * @arg @ref LL_DMA_STREAM_3
1513 * @arg @ref LL_DMA_STREAM_4
1514 * @arg @ref LL_DMA_STREAM_5
1515 * @arg @ref LL_DMA_STREAM_6
1516 * @arg @ref LL_DMA_STREAM_7
1517 * @retval Returned value can be one of the following values:
1518 * @arg @ref LL_DMA_FIFOSTATUS_0_25
1519 * @arg @ref LL_DMA_FIFOSTATUS_25_50
1520 * @arg @ref LL_DMA_FIFOSTATUS_50_75
1521 * @arg @ref LL_DMA_FIFOSTATUS_75_100
1522 * @arg @ref LL_DMA_FIFOSTATUS_EMPTY
1523 * @arg @ref LL_DMA_FIFOSTATUS_FULL
1524 */
1526 {
1529 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FS));
1530 }
1532 /**
1533 * @brief Disable Fifo mode.
1534 * @rmtoll FCR DMDIS LL_DMA_DisableFifoMode
1535 * @param DMAx DMAx Instance
1536 * @param Stream This parameter can be one of the following values:
1537 * @arg @ref LL_DMA_STREAM_0
1538 * @arg @ref LL_DMA_STREAM_1
1539 * @arg @ref LL_DMA_STREAM_2
1540 * @arg @ref LL_DMA_STREAM_3
1541 * @arg @ref LL_DMA_STREAM_4
1542 * @arg @ref LL_DMA_STREAM_5
1543 * @arg @ref LL_DMA_STREAM_6
1544 * @arg @ref LL_DMA_STREAM_7
1545 * @retval None
1546 */
1548 {
1551 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1552 }
1554 /**
1555 * @brief Enable Fifo mode.
1556 * @rmtoll FCR DMDIS LL_DMA_EnableFifoMode
1557 * @param DMAx DMAx Instance
1558 * @param Stream This parameter can be one of the following values:
1559 * @arg @ref LL_DMA_STREAM_0
1560 * @arg @ref LL_DMA_STREAM_1
1561 * @arg @ref LL_DMA_STREAM_2
1562 * @arg @ref LL_DMA_STREAM_3
1563 * @arg @ref LL_DMA_STREAM_4
1564 * @arg @ref LL_DMA_STREAM_5
1565 * @arg @ref LL_DMA_STREAM_6
1566 * @arg @ref LL_DMA_STREAM_7
1567 * @retval None
1568 */
1570 {
1573 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_DMDIS);
1574 }
1576 /**
1577 * @brief Select FIFO threshold.
1578 * @rmtoll FCR FTH LL_DMA_SetFIFOThreshold
1579 * @param DMAx DMAx Instance
1580 * @param Stream This parameter can be one of the following values:
1581 * @arg @ref LL_DMA_STREAM_0
1582 * @arg @ref LL_DMA_STREAM_1
1583 * @arg @ref LL_DMA_STREAM_2
1584 * @arg @ref LL_DMA_STREAM_3
1585 * @arg @ref LL_DMA_STREAM_4
1586 * @arg @ref LL_DMA_STREAM_5
1587 * @arg @ref LL_DMA_STREAM_6
1588 * @arg @ref LL_DMA_STREAM_7
1589 * @param Threshold This parameter can be one of the following values:
1590 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1591 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1592 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1593 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1594 * @retval None
1595 */
1596 __STATIC_INLINE void LL_DMA_SetFIFOThreshold(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Threshold)
1597 {
1600 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH, Threshold);
1601 }
1603 /**
1604 * @brief Get FIFO threshold.
1605 * @rmtoll FCR FTH LL_DMA_GetFIFOThreshold
1606 * @param DMAx DMAx Instance
1607 * @param Stream This parameter can be one of the following values:
1608 * @arg @ref LL_DMA_STREAM_0
1609 * @arg @ref LL_DMA_STREAM_1
1610 * @arg @ref LL_DMA_STREAM_2
1611 * @arg @ref LL_DMA_STREAM_3
1612 * @arg @ref LL_DMA_STREAM_4
1613 * @arg @ref LL_DMA_STREAM_5
1614 * @arg @ref LL_DMA_STREAM_6
1615 * @arg @ref LL_DMA_STREAM_7
1616 * @retval Returned value can be one of the following values:
1617 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1618 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1619 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1620 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1621 */
1623 {
1626 return (READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH));
1627 }
1629 /**
1630 * @brief Configure the FIFO .
1631 * @rmtoll FCR FTH LL_DMA_ConfigFifo\n
1632 * FCR DMDIS LL_DMA_ConfigFifo
1633 * @param DMAx DMAx Instance
1634 * @param Stream This parameter can be one of the following values:
1635 * @arg @ref LL_DMA_STREAM_0
1636 * @arg @ref LL_DMA_STREAM_1
1637 * @arg @ref LL_DMA_STREAM_2
1638 * @arg @ref LL_DMA_STREAM_3
1639 * @arg @ref LL_DMA_STREAM_4
1640 * @arg @ref LL_DMA_STREAM_5
1641 * @arg @ref LL_DMA_STREAM_6
1642 * @arg @ref LL_DMA_STREAM_7
1643 * @param FifoMode This parameter can be one of the following values:
1644 * @arg @ref LL_DMA_FIFOMODE_ENABLE
1645 * @arg @ref LL_DMA_FIFOMODE_DISABLE
1646 * @param FifoThreshold This parameter can be one of the following values:
1647 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_4
1648 * @arg @ref LL_DMA_FIFOTHRESHOLD_1_2
1649 * @arg @ref LL_DMA_FIFOTHRESHOLD_3_4
1650 * @arg @ref LL_DMA_FIFOTHRESHOLD_FULL
1651 * @retval None
1652 */
1653 __STATIC_INLINE void LL_DMA_ConfigFifo(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t FifoMode, uint32_t FifoThreshold)
1654 {
1657 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FTH | DMA_SxFCR_DMDIS, FifoMode | FifoThreshold);
1658 }
1660 /**
1661 * @brief Configure the Source and Destination addresses.
1662 * @note This API must not be called when the DMA stream is enabled.
1663 * @rmtoll M0AR M0A LL_DMA_ConfigAddresses\n
1664 * PAR PA LL_DMA_ConfigAddresses
1665 * @param DMAx DMAx Instance
1666 * @param Stream This parameter can be one of the following values:
1667 * @arg @ref LL_DMA_STREAM_0
1668 * @arg @ref LL_DMA_STREAM_1
1669 * @arg @ref LL_DMA_STREAM_2
1670 * @arg @ref LL_DMA_STREAM_3
1671 * @arg @ref LL_DMA_STREAM_4
1672 * @arg @ref LL_DMA_STREAM_5
1673 * @arg @ref LL_DMA_STREAM_6
1674 * @arg @ref LL_DMA_STREAM_7
1675 * @param SrcAddress Between 0 to 0xFFFFFFFF
1676 * @param DstAddress Between 0 to 0xFFFFFFFF
1677 * @param Direction This parameter can be one of the following values:
1678 * @arg @ref LL_DMA_DIRECTION_PERIPH_TO_MEMORY
1679 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_PERIPH
1680 * @arg @ref LL_DMA_DIRECTION_MEMORY_TO_MEMORY
1681 * @retval None
1682 */
1683 __STATIC_INLINE void LL_DMA_ConfigAddresses(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t SrcAddress, uint32_t DstAddress, uint32_t Direction)
1684 {
1687 /* Direction Memory to Periph */
1689 {
1690 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, SrcAddress);
1691 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, DstAddress);
1692 }
1693 /* Direction Periph to Memory and Memory to Memory */
1694 else
1695 {
1696 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, SrcAddress);
1697 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, DstAddress);
1698 }
1699 }
1701 /**
1702 * @brief Set the Memory address.
1703 * @rmtoll M0AR M0A LL_DMA_SetMemoryAddress
1704 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1705 * @note This API must not be called when the DMA stream is enabled.
1706 * @param DMAx DMAx Instance
1707 * @param Stream This parameter can be one of the following values:
1708 * @arg @ref LL_DMA_STREAM_0
1709 * @arg @ref LL_DMA_STREAM_1
1710 * @arg @ref LL_DMA_STREAM_2
1711 * @arg @ref LL_DMA_STREAM_3
1712 * @arg @ref LL_DMA_STREAM_4
1713 * @arg @ref LL_DMA_STREAM_5
1714 * @arg @ref LL_DMA_STREAM_6
1715 * @arg @ref LL_DMA_STREAM_7
1716 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1717 * @retval None
1718 */
1719 __STATIC_INLINE void LL_DMA_SetMemoryAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1720 {
1723 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1724 }
1726 /**
1727 * @brief Set the Peripheral address.
1728 * @rmtoll PAR PA LL_DMA_SetPeriphAddress
1729 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1730 * @note This API must not be called when the DMA stream is enabled.
1731 * @param DMAx DMAx Instance
1732 * @param Stream This parameter can be one of the following values:
1733 * @arg @ref LL_DMA_STREAM_0
1734 * @arg @ref LL_DMA_STREAM_1
1735 * @arg @ref LL_DMA_STREAM_2
1736 * @arg @ref LL_DMA_STREAM_3
1737 * @arg @ref LL_DMA_STREAM_4
1738 * @arg @ref LL_DMA_STREAM_5
1739 * @arg @ref LL_DMA_STREAM_6
1740 * @arg @ref LL_DMA_STREAM_7
1741 * @param PeriphAddress Between 0 to 0xFFFFFFFF
1742 * @retval None
1743 */
1744 __STATIC_INLINE void LL_DMA_SetPeriphAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t PeriphAddress)
1745 {
1748 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, PeriphAddress);
1749 }
1751 /**
1752 * @brief Get the Memory address.
1753 * @rmtoll M0AR M0A LL_DMA_GetMemoryAddress
1754 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1755 * @param DMAx DMAx Instance
1756 * @param Stream This parameter can be one of the following values:
1757 * @arg @ref LL_DMA_STREAM_0
1758 * @arg @ref LL_DMA_STREAM_1
1759 * @arg @ref LL_DMA_STREAM_2
1760 * @arg @ref LL_DMA_STREAM_3
1761 * @arg @ref LL_DMA_STREAM_4
1762 * @arg @ref LL_DMA_STREAM_5
1763 * @arg @ref LL_DMA_STREAM_6
1764 * @arg @ref LL_DMA_STREAM_7
1765 * @retval Between 0 to 0xFFFFFFFF
1766 */
1768 {
1771 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1772 }
1774 /**
1775 * @brief Get the Peripheral address.
1776 * @rmtoll PAR PA LL_DMA_GetPeriphAddress
1777 * @note Interface used for direction LL_DMA_DIRECTION_PERIPH_TO_MEMORY or LL_DMA_DIRECTION_MEMORY_TO_PERIPH only.
1778 * @param DMAx DMAx Instance
1779 * @param Stream This parameter can be one of the following values:
1780 * @arg @ref LL_DMA_STREAM_0
1781 * @arg @ref LL_DMA_STREAM_1
1782 * @arg @ref LL_DMA_STREAM_2
1783 * @arg @ref LL_DMA_STREAM_3
1784 * @arg @ref LL_DMA_STREAM_4
1785 * @arg @ref LL_DMA_STREAM_5
1786 * @arg @ref LL_DMA_STREAM_6
1787 * @arg @ref LL_DMA_STREAM_7
1788 * @retval Between 0 to 0xFFFFFFFF
1789 */
1791 {
1794 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1795 }
1797 /**
1798 * @brief Set the Memory to Memory Source address.
1799 * @rmtoll PAR PA LL_DMA_SetM2MSrcAddress
1800 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1801 * @note This API must not be called when the DMA stream is enabled.
1802 * @param DMAx DMAx Instance
1803 * @param Stream This parameter can be one of the following values:
1804 * @arg @ref LL_DMA_STREAM_0
1805 * @arg @ref LL_DMA_STREAM_1
1806 * @arg @ref LL_DMA_STREAM_2
1807 * @arg @ref LL_DMA_STREAM_3
1808 * @arg @ref LL_DMA_STREAM_4
1809 * @arg @ref LL_DMA_STREAM_5
1810 * @arg @ref LL_DMA_STREAM_6
1811 * @arg @ref LL_DMA_STREAM_7
1812 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1813 * @retval None
1814 */
1815 __STATIC_INLINE void LL_DMA_SetM2MSrcAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1816 {
1819 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR, MemoryAddress);
1820 }
1822 /**
1823 * @brief Set the Memory to Memory Destination address.
1824 * @rmtoll M0AR M0A LL_DMA_SetM2MDstAddress
1825 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1826 * @note This API must not be called when the DMA stream is enabled.
1827 * @param DMAx DMAx Instance
1828 * @param Stream This parameter can be one of the following values:
1829 * @arg @ref LL_DMA_STREAM_0
1830 * @arg @ref LL_DMA_STREAM_1
1831 * @arg @ref LL_DMA_STREAM_2
1832 * @arg @ref LL_DMA_STREAM_3
1833 * @arg @ref LL_DMA_STREAM_4
1834 * @arg @ref LL_DMA_STREAM_5
1835 * @arg @ref LL_DMA_STREAM_6
1836 * @arg @ref LL_DMA_STREAM_7
1837 * @param MemoryAddress Between 0 to 0xFFFFFFFF
1838 * @retval None
1839 */
1840 __STATIC_INLINE void LL_DMA_SetM2MDstAddress(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t MemoryAddress)
1841 {
1844 WRITE_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR, MemoryAddress);
1845 }
1847 /**
1848 * @brief Get the Memory to Memory Source address.
1849 * @rmtoll PAR PA LL_DMA_GetM2MSrcAddress
1850 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1851 * @param DMAx DMAx Instance
1852 * @param Stream This parameter can be one of the following values:
1853 * @arg @ref LL_DMA_STREAM_0
1854 * @arg @ref LL_DMA_STREAM_1
1855 * @arg @ref LL_DMA_STREAM_2
1856 * @arg @ref LL_DMA_STREAM_3
1857 * @arg @ref LL_DMA_STREAM_4
1858 * @arg @ref LL_DMA_STREAM_5
1859 * @arg @ref LL_DMA_STREAM_6
1860 * @arg @ref LL_DMA_STREAM_7
1861 * @retval Between 0 to 0xFFFFFFFF
1862 */
1864 {
1867 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->PAR));
1868 }
1870 /**
1871 * @brief Get the Memory to Memory Destination address.
1872 * @rmtoll M0AR M0A LL_DMA_GetM2MDstAddress
1873 * @note Interface used for direction LL_DMA_DIRECTION_MEMORY_TO_MEMORY only.
1874 * @param DMAx DMAx Instance
1875 * @param Stream This parameter can be one of the following values:
1876 * @arg @ref LL_DMA_STREAM_0
1877 * @arg @ref LL_DMA_STREAM_1
1878 * @arg @ref LL_DMA_STREAM_2
1879 * @arg @ref LL_DMA_STREAM_3
1880 * @arg @ref LL_DMA_STREAM_4
1881 * @arg @ref LL_DMA_STREAM_5
1882 * @arg @ref LL_DMA_STREAM_6
1883 * @arg @ref LL_DMA_STREAM_7
1884 * @retval Between 0 to 0xFFFFFFFF
1885 */
1887 {
1890 return (READ_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M0AR));
1891 }
1893 /**
1894 * @brief Set Memory 1 address (used in case of Double buffer mode).
1895 * @rmtoll M1AR M1A LL_DMA_SetMemory1Address
1896 * @param DMAx DMAx Instance
1897 * @param Stream This parameter can be one of the following values:
1898 * @arg @ref LL_DMA_STREAM_0
1899 * @arg @ref LL_DMA_STREAM_1
1900 * @arg @ref LL_DMA_STREAM_2
1901 * @arg @ref LL_DMA_STREAM_3
1902 * @arg @ref LL_DMA_STREAM_4
1903 * @arg @ref LL_DMA_STREAM_5
1904 * @arg @ref LL_DMA_STREAM_6
1905 * @arg @ref LL_DMA_STREAM_7
1906 * @param Address Between 0 to 0xFFFFFFFF
1907 * @retval None
1908 */
1909 __STATIC_INLINE void LL_DMA_SetMemory1Address(DMA_TypeDef *DMAx, uint32_t Stream, uint32_t Address)
1910 {
1913 MODIFY_REG(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->M1AR, DMA_SxM1AR_M1A, Address);
1914 }
1916 /**
1917 * @brief Get Memory 1 address (used in case of Double buffer mode).
1918 * @rmtoll M1AR M1A LL_DMA_GetMemory1Address
1919 * @param DMAx DMAx Instance
1920 * @param Stream This parameter can be one of the following values:
1921 * @arg @ref LL_DMA_STREAM_0
1922 * @arg @ref LL_DMA_STREAM_1
1923 * @arg @ref LL_DMA_STREAM_2
1924 * @arg @ref LL_DMA_STREAM_3
1925 * @arg @ref LL_DMA_STREAM_4
1926 * @arg @ref LL_DMA_STREAM_5
1927 * @arg @ref LL_DMA_STREAM_6
1928 * @arg @ref LL_DMA_STREAM_7
1929 * @retval Between 0 to 0xFFFFFFFF
1930 */
1932 {
1936 }
1938 /**
1939 * @}
1940 */
1942 /** @defgroup DMA_LL_EF_FLAG_Management FLAG_Management
1943 * @{
1944 */
1946 /**
1947 * @brief Get Stream 0 half transfer flag.
1948 * @rmtoll LISR HTIF0 LL_DMA_IsActiveFlag_HT0
1949 * @param DMAx DMAx Instance
1950 * @retval State of bit (1 or 0).
1951 */
1953 {
1955 }
1957 /**
1958 * @brief Get Stream 1 half transfer flag.
1959 * @rmtoll LISR HTIF1 LL_DMA_IsActiveFlag_HT1
1960 * @param DMAx DMAx Instance
1961 * @retval State of bit (1 or 0).
1962 */
1964 {
1966 }
1968 /**
1969 * @brief Get Stream 2 half transfer flag.
1970 * @rmtoll LISR HTIF2 LL_DMA_IsActiveFlag_HT2
1971 * @param DMAx DMAx Instance
1972 * @retval State of bit (1 or 0).
1973 */
1975 {
1977 }
1979 /**
1980 * @brief Get Stream 3 half transfer flag.
1981 * @rmtoll LISR HTIF3 LL_DMA_IsActiveFlag_HT3
1982 * @param DMAx DMAx Instance
1983 * @retval State of bit (1 or 0).
1984 */
1986 {
1988 }
1990 /**
1991 * @brief Get Stream 4 half transfer flag.
1992 * @rmtoll HISR HTIF4 LL_DMA_IsActiveFlag_HT4
1993 * @param DMAx DMAx Instance
1994 * @retval State of bit (1 or 0).
1995 */
1997 {
1999 }
2001 /**
2002 * @brief Get Stream 5 half transfer flag.
2003 * @rmtoll HISR HTIF0 LL_DMA_IsActiveFlag_HT5
2004 * @param DMAx DMAx Instance
2005 * @retval State of bit (1 or 0).
2006 */
2008 {
2010 }
2012 /**
2013 * @brief Get Stream 6 half transfer flag.
2014 * @rmtoll HISR HTIF6 LL_DMA_IsActiveFlag_HT6
2015 * @param DMAx DMAx Instance
2016 * @retval State of bit (1 or 0).
2017 */
2019 {
2021 }
2023 /**
2024 * @brief Get Stream 7 half transfer flag.
2025 * @rmtoll HISR HTIF7 LL_DMA_IsActiveFlag_HT7
2026 * @param DMAx DMAx Instance
2027 * @retval State of bit (1 or 0).
2028 */
2030 {
2032 }
2034 /**
2035 * @brief Get Stream 0 transfer complete flag.
2036 * @rmtoll LISR TCIF0 LL_DMA_IsActiveFlag_TC0
2037 * @param DMAx DMAx Instance
2038 * @retval State of bit (1 or 0).
2039 */
2041 {
2043 }
2045 /**
2046 * @brief Get Stream 1 transfer complete flag.
2047 * @rmtoll LISR TCIF1 LL_DMA_IsActiveFlag_TC1
2048 * @param DMAx DMAx Instance
2049 * @retval State of bit (1 or 0).
2050 */
2052 {
2054 }
2056 /**
2057 * @brief Get Stream 2 transfer complete flag.
2058 * @rmtoll LISR TCIF2 LL_DMA_IsActiveFlag_TC2
2059 * @param DMAx DMAx Instance
2060 * @retval State of bit (1 or 0).
2061 */
2063 {
2065 }
2067 /**
2068 * @brief Get Stream 3 transfer complete flag.
2069 * @rmtoll LISR TCIF3 LL_DMA_IsActiveFlag_TC3
2070 * @param DMAx DMAx Instance
2071 * @retval State of bit (1 or 0).
2072 */
2074 {
2076 }
2078 /**
2079 * @brief Get Stream 4 transfer complete flag.
2080 * @rmtoll HISR TCIF4 LL_DMA_IsActiveFlag_TC4
2081 * @param DMAx DMAx Instance
2082 * @retval State of bit (1 or 0).
2083 */
2085 {
2087 }
2089 /**
2090 * @brief Get Stream 5 transfer complete flag.
2091 * @rmtoll HISR TCIF0 LL_DMA_IsActiveFlag_TC5
2092 * @param DMAx DMAx Instance
2093 * @retval State of bit (1 or 0).
2094 */
2096 {
2098 }
2100 /**
2101 * @brief Get Stream 6 transfer complete flag.
2102 * @rmtoll HISR TCIF6 LL_DMA_IsActiveFlag_TC6
2103 * @param DMAx DMAx Instance
2104 * @retval State of bit (1 or 0).
2105 */
2107 {
2109 }
2111 /**
2112 * @brief Get Stream 7 transfer complete flag.
2113 * @rmtoll HISR TCIF7 LL_DMA_IsActiveFlag_TC7
2114 * @param DMAx DMAx Instance
2115 * @retval State of bit (1 or 0).
2116 */
2118 {
2120 }
2122 /**
2123 * @brief Get Stream 0 transfer error flag.
2124 * @rmtoll LISR TEIF0 LL_DMA_IsActiveFlag_TE0
2125 * @param DMAx DMAx Instance
2126 * @retval State of bit (1 or 0).
2127 */
2129 {
2131 }
2133 /**
2134 * @brief Get Stream 1 transfer error flag.
2135 * @rmtoll LISR TEIF1 LL_DMA_IsActiveFlag_TE1
2136 * @param DMAx DMAx Instance
2137 * @retval State of bit (1 or 0).
2138 */
2140 {
2142 }
2144 /**
2145 * @brief Get Stream 2 transfer error flag.
2146 * @rmtoll LISR TEIF2 LL_DMA_IsActiveFlag_TE2
2147 * @param DMAx DMAx Instance
2148 * @retval State of bit (1 or 0).
2149 */
2151 {
2153 }
2155 /**
2156 * @brief Get Stream 3 transfer error flag.
2157 * @rmtoll LISR TEIF3 LL_DMA_IsActiveFlag_TE3
2158 * @param DMAx DMAx Instance
2159 * @retval State of bit (1 or 0).
2160 */
2162 {
2164 }
2166 /**
2167 * @brief Get Stream 4 transfer error flag.
2168 * @rmtoll HISR TEIF4 LL_DMA_IsActiveFlag_TE4
2169 * @param DMAx DMAx Instance
2170 * @retval State of bit (1 or 0).
2171 */
2173 {
2175 }
2177 /**
2178 * @brief Get Stream 5 transfer error flag.
2179 * @rmtoll HISR TEIF0 LL_DMA_IsActiveFlag_TE5
2180 * @param DMAx DMAx Instance
2181 * @retval State of bit (1 or 0).
2182 */
2184 {
2186 }
2188 /**
2189 * @brief Get Stream 6 transfer error flag.
2190 * @rmtoll HISR TEIF6 LL_DMA_IsActiveFlag_TE6
2191 * @param DMAx DMAx Instance
2192 * @retval State of bit (1 or 0).
2193 */
2195 {
2197 }
2199 /**
2200 * @brief Get Stream 7 transfer error flag.
2201 * @rmtoll HISR TEIF7 LL_DMA_IsActiveFlag_TE7
2202 * @param DMAx DMAx Instance
2203 * @retval State of bit (1 or 0).
2204 */
2206 {
2208 }
2210 /**
2211 * @brief Get Stream 0 direct mode error flag.
2212 * @rmtoll LISR DMEIF0 LL_DMA_IsActiveFlag_DME0
2213 * @param DMAx DMAx Instance
2214 * @retval State of bit (1 or 0).
2215 */
2217 {
2219 }
2221 /**
2222 * @brief Get Stream 1 direct mode error flag.
2223 * @rmtoll LISR DMEIF1 LL_DMA_IsActiveFlag_DME1
2224 * @param DMAx DMAx Instance
2225 * @retval State of bit (1 or 0).
2226 */
2228 {
2230 }
2232 /**
2233 * @brief Get Stream 2 direct mode error flag.
2234 * @rmtoll LISR DMEIF2 LL_DMA_IsActiveFlag_DME2
2235 * @param DMAx DMAx Instance
2236 * @retval State of bit (1 or 0).
2237 */
2239 {
2241 }
2243 /**
2244 * @brief Get Stream 3 direct mode error flag.
2245 * @rmtoll LISR DMEIF3 LL_DMA_IsActiveFlag_DME3
2246 * @param DMAx DMAx Instance
2247 * @retval State of bit (1 or 0).
2248 */
2250 {
2252 }
2254 /**
2255 * @brief Get Stream 4 direct mode error flag.
2256 * @rmtoll HISR DMEIF4 LL_DMA_IsActiveFlag_DME4
2257 * @param DMAx DMAx Instance
2258 * @retval State of bit (1 or 0).
2259 */
2261 {
2263 }
2265 /**
2266 * @brief Get Stream 5 direct mode error flag.
2267 * @rmtoll HISR DMEIF0 LL_DMA_IsActiveFlag_DME5
2268 * @param DMAx DMAx Instance
2269 * @retval State of bit (1 or 0).
2270 */
2272 {
2274 }
2276 /**
2277 * @brief Get Stream 6 direct mode error flag.
2278 * @rmtoll HISR DMEIF6 LL_DMA_IsActiveFlag_DME6
2279 * @param DMAx DMAx Instance
2280 * @retval State of bit (1 or 0).
2281 */
2283 {
2285 }
2287 /**
2288 * @brief Get Stream 7 direct mode error flag.
2289 * @rmtoll HISR DMEIF7 LL_DMA_IsActiveFlag_DME7
2290 * @param DMAx DMAx Instance
2291 * @retval State of bit (1 or 0).
2292 */
2294 {
2296 }
2298 /**
2299 * @brief Get Stream 0 FIFO error flag.
2300 * @rmtoll LISR FEIF0 LL_DMA_IsActiveFlag_FE0
2301 * @param DMAx DMAx Instance
2302 * @retval State of bit (1 or 0).
2303 */
2305 {
2307 }
2309 /**
2310 * @brief Get Stream 1 FIFO error flag.
2311 * @rmtoll LISR FEIF1 LL_DMA_IsActiveFlag_FE1
2312 * @param DMAx DMAx Instance
2313 * @retval State of bit (1 or 0).
2314 */
2316 {
2318 }
2320 /**
2321 * @brief Get Stream 2 FIFO error flag.
2322 * @rmtoll LISR FEIF2 LL_DMA_IsActiveFlag_FE2
2323 * @param DMAx DMAx Instance
2324 * @retval State of bit (1 or 0).
2325 */
2327 {
2329 }
2331 /**
2332 * @brief Get Stream 3 FIFO error flag.
2333 * @rmtoll LISR FEIF3 LL_DMA_IsActiveFlag_FE3
2334 * @param DMAx DMAx Instance
2335 * @retval State of bit (1 or 0).
2336 */
2338 {
2340 }
2342 /**
2343 * @brief Get Stream 4 FIFO error flag.
2344 * @rmtoll HISR FEIF4 LL_DMA_IsActiveFlag_FE4
2345 * @param DMAx DMAx Instance
2346 * @retval State of bit (1 or 0).
2347 */
2349 {
2351 }
2353 /**
2354 * @brief Get Stream 5 FIFO error flag.
2355 * @rmtoll HISR FEIF0 LL_DMA_IsActiveFlag_FE5
2356 * @param DMAx DMAx Instance
2357 * @retval State of bit (1 or 0).
2358 */
2360 {
2362 }
2364 /**
2365 * @brief Get Stream 6 FIFO error flag.
2366 * @rmtoll HISR FEIF6 LL_DMA_IsActiveFlag_FE6
2367 * @param DMAx DMAx Instance
2368 * @retval State of bit (1 or 0).
2369 */
2371 {
2373 }
2375 /**
2376 * @brief Get Stream 7 FIFO error flag.
2377 * @rmtoll HISR FEIF7 LL_DMA_IsActiveFlag_FE7
2378 * @param DMAx DMAx Instance
2379 * @retval State of bit (1 or 0).
2380 */
2382 {
2384 }
2386 /**
2387 * @brief Clear Stream 0 half transfer flag.
2388 * @rmtoll LIFCR CHTIF0 LL_DMA_ClearFlag_HT0
2389 * @param DMAx DMAx Instance
2390 * @retval None
2391 */
2393 {
2395 }
2397 /**
2398 * @brief Clear Stream 1 half transfer flag.
2399 * @rmtoll LIFCR CHTIF1 LL_DMA_ClearFlag_HT1
2400 * @param DMAx DMAx Instance
2401 * @retval None
2402 */
2404 {
2406 }
2408 /**
2409 * @brief Clear Stream 2 half transfer flag.
2410 * @rmtoll LIFCR CHTIF2 LL_DMA_ClearFlag_HT2
2411 * @param DMAx DMAx Instance
2412 * @retval None
2413 */
2415 {
2417 }
2419 /**
2420 * @brief Clear Stream 3 half transfer flag.
2421 * @rmtoll LIFCR CHTIF3 LL_DMA_ClearFlag_HT3
2422 * @param DMAx DMAx Instance
2423 * @retval None
2424 */
2426 {
2428 }
2430 /**
2431 * @brief Clear Stream 4 half transfer flag.
2432 * @rmtoll HIFCR CHTIF4 LL_DMA_ClearFlag_HT4
2433 * @param DMAx DMAx Instance
2434 * @retval None
2435 */
2437 {
2439 }
2441 /**
2442 * @brief Clear Stream 5 half transfer flag.
2443 * @rmtoll HIFCR CHTIF5 LL_DMA_ClearFlag_HT5
2444 * @param DMAx DMAx Instance
2445 * @retval None
2446 */
2448 {
2450 }
2452 /**
2453 * @brief Clear Stream 6 half transfer flag.
2454 * @rmtoll HIFCR CHTIF6 LL_DMA_ClearFlag_HT6
2455 * @param DMAx DMAx Instance
2456 * @retval None
2457 */
2459 {
2461 }
2463 /**
2464 * @brief Clear Stream 7 half transfer flag.
2465 * @rmtoll HIFCR CHTIF7 LL_DMA_ClearFlag_HT7
2466 * @param DMAx DMAx Instance
2467 * @retval None
2468 */
2470 {
2472 }
2474 /**
2475 * @brief Clear Stream 0 transfer complete flag.
2476 * @rmtoll LIFCR CTCIF0 LL_DMA_ClearFlag_TC0
2477 * @param DMAx DMAx Instance
2478 * @retval None
2479 */
2481 {
2483 }
2485 /**
2486 * @brief Clear Stream 1 transfer complete flag.
2487 * @rmtoll LIFCR CTCIF1 LL_DMA_ClearFlag_TC1
2488 * @param DMAx DMAx Instance
2489 * @retval None
2490 */
2492 {
2494 }
2496 /**
2497 * @brief Clear Stream 2 transfer complete flag.
2498 * @rmtoll LIFCR CTCIF2 LL_DMA_ClearFlag_TC2
2499 * @param DMAx DMAx Instance
2500 * @retval None
2501 */
2503 {
2505 }
2507 /**
2508 * @brief Clear Stream 3 transfer complete flag.
2509 * @rmtoll LIFCR CTCIF3 LL_DMA_ClearFlag_TC3
2510 * @param DMAx DMAx Instance
2511 * @retval None
2512 */
2514 {
2516 }
2518 /**
2519 * @brief Clear Stream 4 transfer complete flag.
2520 * @rmtoll HIFCR CTCIF4 LL_DMA_ClearFlag_TC4
2521 * @param DMAx DMAx Instance
2522 * @retval None
2523 */
2525 {
2527 }
2529 /**
2530 * @brief Clear Stream 5 transfer complete flag.
2531 * @rmtoll HIFCR CTCIF5 LL_DMA_ClearFlag_TC5
2532 * @param DMAx DMAx Instance
2533 * @retval None
2534 */
2536 {
2538 }
2540 /**
2541 * @brief Clear Stream 6 transfer complete flag.
2542 * @rmtoll HIFCR CTCIF6 LL_DMA_ClearFlag_TC6
2543 * @param DMAx DMAx Instance
2544 * @retval None
2545 */
2547 {
2549 }
2551 /**
2552 * @brief Clear Stream 7 transfer complete flag.
2553 * @rmtoll HIFCR CTCIF7 LL_DMA_ClearFlag_TC7
2554 * @param DMAx DMAx Instance
2555 * @retval None
2556 */
2558 {
2560 }
2562 /**
2563 * @brief Clear Stream 0 transfer error flag.
2564 * @rmtoll LIFCR CTEIF0 LL_DMA_ClearFlag_TE0
2565 * @param DMAx DMAx Instance
2566 * @retval None
2567 */
2569 {
2571 }
2573 /**
2574 * @brief Clear Stream 1 transfer error flag.
2575 * @rmtoll LIFCR CTEIF1 LL_DMA_ClearFlag_TE1
2576 * @param DMAx DMAx Instance
2577 * @retval None
2578 */
2580 {
2582 }
2584 /**
2585 * @brief Clear Stream 2 transfer error flag.
2586 * @rmtoll LIFCR CTEIF2 LL_DMA_ClearFlag_TE2
2587 * @param DMAx DMAx Instance
2588 * @retval None
2589 */
2591 {
2593 }
2595 /**
2596 * @brief Clear Stream 3 transfer error flag.
2597 * @rmtoll LIFCR CTEIF3 LL_DMA_ClearFlag_TE3
2598 * @param DMAx DMAx Instance
2599 * @retval None
2600 */
2602 {
2604 }
2606 /**
2607 * @brief Clear Stream 4 transfer error flag.
2608 * @rmtoll HIFCR CTEIF4 LL_DMA_ClearFlag_TE4
2609 * @param DMAx DMAx Instance
2610 * @retval None
2611 */
2613 {
2615 }
2617 /**
2618 * @brief Clear Stream 5 transfer error flag.
2619 * @rmtoll HIFCR CTEIF5 LL_DMA_ClearFlag_TE5
2620 * @param DMAx DMAx Instance
2621 * @retval None
2622 */
2624 {
2626 }
2628 /**
2629 * @brief Clear Stream 6 transfer error flag.
2630 * @rmtoll HIFCR CTEIF6 LL_DMA_ClearFlag_TE6
2631 * @param DMAx DMAx Instance
2632 * @retval None
2633 */
2635 {
2637 }
2639 /**
2640 * @brief Clear Stream 7 transfer error flag.
2641 * @rmtoll HIFCR CTEIF7 LL_DMA_ClearFlag_TE7
2642 * @param DMAx DMAx Instance
2643 * @retval None
2644 */
2646 {
2648 }
2650 /**
2651 * @brief Clear Stream 0 direct mode error flag.
2652 * @rmtoll LIFCR CDMEIF0 LL_DMA_ClearFlag_DME0
2653 * @param DMAx DMAx Instance
2654 * @retval None
2655 */
2657 {
2659 }
2661 /**
2662 * @brief Clear Stream 1 direct mode error flag.
2663 * @rmtoll LIFCR CDMEIF1 LL_DMA_ClearFlag_DME1
2664 * @param DMAx DMAx Instance
2665 * @retval None
2666 */
2668 {
2670 }
2672 /**
2673 * @brief Clear Stream 2 direct mode error flag.
2674 * @rmtoll LIFCR CDMEIF2 LL_DMA_ClearFlag_DME2
2675 * @param DMAx DMAx Instance
2676 * @retval None
2677 */
2679 {
2681 }
2683 /**
2684 * @brief Clear Stream 3 direct mode error flag.
2685 * @rmtoll LIFCR CDMEIF3 LL_DMA_ClearFlag_DME3
2686 * @param DMAx DMAx Instance
2687 * @retval None
2688 */
2690 {
2692 }
2694 /**
2695 * @brief Clear Stream 4 direct mode error flag.
2696 * @rmtoll HIFCR CDMEIF4 LL_DMA_ClearFlag_DME4
2697 * @param DMAx DMAx Instance
2698 * @retval None
2699 */
2701 {
2703 }
2705 /**
2706 * @brief Clear Stream 5 direct mode error flag.
2707 * @rmtoll HIFCR CDMEIF5 LL_DMA_ClearFlag_DME5
2708 * @param DMAx DMAx Instance
2709 * @retval None
2710 */
2712 {
2714 }
2716 /**
2717 * @brief Clear Stream 6 direct mode error flag.
2718 * @rmtoll HIFCR CDMEIF6 LL_DMA_ClearFlag_DME6
2719 * @param DMAx DMAx Instance
2720 * @retval None
2721 */
2723 {
2725 }
2727 /**
2728 * @brief Clear Stream 7 direct mode error flag.
2729 * @rmtoll HIFCR CDMEIF7 LL_DMA_ClearFlag_DME7
2730 * @param DMAx DMAx Instance
2731 * @retval None
2732 */
2734 {
2736 }
2738 /**
2739 * @brief Clear Stream 0 FIFO error flag.
2740 * @rmtoll LIFCR CFEIF0 LL_DMA_ClearFlag_FE0
2741 * @param DMAx DMAx Instance
2742 * @retval None
2743 */
2745 {
2747 }
2749 /**
2750 * @brief Clear Stream 1 FIFO error flag.
2751 * @rmtoll LIFCR CFEIF1 LL_DMA_ClearFlag_FE1
2752 * @param DMAx DMAx Instance
2753 * @retval None
2754 */
2756 {
2758 }
2760 /**
2761 * @brief Clear Stream 2 FIFO error flag.
2762 * @rmtoll LIFCR CFEIF2 LL_DMA_ClearFlag_FE2
2763 * @param DMAx DMAx Instance
2764 * @retval None
2765 */
2767 {
2769 }
2771 /**
2772 * @brief Clear Stream 3 FIFO error flag.
2773 * @rmtoll LIFCR CFEIF3 LL_DMA_ClearFlag_FE3
2774 * @param DMAx DMAx Instance
2775 * @retval None
2776 */
2778 {
2780 }
2782 /**
2783 * @brief Clear Stream 4 FIFO error flag.
2784 * @rmtoll HIFCR CFEIF4 LL_DMA_ClearFlag_FE4
2785 * @param DMAx DMAx Instance
2786 * @retval None
2787 */
2789 {
2791 }
2793 /**
2794 * @brief Clear Stream 5 FIFO error flag.
2795 * @rmtoll HIFCR CFEIF5 LL_DMA_ClearFlag_FE5
2796 * @param DMAx DMAx Instance
2797 * @retval None
2798 */
2800 {
2802 }
2804 /**
2805 * @brief Clear Stream 6 FIFO error flag.
2806 * @rmtoll HIFCR CFEIF6 LL_DMA_ClearFlag_FE6
2807 * @param DMAx DMAx Instance
2808 * @retval None
2809 */
2811 {
2813 }
2815 /**
2816 * @brief Clear Stream 7 FIFO error flag.
2817 * @rmtoll HIFCR CFEIF7 LL_DMA_ClearFlag_FE7
2818 * @param DMAx DMAx Instance
2819 * @retval None
2820 */
2822 {
2824 }
2826 /**
2827 * @}
2828 */
2830 /** @defgroup DMA_LL_EF_IT_Management IT_Management
2831 * @{
2832 */
2834 /**
2835 * @brief Enable Half transfer interrupt.
2836 * @rmtoll CR HTIE LL_DMA_EnableIT_HT
2837 * @param DMAx DMAx Instance
2838 * @param Stream This parameter can be one of the following values:
2839 * @arg @ref LL_DMA_STREAM_0
2840 * @arg @ref LL_DMA_STREAM_1
2841 * @arg @ref LL_DMA_STREAM_2
2842 * @arg @ref LL_DMA_STREAM_3
2843 * @arg @ref LL_DMA_STREAM_4
2844 * @arg @ref LL_DMA_STREAM_5
2845 * @arg @ref LL_DMA_STREAM_6
2846 * @arg @ref LL_DMA_STREAM_7
2847 * @retval None
2848 */
2850 {
2853 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2854 }
2856 /**
2857 * @brief Enable Transfer error interrupt.
2858 * @rmtoll CR TEIE LL_DMA_EnableIT_TE
2859 * @param DMAx DMAx Instance
2860 * @param Stream This parameter can be one of the following values:
2861 * @arg @ref LL_DMA_STREAM_0
2862 * @arg @ref LL_DMA_STREAM_1
2863 * @arg @ref LL_DMA_STREAM_2
2864 * @arg @ref LL_DMA_STREAM_3
2865 * @arg @ref LL_DMA_STREAM_4
2866 * @arg @ref LL_DMA_STREAM_5
2867 * @arg @ref LL_DMA_STREAM_6
2868 * @arg @ref LL_DMA_STREAM_7
2869 * @retval None
2870 */
2872 {
2875 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2876 }
2878 /**
2879 * @brief Enable Transfer complete interrupt.
2880 * @rmtoll CR TCIE LL_DMA_EnableIT_TC
2881 * @param DMAx DMAx Instance
2882 * @param Stream This parameter can be one of the following values:
2883 * @arg @ref LL_DMA_STREAM_0
2884 * @arg @ref LL_DMA_STREAM_1
2885 * @arg @ref LL_DMA_STREAM_2
2886 * @arg @ref LL_DMA_STREAM_3
2887 * @arg @ref LL_DMA_STREAM_4
2888 * @arg @ref LL_DMA_STREAM_5
2889 * @arg @ref LL_DMA_STREAM_6
2890 * @arg @ref LL_DMA_STREAM_7
2891 * @retval None
2892 */
2894 {
2897 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
2898 }
2900 /**
2901 * @brief Enable Direct mode error interrupt.
2902 * @rmtoll CR DMEIE LL_DMA_EnableIT_DME
2903 * @param DMAx DMAx Instance
2904 * @param Stream This parameter can be one of the following values:
2905 * @arg @ref LL_DMA_STREAM_0
2906 * @arg @ref LL_DMA_STREAM_1
2907 * @arg @ref LL_DMA_STREAM_2
2908 * @arg @ref LL_DMA_STREAM_3
2909 * @arg @ref LL_DMA_STREAM_4
2910 * @arg @ref LL_DMA_STREAM_5
2911 * @arg @ref LL_DMA_STREAM_6
2912 * @arg @ref LL_DMA_STREAM_7
2913 * @retval None
2914 */
2916 {
2919 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
2920 }
2922 /**
2923 * @brief Enable FIFO error interrupt.
2924 * @rmtoll FCR FEIE LL_DMA_EnableIT_FE
2925 * @param DMAx DMAx Instance
2926 * @param Stream This parameter can be one of the following values:
2927 * @arg @ref LL_DMA_STREAM_0
2928 * @arg @ref LL_DMA_STREAM_1
2929 * @arg @ref LL_DMA_STREAM_2
2930 * @arg @ref LL_DMA_STREAM_3
2931 * @arg @ref LL_DMA_STREAM_4
2932 * @arg @ref LL_DMA_STREAM_5
2933 * @arg @ref LL_DMA_STREAM_6
2934 * @arg @ref LL_DMA_STREAM_7
2935 * @retval None
2936 */
2938 {
2941 SET_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
2942 }
2944 /**
2945 * @brief Disable Half transfer interrupt.
2946 * @rmtoll CR HTIE LL_DMA_DisableIT_HT
2947 * @param DMAx DMAx Instance
2948 * @param Stream This parameter can be one of the following values:
2949 * @arg @ref LL_DMA_STREAM_0
2950 * @arg @ref LL_DMA_STREAM_1
2951 * @arg @ref LL_DMA_STREAM_2
2952 * @arg @ref LL_DMA_STREAM_3
2953 * @arg @ref LL_DMA_STREAM_4
2954 * @arg @ref LL_DMA_STREAM_5
2955 * @arg @ref LL_DMA_STREAM_6
2956 * @arg @ref LL_DMA_STREAM_7
2957 * @retval None
2958 */
2960 {
2963 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE);
2964 }
2966 /**
2967 * @brief Disable Transfer error interrupt.
2968 * @rmtoll CR TEIE LL_DMA_DisableIT_TE
2969 * @param DMAx DMAx Instance
2970 * @param Stream This parameter can be one of the following values:
2971 * @arg @ref LL_DMA_STREAM_0
2972 * @arg @ref LL_DMA_STREAM_1
2973 * @arg @ref LL_DMA_STREAM_2
2974 * @arg @ref LL_DMA_STREAM_3
2975 * @arg @ref LL_DMA_STREAM_4
2976 * @arg @ref LL_DMA_STREAM_5
2977 * @arg @ref LL_DMA_STREAM_6
2978 * @arg @ref LL_DMA_STREAM_7
2979 * @retval None
2980 */
2982 {
2985 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE);
2986 }
2988 /**
2989 * @brief Disable Transfer complete interrupt.
2990 * @rmtoll CR TCIE LL_DMA_DisableIT_TC
2991 * @param DMAx DMAx Instance
2992 * @param Stream This parameter can be one of the following values:
2993 * @arg @ref LL_DMA_STREAM_0
2994 * @arg @ref LL_DMA_STREAM_1
2995 * @arg @ref LL_DMA_STREAM_2
2996 * @arg @ref LL_DMA_STREAM_3
2997 * @arg @ref LL_DMA_STREAM_4
2998 * @arg @ref LL_DMA_STREAM_5
2999 * @arg @ref LL_DMA_STREAM_6
3000 * @arg @ref LL_DMA_STREAM_7
3001 * @retval None
3002 */
3004 {
3007 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE);
3008 }
3010 /**
3011 * @brief Disable Direct mode error interrupt.
3012 * @rmtoll CR DMEIE LL_DMA_DisableIT_DME
3013 * @param DMAx DMAx Instance
3014 * @param Stream This parameter can be one of the following values:
3015 * @arg @ref LL_DMA_STREAM_0
3016 * @arg @ref LL_DMA_STREAM_1
3017 * @arg @ref LL_DMA_STREAM_2
3018 * @arg @ref LL_DMA_STREAM_3
3019 * @arg @ref LL_DMA_STREAM_4
3020 * @arg @ref LL_DMA_STREAM_5
3021 * @arg @ref LL_DMA_STREAM_6
3022 * @arg @ref LL_DMA_STREAM_7
3023 * @retval None
3024 */
3026 {
3029 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE);
3030 }
3032 /**
3033 * @brief Disable FIFO error interrupt.
3034 * @rmtoll FCR FEIE LL_DMA_DisableIT_FE
3035 * @param DMAx DMAx Instance
3036 * @param Stream This parameter can be one of the following values:
3037 * @arg @ref LL_DMA_STREAM_0
3038 * @arg @ref LL_DMA_STREAM_1
3039 * @arg @ref LL_DMA_STREAM_2
3040 * @arg @ref LL_DMA_STREAM_3
3041 * @arg @ref LL_DMA_STREAM_4
3042 * @arg @ref LL_DMA_STREAM_5
3043 * @arg @ref LL_DMA_STREAM_6
3044 * @arg @ref LL_DMA_STREAM_7
3045 * @retval None
3046 */
3048 {
3051 CLEAR_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE);
3052 }
3054 /**
3055 * @brief Check if Half transfer interrup is enabled.
3056 * @rmtoll CR HTIE LL_DMA_IsEnabledIT_HT
3057 * @param DMAx DMAx Instance
3058 * @param Stream This parameter can be one of the following values:
3059 * @arg @ref LL_DMA_STREAM_0
3060 * @arg @ref LL_DMA_STREAM_1
3061 * @arg @ref LL_DMA_STREAM_2
3062 * @arg @ref LL_DMA_STREAM_3
3063 * @arg @ref LL_DMA_STREAM_4
3064 * @arg @ref LL_DMA_STREAM_5
3065 * @arg @ref LL_DMA_STREAM_6
3066 * @arg @ref LL_DMA_STREAM_7
3067 * @retval State of bit (1 or 0).
3068 */
3070 {
3073 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_HTIE) == DMA_SxCR_HTIE) ? 1UL : 0UL);
3074 }
3076 /**
3077 * @brief Check if Transfer error nterrup is enabled.
3078 * @rmtoll CR TEIE LL_DMA_IsEnabledIT_TE
3079 * @param DMAx DMAx Instance
3080 * @param Stream This parameter can be one of the following values:
3081 * @arg @ref LL_DMA_STREAM_0
3082 * @arg @ref LL_DMA_STREAM_1
3083 * @arg @ref LL_DMA_STREAM_2
3084 * @arg @ref LL_DMA_STREAM_3
3085 * @arg @ref LL_DMA_STREAM_4
3086 * @arg @ref LL_DMA_STREAM_5
3087 * @arg @ref LL_DMA_STREAM_6
3088 * @arg @ref LL_DMA_STREAM_7
3089 * @retval State of bit (1 or 0).
3090 */
3092 {
3095 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TEIE) == DMA_SxCR_TEIE) ? 1UL : 0UL);
3096 }
3098 /**
3099 * @brief Check if Transfer complete interrup is enabled.
3100 * @rmtoll CR TCIE LL_DMA_IsEnabledIT_TC
3101 * @param DMAx DMAx Instance
3102 * @param Stream This parameter can be one of the following values:
3103 * @arg @ref LL_DMA_STREAM_0
3104 * @arg @ref LL_DMA_STREAM_1
3105 * @arg @ref LL_DMA_STREAM_2
3106 * @arg @ref LL_DMA_STREAM_3
3107 * @arg @ref LL_DMA_STREAM_4
3108 * @arg @ref LL_DMA_STREAM_5
3109 * @arg @ref LL_DMA_STREAM_6
3110 * @arg @ref LL_DMA_STREAM_7
3111 * @retval State of bit (1 or 0).
3112 */
3114 {
3117 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_TCIE) == DMA_SxCR_TCIE) ? 1UL : 0UL);
3118 }
3120 /**
3121 * @brief Check if Direct mode error interrupt is enabled.
3122 * @rmtoll CR DMEIE LL_DMA_IsEnabledIT_DME
3123 * @param DMAx DMAx Instance
3124 * @param Stream This parameter can be one of the following values:
3125 * @arg @ref LL_DMA_STREAM_0
3126 * @arg @ref LL_DMA_STREAM_1
3127 * @arg @ref LL_DMA_STREAM_2
3128 * @arg @ref LL_DMA_STREAM_3
3129 * @arg @ref LL_DMA_STREAM_4
3130 * @arg @ref LL_DMA_STREAM_5
3131 * @arg @ref LL_DMA_STREAM_6
3132 * @arg @ref LL_DMA_STREAM_7
3133 * @retval State of bit (1 or 0).
3134 */
3136 {
3139 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->CR, DMA_SxCR_DMEIE) == DMA_SxCR_DMEIE) ? 1UL : 0UL);
3140 }
3142 /**
3143 * @brief Check if FIFO error interrup is enabled.
3144 * @rmtoll FCR FEIE LL_DMA_IsEnabledIT_FE
3145 * @param DMAx DMAx Instance
3146 * @param Stream This parameter can be one of the following values:
3147 * @arg @ref LL_DMA_STREAM_0
3148 * @arg @ref LL_DMA_STREAM_1
3149 * @arg @ref LL_DMA_STREAM_2
3150 * @arg @ref LL_DMA_STREAM_3
3151 * @arg @ref LL_DMA_STREAM_4
3152 * @arg @ref LL_DMA_STREAM_5
3153 * @arg @ref LL_DMA_STREAM_6
3154 * @arg @ref LL_DMA_STREAM_7
3155 * @retval State of bit (1 or 0).
3156 */
3158 {
3161 return ((READ_BIT(((DMA_Stream_TypeDef *)(dma_base_addr + LL_DMA_STR_OFFSET_TAB[Stream]))->FCR, DMA_SxFCR_FEIE) == DMA_SxFCR_FEIE) ? 1UL : 0UL);
3162 }
3164 /**
3165 * @}
3166 */
3168 #if defined(USE_FULL_LL_DRIVER)
3169 /** @defgroup DMA_LL_EF_Init Initialization and de-initialization functions
3170 * @{
3171 */
3177 /**
3178 * @}
3179 */
3182 /**
3183 * @}
3184 */
3186 /**
3187 * @}
3188 */
3192 /**
3193 * @}
3194 */
3196 #ifdef __cplusplus
3197 }
3198 #endif
3202 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/