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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_dma2d.h
blob905cbc7eafccc9ef6909cebface0456fdab7b278
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dma2d.h
4 * @author MCD Application Team
5 * @brief Header file of DMA2D LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file
13 * in the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 *
16 ******************************************************************************
17 */
18
19 /* Define to prevent recursive inclusion -------------------------------------*/
20 #ifndef STM32H7xx_LL_DMA2D_H
21 #define STM32H7xx_LL_DMA2D_H
22
23 #ifdef __cplusplus
24 extern "C" {
25 #endif
26
27 /* Includes ------------------------------------------------------------------*/
28 #include "stm32h7xx.h"
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined (DMA2D)
35
36 /** @defgroup DMA2D_LL DMA2D
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /* Private constants ---------------------------------------------------------*/
43 /* Private macros ------------------------------------------------------------*/
44 #if defined(USE_FULL_LL_DRIVER)
45 /** @defgroup DMA2D_LL_Private_Macros DMA2D Private Macros
46 * @{
47 */
48
49 /**
50 * @}
51 */
52 #endif /*USE_FULL_LL_DRIVER*/
53
54 /* Exported types ------------------------------------------------------------*/
55 #if defined(USE_FULL_LL_DRIVER)
56 /** @defgroup DMA2D_LL_ES_Init_Struct DMA2D Exported Init structures
57 * @{
58 */
59
60 /**
61 * @brief LL DMA2D Init Structure Definition
62 */
63 typedef struct
64 {
65 uint32_t Mode; /*!< Specifies the DMA2D transfer mode.
66 - This parameter can be one value of @ref DMA2D_LL_EC_MODE.
67
68 This parameter can be modified afterwards,
69 using unitary function @ref LL_DMA2D_SetMode(). */
70
71 uint32_t ColorMode; /*!< Specifies the color format of the output image.
72 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
73
74 This parameter can be modified afterwards using,
75 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
76
77 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
78 - This parameter must be a number between:
79 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
80 - This parameter must be a number between:
81 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
82 - This parameter must be a number between:
83 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
84 - This parameter must be a number between:
85 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
86 - This parameter must be a number between:
87 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
88
89 This parameter can be modified afterwards,
90 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
91 function @ref LL_DMA2D_ConfigOutputColor(). */
92
93 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
94 - This parameter must be a number between:
95 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
96 - This parameter must be a number between:
97 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
98 - This parameter must be a number between:
99 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
100 - This parameter must be a number between:
101 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
102 - This parameter must be a number between:
103 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
104
105 This parameter can be modified afterwards
106 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
107 function @ref LL_DMA2D_ConfigOutputColor(). */
108
109 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
110 - This parameter must be a number between:
111 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
112 - This parameter must be a number between:
113 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
114 - This parameter must be a number between:
115 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
116 - This parameter must be a number between:
117 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
118 - This parameter must be a number between:
119 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
120
121 This parameter can be modified afterwards
122 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
123 function @ref LL_DMA2D_ConfigOutputColor(). */
124
125 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
126 - This parameter must be a number between:
127 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
128 - This parameter must be a number between:
129 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
130 - This parameter must be a number between:
131 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
132 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
133
134 This parameter can be modified afterwards using,
135 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
136 function @ref LL_DMA2D_ConfigOutputColor(). */
137
138 uint32_t OutputMemoryAddress; /*!< Specifies the memory address.
139 - This parameter must be a number between:
140 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
141
142 This parameter can be modified afterwards,
143 using unitary function @ref LL_DMA2D_SetOutputMemAddr(). */
144
145 uint32_t OutputSwapMode; /*!< Specifies the output swap mode color format of the output image.
146 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_SWAP_MODE.
147
148 This parameter can be modified afterwards,
149 using unitary function @ref LL_DMA2D_SetOutputSwapMode(). */
150
151 uint32_t LineOffsetMode; /*!< Specifies the output line offset mode.
152 - This parameter can be one value of @ref DMA2D_LL_EC_LINE_OFFSET_MODE.
153
154 This parameter can be modified afterwards,
155 using unitary function @ref LL_DMA2D_SetLineOffsetMode(). */
156
157 uint32_t LineOffset; /*!< Specifies the output line offset value.
158 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0xFFFF.
159
160 This parameter can be modified afterwards,
161 using unitary function @ref LL_DMA2D_SetLineOffset(). */
162
163 uint32_t NbrOfLines; /*!< Specifies the number of lines of the area to be transferred.
164 - This parameter must be a number between:
165 Min_Data = 0x0000 and Max_Data = 0xFFFF.
166
167 This parameter can be modified afterwards,
168 using unitary function @ref LL_DMA2D_SetNbrOfLines(). */
169
170 uint32_t NbrOfPixelsPerLines; /*!< Specifies the number of pixels per lines of the area to be transferred.
171 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
172
173 This parameter can be modified afterwards using,
174 unitary function @ref LL_DMA2D_SetNbrOfPixelsPerLines(). */
175
176 uint32_t AlphaInversionMode; /*!< Specifies the output alpha inversion mode.
177 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
178
179 This parameter can be modified afterwards,
180 using unitary function @ref LL_DMA2D_SetOutputAlphaInvMode(). */
181
182 uint32_t RBSwapMode; /*!< Specifies the output Red Blue swap mode.
183 - This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP.
184
185 This parameter can be modified afterwards,
186 using unitary function @ref LL_DMA2D_SetOutputRBSwapMode(). */
187
188 } LL_DMA2D_InitTypeDef;
189
190 /**
191 * @brief LL DMA2D Layer Configuration Structure Definition
192 */
193 typedef struct
194 {
195 uint32_t MemoryAddress; /*!< Specifies the foreground or background memory address.
196 - This parameter must be a number between:
197 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
198
199 This parameter can be modified afterwards using unitary functions
200 - @ref LL_DMA2D_FGND_SetMemAddr() for foreground layer,
201 - @ref LL_DMA2D_BGND_SetMemAddr() for background layer. */
202
203 uint32_t LineOffset; /*!< Specifies the foreground or background line offset value.
204 - This parameter must be a number between Min_Data = 0x0000 and Max_Data = 0x3FFF.
205
206 This parameter can be modified afterwards using unitary functions
207 - @ref LL_DMA2D_FGND_SetLineOffset() for foreground layer,
208 - @ref LL_DMA2D_BGND_SetLineOffset() for background layer. */
209
210 uint32_t ColorMode; /*!< Specifies the foreground or background color mode.
211 - This parameter can be one value of @ref DMA2D_LL_EC_INPUT_COLOR_MODE.
212
213 This parameter can be modified afterwards using unitary functions
214 - @ref LL_DMA2D_FGND_SetColorMode() for foreground layer,
215 - @ref LL_DMA2D_BGND_SetColorMode() for background layer. */
216
217 uint32_t CLUTColorMode; /*!< Specifies the foreground or background CLUT color mode.
218 - This parameter can be one value of @ref DMA2D_LL_EC_CLUT_COLOR_MODE.
219
220 This parameter can be modified afterwards using unitary functions
221 - @ref LL_DMA2D_FGND_SetCLUTColorMode() for foreground layer,
222 - @ref LL_DMA2D_BGND_SetCLUTColorMode() for background layer. */
223
224 uint32_t CLUTSize; /*!< Specifies the foreground or background CLUT size.
225 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
226
227 This parameter can be modified afterwards using unitary functions
228 - @ref LL_DMA2D_FGND_SetCLUTSize() for foreground layer,
229 - @ref LL_DMA2D_BGND_SetCLUTSize() for background layer. */
230
231 uint32_t AlphaMode; /*!< Specifies the foreground or background alpha mode.
232 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_MODE.
233
234 This parameter can be modified afterwards using unitary functions
235 - @ref LL_DMA2D_FGND_SetAlphaMode() for foreground layer,
236 - @ref LL_DMA2D_BGND_SetAlphaMode() for background layer. */
237
238 uint32_t Alpha; /*!< Specifies the foreground or background Alpha value.
239 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
240
241 This parameter can be modified afterwards using unitary functions
242 - @ref LL_DMA2D_FGND_SetAlpha() for foreground layer,
243 - @ref LL_DMA2D_BGND_SetAlpha() for background layer. */
244
245 uint32_t Blue; /*!< Specifies the foreground or background Blue color value.
246 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
247
248 This parameter can be modified afterwards using unitary functions
249 - @ref LL_DMA2D_FGND_SetBlueColor() for foreground layer,
250 - @ref LL_DMA2D_BGND_SetBlueColor() for background layer. */
251
252 uint32_t Green; /*!< Specifies the foreground or background Green color value.
253 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
254
255 This parameter can be modified afterwards using unitary functions
256 - @ref LL_DMA2D_FGND_SetGreenColor() for foreground layer,
257 - @ref LL_DMA2D_BGND_SetGreenColor() for background layer. */
258
259 uint32_t Red; /*!< Specifies the foreground or background Red color value.
260 - This parameter must be a number between Min_Data = 0x00 and Max_Data = 0xFF.
261
262 This parameter can be modified afterwards using unitary functions
263 - @ref LL_DMA2D_FGND_SetRedColor() for foreground layer,
264 - @ref LL_DMA2D_BGND_SetRedColor() for background layer. */
265
266 uint32_t CLUTMemoryAddress; /*!< Specifies the foreground or background CLUT memory address.
267 - This parameter must be a number between:
268 Min_Data = 0x0000 and Max_Data = 0xFFFFFFFF.
269
270 This parameter can be modified afterwards using unitary functions
271 - @ref LL_DMA2D_FGND_SetCLUTMemAddr() for foreground layer,
272 - @ref LL_DMA2D_BGND_SetCLUTMemAddr() for background layer. */
273
274 uint32_t AlphaInversionMode; /*!< Specifies the foreground or background alpha inversion mode.
275 - This parameter can be one value of @ref DMA2D_LL_EC_ALPHA_INVERSION.
276
277 This parameter can be modified afterwards using unitary functions
278 - @ref LL_DMA2D_FGND_SetAlphaInvMode() for foreground layer,
279 - @ref LL_DMA2D_BGND_SetAlphaInvMode() for background layer. */
280
281 uint32_t RBSwapMode; /*!< Specifies the foreground or background Red Blue swap mode.
282 This parameter can be one value of @ref DMA2D_LL_EC_RED_BLUE_SWAP .
283
284 This parameter can be modified afterwards using unitary functions
285 - @ref LL_DMA2D_FGND_SetRBSwapMode() for foreground layer,
286 - @ref LL_DMA2D_BGND_SetRBSwapMode() for background layer. */
287
288 uint32_t ChromaSubSampling; /*!< Configure the chroma sub-sampling mode for the YCbCr color mode
289 This parameter is applicable for foreground layer only.
290 This parameter can be one value of @ref DMA2D_LL_CHROMA_SUB_SAMPLING
291
292 This parameter can be modified afterwards using unitary functions
293 - @ref LL_DMA2D_FGND_SetChrSubSampling() for foreground layer. */
294
295 } LL_DMA2D_LayerCfgTypeDef;
296
297 /**
298 * @brief LL DMA2D Output Color Structure Definition
299 */
300 typedef struct
301 {
302 uint32_t ColorMode; /*!< Specifies the color format of the output image.
303 - This parameter can be one value of @ref DMA2D_LL_EC_OUTPUT_COLOR_MODE.
304
305 This parameter can be modified afterwards using
306 unitary function @ref LL_DMA2D_SetOutputColorMode(). */
307
308 uint32_t OutputBlue; /*!< Specifies the Blue value of the output image.
309 - This parameter must be a number between:
310 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
311 - This parameter must be a number between:
312 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
313 - This parameter must be a number between:
314 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
315 - This parameter must be a number between:
316 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
317 - This parameter must be a number between:
318 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
319
320 This parameter can be modified afterwards using,
321 unitary function @ref LL_DMA2D_SetOutputColor() or configuration
322 function @ref LL_DMA2D_ConfigOutputColor(). */
323
324 uint32_t OutputGreen; /*!< Specifies the Green value of the output image.
325 - This parameter must be a number between:
326 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
327 - This parameter must be a number between
328 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
329 - This parameter must be a number between:
330 Min_Data = 0x00 and Max_Data = 0x3F if RGB565 color mode is selected.
331 - This parameter must be a number between:
332 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
333 - This parameter must be a number between:
334 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
335
336 This parameter can be modified afterwards,
337 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
338 function @ref LL_DMA2D_ConfigOutputColor(). */
339
340 uint32_t OutputRed; /*!< Specifies the Red value of the output image.
341 - This parameter must be a number between:
342 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
343 - This parameter must be a number between:
344 Min_Data = 0x00 and Max_Data = 0xFF if RGB888 color mode is selected.
345 - This parameter must be a number between:
346 Min_Data = 0x00 and Max_Data = 0x1F if RGB565 color mode is selected.
347 - This parameter must be a number between:
348 Min_Data = 0x00 and Max_Data = 0x1F if ARGB1555 color mode is selected.
349 - This parameter must be a number between:
350 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
351
352 This parameter can be modified afterwards,
353 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
354 function @ref LL_DMA2D_ConfigOutputColor(). */
355
356 uint32_t OutputAlpha; /*!< Specifies the Alpha channel of the output image.
357 - This parameter must be a number between:
358 Min_Data = 0x00 and Max_Data = 0xFF if ARGB8888 color mode is selected.
359 - This parameter must be a number between:
360 Min_Data = 0x00 and Max_Data = 0x01 if ARGB1555 color mode is selected.
361 - This parameter must be a number between:
362 Min_Data = 0x00 and Max_Data = 0x0F if ARGB4444 color mode is selected.
363 - This parameter is not considered if RGB888 or RGB565 color mode is selected.
364
365 This parameter can be modified afterwards,
366 using unitary function @ref LL_DMA2D_SetOutputColor() or configuration
367 function @ref LL_DMA2D_ConfigOutputColor(). */
368
369 } LL_DMA2D_ColorTypeDef;
370
371 /**
372 * @}
373 */
374 #endif /* USE_FULL_LL_DRIVER */
375
376 /* Exported constants --------------------------------------------------------*/
377 /** @defgroup DMA2D_LL_Exported_Constants DMA2D Exported Constants
378 * @{
379 */
380
381 /** @defgroup DMA2D_LL_EC_GET_FLAG Get Flags Defines
382 * @brief Flags defines which can be used with LL_DMA2D_ReadReg function
383 * @{
384 */
385 #define LL_DMA2D_FLAG_CEIF DMA2D_ISR_CEIF /*!< Configuration Error Interrupt Flag */
386 #define LL_DMA2D_FLAG_CTCIF DMA2D_ISR_CTCIF /*!< CLUT Transfer Complete Interrupt Flag */
387 #define LL_DMA2D_FLAG_CAEIF DMA2D_ISR_CAEIF /*!< CLUT Access Error Interrupt Flag */
388 #define LL_DMA2D_FLAG_TWIF DMA2D_ISR_TWIF /*!< Transfer Watermark Interrupt Flag */
389 #define LL_DMA2D_FLAG_TCIF DMA2D_ISR_TCIF /*!< Transfer Complete Interrupt Flag */
390 #define LL_DMA2D_FLAG_TEIF DMA2D_ISR_TEIF /*!< Transfer Error Interrupt Flag */
391 /**
392 * @}
393 */
394
395 /** @defgroup DMA2D_LL_EC_IT IT Defines
396 * @brief IT defines which can be used with LL_DMA2D_ReadReg and LL_DMA2D_WriteReg functions
397 * @{
398 */
399 #define LL_DMA2D_IT_CEIE DMA2D_CR_CEIE /*!< Configuration Error Interrupt */
400 #define LL_DMA2D_IT_CTCIE DMA2D_CR_CTCIE /*!< CLUT Transfer Complete Interrupt */
401 #define LL_DMA2D_IT_CAEIE DMA2D_CR_CAEIE /*!< CLUT Access Error Interrupt */
402 #define LL_DMA2D_IT_TWIE DMA2D_CR_TWIE /*!< Transfer Watermark Interrupt */
403 #define LL_DMA2D_IT_TCIE DMA2D_CR_TCIE /*!< Transfer Complete Interrupt */
404 #define LL_DMA2D_IT_TEIE DMA2D_CR_TEIE /*!< Transfer Error Interrupt */
405 /**
406 * @}
407 */
408
409 /** @defgroup DMA2D_LL_EC_MODE Mode
410 * @{
411 */
412 #define LL_DMA2D_MODE_M2M 0x00000000U /*!< DMA2D memory to memory transfer mode */
413 #define LL_DMA2D_MODE_M2M_PFC DMA2D_CR_MODE_0 /*!< DMA2D memory to memory with pixel format conversion transfer mode */
414 #define LL_DMA2D_MODE_M2M_BLEND DMA2D_CR_MODE_1 /*!< DMA2D memory to memory with blending transfer mode */
415 #define LL_DMA2D_MODE_R2M (DMA2D_CR_MODE_0|DMA2D_CR_MODE_1) /*!< DMA2D register to memory transfer mode */
416 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG DMA2D_CR_MODE_2 /*!< DMA2D memory to memory with blending transfer mode and fixed color foreground */
417 #define LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG (DMA2D_CR_MODE_0|DMA2D_CR_MODE_2) /*!< DMA2D memory to memory with blending transfer mode and fixed color background */
418 /**
419 * @}
420 */
421
422 /** @defgroup DMA2D_LL_EC_OUTPUT_COLOR_MODE Output Color Mode
423 * @{
424 */
425 #define LL_DMA2D_OUTPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
426 #define LL_DMA2D_OUTPUT_MODE_RGB888 DMA2D_OPFCCR_CM_0 /*!< RGB888 */
427 #define LL_DMA2D_OUTPUT_MODE_RGB565 DMA2D_OPFCCR_CM_1 /*!< RGB565 */
428 #define LL_DMA2D_OUTPUT_MODE_ARGB1555 (DMA2D_OPFCCR_CM_0|DMA2D_OPFCCR_CM_1) /*!< ARGB1555 */
429 #define LL_DMA2D_OUTPUT_MODE_ARGB4444 DMA2D_OPFCCR_CM_2 /*!< ARGB4444 */
430 /**
431 * @}
432 */
433
434 /** @defgroup DMA2D_LL_EC_INPUT_COLOR_MODE Input Color Mode
435 * @{
436 */
437 #define LL_DMA2D_INPUT_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
438 #define LL_DMA2D_INPUT_MODE_RGB888 DMA2D_FGPFCCR_CM_0 /*!< RGB888 */
439 #define LL_DMA2D_INPUT_MODE_RGB565 DMA2D_FGPFCCR_CM_1 /*!< RGB565 */
440 #define LL_DMA2D_INPUT_MODE_ARGB1555 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1) /*!< ARGB1555 */
441 #define LL_DMA2D_INPUT_MODE_ARGB4444 DMA2D_FGPFCCR_CM_2 /*!< ARGB4444 */
442 #define LL_DMA2D_INPUT_MODE_L8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_2) /*!< L8 */
443 #define LL_DMA2D_INPUT_MODE_AL44 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL44 */
444 #define LL_DMA2D_INPUT_MODE_AL88 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_2) /*!< AL88 */
445 #define LL_DMA2D_INPUT_MODE_L4 DMA2D_FGPFCCR_CM_3 /*!< L4 */
446 #define LL_DMA2D_INPUT_MODE_A8 (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_3) /*!< A8 */
447 #define LL_DMA2D_INPUT_MODE_A4 (DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< A4 */
448 #define LL_DMA2D_INPUT_MODE_YCBCR (DMA2D_FGPFCCR_CM_0|DMA2D_FGPFCCR_CM_1|DMA2D_FGPFCCR_CM_3) /*!< YCbCr */
449 /**
450 * @}
451 */
452
453 /** @defgroup DMA2D_LL_EC_ALPHA_MODE Alpha Mode
454 * @{
455 */
456 #define LL_DMA2D_ALPHA_MODE_NO_MODIF 0x00000000U /*!< No modification of the alpha channel value */
457 #define LL_DMA2D_ALPHA_MODE_REPLACE DMA2D_FGPFCCR_AM_0 /*!< Replace original alpha channel value by
458 programmed alpha value */
459 #define LL_DMA2D_ALPHA_MODE_COMBINE DMA2D_FGPFCCR_AM_1 /*!< Replace original alpha channel value by
460 programmed alpha value with,
461 original alpha channel value */
462 /**
463 * @}
464 */
465
466 /** @defgroup DMA2D_LL_EC_OUTPUT_SWAP_MODE Swap Mode
467 * @{
468 */
469 #define LL_DMA2D_SWAP_MODE_REGULAR 0x00000000U /*!< Regular order */
470 #define LL_DMA2D_SWAP_MODE_TWO_BY_TWO DMA2D_OPFCCR_SB /*!< Bytes swapped two by two */
471 /**
472 * @}
473 */
474
475 /** @defgroup DMA2D_LL_EC_RED_BLUE_SWAP Red Blue Swap
476 * @{
477 */
478 #define LL_DMA2D_RB_MODE_REGULAR 0x00000000U /*!< RGB or ARGB */
479 #define LL_DMA2D_RB_MODE_SWAP DMA2D_FGPFCCR_RBS /*!< BGR or ABGR */
480 /**
481 * @}
482 */
483
484 /** @defgroup DMA2D_LL_EC_ALPHA_INVERSION Alpha Inversion
485 * @{
486 */
487 #define LL_DMA2D_ALPHA_REGULAR 0x00000000U /*!< Regular alpha */
488 #define LL_DMA2D_ALPHA_INVERTED DMA2D_FGPFCCR_AI /*!< Inverted alpha */
489 /**
490 * @}
491 */
492
493
494 /** @defgroup DMA2D_LL_EC_LINE_OFFSET_MODE Line Offset Mode
495 * @{
496 */
497 #define LL_DMA2D_LINE_OFFSET_PIXELS 0x00000000U /*!< Line offsets are expressed in pixels */
498 #define LL_DMA2D_LINE_OFFSET_BYTES DMA2D_CR_LOM /*!< Line offsets are expressed in bytes */
499 /**
500 * @}
501 */
502
503 /** @defgroup DMA2D_LL_EC_CLUT_COLOR_MODE CLUT Color Mode
504 * @{
505 */
506 #define LL_DMA2D_CLUT_COLOR_MODE_ARGB8888 0x00000000U /*!< ARGB8888 */
507 #define LL_DMA2D_CLUT_COLOR_MODE_RGB888 DMA2D_FGPFCCR_CCM /*!< RGB888 */
508 /**
509 * @}
510 */
511
512 /** @defgroup DMA2D_LL_CHROMA_SUB_SAMPLING Chroma Sub Sampling
513 * @{
514 */
515 #define LL_DMA2D_CSS_444 0x00000000U /*!< No chroma sub-sampling 4:4:4 */
516 #define LL_DMA2D_CSS_422 DMA2D_FGPFCCR_CSS_0 /*!< chroma sub-sampling 4:2:2 */
517 #define LL_DMA2D_CSS_420 DMA2D_FGPFCCR_CSS_1 /*!< chroma sub-sampling 4:2:0 */
518 /**
519 * @}
520 */
521
522 /**
523 * @}
524 */
525
526 /* Exported macro ------------------------------------------------------------*/
527 /** @defgroup DMA2D_LL_Exported_Macros DMA2D Exported Macros
528 * @{
529 */
530
531 /** @defgroup DMA2D_LL_EM_WRITE_READ Common Write and read registers Macros
532 * @{
533 */
534
535 /**
536 * @brief Write a value in DMA2D register.
537 * @param __INSTANCE__ DMA2D Instance
538 * @param __REG__ Register to be written
539 * @param __VALUE__ Value to be written in the register
540 * @retval None
541 */
542 #define LL_DMA2D_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG((__INSTANCE__)->__REG__, (__VALUE__))
543
544 /**
545 * @brief Read a value in DMA2D register.
546 * @param __INSTANCE__ DMA2D Instance
547 * @param __REG__ Register to be read
548 * @retval Register value
549 */
550 #define LL_DMA2D_ReadReg(__INSTANCE__, __REG__) READ_REG((__INSTANCE__)->__REG__)
551 /**
552 * @}
553 */
554
555 /**
556 * @}
557 */
558
559 /* Exported functions --------------------------------------------------------*/
560 /** @defgroup DMA2D_LL_Exported_Functions DMA2D Exported Functions
561 * @{
562 */
563
564 /** @defgroup DMA2D_LL_EF_Configuration Configuration Functions
565 * @{
566 */
567
568 /**
569 * @brief Start a DMA2D transfer.
570 * @rmtoll CR START LL_DMA2D_Start
571 * @param DMA2Dx DMA2D Instance
572 * @retval None
573 */
574 __STATIC_INLINE void LL_DMA2D_Start(DMA2D_TypeDef *DMA2Dx)
575 {
576 SET_BIT(DMA2Dx->CR, DMA2D_CR_START);
577 }
578
579 /**
580 * @brief Indicate if a DMA2D transfer is ongoing.
581 * @rmtoll CR START LL_DMA2D_IsTransferOngoing
582 * @param DMA2Dx DMA2D Instance
583 * @retval State of bit (1 or 0).
584 */
585 __STATIC_INLINE uint32_t LL_DMA2D_IsTransferOngoing(const DMA2D_TypeDef *DMA2Dx)
586 {
587 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_START) == (DMA2D_CR_START)) ? 1UL : 0UL);
588 }
589
590 /**
591 * @brief Suspend DMA2D transfer.
592 * @note This API can be used to suspend automatic foreground or background CLUT loading.
593 * @rmtoll CR SUSP LL_DMA2D_Suspend
594 * @param DMA2Dx DMA2D Instance
595 * @retval None
596 */
597 __STATIC_INLINE void LL_DMA2D_Suspend(DMA2D_TypeDef *DMA2Dx)
598 {
599 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START, DMA2D_CR_SUSP);
600 }
601
602 /**
603 * @brief Resume DMA2D transfer.
604 * @note This API can be used to resume automatic foreground or background CLUT loading.
605 * @rmtoll CR SUSP LL_DMA2D_Resume
606 * @param DMA2Dx DMA2D Instance
607 * @retval None
608 */
609 __STATIC_INLINE void LL_DMA2D_Resume(DMA2D_TypeDef *DMA2Dx)
610 {
611 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_SUSP | DMA2D_CR_START);
612 }
613
614 /**
615 * @brief Indicate if DMA2D transfer is suspended.
616 * @note This API can be used to indicate whether or not automatic foreground or
617 * background CLUT loading is suspended.
618 * @rmtoll CR SUSP LL_DMA2D_IsSuspended
619 * @param DMA2Dx DMA2D Instance
620 * @retval State of bit (1 or 0).
621 */
622 __STATIC_INLINE uint32_t LL_DMA2D_IsSuspended(const DMA2D_TypeDef *DMA2Dx)
623 {
624 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_SUSP) == (DMA2D_CR_SUSP)) ? 1UL : 0UL);
625 }
626
627 /**
628 * @brief Abort DMA2D transfer.
629 * @note This API can be used to abort automatic foreground or background CLUT loading.
630 * @rmtoll CR ABORT LL_DMA2D_Abort
631 * @param DMA2Dx DMA2D Instance
632 * @retval None
633 */
634 __STATIC_INLINE void LL_DMA2D_Abort(DMA2D_TypeDef *DMA2Dx)
635 {
636 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_ABORT | DMA2D_CR_START, DMA2D_CR_ABORT);
637 }
638
639 /**
640 * @brief Indicate if DMA2D transfer is aborted.
641 * @note This API can be used to indicate whether or not automatic foreground or
642 * background CLUT loading is aborted.
643 * @rmtoll CR ABORT LL_DMA2D_IsAborted
644 * @param DMA2Dx DMA2D Instance
645 * @retval State of bit (1 or 0).
646 */
647 __STATIC_INLINE uint32_t LL_DMA2D_IsAborted(const DMA2D_TypeDef *DMA2Dx)
648 {
649 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_ABORT) == (DMA2D_CR_ABORT)) ? 1UL : 0UL);
650 }
651
652 /**
653 * @brief Set DMA2D mode.
654 * @rmtoll CR MODE LL_DMA2D_SetMode
655 * @param DMA2Dx DMA2D Instance
656 * @param Mode This parameter can be one of the following values:
657 * @arg @ref LL_DMA2D_MODE_M2M
658 * @arg @ref LL_DMA2D_MODE_M2M_PFC
659 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
660 * @arg @ref LL_DMA2D_MODE_R2M
661 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
662 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
663 * @retval None
664 */
665 __STATIC_INLINE void LL_DMA2D_SetMode(DMA2D_TypeDef *DMA2Dx, uint32_t Mode)
666 {
667 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_MODE, Mode);
668 }
669
670 /**
671 * @brief Return DMA2D mode
672 * @rmtoll CR MODE LL_DMA2D_GetMode
673 * @param DMA2Dx DMA2D Instance
674 * @retval Returned value can be one of the following values:
675 * @arg @ref LL_DMA2D_MODE_M2M
676 * @arg @ref LL_DMA2D_MODE_M2M_PFC
677 * @arg @ref LL_DMA2D_MODE_M2M_BLEND
678 * @arg @ref LL_DMA2D_MODE_R2M
679 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_FG
680 * @arg @ref LL_DMA2D_MODE_M2M_BLEND_FIXED_COLOR_BG
681 */
682 __STATIC_INLINE uint32_t LL_DMA2D_GetMode(const DMA2D_TypeDef *DMA2Dx)
683 {
684 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_MODE));
685 }
686
687 /**
688 * @brief Set DMA2D output color mode.
689 * @rmtoll OPFCCR CM LL_DMA2D_SetOutputColorMode
690 * @param DMA2Dx DMA2D Instance
691 * @param ColorMode This parameter can be one of the following values:
692 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
693 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
694 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
695 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
696 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
697 * @retval None
698 */
699 __STATIC_INLINE void LL_DMA2D_SetOutputColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
700 {
701 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM, ColorMode);
702 }
703
704 /**
705 * @brief Return DMA2D output color mode.
706 * @rmtoll OPFCCR CM LL_DMA2D_GetOutputColorMode
707 * @param DMA2Dx DMA2D Instance
708 * @retval Returned value can be one of the following values:
709 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB8888
710 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB888
711 * @arg @ref LL_DMA2D_OUTPUT_MODE_RGB565
712 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB1555
713 * @arg @ref LL_DMA2D_OUTPUT_MODE_ARGB4444
714 */
715 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColorMode(const DMA2D_TypeDef *DMA2Dx)
716 {
717 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_CM));
718 }
719
720 /**
721 * @brief Set DMA2D output Red Blue swap mode.
722 * @rmtoll OPFCCR RBS LL_DMA2D_SetOutputRBSwapMode
723 * @param DMA2Dx DMA2D Instance
724 * @param RBSwapMode This parameter can be one of the following values:
725 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
726 * @arg @ref LL_DMA2D_RB_MODE_SWAP
727 * @retval None
728 */
729 __STATIC_INLINE void LL_DMA2D_SetOutputRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
730 {
731 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS, RBSwapMode);
732 }
733
734 /**
735 * @brief Return DMA2D output Red Blue swap mode.
736 * @rmtoll OPFCCR RBS LL_DMA2D_GetOutputRBSwapMode
737 * @param DMA2Dx DMA2D Instance
738 * @retval Returned value can be one of the following values:
739 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
740 * @arg @ref LL_DMA2D_RB_MODE_SWAP
741 */
742 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
743 {
744 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_RBS));
745 }
746
747 /**
748 * @brief Set DMA2D output alpha inversion mode.
749 * @rmtoll OPFCCR AI LL_DMA2D_SetOutputAlphaInvMode
750 * @param DMA2Dx DMA2D Instance
751 * @param AlphaInversionMode This parameter can be one of the following values:
752 * @arg @ref LL_DMA2D_ALPHA_REGULAR
753 * @arg @ref LL_DMA2D_ALPHA_INVERTED
754 * @retval None
755 */
756 __STATIC_INLINE void LL_DMA2D_SetOutputAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
757 {
758 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI, AlphaInversionMode);
759 }
760
761 /**
762 * @brief Return DMA2D output alpha inversion mode.
763 * @rmtoll OPFCCR AI LL_DMA2D_GetOutputAlphaInvMode
764 * @param DMA2Dx DMA2D Instance
765 * @retval Returned value can be one of the following values:
766 * @arg @ref LL_DMA2D_ALPHA_REGULAR
767 * @arg @ref LL_DMA2D_ALPHA_INVERTED
768 */
769 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
770 {
771 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_AI));
772 }
773
774
775 /**
776 * @brief Set DMA2D output swap mode.
777 * @rmtoll OPFCCR SB LL_DMA2D_SetOutputSwapMode
778 * @param DMA2Dx DMA2D Instance
779 * @param OutputSwapMode This parameter can be one of the following values:
780 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
781 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
782 * @retval None
783 */
784 __STATIC_INLINE void LL_DMA2D_SetOutputSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t OutputSwapMode)
785 {
786 MODIFY_REG(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB, OutputSwapMode);
787 }
788
789 /**
790 * @brief Return DMA2D output swap mode.
791 * @rmtoll OPFCCR SB LL_DMA2D_GetOutputSwapMode
792 * @param DMA2Dx DMA2D Instance
793 * @retval Returned value can be one of the following values:
794 * @arg @ref LL_DMA2D_SWAP_MODE_REGULAR
795 * @arg @ref LL_DMA2D_SWAP_MODE_TWO_BY_TWO
796 */
797 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputSwapMode(const DMA2D_TypeDef *DMA2Dx)
798 {
799 return (uint32_t)(READ_BIT(DMA2Dx->OPFCCR, DMA2D_OPFCCR_SB));
800 }
801
802 /**
803 * @brief Set DMA2D line offset mode.
804 * @rmtoll CR LOM LL_DMA2D_SetLineOffsetMode
805 * @param DMA2Dx DMA2D Instance
806 * @param LineOffsetMode This parameter can be one of the following values:
807 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
808 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
809 * @retval None
810 */
811 __STATIC_INLINE void LL_DMA2D_SetLineOffsetMode(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffsetMode)
812 {
813 MODIFY_REG(DMA2Dx->CR, DMA2D_CR_LOM, LineOffsetMode);
814 }
815
816 /**
817 * @brief Return DMA2D line offset mode.
818 * @rmtoll CR LOM LL_DMA2D_GetLineOffsetMode
819 * @param DMA2Dx DMA2D Instance
820 * @retval Returned value can be one of the following values:
821 * @arg @ref LL_DMA2D_LINE_OFFSET_PIXELS
822 * @arg @ref LL_DMA2D_LINE_OFFSET_BYTES
823 */
824 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffsetMode(const DMA2D_TypeDef *DMA2Dx)
825 {
826 return (uint32_t)(READ_BIT(DMA2Dx->CR, DMA2D_CR_LOM));
827 }
828
829 /**
830 * @brief Set DMA2D line offset, expressed on 14 bits ([13:0] bits).
831 * @rmtoll OOR LO LL_DMA2D_SetLineOffset
832 * @param DMA2Dx DMA2D Instance
833 * @param LineOffset Value between Min_Data=0 and Max_Data=0xFFFF
834 * @retval None
835 */
836 __STATIC_INLINE void LL_DMA2D_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
837 {
838 MODIFY_REG(DMA2Dx->OOR, DMA2D_OOR_LO, LineOffset);
839 }
840
841 /**
842 * @brief Return DMA2D line offset, expressed on 14 bits ([13:0] bits).
843 * @rmtoll OOR LO LL_DMA2D_GetLineOffset
844 * @param DMA2Dx DMA2D Instance
845 * @retval Line offset value between Min_Data=0 and Max_Data=0xFFFF
846 */
847 __STATIC_INLINE uint32_t LL_DMA2D_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
848 {
849 return (uint32_t)(READ_BIT(DMA2Dx->OOR, DMA2D_OOR_LO));
850 }
851
852 /**
853 * @brief Set DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits).
854 * @rmtoll NLR PL LL_DMA2D_SetNbrOfPixelsPerLines
855 * @param DMA2Dx DMA2D Instance
856 * @param NbrOfPixelsPerLines Value between Min_Data=0 and Max_Data=0x3FFF
857 * @retval None
858 */
859 __STATIC_INLINE void LL_DMA2D_SetNbrOfPixelsPerLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfPixelsPerLines)
860 {
861 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_PL, (NbrOfPixelsPerLines << DMA2D_NLR_PL_Pos));
862 }
863
864 /**
865 * @brief Return DMA2D number of pixels per lines, expressed on 14 bits ([13:0] bits)
866 * @rmtoll NLR PL LL_DMA2D_GetNbrOfPixelsPerLines
867 * @param DMA2Dx DMA2D Instance
868 * @retval Number of pixels per lines value between Min_Data=0 and Max_Data=0x3FFF
869 */
870 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfPixelsPerLines(const DMA2D_TypeDef *DMA2Dx)
871 {
872 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_PL) >> DMA2D_NLR_PL_Pos);
873 }
874
875 /**
876 * @brief Set DMA2D number of lines, expressed on 16 bits ([15:0] bits).
877 * @rmtoll NLR NL LL_DMA2D_SetNbrOfLines
878 * @param DMA2Dx DMA2D Instance
879 * @param NbrOfLines Value between Min_Data=0 and Max_Data=0xFFFF
880 * @retval None
881 */
882 __STATIC_INLINE void LL_DMA2D_SetNbrOfLines(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines)
883 {
884 MODIFY_REG(DMA2Dx->NLR, DMA2D_NLR_NL, NbrOfLines);
885 }
886
887 /**
888 * @brief Return DMA2D number of lines, expressed on 16 bits ([15:0] bits).
889 * @rmtoll NLR NL LL_DMA2D_GetNbrOfLines
890 * @param DMA2Dx DMA2D Instance
891 * @retval Number of lines value between Min_Data=0 and Max_Data=0xFFFF
892 */
893 __STATIC_INLINE uint32_t LL_DMA2D_GetNbrOfLines(const DMA2D_TypeDef *DMA2Dx)
894 {
895 return (uint32_t)(READ_BIT(DMA2Dx->NLR, DMA2D_NLR_NL));
896 }
897
898 /**
899 * @brief Set DMA2D output memory address, expressed on 32 bits ([31:0] bits).
900 * @rmtoll OMAR MA LL_DMA2D_SetOutputMemAddr
901 * @param DMA2Dx DMA2D Instance
902 * @param OutputMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
903 * @retval None
904 */
905 __STATIC_INLINE void LL_DMA2D_SetOutputMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t OutputMemoryAddress)
906 {
907 LL_DMA2D_WriteReg(DMA2Dx, OMAR, OutputMemoryAddress);
908 }
909
910 /**
911 * @brief Get DMA2D output memory address, expressed on 32 bits ([31:0] bits).
912 * @rmtoll OMAR MA LL_DMA2D_GetOutputMemAddr
913 * @param DMA2Dx DMA2D Instance
914 * @retval Output memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
915 */
916 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputMemAddr(const DMA2D_TypeDef *DMA2Dx)
917 {
918 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, OMAR));
919 }
920
921 /**
922 * @brief Set DMA2D output color, expressed on 32 bits ([31:0] bits).
923 * @note Output color format depends on output color mode, ARGB8888, RGB888,
924 * RGB565, ARGB1555 or ARGB4444.
925 * @note LL_DMA2D_ConfigOutputColor() API may be used instead if colors values formatting
926 * with respect to color mode is not done by the user code.
927 * @rmtoll OCOLR BLUE LL_DMA2D_SetOutputColor\n
928 * OCOLR GREEN LL_DMA2D_SetOutputColor\n
929 * OCOLR RED LL_DMA2D_SetOutputColor\n
930 * OCOLR ALPHA LL_DMA2D_SetOutputColor
931 * @param DMA2Dx DMA2D Instance
932 * @param OutputColor Value between Min_Data=0 and Max_Data=0xFFFFFFFF
933 * @retval None
934 */
935 __STATIC_INLINE void LL_DMA2D_SetOutputColor(DMA2D_TypeDef *DMA2Dx, uint32_t OutputColor)
936 {
937 WRITE_REG(DMA2Dx->OCOLR, OutputColor);
938 }
939
940 /**
941 * @brief Get DMA2D output color, expressed on 32 bits ([31:0] bits).
942 * @note Alpha channel and red, green, blue color values must be retrieved from the returned
943 * value based on the output color mode (ARGB8888, RGB888, RGB565, ARGB1555 or ARGB4444)
944 * as set by @ref LL_DMA2D_SetOutputColorMode.
945 * @rmtoll OCOLR BLUE LL_DMA2D_GetOutputColor\n
946 * OCOLR GREEN LL_DMA2D_GetOutputColor\n
947 * OCOLR RED LL_DMA2D_GetOutputColor\n
948 * OCOLR ALPHA LL_DMA2D_GetOutputColor
949 * @param DMA2Dx DMA2D Instance
950 * @retval Output color value between Min_Data=0 and Max_Data=0xFFFFFFFF
951 */
952 __STATIC_INLINE uint32_t LL_DMA2D_GetOutputColor(const DMA2D_TypeDef *DMA2Dx)
953 {
954 return (uint32_t)(READ_BIT(DMA2Dx->OCOLR, \
955 (DMA2D_OCOLR_BLUE_1 | DMA2D_OCOLR_GREEN_1 | DMA2D_OCOLR_RED_1 | DMA2D_OCOLR_ALPHA_1)));
956 }
957
958 /**
959 * @brief Set DMA2D line watermark, expressed on 16 bits ([15:0] bits).
960 * @rmtoll LWR LW LL_DMA2D_SetLineWatermark
961 * @param DMA2Dx DMA2D Instance
962 * @param LineWatermark Value between Min_Data=0 and Max_Data=0xFFFF
963 * @retval None
964 */
965 __STATIC_INLINE void LL_DMA2D_SetLineWatermark(DMA2D_TypeDef *DMA2Dx, uint32_t LineWatermark)
966 {
967 MODIFY_REG(DMA2Dx->LWR, DMA2D_LWR_LW, LineWatermark);
968 }
969
970 /**
971 * @brief Return DMA2D line watermark, expressed on 16 bits ([15:0] bits).
972 * @rmtoll LWR LW LL_DMA2D_GetLineWatermark
973 * @param DMA2Dx DMA2D Instance
974 * @retval Line watermark value between Min_Data=0 and Max_Data=0xFFFF
975 */
976 __STATIC_INLINE uint32_t LL_DMA2D_GetLineWatermark(const DMA2D_TypeDef *DMA2Dx)
977 {
978 return (uint32_t)(READ_BIT(DMA2Dx->LWR, DMA2D_LWR_LW));
979 }
980
981 /**
982 * @brief Set DMA2D dead time, expressed on 8 bits ([7:0] bits).
983 * @rmtoll AMTCR DT LL_DMA2D_SetDeadTime
984 * @param DMA2Dx DMA2D Instance
985 * @param DeadTime Value between Min_Data=0 and Max_Data=0xFF
986 * @retval None
987 */
988 __STATIC_INLINE void LL_DMA2D_SetDeadTime(DMA2D_TypeDef *DMA2Dx, uint32_t DeadTime)
989 {
990 MODIFY_REG(DMA2Dx->AMTCR, DMA2D_AMTCR_DT, (DeadTime << DMA2D_AMTCR_DT_Pos));
991 }
992
993 /**
994 * @brief Return DMA2D dead time, expressed on 8 bits ([7:0] bits).
995 * @rmtoll AMTCR DT LL_DMA2D_GetDeadTime
996 * @param DMA2Dx DMA2D Instance
997 * @retval Dead time value between Min_Data=0 and Max_Data=0xFF
998 */
999 __STATIC_INLINE uint32_t LL_DMA2D_GetDeadTime(const DMA2D_TypeDef *DMA2Dx)
1000 {
1001 return (uint32_t)(READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_DT) >> DMA2D_AMTCR_DT_Pos);
1002 }
1003
1004 /**
1005 * @brief Enable DMA2D dead time functionality.
1006 * @rmtoll AMTCR EN LL_DMA2D_EnableDeadTime
1007 * @param DMA2Dx DMA2D Instance
1008 * @retval None
1009 */
1010 __STATIC_INLINE void LL_DMA2D_EnableDeadTime(DMA2D_TypeDef *DMA2Dx)
1011 {
1012 SET_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1013 }
1014
1015 /**
1016 * @brief Disable DMA2D dead time functionality.
1017 * @rmtoll AMTCR EN LL_DMA2D_DisableDeadTime
1018 * @param DMA2Dx DMA2D Instance
1019 * @retval None
1020 */
1021 __STATIC_INLINE void LL_DMA2D_DisableDeadTime(DMA2D_TypeDef *DMA2Dx)
1022 {
1023 CLEAR_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN);
1024 }
1025
1026 /**
1027 * @brief Indicate if DMA2D dead time functionality is enabled.
1028 * @rmtoll AMTCR EN LL_DMA2D_IsEnabledDeadTime
1029 * @param DMA2Dx DMA2D Instance
1030 * @retval State of bit (1 or 0).
1031 */
1032 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledDeadTime(const DMA2D_TypeDef *DMA2Dx)
1033 {
1034 return ((READ_BIT(DMA2Dx->AMTCR, DMA2D_AMTCR_EN) == (DMA2D_AMTCR_EN)) ? 1UL : 0UL);
1035 }
1036
1037 /** @defgroup DMA2D_LL_EF_FGND_Configuration Foreground Configuration Functions
1038 * @{
1039 */
1040
1041 /**
1042 * @brief Set DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1043 * @rmtoll FGMAR MA LL_DMA2D_FGND_SetMemAddr
1044 * @param DMA2Dx DMA2D Instance
1045 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1046 * @retval None
1047 */
1048 __STATIC_INLINE void LL_DMA2D_FGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1049 {
1050 LL_DMA2D_WriteReg(DMA2Dx, FGMAR, MemoryAddress);
1051 }
1052
1053 /**
1054 * @brief Get DMA2D foreground memory address, expressed on 32 bits ([31:0] bits).
1055 * @rmtoll FGMAR MA LL_DMA2D_FGND_GetMemAddr
1056 * @param DMA2Dx DMA2D Instance
1057 * @retval Foreground memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1058 */
1059 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1060 {
1061 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGMAR));
1062 }
1063
1064 /**
1065 * @brief Enable DMA2D foreground CLUT loading.
1066 * @rmtoll FGPFCCR START LL_DMA2D_FGND_EnableCLUTLoad
1067 * @param DMA2Dx DMA2D Instance
1068 * @retval None
1069 */
1070 __STATIC_INLINE void LL_DMA2D_FGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1071 {
1072 SET_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START);
1073 }
1074
1075 /**
1076 * @brief Indicate if DMA2D foreground CLUT loading is enabled.
1077 * @rmtoll FGPFCCR START LL_DMA2D_FGND_IsEnabledCLUTLoad
1078 * @param DMA2Dx DMA2D Instance
1079 * @retval State of bit (1 or 0).
1080 */
1081 __STATIC_INLINE uint32_t LL_DMA2D_FGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1082 {
1083 return ((READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_START) == (DMA2D_FGPFCCR_START)) ? 1UL : 0UL);
1084 }
1085
1086 /**
1087 * @brief Set DMA2D foreground color mode.
1088 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_SetColorMode
1089 * @param DMA2Dx DMA2D Instance
1090 * @param ColorMode This parameter can be one of the following values:
1091 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1092 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1093 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1094 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1095 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1096 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1097 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1098 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1099 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1100 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1101 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1102 * @retval None
1103 */
1104 __STATIC_INLINE void LL_DMA2D_FGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1105 {
1106 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM, ColorMode);
1107 }
1108
1109 /**
1110 * @brief Return DMA2D foreground color mode.
1111 * @rmtoll FGPFCCR CM LL_DMA2D_FGND_GetColorMode
1112 * @param DMA2Dx DMA2D Instance
1113 * @retval Returned value can be one of the following values:
1114 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1115 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1116 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1117 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1118 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1119 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1120 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1121 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1122 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1123 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1124 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1125 */
1126 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1127 {
1128 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CM));
1129 }
1130
1131 /**
1132 * @brief Set DMA2D foreground alpha mode.
1133 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_SetAlphaMode
1134 * @param DMA2Dx DMA2D Instance
1135 * @param AphaMode This parameter can be one of the following values:
1136 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1137 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1138 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1139 * @retval None
1140 */
1141 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1142 {
1143 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM, AphaMode);
1144 }
1145
1146 /**
1147 * @brief Return DMA2D foreground alpha mode.
1148 * @rmtoll FGPFCCR AM LL_DMA2D_FGND_GetAlphaMode
1149 * @param DMA2Dx DMA2D Instance
1150 * @retval Returned value can be one of the following values:
1151 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1152 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1153 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1154 */
1155 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1156 {
1157 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AM));
1158 }
1159
1160 /**
1161 * @brief Set DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1162 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_SetAlpha
1163 * @param DMA2Dx DMA2D Instance
1164 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1165 * @retval None
1166 */
1167 __STATIC_INLINE void LL_DMA2D_FGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1168 {
1169 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA, (Alpha << DMA2D_FGPFCCR_ALPHA_Pos));
1170 }
1171
1172 /**
1173 * @brief Return DMA2D foreground alpha value, expressed on 8 bits ([7:0] bits).
1174 * @rmtoll FGPFCCR ALPHA LL_DMA2D_FGND_GetAlpha
1175 * @param DMA2Dx DMA2D Instance
1176 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1177 */
1178 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1179 {
1180 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_ALPHA) >> DMA2D_FGPFCCR_ALPHA_Pos);
1181 }
1182
1183 /**
1184 * @brief Set DMA2D foreground Red Blue swap mode.
1185 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_SetRBSwapMode
1186 * @param DMA2Dx DMA2D Instance
1187 * @param RBSwapMode This parameter can be one of the following values:
1188 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1189 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1190 * @retval None
1191 */
1192 __STATIC_INLINE void LL_DMA2D_FGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1193 {
1194 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS, RBSwapMode);
1195 }
1196
1197 /**
1198 * @brief Return DMA2D foreground Red Blue swap mode.
1199 * @rmtoll FGPFCCR RBS LL_DMA2D_FGND_GetRBSwapMode
1200 * @param DMA2Dx DMA2D Instance
1201 * @retval Returned value can be one of the following values:
1202 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1203 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1204 */
1205 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1206 {
1207 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_RBS));
1208 }
1209
1210 /**
1211 * @brief Set DMA2D foreground alpha inversion mode.
1212 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_SetAlphaInvMode
1213 * @param DMA2Dx DMA2D Instance
1214 * @param AlphaInversionMode This parameter can be one of the following values:
1215 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1216 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1217 * @retval None
1218 */
1219 __STATIC_INLINE void LL_DMA2D_FGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1220 {
1221 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI, AlphaInversionMode);
1222 }
1223
1224 /**
1225 * @brief Return DMA2D foreground alpha inversion mode.
1226 * @rmtoll FGPFCCR AI LL_DMA2D_FGND_GetAlphaInvMode
1227 * @param DMA2Dx DMA2D Instance
1228 * @retval Returned value can be one of the following values:
1229 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1230 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1231 */
1232 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1233 {
1234 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_AI));
1235 }
1236
1237 /**
1238 * @brief Set DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1239 * @rmtoll FGOR LO LL_DMA2D_FGND_SetLineOffset
1240 * @param DMA2Dx DMA2D Instance
1241 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1242 * @retval None
1243 */
1244 __STATIC_INLINE void LL_DMA2D_FGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1245 {
1246 MODIFY_REG(DMA2Dx->FGOR, DMA2D_FGOR_LO, LineOffset);
1247 }
1248
1249 /**
1250 * @brief Return DMA2D foreground line offset, expressed on 14 bits ([13:0] bits).
1251 * @rmtoll FGOR LO LL_DMA2D_FGND_GetLineOffset
1252 * @param DMA2Dx DMA2D Instance
1253 * @retval Foreground line offset value between Min_Data=0 and Max_Data=0x3FF
1254 */
1255 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1256 {
1257 return (uint32_t)(READ_BIT(DMA2Dx->FGOR, DMA2D_FGOR_LO));
1258 }
1259
1260 /**
1261 * @brief Set DMA2D foreground color values, expressed on 24 bits ([23:0] bits).
1262 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetColor
1263 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetColor
1264 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetColor
1265 * @param DMA2Dx DMA2D Instance
1266 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1267 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1268 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1269 * @retval None
1270 */
1271 __STATIC_INLINE void LL_DMA2D_FGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1272 {
1273 MODIFY_REG(DMA2Dx->FGCOLR, (DMA2D_FGCOLR_RED | DMA2D_FGCOLR_GREEN | DMA2D_FGCOLR_BLUE), \
1274 ((Red << DMA2D_FGCOLR_RED_Pos) | (Green << DMA2D_FGCOLR_GREEN_Pos) | Blue));
1275 }
1276
1277 /**
1278 * @brief Set DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1279 * @rmtoll FGCOLR RED LL_DMA2D_FGND_SetRedColor
1280 * @param DMA2Dx DMA2D Instance
1281 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1282 * @retval None
1283 */
1284 __STATIC_INLINE void LL_DMA2D_FGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1285 {
1286 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED, (Red << DMA2D_FGCOLR_RED_Pos));
1287 }
1288
1289 /**
1290 * @brief Return DMA2D foreground red color value, expressed on 8 bits ([7:0] bits).
1291 * @rmtoll FGCOLR RED LL_DMA2D_FGND_GetRedColor
1292 * @param DMA2Dx DMA2D Instance
1293 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1294 */
1295 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1296 {
1297 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_RED) >> DMA2D_FGCOLR_RED_Pos);
1298 }
1299
1300 /**
1301 * @brief Set DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1302 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_SetGreenColor
1303 * @param DMA2Dx DMA2D Instance
1304 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1305 * @retval None
1306 */
1307 __STATIC_INLINE void LL_DMA2D_FGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1308 {
1309 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN, (Green << DMA2D_FGCOLR_GREEN_Pos));
1310 }
1311
1312 /**
1313 * @brief Return DMA2D foreground green color value, expressed on 8 bits ([7:0] bits).
1314 * @rmtoll FGCOLR GREEN LL_DMA2D_FGND_GetGreenColor
1315 * @param DMA2Dx DMA2D Instance
1316 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1317 */
1318 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1319 {
1320 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_GREEN) >> DMA2D_FGCOLR_GREEN_Pos);
1321 }
1322
1323 /**
1324 * @brief Set DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1325 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_SetBlueColor
1326 * @param DMA2Dx DMA2D Instance
1327 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1328 * @retval None
1329 */
1330 __STATIC_INLINE void LL_DMA2D_FGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1331 {
1332 MODIFY_REG(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE, Blue);
1333 }
1334
1335 /**
1336 * @brief Return DMA2D foreground blue color value, expressed on 8 bits ([7:0] bits).
1337 * @rmtoll FGCOLR BLUE LL_DMA2D_FGND_GetBlueColor
1338 * @param DMA2Dx DMA2D Instance
1339 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1340 */
1341 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1342 {
1343 return (uint32_t)(READ_BIT(DMA2Dx->FGCOLR, DMA2D_FGCOLR_BLUE));
1344 }
1345
1346 /**
1347 * @brief Set DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1348 * @rmtoll FGCMAR MA LL_DMA2D_FGND_SetCLUTMemAddr
1349 * @param DMA2Dx DMA2D Instance
1350 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1351 * @retval None
1352 */
1353 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1354 {
1355 LL_DMA2D_WriteReg(DMA2Dx, FGCMAR, CLUTMemoryAddress);
1356 }
1357
1358 /**
1359 * @brief Get DMA2D foreground CLUT memory address, expressed on 32 bits ([31:0] bits).
1360 * @rmtoll FGCMAR MA LL_DMA2D_FGND_GetCLUTMemAddr
1361 * @param DMA2Dx DMA2D Instance
1362 * @retval Foreground CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1363 */
1364 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1365 {
1366 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, FGCMAR));
1367 }
1368
1369 /**
1370 * @brief Set DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1371 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_SetCLUTSize
1372 * @param DMA2Dx DMA2D Instance
1373 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1374 * @retval None
1375 */
1376 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1377 {
1378 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS, (CLUTSize << DMA2D_FGPFCCR_CS_Pos));
1379 }
1380
1381 /**
1382 * @brief Get DMA2D foreground CLUT size, expressed on 8 bits ([7:0] bits).
1383 * @rmtoll FGPFCCR CS LL_DMA2D_FGND_GetCLUTSize
1384 * @param DMA2Dx DMA2D Instance
1385 * @retval Foreground CLUT size value between Min_Data=0 and Max_Data=0xFF
1386 */
1387 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1388 {
1389 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CS) >> DMA2D_FGPFCCR_CS_Pos);
1390 }
1391
1392 /**
1393 * @brief Set DMA2D foreground CLUT color mode.
1394 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_SetCLUTColorMode
1395 * @param DMA2Dx DMA2D Instance
1396 * @param CLUTColorMode This parameter can be one of the following values:
1397 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1398 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1399 * @retval None
1400 */
1401 __STATIC_INLINE void LL_DMA2D_FGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1402 {
1403 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM, CLUTColorMode);
1404 }
1405
1406 /**
1407 * @brief Return DMA2D foreground CLUT color mode.
1408 * @rmtoll FGPFCCR CCM LL_DMA2D_FGND_GetCLUTColorMode
1409 * @param DMA2Dx DMA2D Instance
1410 * @retval Returned value can be one of the following values:
1411 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1412 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1413 */
1414 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1415 {
1416 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CCM));
1417 }
1418
1419 /**
1420 * @brief Set DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1421 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_SetChrSubSampling
1422 * @param DMA2Dx DMA2D Instance
1423 * @param ChromaSubSampling This parameter can be one of the following values:
1424 * @arg @ref LL_DMA2D_CSS_444
1425 * @arg @ref LL_DMA2D_CSS_422
1426 * @arg @ref LL_DMA2D_CSS_420
1427 * @retval None
1428 */
1429 __STATIC_INLINE void LL_DMA2D_FGND_SetChrSubSampling(DMA2D_TypeDef *DMA2Dx, uint32_t ChromaSubSampling)
1430 {
1431 MODIFY_REG(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS, ChromaSubSampling);
1432 }
1433
1434 /**
1435 * @brief Return DMA2D foreground Chroma Sub Sampling (for YCbCr input color mode).
1436 * @rmtoll FGPFCCR CSS LL_DMA2D_FGND_GetChrSubSampling
1437 * @param DMA2Dx DMA2D Instance
1438 * @retval Returned value can be one of the following values:
1439 * @arg @ref LL_DMA2D_CSS_444
1440 * @arg @ref LL_DMA2D_CSS_422
1441 * @arg @ref LL_DMA2D_CSS_420
1442 */
1443 __STATIC_INLINE uint32_t LL_DMA2D_FGND_GetChrSubSampling(const DMA2D_TypeDef *DMA2Dx)
1444 {
1445 return (uint32_t)(READ_BIT(DMA2Dx->FGPFCCR, DMA2D_FGPFCCR_CSS));
1446 }
1447 /**
1448 * @}
1449 */
1450
1451 /** @defgroup DMA2D_LL_EF_BGND_Configuration Background Configuration Functions
1452 * @{
1453 */
1454
1455 /**
1456 * @brief Set DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1457 * @rmtoll BGMAR MA LL_DMA2D_BGND_SetMemAddr
1458 * @param DMA2Dx DMA2D Instance
1459 * @param MemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1460 * @retval None
1461 */
1462 __STATIC_INLINE void LL_DMA2D_BGND_SetMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t MemoryAddress)
1463 {
1464 LL_DMA2D_WriteReg(DMA2Dx, BGMAR, MemoryAddress);
1465 }
1466
1467 /**
1468 * @brief Get DMA2D background memory address, expressed on 32 bits ([31:0] bits).
1469 * @rmtoll BGMAR MA LL_DMA2D_BGND_GetMemAddr
1470 * @param DMA2Dx DMA2D Instance
1471 * @retval Background memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1472 */
1473 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetMemAddr(const DMA2D_TypeDef *DMA2Dx)
1474 {
1475 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGMAR));
1476 }
1477
1478 /**
1479 * @brief Enable DMA2D background CLUT loading.
1480 * @rmtoll BGPFCCR START LL_DMA2D_BGND_EnableCLUTLoad
1481 * @param DMA2Dx DMA2D Instance
1482 * @retval None
1483 */
1484 __STATIC_INLINE void LL_DMA2D_BGND_EnableCLUTLoad(DMA2D_TypeDef *DMA2Dx)
1485 {
1486 SET_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START);
1487 }
1488
1489 /**
1490 * @brief Indicate if DMA2D background CLUT loading is enabled.
1491 * @rmtoll BGPFCCR START LL_DMA2D_BGND_IsEnabledCLUTLoad
1492 * @param DMA2Dx DMA2D Instance
1493 * @retval State of bit (1 or 0).
1494 */
1495 __STATIC_INLINE uint32_t LL_DMA2D_BGND_IsEnabledCLUTLoad(const DMA2D_TypeDef *DMA2Dx)
1496 {
1497 return ((READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_START) == (DMA2D_BGPFCCR_START)) ? 1UL : 0UL);
1498 }
1499
1500 /**
1501 * @brief Set DMA2D background color mode.
1502 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_SetColorMode
1503 * @param DMA2Dx DMA2D Instance
1504 * @param ColorMode This parameter can be one of the following values:
1505 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1506 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1507 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1508 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1509 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1510 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1511 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1512 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1513 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1514 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1515 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1516 * @retval None
1517 */
1518 __STATIC_INLINE void LL_DMA2D_BGND_SetColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode)
1519 {
1520 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM, ColorMode);
1521 }
1522
1523 /**
1524 * @brief Return DMA2D background color mode.
1525 * @rmtoll BGPFCCR CM LL_DMA2D_BGND_GetColorMode
1526 * @param DMA2Dx DMA2D Instance
1527 * @retval Returned value can be one of the following values:
1528 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB8888
1529 * @arg @ref LL_DMA2D_INPUT_MODE_RGB888
1530 * @arg @ref LL_DMA2D_INPUT_MODE_RGB565
1531 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB1555
1532 * @arg @ref LL_DMA2D_INPUT_MODE_ARGB4444
1533 * @arg @ref LL_DMA2D_INPUT_MODE_L8
1534 * @arg @ref LL_DMA2D_INPUT_MODE_AL44
1535 * @arg @ref LL_DMA2D_INPUT_MODE_AL88
1536 * @arg @ref LL_DMA2D_INPUT_MODE_L4
1537 * @arg @ref LL_DMA2D_INPUT_MODE_A8
1538 * @arg @ref LL_DMA2D_INPUT_MODE_A4
1539 */
1540 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetColorMode(const DMA2D_TypeDef *DMA2Dx)
1541 {
1542 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CM));
1543 }
1544
1545 /**
1546 * @brief Set DMA2D background alpha mode.
1547 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_SetAlphaMode
1548 * @param DMA2Dx DMA2D Instance
1549 * @param AphaMode This parameter can be one of the following values:
1550 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1551 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1552 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1553 * @retval None
1554 */
1555 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaMode(DMA2D_TypeDef *DMA2Dx, uint32_t AphaMode)
1556 {
1557 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM, AphaMode);
1558 }
1559
1560 /**
1561 * @brief Return DMA2D background alpha mode.
1562 * @rmtoll BGPFCCR AM LL_DMA2D_BGND_GetAlphaMode
1563 * @param DMA2Dx DMA2D Instance
1564 * @retval Returned value can be one of the following values:
1565 * @arg @ref LL_DMA2D_ALPHA_MODE_NO_MODIF
1566 * @arg @ref LL_DMA2D_ALPHA_MODE_REPLACE
1567 * @arg @ref LL_DMA2D_ALPHA_MODE_COMBINE
1568 */
1569 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaMode(const DMA2D_TypeDef *DMA2Dx)
1570 {
1571 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AM));
1572 }
1573
1574 /**
1575 * @brief Set DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1576 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_SetAlpha
1577 * @param DMA2Dx DMA2D Instance
1578 * @param Alpha Value between Min_Data=0 and Max_Data=0xFF
1579 * @retval None
1580 */
1581 __STATIC_INLINE void LL_DMA2D_BGND_SetAlpha(DMA2D_TypeDef *DMA2Dx, uint32_t Alpha)
1582 {
1583 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA, (Alpha << DMA2D_BGPFCCR_ALPHA_Pos));
1584 }
1585
1586 /**
1587 * @brief Return DMA2D background alpha value, expressed on 8 bits ([7:0] bits).
1588 * @rmtoll BGPFCCR ALPHA LL_DMA2D_BGND_GetAlpha
1589 * @param DMA2Dx DMA2D Instance
1590 * @retval Alpha value between Min_Data=0 and Max_Data=0xFF
1591 */
1592 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlpha(const DMA2D_TypeDef *DMA2Dx)
1593 {
1594 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_ALPHA) >> DMA2D_BGPFCCR_ALPHA_Pos);
1595 }
1596
1597 /**
1598 * @brief Set DMA2D background Red Blue swap mode.
1599 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_SetRBSwapMode
1600 * @param DMA2Dx DMA2D Instance
1601 * @param RBSwapMode This parameter can be one of the following values:
1602 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1603 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1604 * @retval None
1605 */
1606 __STATIC_INLINE void LL_DMA2D_BGND_SetRBSwapMode(DMA2D_TypeDef *DMA2Dx, uint32_t RBSwapMode)
1607 {
1608 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS, RBSwapMode);
1609 }
1610
1611 /**
1612 * @brief Return DMA2D background Red Blue swap mode.
1613 * @rmtoll BGPFCCR RBS LL_DMA2D_BGND_GetRBSwapMode
1614 * @param DMA2Dx DMA2D Instance
1615 * @retval Returned value can be one of the following values:
1616 * @arg @ref LL_DMA2D_RB_MODE_REGULAR
1617 * @arg @ref LL_DMA2D_RB_MODE_SWAP
1618 */
1619 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRBSwapMode(const DMA2D_TypeDef *DMA2Dx)
1620 {
1621 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_RBS));
1622 }
1623
1624 /**
1625 * @brief Set DMA2D background alpha inversion mode.
1626 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_SetAlphaInvMode
1627 * @param DMA2Dx DMA2D Instance
1628 * @param AlphaInversionMode This parameter can be one of the following values:
1629 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1630 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1631 * @retval None
1632 */
1633 __STATIC_INLINE void LL_DMA2D_BGND_SetAlphaInvMode(DMA2D_TypeDef *DMA2Dx, uint32_t AlphaInversionMode)
1634 {
1635 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI, AlphaInversionMode);
1636 }
1637
1638 /**
1639 * @brief Return DMA2D background alpha inversion mode.
1640 * @rmtoll BGPFCCR AI LL_DMA2D_BGND_GetAlphaInvMode
1641 * @param DMA2Dx DMA2D Instance
1642 * @retval Returned value can be one of the following values:
1643 * @arg @ref LL_DMA2D_ALPHA_REGULAR
1644 * @arg @ref LL_DMA2D_ALPHA_INVERTED
1645 */
1646 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetAlphaInvMode(const DMA2D_TypeDef *DMA2Dx)
1647 {
1648 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_AI));
1649 }
1650
1651 /**
1652 * @brief Set DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1653 * @rmtoll BGOR LO LL_DMA2D_BGND_SetLineOffset
1654 * @param DMA2Dx DMA2D Instance
1655 * @param LineOffset Value between Min_Data=0 and Max_Data=0x3FF
1656 * @retval None
1657 */
1658 __STATIC_INLINE void LL_DMA2D_BGND_SetLineOffset(DMA2D_TypeDef *DMA2Dx, uint32_t LineOffset)
1659 {
1660 MODIFY_REG(DMA2Dx->BGOR, DMA2D_BGOR_LO, LineOffset);
1661 }
1662
1663 /**
1664 * @brief Return DMA2D background line offset, expressed on 14 bits ([13:0] bits).
1665 * @rmtoll BGOR LO LL_DMA2D_BGND_GetLineOffset
1666 * @param DMA2Dx DMA2D Instance
1667 * @retval Background line offset value between Min_Data=0 and Max_Data=0x3FF
1668 */
1669 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetLineOffset(const DMA2D_TypeDef *DMA2Dx)
1670 {
1671 return (uint32_t)(READ_BIT(DMA2Dx->BGOR, DMA2D_BGOR_LO));
1672 }
1673
1674 /**
1675 * @brief Set DMA2D background color values, expressed on 24 bits ([23:0] bits).
1676 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetColor
1677 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetColor
1678 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetColor
1679 * @param DMA2Dx DMA2D Instance
1680 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1681 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1682 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1683 * @retval None
1684 */
1685 __STATIC_INLINE void LL_DMA2D_BGND_SetColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red, uint32_t Green, uint32_t Blue)
1686 {
1687 MODIFY_REG(DMA2Dx->BGCOLR, (DMA2D_BGCOLR_RED | DMA2D_BGCOLR_GREEN | DMA2D_BGCOLR_BLUE), \
1688 ((Red << DMA2D_BGCOLR_RED_Pos) | (Green << DMA2D_BGCOLR_GREEN_Pos) | Blue));
1689 }
1690
1691 /**
1692 * @brief Set DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1693 * @rmtoll BGCOLR RED LL_DMA2D_BGND_SetRedColor
1694 * @param DMA2Dx DMA2D Instance
1695 * @param Red Value between Min_Data=0 and Max_Data=0xFF
1696 * @retval None
1697 */
1698 __STATIC_INLINE void LL_DMA2D_BGND_SetRedColor(DMA2D_TypeDef *DMA2Dx, uint32_t Red)
1699 {
1700 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED, (Red << DMA2D_BGCOLR_RED_Pos));
1701 }
1702
1703 /**
1704 * @brief Return DMA2D background red color value, expressed on 8 bits ([7:0] bits).
1705 * @rmtoll BGCOLR RED LL_DMA2D_BGND_GetRedColor
1706 * @param DMA2Dx DMA2D Instance
1707 * @retval Red color value between Min_Data=0 and Max_Data=0xFF
1708 */
1709 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetRedColor(const DMA2D_TypeDef *DMA2Dx)
1710 {
1711 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_RED) >> DMA2D_BGCOLR_RED_Pos);
1712 }
1713
1714 /**
1715 * @brief Set DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1716 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_SetGreenColor
1717 * @param DMA2Dx DMA2D Instance
1718 * @param Green Value between Min_Data=0 and Max_Data=0xFF
1719 * @retval None
1720 */
1721 __STATIC_INLINE void LL_DMA2D_BGND_SetGreenColor(DMA2D_TypeDef *DMA2Dx, uint32_t Green)
1722 {
1723 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN, (Green << DMA2D_BGCOLR_GREEN_Pos));
1724 }
1725
1726 /**
1727 * @brief Return DMA2D background green color value, expressed on 8 bits ([7:0] bits).
1728 * @rmtoll BGCOLR GREEN LL_DMA2D_BGND_GetGreenColor
1729 * @param DMA2Dx DMA2D Instance
1730 * @retval Green color value between Min_Data=0 and Max_Data=0xFF
1731 */
1732 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetGreenColor(const DMA2D_TypeDef *DMA2Dx)
1733 {
1734 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_GREEN) >> DMA2D_BGCOLR_GREEN_Pos);
1735 }
1736
1737 /**
1738 * @brief Set DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1739 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_SetBlueColor
1740 * @param DMA2Dx DMA2D Instance
1741 * @param Blue Value between Min_Data=0 and Max_Data=0xFF
1742 * @retval None
1743 */
1744 __STATIC_INLINE void LL_DMA2D_BGND_SetBlueColor(DMA2D_TypeDef *DMA2Dx, uint32_t Blue)
1745 {
1746 MODIFY_REG(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE, Blue);
1747 }
1748
1749 /**
1750 * @brief Return DMA2D background blue color value, expressed on 8 bits ([7:0] bits).
1751 * @rmtoll BGCOLR BLUE LL_DMA2D_BGND_GetBlueColor
1752 * @param DMA2Dx DMA2D Instance
1753 * @retval Blue color value between Min_Data=0 and Max_Data=0xFF
1754 */
1755 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetBlueColor(const DMA2D_TypeDef *DMA2Dx)
1756 {
1757 return (uint32_t)(READ_BIT(DMA2Dx->BGCOLR, DMA2D_BGCOLR_BLUE));
1758 }
1759
1760 /**
1761 * @brief Set DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1762 * @rmtoll BGCMAR MA LL_DMA2D_BGND_SetCLUTMemAddr
1763 * @param DMA2Dx DMA2D Instance
1764 * @param CLUTMemoryAddress Value between Min_Data=0 and Max_Data=0xFFFFFFFF
1765 * @retval None
1766 */
1767 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTMemAddr(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTMemoryAddress)
1768 {
1769 LL_DMA2D_WriteReg(DMA2Dx, BGCMAR, CLUTMemoryAddress);
1770 }
1771
1772 /**
1773 * @brief Get DMA2D background CLUT memory address, expressed on 32 bits ([31:0] bits).
1774 * @rmtoll BGCMAR MA LL_DMA2D_BGND_GetCLUTMemAddr
1775 * @param DMA2Dx DMA2D Instance
1776 * @retval Background CLUT memory address value between Min_Data=0 and Max_Data=0xFFFFFFFF
1777 */
1778 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTMemAddr(const DMA2D_TypeDef *DMA2Dx)
1779 {
1780 return (uint32_t)(LL_DMA2D_ReadReg(DMA2Dx, BGCMAR));
1781 }
1782
1783 /**
1784 * @brief Set DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1785 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_SetCLUTSize
1786 * @param DMA2Dx DMA2D Instance
1787 * @param CLUTSize Value between Min_Data=0 and Max_Data=0xFF
1788 * @retval None
1789 */
1790 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTSize(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTSize)
1791 {
1792 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS, (CLUTSize << DMA2D_BGPFCCR_CS_Pos));
1793 }
1794
1795 /**
1796 * @brief Get DMA2D background CLUT size, expressed on 8 bits ([7:0] bits).
1797 * @rmtoll BGPFCCR CS LL_DMA2D_BGND_GetCLUTSize
1798 * @param DMA2Dx DMA2D Instance
1799 * @retval Background CLUT size value between Min_Data=0 and Max_Data=0xFF
1800 */
1801 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTSize(const DMA2D_TypeDef *DMA2Dx)
1802 {
1803 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CS) >> DMA2D_BGPFCCR_CS_Pos);
1804 }
1805
1806 /**
1807 * @brief Set DMA2D background CLUT color mode.
1808 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_SetCLUTColorMode
1809 * @param DMA2Dx DMA2D Instance
1810 * @param CLUTColorMode This parameter can be one of the following values:
1811 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1812 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1813 * @retval None
1814 */
1815 __STATIC_INLINE void LL_DMA2D_BGND_SetCLUTColorMode(DMA2D_TypeDef *DMA2Dx, uint32_t CLUTColorMode)
1816 {
1817 MODIFY_REG(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM, CLUTColorMode);
1818 }
1819
1820 /**
1821 * @brief Return DMA2D background CLUT color mode.
1822 * @rmtoll BGPFCCR CCM LL_DMA2D_BGND_GetCLUTColorMode
1823 * @param DMA2Dx DMA2D Instance
1824 * @retval Returned value can be one of the following values:
1825 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_ARGB8888
1826 * @arg @ref LL_DMA2D_CLUT_COLOR_MODE_RGB888
1827 */
1828 __STATIC_INLINE uint32_t LL_DMA2D_BGND_GetCLUTColorMode(const DMA2D_TypeDef *DMA2Dx)
1829 {
1830 return (uint32_t)(READ_BIT(DMA2Dx->BGPFCCR, DMA2D_BGPFCCR_CCM));
1831 }
1832
1833 /**
1834 * @}
1835 */
1836
1837 /**
1838 * @}
1839 */
1840
1841
1842 /** @defgroup DMA2D_LL_EF_FLAG_MANAGEMENT Flag Management
1843 * @{
1844 */
1845
1846 /**
1847 * @brief Check if the DMA2D Configuration Error Interrupt Flag is set or not
1848 * @rmtoll ISR CEIF LL_DMA2D_IsActiveFlag_CE
1849 * @param DMA2Dx DMA2D Instance
1850 * @retval State of bit (1 or 0).
1851 */
1852 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CE(const DMA2D_TypeDef *DMA2Dx)
1853 {
1854 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CEIF) == (DMA2D_ISR_CEIF)) ? 1UL : 0UL);
1855 }
1856
1857 /**
1858 * @brief Check if the DMA2D CLUT Transfer Complete Interrupt Flag is set or not
1859 * @rmtoll ISR CTCIF LL_DMA2D_IsActiveFlag_CTC
1860 * @param DMA2Dx DMA2D Instance
1861 * @retval State of bit (1 or 0).
1862 */
1863 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CTC(const DMA2D_TypeDef *DMA2Dx)
1864 {
1865 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CTCIF) == (DMA2D_ISR_CTCIF)) ? 1UL : 0UL);
1866 }
1867
1868 /**
1869 * @brief Check if the DMA2D CLUT Access Error Interrupt Flag is set or not
1870 * @rmtoll ISR CAEIF LL_DMA2D_IsActiveFlag_CAE
1871 * @param DMA2Dx DMA2D Instance
1872 * @retval State of bit (1 or 0).
1873 */
1874 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_CAE(const DMA2D_TypeDef *DMA2Dx)
1875 {
1876 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_CAEIF) == (DMA2D_ISR_CAEIF)) ? 1UL : 0UL);
1877 }
1878
1879 /**
1880 * @brief Check if the DMA2D Transfer Watermark Interrupt Flag is set or not
1881 * @rmtoll ISR TWIF LL_DMA2D_IsActiveFlag_TW
1882 * @param DMA2Dx DMA2D Instance
1883 * @retval State of bit (1 or 0).
1884 */
1885 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TW(const DMA2D_TypeDef *DMA2Dx)
1886 {
1887 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TWIF) == (DMA2D_ISR_TWIF)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Check if the DMA2D Transfer Complete Interrupt Flag is set or not
1892 * @rmtoll ISR TCIF LL_DMA2D_IsActiveFlag_TC
1893 * @param DMA2Dx DMA2D Instance
1894 * @retval State of bit (1 or 0).
1895 */
1896 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TC(const DMA2D_TypeDef *DMA2Dx)
1897 {
1898 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TCIF) == (DMA2D_ISR_TCIF)) ? 1UL : 0UL);
1899 }
1900
1901 /**
1902 * @brief Check if the DMA2D Transfer Error Interrupt Flag is set or not
1903 * @rmtoll ISR TEIF LL_DMA2D_IsActiveFlag_TE
1904 * @param DMA2Dx DMA2D Instance
1905 * @retval State of bit (1 or 0).
1906 */
1907 __STATIC_INLINE uint32_t LL_DMA2D_IsActiveFlag_TE(const DMA2D_TypeDef *DMA2Dx)
1908 {
1909 return ((READ_BIT(DMA2Dx->ISR, DMA2D_ISR_TEIF) == (DMA2D_ISR_TEIF)) ? 1UL : 0UL);
1910 }
1911
1912 /**
1913 * @brief Clear DMA2D Configuration Error Interrupt Flag
1914 * @rmtoll IFCR CCEIF LL_DMA2D_ClearFlag_CE
1915 * @param DMA2Dx DMA2D Instance
1916 * @retval None
1917 */
1918 __STATIC_INLINE void LL_DMA2D_ClearFlag_CE(DMA2D_TypeDef *DMA2Dx)
1919 {
1920 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCEIF);
1921 }
1922
1923 /**
1924 * @brief Clear DMA2D CLUT Transfer Complete Interrupt Flag
1925 * @rmtoll IFCR CCTCIF LL_DMA2D_ClearFlag_CTC
1926 * @param DMA2Dx DMA2D Instance
1927 * @retval None
1928 */
1929 __STATIC_INLINE void LL_DMA2D_ClearFlag_CTC(DMA2D_TypeDef *DMA2Dx)
1930 {
1931 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CCTCIF);
1932 }
1933
1934 /**
1935 * @brief Clear DMA2D CLUT Access Error Interrupt Flag
1936 * @rmtoll IFCR CAECIF LL_DMA2D_ClearFlag_CAE
1937 * @param DMA2Dx DMA2D Instance
1938 * @retval None
1939 */
1940 __STATIC_INLINE void LL_DMA2D_ClearFlag_CAE(DMA2D_TypeDef *DMA2Dx)
1941 {
1942 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CAECIF);
1943 }
1944
1945 /**
1946 * @brief Clear DMA2D Transfer Watermark Interrupt Flag
1947 * @rmtoll IFCR CTWIF LL_DMA2D_ClearFlag_TW
1948 * @param DMA2Dx DMA2D Instance
1949 * @retval None
1950 */
1951 __STATIC_INLINE void LL_DMA2D_ClearFlag_TW(DMA2D_TypeDef *DMA2Dx)
1952 {
1953 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTWIF);
1954 }
1955
1956 /**
1957 * @brief Clear DMA2D Transfer Complete Interrupt Flag
1958 * @rmtoll IFCR CTCIF LL_DMA2D_ClearFlag_TC
1959 * @param DMA2Dx DMA2D Instance
1960 * @retval None
1961 */
1962 __STATIC_INLINE void LL_DMA2D_ClearFlag_TC(DMA2D_TypeDef *DMA2Dx)
1963 {
1964 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTCIF);
1965 }
1966
1967 /**
1968 * @brief Clear DMA2D Transfer Error Interrupt Flag
1969 * @rmtoll IFCR CTEIF LL_DMA2D_ClearFlag_TE
1970 * @param DMA2Dx DMA2D Instance
1971 * @retval None
1972 */
1973 __STATIC_INLINE void LL_DMA2D_ClearFlag_TE(DMA2D_TypeDef *DMA2Dx)
1974 {
1975 WRITE_REG(DMA2Dx->IFCR, DMA2D_IFCR_CTEIF);
1976 }
1977
1978 /**
1979 * @}
1980 */
1981
1982 /** @defgroup DMA2D_LL_EF_IT_MANAGEMENT Interruption Management
1983 * @{
1984 */
1985
1986 /**
1987 * @brief Enable Configuration Error Interrupt
1988 * @rmtoll CR CEIE LL_DMA2D_EnableIT_CE
1989 * @param DMA2Dx DMA2D Instance
1990 * @retval None
1991 */
1992 __STATIC_INLINE void LL_DMA2D_EnableIT_CE(DMA2D_TypeDef *DMA2Dx)
1993 {
1994 SET_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
1995 }
1996
1997 /**
1998 * @brief Enable CLUT Transfer Complete Interrupt
1999 * @rmtoll CR CTCIE LL_DMA2D_EnableIT_CTC
2000 * @param DMA2Dx DMA2D Instance
2001 * @retval None
2002 */
2003 __STATIC_INLINE void LL_DMA2D_EnableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2004 {
2005 SET_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2006 }
2007
2008 /**
2009 * @brief Enable CLUT Access Error Interrupt
2010 * @rmtoll CR CAEIE LL_DMA2D_EnableIT_CAE
2011 * @param DMA2Dx DMA2D Instance
2012 * @retval None
2013 */
2014 __STATIC_INLINE void LL_DMA2D_EnableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2015 {
2016 SET_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2017 }
2018
2019 /**
2020 * @brief Enable Transfer Watermark Interrupt
2021 * @rmtoll CR TWIE LL_DMA2D_EnableIT_TW
2022 * @param DMA2Dx DMA2D Instance
2023 * @retval None
2024 */
2025 __STATIC_INLINE void LL_DMA2D_EnableIT_TW(DMA2D_TypeDef *DMA2Dx)
2026 {
2027 SET_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2028 }
2029
2030 /**
2031 * @brief Enable Transfer Complete Interrupt
2032 * @rmtoll CR TCIE LL_DMA2D_EnableIT_TC
2033 * @param DMA2Dx DMA2D Instance
2034 * @retval None
2035 */
2036 __STATIC_INLINE void LL_DMA2D_EnableIT_TC(DMA2D_TypeDef *DMA2Dx)
2037 {
2038 SET_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2039 }
2040
2041 /**
2042 * @brief Enable Transfer Error Interrupt
2043 * @rmtoll CR TEIE LL_DMA2D_EnableIT_TE
2044 * @param DMA2Dx DMA2D Instance
2045 * @retval None
2046 */
2047 __STATIC_INLINE void LL_DMA2D_EnableIT_TE(DMA2D_TypeDef *DMA2Dx)
2048 {
2049 SET_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2050 }
2051
2052 /**
2053 * @brief Disable Configuration Error Interrupt
2054 * @rmtoll CR CEIE LL_DMA2D_DisableIT_CE
2055 * @param DMA2Dx DMA2D Instance
2056 * @retval None
2057 */
2058 __STATIC_INLINE void LL_DMA2D_DisableIT_CE(DMA2D_TypeDef *DMA2Dx)
2059 {
2060 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CEIE);
2061 }
2062
2063 /**
2064 * @brief Disable CLUT Transfer Complete Interrupt
2065 * @rmtoll CR CTCIE LL_DMA2D_DisableIT_CTC
2066 * @param DMA2Dx DMA2D Instance
2067 * @retval None
2068 */
2069 __STATIC_INLINE void LL_DMA2D_DisableIT_CTC(DMA2D_TypeDef *DMA2Dx)
2070 {
2071 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE);
2072 }
2073
2074 /**
2075 * @brief Disable CLUT Access Error Interrupt
2076 * @rmtoll CR CAEIE LL_DMA2D_DisableIT_CAE
2077 * @param DMA2Dx DMA2D Instance
2078 * @retval None
2079 */
2080 __STATIC_INLINE void LL_DMA2D_DisableIT_CAE(DMA2D_TypeDef *DMA2Dx)
2081 {
2082 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE);
2083 }
2084
2085 /**
2086 * @brief Disable Transfer Watermark Interrupt
2087 * @rmtoll CR TWIE LL_DMA2D_DisableIT_TW
2088 * @param DMA2Dx DMA2D Instance
2089 * @retval None
2090 */
2091 __STATIC_INLINE void LL_DMA2D_DisableIT_TW(DMA2D_TypeDef *DMA2Dx)
2092 {
2093 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TWIE);
2094 }
2095
2096 /**
2097 * @brief Disable Transfer Complete Interrupt
2098 * @rmtoll CR TCIE LL_DMA2D_DisableIT_TC
2099 * @param DMA2Dx DMA2D Instance
2100 * @retval None
2101 */
2102 __STATIC_INLINE void LL_DMA2D_DisableIT_TC(DMA2D_TypeDef *DMA2Dx)
2103 {
2104 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TCIE);
2105 }
2106
2107 /**
2108 * @brief Disable Transfer Error Interrupt
2109 * @rmtoll CR TEIE LL_DMA2D_DisableIT_TE
2110 * @param DMA2Dx DMA2D Instance
2111 * @retval None
2112 */
2113 __STATIC_INLINE void LL_DMA2D_DisableIT_TE(DMA2D_TypeDef *DMA2Dx)
2114 {
2115 CLEAR_BIT(DMA2Dx->CR, DMA2D_CR_TEIE);
2116 }
2117
2118 /**
2119 * @brief Check if the DMA2D Configuration Error interrupt source is enabled or disabled.
2120 * @rmtoll CR CEIE LL_DMA2D_IsEnabledIT_CE
2121 * @param DMA2Dx DMA2D Instance
2122 * @retval State of bit (1 or 0).
2123 */
2124 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CE(const DMA2D_TypeDef *DMA2Dx)
2125 {
2126 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CEIE) == (DMA2D_CR_CEIE)) ? 1UL : 0UL);
2127 }
2128
2129 /**
2130 * @brief Check if the DMA2D CLUT Transfer Complete interrupt source is enabled or disabled.
2131 * @rmtoll CR CTCIE LL_DMA2D_IsEnabledIT_CTC
2132 * @param DMA2Dx DMA2D Instance
2133 * @retval State of bit (1 or 0).
2134 */
2135 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CTC(const DMA2D_TypeDef *DMA2Dx)
2136 {
2137 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CTCIE) == (DMA2D_CR_CTCIE)) ? 1UL : 0UL);
2138 }
2139
2140 /**
2141 * @brief Check if the DMA2D CLUT Access Error interrupt source is enabled or disabled.
2142 * @rmtoll CR CAEIE LL_DMA2D_IsEnabledIT_CAE
2143 * @param DMA2Dx DMA2D Instance
2144 * @retval State of bit (1 or 0).
2145 */
2146 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_CAE(const DMA2D_TypeDef *DMA2Dx)
2147 {
2148 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_CAEIE) == (DMA2D_CR_CAEIE)) ? 1UL : 0UL);
2149 }
2150
2151 /**
2152 * @brief Check if the DMA2D Transfer Watermark interrupt source is enabled or disabled.
2153 * @rmtoll CR TWIE LL_DMA2D_IsEnabledIT_TW
2154 * @param DMA2Dx DMA2D Instance
2155 * @retval State of bit (1 or 0).
2156 */
2157 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TW(const DMA2D_TypeDef *DMA2Dx)
2158 {
2159 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TWIE) == (DMA2D_CR_TWIE)) ? 1UL : 0UL);
2160 }
2161
2162 /**
2163 * @brief Check if the DMA2D Transfer Complete interrupt source is enabled or disabled.
2164 * @rmtoll CR TCIE LL_DMA2D_IsEnabledIT_TC
2165 * @param DMA2Dx DMA2D Instance
2166 * @retval State of bit (1 or 0).
2167 */
2168 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TC(const DMA2D_TypeDef *DMA2Dx)
2169 {
2170 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TCIE) == (DMA2D_CR_TCIE)) ? 1UL : 0UL);
2171 }
2172
2173 /**
2174 * @brief Check if the DMA2D Transfer Error interrupt source is enabled or disabled.
2175 * @rmtoll CR TEIE LL_DMA2D_IsEnabledIT_TE
2176 * @param DMA2Dx DMA2D Instance
2177 * @retval State of bit (1 or 0).
2178 */
2179 __STATIC_INLINE uint32_t LL_DMA2D_IsEnabledIT_TE(const DMA2D_TypeDef *DMA2Dx)
2180 {
2181 return ((READ_BIT(DMA2Dx->CR, DMA2D_CR_TEIE) == (DMA2D_CR_TEIE)) ? 1UL : 0UL);
2182 }
2183
2184
2185
2186 /**
2187 * @}
2188 */
2189
2190 #if defined(USE_FULL_LL_DRIVER)
2191 /** @defgroup DMA2D_LL_EF_Init_Functions Initialization and De-initialization Functions
2192 * @{
2193 */
2194
2195 ErrorStatus LL_DMA2D_DeInit(const DMA2D_TypeDef *DMA2Dx);
2196 ErrorStatus LL_DMA2D_Init(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2197 void LL_DMA2D_StructInit(LL_DMA2D_InitTypeDef *DMA2D_InitStruct);
2198 void LL_DMA2D_ConfigLayer(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg, uint32_t LayerIdx);
2199 void LL_DMA2D_LayerCfgStructInit(LL_DMA2D_LayerCfgTypeDef *DMA2D_LayerCfg);
2200 void LL_DMA2D_ConfigOutputColor(DMA2D_TypeDef *DMA2Dx, LL_DMA2D_ColorTypeDef *DMA2D_ColorStruct);
2201 uint32_t LL_DMA2D_GetOutputBlueColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2202 uint32_t LL_DMA2D_GetOutputGreenColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2203 uint32_t LL_DMA2D_GetOutputRedColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2204 uint32_t LL_DMA2D_GetOutputAlphaColor(const DMA2D_TypeDef *DMA2Dx, uint32_t ColorMode);
2205 void LL_DMA2D_ConfigSize(DMA2D_TypeDef *DMA2Dx, uint32_t NbrOfLines, uint32_t NbrOfPixelsPerLines);
2206
2207 /**
2208 * @}
2209 */
2210 #endif /* USE_FULL_LL_DRIVER */
2211
2212 /**
2213 * @}
2214 */
2215
2216 /**
2217 * @}
2218 */
2219
2220 #endif /* defined (DMA2D) */
2221
2222 /**
2223 * @}
2224 */
2225
2226 #ifdef __cplusplus
2227 }
2228 #endif
2229
2230 #endif /* STM32H7xx_LL_DMA2D_H */
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