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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_dmamux.h
blobf84f0e612149bdb5f98958b2c384d1d4806a8db5
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_dmamux.h
4 * @author MCD Application Team
5 * @brief Header file of DMAMUX LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_DMAMUX_H
22 #define STM32H7xx_LL_DMAMUX_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (DMAMUX1) || defined (DMAMUX2)
36
37 /** @defgroup DMAMUX_LL DMAMUX
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup DMAMUX_LL_Private_Constants DMAMUX Private Constants
45 * @{
46 */
47 /* Define used to get DMAMUX CCR register size */
48 #define DMAMUX_CCR_SIZE 0x00000004U
49
50 /* Define used to get DMAMUX RGCR register size */
51 #define DMAMUX_RGCR_SIZE 0x00000004U
52
53 /* Define used to get DMAMUX RequestGenerator offset */
54 #define DMAMUX_REQ_GEN_OFFSET (DMAMUX1_RequestGenerator0_BASE - DMAMUX1_BASE)
55 /* Define used to get DMAMUX Channel Status offset */
56 #define DMAMUX_CH_STATUS_OFFSET (DMAMUX1_ChannelStatus_BASE - DMAMUX1_BASE)
57 /* Define used to get DMAMUX RequestGenerator status offset */
58 #define DMAMUX_REQ_GEN_STATUS_OFFSET (DMAMUX1_RequestGenStatus_BASE - DMAMUX1_BASE)
59
60 /**
61 * @}
62 */
63
64 /* Private macros ------------------------------------------------------------*/
65 /* Exported types ------------------------------------------------------------*/
66 /* Exported constants --------------------------------------------------------*/
67 /** @defgroup DMAMUX_LL_Exported_Constants DMAMUX Exported Constants
68 * @{
69 */
70 /** @defgroup DMAMUX_LL_EC_CLEAR_FLAG Clear Flags Defines
71 * @brief Flags defines which can be used with LL_DMAMUX_WriteReg function
72 * @{
73 */
74 #define LL_DMAMUX_CFR_CSOF0 DMAMUX_CFR_CSOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
75 #define LL_DMAMUX_CFR_CSOF1 DMAMUX_CFR_CSOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
76 #define LL_DMAMUX_CFR_CSOF2 DMAMUX_CFR_CSOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
77 #define LL_DMAMUX_CFR_CSOF3 DMAMUX_CFR_CSOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
78 #define LL_DMAMUX_CFR_CSOF4 DMAMUX_CFR_CSOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
79 #define LL_DMAMUX_CFR_CSOF5 DMAMUX_CFR_CSOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
80 #define LL_DMAMUX_CFR_CSOF6 DMAMUX_CFR_CSOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
81 #define LL_DMAMUX_CFR_CSOF7 DMAMUX_CFR_CSOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
82 #define LL_DMAMUX_CFR_CSOF8 DMAMUX_CFR_CSOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
83 #define LL_DMAMUX_CFR_CSOF9 DMAMUX_CFR_CSOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
84 #define LL_DMAMUX_CFR_CSOF10 DMAMUX_CFR_CSOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
85 #define LL_DMAMUX_CFR_CSOF11 DMAMUX_CFR_CSOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
86 #define LL_DMAMUX_CFR_CSOF12 DMAMUX_CFR_CSOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
87 #define LL_DMAMUX_CFR_CSOF13 DMAMUX_CFR_CSOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
88 #define LL_DMAMUX_CFR_CSOF14 DMAMUX_CFR_CSOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
89 #define LL_DMAMUX_CFR_CSOF15 DMAMUX_CFR_CSOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
90 #define LL_DMAMUX_RGCFR_RGCOF0 DMAMUX_RGCFR_COF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
91 #define LL_DMAMUX_RGCFR_RGCOF1 DMAMUX_RGCFR_COF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
92 #define LL_DMAMUX_RGCFR_RGCOF2 DMAMUX_RGCFR_COF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
93 #define LL_DMAMUX_RGCFR_RGCOF3 DMAMUX_RGCFR_COF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
94 #define LL_DMAMUX_RGCFR_RGCOF4 DMAMUX_RGCFR_COF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
95 #define LL_DMAMUX_RGCFR_RGCOF5 DMAMUX_RGCFR_COF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
96 #define LL_DMAMUX_RGCFR_RGCOF6 DMAMUX_RGCFR_COF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
97 #define LL_DMAMUX_RGCFR_RGCOF7 DMAMUX_RGCFR_COF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
98 /**
99 * @}
100 */
101
102 /** @defgroup DMAMUX_LL_EC_GET_FLAG Get Flags Defines
103 * @brief Flags defines which can be used with LL_DMAMUX_ReadReg function
104 * @{
105 */
106 #define LL_DMAMUX_CSR_SOF0 DMAMUX_CSR_SOF0 /*!< Synchronization Event Overrun Flag Channel 0 */
107 #define LL_DMAMUX_CSR_SOF1 DMAMUX_CSR_SOF1 /*!< Synchronization Event Overrun Flag Channel 1 */
108 #define LL_DMAMUX_CSR_SOF2 DMAMUX_CSR_SOF2 /*!< Synchronization Event Overrun Flag Channel 2 */
109 #define LL_DMAMUX_CSR_SOF3 DMAMUX_CSR_SOF3 /*!< Synchronization Event Overrun Flag Channel 3 */
110 #define LL_DMAMUX_CSR_SOF4 DMAMUX_CSR_SOF4 /*!< Synchronization Event Overrun Flag Channel 4 */
111 #define LL_DMAMUX_CSR_SOF5 DMAMUX_CSR_SOF5 /*!< Synchronization Event Overrun Flag Channel 5 */
112 #define LL_DMAMUX_CSR_SOF6 DMAMUX_CSR_SOF6 /*!< Synchronization Event Overrun Flag Channel 6 */
113 #define LL_DMAMUX_CSR_SOF7 DMAMUX_CSR_SOF7 /*!< Synchronization Event Overrun Flag Channel 7 */
114 #define LL_DMAMUX_CSR_SOF8 DMAMUX_CSR_SOF8 /*!< Synchronization Event Overrun Flag Channel 8 */
115 #define LL_DMAMUX_CSR_SOF9 DMAMUX_CSR_SOF9 /*!< Synchronization Event Overrun Flag Channel 9 */
116 #define LL_DMAMUX_CSR_SOF10 DMAMUX_CSR_SOF10 /*!< Synchronization Event Overrun Flag Channel 10 */
117 #define LL_DMAMUX_CSR_SOF11 DMAMUX_CSR_SOF11 /*!< Synchronization Event Overrun Flag Channel 11 */
118 #define LL_DMAMUX_CSR_SOF12 DMAMUX_CSR_SOF12 /*!< Synchronization Event Overrun Flag Channel 12 */
119 #define LL_DMAMUX_CSR_SOF13 DMAMUX_CSR_SOF13 /*!< Synchronization Event Overrun Flag Channel 13 */
120 #define LL_DMAMUX_CSR_SOF14 DMAMUX_CSR_SOF14 /*!< Synchronization Event Overrun Flag Channel 14 */
121 #define LL_DMAMUX_CSR_SOF15 DMAMUX_CSR_SOF15 /*!< Synchronization Event Overrun Flag Channel 15 */
122 #define LL_DMAMUX_RGSR_RGOF0 DMAMUX_RGSR_OF0 /*!< Request Generator 0 Trigger Event Overrun Flag */
123 #define LL_DMAMUX_RGSR_RGOF1 DMAMUX_RGSR_OF1 /*!< Request Generator 1 Trigger Event Overrun Flag */
124 #define LL_DMAMUX_RGSR_RGOF2 DMAMUX_RGSR_OF2 /*!< Request Generator 2 Trigger Event Overrun Flag */
125 #define LL_DMAMUX_RGSR_RGOF3 DMAMUX_RGSR_OF3 /*!< Request Generator 3 Trigger Event Overrun Flag */
126 #define LL_DMAMUX_RGSR_RGOF4 DMAMUX_RGSR_OF4 /*!< Request Generator 4 Trigger Event Overrun Flag */
127 #define LL_DMAMUX_RGSR_RGOF5 DMAMUX_RGSR_OF5 /*!< Request Generator 5 Trigger Event Overrun Flag */
128 #define LL_DMAMUX_RGSR_RGOF6 DMAMUX_RGSR_OF6 /*!< Request Generator 6 Trigger Event Overrun Flag */
129 #define LL_DMAMUX_RGSR_RGOF7 DMAMUX_RGSR_OF7 /*!< Request Generator 7 Trigger Event Overrun Flag */
130 /**
131 * @}
132 */
133
134 /** @defgroup DMAMUX_LL_EC_IT IT Defines
135 * @brief IT defines which can be used with LL_DMA_ReadReg and LL_DMAMUX_WriteReg functions
136 * @{
137 */
138 #define LL_DMAMUX_CCR_SOIE DMAMUX_CxCR_SOIE /*!< Synchronization Event Overrun Interrupt */
139 #define LL_DMAMUX_RGCR_RGOIE DMAMUX_RGxCR_OIE /*!< Request Generation Trigger Event Overrun Interrupt */
140 /**
141 * @}
142 */
143
144 /** @defgroup DMAMUX_Request_selection DMAMUX Request selection
145 * @brief DMA Request selection
146 * @{
147 */
148 /* DMAMUX1 requests */
149 #define LL_DMAMUX1_REQ_MEM2MEM 0U /*!< memory to memory transfer */
150 #define LL_DMAMUX1_REQ_GENERATOR0 1U /*!< DMAMUX1 request generator 0 */
151 #define LL_DMAMUX1_REQ_GENERATOR1 2U /*!< DMAMUX1 request generator 1 */
152 #define LL_DMAMUX1_REQ_GENERATOR2 3U /*!< DMAMUX1 request generator 2 */
153 #define LL_DMAMUX1_REQ_GENERATOR3 4U /*!< DMAMUX1 request generator 3 */
154 #define LL_DMAMUX1_REQ_GENERATOR4 5U /*!< DMAMUX1 request generator 4 */
155 #define LL_DMAMUX1_REQ_GENERATOR5 6U /*!< DMAMUX1 request generator 5 */
156 #define LL_DMAMUX1_REQ_GENERATOR6 7U /*!< DMAMUX1 request generator 6 */
157 #define LL_DMAMUX1_REQ_GENERATOR7 8U /*!< DMAMUX1 request generator 7 */
158 #define LL_DMAMUX1_REQ_ADC1 9U /*!< DMAMUX1 ADC1 request */
159 #define LL_DMAMUX1_REQ_ADC2 10U /*!< DMAMUX1 ADC2 request */
160 #define LL_DMAMUX1_REQ_TIM1_CH1 11U /*!< DMAMUX1 TIM1 CH1 request */
161 #define LL_DMAMUX1_REQ_TIM1_CH2 12U /*!< DMAMUX1 TIM1 CH2 request */
162 #define LL_DMAMUX1_REQ_TIM1_CH3 13U /*!< DMAMUX1 TIM1 CH3 request */
163 #define LL_DMAMUX1_REQ_TIM1_CH4 14U /*!< DMAMUX1 TIM1 CH4 request */
164 #define LL_DMAMUX1_REQ_TIM1_UP 15U /*!< DMAMUX1 TIM1 UP request */
165 #define LL_DMAMUX1_REQ_TIM1_TRIG 16U /*!< DMAMUX1 TIM1 TRIG request */
166 #define LL_DMAMUX1_REQ_TIM1_COM 17U /*!< DMAMUX1 TIM1 COM request */
167 #define LL_DMAMUX1_REQ_TIM2_CH1 18U /*!< DMAMUX1 TIM2 CH1 request */
168 #define LL_DMAMUX1_REQ_TIM2_CH2 19U /*!< DMAMUX1 TIM2 CH2 request */
169 #define LL_DMAMUX1_REQ_TIM2_CH3 20U /*!< DMAMUX1 TIM2 CH3 request */
170 #define LL_DMAMUX1_REQ_TIM2_CH4 21U /*!< DMAMUX1 TIM2 CH4 request */
171 #define LL_DMAMUX1_REQ_TIM2_UP 22U /*!< DMAMUX1 TIM2 UP request */
172 #define LL_DMAMUX1_REQ_TIM3_CH1 23U /*!< DMAMUX1 TIM3 CH1 request */
173 #define LL_DMAMUX1_REQ_TIM3_CH2 24U /*!< DMAMUX1 TIM3 CH2 request */
174 #define LL_DMAMUX1_REQ_TIM3_CH3 25U /*!< DMAMUX1 TIM3 CH3 request */
175 #define LL_DMAMUX1_REQ_TIM3_CH4 26U /*!< DMAMUX1 TIM3 CH4 request */
176 #define LL_DMAMUX1_REQ_TIM3_UP 27U /*!< DMAMUX1 TIM3 UP request */
177 #define LL_DMAMUX1_REQ_TIM3_TRIG 28U /*!< DMAMUX1 TIM3 TRIG request */
178 #define LL_DMAMUX1_REQ_TIM4_CH1 29U /*!< DMAMUX1 TIM4 CH1 request */
179 #define LL_DMAMUX1_REQ_TIM4_CH2 30U /*!< DMAMUX1 TIM4 CH2 request */
180 #define LL_DMAMUX1_REQ_TIM4_CH3 31U /*!< DMAMUX1 TIM4 CH3 request */
181 #define LL_DMAMUX1_REQ_TIM4_UP 32U /*!< DMAMUX1 TIM4 UP request */
182 #define LL_DMAMUX1_REQ_I2C1_RX 33U /*!< DMAMUX1 I2C1 RX request */
183 #define LL_DMAMUX1_REQ_I2C1_TX 34U /*!< DMAMUX1 I2C1 TX request */
184 #define LL_DMAMUX1_REQ_I2C2_RX 35U /*!< DMAMUX1 I2C2 RX request */
185 #define LL_DMAMUX1_REQ_I2C2_TX 36U /*!< DMAMUX1 I2C2 TX request */
186 #define LL_DMAMUX1_REQ_SPI1_RX 37U /*!< DMAMUX1 SPI1 RX request */
187 #define LL_DMAMUX1_REQ_SPI1_TX 38U /*!< DMAMUX1 SPI1 TX request */
188 #define LL_DMAMUX1_REQ_SPI2_RX 39U /*!< DMAMUX1 SPI2 RX request */
189 #define LL_DMAMUX1_REQ_SPI2_TX 40U /*!< DMAMUX1 SPI2 TX request */
190 #define LL_DMAMUX1_REQ_USART1_RX 41U /*!< DMAMUX1 USART1 RX request */
191 #define LL_DMAMUX1_REQ_USART1_TX 42U /*!< DMAMUX1 USART1 TX request */
192 #define LL_DMAMUX1_REQ_USART2_RX 43U /*!< DMAMUX1 USART2 RX request */
193 #define LL_DMAMUX1_REQ_USART2_TX 44U /*!< DMAMUX1 USART2 TX request */
194 #define LL_DMAMUX1_REQ_USART3_RX 45U /*!< DMAMUX1 USART3 RX request */
195 #define LL_DMAMUX1_REQ_USART3_TX 46U /*!< DMAMUX1 USART3 TX request */
196 #define LL_DMAMUX1_REQ_TIM8_CH1 47U /*!< DMAMUX1 TIM8 CH1 request */
197 #define LL_DMAMUX1_REQ_TIM8_CH2 48U /*!< DMAMUX1 TIM8 CH2 request */
198 #define LL_DMAMUX1_REQ_TIM8_CH3 49U /*!< DMAMUX1 TIM8 CH3 request */
199 #define LL_DMAMUX1_REQ_TIM8_CH4 50U /*!< DMAMUX1 TIM8 CH4 request */
200 #define LL_DMAMUX1_REQ_TIM8_UP 51U /*!< DMAMUX1 TIM8 UP request */
201 #define LL_DMAMUX1_REQ_TIM8_TRIG 52U /*!< DMAMUX1 TIM8 TRIG request */
202 #define LL_DMAMUX1_REQ_TIM8_COM 53U /*!< DMAMUX1 TIM8 COM request */
203 #define LL_DMAMUX1_REQ_TIM5_CH1 55U /*!< DMAMUX1 TIM5 CH1 request */
204 #define LL_DMAMUX1_REQ_TIM5_CH2 56U /*!< DMAMUX1 TIM5 CH2 request */
205 #define LL_DMAMUX1_REQ_TIM5_CH3 57U /*!< DMAMUX1 TIM5 CH3 request */
206 #define LL_DMAMUX1_REQ_TIM5_CH4 58U /*!< DMAMUX1 TIM5 CH4 request */
207 #define LL_DMAMUX1_REQ_TIM5_UP 59U /*!< DMAMUX1 TIM5 UP request */
208 #define LL_DMAMUX1_REQ_TIM5_TRIG 60U /*!< DMAMUX1 TIM5 TRIG request */
209 #define LL_DMAMUX1_REQ_SPI3_RX 61U /*!< DMAMUX1 SPI3 RX request */
210 #define LL_DMAMUX1_REQ_SPI3_TX 62U /*!< DMAMUX1 SPI3 TX request */
211 #define LL_DMAMUX1_REQ_UART4_RX 63U /*!< DMAMUX1 UART4 RX request */
212 #define LL_DMAMUX1_REQ_UART4_TX 64U /*!< DMAMUX1 UART4 TX request */
213 #define LL_DMAMUX1_REQ_UART5_RX 65U /*!< DMAMUX1 UART5 RX request */
214 #define LL_DMAMUX1_REQ_UART5_TX 66U /*!< DMAMUX1 UART5 TX request */
215 #define LL_DMAMUX1_REQ_DAC1_CH1 67U /*!< DMAMUX1 DAC1 Channel 1 request */
216 #define LL_DMAMUX1_REQ_DAC1_CH2 68U /*!< DMAMUX1 DAC1 Channel 2 request */
217 #define LL_DMAMUX1_REQ_TIM6_UP 69U /*!< DMAMUX1 TIM6 UP request */
218 #define LL_DMAMUX1_REQ_TIM7_UP 70U /*!< DMAMUX1 TIM7 UP request */
219 #define LL_DMAMUX1_REQ_USART6_RX 71U /*!< DMAMUX1 USART6 RX request */
220 #define LL_DMAMUX1_REQ_USART6_TX 72U /*!< DMAMUX1 USART6 TX request */
221 #define LL_DMAMUX1_REQ_I2C3_RX 73U /*!< DMAMUX1 I2C3 RX request */
222 #define LL_DMAMUX1_REQ_I2C3_TX 74U /*!< DMAMUX1 I2C3 TX request */
223 #if defined (PSSI)
224 #define LL_DMAMUX1_REQ_DCMI_PSSI 75U /*!< DMAMUX1 DCMI/PSSI request */
225 #define LL_DMAMUX1_REQ_DCMI LL_DMAMUX1_REQ_DCMI_PSSI /* Legacy define */
226 #else
227 #define LL_DMAMUX1_REQ_DCMI 75U /*!< DMAMUX1 DCMI request */
228 #endif /* PSSI */
229 #define LL_DMAMUX1_REQ_CRYP_IN 76U /*!< DMAMUX1 CRYP IN request */
230 #define LL_DMAMUX1_REQ_CRYP_OUT 77U /*!< DMAMUX1 CRYP OUT request */
231 #define LL_DMAMUX1_REQ_HASH_IN 78U /*!< DMAMUX1 HASH IN request */
232 #define LL_DMAMUX1_REQ_UART7_RX 79U /*!< DMAMUX1 UART7 RX request */
233 #define LL_DMAMUX1_REQ_UART7_TX 80U /*!< DMAMUX1 UART7 TX request */
234 #define LL_DMAMUX1_REQ_UART8_RX 81U /*!< DMAMUX1 UART8 RX request */
235 #define LL_DMAMUX1_REQ_UART8_TX 82U /*!< DMAMUX1 UART8 TX request */
236 #define LL_DMAMUX1_REQ_SPI4_RX 83U /*!< DMAMUX1 SPI4 RX request */
237 #define LL_DMAMUX1_REQ_SPI4_TX 84U /*!< DMAMUX1 SPI4 TX request */
238 #define LL_DMAMUX1_REQ_SPI5_RX 85U /*!< DMAMUX1 SPI5 RX request */
239 #define LL_DMAMUX1_REQ_SPI5_TX 86U /*!< DMAMUX1 SPI5 TX request */
240 #define LL_DMAMUX1_REQ_SAI1_A 87U /*!< DMAMUX1 SAI1 A request */
241 #define LL_DMAMUX1_REQ_SAI1_B 88U /*!< DMAMUX1 SAI1 B request */
242 #define LL_DMAMUX1_REQ_SAI2_A 89U /*!< DMAMUX1 SAI2 A request */
243 #define LL_DMAMUX1_REQ_SAI2_B 90U /*!< DMAMUX1 SAI2 B request */
244 #define LL_DMAMUX1_REQ_SWPMI_RX 91U /*!< DMAMUX1 SWPMI RX request */
245 #define LL_DMAMUX1_REQ_SWPMI_TX 92U /*!< DMAMUX1 SWPMI TX request */
246 #define LL_DMAMUX1_REQ_SPDIF_RX_DT 93U /*!< DMAMUX1 SPDIF RXDT request */
247 #define LL_DMAMUX1_REQ_SPDIF_RX_CS 94U /*!< DMAMUX1 SPDIF RXCS request */
248 #if defined (HRTIM1)
249 #define LL_DMAMUX1_REQ_HRTIM_MASTER 95U /*!< DMAMUX1 HRTIM1 Master request 1 */
250 #define LL_DMAMUX1_REQ_HRTIM_TIMER_A 96U /*!< DMAMUX1 HRTIM1 TimerA request 2 */
251 #define LL_DMAMUX1_REQ_HRTIM_TIMER_B 97U /*!< DMAMUX1 HRTIM1 TimerB request 3 */
252 #define LL_DMAMUX1_REQ_HRTIM_TIMER_C 98U /*!< DMAMUX1 HRTIM1 TimerC request 4 */
253 #define LL_DMAMUX1_REQ_HRTIM_TIMER_D 99U /*!< DMAMUX1 HRTIM1 TimerD request 5 */
254 #define LL_DMAMUX1_REQ_HRTIM_TIMER_E 100U /*!< DMAMUX1 HRTIM1 TimerE request 6 */
255 #endif /* HRTIM1 */
256 #define LL_DMAMUX1_REQ_DFSDM1_FLT0 101U /*!< DMAMUX1 DFSDM1 Filter0 request */
257 #define LL_DMAMUX1_REQ_DFSDM1_FLT1 102U /*!< DMAMUX1 DFSDM1 Filter1 request */
258 #define LL_DMAMUX1_REQ_DFSDM1_FLT2 103U /*!< DMAMUX1 DFSDM1 Filter2 request */
259 #define LL_DMAMUX1_REQ_DFSDM1_FLT3 104U /*!< DMAMUX1 DFSDM1 Filter3 request */
260 #define LL_DMAMUX1_REQ_TIM15_CH1 105U /*!< DMAMUX1 TIM15 CH1 request */
261 #define LL_DMAMUX1_REQ_TIM15_UP 106U /*!< DMAMUX1 TIM15 UP request */
262 #define LL_DMAMUX1_REQ_TIM15_TRIG 107U /*!< DMAMUX1 TIM15 TRIG request */
263 #define LL_DMAMUX1_REQ_TIM15_COM 108U /*!< DMAMUX1 TIM15 COM request */
264 #define LL_DMAMUX1_REQ_TIM16_CH1 109U /*!< DMAMUX1 TIM16 CH1 request */
265 #define LL_DMAMUX1_REQ_TIM16_UP 110U /*!< DMAMUX1 TIM16 UP request */
266 #define LL_DMAMUX1_REQ_TIM17_CH1 111U /*!< DMAMUX1 TIM17 CH1 request */
267 #define LL_DMAMUX1_REQ_TIM17_UP 112U /*!< DMAMUX1 TIM17 UP request */
268 #if defined (SAI3)
269 #define LL_DMAMUX1_REQ_SAI3_A 113U /*!< DMAMUX1 SAI3 A request */
270 #define LL_DMAMUX1_REQ_SAI3_B 114U /*!< DMAMUX1 SAI3 B request */
271 #endif /* SAI3 */
272 #if defined (ADC3)
273 #define LL_DMAMUX1_REQ_ADC3 115U /*!< DMAMUX1 ADC3 request */
274 #endif /* ADC3 */
275 #if defined (UART9)
276 #define LL_DMAMUX1_REQ_UART9_RX 116U /*!< DMAMUX1 UART9 RX request */
277 #define LL_DMAMUX1_REQ_UART9_TX 117U /*!< DMAMUX1 UART9 TX request */
278 #endif /* UART9 */
279 #if defined (USART10)
280 #define LL_DMAMUX1_REQ_USART10_RX 118U /*!< DMAMUX1 USART10 RX request */
281 #define LL_DMAMUX1_REQ_USART10_TX 119U /*!< DMAMUX1 USART10 TX request */
282 #endif /* USART10 */
283
284 /* DMAMUX2 requests */
285 #define LL_DMAMUX2_REQ_MEM2MEM 0U /*!< memory to memory transfer */
286 #define LL_DMAMUX2_REQ_GENERATOR0 1U /*!< DMAMUX2 request generator 0 */
287 #define LL_DMAMUX2_REQ_GENERATOR1 2U /*!< DMAMUX2 request generator 1 */
288 #define LL_DMAMUX2_REQ_GENERATOR2 3U /*!< DMAMUX2 request generator 2 */
289 #define LL_DMAMUX2_REQ_GENERATOR3 4U /*!< DMAMUX2 request generator 3 */
290 #define LL_DMAMUX2_REQ_GENERATOR4 5U /*!< DMAMUX2 request generator 4 */
291 #define LL_DMAMUX2_REQ_GENERATOR5 6U /*!< DMAMUX2 request generator 5 */
292 #define LL_DMAMUX2_REQ_GENERATOR6 7U /*!< DMAMUX2 request generator 6 */
293 #define LL_DMAMUX2_REQ_GENERATOR7 8U /*!< DMAMUX2 request generator 7 */
294 #define LL_DMAMUX2_REQ_LPUART1_RX 9U /*!< DMAMUX2 LP_UART1_RX request */
295 #define LL_DMAMUX2_REQ_LPUART1_TX 10U /*!< DMAMUX2 LP_UART1_TX request */
296 #define LL_DMAMUX2_REQ_SPI6_RX 11U /*!< DMAMUX2 SPI6 RX request */
297 #define LL_DMAMUX2_REQ_SPI6_TX 12U /*!< DMAMUX2 SPI6 TX request */
298 #define LL_DMAMUX2_REQ_I2C4_RX 13U /*!< DMAMUX2 I2C4 RX request */
299 #define LL_DMAMUX2_REQ_I2C4_TX 14U /*!< DMAMUX2 I2C4 TX request */
300 #if defined (SAI4)
301 #define LL_DMAMUX2_REQ_SAI4_A 15U /*!< DMAMUX2 SAI4 A request */
302 #define LL_DMAMUX2_REQ_SAI4_B 16U /*!< DMAMUX2 SAI4 B request */
303 #endif /* SAI4 */
304 #if defined (ADC3)
305 #define LL_DMAMUX2_REQ_ADC3 17U /*!< DMAMUX2 ADC3 request */
306 #endif /* ADC3 */
307 #if defined (DAC2)
308 #define LL_DMAMUX2_REQ_DAC2_CH1 17U /*!< DMAMUX2 DAC2 CH1 request */
309 #endif /* DAC2 */
310 #if defined (DFSDM2_Channel0)
311 #define LL_DMAMUX2_REQ_DFSDM2_FLT0 18U /*!< DMAMUX2 DFSDM2 Filter0 request */
312 #endif /* DFSDM2_Channel0 */
313 /**
314 * @}
315 */
316
317
318 /** @defgroup DMAMUX_LL_EC_CHANNEL DMAMUX Channel
319 * @{
320 */
321 #define LL_DMAMUX_CHANNEL_0 0x00000000U /*!< DMAMUX1 Channel 0 connected to DMA1 Channel 0 , DMAMUX2 Channel 0 connected to BDMA Channel 0 */
322 #define LL_DMAMUX_CHANNEL_1 0x00000001U /*!< DMAMUX1 Channel 1 connected to DMA1 Channel 1 , DMAMUX2 Channel 1 connected to BDMA Channel 1 */
323 #define LL_DMAMUX_CHANNEL_2 0x00000002U /*!< DMAMUX1 Channel 2 connected to DMA1 Channel 2 , DMAMUX2 Channel 2 connected to BDMA Channel 2 */
324 #define LL_DMAMUX_CHANNEL_3 0x00000003U /*!< DMAMUX1 Channel 3 connected to DMA1 Channel 3 , DMAMUX2 Channel 3 connected to BDMA Channel 3 */
325 #define LL_DMAMUX_CHANNEL_4 0x00000004U /*!< DMAMUX1 Channel 4 connected to DMA1 Channel 4 , DMAMUX2 Channel 4 connected to BDMA Channel 4 */
326 #define LL_DMAMUX_CHANNEL_5 0x00000005U /*!< DMAMUX1 Channel 5 connected to DMA1 Channel 5 , DMAMUX2 Channel 5 connected to BDMA Channel 5 */
327 #define LL_DMAMUX_CHANNEL_6 0x00000006U /*!< DMAMUX1 Channel 6 connected to DMA1 Channel 6 , DMAMUX2 Channel 6 connected to BDMA Channel 6 */
328 #define LL_DMAMUX_CHANNEL_7 0x00000007U /*!< DMAMUX1 Channel 7 connected to DMA1 Channel 7 , DMAMUX2 Channel 7 connected to BDMA Channel 7 */
329 #define LL_DMAMUX_CHANNEL_8 0x00000008U /*!< DMAMUX1 Channel 8 connected to DMA2 Channel 0 */
330 #define LL_DMAMUX_CHANNEL_9 0x00000009U /*!< DMAMUX1 Channel 9 connected to DMA2 Channel 1 */
331 #define LL_DMAMUX_CHANNEL_10 0x0000000AU /*!< DMAMUX1 Channel 10 connected to DMA2 Channel 2 */
332 #define LL_DMAMUX_CHANNEL_11 0x0000000BU /*!< DMAMUX1 Channel 11 connected to DMA2 Channel 3 */
333 #define LL_DMAMUX_CHANNEL_12 0x0000000CU /*!< DMAMUX1 Channel 12 connected to DMA2 Channel 4 */
334 #define LL_DMAMUX_CHANNEL_13 0x0000000DU /*!< DMAMUX1 Channel 13 connected to DMA2 Channel 5 */
335 #define LL_DMAMUX_CHANNEL_14 0x0000000EU /*!< DMAMUX1 Channel 14 connected to DMA2 Channel 6 */
336 #define LL_DMAMUX_CHANNEL_15 0x0000000FU /*!< DMAMUX1 Channel 15 connected to DMA2 Channel 7 */
337 /**
338 * @}
339 */
340
341 /** @defgroup DMAMUX_LL_EC_SYNC_NO Synchronization Signal Polarity
342 * @{
343 */
344 #define LL_DMAMUX_SYNC_NO_EVENT 0x00000000U /*!< All requests are blocked */
345 #define LL_DMAMUX_SYNC_POL_RISING DMAMUX_CxCR_SPOL_0 /*!< Synchronization on event on rising edge */
346 #define LL_DMAMUX_SYNC_POL_FALLING DMAMUX_CxCR_SPOL_1 /*!< Synchronization on event on falling edge */
347 #define LL_DMAMUX_SYNC_POL_RISING_FALLING (DMAMUX_CxCR_SPOL_0 | DMAMUX_CxCR_SPOL_1) /*!< Synchronization on event on rising and falling edge */
348 /**
349 * @}
350 */
351
352 /** @defgroup DMAMUX_LL_EC_SYNC_EVT Synchronization Signal Event
353 * @{
354 */
355 #define LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT 0x00000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel0 Event */
356 #define LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT 0x01000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel1 Event */
357 #define LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT 0x02000000U /*!< DMAMUX1 synchronization Signal is DMAMUX1 Channel2 Event */
358 #define LL_DMAMUX1_SYNC_LPTIM1_OUT 0x03000000U /*!< DMAMUX1 synchronization Signal is LPTIM1 OUT */
359 #define LL_DMAMUX1_SYNC_LPTIM2_OUT 0x04000000U /*!< DMAMUX1 synchronization Signal is LPTIM2 OUT */
360 #define LL_DMAMUX1_SYNC_LPTIM3_OUT 0x05000000U /*!< DMAMUX1 synchronization Signal is LPTIM3 OUT */
361 #define LL_DMAMUX1_SYNC_EXTI0 0x06000000U /*!< DMAMUX1 synchronization Signal is EXTI0 IT */
362 #define LL_DMAMUX1_SYNC_TIM12_TRGO 0x07000000U /*!< DMAMUX1 synchronization Signal is TIM12 TRGO */
363
364 #define LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT 0x00000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel0 Event */
365 #define LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT 0x01000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel1 Event */
366 #define LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT 0x02000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel2 Event */
367 #define LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT 0x03000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel3 Event */
368 #define LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT 0x04000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel4 Event */
369 #define LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT 0x05000000U /*!< DMAMUX2 synchronization Signal is DMAMUX2 Channel5 Event */
370 #define LL_DMAMUX2_SYNC_LPUART1_RX_WKUP 0x06000000U /*!< DMAMUX2 synchronization Signal is LPUART1 RX Wakeup */
371 #define LL_DMAMUX2_SYNC_LPUART1_TX_WKUP 0x07000000U /*!< DMAMUX2 synchronization Signal is LPUART1 TX Wakeup */
372 #define LL_DMAMUX2_SYNC_LPTIM2_OUT 0x08000000U /*!< DMAMUX2 synchronization Signal is LPTIM2 output */
373 #define LL_DMAMUX2_SYNC_LPTIM3_OUT 0x09000000U /*!< DMAMUX2 synchronization Signal is LPTIM3 output */
374 #define LL_DMAMUX2_SYNC_I2C4_WKUP 0x0A000000U /*!< DMAMUX2 synchronization Signal is I2C4 Wakeup */
375 #define LL_DMAMUX2_SYNC_SPI6_WKUP 0x0B000000U /*!< DMAMUX2 synchronization Signal is SPI6 Wakeup */
376 #define LL_DMAMUX2_SYNC_COMP1_OUT 0x0C000000U /*!< DMAMUX2 synchronization Signal is Comparator 1 output */
377 #define LL_DMAMUX2_SYNC_RTC_WKUP 0x0D000000U /*!< DMAMUX2 synchronization Signal is RTC Wakeup */
378 #define LL_DMAMUX2_SYNC_EXTI0 0x0E000000U /*!< DMAMUX2 synchronization Signal is EXTI0 IT */
379 #define LL_DMAMUX2_SYNC_EXTI2 0x0F000000U /*!< DMAMUX2 synchronization Signal is EXTI2 IT */
380
381 /**
382 * @}
383 */
384
385 /** @defgroup DMAMUX_LL_EC_REQUEST_GENERATOR Request Generator Channel
386 * @{
387 */
388 #define LL_DMAMUX_REQ_GEN_0 0x00000000U
389 #define LL_DMAMUX_REQ_GEN_1 0x00000001U
390 #define LL_DMAMUX_REQ_GEN_2 0x00000002U
391 #define LL_DMAMUX_REQ_GEN_3 0x00000003U
392 #define LL_DMAMUX_REQ_GEN_4 0x00000004U
393 #define LL_DMAMUX_REQ_GEN_5 0x00000005U
394 #define LL_DMAMUX_REQ_GEN_6 0x00000006U
395 #define LL_DMAMUX_REQ_GEN_7 0x00000007U
396 /**
397 * @}
398 */
399
400 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN_POLARITY External Request Signal Generation Polarity
401 * @{
402 */
403 #define LL_DMAMUX_REQ_GEN_NO_EVENT 0x00000000U /*!< No external DMA request generation */
404 #define LL_DMAMUX_REQ_GEN_POL_RISING DMAMUX_RGxCR_GPOL_0 /*!< External DMA request generation on event on rising edge */
405 #define LL_DMAMUX_REQ_GEN_POL_FALLING DMAMUX_RGxCR_GPOL_1 /*!< External DMA request generation on event on falling edge */
406 #define LL_DMAMUX_REQ_GEN_POL_RISING_FALLING (DMAMUX_RGxCR_GPOL_0 | DMAMUX_RGxCR_GPOL_1) /*!< External DMA request generation on rising and falling edge */
407 /**
408 * @}
409 */
410
411 /** @defgroup DMAMUX_LL_EC_REQUEST_GEN External Request Signal Generation
412 * @{
413 */
414 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT 0U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel0 Event */
415 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT 1U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel1 Event */
416 #define LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT 2U /*!< DMAMUX1 Request generator Signal is DMAMUX1 Channel2 Event */
417 #define LL_DMAMUX1_REQ_GEN_LPTIM1_OUT 3U /*!< DMAMUX1 Request generator Signal is LPTIM1 OUT */
418 #define LL_DMAMUX1_REQ_GEN_LPTIM2_OUT 4U /*!< DMAMUX1 Request generator Signal is LPTIM2 OUT */
419 #define LL_DMAMUX1_REQ_GEN_LPTIM3_OUT 5U /*!< DMAMUX1 Request generator Signal is LPTIM3 OUT */
420 #define LL_DMAMUX1_REQ_GEN_EXTI0 6U /*!< DMAMUX1 Request generator Signal is EXTI0 IT */
421 #define LL_DMAMUX1_REQ_GEN_TIM12_TRGO 7U /*!< DMAMUX1 Request generator Signal is TIM12 TRGO */
422
423 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT 0U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel0 Event */
424 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT 1U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel1 Event */
425 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT 2U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel2 Event */
426 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT 3U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel3 Event */
427 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT 4U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel4 Event */
428 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT 5U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel5 Event */
429 #define LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT 6U /*!< DMAMUX2 Request generator Signal is DMAMUX2 Channel6 Event */
430 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP 7U /*!< DMAMUX2 Request generator Signal is LPUART1 RX Wakeup */
431 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP 8U /*!< DMAMUX2 Request generator Signal is LPUART1 TX Wakeup */
432 #define LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP 9U /*!< DMAMUX2 Request generator Signal is LPTIM2 Wakeup */
433 #define LL_DMAMUX2_REQ_GEN_LPTIM2_OUT 10U /*!< DMAMUX2 Request generator Signal is LPTIM2 OUT */
434 #define LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP 11U /*!< DMAMUX2 Request generator Signal is LPTIM3 Wakeup */
435 #define LL_DMAMUX2_REQ_GEN_LPTIM3_OUT 12U /*!< DMAMUX2 Request generator Signal is LPTIM3 OUT */
436 #if defined (LPTIM4)
437 #define LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP 13U /*!< DMAMUX2 Request generator Signal is LPTIM4 Wakeup */
438 #endif /* LPTIM4 */
439 #if defined (LPTIM5)
440 #define LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP 14U /*!< DMAMUX2 Request generator Signal is LPTIM5 Wakeup */
441 #endif /* LPTIM5 */
442 #define LL_DMAMUX2_REQ_GEN_I2C4_WKUP 15U /*!< DMAMUX2 Request generator Signal is I2C4 Wakeup */
443 #define LL_DMAMUX2_REQ_GEN_SPI6_WKUP 16U /*!< DMAMUX2 Request generator Signal is SPI6 Wakeup */
444 #define LL_DMAMUX2_REQ_GEN_COMP1_OUT 17U /*!< DMAMUX2 Request generator Signal is Comparator 1 output */
445 #define LL_DMAMUX2_REQ_GEN_COMP2_OUT 18U /*!< DMAMUX2 Request generator Signal is Comparator 2 output */
446 #define LL_DMAMUX2_REQ_GEN_RTC_WKUP 19U /*!< DMAMUX2 Request generator Signal is RTC Wakeup */
447 #define LL_DMAMUX2_REQ_GEN_EXTI0 20U /*!< DMAMUX2 Request generator Signal is EXTI0 */
448 #define LL_DMAMUX2_REQ_GEN_EXTI2 21U /*!< DMAMUX2 Request generator Signal is EXTI2 */
449 #define LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT 22U /*!< DMAMUX2 Request generator Signal is I2C4 IT Event */
450 #define LL_DMAMUX2_REQ_GEN_SPI6_IT 23U /*!< DMAMUX2 Request generator Signal is SPI6 IT */
451 #define LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT 24U /*!< DMAMUX2 Request generator Signal is LPUART1 Tx IT */
452 #define LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT 25U /*!< DMAMUX2 Request generator Signal is LPUART1 Rx IT */
453 #if defined (ADC3)
454 #define LL_DMAMUX2_REQ_GEN_ADC3_IT 26U /*!< DMAMUX2 Request generator Signal is ADC3 IT */
455 #define LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT 27U /*!< DMAMUX2 Request generator Signal is ADC3 Analog Watchdog 1 output */
456 #endif /* ADC3 */
457 #define LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT 28U /*!< DMAMUX2 Request generator Signal is BDMA Channel 0 IT */
458 #define LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT 29U /*!< DMAMUX2 Request generator Signal is BDMA Channel 1 IT */
459 /**
460 * @}
461 */
462
463 /**
464 * @}
465 */
466
467 /* Exported macro ------------------------------------------------------------*/
468 /** @defgroup DMAMUX_LL_Exported_Macros DMAMUX Exported Macros
469 * @{
470 */
471
472 /** @defgroup DMAMUX_LL_EM_WRITE_READ Common Write and read registers macros
473 * @{
474 */
475 /**
476 * @brief Write a value in DMAMUX register
477 * @param __INSTANCE__ DMAMUX Instance
478 * @param __REG__ Register to be written
479 * @param __VALUE__ Value to be written in the register
480 * @retval None
481 */
482 #define LL_DMAMUX_WriteReg(__INSTANCE__, __REG__, __VALUE__) WRITE_REG(__INSTANCE__->__REG__, (__VALUE__))
483
484 /**
485 * @brief Read a value in DMAMUX register
486 * @param __INSTANCE__ DMAMUX Instance
487 * @param __REG__ Register to be read
488 * @retval Register value
489 */
490 #define LL_DMAMUX_ReadReg(__INSTANCE__, __REG__) READ_REG(__INSTANCE__->__REG__)
491 /**
492 * @}
493 */
494
495 /**
496 * @}
497 */
498
499 /* Exported functions --------------------------------------------------------*/
500 /** @defgroup DMAMUX_LL_Exported_Functions DMAMUX Exported Functions
501 * @{
502 */
503
504 /** @defgroup DMAMUX_LL_EF_Configuration Configuration
505 * @{
506 */
507 /**
508 * @brief Set DMAMUX request ID for DMAMUX Channel x.
509 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
510 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
511 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
512 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_SetRequestID
513 * @param DMAMUXx DMAMUXx Instance
514 * @param Channel This parameter can be one of the following values:
515 * @arg @ref LL_DMAMUX_CHANNEL_0
516 * @arg @ref LL_DMAMUX_CHANNEL_1
517 * @arg @ref LL_DMAMUX_CHANNEL_2
518 * @arg @ref LL_DMAMUX_CHANNEL_3
519 * @arg @ref LL_DMAMUX_CHANNEL_4
520 * @arg @ref LL_DMAMUX_CHANNEL_5
521 * @arg @ref LL_DMAMUX_CHANNEL_6
522 * @arg @ref LL_DMAMUX_CHANNEL_7
523 * @arg @ref LL_DMAMUX_CHANNEL_8
524 * @arg @ref LL_DMAMUX_CHANNEL_9
525 * @arg @ref LL_DMAMUX_CHANNEL_10
526 * @arg @ref LL_DMAMUX_CHANNEL_11
527 * @arg @ref LL_DMAMUX_CHANNEL_12
528 * @arg @ref LL_DMAMUX_CHANNEL_13
529 * @arg @ref LL_DMAMUX_CHANNEL_14
530 * @arg @ref LL_DMAMUX_CHANNEL_15
531 * @param Request This parameter can be one of the following values:
532 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
533 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
534 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
535 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
536 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
537 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
538 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
539 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
540 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
541 * @arg @ref LL_DMAMUX1_REQ_ADC1
542 * @arg @ref LL_DMAMUX1_REQ_ADC2
543 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
544 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
545 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
546 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
547 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
548 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
549 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
550 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
551 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
552 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
553 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
554 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
555 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
556 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
557 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
558 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
559 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
560 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
561 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
562 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
563 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
564 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
565 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
566 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
567 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
568 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
569 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
570 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
571 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
572 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
573 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
574 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
575 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
576 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
577 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
578 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
579 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
580 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
581 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
582 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
583 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
584 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
585 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
586 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
587 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
588 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
589 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
590 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
591 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
592 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
593 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
594 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
595 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
596 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
597 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
598 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
599 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
600 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
601 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
602 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
603 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
604 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
605 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
606 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
607 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
608 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
609 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
610 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
611 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
612 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
613 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
614 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
615 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
616 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
617 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
618 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
619 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
620 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
621 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
622 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
623 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
624 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
625 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
626 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
627 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
628 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
629 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
630 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
631 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
632 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
633 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
634 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
635 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
636 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
637 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
638 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
639 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
640 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
641 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
642 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
643 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
644 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
645 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
646 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
647 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
648 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
649 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
650 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
651 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
652 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
653 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
654 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
655 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
656 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
657 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
658 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
659 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
660 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
661 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
662 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
663 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
664 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
665 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
666 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
667 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
668 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
669 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
670 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
671 * @note (*) Availability depends on devices.
672 * @retval None
673 */
674 __STATIC_INLINE void LL_DMAMUX_SetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Request)
675 {
676 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
677
678 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID, Request);
679 }
680
681 /**
682 * @brief Get DMAMUX request ID for DMAMUX Channel x.
683 * @note DMAMUX1 channel 0 to 7 are mapped to DMA1 channel 0 to 7.
684 * DMAMUX1 channel 8 to 15 are mapped to DMA2 channel 0 to 7.
685 * DMAMUX2 channel 0 to 7 are mapped to BDMA channel 0 to 7.
686 * @rmtoll CxCR DMAREQ_ID LL_DMAMUX_GetRequestID
687 * @param DMAMUXx DMAMUXx Instance
688 * @param Channel This parameter can be one of the following values:
689 * @arg @ref LL_DMAMUX_CHANNEL_0
690 * @arg @ref LL_DMAMUX_CHANNEL_1
691 * @arg @ref LL_DMAMUX_CHANNEL_2
692 * @arg @ref LL_DMAMUX_CHANNEL_3
693 * @arg @ref LL_DMAMUX_CHANNEL_4
694 * @arg @ref LL_DMAMUX_CHANNEL_5
695 * @arg @ref LL_DMAMUX_CHANNEL_6
696 * @arg @ref LL_DMAMUX_CHANNEL_7
697 * @arg @ref LL_DMAMUX_CHANNEL_8
698 * @arg @ref LL_DMAMUX_CHANNEL_9
699 * @arg @ref LL_DMAMUX_CHANNEL_10
700 * @arg @ref LL_DMAMUX_CHANNEL_11
701 * @arg @ref LL_DMAMUX_CHANNEL_12
702 * @arg @ref LL_DMAMUX_CHANNEL_13
703 * @arg @ref LL_DMAMUX_CHANNEL_14
704 * @arg @ref LL_DMAMUX_CHANNEL_15
705 * @retval Returned value can be one of the following values:
706 * @arg @ref LL_DMAMUX1_REQ_MEM2MEM
707 * @arg @ref LL_DMAMUX1_REQ_GENERATOR0
708 * @arg @ref LL_DMAMUX1_REQ_GENERATOR1
709 * @arg @ref LL_DMAMUX1_REQ_GENERATOR2
710 * @arg @ref LL_DMAMUX1_REQ_GENERATOR3
711 * @arg @ref LL_DMAMUX1_REQ_GENERATOR4
712 * @arg @ref LL_DMAMUX1_REQ_GENERATOR5
713 * @arg @ref LL_DMAMUX1_REQ_GENERATOR6
714 * @arg @ref LL_DMAMUX1_REQ_GENERATOR7
715 * @arg @ref LL_DMAMUX1_REQ_ADC1
716 * @arg @ref LL_DMAMUX1_REQ_ADC2
717 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH1
718 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH2
719 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH3
720 * @arg @ref LL_DMAMUX1_REQ_TIM1_CH4
721 * @arg @ref LL_DMAMUX1_REQ_TIM1_UP
722 * @arg @ref LL_DMAMUX1_REQ_TIM1_TRIG
723 * @arg @ref LL_DMAMUX1_REQ_TIM1_COM
724 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH1
725 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH2
726 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH3
727 * @arg @ref LL_DMAMUX1_REQ_TIM2_CH4
728 * @arg @ref LL_DMAMUX1_REQ_TIM2_UP
729 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH1
730 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH2
731 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH3
732 * @arg @ref LL_DMAMUX1_REQ_TIM3_CH4
733 * @arg @ref LL_DMAMUX1_REQ_TIM3_UP
734 * @arg @ref LL_DMAMUX1_REQ_TIM3_TRIG
735 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH1
736 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH2
737 * @arg @ref LL_DMAMUX1_REQ_TIM4_CH3
738 * @arg @ref LL_DMAMUX1_REQ_TIM4_UP
739 * @arg @ref LL_DMAMUX1_REQ_I2C1_RX
740 * @arg @ref LL_DMAMUX1_REQ_I2C1_TX
741 * @arg @ref LL_DMAMUX1_REQ_I2C2_RX
742 * @arg @ref LL_DMAMUX1_REQ_I2C2_TX
743 * @arg @ref LL_DMAMUX1_REQ_SPI1_RX
744 * @arg @ref LL_DMAMUX1_REQ_SPI1_TX
745 * @arg @ref LL_DMAMUX1_REQ_SPI2_RX
746 * @arg @ref LL_DMAMUX1_REQ_SPI2_TX
747 * @arg @ref LL_DMAMUX1_REQ_USART1_RX
748 * @arg @ref LL_DMAMUX1_REQ_USART1_TX
749 * @arg @ref LL_DMAMUX1_REQ_USART2_RX
750 * @arg @ref LL_DMAMUX1_REQ_USART2_TX
751 * @arg @ref LL_DMAMUX1_REQ_USART3_RX
752 * @arg @ref LL_DMAMUX1_REQ_USART3_TX
753 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH1
754 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH2
755 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH3
756 * @arg @ref LL_DMAMUX1_REQ_TIM8_CH4
757 * @arg @ref LL_DMAMUX1_REQ_TIM8_UP
758 * @arg @ref LL_DMAMUX1_REQ_TIM8_TRIG
759 * @arg @ref LL_DMAMUX1_REQ_TIM8_COM
760 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH1
761 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH2
762 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH3
763 * @arg @ref LL_DMAMUX1_REQ_TIM5_CH4
764 * @arg @ref LL_DMAMUX1_REQ_TIM5_UP
765 * @arg @ref LL_DMAMUX1_REQ_TIM5_TRIG
766 * @arg @ref LL_DMAMUX1_REQ_SPI3_RX
767 * @arg @ref LL_DMAMUX1_REQ_SPI3_TX
768 * @arg @ref LL_DMAMUX1_REQ_UART4_RX
769 * @arg @ref LL_DMAMUX1_REQ_UART4_TX
770 * @arg @ref LL_DMAMUX1_REQ_UART5_RX
771 * @arg @ref LL_DMAMUX1_REQ_UART5_TX
772 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH1
773 * @arg @ref LL_DMAMUX1_REQ_DAC1_CH2
774 * @arg @ref LL_DMAMUX1_REQ_TIM6_UP
775 * @arg @ref LL_DMAMUX1_REQ_TIM7_UP
776 * @arg @ref LL_DMAMUX1_REQ_USART6_RX
777 * @arg @ref LL_DMAMUX1_REQ_USART6_TX
778 * @arg @ref LL_DMAMUX1_REQ_I2C3_RX
779 * @arg @ref LL_DMAMUX1_REQ_I2C3_TX
780 * @arg @ref LL_DMAMUX1_REQ_DCMI_PSSI
781 * @arg @ref LL_DMAMUX1_REQ_CRYP_IN
782 * @arg @ref LL_DMAMUX1_REQ_CRYP_OUT
783 * @arg @ref LL_DMAMUX1_REQ_HASH_IN
784 * @arg @ref LL_DMAMUX1_REQ_UART7_RX
785 * @arg @ref LL_DMAMUX1_REQ_UART7_TX
786 * @arg @ref LL_DMAMUX1_REQ_UART8_RX
787 * @arg @ref LL_DMAMUX1_REQ_UART8_TX
788 * @arg @ref LL_DMAMUX1_REQ_SPI4_RX
789 * @arg @ref LL_DMAMUX1_REQ_SPI4_TX
790 * @arg @ref LL_DMAMUX1_REQ_SPI5_RX
791 * @arg @ref LL_DMAMUX1_REQ_SPI5_TX
792 * @arg @ref LL_DMAMUX1_REQ_SAI1_A
793 * @arg @ref LL_DMAMUX1_REQ_SAI1_B
794 * @arg @ref LL_DMAMUX1_REQ_SAI2_A
795 * @arg @ref LL_DMAMUX1_REQ_SAI2_B
796 * @arg @ref LL_DMAMUX1_REQ_SWPMI_RX
797 * @arg @ref LL_DMAMUX1_REQ_SWPMI_TX
798 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_DT
799 * @arg @ref LL_DMAMUX1_REQ_SPDIF_RX_CS
800 * @arg @ref LL_DMAMUX1_REQ_HRTIM_MASTER (*)
801 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_A (*)
802 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_B (*)
803 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_C (*)
804 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_D (*)
805 * @arg @ref LL_DMAMUX1_REQ_HRTIM_TIMER_E (*)
806 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT0
807 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT1
808 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT2
809 * @arg @ref LL_DMAMUX1_REQ_DFSDM1_FLT3
810 * @arg @ref LL_DMAMUX1_REQ_TIM15_CH1
811 * @arg @ref LL_DMAMUX1_REQ_TIM15_UP
812 * @arg @ref LL_DMAMUX1_REQ_TIM15_TRIG
813 * @arg @ref LL_DMAMUX1_REQ_TIM15_COM
814 * @arg @ref LL_DMAMUX1_REQ_TIM16_CH1
815 * @arg @ref LL_DMAMUX1_REQ_TIM16_UP
816 * @arg @ref LL_DMAMUX1_REQ_TIM17_CH1
817 * @arg @ref LL_DMAMUX1_REQ_TIM17_UP
818 * @arg @ref LL_DMAMUX1_REQ_SAI3_A (*)
819 * @arg @ref LL_DMAMUX1_REQ_SAI3_B (*)
820 * @arg @ref LL_DMAMUX1_REQ_ADC3 (*)
821 * @arg @ref LL_DMAMUX1_REQ_UART9_RX (*)
822 * @arg @ref LL_DMAMUX1_REQ_UART9_TX (*)
823 * @arg @ref LL_DMAMUX1_REQ_USART10_RX (*)
824 * @arg @ref LL_DMAMUX1_REQ_USART10_TX (*)
825 * @arg @ref LL_DMAMUX2_REQ_MEM2MEM
826 * @arg @ref LL_DMAMUX2_REQ_GENERATOR0
827 * @arg @ref LL_DMAMUX2_REQ_GENERATOR1
828 * @arg @ref LL_DMAMUX2_REQ_GENERATOR2
829 * @arg @ref LL_DMAMUX2_REQ_GENERATOR3
830 * @arg @ref LL_DMAMUX2_REQ_GENERATOR4
831 * @arg @ref LL_DMAMUX2_REQ_GENERATOR5
832 * @arg @ref LL_DMAMUX2_REQ_GENERATOR6
833 * @arg @ref LL_DMAMUX2_REQ_GENERATOR7
834 * @arg @ref LL_DMAMUX2_REQ_LPUART1_RX
835 * @arg @ref LL_DMAMUX2_REQ_LPUART1_TX
836 * @arg @ref LL_DMAMUX2_REQ_SPI6_RX
837 * @arg @ref LL_DMAMUX2_REQ_SPI6_TX
838 * @arg @ref LL_DMAMUX2_REQ_I2C4_RX
839 * @arg @ref LL_DMAMUX2_REQ_I2C4_TX
840 * @arg @ref LL_DMAMUX2_REQ_SAI4_A (*)
841 * @arg @ref LL_DMAMUX2_REQ_SAI4_B (*)
842 * @arg @ref LL_DMAMUX2_REQ_ADC3 (*)
843 * @arg @ref LL_DMAMUX2_REQ_DAC2_CH1 (*)
844 * @arg @ref LL_DMAMUX2_REQ_DFSDM2_FLT0 (*)
845 * @note (*) Availability depends on devices.
846 * @retval None
847 */
848 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
849 {
850 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
851
852 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_DMAREQ_ID));
853 }
854
855 /**
856 * @brief Set the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
857 * @rmtoll CxCR NBREQ LL_DMAMUX_SetSyncRequestNb
858 * @param DMAMUXx DMAMUXx Instance
859 * @param Channel This parameter can be one of the following values:
860 * @arg @ref LL_DMAMUX_CHANNEL_0
861 * @arg @ref LL_DMAMUX_CHANNEL_1
862 * @arg @ref LL_DMAMUX_CHANNEL_2
863 * @arg @ref LL_DMAMUX_CHANNEL_3
864 * @arg @ref LL_DMAMUX_CHANNEL_4
865 * @arg @ref LL_DMAMUX_CHANNEL_5
866 * @arg @ref LL_DMAMUX_CHANNEL_6
867 * @arg @ref LL_DMAMUX_CHANNEL_7
868 * @arg @ref LL_DMAMUX_CHANNEL_8
869 * @arg @ref LL_DMAMUX_CHANNEL_9
870 * @arg @ref LL_DMAMUX_CHANNEL_10
871 * @arg @ref LL_DMAMUX_CHANNEL_11
872 * @arg @ref LL_DMAMUX_CHANNEL_12
873 * @arg @ref LL_DMAMUX_CHANNEL_13
874 * @arg @ref LL_DMAMUX_CHANNEL_14
875 * @arg @ref LL_DMAMUX_CHANNEL_15
876 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
877 * @retval None
878 */
879 __STATIC_INLINE void LL_DMAMUX_SetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t RequestNb)
880 {
881 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
882
883 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ, (RequestNb - 1U) << DMAMUX_CxCR_NBREQ_Pos);
884 }
885
886 /**
887 * @brief Get the number of DMA request that will be autorized after a synchronization event and/or the number of DMA request needed to generate an event.
888 * @rmtoll CxCR NBREQ LL_DMAMUX_GetSyncRequestNb
889 * @param DMAMUXx DMAMUXx Instance
890 * @param Channel This parameter can be one of the following values:
891 * @arg @ref LL_DMAMUX_CHANNEL_0
892 * @arg @ref LL_DMAMUX_CHANNEL_1
893 * @arg @ref LL_DMAMUX_CHANNEL_2
894 * @arg @ref LL_DMAMUX_CHANNEL_3
895 * @arg @ref LL_DMAMUX_CHANNEL_4
896 * @arg @ref LL_DMAMUX_CHANNEL_5
897 * @arg @ref LL_DMAMUX_CHANNEL_6
898 * @arg @ref LL_DMAMUX_CHANNEL_7
899 * @arg @ref LL_DMAMUX_CHANNEL_8
900 * @arg @ref LL_DMAMUX_CHANNEL_9
901 * @arg @ref LL_DMAMUX_CHANNEL_10
902 * @arg @ref LL_DMAMUX_CHANNEL_11
903 * @arg @ref LL_DMAMUX_CHANNEL_12
904 * @arg @ref LL_DMAMUX_CHANNEL_13
905 * @arg @ref LL_DMAMUX_CHANNEL_14
906 * @arg @ref LL_DMAMUX_CHANNEL_15
907 * @retval Between Min_Data = 1 and Max_Data = 32
908 */
909 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
910 {
911 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
912
913 return (uint32_t)((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_NBREQ) >> DMAMUX_CxCR_NBREQ_Pos) + 1U);
914 }
915
916 /**
917 * @brief Set the polarity of the signal on which the DMA request is synchronized.
918 * @rmtoll CxCR SPOL LL_DMAMUX_SetSyncPolarity
919 * @param DMAMUXx DMAMUXx Instance
920 * @param Channel This parameter can be one of the following values:
921 * @arg @ref LL_DMAMUX_CHANNEL_0
922 * @arg @ref LL_DMAMUX_CHANNEL_1
923 * @arg @ref LL_DMAMUX_CHANNEL_2
924 * @arg @ref LL_DMAMUX_CHANNEL_3
925 * @arg @ref LL_DMAMUX_CHANNEL_4
926 * @arg @ref LL_DMAMUX_CHANNEL_5
927 * @arg @ref LL_DMAMUX_CHANNEL_6
928 * @arg @ref LL_DMAMUX_CHANNEL_7
929 * @arg @ref LL_DMAMUX_CHANNEL_8
930 * @arg @ref LL_DMAMUX_CHANNEL_9
931 * @arg @ref LL_DMAMUX_CHANNEL_10
932 * @arg @ref LL_DMAMUX_CHANNEL_11
933 * @arg @ref LL_DMAMUX_CHANNEL_12
934 * @arg @ref LL_DMAMUX_CHANNEL_13
935 * @arg @ref LL_DMAMUX_CHANNEL_14
936 * @arg @ref LL_DMAMUX_CHANNEL_15
937 * @param Polarity This parameter can be one of the following values:
938 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
939 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
940 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
941 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
942 * @retval None
943 */
944 __STATIC_INLINE void LL_DMAMUX_SetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t Polarity)
945 {
946 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
947
948 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL, Polarity);
949 }
950
951 /**
952 * @brief Get the polarity of the signal on which the DMA request is synchronized.
953 * @rmtoll CxCR SPOL LL_DMAMUX_GetSyncPolarity
954 * @param DMAMUXx DMAMUXx Instance
955 * @param Channel This parameter can be one of the following values:
956 * @arg @ref LL_DMAMUX_CHANNEL_0
957 * @arg @ref LL_DMAMUX_CHANNEL_1
958 * @arg @ref LL_DMAMUX_CHANNEL_2
959 * @arg @ref LL_DMAMUX_CHANNEL_3
960 * @arg @ref LL_DMAMUX_CHANNEL_4
961 * @arg @ref LL_DMAMUX_CHANNEL_5
962 * @arg @ref LL_DMAMUX_CHANNEL_6
963 * @arg @ref LL_DMAMUX_CHANNEL_7
964 * @arg @ref LL_DMAMUX_CHANNEL_8
965 * @arg @ref LL_DMAMUX_CHANNEL_9
966 * @arg @ref LL_DMAMUX_CHANNEL_10
967 * @arg @ref LL_DMAMUX_CHANNEL_11
968 * @arg @ref LL_DMAMUX_CHANNEL_12
969 * @arg @ref LL_DMAMUX_CHANNEL_13
970 * @arg @ref LL_DMAMUX_CHANNEL_14
971 * @arg @ref LL_DMAMUX_CHANNEL_15
972 * @retval Returned value can be one of the following values:
973 * @arg @ref LL_DMAMUX_SYNC_NO_EVENT
974 * @arg @ref LL_DMAMUX_SYNC_POL_RISING
975 * @arg @ref LL_DMAMUX_SYNC_POL_FALLING
976 * @arg @ref LL_DMAMUX_SYNC_POL_RISING_FALLING
977 */
978 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
979 {
980 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
981
982 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SPOL));
983 }
984
985 /**
986 * @brief Enable the Event Generation on DMAMUX channel x.
987 * @rmtoll CxCR EGE LL_DMAMUX_EnableEventGeneration
988 * @param DMAMUXx DMAMUXx Instance
989 * @param Channel This parameter can be one of the following values:
990 * @arg @ref LL_DMAMUX_CHANNEL_0
991 * @arg @ref LL_DMAMUX_CHANNEL_1
992 * @arg @ref LL_DMAMUX_CHANNEL_2
993 * @arg @ref LL_DMAMUX_CHANNEL_3
994 * @arg @ref LL_DMAMUX_CHANNEL_4
995 * @arg @ref LL_DMAMUX_CHANNEL_5
996 * @arg @ref LL_DMAMUX_CHANNEL_6
997 * @arg @ref LL_DMAMUX_CHANNEL_7
998 * @arg @ref LL_DMAMUX_CHANNEL_8
999 * @arg @ref LL_DMAMUX_CHANNEL_9
1000 * @arg @ref LL_DMAMUX_CHANNEL_10
1001 * @arg @ref LL_DMAMUX_CHANNEL_11
1002 * @arg @ref LL_DMAMUX_CHANNEL_12
1003 * @arg @ref LL_DMAMUX_CHANNEL_13
1004 * @arg @ref LL_DMAMUX_CHANNEL_14
1005 * @arg @ref LL_DMAMUX_CHANNEL_15
1006 * @retval None
1007 */
1008 __STATIC_INLINE void LL_DMAMUX_EnableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1009 {
1010 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1011
1012 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1013 }
1014
1015 /**
1016 * @brief Disable the Event Generation on DMAMUX channel x.
1017 * @rmtoll CxCR EGE LL_DMAMUX_DisableEventGeneration
1018 * @param DMAMUXx DMAMUXx Instance
1019 * @param Channel This parameter can be one of the following values:
1020 * @arg @ref LL_DMAMUX_CHANNEL_0
1021 * @arg @ref LL_DMAMUX_CHANNEL_1
1022 * @arg @ref LL_DMAMUX_CHANNEL_2
1023 * @arg @ref LL_DMAMUX_CHANNEL_3
1024 * @arg @ref LL_DMAMUX_CHANNEL_4
1025 * @arg @ref LL_DMAMUX_CHANNEL_5
1026 * @arg @ref LL_DMAMUX_CHANNEL_6
1027 * @arg @ref LL_DMAMUX_CHANNEL_7
1028 * @arg @ref LL_DMAMUX_CHANNEL_8
1029 * @arg @ref LL_DMAMUX_CHANNEL_9
1030 * @arg @ref LL_DMAMUX_CHANNEL_10
1031 * @arg @ref LL_DMAMUX_CHANNEL_11
1032 * @arg @ref LL_DMAMUX_CHANNEL_12
1033 * @arg @ref LL_DMAMUX_CHANNEL_13
1034 * @arg @ref LL_DMAMUX_CHANNEL_14
1035 * @arg @ref LL_DMAMUX_CHANNEL_15
1036 * @retval None
1037 */
1038 __STATIC_INLINE void LL_DMAMUX_DisableEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1039 {
1040 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1041
1042 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE);
1043 }
1044
1045 /**
1046 * @brief Check if the Event Generation on DMAMUX channel x is enabled or disabled.
1047 * @rmtoll CxCR EGE LL_DMAMUX_IsEnabledEventGeneration
1048 * @param DMAMUXx DMAMUXx Instance
1049 * @param Channel This parameter can be one of the following values:
1050 * @arg @ref LL_DMAMUX_CHANNEL_0
1051 * @arg @ref LL_DMAMUX_CHANNEL_1
1052 * @arg @ref LL_DMAMUX_CHANNEL_2
1053 * @arg @ref LL_DMAMUX_CHANNEL_3
1054 * @arg @ref LL_DMAMUX_CHANNEL_4
1055 * @arg @ref LL_DMAMUX_CHANNEL_5
1056 * @arg @ref LL_DMAMUX_CHANNEL_6
1057 * @arg @ref LL_DMAMUX_CHANNEL_7
1058 * @arg @ref LL_DMAMUX_CHANNEL_8
1059 * @arg @ref LL_DMAMUX_CHANNEL_9
1060 * @arg @ref LL_DMAMUX_CHANNEL_10
1061 * @arg @ref LL_DMAMUX_CHANNEL_11
1062 * @arg @ref LL_DMAMUX_CHANNEL_12
1063 * @arg @ref LL_DMAMUX_CHANNEL_13
1064 * @arg @ref LL_DMAMUX_CHANNEL_14
1065 * @arg @ref LL_DMAMUX_CHANNEL_15
1066 * @retval State of bit (1 or 0).
1067 */
1068 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledEventGeneration(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1069 {
1070 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1071
1072 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_EGE) == (DMAMUX_CxCR_EGE)) ? 1UL : 0UL);
1073 }
1074
1075 /**
1076 * @brief Enable the synchronization mode.
1077 * @rmtoll CxCR SE LL_DMAMUX_EnableSync
1078 * @param DMAMUXx DMAMUXx Instance
1079 * @param Channel This parameter can be one of the following values:
1080 * @arg @ref LL_DMAMUX_CHANNEL_0
1081 * @arg @ref LL_DMAMUX_CHANNEL_1
1082 * @arg @ref LL_DMAMUX_CHANNEL_2
1083 * @arg @ref LL_DMAMUX_CHANNEL_3
1084 * @arg @ref LL_DMAMUX_CHANNEL_4
1085 * @arg @ref LL_DMAMUX_CHANNEL_5
1086 * @arg @ref LL_DMAMUX_CHANNEL_6
1087 * @arg @ref LL_DMAMUX_CHANNEL_7
1088 * @arg @ref LL_DMAMUX_CHANNEL_8
1089 * @arg @ref LL_DMAMUX_CHANNEL_9
1090 * @arg @ref LL_DMAMUX_CHANNEL_10
1091 * @arg @ref LL_DMAMUX_CHANNEL_11
1092 * @arg @ref LL_DMAMUX_CHANNEL_12
1093 * @arg @ref LL_DMAMUX_CHANNEL_13
1094 * @arg @ref LL_DMAMUX_CHANNEL_14
1095 * @arg @ref LL_DMAMUX_CHANNEL_15
1096 * @retval None
1097 */
1098 __STATIC_INLINE void LL_DMAMUX_EnableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1099 {
1100 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1101
1102 SET_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1103 }
1104
1105 /**
1106 * @brief Disable the synchronization mode.
1107 * @rmtoll CxCR SE LL_DMAMUX_DisableSync
1108 * @param DMAMUXx DMAMUXx Instance
1109 * @param Channel This parameter can be one of the following values:
1110 * @arg @ref LL_DMAMUX_CHANNEL_0
1111 * @arg @ref LL_DMAMUX_CHANNEL_1
1112 * @arg @ref LL_DMAMUX_CHANNEL_2
1113 * @arg @ref LL_DMAMUX_CHANNEL_3
1114 * @arg @ref LL_DMAMUX_CHANNEL_4
1115 * @arg @ref LL_DMAMUX_CHANNEL_5
1116 * @arg @ref LL_DMAMUX_CHANNEL_6
1117 * @arg @ref LL_DMAMUX_CHANNEL_7
1118 * @arg @ref LL_DMAMUX_CHANNEL_8
1119 * @arg @ref LL_DMAMUX_CHANNEL_9
1120 * @arg @ref LL_DMAMUX_CHANNEL_10
1121 * @arg @ref LL_DMAMUX_CHANNEL_11
1122 * @arg @ref LL_DMAMUX_CHANNEL_12
1123 * @arg @ref LL_DMAMUX_CHANNEL_13
1124 * @arg @ref LL_DMAMUX_CHANNEL_14
1125 * @arg @ref LL_DMAMUX_CHANNEL_15
1126 * @retval None
1127 */
1128 __STATIC_INLINE void LL_DMAMUX_DisableSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1129 {
1130 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1131
1132 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE);
1133 }
1134
1135 /**
1136 * @brief Check if the synchronization mode is enabled or disabled.
1137 * @rmtoll CxCR SE LL_DMAMUX_IsEnabledSync
1138 * @param DMAMUXx DMAMUXx Instance
1139 * @param Channel This parameter can be one of the following values:
1140 * @arg @ref LL_DMAMUX_CHANNEL_0
1141 * @arg @ref LL_DMAMUX_CHANNEL_1
1142 * @arg @ref LL_DMAMUX_CHANNEL_2
1143 * @arg @ref LL_DMAMUX_CHANNEL_3
1144 * @arg @ref LL_DMAMUX_CHANNEL_4
1145 * @arg @ref LL_DMAMUX_CHANNEL_5
1146 * @arg @ref LL_DMAMUX_CHANNEL_6
1147 * @arg @ref LL_DMAMUX_CHANNEL_7
1148 * @arg @ref LL_DMAMUX_CHANNEL_8
1149 * @arg @ref LL_DMAMUX_CHANNEL_9
1150 * @arg @ref LL_DMAMUX_CHANNEL_10
1151 * @arg @ref LL_DMAMUX_CHANNEL_11
1152 * @arg @ref LL_DMAMUX_CHANNEL_12
1153 * @arg @ref LL_DMAMUX_CHANNEL_13
1154 * @arg @ref LL_DMAMUX_CHANNEL_14
1155 * @arg @ref LL_DMAMUX_CHANNEL_15
1156 * @retval State of bit (1 or 0).
1157 */
1158 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledSync(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1159 {
1160 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1161
1162 return ((READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SE) == (DMAMUX_CxCR_SE)) ? 1UL : 0UL);
1163 }
1164
1165 /**
1166 * @brief Set DMAMUX synchronization ID on DMAMUX Channel x.
1167 * @rmtoll CxCR SYNC_ID LL_DMAMUX_SetSyncID
1168 * @param DMAMUXx DMAMUXx Instance
1169 * @param Channel This parameter can be one of the following values:
1170 * @arg @ref LL_DMAMUX_CHANNEL_0
1171 * @arg @ref LL_DMAMUX_CHANNEL_1
1172 * @arg @ref LL_DMAMUX_CHANNEL_2
1173 * @arg @ref LL_DMAMUX_CHANNEL_3
1174 * @arg @ref LL_DMAMUX_CHANNEL_4
1175 * @arg @ref LL_DMAMUX_CHANNEL_5
1176 * @arg @ref LL_DMAMUX_CHANNEL_6
1177 * @arg @ref LL_DMAMUX_CHANNEL_7
1178 * @arg @ref LL_DMAMUX_CHANNEL_8
1179 * @arg @ref LL_DMAMUX_CHANNEL_9
1180 * @arg @ref LL_DMAMUX_CHANNEL_10
1181 * @arg @ref LL_DMAMUX_CHANNEL_11
1182 * @arg @ref LL_DMAMUX_CHANNEL_12
1183 * @arg @ref LL_DMAMUX_CHANNEL_13
1184 * @arg @ref LL_DMAMUX_CHANNEL_14
1185 * @arg @ref LL_DMAMUX_CHANNEL_15
1186 * @param SyncID This parameter can be one of the following values:
1187 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1188 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1189 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1190 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1191 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1192 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1193 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1194 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1195 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1196 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1197 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1198 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1199 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1200 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1201 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1202 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1203 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1204 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1205 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1206 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1207 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1208 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1209 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1210 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1211 * @retval None
1212 */
1213 __STATIC_INLINE void LL_DMAMUX_SetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel, uint32_t SyncID)
1214 {
1215 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1216
1217 MODIFY_REG(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID, SyncID);
1218 }
1219
1220 /**
1221 * @brief Get DMAMUX synchronization ID on DMAMUX Channel x.
1222 * @rmtoll CxCR SYNC_ID LL_DMAMUX_GetSyncID
1223 * @param DMAMUXx DMAMUXx Instance
1224 * @param Channel This parameter can be one of the following values:
1225 * @arg @ref LL_DMAMUX_CHANNEL_0
1226 * @arg @ref LL_DMAMUX_CHANNEL_1
1227 * @arg @ref LL_DMAMUX_CHANNEL_2
1228 * @arg @ref LL_DMAMUX_CHANNEL_3
1229 * @arg @ref LL_DMAMUX_CHANNEL_4
1230 * @arg @ref LL_DMAMUX_CHANNEL_5
1231 * @arg @ref LL_DMAMUX_CHANNEL_6
1232 * @arg @ref LL_DMAMUX_CHANNEL_7
1233 * @arg @ref LL_DMAMUX_CHANNEL_8
1234 * @arg @ref LL_DMAMUX_CHANNEL_9
1235 * @arg @ref LL_DMAMUX_CHANNEL_10
1236 * @arg @ref LL_DMAMUX_CHANNEL_11
1237 * @arg @ref LL_DMAMUX_CHANNEL_12
1238 * @arg @ref LL_DMAMUX_CHANNEL_13
1239 * @arg @ref LL_DMAMUX_CHANNEL_14
1240 * @arg @ref LL_DMAMUX_CHANNEL_15
1241 * @retval Returned value can be one of the following values:
1242 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1243 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1244 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1245 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1246 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1247 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1248 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1249 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1250 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1251 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1252 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1253 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1254 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1255 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1256 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1257 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1258 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1259 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1260 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1261 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1262 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1263 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1264 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1265 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1266 */
1267 __STATIC_INLINE uint32_t LL_DMAMUX_GetSyncID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
1268 {
1269 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1270
1271 return (uint32_t)(READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SYNC_ID));
1272 }
1273
1274 /**
1275 * @brief Enable the Request Generator.
1276 * @rmtoll RGxCR GE LL_DMAMUX_EnableRequestGen
1277 * @param DMAMUXx DMAMUXx Instance
1278 * @param RequestGenChannel This parameter can be one of the following values:
1279 * @arg @ref LL_DMAMUX_REQ_GEN_0
1280 * @arg @ref LL_DMAMUX_REQ_GEN_1
1281 * @arg @ref LL_DMAMUX_REQ_GEN_2
1282 * @arg @ref LL_DMAMUX_REQ_GEN_3
1283 * @arg @ref LL_DMAMUX_REQ_GEN_4
1284 * @arg @ref LL_DMAMUX_REQ_GEN_5
1285 * @arg @ref LL_DMAMUX_REQ_GEN_6
1286 * @arg @ref LL_DMAMUX_REQ_GEN_7
1287 * @retval None
1288 */
1289 __STATIC_INLINE void LL_DMAMUX_EnableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1290 {
1291 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1292
1293 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1294 }
1295
1296 /**
1297 * @brief Disable the Request Generator.
1298 * @rmtoll RGxCR GE LL_DMAMUX_DisableRequestGen
1299 * @param DMAMUXx DMAMUXx Instance
1300 * @param RequestGenChannel This parameter can be one of the following values:
1301 * @arg @ref LL_DMAMUX_REQ_GEN_0
1302 * @arg @ref LL_DMAMUX_REQ_GEN_1
1303 * @arg @ref LL_DMAMUX_REQ_GEN_2
1304 * @arg @ref LL_DMAMUX_REQ_GEN_3
1305 * @retval None
1306 */
1307 __STATIC_INLINE void LL_DMAMUX_DisableRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1308 {
1309 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1310
1311 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * (RequestGenChannel))))->RGCR, DMAMUX_RGxCR_GE);
1312 }
1313
1314 /**
1315 * @brief Check if the Request Generator is enabled or disabled.
1316 * @rmtoll RGxCR GE LL_DMAMUX_IsEnabledRequestGen
1317 * @param DMAMUXx DMAMUXx Instance
1318 * @param RequestGenChannel This parameter can be one of the following values:
1319 * @arg @ref LL_DMAMUX_REQ_GEN_0
1320 * @arg @ref LL_DMAMUX_REQ_GEN_1
1321 * @arg @ref LL_DMAMUX_REQ_GEN_2
1322 * @arg @ref LL_DMAMUX_REQ_GEN_3
1323 * @arg @ref LL_DMAMUX_REQ_GEN_4
1324 * @arg @ref LL_DMAMUX_REQ_GEN_5
1325 * @arg @ref LL_DMAMUX_REQ_GEN_6
1326 * @arg @ref LL_DMAMUX_REQ_GEN_7
1327 * @retval State of bit (1 or 0).
1328 */
1329 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledRequestGen(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1330 {
1331 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1332
1333 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GE) == (DMAMUX_RGxCR_GE)) ? 1UL : 0UL);
1334 }
1335
1336 /**
1337 * @brief Set the polarity of the signal on which the DMA request is generated.
1338 * @rmtoll RGxCR GPOL LL_DMAMUX_SetRequestGenPolarity
1339 * @param DMAMUXx DMAMUXx Instance
1340 * @param RequestGenChannel This parameter can be one of the following values:
1341 * @arg @ref LL_DMAMUX_REQ_GEN_0
1342 * @arg @ref LL_DMAMUX_REQ_GEN_1
1343 * @arg @ref LL_DMAMUX_REQ_GEN_2
1344 * @arg @ref LL_DMAMUX_REQ_GEN_3
1345 * @arg @ref LL_DMAMUX_REQ_GEN_4
1346 * @arg @ref LL_DMAMUX_REQ_GEN_5
1347 * @arg @ref LL_DMAMUX_REQ_GEN_6
1348 * @arg @ref LL_DMAMUX_REQ_GEN_7
1349 * @param Polarity This parameter can be one of the following values:
1350 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1351 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1352 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1353 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1354 * @retval None
1355 */
1356 __STATIC_INLINE void LL_DMAMUX_SetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t Polarity)
1357 {
1358 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1359
1360 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL, Polarity);
1361 }
1362
1363 /**
1364 * @brief Get the polarity of the signal on which the DMA request is generated.
1365 * @rmtoll RGxCR GPOL LL_DMAMUX_GetRequestGenPolarity
1366 * @param DMAMUXx DMAMUXx Instance
1367 * @param RequestGenChannel This parameter can be one of the following values:
1368 * @arg @ref LL_DMAMUX_REQ_GEN_0
1369 * @arg @ref LL_DMAMUX_REQ_GEN_1
1370 * @arg @ref LL_DMAMUX_REQ_GEN_2
1371 * @arg @ref LL_DMAMUX_REQ_GEN_3
1372 * @arg @ref LL_DMAMUX_REQ_GEN_4
1373 * @arg @ref LL_DMAMUX_REQ_GEN_5
1374 * @arg @ref LL_DMAMUX_REQ_GEN_6
1375 * @arg @ref LL_DMAMUX_REQ_GEN_7
1376 * @retval Returned value can be one of the following values:
1377 * @arg @ref LL_DMAMUX_REQ_GEN_NO_EVENT
1378 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING
1379 * @arg @ref LL_DMAMUX_REQ_GEN_POL_FALLING
1380 * @arg @ref LL_DMAMUX_REQ_GEN_POL_RISING_FALLING
1381 */
1382 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestGenPolarity(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1383 {
1384 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1385
1386 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GPOL));
1387 }
1388
1389 /**
1390 * @brief Set the number of DMA request that will be autorized after a generation event.
1391 * @note This field can only be written when Generator is disabled.
1392 * @rmtoll RGxCR GNBREQ LL_DMAMUX_SetGenRequestNb
1393 * @param DMAMUXx DMAMUXx Instance
1394 * @param RequestGenChannel This parameter can be one of the following values:
1395 * @arg @ref LL_DMAMUX_REQ_GEN_0
1396 * @arg @ref LL_DMAMUX_REQ_GEN_1
1397 * @arg @ref LL_DMAMUX_REQ_GEN_2
1398 * @arg @ref LL_DMAMUX_REQ_GEN_3
1399 * @arg @ref LL_DMAMUX_REQ_GEN_4
1400 * @arg @ref LL_DMAMUX_REQ_GEN_5
1401 * @arg @ref LL_DMAMUX_REQ_GEN_6
1402 * @arg @ref LL_DMAMUX_REQ_GEN_7
1403 * @param RequestNb This parameter must be a value between Min_Data = 1 and Max_Data = 32.
1404 * @retval None
1405 */
1406 __STATIC_INLINE void LL_DMAMUX_SetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestNb)
1407 {
1408 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1409
1410 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ, (RequestNb - 1U) << DMAMUX_RGxCR_GNBREQ_Pos);
1411 }
1412
1413 /**
1414 * @brief Get the number of DMA request that will be autorized after a generation event.
1415 * @rmtoll RGxCR GNBREQ LL_DMAMUX_GetGenRequestNb
1416 * @param DMAMUXx DMAMUXx Instance
1417 * @param RequestGenChannel This parameter can be one of the following values:
1418 * @arg @ref LL_DMAMUX_REQ_GEN_0
1419 * @arg @ref LL_DMAMUX_REQ_GEN_1
1420 * @arg @ref LL_DMAMUX_REQ_GEN_2
1421 * @arg @ref LL_DMAMUX_REQ_GEN_3
1422 * @arg @ref LL_DMAMUX_REQ_GEN_4
1423 * @arg @ref LL_DMAMUX_REQ_GEN_5
1424 * @arg @ref LL_DMAMUX_REQ_GEN_6
1425 * @arg @ref LL_DMAMUX_REQ_GEN_7
1426 * @retval Between Min_Data = 1 and Max_Data = 32
1427 */
1428 __STATIC_INLINE uint32_t LL_DMAMUX_GetGenRequestNb(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1429 {
1430 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1431
1432 return (uint32_t)((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_GNBREQ) >> DMAMUX_RGxCR_GNBREQ_Pos) + 1U);
1433 }
1434
1435 /**
1436 * @brief Set DMAMUX external Request Signal ID on DMAMUX Request Generation Trigger Event Channel x.
1437 * @rmtoll RGxCR SIG_ID LL_DMAMUX_SetRequestSignalID
1438 * @param DMAMUXx DMAMUXx Instance
1439 * @param RequestGenChannel This parameter can be one of the following values:
1440 * @arg @ref LL_DMAMUX_REQ_GEN_0
1441 * @arg @ref LL_DMAMUX_REQ_GEN_1
1442 * @arg @ref LL_DMAMUX_REQ_GEN_2
1443 * @arg @ref LL_DMAMUX_REQ_GEN_3
1444 * @arg @ref LL_DMAMUX_REQ_GEN_4
1445 * @arg @ref LL_DMAMUX_REQ_GEN_5
1446 * @arg @ref LL_DMAMUX_REQ_GEN_6
1447 * @arg @ref LL_DMAMUX_REQ_GEN_7
1448 * @param RequestSignalID This parameter can be one of the following values:
1449 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH0_EVT
1450 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH1_EVT
1451 * @arg @ref LL_DMAMUX1_REQ_GEN_DMAMUX1_CH2_EVT
1452 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM1_OUT
1453 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM2_OUT
1454 * @arg @ref LL_DMAMUX1_REQ_GEN_LPTIM3_OUT
1455 * @arg @ref LL_DMAMUX1_REQ_GEN_EXTI0
1456 * @arg @ref LL_DMAMUX1_REQ_GEN_TIM12_TRGO
1457 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH0_EVT
1458 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH1_EVT
1459 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH2_EVT
1460 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH3_EVT
1461 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH4_EVT
1462 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH5_EVT
1463 * @arg @ref LL_DMAMUX2_REQ_GEN_DMAMUX2_CH6_EVT
1464 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_WKUP
1465 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_WKUP
1466 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_WKUP
1467 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM2_OUT
1468 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_WKUP
1469 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM3_OUT
1470 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM4_WKUP (*)
1471 * @arg @ref LL_DMAMUX2_REQ_GEN_LPTIM5_WKUP (*)
1472 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_WKUP
1473 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_WKUP
1474 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP1_OUT
1475 * @arg @ref LL_DMAMUX2_REQ_GEN_COMP2_OUT
1476 * @arg @ref LL_DMAMUX2_REQ_GEN_RTC_WKUP
1477 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI0
1478 * @arg @ref LL_DMAMUX2_REQ_GEN_EXTI2
1479 * @arg @ref LL_DMAMUX2_REQ_GEN_I2C4_IT_EVT
1480 * @arg @ref LL_DMAMUX2_REQ_GEN_SPI6_IT
1481 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_TX_IT
1482 * @arg @ref LL_DMAMUX2_REQ_GEN_LPUART1_RX_IT
1483 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_IT (*)
1484 * @arg @ref LL_DMAMUX2_REQ_GEN_ADC3_AWD1_OUT (*)
1485 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH0_IT
1486 * @arg @ref LL_DMAMUX2_REQ_GEN_BDMA_CH1_IT
1487 * @note (*) Availability depends on devices.
1488 * @retval None
1489 */
1490 __STATIC_INLINE void LL_DMAMUX_SetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel, uint32_t RequestSignalID)
1491 {
1492 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1493
1494 MODIFY_REG(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID, RequestSignalID);
1495 }
1496
1497 /**
1498 * @brief Get DMAMUX external Request Signal ID set on DMAMUX Channel x.
1499 * @rmtoll RGxCR SIG_ID LL_DMAMUX_GetRequestSignalID
1500 * @param DMAMUXx DMAMUXx Instance
1501 * @param RequestGenChannel This parameter can be one of the following values:
1502 * @arg @ref LL_DMAMUX_REQ_GEN_0
1503 * @arg @ref LL_DMAMUX_REQ_GEN_1
1504 * @arg @ref LL_DMAMUX_REQ_GEN_2
1505 * @arg @ref LL_DMAMUX_REQ_GEN_3
1506 * @arg @ref LL_DMAMUX_REQ_GEN_4
1507 * @arg @ref LL_DMAMUX_REQ_GEN_5
1508 * @arg @ref LL_DMAMUX_REQ_GEN_6
1509 * @arg @ref LL_DMAMUX_REQ_GEN_7
1510 * @retval Returned value can be one of the following values:
1511 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH0_EVT
1512 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH1_EVT
1513 * @arg @ref LL_DMAMUX1_SYNC_DMAMUX1_CH2_EVT
1514 * @arg @ref LL_DMAMUX1_SYNC_LPTIM1_OUT
1515 * @arg @ref LL_DMAMUX1_SYNC_LPTIM2_OUT
1516 * @arg @ref LL_DMAMUX1_SYNC_LPTIM3_OUT
1517 * @arg @ref LL_DMAMUX1_SYNC_EXTI0
1518 * @arg @ref LL_DMAMUX1_SYNC_TIM12_TRGO
1519 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH0_EVT
1520 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH1_EVT
1521 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH2_EVT
1522 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH3_EVT
1523 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH4_EVT
1524 * @arg @ref LL_DMAMUX2_SYNC_DMAMUX2_CH5_EVT
1525 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_RX_WKUP
1526 * @arg @ref LL_DMAMUX2_SYNC_LPUART1_TX_WKUP
1527 * @arg @ref LL_DMAMUX2_SYNC_LPTIM2_OUT
1528 * @arg @ref LL_DMAMUX2_SYNC_LPTIM3_OUT
1529 * @arg @ref LL_DMAMUX2_SYNC_I2C4_WKUP
1530 * @arg @ref LL_DMAMUX2_SYNC_SPI6_WKUP
1531 * @arg @ref LL_DMAMUX2_SYNC_COMP1_OUT
1532 * @arg @ref LL_DMAMUX2_SYNC_RTC_WKUP
1533 * @arg @ref LL_DMAMUX2_SYNC_EXTI0
1534 * @arg @ref LL_DMAMUX2_SYNC_EXTI2
1535 */
1536 __STATIC_INLINE uint32_t LL_DMAMUX_GetRequestSignalID(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
1537 {
1538 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1539
1540 return (uint32_t)(READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_SIG_ID));
1541 }
1542
1543 /**
1544 * @}
1545 */
1546
1547 /** @defgroup DMAMUX_LL_EF_FLAG_Management FLAG_Management
1548 * @{
1549 */
1550
1551 /**
1552 * @brief Get Synchronization Event Overrun Flag Channel 0.
1553 * @rmtoll CSR SOF0 LL_DMAMUX_IsActiveFlag_SO0
1554 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1555 * @retval State of bit (1 or 0).
1556 */
1557 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1558 {
1559 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1560
1561 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF0) == (DMAMUX_CSR_SOF0)) ? 1UL : 0UL);
1562 }
1563
1564 /**
1565 * @brief Get Synchronization Event Overrun Flag Channel 1.
1566 * @rmtoll CSR SOF1 LL_DMAMUX_IsActiveFlag_SO1
1567 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1568 * @retval State of bit (1 or 0).
1569 */
1570 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1571 {
1572 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1573
1574 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF1) == (DMAMUX_CSR_SOF1)) ? 1UL : 0UL);
1575 }
1576
1577 /**
1578 * @brief Get Synchronization Event Overrun Flag Channel 2.
1579 * @rmtoll CSR SOF2 LL_DMAMUX_IsActiveFlag_SO2
1580 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1581 * @retval State of bit (1 or 0).
1582 */
1583 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1584 {
1585 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1586
1587 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF2) == (DMAMUX_CSR_SOF2)) ? 1UL : 0UL);
1588 }
1589
1590 /**
1591 * @brief Get Synchronization Event Overrun Flag Channel 3.
1592 * @rmtoll CSR SOF3 LL_DMAMUX_IsActiveFlag_SO3
1593 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1594 * @retval State of bit (1 or 0).
1595 */
1596 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1597 {
1598 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1599
1600 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF3) == (DMAMUX_CSR_SOF3)) ? 1UL : 0UL);
1601 }
1602
1603 /**
1604 * @brief Get Synchronization Event Overrun Flag Channel 4.
1605 * @rmtoll CSR SOF4 LL_DMAMUX_IsActiveFlag_SO4
1606 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1607 * @retval State of bit (1 or 0).
1608 */
1609 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1610 {
1611 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1612
1613 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF4) == (DMAMUX_CSR_SOF4)) ? 1UL : 0UL);
1614 }
1615
1616 /**
1617 * @brief Get Synchronization Event Overrun Flag Channel 5.
1618 * @rmtoll CSR SOF5 LL_DMAMUX_IsActiveFlag_SO5
1619 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1620 * @retval State of bit (1 or 0).
1621 */
1622 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1623 {
1624 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1625
1626 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF5) == (DMAMUX_CSR_SOF5)) ? 1UL : 0UL);
1627 }
1628
1629 /**
1630 * @brief Get Synchronization Event Overrun Flag Channel 6.
1631 * @rmtoll CSR SOF6 LL_DMAMUX_IsActiveFlag_SO6
1632 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1633 * @retval State of bit (1 or 0).
1634 */
1635 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1636 {
1637 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1638
1639 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF6) == (DMAMUX_CSR_SOF6)) ? 1UL : 0UL);
1640 }
1641
1642 /**
1643 * @brief Get Synchronization Event Overrun Flag Channel 7.
1644 * @rmtoll CSR SOF7 LL_DMAMUX_IsActiveFlag_SO7
1645 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1646 * @retval State of bit (1 or 0).
1647 */
1648 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1649 {
1650 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1651
1652 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF7) == (DMAMUX_CSR_SOF7)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Get Synchronization Event Overrun Flag Channel 8.
1657 * @rmtoll CSR SOF8 LL_DMAMUX_IsActiveFlag_SO8
1658 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1659 * @retval State of bit (1 or 0).
1660 */
1661 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1662 {
1663 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1664
1665 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF8) == (DMAMUX_CSR_SOF8)) ? 1UL : 0UL);
1666 }
1667
1668 /**
1669 * @brief Get Synchronization Event Overrun Flag Channel 9.
1670 * @rmtoll CSR SOF9 LL_DMAMUX_IsActiveFlag_SO9
1671 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1672 * @retval State of bit (1 or 0).
1673 */
1674 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1675 {
1676 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1677
1678 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF9) == (DMAMUX_CSR_SOF9)) ? 1UL : 0UL);
1679 }
1680
1681 /**
1682 * @brief Get Synchronization Event Overrun Flag Channel 10.
1683 * @rmtoll CSR SOF10 LL_DMAMUX_IsActiveFlag_SO10
1684 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1685 * @retval State of bit (1 or 0).
1686 */
1687 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
1688 {
1689 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1690
1691 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF10) == (DMAMUX_CSR_SOF10)) ? 1UL : 0UL);
1692 }
1693
1694 /**
1695 * @brief Get Synchronization Event Overrun Flag Channel 11.
1696 * @rmtoll CSR SOF11 LL_DMAMUX_IsActiveFlag_SO11
1697 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1698 * @retval State of bit (1 or 0).
1699 */
1700 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
1701 {
1702 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1703
1704 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF11) == (DMAMUX_CSR_SOF11)) ? 1UL : 0UL);
1705 }
1706
1707 /**
1708 * @brief Get Synchronization Event Overrun Flag Channel 12.
1709 * @rmtoll CSR SOF12 LL_DMAMUX_IsActiveFlag_SO12
1710 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1711 * @retval State of bit (1 or 0).
1712 */
1713 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
1714 {
1715 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1716
1717 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF12) == (DMAMUX_CSR_SOF12)) ? 1UL : 0UL);
1718 }
1719
1720 /**
1721 * @brief Get Synchronization Event Overrun Flag Channel 13.
1722 * @rmtoll CSR SOF13 LL_DMAMUX_IsActiveFlag_SO13
1723 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1724 * @retval State of bit (1 or 0).
1725 */
1726 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
1727 {
1728 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1729
1730 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF13) == (DMAMUX_CSR_SOF13)) ? 1UL : 0UL);
1731 }
1732
1733 /**
1734 * @brief Get Synchronization Event Overrun Flag Channel 14.
1735 * @rmtoll CSR SOF14 LL_DMAMUX_IsActiveFlag_SO14
1736 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1737 * @retval State of bit (1 or 0).
1738 */
1739 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
1740 {
1741 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1742
1743 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF14) == (DMAMUX_CSR_SOF14)) ? 1UL : 0UL);
1744 }
1745
1746 /**
1747 * @brief Get Synchronization Event Overrun Flag Channel 15.
1748 * @rmtoll CSR SOF15 LL_DMAMUX_IsActiveFlag_SO15
1749 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1750 * @retval State of bit (1 or 0).
1751 */
1752 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
1753 {
1754 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1755
1756 return ((READ_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CSR, DMAMUX_CSR_SOF15) == (DMAMUX_CSR_SOF15)) ? 1UL : 0UL);
1757 }
1758
1759 /**
1760 * @brief Get Request Generator 0 Trigger Event Overrun Flag.
1761 * @rmtoll RGSR OF0 LL_DMAMUX_IsActiveFlag_RGO0
1762 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1763 * @retval State of bit (1 or 0).
1764 */
1765 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1766 {
1767 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1768
1769 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF0) == (DMAMUX_RGSR_OF0)) ? 1UL : 0UL);
1770 }
1771
1772 /**
1773 * @brief Get Request Generator 1 Trigger Event Overrun Flag.
1774 * @rmtoll RGSR OF1 LL_DMAMUX_IsActiveFlag_RGO1
1775 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1776 * @retval State of bit (1 or 0).
1777 */
1778 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1779 {
1780 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1781
1782 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF1) == (DMAMUX_RGSR_OF1)) ? 1UL : 0UL);
1783 }
1784
1785 /**
1786 * @brief Get Request Generator 2 Trigger Event Overrun Flag.
1787 * @rmtoll RGSR OF2 LL_DMAMUX_IsActiveFlag_RGO2
1788 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1789 * @retval State of bit (1 or 0).
1790 */
1791 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1792 {
1793 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1794
1795 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF2) == (DMAMUX_RGSR_OF2)) ? 1UL : 0UL);
1796 }
1797
1798 /**
1799 * @brief Get Request Generator 3 Trigger Event Overrun Flag.
1800 * @rmtoll RGSR OF3 LL_DMAMUX_IsActiveFlag_RGO3
1801 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1802 * @retval State of bit (1 or 0).
1803 */
1804 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1805 {
1806 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1807
1808 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF3) == (DMAMUX_RGSR_OF3)) ? 1UL : 0UL);
1809 }
1810
1811 /**
1812 * @brief Get Request Generator 4 Trigger Event Overrun Flag.
1813 * @rmtoll RGSR OF4 LL_DMAMUX_IsActiveFlag_RGO4
1814 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1815 * @retval State of bit (1 or 0).
1816 */
1817 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1818 {
1819 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1820
1821 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF4) == (DMAMUX_RGSR_OF4)) ? 1UL : 0UL);
1822 }
1823
1824 /**
1825 * @brief Get Request Generator 5 Trigger Event Overrun Flag.
1826 * @rmtoll RGSR OF5 LL_DMAMUX_IsActiveFlag_RGO5
1827 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1828 * @retval State of bit (1 or 0).
1829 */
1830 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1831 {
1832 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1833
1834 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF5) == (DMAMUX_RGSR_OF5)) ? 1UL : 0UL);
1835 }
1836
1837 /**
1838 * @brief Get Request Generator 6 Trigger Event Overrun Flag.
1839 * @rmtoll RGSR OF6 LL_DMAMUX_IsActiveFlag_RGO6
1840 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1841 * @retval State of bit (1 or 0).
1842 */
1843 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1844 {
1845 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1846
1847 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF6) == (DMAMUX_RGSR_OF6)) ? 1UL : 0UL);
1848 }
1849
1850 /**
1851 * @brief Get Request Generator 7 Trigger Event Overrun Flag.
1852 * @rmtoll RGSR OF7 LL_DMAMUX_IsActiveFlag_RGO7
1853 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1854 * @retval State of bit (1 or 0).
1855 */
1856 __STATIC_INLINE uint32_t LL_DMAMUX_IsActiveFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1857 {
1858 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1859
1860 return ((READ_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGSR, DMAMUX_RGSR_OF7) == (DMAMUX_RGSR_OF7)) ? 1UL : 0UL);
1861 }
1862
1863 /**
1864 * @brief Clear Synchronization Event Overrun Flag Channel 0.
1865 * @rmtoll CFR CSOF0 LL_DMAMUX_ClearFlag_SO0
1866 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1867 * @retval None
1868 */
1869 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO0(DMAMUX_Channel_TypeDef *DMAMUXx)
1870 {
1871 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1872
1873 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF0);
1874 }
1875
1876 /**
1877 * @brief Clear Synchronization Event Overrun Flag Channel 1.
1878 * @rmtoll CFR CSOF1 LL_DMAMUX_ClearFlag_SO1
1879 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1880 * @retval None
1881 */
1882 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO1(DMAMUX_Channel_TypeDef *DMAMUXx)
1883 {
1884 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1885
1886 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF1);
1887 }
1888
1889 /**
1890 * @brief Clear Synchronization Event Overrun Flag Channel 2.
1891 * @rmtoll CFR CSOF2 LL_DMAMUX_ClearFlag_SO2
1892 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1893 * @retval None
1894 */
1895 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO2(DMAMUX_Channel_TypeDef *DMAMUXx)
1896 {
1897 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1898
1899 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF2);
1900 }
1901
1902 /**
1903 * @brief Clear Synchronization Event Overrun Flag Channel 3.
1904 * @rmtoll CFR CSOF3 LL_DMAMUX_ClearFlag_SO3
1905 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1906 * @retval None
1907 */
1908 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO3(DMAMUX_Channel_TypeDef *DMAMUXx)
1909 {
1910 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1911
1912 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF3);
1913 }
1914
1915 /**
1916 * @brief Clear Synchronization Event Overrun Flag Channel 4.
1917 * @rmtoll CFR CSOF4 LL_DMAMUX_ClearFlag_SO4
1918 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1919 * @retval None
1920 */
1921 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO4(DMAMUX_Channel_TypeDef *DMAMUXx)
1922 {
1923 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1924
1925 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF4);
1926 }
1927
1928 /**
1929 * @brief Clear Synchronization Event Overrun Flag Channel 5.
1930 * @rmtoll CFR CSOF5 LL_DMAMUX_ClearFlag_SO5
1931 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1932 * @retval None
1933 */
1934 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO5(DMAMUX_Channel_TypeDef *DMAMUXx)
1935 {
1936 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1937
1938 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF5);
1939 }
1940
1941 /**
1942 * @brief Clear Synchronization Event Overrun Flag Channel 6.
1943 * @rmtoll CFR CSOF6 LL_DMAMUX_ClearFlag_SO6
1944 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1945 * @retval None
1946 */
1947 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO6(DMAMUX_Channel_TypeDef *DMAMUXx)
1948 {
1949 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1950
1951 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF6);
1952 }
1953
1954 /**
1955 * @brief Clear Synchronization Event Overrun Flag Channel 7.
1956 * @rmtoll CFR CSOF7 LL_DMAMUX_ClearFlag_SO7
1957 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1958 * @retval None
1959 */
1960 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO7(DMAMUX_Channel_TypeDef *DMAMUXx)
1961 {
1962 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1963
1964 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF7);
1965 }
1966
1967 /**
1968 * @brief Clear Synchronization Event Overrun Flag Channel 8.
1969 * @rmtoll CFR CSOF8 LL_DMAMUX_ClearFlag_SO8
1970 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1971 * @retval None
1972 */
1973 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO8(DMAMUX_Channel_TypeDef *DMAMUXx)
1974 {
1975 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1976
1977 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF8);
1978 }
1979
1980 /**
1981 * @brief Clear Synchronization Event Overrun Flag Channel 9.
1982 * @rmtoll CFR CSOF9 LL_DMAMUX_ClearFlag_SO9
1983 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1984 * @retval None
1985 */
1986 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO9(DMAMUX_Channel_TypeDef *DMAMUXx)
1987 {
1988 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
1989
1990 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF9);
1991 }
1992
1993 /**
1994 * @brief Clear Synchronization Event Overrun Flag Channel 10.
1995 * @rmtoll CFR CSOF10 LL_DMAMUX_ClearFlag_SO10
1996 * @param DMAMUXx DMAMUXx DMAMUXx Instance
1997 * @retval None
1998 */
1999 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO10(DMAMUX_Channel_TypeDef *DMAMUXx)
2000 {
2001 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2002
2003 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF10);
2004 }
2005
2006 /**
2007 * @brief Clear Synchronization Event Overrun Flag Channel 11.
2008 * @rmtoll CFR CSOF11 LL_DMAMUX_ClearFlag_SO11
2009 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2010 * @retval None
2011 */
2012 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO11(DMAMUX_Channel_TypeDef *DMAMUXx)
2013 {
2014 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2015
2016 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF11);
2017 }
2018
2019 /**
2020 * @brief Clear Synchronization Event Overrun Flag Channel 12.
2021 * @rmtoll CFR CSOF12 LL_DMAMUX_ClearFlag_SO12
2022 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2023 * @retval None
2024 */
2025 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO12(DMAMUX_Channel_TypeDef *DMAMUXx)
2026 {
2027 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2028
2029 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF12);
2030 }
2031
2032 /**
2033 * @brief Clear Synchronization Event Overrun Flag Channel 13.
2034 * @rmtoll CFR CSOF13 LL_DMAMUX_ClearFlag_SO13
2035 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2036 * @retval None
2037 */
2038 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO13(DMAMUX_Channel_TypeDef *DMAMUXx)
2039 {
2040 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2041
2042 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF13);
2043 }
2044
2045 /**
2046 * @brief Clear Synchronization Event Overrun Flag Channel 14.
2047 * @rmtoll CFR CSOF14 LL_DMAMUX_ClearFlag_SO14
2048 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2049 * @retval None
2050 */
2051 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO14(DMAMUX_Channel_TypeDef *DMAMUXx)
2052 {
2053 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2054
2055 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF14);
2056 }
2057
2058 /**
2059 * @brief Clear Synchronization Event Overrun Flag Channel 15.
2060 * @rmtoll CFR CSOF15 LL_DMAMUX_ClearFlag_SO15
2061 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2062 * @retval None
2063 */
2064 __STATIC_INLINE void LL_DMAMUX_ClearFlag_SO15(DMAMUX_Channel_TypeDef *DMAMUXx)
2065 {
2066 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2067
2068 SET_BIT(((DMAMUX_ChannelStatus_TypeDef *)(dmamux_base_addr + DMAMUX_CH_STATUS_OFFSET))->CFR, DMAMUX_CFR_CSOF15);
2069 }
2070
2071 /**
2072 * @brief Clear Request Generator 0 Trigger Event Overrun Flag.
2073 * @rmtoll RGCFR COF0 LL_DMAMUX_ClearFlag_RGO0
2074 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2075 * @retval None
2076 */
2077 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO0(DMAMUX_Channel_TypeDef *DMAMUXx)
2078 {
2079 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2080
2081 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF0);
2082 }
2083
2084 /**
2085 * @brief Clear Request Generator 1 Trigger Event Overrun Flag.
2086 * @rmtoll RGCFR COF1 LL_DMAMUX_ClearFlag_RGO1
2087 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2088 * @retval None
2089 */
2090 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO1(DMAMUX_Channel_TypeDef *DMAMUXx)
2091 {
2092 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2093
2094 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF1);
2095 }
2096
2097 /**
2098 * @brief Clear Request Generator 2 Trigger Event Overrun Flag.
2099 * @rmtoll RGCFR COF2 LL_DMAMUX_ClearFlag_RGO2
2100 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2101 * @retval None
2102 */
2103 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO2(DMAMUX_Channel_TypeDef *DMAMUXx)
2104 {
2105 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2106
2107 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF2);
2108 }
2109
2110 /**
2111 * @brief Clear Request Generator 3 Trigger Event Overrun Flag.
2112 * @rmtoll RGCFR COF3 LL_DMAMUX_ClearFlag_RGO3
2113 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2114 * @retval None
2115 */
2116 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO3(DMAMUX_Channel_TypeDef *DMAMUXx)
2117 {
2118 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2119
2120 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF3);
2121 }
2122
2123 /**
2124 * @brief Clear Request Generator 4 Trigger Event Overrun Flag.
2125 * @rmtoll RGCFR COF4 LL_DMAMUX_ClearFlag_RGO4
2126 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2127 * @retval None
2128 */
2129 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO4(DMAMUX_Channel_TypeDef *DMAMUXx)
2130 {
2131 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2132
2133 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF4);
2134 }
2135
2136 /**
2137 * @brief Clear Request Generator 5 Trigger Event Overrun Flag.
2138 * @rmtoll RGCFR COF5 LL_DMAMUX_ClearFlag_RGO5
2139 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2140 * @retval None
2141 */
2142 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO5(DMAMUX_Channel_TypeDef *DMAMUXx)
2143 {
2144 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2145
2146 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF5);
2147 }
2148
2149 /**
2150 * @brief Clear Request Generator 6 Trigger Event Overrun Flag.
2151 * @rmtoll RGCFR COF6 LL_DMAMUX_ClearFlag_RGO6
2152 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2153 * @retval None
2154 */
2155 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO6(DMAMUX_Channel_TypeDef *DMAMUXx)
2156 {
2157 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2158
2159 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF6);
2160 }
2161
2162 /**
2163 * @brief Clear Request Generator 7 Trigger Event Overrun Flag.
2164 * @rmtoll RGCFR COF7 LL_DMAMUX_ClearFlag_RGO7
2165 * @param DMAMUXx DMAMUXx DMAMUXx Instance
2166 * @retval None
2167 */
2168 __STATIC_INLINE void LL_DMAMUX_ClearFlag_RGO7(DMAMUX_Channel_TypeDef *DMAMUXx)
2169 {
2170 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2171
2172 SET_BIT(((DMAMUX_RequestGenStatus_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_STATUS_OFFSET))->RGCFR, DMAMUX_RGCFR_COF7);
2173 }
2174
2175 /**
2176 * @}
2177 */
2178
2179 /** @defgroup DMAMUX_LL_EF_IT_Management IT_Management
2180 * @{
2181 */
2182
2183 /**
2184 * @brief Enable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2185 * @rmtoll CxCR SOIE LL_DMAMUX_EnableIT_SO
2186 * @param DMAMUXx DMAMUXx Instance
2187 * @param Channel This parameter can be one of the following values:
2188 * @arg @ref LL_DMAMUX_CHANNEL_0
2189 * @arg @ref LL_DMAMUX_CHANNEL_1
2190 * @arg @ref LL_DMAMUX_CHANNEL_2
2191 * @arg @ref LL_DMAMUX_CHANNEL_3
2192 * @arg @ref LL_DMAMUX_CHANNEL_4
2193 * @arg @ref LL_DMAMUX_CHANNEL_5
2194 * @arg @ref LL_DMAMUX_CHANNEL_6
2195 * @arg @ref LL_DMAMUX_CHANNEL_7
2196 * @arg @ref LL_DMAMUX_CHANNEL_8
2197 * @arg @ref LL_DMAMUX_CHANNEL_9
2198 * @arg @ref LL_DMAMUX_CHANNEL_10
2199 * @arg @ref LL_DMAMUX_CHANNEL_11
2200 * @arg @ref LL_DMAMUX_CHANNEL_12
2201 * @arg @ref LL_DMAMUX_CHANNEL_13
2202 * @arg @ref LL_DMAMUX_CHANNEL_14
2203 * @arg @ref LL_DMAMUX_CHANNEL_15
2204 * @retval None
2205 */
2206 __STATIC_INLINE void LL_DMAMUX_EnableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2207 {
2208 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2209
2210 SET_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2211 }
2212
2213 /**
2214 * @brief Disable the Synchronization Event Overrun Interrupt on DMAMUX channel x.
2215 * @rmtoll CxCR SOIE LL_DMAMUX_DisableIT_SO
2216 * @param DMAMUXx DMAMUXx Instance
2217 * @param Channel This parameter can be one of the following values:
2218 * @arg @ref LL_DMAMUX_CHANNEL_0
2219 * @arg @ref LL_DMAMUX_CHANNEL_1
2220 * @arg @ref LL_DMAMUX_CHANNEL_2
2221 * @arg @ref LL_DMAMUX_CHANNEL_3
2222 * @arg @ref LL_DMAMUX_CHANNEL_4
2223 * @arg @ref LL_DMAMUX_CHANNEL_5
2224 * @arg @ref LL_DMAMUX_CHANNEL_6
2225 * @arg @ref LL_DMAMUX_CHANNEL_7
2226 * @arg @ref LL_DMAMUX_CHANNEL_8
2227 * @arg @ref LL_DMAMUX_CHANNEL_9
2228 * @arg @ref LL_DMAMUX_CHANNEL_10
2229 * @arg @ref LL_DMAMUX_CHANNEL_11
2230 * @arg @ref LL_DMAMUX_CHANNEL_12
2231 * @arg @ref LL_DMAMUX_CHANNEL_13
2232 * @arg @ref LL_DMAMUX_CHANNEL_14
2233 * @arg @ref LL_DMAMUX_CHANNEL_15
2234 * @retval None
2235 */
2236 __STATIC_INLINE void LL_DMAMUX_DisableIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2237 {
2238 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2239
2240 CLEAR_BIT(((DMAMUX_Channel_TypeDef *)((uint32_t)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel)))))->CCR, DMAMUX_CxCR_SOIE);
2241 }
2242
2243 /**
2244 * @brief Check if the Synchronization Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2245 * @rmtoll CxCR SOIE LL_DMAMUX_IsEnabledIT_SO
2246 * @param DMAMUXx DMAMUXx Instance
2247 * @param Channel This parameter can be one of the following values:
2248 * @arg @ref LL_DMAMUX_CHANNEL_0
2249 * @arg @ref LL_DMAMUX_CHANNEL_1
2250 * @arg @ref LL_DMAMUX_CHANNEL_2
2251 * @arg @ref LL_DMAMUX_CHANNEL_3
2252 * @arg @ref LL_DMAMUX_CHANNEL_4
2253 * @arg @ref LL_DMAMUX_CHANNEL_5
2254 * @arg @ref LL_DMAMUX_CHANNEL_6
2255 * @arg @ref LL_DMAMUX_CHANNEL_7
2256 * @arg @ref LL_DMAMUX_CHANNEL_8
2257 * @arg @ref LL_DMAMUX_CHANNEL_9
2258 * @arg @ref LL_DMAMUX_CHANNEL_10
2259 * @arg @ref LL_DMAMUX_CHANNEL_11
2260 * @arg @ref LL_DMAMUX_CHANNEL_12
2261 * @arg @ref LL_DMAMUX_CHANNEL_13
2262 * @arg @ref LL_DMAMUX_CHANNEL_14
2263 * @arg @ref LL_DMAMUX_CHANNEL_15
2264 * @retval State of bit (1 or 0).
2265 */
2266 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_SO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t Channel)
2267 {
2268 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2269
2270 return (READ_BIT(((DMAMUX_Channel_TypeDef *)(dmamux_base_addr + (DMAMUX_CCR_SIZE * (Channel))))->CCR, DMAMUX_CxCR_SOIE));
2271 }
2272
2273 /**
2274 * @brief Enable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2275 * @rmtoll RGxCR OIE LL_DMAMUX_EnableIT_RGO
2276 * @param DMAMUXx DMAMUXx Instance
2277 * @param RequestGenChannel This parameter can be one of the following values:
2278 * @arg @ref LL_DMAMUX_REQ_GEN_0
2279 * @arg @ref LL_DMAMUX_REQ_GEN_1
2280 * @arg @ref LL_DMAMUX_REQ_GEN_2
2281 * @arg @ref LL_DMAMUX_REQ_GEN_3
2282 * @arg @ref LL_DMAMUX_REQ_GEN_4
2283 * @arg @ref LL_DMAMUX_REQ_GEN_5
2284 * @arg @ref LL_DMAMUX_REQ_GEN_6
2285 * @arg @ref LL_DMAMUX_REQ_GEN_7
2286 * @retval None
2287 */
2288 __STATIC_INLINE void LL_DMAMUX_EnableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2289 {
2290 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2291
2292 SET_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2293 }
2294
2295 /**
2296 * @brief Disable the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x.
2297 * @rmtoll RGxCR OIE LL_DMAMUX_DisableIT_RGO
2298 * @param DMAMUXx DMAMUXx Instance
2299 * @param RequestGenChannel This parameter can be one of the following values:
2300 * @arg @ref LL_DMAMUX_REQ_GEN_0
2301 * @arg @ref LL_DMAMUX_REQ_GEN_1
2302 * @arg @ref LL_DMAMUX_REQ_GEN_2
2303 * @arg @ref LL_DMAMUX_REQ_GEN_3
2304 * @arg @ref LL_DMAMUX_REQ_GEN_4
2305 * @arg @ref LL_DMAMUX_REQ_GEN_5
2306 * @arg @ref LL_DMAMUX_REQ_GEN_6
2307 * @arg @ref LL_DMAMUX_REQ_GEN_7
2308 * @retval None
2309 */
2310 __STATIC_INLINE void LL_DMAMUX_DisableIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2311 {
2312 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2313
2314 CLEAR_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE);
2315 }
2316
2317 /**
2318 * @brief Check if the Request Generation Trigger Event Overrun Interrupt on DMAMUX channel x is enabled or disabled.
2319 * @rmtoll RGxCR OIE LL_DMAMUX_IsEnabledIT_RGO
2320 * @param DMAMUXx DMAMUXx Instance
2321 * @param RequestGenChannel This parameter can be one of the following values:
2322 * @arg @ref LL_DMAMUX_REQ_GEN_0
2323 * @arg @ref LL_DMAMUX_REQ_GEN_1
2324 * @arg @ref LL_DMAMUX_REQ_GEN_2
2325 * @arg @ref LL_DMAMUX_REQ_GEN_3
2326 * @arg @ref LL_DMAMUX_REQ_GEN_4
2327 * @arg @ref LL_DMAMUX_REQ_GEN_5
2328 * @arg @ref LL_DMAMUX_REQ_GEN_6
2329 * @arg @ref LL_DMAMUX_REQ_GEN_7
2330 * @retval State of bit (1 or 0).
2331 */
2332 __STATIC_INLINE uint32_t LL_DMAMUX_IsEnabledIT_RGO(DMAMUX_Channel_TypeDef *DMAMUXx, uint32_t RequestGenChannel)
2333 {
2334 register uint32_t dmamux_base_addr = (uint32_t)DMAMUXx;
2335
2336 return ((READ_BIT(((DMAMUX_RequestGen_TypeDef *)(dmamux_base_addr + DMAMUX_REQ_GEN_OFFSET + (DMAMUX_RGCR_SIZE * RequestGenChannel)))->RGCR, DMAMUX_RGxCR_OIE) == (DMAMUX_RGxCR_OIE)) ? 1UL : 0UL);
2337 }
2338
2339 /**
2340 * @}
2341 */
2342
2343 /**
2344 * @}
2345 */
2346
2347 /**
2348 * @}
2349 */
2350
2351 #endif /* DMAMUX1 || DMAMUX2 */
2352
2353 /**
2354 * @}
2355 */
2356
2357 #ifdef __cplusplus
2358 }
2359 #endif
2360
2361 #endif /* __STM32H7xx_LL_DMAMUX_H */
2362
2363 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software