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Merge pull request #10592 from iNavFlight/MrD_Update-parameter-description
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_pwr.h
blob1e0d0cd3e0c9715dee5ab429f93708e2a2ec14c5
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_pwr.h
4 * @author MCD Application Team
5 * @brief Header file of PWR LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * <h2><center>&copy; COPYRIGHT(c) 2017 STMicroelectronics.
10 * All rights reserved.</center></h2>
11 *
12 * This software component is licensed by ST under BSD 3-Clause license,
13 * the "License"; You may not use this file except in compliance with the
14 * License. You may obtain a copy of the License at:
15 * opensource.org/licenses/BSD-3-Clause
16 *
17 ******************************************************************************
18 */
19
20 /* Define to prevent recursive inclusion -------------------------------------*/
21 #ifndef STM32H7xx_LL_PWR_H
22 #define STM32H7xx_LL_PWR_H
23
24 #ifdef __cplusplus
25 extern "C" {
26 #endif
27
28 /* Includes ------------------------------------------------------------------*/
29 #include "stm32h7xx.h"
30
31 /** @addtogroup STM32H7xx_LL_Driver
32 * @{
33 */
34
35 #if defined (PWR)
36
37 /** @defgroup PWR_LL PWR
38 * @{
39 */
40
41 /* Private types -------------------------------------------------------------*/
42 /* Private variables ---------------------------------------------------------*/
43 /* Private constants ---------------------------------------------------------*/
44 /** @defgroup PWR_LL_Private_Constants PWR Private Constants
45 * @{
46 */
47
48 /** @defgroup PWR_LL_WAKEUP_PIN_OFFSET Wake-Up Pins register offsets Defines
49 * @brief Flags defines which can be used with LL_PWR_WriteReg function
50 * @{
51 */
52 /* Wake-Up Pins PWR register offsets */
53 #define LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET 2UL
54 #define LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK 0x1FU
55 /**
56 * @}
57 */
58 /**
59 * @}
60 */
61 /* Private macros ------------------------------------------------------------*/
62 /* Exported types ------------------------------------------------------------*/
63 /* Exported constants --------------------------------------------------------*/
64 /** @defgroup PWR_LL_Exported_Constants PWR Exported Constants
65 * @{
66 */
67
68 /** @defgroup PWR_LL_EC_CLEAR_FLAG Clear Flags Defines
69 * @brief Flags defines which can be used with LL_PWR_WriteReg function
70 * @{
71 */
72 #define LL_PWR_FLAG_CPU_CSSF PWR_CPUCR_CSSF /*!< Clear flags for CPU */
73 #if defined (DUAL_CORE)
74 #define LL_PWR_FLAG_CPU2_CSSF PWR_CPU2CR_CSSF /*!< Clear flags for CPU2 */
75 #endif /* DUAL_CORE */
76 #define LL_PWR_FLAG_WKUPCR_WKUPC6 PWR_WKUPCR_WKUPC6 /*!< Clear PC1 WKUP flag */
77 #define LL_PWR_FLAG_WKUPCR_WKUPC5 PWR_WKUPCR_WKUPC5 /*!< Clear PI11 WKUP flag */
78 #define LL_PWR_FLAG_WKUPCR_WKUPC4 PWR_WKUPCR_WKUPC4 /*!< Clear PC13 WKUP flag */
79 #define LL_PWR_FLAG_WKUPCR_WKUPC3 PWR_WKUPCR_WKUPC3 /*!< Clear PI8 WKUP flag */
80 #define LL_PWR_FLAG_WKUPCR_WKUPC2 PWR_WKUPCR_WKUPC2 /*!< Clear PA2 WKUP flag */
81 #define LL_PWR_FLAG_WKUPCR_WKUPC1 PWR_WKUPCR_WKUPC1 /*!< Clear PA0 WKUP flag */
82 /**
83 * @}
84 */
85
86 /** @defgroup PWR_LL_EC_GET_FLAG Get Flags Defines
87 * @brief Flags defines which can be used with LL_PWR_ReadReg function
88 * @{
89 */
90 #define LL_PWR_FLAG_AVDO PWR_CSR1_AVDO /*!< Analog voltage detector output on VDDA flag */
91 #define LL_PWR_FLAG_PVDO PWR_CSR1_PVDO /*!< Programmable voltage detect output flag */
92 #define LL_PWR_FLAG_ACTVOS PWR_CSR1_ACTVOS /*!< Current VOS applied for VCORE voltage scaling flag */
93 #define LL_PWR_FLAG_ACTVOSRDY PWR_CSR1_ACTVOSRDY /*!< Ready bit for current actual used VOS for VCORE voltage scaling flag */
94 #if defined (PWR_CSR1_MMCVDO)
95 #define LL_PWR_FLAG_MMCVDO PWR_CSR1_MMCVDO /*!< Voltage detector output on VDDMMC flag */
96 #endif /* PWR_CSR1_MMCVDO */
97
98 #define LL_PWR_FLAG_TEMPH PWR_CR2_TEMPH /*!< Temperature high threshold flag */
99 #define LL_PWR_FLAG_TEMPL PWR_CR2_TEMPL /*!< Temperature low threshold flag */
100 #define LL_PWR_FLAG_VBATH PWR_CR2_VBATH /*!< VBAT high threshold flag */
101 #define LL_PWR_FLAG_VBATL PWR_CR2_VBATL /*!< VBAT low threshold flag */
102 #define LL_PWR_FLAG_BRRDY PWR_CR2_BRRDY /*!< Backup Regulator ready flag */
103
104 #define LL_PWR_FLAG_USBRDY PWR_CR3_USB33RDY /*!< USB supply ready flag */
105 #define LL_PWR_FLAG_SMPSEXTRDY PWR_CR3_SMPSEXTRDY /*!< SMPS External supply ready flag */
106
107 #if defined (PWR_CPUCR_SBF_D2)
108 #define LL_PWR_FLAG_CPU_SBF_D2 PWR_CPUCR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
109 #endif /* PWR_CPUCR_SBF_D2 */
110 #if defined (PWR_CPUCR_SBF_D1)
111 #define LL_PWR_FLAG_CPU_SBF_D1 PWR_CPUCR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
112 #endif /* PWR_CPUCR_SBF_D1 */
113 #define LL_PWR_FLAG_CPU_SBF PWR_CPUCR_SBF /*!< System STANDBY Flag */
114 #define LL_PWR_FLAG_CPU_STOPF PWR_CPUCR_STOPF /*!< STOP Flag */
115 #if defined (DUAL_CORE)
116 #define LL_PWR_FLAG_CPU_HOLD2F PWR_CPUCR_HOLD2F /*!< CPU2 in hold wakeup flag */
117 #endif /* DUAL_CORE */
118
119 #if defined (DUAL_CORE)
120 #define LL_PWR_FLAG_CPU2_SBF_D2 PWR_CPU2CR_SBF_D2 /*!< D2 domain DSTANDBY Flag */
121 #define LL_PWR_FLAG_CPU2_SBF_D1 PWR_CPU2CR_SBF_D1 /*!< D1 domain DSTANDBY Flag */
122 #define LL_PWR_FLAG_CPU2_SBF PWR_CPU2CR_SBF /*!< System STANDBY Flag */
123 #define LL_PWR_FLAG_CPU2_STOPF PWR_CPU2CR_STOPF /*!< STOP Flag */
124 #define LL_PWR_FLAG_CPU2_HOLD1F PWR_CPU2CR_HOLD1F /*!< CPU1 in hold wakeup flag */
125 #endif /* DUAL_CORE */
126
127 #if defined (PWR_CPUCR_PDDS_D2)
128 #define LL_PWR_D3CR_VOSRDY PWR_D3CR_VOSRDY /*!< Voltage scaling ready flag */
129 #else
130 #define LL_PWR_SRDCR_VOSRDY PWR_SRDCR_VOSRDY /*!< Voltage scaling ready flag */
131 #endif /* PWR_CPUCR_PDDS_D2 */
132
133 #define LL_PWR_WKUPFR_WKUPF6 PWR_WKUPFR_WKUPF6 /*!< Wakeup flag on PC1 */
134 #define LL_PWR_WKUPFR_WKUPF5 PWR_WKUPFR_WKUPF5 /*!< Wakeup flag on PI11 */
135 #define LL_PWR_WKUPFR_WKUPF4 PWR_WKUPFR_WKUPF4 /*!< Wakeup flag on PC13 */
136 #define LL_PWR_WKUPFR_WKUPF3 PWR_WKUPFR_WKUPF3 /*!< Wakeup flag on PI8 */
137 #define LL_PWR_WKUPFR_WKUPF2 PWR_WKUPFR_WKUPF2 /*!< Wakeup flag on PA2 */
138 #define LL_PWR_WKUPFR_WKUPF1 PWR_WKUPFR_WKUPF1 /*!< Wakeup flag on PA0 */
139 /**
140 * @}
141 */
142
143 /** @defgroup PWR_LL_EC_MODE_PWR Power mode
144 * @{
145 */
146 #if defined (PWR_CPUCR_PDDS_D2)
147 #define LL_PWR_CPU_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU enters deepsleep */
148 #define LL_PWR_CPU_MODE_D1STANDBY PWR_CPUCR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU enters deepsleep */
149 #else
150 #define LL_PWR_CPU_MODE_CDSTOP 0x00000000U /*!< Enter CD domain to Stop mode when the CPU enters deepsleep */
151 #define LL_PWR_CPU_MODE_CDSTOP2 PWR_CPUCR_RETDS_CD /*!< Enter CD domain to Stop2 mode when the CPU enters deepsleep */
152 #endif /* PWR_CPUCR_PDDS_D2 */
153
154 #if defined (PWR_CPUCR_PDDS_D2)
155 #define LL_PWR_CPU_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU enters deepsleep */
156 #define LL_PWR_CPU_MODE_D2STANDBY PWR_CPUCR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU enters deepsleep */
157 #endif /* PWR_CPUCR_PDDS_D2 */
158
159 #if defined (PWR_CPUCR_PDDS_D2)
160 #define LL_PWR_CPU_MODE_D3RUN PWR_CPUCR_RUN_D3 /*!< Keep system D3 domain in Run mode when the CPU enter deepsleep */
161 #define LL_PWR_CPU_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU enters deepsleep */
162 #define LL_PWR_CPU_MODE_D3STANDBY PWR_CPUCR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU enters deepsleep */
163 #else
164 #define LL_PWR_CPU_MODE_SRDRUN PWR_CPUCR_RUN_SRD /*!< Keep system SRD domain in Run mode when the CPU enter deepsleep */
165 #define LL_PWR_CPU_MODE_SRDSTOP 0x00000000U /*!< Enter SRD domain to Stop mode when the CPU enters deepsleep */
166 #define LL_PWR_CPU_MODE_SRDSTANDBY PWR_CPUCR_PDDS_SRD /*!< Enter SRD domain to Standby mode when the CPU enters deepsleep */
167 #endif /* PWR_CPUCR_PDDS_D2 */
168
169 #if defined (DUAL_CORE)
170 #define LL_PWR_CPU2_MODE_D1STOP 0x00000000U /*!< Enter D1 domain to Stop mode when the CPU2 enters deepsleep */
171 #define LL_PWR_CPU2_MODE_D1STANDBY PWR_CPU2CR_PDDS_D1 /*!< Enter D1 domain to Standby mode when the CPU2 enters deepsleep */
172 #define LL_PWR_CPU2_MODE_D2STOP 0x00000000U /*!< Enter D2 domain to Stop mode when the CPU2 enters deepsleep */
173 #define LL_PWR_CPU2_MODE_D2STANDBY PWR_CPU2CR_PDDS_D2 /*!< Enter D2 domain to Standby mode when the CPU2 enters deepsleep */
174 #define LL_PWR_CPU2_MODE_D3RUN PWR_CPU2CR_RUN_D3 /*!< Keep system D3 domain in RUN mode when the CPU2 enter deepsleep */
175 #define LL_PWR_CPU2_MODE_D3STOP 0x00000000U /*!< Enter D3 domain to Stop mode when the CPU2 enters deepsleep */
176 #define LL_PWR_CPU2_MODE_D3STANDBY PWR_CPU2CR_PDDS_D3 /*!< Enter D3 domain to Standby mode when the CPU2 enter deepsleep */
177 #endif /* DUAL_CORE */
178 /**
179 * @}
180 */
181
182 /** @defgroup PWR_LL_EC_REGU_VOLTAGE Run mode Regulator Voltage Scaling
183 * @{
184 */
185 #if defined (PWR_CPUCR_PDDS_D2)
186 #define LL_PWR_REGU_VOLTAGE_SCALE3 PWR_D3CR_VOS_0 /*!< Select voltage scale 3 */
187 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_1 /*!< Select voltage scale 2 */
188 #define LL_PWR_REGU_VOLTAGE_SCALE1 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 1 */
189 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
190 #else
191 #define LL_PWR_REGU_VOLTAGE_SCALE3 0x00000000U /*!< Select voltage scale 3 */
192 #define LL_PWR_REGU_VOLTAGE_SCALE2 PWR_D3CR_VOS_0 /*!< Select voltage scale 2 */
193 #define LL_PWR_REGU_VOLTAGE_SCALE1 PWR_D3CR_VOS_1 /*!< Select voltage scale 1 */
194 #define LL_PWR_REGU_VOLTAGE_SCALE0 (PWR_D3CR_VOS_0 | PWR_D3CR_VOS_1) /*!< Select voltage scale 0 */
195 #endif /* PWR_CPUCR_PDDS_D2 */
196 /**
197 * @}
198 */
199
200 /** @defgroup PWR_LL_EC_STOP_MODE_REGU_VOLTAGE Stop mode Regulator Voltage Scaling
201 * @{
202 */
203 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE5 PWR_CR1_SVOS_0 /*!< Select voltage scale 5 when system enters STOP mode */
204 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE4 PWR_CR1_SVOS_1 /*!< Select voltage scale 4 when system enters STOP mode */
205 #define LL_PWR_REGU_VOLTAGE_SVOS_SCALE3 (PWR_CR1_SVOS_0 | PWR_CR1_SVOS_1) /*!< Select voltage scale 3 when system enters STOP mode */
206 /**
207 * @}
208 */
209
210 /** @defgroup PWR_LL_EC_REGU_MODE_DS_MODE Regulator Mode In Deep Sleep Mode
211 * @{
212 */
213 #define LL_PWR_REGU_DSMODE_MAIN 0x00000000U /*!< Voltage Regulator in main mode during deepsleep mode */
214 #define LL_PWR_REGU_DSMODE_LOW_POWER PWR_CR1_LPDS /*!< Voltage Regulator in low-power mode during deepsleep mode */
215 /**
216 * @}
217 */
218
219 /** @defgroup PWR_LL_EC_PVDLEVEL Power Digital Voltage Level Detector
220 * @{
221 */
222 #define LL_PWR_PVDLEVEL_0 PWR_CR1_PLS_LEV0 /*!< Voltage threshold detected by PVD 1.95 V */
223 #define LL_PWR_PVDLEVEL_1 PWR_CR1_PLS_LEV1 /*!< Voltage threshold detected by PVD 2.1 V */
224 #define LL_PWR_PVDLEVEL_2 PWR_CR1_PLS_LEV2 /*!< Voltage threshold detected by PVD 2.25 V */
225 #define LL_PWR_PVDLEVEL_3 PWR_CR1_PLS_LEV3 /*!< Voltage threshold detected by PVD 2.4 V */
226 #define LL_PWR_PVDLEVEL_4 PWR_CR1_PLS_LEV4 /*!< Voltage threshold detected by PVD 2.55 V */
227 #define LL_PWR_PVDLEVEL_5 PWR_CR1_PLS_LEV5 /*!< Voltage threshold detected by PVD 2.7 V */
228 #define LL_PWR_PVDLEVEL_6 PWR_CR1_PLS_LEV6 /*!< Voltage threshold detected by PVD 2.85 V */
229 #define LL_PWR_PVDLEVEL_7 PWR_CR1_PLS_LEV7 /*!< External voltage level on PVD_IN pin, compared to internal VREFINT level. */
230 /**
231 * @}
232 */
233
234 /** @defgroup PWR_LL_EC_AVDLEVEL Power Analog Voltage Level Detector
235 * @{
236 */
237 #define LL_PWR_AVDLEVEL_0 PWR_CR1_ALS_LEV0 /*!< Analog Voltage threshold detected by AVD 1.7 V */
238 #define LL_PWR_AVDLEVEL_1 PWR_CR1_ALS_LEV1 /*!< Analog Voltage threshold detected by AVD 2.1 V */
239 #define LL_PWR_AVDLEVEL_2 PWR_CR1_ALS_LEV2 /*!< Analog Voltage threshold detected by AVD 2.5 V */
240 #define LL_PWR_AVDLEVEL_3 PWR_CR1_ALS_LEV3 /*!< Analog Voltage threshold detected by AVD 2.8 V */
241
242 /**
243 * @}
244 */
245
246 /** @defgroup PWR_LL_EC_BATT_CHARG_RESISTOR Battery Charge Resistor
247 * @{
248 */
249 #define LL_PWR_BATT_CHARG_RESISTOR_5K 0x00000000U /*!< Charge the Battery through a 5 kO resistor */
250 #define LL_PWR_BATT_CHARGRESISTOR_1_5K PWR_CR3_VBRS /*!< Charge the Battery through a 1.5 kO resistor */
251 /**
252 * @}
253 */
254
255 /** @defgroup PWR_LL_EC_WAKEUP_PIN Wakeup Pins
256 * @{
257 */
258 #define LL_PWR_WAKEUP_PIN1 PWR_WKUPEPR_WKUPEN1 /*!< Wake-Up pin 1 : PA0 */
259 #define LL_PWR_WAKEUP_PIN2 PWR_WKUPEPR_WKUPEN2 /*!< Wake-Up pin 2 : PA2 */
260 #define LL_PWR_WAKEUP_PIN3 PWR_WKUPEPR_WKUPEN3 /*!< Wake-Up pin 3 : PI8 */
261 #define LL_PWR_WAKEUP_PIN4 PWR_WKUPEPR_WKUPEN4 /*!< Wake-Up pin 4 : PC13 */
262 #define LL_PWR_WAKEUP_PIN5 PWR_WKUPEPR_WKUPEN5 /*!< Wake-Up pin 5 : PI11 */
263 #define LL_PWR_WAKEUP_PIN6 PWR_WKUPEPR_WKUPEN6 /*!< Wake-Up pin 6 : PC1 */
264 /**
265 * @}
266 */
267
268 /** @defgroup PWR_LL_EC_WAKEUP_PIN_PULL Wakeup Pins pull configuration
269 * @{
270 */
271 #define LL_PWR_WAKEUP_PIN_NOPULL 0x00000000UL /*!< Configure Wake-Up pin in no pull */
272 #define LL_PWR_WAKEUP_PIN_PULLUP 0x00000001UL /*!< Configure Wake-Up pin in pull Up */
273 #define LL_PWR_WAKEUP_PIN_PULLDOWN 0x00000002UL /*!< Configure Wake-Up pin in pull Down */
274 /**
275 * @}
276 */
277
278 /** @defgroup PWR_LL_EC_SUPPLY_PWR Power supply source configuration
279 * @{
280 */
281 #define LL_PWR_LDO_SUPPLY PWR_CR3_LDOEN /*!< Core domains are suppplied from the LDO */
282 #if defined (SMPS)
283 #define LL_PWR_DIRECT_SMPS_SUPPLY PWR_CR3_SMPSEN /*!< Core domains are suppplied from the SMPS */
284 #define LL_PWR_SMPS_1V8_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies the LDO which supplies the Core domains */
285 #define LL_PWR_SMPS_2V5_SUPPLIES_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies the LDO which supplies the Core domains */
286 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 1.8V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
287 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN) /*!< The SMPS 2.5V output supplies an external circuits and the LDO. The Core domains are suppplied from the LDO */
288 #define LL_PWR_SMPS_1V8_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_0 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 1.8V output supplies an external source which supplies the Core domains */
289 #define LL_PWR_SMPS_2V5_SUPPLIES_EXT (PWR_CR3_SMPSLEVEL_1 | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_BYPASS) /*!< The SMPS 2.5V output supplies an external source which supplies the Core domains */
290 #endif /* SMPS */
291 #define LL_PWR_EXTERNAL_SOURCE_SUPPLY PWR_CR3_BYPASS /*!< The SMPS and the LDO are Bypassed. The Core domains are supplied from an external source */
292 /**
293 * @}
294 */
295
296 /**
297 * @}
298 */
299 /* Exported macro ------------------------------------------------------------*/
300 /** @defgroup PWR_LL_Exported_Macros PWR Exported Macros
301 * @{
302 */
303
304 /** @defgroup PWR_LL_EM_WRITE_READ Common write and read registers Macros
305 * @{
306 */
307
308 /**
309 * @brief Write a value in PWR register
310 * @param __REG__ Register to be written
311 * @param __VALUE__ Value to be written in the register
312 * @retval None
313 */
314 #define LL_PWR_WriteReg(__REG__, __VALUE__) WRITE_REG(PWR->__REG__, (__VALUE__))
315
316 /**
317 * @brief Read a value in PWR register
318 * @param __REG__ Register to be read
319 * @retval Register value
320 */
321 #define LL_PWR_ReadReg(__REG__) READ_REG(PWR->__REG__)
322 /**
323 * @}
324 */
325
326 /**
327 * @}
328 */
329 /* Exported functions --------------------------------------------------------*/
330 /** @defgroup PWR_LL_Exported_Functions PWR Exported Functions
331 * @{
332 */
333
334 /** @defgroup PWR_LL_EF_Configuration Configuration
335 * @{
336 */
337
338 /**
339 * @brief Set the voltage Regulator mode during deep sleep mode
340 * @rmtoll CR1 LPDS LL_PWR_SetRegulModeDS
341 * @param RegulMode This parameter can be one of the following values:
342 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
343 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
344 * @retval None
345 */
346 __STATIC_INLINE void LL_PWR_SetRegulModeDS(uint32_t RegulMode)
347 {
348 MODIFY_REG(PWR->CR1, PWR_CR1_LPDS, RegulMode);
349 }
350
351 /**
352 * @brief Get the voltage Regulator mode during deep sleep mode
353 * @rmtoll CR1 LPDS LL_PWR_GetRegulModeDS
354 * @retval Returned value can be one of the following values:
355 * @arg @ref LL_PWR_REGU_DSMODE_MAIN
356 * @arg @ref LL_PWR_REGU_DSMODE_LOW_POWER
357 */
358 __STATIC_INLINE uint32_t LL_PWR_GetRegulModeDS(void)
359 {
360 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_LPDS));
361 }
362
363 /**
364 * @brief Enable Power Voltage Detector
365 * @rmtoll CR1 PVDEN LL_PWR_EnablePVD
366 * @retval None
367 */
368 __STATIC_INLINE void LL_PWR_EnablePVD(void)
369 {
370 SET_BIT(PWR->CR1, PWR_CR1_PVDEN);
371 }
372
373 /**
374 * @brief Disable Power Voltage Detector
375 * @rmtoll CR1 PVDEN LL_PWR_DisablePVD
376 * @retval None
377 */
378 __STATIC_INLINE void LL_PWR_DisablePVD(void)
379 {
380 CLEAR_BIT(PWR->CR1, PWR_CR1_PVDEN);
381 }
382
383 /**
384 * @brief Check if Power Voltage Detector is enabled
385 * @rmtoll CR1 PVDEN LL_PWR_IsEnabledPVD
386 * @retval State of bit (1 or 0).
387 */
388 __STATIC_INLINE uint32_t LL_PWR_IsEnabledPVD(void)
389 {
390 return ((READ_BIT(PWR->CR1, PWR_CR1_PVDEN) == (PWR_CR1_PVDEN)) ? 1UL : 0UL);
391 }
392
393 /**
394 * @brief Configure the voltage threshold detected by the Power Voltage Detector
395 * @rmtoll CR1 PLS LL_PWR_SetPVDLevel
396 * @param PVDLevel This parameter can be one of the following values:
397 * @arg @ref LL_PWR_PVDLEVEL_0
398 * @arg @ref LL_PWR_PVDLEVEL_1
399 * @arg @ref LL_PWR_PVDLEVEL_2
400 * @arg @ref LL_PWR_PVDLEVEL_3
401 * @arg @ref LL_PWR_PVDLEVEL_4
402 * @arg @ref LL_PWR_PVDLEVEL_5
403 * @arg @ref LL_PWR_PVDLEVEL_6
404 * @arg @ref LL_PWR_PVDLEVEL_7
405 * @retval None
406 */
407 __STATIC_INLINE void LL_PWR_SetPVDLevel(uint32_t PVDLevel)
408 {
409 MODIFY_REG(PWR->CR1, PWR_CR1_PLS, PVDLevel);
410 }
411
412 /**
413 * @brief Get the voltage threshold detection
414 * @rmtoll CR1 PLS LL_PWR_GetPVDLevel
415 * @retval Returned value can be one of the following values:
416 * @arg @ref LL_PWR_PVDLEVEL_0
417 * @arg @ref LL_PWR_PVDLEVEL_1
418 * @arg @ref LL_PWR_PVDLEVEL_2
419 * @arg @ref LL_PWR_PVDLEVEL_3
420 * @arg @ref LL_PWR_PVDLEVEL_4
421 * @arg @ref LL_PWR_PVDLEVEL_5
422 * @arg @ref LL_PWR_PVDLEVEL_6
423 * @arg @ref LL_PWR_PVDLEVEL_7
424 */
425 __STATIC_INLINE uint32_t LL_PWR_GetPVDLevel(void)
426 {
427 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_PLS));
428 }
429
430 /**
431 * @brief Enable access to the backup domain
432 * @rmtoll CR1 DBP LL_PWR_EnableBkUpAccess
433 * @retval None
434 */
435 __STATIC_INLINE void LL_PWR_EnableBkUpAccess(void)
436 {
437 SET_BIT(PWR->CR1, PWR_CR1_DBP);
438 }
439
440 /**
441 * @brief Disable access to the backup domain
442 * @rmtoll CR1 DBP LL_PWR_DisableBkUpAccess
443 * @retval None
444 */
445 __STATIC_INLINE void LL_PWR_DisableBkUpAccess(void)
446 {
447 CLEAR_BIT(PWR->CR1, PWR_CR1_DBP);
448 }
449
450 /**
451 * @brief Check if the backup domain is enabled
452 * @rmtoll CR1 DBP LL_PWR_IsEnabledBkUpAccess
453 * @retval State of bit (1 or 0).
454 */
455 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpAccess(void)
456 {
457 return ((READ_BIT(PWR->CR1, PWR_CR1_DBP) == (PWR_CR1_DBP)) ? 1UL : 0UL);
458 }
459
460 /**
461 * @brief Enable the Flash Power Down in Stop Mode
462 * @rmtoll CR1 FLPS LL_PWR_EnableFlashPowerDown
463 * @retval None
464 */
465 __STATIC_INLINE void LL_PWR_EnableFlashPowerDown(void)
466 {
467 SET_BIT(PWR->CR1, PWR_CR1_FLPS);
468 }
469
470 /**
471 * @brief Disable the Flash Power Down in Stop Mode
472 * @rmtoll CR1 FLPS LL_PWR_DisableFlashPowerDown
473 * @retval None
474 */
475 __STATIC_INLINE void LL_PWR_DisableFlashPowerDown(void)
476 {
477 CLEAR_BIT(PWR->CR1, PWR_CR1_FLPS);
478 }
479
480 /**
481 * @brief Check if the Flash Power Down in Stop Mode is enabled
482 * @rmtoll CR1 FLPS LL_PWR_IsEnabledFlashPowerDown
483 * @retval State of bit (1 or 0).
484 */
485 __STATIC_INLINE uint32_t LL_PWR_IsEnabledFlashPowerDown(void)
486 {
487 return ((READ_BIT(PWR->CR1, PWR_CR1_FLPS) == (PWR_CR1_FLPS)) ? 1UL : 0UL);
488 }
489
490 #if defined (PWR_CR1_BOOSTE)
491 /**
492 * @brief Enable the Analog Voltage Booster (VDDA)
493 * @rmtoll CR1 BOOSTE LL_PWR_EnableAnalogBooster
494 * @retval None
495 */
496 __STATIC_INLINE void LL_PWR_EnableAnalogBooster(void)
497 {
498 SET_BIT(PWR->CR1, PWR_CR1_BOOSTE);
499 }
500
501 /**
502 * @brief Disable the Analog Voltage Booster (VDDA)
503 * @rmtoll CR1 BOOSTE LL_PWR_DisableAnalogBooster
504 * @retval None
505 */
506 __STATIC_INLINE void LL_PWR_DisableAnalogBooster(void)
507 {
508 CLEAR_BIT(PWR->CR1, PWR_CR1_BOOSTE);
509 }
510
511 /**
512 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
513 * @rmtoll CR1 BOOSTE LL_PWR_IsEnabledAnalogBooster
514 * @retval State of bit (1 or 0).
515 */
516 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogBooster(void)
517 {
518 return ((READ_BIT(PWR->CR1, PWR_CR1_BOOSTE) == (PWR_CR1_BOOSTE)) ? 1UL : 0UL);
519 }
520 #endif /* PWR_CR1_BOOSTE */
521
522 #if defined (PWR_CR1_AVD_READY)
523 /**
524 * @brief Enable the Analog Voltage Ready to isolate the BOOST IP untill VDDA will be ready
525 * @rmtoll CR1 AVD_READY LL_PWR_EnableAnalogVoltageReady
526 * @retval None
527 */
528 __STATIC_INLINE void LL_PWR_EnableAnalogVoltageReady(void)
529 {
530 SET_BIT(PWR->CR1, PWR_CR1_AVD_READY);
531 }
532
533 /**
534 * @brief Disable the Analog Voltage Ready (VDDA)
535 * @rmtoll CR1 AVD_READY LL_PWR_DisableAnalogVoltageReady
536 * @retval None
537 */
538 __STATIC_INLINE void LL_PWR_DisableAnalogVoltageReady(void)
539 {
540 CLEAR_BIT(PWR->CR1, PWR_CR1_AVD_READY);
541 }
542
543 /**
544 * @brief Check if the Analog Voltage Booster (VDDA) is enabled
545 * @rmtoll CR1 AVD_READY LL_PWR_IsEnabledAnalogVoltageReady
546 * @retval State of bit (1 or 0).
547 */
548 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAnalogVoltageReady(void)
549 {
550 return ((READ_BIT(PWR->CR1, PWR_CR1_AVD_READY) == (PWR_CR1_AVD_READY)) ? 1UL : 0UL);
551 }
552 #endif /* PWR_CR1_AVD_READY */
553
554 /**
555 * @brief Set the internal Regulator output voltage in STOP mode
556 * @rmtoll CR1 SVOS LL_PWR_SetStopModeRegulVoltageScaling
557 * @param VoltageScaling This parameter can be one of the following values:
558 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
559 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
560 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
561 * @retval None
562 */
563 __STATIC_INLINE void LL_PWR_SetStopModeRegulVoltageScaling(uint32_t VoltageScaling)
564 {
565 MODIFY_REG(PWR->CR1, PWR_CR1_SVOS, VoltageScaling);
566 }
567
568 /**
569 * @brief Get the internal Regulator output voltage in STOP mode
570 * @rmtoll CR1 SVOS LL_PWR_GetStopModeRegulVoltageScaling
571 * @retval Returned value can be one of the following values:
572 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE3
573 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE4
574 * @arg @ref LL_PWR_REGU_VOLTAGE_SVOS_SCALE5
575 */
576 __STATIC_INLINE uint32_t LL_PWR_GetStopModeRegulVoltageScaling(void)
577 {
578 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_SVOS));
579 }
580
581 /**
582 * @brief Enable Analog Power Voltage Detector
583 * @rmtoll CR1 AVDEN LL_PWR_EnableAVD
584 * @retval None
585 */
586 __STATIC_INLINE void LL_PWR_EnableAVD(void)
587 {
588 SET_BIT(PWR->CR1, PWR_CR1_AVDEN);
589 }
590
591 /**
592 * @brief Disable Analog Power Voltage Detector
593 * @rmtoll CR1 AVDEN LL_PWR_DisableAVD
594 * @retval None
595 */
596 __STATIC_INLINE void LL_PWR_DisableAVD(void)
597 {
598 CLEAR_BIT(PWR->CR1, PWR_CR1_AVDEN);
599 }
600
601 /**
602 * @brief Check if Analog Power Voltage Detector is enabled
603 * @rmtoll CR1 AVDEN LL_PWR_IsEnabledAVD
604 * @retval State of bit (1 or 0).
605 */
606 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAVD(void)
607 {
608 return ((READ_BIT(PWR->CR1, PWR_CR1_AVDEN) == (PWR_CR1_AVDEN)) ? 1UL : 0UL);
609 }
610
611 /**
612 * @brief Configure the voltage threshold to be detected by the Analog Power Voltage Detector
613 * @rmtoll CR1 ALS LL_PWR_SetAVDLevel
614 * @param AVDLevel This parameter can be one of the following values:
615 * @arg @ref LL_PWR_AVDLEVEL_0
616 * @arg @ref LL_PWR_AVDLEVEL_1
617 * @arg @ref LL_PWR_AVDLEVEL_2
618 * @arg @ref LL_PWR_AVDLEVEL_3
619 * @retval None
620 */
621 __STATIC_INLINE void LL_PWR_SetAVDLevel(uint32_t AVDLevel)
622 {
623 MODIFY_REG(PWR->CR1, PWR_CR1_ALS, AVDLevel);
624 }
625
626 /**
627 * @brief Get the Analog Voltage threshold to be detected by the Analog Power Voltage Detector
628 * @rmtoll CR1 ALS LL_PWR_GetAVDLevel
629 * @retval Returned value can be one of the following values:
630 * @arg @ref LL_PWR_AVDLEVEL_0
631 * @arg @ref LL_PWR_AVDLEVEL_1
632 * @arg @ref LL_PWR_AVDLEVEL_2
633 * @arg @ref LL_PWR_AVDLEVEL_3
634 */
635 __STATIC_INLINE uint32_t LL_PWR_GetAVDLevel(void)
636 {
637 return (uint32_t)(READ_BIT(PWR->CR1, PWR_CR1_ALS));
638 }
639
640 #if defined (PWR_CR1_AXIRAM1SO)
641 /**
642 * @brief Enable the AXI RAM1 shut-off in DStop/DStop2 mode
643 * @rmtoll CR1 AXIRAM1SO LL_PWR_EnableAXIRAM1ShutOff
644 * @retval None
645 */
646 __STATIC_INLINE void LL_PWR_EnableAXIRAM1ShutOff(void)
647 {
648 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
649 }
650
651 /**
652 * @brief Disable the AXI RAM1 shut-off in DStop/DStop2 mode
653 * @rmtoll CR1 AXIRAM1SO LL_PWR_DisableAXIRAM1ShutOff
654 * @retval None
655 */
656 __STATIC_INLINE void LL_PWR_DisableAXIRAM1ShutOff(void)
657 {
658 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO);
659 }
660
661 /**
662 * @brief Check if the AXI RAM1 shut-off in DStop/DStop2 mode is enabled
663 * @rmtoll CR1 AXIRAM1SO LL_PWR_IsEnabledAXIRAM1ShutOff
664 * @retval State of bit (1 or 0).
665 */
666 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM1ShutOff(void)
667 {
668 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM1SO) == (PWR_CR1_AXIRAM1SO)) ? 1UL : 0UL);
669 }
670 #endif /* PWR_CR1_AXIRAM1SO */
671
672 #if defined (PWR_CR1_AXIRAM2SO)
673 /**
674 * @brief Enable the AXI RAM2 shut-off in DStop/DStop2 mode
675 * @rmtoll CR1 AXIRAM2SO LL_PWR_EnableAXIRAM2ShutOff
676 * @retval None
677 */
678 __STATIC_INLINE void LL_PWR_EnableAXIRAM2ShutOff(void)
679 {
680 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
681 }
682
683 /**
684 * @brief Disable the AXI RAM2 shut-off in DStop/DStop2 mode
685 * @rmtoll CR1 AXIRAM2SO LL_PWR_DisableAXIRAM2ShutOff
686 * @retval None
687 */
688 __STATIC_INLINE void LL_PWR_DisableAXIRAM2ShutOff(void)
689 {
690 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO);
691 }
692
693 /**
694 * @brief Check if the AXI RAM2 shut-off in DStop/DStop2 mode is enabled
695 * @rmtoll CR1 AXIRAM2SO LL_PWR_IsEnabledAXIRAM2ShutOff
696 * @retval State of bit (1 or 0).
697 */
698 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM2ShutOff(void)
699 {
700 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM2SO) == (PWR_CR1_AXIRAM2SO)) ? 1UL : 0UL);
701 }
702 #endif /* PWR_CR1_AXIRAM2SO */
703
704 #if defined (PWR_CR1_AXIRAM3SO)
705 /**
706 * @brief Enable the AXI RAM3 shut-off in DStop/DStop2 mode
707 * @rmtoll CR1 AXIRAM3SO LL_PWR_EnableAXIRAM3ShutOff
708 * @retval None
709 */
710 __STATIC_INLINE void LL_PWR_EnableAXIRAM3ShutOff(void)
711 {
712 SET_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
713 }
714
715 /**
716 * @brief Disable the AXI RAM3 shut-off in DStop/DStop2 mode
717 * @rmtoll CR1 AXIRAM3SO LL_PWR_DisableAXIRAM3ShutOff
718 * @retval None
719 */
720 __STATIC_INLINE void LL_PWR_DisableAXIRAM3ShutOff(void)
721 {
722 CLEAR_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO);
723 }
724
725 /**
726 * @brief Check if the AXI RAM3 shut-off in DStop/DStop2 mode is enabled
727 * @rmtoll CR1 AXIRAM3SO LL_PWR_IsEnabledAXIRAM3ShutOff
728 * @retval State of bit (1 or 0).
729 */
730 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAXIRAM3ShutOff(void)
731 {
732 return ((READ_BIT(PWR->CR1, PWR_CR1_AXIRAM3SO) == (PWR_CR1_AXIRAM3SO)) ? 1UL : 0UL);
733 }
734 #endif /* PWR_CR1_AXIRAM3SO */
735
736 #if defined (PWR_CR1_AHBRAM1SO)
737 /**
738 * @brief Enable the AHB RAM1 shut-off in DStop/DStop2 mode
739 * @rmtoll CR1 AHBRAM1SO LL_PWR_EnableAHBRAM1ShutOff
740 * @retval None
741 */
742 __STATIC_INLINE void LL_PWR_EnableAHBRAM1ShutOff(void)
743 {
744 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
745 }
746
747 /**
748 * @brief Disable the AHB RAM1 shut-off in DStop/DStop2 mode
749 * @rmtoll CR1 AHBRAM1SO LL_PWR_DisableAHBRAM1ShutOff
750 * @retval None
751 */
752 __STATIC_INLINE void LL_PWR_DisableAHBRAM1ShutOff(void)
753 {
754 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO);
755 }
756
757 /**
758 * @brief Check if the AHB RAM1 shut-off in DStop/DStop2 mode is enabled
759 * @rmtoll CR1 AHBRAM1SO LL_PWR_IsEnabledAHBRAM1ShutOff
760 * @retval State of bit (1 or 0).
761 */
762 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM1ShutOff(void)
763 {
764 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM1SO) == (PWR_CR1_AHBRAM1SO)) ? 1UL : 0UL);
765 }
766 #endif /* PWR_CR1_AHBRAM1SO */
767
768 #if defined (PWR_CR1_AHBRAM2SO)
769 /**
770 * @brief Enable the AHB RAM2 shut-off in DStop/DStop2 mode
771 * @rmtoll CR1 AHBRAM2SO LL_PWR_EnableAHBRAM2ShutOff
772 * @retval None
773 */
774 __STATIC_INLINE void LL_PWR_EnableAHBRAM2ShutOff(void)
775 {
776 SET_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
777 }
778
779 /**
780 * @brief Disable the AHB RAM2 shut-off in DStop/DStop2 mode
781 * @rmtoll CR1 AHBRAM2SO LL_PWR_DisableAHBRAM2ShutOff
782 * @retval None
783 */
784 __STATIC_INLINE void LL_PWR_DisableAHBRAM2ShutOff(void)
785 {
786 CLEAR_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO);
787 }
788
789 /**
790 * @brief Check if the AHB RAM2 shut-off in DStop/DStop2 mode is enabled
791 * @rmtoll CR1 AHBRAM2SO LL_PWR_IsEnabledAHBRAM2ShutOff
792 * @retval State of bit (1 or 0).
793 */
794 __STATIC_INLINE uint32_t LL_PWR_IsEnabledAHBRAM2ShutOff(void)
795 {
796 return ((READ_BIT(PWR->CR1, PWR_CR1_AHBRAM2SO) == (PWR_CR1_AHBRAM2SO)) ? 1UL : 0UL);
797 }
798 #endif /* PWR_CR1_AHBRAM2SO */
799
800 #if defined (PWR_CR1_ITCMSO)
801 /**
802 * @brief Enable the ITCM shut-off in DStop/DStop2 mode
803 * @rmtoll CR1 ITCMSO LL_PWR_EnableITCMSOShutOff
804 * @retval None
805 */
806 __STATIC_INLINE void LL_PWR_EnableITCMSOShutOff(void)
807 {
808 SET_BIT(PWR->CR1, PWR_CR1_ITCMSO);
809 }
810
811 /**
812 * @brief Disable the ITCM shut-off in DStop/DStop2 mode
813 * @rmtoll CR1 ITCMSO LL_PWR_DisableITCMSOShutOff
814 * @retval None
815 */
816 __STATIC_INLINE void LL_PWR_DisableITCMSOShutOff(void)
817 {
818 CLEAR_BIT(PWR->CR1, PWR_CR1_ITCMSO);
819 }
820
821 /**
822 * @brief Check if the ITCM shut-off in DStop/DStop2 mode is enabled
823 * @rmtoll CR1 ITCMSO LL_PWR_IsEnabledITCMShutOff
824 * @retval State of bit (1 or 0).
825 */
826 __STATIC_INLINE uint32_t LL_PWR_IsEnabledITCMShutOff(void)
827 {
828 return ((READ_BIT(PWR->CR1, PWR_CR1_ITCMSO) == (PWR_CR1_ITCMSO)) ? 1UL : 0UL);
829 }
830 #endif /* PWR_CR1_ITCMSO */
831
832 #if defined (PWR_CR1_HSITFSO)
833 /**
834 * @brief Enable the USB and FDCAN shut-off in DStop/DStop2 mode
835 * @rmtoll CR1 HSITFSO LL_PWR_EnableHSITFShutOff
836 * @retval None
837 */
838 __STATIC_INLINE void LL_PWR_EnableHSITFShutOff(void)
839 {
840 SET_BIT(PWR->CR1, PWR_CR1_HSITFSO);
841 }
842
843 /**
844 * @brief Disable the USB and FDCAN shut-off in DStop/DStop2 mode
845 * @rmtoll CR1 HSITFSO LL_PWR_DisableHSITFShutOff
846 * @retval None
847 */
848 __STATIC_INLINE void LL_PWR_DisableHSITFShutOff(void)
849 {
850 CLEAR_BIT(PWR->CR1, PWR_CR1_HSITFSO);
851 }
852
853 /**
854 * @brief Check if the USB and FDCAN shut-off in DStop/DStop2 mode is enabled
855 * @rmtoll CR1 HSITFSO LL_PWR_IsEnabledHSITFShutOff
856 * @retval State of bit (1 or 0).
857 */
858 __STATIC_INLINE uint32_t LL_PWR_IsEnabledHSITFShutOff(void)
859 {
860 return ((READ_BIT(PWR->CR1, PWR_CR1_HSITFSO) == (PWR_CR1_HSITFSO)) ? 1UL : 0UL);
861 }
862 #endif /* PWR_CR1_HSITFSO */
863
864 #if defined (PWR_CR1_SRDRAMSO)
865 /**
866 * @brief Enable the SRD AHB RAM shut-off in DStop/DStop2 mode
867 * @rmtoll CR1 SRDRAMSO LL_PWR_EnableSRDRAMShutOff
868 * @retval None
869 */
870 __STATIC_INLINE void LL_PWR_EnableSRDRAMShutOff(void)
871 {
872 SET_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
873 }
874
875 /**
876 * @brief Disable the SRD AHB RAM shut-off in DStop/DStop2 mode
877 * @rmtoll CR1 SRDRAMSO LL_PWR_DisableSRDRAMShutOff
878 * @retval None
879 */
880 __STATIC_INLINE void LL_PWR_DisableSRDRAMShutOff(void)
881 {
882 CLEAR_BIT(PWR->CR1, PWR_CR1_SRDRAMSO);
883 }
884
885 /**
886 * @brief Check if the SRD AHB RAM shut-off in DStop/DStop2 mode is enabled
887 * @rmtoll CR1 SRDRAMSO LL_PWR_IsEnabledSRDRAMShutOff
888 * @retval State of bit (1 or 0).
889 */
890 __STATIC_INLINE uint32_t LL_PWR_IsEnabledSRDRAMShutOff(void)
891 {
892 return ((READ_BIT(PWR->CR1, PWR_CR1_SRDRAMSO) == (PWR_CR1_SRDRAMSO)) ? 1UL : 0UL);
893 }
894 #endif /* PWR_CR1_SRDRAMSO */
895
896 /**
897 * @brief Enable Backup Regulator
898 * @rmtoll CR2 BREN LL_PWR_EnableBkUpRegulator
899 * @note When set, the Backup Regulator (used to maintain backup SRAM content in Standby and
900 * VBAT modes) is enabled. If BRE is reset, the backup Regulator is switched off. The backup
901 * SRAM can still be used but its content will be lost in the Standby and VBAT modes. Once set,
902 * the application must wait that the Backup Regulator Ready flag (BRR) is set to indicate that
903 * the data written into the RAM will be maintained in the Standby and VBAT modes.
904 * @retval None
905 */
906 __STATIC_INLINE void LL_PWR_EnableBkUpRegulator(void)
907 {
908 SET_BIT(PWR->CR2, PWR_CR2_BREN);
909 }
910
911 /**
912 * @brief Disable Backup Regulator
913 * @rmtoll CR2 BREN LL_PWR_DisableBkUpRegulator
914 * @retval None
915 */
916 __STATIC_INLINE void LL_PWR_DisableBkUpRegulator(void)
917 {
918 CLEAR_BIT(PWR->CR2, PWR_CR2_BREN);
919 }
920
921 /**
922 * @brief Check if the backup Regulator is enabled
923 * @rmtoll CR2 BREN LL_PWR_IsEnabledBkUpRegulator
924 * @retval State of bit (1 or 0).
925 */
926 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBkUpRegulator(void)
927 {
928 return ((READ_BIT(PWR->CR2, PWR_CR2_BREN) == (PWR_CR2_BREN)) ? 1UL : 0UL);
929 }
930
931 /**
932 * @brief Enable VBAT and Temperature monitoring
933 * @rmtoll CR2 MONEN LL_PWR_EnableMonitoring
934 * @retval None
935 */
936 __STATIC_INLINE void LL_PWR_EnableMonitoring(void)
937 {
938 SET_BIT(PWR->CR2, PWR_CR2_MONEN);
939 }
940
941 /**
942 * @brief Disable VBAT and Temperature monitoring
943 * @rmtoll CR2 MONEN LL_PWR_DisableMonitoring
944 * @retval None
945 */
946 __STATIC_INLINE void LL_PWR_DisableMonitoring(void)
947 {
948 CLEAR_BIT(PWR->CR2, PWR_CR2_MONEN);
949 }
950
951 /**
952 * @brief Check if the VBAT and Temperature monitoring is enabled
953 * @rmtoll CR2 MONEN LL_PWR_IsEnabledMonitoring
954 * @retval State of bit (1 or 0).
955 */
956 __STATIC_INLINE uint32_t LL_PWR_IsEnabledMonitoring(void)
957 {
958 return ((READ_BIT(PWR->CR2, PWR_CR2_MONEN) == (PWR_CR2_MONEN)) ? 1UL : 0UL);
959 }
960
961 #if defined (SMPS)
962 /**
963 * @brief Configure the PWR supply
964 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
965 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
966 * @rmtoll CR3 SMPSEN LL_PWR_ConfigSupply
967 * @rmtoll CR3 SMPSEXTHP LL_PWR_ConfigSupply
968 * @rmtoll CR3 SMPSLEVEL LL_PWR_ConfigSupply
969 * @param SupplySource This parameter can be one of the following values:
970 * @arg @ref LL_PWR_LDO_SUPPLY
971 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
972 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
973 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
974 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
975 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
976 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
977 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
978 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
979 * @retval None
980 */
981 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
982 {
983 /* Set the power supply configuration */
984 MODIFY_REG(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
985 }
986 #else
987 /**
988 * @brief Configure the PWR supply
989 * @rmtoll CR3 BYPASS LL_PWR_ConfigSupply
990 * @rmtoll CR3 LDOEN LL_PWR_ConfigSupply
991 * @rmtoll CR3 SCUEN LL_PWR_ConfigSupply
992 * @param SupplySource This parameter can be one of the following values:
993 * @arg @ref LL_PWR_LDO_SUPPLY
994 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
995 * @retval None
996 */
997 __STATIC_INLINE void LL_PWR_ConfigSupply(uint32_t SupplySource)
998 {
999 /* Set the power supply configuration */
1000 MODIFY_REG(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS), SupplySource);
1001 }
1002 #endif /* defined (SMPS) */
1003
1004 #if defined (SMPS)
1005 /**
1006 * @brief Get the PWR supply
1007 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1008 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1009 * @rmtoll CR3 SMPSEN LL_PWR_GetSupply
1010 * @rmtoll CR3 SMPSEXTHP LL_PWR_GetSupply
1011 * @rmtoll CR3 SMPSLEVEL LL_PWR_GetSupply
1012 * @retval Returned value can be one of the following values:
1013 * @arg @ref LL_PWR_LDO_SUPPLY
1014 * @arg @ref LL_PWR_DIRECT_SMPS_SUPPLY
1015 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_LDO
1016 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_LDO
1017 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT_AND_LDO
1018 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT_AND_LDO
1019 * @arg @ref LL_PWR_SMPS_1V8_SUPPLIES_EXT
1020 * @arg @ref LL_PWR_SMPS_2V5_SUPPLIES_EXT
1021 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1022 */
1023 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1024 {
1025 /* Get the power supply configuration */
1026 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SMPSLEVEL | PWR_CR3_SMPSEXTHP | PWR_CR3_SMPSEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1027 }
1028 #else
1029 /**
1030 * @brief Get the PWR supply
1031 * @rmtoll CR3 BYPASS LL_PWR_GetSupply
1032 * @rmtoll CR3 LDOEN LL_PWR_GetSupply
1033 * @rmtoll CR3 SCUEN LL_PWR_GetSupply
1034 * @retval Returned value can be one of the following values:
1035 * @arg @ref LL_PWR_LDO_SUPPLY
1036 * @arg @ref LL_PWR_EXTERNAL_SOURCE_SUPPLY
1037 */
1038 __STATIC_INLINE uint32_t LL_PWR_GetSupply(void)
1039 {
1040 /* Get the power supply configuration */
1041 return(uint32_t)(READ_BIT(PWR->CR3, (PWR_CR3_SCUEN | PWR_CR3_LDOEN | PWR_CR3_BYPASS)));
1042 }
1043 #endif /* defined (SMPS) */
1044
1045 /**
1046 * @brief Enable battery charging
1047 * @rmtoll CR3 VBE LL_PWR_EnableBatteryCharging
1048 * @retval None
1049 */
1050 __STATIC_INLINE void LL_PWR_EnableBatteryCharging(void)
1051 {
1052 SET_BIT(PWR->CR3, PWR_CR3_VBE);
1053 }
1054
1055 /**
1056 * @brief Disable battery charging
1057 * @rmtoll CR3 VBE LL_PWR_DisableBatteryCharging
1058 * @retval None
1059 */
1060 __STATIC_INLINE void LL_PWR_DisableBatteryCharging(void)
1061 {
1062 CLEAR_BIT(PWR->CR3, PWR_CR3_VBE);
1063 }
1064
1065 /**
1066 * @brief Check if battery charging is enabled
1067 * @rmtoll CR3 VBE LL_PWR_IsEnabledBatteryCharging
1068 * @retval State of bit (1 or 0).
1069 */
1070 __STATIC_INLINE uint32_t LL_PWR_IsEnabledBatteryCharging(void)
1071 {
1072 return ((READ_BIT(PWR->CR3, PWR_CR3_VBE) == (PWR_CR3_VBE)) ? 1UL : 0UL);
1073 }
1074
1075 /**
1076 * @brief Set the Battery charge resistor impedance
1077 * @rmtoll CR3 VBRS LL_PWR_SetBattChargResistor
1078 * @param Resistor This parameter can be one of the following values:
1079 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1080 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1081 * @retval None
1082 */
1083 __STATIC_INLINE void LL_PWR_SetBattChargResistor(uint32_t Resistor)
1084 {
1085 MODIFY_REG(PWR->CR3, PWR_CR3_VBRS, Resistor);
1086 }
1087
1088 /**
1089 * @brief Get the Battery charge resistor impedance
1090 * @rmtoll CR3 VBRS LL_PWR_GetBattChargResistor
1091 * @retval Returned value can be one of the following values:
1092 * @arg @ref LL_PWR_BATT_CHARG_RESISTOR_5K
1093 * @arg @ref LL_PWR_BATT_CHARGRESISTOR_1_5K
1094 */
1095 __STATIC_INLINE uint32_t LL_PWR_GetBattChargResistor(void)
1096 {
1097 return (uint32_t)(READ_BIT(PWR->CR3, PWR_CR3_VBRS));
1098 }
1099
1100 /**
1101 * @brief Enable the USB regulator
1102 * @rmtoll CR3 USBREGEN LL_PWR_EnableUSBReg
1103 * @retval None
1104 */
1105 __STATIC_INLINE void LL_PWR_EnableUSBReg(void)
1106 {
1107 SET_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1108 }
1109
1110 /**
1111 * @brief Disable the USB regulator
1112 * @rmtoll CR3 USBREGEN LL_PWR_DisableUSBReg
1113 * @retval None
1114 */
1115 __STATIC_INLINE void LL_PWR_DisableUSBReg(void)
1116 {
1117 CLEAR_BIT(PWR->CR3, PWR_CR3_USBREGEN);
1118 }
1119
1120 /**
1121 * @brief Check if the USB regulator is enabled
1122 * @rmtoll CR3 USBREGEN LL_PWR_IsEnabledUSBReg
1123 * @retval State of bit (1 or 0).
1124 */
1125 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBReg(void)
1126 {
1127 return ((READ_BIT(PWR->CR3, PWR_CR3_USBREGEN) == (PWR_CR3_USBREGEN)) ? 1UL : 0UL);
1128 }
1129
1130 /**
1131 * @brief Enable the USB voltage detector
1132 * @rmtoll CR3 USB33DEN LL_PWR_EnableUSBVoltageDetector
1133 * @retval None
1134 */
1135 __STATIC_INLINE void LL_PWR_EnableUSBVoltageDetector(void)
1136 {
1137 SET_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1138 }
1139
1140 /**
1141 * @brief Disable the USB voltage detector
1142 * @rmtoll CR3 USB33DEN LL_PWR_DisableUSBVoltageDetector
1143 * @retval None
1144 */
1145 __STATIC_INLINE void LL_PWR_DisableUSBVoltageDetector(void)
1146 {
1147 CLEAR_BIT(PWR->CR3, PWR_CR3_USB33DEN);
1148 }
1149
1150 /**
1151 * @brief Check if the USB voltage detector is enabled
1152 * @rmtoll CR3 USB33DEN LL_PWR_IsEnabledUSBVoltageDetector
1153 * @retval State of bit (1 or 0).
1154 */
1155 __STATIC_INLINE uint32_t LL_PWR_IsEnabledUSBVoltageDetector(void)
1156 {
1157 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33DEN) == (PWR_CR3_USB33DEN)) ? 1UL : 0UL);
1158 }
1159
1160 #if defined (PWR_CPUCR_PDDS_D2)
1161 /**
1162 * @brief Set the D1 domain Power Down mode when the CPU enters deepsleep
1163 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_SetD1PowerMode
1164 * @param PDMode This parameter can be one of the following values:
1165 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1166 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1167 * @retval None
1168 */
1169 __STATIC_INLINE void LL_PWR_CPU_SetD1PowerMode(uint32_t PDMode)
1170 {
1171 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D1, PDMode);
1172 }
1173 #else
1174 /**
1175 * @brief Set the CPU domain Power Down mode when the CPU enters deepsleep
1176 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_SetCDPowerMode
1177 * @param PDMode This parameter can be one of the following values:
1178 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1179 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1180 * @retval None
1181 */
1182 __STATIC_INLINE void LL_PWR_CPU_SetCDPowerMode(uint32_t PDMode)
1183 {
1184 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_RETDS_CD, PDMode);
1185 }
1186 #endif /* PWR_CPUCR_PDDS_D2 */
1187
1188 #if defined (DUAL_CORE)
1189 /**
1190 * @brief Set the D1 domain Power Down mode when the CPU2 enters deepsleep
1191 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_SetD1PowerMode
1192 * @param PDMode This parameter can be one of the following values:
1193 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1194 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1195 * @retval None
1196 */
1197 __STATIC_INLINE void LL_PWR_CPU2_SetD1PowerMode(uint32_t PDMode)
1198 {
1199 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1, PDMode);
1200 }
1201 #endif /* DUAL_CORE */
1202
1203 #if defined (PWR_CPUCR_PDDS_D2)
1204 /**
1205 * @brief Get the D1 Domain Power Down mode when the CPU enters deepsleep
1206 * @rmtoll CPUCR PDDS_D1 LL_PWR_CPU_GetD1PowerMode
1207 * @retval Returned value can be one of the following values:
1208 * @arg @ref LL_PWR_CPU_MODE_D1STOP
1209 * @arg @ref LL_PWR_CPU_MODE_D1STANDBY
1210 */
1211 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD1PowerMode(void)
1212 {
1213 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D1));
1214 }
1215 #else
1216 /**
1217 * @brief Get the CD Domain Power Down mode when the CPU enters deepsleep
1218 * @rmtoll CPUCR RETDS_CD LL_PWR_CPU_GetCDPowerMode
1219 * @retval Returned value can be one of the following values:
1220 * @arg @ref LL_PWR_CPU_MODE_CDSTOP
1221 * @arg @ref LL_PWR_CPU_MODE_CDSTOP2
1222 */
1223 __STATIC_INLINE uint32_t LL_PWR_CPU_GetCDPowerMode(void)
1224 {
1225 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_RETDS_CD));
1226 }
1227 #endif /* PWR_CPUCR_PDDS_D2 */
1228
1229 #if defined (DUAL_CORE)
1230 /**
1231 * @brief Get the D1 Domain Power Down mode when the CPU2 enters deepsleep
1232 * @rmtoll CPU2CR PDDS_D1 LL_PWR_CPU2_GetD1PowerMode
1233 * @retval Returned value can be one of the following values:
1234 * @arg @ref LL_PWR_CPU2_MODE_D1STOP
1235 * @arg @ref LL_PWR_CPU2_MODE_D1STANDBY
1236 */
1237 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD1PowerMode(void)
1238 {
1239 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D1));
1240 }
1241 #endif /* DUAL_CORE */
1242
1243 #if defined (PWR_CPUCR_PDDS_D2)
1244 /**
1245 * @brief Set the D2 domain Power Down mode when the CPU enters deepsleep
1246 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_SetD2PowerMode
1247 * @param PDMode This parameter can be one of the following values:
1248 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1249 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1250 * @retval None
1251 */
1252 __STATIC_INLINE void LL_PWR_CPU_SetD2PowerMode(uint32_t PDMode)
1253 {
1254 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D2, PDMode);
1255 }
1256 #endif /* PWR_CPUCR_PDDS_D2 */
1257
1258 #if defined (DUAL_CORE)
1259 /**
1260 * @brief Set the D2 domain Power Down mode when the CPU2 enters deepsleep
1261 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_SetD2PowerMode
1262 * @param PDMode This parameter can be one of the following values:
1263 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1264 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1265 * @retval None
1266 */
1267 __STATIC_INLINE void LL_PWR_CPU2_SetD2PowerMode(uint32_t PDMode)
1268 {
1269 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2, PDMode);
1270 }
1271 #endif /* DUAL_CORE */
1272
1273 #if defined (PWR_CPUCR_PDDS_D2)
1274 /**
1275 * @brief Get the D2 Domain Power Down mode when the CPU enters deepsleep
1276 * @rmtoll CPUCR PDDS_D2 LL_PWR_CPU_GetD2PowerMode
1277 * @retval Returned value can be one of the following values:
1278 * @arg @ref LL_PWR_CPU_MODE_D2STOP
1279 * @arg @ref LL_PWR_CPU_MODE_D2STANDBY
1280 */
1281 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD2PowerMode(void)
1282 {
1283 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D2));
1284 }
1285 #endif /* PWR_CPUCR_PDDS_D2 */
1286
1287 #if defined (DUAL_CORE)
1288 /**
1289 * @brief Get the D2 Domain Power Down mode when the CPU2 enters deepsleep
1290 * @rmtoll CPU2CR PDDS_D2 LL_PWR_CPU2_GetD2PowerMode
1291 * @retval Returned value can be one of the following values:
1292 * @arg @ref LL_PWR_CPU2_MODE_D2STOP
1293 * @arg @ref LL_PWR_CPU2_MODE_D2STANDBY
1294 */
1295 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD2PowerMode(void)
1296 {
1297 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D2));
1298 }
1299 #endif /* DUAL_CORE */
1300
1301 #if defined (PWR_CPUCR_PDDS_D2)
1302 /**
1303 * @brief Set the D3 domain Power Down mode when the CPU enters deepsleep
1304 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_SetD3PowerMode
1305 * @param PDMode This parameter can be one of the following values:
1306 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1307 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1308 * @retval None
1309 */
1310 __STATIC_INLINE void LL_PWR_CPU_SetD3PowerMode(uint32_t PDMode)
1311 {
1312 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_D3 , PDMode);
1313 }
1314 #else
1315 /**
1316 * @brief Set the SRD domain Power Down mode when the CPU enters deepsleep
1317 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_SetSRDPowerMode
1318 * @param PDMode This parameter can be one of the following values:
1319 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1320 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1321 * @retval None
1322 */
1323 __STATIC_INLINE void LL_PWR_CPU_SetSRDPowerMode(uint32_t PDMode)
1324 {
1325 MODIFY_REG(PWR->CPUCR, PWR_CPUCR_PDDS_SRD , PDMode);
1326 }
1327 #endif /* PWR_CPUCR_PDDS_D2 */
1328
1329 #if defined (DUAL_CORE)
1330 /**
1331 * @brief Set the D3 domain Power Down mode when the CPU2 enters deepsleep
1332 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_SetD3PowerMode
1333 * @param PDMode This parameter can be one of the following values:
1334 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1335 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1336 * @retval None
1337 */
1338 __STATIC_INLINE void LL_PWR_CPU2_SetD3PowerMode(uint32_t PDMode)
1339 {
1340 MODIFY_REG(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3, PDMode);
1341 }
1342 #endif /* DUAL_CORE */
1343
1344 #if defined (PWR_CPUCR_PDDS_D3)
1345 /**
1346 * @brief Get the D3 Domain Power Down mode when the CPU enters deepsleep
1347 * @rmtoll CPUCR PDDS_D3 LL_PWR_CPU_GetD3PowerMode
1348 * @retval Returned value can be one of the following values:
1349 * @arg @ref LL_PWR_CPU_MODE_D3STOP
1350 * @arg @ref LL_PWR_CPU_MODE_D3STANDBY
1351 */
1352 __STATIC_INLINE uint32_t LL_PWR_CPU_GetD3PowerMode(void)
1353 {
1354 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_D3));
1355 }
1356 #else
1357 /**
1358 * @brief Get the SRD Domain Power Down mode when the CPU enters deepsleep
1359 * @rmtoll CPUCR PDDS_SRD LL_PWR_CPU_GetSRDPowerMode
1360 * @retval Returned value can be one of the following values:
1361 * @arg @ref LL_PWR_CPU_MODE_SRDSTOP
1362 * @arg @ref LL_PWR_CPU_MODE_SRDSTANDBY
1363 */
1364 __STATIC_INLINE uint32_t LL_PWR_CPU_GetSRDPowerMode(void)
1365 {
1366 return (uint32_t)(READ_BIT(PWR->CPUCR, PWR_CPUCR_PDDS_SRD));
1367 }
1368 #endif /* PWR_CPUCR_PDDS_D3 */
1369
1370 #if defined (DUAL_CORE)
1371 /**
1372 * @brief Get the D3 Domain Power Down mode when the CPU2 enters deepsleep
1373 * @rmtoll CPU2CR PDDS_D3 LL_PWR_CPU2_GetD3PowerMode
1374 * @retval Returned value can be one of the following values:
1375 * @arg @ref LL_PWR_CPU2_MODE_D3STOP
1376 * @arg @ref LL_PWR_CPU2_MODE_D3STANDBY
1377 */
1378 __STATIC_INLINE uint32_t LL_PWR_CPU2_GetD3PowerMode(void)
1379 {
1380 return (uint32_t)(READ_BIT(PWR->CPU2CR, PWR_CPU2CR_PDDS_D3));
1381 }
1382 #endif /* DUAL_CORE */
1383
1384 #if defined (DUAL_CORE)
1385 /**
1386 * @brief Hold the CPU1 and allocated peripherals when exiting from STOP mode
1387 * @rmtoll CPU2CR HOLD1 LL_PWR_HoldCPU1
1388 * @retval None
1389 */
1390 __STATIC_INLINE void LL_PWR_HoldCPU1(void)
1391 {
1392 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1393 }
1394
1395 /**
1396 * @brief Release the CPU1 and allocated peripherals
1397 * @rmtoll CPU2CR HOLD1 LL_PWR_ReleaseCPU1
1398 * @retval None
1399 */
1400 __STATIC_INLINE void LL_PWR_ReleaseCPU1(void)
1401 {
1402 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1);
1403 }
1404
1405 /**
1406 * @brief Ckeck if the CPU1 and allocated peripherals are held
1407 * @rmtoll CPU2CR HOLD1 LL_PWR_IsCPU1Held
1408 * @retval State of bit (1 or 0).
1409 */
1410 __STATIC_INLINE uint32_t LL_PWR_IsCPU1Held(void)
1411 {
1412 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1) == (PWR_CPU2CR_HOLD1)) ? 1UL : 0UL);
1413 }
1414
1415 /**
1416 * @brief Hold the CPU2 and allocated peripherals when exiting from STOP mode
1417 * @rmtoll CPUCR HOLD2 LL_PWR_HoldCPU2
1418 * @retval None
1419 */
1420 __STATIC_INLINE void LL_PWR_HoldCPU2(void)
1421 {
1422 SET_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1423 }
1424
1425 /**
1426 * @brief Release the CPU2 and allocated peripherals
1427 * @rmtoll CPUCR HOLD2 LL_PWR_ReleaseCPU2
1428 * @retval None
1429 */
1430 __STATIC_INLINE void LL_PWR_ReleaseCPU2(void)
1431 {
1432 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2);
1433 }
1434
1435 /**
1436 * @brief Ckeck if the CPU2 and allocated peripherals are held
1437 * @rmtoll CPUCR HOLD2 LL_PWR_IsCPU2Held
1438 * @retval State of bit (1 or 0).
1439 */
1440 __STATIC_INLINE uint32_t LL_PWR_IsCPU2Held(void)
1441 {
1442 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2) == (PWR_CPUCR_HOLD2)) ? 1UL : 0UL);
1443 }
1444 #endif /* DUAL_CORE */
1445
1446 #if defined (PWR_CPUCR_PDDS_D2)
1447 /**
1448 * @brief D3 domain remains in Run mode regardless of CPU subsystem modes
1449 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_EnableD3RunInLowPowerMode
1450 * @retval None
1451 */
1452 __STATIC_INLINE void LL_PWR_CPU_EnableD3RunInLowPowerMode(void)
1453 {
1454 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1455 }
1456 #else
1457 /**
1458 * @brief SRD domain remains in Run mode regardless of CPU subsystem modes
1459 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_EnableSRDRunInLowPowerMode
1460 * @retval None
1461 */
1462 __STATIC_INLINE void LL_PWR_CPU_EnableSRDRunInLowPowerMode(void)
1463 {
1464 SET_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1465 }
1466 #endif /* PWR_CPUCR_PDDS_D2 */
1467
1468 #if defined (DUAL_CORE)
1469 /**
1470 * @brief D3 domain remains in Run mode regardless of CPU2 subsystem modes
1471 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_EnableD3RunInLowPowerMode
1472 * @retval None
1473 */
1474 __STATIC_INLINE void LL_PWR_CPU2_EnableD3RunInLowPowerMode(void)
1475 {
1476 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1477 }
1478 #endif /* DUAL_CORE */
1479
1480 #if defined (PWR_CPUCR_PDDS_D2)
1481 /**
1482 * @brief D3 domain follows CPU subsystem modes
1483 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_DisableD3RunInLowPowerMode
1484 * @retval None
1485 */
1486 __STATIC_INLINE void LL_PWR_CPU_DisableD3RunInLowPowerMode(void)
1487 {
1488 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3);
1489 }
1490 #else
1491 /**
1492 * @brief SRD domain follows CPU subsystem modes
1493 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_DisableSRDRunInLowPowerMode
1494 * @retval None
1495 */
1496 __STATIC_INLINE void LL_PWR_CPU_DisableSRDRunInLowPowerMode(void)
1497 {
1498 CLEAR_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD);
1499 }
1500 #endif /* PWR_CPUCR_PDDS_D2 */
1501
1502 #if defined (DUAL_CORE)
1503 /**
1504 * @brief D3 domain follows CPU2 subsystem modes
1505 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_DisableD3RunInLowPowerMode
1506 * @retval None
1507 */
1508 __STATIC_INLINE void LL_PWR_CPU2_DisableD3RunInLowPowerMode(void)
1509 {
1510 CLEAR_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3);
1511 }
1512 #endif /* DUAL_CORE */
1513
1514 #if defined (PWR_CPUCR_PDDS_D2)
1515 /**
1516 * @brief Check if D3 is kept in Run mode when CPU enters low power mode
1517 * @rmtoll CPUCR RUN_D3 LL_PWR_CPU_IsEnabledD3RunInLowPowerMode
1518 * @retval State of bit (1 or 0).
1519 */
1520 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledD3RunInLowPowerMode(void)
1521 {
1522 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_D3) == (PWR_CPUCR_RUN_D3)) ? 1UL : 0UL);
1523 }
1524 #else
1525 /**
1526 * @brief Check if SRD is kept in Run mode when CPU enters low power mode
1527 * @rmtoll CPUCR RUN_SRD LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode
1528 * @retval State of bit (1 or 0).
1529 */
1530 __STATIC_INLINE uint32_t LL_PWR_CPU_IsEnabledSRDRunInLowPowerMode(void)
1531 {
1532 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_RUN_SRD) == (PWR_CPUCR_RUN_SRD)) ? 1UL : 0UL);
1533 }
1534 #endif /* PWR_CPUCR_PDDS_D2 */
1535
1536 #if defined (DUAL_CORE)
1537 /**
1538 * @brief Check if D3 is kept in Run mode when CPU2 enters low power mode
1539 * @rmtoll CPU2CR RUN_D3 LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode
1540 * @retval State of bit (1 or 0).
1541 */
1542 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsEnabledD3RunInLowPowerMode(void)
1543 {
1544 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_RUN_D3) == (PWR_CPU2CR_RUN_D3)) ? 1UL : 0UL);
1545 }
1546 #endif /* DUAL_CORE */
1547
1548 /**
1549 * @brief Set the main internal Regulator output voltage
1550 * @rmtoll D3CR VOS LL_PWR_SetRegulVoltageScaling
1551 * @param VoltageScaling This parameter can be one of the following values:
1552 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1553 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1554 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1555 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1556 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, VOS0
1557 * is applied when PWR_D3CR_VOS[1:0] = 0b11 and SYSCFG_PWRCR_ODEN = 0b1.
1558 * @retval None
1559 */
1560 __STATIC_INLINE void LL_PWR_SetRegulVoltageScaling(uint32_t VoltageScaling)
1561 {
1562 #if defined (PWR_CPUCR_PDDS_D2)
1563 MODIFY_REG(PWR->D3CR, PWR_D3CR_VOS, VoltageScaling);
1564 #else
1565 MODIFY_REG(PWR->SRDCR, PWR_SRDCR_VOS, VoltageScaling);
1566 #endif /* PWR_CPUCR_PDDS_D2 */
1567 }
1568
1569 /**
1570 * @brief Get the main internal Regulator output voltage
1571 * @rmtoll D3CR VOS LL_PWR_GetRegulVoltageScaling
1572 * @note For all H7 lines except STM32H7Axxx and STM32H7Bxxx lines, checking
1573 * VOS0 need the check of PWR_D3CR_VOS[1:0] field and SYSCFG_PWRCR_ODEN bit.
1574 * @retval Returned value can be one of the following values:
1575 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE0
1576 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE1
1577 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE2
1578 * @arg @ref LL_PWR_REGU_VOLTAGE_SCALE3
1579 */
1580 __STATIC_INLINE uint32_t LL_PWR_GetRegulVoltageScaling(void)
1581 {
1582 #if defined (PWR_CPUCR_PDDS_D2)
1583 return (uint32_t)(READ_BIT(PWR->D3CR, PWR_D3CR_VOS));
1584 #else
1585 return (uint32_t)(READ_BIT(PWR->SRDCR, PWR_SRDCR_VOS));
1586 #endif /* PWR_CPUCR_PDDS_D2 */
1587 }
1588
1589 /**
1590 * @brief Enable the WakeUp PINx functionality
1591 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_EnableWakeUpPin\n
1592 * WKUPEPR WKUPEN2 LL_PWR_EnableWakeUpPin\n
1593 * WKUPEPR WKUPEN3 LL_PWR_EnableWakeUpPin\n
1594 * WKUPEPR WKUPEN4 LL_PWR_EnableWakeUpPin\n
1595 * WKUPEPR WKUPEN5 LL_PWR_EnableWakeUpPin\n
1596 * WKUPEPR WKUPEN6 LL_PWR_EnableWakeUpPin
1597 * @param WakeUpPin This parameter can be one of the following values:
1598 * @arg @ref LL_PWR_WAKEUP_PIN1
1599 * @arg @ref LL_PWR_WAKEUP_PIN2
1600 * @arg @ref LL_PWR_WAKEUP_PIN3
1601 * @arg @ref LL_PWR_WAKEUP_PIN4
1602 * @arg @ref LL_PWR_WAKEUP_PIN5
1603 * @arg @ref LL_PWR_WAKEUP_PIN6
1604 * @retval None
1605 */
1606 __STATIC_INLINE void LL_PWR_EnableWakeUpPin(uint32_t WakeUpPin)
1607 {
1608 SET_BIT(PWR->WKUPEPR, WakeUpPin);
1609 }
1610
1611 /**
1612 * @brief Disable the WakeUp PINx functionality
1613 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_DisableWakeUpPin\n
1614 * WKUPEPR WKUPEN2 LL_PWR_DisableWakeUpPin\n
1615 * WKUPEPR WKUPEN3 LL_PWR_DisableWakeUpPin\n
1616 * WKUPEPR WKUPEN4 LL_PWR_DisableWakeUpPin\n
1617 * WKUPEPR WKUPEN5 LL_PWR_DisableWakeUpPin\n
1618 * WKUPEPR WKUPEN6 LL_PWR_DisableWakeUpPin
1619 * @param WakeUpPin This parameter can be one of the following values:
1620 * @arg @ref LL_PWR_WAKEUP_PIN1
1621 * @arg @ref LL_PWR_WAKEUP_PIN2
1622 * @arg @ref LL_PWR_WAKEUP_PIN3
1623 * @arg @ref LL_PWR_WAKEUP_PIN4
1624 * @arg @ref LL_PWR_WAKEUP_PIN5
1625 * @arg @ref LL_PWR_WAKEUP_PIN6
1626 * @retval None
1627 */
1628 __STATIC_INLINE void LL_PWR_DisableWakeUpPin(uint32_t WakeUpPin)
1629 {
1630 CLEAR_BIT(PWR->WKUPEPR, WakeUpPin);
1631 }
1632
1633 /**
1634 * @brief Check if the WakeUp PINx functionality is enabled
1635 * @rmtoll WKUPEPR WKUPEN1 LL_PWR_IsEnabledWakeUpPin\n
1636 * WKUPEPR WKUPEN2 LL_PWR_IsEnabledWakeUpPin\n
1637 * WKUPEPR WKUPEN3 LL_PWR_IsEnabledWakeUpPin\n
1638 * WKUPEPR WKUPEN4 LL_PWR_IsEnabledWakeUpPin\n
1639 * WKUPEPR WKUPEN5 LL_PWR_IsEnabledWakeUpPin\n
1640 * WKUPEPR WKUPEN6 LL_PWR_IsEnabledWakeUpPin
1641 * @param WakeUpPin This parameter can be one of the following values:
1642 * @arg @ref LL_PWR_WAKEUP_PIN1
1643 * @arg @ref LL_PWR_WAKEUP_PIN2
1644 * @arg @ref LL_PWR_WAKEUP_PIN3
1645 * @arg @ref LL_PWR_WAKEUP_PIN4
1646 * @arg @ref LL_PWR_WAKEUP_PIN5
1647 * @arg @ref LL_PWR_WAKEUP_PIN6
1648 * @retval State of bit (1 or 0).
1649 */
1650 __STATIC_INLINE uint32_t LL_PWR_IsEnabledWakeUpPin(uint32_t WakeUpPin)
1651 {
1652 return ((READ_BIT(PWR->WKUPEPR, WakeUpPin) == (WakeUpPin)) ? 1UL : 0UL);
1653 }
1654
1655 /**
1656 * @brief Set the Wake-Up pin polarity low for the event detection
1657 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityLow\n
1658 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityLow\n
1659 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityLow\n
1660 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityLow\n
1661 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityLow\n
1662 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityLow
1663 * @param WakeUpPin This parameter can be one of the following values:
1664 * @arg @ref LL_PWR_WAKEUP_PIN1
1665 * @arg @ref LL_PWR_WAKEUP_PIN2
1666 * @arg @ref LL_PWR_WAKEUP_PIN3
1667 * @arg @ref LL_PWR_WAKEUP_PIN4
1668 * @arg @ref LL_PWR_WAKEUP_PIN5
1669 * @arg @ref LL_PWR_WAKEUP_PIN6
1670 * @retval None
1671 */
1672 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityLow(uint32_t WakeUpPin)
1673 {
1674 SET_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1675 }
1676
1677 /**
1678 * @brief Set the Wake-Up pin polarity high for the event detection
1679 * @rmtoll WKUPEPR WKUPP1 LL_PWR_SetWakeUpPinPolarityHigh\n
1680 * WKUPEPR WKUPP2 LL_PWR_SetWakeUpPinPolarityHigh\n
1681 * WKUPEPR WKUPP3 LL_PWR_SetWakeUpPinPolarityHigh\n
1682 * WKUPEPR WKUPP4 LL_PWR_SetWakeUpPinPolarityHigh\n
1683 * WKUPEPR WKUPP5 LL_PWR_SetWakeUpPinPolarityHigh\n
1684 * WKUPEPR WKUPP6 LL_PWR_SetWakeUpPinPolarityHigh
1685 * @param WakeUpPin This parameter can be one of the following values:
1686 * @arg @ref LL_PWR_WAKEUP_PIN1
1687 * @arg @ref LL_PWR_WAKEUP_PIN2
1688 * @arg @ref LL_PWR_WAKEUP_PIN3
1689 * @arg @ref LL_PWR_WAKEUP_PIN4
1690 * @arg @ref LL_PWR_WAKEUP_PIN5
1691 * @arg @ref LL_PWR_WAKEUP_PIN6
1692 * @retval None
1693 */
1694 __STATIC_INLINE void LL_PWR_SetWakeUpPinPolarityHigh(uint32_t WakeUpPin)
1695 {
1696 CLEAR_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos));
1697 }
1698
1699 /**
1700 * @brief Get the Wake-Up pin polarity for the event detection
1701 * @rmtoll WKUPEPR WKUPP1 LL_PWR_IsWakeUpPinPolarityLow\n
1702 * WKUPEPR WKUPP2 LL_PWR_IsWakeUpPinPolarityLow\n
1703 * WKUPEPR WKUPP3 LL_PWR_IsWakeUpPinPolarityLow\n
1704 * WKUPEPR WKUPP4 LL_PWR_IsWakeUpPinPolarityLow\n
1705 * WKUPEPR WKUPP5 LL_PWR_IsWakeUpPinPolarityLow\n
1706 * WKUPEPR WKUPP6 LL_PWR_IsWakeUpPinPolarityLow
1707 * @param WakeUpPin This parameter can be one of the following values:
1708 * @arg @ref LL_PWR_WAKEUP_PIN1
1709 * @arg @ref LL_PWR_WAKEUP_PIN2
1710 * @arg @ref LL_PWR_WAKEUP_PIN3
1711 * @arg @ref LL_PWR_WAKEUP_PIN4
1712 * @arg @ref LL_PWR_WAKEUP_PIN5
1713 * @arg @ref LL_PWR_WAKEUP_PIN6
1714 * @retval State of bit (1 or 0).
1715 */
1716 __STATIC_INLINE uint32_t LL_PWR_IsWakeUpPinPolarityLow(uint32_t WakeUpPin)
1717 {
1718 return ((READ_BIT(PWR->WKUPEPR, (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) == (WakeUpPin << PWR_WKUPEPR_WKUPP1_Pos)) ? 1UL : 0UL);
1719 }
1720
1721 /**
1722 * @brief Set the Wake-Up pin Pull None
1723 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullNone\n
1724 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullNone\n
1725 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullNone\n
1726 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullNone\n
1727 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullNone\n
1728 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullNone
1729 * @param WakeUpPin This parameter can be one of the following values:
1730 * @arg @ref LL_PWR_WAKEUP_PIN1
1731 * @arg @ref LL_PWR_WAKEUP_PIN2
1732 * @arg @ref LL_PWR_WAKEUP_PIN3
1733 * @arg @ref LL_PWR_WAKEUP_PIN4
1734 * @arg @ref LL_PWR_WAKEUP_PIN5
1735 * @arg @ref LL_PWR_WAKEUP_PIN6
1736 * @retval None
1737 */
1738 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullNone(uint32_t WakeUpPin)
1739 {
1740 MODIFY_REG(PWR->WKUPEPR, \
1741 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1742 (LL_PWR_WAKEUP_PIN_NOPULL << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1743 }
1744
1745 /**
1746 * @brief Set the Wake-Up pin Pull Up
1747 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullUp\n
1748 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullUp\n
1749 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullUp\n
1750 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullUp\n
1751 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullUp\n
1752 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullUp
1753 * @param WakeUpPin This parameter can be one of the following values:
1754 * @arg @ref LL_PWR_WAKEUP_PIN1
1755 * @arg @ref LL_PWR_WAKEUP_PIN2
1756 * @arg @ref LL_PWR_WAKEUP_PIN3
1757 * @arg @ref LL_PWR_WAKEUP_PIN4
1758 * @arg @ref LL_PWR_WAKEUP_PIN5
1759 * @arg @ref LL_PWR_WAKEUP_PIN6
1760 * @retval None
1761 */
1762 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullUp(uint32_t WakeUpPin)
1763 {
1764 MODIFY_REG(PWR->WKUPEPR, \
1765 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1766 (LL_PWR_WAKEUP_PIN_PULLUP << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1767 }
1768
1769 /**
1770 * @brief Set the Wake-Up pin Pull Down
1771 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_SetWakeUpPinPullDown\n
1772 * WKUPEPR WKUPPUPD2 LL_PWR_SetWakeUpPinPullDown\n
1773 * WKUPEPR WKUPPUPD3 LL_PWR_SetWakeUpPinPullDown\n
1774 * WKUPEPR WKUPPUPD4 LL_PWR_SetWakeUpPinPullDown\n
1775 * WKUPEPR WKUPPUPD5 LL_PWR_SetWakeUpPinPullDown\n
1776 * WKUPEPR WKUPPUPD6 LL_PWR_SetWakeUpPinPullDown
1777 * @param WakeUpPin This parameter can be one of the following values:
1778 * @arg @ref LL_PWR_WAKEUP_PIN1
1779 * @arg @ref LL_PWR_WAKEUP_PIN2
1780 * @arg @ref LL_PWR_WAKEUP_PIN3
1781 * @arg @ref LL_PWR_WAKEUP_PIN4
1782 * @arg @ref LL_PWR_WAKEUP_PIN5
1783 * @arg @ref LL_PWR_WAKEUP_PIN6
1784 * @retval None
1785 */
1786 __STATIC_INLINE void LL_PWR_SetWakeUpPinPullDown(uint32_t WakeUpPin)
1787 {
1788 MODIFY_REG(PWR->WKUPEPR, \
1789 (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)), \
1790 (LL_PWR_WAKEUP_PIN_PULLDOWN << ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1791 }
1792
1793 /**
1794 * @brief Get the Wake-Up pin pull
1795 * @rmtoll WKUPEPR WKUPPUPD1 LL_PWR_GetWakeUpPinPull\n
1796 * WKUPEPR WKUPPUPD2 LL_PWR_GetWakeUpPinPull\n
1797 * WKUPEPR WKUPPUPD3 LL_PWR_GetWakeUpPinPull\n
1798 * WKUPEPR WKUPPUPD4 LL_PWR_GetWakeUpPinPull\n
1799 * WKUPEPR WKUPPUPD5 LL_PWR_GetWakeUpPinPull\n
1800 * WKUPEPR WKUPPUPD6 LL_PWR_GetWakeUpPinPull
1801 * @param WakeUpPin This parameter can be one of the following values:
1802 * @arg @ref LL_PWR_WAKEUP_PIN1
1803 * @arg @ref LL_PWR_WAKEUP_PIN2
1804 * @arg @ref LL_PWR_WAKEUP_PIN3
1805 * @arg @ref LL_PWR_WAKEUP_PIN4
1806 * @arg @ref LL_PWR_WAKEUP_PIN5
1807 * @arg @ref LL_PWR_WAKEUP_PIN6
1808 * @retval Returned value can be one of the following values:
1809 * @arg @ref LL_PWR_WAKEUP_PIN_NOPULL
1810 * @arg @ref LL_PWR_WAKEUP_PIN_PULLUP
1811 * @arg @ref LL_PWR_WAKEUP_PIN_PULLDOWN
1812 */
1813 __STATIC_INLINE uint32_t LL_PWR_GetWakeUpPinPull(uint32_t WakeUpPin)
1814 {
1815 register uint32_t regValue = READ_BIT(PWR->WKUPEPR, (PWR_WKUPEPR_WKUPPUPD1 << ((LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin)) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK)));
1816
1817 return (uint32_t)(regValue >> ((PWR_WKUPEPR_WKUPPUPD1_Pos + (LL_PWR_WAKEUP_PINS_PULL_SHIFT_OFFSET * POSITION_VAL(WakeUpPin))) & LL_PWR_WAKEUP_PINS_MAX_SHIFT_MASK));
1818 }
1819
1820 /**
1821 * @}
1822 */
1823
1824 /** @defgroup PWR_LL_EF_FLAG_Management FLAG_Management
1825 * @{
1826 */
1827
1828 /**
1829 * @brief Indicate whether VDD voltage is below the selected PVD threshold
1830 * @rmtoll CSR1 PVDO LL_PWR_IsActiveFlag_PVDO
1831 * @retval State of bit (1 or 0).
1832 */
1833 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_PVDO(void)
1834 {
1835 return ((READ_BIT(PWR->CSR1, PWR_CSR1_PVDO) == (PWR_CSR1_PVDO)) ? 1UL : 0UL);
1836 }
1837
1838 /**
1839 * @brief Indicate whether the voltage level is ready for current actual used VOS
1840 * @rmtoll CSR1 ACTVOSRDY LL_PWR_IsActiveFlag_ACTVOS
1841 * @retval State of bit (1 or 0).
1842 */
1843 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_ACTVOS(void)
1844 {
1845 return ((READ_BIT(PWR->CSR1, PWR_CSR1_ACTVOSRDY) == (PWR_CSR1_ACTVOSRDY)) ? 1UL : 0UL);
1846 }
1847
1848 /**
1849 * @brief Indicate whether VDDA voltage is below the selected AVD threshold
1850 * @rmtoll CSR1 AVDO LL_PWR_IsActiveFlag_AVDO
1851 * @retval State of bit (1 or 0).
1852 */
1853 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_AVDO(void)
1854 {
1855 return ((READ_BIT(PWR->CSR1, PWR_CSR1_AVDO) == (PWR_CSR1_AVDO)) ? 1UL : 0UL);
1856 }
1857
1858 #if defined (PWR_CSR1_MMCVDO)
1859 /**
1860 * @brief Indicate whether VDDMMC voltage is below 1V2
1861 * @rmtoll CSR1 MMCVDO LL_PWR_IsActiveFlag_MMCVDO
1862 * @retval State of bit (1 or 0).
1863 */
1864 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_MMCVDO(void)
1865 {
1866 return ((READ_BIT(PWR->CSR1, PWR_CSR1_MMCVDO) == (PWR_CSR1_MMCVDO)) ? 1UL : 0UL);
1867 }
1868 #endif /* PWR_CSR1_MMCVDO */
1869
1870 /**
1871 * @brief Get Backup Regulator ready Flag
1872 * @rmtoll CR2 BRRDY LL_PWR_IsActiveFlag_BRR
1873 * @retval State of bit (1 or 0).
1874 */
1875 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_BRR(void)
1876 {
1877 return ((READ_BIT(PWR->CR2, PWR_CR2_BRRDY) == (PWR_CR2_BRRDY)) ? 1UL : 0UL);
1878 }
1879
1880 /**
1881 * @brief Indicate whether the VBAT level is above or below low threshold
1882 * @rmtoll CR2 VBATL LL_PWR_IsActiveFlag_VBATL
1883 * @retval State of bit (1 or 0).
1884 */
1885 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATL(void)
1886 {
1887 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATL) == (PWR_CR2_VBATL)) ? 1UL : 0UL);
1888 }
1889
1890 /**
1891 * @brief Indicate whether the VBAT level is above or below high threshold
1892 * @rmtoll CR2 VBATH LL_PWR_IsActiveFlag_VBATH
1893 * @retval State of bit (1 or 0).
1894 */
1895 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VBATH(void)
1896 {
1897 return ((READ_BIT(PWR->CR2, PWR_CR2_VBATH) == (PWR_CR2_VBATH)) ? 1UL : 0UL);
1898 }
1899
1900 /**
1901 * @brief Indicate whether the CPU temperature level is above or below low threshold
1902 * @rmtoll CR2 TEMPL LL_PWR_IsActiveFlag_TEMPL
1903 * @retval State of bit (1 or 0).
1904 */
1905 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPL(void)
1906 {
1907 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPL) == (PWR_CR2_TEMPL)) ? 1UL : 0UL);
1908 }
1909
1910 /**
1911 * @brief Indicate whether the CPU temperature level is above or below high threshold
1912 * @rmtoll CR2 TEMPH LL_PWR_IsActiveFlag_TEMPH
1913 * @retval State of bit (1 or 0).
1914 */
1915 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_TEMPH(void)
1916 {
1917 return ((READ_BIT(PWR->CR2, PWR_CR2_TEMPH) == (PWR_CR2_TEMPH)) ? 1UL : 0UL);
1918 }
1919
1920 #if defined (SMPS)
1921 /**
1922 * @brief Indicate whether the SMPS external supply is ready or not
1923 * @rmtoll CR3 SMPSEXTRDY LL_PWR_IsActiveFlag_SMPSEXT
1924 * @retval State of bit (1 or 0).
1925 */
1926 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_SMPSEXT(void)
1927 {
1928 return ((READ_BIT(PWR->CR3, PWR_CR3_SMPSEXTRDY) == (PWR_CR3_SMPSEXTRDY)) ? 1UL : 0UL);
1929 }
1930 #endif /* SMPS */
1931
1932 /**
1933 * @brief Indicate whether the USB supply is ready or not
1934 * @rmtoll CR3 USBRDY LL_PWR_IsActiveFlag_USB
1935 * @retval State of bit (1 or 0).
1936 */
1937 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_USB(void)
1938 {
1939 return ((READ_BIT(PWR->CR3, PWR_CR3_USB33RDY) == (PWR_CR3_USB33RDY)) ? 1UL : 0UL);
1940 }
1941
1942 #if defined (DUAL_CORE)
1943 /**
1944 * @brief Get HOLD2 Flag
1945 * @rmtoll CPUCR HOLD2F LL_PWR_IsActiveFlag_HOLD2
1946 * @retval State of bit (1 or 0).
1947 */
1948 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD2(void)
1949 {
1950 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_HOLD2F) == (PWR_CPUCR_HOLD2F)) ? 1UL : 0UL);
1951 }
1952
1953 /**
1954 * @brief Get HOLD1 Flag
1955 * @rmtoll CPU2CR HOLD1F LL_PWR_IsActiveFlag_HOLD1
1956 * @retval State of bit (1 or 0).
1957 */
1958 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_HOLD1(void)
1959 {
1960 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_HOLD1F) == (PWR_CPU2CR_HOLD1F)) ? 1UL : 0UL);
1961 }
1962 #endif /* DUAL_CORE */
1963
1964 /**
1965 * @brief Get CPU System Stop Flag
1966 * @rmtoll CPUCR STOPF LL_PWR_CPU_IsActiveFlag_STOP
1967 * @retval State of bit (1 or 0).
1968 */
1969 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_STOP(void)
1970 {
1971 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_STOPF) == (PWR_CPUCR_STOPF)) ? 1UL : 0UL);
1972 }
1973
1974 #if defined (DUAL_CORE)
1975 /**
1976 * @brief Get CPU2 System Stop Flag
1977 * @rmtoll CPU2CR STOPF LL_PWR_CPU2_IsActiveFlag_STOP
1978 * @retval State of bit (1 or 0).
1979 */
1980 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_STOP(void)
1981 {
1982 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_STOPF) == (PWR_CPU2CR_STOPF)) ? 1UL : 0UL);
1983 }
1984 #endif /* DUAL_CORE */
1985
1986 /**
1987 * @brief Get CPU System Standby Flag
1988 * @rmtoll CPUCR SBF LL_PWR_CPU_IsActiveFlag_SB
1989 * @retval State of bit (1 or 0).
1990 */
1991 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB(void)
1992 {
1993 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF) == (PWR_CPUCR_SBF)) ? 1UL : 0UL);
1994 }
1995
1996 #if defined (DUAL_CORE)
1997 /**
1998 * @brief Get CPU2 System Standby Flag
1999 * @rmtoll CPU2CR SBF LL_PWR_CPU2_IsActiveFlag_SB
2000 * @retval State of bit (1 or 0).
2001 */
2002 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB(void)
2003 {
2004 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF) == (PWR_CPU2CR_SBF)) ? 1UL : 0UL);
2005 }
2006 #endif /* DUAL_CORE */
2007
2008 #if defined (PWR_CPUCR_SBF_D1)
2009 /**
2010 * @brief Get CPU D1 Domain Standby Flag
2011 * @rmtoll CPUCR SBF_D1 LL_PWR_CPU_IsActiveFlag_SB_D1
2012 * @retval State of bit (1 or 0).
2013 */
2014 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D1(void)
2015 {
2016 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D1) == (PWR_CPUCR_SBF_D1)) ? 1UL : 0UL);
2017 }
2018 #endif /* PWR_CPUCR_SBF_D1 */
2019
2020 #if defined (DUAL_CORE)
2021 /**
2022 * @brief Get CPU2 D1 Domain Standby Flag
2023 * @rmtoll CPU2CR SBF_D1 LL_PWR_CPU2_IsActiveFlag_SB_D1
2024 * @retval State of bit (1 or 0).
2025 */
2026 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D1(void)
2027 {
2028 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D1) == (PWR_CPU2CR_SBF_D1)) ? 1UL : 0UL);
2029 }
2030 #endif /* DUAL_CORE */
2031
2032 #if defined (PWR_CPUCR_SBF_D2)
2033 /**
2034 * @brief Get CPU D2 Domain Standby Flag
2035 * @rmtoll CPUCR SBF_D2 LL_PWR_CPU_IsActiveFlag_SB_D2
2036 * @retval State of bit (1 or 0).
2037 */
2038 __STATIC_INLINE uint32_t LL_PWR_CPU_IsActiveFlag_SB_D2(void)
2039 {
2040 return ((READ_BIT(PWR->CPUCR, PWR_CPUCR_SBF_D2) == (PWR_CPUCR_SBF_D2)) ? 1UL : 0UL);
2041 }
2042 #endif /* PWR_CPUCR_SBF_D2 */
2043
2044 #if defined (DUAL_CORE)
2045 /**
2046 * @brief Get CPU2 D2 Domain Standby Flag
2047 * @rmtoll CPU2CR SBF_D2 LL_PWR_CPU2_IsActiveFlag_SB_D2
2048 * @retval State of bit (1 or 0).
2049 */
2050 __STATIC_INLINE uint32_t LL_PWR_CPU2_IsActiveFlag_SB_D2(void)
2051 {
2052 return ((READ_BIT(PWR->CPU2CR, PWR_CPU2CR_SBF_D2) == (PWR_CPU2CR_SBF_D2)) ? 1UL : 0UL);
2053 }
2054 #endif /* DUAL_CORE */
2055
2056
2057 /**
2058 * @brief Indicate whether the Regulator is ready in the selected voltage range
2059 * or if its output voltage is still changing to the required voltage level
2060 * @rmtoll D3CR VOSRDY LL_PWR_IsActiveFlag_VOS
2061 * @retval State of bit (1 or 0).
2062 */
2063 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_VOS(void)
2064 {
2065 #if defined (PWR_CPUCR_PDDS_D2)
2066 return ((READ_BIT(PWR->D3CR, PWR_D3CR_VOSRDY) == (PWR_D3CR_VOSRDY)) ? 1UL : 0UL);
2067 #else
2068 return ((READ_BIT(PWR->SRDCR, PWR_SRDCR_VOSRDY) == (PWR_SRDCR_VOSRDY)) ? 1UL : 0UL);
2069 #endif /* PWR_CPUCR_PDDS_D2 */
2070 }
2071
2072 /**
2073 * @brief Get Wake-up Flag 6
2074 * @rmtoll WKUPFR WKUPF6 LL_PWR_IsActiveFlag_WU6
2075 * @retval State of bit (1 or 0).
2076 */
2077 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU6(void)
2078 {
2079 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF6) == (PWR_WKUPFR_WKUPF6)) ? 1UL : 0UL);
2080 }
2081
2082 /**
2083 * @brief Get Wake-up Flag 5
2084 * @rmtoll WKUPFR WKUPF5 LL_PWR_IsActiveFlag_WU5
2085 * @retval State of bit (1 or 0).
2086 */
2087 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU5(void)
2088 {
2089 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF5) == (PWR_WKUPFR_WKUPF5)) ? 1UL : 0UL);
2090 }
2091
2092 /**
2093 * @brief Get Wake-up Flag 4
2094 * @rmtoll WKUPFR WKUPF4 LL_PWR_IsActiveFlag_WU4
2095 * @retval State of bit (1 or 0).
2096 */
2097 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU4(void)
2098 {
2099 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF4) == (PWR_WKUPFR_WKUPF4)) ? 1UL : 0UL);
2100 }
2101
2102 /**
2103 * @brief Get Wake-up Flag 3
2104 * @rmtoll WKUPFR WKUPF3 LL_PWR_IsActiveFlag_WU3
2105 * @retval State of bit (1 or 0).
2106 */
2107 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU3(void)
2108 {
2109 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF3) == (PWR_WKUPFR_WKUPF3)) ? 1UL : 0UL);
2110 }
2111
2112 /**
2113 * @brief Get Wake-up Flag 2
2114 * @rmtoll WKUPFR WKUPF2 LL_PWR_IsActiveFlag_WU2
2115 * @retval State of bit (1 or 0).
2116 */
2117 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU2(void)
2118 {
2119 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF2) == (PWR_WKUPFR_WKUPF2)) ? 1UL : 0UL);
2120 }
2121
2122 /**
2123 * @brief Get Wake-up Flag 1
2124 * @rmtoll WKUPFR WKUPF1 LL_PWR_IsActiveFlag_WU1
2125 * @retval State of bit (1 or 0).
2126 */
2127 __STATIC_INLINE uint32_t LL_PWR_IsActiveFlag_WU1(void)
2128 {
2129 return ((READ_BIT(PWR->WKUPFR, PWR_WKUPFR_WKUPF1) == (PWR_WKUPFR_WKUPF1)) ? 1UL : 0UL);
2130 }
2131
2132 /**
2133 * @brief Clear CPU STANDBY, STOP and HOLD flags
2134 * @rmtoll CPUCR CSSF LL_PWR_ClearFlag_CPU
2135 * @retval None
2136 */
2137 __STATIC_INLINE void LL_PWR_ClearFlag_CPU(void)
2138 {
2139 SET_BIT(PWR->CPUCR, PWR_CPUCR_CSSF);
2140 }
2141
2142 #if defined (DUAL_CORE)
2143 /**
2144 * @brief Clear CPU2 STANDBY, STOP and HOLD flags
2145 * @rmtoll CPU2CR CSSF LL_PWR_ClearFlag_CPU2
2146 * @retval None
2147 */
2148 __STATIC_INLINE void LL_PWR_ClearFlag_CPU2(void)
2149 {
2150 SET_BIT(PWR->CPU2CR, PWR_CPU2CR_CSSF);
2151 }
2152 #endif /* DUAL_CORE */
2153
2154 /**
2155 * @brief Clear Wake-up Flag 6
2156 * @rmtoll WKUPCR WKUPC6 LL_PWR_ClearFlag_WU6
2157 * @retval None
2158 */
2159 __STATIC_INLINE void LL_PWR_ClearFlag_WU6(void)
2160 {
2161 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC6);
2162 }
2163
2164 /**
2165 * @brief Clear Wake-up Flag 5
2166 * @rmtoll WKUPCR WKUPC5 LL_PWR_ClearFlag_WU5
2167 * @retval None
2168 */
2169 __STATIC_INLINE void LL_PWR_ClearFlag_WU5(void)
2170 {
2171 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC5);
2172 }
2173
2174 /**
2175 * @brief Clear Wake-up Flag 4
2176 * @rmtoll WKUPCR WKUPC4 LL_PWR_ClearFlag_WU4
2177 * @retval None
2178 */
2179 __STATIC_INLINE void LL_PWR_ClearFlag_WU4(void)
2180 {
2181 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC4);
2182 }
2183
2184 /**
2185 * @brief Clear Wake-up Flag 3
2186 * @rmtoll WKUPCR WKUPC3 LL_PWR_ClearFlag_WU3
2187 * @retval None
2188 */
2189 __STATIC_INLINE void LL_PWR_ClearFlag_WU3(void)
2190 {
2191 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC3);
2192 }
2193
2194 /**
2195 * @brief Clear Wake-up Flag 2
2196 * @rmtoll WKUPCR WKUPC2 LL_PWR_ClearFlag_WU2
2197 * @retval None
2198 */
2199 __STATIC_INLINE void LL_PWR_ClearFlag_WU2(void)
2200 {
2201 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC2);
2202 }
2203
2204 /**
2205 * @brief Clear Wake-up Flag 1
2206 * @rmtoll WKUPCR WKUPC1 LL_PWR_ClearFlag_WU1
2207 * @retval None
2208 */
2209 __STATIC_INLINE void LL_PWR_ClearFlag_WU1(void)
2210 {
2211 WRITE_REG(PWR->WKUPCR, PWR_WKUPCR_WKUPC1);
2212 }
2213
2214 #if defined (USE_FULL_LL_DRIVER)
2215 /** @defgroup PWR_LL_EF_Init De-initialization function
2216 * @{
2217 */
2218 ErrorStatus LL_PWR_DeInit(void);
2219 /**
2220 * @}
2221 */
2222 #endif /* defined (USE_FULL_LL_DRIVER) */
2223
2224
2225 /**
2226 * @}
2227 */
2228
2229 /**
2230 * @}
2231 */
2232
2233 /**
2234 * @}
2235 */
2236
2237 #endif /* defined (PWR) */
2238
2239 /**
2240 * @}
2241 */
2242
2243 #ifdef __cplusplus
2244 }
2245 #endif
2246
2247 #endif /* STM32H7xx_LL_PWR_H */
2248
2249 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/
INAV: Navigation-enabled flight control software