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Merge maintenance-8.x.x fixes into master
[inav.git] / lib / main / STM32H7 / Drivers / STM32H7xx_HAL_Driver / Inc / stm32h7xx_ll_rcc.h
blobbd700dc2b8c97ed39477bc22a40338142121d279
1 /**
2 ******************************************************************************
3 * @file stm32h7xx_ll_rcc.h
4 * @author MCD Application Team
5 * @brief Header file of RCC LL module.
6 ******************************************************************************
7 * @attention
8 *
9 * Copyright (c) 2017 STMicroelectronics.
10 * All rights reserved.
11 *
12 * This software is licensed under terms that can be found in the LICENSE file in
13 * the root directory of this software component.
14 * If no LICENSE file comes with this software, it is provided AS-IS.
15 ******************************************************************************
16 */
17
18 /* Define to prevent recursive inclusion -------------------------------------*/
19 #ifndef STM32H7xx_LL_RCC_H
20 #define STM32H7xx_LL_RCC_H
21
22 #ifdef __cplusplus
23 extern "C" {
24 #endif
25
26 /* Includes ------------------------------------------------------------------*/
27 #include "stm32h7xx.h"
28 #include <math.h>
29
30 /** @addtogroup STM32H7xx_LL_Driver
31 * @{
32 */
33
34 #if defined(RCC)
35
36 /** @defgroup RCC_LL RCC
37 * @{
38 */
39
40 /* Private types -------------------------------------------------------------*/
41 /* Private variables ---------------------------------------------------------*/
42 /** @defgroup RCC_LL_Private_Variables RCC Private Variables
43 * @{
44 */
45 extern const uint8_t LL_RCC_PrescTable[16];
46
47 /**
48 * @}
49 */
50 /* Private constants ---------------------------------------------------------*/
51 /* Private macros ------------------------------------------------------------*/
52 /** @defgroup RCC_LL_Private_Macros RCC Private Macros
53 * @{
54 */
55 #if !defined(UNUSED)
56 #define UNUSED(x) ((void)(x))
57 #endif
58
59 /* 32 24 16 8 0
60 --------------------------------------------------------
61 | Mask | ClkSource | Bit | Register |
62 | | Config | Position | Offset |
63 --------------------------------------------------------*/
64
65 #if defined(RCC_VER_2_0)
66 /* Clock source register offset Vs CDCCIPR register */
67 #define CDCCIP 0x0UL
68 #define CDCCIP1 0x4UL
69 #define CDCCIP2 0x8UL
70 #define SRDCCIP 0xCUL
71 #else
72 /* Clock source register offset Vs D1CCIPR register */
73 #define D1CCIP 0x0UL
74 #define D2CCIP1 0x4UL
75 #define D2CCIP2 0x8UL
76 #define D3CCIP 0xCUL
77 #endif /* RCC_VER_2_0 */
78
79 #define LL_RCC_REG_SHIFT 0U
80 #define LL_RCC_POS_SHIFT 8U
81 #define LL_RCC_CONFIG_SHIFT 16U
82 #define LL_RCC_MASK_SHIFT 24U
83
84 #define LL_CLKSOURCE_SHIFT(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_POS_SHIFT ) & 0x1FUL)
85
86 #define LL_CLKSOURCE_MASK(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_MASK_SHIFT ) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
87
88 #define LL_CLKSOURCE_CONFIG(__CLKSOURCE__) ((((__CLKSOURCE__) >> LL_RCC_CONFIG_SHIFT) & 0xFFUL) << LL_CLKSOURCE_SHIFT(__CLKSOURCE__))
89
90 #define LL_CLKSOURCE_REG(__CLKSOURCE__) (((__CLKSOURCE__) >> LL_RCC_REG_SHIFT ) & 0xFFUL)
91
92 #define LL_CLKSOURCE(__REG__, __MSK__, __POS__, __CLK__) ((uint32_t)((((__MSK__) >> (__POS__)) << LL_RCC_MASK_SHIFT) | \
93 (( __POS__ ) << LL_RCC_POS_SHIFT) | \
94 (( __REG__ ) << LL_RCC_REG_SHIFT) | \
95 (((__CLK__) >> (__POS__)) << LL_RCC_CONFIG_SHIFT)))
96 /**
97 * @}
98 */
99 /* Exported types ------------------------------------------------------------*/
100 #if defined(USE_FULL_LL_DRIVER)
101 /** @defgroup RCC_LL_Exported_Types RCC Exported Types
102 * @{
103 */
104
105 /** @defgroup LL_ES_CLOCK_FREQ Clocks Frequency Structure
106 * @{
107 */
108
109 /**
110 * @brief RCC Clocks Frequency Structure
111 */
112 typedef struct
113 {
114 uint32_t SYSCLK_Frequency;
115 uint32_t CPUCLK_Frequency;
116 uint32_t HCLK_Frequency;
117 uint32_t PCLK1_Frequency;
118 uint32_t PCLK2_Frequency;
119 uint32_t PCLK3_Frequency;
120 uint32_t PCLK4_Frequency;
121 } LL_RCC_ClocksTypeDef;
122
123 /**
124 * @}
125 */
126
127 /**
128 * @brief PLL Clocks Frequency Structure
129 */
130 typedef struct
131 {
132 uint32_t PLL_P_Frequency;
133 uint32_t PLL_Q_Frequency;
134 uint32_t PLL_R_Frequency;
135 } LL_PLL_ClocksTypeDef;
136
137 /**
138 * @}
139 */
140
141 #endif /* USE_FULL_LL_DRIVER */
142
143 /* Exported constants --------------------------------------------------------*/
144 /** @defgroup RCC_LL_Exported_Constants RCC Exported Constants
145 * @{
146 */
147
148 /** @defgroup RCC_LL_EC_OSC_VALUES Oscillator Values adaptation
149 * @brief Defines used to adapt values of different oscillators
150 * @note These values could be modified in the user environment according to
151 * HW set-up.
152 * @{
153 */
154 #if !defined (HSE_VALUE)
155 #if defined(RCC_VER_X) || defined(RCC_VER_3_0)
156 #define HSE_VALUE 25000000U /*!< Value of the HSE oscillator in Hz */
157 #else
158 #define HSE_VALUE 24000000U /*!< Value of the HSE oscillator in Hz */
159 #endif /* RCC_VER_X || RCC_VER_3_0 */
160 #endif /* HSE_VALUE */
161
162 #if !defined (HSI_VALUE)
163 #define HSI_VALUE 64000000U /*!< Value of the HSI oscillator in Hz */
164 #endif /* HSI_VALUE */
165
166 #if !defined (CSI_VALUE)
167 #define CSI_VALUE 4000000U /*!< Value of the CSI oscillator in Hz */
168 #endif /* CSI_VALUE */
169
170 #if !defined (LSE_VALUE)
171 #define LSE_VALUE 32768U /*!< Value of the LSE oscillator in Hz */
172 #endif /* LSE_VALUE */
173
174 #if !defined (LSI_VALUE)
175 #define LSI_VALUE 32000U /*!< Value of the LSI oscillator in Hz */
176 #endif /* LSI_VALUE */
177
178 #if !defined (EXTERNAL_CLOCK_VALUE)
179 #define EXTERNAL_CLOCK_VALUE 12288000U /*!< Value of the I2S_CKIN external oscillator in Hz */
180 #endif /* EXTERNAL_CLOCK_VALUE */
181
182 #if !defined (HSI48_VALUE)
183 #define HSI48_VALUE 48000000U /*!< Value of the HSI48 oscillator in Hz */
184 #endif /* HSI48_VALUE */
185
186 /**
187 * @}
188 */
189
190 /** @defgroup RCC_LL_EC_HSIDIV HSI oscillator divider
191 * @{
192 */
193 #define LL_RCC_HSI_DIV1 RCC_CR_HSIDIV_1
194 #define LL_RCC_HSI_DIV2 RCC_CR_HSIDIV_2
195 #define LL_RCC_HSI_DIV4 RCC_CR_HSIDIV_4
196 #define LL_RCC_HSI_DIV8 RCC_CR_HSIDIV_8
197 /**
198 * @}
199 */
200
201 /** @defgroup RCC_LL_EC_LSEDRIVE LSE oscillator drive capability
202 * @{
203 */
204 #define LL_RCC_LSEDRIVE_LOW (uint32_t)(0x00000000U)
205 #define LL_RCC_LSEDRIVE_MEDIUMLOW (uint32_t)(RCC_BDCR_LSEDRV_0)
206 #define LL_RCC_LSEDRIVE_MEDIUMHIGH (uint32_t)(RCC_BDCR_LSEDRV_1)
207 #define LL_RCC_LSEDRIVE_HIGH (uint32_t)(RCC_BDCR_LSEDRV)
208 /**
209 * @}
210 */
211
212 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE System clock switch
213 * @{
214 */
215 #define LL_RCC_SYS_CLKSOURCE_HSI RCC_CFGR_SW_HSI
216 #define LL_RCC_SYS_CLKSOURCE_CSI RCC_CFGR_SW_CSI
217 #define LL_RCC_SYS_CLKSOURCE_HSE RCC_CFGR_SW_HSE
218 #define LL_RCC_SYS_CLKSOURCE_PLL1 RCC_CFGR_SW_PLL1
219 /**
220 * @}
221 */
222
223 /** @defgroup RCC_LL_EC_SYS_CLKSOURCE_STATUS System clock switch status
224 * @{
225 */
226 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSI RCC_CFGR_SWS_HSI /*!< HSI used as system clock */
227 #define LL_RCC_SYS_CLKSOURCE_STATUS_CSI RCC_CFGR_SWS_CSI /*!< CSI used as system clock */
228 #define LL_RCC_SYS_CLKSOURCE_STATUS_HSE RCC_CFGR_SWS_HSE /*!< HSE used as system clock */
229 #define LL_RCC_SYS_CLKSOURCE_STATUS_PLL1 RCC_CFGR_SWS_PLL1 /*!< PLL1 used as system clock */
230 /**
231 * @}
232 */
233
234 /** @defgroup RCC_LL_EC_SYSWAKEUP_CLKSOURCE System wakeup clock source
235 * @{
236 */
237 #define LL_RCC_SYSWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
238 #define LL_RCC_SYSWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPWUCK)
239 /**
240 * @}
241 */
242
243 /** @defgroup RCC_LL_EC_KERWAKEUP_CLKSOURCE Kernel wakeup clock source
244 * @{
245 */
246 #define LL_RCC_KERWAKEUP_CLKSOURCE_HSI (uint32_t)(0x00000000U)
247 #define LL_RCC_KERWAKEUP_CLKSOURCE_CSI (uint32_t)(RCC_CFGR_STOPKERWUCK)
248 /**
249 * @}
250 */
251
252 /** @defgroup RCC_LL_EC_SYSCLK_DIV System prescaler
253 * @{
254 */
255 #if defined(RCC_D1CFGR_D1CPRE_DIV1)
256 #define LL_RCC_SYSCLK_DIV_1 RCC_D1CFGR_D1CPRE_DIV1
257 #define LL_RCC_SYSCLK_DIV_2 RCC_D1CFGR_D1CPRE_DIV2
258 #define LL_RCC_SYSCLK_DIV_4 RCC_D1CFGR_D1CPRE_DIV4
259 #define LL_RCC_SYSCLK_DIV_8 RCC_D1CFGR_D1CPRE_DIV8
260 #define LL_RCC_SYSCLK_DIV_16 RCC_D1CFGR_D1CPRE_DIV16
261 #define LL_RCC_SYSCLK_DIV_64 RCC_D1CFGR_D1CPRE_DIV64
262 #define LL_RCC_SYSCLK_DIV_128 RCC_D1CFGR_D1CPRE_DIV128
263 #define LL_RCC_SYSCLK_DIV_256 RCC_D1CFGR_D1CPRE_DIV256
264 #define LL_RCC_SYSCLK_DIV_512 RCC_D1CFGR_D1CPRE_DIV512
265 #else
266 #define LL_RCC_SYSCLK_DIV_1 RCC_CDCFGR1_CDCPRE_DIV1
267 #define LL_RCC_SYSCLK_DIV_2 RCC_CDCFGR1_CDCPRE_DIV2
268 #define LL_RCC_SYSCLK_DIV_4 RCC_CDCFGR1_CDCPRE_DIV4
269 #define LL_RCC_SYSCLK_DIV_8 RCC_CDCFGR1_CDCPRE_DIV8
270 #define LL_RCC_SYSCLK_DIV_16 RCC_CDCFGR1_CDCPRE_DIV16
271 #define LL_RCC_SYSCLK_DIV_64 RCC_CDCFGR1_CDCPRE_DIV64
272 #define LL_RCC_SYSCLK_DIV_128 RCC_CDCFGR1_CDCPRE_DIV128
273 #define LL_RCC_SYSCLK_DIV_256 RCC_CDCFGR1_CDCPRE_DIV256
274 #define LL_RCC_SYSCLK_DIV_512 RCC_CDCFGR1_CDCPRE_DIV512
275 #endif /* RCC_D1CFGR_D1CPRE_DIV1 */
276 /**
277 * @}
278 */
279
280 /** @defgroup RCC_LL_EC_AHB_DIV AHB prescaler
281 * @{
282 */
283 #if defined(RCC_D1CFGR_HPRE_DIV1)
284 #define LL_RCC_AHB_DIV_1 RCC_D1CFGR_HPRE_DIV1
285 #define LL_RCC_AHB_DIV_2 RCC_D1CFGR_HPRE_DIV2
286 #define LL_RCC_AHB_DIV_4 RCC_D1CFGR_HPRE_DIV4
287 #define LL_RCC_AHB_DIV_8 RCC_D1CFGR_HPRE_DIV8
288 #define LL_RCC_AHB_DIV_16 RCC_D1CFGR_HPRE_DIV16
289 #define LL_RCC_AHB_DIV_64 RCC_D1CFGR_HPRE_DIV64
290 #define LL_RCC_AHB_DIV_128 RCC_D1CFGR_HPRE_DIV128
291 #define LL_RCC_AHB_DIV_256 RCC_D1CFGR_HPRE_DIV256
292 #define LL_RCC_AHB_DIV_512 RCC_D1CFGR_HPRE_DIV512
293 #else
294 #define LL_RCC_AHB_DIV_1 RCC_CDCFGR1_HPRE_DIV1
295 #define LL_RCC_AHB_DIV_2 RCC_CDCFGR1_HPRE_DIV2
296 #define LL_RCC_AHB_DIV_4 RCC_CDCFGR1_HPRE_DIV4
297 #define LL_RCC_AHB_DIV_8 RCC_CDCFGR1_HPRE_DIV8
298 #define LL_RCC_AHB_DIV_16 RCC_CDCFGR1_HPRE_DIV16
299 #define LL_RCC_AHB_DIV_64 RCC_CDCFGR1_HPRE_DIV64
300 #define LL_RCC_AHB_DIV_128 RCC_CDCFGR1_HPRE_DIV128
301 #define LL_RCC_AHB_DIV_256 RCC_CDCFGR1_HPRE_DIV256
302 #define LL_RCC_AHB_DIV_512 RCC_CDCFGR1_HPRE_DIV512
303 #endif /* RCC_D1CFGR_HPRE_DIV1 */
304 /**
305 * @}
306 */
307
308 /** @defgroup RCC_LL_EC_APB1_DIV APB low-speed prescaler (APB1)
309 * @{
310 */
311 #if defined(RCC_D2CFGR_D2PPRE1_DIV1)
312 #define LL_RCC_APB1_DIV_1 RCC_D2CFGR_D2PPRE1_DIV1
313 #define LL_RCC_APB1_DIV_2 RCC_D2CFGR_D2PPRE1_DIV2
314 #define LL_RCC_APB1_DIV_4 RCC_D2CFGR_D2PPRE1_DIV4
315 #define LL_RCC_APB1_DIV_8 RCC_D2CFGR_D2PPRE1_DIV8
316 #define LL_RCC_APB1_DIV_16 RCC_D2CFGR_D2PPRE1_DIV16
317 #else
318 #define LL_RCC_APB1_DIV_1 RCC_CDCFGR2_CDPPRE1_DIV1
319 #define LL_RCC_APB1_DIV_2 RCC_CDCFGR2_CDPPRE1_DIV2
320 #define LL_RCC_APB1_DIV_4 RCC_CDCFGR2_CDPPRE1_DIV4
321 #define LL_RCC_APB1_DIV_8 RCC_CDCFGR2_CDPPRE1_DIV8
322 #define LL_RCC_APB1_DIV_16 RCC_CDCFGR2_CDPPRE1_DIV16
323 #endif /* RCC_D2CFGR_D2PPRE1_DIV1 */
324 /**
325 * @}
326 */
327
328 /** @defgroup RCC_LL_EC_APB2_DIV APB low-speed prescaler (APB2)
329 * @{
330 */
331 #if defined(RCC_D2CFGR_D2PPRE2_DIV1)
332 #define LL_RCC_APB2_DIV_1 RCC_D2CFGR_D2PPRE2_DIV1
333 #define LL_RCC_APB2_DIV_2 RCC_D2CFGR_D2PPRE2_DIV2
334 #define LL_RCC_APB2_DIV_4 RCC_D2CFGR_D2PPRE2_DIV4
335 #define LL_RCC_APB2_DIV_8 RCC_D2CFGR_D2PPRE2_DIV8
336 #define LL_RCC_APB2_DIV_16 RCC_D2CFGR_D2PPRE2_DIV16
337 #else
338 #define LL_RCC_APB2_DIV_1 RCC_CDCFGR2_CDPPRE2_DIV1
339 #define LL_RCC_APB2_DIV_2 RCC_CDCFGR2_CDPPRE2_DIV2
340 #define LL_RCC_APB2_DIV_4 RCC_CDCFGR2_CDPPRE2_DIV4
341 #define LL_RCC_APB2_DIV_8 RCC_CDCFGR2_CDPPRE2_DIV8
342 #define LL_RCC_APB2_DIV_16 RCC_CDCFGR2_CDPPRE2_DIV16
343 #endif /* RCC_D2CFGR_D2PPRE2_DIV1 */
344 /**
345 * @}
346 */
347
348 /** @defgroup RCC_LL_EC_APB3_DIV APB low-speed prescaler (APB3)
349 * @{
350 */
351 #if defined(RCC_D1CFGR_D1PPRE_DIV1)
352 #define LL_RCC_APB3_DIV_1 RCC_D1CFGR_D1PPRE_DIV1
353 #define LL_RCC_APB3_DIV_2 RCC_D1CFGR_D1PPRE_DIV2
354 #define LL_RCC_APB3_DIV_4 RCC_D1CFGR_D1PPRE_DIV4
355 #define LL_RCC_APB3_DIV_8 RCC_D1CFGR_D1PPRE_DIV8
356 #define LL_RCC_APB3_DIV_16 RCC_D1CFGR_D1PPRE_DIV16
357 #else
358 #define LL_RCC_APB3_DIV_1 RCC_CDCFGR1_CDPPRE_DIV1
359 #define LL_RCC_APB3_DIV_2 RCC_CDCFGR1_CDPPRE_DIV2
360 #define LL_RCC_APB3_DIV_4 RCC_CDCFGR1_CDPPRE_DIV4
361 #define LL_RCC_APB3_DIV_8 RCC_CDCFGR1_CDPPRE_DIV8
362 #define LL_RCC_APB3_DIV_16 RCC_CDCFGR1_CDPPRE_DIV16
363 #endif /* RCC_D1CFGR_D1PPRE_DIV1 */
364 /**
365 * @}
366 */
367
368 /** @defgroup RCC_LL_EC_APB4_DIV APB low-speed prescaler (APB4)
369 * @{
370 */
371 #if defined(RCC_D3CFGR_D3PPRE_DIV1)
372 #define LL_RCC_APB4_DIV_1 RCC_D3CFGR_D3PPRE_DIV1
373 #define LL_RCC_APB4_DIV_2 RCC_D3CFGR_D3PPRE_DIV2
374 #define LL_RCC_APB4_DIV_4 RCC_D3CFGR_D3PPRE_DIV4
375 #define LL_RCC_APB4_DIV_8 RCC_D3CFGR_D3PPRE_DIV8
376 #define LL_RCC_APB4_DIV_16 RCC_D3CFGR_D3PPRE_DIV16
377 #else
378 #define LL_RCC_APB4_DIV_1 RCC_SRDCFGR_SRDPPRE_DIV1
379 #define LL_RCC_APB4_DIV_2 RCC_SRDCFGR_SRDPPRE_DIV2
380 #define LL_RCC_APB4_DIV_4 RCC_SRDCFGR_SRDPPRE_DIV4
381 #define LL_RCC_APB4_DIV_8 RCC_SRDCFGR_SRDPPRE_DIV8
382 #define LL_RCC_APB4_DIV_16 RCC_SRDCFGR_SRDPPRE_DIV16
383 #endif /* RCC_D3CFGR_D3PPRE_DIV1 */
384 /**
385 * @}
386 */
387
388 /** @defgroup RCC_LL_EC_MCOxSOURCE MCO source selection
389 * @{
390 */
391 #define LL_RCC_MCO1SOURCE_HSI (uint32_t)((RCC_CFGR_MCO1>>16U) | 0x00000000U)
392 #define LL_RCC_MCO1SOURCE_LSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_0)
393 #define LL_RCC_MCO1SOURCE_HSE (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1)
394 #define LL_RCC_MCO1SOURCE_PLL1QCLK (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_1|RCC_CFGR_MCO1_0)
395 #define LL_RCC_MCO1SOURCE_HSI48 (uint32_t)((RCC_CFGR_MCO1>>16U) | RCC_CFGR_MCO1_2)
396 #define LL_RCC_MCO2SOURCE_SYSCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | 0x00000000U)
397 #define LL_RCC_MCO2SOURCE_PLL2PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_0)
398 #define LL_RCC_MCO2SOURCE_HSE (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1)
399 #define LL_RCC_MCO2SOURCE_PLL1PCLK (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_1|RCC_CFGR_MCO2_0)
400 #define LL_RCC_MCO2SOURCE_CSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2)
401 #define LL_RCC_MCO2SOURCE_LSI (uint32_t)((RCC_CFGR_MCO2>>16U) | RCC_CFGR_MCO2_2|RCC_CFGR_MCO2_0)
402 /**
403 * @}
404 */
405
406 /** @defgroup RCC_LL_EC_MCOx_DIV MCO prescaler
407 * @{
408 */
409 #define LL_RCC_MCO1_DIV_1 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0)
410 #define LL_RCC_MCO1_DIV_2 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1)
411 #define LL_RCC_MCO1_DIV_3 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1)
412 #define LL_RCC_MCO1_DIV_4 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2)
413 #define LL_RCC_MCO1_DIV_5 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2)
414 #define LL_RCC_MCO1_DIV_6 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
415 #define LL_RCC_MCO1_DIV_7 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2)
416 #define LL_RCC_MCO1_DIV_8 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_3)
417 #define LL_RCC_MCO1_DIV_9 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_3)
418 #define LL_RCC_MCO1_DIV_10 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
419 #define LL_RCC_MCO1_DIV_11 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_3)
420 #define LL_RCC_MCO1_DIV_12 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
421 #define LL_RCC_MCO1_DIV_13 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_0 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
422 #define LL_RCC_MCO1_DIV_14 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE_1 | RCC_CFGR_MCO1PRE_2 | RCC_CFGR_MCO1PRE_3)
423 #define LL_RCC_MCO1_DIV_15 (uint32_t)((RCC_CFGR_MCO1PRE>>16U) | RCC_CFGR_MCO1PRE)
424 #define LL_RCC_MCO2_DIV_1 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0)
425 #define LL_RCC_MCO2_DIV_2 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1)
426 #define LL_RCC_MCO2_DIV_3 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1)
427 #define LL_RCC_MCO2_DIV_4 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2)
428 #define LL_RCC_MCO2_DIV_5 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2)
429 #define LL_RCC_MCO2_DIV_6 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
430 #define LL_RCC_MCO2_DIV_7 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2)
431 #define LL_RCC_MCO2_DIV_8 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_3)
432 #define LL_RCC_MCO2_DIV_9 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_3)
433 #define LL_RCC_MCO2_DIV_10 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
434 #define LL_RCC_MCO2_DIV_11 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_3)
435 #define LL_RCC_MCO2_DIV_12 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
436 #define LL_RCC_MCO2_DIV_13 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_0 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
437 #define LL_RCC_MCO2_DIV_14 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE_1 | RCC_CFGR_MCO2PRE_2 | RCC_CFGR_MCO2PRE_3)
438 #define LL_RCC_MCO2_DIV_15 (uint32_t)((RCC_CFGR_MCO2PRE>>16U) | RCC_CFGR_MCO2PRE)
439
440 /**
441 * @}
442 */
443
444 /** @defgroup RCC_LL_EC_RTC_HSEDIV HSE prescaler for RTC clock
445 * @{
446 */
447 #define LL_RCC_RTC_NOCLOCK (uint32_t)(0x00000000U)
448 #define LL_RCC_RTC_HSE_DIV_2 (uint32_t)(RCC_CFGR_RTCPRE_1)
449 #define LL_RCC_RTC_HSE_DIV_3 (uint32_t)(RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
450 #define LL_RCC_RTC_HSE_DIV_4 (uint32_t)(RCC_CFGR_RTCPRE_2)
451 #define LL_RCC_RTC_HSE_DIV_5 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
452 #define LL_RCC_RTC_HSE_DIV_6 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
453 #define LL_RCC_RTC_HSE_DIV_7 (uint32_t)(RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
454 #define LL_RCC_RTC_HSE_DIV_8 (uint32_t)(RCC_CFGR_RTCPRE_3)
455 #define LL_RCC_RTC_HSE_DIV_9 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
456 #define LL_RCC_RTC_HSE_DIV_10 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
457 #define LL_RCC_RTC_HSE_DIV_11 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
458 #define LL_RCC_RTC_HSE_DIV_12 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
459 #define LL_RCC_RTC_HSE_DIV_13 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
460 #define LL_RCC_RTC_HSE_DIV_14 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
461 #define LL_RCC_RTC_HSE_DIV_15 (uint32_t)(RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
462 #define LL_RCC_RTC_HSE_DIV_16 (uint32_t)(RCC_CFGR_RTCPRE_4)
463 #define LL_RCC_RTC_HSE_DIV_17 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
464 #define LL_RCC_RTC_HSE_DIV_18 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
465 #define LL_RCC_RTC_HSE_DIV_19 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
466 #define LL_RCC_RTC_HSE_DIV_20 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
467 #define LL_RCC_RTC_HSE_DIV_21 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
468 #define LL_RCC_RTC_HSE_DIV_22 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
469 #define LL_RCC_RTC_HSE_DIV_23 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
470 #define LL_RCC_RTC_HSE_DIV_24 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
471 #define LL_RCC_RTC_HSE_DIV_25 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
472 #define LL_RCC_RTC_HSE_DIV_26 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
473 #define LL_RCC_RTC_HSE_DIV_27 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
474 #define LL_RCC_RTC_HSE_DIV_28 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
475 #define LL_RCC_RTC_HSE_DIV_29 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
476 #define LL_RCC_RTC_HSE_DIV_30 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
477 #define LL_RCC_RTC_HSE_DIV_31 (uint32_t)(RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
478 #define LL_RCC_RTC_HSE_DIV_32 (uint32_t)(RCC_CFGR_RTCPRE_5)
479 #define LL_RCC_RTC_HSE_DIV_33 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_0)
480 #define LL_RCC_RTC_HSE_DIV_34 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1)
481 #define LL_RCC_RTC_HSE_DIV_35 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
482 #define LL_RCC_RTC_HSE_DIV_36 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2)
483 #define LL_RCC_RTC_HSE_DIV_37 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
484 #define LL_RCC_RTC_HSE_DIV_38 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
485 #define LL_RCC_RTC_HSE_DIV_39 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
486 #define LL_RCC_RTC_HSE_DIV_40 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3)
487 #define LL_RCC_RTC_HSE_DIV_41 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
488 #define LL_RCC_RTC_HSE_DIV_42 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
489 #define LL_RCC_RTC_HSE_DIV_43 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
490 #define LL_RCC_RTC_HSE_DIV_44 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
491 #define LL_RCC_RTC_HSE_DIV_45 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
492 #define LL_RCC_RTC_HSE_DIV_46 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
493 #define LL_RCC_RTC_HSE_DIV_47 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
494 #define LL_RCC_RTC_HSE_DIV_48 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4)
495 #define LL_RCC_RTC_HSE_DIV_49 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_0)
496 #define LL_RCC_RTC_HSE_DIV_50 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1)
497 #define LL_RCC_RTC_HSE_DIV_51 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
498 #define LL_RCC_RTC_HSE_DIV_52 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2)
499 #define LL_RCC_RTC_HSE_DIV_53 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
500 #define LL_RCC_RTC_HSE_DIV_54 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
501 #define LL_RCC_RTC_HSE_DIV_55 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
502 #define LL_RCC_RTC_HSE_DIV_56 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3)
503 #define LL_RCC_RTC_HSE_DIV_57 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_0)
504 #define LL_RCC_RTC_HSE_DIV_58 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1)
505 #define LL_RCC_RTC_HSE_DIV_59 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
506 #define LL_RCC_RTC_HSE_DIV_60 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2)
507 #define LL_RCC_RTC_HSE_DIV_61 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_0)
508 #define LL_RCC_RTC_HSE_DIV_62 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1)
509 #define LL_RCC_RTC_HSE_DIV_63 (uint32_t)(RCC_CFGR_RTCPRE_5|RCC_CFGR_RTCPRE_4|RCC_CFGR_RTCPRE_3|RCC_CFGR_RTCPRE_2|RCC_CFGR_RTCPRE_1|RCC_CFGR_RTCPRE_0)
510 /**
511 * @}
512 */
513
514 /** @defgroup RCC_LL_EC_USARTx_CLKSOURCE Peripheral USART clock source selection
515 * @{
516 */
517 #if defined(RCC_D2CCIP2R_USART16SEL)
518 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
519 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0)
520 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_1)
521 #define LL_RCC_USART16_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_1)
522 #define LL_RCC_USART16_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_2)
523 #define LL_RCC_USART16_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, RCC_D2CCIP2R_USART16SEL_0 | RCC_D2CCIP2R_USART16SEL_2)
524 /* Aliases */
525 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_RCC_USART16_CLKSOURCE_PCLK2
526 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_RCC_USART16_CLKSOURCE_PLL2Q
527 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_RCC_USART16_CLKSOURCE_PLL3Q
528 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_RCC_USART16_CLKSOURCE_HSI
529 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_RCC_USART16_CLKSOURCE_CSI
530 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_RCC_USART16_CLKSOURCE_LSE
531
532 #elif defined(RCC_D2CCIP2R_USART16910SEL)
533 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
534 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0)
535 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_1)
536 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_1)
537 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_2)
538 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, RCC_D2CCIP2R_USART16910SEL_0 | RCC_D2CCIP2R_USART16910SEL_2)
539 /* Aliases */
540 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
541 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
542 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
543 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
544 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
545 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
546
547 #else
548 #define LL_RCC_USART16910_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
549 #define LL_RCC_USART16910_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0)
550 #define LL_RCC_USART16910_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_1)
551 #define LL_RCC_USART16910_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_1)
552 #define LL_RCC_USART16910_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_2)
553 #define LL_RCC_USART16910_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, RCC_CDCCIP2R_USART16910SEL_0 | RCC_CDCCIP2R_USART16910SEL_2)
554 /* Aliases */
555 #define LL_RCC_USART16_CLKSOURCE_PCLK2 LL_RCC_USART16910_CLKSOURCE_PCLK2
556 #define LL_RCC_USART16_CLKSOURCE_PLL2Q LL_RCC_USART16910_CLKSOURCE_PLL2Q
557 #define LL_RCC_USART16_CLKSOURCE_PLL3Q LL_RCC_USART16910_CLKSOURCE_PLL3Q
558 #define LL_RCC_USART16_CLKSOURCE_HSI LL_RCC_USART16910_CLKSOURCE_HSI
559 #define LL_RCC_USART16_CLKSOURCE_CSI LL_RCC_USART16910_CLKSOURCE_CSI
560 #define LL_RCC_USART16_CLKSOURCE_LSE LL_RCC_USART16910_CLKSOURCE_LSE
561 #endif /* RCC_D2CCIP2R_USART16SEL */
562 #if defined(RCC_D2CCIP2R_USART28SEL)
563 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
564 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0)
565 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_1)
566 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_1)
567 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_2)
568 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, RCC_D2CCIP2R_USART28SEL_0 | RCC_D2CCIP2R_USART28SEL_2)
569 #else
570 #define LL_RCC_USART234578_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
571 #define LL_RCC_USART234578_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0)
572 #define LL_RCC_USART234578_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_1)
573 #define LL_RCC_USART234578_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_1)
574 #define LL_RCC_USART234578_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_2)
575 #define LL_RCC_USART234578_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, RCC_CDCCIP2R_USART234578SEL_0 | RCC_CDCCIP2R_USART234578SEL_2)
576 #endif /* RCC_D2CCIP2R_USART28SEL */
577 /**
578 * @}
579 */
580
581 /** @defgroup RCC_LL_EC_LPUARTx_CLKSOURCE Peripheral LPUART clock source selection
582 * @{
583 */
584 #if defined(RCC_D3CCIPR_LPUART1SEL)
585 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
586 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_D3CCIPR_LPUART1SEL_0)
587 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_D3CCIPR_LPUART1SEL_1)
588 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_1)
589 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_D3CCIPR_LPUART1SEL_2)
590 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_D3CCIPR_LPUART1SEL_0 | RCC_D3CCIPR_LPUART1SEL_2)
591 #else
592 #define LL_RCC_LPUART1_CLKSOURCE_PCLK4 (0x00000000U)
593 #define LL_RCC_LPUART1_CLKSOURCE_PLL2Q (RCC_SRDCCIPR_LPUART1SEL_0)
594 #define LL_RCC_LPUART1_CLKSOURCE_PLL3Q (RCC_SRDCCIPR_LPUART1SEL_1)
595 #define LL_RCC_LPUART1_CLKSOURCE_HSI (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_1)
596 #define LL_RCC_LPUART1_CLKSOURCE_CSI (RCC_SRDCCIPR_LPUART1SEL_2)
597 #define LL_RCC_LPUART1_CLKSOURCE_LSE (RCC_SRDCCIPR_LPUART1SEL_0 | RCC_SRDCCIPR_LPUART1SEL_2)
598 #endif /* RCC_D3CCIPR_LPUART1SEL */
599 /**
600 * @}
601 */
602
603 /** @defgroup RCC_LL_EC_I2Cx_CLKSOURCE Peripheral I2C clock source selection
604 * @{
605 */
606 #if defined (RCC_D2CCIP2R_I2C123SEL)
607 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
608 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0)
609 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_1)
610 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, RCC_D2CCIP2R_I2C123SEL_0 | RCC_D2CCIP2R_I2C123SEL_1)
611 /* Aliases */
612 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_RCC_I2C123_CLKSOURCE_PCLK1
613 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_RCC_I2C123_CLKSOURCE_PLL3R
614 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_RCC_I2C123_CLKSOURCE_HSI
615 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_RCC_I2C123_CLKSOURCE_CSI
616
617 #elif defined (RCC_D2CCIP2R_I2C1235SEL)
618 #define LL_RCC_I2C1235_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
619 #define LL_RCC_I2C1235_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0)
620 #define LL_RCC_I2C1235_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_1)
621 #define LL_RCC_I2C1235_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, RCC_D2CCIP2R_I2C1235SEL_0 | RCC_D2CCIP2R_I2C1235SEL_1)
622 /* Aliases */
623 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_RCC_I2C1235_CLKSOURCE_PCLK1
624 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_RCC_I2C1235_CLKSOURCE_PLL3R
625 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_RCC_I2C1235_CLKSOURCE_HSI
626 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_RCC_I2C1235_CLKSOURCE_CSI
627
628 #else
629 #define LL_RCC_I2C123_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
630 #define LL_RCC_I2C123_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0)
631 #define LL_RCC_I2C123_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_1)
632 #define LL_RCC_I2C123_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, RCC_CDCCIP2R_I2C123SEL_0 | RCC_CDCCIP2R_I2C123SEL_1)
633 #endif /* RCC_D2CCIP2R_I2C123SEL */
634 #if defined (RCC_D3CCIPR_I2C4SEL)
635 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
636 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0)
637 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_1)
638 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, RCC_D3CCIPR_I2C4SEL_0 | RCC_D3CCIPR_I2C4SEL_1)
639 #else
640 #define LL_RCC_I2C4_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
641 #define LL_RCC_I2C4_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0)
642 #define LL_RCC_I2C4_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_1)
643 #define LL_RCC_I2C4_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, RCC_SRDCCIPR_I2C4SEL_0 | RCC_SRDCCIPR_I2C4SEL_1)
644 #endif /* RCC_D3CCIPR_I2C4SEL */
645 /**
646 * @}
647 */
648
649 /** @defgroup RCC_LL_EC_LPTIMx_CLKSOURCE Peripheral LPTIM clock source selection
650 * @{
651 */
652 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
653 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
654 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0)
655 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_1)
656 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_1)
657 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_2)
658 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, RCC_D2CCIP2R_LPTIM1SEL_0 | RCC_D2CCIP2R_LPTIM1SEL_2)
659 #else
660 #define LL_RCC_LPTIM1_CLKSOURCE_PCLK1 LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
661 #define LL_RCC_LPTIM1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0)
662 #define LL_RCC_LPTIM1_CLKSOURCE_PLL3R LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_1)
663 #define LL_RCC_LPTIM1_CLKSOURCE_LSE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_1)
664 #define LL_RCC_LPTIM1_CLKSOURCE_LSI LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_2)
665 #define LL_RCC_LPTIM1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, RCC_CDCCIP2R_LPTIM1SEL_0 | RCC_CDCCIP2R_LPTIM1SEL_2)
666 #endif /* RCC_D2CCIP2R_LPTIM1SEL */
667 #if defined(RCC_D3CCIPR_LPTIM2SEL)
668 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
669 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0)
670 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_1)
671 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_1)
672 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_2)
673 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, RCC_D3CCIPR_LPTIM2SEL_0 | RCC_D3CCIPR_LPTIM2SEL_2)
674 #else
675 #define LL_RCC_LPTIM2_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
676 #define LL_RCC_LPTIM2_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0)
677 #define LL_RCC_LPTIM2_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_1)
678 #define LL_RCC_LPTIM2_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_1)
679 #define LL_RCC_LPTIM2_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_2)
680 #define LL_RCC_LPTIM2_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, RCC_SRDCCIPR_LPTIM2SEL_0 | RCC_SRDCCIPR_LPTIM2SEL_2)
681 #endif /* RCC_D3CCIPR_LPTIM2SEL */
682 #if defined(RCC_D3CCIPR_LPTIM345SEL)
683 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
684 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0)
685 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_1)
686 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_1)
687 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_2)
688 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, RCC_D3CCIPR_LPTIM345SEL_0 | RCC_D3CCIPR_LPTIM345SEL_2)
689 #else
690 #define LL_RCC_LPTIM345_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
691 #define LL_RCC_LPTIM345_CLKSOURCE_PLL2P LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0)
692 #define LL_RCC_LPTIM345_CLKSOURCE_PLL3R LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_1)
693 #define LL_RCC_LPTIM345_CLKSOURCE_LSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_1)
694 #define LL_RCC_LPTIM345_CLKSOURCE_LSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_2)
695 #define LL_RCC_LPTIM345_CLKSOURCE_CLKP LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, RCC_SRDCCIPR_LPTIM3SEL_0 | RCC_SRDCCIPR_LPTIM3SEL_2)
696 /* aliases*/
697 #define LL_RCC_LPTIM3_CLKSOURCE_PCLK4 LL_RCC_LPTIM345_CLKSOURCE_PCLK4
698 #define LL_RCC_LPTIM3_CLKSOURCE_PLL2P LL_RCC_LPTIM345_CLKSOURCE_PLL2P
699 #define LL_RCC_LPTIM3_CLKSOURCE_PLL3R LL_RCC_LPTIM345_CLKSOURCE_PLL3R
700 #define LL_RCC_LPTIM3_CLKSOURCE_LSE LL_RCC_LPTIM345_CLKSOURCE_LSE
701 #define LL_RCC_LPTIM3_CLKSOURCE_LSI LL_RCC_LPTIM345_CLKSOURCE_LSI
702 #define LL_RCC_LPTIM3_CLKSOURCE_CLKP LL_RCC_LPTIM345_CLKSOURCE_CLKP
703 #endif /* RCC_D3CCIPR_LPTIM345SEL */
704 /**
705 * @}
706 */
707
708 /** @defgroup RCC_LL_EC_SAIx_CLKSOURCE Peripheral SAI clock source selection
709 * @{
710 */
711 #if defined(RCC_D2CCIP1R_SAI1SEL)
712 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
713 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0)
714 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_1)
715 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_0 | RCC_D2CCIP1R_SAI1SEL_1)
716 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, RCC_D2CCIP1R_SAI1SEL_2)
717 #else
718 #define LL_RCC_SAI1_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
719 #define LL_RCC_SAI1_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0)
720 #define LL_RCC_SAI1_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_1)
721 #define LL_RCC_SAI1_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_0 | RCC_CDCCIP1R_SAI1SEL_1)
722 #define LL_RCC_SAI1_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, RCC_CDCCIP1R_SAI1SEL_2)
723 #endif
724 #if defined(SAI3)
725 #define LL_RCC_SAI23_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
726 #define LL_RCC_SAI23_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0)
727 #define LL_RCC_SAI23_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_1)
728 #define LL_RCC_SAI23_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_0 | RCC_D2CCIP1R_SAI23SEL_1)
729 #define LL_RCC_SAI23_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, RCC_D2CCIP1R_SAI23SEL_2)
730 #endif /* SAI3 */
731 #if defined(RCC_CDCCIP1R_SAI2ASEL)
732 #define LL_RCC_SAI2A_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
733 #define LL_RCC_SAI2A_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0)
734 #define LL_RCC_SAI2A_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_1)
735 #define LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_1)
736 #define LL_RCC_SAI2A_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_2)
737 #define LL_RCC_SAI2A_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, RCC_CDCCIP1R_SAI2ASEL_0 | RCC_CDCCIP1R_SAI2ASEL_2)
738 #endif /* RCC_CDCCIP1R_SAI2ASEL */
739 #if defined(RCC_CDCCIP1R_SAI2BSEL)
740 #define LL_RCC_SAI2B_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
741 #define LL_RCC_SAI2B_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0)
742 #define LL_RCC_SAI2B_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_1)
743 #define LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_1)
744 #define LL_RCC_SAI2B_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_2)
745 #define LL_RCC_SAI2B_CLKSOURCE_SPDIF LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, RCC_CDCCIP1R_SAI2BSEL_0 | RCC_CDCCIP1R_SAI2BSEL_2)
746 #endif /* RCC_CDCCIP1R_SAI2BSEL */
747 #if defined(SAI4_Block_A)
748 #define LL_RCC_SAI4A_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
749 #define LL_RCC_SAI4A_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0)
750 #define LL_RCC_SAI4A_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_1)
751 #define LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_0 | RCC_D3CCIPR_SAI4ASEL_1)
752 #define LL_RCC_SAI4A_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2)
753 #if defined(RCC_VER_3_0)
754 #define LL_RCC_SAI4A_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, RCC_D3CCIPR_SAI4ASEL_2 | RCC_D3CCIPR_SAI4ASEL_0)
755 #endif /* RCC_VER_3_0 */
756 #endif /* SAI4_Block_A */
757 #if defined(SAI4_Block_B)
758 #define LL_RCC_SAI4B_CLKSOURCE_PLL1Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
759 #define LL_RCC_SAI4B_CLKSOURCE_PLL2P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0)
760 #define LL_RCC_SAI4B_CLKSOURCE_PLL3P LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_1)
761 #define LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_0 | RCC_D3CCIPR_SAI4BSEL_1)
762 #define LL_RCC_SAI4B_CLKSOURCE_CLKP LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2)
763 #if defined(RCC_VER_3_0)
764 #define LL_RCC_SAI4B_CLKSOURCE_SPDIF LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, RCC_D3CCIPR_SAI4BSEL_2 | RCC_D3CCIPR_SAI4BSEL_0)
765 #endif /* RCC_VER_3_0 */
766 #endif /* SAI4_Block_B */
767 /**
768 * @}
769 */
770
771 /** @defgroup RCC_LL_EC_SDMMC_CLKSOURCE Peripheral SDMMC clock source selection
772 * @{
773 */
774 #if defined(RCC_D1CCIPR_SDMMCSEL)
775 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
776 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_SDMMCSEL)
777 #else
778 #define LL_RCC_SDMMC_CLKSOURCE_PLL1Q (0x00000000U)
779 #define LL_RCC_SDMMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_SDMMCSEL)
780 #endif /* RCC_D1CCIPR_SDMMCSEL */
781 /**
782 * @}
783 */
784
785 /** @defgroup RCC_LL_EC_RNG_CLKSOURCE Peripheral RNG clock source selection
786 * @{
787 */
788 #if defined(RCC_D2CCIP2R_RNGSEL)
789 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
790 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_RNGSEL_0)
791 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_D2CCIP2R_RNGSEL_1)
792 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_D2CCIP2R_RNGSEL_1 | RCC_D2CCIP2R_RNGSEL_0)
793 #else
794 #define LL_RCC_RNG_CLKSOURCE_HSI48 (0x00000000U)
795 #define LL_RCC_RNG_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_RNGSEL_0)
796 #define LL_RCC_RNG_CLKSOURCE_LSE (RCC_CDCCIP2R_RNGSEL_1)
797 #define LL_RCC_RNG_CLKSOURCE_LSI (RCC_CDCCIP2R_RNGSEL_1 | RCC_CDCCIP2R_RNGSEL_0)
798 #endif /* RCC_D2CCIP2R_RNGSEL */
799 /**
800 * @}
801 */
802
803 /** @defgroup RCC_LL_EC_USB_CLKSOURCE Peripheral USB clock source selection
804 * @{
805 */
806 #if defined(RCC_D2CCIP2R_USBSEL)
807 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
808 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_D2CCIP2R_USBSEL_0)
809 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_D2CCIP2R_USBSEL_1)
810 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_D2CCIP2R_USBSEL_1 | RCC_D2CCIP2R_USBSEL_0)
811 #else
812 #define LL_RCC_USB_CLKSOURCE_DISABLE (0x00000000U)
813 #define LL_RCC_USB_CLKSOURCE_PLL1Q (RCC_CDCCIP2R_USBSEL_0)
814 #define LL_RCC_USB_CLKSOURCE_PLL3Q (RCC_CDCCIP2R_USBSEL_1)
815 #define LL_RCC_USB_CLKSOURCE_HSI48 (RCC_CDCCIP2R_USBSEL_1 | RCC_CDCCIP2R_USBSEL_0)
816 #endif /* RCC_D2CCIP2R_USBSEL */
817 /**
818 * @}
819 */
820
821 /** @defgroup RCC_LL_EC_CEC_CLKSOURCE Peripheral CEC clock source selection
822 * @{
823 */
824 #if defined(RCC_D2CCIP2R_CECSEL)
825 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
826 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_D2CCIP2R_CECSEL_0)
827 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_D2CCIP2R_CECSEL_1)
828 #else
829 #define LL_RCC_CEC_CLKSOURCE_LSE (0x00000000U)
830 #define LL_RCC_CEC_CLKSOURCE_LSI (RCC_CDCCIP2R_CECSEL_0)
831 #define LL_RCC_CEC_CLKSOURCE_CSI_DIV122 (RCC_CDCCIP2R_CECSEL_1)
832 #endif
833 /**
834 * @}
835 */
836
837 #if defined(DSI)
838 /** @defgroup RCC_LL_EC_DSI_CLKSOURCE Peripheral DSI clock source selection
839 * @{
840 */
841 #define LL_RCC_DSI_CLKSOURCE_PHY (0x00000000U)
842 #define LL_RCC_DSI_CLKSOURCE_PLL2Q (RCC_D1CCIPR_DSISEL)
843 /**
844 * @}
845 */
846 #endif /* DSI */
847
848 /** @defgroup RCC_LL_EC_DFSDM_CLKSOURCE Peripheral DFSDM clock source selection
849 * @{
850 */
851 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
852 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
853 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_D2CCIP1R_DFSDM1SEL)
854 #else
855 #define LL_RCC_DFSDM1_CLKSOURCE_PCLK2 (0x00000000U)
856 #define LL_RCC_DFSDM1_CLKSOURCE_SYSCLK (RCC_CDCCIP1R_DFSDM1SEL)
857 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
858 /**
859 * @}
860 */
861
862 #if defined(DFSDM2_BASE)
863 /** @defgroup RCC_LL_EC_DFSDM2_CLKSOURCE Peripheral DFSDM2 clock source selection
864 * @{
865 */
866 #define LL_RCC_DFSDM2_CLKSOURCE_PCLK4 (0x00000000U)
867 #define LL_RCC_DFSDM2_CLKSOURCE_SYSCLK (RCC_SRDCCIPR_DFSDM2SEL)
868 /**
869 * @}
870 */
871 #endif /* DFSDM2_BASE */
872
873 /** @defgroup RCC_LL_EC_FMC_CLKSOURCE Peripheral FMC clock source selection
874 * @{
875 */
876 #if defined(RCC_D1CCIPR_FMCSEL)
877 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
878 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_D1CCIPR_FMCSEL_0)
879 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_D1CCIPR_FMCSEL_1)
880 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_D1CCIPR_FMCSEL_0 | RCC_D1CCIPR_FMCSEL_1)
881 #else
882 #define LL_RCC_FMC_CLKSOURCE_HCLK (0x00000000U)
883 #define LL_RCC_FMC_CLKSOURCE_PLL1Q (RCC_CDCCIPR_FMCSEL_0)
884 #define LL_RCC_FMC_CLKSOURCE_PLL2R (RCC_CDCCIPR_FMCSEL_1)
885 #define LL_RCC_FMC_CLKSOURCE_CLKP (RCC_CDCCIPR_FMCSEL_0 | RCC_CDCCIPR_FMCSEL_1)
886 #endif /* RCC_D1CCIPR_FMCSEL */
887 /**
888 * @}
889 */
890
891 #if defined(QUADSPI)
892 /** @defgroup RCC_LL_EC_QSPI_CLKSOURCE Peripheral QSPI clock source selection
893 * @{
894 */
895 #define LL_RCC_QSPI_CLKSOURCE_HCLK (0x00000000U)
896 #define LL_RCC_QSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_QSPISEL_0)
897 #define LL_RCC_QSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_QSPISEL_1)
898 #define LL_RCC_QSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_QSPISEL_0 | RCC_D1CCIPR_QSPISEL_1)
899 /**
900 * @}
901 */
902 #endif /* QUADSPI */
903
904
905 #if defined(OCTOSPI1) || defined(OCTOSPI2)
906 /** @defgroup RCC_LL_EC_OSPI_CLKSOURCE Peripheral OSPI clock source selection
907 * @{
908 */
909 #if defined(RCC_D1CCIPR_OCTOSPISEL)
910 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
911 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_D1CCIPR_OCTOSPISEL_0)
912 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_D1CCIPR_OCTOSPISEL_1)
913 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_D1CCIPR_OCTOSPISEL_0 | RCC_D1CCIPR_OCTOSPISEL_1)
914 #else
915 #define LL_RCC_OSPI_CLKSOURCE_HCLK (0x00000000U)
916 #define LL_RCC_OSPI_CLKSOURCE_PLL1Q (RCC_CDCCIPR_OCTOSPISEL_0)
917 #define LL_RCC_OSPI_CLKSOURCE_PLL2R (RCC_CDCCIPR_OCTOSPISEL_1)
918 #define LL_RCC_OSPI_CLKSOURCE_CLKP (RCC_CDCCIPR_OCTOSPISEL_0 | RCC_CDCCIPR_OCTOSPISEL_1)
919 #endif /* RCC_D1CCIPR_OCTOSPISEL */
920 /**
921 * @}
922 */
923 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
924
925
926 /** @defgroup RCC_LL_EC_CLKP_CLKSOURCE Peripheral CLKP clock source selection
927 * @{
928 */
929 #if defined(RCC_D1CCIPR_CKPERSEL)
930 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
931 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_D1CCIPR_CKPERSEL_0)
932 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_D1CCIPR_CKPERSEL_1)
933 #else
934 #define LL_RCC_CLKP_CLKSOURCE_HSI (0x00000000U)
935 #define LL_RCC_CLKP_CLKSOURCE_CSI (RCC_CDCCIPR_CKPERSEL_0)
936 #define LL_RCC_CLKP_CLKSOURCE_HSE (RCC_CDCCIPR_CKPERSEL_1)
937 #endif /* RCC_D1CCIPR_CKPERSEL */
938 /**
939 * @}
940 */
941
942 /** @defgroup RCC_LL_EC_SPIx_CLKSOURCE Peripheral SPI clock source selection
943 * @{
944 */
945 #if defined(RCC_D2CCIP1R_SPI123SEL)
946 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
947 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0)
948 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_1)
949 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_0 | RCC_D2CCIP1R_SPI123SEL_1)
950 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, RCC_D2CCIP1R_SPI123SEL_2)
951 #else
952 #define LL_RCC_SPI123_CLKSOURCE_PLL1Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
953 #define LL_RCC_SPI123_CLKSOURCE_PLL2P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0)
954 #define LL_RCC_SPI123_CLKSOURCE_PLL3P LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_1)
955 #define LL_RCC_SPI123_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_0 | RCC_CDCCIP1R_SPI123SEL_1)
956 #define LL_RCC_SPI123_CLKSOURCE_CLKP LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, RCC_CDCCIP1R_SPI123SEL_2)
957 #endif /* RCC_D2CCIP1R_SPI123SEL */
958 #if defined(RCC_D2CCIP1R_SPI45SEL)
959 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
960 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0)
961 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_1)
962 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_1)
963 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_2)
964 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, RCC_D2CCIP1R_SPI45SEL_0 | RCC_D2CCIP1R_SPI45SEL_2)
965 #else
966 #define LL_RCC_SPI45_CLKSOURCE_PCLK2 LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
967 #define LL_RCC_SPI45_CLKSOURCE_PLL2Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0)
968 #define LL_RCC_SPI45_CLKSOURCE_PLL3Q LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_1)
969 #define LL_RCC_SPI45_CLKSOURCE_HSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_1)
970 #define LL_RCC_SPI45_CLKSOURCE_CSI LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_2)
971 #define LL_RCC_SPI45_CLKSOURCE_HSE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, RCC_CDCCIP1R_SPI45SEL_0 | RCC_CDCCIP1R_SPI45SEL_2)
972 #endif /* (RCC_D2CCIP1R_SPI45SEL */
973 #if defined(RCC_D3CCIPR_SPI6SEL)
974 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
975 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0)
976 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_1)
977 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_1)
978 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_2)
979 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, RCC_D3CCIPR_SPI6SEL_0 | RCC_D3CCIPR_SPI6SEL_2)
980 #else
981 #define LL_RCC_SPI6_CLKSOURCE_PCLK4 LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
982 #define LL_RCC_SPI6_CLKSOURCE_PLL2Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0)
983 #define LL_RCC_SPI6_CLKSOURCE_PLL3Q LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1)
984 #define LL_RCC_SPI6_CLKSOURCE_HSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_1)
985 #define LL_RCC_SPI6_CLKSOURCE_CSI LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_2)
986 #define LL_RCC_SPI6_CLKSOURCE_HSE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_0 | RCC_SRDCCIPR_SPI6SEL_2)
987 #define LL_RCC_SPI6_CLKSOURCE_I2S_CKIN LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, RCC_SRDCCIPR_SPI6SEL_1 | RCC_SRDCCIPR_SPI6SEL_2)
988 #endif /* RCC_D3CCIPR_SPI6SEL */
989 /**
990 * @}
991 */
992
993 /** @defgroup RCC_LL_EC_SPDIF_CLKSOURCE Peripheral SPDIF clock source selection
994 * @{
995 */
996 #if defined(RCC_D2CCIP1R_SPDIFSEL)
997 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
998 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_D2CCIP1R_SPDIFSEL_0)
999 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_D2CCIP1R_SPDIFSEL_1)
1000 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_D2CCIP1R_SPDIFSEL_0 | RCC_D2CCIP1R_SPDIFSEL_1)
1001 #else
1002 #define LL_RCC_SPDIF_CLKSOURCE_PLL1Q (0x00000000U)
1003 #define LL_RCC_SPDIF_CLKSOURCE_PLL2R (RCC_CDCCIP1R_SPDIFSEL_0)
1004 #define LL_RCC_SPDIF_CLKSOURCE_PLL3R (RCC_CDCCIP1R_SPDIFSEL_1)
1005 #define LL_RCC_SPDIF_CLKSOURCE_HSI (RCC_CDCCIP1R_SPDIFSEL_0 | RCC_CDCCIP1R_SPDIFSEL_1)
1006 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1007 /**
1008 * @}
1009 */
1010
1011 #if defined(FDCAN1) || defined(FDCAN2)
1012 /** @defgroup RCC_LL_EC_FDCAN_CLKSOURCE Peripheral FDCAN clock source selection
1013 * @{
1014 */
1015 #if defined(RCC_D2CCIP1R_FDCANSEL)
1016 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
1017 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_D2CCIP1R_FDCANSEL_0)
1018 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_D2CCIP1R_FDCANSEL_1)
1019 #else
1020 #define LL_RCC_FDCAN_CLKSOURCE_HSE (0x00000000U)
1021 #define LL_RCC_FDCAN_CLKSOURCE_PLL1Q (RCC_CDCCIP1R_FDCANSEL_0)
1022 #define LL_RCC_FDCAN_CLKSOURCE_PLL2Q (RCC_CDCCIP1R_FDCANSEL_1)
1023 #endif /* RCC_D2CCIP1R_FDCANSEL */
1024 /**
1025 * @}
1026 */
1027 #endif /*FDCAN1 || FDCAN2*/
1028
1029 /** @defgroup RCC_LL_EC_SWP_CLKSOURCE Peripheral SWP clock source selection
1030 * @{
1031 */
1032 #if defined(RCC_D2CCIP1R_SWPSEL)
1033 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
1034 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_D2CCIP1R_SWPSEL)
1035 #else
1036 #define LL_RCC_SWP_CLKSOURCE_PCLK1 (0x00000000U)
1037 #define LL_RCC_SWP_CLKSOURCE_HSI (RCC_CDCCIP1R_SWPSEL)
1038 #endif /* RCC_D2CCIP1R_SWPSEL */
1039 /**
1040 * @}
1041 */
1042
1043 /** @defgroup RCC_LL_EC_ADC_CLKSOURCE Peripheral ADC clock source selection
1044 * @{
1045 */
1046 #if defined(RCC_D3CCIPR_ADCSEL)
1047 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1048 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_D3CCIPR_ADCSEL_0)
1049 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_D3CCIPR_ADCSEL_1)
1050 #else
1051 #define LL_RCC_ADC_CLKSOURCE_PLL2P (0x00000000U)
1052 #define LL_RCC_ADC_CLKSOURCE_PLL3R (RCC_SRDCCIPR_ADCSEL_0)
1053 #define LL_RCC_ADC_CLKSOURCE_CLKP (RCC_SRDCCIPR_ADCSEL_1)
1054 #endif /* RCC_D3CCIPR_ADCSEL */
1055 /**
1056 * @}
1057 */
1058
1059 /** @defgroup RCC_LL_EC_USARTx Peripheral USART get clock source
1060 * @{
1061 */
1062 #if defined (RCC_D2CCIP2R_USART16SEL)
1063 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16SEL, RCC_D2CCIP2R_USART16SEL_Pos, 0x00000000U)
1064 #elif defined (RCC_D2CCIP2R_USART16910SEL)
1065 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART16910SEL, RCC_D2CCIP2R_USART16910SEL_Pos, 0x00000000U)
1066 /* alias*/
1067 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
1068 #else
1069 #define LL_RCC_USART16_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART16910SEL, RCC_CDCCIP2R_USART16910SEL_Pos, 0x00000000U)
1070 /* alias*/
1071 #define LL_RCC_USART16910_CLKSOURCE LL_RCC_USART16_CLKSOURCE
1072 #endif /* RCC_D2CCIP2R_USART16SEL */
1073 #if defined (RCC_D2CCIP2R_USART28SEL)
1074 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_USART28SEL, RCC_D2CCIP2R_USART28SEL_Pos, 0x00000000U)
1075 #else
1076 #define LL_RCC_USART234578_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_USART234578SEL, RCC_CDCCIP2R_USART234578SEL_Pos, 0x00000000U)
1077 #endif /* RCC_D2CCIP2R_USART28SEL */
1078 /**
1079 * @}
1080 */
1081
1082 /** @defgroup RCC_LL_EC_LPUARTx Peripheral LPUART get clock source
1083 * @{
1084 */
1085 #if defined(RCC_D3CCIPR_LPUART1SEL)
1086 #define LL_RCC_LPUART1_CLKSOURCE RCC_D3CCIPR_LPUART1SEL
1087 #else
1088 #define LL_RCC_LPUART1_CLKSOURCE RCC_SRDCCIPR_LPUART1SEL
1089 #endif /* RCC_D3CCIPR_LPUART1SEL */
1090 /**
1091 * @}
1092 */
1093
1094 /** @defgroup RCC_LL_EC_I2Cx Peripheral I2C get clock source
1095 * @{
1096 */
1097 #if defined(RCC_D2CCIP2R_I2C123SEL)
1098 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C123SEL, RCC_D2CCIP2R_I2C123SEL_Pos, 0x00000000U)
1099 /* alias */
1100 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
1101 #elif defined(RCC_D2CCIP2R_I2C1235SEL)
1102 #define LL_RCC_I2C1235_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_I2C1235SEL, RCC_D2CCIP2R_I2C1235SEL_Pos, 0x00000000U)
1103 /* alias */
1104 #define LL_RCC_I2C123_CLKSOURCE LL_RCC_I2C1235_CLKSOURCE
1105 #else
1106 #define LL_RCC_I2C123_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_I2C123SEL, RCC_CDCCIP2R_I2C123SEL_Pos, 0x00000000U)
1107 /* alias */
1108 #define LL_RCC_I2C1235_CLKSOURCE LL_RCC_I2C123_CLKSOURCE
1109 #endif /* RCC_D2CCIP2R_I2C123SEL */
1110 #if defined(RCC_D3CCIPR_I2C4SEL)
1111 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_I2C4SEL, RCC_D3CCIPR_I2C4SEL_Pos, 0x00000000U)
1112 #else
1113 #define LL_RCC_I2C4_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_I2C4SEL, RCC_SRDCCIPR_I2C4SEL_Pos, 0x00000000U)
1114 #endif /* RCC_D3CCIPR_I2C4SEL */
1115 /**
1116 * @}
1117 */
1118
1119 /** @defgroup RCC_LL_EC_LPTIMx Peripheral LPTIM get clock source
1120 * @{
1121 */
1122 #if defined(RCC_D2CCIP2R_LPTIM1SEL)
1123 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(D2CCIP2, RCC_D2CCIP2R_LPTIM1SEL, RCC_D2CCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1124 #else
1125 #define LL_RCC_LPTIM1_CLKSOURCE LL_CLKSOURCE(CDCCIP2, RCC_CDCCIP2R_LPTIM1SEL, RCC_CDCCIP2R_LPTIM1SEL_Pos, 0x00000000U)
1126 #endif /* RCC_D2CCIP2R_LPTIM1SEL) */
1127 #if defined(RCC_D3CCIPR_LPTIM2SEL)
1128 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM2SEL, RCC_D3CCIPR_LPTIM2SEL_Pos, 0x00000000U)
1129 #else
1130 #define LL_RCC_LPTIM2_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM2SEL, RCC_SRDCCIPR_LPTIM2SEL_Pos, 0x00000000U)
1131 #endif /* RCC_D3CCIPR_LPTIM2SEL */
1132 #if defined(RCC_D3CCIPR_LPTIM345SEL)
1133 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_LPTIM345SEL, RCC_D3CCIPR_LPTIM345SEL_Pos, 0x00000000U)
1134 #else
1135 #define LL_RCC_LPTIM345_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_LPTIM3SEL, RCC_SRDCCIPR_LPTIM3SEL_Pos, 0x00000000U)
1136 #define LL_RCC_LPTIM3_CLKSOURCE LL_RCC_LPTIM345_CLKSOURCE /* alias */
1137 #endif /* RCC_D3CCIPR_LPTIM345SEL */
1138 /**
1139 * @}
1140 */
1141
1142 /** @defgroup RCC_LL_EC_SAIx Peripheral SAI get clock source
1143 * @{
1144 */
1145 #if defined(RCC_D2CCIP1R_SAI1SEL)
1146 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI1SEL, RCC_D2CCIP1R_SAI1SEL_Pos, 0x00000000U)
1147 #else
1148 #define LL_RCC_SAI1_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI1SEL, RCC_CDCCIP1R_SAI1SEL_Pos, 0x00000000U)
1149 #endif /* RCC_D2CCIP1R_SAI1SEL */
1150 #if defined(RCC_D2CCIP1R_SAI23SEL)
1151 #define LL_RCC_SAI23_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SAI23SEL, RCC_D2CCIP1R_SAI23SEL_Pos, 0x00000000U)
1152 #endif /* RCC_D2CCIP1R_SAI23SEL */
1153 #if defined(RCC_CDCCIP1R_SAI2ASEL)
1154 #define LL_RCC_SAI2A_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2ASEL, RCC_CDCCIP1R_SAI2ASEL_Pos, 0x00000000U)
1155 #endif /* RCC_CDCCIP1R_SAI2ASEL */
1156 #if defined(RCC_CDCCIP1R_SAI2BSEL)
1157 #define LL_RCC_SAI2B_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SAI2BSEL, RCC_CDCCIP1R_SAI2BSEL_Pos, 0x00000000U)
1158 #endif /* RCC_CDCCIP1R_SAI2BSEL */
1159 #if defined(RCC_D3CCIPR_SAI4ASEL)
1160 #define LL_RCC_SAI4A_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4ASEL, RCC_D3CCIPR_SAI4ASEL_Pos, 0x00000000U)
1161 #endif /* RCC_D3CCIPR_SAI4ASEL */
1162 #if defined(RCC_D3CCIPR_SAI4BSEL)
1163 #define LL_RCC_SAI4B_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SAI4BSEL, RCC_D3CCIPR_SAI4BSEL_Pos, 0x00000000U)
1164 #endif /* RCC_D3CCIPR_SAI4BSEL */
1165 /**
1166 * @}
1167 */
1168
1169 /** @defgroup RCC_LL_EC_SDMMC Peripheral SDMMC get clock source
1170 * @{
1171 */
1172 #if defined(RCC_D1CCIPR_SDMMCSEL)
1173 #define LL_RCC_SDMMC_CLKSOURCE RCC_D1CCIPR_SDMMCSEL
1174 #else
1175 #define LL_RCC_SDMMC_CLKSOURCE RCC_CDCCIPR_SDMMCSEL
1176 #endif /* RCC_D1CCIPR_SDMMCSEL */
1177 /**
1178 * @}
1179 */
1180
1181 /** @defgroup RCC_LL_EC_RNG Peripheral RNG get clock source
1182 * @{
1183 */
1184 #if (RCC_D2CCIP2R_RNGSEL)
1185 #define LL_RCC_RNG_CLKSOURCE RCC_D2CCIP2R_RNGSEL
1186 #else
1187 #define LL_RCC_RNG_CLKSOURCE RCC_CDCCIP2R_RNGSEL
1188 #endif /* RCC_D2CCIP2R_RNGSEL */
1189 /**
1190 * @}
1191 */
1192
1193 /** @defgroup RCC_LL_EC_USB Peripheral USB get clock source
1194 * @{
1195 */
1196 #if (RCC_D2CCIP2R_USBSEL)
1197 #define LL_RCC_USB_CLKSOURCE RCC_D2CCIP2R_USBSEL
1198 #else
1199 #define LL_RCC_USB_CLKSOURCE RCC_CDCCIP2R_USBSEL
1200 #endif /* RCC_D2CCIP2R_USBSEL */
1201 /**
1202 * @}
1203 */
1204
1205 /** @defgroup RCC_LL_EC_CEC Peripheral CEC get clock source
1206 * @{
1207 */
1208 #if (RCC_D2CCIP2R_CECSEL)
1209 #define LL_RCC_CEC_CLKSOURCE RCC_D2CCIP2R_CECSEL
1210 #else
1211 #define LL_RCC_CEC_CLKSOURCE RCC_CDCCIP2R_CECSEL
1212 #endif /* RCC_D2CCIP2R_CECSEL */
1213 /**
1214 * @}
1215 */
1216
1217 #if defined(DSI)
1218 /** @defgroup RCC_LL_EC_DSI Peripheral DSI get clock source
1219 * @{
1220 */
1221 #define LL_RCC_DSI_CLKSOURCE RCC_D1CCIPR_DSISEL
1222 /**
1223 * @}
1224 */
1225 #endif /* DSI */
1226
1227 /** @defgroup RCC_LL_EC_DFSDM Peripheral DFSDM get clock source
1228 * @{
1229 */
1230 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
1231 #define LL_RCC_DFSDM1_CLKSOURCE RCC_D2CCIP1R_DFSDM1SEL
1232 #else
1233 #define LL_RCC_DFSDM1_CLKSOURCE RCC_CDCCIP1R_DFSDM1SEL
1234 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
1235 /**
1236 * @}
1237 */
1238
1239 #if defined(DFSDM2_BASE)
1240 /** @defgroup RCC_LL_EC_DFSDM2 Peripheral DFSDM2 get clock source
1241 * @{
1242 */
1243 #define LL_RCC_DFSDM2_CLKSOURCE RCC_SRDCCIPR_DFSDM2SEL
1244 /**
1245 * @}
1246 */
1247 #endif /* DFSDM2_BASE */
1248
1249
1250
1251 /** @defgroup RCC_LL_EC_FMC Peripheral FMC get clock source
1252 * @{
1253 */
1254 #if defined(RCC_D1CCIPR_FMCSEL)
1255 #define LL_RCC_FMC_CLKSOURCE RCC_D1CCIPR_FMCSEL
1256 #else
1257 #define LL_RCC_FMC_CLKSOURCE RCC_CDCCIPR_FMCSEL
1258 #endif
1259 /**
1260 * @}
1261 */
1262
1263 #if defined(QUADSPI)
1264 /** @defgroup RCC_LL_EC_QSPI Peripheral QSPI get clock source
1265 * @{
1266 */
1267 #define LL_RCC_QSPI_CLKSOURCE RCC_D1CCIPR_QSPISEL
1268 /**
1269 * @}
1270 */
1271 #endif /* QUADSPI */
1272
1273 #if defined(OCTOSPI1) || defined(OCTOSPI2)
1274 /** @defgroup RCC_LL_EC_OSPI Peripheral OSPI get clock source
1275 * @{
1276 */
1277 #if defined(RCC_CDCCIPR_OCTOSPISEL)
1278 #define LL_RCC_OSPI_CLKSOURCE RCC_CDCCIPR_OCTOSPISEL
1279 #else
1280 #define LL_RCC_OSPI_CLKSOURCE RCC_D1CCIPR_OCTOSPISEL
1281 #endif /* RCC_CDCCIPR_OCTOSPISEL */
1282 /**
1283 * @}
1284 */
1285 #endif /* OCTOSPI1 || OCTOSPI2 */
1286
1287 /** @defgroup RCC_LL_EC_CLKP Peripheral CLKP get clock source
1288 * @{
1289 */
1290 #if defined(RCC_D1CCIPR_CKPERSEL)
1291 #define LL_RCC_CLKP_CLKSOURCE RCC_D1CCIPR_CKPERSEL
1292 #else
1293 #define LL_RCC_CLKP_CLKSOURCE RCC_CDCCIPR_CKPERSEL
1294 #endif /* RCC_D1CCIPR_CKPERSEL */
1295 /**
1296 * @}
1297 */
1298
1299 /** @defgroup RCC_LL_EC_SPIx Peripheral SPI get clock source
1300 * @{
1301 */
1302 #if defined(RCC_D2CCIP1R_SPI123SEL)
1303 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI123SEL, RCC_D2CCIP1R_SPI123SEL_Pos, 0x00000000U)
1304 #else
1305 #define LL_RCC_SPI123_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI123SEL, RCC_CDCCIP1R_SPI123SEL_Pos, 0x00000000U)
1306 #endif /* RCC_D2CCIP1R_SPI123SEL */
1307 #if defined(RCC_D2CCIP1R_SPI45SEL)
1308 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(D2CCIP1, RCC_D2CCIP1R_SPI45SEL, RCC_D2CCIP1R_SPI45SEL_Pos, 0x00000000U)
1309 #else
1310 #define LL_RCC_SPI45_CLKSOURCE LL_CLKSOURCE(CDCCIP1, RCC_CDCCIP1R_SPI45SEL, RCC_CDCCIP1R_SPI45SEL_Pos, 0x00000000U)
1311 #endif /* RCC_D2CCIP1R_SPI45SEL */
1312 #if defined(RCC_D3CCIPR_SPI6SEL)
1313 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(D3CCIP, RCC_D3CCIPR_SPI6SEL, RCC_D3CCIPR_SPI6SEL_Pos, 0x00000000U)
1314 #else
1315 #define LL_RCC_SPI6_CLKSOURCE LL_CLKSOURCE(SRDCCIP, RCC_SRDCCIPR_SPI6SEL, RCC_SRDCCIPR_SPI6SEL_Pos, 0x00000000U)
1316 #endif /* RCC_D3CCIPR_SPI6SEL */
1317 /**
1318 * @}
1319 */
1320
1321 /** @defgroup RCC_LL_EC_SPDIF Peripheral SPDIF get clock source
1322 * @{
1323 */
1324 #if defined(RCC_D2CCIP1R_SPDIFSEL)
1325 #define LL_RCC_SPDIF_CLKSOURCE RCC_D2CCIP1R_SPDIFSEL
1326 #else
1327 #define LL_RCC_SPDIF_CLKSOURCE RCC_CDCCIP1R_SPDIFSEL
1328 #endif /* RCC_D2CCIP1R_SPDIFSEL */
1329 /**
1330 * @}
1331 */
1332
1333 #if defined(FDCAN1) || defined(FDCAN2)
1334 /** @defgroup RCC_LL_EC_FDCAN Peripheral FDCAN get clock source
1335 * @{
1336 */
1337 #if defined(RCC_D2CCIP1R_FDCANSEL)
1338 #define LL_RCC_FDCAN_CLKSOURCE RCC_D2CCIP1R_FDCANSEL
1339 #else
1340 #define LL_RCC_FDCAN_CLKSOURCE RCC_CDCCIP1R_FDCANSEL
1341 #endif
1342 /**
1343 * @}
1344 */
1345 #endif /*FDCAN1 || FDCAN2*/
1346
1347 /** @defgroup RCC_LL_EC_SWP Peripheral SWP get clock source
1348 * @{
1349 */
1350 #if defined(RCC_D2CCIP1R_SWPSEL)
1351 #define LL_RCC_SWP_CLKSOURCE RCC_D2CCIP1R_SWPSEL
1352 #else
1353 #define LL_RCC_SWP_CLKSOURCE RCC_CDCCIP1R_SWPSEL
1354 #endif /* RCC_D2CCIP1R_SWPSEL */
1355 /**
1356 * @}
1357 */
1358
1359 /** @defgroup RCC_LL_EC_ADC Peripheral ADC get clock source
1360 * @{
1361 */
1362 #if defined(RCC_D3CCIPR_ADCSEL)
1363 #define LL_RCC_ADC_CLKSOURCE RCC_D3CCIPR_ADCSEL
1364 #else
1365 #define LL_RCC_ADC_CLKSOURCE RCC_SRDCCIPR_ADCSEL
1366 #endif /* RCC_D3CCIPR_ADCSEL */
1367 /**
1368 * @}
1369 */
1370
1371 /** @defgroup RCC_LL_EC_RTC_CLKSOURCE RTC clock source selection
1372 * @{
1373 */
1374 #define LL_RCC_RTC_CLKSOURCE_NONE (uint32_t)(0x00000000U)
1375 #define LL_RCC_RTC_CLKSOURCE_LSE (uint32_t)(RCC_BDCR_RTCSEL_0)
1376 #define LL_RCC_RTC_CLKSOURCE_LSI (uint32_t)(RCC_BDCR_RTCSEL_1)
1377 #define LL_RCC_RTC_CLKSOURCE_HSE (uint32_t)(RCC_BDCR_RTCSEL_0 | RCC_BDCR_RTCSEL_1)
1378 /**
1379 * @}
1380 */
1381
1382 /** @defgroup RCC_LL_EC_TIM_CLKPRESCALER Timers clocks prescalers selection
1383 * @{
1384 */
1385 #define LL_RCC_TIM_PRESCALER_TWICE (uint32_t)(0x00000000U)
1386 #define LL_RCC_TIM_PRESCALER_FOUR_TIMES (uint32_t)(RCC_CFGR_TIMPRE)
1387 /**
1388 * @}
1389 */
1390
1391 #if defined(HRTIM1)
1392 /** @defgroup RCC_LL_EC_HRTIM_CLKSOURCE High Resolution Timers clock selection
1393 * @{
1394 */
1395 #define LL_RCC_HRTIM_CLKSOURCE_TIM (uint32_t)(0x00000000U) /* HRTIM Clock source is same as other timers */
1396 #define LL_RCC_HRTIM_CLKSOURCE_CPU (uint32_t)(RCC_CFGR_HRTIMSEL) /* HRTIM Clock source is the CPU clock */
1397 /**
1398 * @}
1399 */
1400 #endif /* HRTIM1 */
1401
1402 /** @defgroup RCC_LL_EC_PLLSOURCE All PLLs entry clock source
1403 * @{
1404 */
1405 #define LL_RCC_PLLSOURCE_HSI RCC_PLLCKSELR_PLLSRC_HSI
1406 #define LL_RCC_PLLSOURCE_CSI RCC_PLLCKSELR_PLLSRC_CSI
1407 #define LL_RCC_PLLSOURCE_HSE RCC_PLLCKSELR_PLLSRC_HSE
1408 #define LL_RCC_PLLSOURCE_NONE RCC_PLLCKSELR_PLLSRC_NONE
1409 /**
1410 * @}
1411 */
1412
1413 /** @defgroup RCC_LL_EC_PLLINPUTRANGE All PLLs input range
1414 * @{
1415 */
1416 #define LL_RCC_PLLINPUTRANGE_1_2 (uint32_t)(0x00000000U)
1417 #define LL_RCC_PLLINPUTRANGE_2_4 (uint32_t)(0x00000001)
1418 #define LL_RCC_PLLINPUTRANGE_4_8 (uint32_t)(0x00000002)
1419 #define LL_RCC_PLLINPUTRANGE_8_16 (uint32_t)(0x00000003)
1420 /**
1421 * @}
1422 */
1423
1424 /** @defgroup RCC_LL_EC_PLLVCORANGE All PLLs VCO range
1425 * @{
1426 */
1427 #define LL_RCC_PLLVCORANGE_WIDE (uint32_t)(0x00000000U) /* VCO output range: 192 to 836 MHz OR 128 to 544 MHz (*) */
1428 #define LL_RCC_PLLVCORANGE_MEDIUM (uint32_t)(0x00000001) /* VCO output range: 150 to 420 MHz */
1429 /**
1430 * (*) : For stm32h7a3xx and stm32h7b3xx family lines.
1431 * @}
1432 */
1433
1434 /**
1435 * @}
1436 */
1437
1438 /* Exported macro ------------------------------------------------------------*/
1439 /** @defgroup RCC_LL_Exported_Macros RCC Exported Macros
1440 * @{
1441 */
1442
1443 /** @defgroup RCC_LL_EM_WRITE_READ Common Write and read registers Macros
1444 * @{
1445 */
1446
1447 /**
1448 * @brief Write a value in RCC register
1449 * @param __REG__ Register to be written
1450 * @param __VALUE__ Value to be written in the register
1451 * @retval None
1452 */
1453 #define LL_RCC_WriteReg(__REG__, __VALUE__) WRITE_REG(RCC->__REG__, (__VALUE__))
1454
1455 /**
1456 * @brief Read a value in RCC register
1457 * @param __REG__ Register to be read
1458 * @retval Register value
1459 */
1460 #define LL_RCC_ReadReg(__REG__) READ_REG(RCC->__REG__)
1461 /**
1462 * @}
1463 */
1464
1465 /** @defgroup RCC_LL_EM_CALC_FREQ Calculate frequencies
1466 * @{
1467 */
1468
1469 /**
1470 * @brief Helper macro to calculate the SYSCLK frequency
1471 * @param __SYSINPUTCLKFREQ__ Frequency of the input of sys_ck (based on HSE/CSI/HSI/PLL1P)
1472 * @param __SYSPRESCALER__ This parameter can be one of the following values:
1473 * @arg @ref LL_RCC_SYSCLK_DIV_1
1474 * @arg @ref LL_RCC_SYSCLK_DIV_2
1475 * @arg @ref LL_RCC_SYSCLK_DIV_4
1476 * @arg @ref LL_RCC_SYSCLK_DIV_8
1477 * @arg @ref LL_RCC_SYSCLK_DIV_16
1478 * @arg @ref LL_RCC_SYSCLK_DIV_64
1479 * @arg @ref LL_RCC_SYSCLK_DIV_128
1480 * @arg @ref LL_RCC_SYSCLK_DIV_256
1481 * @arg @ref LL_RCC_SYSCLK_DIV_512
1482 * @retval SYSCLK clock frequency (in Hz)
1483 */
1484 #if defined(RCC_D1CFGR_D1CPRE)
1485 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_D1CFGR_D1CPRE) >> RCC_D1CFGR_D1CPRE_Pos]) & 0x1FU))
1486 #else
1487 #define LL_RCC_CALC_SYSCLK_FREQ(__SYSINPUTCLKFREQ__, __SYSPRESCALER__) ((__SYSINPUTCLKFREQ__) >> ((LL_RCC_PrescTable[((__SYSPRESCALER__) & RCC_CDCFGR1_CDCPRE) >> RCC_CDCFGR1_CDCPRE_Pos]) & 0x1FU))
1488 #endif /* RCC_D1CFGR_D1CPRE */
1489
1490 /**
1491 * @brief Helper macro to calculate the HCLK frequency
1492 * @param __SYSCLKFREQ__ SYSCLK frequency.
1493 * @param __HPRESCALER__ This parameter can be one of the following values:
1494 * @arg @ref LL_RCC_AHB_DIV_1
1495 * @arg @ref LL_RCC_AHB_DIV_2
1496 * @arg @ref LL_RCC_AHB_DIV_4
1497 * @arg @ref LL_RCC_AHB_DIV_8
1498 * @arg @ref LL_RCC_AHB_DIV_16
1499 * @arg @ref LL_RCC_AHB_DIV_64
1500 * @arg @ref LL_RCC_AHB_DIV_128
1501 * @arg @ref LL_RCC_AHB_DIV_256
1502 * @arg @ref LL_RCC_AHB_DIV_512
1503 * @retval HCLK clock frequency (in Hz)
1504 */
1505 #if defined(RCC_D1CFGR_HPRE)
1506 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_D1CFGR_HPRE) >> RCC_D1CFGR_HPRE_Pos]) & 0x1FU))
1507 #else
1508 #define LL_RCC_CALC_HCLK_FREQ(__SYSCLKFREQ__, __HPRESCALER__) ((__SYSCLKFREQ__) >> ((LL_RCC_PrescTable[((__HPRESCALER__) & RCC_CDCFGR1_HPRE) >> RCC_CDCFGR1_HPRE_Pos]) & 0x1FU))
1509 #endif /* RCC_D1CFGR_HPRE */
1510
1511 /**
1512 * @brief Helper macro to calculate the PCLK1 frequency (ABP1)
1513 * @param __HCLKFREQ__ HCLK frequency
1514 * @param __APB1PRESCALER__ This parameter can be one of the following values:
1515 * @arg @ref LL_RCC_APB1_DIV_1
1516 * @arg @ref LL_RCC_APB1_DIV_2
1517 * @arg @ref LL_RCC_APB1_DIV_4
1518 * @arg @ref LL_RCC_APB1_DIV_8
1519 * @arg @ref LL_RCC_APB1_DIV_16
1520 * @retval PCLK1 clock frequency (in Hz)
1521 */
1522 #if defined(RCC_D2CFGR_D2PPRE1)
1523 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_D2CFGR_D2PPRE1) >> RCC_D2CFGR_D2PPRE1_Pos]) & 0x1FU))
1524 #else
1525 #define LL_RCC_CALC_PCLK1_FREQ(__HCLKFREQ__, __APB1PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB1PRESCALER__) & RCC_CDCFGR2_CDPPRE1) >> RCC_CDCFGR2_CDPPRE1_Pos]) & 0x1FU))
1526 #endif /* RCC_D2CFGR_D2PPRE1 */
1527
1528 /**
1529 * @brief Helper macro to calculate the PCLK2 frequency (ABP2)
1530 * @param __HCLKFREQ__ HCLK frequency
1531 * @param __APB2PRESCALER__ This parameter can be one of the following values:
1532 * @arg @ref LL_RCC_APB2_DIV_1
1533 * @arg @ref LL_RCC_APB2_DIV_2
1534 * @arg @ref LL_RCC_APB2_DIV_4
1535 * @arg @ref LL_RCC_APB2_DIV_8
1536 * @arg @ref LL_RCC_APB2_DIV_16
1537 * @retval PCLK2 clock frequency (in Hz)
1538 */
1539 #if defined(RCC_D2CFGR_D2PPRE2)
1540 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_D2CFGR_D2PPRE2) >> RCC_D2CFGR_D2PPRE2_Pos]) & 0x1FU))
1541 #else
1542 #define LL_RCC_CALC_PCLK2_FREQ(__HCLKFREQ__, __APB2PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB2PRESCALER__) & RCC_CDCFGR2_CDPPRE2) >> RCC_CDCFGR2_CDPPRE2_Pos]) & 0x1FU))
1543 #endif /* RCC_D2CFGR_D2PPRE2 */
1544
1545 /**
1546 * @brief Helper macro to calculate the PCLK3 frequency (APB3)
1547 * @param __HCLKFREQ__ HCLK frequency
1548 * @param __APB3PRESCALER__ This parameter can be one of the following values:
1549 * @arg @ref LL_RCC_APB3_DIV_1
1550 * @arg @ref LL_RCC_APB3_DIV_2
1551 * @arg @ref LL_RCC_APB3_DIV_4
1552 * @arg @ref LL_RCC_APB3_DIV_8
1553 * @arg @ref LL_RCC_APB3_DIV_16
1554 * @retval PCLK1 clock frequency (in Hz)
1555 */
1556 #if defined(RCC_D1CFGR_D1PPRE)
1557 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_D1CFGR_D1PPRE) >> RCC_D1CFGR_D1PPRE_Pos]) & 0x1FU))
1558 #else
1559 #define LL_RCC_CALC_PCLK3_FREQ(__HCLKFREQ__, __APB3PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB3PRESCALER__) & RCC_CDCFGR1_CDPPRE) >> RCC_CDCFGR1_CDPPRE_Pos]) & 0x1FU))
1560 #endif /* RCC_D1CFGR_D1PPRE */
1561
1562 /**
1563 * @brief Helper macro to calculate the PCLK4 frequency (ABP4)
1564 * @param __HCLKFREQ__ HCLK frequency
1565 * @param __APB4PRESCALER__ This parameter can be one of the following values:
1566 * @arg @ref LL_RCC_APB4_DIV_1
1567 * @arg @ref LL_RCC_APB4_DIV_2
1568 * @arg @ref LL_RCC_APB4_DIV_4
1569 * @arg @ref LL_RCC_APB4_DIV_8
1570 * @arg @ref LL_RCC_APB4_DIV_16
1571 * @retval PCLK1 clock frequency (in Hz)
1572 */
1573 #if defined(RCC_D3CFGR_D3PPRE)
1574 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_D3CFGR_D3PPRE) >> RCC_D3CFGR_D3PPRE_Pos]) & 0x1FU))
1575 #else
1576 #define LL_RCC_CALC_PCLK4_FREQ(__HCLKFREQ__, __APB4PRESCALER__) ((__HCLKFREQ__) >> ((LL_RCC_PrescTable[((__APB4PRESCALER__) & RCC_SRDCFGR_SRDPPRE) >> RCC_SRDCFGR_SRDPPRE_Pos]) & 0x1FU))
1577 #endif /* RCC_D3CFGR_D3PPRE */
1578
1579 /**
1580 * @}
1581 */
1582
1583 #if defined(USE_FULL_LL_DRIVER)
1584 /** @defgroup RCC_LL_EC_PERIPH_FREQUENCY Peripheral clock frequency
1585 * @{
1586 */
1587 #define LL_RCC_PERIPH_FREQUENCY_NO 0x00000000U /*!< No clock enabled for the peripheral */
1588 #define LL_RCC_PERIPH_FREQUENCY_NA 0xFFFFFFFFU /*!< Frequency cannot be provided as external clock */
1589 /**
1590 * @}
1591 */
1592 #endif /* USE_FULL_LL_DRIVER */
1593
1594 /**
1595 * @}
1596 */
1597
1598 /* Exported functions --------------------------------------------------------*/
1599 /** @defgroup RCC_LL_Exported_Functions RCC Exported Functions
1600 * @{
1601 */
1602
1603 /** @defgroup RCC_LL_EF_HSE HSE
1604 * @{
1605 */
1606
1607 /**
1608 * @brief Enable the Clock Security System.
1609 * @note Once HSE Clock Security System is enabled it cannot be changed anymore unless
1610 * a reset occurs or system enter in standby mode.
1611 * @rmtoll CR CSSHSEON LL_RCC_HSE_EnableCSS
1612 * @retval None
1613 */
1614 __STATIC_INLINE void LL_RCC_HSE_EnableCSS(void)
1615 {
1616 SET_BIT(RCC->CR, RCC_CR_CSSHSEON);
1617 }
1618
1619 /**
1620 * @brief Enable HSE external oscillator (HSE Bypass)
1621 * @rmtoll CR HSEBYP LL_RCC_HSE_EnableBypass
1622 * @retval None
1623 */
1624 __STATIC_INLINE void LL_RCC_HSE_EnableBypass(void)
1625 {
1626 SET_BIT(RCC->CR, RCC_CR_HSEBYP);
1627 }
1628
1629 /**
1630 * @brief Disable HSE external oscillator (HSE Bypass)
1631 * @rmtoll CR HSEBYP LL_RCC_HSE_DisableBypass
1632 * @retval None
1633 */
1634 __STATIC_INLINE void LL_RCC_HSE_DisableBypass(void)
1635 {
1636 CLEAR_BIT(RCC->CR, RCC_CR_HSEBYP);
1637 }
1638
1639 #if defined(RCC_CR_HSEEXT)
1640 /**
1641 * @brief Select the Analog HSE external clock type in Bypass mode
1642 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectAnalogClock
1643 * @retval None
1644 */
1645 __STATIC_INLINE void LL_RCC_HSE_SelectAnalogClock(void)
1646 {
1647 CLEAR_BIT(RCC->CR, RCC_CR_HSEEXT);
1648 }
1649
1650 /**
1651 * @brief Select the Digital HSE external clock type in Bypass mode
1652 * @rmtoll CR HSEEXT LL_RCC_HSE_SelectDigitalClock
1653 * @retval None
1654 */
1655 __STATIC_INLINE void LL_RCC_HSE_SelectDigitalClock(void)
1656 {
1657 SET_BIT(RCC->CR, RCC_CR_HSEEXT);
1658 }
1659 #endif /* RCC_CR_HSEEXT */
1660
1661 /**
1662 * @brief Enable HSE crystal oscillator (HSE ON)
1663 * @rmtoll CR HSEON LL_RCC_HSE_Enable
1664 * @retval None
1665 */
1666 __STATIC_INLINE void LL_RCC_HSE_Enable(void)
1667 {
1668 SET_BIT(RCC->CR, RCC_CR_HSEON);
1669 }
1670
1671 /**
1672 * @brief Disable HSE crystal oscillator (HSE ON)
1673 * @rmtoll CR HSEON LL_RCC_HSE_Disable
1674 * @retval None
1675 */
1676 __STATIC_INLINE void LL_RCC_HSE_Disable(void)
1677 {
1678 CLEAR_BIT(RCC->CR, RCC_CR_HSEON);
1679 }
1680
1681 /**
1682 * @brief Check if HSE oscillator Ready
1683 * @rmtoll CR HSERDY LL_RCC_HSE_IsReady
1684 * @retval State of bit (1 or 0).
1685 */
1686 __STATIC_INLINE uint32_t LL_RCC_HSE_IsReady(void)
1687 {
1688 return ((READ_BIT(RCC->CR, RCC_CR_HSERDY) == (RCC_CR_HSERDY)) ? 1UL : 0UL);
1689 }
1690
1691 /**
1692 * @}
1693 */
1694
1695 /** @defgroup RCC_LL_EF_HSI HSI
1696 * @{
1697 */
1698
1699 /**
1700 * @brief Enable HSI oscillator
1701 * @rmtoll CR HSION LL_RCC_HSI_Enable
1702 * @retval None
1703 */
1704 __STATIC_INLINE void LL_RCC_HSI_Enable(void)
1705 {
1706 SET_BIT(RCC->CR, RCC_CR_HSION);
1707 }
1708
1709 /**
1710 * @brief Disable HSI oscillator
1711 * @rmtoll CR HSION LL_RCC_HSI_Disable
1712 * @retval None
1713 */
1714 __STATIC_INLINE void LL_RCC_HSI_Disable(void)
1715 {
1716 CLEAR_BIT(RCC->CR, RCC_CR_HSION);
1717 }
1718
1719 /**
1720 * @brief Check if HSI clock is ready
1721 * @rmtoll CR HSIRDY LL_RCC_HSI_IsReady
1722 * @retval State of bit (1 or 0).
1723 */
1724 __STATIC_INLINE uint32_t LL_RCC_HSI_IsReady(void)
1725 {
1726 return ((READ_BIT(RCC->CR, RCC_CR_HSIRDY) == (RCC_CR_HSIRDY)) ? 1UL : 0UL);
1727 }
1728
1729 /**
1730 * @brief Check if HSI new divider applied and ready
1731 * @rmtoll CR HSIDIVF LL_RCC_HSI_IsDividerReady
1732 * @retval State of bit (1 or 0).
1733 */
1734 __STATIC_INLINE uint32_t LL_RCC_HSI_IsDividerReady(void)
1735 {
1736 return ((READ_BIT(RCC->CR, RCC_CR_HSIDIVF) == (RCC_CR_HSIDIVF)) ? 1UL : 0UL);
1737 }
1738
1739 /**
1740 * @brief Set HSI divider
1741 * @rmtoll CR HSIDIV LL_RCC_HSI_SetDivider
1742 * @param Divider This parameter can be one of the following values:
1743 * @arg @ref LL_RCC_HSI_DIV1
1744 * @arg @ref LL_RCC_HSI_DIV2
1745 * @arg @ref LL_RCC_HSI_DIV4
1746 * @arg @ref LL_RCC_HSI_DIV8
1747 * @retval None.
1748 */
1749 __STATIC_INLINE void LL_RCC_HSI_SetDivider(uint32_t Divider)
1750 {
1751 MODIFY_REG(RCC->CR, RCC_CR_HSIDIV, Divider);
1752 }
1753
1754 /**
1755 * @brief Get HSI divider
1756 * @rmtoll CR HSIDIV LL_RCC_HSI_GetDivider
1757 * @retval can be one of the following values:
1758 * @arg @ref LL_RCC_HSI_DIV1
1759 * @arg @ref LL_RCC_HSI_DIV2
1760 * @arg @ref LL_RCC_HSI_DIV4
1761 * @arg @ref LL_RCC_HSI_DIV8
1762 */
1763 __STATIC_INLINE uint32_t LL_RCC_HSI_GetDivider(void)
1764 {
1765 return (READ_BIT(RCC->CR, RCC_CR_HSIDIV));
1766 }
1767
1768 /**
1769 * @brief Enable HSI oscillator in Stop mode
1770 * @rmtoll CR HSIKERON LL_RCC_HSI_EnableStopMode
1771 * @retval None
1772 */
1773 __STATIC_INLINE void LL_RCC_HSI_EnableStopMode(void)
1774 {
1775 SET_BIT(RCC->CR, RCC_CR_HSIKERON);
1776 }
1777
1778 /**
1779 * @brief Disable HSI oscillator in Stop mode
1780 * @rmtoll CR HSION LL_RCC_HSI_DisableStopMode
1781 * @retval None
1782 */
1783 __STATIC_INLINE void LL_RCC_HSI_DisableStopMode(void)
1784 {
1785 CLEAR_BIT(RCC->CR, RCC_CR_HSIKERON);
1786 }
1787
1788 /**
1789 * @brief Get HSI Calibration value
1790 * @note When HSITRIM is written, HSICAL is updated with the sum of
1791 * HSITRIM and the factory trim value
1792 * @rmtoll HSICFGR HSICAL LL_RCC_HSI_GetCalibration
1793 * @retval A value between 0 and 4095 (0xFFF)
1794 */
1795 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibration(void)
1796 {
1797 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSICAL) >> RCC_HSICFGR_HSICAL_Pos);
1798 }
1799
1800 /**
1801 * @brief Set HSI Calibration trimming
1802 * @note user-programmable trimming value that is added to the HSICAL
1803 * @note Default value is 64 (32 for Cut1.x), which, when added to the HSICAL value,
1804 * should trim the HSI to 64 MHz +/- 1 %
1805 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_SetCalibTrimming
1806 * @param Value can be a value between 0 and 127 (63 for Cut1.x)
1807 * @retval None
1808 */
1809 __STATIC_INLINE void LL_RCC_HSI_SetCalibTrimming(uint32_t Value)
1810 {
1811 #if defined(RCC_VER_X)
1812 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1813 {
1814 /* STM32H7 Rev.Y */
1815 MODIFY_REG(RCC->HSICFGR, 0x3F000U, Value << 12U);
1816 }
1817 else
1818 {
1819 /* STM32H7 Rev.V */
1820 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1821 }
1822 #else
1823 MODIFY_REG(RCC->HSICFGR, RCC_HSICFGR_HSITRIM, Value << RCC_HSICFGR_HSITRIM_Pos);
1824 #endif /* RCC_VER_X */
1825 }
1826
1827 /**
1828 * @brief Get HSI Calibration trimming
1829 * @rmtoll HSICFGR HSITRIM LL_RCC_HSI_GetCalibTrimming
1830 * @retval A value between 0 and 127 (63 for Cut1.x)
1831 */
1832 __STATIC_INLINE uint32_t LL_RCC_HSI_GetCalibTrimming(void)
1833 {
1834 #if defined(RCC_VER_X)
1835 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1836 {
1837 /* STM32H7 Rev.Y */
1838 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3F000U) >> 12U);
1839 }
1840 else
1841 {
1842 /* STM32H7 Rev.V */
1843 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1844 }
1845 #else
1846 return (uint32_t)(READ_BIT(RCC->HSICFGR, RCC_HSICFGR_HSITRIM) >> RCC_HSICFGR_HSITRIM_Pos);
1847 #endif /* RCC_VER_X */
1848 }
1849
1850 /**
1851 * @}
1852 */
1853
1854 /** @defgroup RCC_LL_EF_CSI CSI
1855 * @{
1856 */
1857
1858 /**
1859 * @brief Enable CSI oscillator
1860 * @rmtoll CR CSION LL_RCC_CSI_Enable
1861 * @retval None
1862 */
1863 __STATIC_INLINE void LL_RCC_CSI_Enable(void)
1864 {
1865 SET_BIT(RCC->CR, RCC_CR_CSION);
1866 }
1867
1868 /**
1869 * @brief Disable CSI oscillator
1870 * @rmtoll CR CSION LL_RCC_CSI_Disable
1871 * @retval None
1872 */
1873 __STATIC_INLINE void LL_RCC_CSI_Disable(void)
1874 {
1875 CLEAR_BIT(RCC->CR, RCC_CR_CSION);
1876 }
1877
1878 /**
1879 * @brief Check if CSI clock is ready
1880 * @rmtoll CR CSIRDY LL_RCC_CSI_IsReady
1881 * @retval State of bit (1 or 0).
1882 */
1883 __STATIC_INLINE uint32_t LL_RCC_CSI_IsReady(void)
1884 {
1885 return ((READ_BIT(RCC->CR, RCC_CR_CSIRDY) == (RCC_CR_CSIRDY)) ? 1UL : 0UL);
1886 }
1887
1888 /**
1889 * @brief Enable CSI oscillator in Stop mode
1890 * @rmtoll CR CSIKERON LL_RCC_CSI_EnableStopMode
1891 * @retval None
1892 */
1893 __STATIC_INLINE void LL_RCC_CSI_EnableStopMode(void)
1894 {
1895 SET_BIT(RCC->CR, RCC_CR_CSIKERON);
1896 }
1897
1898 /**
1899 * @brief Disable CSI oscillator in Stop mode
1900 * @rmtoll CR CSIKERON LL_RCC_CSI_DisableStopMode
1901 * @retval None
1902 */
1903 __STATIC_INLINE void LL_RCC_CSI_DisableStopMode(void)
1904 {
1905 CLEAR_BIT(RCC->CR, RCC_CR_CSIKERON);
1906 }
1907
1908 /**
1909 * @brief Get CSI Calibration value
1910 * @note When CSITRIM is written, CSICAL is updated with the sum of
1911 * CSITRIM and the factory trim value
1912 * @rmtoll CSICFGR CSICAL LL_RCC_CSI_GetCalibration
1913 * @retval A value between 0 and 255 (0xFF)
1914 */
1915 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibration(void)
1916 {
1917 #if defined(RCC_VER_X)
1918 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1919 {
1920 /* STM32H7 Rev.Y */
1921 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x3FC0000U) >> 18U);
1922 }
1923 else
1924 {
1925 /* STM32H7 Rev.V */
1926 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1927 }
1928 #else
1929 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSICAL) >> RCC_CSICFGR_CSICAL_Pos);
1930 #endif /* RCC_VER_X */
1931 }
1932
1933 /**
1934 * @brief Set CSI Calibration trimming
1935 * @note user-programmable trimming value that is added to the CSICAL
1936 * @note Default value is 16, which, when added to the CSICAL value,
1937 * should trim the CSI to 4 MHz +/- 1 %
1938 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_SetCalibTrimming
1939 * @param Value can be a value between 0 and 31
1940 * @retval None
1941 */
1942 __STATIC_INLINE void LL_RCC_CSI_SetCalibTrimming(uint32_t Value)
1943 {
1944 #if defined(RCC_VER_X)
1945 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1946 {
1947 /* STM32H7 Rev.Y */
1948 MODIFY_REG(RCC->HSICFGR, 0x7C000000U, Value << 26U);
1949 }
1950 else
1951 {
1952 /* STM32H7 Rev.V */
1953 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1954 }
1955 #else
1956 MODIFY_REG(RCC->CSICFGR, RCC_CSICFGR_CSITRIM, Value << RCC_CSICFGR_CSITRIM_Pos);
1957 #endif /* RCC_VER_X */
1958 }
1959
1960 /**
1961 * @brief Get CSI Calibration trimming
1962 * @rmtoll CSICFGR CSITRIM LL_RCC_CSI_GetCalibTrimming
1963 * @retval A value between 0 and 31
1964 */
1965 __STATIC_INLINE uint32_t LL_RCC_CSI_GetCalibTrimming(void)
1966 {
1967 #if defined(RCC_VER_X)
1968 if ((DBGMCU->IDCODE & 0xF0000000U) == 0x10000000U)
1969 {
1970 /* STM32H7 Rev.Y */
1971 return (uint32_t)(READ_BIT(RCC->HSICFGR, 0x7C000000U) >> 26U);
1972 }
1973 else
1974 {
1975 /* STM32H7 Rev.V */
1976 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1977 }
1978 #else
1979 return (uint32_t)(READ_BIT(RCC->CSICFGR, RCC_CSICFGR_CSITRIM) >> RCC_CSICFGR_CSITRIM_Pos);
1980 #endif /* RCC_VER_X */
1981 }
1982
1983 /**
1984 * @}
1985 */
1986
1987 /** @defgroup RCC_LL_EF_HSI48 HSI48
1988 * @{
1989 */
1990
1991 /**
1992 * @brief Enable HSI48 oscillator
1993 * @rmtoll CR HSI48ON LL_RCC_HSI48_Enable
1994 * @retval None
1995 */
1996 __STATIC_INLINE void LL_RCC_HSI48_Enable(void)
1997 {
1998 SET_BIT(RCC->CR, RCC_CR_HSI48ON);
1999 }
2000
2001 /**
2002 * @brief Disable HSI48 oscillator
2003 * @rmtoll CR HSI48ON LL_RCC_HSI48_Disable
2004 * @retval None
2005 */
2006 __STATIC_INLINE void LL_RCC_HSI48_Disable(void)
2007 {
2008 CLEAR_BIT(RCC->CR, RCC_CR_HSI48ON);
2009 }
2010
2011 /**
2012 * @brief Check if HSI48 clock is ready
2013 * @rmtoll CR HSI48RDY LL_RCC_HSI48_IsReady
2014 * @retval State of bit (1 or 0).
2015 */
2016 __STATIC_INLINE uint32_t LL_RCC_HSI48_IsReady(void)
2017 {
2018 return ((READ_BIT(RCC->CR, RCC_CR_HSI48RDY) == (RCC_CR_HSI48RDY)) ? 1UL : 0UL);
2019 }
2020
2021 /**
2022 * @brief Get HSI48 Calibration value
2023 * @note When HSI48TRIM is written, HSI48CAL is updated with the sum of
2024 * HSI48TRIM and the factory trim value
2025 * @rmtoll CRRCR HSI48CAL LL_RCC_HSI48_GetCalibration
2026 * @retval A value between 0 and 1023 (0x3FF)
2027 */
2028 __STATIC_INLINE uint32_t LL_RCC_HSI48_GetCalibration(void)
2029 {
2030 return (uint32_t)(READ_BIT(RCC->CRRCR, RCC_CRRCR_HSI48CAL) >> RCC_CRRCR_HSI48CAL_Pos);
2031 }
2032 /**
2033 * @}
2034 */
2035
2036 #if defined(RCC_CR_D1CKRDY)
2037
2038 /** @defgroup RCC_LL_EF_D1CLK D1CKREADY
2039 * @{
2040 */
2041
2042 /**
2043 * @brief Check if D1 clock is ready
2044 * @rmtoll CR D1CKRDY LL_RCC_D1CK_IsReady
2045 * @retval State of bit (1 or 0).
2046 */
2047 __STATIC_INLINE uint32_t LL_RCC_D1CK_IsReady(void)
2048 {
2049 return ((READ_BIT(RCC->CR, RCC_CR_D1CKRDY) == (RCC_CR_D1CKRDY)) ? 1UL : 0UL);
2050 }
2051
2052 /**
2053 * @}
2054 */
2055 #else
2056
2057 /** @defgroup RCC_LL_EF_CPUCLK CPUCKREADY
2058 * @{
2059 */
2060
2061 /**
2062 * @brief Check if CPU clock is ready
2063 * @rmtoll CR CPUCKRDY LL_RCC_CPUCK_IsReady
2064 * @retval State of bit (1 or 0).
2065 */
2066 __STATIC_INLINE uint32_t LL_RCC_CPUCK_IsReady(void)
2067 {
2068 return ((READ_BIT(RCC->CR, RCC_CR_CPUCKRDY) == (RCC_CR_CPUCKRDY)) ? 1UL : 0UL);
2069 }
2070 /* alias */
2071 #define LL_RCC_D1CK_IsReady LL_RCC_CPUCK_IsReady
2072 /**
2073 * @}
2074 */
2075 #endif /* RCC_CR_D1CKRDY */
2076
2077 #if defined(RCC_CR_D2CKRDY)
2078
2079 /** @defgroup RCC_LL_EF_D2CLK D2CKREADY
2080 * @{
2081 */
2082
2083 /**
2084 * @brief Check if D2 clock is ready
2085 * @rmtoll CR D2CKRDY LL_RCC_D2CK_IsReady
2086 * @retval State of bit (1 or 0).
2087 */
2088 __STATIC_INLINE uint32_t LL_RCC_D2CK_IsReady(void)
2089 {
2090 return ((READ_BIT(RCC->CR, RCC_CR_D2CKRDY) == (RCC_CR_D2CKRDY)) ? 1UL : 0UL);
2091 }
2092 /**
2093 * @}
2094 */
2095 #else
2096
2097 /** @defgroup RCC_LL_EF_CDCLK CDCKREADY
2098 * @{
2099 */
2100
2101 /**
2102 * @brief Check if CD clock is ready
2103 * @rmtoll CR CDCKRDY LL_RCC_CDCK_IsReady
2104 * @retval State of bit (1 or 0).
2105 */
2106 __STATIC_INLINE uint32_t LL_RCC_CDCK_IsReady(void)
2107 {
2108 return ((READ_BIT(RCC->CR, RCC_CR_CDCKRDY) == (RCC_CR_CDCKRDY)) ? 1UL : 0UL);
2109 }
2110 #define LL_RCC_D2CK_IsReady LL_RCC_CDCK_IsReady
2111 /**
2112 * @}
2113 */
2114 #endif /* RCC_CR_D2CKRDY */
2115
2116 /** @defgroup RCC_LL_EF_SYSTEM_WIDE_RESET RESET
2117 * @{
2118 */
2119 #if defined(RCC_GCR_WW1RSC)
2120
2121 /**
2122 * @brief Enable system wide reset for Window Watch Dog 1
2123 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_EnableSystemReset
2124 * @retval None.
2125 */
2126 __STATIC_INLINE void LL_RCC_WWDG1_EnableSystemReset(void)
2127 {
2128 SET_BIT(RCC->GCR, RCC_GCR_WW1RSC);
2129 }
2130
2131 /**
2132 * @brief Check if Window Watch Dog 1 reset is system wide
2133 * @rmtoll GCR WW1RSC LL_RCC_WWDG1_IsSystemReset
2134 * @retval State of bit (1 or 0).
2135 */
2136 __STATIC_INLINE uint32_t LL_RCC_WWDG1_IsSystemReset(void)
2137 {
2138 return ((READ_BIT(RCC->GCR, RCC_GCR_WW1RSC) == RCC_GCR_WW1RSC) ? 1UL : 0UL);
2139 }
2140 #endif /* RCC_GCR_WW1RSC */
2141
2142 #if defined(DUAL_CORE)
2143 /**
2144 * @brief Enable system wide reset for Window Watch Dog 2
2145 * @rmtoll GCR WW1RSC LL_RCC_WWDG2_EnableSystemReset
2146 * @retval None.
2147 */
2148 __STATIC_INLINE void LL_RCC_WWDG2_EnableSystemReset(void)
2149 {
2150 SET_BIT(RCC->GCR, RCC_GCR_WW2RSC);
2151 }
2152
2153 /**
2154 * @brief Check if Window Watch Dog 2 reset is system wide
2155 * @rmtoll GCR WW2RSC LL_RCC_WWDG2_IsSystemReset
2156 * @retval State of bit (1 or 0).
2157 */
2158 __STATIC_INLINE uint32_t LL_RCC_WWDG2_IsSystemReset(void)
2159 {
2160 return ((READ_BIT(RCC->GCR, RCC_GCR_WW2RSC) == RCC_GCR_WW2RSC) ? 1UL : 0UL);
2161 }
2162 #endif /*DUAL_CORE*/
2163 /**
2164 * @}
2165 */
2166
2167 #if defined(DUAL_CORE)
2168 /** @defgroup RCC_LL_EF_BOOT_CPU CPU
2169 * @{
2170 */
2171
2172 /**
2173 * @brief Force CM4 boot (if hold by option byte BCM4 = 0)
2174 * @rmtoll GCR BOOT_C2 LL_RCC_ForceCM4Boot
2175 * @retval None.
2176 */
2177 __STATIC_INLINE void LL_RCC_ForceCM4Boot(void)
2178 {
2179 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C2);
2180 }
2181
2182 /**
2183 * @brief Check if CM4 boot is forced
2184 * @rmtoll GCR BOOT_C2 LL_RCC_IsCM4BootForced
2185 * @retval State of bit (1 or 0).
2186 */
2187 __STATIC_INLINE uint32_t LL_RCC_IsCM4BootForced(void)
2188 {
2189 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C2) == RCC_GCR_BOOT_C2) ? 1UL : 0UL);
2190 }
2191
2192 /**
2193 * @brief Force CM7 boot (if hold by option byte BCM7 = 0)
2194 * @rmtoll GCR BOOT_C1 LL_RCC_ForceCM7Boot
2195 * @retval None.
2196 */
2197 __STATIC_INLINE void LL_RCC_ForceCM7Boot(void)
2198 {
2199 SET_BIT(RCC->GCR, RCC_GCR_BOOT_C1);
2200 }
2201
2202 /**
2203 * @brief Check if CM7 boot is forced
2204 * @rmtoll GCR BOOT_C1 LL_RCC_IsCM7BootForced
2205 * @retval State of bit (1 or 0).
2206 */
2207 __STATIC_INLINE uint32_t LL_RCC_IsCM7BootForced(void)
2208 {
2209 return ((READ_BIT(RCC->GCR, RCC_GCR_BOOT_C1) == RCC_GCR_BOOT_C1) ? 1UL : 0UL);
2210 }
2211
2212 /**
2213 * @}
2214 */
2215 #endif /*DUAL_CORE*/
2216
2217 /** @defgroup RCC_LL_EF_LSE LSE
2218 * @{
2219 */
2220
2221 /**
2222 * @brief Enable the Clock Security System on LSE.
2223 * @note Once LSE Clock Security System is enabled it cannot be changed anymore unless
2224 * a clock failure is detected.
2225 * @rmtoll BDCR LSECSSON LL_RCC_LSE_EnableCSS
2226 * @retval None
2227 */
2228 __STATIC_INLINE void LL_RCC_LSE_EnableCSS(void)
2229 {
2230 SET_BIT(RCC->BDCR, RCC_BDCR_LSECSSON);
2231 }
2232
2233 /**
2234 * @brief Check if LSE failure is detected by Clock Security System
2235 * @rmtoll BDCR LSECSSD LL_RCC_LSE_IsFailureDetected
2236 * @retval State of bit (1 or 0).
2237 */
2238 __STATIC_INLINE uint32_t LL_RCC_LSE_IsFailureDetected(void)
2239 {
2240 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSECSSD) == (RCC_BDCR_LSECSSD)) ? 1UL : 0UL);
2241 }
2242
2243 /**
2244 * @brief Enable Low Speed External (LSE) crystal.
2245 * @rmtoll BDCR LSEON LL_RCC_LSE_Enable
2246 * @retval None
2247 */
2248 __STATIC_INLINE void LL_RCC_LSE_Enable(void)
2249 {
2250 SET_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2251 }
2252
2253 /**
2254 * @brief Disable Low Speed External (LSE) crystal.
2255 * @rmtoll BDCR LSEON LL_RCC_LSE_Disable
2256 * @retval None
2257 */
2258 __STATIC_INLINE void LL_RCC_LSE_Disable(void)
2259 {
2260 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEON);
2261 }
2262
2263 /**
2264 * @brief Enable external clock source (LSE bypass).
2265 * @rmtoll BDCR LSEBYP LL_RCC_LSE_EnableBypass
2266 * @retval None
2267 */
2268 __STATIC_INLINE void LL_RCC_LSE_EnableBypass(void)
2269 {
2270 SET_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2271 }
2272
2273 /**
2274 * @brief Disable external clock source (LSE bypass).
2275 * @rmtoll BDCR LSEBYP LL_RCC_LSE_DisableBypass
2276 * @retval None
2277 */
2278 __STATIC_INLINE void LL_RCC_LSE_DisableBypass(void)
2279 {
2280 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEBYP);
2281 }
2282
2283 #if defined(RCC_BDCR_LSEEXT)
2284 /**
2285 * @brief Enable Low-speed external DIGITAL clock type in Bypass mode (not to be used if RTC is active).
2286 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2287 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2288 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectDigitalClock
2289 * @retval None
2290 */
2291 __STATIC_INLINE void LL_RCC_LSE_SelectDigitalClock(void)
2292 {
2293 SET_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2294 }
2295
2296 /**
2297 * @brief Enable Low-speed external ANALOG clock type in Bypass mode (default after Backup domain reset).
2298 * @note The external clock must be enabled with the LSEON bit, to be used by the device.
2299 * The LSEEXT bit can be written only if the LSE oscillator is disabled.
2300 * @rmtoll BDCR LSEEXT LL_RCC_LSE_SelectAnalogClock
2301 * @retval None
2302 */
2303 __STATIC_INLINE void LL_RCC_LSE_SelectAnalogClock(void)
2304 {
2305 CLEAR_BIT(RCC->BDCR, RCC_BDCR_LSEEXT);
2306 }
2307 #endif /* RCC_BDCR_LSEEXT */
2308
2309 /**
2310 * @brief Set LSE oscillator drive capability
2311 * @note The oscillator is in Xtal mode when it is not in bypass mode.
2312 * @rmtoll BDCR LSEDRV LL_RCC_LSE_SetDriveCapability
2313 * @param LSEDrive This parameter can be one of the following values:
2314 * @arg @ref LL_RCC_LSEDRIVE_LOW
2315 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2316 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2317 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2318 * @retval None
2319 */
2320 __STATIC_INLINE void LL_RCC_LSE_SetDriveCapability(uint32_t LSEDrive)
2321 {
2322 MODIFY_REG(RCC->BDCR, RCC_BDCR_LSEDRV, LSEDrive);
2323 }
2324
2325 /**
2326 * @brief Get LSE oscillator drive capability
2327 * @rmtoll BDCR LSEDRV LL_RCC_LSE_GetDriveCapability
2328 * @retval Returned value can be one of the following values:
2329 * @arg @ref LL_RCC_LSEDRIVE_LOW
2330 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMLOW
2331 * @arg @ref LL_RCC_LSEDRIVE_MEDIUMHIGH
2332 * @arg @ref LL_RCC_LSEDRIVE_HIGH
2333 */
2334 __STATIC_INLINE uint32_t LL_RCC_LSE_GetDriveCapability(void)
2335 {
2336 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_LSEDRV));
2337 }
2338
2339 /**
2340 * @brief Check if LSE oscillator Ready
2341 * @rmtoll BDCR LSERDY LL_RCC_LSE_IsReady
2342 * @retval State of bit (1 or 0).
2343 */
2344 __STATIC_INLINE uint32_t LL_RCC_LSE_IsReady(void)
2345 {
2346 return ((READ_BIT(RCC->BDCR, RCC_BDCR_LSERDY) == (RCC_BDCR_LSERDY)) ? 1UL : 0UL);
2347 }
2348
2349 /**
2350 * @}
2351 */
2352
2353 /** @defgroup RCC_LL_EF_LSI LSI
2354 * @{
2355 */
2356
2357 /**
2358 * @brief Enable LSI Oscillator
2359 * @rmtoll CSR LSION LL_RCC_LSI_Enable
2360 * @retval None
2361 */
2362 __STATIC_INLINE void LL_RCC_LSI_Enable(void)
2363 {
2364 SET_BIT(RCC->CSR, RCC_CSR_LSION);
2365 }
2366
2367 /**
2368 * @brief Disable LSI Oscillator
2369 * @rmtoll CSR LSION LL_RCC_LSI_Disable
2370 * @retval None
2371 */
2372 __STATIC_INLINE void LL_RCC_LSI_Disable(void)
2373 {
2374 CLEAR_BIT(RCC->CSR, RCC_CSR_LSION);
2375 }
2376
2377 /**
2378 * @brief Check if LSI is Ready
2379 * @rmtoll CSR LSIRDY LL_RCC_LSI_IsReady
2380 * @retval State of bit (1 or 0).
2381 */
2382 __STATIC_INLINE uint32_t LL_RCC_LSI_IsReady(void)
2383 {
2384 return ((READ_BIT(RCC->CSR, RCC_CSR_LSIRDY) == (RCC_CSR_LSIRDY)) ? 1UL : 0UL);
2385 }
2386
2387 /**
2388 * @}
2389 */
2390
2391 /** @defgroup RCC_LL_EF_System System
2392 * @{
2393 */
2394
2395 /**
2396 * @brief Configure the system clock source
2397 * @rmtoll CFGR SW LL_RCC_SetSysClkSource
2398 * @param Source This parameter can be one of the following values:
2399 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSI
2400 * @arg @ref LL_RCC_SYS_CLKSOURCE_CSI
2401 * @arg @ref LL_RCC_SYS_CLKSOURCE_HSE
2402 * @arg @ref LL_RCC_SYS_CLKSOURCE_PLL1
2403 * @retval None
2404 */
2405 __STATIC_INLINE void LL_RCC_SetSysClkSource(uint32_t Source)
2406 {
2407 MODIFY_REG(RCC->CFGR, RCC_CFGR_SW, Source);
2408 }
2409
2410 /**
2411 * @brief Get the system clock source
2412 * @rmtoll CFGR SWS LL_RCC_GetSysClkSource
2413 * @retval Returned value can be one of the following values:
2414 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSI
2415 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_CSI
2416 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_HSE
2417 * @arg @ref LL_RCC_SYS_CLKSOURCE_STATUS_PLL1
2418 */
2419 __STATIC_INLINE uint32_t LL_RCC_GetSysClkSource(void)
2420 {
2421 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_SWS));
2422 }
2423
2424 /**
2425 * @brief Configure the system wakeup clock source
2426 * @rmtoll CFGR STOPWUCK LL_RCC_SetSysWakeUpClkSource
2427 * @param Source This parameter can be one of the following values:
2428 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2429 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2430 * @retval None
2431 */
2432 __STATIC_INLINE void LL_RCC_SetSysWakeUpClkSource(uint32_t Source)
2433 {
2434 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPWUCK, Source);
2435 }
2436
2437 /**
2438 * @brief Get the system wakeup clock source
2439 * @rmtoll CFGR STOPWUCK LL_RCC_GetSysWakeUpClkSource
2440 * @retval Returned value can be one of the following values:
2441 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_HSI
2442 * @arg @ref LL_RCC_SYSWAKEUP_CLKSOURCE_CSI
2443 */
2444 __STATIC_INLINE uint32_t LL_RCC_GetSysWakeUpClkSource(void)
2445 {
2446 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPWUCK));
2447 }
2448
2449 /**
2450 * @brief Configure the kernel wakeup clock source
2451 * @rmtoll CFGR STOPKERWUCK LL_RCC_SetKerWakeUpClkSource
2452 * @param Source This parameter can be one of the following values:
2453 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2454 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2455 * @retval None
2456 */
2457 __STATIC_INLINE void LL_RCC_SetKerWakeUpClkSource(uint32_t Source)
2458 {
2459 MODIFY_REG(RCC->CFGR, RCC_CFGR_STOPKERWUCK, Source);
2460 }
2461
2462 /**
2463 * @brief Get the kernel wakeup clock source
2464 * @rmtoll CFGR STOPKERWUCK LL_RCC_GetKerWakeUpClkSource
2465 * @retval Returned value can be one of the following values:
2466 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_HSI
2467 * @arg @ref LL_RCC_KERWAKEUP_CLKSOURCE_CSI
2468 */
2469 __STATIC_INLINE uint32_t LL_RCC_GetKerWakeUpClkSource(void)
2470 {
2471 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_STOPKERWUCK));
2472 }
2473
2474 /**
2475 * @brief Set System prescaler
2476 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_SetSysPrescaler
2477 * @param Prescaler This parameter can be one of the following values:
2478 * @arg @ref LL_RCC_SYSCLK_DIV_1
2479 * @arg @ref LL_RCC_SYSCLK_DIV_2
2480 * @arg @ref LL_RCC_SYSCLK_DIV_4
2481 * @arg @ref LL_RCC_SYSCLK_DIV_8
2482 * @arg @ref LL_RCC_SYSCLK_DIV_16
2483 * @arg @ref LL_RCC_SYSCLK_DIV_64
2484 * @arg @ref LL_RCC_SYSCLK_DIV_128
2485 * @arg @ref LL_RCC_SYSCLK_DIV_256
2486 * @arg @ref LL_RCC_SYSCLK_DIV_512
2487 * @retval None
2488 */
2489 __STATIC_INLINE void LL_RCC_SetSysPrescaler(uint32_t Prescaler)
2490 {
2491 #if defined(RCC_D1CFGR_D1CPRE)
2492 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1CPRE, Prescaler);
2493 #else
2494 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE, Prescaler);
2495 #endif /* RCC_D1CFGR_D1CPRE */
2496 }
2497
2498 /**
2499 * @brief Set AHB prescaler
2500 * @rmtoll D1CFGR/CDCFGR1 HPRE LL_RCC_SetAHBPrescaler
2501 * @param Prescaler This parameter can be one of the following values:
2502 * @arg @ref LL_RCC_AHB_DIV_1
2503 * @arg @ref LL_RCC_AHB_DIV_2
2504 * @arg @ref LL_RCC_AHB_DIV_4
2505 * @arg @ref LL_RCC_AHB_DIV_8
2506 * @arg @ref LL_RCC_AHB_DIV_16
2507 * @arg @ref LL_RCC_AHB_DIV_64
2508 * @arg @ref LL_RCC_AHB_DIV_128
2509 * @arg @ref LL_RCC_AHB_DIV_256
2510 * @arg @ref LL_RCC_AHB_DIV_512
2511 * @retval None
2512 */
2513 __STATIC_INLINE void LL_RCC_SetAHBPrescaler(uint32_t Prescaler)
2514 {
2515 #if defined(RCC_D1CFGR_HPRE)
2516 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_HPRE, Prescaler);
2517 #else
2518 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_HPRE, Prescaler);
2519 #endif /* RCC_D1CFGR_HPRE */
2520 }
2521
2522 /**
2523 * @brief Set APB1 prescaler
2524 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_SetAPB1Prescaler
2525 * @param Prescaler This parameter can be one of the following values:
2526 * @arg @ref LL_RCC_APB1_DIV_1
2527 * @arg @ref LL_RCC_APB1_DIV_2
2528 * @arg @ref LL_RCC_APB1_DIV_4
2529 * @arg @ref LL_RCC_APB1_DIV_8
2530 * @arg @ref LL_RCC_APB1_DIV_16
2531 * @retval None
2532 */
2533 __STATIC_INLINE void LL_RCC_SetAPB1Prescaler(uint32_t Prescaler)
2534 {
2535 #if defined(RCC_D2CFGR_D2PPRE1)
2536 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1, Prescaler);
2537 #else
2538 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1, Prescaler);
2539 #endif /* RCC_D2CFGR_D2PPRE1 */
2540 }
2541
2542 /**
2543 * @brief Set APB2 prescaler
2544 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_SetAPB2Prescaler
2545 * @param Prescaler This parameter can be one of the following values:
2546 * @arg @ref LL_RCC_APB2_DIV_1
2547 * @arg @ref LL_RCC_APB2_DIV_2
2548 * @arg @ref LL_RCC_APB2_DIV_4
2549 * @arg @ref LL_RCC_APB2_DIV_8
2550 * @arg @ref LL_RCC_APB2_DIV_16
2551 * @retval None
2552 */
2553 __STATIC_INLINE void LL_RCC_SetAPB2Prescaler(uint32_t Prescaler)
2554 {
2555 #if defined(RCC_D2CFGR_D2PPRE2)
2556 MODIFY_REG(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2, Prescaler);
2557 #else
2558 MODIFY_REG(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2, Prescaler);
2559 #endif /* RCC_D2CFGR_D2PPRE2 */
2560 }
2561
2562 /**
2563 * @brief Set APB3 prescaler
2564 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_SetAPB3Prescaler
2565 * @param Prescaler This parameter can be one of the following values:
2566 * @arg @ref LL_RCC_APB3_DIV_1
2567 * @arg @ref LL_RCC_APB3_DIV_2
2568 * @arg @ref LL_RCC_APB3_DIV_4
2569 * @arg @ref LL_RCC_APB3_DIV_8
2570 * @arg @ref LL_RCC_APB3_DIV_16
2571 * @retval None
2572 */
2573 __STATIC_INLINE void LL_RCC_SetAPB3Prescaler(uint32_t Prescaler)
2574 {
2575 #if defined(RCC_D1CFGR_D1PPRE)
2576 MODIFY_REG(RCC->D1CFGR, RCC_D1CFGR_D1PPRE, Prescaler);
2577 #else
2578 MODIFY_REG(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE, Prescaler);
2579 #endif /* RCC_D1CFGR_D1PPRE */
2580 }
2581
2582 /**
2583 * @brief Set APB4 prescaler
2584 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_SetAPB4Prescaler
2585 * @param Prescaler This parameter can be one of the following values:
2586 * @arg @ref LL_RCC_APB4_DIV_1
2587 * @arg @ref LL_RCC_APB4_DIV_2
2588 * @arg @ref LL_RCC_APB4_DIV_4
2589 * @arg @ref LL_RCC_APB4_DIV_8
2590 * @arg @ref LL_RCC_APB4_DIV_16
2591 * @retval None
2592 */
2593 __STATIC_INLINE void LL_RCC_SetAPB4Prescaler(uint32_t Prescaler)
2594 {
2595 #if defined(RCC_D3CFGR_D3PPRE)
2596 MODIFY_REG(RCC->D3CFGR, RCC_D3CFGR_D3PPRE, Prescaler);
2597 #else
2598 MODIFY_REG(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE, Prescaler);
2599 #endif /* RCC_D3CFGR_D3PPRE */
2600 }
2601
2602 /**
2603 * @brief Get System prescaler
2604 * @rmtoll D1CFGR/CDCFGR1 D1CPRE/CDCPRE LL_RCC_GetSysPrescaler
2605 * @retval Returned value can be one of the following values:
2606 * @arg @ref LL_RCC_SYSCLK_DIV_1
2607 * @arg @ref LL_RCC_SYSCLK_DIV_2
2608 * @arg @ref LL_RCC_SYSCLK_DIV_4
2609 * @arg @ref LL_RCC_SYSCLK_DIV_8
2610 * @arg @ref LL_RCC_SYSCLK_DIV_16
2611 * @arg @ref LL_RCC_SYSCLK_DIV_64
2612 * @arg @ref LL_RCC_SYSCLK_DIV_128
2613 * @arg @ref LL_RCC_SYSCLK_DIV_256
2614 * @arg @ref LL_RCC_SYSCLK_DIV_512
2615 */
2616 __STATIC_INLINE uint32_t LL_RCC_GetSysPrescaler(void)
2617 {
2618 #if defined(RCC_D1CFGR_D1CPRE)
2619 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1CPRE));
2620 #else
2621 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDCPRE));
2622 #endif /* RCC_D1CFGR_D1CPRE */
2623 }
2624
2625 /**
2626 * @brief Get AHB prescaler
2627 * @rmtoll D1CFGR/ CDCFGR1 HPRE LL_RCC_GetAHBPrescaler
2628 * @retval Returned value can be one of the following values:
2629 * @arg @ref LL_RCC_AHB_DIV_1
2630 * @arg @ref LL_RCC_AHB_DIV_2
2631 * @arg @ref LL_RCC_AHB_DIV_4
2632 * @arg @ref LL_RCC_AHB_DIV_8
2633 * @arg @ref LL_RCC_AHB_DIV_16
2634 * @arg @ref LL_RCC_AHB_DIV_64
2635 * @arg @ref LL_RCC_AHB_DIV_128
2636 * @arg @ref LL_RCC_AHB_DIV_256
2637 * @arg @ref LL_RCC_AHB_DIV_512
2638 */
2639 __STATIC_INLINE uint32_t LL_RCC_GetAHBPrescaler(void)
2640 {
2641 #if defined(RCC_D1CFGR_HPRE)
2642 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_HPRE));
2643 #else
2644 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_HPRE));
2645 #endif /* RCC_D1CFGR_HPRE */
2646 }
2647
2648 /**
2649 * @brief Get APB1 prescaler
2650 * @rmtoll D2CFGR/CDCFGR2 D2PPRE1/CDPPRE1 LL_RCC_GetAPB1Prescaler
2651 * @retval Returned value can be one of the following values:
2652 * @arg @ref LL_RCC_APB1_DIV_1
2653 * @arg @ref LL_RCC_APB1_DIV_2
2654 * @arg @ref LL_RCC_APB1_DIV_4
2655 * @arg @ref LL_RCC_APB1_DIV_8
2656 * @arg @ref LL_RCC_APB1_DIV_16
2657 */
2658 __STATIC_INLINE uint32_t LL_RCC_GetAPB1Prescaler(void)
2659 {
2660 #if defined(RCC_D2CFGR_D2PPRE1)
2661 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE1));
2662 #else
2663 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE1));
2664 #endif /* RCC_D2CFGR_D2PPRE1 */
2665 }
2666
2667 /**
2668 * @brief Get APB2 prescaler
2669 * @rmtoll D2CFGR/CDCFGR2 D2PPRE2/CDPPRE2 LL_RCC_GetAPB2Prescaler
2670 * @retval Returned value can be one of the following values:
2671 * @arg @ref LL_RCC_APB2_DIV_1
2672 * @arg @ref LL_RCC_APB2_DIV_2
2673 * @arg @ref LL_RCC_APB2_DIV_4
2674 * @arg @ref LL_RCC_APB2_DIV_8
2675 * @arg @ref LL_RCC_APB2_DIV_16
2676 */
2677 __STATIC_INLINE uint32_t LL_RCC_GetAPB2Prescaler(void)
2678 {
2679 #if defined(RCC_D2CFGR_D2PPRE2)
2680 return (uint32_t)(READ_BIT(RCC->D2CFGR, RCC_D2CFGR_D2PPRE2));
2681 #else
2682 return (uint32_t)(READ_BIT(RCC->CDCFGR2, RCC_CDCFGR2_CDPPRE2));
2683 #endif /* RCC_D2CFGR_D2PPRE2 */
2684 }
2685
2686 /**
2687 * @brief Get APB3 prescaler
2688 * @rmtoll D1CFGR/CDCFGR1 D1PPRE/CDPPRE LL_RCC_GetAPB3Prescaler
2689 * @retval Returned value can be one of the following values:
2690 * @arg @ref LL_RCC_APB3_DIV_1
2691 * @arg @ref LL_RCC_APB3_DIV_2
2692 * @arg @ref LL_RCC_APB3_DIV_4
2693 * @arg @ref LL_RCC_APB3_DIV_8
2694 * @arg @ref LL_RCC_APB3_DIV_16
2695 */
2696 __STATIC_INLINE uint32_t LL_RCC_GetAPB3Prescaler(void)
2697 {
2698 #if defined(RCC_D1CFGR_D1PPRE)
2699 return (uint32_t)(READ_BIT(RCC->D1CFGR, RCC_D1CFGR_D1PPRE));
2700 #else
2701 return (uint32_t)(READ_BIT(RCC->CDCFGR1, RCC_CDCFGR1_CDPPRE));
2702 #endif /* RCC_D1CFGR_D1PPRE */
2703 }
2704
2705 /**
2706 * @brief Get APB4 prescaler
2707 * @rmtoll D3CFGR/SRDCFGR D3PPRE/SRDPPRE LL_RCC_GetAPB4Prescaler
2708 * @retval Returned value can be one of the following values:
2709 * @arg @ref LL_RCC_APB4_DIV_1
2710 * @arg @ref LL_RCC_APB4_DIV_2
2711 * @arg @ref LL_RCC_APB4_DIV_4
2712 * @arg @ref LL_RCC_APB4_DIV_8
2713 * @arg @ref LL_RCC_APB4_DIV_16
2714 */
2715 __STATIC_INLINE uint32_t LL_RCC_GetAPB4Prescaler(void)
2716 {
2717 #if defined(RCC_D3CFGR_D3PPRE)
2718 return (uint32_t)(READ_BIT(RCC->D3CFGR, RCC_D3CFGR_D3PPRE));
2719 #else
2720 return (uint32_t)(READ_BIT(RCC->SRDCFGR, RCC_SRDCFGR_SRDPPRE));
2721 #endif /* RCC_D3CFGR_D3PPRE */
2722 }
2723
2724 /**
2725 * @}
2726 */
2727
2728 /** @defgroup RCC_LL_EF_MCO MCO
2729 * @{
2730 */
2731
2732 /**
2733 * @brief Configure MCOx
2734 * @rmtoll CFGR MCO1 LL_RCC_ConfigMCO\n
2735 * CFGR MCO1PRE LL_RCC_ConfigMCO\n
2736 * CFGR MCO2 LL_RCC_ConfigMCO\n
2737 * CFGR MCO2PRE LL_RCC_ConfigMCO
2738 * @param MCOxSource This parameter can be one of the following values:
2739 * @arg @ref LL_RCC_MCO1SOURCE_HSI
2740 * @arg @ref LL_RCC_MCO1SOURCE_LSE
2741 * @arg @ref LL_RCC_MCO1SOURCE_HSE
2742 * @arg @ref LL_RCC_MCO1SOURCE_PLL1QCLK
2743 * @arg @ref LL_RCC_MCO1SOURCE_HSI48
2744 * @arg @ref LL_RCC_MCO2SOURCE_SYSCLK
2745 * @arg @ref LL_RCC_MCO2SOURCE_PLL2PCLK
2746 * @arg @ref LL_RCC_MCO2SOURCE_HSE
2747 * @arg @ref LL_RCC_MCO2SOURCE_PLL1PCLK
2748 * @arg @ref LL_RCC_MCO2SOURCE_CSI
2749 * @arg @ref LL_RCC_MCO2SOURCE_LSI
2750 * @param MCOxPrescaler This parameter can be one of the following values:
2751 * @arg @ref LL_RCC_MCO1_DIV_1
2752 * @arg @ref LL_RCC_MCO1_DIV_2
2753 * @arg @ref LL_RCC_MCO1_DIV_3
2754 * @arg @ref LL_RCC_MCO1_DIV_4
2755 * @arg @ref LL_RCC_MCO1_DIV_5
2756 * @arg @ref LL_RCC_MCO1_DIV_6
2757 * @arg @ref LL_RCC_MCO1_DIV_7
2758 * @arg @ref LL_RCC_MCO1_DIV_8
2759 * @arg @ref LL_RCC_MCO1_DIV_9
2760 * @arg @ref LL_RCC_MCO1_DIV_10
2761 * @arg @ref LL_RCC_MCO1_DIV_11
2762 * @arg @ref LL_RCC_MCO1_DIV_12
2763 * @arg @ref LL_RCC_MCO1_DIV_13
2764 * @arg @ref LL_RCC_MCO1_DIV_14
2765 * @arg @ref LL_RCC_MCO1_DIV_15
2766 * @arg @ref LL_RCC_MCO2_DIV_1
2767 * @arg @ref LL_RCC_MCO2_DIV_2
2768 * @arg @ref LL_RCC_MCO2_DIV_3
2769 * @arg @ref LL_RCC_MCO2_DIV_4
2770 * @arg @ref LL_RCC_MCO2_DIV_5
2771 * @arg @ref LL_RCC_MCO2_DIV_6
2772 * @arg @ref LL_RCC_MCO2_DIV_7
2773 * @arg @ref LL_RCC_MCO2_DIV_8
2774 * @arg @ref LL_RCC_MCO2_DIV_9
2775 * @arg @ref LL_RCC_MCO2_DIV_10
2776 * @arg @ref LL_RCC_MCO2_DIV_11
2777 * @arg @ref LL_RCC_MCO2_DIV_12
2778 * @arg @ref LL_RCC_MCO2_DIV_13
2779 * @arg @ref LL_RCC_MCO2_DIV_14
2780 * @arg @ref LL_RCC_MCO2_DIV_15
2781 * @retval None
2782 */
2783 __STATIC_INLINE void LL_RCC_ConfigMCO(uint32_t MCOxSource, uint32_t MCOxPrescaler)
2784 {
2785 MODIFY_REG(RCC->CFGR, (MCOxSource << 16U) | (MCOxPrescaler << 16U), (MCOxSource & 0xFFFF0000U) | (MCOxPrescaler & 0xFFFF0000U));
2786 }
2787
2788 /**
2789 * @}
2790 */
2791
2792 /** @defgroup RCC_LL_EF_Peripheral_Clock_Source Peripheral Clock Source
2793 * @{
2794 */
2795
2796 /**
2797 * @brief Configure periph clock source
2798 * @rmtoll D2CCIP1R/CDCCIP1R * LL_RCC_SetClockSource\n
2799 * D2CCIP2R/CDCCIP2R * LL_RCC_SetClockSource\n
2800 * D3CCIPR/SRDCCIPR * LL_RCC_SetClockSource
2801 * @param ClkSource This parameter can be one of the following values:
2802 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2803 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2804 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2805 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2806 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2807 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2808 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2809 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2810 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2811 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2812 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2813 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2814 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2815 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2816 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2817 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2818 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2819 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2820 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2821 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2822 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2823 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2824 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2825 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2826 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2827 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2828 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2829 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2830 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2831 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2832 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2833 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2834 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2835 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2836 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2837 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2838 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2839 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2840 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
2841 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
2842 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
2843 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
2844 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
2845 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
2846 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
2847 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
2848 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
2849 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
2850 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
2851 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
2852 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
2853 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
2854 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
2855 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
2856 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
2857 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
2858 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
2859 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
2860 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
2861 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
2862 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
2863 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
2864 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
2865 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
2866 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
2867 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
2868 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
2869 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
2870 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
2871 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
2872 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
2873 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
2874 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
2875 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
2876 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
2877 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
2878 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
2879 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
2880 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
2881 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
2882 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
2883 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
2884 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
2885 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
2886 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
2887 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
2888 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
2889 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
2890 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
2891 *
2892 * (*) value not defined in all devices.
2893 * @retval None
2894 */
2895 __STATIC_INLINE void LL_RCC_SetClockSource(uint32_t ClkSource)
2896 {
2897 #if defined(RCC_D1CCIPR_FMCSEL)
2898 uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->D1CCIPR + LL_CLKSOURCE_REG(ClkSource));
2899 #else
2900 uint32_t *pReg = (uint32_t *)((uint32_t)&RCC->CDCCIPR + LL_CLKSOURCE_REG(ClkSource));
2901 #endif /* */
2902 MODIFY_REG(*pReg, LL_CLKSOURCE_MASK(ClkSource), LL_CLKSOURCE_CONFIG(ClkSource));
2903 }
2904
2905 /**
2906 * @brief Configure USARTx clock source
2907 * @rmtoll D2CCIP2R / D2CCIP2R USART16SEL LL_RCC_SetUSARTClockSource\n
2908 * D2CCIP2R / D2CCIP2R USART28SEL LL_RCC_SetUSARTClockSource
2909 * @param ClkSource This parameter can be one of the following values:
2910 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
2911 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
2912 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
2913 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
2914 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
2915 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
2916 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
2917 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
2918 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
2919 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
2920 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
2921 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
2922 * @retval None
2923 */
2924 __STATIC_INLINE void LL_RCC_SetUSARTClockSource(uint32_t ClkSource)
2925 {
2926 LL_RCC_SetClockSource(ClkSource);
2927 }
2928
2929 /**
2930 * @brief Configure LPUARTx clock source
2931 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_SetLPUARTClockSource
2932 * @param ClkSource This parameter can be one of the following values:
2933 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
2934 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
2935 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
2936 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
2937 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
2938 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
2939 * @retval None
2940 */
2941 __STATIC_INLINE void LL_RCC_SetLPUARTClockSource(uint32_t ClkSource)
2942 {
2943 #if defined(RCC_D3CCIPR_LPUART1SEL)
2944 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL, ClkSource);
2945 #else
2946 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL, ClkSource);
2947 #endif /* RCC_D3CCIPR_LPUART1SEL */
2948 }
2949
2950 /**
2951 * @brief Configure I2Cx clock source
2952 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_SetI2CClockSource\n
2953 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_SetI2CClockSource
2954 * @param ClkSource This parameter can be one of the following values:
2955 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
2956 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
2957 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
2958 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
2959 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
2960 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
2961 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
2962 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
2963 * @retval None
2964 */
2965 __STATIC_INLINE void LL_RCC_SetI2CClockSource(uint32_t ClkSource)
2966 {
2967 LL_RCC_SetClockSource(ClkSource);
2968 }
2969
2970 /**
2971 * @brief Configure LPTIMx clock source
2972 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_SetLPTIMClockSource
2973 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_SetLPTIMClockSource\n
2974 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_SetLPTIMClockSource
2975 * @param ClkSource This parameter can be one of the following values:
2976 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
2977 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
2978 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
2979 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
2980 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
2981 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
2982 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
2983 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
2984 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
2985 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
2986 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
2987 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
2988 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
2989 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
2990 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
2991 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
2992 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
2993 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
2994 * @retval None
2995 */
2996 __STATIC_INLINE void LL_RCC_SetLPTIMClockSource(uint32_t ClkSource)
2997 {
2998 LL_RCC_SetClockSource(ClkSource);
2999 }
3000
3001 /**
3002 * @brief Configure SAIx clock source
3003 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_SetSAIClockSource\n
3004 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_SetSAIClockSource
3005 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_SetSAI4xClockSource\n
3006 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_SetSAI4xClockSource
3007 * @param ClkSource This parameter can be one of the following values:
3008 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3009 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3010 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3011 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3012 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3013 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3014 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3015 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3016 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3017 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3018 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3019 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3020 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3021 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3022 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_SPDIF (*)
3023 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3024 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3025 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3026 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3027 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3028 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3029 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3030 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3031 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3032 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3033 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3034 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_SPDIF (*)
3035 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3036 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3037 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3038 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3039 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3040 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3041 *
3042 * (*) value not defined in all devices.
3043 * @retval None
3044 */
3045 __STATIC_INLINE void LL_RCC_SetSAIClockSource(uint32_t ClkSource)
3046 {
3047 LL_RCC_SetClockSource(ClkSource);
3048 }
3049
3050 /**
3051 * @brief Configure SDMMCx clock source
3052 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_SetSDMMCClockSource
3053 * @param ClkSource This parameter can be one of the following values:
3054 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3055 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3056 * @retval None
3057 */
3058 __STATIC_INLINE void LL_RCC_SetSDMMCClockSource(uint32_t ClkSource)
3059 {
3060 #if defined(RCC_D1CCIPR_SDMMCSEL)
3061 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL, ClkSource);
3062 #else
3063 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL, ClkSource);
3064 #endif /* RCC_D1CCIPR_SDMMCSEL */
3065 }
3066
3067 /**
3068 * @brief Configure RNGx clock source
3069 * @rmtoll D2CCIP2R / CDCCIP2R RNGSEL LL_RCC_SetRNGClockSource
3070 * @param ClkSource This parameter can be one of the following values:
3071 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3072 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3073 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3074 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3075 * @retval None
3076 */
3077 __STATIC_INLINE void LL_RCC_SetRNGClockSource(uint32_t ClkSource)
3078 {
3079 #if defined(RCC_D2CCIP2R_RNGSEL)
3080 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL, ClkSource);
3081 #else
3082 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL, ClkSource);
3083 #endif /* RCC_D2CCIP2R_RNGSEL */
3084 }
3085
3086 /**
3087 * @brief Configure USBx clock source
3088 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_SetUSBClockSource
3089 * @param ClkSource This parameter can be one of the following values:
3090 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3091 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3092 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3093 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3094 * @retval None
3095 */
3096 __STATIC_INLINE void LL_RCC_SetUSBClockSource(uint32_t ClkSource)
3097 {
3098 #if defined(RCC_D2CCIP2R_USBSEL)
3099 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL, ClkSource);
3100 #else
3101 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL, ClkSource);
3102 #endif /* RCC_D2CCIP2R_USBSEL */
3103 }
3104
3105 /**
3106 * @brief Configure CECx clock source
3107 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_SetCECClockSource
3108 * @param ClkSource This parameter can be one of the following values:
3109 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3110 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3111 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3112 * @retval None
3113 */
3114 __STATIC_INLINE void LL_RCC_SetCECClockSource(uint32_t ClkSource)
3115 {
3116 #if defined(RCC_D2CCIP2R_CECSEL)
3117 MODIFY_REG(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL, ClkSource);
3118 #else
3119 MODIFY_REG(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL, ClkSource);
3120 #endif /* RCC_D2CCIP2R_CECSEL */
3121 }
3122
3123 #if defined(DSI)
3124 /**
3125 * @brief Configure DSIx clock source
3126 * @rmtoll D1CCIPR DSISEL LL_RCC_SetDSIClockSource
3127 * @param ClkSource This parameter can be one of the following values:
3128 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3129 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3130 * @retval None
3131 */
3132 __STATIC_INLINE void LL_RCC_SetDSIClockSource(uint32_t ClkSource)
3133 {
3134 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL, ClkSource);
3135 }
3136 #endif /* DSI */
3137
3138 /**
3139 * @brief Configure DFSDMx Kernel clock source
3140 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_SetDFSDMClockSource
3141 * @param ClkSource This parameter can be one of the following values:
3142 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3143 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3144 * @retval None
3145 */
3146 __STATIC_INLINE void LL_RCC_SetDFSDMClockSource(uint32_t ClkSource)
3147 {
3148 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3149 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL, ClkSource);
3150 #else
3151 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL, ClkSource);
3152 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3153 }
3154
3155 #if defined(DFSDM2_BASE)
3156 /**
3157 * @brief Configure DFSDMx Kernel clock source
3158 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_SetDFSDM2ClockSource
3159 * @param ClkSource This parameter can be one of the following values:
3160 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3161 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3162 * @retval None
3163 */
3164 __STATIC_INLINE void LL_RCC_SetDFSDM2ClockSource(uint32_t ClkSource)
3165 {
3166 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL, ClkSource);
3167 }
3168 #endif /* DFSDM2_BASE */
3169
3170 /**
3171 * @brief Configure FMCx Kernel clock source
3172 * @rmtoll D1CCIPR / CDCCIPR FMCSEL LL_RCC_SetFMCClockSource
3173 * @param ClkSource This parameter can be one of the following values:
3174 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3175 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3176 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3177 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3178 * @retval None
3179 */
3180 __STATIC_INLINE void LL_RCC_SetFMCClockSource(uint32_t ClkSource)
3181 {
3182 #if defined(RCC_D1CCIPR_FMCSEL)
3183 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL, ClkSource);
3184 #else
3185 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL, ClkSource);
3186 #endif /* RCC_D1CCIPR_FMCSEL */
3187 }
3188
3189 #if defined(QUADSPI)
3190 /**
3191 * @brief Configure QSPIx Kernel clock source
3192 * @rmtoll D1CCIPR QSPISEL LL_RCC_SetQSPIClockSource
3193 * @param ClkSource This parameter can be one of the following values:
3194 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3195 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3196 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3197 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3198 * @retval None
3199 */
3200 __STATIC_INLINE void LL_RCC_SetQSPIClockSource(uint32_t ClkSource)
3201 {
3202 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL, ClkSource);
3203 }
3204 #endif /* QUADSPI */
3205
3206 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3207 /**
3208 * @brief Configure OSPIx Kernel clock source
3209 * @rmtoll D1CCIPR OPISEL LL_RCC_SetOSPIClockSource
3210 * @param ClkSource This parameter can be one of the following values:
3211 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3212 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3213 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3214 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3215 * @retval None
3216 */
3217 __STATIC_INLINE void LL_RCC_SetOSPIClockSource(uint32_t ClkSource)
3218 {
3219 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3220 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL, ClkSource);
3221 #else
3222 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL, ClkSource);
3223 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3224 }
3225 #endif /* OCTOSPI1 || OCTOSPI2 */
3226
3227 /**
3228 * @brief Configure CLKP Kernel clock source
3229 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_SetCLKPClockSource
3230 * @param ClkSource This parameter can be one of the following values:
3231 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3232 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3233 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3234 * @retval None
3235 */
3236 __STATIC_INLINE void LL_RCC_SetCLKPClockSource(uint32_t ClkSource)
3237 {
3238 #if defined(RCC_D1CCIPR_CKPERSEL)
3239 MODIFY_REG(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL, ClkSource);
3240 #else
3241 MODIFY_REG(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL, ClkSource);
3242 #endif /* RCC_D1CCIPR_CKPERSEL */
3243 }
3244
3245 /**
3246 * @brief Configure SPIx Kernel clock source
3247 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_SetSPIClockSource\n
3248 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_SetSPIClockSource\n
3249 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_SetSPIClockSource
3250 * @param ClkSource This parameter can be one of the following values:
3251 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3252 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3253 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3254 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3255 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3256 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3257 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3258 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3259 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3260 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3261 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3262 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3263 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3264 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3265 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3266 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3267 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3268 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3269 *
3270 * (*) value not defined in all devices.
3271 * @retval None
3272 */
3273 __STATIC_INLINE void LL_RCC_SetSPIClockSource(uint32_t ClkSource)
3274 {
3275 LL_RCC_SetClockSource(ClkSource);
3276 }
3277
3278 /**
3279 * @brief Configure SPDIFx Kernel clock source
3280 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_SetSPDIFClockSource
3281 * @param ClkSource This parameter can be one of the following values:
3282 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3283 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3284 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3285 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3286 * @retval None
3287 */
3288 __STATIC_INLINE void LL_RCC_SetSPDIFClockSource(uint32_t ClkSource)
3289 {
3290 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3291 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL, ClkSource);
3292 #else
3293 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL, ClkSource);
3294 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3295 }
3296
3297 /**
3298 * @brief Configure FDCANx Kernel clock source
3299 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_SetFDCANClockSource
3300 * @param ClkSource This parameter can be one of the following values:
3301 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3302 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3303 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3304 * @retval None
3305 */
3306 __STATIC_INLINE void LL_RCC_SetFDCANClockSource(uint32_t ClkSource)
3307 {
3308 #if defined(RCC_D2CCIP1R_FDCANSEL)
3309 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL, ClkSource);
3310 #else
3311 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL, ClkSource);
3312 #endif /* RCC_D2CCIP1R_FDCANSEL */
3313 }
3314
3315 /**
3316 * @brief Configure SWPx Kernel clock source
3317 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_SetSWPClockSource
3318 * @param ClkSource This parameter can be one of the following values:
3319 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3320 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3321 * @retval None
3322 */
3323 __STATIC_INLINE void LL_RCC_SetSWPClockSource(uint32_t ClkSource)
3324 {
3325 #if defined(RCC_D2CCIP1R_SWPSEL)
3326 MODIFY_REG(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL, ClkSource);
3327 #else
3328 MODIFY_REG(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL, ClkSource);
3329 #endif /* RCC_D2CCIP1R_SWPSEL */
3330 }
3331
3332 /**
3333 * @brief Configure ADCx Kernel clock source
3334 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_SetADCClockSource
3335 * @param ClkSource This parameter can be one of the following values:
3336 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3337 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3338 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3339 * @retval None
3340 */
3341 __STATIC_INLINE void LL_RCC_SetADCClockSource(uint32_t ClkSource)
3342 {
3343 #if defined(RCC_D3CCIPR_ADCSEL)
3344 MODIFY_REG(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL, ClkSource);
3345 #else
3346 MODIFY_REG(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL, ClkSource);
3347 #endif /* RCC_D3CCIPR_ADCSEL */
3348 }
3349
3350 /**
3351 * @brief Get periph clock source
3352 * @rmtoll D1CCIPR / CDCCIPR * LL_RCC_GetClockSource\n
3353 * D2CCIP1R / CDCCIP1R * LL_RCC_GetClockSource\n
3354 * D2CCIP2R / CDCCIP2R * LL_RCC_GetClockSource\n
3355 * D3CCIPR / SRDCCIPR * LL_RCC_GetClockSource
3356 * @param Periph This parameter can be one of the following values:
3357 * @arg @ref LL_RCC_USART16_CLKSOURCE
3358 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3359 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3360 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3361 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3362 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3363 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3364 * @arg @ref LL_RCC_SAI1_CLKSOURCE
3365 * @arg @ref LL_RCC_SAI23_CLKSOURCE
3366 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3367 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3368 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3369 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3370 * @arg @ref LL_RCC_SPI123_CLKSOURCE (*)
3371 * @arg @ref LL_RCC_SPI45_CLKSOURCE (*)
3372 * @arg @ref LL_RCC_SPI6_CLKSOURCE (*)
3373 * @retval Returned value can be one of the following values:
3374 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3375 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3376 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3377 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3378 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3379 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3380 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3381 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3382 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3383 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3384 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3385 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3386 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3387 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3388 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3389 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3390 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3391 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3392 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3393 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3394 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3395 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3396 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3397 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3398 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3399 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3400 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3401 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3402 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3403 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3404 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3405 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3406 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3407 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3408 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3409 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3410 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3411 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3412 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3413 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3414 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3415 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3416 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3417 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3418 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3419 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3420 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3421 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3422 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3423 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3424 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3425 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3426 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3427 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3428 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3429 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3430 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3431 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3432 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3433 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3434 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3435 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3436 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3437 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3438 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3439 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3440 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3441 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3442 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3443 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3444 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3445 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3446 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3447 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3448 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3449 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3450 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3451 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3452 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3453 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3454 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3455 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3456 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3457 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3458 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3459 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3460 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3461 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3462 *
3463 * (*) value not defined in all devices.
3464 * @retval None
3465 */
3466 __STATIC_INLINE uint32_t LL_RCC_GetClockSource(uint32_t Periph)
3467 {
3468 #if defined(RCC_D1CCIPR_FMCSEL)
3469 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->D1CCIPR) + LL_CLKSOURCE_REG(Periph)));
3470 #else
3471 const uint32_t *pReg = (uint32_t *)((uint32_t)((uint32_t)(&RCC->CDCCIPR) + LL_CLKSOURCE_REG(Periph)));
3472 #endif /* RCC_D1CCIPR_FMCSEL */
3473 return (uint32_t)(Periph | (((READ_BIT(*pReg, LL_CLKSOURCE_MASK(Periph))) >> LL_CLKSOURCE_SHIFT(Periph)) << LL_RCC_CONFIG_SHIFT));
3474 }
3475
3476 /**
3477 * @brief Get USARTx clock source
3478 * @rmtoll D2CCIP2R / CDCCIP2R USART16SEL LL_RCC_GetUSARTClockSource\n
3479 * D2CCIP2R / CDCCIP2R USART28SEL LL_RCC_GetUSARTClockSource
3480 * @param Periph This parameter can be one of the following values:
3481 * @arg @ref LL_RCC_USART16_CLKSOURCE
3482 * @arg @ref LL_RCC_USART234578_CLKSOURCE
3483 * @retval Returned value can be one of the following values:
3484 * @arg @ref LL_RCC_USART16_CLKSOURCE_PCLK2
3485 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL2Q
3486 * @arg @ref LL_RCC_USART16_CLKSOURCE_PLL3Q
3487 * @arg @ref LL_RCC_USART16_CLKSOURCE_HSI
3488 * @arg @ref LL_RCC_USART16_CLKSOURCE_CSI
3489 * @arg @ref LL_RCC_USART16_CLKSOURCE_LSE
3490 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PCLK1
3491 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL2Q
3492 * @arg @ref LL_RCC_USART234578_CLKSOURCE_PLL3Q
3493 * @arg @ref LL_RCC_USART234578_CLKSOURCE_HSI
3494 * @arg @ref LL_RCC_USART234578_CLKSOURCE_CSI
3495 * @arg @ref LL_RCC_USART234578_CLKSOURCE_LSE
3496 */
3497 __STATIC_INLINE uint32_t LL_RCC_GetUSARTClockSource(uint32_t Periph)
3498 {
3499 return LL_RCC_GetClockSource(Periph);
3500 }
3501
3502 /**
3503 * @brief Get LPUART clock source
3504 * @rmtoll D3CCIPR / SRDCCIPR LPUART1SEL LL_RCC_GetLPUARTClockSource
3505 * @param Periph This parameter can be one of the following values:
3506 * @arg @ref LL_RCC_LPUART1_CLKSOURCE
3507 * @retval Returned value can be one of the following values:
3508 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PCLK4
3509 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL2Q
3510 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_PLL3Q
3511 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_HSI
3512 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_CSI
3513 * @arg @ref LL_RCC_LPUART1_CLKSOURCE_LSE
3514 */
3515 __STATIC_INLINE uint32_t LL_RCC_GetLPUARTClockSource(uint32_t Periph)
3516 {
3517 UNUSED(Periph);
3518 #if defined(RCC_D3CCIPR_LPUART1SEL)
3519 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_LPUART1SEL));
3520 #else
3521 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_LPUART1SEL));
3522 #endif /* RCC_D3CCIPR_LPUART1SEL */
3523 }
3524
3525 /**
3526 * @brief Get I2Cx clock source
3527 * @rmtoll D2CCIP2R / CDCCIP2R I2C123SEL LL_RCC_GetI2CClockSource\n
3528 * D3CCIPR / SRDCCIPR I2C4SEL LL_RCC_GetI2CClockSource
3529 * @param Periph This parameter can be one of the following values:
3530 * @arg @ref LL_RCC_I2C123_CLKSOURCE
3531 * @arg @ref LL_RCC_I2C4_CLKSOURCE
3532 * @retval Returned value can be one of the following values:
3533 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PCLK1
3534 * @arg @ref LL_RCC_I2C123_CLKSOURCE_PLL3R
3535 * @arg @ref LL_RCC_I2C123_CLKSOURCE_HSI
3536 * @arg @ref LL_RCC_I2C123_CLKSOURCE_CSI
3537 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PCLK4
3538 * @arg @ref LL_RCC_I2C4_CLKSOURCE_PLL3R
3539 * @arg @ref LL_RCC_I2C4_CLKSOURCE_HSI
3540 * @arg @ref LL_RCC_I2C4_CLKSOURCE_CSI
3541 */
3542 __STATIC_INLINE uint32_t LL_RCC_GetI2CClockSource(uint32_t Periph)
3543 {
3544 return LL_RCC_GetClockSource(Periph);
3545 }
3546
3547 /**
3548 * @brief Get LPTIM clock source
3549 * @rmtoll D2CCIP2R / CDCCIP2R LPTIM1SEL LL_RCC_GetLPTIMClockSource\n
3550 * D3CCIPR / SRDCCIPR LPTIM2SEL LL_RCC_GetLPTIMClockSource\n
3551 * D3CCIPR / SRDCCIPR LPTIM345SEL LL_RCC_GetLPTIMClockSource
3552 * @param Periph This parameter can be one of the following values:
3553 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE
3554 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE
3555 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE
3556 * @retval Returned value can be one of the following values:
3557 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PCLK1
3558 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL2P
3559 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_PLL3R
3560 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSE
3561 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_LSI
3562 * @arg @ref LL_RCC_LPTIM1_CLKSOURCE_CLKP
3563 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PCLK4
3564 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL2P
3565 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_PLL3R
3566 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSE
3567 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_LSI
3568 * @arg @ref LL_RCC_LPTIM2_CLKSOURCE_CLKP
3569 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PCLK4
3570 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL2P
3571 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_PLL3R
3572 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSE
3573 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_LSI
3574 * @arg @ref LL_RCC_LPTIM345_CLKSOURCE_CLKP
3575 * @retval None
3576 */
3577 __STATIC_INLINE uint32_t LL_RCC_GetLPTIMClockSource(uint32_t Periph)
3578 {
3579 return LL_RCC_GetClockSource(Periph);
3580 }
3581
3582 /**
3583 * @brief Get SAIx clock source
3584 * @rmtoll D2CCIP1R / CDCCIP1R SAI1SEL LL_RCC_GetSAIClockSource\n
3585 * D2CCIP1R / CDCCIP1R SAI23SEL LL_RCC_GetSAIClockSource
3586 * D3CCIPR / SRDCCIPR SAI4ASEL LL_RCC_GetSAIClockSource\n
3587 * D3CCIPR / SRDCCIPR SAI4BSEL LL_RCC_GetSAIClockSource
3588 * @param Periph This parameter can be one of the following values:
3589 * @arg @ref LL_RCC_SAI1_CLKSOURCE (*)
3590 * @arg @ref LL_RCC_SAI2A_CLKSOURCE (*)
3591 * @arg @ref LL_RCC_SAI2B_CLKSOURCE (*)
3592 * @arg @ref LL_RCC_SAI23_CLKSOURCE (*)
3593 * @arg @ref LL_RCC_SAI4A_CLKSOURCE (*)
3594 * @arg @ref LL_RCC_SAI4B_CLKSOURCE (*)
3595 * @retval Returned value can be one of the following values:
3596 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL1Q
3597 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL2P
3598 * @arg @ref LL_RCC_SAI1_CLKSOURCE_PLL3P
3599 * @arg @ref LL_RCC_SAI1_CLKSOURCE_I2S_CKIN
3600 * @arg @ref LL_RCC_SAI1_CLKSOURCE_CLKP
3601 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL1Q (*)
3602 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL2P (*)
3603 * @arg @ref LL_RCC_SAI23_CLKSOURCE_PLL3P (*)
3604 * @arg @ref LL_RCC_SAI23_CLKSOURCE_I2S_CKIN (*)
3605 * @arg @ref LL_RCC_SAI23_CLKSOURCE_CLKP (*)
3606 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL1Q (*)
3607 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL2P (*)
3608 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_PLL3P (*)
3609 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_I2S_CKIN (*)
3610 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_CLKP (*)
3611 * @arg @ref LL_RCC_SAI2A_CLKSOURCE_SPDIF (*)
3612 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL1Q (*)
3613 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL2P (*)
3614 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_PLL3P (*)
3615 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_I2S_CKIN (*)
3616 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_CLKP (*)
3617 * @arg @ref LL_RCC_SAI2B_CLKSOURCE_SPDIF (*)
3618 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL1Q (*)
3619 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL2P (*)
3620 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_PLL3P (*)
3621 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_I2S_CKIN (*)
3622 * @arg @ref LL_RCC_SAI4A_CLKSOURCE_CLKP (*)
3623 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL1Q (*)
3624 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL2P (*)
3625 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_PLL3P (*)
3626 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_I2S_CKIN (*)
3627 * @arg @ref LL_RCC_SAI4B_CLKSOURCE_CLKP (*)
3628 *
3629 * (*) value not defined in all devices.
3630 */
3631 __STATIC_INLINE uint32_t LL_RCC_GetSAIClockSource(uint32_t Periph)
3632 {
3633 return LL_RCC_GetClockSource(Periph);
3634 }
3635
3636 /**
3637 * @brief Get SDMMC clock source
3638 * @rmtoll D1CCIPR / CDCCIPR SDMMCSEL LL_RCC_GetSDMMCClockSource
3639 * @param Periph This parameter can be one of the following values:
3640 * @arg @ref LL_RCC_SDMMC_CLKSOURCE
3641 * @retval Returned value can be one of the following values:
3642 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL1Q
3643 * @arg @ref LL_RCC_SDMMC_CLKSOURCE_PLL2R
3644 */
3645 __STATIC_INLINE uint32_t LL_RCC_GetSDMMCClockSource(uint32_t Periph)
3646 {
3647 UNUSED(Periph);
3648 #if defined(RCC_D1CCIPR_SDMMCSEL)
3649 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_SDMMCSEL));
3650 #else
3651 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_SDMMCSEL));
3652 #endif /* RCC_D1CCIPR_SDMMCSEL */
3653 }
3654
3655 /**
3656 * @brief Get RNG clock source
3657 * @rmtoll D2CCIP2R RNGSEL LL_RCC_GetRNGClockSource
3658 * @param Periph This parameter can be one of the following values:
3659 * @arg @ref LL_RCC_RNG_CLKSOURCE
3660 * @retval Returned value can be one of the following values:
3661 * @arg @ref LL_RCC_RNG_CLKSOURCE_HSI48
3662 * @arg @ref LL_RCC_RNG_CLKSOURCE_PLL1Q
3663 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSE
3664 * @arg @ref LL_RCC_RNG_CLKSOURCE_LSI
3665 */
3666 __STATIC_INLINE uint32_t LL_RCC_GetRNGClockSource(uint32_t Periph)
3667 {
3668 UNUSED(Periph);
3669 #if defined(RCC_D2CCIP2R_RNGSEL)
3670 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_RNGSEL));
3671 #else
3672 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_RNGSEL));
3673 #endif /* RCC_D2CCIP2R_RNGSEL */
3674 }
3675
3676 /**
3677 * @brief Get USB clock source
3678 * @rmtoll D2CCIP2R / CDCCIP2R USBSEL LL_RCC_GetUSBClockSource
3679 * @param Periph This parameter can be one of the following values:
3680 * @arg @ref LL_RCC_USB_CLKSOURCE
3681 * @retval Returned value can be one of the following values:
3682 * @arg @ref LL_RCC_USB_CLKSOURCE_DISABLE
3683 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL1Q
3684 * @arg @ref LL_RCC_USB_CLKSOURCE_PLL3Q
3685 * @arg @ref LL_RCC_USB_CLKSOURCE_HSI48
3686 */
3687 __STATIC_INLINE uint32_t LL_RCC_GetUSBClockSource(uint32_t Periph)
3688 {
3689 UNUSED(Periph);
3690 #if defined(RCC_D2CCIP2R_USBSEL)
3691 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_USBSEL));
3692 #else
3693 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_USBSEL));
3694 #endif /* RCC_D2CCIP2R_USBSEL */
3695 }
3696
3697 /**
3698 * @brief Get CEC clock source
3699 * @rmtoll D2CCIP2R / CDCCIP2R CECSEL LL_RCC_GetCECClockSource
3700 * @param Periph This parameter can be one of the following values:
3701 * @arg @ref LL_RCC_CEC_CLKSOURCE
3702 * @retval Returned value can be one of the following values:
3703 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSE
3704 * @arg @ref LL_RCC_CEC_CLKSOURCE_LSI
3705 * @arg @ref LL_RCC_CEC_CLKSOURCE_CSI_DIV122
3706 */
3707 __STATIC_INLINE uint32_t LL_RCC_GetCECClockSource(uint32_t Periph)
3708 {
3709 UNUSED(Periph);
3710 #if defined(RCC_D2CCIP2R_CECSEL)
3711 return (uint32_t)(READ_BIT(RCC->D2CCIP2R, RCC_D2CCIP2R_CECSEL));
3712 #else
3713 return (uint32_t)(READ_BIT(RCC->CDCCIP2R, RCC_CDCCIP2R_CECSEL));
3714 #endif /* RCC_D2CCIP2R_CECSEL */
3715 }
3716
3717 #if defined(DSI)
3718 /**
3719 * @brief Get DSI clock source
3720 * @rmtoll D1CCIPR DSISEL LL_RCC_GetDSIClockSource
3721 * @param Periph This parameter can be one of the following values:
3722 * @arg @ref LL_RCC_DSI_CLKSOURCE
3723 * @retval Returned value can be one of the following values:
3724 * @arg @ref LL_RCC_DSI_CLKSOURCE_PHY
3725 * @arg @ref LL_RCC_DSI_CLKSOURCE_PLL2Q
3726 */
3727 __STATIC_INLINE uint32_t LL_RCC_GetDSIClockSource(uint32_t Periph)
3728 {
3729 UNUSED(Periph);
3730 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_DSISEL));
3731 }
3732 #endif /* DSI */
3733
3734 /**
3735 * @brief Get DFSDM Kernel clock source
3736 * @rmtoll D2CCIP1R / CDCCIP1R DFSDM1SEL LL_RCC_GetDFSDMClockSource
3737 * @param Periph This parameter can be one of the following values:
3738 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE
3739 * @retval Returned value can be one of the following values:
3740 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_PCLK2
3741 * @arg @ref LL_RCC_DFSDM1_CLKSOURCE_SYSCLK
3742 */
3743 __STATIC_INLINE uint32_t LL_RCC_GetDFSDMClockSource(uint32_t Periph)
3744 {
3745 UNUSED(Periph);
3746 #if defined(RCC_D2CCIP1R_DFSDM1SEL)
3747 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_DFSDM1SEL));
3748 #else
3749 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_DFSDM1SEL));
3750 #endif /* RCC_D2CCIP1R_DFSDM1SEL */
3751 }
3752
3753 #if defined(DFSDM2_BASE)
3754 /**
3755 * @brief Get DFSDM2 Kernel clock source
3756 * @rmtoll SRDCCIPR DFSDM2SEL LL_RCC_GetDFSDM2ClockSource
3757 * @param Periph This parameter can be one of the following values:
3758 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE
3759 * @retval Returned value can be one of the following values:
3760 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_PCLK4
3761 * @arg @ref LL_RCC_DFSDM2_CLKSOURCE_SYSCLK
3762 */
3763 __STATIC_INLINE uint32_t LL_RCC_GetDFSDM2ClockSource(uint32_t Periph)
3764 {
3765 UNUSED(Periph);
3766 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_DFSDM2SEL));
3767 }
3768 #endif /* DFSDM2_BASE */
3769
3770 /**
3771 * @brief Get FMC Kernel clock source
3772 * @rmtoll D1CCIPR / D1CCIPR FMCSEL LL_RCC_GetFMCClockSource
3773 * @param Periph This parameter can be one of the following values:
3774 * @arg @ref LL_RCC_FMC_CLKSOURCE
3775 * @retval Returned value can be one of the following values:
3776 * @arg @ref LL_RCC_FMC_CLKSOURCE_HCLK
3777 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL1Q
3778 * @arg @ref LL_RCC_FMC_CLKSOURCE_PLL2R
3779 * @arg @ref LL_RCC_FMC_CLKSOURCE_CLKP
3780 */
3781 __STATIC_INLINE uint32_t LL_RCC_GetFMCClockSource(uint32_t Periph)
3782 {
3783 UNUSED(Periph);
3784 #if defined(RCC_D1CCIPR_FMCSEL)
3785 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_FMCSEL));
3786 #else
3787 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_FMCSEL));
3788 #endif /* RCC_D1CCIPR_FMCSEL */
3789 }
3790
3791 #if defined(QUADSPI)
3792 /**
3793 * @brief Get QSPI Kernel clock source
3794 * @rmtoll D1CCIPR / CDCCIPR QSPISEL LL_RCC_GetQSPIClockSource
3795 * @param Periph This parameter can be one of the following values:
3796 * @arg @ref LL_RCC_QSPI_CLKSOURCE
3797 * @retval Returned value can be one of the following values:
3798 * @arg @ref LL_RCC_QSPI_CLKSOURCE_HCLK
3799 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL1Q
3800 * @arg @ref LL_RCC_QSPI_CLKSOURCE_PLL2R
3801 * @arg @ref LL_RCC_QSPI_CLKSOURCE_CLKP
3802 */
3803 __STATIC_INLINE uint32_t LL_RCC_GetQSPIClockSource(uint32_t Periph)
3804 {
3805 UNUSED(Periph);
3806 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_QSPISEL));
3807 }
3808 #endif /* QUADSPI */
3809
3810 #if defined(OCTOSPI1) || defined(OCTOSPI2)
3811 /**
3812 * @brief Get OSPI Kernel clock source
3813 * @rmtoll CDCCIPR OSPISEL LL_RCC_GetOSPIClockSource
3814 * @param Periph This parameter can be one of the following values:
3815 * @arg @ref LL_RCC_OSPI_CLKSOURCE
3816 * @retval Returned value can be one of the following values:
3817 * @arg @ref LL_RCC_OSPI_CLKSOURCE_HCLK
3818 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL1Q
3819 * @arg @ref LL_RCC_OSPI_CLKSOURCE_PLL2R
3820 * @arg @ref LL_RCC_OSPI_CLKSOURCE_CLKP
3821 */
3822 __STATIC_INLINE uint32_t LL_RCC_GetOSPIClockSource(uint32_t Periph)
3823 {
3824 UNUSED(Periph);
3825 #if defined(RCC_D1CCIPR_OCTOSPISEL)
3826 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_OCTOSPISEL));
3827 #else
3828 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_OCTOSPISEL));
3829 #endif /* RCC_D1CCIPR_OCTOSPISEL */
3830 }
3831 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
3832
3833 /**
3834 * @brief Get CLKP Kernel clock source
3835 * @rmtoll D1CCIPR / CDCCIPR CKPERSEL LL_RCC_GetCLKPClockSource
3836 * @param Periph This parameter can be one of the following values:
3837 * @arg @ref LL_RCC_CLKP_CLKSOURCE
3838 * @retval Returned value can be one of the following values:
3839 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSI
3840 * @arg @ref LL_RCC_CLKP_CLKSOURCE_CSI
3841 * @arg @ref LL_RCC_CLKP_CLKSOURCE_HSE
3842 */
3843 __STATIC_INLINE uint32_t LL_RCC_GetCLKPClockSource(uint32_t Periph)
3844 {
3845 UNUSED(Periph);
3846 #if defined(RCC_D1CCIPR_CKPERSEL)
3847 return (uint32_t)(READ_BIT(RCC->D1CCIPR, RCC_D1CCIPR_CKPERSEL));
3848 #else
3849 return (uint32_t)(READ_BIT(RCC->CDCCIPR, RCC_CDCCIPR_CKPERSEL));
3850 #endif /* RCC_D1CCIPR_CKPERSEL */
3851 }
3852
3853 /**
3854 * @brief Get SPIx Kernel clock source
3855 * @rmtoll D2CCIP1R / CDCCIP1R SPI123SEL LL_RCC_GetSPIClockSource\n
3856 * D2CCIP1R / CDCCIP1R SPI45SEL LL_RCC_GetSPIClockSource\n
3857 * D3CCIPR / SRDCCIPR SPI6SEL LL_RCC_GetSPIClockSource
3858 * @param Periph This parameter can be one of the following values:
3859 * @arg @ref LL_RCC_SPI123_CLKSOURCE
3860 * @arg @ref LL_RCC_SPI45_CLKSOURCE
3861 * @arg @ref LL_RCC_SPI6_CLKSOURCE
3862 * @retval Returned value can be one of the following values:
3863 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL1Q
3864 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL2P
3865 * @arg @ref LL_RCC_SPI123_CLKSOURCE_PLL3P
3866 * @arg @ref LL_RCC_SPI123_CLKSOURCE_I2S_CKIN
3867 * @arg @ref LL_RCC_SPI123_CLKSOURCE_CLKP
3868 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PCLK2
3869 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL2Q
3870 * @arg @ref LL_RCC_SPI45_CLKSOURCE_PLL3Q
3871 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSI
3872 * @arg @ref LL_RCC_SPI45_CLKSOURCE_CSI
3873 * @arg @ref LL_RCC_SPI45_CLKSOURCE_HSE
3874 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PCLK4
3875 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL2Q
3876 * @arg @ref LL_RCC_SPI6_CLKSOURCE_PLL3Q
3877 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSI
3878 * @arg @ref LL_RCC_SPI6_CLKSOURCE_CSI
3879 * @arg @ref LL_RCC_SPI6_CLKSOURCE_HSE
3880 * @arg @ref LL_RCC_SPI6_CLKSOURCE_I2S_CKIN (*)
3881 *
3882 * (*) value not defined in all stm32h7xx lines.
3883 */
3884 __STATIC_INLINE uint32_t LL_RCC_GetSPIClockSource(uint32_t Periph)
3885 {
3886 return LL_RCC_GetClockSource(Periph);
3887 }
3888
3889 /**
3890 * @brief Get SPDIF Kernel clock source
3891 * @rmtoll D2CCIP1R / CDCCIP1R SPDIFSEL LL_RCC_GetSPDIFClockSource
3892 * @param Periph This parameter can be one of the following values:
3893 * @arg @ref LL_RCC_SPDIF_CLKSOURCE
3894 * @retval Returned value can be one of the following values:
3895 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL1Q
3896 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL2R
3897 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_PLL3R
3898 * @arg @ref LL_RCC_SPDIF_CLKSOURCE_HSI
3899 */
3900 __STATIC_INLINE uint32_t LL_RCC_GetSPDIFClockSource(uint32_t Periph)
3901 {
3902 UNUSED(Periph);
3903 #if defined(RCC_D2CCIP1R_SPDIFSEL)
3904 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SPDIFSEL));
3905 #else
3906 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SPDIFSEL));
3907 #endif /* RCC_D2CCIP1R_SPDIFSEL */
3908 }
3909
3910 /**
3911 * @brief Get FDCAN Kernel clock source
3912 * @rmtoll D2CCIP1R / CDCCIP1R FDCANSEL LL_RCC_GetFDCANClockSource
3913 * @param Periph This parameter can be one of the following values:
3914 * @arg @ref LL_RCC_FDCAN_CLKSOURCE
3915 * @retval Returned value can be one of the following values:
3916 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_HSE
3917 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL1Q
3918 * @arg @ref LL_RCC_FDCAN_CLKSOURCE_PLL2Q
3919 */
3920 __STATIC_INLINE uint32_t LL_RCC_GetFDCANClockSource(uint32_t Periph)
3921 {
3922 UNUSED(Periph);
3923 #if defined(RCC_D2CCIP1R_FDCANSEL)
3924 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_FDCANSEL));
3925 #else
3926 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_FDCANSEL));
3927 #endif /* RCC_D2CCIP1R_FDCANSEL */
3928 }
3929
3930 /**
3931 * @brief Get SWP Kernel clock source
3932 * @rmtoll D2CCIP1R / CDCCIP1R SWPSEL LL_RCC_GetSWPClockSource
3933 * @param Periph This parameter can be one of the following values:
3934 * @arg @ref LL_RCC_SWP_CLKSOURCE
3935 * @retval Returned value can be one of the following values:
3936 * @arg @ref LL_RCC_SWP_CLKSOURCE_PCLK1
3937 * @arg @ref LL_RCC_SWP_CLKSOURCE_HSI
3938 */
3939 __STATIC_INLINE uint32_t LL_RCC_GetSWPClockSource(uint32_t Periph)
3940 {
3941 UNUSED(Periph);
3942 #if defined(RCC_D2CCIP1R_SWPSEL)
3943 return (uint32_t)(READ_BIT(RCC->D2CCIP1R, RCC_D2CCIP1R_SWPSEL));
3944 #else
3945 return (uint32_t)(READ_BIT(RCC->CDCCIP1R, RCC_CDCCIP1R_SWPSEL));
3946 #endif /* RCC_D2CCIP1R_SWPSEL */
3947 }
3948
3949 /**
3950 * @brief Get ADC Kernel clock source
3951 * @rmtoll D3CCIPR / SRDCCIPR ADCSEL LL_RCC_GetADCClockSource
3952 * @param Periph This parameter can be one of the following values:
3953 * @arg @ref LL_RCC_ADC_CLKSOURCE
3954 * @retval Returned value can be one of the following values:
3955 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL2P
3956 * @arg @ref LL_RCC_ADC_CLKSOURCE_PLL3R
3957 * @arg @ref LL_RCC_ADC_CLKSOURCE_CLKP
3958 */
3959 __STATIC_INLINE uint32_t LL_RCC_GetADCClockSource(uint32_t Periph)
3960 {
3961 UNUSED(Periph);
3962 #if defined (RCC_D3CCIPR_ADCSEL)
3963 return (uint32_t)(READ_BIT(RCC->D3CCIPR, RCC_D3CCIPR_ADCSEL));
3964 #else
3965 return (uint32_t)(READ_BIT(RCC->SRDCCIPR, RCC_SRDCCIPR_ADCSEL));
3966 #endif /* RCC_D3CCIPR_ADCSEL */
3967 }
3968
3969 /**
3970 * @}
3971 */
3972
3973 /** @defgroup RCC_LL_EF_RTC RTC
3974 * @{
3975 */
3976
3977 /**
3978 * @brief Set RTC Clock Source
3979 * @note Once the RTC clock source has been selected, it cannot be changed anymore unless
3980 * the Backup domain is reset, or unless a failure is detected on LSE (LSECSSD is
3981 * set). The BDRST bit can be used to reset them.
3982 * @rmtoll BDCR RTCSEL LL_RCC_SetRTCClockSource
3983 * @param Source This parameter can be one of the following values:
3984 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
3985 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
3986 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
3987 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
3988 * @retval None
3989 */
3990 __STATIC_INLINE void LL_RCC_SetRTCClockSource(uint32_t Source)
3991 {
3992 MODIFY_REG(RCC->BDCR, RCC_BDCR_RTCSEL, Source);
3993 }
3994
3995 /**
3996 * @brief Get RTC Clock Source
3997 * @rmtoll BDCR RTCSEL LL_RCC_GetRTCClockSource
3998 * @retval Returned value can be one of the following values:
3999 * @arg @ref LL_RCC_RTC_CLKSOURCE_NONE
4000 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSE
4001 * @arg @ref LL_RCC_RTC_CLKSOURCE_LSI
4002 * @arg @ref LL_RCC_RTC_CLKSOURCE_HSE
4003 */
4004 __STATIC_INLINE uint32_t LL_RCC_GetRTCClockSource(void)
4005 {
4006 return (uint32_t)(READ_BIT(RCC->BDCR, RCC_BDCR_RTCSEL));
4007 }
4008
4009 /**
4010 * @brief Enable RTC
4011 * @rmtoll BDCR RTCEN LL_RCC_EnableRTC
4012 * @retval None
4013 */
4014 __STATIC_INLINE void LL_RCC_EnableRTC(void)
4015 {
4016 SET_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4017 }
4018
4019 /**
4020 * @brief Disable RTC
4021 * @rmtoll BDCR RTCEN LL_RCC_DisableRTC
4022 * @retval None
4023 */
4024 __STATIC_INLINE void LL_RCC_DisableRTC(void)
4025 {
4026 CLEAR_BIT(RCC->BDCR, RCC_BDCR_RTCEN);
4027 }
4028
4029 /**
4030 * @brief Check if RTC has been enabled or not
4031 * @rmtoll BDCR RTCEN LL_RCC_IsEnabledRTC
4032 * @retval State of bit (1 or 0).
4033 */
4034 __STATIC_INLINE uint32_t LL_RCC_IsEnabledRTC(void)
4035 {
4036 return ((READ_BIT(RCC->BDCR, RCC_BDCR_RTCEN) == (RCC_BDCR_RTCEN)) ? 1UL : 0UL);
4037 }
4038
4039 /**
4040 * @brief Force the Backup domain reset
4041 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ForceBackupDomainReset
4042 * @retval None
4043 */
4044 __STATIC_INLINE void LL_RCC_ForceBackupDomainReset(void)
4045 {
4046 SET_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4047 }
4048
4049 /**
4050 * @brief Release the Backup domain reset
4051 * @rmtoll BDCR BDRST / VSWRST LL_RCC_ReleaseBackupDomainReset
4052 * @retval None
4053 */
4054 __STATIC_INLINE void LL_RCC_ReleaseBackupDomainReset(void)
4055 {
4056 #if defined(RCC_BDCR_BDRST)
4057 CLEAR_BIT(RCC->BDCR, RCC_BDCR_BDRST);
4058 #else
4059 CLEAR_BIT(RCC->BDCR, RCC_BDCR_VSWRST);
4060 #endif /* RCC_BDCR_BDRST */
4061 }
4062
4063 /**
4064 * @brief Set HSE Prescalers for RTC Clock
4065 * @rmtoll CFGR RTCPRE LL_RCC_SetRTC_HSEPrescaler
4066 * @param Prescaler This parameter can be one of the following values:
4067 * @arg @ref LL_RCC_RTC_NOCLOCK
4068 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4069 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4070 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4071 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4072 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4073 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4074 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4075 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4076 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4077 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4078 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4079 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4080 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4081 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4082 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4083 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4084 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4085 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4086 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4087 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4088 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4089 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4090 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4091 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4092 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4093 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4094 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4095 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4096 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4097 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4098 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4099 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4100 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4101 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4102 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4103 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4104 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4105 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4106 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4107 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4108 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4109 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4110 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4111 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4112 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4113 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4114 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4115 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4116 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4117 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4118 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4119 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4120 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4121 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4122 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4123 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4124 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4125 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4126 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4127 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4128 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4129 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4130 * @retval None
4131 */
4132 __STATIC_INLINE void LL_RCC_SetRTC_HSEPrescaler(uint32_t Prescaler)
4133 {
4134 MODIFY_REG(RCC->CFGR, RCC_CFGR_RTCPRE, Prescaler);
4135 }
4136
4137 /**
4138 * @brief Get HSE Prescalers for RTC Clock
4139 * @rmtoll CFGR RTCPRE LL_RCC_GetRTC_HSEPrescaler
4140 * @retval Returned value can be one of the following values:
4141 * @arg @ref LL_RCC_RTC_NOCLOCK
4142 * @arg @ref LL_RCC_RTC_HSE_DIV_2
4143 * @arg @ref LL_RCC_RTC_HSE_DIV_3
4144 * @arg @ref LL_RCC_RTC_HSE_DIV_4
4145 * @arg @ref LL_RCC_RTC_HSE_DIV_5
4146 * @arg @ref LL_RCC_RTC_HSE_DIV_6
4147 * @arg @ref LL_RCC_RTC_HSE_DIV_7
4148 * @arg @ref LL_RCC_RTC_HSE_DIV_8
4149 * @arg @ref LL_RCC_RTC_HSE_DIV_9
4150 * @arg @ref LL_RCC_RTC_HSE_DIV_10
4151 * @arg @ref LL_RCC_RTC_HSE_DIV_11
4152 * @arg @ref LL_RCC_RTC_HSE_DIV_12
4153 * @arg @ref LL_RCC_RTC_HSE_DIV_13
4154 * @arg @ref LL_RCC_RTC_HSE_DIV_14
4155 * @arg @ref LL_RCC_RTC_HSE_DIV_15
4156 * @arg @ref LL_RCC_RTC_HSE_DIV_16
4157 * @arg @ref LL_RCC_RTC_HSE_DIV_17
4158 * @arg @ref LL_RCC_RTC_HSE_DIV_18
4159 * @arg @ref LL_RCC_RTC_HSE_DIV_19
4160 * @arg @ref LL_RCC_RTC_HSE_DIV_20
4161 * @arg @ref LL_RCC_RTC_HSE_DIV_21
4162 * @arg @ref LL_RCC_RTC_HSE_DIV_22
4163 * @arg @ref LL_RCC_RTC_HSE_DIV_23
4164 * @arg @ref LL_RCC_RTC_HSE_DIV_24
4165 * @arg @ref LL_RCC_RTC_HSE_DIV_25
4166 * @arg @ref LL_RCC_RTC_HSE_DIV_26
4167 * @arg @ref LL_RCC_RTC_HSE_DIV_27
4168 * @arg @ref LL_RCC_RTC_HSE_DIV_28
4169 * @arg @ref LL_RCC_RTC_HSE_DIV_29
4170 * @arg @ref LL_RCC_RTC_HSE_DIV_30
4171 * @arg @ref LL_RCC_RTC_HSE_DIV_31
4172 * @arg @ref LL_RCC_RTC_HSE_DIV_32
4173 * @arg @ref LL_RCC_RTC_HSE_DIV_33
4174 * @arg @ref LL_RCC_RTC_HSE_DIV_34
4175 * @arg @ref LL_RCC_RTC_HSE_DIV_35
4176 * @arg @ref LL_RCC_RTC_HSE_DIV_36
4177 * @arg @ref LL_RCC_RTC_HSE_DIV_37
4178 * @arg @ref LL_RCC_RTC_HSE_DIV_38
4179 * @arg @ref LL_RCC_RTC_HSE_DIV_39
4180 * @arg @ref LL_RCC_RTC_HSE_DIV_40
4181 * @arg @ref LL_RCC_RTC_HSE_DIV_41
4182 * @arg @ref LL_RCC_RTC_HSE_DIV_42
4183 * @arg @ref LL_RCC_RTC_HSE_DIV_43
4184 * @arg @ref LL_RCC_RTC_HSE_DIV_44
4185 * @arg @ref LL_RCC_RTC_HSE_DIV_45
4186 * @arg @ref LL_RCC_RTC_HSE_DIV_46
4187 * @arg @ref LL_RCC_RTC_HSE_DIV_47
4188 * @arg @ref LL_RCC_RTC_HSE_DIV_48
4189 * @arg @ref LL_RCC_RTC_HSE_DIV_49
4190 * @arg @ref LL_RCC_RTC_HSE_DIV_50
4191 * @arg @ref LL_RCC_RTC_HSE_DIV_51
4192 * @arg @ref LL_RCC_RTC_HSE_DIV_52
4193 * @arg @ref LL_RCC_RTC_HSE_DIV_53
4194 * @arg @ref LL_RCC_RTC_HSE_DIV_54
4195 * @arg @ref LL_RCC_RTC_HSE_DIV_55
4196 * @arg @ref LL_RCC_RTC_HSE_DIV_56
4197 * @arg @ref LL_RCC_RTC_HSE_DIV_57
4198 * @arg @ref LL_RCC_RTC_HSE_DIV_58
4199 * @arg @ref LL_RCC_RTC_HSE_DIV_59
4200 * @arg @ref LL_RCC_RTC_HSE_DIV_60
4201 * @arg @ref LL_RCC_RTC_HSE_DIV_61
4202 * @arg @ref LL_RCC_RTC_HSE_DIV_62
4203 * @arg @ref LL_RCC_RTC_HSE_DIV_63
4204 */
4205 __STATIC_INLINE uint32_t LL_RCC_GetRTC_HSEPrescaler(void)
4206 {
4207 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_RTCPRE));
4208 }
4209
4210 /**
4211 * @}
4212 */
4213
4214 /** @defgroup RCC_LL_EF_TIM_CLOCK_PRESCALER TIM
4215 * @{
4216 */
4217
4218 /**
4219 * @brief Set Timers Clock Prescalers
4220 * @rmtoll CFGR TIMPRE LL_RCC_SetTIMPrescaler
4221 * @param Prescaler This parameter can be one of the following values:
4222 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4223 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4224 * @retval None
4225 */
4226 __STATIC_INLINE void LL_RCC_SetTIMPrescaler(uint32_t Prescaler)
4227 {
4228 MODIFY_REG(RCC->CFGR, RCC_CFGR_TIMPRE, Prescaler);
4229 }
4230
4231 /**
4232 * @brief Get Timers Clock Prescalers
4233 * @rmtoll CFGR TIMPRE LL_RCC_GetTIMPrescaler
4234 * @retval Returned value can be one of the following values:
4235 * @arg @ref LL_RCC_TIM_PRESCALER_TWICE
4236 * @arg @ref LL_RCC_TIM_PRESCALER_FOUR_TIMES
4237 */
4238 __STATIC_INLINE uint32_t LL_RCC_GetTIMPrescaler(void)
4239 {
4240 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_TIMPRE));
4241 }
4242
4243 /**
4244 * @}
4245 */
4246
4247 #if defined(HRTIM1)
4248 /** @defgroup RCC_LL_EF_HRTIM_SET_CLOCK_SOURCE HRTIM
4249 * @{
4250 */
4251
4252 /**
4253 * @brief Set High Resolution Timers Clock Source
4254 * @rmtoll CFGR HRTIMSEL LL_RCC_SetHRTIMClockSource
4255 * @param Prescaler This parameter can be one of the following values:
4256 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4257 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4258 * @retval None
4259 */
4260 __STATIC_INLINE void LL_RCC_SetHRTIMClockSource(uint32_t Prescaler)
4261 {
4262 MODIFY_REG(RCC->CFGR, RCC_CFGR_HRTIMSEL, Prescaler);
4263 }
4264 #endif /* HRTIM1 */
4265
4266 #if defined(HRTIM1)
4267 /**
4268 * @brief Get High Resolution Timers Clock Source
4269 * @rmtoll CFGR HRTIMSEL LL_RCC_GetHRTIMClockSource
4270 * @retval Returned value can be one of the following values:
4271 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_TIM
4272 * @arg @ref LL_RCC_HRTIM_CLKSOURCE_CPU
4273 */
4274 __STATIC_INLINE uint32_t LL_RCC_GetHRTIMClockSource(void)
4275 {
4276 return (uint32_t)(READ_BIT(RCC->CFGR, RCC_CFGR_HRTIMSEL));
4277 }
4278 /**
4279 * @}
4280 */
4281 #endif /* HRTIM1 */
4282
4283 /** @defgroup RCC_LL_EF_PLL PLL
4284 * @{
4285 */
4286
4287 /**
4288 * @brief Set the oscillator used as PLL clock source.
4289 * @note PLLSRC can be written only when All PLLs are disabled.
4290 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_SetSource
4291 * @param PLLSource parameter can be one of the following values:
4292 * @arg @ref LL_RCC_PLLSOURCE_HSI
4293 * @arg @ref LL_RCC_PLLSOURCE_CSI
4294 * @arg @ref LL_RCC_PLLSOURCE_HSE
4295 * @arg @ref LL_RCC_PLLSOURCE_NONE
4296 * @retval None
4297 */
4298 __STATIC_INLINE void LL_RCC_PLL_SetSource(uint32_t PLLSource)
4299 {
4300 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC, PLLSource);
4301 }
4302
4303 /**
4304 * @brief Get the oscillator used as PLL clock source.
4305 * @rmtoll PLLCKSELR PLLSRC LL_RCC_PLL_GetSource
4306 * @retval Returned value can be one of the following values:
4307 * @arg @ref LL_RCC_PLLSOURCE_HSI
4308 * @arg @ref LL_RCC_PLLSOURCE_CSI
4309 * @arg @ref LL_RCC_PLLSOURCE_HSE
4310 * @arg @ref LL_RCC_PLLSOURCE_NONE
4311 */
4312 __STATIC_INLINE uint32_t LL_RCC_PLL_GetSource(void)
4313 {
4314 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_PLLSRC));
4315 }
4316
4317 /**
4318 * @brief Enable PLL1
4319 * @rmtoll CR PLL1ON LL_RCC_PLL1_Enable
4320 * @retval None
4321 */
4322 __STATIC_INLINE void LL_RCC_PLL1_Enable(void)
4323 {
4324 SET_BIT(RCC->CR, RCC_CR_PLL1ON);
4325 }
4326
4327 /**
4328 * @brief Disable PLL1
4329 * @note Cannot be disabled if the PLL1 clock is used as the system clock
4330 * @rmtoll CR PLL1ON LL_RCC_PLL1_Disable
4331 * @retval None
4332 */
4333 __STATIC_INLINE void LL_RCC_PLL1_Disable(void)
4334 {
4335 CLEAR_BIT(RCC->CR, RCC_CR_PLL1ON);
4336 }
4337
4338 /**
4339 * @brief Check if PLL1 Ready
4340 * @rmtoll CR PLL1RDY LL_RCC_PLL1_IsReady
4341 * @retval State of bit (1 or 0).
4342 */
4343 __STATIC_INLINE uint32_t LL_RCC_PLL1_IsReady(void)
4344 {
4345 return ((READ_BIT(RCC->CR, RCC_CR_PLL1RDY) == (RCC_CR_PLL1RDY)) ? 1UL : 0UL);
4346 }
4347
4348 /**
4349 * @brief Enable PLL1P
4350 * @note This API shall be called only when PLL1 is disabled.
4351 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Enable
4352 * @retval None
4353 */
4354 __STATIC_INLINE void LL_RCC_PLL1P_Enable(void)
4355 {
4356 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4357 }
4358
4359 /**
4360 * @brief Enable PLL1Q
4361 * @note This API shall be called only when PLL1 is disabled.
4362 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Enable
4363 * @retval None
4364 */
4365 __STATIC_INLINE void LL_RCC_PLL1Q_Enable(void)
4366 {
4367 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4368 }
4369
4370 /**
4371 * @brief Enable PLL1R
4372 * @note This API shall be called only when PLL1 is disabled.
4373 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Enable
4374 * @retval None
4375 */
4376 __STATIC_INLINE void LL_RCC_PLL1R_Enable(void)
4377 {
4378 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4379 }
4380
4381 /**
4382 * @brief Enable PLL1 FRACN
4383 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4384 * @retval None
4385 */
4386 __STATIC_INLINE void LL_RCC_PLL1FRACN_Enable(void)
4387 {
4388 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4389 }
4390
4391 /**
4392 * @brief Check if PLL1 P is enabled
4393 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_IsEnabled
4394 * @retval State of bit (1 or 0).
4395 */
4396 __STATIC_INLINE uint32_t LL_RCC_PLL1P_IsEnabled(void)
4397 {
4398 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN) == RCC_PLLCFGR_DIVP1EN) ? 1UL : 0UL);
4399 }
4400
4401 /**
4402 * @brief Check if PLL1 Q is enabled
4403 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_IsEnabled
4404 * @retval State of bit (1 or 0).
4405 */
4406 __STATIC_INLINE uint32_t LL_RCC_PLL1Q_IsEnabled(void)
4407 {
4408 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN) == RCC_PLLCFGR_DIVQ1EN) ? 1UL : 0UL);
4409 }
4410
4411 /**
4412 * @brief Check if PLL1 R is enabled
4413 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_IsEnabled
4414 * @retval State of bit (1 or 0).
4415 */
4416 __STATIC_INLINE uint32_t LL_RCC_PLL1R_IsEnabled(void)
4417 {
4418 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN) == RCC_PLLCFGR_DIVR1EN) ? 1UL : 0UL);
4419 }
4420
4421 /**
4422 * @brief Check if PLL1 FRACN is enabled
4423 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_IsEnabled
4424 * @retval State of bit (1 or 0).
4425 */
4426 __STATIC_INLINE uint32_t LL_RCC_PLL1FRACN_IsEnabled(void)
4427 {
4428 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN) == RCC_PLLCFGR_PLL1FRACEN) ? 1UL : 0UL);
4429 }
4430
4431 /**
4432 * @brief Disable PLL1P
4433 * @note This API shall be called only when PLL1 is disabled.
4434 * @rmtoll PLLCFGR DIVP1EN LL_RCC_PLL1P_Disable
4435 * @retval None
4436 */
4437 __STATIC_INLINE void LL_RCC_PLL1P_Disable(void)
4438 {
4439 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP1EN);
4440 }
4441
4442 /**
4443 * @brief Disable PLL1Q
4444 * @note This API shall be called only when PLL1 is disabled.
4445 * @rmtoll PLLCFGR DIVQ1EN LL_RCC_PLL1Q_Disable
4446 * @retval None
4447 */
4448 __STATIC_INLINE void LL_RCC_PLL1Q_Disable(void)
4449 {
4450 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ1EN);
4451 }
4452
4453 /**
4454 * @brief Disable PLL1R
4455 * @note This API shall be called only when PLL1 is disabled.
4456 * @rmtoll PLLCFGR DIVR1EN LL_RCC_PLL1R_Disable
4457 * @retval None
4458 */
4459 __STATIC_INLINE void LL_RCC_PLL1R_Disable(void)
4460 {
4461 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR1EN);
4462 }
4463
4464 /**
4465 * @brief Disable PLL1 FRACN
4466 * @rmtoll PLLCFGR PLL1FRACEN LL_RCC_PLL1FRACN_Enable
4467 * @retval None
4468 */
4469 __STATIC_INLINE void LL_RCC_PLL1FRACN_Disable(void)
4470 {
4471 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL1FRACEN);
4472 }
4473
4474 /**
4475 * @brief Set PLL1 VCO OutputRange
4476 * @note This API shall be called only when PLL1 is disabled.
4477 * @rmtoll PLLCFGR PLL1VCOSEL LL_RCC_PLL1_SetVCOOuputRange
4478 * @param VCORange This parameter can be one of the following values:
4479 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4480 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4481 * @retval None
4482 */
4483 __STATIC_INLINE void LL_RCC_PLL1_SetVCOOutputRange(uint32_t VCORange)
4484 {
4485 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1VCOSEL, VCORange << RCC_PLLCFGR_PLL1VCOSEL_Pos);
4486 }
4487
4488 /**
4489 * @brief Set PLL1 VCO Input Range
4490 * @note This API shall be called only when PLL1 is disabled.
4491 * @rmtoll PLLCFGR PLL1RGE LL_RCC_PLL1_SetVCOInputRange
4492 * @param InputRange This parameter can be one of the following values:
4493 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4494 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4495 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4496 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4497 * @retval None
4498 */
4499 __STATIC_INLINE void LL_RCC_PLL1_SetVCOInputRange(uint32_t InputRange)
4500 {
4501 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL1RGE, InputRange << RCC_PLLCFGR_PLL1RGE_Pos);
4502 }
4503
4504 /**
4505 * @brief Get PLL1 N Coefficient
4506 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_GetN
4507 * @retval A value between 4 and 512
4508 */
4509 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetN(void)
4510 {
4511 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_N1) >> RCC_PLL1DIVR_N1_Pos) + 1UL);
4512 }
4513
4514 /**
4515 * @brief Get PLL1 M Coefficient
4516 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_GetM
4517 * @retval A value between 0 and 63
4518 */
4519 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetM(void)
4520 {
4521 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1) >> RCC_PLLCKSELR_DIVM1_Pos);
4522 }
4523
4524 /**
4525 * @brief Get PLL1 P Coefficient
4526 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_GetP
4527 * @retval A value between 2 and 128
4528 */
4529 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetP(void)
4530 {
4531 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_P1) >> RCC_PLL1DIVR_P1_Pos) + 1UL);
4532 }
4533
4534 /**
4535 * @brief Get PLL1 Q Coefficient
4536 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_GetQ
4537 * @retval A value between 1 and 128
4538 */
4539 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetQ(void)
4540 {
4541 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1) >> RCC_PLL1DIVR_Q1_Pos) + 1UL);
4542 }
4543
4544 /**
4545 * @brief Get PLL1 R Coefficient
4546 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_GetR
4547 * @retval A value between 1 and 128
4548 */
4549 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetR(void)
4550 {
4551 return (uint32_t)((READ_BIT(RCC->PLL1DIVR, RCC_PLL1DIVR_R1) >> RCC_PLL1DIVR_R1_Pos) + 1UL);
4552 }
4553
4554 /**
4555 * @brief Get PLL1 FRACN Coefficient
4556 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_GetFRACN
4557 * @retval A value between 0 and 8191 (0x1FFF)
4558 */
4559 __STATIC_INLINE uint32_t LL_RCC_PLL1_GetFRACN(void)
4560 {
4561 return (uint32_t)(READ_BIT(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1) >> RCC_PLL1FRACR_FRACN1_Pos);
4562 }
4563
4564 /**
4565 * @brief Set PLL1 N Coefficient
4566 * @note This API shall be called only when PLL1 is disabled.
4567 * @rmtoll PLL1DIVR N1 LL_RCC_PLL1_SetN
4568 * @param N parameter can be a value between 4 and 512
4569 */
4570 __STATIC_INLINE void LL_RCC_PLL1_SetN(uint32_t N)
4571 {
4572 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_N1, (N - 1UL) << RCC_PLL1DIVR_N1_Pos);
4573 }
4574
4575 /**
4576 * @brief Set PLL1 M Coefficient
4577 * @note This API shall be called only when PLL1 is disabled.
4578 * @rmtoll PLLCKSELR DIVM1 LL_RCC_PLL1_SetM
4579 * @param M parameter can be a value between 0 and 63
4580 */
4581 __STATIC_INLINE void LL_RCC_PLL1_SetM(uint32_t M)
4582 {
4583 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM1, M << RCC_PLLCKSELR_DIVM1_Pos);
4584 }
4585
4586 /**
4587 * @brief Set PLL1 P Coefficient
4588 * @note This API shall be called only when PLL1 is disabled.
4589 * @rmtoll PLL1DIVR P1 LL_RCC_PLL1_SetP
4590 * @param P parameter can be a value between 2 (or 1*) and 128 (ODD division factor not supported)
4591 *
4592 * (*) : For stm32h72xxx and stm32h73xxx family lines.
4593 */
4594 __STATIC_INLINE void LL_RCC_PLL1_SetP(uint32_t P)
4595 {
4596 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_P1, (P - 1UL) << RCC_PLL1DIVR_P1_Pos);
4597 }
4598
4599 /**
4600 * @brief Set PLL1 Q Coefficient
4601 * @note This API shall be called only when PLL1 is disabled.
4602 * @rmtoll PLL1DIVR Q1 LL_RCC_PLL1_SetQ
4603 * @param Q parameter can be a value between 1 and 128
4604 */
4605 __STATIC_INLINE void LL_RCC_PLL1_SetQ(uint32_t Q)
4606 {
4607 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_Q1, (Q - 1UL) << RCC_PLL1DIVR_Q1_Pos);
4608 }
4609
4610 /**
4611 * @brief Set PLL1 R Coefficient
4612 * @note This API shall be called only when PLL1 is disabled.
4613 * @rmtoll PLL1DIVR R1 LL_RCC_PLL1_SetR
4614 * @param R parameter can be a value between 1 and 128
4615 */
4616 __STATIC_INLINE void LL_RCC_PLL1_SetR(uint32_t R)
4617 {
4618 MODIFY_REG(RCC->PLL1DIVR, RCC_PLL1DIVR_R1, (R - 1UL) << RCC_PLL1DIVR_R1_Pos);
4619 }
4620
4621 /**
4622 * @brief Set PLL1 FRACN Coefficient
4623 * @rmtoll PLL1FRACR FRACN1 LL_RCC_PLL1_SetFRACN
4624 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4625 */
4626 __STATIC_INLINE void LL_RCC_PLL1_SetFRACN(uint32_t FRACN)
4627 {
4628 MODIFY_REG(RCC->PLL1FRACR, RCC_PLL1FRACR_FRACN1, FRACN << RCC_PLL1FRACR_FRACN1_Pos);
4629 }
4630
4631 /**
4632 * @brief Enable PLL2
4633 * @rmtoll CR PLL2ON LL_RCC_PLL2_Enable
4634 * @retval None
4635 */
4636 __STATIC_INLINE void LL_RCC_PLL2_Enable(void)
4637 {
4638 SET_BIT(RCC->CR, RCC_CR_PLL2ON);
4639 }
4640
4641 /**
4642 * @brief Disable PLL2
4643 * @note Cannot be disabled if the PLL2 clock is used as the system clock
4644 * @rmtoll CR PLL2ON LL_RCC_PLL2_Disable
4645 * @retval None
4646 */
4647 __STATIC_INLINE void LL_RCC_PLL2_Disable(void)
4648 {
4649 CLEAR_BIT(RCC->CR, RCC_CR_PLL2ON);
4650 }
4651
4652 /**
4653 * @brief Check if PLL2 Ready
4654 * @rmtoll CR PLL2RDY LL_RCC_PLL2_IsReady
4655 * @retval State of bit (1 or 0).
4656 */
4657 __STATIC_INLINE uint32_t LL_RCC_PLL2_IsReady(void)
4658 {
4659 return ((READ_BIT(RCC->CR, RCC_CR_PLL2RDY) == (RCC_CR_PLL2RDY)) ? 1UL : 0UL);
4660 }
4661
4662 /**
4663 * @brief Enable PLL2P
4664 * @note This API shall be called only when PLL2 is disabled.
4665 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Enable
4666 * @retval None
4667 */
4668 __STATIC_INLINE void LL_RCC_PLL2P_Enable(void)
4669 {
4670 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4671 }
4672
4673 /**
4674 * @brief Enable PLL2Q
4675 * @note This API shall be called only when PLL2 is disabled.
4676 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Enable
4677 * @retval None
4678 */
4679 __STATIC_INLINE void LL_RCC_PLL2Q_Enable(void)
4680 {
4681 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4682 }
4683
4684 /**
4685 * @brief Enable PLL2R
4686 * @note This API shall be called only when PLL2 is disabled.
4687 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Enable
4688 * @retval None
4689 */
4690 __STATIC_INLINE void LL_RCC_PLL2R_Enable(void)
4691 {
4692 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4693 }
4694
4695 /**
4696 * @brief Enable PLL2 FRACN
4697 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4698 * @retval None
4699 */
4700 __STATIC_INLINE void LL_RCC_PLL2FRACN_Enable(void)
4701 {
4702 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4703 }
4704
4705 /**
4706 * @brief Check if PLL2 P is enabled
4707 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_IsEnabled
4708 * @retval State of bit (1 or 0).
4709 */
4710 __STATIC_INLINE uint32_t LL_RCC_PLL2P_IsEnabled(void)
4711 {
4712 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN) == RCC_PLLCFGR_DIVP2EN) ? 1UL : 0UL);
4713 }
4714
4715 /**
4716 * @brief Check if PLL2 Q is enabled
4717 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_IsEnabled
4718 * @retval State of bit (1 or 0).
4719 */
4720 __STATIC_INLINE uint32_t LL_RCC_PLL2Q_IsEnabled(void)
4721 {
4722 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN) == RCC_PLLCFGR_DIVQ2EN) ? 1UL : 0UL);
4723 }
4724
4725 /**
4726 * @brief Check if PLL2 R is enabled
4727 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_IsEnabled
4728 * @retval State of bit (1 or 0).
4729 */
4730 __STATIC_INLINE uint32_t LL_RCC_PLL2R_IsEnabled(void)
4731 {
4732 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN) == RCC_PLLCFGR_DIVR2EN) ? 1UL : 0UL);
4733 }
4734
4735 /**
4736 * @brief Check if PLL2 FRACN is enabled
4737 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_IsEnabled
4738 * @retval State of bit (1 or 0).
4739 */
4740 __STATIC_INLINE uint32_t LL_RCC_PLL2FRACN_IsEnabled(void)
4741 {
4742 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN) == RCC_PLLCFGR_PLL2FRACEN) ? 1UL : 0UL);
4743 }
4744
4745 /**
4746 * @brief Disable PLL2P
4747 * @note This API shall be called only when PLL2 is disabled.
4748 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL2P_Disable
4749 * @retval None
4750 */
4751 __STATIC_INLINE void LL_RCC_PLL2P_Disable(void)
4752 {
4753 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP2EN);
4754 }
4755
4756 /**
4757 * @brief Disable PLL2Q
4758 * @note This API shall be called only when PLL2 is disabled.
4759 * @rmtoll PLLCFGR DIVQ2EN LL_RCC_PLL2Q_Disable
4760 * @retval None
4761 */
4762 __STATIC_INLINE void LL_RCC_PLL2Q_Disable(void)
4763 {
4764 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ2EN);
4765 }
4766
4767 /**
4768 * @brief Disable PLL2R
4769 * @note This API shall be called only when PLL2 is disabled.
4770 * @rmtoll PLLCFGR DIVR2EN LL_RCC_PLL2R_Disable
4771 * @retval None
4772 */
4773 __STATIC_INLINE void LL_RCC_PLL2R_Disable(void)
4774 {
4775 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR2EN);
4776 }
4777
4778 /**
4779 * @brief Disable PLL2 FRACN
4780 * @rmtoll PLLCFGR PLL2FRACEN LL_RCC_PLL2FRACN_Enable
4781 * @retval None
4782 */
4783 __STATIC_INLINE void LL_RCC_PLL2FRACN_Disable(void)
4784 {
4785 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL2FRACEN);
4786 }
4787
4788 /**
4789 * @brief Set PLL2 VCO OutputRange
4790 * @note This API shall be called only when PLL2 is disabled.
4791 * @rmtoll PLLCFGR PLL2VCOSEL LL_RCC_PLL2_SetVCOOuputRange
4792 * @param VCORange This parameter can be one of the following values:
4793 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
4794 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
4795 * @retval None
4796 */
4797 __STATIC_INLINE void LL_RCC_PLL2_SetVCOOutputRange(uint32_t VCORange)
4798 {
4799 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2VCOSEL, VCORange << RCC_PLLCFGR_PLL2VCOSEL_Pos);
4800 }
4801
4802 /**
4803 * @brief Set PLL2 VCO Input Range
4804 * @note This API shall be called only when PLL2 is disabled.
4805 * @rmtoll PLLCFGR PLL2RGE LL_RCC_PLL2_SetVCOInputRange
4806 * @param InputRange This parameter can be one of the following values:
4807 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
4808 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
4809 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
4810 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
4811 * @retval None
4812 */
4813 __STATIC_INLINE void LL_RCC_PLL2_SetVCOInputRange(uint32_t InputRange)
4814 {
4815 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL2RGE, InputRange << RCC_PLLCFGR_PLL2RGE_Pos);
4816 }
4817
4818 /**
4819 * @brief Get PLL2 N Coefficient
4820 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_GetN
4821 * @retval A value between 4 and 512
4822 */
4823 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetN(void)
4824 {
4825 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_N2) >> RCC_PLL2DIVR_N2_Pos) + 1UL);
4826 }
4827
4828 /**
4829 * @brief Get PLL2 M Coefficient
4830 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_GetM
4831 * @retval A value between 0 and 63
4832 */
4833 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetM(void)
4834 {
4835 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2) >> RCC_PLLCKSELR_DIVM2_Pos);
4836 }
4837
4838 /**
4839 * @brief Get PLL2 P Coefficient
4840 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_GetP
4841 * @retval A value between 1 and 128
4842 */
4843 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetP(void)
4844 {
4845 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_P2) >> RCC_PLL2DIVR_P2_Pos) + 1UL);
4846 }
4847
4848 /**
4849 * @brief Get PLL2 Q Coefficient
4850 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_GetQ
4851 * @retval A value between 1 and 128
4852 */
4853 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetQ(void)
4854 {
4855 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2) >> RCC_PLL2DIVR_Q2_Pos) + 1UL);
4856 }
4857
4858 /**
4859 * @brief Get PLL2 R Coefficient
4860 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_GetR
4861 * @retval A value between 1 and 128
4862 */
4863 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetR(void)
4864 {
4865 return (uint32_t)((READ_BIT(RCC->PLL2DIVR, RCC_PLL2DIVR_R2) >> RCC_PLL2DIVR_R2_Pos) + 1UL);
4866 }
4867
4868 /**
4869 * @brief Get PLL2 FRACN Coefficient
4870 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_GetFRACN
4871 * @retval A value between 0 and 8191 (0x1FFF)
4872 */
4873 __STATIC_INLINE uint32_t LL_RCC_PLL2_GetFRACN(void)
4874 {
4875 return (uint32_t)(READ_BIT(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2) >> RCC_PLL2FRACR_FRACN2_Pos);
4876 }
4877
4878 /**
4879 * @brief Set PLL2 N Coefficient
4880 * @note This API shall be called only when PLL2 is disabled.
4881 * @rmtoll PLL2DIVR N2 LL_RCC_PLL2_SetN
4882 * @param N parameter can be a value between 4 and 512
4883 */
4884 __STATIC_INLINE void LL_RCC_PLL2_SetN(uint32_t N)
4885 {
4886 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_N2, (N - 1UL) << RCC_PLL2DIVR_N2_Pos);
4887 }
4888
4889 /**
4890 * @brief Set PLL2 M Coefficient
4891 * @note This API shall be called only when PLL2 is disabled.
4892 * @rmtoll PLLCKSELR DIVM2 LL_RCC_PLL2_SetM
4893 * @param M parameter can be a value between 0 and 63
4894 */
4895 __STATIC_INLINE void LL_RCC_PLL2_SetM(uint32_t M)
4896 {
4897 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM2, M << RCC_PLLCKSELR_DIVM2_Pos);
4898 }
4899
4900 /**
4901 * @brief Set PLL2 P Coefficient
4902 * @note This API shall be called only when PLL2 is disabled.
4903 * @rmtoll PLL2DIVR P2 LL_RCC_PLL2_SetP
4904 * @param P parameter can be a value between 1 and 128
4905 */
4906 __STATIC_INLINE void LL_RCC_PLL2_SetP(uint32_t P)
4907 {
4908 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_P2, (P - 1UL) << RCC_PLL2DIVR_P2_Pos);
4909 }
4910
4911 /**
4912 * @brief Set PLL2 Q Coefficient
4913 * @note This API shall be called only when PLL2 is disabled.
4914 * @rmtoll PLL2DIVR Q2 LL_RCC_PLL2_SetQ
4915 * @param Q parameter can be a value between 1 and 128
4916 */
4917 __STATIC_INLINE void LL_RCC_PLL2_SetQ(uint32_t Q)
4918 {
4919 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_Q2, (Q - 1UL) << RCC_PLL2DIVR_Q2_Pos);
4920 }
4921
4922 /**
4923 * @brief Set PLL2 R Coefficient
4924 * @note This API shall be called only when PLL2 is disabled.
4925 * @rmtoll PLL2DIVR R2 LL_RCC_PLL2_SetR
4926 * @param R parameter can be a value between 1 and 128
4927 */
4928 __STATIC_INLINE void LL_RCC_PLL2_SetR(uint32_t R)
4929 {
4930 MODIFY_REG(RCC->PLL2DIVR, RCC_PLL2DIVR_R2, (R - 1UL) << RCC_PLL2DIVR_R2_Pos);
4931 }
4932
4933 /**
4934 * @brief Set PLL2 FRACN Coefficient
4935 * @rmtoll PLL2FRACR FRACN2 LL_RCC_PLL2_SetFRACN
4936 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
4937 */
4938 __STATIC_INLINE void LL_RCC_PLL2_SetFRACN(uint32_t FRACN)
4939 {
4940 MODIFY_REG(RCC->PLL2FRACR, RCC_PLL2FRACR_FRACN2, FRACN << RCC_PLL2FRACR_FRACN2_Pos);
4941 }
4942
4943 /**
4944 * @brief Enable PLL3
4945 * @rmtoll CR PLL3ON LL_RCC_PLL3_Enable
4946 * @retval None
4947 */
4948 __STATIC_INLINE void LL_RCC_PLL3_Enable(void)
4949 {
4950 SET_BIT(RCC->CR, RCC_CR_PLL3ON);
4951 }
4952
4953 /**
4954 * @brief Disable PLL3
4955 * @note Cannot be disabled if the PLL3 clock is used as the system clock
4956 * @rmtoll CR PLL3ON LL_RCC_PLL3_Disable
4957 * @retval None
4958 */
4959 __STATIC_INLINE void LL_RCC_PLL3_Disable(void)
4960 {
4961 CLEAR_BIT(RCC->CR, RCC_CR_PLL3ON);
4962 }
4963
4964 /**
4965 * @brief Check if PLL3 Ready
4966 * @rmtoll CR PLL3RDY LL_RCC_PLL3_IsReady
4967 * @retval State of bit (1 or 0).
4968 */
4969 __STATIC_INLINE uint32_t LL_RCC_PLL3_IsReady(void)
4970 {
4971 return ((READ_BIT(RCC->CR, RCC_CR_PLL3RDY) == (RCC_CR_PLL3RDY)) ? 1UL : 0UL);
4972 }
4973
4974 /**
4975 * @brief Enable PLL3P
4976 * @note This API shall be called only when PLL3 is disabled.
4977 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_Enable
4978 * @retval None
4979 */
4980 __STATIC_INLINE void LL_RCC_PLL3P_Enable(void)
4981 {
4982 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
4983 }
4984
4985 /**
4986 * @brief Enable PLL3Q
4987 * @note This API shall be called only when PLL3 is disabled.
4988 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Enable
4989 * @retval None
4990 */
4991 __STATIC_INLINE void LL_RCC_PLL3Q_Enable(void)
4992 {
4993 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
4994 }
4995
4996 /**
4997 * @brief Enable PLL3R
4998 * @note This API shall be called only when PLL3 is disabled.
4999 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Enable
5000 * @retval None
5001 */
5002 __STATIC_INLINE void LL_RCC_PLL3R_Enable(void)
5003 {
5004 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5005 }
5006
5007 /**
5008 * @brief Enable PLL3 FRACN
5009 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5010 * @retval None
5011 */
5012 __STATIC_INLINE void LL_RCC_PLL3FRACN_Enable(void)
5013 {
5014 SET_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5015 }
5016
5017 /**
5018 * @brief Check if PLL3 P is enabled
5019 * @rmtoll PLLCFGR DIVP3EN LL_RCC_PLL3P_IsEnabled
5020 * @retval State of bit (1 or 0).
5021 */
5022 __STATIC_INLINE uint32_t LL_RCC_PLL3P_IsEnabled(void)
5023 {
5024 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN) == RCC_PLLCFGR_DIVP3EN) ? 1UL : 0UL);
5025 }
5026
5027 /**
5028 * @brief Check if PLL3 Q is enabled
5029 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_IsEnabled
5030 * @retval State of bit (1 or 0).
5031 */
5032 __STATIC_INLINE uint32_t LL_RCC_PLL3Q_IsEnabled(void)
5033 {
5034 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN) == RCC_PLLCFGR_DIVQ3EN) ? 1UL : 0UL);
5035 }
5036
5037 /**
5038 * @brief Check if PLL3 R is enabled
5039 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_IsEnabled
5040 * @retval State of bit (1 or 0).
5041 */
5042 __STATIC_INLINE uint32_t LL_RCC_PLL3R_IsEnabled(void)
5043 {
5044 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN) == RCC_PLLCFGR_DIVR3EN) ? 1UL : 0UL);
5045 }
5046
5047 /**
5048 * @brief Check if PLL3 FRACN is enabled
5049 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_IsEnabled
5050 * @retval State of bit (1 or 0).
5051 */
5052 __STATIC_INLINE uint32_t LL_RCC_PLL3FRACN_IsEnabled(void)
5053 {
5054 return ((READ_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN) == RCC_PLLCFGR_PLL3FRACEN) ? 1UL : 0UL);
5055 }
5056
5057 /**
5058 * @brief Disable PLL3P
5059 * @note This API shall be called only when PLL3 is disabled.
5060 * @rmtoll PLLCFGR DIVP2EN LL_RCC_PLL3P_Disable
5061 * @retval None
5062 */
5063 __STATIC_INLINE void LL_RCC_PLL3P_Disable(void)
5064 {
5065 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVP3EN);
5066 }
5067
5068 /**
5069 * @brief Disable PLL3Q
5070 * @note This API shall be called only when PLL3 is disabled.
5071 * @rmtoll PLLCFGR DIVQ3EN LL_RCC_PLL3Q_Disable
5072 * @retval None
5073 */
5074 __STATIC_INLINE void LL_RCC_PLL3Q_Disable(void)
5075 {
5076 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVQ3EN);
5077 }
5078
5079 /**
5080 * @brief Disable PLL3R
5081 * @note This API shall be called only when PLL3 is disabled.
5082 * @rmtoll PLLCFGR DIVR3EN LL_RCC_PLL3R_Disable
5083 * @retval None
5084 */
5085 __STATIC_INLINE void LL_RCC_PLL3R_Disable(void)
5086 {
5087 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_DIVR3EN);
5088 }
5089
5090 /**
5091 * @brief Disable PLL3 FRACN
5092 * @rmtoll PLLCFGR PLL3FRACEN LL_RCC_PLL3FRACN_Enable
5093 * @retval None
5094 */
5095 __STATIC_INLINE void LL_RCC_PLL3FRACN_Disable(void)
5096 {
5097 CLEAR_BIT(RCC->PLLCFGR, RCC_PLLCFGR_PLL3FRACEN);
5098 }
5099
5100 /**
5101 * @brief Set PLL3 VCO OutputRange
5102 * @note This API shall be called only when PLL3 is disabled.
5103 * @rmtoll PLLCFGR PLL3VCOSEL LL_RCC_PLL3_SetVCOOuputRange
5104 * @param VCORange This parameter can be one of the following values:
5105 * @arg @ref LL_RCC_PLLVCORANGE_WIDE
5106 * @arg @ref LL_RCC_PLLVCORANGE_MEDIUM
5107 * @retval None
5108 */
5109 __STATIC_INLINE void LL_RCC_PLL3_SetVCOOutputRange(uint32_t VCORange)
5110 {
5111 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3VCOSEL, VCORange << RCC_PLLCFGR_PLL3VCOSEL_Pos);
5112 }
5113
5114 /**
5115 * @brief Set PLL3 VCO Input Range
5116 * @note This API shall be called only when PLL3 is disabled.
5117 * @rmtoll PLLCFGR PLL3RGE LL_RCC_PLL3_SetVCOInputRange
5118 * @param InputRange This parameter can be one of the following values:
5119 * @arg @ref LL_RCC_PLLINPUTRANGE_1_2
5120 * @arg @ref LL_RCC_PLLINPUTRANGE_2_4
5121 * @arg @ref LL_RCC_PLLINPUTRANGE_4_8
5122 * @arg @ref LL_RCC_PLLINPUTRANGE_8_16
5123 * @retval None
5124 */
5125 __STATIC_INLINE void LL_RCC_PLL3_SetVCOInputRange(uint32_t InputRange)
5126 {
5127 MODIFY_REG(RCC->PLLCFGR, RCC_PLLCFGR_PLL3RGE, InputRange << RCC_PLLCFGR_PLL3RGE_Pos);
5128 }
5129
5130 /**
5131 * @brief Get PLL3 N Coefficient
5132 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_GetN
5133 * @retval A value between 4 and 512
5134 */
5135 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetN(void)
5136 {
5137 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_N3) >> RCC_PLL3DIVR_N3_Pos) + 1UL);
5138 }
5139
5140 /**
5141 * @brief Get PLL3 M Coefficient
5142 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_GetM
5143 * @retval A value between 0 and 63
5144 */
5145 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetM(void)
5146 {
5147 return (uint32_t)(READ_BIT(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3) >> RCC_PLLCKSELR_DIVM3_Pos);
5148 }
5149
5150 /**
5151 * @brief Get PLL3 P Coefficient
5152 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_GetP
5153 * @retval A value between 1 and 128
5154 */
5155 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetP(void)
5156 {
5157 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_P3) >> RCC_PLL3DIVR_P3_Pos) + 1UL);
5158 }
5159
5160 /**
5161 * @brief Get PLL3 Q Coefficient
5162 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_GetQ
5163 * @retval A value between 1 and 128
5164 */
5165 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetQ(void)
5166 {
5167 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3) >> RCC_PLL3DIVR_Q3_Pos) + 1UL);
5168 }
5169
5170 /**
5171 * @brief Get PLL3 R Coefficient
5172 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_GetR
5173 * @retval A value between 1 and 128
5174 */
5175 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetR(void)
5176 {
5177 return (uint32_t)((READ_BIT(RCC->PLL3DIVR, RCC_PLL3DIVR_R3) >> RCC_PLL3DIVR_R3_Pos) + 1UL);
5178 }
5179
5180 /**
5181 * @brief Get PLL3 FRACN Coefficient
5182 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_GetFRACN
5183 * @retval A value between 0 and 8191 (0x1FFF)
5184 */
5185 __STATIC_INLINE uint32_t LL_RCC_PLL3_GetFRACN(void)
5186 {
5187 return (uint32_t)(READ_BIT(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3) >> RCC_PLL3FRACR_FRACN3_Pos);
5188 }
5189
5190 /**
5191 * @brief Set PLL3 N Coefficient
5192 * @note This API shall be called only when PLL3 is disabled.
5193 * @rmtoll PLL3DIVR N3 LL_RCC_PLL3_SetN
5194 * @param N parameter can be a value between 4 and 512
5195 */
5196 __STATIC_INLINE void LL_RCC_PLL3_SetN(uint32_t N)
5197 {
5198 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_N3, (N - 1UL) << RCC_PLL3DIVR_N3_Pos);
5199 }
5200
5201 /**
5202 * @brief Set PLL3 M Coefficient
5203 * @note This API shall be called only when PLL3 is disabled.
5204 * @rmtoll PLLCKSELR DIVM3 LL_RCC_PLL3_SetM
5205 * @param M parameter can be a value between 0 and 63
5206 */
5207 __STATIC_INLINE void LL_RCC_PLL3_SetM(uint32_t M)
5208 {
5209 MODIFY_REG(RCC->PLLCKSELR, RCC_PLLCKSELR_DIVM3, M << RCC_PLLCKSELR_DIVM3_Pos);
5210 }
5211
5212 /**
5213 * @brief Set PLL3 P Coefficient
5214 * @note This API shall be called only when PLL3 is disabled.
5215 * @rmtoll PLL3DIVR P3 LL_RCC_PLL3_SetP
5216 * @param P parameter can be a value between 1 and 128
5217 */
5218 __STATIC_INLINE void LL_RCC_PLL3_SetP(uint32_t P)
5219 {
5220 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_P3, (P - 1UL) << RCC_PLL3DIVR_P3_Pos);
5221 }
5222
5223 /**
5224 * @brief Set PLL3 Q Coefficient
5225 * @note This API shall be called only when PLL3 is disabled.
5226 * @rmtoll PLL3DIVR Q3 LL_RCC_PLL3_SetQ
5227 * @param Q parameter can be a value between 1 and 128
5228 */
5229 __STATIC_INLINE void LL_RCC_PLL3_SetQ(uint32_t Q)
5230 {
5231 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_Q3, (Q - 1UL) << RCC_PLL3DIVR_Q3_Pos);
5232 }
5233
5234 /**
5235 * @brief Set PLL3 R Coefficient
5236 * @note This API shall be called only when PLL3 is disabled.
5237 * @rmtoll PLL3DIVR R3 LL_RCC_PLL3_SetR
5238 * @param R parameter can be a value between 1 and 128
5239 */
5240 __STATIC_INLINE void LL_RCC_PLL3_SetR(uint32_t R)
5241 {
5242 MODIFY_REG(RCC->PLL3DIVR, RCC_PLL3DIVR_R3, (R - 1UL) << RCC_PLL3DIVR_R3_Pos);
5243 }
5244
5245 /**
5246 * @brief Set PLL3 FRACN Coefficient
5247 * @rmtoll PLL3FRACR FRACN3 LL_RCC_PLL3_SetFRACN
5248 * @param FRACN parameter can be a value between 0 and 8191 (0x1FFF)
5249 */
5250 __STATIC_INLINE void LL_RCC_PLL3_SetFRACN(uint32_t FRACN)
5251 {
5252 MODIFY_REG(RCC->PLL3FRACR, RCC_PLL3FRACR_FRACN3, FRACN << RCC_PLL3FRACR_FRACN3_Pos);
5253 }
5254
5255
5256 /**
5257 * @}
5258 */
5259
5260
5261 /** @defgroup RCC_LL_EF_FLAG_Management FLAG Management
5262 * @{
5263 */
5264
5265 /**
5266 * @brief Clear LSI ready interrupt flag
5267 * @rmtoll CICR LSIRDYC LL_RCC_ClearFlag_LSIRDY
5268 * @retval None
5269 */
5270 __STATIC_INLINE void LL_RCC_ClearFlag_LSIRDY(void)
5271 {
5272 SET_BIT(RCC->CICR, RCC_CICR_LSIRDYC);
5273 }
5274
5275 /**
5276 * @brief Clear LSE ready interrupt flag
5277 * @rmtoll CICR LSERDYC LL_RCC_ClearFlag_LSERDY
5278 * @retval None
5279 */
5280 __STATIC_INLINE void LL_RCC_ClearFlag_LSERDY(void)
5281 {
5282 SET_BIT(RCC->CICR, RCC_CICR_LSERDYC);
5283 }
5284
5285 /**
5286 * @brief Clear HSI ready interrupt flag
5287 * @rmtoll CICR HSIRDYC LL_RCC_ClearFlag_HSIRDY
5288 * @retval None
5289 */
5290 __STATIC_INLINE void LL_RCC_ClearFlag_HSIRDY(void)
5291 {
5292 SET_BIT(RCC->CICR, RCC_CICR_HSIRDYC);
5293 }
5294
5295 /**
5296 * @brief Clear HSE ready interrupt flag
5297 * @rmtoll CICR HSERDYC LL_RCC_ClearFlag_HSERDY
5298 * @retval None
5299 */
5300 __STATIC_INLINE void LL_RCC_ClearFlag_HSERDY(void)
5301 {
5302 SET_BIT(RCC->CICR, RCC_CICR_HSERDYC);
5303 }
5304
5305 /**
5306 * @brief Clear CSI ready interrupt flag
5307 * @rmtoll CICR CSIRDYC LL_RCC_ClearFlag_CSIRDY
5308 * @retval None
5309 */
5310 __STATIC_INLINE void LL_RCC_ClearFlag_CSIRDY(void)
5311 {
5312 SET_BIT(RCC->CICR, RCC_CICR_CSIRDYC);
5313 }
5314
5315 /**
5316 * @brief Clear HSI48 ready interrupt flag
5317 * @rmtoll CICR HSI48RDYC LL_RCC_ClearFlag_HSI48RDY
5318 * @retval None
5319 */
5320 __STATIC_INLINE void LL_RCC_ClearFlag_HSI48RDY(void)
5321 {
5322 SET_BIT(RCC->CICR, RCC_CICR_HSI48RDYC);
5323 }
5324
5325 /**
5326 * @brief Clear PLL1 ready interrupt flag
5327 * @rmtoll CICR PLL1RDYC LL_RCC_ClearFlag_PLL1RDY
5328 * @retval None
5329 */
5330 __STATIC_INLINE void LL_RCC_ClearFlag_PLL1RDY(void)
5331 {
5332 SET_BIT(RCC->CICR, RCC_CICR_PLLRDYC);
5333 }
5334
5335 /**
5336 * @brief Clear PLL2 ready interrupt flag
5337 * @rmtoll CICR PLL2RDYC LL_RCC_ClearFlag_PLL2RDY
5338 * @retval None
5339 */
5340 __STATIC_INLINE void LL_RCC_ClearFlag_PLL2RDY(void)
5341 {
5342 SET_BIT(RCC->CICR, RCC_CICR_PLL2RDYC);
5343 }
5344
5345 /**
5346 * @brief Clear PLL3 ready interrupt flag
5347 * @rmtoll CICR PLL3RDYC LL_RCC_ClearFlag_PLL3RDY
5348 * @retval None
5349 */
5350 __STATIC_INLINE void LL_RCC_ClearFlag_PLL3RDY(void)
5351 {
5352 SET_BIT(RCC->CICR, RCC_CICR_PLL3RDYC);
5353 }
5354
5355 /**
5356 * @brief Clear LSE Clock security system interrupt flag
5357 * @rmtoll CICR LSECSSC LL_RCC_ClearFlag_LSECSS
5358 * @retval None
5359 */
5360 __STATIC_INLINE void LL_RCC_ClearFlag_LSECSS(void)
5361 {
5362 SET_BIT(RCC->CICR, RCC_CICR_LSECSSC);
5363 }
5364
5365 /**
5366 * @brief Clear HSE Clock security system interrupt flag
5367 * @rmtoll CICR HSECSSC LL_RCC_ClearFlag_HSECSS
5368 * @retval None
5369 */
5370 __STATIC_INLINE void LL_RCC_ClearFlag_HSECSS(void)
5371 {
5372 SET_BIT(RCC->CICR, RCC_CICR_HSECSSC);
5373 }
5374
5375 /**
5376 * @brief Check if LSI ready interrupt occurred or not
5377 * @rmtoll CIFR LSIRDYF LL_RCC_IsActiveFlag_LSIRDY
5378 * @retval State of bit (1 or 0).
5379 */
5380 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSIRDY(void)
5381 {
5382 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSIRDYF) == (RCC_CIFR_LSIRDYF)) ? 1UL : 0UL);
5383 }
5384
5385 /**
5386 * @brief Check if LSE ready interrupt occurred or not
5387 * @rmtoll CIFR LSERDYF LL_RCC_IsActiveFlag_LSERDY
5388 * @retval State of bit (1 or 0).
5389 */
5390 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSERDY(void)
5391 {
5392 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSERDYF) == (RCC_CIFR_LSERDYF)) ? 1UL : 0UL);
5393 }
5394
5395 /**
5396 * @brief Check if HSI ready interrupt occurred or not
5397 * @rmtoll CIFR HSIRDYF LL_RCC_IsActiveFlag_HSIRDY
5398 * @retval State of bit (1 or 0).
5399 */
5400 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSIRDY(void)
5401 {
5402 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSIRDYF) == (RCC_CIFR_HSIRDYF)) ? 1UL : 0UL);
5403 }
5404
5405 /**
5406 * @brief Check if HSE ready interrupt occurred or not
5407 * @rmtoll CIFR HSERDYF LL_RCC_IsActiveFlag_HSERDY
5408 * @retval State of bit (1 or 0).
5409 */
5410 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSERDY(void)
5411 {
5412 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSERDYF) == (RCC_CIFR_HSERDYF)) ? 1UL : 0UL);
5413 }
5414
5415 /**
5416 * @brief Check if CSI ready interrupt occurred or not
5417 * @rmtoll CIFR CSIRDYF LL_RCC_IsActiveFlag_CSIRDY
5418 * @retval State of bit (1 or 0).
5419 */
5420 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CSIRDY(void)
5421 {
5422 return ((READ_BIT(RCC->CIFR, RCC_CIFR_CSIRDYF) == (RCC_CIFR_CSIRDYF)) ? 1UL : 0UL);
5423 }
5424
5425 /**
5426 * @brief Check if HSI48 ready interrupt occurred or not
5427 * @rmtoll CIFR HSI48RDYF LL_RCC_IsActiveFlag_HSI48RDY
5428 * @retval State of bit (1 or 0).
5429 */
5430 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSI48RDY(void)
5431 {
5432 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSI48RDYF) == (RCC_CIFR_HSI48RDYF)) ? 1UL : 0UL);
5433 }
5434
5435 /**
5436 * @brief Check if PLL1 ready interrupt occurred or not
5437 * @rmtoll CIFR PLLRDYF LL_RCC_IsActiveFlag_PLL1RDY
5438 * @retval State of bit (1 or 0).
5439 */
5440 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL1RDY(void)
5441 {
5442 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLLRDYF) == (RCC_CIFR_PLLRDYF)) ? 1UL : 0UL);
5443 }
5444
5445 /**
5446 * @brief Check if PLL2 ready interrupt occurred or not
5447 * @rmtoll CIFR PLL2RDYF LL_RCC_IsActiveFlag_PLL2RDY
5448 * @retval State of bit (1 or 0).
5449 */
5450 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL2RDY(void)
5451 {
5452 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL2RDYF) == (RCC_CIFR_PLL2RDYF)) ? 1UL : 0UL);
5453 }
5454
5455 /**
5456 * @brief Check if PLL3 ready interrupt occurred or not
5457 * @rmtoll CIFR PLL3RDYF LL_RCC_IsActiveFlag_PLL3RDY
5458 * @retval State of bit (1 or 0).
5459 */
5460 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PLL3RDY(void)
5461 {
5462 return ((READ_BIT(RCC->CIFR, RCC_CIFR_PLL3RDYF) == (RCC_CIFR_PLL3RDYF)) ? 1UL : 0UL);
5463 }
5464
5465 /**
5466 * @brief Check if LSE Clock security system interrupt occurred or not
5467 * @rmtoll CIFR LSECSSF LL_RCC_IsActiveFlag_LSECSS
5468 * @retval State of bit (1 or 0).
5469 */
5470 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LSECSS(void)
5471 {
5472 return ((READ_BIT(RCC->CIFR, RCC_CIFR_LSECSSF) == (RCC_CIFR_LSECSSF)) ? 1UL : 0UL);
5473 }
5474
5475 /**
5476 * @brief Check if HSE Clock security system interrupt occurred or not
5477 * @rmtoll CIFR HSECSSF LL_RCC_IsActiveFlag_HSECSS
5478 * @retval State of bit (1 or 0).
5479 */
5480 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_HSECSS(void)
5481 {
5482 return ((READ_BIT(RCC->CIFR, RCC_CIFR_HSECSSF) == (RCC_CIFR_HSECSSF)) ? 1UL : 0UL);
5483 }
5484
5485 /**
5486 * @brief Check if RCC flag Low Power D1 reset is set or not.
5487 * @rmtoll RSR LPWRRSTF LL_RCC_IsActiveFlag_LPWRRST (*)\n
5488 * RSR LPWR1RSTF LL_RCC_IsActiveFlag_LPWRRST (**)
5489 *
5490 * (*) Only available for single core devices
5491 * (**) Only available for Dual core devices
5492 * @retval State of bit (1 or 0).
5493 */
5494 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWRRST(void)
5495 {
5496 #if defined(DUAL_CORE)
5497 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5498 #else
5499 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWRRSTF) == (RCC_RSR_LPWRRSTF)) ? 1UL : 0UL);
5500 #endif /*DUAL_CORE*/
5501 }
5502
5503 #if defined(DUAL_CORE)
5504 /**
5505 * @brief Check if RCC flag Low Power D2 reset is set or not.
5506 * @rmtoll RSR LPWR2RSTF LL_RCC_IsActiveFlag_LPWR2RST
5507 * @retval State of bit (1 or 0).
5508 */
5509 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_LPWR2RST(void)
5510 {
5511 return ((READ_BIT(RCC->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5512 }
5513 #endif /*DUAL_CORE*/
5514
5515 /**
5516 * @brief Check if RCC flag Window Watchdog 1 reset is set or not.
5517 * @rmtoll RSR WWDG1RSTF LL_RCC_IsActiveFlag_WWDG1RST
5518 * @retval State of bit (1 or 0).
5519 */
5520 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG1RST(void)
5521 {
5522 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5523 }
5524
5525 #if defined(DUAL_CORE)
5526 /**
5527 * @brief Check if RCC flag Window Watchdog 2 reset is set or not.
5528 * @rmtoll RSR WWDG2RSTF LL_RCC_IsActiveFlag_WWDG2RST
5529 * @retval State of bit (1 or 0).
5530 */
5531 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_WWDG2RST(void)
5532 {
5533 return ((READ_BIT(RCC->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5534 }
5535 #endif /*DUAL_CORE*/
5536
5537 /**
5538 * @brief Check if RCC flag Independent Watchdog 1 reset is set or not.
5539 * @rmtoll RSR IWDG1RSTF LL_RCC_IsActiveFlag_IWDG1RST
5540 * @retval State of bit (1 or 0).
5541 */
5542 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG1RST(void)
5543 {
5544 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
5545 }
5546
5547 #if defined(DUAL_CORE)
5548 /**
5549 * @brief Check if RCC flag Independent Watchdog 2 reset is set or not.
5550 * @rmtoll RSR IWDG2RSTF LL_RCC_IsActiveFlag_IWDG2RST
5551 * @retval State of bit (1 or 0).
5552 */
5553 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_IWDG2RST(void)
5554 {
5555 return ((READ_BIT(RCC->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
5556 }
5557 #endif /*DUAL_CORE*/
5558
5559 /**
5560 * @brief Check if RCC flag Software reset is set or not.
5561 * @rmtoll RSR SFTRSTF LL_RCC_IsActiveFlag_SFTRST (*)\n
5562 * RSR SFT1RSTF LL_RCC_IsActiveFlag_SFTRST (**)
5563 *
5564 * (*) Only available for single core devices
5565 * (**) Only available for Dual core devices
5566 * @retval State of bit (1 or 0).
5567 */
5568 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFTRST(void)
5569 {
5570 #if defined(DUAL_CORE)
5571 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
5572 #else
5573 return ((READ_BIT(RCC->RSR, RCC_RSR_SFTRSTF) == (RCC_RSR_SFTRSTF)) ? 1UL : 0UL);
5574 #endif /*DUAL_CORE*/
5575 }
5576
5577 #if defined(DUAL_CORE)
5578 /**
5579 * @brief Check if RCC flag Software reset is set or not.
5580 * @rmtoll RSR SFT2RSTF LL_RCC_IsActiveFlag_SFT2RST
5581 * @retval State of bit (1 or 0).
5582 */
5583 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_SFT2RST(void)
5584 {
5585 return ((READ_BIT(RCC->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
5586 }
5587 #endif /*DUAL_CORE*/
5588
5589 /**
5590 * @brief Check if RCC flag POR/PDR reset is set or not.
5591 * @rmtoll RSR PORRSTF LL_RCC_IsActiveFlag_PORRST
5592 * @retval State of bit (1 or 0).
5593 */
5594 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PORRST(void)
5595 {
5596 return ((READ_BIT(RCC->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
5597 }
5598
5599 /**
5600 * @brief Check if RCC flag Pin reset is set or not.
5601 * @rmtoll RSR PINRSTF LL_RCC_IsActiveFlag_PINRST
5602 * @retval State of bit (1 or 0).
5603 */
5604 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_PINRST(void)
5605 {
5606 return ((READ_BIT(RCC->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
5607 }
5608
5609 /**
5610 * @brief Check if RCC flag BOR reset is set or not.
5611 * @rmtoll RSR BORRSTF LL_RCC_IsActiveFlag_BORRST
5612 * @retval State of bit (1 or 0).
5613 */
5614 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_BORRST(void)
5615 {
5616 return ((READ_BIT(RCC->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5617 }
5618
5619 #if defined(RCC_RSR_D1RSTF)
5620 /**
5621 * @brief Check if RCC flag D1 reset is set or not.
5622 * @rmtoll RSR D1RSTF LL_RCC_IsActiveFlag_D1RST
5623 * @retval State of bit (1 or 0).
5624 */
5625 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D1RST(void)
5626 {
5627 return ((READ_BIT(RCC->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
5628 }
5629 #endif /* RCC_RSR_D1RSTF */
5630
5631 #if defined(RCC_RSR_CDRSTF)
5632 /**
5633 * @brief Check if RCC flag CD reset is set or not.
5634 * @rmtoll RSR CDRSTF LL_RCC_IsActiveFlag_CDRST
5635 * @retval State of bit (1 or 0).
5636 */
5637 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CDRST(void)
5638 {
5639 return ((READ_BIT(RCC->RSR, RCC_RSR_CDRSTF) == (RCC_RSR_CDRSTF)) ? 1UL : 0UL);
5640 }
5641 #endif /* RCC_RSR_CDRSTF */
5642
5643 #if defined(RCC_RSR_D2RSTF)
5644 /**
5645 * @brief Check if RCC flag D2 reset is set or not.
5646 * @rmtoll RSR D2RSTF LL_RCC_IsActiveFlag_D2RST
5647 * @retval State of bit (1 or 0).
5648 */
5649 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_D2RST(void)
5650 {
5651 return ((READ_BIT(RCC->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
5652 }
5653 #endif /* RCC_RSR_D2RSTF */
5654
5655 #if defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF)
5656 /**
5657 * @brief Check if RCC flag CPU reset is set or not.
5658 * @rmtoll RSR CPURSTF LL_RCC_IsActiveFlag_CPURST (*)\n
5659 * RSR C1RSTF LL_RCC_IsActiveFlag_CPURST (**)
5660 *
5661 * (*) Only available for single core devices
5662 * (**) Only available for Dual core devices
5663 * @retval State of bit (1 or 0).
5664 */
5665 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPURST(void)
5666 {
5667 #if defined(DUAL_CORE)
5668 return ((READ_BIT(RCC->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
5669 #else
5670 return ((READ_BIT(RCC->RSR, RCC_RSR_CPURSTF) == (RCC_RSR_CPURSTF)) ? 1UL : 0UL);
5671 #endif/*DUAL_CORE*/
5672 }
5673 #endif /* defined(RCC_RSR_C1RSTF) || defined(RCC_RSR_CPURSTF) */
5674
5675 #if defined(DUAL_CORE)
5676 /**
5677 * @brief Check if RCC flag CPU2 reset is set or not.
5678 * @rmtoll RSR C2RSTF LL_RCC_IsActiveFlag_CPU2RST
5679 * @retval State of bit (1 or 0).
5680 */
5681 __STATIC_INLINE uint32_t LL_RCC_IsActiveFlag_CPU2RST(void)
5682 {
5683 return ((READ_BIT(RCC->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
5684 }
5685 #endif /*DUAL_CORE*/
5686
5687 /**
5688 * @brief Set RMVF bit to clear all reset flags.
5689 * @rmtoll RSR RMVF LL_RCC_ClearResetFlags
5690 * @retval None
5691 */
5692 __STATIC_INLINE void LL_RCC_ClearResetFlags(void)
5693 {
5694 SET_BIT(RCC->RSR, RCC_RSR_RMVF);
5695 }
5696
5697 #if defined(DUAL_CORE)
5698 /**
5699 * @brief Check if RCC_C1 flag Low Power D1 reset is set or not.
5700 * @rmtoll RSR LPWR1RSTF LL_C1_RCC_IsActiveFlag_LPWRRST
5701 * @retval State of bit (1 or 0).
5702 */
5703 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWRRST(void)
5704 {
5705 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5706 }
5707
5708 /**
5709 * @brief Check if RCC_C1 flag Low Power D2 reset is set or not.
5710 * @rmtoll RSR LPWR2RSTF LL_C1_RCC_IsActiveFlag_LPWR2RST
5711 * @retval State of bit (1 or 0).
5712 */
5713 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_LPWR2RST(void)
5714 {
5715 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5716 }
5717
5718 /**
5719 * @brief Check if RCC_C1 flag Window Watchdog 1 reset is set or not.
5720 * @rmtoll RSR WWDG1RSTF LL_C1_RCC_IsActiveFlag_WWDG1RST
5721 * @retval State of bit (1 or 0).
5722 */
5723 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG1RST(void)
5724 {
5725 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5726 }
5727
5728 /**
5729 * @brief Check if RCC_C1 flag Window Watchdog 2 reset is set or not.
5730 * @rmtoll RSR WWDG2RSTF LL_C1_RCC_IsActiveFlag_WWDG2RST
5731 * @retval State of bit (1 or 0).
5732 */
5733 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_WWDG2RST(void)
5734 {
5735 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5736 }
5737
5738 /**
5739 * @brief Check if RCC_C1 flag Independent Watchdog 1 reset is set or not.
5740 * @rmtoll RSR IWDG1RSTF LL_C1_RCC_IsActiveFlag_IWDG1RST
5741 * @retval State of bit (1 or 0).
5742 */
5743 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG1RST(void)
5744 {
5745 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
5746 }
5747
5748 /**
5749 * @brief Check if RCC_C1 flag Independent Watchdog 2 reset is set or not.
5750 * @rmtoll RSR IWDG2RSTF LL_C1_RCC_IsActiveFlag_IWDG2RST
5751 * @retval State of bit (1 or 0).
5752 */
5753 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_IWDG2RST(void)
5754 {
5755 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
5756 }
5757
5758 /**
5759 * @brief Check if RCC_C1 flag Software reset is set or not.
5760 * @rmtoll RSR SFT1RSTF LL_C1_RCC_IsActiveFlag_SFTRST
5761 * @retval State of bit (1 or 0).
5762 */
5763 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFTRST(void)
5764 {
5765 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
5766 }
5767
5768 /**
5769 * @brief Check if RCC_C1 flag Software reset is set or not.
5770 * @rmtoll RSR SFT2RSTF LL_C1_RCC_IsActiveFlag_SFT2RST
5771 * @retval State of bit (1 or 0).
5772 */
5773 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_SFT2RST(void)
5774 {
5775 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
5776 }
5777
5778 /**
5779 * @brief Check if RCC_C1 flag POR/PDR reset is set or not.
5780 * @rmtoll RSR PORRSTF LL_C1_RCC_IsActiveFlag_PORRST
5781 * @retval State of bit (1 or 0).
5782 */
5783 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PORRST(void)
5784 {
5785 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
5786 }
5787
5788 /**
5789 * @brief Check if RCC_C1 flag Pin reset is set or not.
5790 * @rmtoll RSR PINRSTF LL_C1_RCC_IsActiveFlag_PINRST
5791 * @retval State of bit (1 or 0).
5792 */
5793 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_PINRST(void)
5794 {
5795 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
5796 }
5797
5798 /**
5799 * @brief Check if RCC_C1 flag BOR reset is set or not.
5800 * @rmtoll RSR BORRSTF LL_C1_RCC_IsActiveFlag_BORRST
5801 * @retval State of bit (1 or 0).
5802 */
5803 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_BORRST(void)
5804 {
5805 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5806 }
5807
5808 /**
5809 * @brief Check if RCC_C1 flag D1 reset is set or not.
5810 * @rmtoll RSR D1RSTF LL_C1_RCC_IsActiveFlag_D1RST
5811 * @retval State of bit (1 or 0).
5812 */
5813 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D1RST(void)
5814 {
5815 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
5816 }
5817
5818 /**
5819 * @brief Check if RCC_C1 flag D2 reset is set or not.
5820 * @rmtoll RSR D2RSTF LL_C1_RCC_IsActiveFlag_D2RST
5821 * @retval State of bit (1 or 0).
5822 */
5823 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_D2RST(void)
5824 {
5825 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
5826 }
5827
5828 /**
5829 * @brief Check if RCC_C1 flag CPU reset is set or not.
5830 * @rmtoll RSR C1RSTF LL_C1_RCC_IsActiveFlag_CPURST
5831 * @retval State of bit (1 or 0).
5832 */
5833 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPURST(void)
5834 {
5835 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
5836 }
5837
5838 /**
5839 * @brief Check if RCC_C1 flag CPU2 reset is set or not.
5840 * @rmtoll RSR C2RSTF LL_C1_RCC_IsActiveFlag_CPU2RST
5841 * @retval State of bit (1 or 0).
5842 */
5843 __STATIC_INLINE uint32_t LL_C1_RCC_IsActiveFlag_CPU2RST(void)
5844 {
5845 return ((READ_BIT(RCC_C1->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
5846 }
5847
5848 /**
5849 * @brief Set RMVF bit to clear the reset flags.
5850 * @rmtoll RSR RMVF LL_C1_RCC_ClearResetFlags
5851 * @retval None
5852 */
5853 __STATIC_INLINE void LL_C1_RCC_ClearResetFlags(void)
5854 {
5855 SET_BIT(RCC_C1->RSR, RCC_RSR_RMVF);
5856 }
5857
5858 /**
5859 * @brief Check if RCC_C2 flag Low Power D1 reset is set or not.
5860 * @rmtoll RSR LPWR1RSTF LL_C2_RCC_IsActiveFlag_LPWRRST
5861 * @retval State of bit (1 or 0).
5862 */
5863 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWRRST(void)
5864 {
5865 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR1RSTF) == (RCC_RSR_LPWR1RSTF)) ? 1UL : 0UL);
5866 }
5867
5868 /**
5869 * @brief Check if RCC_C2 flag Low Power D2 reset is set or not.
5870 * @rmtoll RSR LPWR2RSTF LL_C2_RCC_IsActiveFlag_LPWR2RST
5871 * @retval State of bit (1 or 0).
5872 */
5873 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_LPWR2RST(void)
5874 {
5875 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_LPWR2RSTF) == (RCC_RSR_LPWR2RSTF)) ? 1UL : 0UL);
5876 }
5877
5878 /**
5879 * @brief Check if RCC_C2 flag Window Watchdog 1 reset is set or not.
5880 * @rmtoll RSR WWDG1RSTF LL_C2_RCC_IsActiveFlag_WWDG1RST
5881 * @retval State of bit (1 or 0).
5882 */
5883 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG1RST(void)
5884 {
5885 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG1RSTF) == (RCC_RSR_WWDG1RSTF)) ? 1UL : 0UL);
5886 }
5887
5888 /**
5889 * @brief Check if RCC_C2 flag Window Watchdog 2 reset is set or not.
5890 * @rmtoll RSR WWDG2RSTF LL_C2_RCC_IsActiveFlag_WWDG2RST
5891 * @retval State of bit (1 or 0).
5892 */
5893 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_WWDG2RST(void)
5894 {
5895 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_WWDG2RSTF) == (RCC_RSR_WWDG2RSTF)) ? 1UL : 0UL);
5896 }
5897
5898 /**
5899 * @brief Check if RCC_C2 flag Independent Watchdog 1 reset is set or not.
5900 * @rmtoll RSR IWDG1RSTF LL_C2_RCC_IsActiveFlag_IWDG1RST
5901 * @retval State of bit (1 or 0).
5902 */
5903 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG1RST(void)
5904 {
5905 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG1RSTF) == (RCC_RSR_IWDG1RSTF)) ? 1UL : 0UL);
5906 }
5907
5908 /**
5909 * @brief Check if RCC_C2 flag Independent Watchdog 2 reset is set or not.
5910 * @rmtoll RSR IWDG2RSTF LL_C2_RCC_IsActiveFlag_IWDG2RST
5911 * @retval State of bit (1 or 0).
5912 */
5913 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_IWDG2RST(void)
5914 {
5915 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_IWDG2RSTF) == (RCC_RSR_IWDG2RSTF)) ? 1UL : 0UL);
5916 }
5917
5918 /**
5919 * @brief Check if RCC_C2 flag Software reset is set or not.
5920 * @rmtoll RSR SFT1RSTF LL_C2_RCC_IsActiveFlag_SFTRST
5921 * @retval State of bit (1 or 0).
5922 */
5923 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFTRST(void)
5924 {
5925 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT1RSTF) == (RCC_RSR_SFT1RSTF)) ? 1UL : 0UL);
5926 }
5927
5928 /**
5929 * @brief Check if RCC_C2 flag Software reset is set or not.
5930 * @rmtoll RSR SFT2RSTF LL_C2_RCC_IsActiveFlag_SFT2RST
5931 * @retval State of bit (1 or 0).
5932 */
5933 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_SFT2RST(void)
5934 {
5935 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_SFT2RSTF) == (RCC_RSR_SFT2RSTF)) ? 1UL : 0UL);
5936 }
5937
5938 /**
5939 * @brief Check if RCC_C2 flag POR/PDR reset is set or not.
5940 * @rmtoll RSR PORRSTF LL_C2_RCC_IsActiveFlag_PORRST
5941 * @retval State of bit (1 or 0).
5942 */
5943 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PORRST(void)
5944 {
5945 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PORRSTF) == (RCC_RSR_PORRSTF)) ? 1UL : 0UL);
5946 }
5947
5948 /**
5949 * @brief Check if RCC_C2 flag Pin reset is set or not.
5950 * @rmtoll RSR PINRSTF LL_C2_RCC_IsActiveFlag_PINRST
5951 * @retval State of bit (1 or 0).
5952 */
5953 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_PINRST(void)
5954 {
5955 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_PINRSTF) == (RCC_RSR_PINRSTF)) ? 1UL : 0UL);
5956 }
5957
5958 /**
5959 * @brief Check if RCC_C2 flag BOR reset is set or not.
5960 * @rmtoll RSR BORRSTF LL_C2_RCC_IsActiveFlag_BORRST
5961 * @retval State of bit (1 or 0).
5962 */
5963 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_BORRST(void)
5964 {
5965 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_BORRSTF) == (RCC_RSR_BORRSTF)) ? 1UL : 0UL);
5966 }
5967
5968 /**
5969 * @brief Check if RCC_C2 flag D1 reset is set or not.
5970 * @rmtoll RSR D1RSTF LL_C2_RCC_IsActiveFlag_D1RST
5971 * @retval State of bit (1 or 0).
5972 */
5973 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D1RST(void)
5974 {
5975 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D1RSTF) == (RCC_RSR_D1RSTF)) ? 1UL : 0UL);
5976 }
5977
5978 /**
5979 * @brief Check if RCC_C2 flag D2 reset is set or not.
5980 * @rmtoll RSR D2RSTF LL_C2_RCC_IsActiveFlag_D2RST
5981 * @retval State of bit (1 or 0).
5982 */
5983 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_D2RST(void)
5984 {
5985 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_D2RSTF) == (RCC_RSR_D2RSTF)) ? 1UL : 0UL);
5986 }
5987
5988 /**
5989 * @brief Check if RCC_C2 flag CPU reset is set or not.
5990 * @rmtoll RSR C1RSTF LL_C2_RCC_IsActiveFlag_CPURST
5991 * @retval State of bit (1 or 0).
5992 */
5993 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPURST(void)
5994 {
5995 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C1RSTF) == (RCC_RSR_C1RSTF)) ? 1UL : 0UL);
5996 }
5997
5998 /**
5999 * @brief Check if RCC_C2 flag CPU2 reset is set or not.
6000 * @rmtoll RSR C2RSTF LL_C2_RCC_IsActiveFlag_CPU2RST
6001 * @retval State of bit (1 or 0).
6002 */
6003 __STATIC_INLINE uint32_t LL_C2_RCC_IsActiveFlag_CPU2RST(void)
6004 {
6005 return ((READ_BIT(RCC_C2->RSR, RCC_RSR_C2RSTF) == (RCC_RSR_C2RSTF)) ? 1UL : 0UL);
6006 }
6007
6008 /**
6009 * @brief Set RMVF bit to clear the reset flags.
6010 * @rmtoll RSR RMVF LL_C2_RCC_ClearResetFlags
6011 * @retval None
6012 */
6013 __STATIC_INLINE void LL_C2_RCC_ClearResetFlags(void)
6014 {
6015 SET_BIT(RCC_C2->RSR, RCC_RSR_RMVF);
6016 }
6017 #endif /*DUAL_CORE*/
6018
6019 /**
6020 * @}
6021 */
6022
6023 /** @defgroup RCC_LL_EF_IT_Management IT Management
6024 * @{
6025 */
6026
6027 /**
6028 * @brief Enable LSI ready interrupt
6029 * @rmtoll CIER LSIRDYIE LL_RCC_EnableIT_LSIRDY
6030 * @retval None
6031 */
6032 __STATIC_INLINE void LL_RCC_EnableIT_LSIRDY(void)
6033 {
6034 SET_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6035 }
6036
6037 /**
6038 * @brief Enable LSE ready interrupt
6039 * @rmtoll CIER LSERDYIE LL_RCC_EnableIT_LSERDY
6040 * @retval None
6041 */
6042 __STATIC_INLINE void LL_RCC_EnableIT_LSERDY(void)
6043 {
6044 SET_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6045 }
6046
6047 /**
6048 * @brief Enable HSI ready interrupt
6049 * @rmtoll CIER HSIRDYIE LL_RCC_EnableIT_HSIRDY
6050 * @retval None
6051 */
6052 __STATIC_INLINE void LL_RCC_EnableIT_HSIRDY(void)
6053 {
6054 SET_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6055 }
6056
6057 /**
6058 * @brief Enable HSE ready interrupt
6059 * @rmtoll CIER HSERDYIE LL_RCC_EnableIT_HSERDY
6060 * @retval None
6061 */
6062 __STATIC_INLINE void LL_RCC_EnableIT_HSERDY(void)
6063 {
6064 SET_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6065 }
6066
6067 /**
6068 * @brief Enable CSI ready interrupt
6069 * @rmtoll CIER CSIRDYIE LL_RCC_EnableIT_CSIRDY
6070 * @retval None
6071 */
6072 __STATIC_INLINE void LL_RCC_EnableIT_CSIRDY(void)
6073 {
6074 SET_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6075 }
6076
6077 /**
6078 * @brief Enable HSI48 ready interrupt
6079 * @rmtoll CIER HSI48RDYIE LL_RCC_EnableIT_HSI48RDY
6080 * @retval None
6081 */
6082 __STATIC_INLINE void LL_RCC_EnableIT_HSI48RDY(void)
6083 {
6084 SET_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6085 }
6086
6087 /**
6088 * @brief Enable PLL1 ready interrupt
6089 * @rmtoll CIER PLL1RDYIE LL_RCC_EnableIT_PLL1RDY
6090 * @retval None
6091 */
6092 __STATIC_INLINE void LL_RCC_EnableIT_PLL1RDY(void)
6093 {
6094 SET_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6095 }
6096
6097 /**
6098 * @brief Enable PLL2 ready interrupt
6099 * @rmtoll CIER PLL2RDYIE LL_RCC_EnableIT_PLL2RDY
6100 * @retval None
6101 */
6102 __STATIC_INLINE void LL_RCC_EnableIT_PLL2RDY(void)
6103 {
6104 SET_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6105 }
6106
6107 /**
6108 * @brief Enable PLL3 ready interrupt
6109 * @rmtoll CIER PLL3RDYIE LL_RCC_EnableIT_PLL3RDY
6110 * @retval None
6111 */
6112 __STATIC_INLINE void LL_RCC_EnableIT_PLL3RDY(void)
6113 {
6114 SET_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6115 }
6116
6117 /**
6118 * @brief Enable LSECSS interrupt
6119 * @rmtoll CIER LSECSSIE LL_RCC_EnableIT_LSECSS
6120 * @retval None
6121 */
6122 __STATIC_INLINE void LL_RCC_EnableIT_LSECSS(void)
6123 {
6124 SET_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6125 }
6126
6127 /**
6128 * @brief Disable LSI ready interrupt
6129 * @rmtoll CIER LSIRDYIE LL_RCC_DisableIT_LSIRDY
6130 * @retval None
6131 */
6132 __STATIC_INLINE void LL_RCC_DisableIT_LSIRDY(void)
6133 {
6134 CLEAR_BIT(RCC->CIER, RCC_CIER_LSIRDYIE);
6135 }
6136
6137 /**
6138 * @brief Disable LSE ready interrupt
6139 * @rmtoll CIER LSERDYIE LL_RCC_DisableIT_LSERDY
6140 * @retval None
6141 */
6142 __STATIC_INLINE void LL_RCC_DisableIT_LSERDY(void)
6143 {
6144 CLEAR_BIT(RCC->CIER, RCC_CIER_LSERDYIE);
6145 }
6146
6147 /**
6148 * @brief Disable HSI ready interrupt
6149 * @rmtoll CIER HSIRDYIE LL_RCC_DisableIT_HSIRDY
6150 * @retval None
6151 */
6152 __STATIC_INLINE void LL_RCC_DisableIT_HSIRDY(void)
6153 {
6154 CLEAR_BIT(RCC->CIER, RCC_CIER_HSIRDYIE);
6155 }
6156
6157 /**
6158 * @brief Disable HSE ready interrupt
6159 * @rmtoll CIER HSERDYIE LL_RCC_DisableIT_HSERDY
6160 * @retval None
6161 */
6162 __STATIC_INLINE void LL_RCC_DisableIT_HSERDY(void)
6163 {
6164 CLEAR_BIT(RCC->CIER, RCC_CIER_HSERDYIE);
6165 }
6166
6167 /**
6168 * @brief Disable CSI ready interrupt
6169 * @rmtoll CIER CSIRDYIE LL_RCC_DisableIT_CSIRDY
6170 * @retval None
6171 */
6172 __STATIC_INLINE void LL_RCC_DisableIT_CSIRDY(void)
6173 {
6174 CLEAR_BIT(RCC->CIER, RCC_CIER_CSIRDYIE);
6175 }
6176
6177 /**
6178 * @brief Disable HSI48 ready interrupt
6179 * @rmtoll CIER HSI48RDYIE LL_RCC_DisableIT_HSI48RDY
6180 * @retval None
6181 */
6182 __STATIC_INLINE void LL_RCC_DisableIT_HSI48RDY(void)
6183 {
6184 CLEAR_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE);
6185 }
6186
6187 /**
6188 * @brief Disable PLL1 ready interrupt
6189 * @rmtoll CIER PLL1RDYIE LL_RCC_DisableIT_PLL1RDY
6190 * @retval None
6191 */
6192 __STATIC_INLINE void LL_RCC_DisableIT_PLL1RDY(void)
6193 {
6194 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE);
6195 }
6196
6197 /**
6198 * @brief Disable PLL2 ready interrupt
6199 * @rmtoll CIER PLL2RDYIE LL_RCC_DisableIT_PLL2RDY
6200 * @retval None
6201 */
6202 __STATIC_INLINE void LL_RCC_DisableIT_PLL2RDY(void)
6203 {
6204 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE);
6205 }
6206
6207 /**
6208 * @brief Disable PLL3 ready interrupt
6209 * @rmtoll CIER PLL3RDYIE LL_RCC_DisableIT_PLL3RDY
6210 * @retval None
6211 */
6212 __STATIC_INLINE void LL_RCC_DisableIT_PLL3RDY(void)
6213 {
6214 CLEAR_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE);
6215 }
6216
6217 /**
6218 * @brief Disable LSECSS interrupt
6219 * @rmtoll CIER LSECSSIE LL_RCC_DisableIT_LSECSS
6220 * @retval None
6221 */
6222 __STATIC_INLINE void LL_RCC_DisableIT_LSECSS(void)
6223 {
6224 CLEAR_BIT(RCC->CIER, RCC_CIER_LSECSSIE);
6225 }
6226
6227 /**
6228 * @brief Checks if LSI ready interrupt source is enabled or disabled.
6229 * @rmtoll CIER LSIRDYIE LL_RCC_IsEnableIT_LSIRDY
6230 * @retval State of bit (1 or 0).
6231 */
6232 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSIRDY(void)
6233 {
6234 return ((READ_BIT(RCC->CIER, RCC_CIER_LSIRDYIE) == RCC_CIER_LSIRDYIE) ? 1UL : 0UL);
6235 }
6236
6237 /**
6238 * @brief Checks if LSE ready interrupt source is enabled or disabled.
6239 * @rmtoll CIER LSERDYIE LL_RCC_IsEnableIT_LSERDY
6240 * @retval State of bit (1 or 0).
6241 */
6242 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSERDY(void)
6243 {
6244 return ((READ_BIT(RCC->CIER, RCC_CIER_LSERDYIE) == RCC_CIER_LSERDYIE) ? 1UL : 0UL);
6245 }
6246
6247 /**
6248 * @brief Checks if HSI ready interrupt source is enabled or disabled.
6249 * @rmtoll CIER HSIRDYIE LL_RCC_IsEnableIT_HSIRDY
6250 * @retval State of bit (1 or 0).
6251 */
6252 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSIRDY(void)
6253 {
6254 return ((READ_BIT(RCC->CIER, RCC_CIER_HSIRDYIE) == RCC_CIER_HSIRDYIE) ? 1UL : 0UL);
6255 }
6256
6257 /**
6258 * @brief Checks if HSE ready interrupt source is enabled or disabled.
6259 * @rmtoll CIER HSERDYIE LL_RCC_IsEnableIT_HSERDY
6260 * @retval State of bit (1 or 0).
6261 */
6262 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSERDY(void)
6263 {
6264 return ((READ_BIT(RCC->CIER, RCC_CIER_HSERDYIE) == RCC_CIER_HSERDYIE) ? 1UL : 0UL);
6265 }
6266
6267 /**
6268 * @brief Checks if CSI ready interrupt source is enabled or disabled.
6269 * @rmtoll CIER CSIRDYIE LL_RCC_IsEnableIT_CSIRDY
6270 * @retval State of bit (1 or 0).
6271 */
6272 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_CSIRDY(void)
6273 {
6274 return ((READ_BIT(RCC->CIER, RCC_CIER_CSIRDYIE) == RCC_CIER_CSIRDYIE) ? 1UL : 0UL);
6275 }
6276
6277 /**
6278 * @brief Checks if HSI48 ready interrupt source is enabled or disabled.
6279 * @rmtoll CIER HSI48RDYIE LL_RCC_IsEnableIT_HSI48RDY
6280 * @retval State of bit (1 or 0).
6281 */
6282 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_HSI48RDY(void)
6283 {
6284 return ((READ_BIT(RCC->CIER, RCC_CIER_HSI48RDYIE) == RCC_CIER_HSI48RDYIE) ? 1UL : 0UL);
6285 }
6286
6287 /**
6288 * @brief Checks if PLL1 ready interrupt source is enabled or disabled.
6289 * @rmtoll CIER PLL1RDYIE LL_RCC_IsEnableIT_PLL1RDY
6290 * @retval State of bit (1 or 0).
6291 */
6292 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL1RDY(void)
6293 {
6294 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL1RDYIE) == RCC_CIER_PLL1RDYIE) ? 1UL : 0UL);
6295 }
6296
6297 /**
6298 * @brief Checks if PLL2 ready interrupt source is enabled or disabled.
6299 * @rmtoll CIER PLL2RDYIE LL_RCC_IsEnableIT_PLL2RDY
6300 * @retval State of bit (1 or 0).
6301 */
6302 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL2RDY(void)
6303 {
6304 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL2RDYIE) == RCC_CIER_PLL2RDYIE) ? 1UL : 0UL);
6305 }
6306
6307 /**
6308 * @brief Checks if PLL3 ready interrupt source is enabled or disabled.
6309 * @rmtoll CIER PLL3RDYIE LL_RCC_IsEnableIT_PLL3RDY
6310 * @retval State of bit (1 or 0).
6311 */
6312 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_PLL3RDY(void)
6313 {
6314 return ((READ_BIT(RCC->CIER, RCC_CIER_PLL3RDYIE) == RCC_CIER_PLL3RDYIE) ? 1UL : 0UL);
6315 }
6316
6317 /**
6318 * @brief Checks if LSECSS interrupt source is enabled or disabled.
6319 * @rmtoll CIER LSECSSIE LL_RCC_IsEnableIT_LSECSS
6320 * @retval State of bit (1 or 0).
6321 */
6322 __STATIC_INLINE uint32_t LL_RCC_IsEnableIT_LSECSS(void)
6323 {
6324 return ((READ_BIT(RCC->CIER, RCC_CIER_LSECSSIE) == RCC_CIER_LSECSSIE) ? 1UL : 0UL);
6325 }
6326 /**
6327 * @}
6328 */
6329
6330 #if defined(USE_FULL_LL_DRIVER)
6331 /** @defgroup RCC_LL_EF_Init De-initialization function
6332 * @{
6333 */
6334 void LL_RCC_DeInit(void);
6335 /**
6336 * @}
6337 */
6338
6339 /** @defgroup RCC_LL_EF_Get_Freq Get system and peripherals clocks frequency functions
6340 * @{
6341 */
6342 uint32_t LL_RCC_CalcPLLClockFreq(uint32_t PLLInputFreq, uint32_t M, uint32_t N, uint32_t FRACN, uint32_t PQR);
6343
6344 void LL_RCC_GetPLL1ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6345 void LL_RCC_GetPLL2ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6346 void LL_RCC_GetPLL3ClockFreq(LL_PLL_ClocksTypeDef *PLL_Clocks);
6347 void LL_RCC_GetSystemClocksFreq(LL_RCC_ClocksTypeDef *RCC_Clocks);
6348
6349 uint32_t LL_RCC_GetUSARTClockFreq(uint32_t USARTxSource);
6350 uint32_t LL_RCC_GetLPUARTClockFreq(uint32_t LPUARTxSource);
6351 uint32_t LL_RCC_GetI2CClockFreq(uint32_t I2CxSource);
6352 uint32_t LL_RCC_GetLPTIMClockFreq(uint32_t LPTIMxSource);
6353 uint32_t LL_RCC_GetSAIClockFreq(uint32_t SAIxSource);
6354 uint32_t LL_RCC_GetADCClockFreq(uint32_t ADCxSource);
6355 uint32_t LL_RCC_GetSDMMCClockFreq(uint32_t SDMMCxSource);
6356 uint32_t LL_RCC_GetRNGClockFreq(uint32_t RNGxSource);
6357 uint32_t LL_RCC_GetCECClockFreq(uint32_t CECxSource);
6358 uint32_t LL_RCC_GetUSBClockFreq(uint32_t USBxSource);
6359 uint32_t LL_RCC_GetDFSDMClockFreq(uint32_t DFSDMxSource);
6360 #if defined(DFSDM2_BASE)
6361 uint32_t LL_RCC_GetDFSDM2ClockFreq(uint32_t DFSDMxSource);
6362 #endif /* DFSDM2_BASE */
6363 #if defined(DSI)
6364 uint32_t LL_RCC_GetDSIClockFreq(uint32_t DSIxSource);
6365 #endif /* DSI */
6366 uint32_t LL_RCC_GetSPDIFClockFreq(uint32_t SPDIFxSource);
6367 uint32_t LL_RCC_GetSPIClockFreq(uint32_t SPIxSource);
6368 uint32_t LL_RCC_GetSWPClockFreq(uint32_t SWPxSource);
6369 uint32_t LL_RCC_GetFDCANClockFreq(uint32_t FDCANxSource);
6370 uint32_t LL_RCC_GetFMCClockFreq(uint32_t FMCxSource);
6371 #if defined(QUADSPI)
6372 uint32_t LL_RCC_GetQSPIClockFreq(uint32_t QSPIxSource);
6373 #endif /* QUADSPI */
6374 #if defined(OCTOSPI1) || defined(OCTOSPI2)
6375 uint32_t LL_RCC_GetOSPIClockFreq(uint32_t OSPIxSource);
6376 #endif /* defined(OCTOSPI1) || defined(OCTOSPI2) */
6377 uint32_t LL_RCC_GetCLKPClockFreq(uint32_t CLKPxSource);
6378
6379
6380 /**
6381 * @}
6382 */
6383 #endif /* USE_FULL_LL_DRIVER */
6384
6385 /**
6386 * @}
6387 */
6388
6389
6390 /**
6391 * @}
6392 */
6393 #endif /* defined(RCC) */
6394
6395 /**
6396 * @}
6397 */
6398
6399 #ifdef __cplusplus
6400 }
6401 #endif
6402
6403 #endif /* STM32H7xx_LL_RCC_H */
6404
INAV: Navigation-enabled flight control software